1 //===-- ScheduleDAGSimple.cpp - Implement a trivial DAG scheduler ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CodeGen/SchedulerRegistry.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/Visibility.h"
32 static RegisterScheduler
33 bfsDAGScheduler("none", " No scheduling: breadth first sequencing",
34 createBFS_DAGScheduler);
35 static RegisterScheduler
36 simpleDAGScheduler("simple",
37 " Simple two pass scheduling: minimize critical path "
38 "and maximize processor utilization",
39 createSimpleDAGScheduler);
40 static RegisterScheduler
41 noitinDAGScheduler("simple-noitin",
42 " Simple two pass scheduling: Same as simple "
43 "except using generic latency",
44 createNoItinsDAGScheduler);
47 typedef NodeInfo *NodeInfoPtr;
48 typedef std::vector<NodeInfoPtr> NIVector;
49 typedef std::vector<NodeInfoPtr>::iterator NIIterator;
51 //===--------------------------------------------------------------------===//
53 /// Node group - This struct is used to manage flagged node groups.
59 NIVector Members; // Group member nodes
60 NodeInfo *Dominator; // Node with highest latency
61 unsigned Latency; // Total latency of the group
62 int Pending; // Number of visits pending before
67 NodeGroup() : Next(NULL), Dominator(NULL), Pending(0) {}
70 inline void setDominator(NodeInfo *D) { Dominator = D; }
71 inline NodeInfo *getTop() { return Members.front(); }
72 inline NodeInfo *getBottom() { return Members.back(); }
73 inline NodeInfo *getDominator() { return Dominator; }
74 inline void setLatency(unsigned L) { Latency = L; }
75 inline unsigned getLatency() { return Latency; }
76 inline int getPending() const { return Pending; }
77 inline void setPending(int P) { Pending = P; }
78 inline int addPending(int I) { return Pending += I; }
81 inline bool group_empty() { return Members.empty(); }
82 inline NIIterator group_begin() { return Members.begin(); }
83 inline NIIterator group_end() { return Members.end(); }
84 inline void group_push_back(const NodeInfoPtr &NI) {
85 Members.push_back(NI);
87 inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
88 return Members.insert(Pos, NI);
90 inline void group_insert(NIIterator Pos, NIIterator First,
92 Members.insert(Pos, First, Last);
95 static void Add(NodeInfo *D, NodeInfo *U);
98 //===--------------------------------------------------------------------===//
100 /// NodeInfo - This struct tracks information used to schedule the a node.
104 int Pending; // Number of visits pending before
107 SDNode *Node; // DAG node
108 InstrStage *StageBegin; // First stage in itinerary
109 InstrStage *StageEnd; // Last+1 stage in itinerary
110 unsigned Latency; // Total cycles to complete instr
111 bool IsCall : 1; // Is function call
112 bool IsLoad : 1; // Is memory load
113 bool IsStore : 1; // Is memory store
114 unsigned Slot; // Node's time slot
115 NodeGroup *Group; // Grouping information
117 unsigned Preorder; // Index before scheduling
121 NodeInfo(SDNode *N = NULL)
136 inline bool isInGroup() const {
137 assert(!Group || !Group->group_empty() && "Group with no members");
138 return Group != NULL;
140 inline bool isGroupDominator() const {
141 return isInGroup() && Group->getDominator() == this;
143 inline int getPending() const {
144 return Group ? Group->getPending() : Pending;
146 inline void setPending(int P) {
147 if (Group) Group->setPending(P);
150 inline int addPending(int I) {
151 if (Group) return Group->addPending(I);
152 else return Pending += I;
156 //===--------------------------------------------------------------------===//
158 /// NodeGroupIterator - Iterates over all the nodes indicated by the node
159 /// info. If the node is in a group then iterate over the members of the
160 /// group, otherwise just the node info.
162 class NodeGroupIterator {
164 NodeInfo *NI; // Node info
165 NIIterator NGI; // Node group iterator
166 NIIterator NGE; // Node group iterator end
170 NodeGroupIterator(NodeInfo *N) : NI(N) {
171 // If the node is in a group then set up the group iterator. Otherwise
172 // the group iterators will trip first time out.
173 if (N->isInGroup()) {
175 NodeGroup *Group = NI->Group;
176 NGI = Group->group_begin();
177 NGE = Group->group_end();
178 // Prevent this node from being used (will be in members list
183 /// next - Return the next node info, otherwise NULL.
187 if (NGI != NGE) return *NGI++;
188 // Use node as the result (may be NULL)
189 NodeInfo *Result = NI;
192 // Return node or NULL
196 //===--------------------------------------------------------------------===//
199 //===--------------------------------------------------------------------===//
201 /// NodeGroupOpIterator - Iterates over all the operands of a node. If the
202 /// node is a member of a group, this iterates over all the operands of all
203 /// the members of the group.
205 class NodeGroupOpIterator {
207 NodeInfo *NI; // Node containing operands
208 NodeGroupIterator GI; // Node group iterator
209 SDNode::op_iterator OI; // Operand iterator
210 SDNode::op_iterator OE; // Operand iterator end
212 /// CheckNode - Test if node has more operands. If not get the next node
213 /// skipping over nodes that have no operands.
215 // Only if operands are exhausted first
217 // Get next node info
218 NodeInfo *NI = GI.next();
219 // Exit if nodes are exhausted
222 SDNode *Node = NI->Node;
223 // Set up the operand iterators
224 OI = Node->op_begin();
231 NodeGroupOpIterator(NodeInfo *N)
232 : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
234 /// isEnd - Returns true when not more operands are available.
236 inline bool isEnd() { CheckNode(); return OI == OE; }
238 /// next - Returns the next available operand.
240 inline SDOperand next() {
242 "Not checking for end of NodeGroupOpIterator correctly");
248 //===----------------------------------------------------------------------===//
250 /// BitsIterator - Provides iteration through individual bits in a bit vector.
255 T Bits; // Bits left to iterate through
259 BitsIterator(T Initial) : Bits(Initial) {}
261 /// Next - Returns the next bit set or zero if exhausted.
263 // Get the rightmost bit set
264 T Result = Bits & -Bits;
267 // Return single bit or zero
272 //===----------------------------------------------------------------------===//
275 //===----------------------------------------------------------------------===//
277 /// ResourceTally - Manages the use of resources over time intervals. Each
278 /// item (slot) in the tally vector represents the resources used at a given
279 /// moment. A bit set to 1 indicates that a resource is in use, otherwise
280 /// available. An assumption is made that the tally is large enough to schedule
281 /// all current instructions (asserts otherwise.)
284 class ResourceTally {
286 std::vector<T> Tally; // Resources used per slot
287 typedef typename std::vector<T>::iterator Iter;
290 /// SlotsAvailable - Returns true if all units are available.
292 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
293 unsigned &Resource) {
294 assert(N && "Must check availability with N != 0");
295 // Determine end of interval
296 Iter End = Begin + N;
297 assert(End <= Tally.end() && "Tally is not large enough for schedule");
299 // Iterate thru each resource
300 BitsIterator<T> Resources(ResourceSet & ~*Begin);
301 while (unsigned Res = Resources.Next()) {
302 // Check if resource is available for next N slots
306 if (*Interval & Res) break;
307 } while (Interval != Begin);
309 // If available for N
310 if (Interval == Begin) {
322 /// RetrySlot - Finds a good candidate slot to retry search.
323 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
324 assert(N && "Must check availability with N != 0");
325 // Determine end of interval
326 Iter End = Begin + N;
327 assert(End <= Tally.end() && "Tally is not large enough for schedule");
329 while (Begin != End--) {
330 // Clear units in use
331 ResourceSet &= ~*End;
332 // If no units left then we should go no further
333 if (!ResourceSet) return End + 1;
335 // Made it all the way through
339 /// FindAndReserveStages - Return true if the stages can be completed. If
341 bool FindAndReserveStages(Iter Begin,
342 InstrStage *Stage, InstrStage *StageEnd) {
343 // If at last stage then we're done
344 if (Stage == StageEnd) return true;
345 // Get number of cycles for current stage
346 unsigned N = Stage->Cycles;
347 // Check to see if N slots are available, if not fail
349 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
350 // Check to see if remaining stages are available, if not fail
351 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
353 Reserve(Begin, N, Resource);
358 /// Reserve - Mark busy (set) the specified N slots.
359 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
360 // Determine end of interval
361 Iter End = Begin + N;
362 assert(End <= Tally.end() && "Tally is not large enough for schedule");
364 // Set resource bit in each slot
365 for (; Begin < End; Begin++)
369 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
370 /// can be completed. Returns the address of first slot.
371 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
375 // Try all possible slots forward
377 // Try at cursor, if successful return position.
378 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
379 // Locate a better position
380 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
385 /// Initialize - Resize and zero the tally to the specified number of time
387 inline void Initialize(unsigned N) {
388 Tally.assign(N, 0); // Initialize tally to all zeros.
391 // FindAndReserve - Locate an ideal slot for the specified stages and mark
393 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
394 InstrStage *StageEnd) {
396 Iter Begin = Tally.begin() + Slot;
398 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
399 // Distance is slot number
400 unsigned Final = Where - Tally.begin();
406 //===----------------------------------------------------------------------===//
408 /// ScheduleDAGSimple - Simple two pass scheduler.
410 class VISIBILITY_HIDDEN ScheduleDAGSimple : public ScheduleDAG {
412 bool NoSched; // Just do a BFS schedule, nothing fancy
413 bool NoItins; // Don't use itineraries?
414 ResourceTally<unsigned> Tally; // Resource usage tally
415 unsigned NSlots; // Total latency
416 static const unsigned NotFound = ~0U; // Search marker
418 unsigned NodeCount; // Number of nodes in DAG
419 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
420 bool HasGroups; // True if there are any groups
421 NodeInfo *Info; // Info for nodes being scheduled
422 NIVector Ordering; // Emit ordering of nodes
423 NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
428 ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
429 MachineBasicBlock *bb, const TargetMachine &tm)
430 : ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
431 NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
432 assert(&TII && "Target doesn't provide instr info?");
433 assert(&MRI && "Target doesn't provide register info?");
436 virtual ~ScheduleDAGSimple() {
440 NodeGroup *NG = HeadNG;
442 NodeGroup *NextSU = NG->Next;
450 /// getNI - Returns the node info for the specified node.
452 NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
455 static bool isDefiner(NodeInfo *A, NodeInfo *B);
456 void IncludeNode(NodeInfo *NI);
458 void GatherSchedulingInfo();
459 void FakeGroupDominators();
460 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
461 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
462 void ScheduleBackward();
463 void ScheduleForward();
465 void AddToGroup(NodeInfo *D, NodeInfo *U);
466 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
468 void PrepareNodeInfo();
470 /// IdentifyGroups - Put flagged nodes into groups.
472 void IdentifyGroups();
474 /// print - Print ordering to specified output stream.
476 void print(std::ostream &O) const;
478 void dump(const char *tag) const;
480 virtual void dump() const;
482 /// EmitAll - Emit all nodes in schedule sorted order.
486 /// printNI - Print node info.
488 void printNI(std::ostream &O, NodeInfo *NI) const;
490 /// printChanges - Hilight changes in order caused by scheduling.
492 void printChanges(unsigned Index) const;
495 //===----------------------------------------------------------------------===//
496 /// Special case itineraries.
499 CallLatency = 40, // To push calls back in time
501 RSInteger = 0xC0000000, // Two integer units
502 RSFloat = 0x30000000, // Two float units
503 RSLoadStore = 0x0C000000, // Two load store units
504 RSBranch = 0x02000000 // One branch unit
506 static InstrStage CallStage = { CallLatency, RSBranch };
507 static InstrStage LoadStage = { 5, RSLoadStore };
508 static InstrStage StoreStage = { 2, RSLoadStore };
509 static InstrStage IntStage = { 2, RSInteger };
510 static InstrStage FloatStage = { 3, RSFloat };
511 //===----------------------------------------------------------------------===//
515 //===----------------------------------------------------------------------===//
517 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
519 void ScheduleDAGSimple::PrepareNodeInfo() {
520 // Allocate node information
521 Info = new NodeInfo[NodeCount];
524 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
525 E = DAG.allnodes_end(); I != E; ++I, ++i) {
526 // Fast reference to node schedule info
527 NodeInfo* NI = &Info[i];
532 // Set pending visit count
533 NI->setPending(I->use_size());
537 /// IdentifyGroups - Put flagged nodes into groups.
539 void ScheduleDAGSimple::IdentifyGroups() {
540 for (unsigned i = 0, N = NodeCount; i < N; i++) {
541 NodeInfo* NI = &Info[i];
542 SDNode *Node = NI->Node;
544 // For each operand (in reverse to only look at flags)
545 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
547 SDOperand Op = Node->getOperand(N);
548 // No more flags to walk
549 if (Op.getValueType() != MVT::Flag) break;
551 AddToGroup(getNI(Op.Val), NI);
552 // Let everyone else know
558 /// CountInternalUses - Returns the number of edges between the two nodes.
560 static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U) {
562 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
563 SDOperand Op = U->Node->getOperand(M);
564 if (Op.Val == D->Node) N++;
570 //===----------------------------------------------------------------------===//
571 /// Add - Adds a definer and user pair to a node group.
573 void ScheduleDAGSimple::AddToGroup(NodeInfo *D, NodeInfo *U) {
574 // Get current groups
575 NodeGroup *DGroup = D->Group;
576 NodeGroup *UGroup = U->Group;
577 // If both are members of groups
578 if (DGroup && UGroup) {
579 // There may have been another edge connecting
580 if (DGroup == UGroup) return;
581 // Add the pending users count
582 DGroup->addPending(UGroup->getPending());
583 // For each member of the users group
584 NodeGroupIterator UNGI(U);
585 while (NodeInfo *UNI = UNGI.next() ) {
588 // For each member of the definers group
589 NodeGroupIterator DNGI(D);
590 while (NodeInfo *DNI = DNGI.next() ) {
591 // Remove internal edges
592 DGroup->addPending(-CountInternalUses(DNI, UNI));
595 // Merge the two lists
596 DGroup->group_insert(DGroup->group_end(),
597 UGroup->group_begin(), UGroup->group_end());
599 // Make user member of definers group
601 // Add users uses to definers group pending
602 DGroup->addPending(U->Node->use_size());
603 // For each member of the definers group
604 NodeGroupIterator DNGI(D);
605 while (NodeInfo *DNI = DNGI.next() ) {
606 // Remove internal edges
607 DGroup->addPending(-CountInternalUses(DNI, U));
609 DGroup->group_push_back(U);
611 // Make definer member of users group
613 // Add definers uses to users group pending
614 UGroup->addPending(D->Node->use_size());
615 // For each member of the users group
616 NodeGroupIterator UNGI(U);
617 while (NodeInfo *UNI = UNGI.next() ) {
618 // Remove internal edges
619 UGroup->addPending(-CountInternalUses(D, UNI));
621 UGroup->group_insert(UGroup->group_begin(), D);
623 D->Group = U->Group = DGroup = new NodeGroup();
624 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
625 CountInternalUses(D, U));
626 DGroup->group_push_back(D);
627 DGroup->group_push_back(U);
632 TailNG->Next = DGroup;
638 /// print - Print ordering to specified output stream.
640 void ScheduleDAGSimple::print(std::ostream &O) const {
643 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
644 NodeInfo *NI = Ordering[i];
647 if (NI->isGroupDominator()) {
648 NodeGroup *Group = NI->Group;
649 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
660 void ScheduleDAGSimple::dump(const char *tag) const {
661 std::cerr << tag; dump();
664 void ScheduleDAGSimple::dump() const {
669 /// EmitAll - Emit all nodes in schedule sorted order.
671 void ScheduleDAGSimple::EmitAll() {
672 std::map<SDNode*, unsigned> VRBaseMap;
674 // For each node in the ordering
675 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
676 // Get the scheduling info
677 NodeInfo *NI = Ordering[i];
678 if (NI->isInGroup()) {
679 NodeGroupIterator NGI(Ordering[i]);
680 while (NodeInfo *NI = NGI.next()) EmitNode(NI->Node, VRBaseMap);
682 EmitNode(NI->Node, VRBaseMap);
687 /// isFlagDefiner - Returns true if the node defines a flag result.
688 static bool isFlagDefiner(SDNode *A) {
689 unsigned N = A->getNumValues();
690 return N && A->getValueType(N - 1) == MVT::Flag;
693 /// isFlagUser - Returns true if the node uses a flag result.
695 static bool isFlagUser(SDNode *A) {
696 unsigned N = A->getNumOperands();
697 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
700 /// printNI - Print node info.
702 void ScheduleDAGSimple::printNI(std::ostream &O, NodeInfo *NI) const {
704 SDNode *Node = NI->Node;
706 << std::hex << Node << std::dec
707 << ", Lat=" << NI->Latency
708 << ", Slot=" << NI->Slot
709 << ", ARITY=(" << Node->getNumOperands() << ","
710 << Node->getNumValues() << ")"
711 << " " << Node->getOperationName(&DAG);
712 if (isFlagDefiner(Node)) O << "<#";
713 if (isFlagUser(Node)) O << ">#";
717 /// printChanges - Hilight changes in order caused by scheduling.
719 void ScheduleDAGSimple::printChanges(unsigned Index) const {
721 // Get the ordered node count
722 unsigned N = Ordering.size();
723 // Determine if any changes
726 NodeInfo *NI = Ordering[i];
727 if (NI->Preorder != i) break;
731 std::cerr << Index << ". New Ordering\n";
733 for (i = 0; i < N; i++) {
734 NodeInfo *NI = Ordering[i];
735 std::cerr << " " << NI->Preorder << ". ";
736 printNI(std::cerr, NI);
738 if (NI->isGroupDominator()) {
739 NodeGroup *Group = NI->Group;
740 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
743 printNI(std::cerr, *NII);
749 std::cerr << Index << ". No Changes\n";
754 //===----------------------------------------------------------------------===//
755 /// isDefiner - Return true if node A is a definer for B.
757 bool ScheduleDAGSimple::isDefiner(NodeInfo *A, NodeInfo *B) {
758 // While there are A nodes
759 NodeGroupIterator NII(A);
760 while (NodeInfo *NI = NII.next()) {
762 SDNode *Node = NI->Node;
763 // While there operands in nodes of B
764 NodeGroupOpIterator NGOI(B);
765 while (!NGOI.isEnd()) {
766 SDOperand Op = NGOI.next();
767 // If node from A defines a node in B
768 if (Node == Op.Val) return true;
774 /// IncludeNode - Add node to NodeInfo vector.
776 void ScheduleDAGSimple::IncludeNode(NodeInfo *NI) {
778 SDNode *Node = NI->Node;
780 if (Node->getOpcode() == ISD::EntryToken) return;
781 // Check current count for node
782 int Count = NI->getPending();
783 // If the node is already in list
784 if (Count < 0) return;
785 // Decrement count to indicate a visit
787 // If count has gone to zero then add node to list
790 if (NI->isInGroup()) {
791 Ordering.push_back(NI->Group->getDominator());
793 Ordering.push_back(NI);
795 // indicate node has been added
798 // Mark as visited with new count
799 NI->setPending(Count);
802 /// GatherSchedulingInfo - Get latency and resource information about each node.
804 void ScheduleDAGSimple::GatherSchedulingInfo() {
805 // Get instruction itineraries for the target
806 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
809 for (unsigned i = 0, N = NodeCount; i < N; i++) {
811 NodeInfo* NI = &Info[i];
812 SDNode *Node = NI->Node;
814 // If there are itineraries and it is a machine instruction
815 if (InstrItins.isEmpty() || NoItins) {
817 if (Node->isTargetOpcode()) {
818 // Get return type to guess which processing unit
819 MVT::ValueType VT = Node->getValueType(0);
820 // Get machine opcode
821 MachineOpCode TOpc = Node->getTargetOpcode();
822 NI->IsCall = TII->isCall(TOpc);
823 NI->IsLoad = TII->isLoad(TOpc);
824 NI->IsStore = TII->isStore(TOpc);
826 if (TII->isLoad(TOpc)) NI->StageBegin = &LoadStage;
827 else if (TII->isStore(TOpc)) NI->StageBegin = &StoreStage;
828 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
829 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
830 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
832 } else if (Node->isTargetOpcode()) {
833 // get machine opcode
834 MachineOpCode TOpc = Node->getTargetOpcode();
835 // Check to see if it is a call
836 NI->IsCall = TII->isCall(TOpc);
837 // Get itinerary stages for instruction
838 unsigned II = TII->getSchedClass(TOpc);
839 NI->StageBegin = InstrItins.begin(II);
840 NI->StageEnd = InstrItins.end(II);
843 // One slot for the instruction itself
846 // Add long latency for a call to push it back in time
847 if (NI->IsCall) NI->Latency += CallLatency;
849 // Sum up all the latencies
850 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
851 Stage != E; Stage++) {
852 NI->Latency += Stage->Cycles;
855 // Sum up all the latencies for max tally size
856 NSlots += NI->Latency;
859 // Unify metrics if in a group
861 for (unsigned i = 0, N = NodeCount; i < N; i++) {
862 NodeInfo* NI = &Info[i];
864 if (NI->isInGroup()) {
865 NodeGroup *Group = NI->Group;
867 if (!Group->getDominator()) {
868 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
869 NodeInfo *Dominator = *NGI;
870 unsigned Latency = 0;
872 for (NGI++; NGI != NGE; NGI++) {
873 NodeInfo* NGNI = *NGI;
874 Latency += NGNI->Latency;
875 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
878 Dominator->Latency = Latency;
879 Group->setDominator(Dominator);
886 /// VisitAll - Visit each node breadth-wise to produce an initial ordering.
887 /// Note that the ordering in the Nodes vector is reversed.
888 void ScheduleDAGSimple::VisitAll() {
889 // Add first element to list
890 NodeInfo *NI = getNI(DAG.getRoot().Val);
891 if (NI->isInGroup()) {
892 Ordering.push_back(NI->Group->getDominator());
894 Ordering.push_back(NI);
897 // Iterate through all nodes that have been added
898 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
899 // Visit all operands
900 NodeGroupOpIterator NGI(Ordering[i]);
901 while (!NGI.isEnd()) {
903 SDOperand Op = NGI.next();
905 SDNode *Node = Op.Val;
906 // Ignore passive nodes
907 if (isPassiveNode(Node)) continue;
909 IncludeNode(getNI(Node));
913 // Add entry node last (IncludeNode filters entry nodes)
914 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
915 Ordering.push_back(getNI(DAG.getEntryNode().Val));
918 std::reverse(Ordering.begin(), Ordering.end());
921 /// FakeGroupDominators - Set dominators for non-scheduling.
923 void ScheduleDAGSimple::FakeGroupDominators() {
924 for (unsigned i = 0, N = NodeCount; i < N; i++) {
925 NodeInfo* NI = &Info[i];
927 if (NI->isInGroup()) {
928 NodeGroup *Group = NI->Group;
930 if (!Group->getDominator()) {
931 Group->setDominator(NI);
937 /// isStrongDependency - Return true if node A has results used by node B.
938 /// I.E., B must wait for latency of A.
939 bool ScheduleDAGSimple::isStrongDependency(NodeInfo *A, NodeInfo *B) {
940 // If A defines for B then it's a strong dependency or
941 // if a load follows a store (may be dependent but why take a chance.)
942 return isDefiner(A, B) || (A->IsStore && B->IsLoad);
945 /// isWeakDependency Return true if node A produces a result that will
946 /// conflict with operands of B. It is assumed that we have called
947 /// isStrongDependency prior.
948 bool ScheduleDAGSimple::isWeakDependency(NodeInfo *A, NodeInfo *B) {
949 // TODO check for conflicting real registers and aliases
950 #if 0 // FIXME - Since we are in SSA form and not checking register aliasing
951 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
953 return A->Node->getOpcode() == ISD::EntryToken;
957 /// ScheduleBackward - Schedule instructions so that any long latency
958 /// instructions and the critical path get pushed back in time. Time is run in
959 /// reverse to allow code reuse of the Tally and eliminate the overhead of
960 /// biasing every slot indices against NSlots.
961 void ScheduleDAGSimple::ScheduleBackward() {
962 // Size and clear the resource tally
963 Tally.Initialize(NSlots);
964 // Get number of nodes to schedule
965 unsigned N = Ordering.size();
967 // For each node being scheduled
968 for (unsigned i = N; 0 < i--;) {
969 NodeInfo *NI = Ordering[i];
971 unsigned Slot = NotFound;
973 // Compare against those previously scheduled nodes
976 // Get following instruction
977 NodeInfo *Other = Ordering[j];
979 // Check dependency against previously inserted nodes
980 if (isStrongDependency(NI, Other)) {
981 Slot = Other->Slot + Other->Latency;
983 } else if (isWeakDependency(NI, Other)) {
989 // If independent of others (or first entry)
990 if (Slot == NotFound) Slot = 0;
992 #if 0 // FIXME - measure later
993 // Find a slot where the needed resources are available
994 if (NI->StageBegin != NI->StageEnd)
995 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
1001 // Insert sort based on slot
1003 for (; j < N; j++) {
1004 // Get following instruction
1005 NodeInfo *Other = Ordering[j];
1006 // Should we look further (remember slots are in reverse time)
1007 if (Slot >= Other->Slot) break;
1008 // Shuffle other into ordering
1009 Ordering[j - 1] = Other;
1011 // Insert node in proper slot
1012 if (j != i + 1) Ordering[j - 1] = NI;
1016 /// ScheduleForward - Schedule instructions to maximize packing.
1018 void ScheduleDAGSimple::ScheduleForward() {
1019 // Size and clear the resource tally
1020 Tally.Initialize(NSlots);
1021 // Get number of nodes to schedule
1022 unsigned N = Ordering.size();
1024 // For each node being scheduled
1025 for (unsigned i = 0; i < N; i++) {
1026 NodeInfo *NI = Ordering[i];
1028 unsigned Slot = NotFound;
1030 // Compare against those previously scheduled nodes
1033 // Get following instruction
1034 NodeInfo *Other = Ordering[j];
1036 // Check dependency against previously inserted nodes
1037 if (isStrongDependency(Other, NI)) {
1038 Slot = Other->Slot + Other->Latency;
1040 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
1046 // If independent of others (or first entry)
1047 if (Slot == NotFound) Slot = 0;
1049 // Find a slot where the needed resources are available
1050 if (NI->StageBegin != NI->StageEnd)
1051 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
1056 // Insert sort based on slot
1059 // Get prior instruction
1060 NodeInfo *Other = Ordering[j];
1061 // Should we look further
1062 if (Slot >= Other->Slot) break;
1063 // Shuffle other into ordering
1064 Ordering[j + 1] = Other;
1066 // Insert node in proper slot
1067 if (j != i) Ordering[j + 1] = NI;
1071 /// Schedule - Order nodes according to selected style.
1073 void ScheduleDAGSimple::Schedule() {
1075 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
1077 // Set up minimum info for scheduling
1079 // Construct node groups for flagged nodes
1082 // Test to see if scheduling should occur
1083 bool ShouldSchedule = NodeCount > 3 && !NoSched;
1084 // Don't waste time if is only entry and return
1085 if (ShouldSchedule) {
1086 // Get latency and resource requirements
1087 GatherSchedulingInfo();
1088 } else if (HasGroups) {
1089 // Make sure all the groups have dominators
1090 FakeGroupDominators();
1093 // Breadth first walk of DAG
1097 static unsigned Count = 0;
1099 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1100 NodeInfo *NI = Ordering[i];
1105 // Don't waste time if is only entry and return
1106 if (ShouldSchedule) {
1107 // Push back long instructions and critical path
1110 // Pack instructions to maximize resource utilization
1114 DEBUG(printChanges(Count));
1116 // Emit in scheduled order
1121 /// createSimpleDAGScheduler - This creates a simple two pass instruction
1122 /// scheduler using instruction itinerary.
1123 llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAGISel *IS,
1125 MachineBasicBlock *BB) {
1126 return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
1129 /// createNoItinsDAGScheduler - This creates a simple two pass instruction
1130 /// scheduler without using instruction itinerary.
1131 llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAGISel *IS,
1133 MachineBasicBlock *BB) {
1134 return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
1137 /// createBFS_DAGScheduler - This creates a simple breadth first instruction
1139 llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAGISel *IS,
1141 MachineBasicBlock *BB) {
1142 return new ScheduleDAGSimple(true, false, *DAG, BB, DAG->getTarget());