1 //===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAG class.
12 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/SelectionDAG.h"
14 #include "llvm/Constants.h"
15 #include "llvm/Analysis/ValueTracking.h"
16 #include "llvm/GlobalAlias.h"
17 #include "llvm/GlobalVariable.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/SetVector.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/StringExtras.h"
45 /// makeVTList - Return an instance of the SDVTList struct initialized with the
46 /// specified members.
47 static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
48 SDVTList Res = {VTs, NumVTs};
52 static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
53 switch (VT.getSimpleVT()) {
54 default: assert(0 && "Unknown FP format");
55 case MVT::f32: return &APFloat::IEEEsingle;
56 case MVT::f64: return &APFloat::IEEEdouble;
57 case MVT::f80: return &APFloat::x87DoubleExtended;
58 case MVT::f128: return &APFloat::IEEEquad;
59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
63 SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {}
65 //===----------------------------------------------------------------------===//
66 // ConstantFPSDNode Class
67 //===----------------------------------------------------------------------===//
69 /// isExactlyValue - We don't rely on operator== working on double values, as
70 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
71 /// As such, this method can be used to do an exact bit-for-bit comparison of
72 /// two floating point values.
73 bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const {
74 return getValueAPF().bitwiseIsEqual(V);
77 bool ConstantFPSDNode::isValueValidForType(MVT VT,
79 assert(VT.isFloatingPoint() && "Can only convert between FP types");
81 // PPC long double cannot be converted to any other type.
82 if (VT == MVT::ppcf128 ||
83 &Val.getSemantics() == &APFloat::PPCDoubleDouble)
86 // convert modifies in place, so make a copy.
87 APFloat Val2 = APFloat(Val);
89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
98 /// isBuildVectorAllOnes - Return true if the specified node is a
99 /// BUILD_VECTOR where all of the elements are ~0 or undef.
100 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
101 // Look through a bit convert.
102 if (N->getOpcode() == ISD::BIT_CONVERT)
103 N = N->getOperand(0).getNode();
105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
107 unsigned i = 0, e = N->getNumOperands();
109 // Skip over all of the undef values.
110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
113 // Do not accept an all-undef vector.
114 if (i == e) return false;
116 // Do not accept build_vectors that aren't all constants or which have non-~0
118 SDValue NotZero = N->getOperand(i);
119 if (isa<ConstantSDNode>(NotZero)) {
120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
122 } else if (isa<ConstantFPSDNode>(NotZero)) {
123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF().
124 bitcastToAPInt().isAllOnesValue())
129 // Okay, we have at least one ~0 value, check to see if the rest match or are
131 for (++i; i != e; ++i)
132 if (N->getOperand(i) != NotZero &&
133 N->getOperand(i).getOpcode() != ISD::UNDEF)
139 /// isBuildVectorAllZeros - Return true if the specified node is a
140 /// BUILD_VECTOR where all of the elements are 0 or undef.
141 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
142 // Look through a bit convert.
143 if (N->getOpcode() == ISD::BIT_CONVERT)
144 N = N->getOperand(0).getNode();
146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
148 unsigned i = 0, e = N->getNumOperands();
150 // Skip over all of the undef values.
151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
154 // Do not accept an all-undef vector.
155 if (i == e) return false;
157 // Do not accept build_vectors that aren't all constants or which have non-0
159 SDValue Zero = N->getOperand(i);
160 if (isa<ConstantSDNode>(Zero)) {
161 if (!cast<ConstantSDNode>(Zero)->isNullValue())
163 } else if (isa<ConstantFPSDNode>(Zero)) {
164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero())
169 // Okay, we have at least one 0 value, check to see if the rest match or are
171 for (++i; i != e; ++i)
172 if (N->getOperand(i) != Zero &&
173 N->getOperand(i).getOpcode() != ISD::UNDEF)
178 /// isScalarToVector - Return true if the specified node is a
179 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
180 /// element is not an undef.
181 bool ISD::isScalarToVector(const SDNode *N) {
182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
185 if (N->getOpcode() != ISD::BUILD_VECTOR)
187 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
189 unsigned NumElems = N->getNumOperands();
190 for (unsigned i = 1; i < NumElems; ++i) {
191 SDValue V = N->getOperand(i);
192 if (V.getOpcode() != ISD::UNDEF)
199 /// isDebugLabel - Return true if the specified node represents a debug
200 /// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
201 bool ISD::isDebugLabel(const SDNode *N) {
203 if (N->getOpcode() == ISD::DBG_LABEL)
205 if (N->isMachineOpcode() &&
206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL)
211 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
212 /// when given the operation for (X op Y).
213 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
214 // To perform this operation, we just need to swap the L and G bits of the
216 unsigned OldL = (Operation >> 2) & 1;
217 unsigned OldG = (Operation >> 1) & 1;
218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
219 (OldL << 1) | // New G bit
220 (OldG << 2)); // New L bit.
223 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
224 /// 'op' is a valid SetCC operation.
225 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
226 unsigned Operation = Op;
228 Operation ^= 7; // Flip L, G, E bits, but not U.
230 Operation ^= 15; // Flip all of the condition bits.
232 if (Operation > ISD::SETTRUE2)
233 Operation &= ~8; // Don't let N and U bits get set.
235 return ISD::CondCode(Operation);
239 /// isSignedOp - For an integer comparison, return 1 if the comparison is a
240 /// signed operation and 2 if the result is an unsigned comparison. Return zero
241 /// if the operation does not depend on the sign of the input (setne and seteq).
242 static int isSignedOp(ISD::CondCode Opcode) {
244 default: assert(0 && "Illegal integer setcc operation!");
246 case ISD::SETNE: return 0;
250 case ISD::SETGE: return 1;
254 case ISD::SETUGE: return 2;
258 /// getSetCCOrOperation - Return the result of a logical OR between different
259 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
260 /// returns SETCC_INVALID if it is not possible to represent the resultant
262 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
265 // Cannot fold a signed integer setcc with an unsigned integer setcc.
266 return ISD::SETCC_INVALID;
268 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
270 // If the N and U bits get set then the resultant comparison DOES suddenly
271 // care about orderedness, and is true when ordered.
272 if (Op > ISD::SETTRUE2)
273 Op &= ~16; // Clear the U bit if the N bit is set.
275 // Canonicalize illegal integer setcc's.
276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
279 return ISD::CondCode(Op);
282 /// getSetCCAndOperation - Return the result of a logical AND between different
283 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
284 /// function returns zero if it is not possible to represent the resultant
286 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
289 // Cannot fold a signed setcc with an unsigned setcc.
290 return ISD::SETCC_INVALID;
292 // Combine all of the condition bits.
293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
295 // Canonicalize illegal integer setcc's.
299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
300 case ISD::SETOEQ: // SETEQ & SETU[LG]E
301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
310 const TargetMachine &SelectionDAG::getTarget() const {
311 return MF->getTarget();
314 //===----------------------------------------------------------------------===//
315 // SDNode Profile Support
316 //===----------------------------------------------------------------------===//
318 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
320 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
324 /// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
325 /// solely with their pointer.
326 static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
327 ID.AddPointer(VTList.VTs);
330 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
332 static void AddNodeIDOperands(FoldingSetNodeID &ID,
333 const SDValue *Ops, unsigned NumOps) {
334 for (; NumOps; --NumOps, ++Ops) {
335 ID.AddPointer(Ops->getNode());
336 ID.AddInteger(Ops->getResNo());
340 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
342 static void AddNodeIDOperands(FoldingSetNodeID &ID,
343 const SDUse *Ops, unsigned NumOps) {
344 for (; NumOps; --NumOps, ++Ops) {
345 ID.AddPointer(Ops->getNode());
346 ID.AddInteger(Ops->getResNo());
350 static void AddNodeIDNode(FoldingSetNodeID &ID,
351 unsigned short OpC, SDVTList VTList,
352 const SDValue *OpList, unsigned N) {
353 AddNodeIDOpcode(ID, OpC);
354 AddNodeIDValueTypes(ID, VTList);
355 AddNodeIDOperands(ID, OpList, N);
358 /// AddNodeIDCustom - If this is an SDNode with special info, add this info to
360 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
361 switch (N->getOpcode()) {
362 default: break; // Normal nodes don't need extra info.
364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
366 case ISD::TargetConstant:
368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue());
370 case ISD::TargetConstantFP:
371 case ISD::ConstantFP: {
372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue());
375 case ISD::TargetGlobalAddress:
376 case ISD::GlobalAddress:
377 case ISD::TargetGlobalTLSAddress:
378 case ISD::GlobalTLSAddress: {
379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
380 ID.AddPointer(GA->getGlobal());
381 ID.AddInteger(GA->getOffset());
384 case ISD::BasicBlock:
385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock());
388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
390 case ISD::DBG_STOPPOINT: {
391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N);
392 ID.AddInteger(DSP->getLine());
393 ID.AddInteger(DSP->getColumn());
394 ID.AddPointer(DSP->getCompileUnit());
398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
400 case ISD::MEMOPERAND: {
401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO;
405 case ISD::FrameIndex:
406 case ISD::TargetFrameIndex:
407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex());
410 case ISD::TargetJumpTable:
411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex());
413 case ISD::ConstantPool:
414 case ISD::TargetConstantPool: {
415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
416 ID.AddInteger(CP->getAlignment());
417 ID.AddInteger(CP->getOffset());
418 if (CP->isMachineConstantPoolEntry())
419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID);
421 ID.AddPointer(CP->getConstVal());
425 const CallSDNode *Call = cast<CallSDNode>(N);
426 ID.AddInteger(Call->getCallingConv());
427 ID.AddInteger(Call->isVarArg());
431 const LoadSDNode *LD = cast<LoadSDNode>(N);
432 ID.AddInteger(LD->getMemoryVT().getRawBits());
433 ID.AddInteger(LD->getRawSubclassData());
437 const StoreSDNode *ST = cast<StoreSDNode>(N);
438 ID.AddInteger(ST->getMemoryVT().getRawBits());
439 ID.AddInteger(ST->getRawSubclassData());
442 case ISD::ATOMIC_CMP_SWAP:
443 case ISD::ATOMIC_SWAP:
444 case ISD::ATOMIC_LOAD_ADD:
445 case ISD::ATOMIC_LOAD_SUB:
446 case ISD::ATOMIC_LOAD_AND:
447 case ISD::ATOMIC_LOAD_OR:
448 case ISD::ATOMIC_LOAD_XOR:
449 case ISD::ATOMIC_LOAD_NAND:
450 case ISD::ATOMIC_LOAD_MIN:
451 case ISD::ATOMIC_LOAD_MAX:
452 case ISD::ATOMIC_LOAD_UMIN:
453 case ISD::ATOMIC_LOAD_UMAX: {
454 const AtomicSDNode *AT = cast<AtomicSDNode>(N);
455 ID.AddInteger(AT->getMemoryVT().getRawBits());
456 ID.AddInteger(AT->getRawSubclassData());
459 case ISD::VECTOR_SHUFFLE: {
460 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
461 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements();
463 ID.AddInteger(SVN->getMaskElt(i));
466 } // end switch (N->getOpcode())
469 /// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID
471 static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
472 AddNodeIDOpcode(ID, N->getOpcode());
473 // Add the return value info.
474 AddNodeIDValueTypes(ID, N->getVTList());
475 // Add the operand info.
476 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands());
478 // Handle SDNode leafs with special info.
479 AddNodeIDCustom(ID, N);
482 /// encodeMemSDNodeFlags - Generic routine for computing a value for use in
483 /// the CSE map that carries alignment, volatility, indexing mode, and
484 /// extension/truncation information.
486 static inline unsigned
487 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM,
488 bool isVolatile, unsigned Alignment) {
489 assert((ConvType & 3) == ConvType &&
490 "ConvType may not require more than 2 bits!");
491 assert((AM & 7) == AM &&
492 "AM may not require more than 3 bits!");
496 ((Log2_32(Alignment) + 1) << 6);
499 //===----------------------------------------------------------------------===//
500 // SelectionDAG Class
501 //===----------------------------------------------------------------------===//
503 /// doNotCSE - Return true if CSE should not be performed for this node.
504 static bool doNotCSE(SDNode *N) {
505 if (N->getValueType(0) == MVT::Flag)
506 return true; // Never CSE anything that produces a flag.
508 switch (N->getOpcode()) {
510 case ISD::HANDLENODE:
512 case ISD::DBG_STOPPOINT:
515 return true; // Never CSE these nodes.
518 // Check that remaining values produced are not flags.
519 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
520 if (N->getValueType(i) == MVT::Flag)
521 return true; // Never CSE anything that produces a flag.
526 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
528 void SelectionDAG::RemoveDeadNodes() {
529 // Create a dummy node (which is not added to allnodes), that adds a reference
530 // to the root node, preventing it from being deleted.
531 HandleSDNode Dummy(getRoot());
533 SmallVector<SDNode*, 128> DeadNodes;
535 // Add all obviously-dead nodes to the DeadNodes worklist.
536 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I)
538 DeadNodes.push_back(I);
540 RemoveDeadNodes(DeadNodes);
542 // If the root changed (e.g. it was a dead load, update the root).
543 setRoot(Dummy.getValue());
546 /// RemoveDeadNodes - This method deletes the unreachable nodes in the
547 /// given list, and any nodes that become unreachable as a result.
548 void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes,
549 DAGUpdateListener *UpdateListener) {
551 // Process the worklist, deleting the nodes and adding their uses to the
553 while (!DeadNodes.empty()) {
554 SDNode *N = DeadNodes.pop_back_val();
557 UpdateListener->NodeDeleted(N, 0);
559 // Take the node out of the appropriate CSE map.
560 RemoveNodeFromCSEMaps(N);
562 // Next, brutally remove the operand list. This is safe to do, as there are
563 // no cycles in the graph.
564 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
566 SDNode *Operand = Use.getNode();
569 // Now that we removed this operand, see if there are no uses of it left.
570 if (Operand->use_empty())
571 DeadNodes.push_back(Operand);
578 void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){
579 SmallVector<SDNode*, 16> DeadNodes(1, N);
580 RemoveDeadNodes(DeadNodes, UpdateListener);
583 void SelectionDAG::DeleteNode(SDNode *N) {
584 // First take this out of the appropriate CSE map.
585 RemoveNodeFromCSEMaps(N);
587 // Finally, remove uses due to operands of this node, remove from the
588 // AllNodes list, and delete the node.
589 DeleteNodeNotInCSEMaps(N);
592 void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
593 assert(N != AllNodes.begin() && "Cannot delete the entry node!");
594 assert(N->use_empty() && "Cannot delete a node that is not dead!");
596 // Drop all of the operands and decrement used node's use counts.
602 void SelectionDAG::DeallocateNode(SDNode *N) {
603 if (N->OperandsNeedDelete)
604 delete[] N->OperandList;
606 // Set the opcode to DELETED_NODE to help catch bugs when node
607 // memory is reallocated.
608 N->NodeType = ISD::DELETED_NODE;
610 NodeAllocator.Deallocate(AllNodes.remove(N));
613 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
614 /// correspond to it. This is useful when we're about to delete or repurpose
615 /// the node. We don't want future request for structurally identical nodes
616 /// to return N anymore.
617 bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
619 switch (N->getOpcode()) {
620 case ISD::EntryToken:
621 assert(0 && "EntryToken should not be in CSEMaps!");
623 case ISD::HANDLENODE: return false; // noop.
625 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
626 "Cond code doesn't exist!");
627 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0;
628 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0;
630 case ISD::ExternalSymbol:
631 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
633 case ISD::TargetExternalSymbol:
635 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
637 case ISD::VALUETYPE: {
638 MVT VT = cast<VTSDNode>(N)->getVT();
639 if (VT.isExtended()) {
640 Erased = ExtendedValueTypeNodes.erase(VT);
642 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
643 ValueTypeNodes[VT.getSimpleVT()] = 0;
648 // Remove it from the CSE Map.
649 Erased = CSEMap.RemoveNode(N);
653 // Verify that the node was actually in one of the CSE maps, unless it has a
654 // flag result (which cannot be CSE'd) or is one of the special cases that are
655 // not subject to CSE.
656 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
657 !N->isMachineOpcode() && !doNotCSE(N)) {
660 assert(0 && "Node is not in map!");
666 /// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE
667 /// maps and modified in place. Add it back to the CSE maps, unless an identical
668 /// node already exists, in which case transfer all its users to the existing
669 /// node. This transfer can potentially trigger recursive merging.
672 SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N,
673 DAGUpdateListener *UpdateListener) {
674 // For node types that aren't CSE'd, just act as if no identical node
677 SDNode *Existing = CSEMap.GetOrInsertNode(N);
679 // If there was already an existing matching node, use ReplaceAllUsesWith
680 // to replace the dead one with the existing one. This can cause
681 // recursive merging of other unrelated nodes down the line.
682 ReplaceAllUsesWith(N, Existing, UpdateListener);
684 // N is now dead. Inform the listener if it exists and delete it.
686 UpdateListener->NodeDeleted(N, Existing);
687 DeleteNodeNotInCSEMaps(N);
692 // If the node doesn't already exist, we updated it. Inform a listener if
695 UpdateListener->NodeUpdated(N);
698 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
699 /// were replaced with those specified. If this node is never memoized,
700 /// return null, otherwise return a pointer to the slot it would take. If a
701 /// node already exists with these operands, the slot will be non-null.
702 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
707 SDValue Ops[] = { Op };
709 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1);
710 AddNodeIDCustom(ID, N);
711 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
714 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
715 /// were replaced with those specified. If this node is never memoized,
716 /// return null, otherwise return a pointer to the slot it would take. If a
717 /// node already exists with these operands, the slot will be non-null.
718 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
719 SDValue Op1, SDValue Op2,
724 SDValue Ops[] = { Op1, Op2 };
726 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2);
727 AddNodeIDCustom(ID, N);
728 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
732 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
733 /// were replaced with those specified. If this node is never memoized,
734 /// return null, otherwise return a pointer to the slot it would take. If a
735 /// node already exists with these operands, the slot will be non-null.
736 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
737 const SDValue *Ops,unsigned NumOps,
743 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps);
744 AddNodeIDCustom(ID, N);
745 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
748 /// VerifyNode - Sanity check the given node. Aborts if it is invalid.
749 void SelectionDAG::VerifyNode(SDNode *N) {
750 switch (N->getOpcode()) {
753 case ISD::BUILD_PAIR: {
754 MVT VT = N->getValueType(0);
755 assert(N->getNumValues() == 1 && "Too many results!");
756 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
757 "Wrong return type!");
758 assert(N->getNumOperands() == 2 && "Wrong number of operands!");
759 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() &&
760 "Mismatched operand types!");
761 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() &&
762 "Wrong operand type!");
763 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() &&
764 "Wrong return type size");
767 case ISD::BUILD_VECTOR: {
768 assert(N->getNumValues() == 1 && "Too many results!");
769 assert(N->getValueType(0).isVector() && "Wrong return type!");
770 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
771 "Wrong number of operands!");
772 MVT EltVT = N->getValueType(0).getVectorElementType();
773 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
774 assert((I->getValueType() == EltVT ||
775 (EltVT.isInteger() && I->getValueType().isInteger() &&
776 EltVT.bitsLE(I->getValueType()))) &&
777 "Wrong operand type!");
783 /// getMVTAlignment - Compute the default alignment value for the
786 unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
787 const Type *Ty = VT == MVT::iPTR ?
788 PointerType::get(Type::Int8Ty, 0) :
791 return TLI.getTargetData()->getABITypeAlignment(Ty);
794 // EntryNode could meaningfully have debug info if we can find it...
795 SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
796 : TLI(tli), FLI(fli), DW(0),
797 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
798 getVTList(MVT::Other)), Root(getEntryNode()) {
799 AllNodes.push_back(&EntryNode);
802 void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
809 SelectionDAG::~SelectionDAG() {
813 void SelectionDAG::allnodes_clear() {
814 assert(&*AllNodes.begin() == &EntryNode);
815 AllNodes.remove(AllNodes.begin());
816 while (!AllNodes.empty())
817 DeallocateNode(AllNodes.begin());
820 void SelectionDAG::clear() {
822 OperandAllocator.Reset();
825 ExtendedValueTypeNodes.clear();
826 ExternalSymbols.clear();
827 TargetExternalSymbols.clear();
828 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
829 static_cast<CondCodeSDNode*>(0));
830 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
831 static_cast<SDNode*>(0));
833 EntryNode.UseList = 0;
834 AllNodes.push_back(&EntryNode);
835 Root = getEntryNode();
838 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
839 if (Op.getValueType() == VT) return Op;
840 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
842 return getNode(ISD::AND, DL, Op.getValueType(), Op,
843 getConstant(Imm, Op.getValueType()));
846 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
848 SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
851 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
852 return getNode(ISD::XOR, DL, VT, Val, NegOne);
855 SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
856 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
857 assert((EltVT.getSizeInBits() >= 64 ||
858 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
859 "getConstant with a uint64_t value that doesn't fit in the type!");
860 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
863 SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
864 return getConstant(*ConstantInt::get(Val), VT, isT);
867 SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) {
868 assert(VT.isInteger() && "Cannot create FP integer constant!");
870 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
871 assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
872 "APInt size does not match type size!");
874 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
876 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
880 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
882 return SDValue(N, 0);
884 N = NodeAllocator.Allocate<ConstantSDNode>();
885 new (N) ConstantSDNode(isT, &Val, EltVT);
886 CSEMap.InsertNode(N, IP);
887 AllNodes.push_back(N);
890 SDValue Result(N, 0);
892 SmallVector<SDValue, 8> Ops;
893 Ops.assign(VT.getVectorNumElements(), Result);
894 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
895 VT, &Ops[0], Ops.size());
900 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
901 return getConstant(Val, TLI.getPointerTy(), isTarget);
905 SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
906 return getConstantFP(*ConstantFP::get(V), VT, isTarget);
909 SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
910 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
913 VT.isVector() ? VT.getVectorElementType() : VT;
915 // Do the map lookup using the actual bit pattern for the floating point
916 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and
917 // we don't have issues with SNANs.
918 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
920 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
924 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
926 return SDValue(N, 0);
928 N = NodeAllocator.Allocate<ConstantFPSDNode>();
929 new (N) ConstantFPSDNode(isTarget, &V, EltVT);
930 CSEMap.InsertNode(N, IP);
931 AllNodes.push_back(N);
934 SDValue Result(N, 0);
936 SmallVector<SDValue, 8> Ops;
937 Ops.assign(VT.getVectorNumElements(), Result);
938 // FIXME DebugLoc info might be appropriate here
939 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
940 VT, &Ops[0], Ops.size());
945 SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
947 VT.isVector() ? VT.getVectorElementType() : VT;
949 return getConstantFP(APFloat((float)Val), VT, isTarget);
951 return getConstantFP(APFloat(Val), VT, isTarget);
954 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
955 MVT VT, int64_t Offset,
959 // Truncate (with sign-extension) the offset value to the pointer size.
960 unsigned BitWidth = TLI.getPointerTy().getSizeInBits();
962 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth));
964 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
966 // If GV is an alias then use the aliasee for determining thread-localness.
967 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
968 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
971 if (GVar && GVar->isThreadLocal())
972 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
974 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
977 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
979 ID.AddInteger(Offset);
981 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
982 return SDValue(E, 0);
983 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>();
984 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset);
985 CSEMap.InsertNode(N, IP);
986 AllNodes.push_back(N);
987 return SDValue(N, 0);
990 SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
991 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
997 return SDValue(E, 0);
998 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>();
999 new (N) FrameIndexSDNode(FI, VT, isTarget);
1000 CSEMap.InsertNode(N, IP);
1001 AllNodes.push_back(N);
1002 return SDValue(N, 0);
1005 SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){
1006 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1007 FoldingSetNodeID ID;
1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1012 return SDValue(E, 0);
1013 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>();
1014 new (N) JumpTableSDNode(JTI, VT, isTarget);
1015 CSEMap.InsertNode(N, IP);
1016 AllNodes.push_back(N);
1017 return SDValue(N, 0);
1020 SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
1021 unsigned Alignment, int Offset,
1024 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType());
1025 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1026 FoldingSetNodeID ID;
1027 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1028 ID.AddInteger(Alignment);
1029 ID.AddInteger(Offset);
1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1033 return SDValue(E, 0);
1034 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1035 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
1036 CSEMap.InsertNode(N, IP);
1037 AllNodes.push_back(N);
1038 return SDValue(N, 0);
1042 SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
1043 unsigned Alignment, int Offset,
1046 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType());
1047 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1048 FoldingSetNodeID ID;
1049 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1050 ID.AddInteger(Alignment);
1051 ID.AddInteger(Offset);
1052 C->AddSelectionDAGCSEId(ID);
1054 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1055 return SDValue(E, 0);
1056 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1057 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
1058 CSEMap.InsertNode(N, IP);
1059 AllNodes.push_back(N);
1060 return SDValue(N, 0);
1063 SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
1064 FoldingSetNodeID ID;
1065 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1068 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1069 return SDValue(E, 0);
1070 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>();
1071 new (N) BasicBlockSDNode(MBB);
1072 CSEMap.InsertNode(N, IP);
1073 AllNodes.push_back(N);
1074 return SDValue(N, 0);
1077 SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
1078 FoldingSetNodeID ID;
1079 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
1080 ID.AddInteger(Flags.getRawBits());
1082 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1083 return SDValue(E, 0);
1084 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>();
1085 new (N) ARG_FLAGSSDNode(Flags);
1086 CSEMap.InsertNode(N, IP);
1087 AllNodes.push_back(N);
1088 return SDValue(N, 0);
1091 SDValue SelectionDAG::getValueType(MVT VT) {
1092 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
1093 ValueTypeNodes.resize(VT.getSimpleVT()+1);
1095 SDNode *&N = VT.isExtended() ?
1096 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
1098 if (N) return SDValue(N, 0);
1099 N = NodeAllocator.Allocate<VTSDNode>();
1100 new (N) VTSDNode(VT);
1101 AllNodes.push_back(N);
1102 return SDValue(N, 0);
1105 SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
1106 SDNode *&N = ExternalSymbols[Sym];
1107 if (N) return SDValue(N, 0);
1108 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1109 new (N) ExternalSymbolSDNode(false, Sym, VT);
1110 AllNodes.push_back(N);
1111 return SDValue(N, 0);
1114 SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
1115 SDNode *&N = TargetExternalSymbols[Sym];
1116 if (N) return SDValue(N, 0);
1117 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1118 new (N) ExternalSymbolSDNode(true, Sym, VT);
1119 AllNodes.push_back(N);
1120 return SDValue(N, 0);
1123 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1124 if ((unsigned)Cond >= CondCodeNodes.size())
1125 CondCodeNodes.resize(Cond+1);
1127 if (CondCodeNodes[Cond] == 0) {
1128 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>();
1129 new (N) CondCodeSDNode(Cond);
1130 CondCodeNodes[Cond] = N;
1131 AllNodes.push_back(N);
1133 return SDValue(CondCodeNodes[Cond], 0);
1136 // commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
1137 // the shuffle mask M that point at N1 to point at N2, and indices that point
1138 // N2 to point at N1.
1139 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
1141 int NElts = M.size();
1142 for (int i = 0; i != NElts; ++i) {
1150 SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1,
1151 SDValue N2, const int *Mask) {
1152 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
1153 assert(VT.isVector() && N1.getValueType().isVector() &&
1154 "Vector Shuffle VTs must be a vectors");
1155 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType()
1156 && "Vector Shuffle VTs must have same element type");
1158 // Canonicalize shuffle undef, undef -> undef
1159 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
1162 // Validate that all indices in Mask are within the range of the elements
1163 // input to the shuffle.
1164 unsigned NElts = VT.getVectorNumElements();
1165 SmallVector<int, 8> MaskVec;
1166 for (unsigned i = 0; i != NElts; ++i) {
1167 assert(Mask[i] < (int)(NElts * 2) && "Index out of range");
1168 MaskVec.push_back(Mask[i]);
1171 // Canonicalize shuffle v, v -> v, undef
1174 for (unsigned i = 0; i != NElts; ++i)
1175 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts;
1178 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
1179 if (N1.getOpcode() == ISD::UNDEF)
1180 commuteShuffle(N1, N2, MaskVec);
1182 // Canonicalize all index into lhs, -> shuffle lhs, undef
1183 // Canonicalize all index into rhs, -> shuffle rhs, undef
1184 bool AllLHS = true, AllRHS = true;
1185 bool N2Undef = N2.getOpcode() == ISD::UNDEF;
1186 for (unsigned i = 0; i != NElts; ++i) {
1187 if (MaskVec[i] >= (int)NElts) {
1192 } else if (MaskVec[i] >= 0) {
1196 if (AllLHS && AllRHS)
1197 return getUNDEF(VT);
1198 if (AllLHS && !N2Undef)
1202 commuteShuffle(N1, N2, MaskVec);
1205 // If Identity shuffle, or all shuffle in to undef, return that node.
1206 bool AllUndef = true;
1207 bool Identity = true;
1208 for (unsigned i = 0; i != NElts; ++i) {
1209 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false;
1210 if (MaskVec[i] >= 0) AllUndef = false;
1215 return getUNDEF(VT);
1217 FoldingSetNodeID ID;
1218 SDValue Ops[2] = { N1, N2 };
1219 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
1220 for (unsigned i = 0; i != NElts; ++i)
1221 ID.AddInteger(MaskVec[i]);
1224 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1225 return SDValue(E, 0);
1227 // Allocate the mask array for the node out of the BumpPtrAllocator, since
1228 // SDNode doesn't have access to it. This memory will be "leaked" when
1229 // the node is deallocated, but recovered when the NodeAllocator is released.
1230 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts);
1231 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int));
1233 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>();
1234 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc);
1235 CSEMap.InsertNode(N, IP);
1236 AllNodes.push_back(N);
1237 return SDValue(N, 0);
1240 SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
1241 SDValue Val, SDValue DTy,
1242 SDValue STy, SDValue Rnd, SDValue Sat,
1243 ISD::CvtCode Code) {
1244 // If the src and dest types are the same and the conversion is between
1245 // integer types of the same sign or two floats, no conversion is necessary.
1247 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF))
1250 FoldingSetNodeID ID;
1252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1253 return SDValue(E, 0);
1254 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>();
1255 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat };
1256 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code);
1257 CSEMap.InsertNode(N, IP);
1258 AllNodes.push_back(N);
1259 return SDValue(N, 0);
1262 SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
1263 FoldingSetNodeID ID;
1264 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1265 ID.AddInteger(RegNo);
1267 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1268 return SDValue(E, 0);
1269 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>();
1270 new (N) RegisterSDNode(RegNo, VT);
1271 CSEMap.InsertNode(N, IP);
1272 AllNodes.push_back(N);
1273 return SDValue(N, 0);
1276 SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root,
1277 unsigned Line, unsigned Col,
1279 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>();
1280 new (N) DbgStopPointSDNode(Root, Line, Col, CU);
1282 AllNodes.push_back(N);
1283 return SDValue(N, 0);
1286 SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
1289 FoldingSetNodeID ID;
1290 SDValue Ops[] = { Root };
1291 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
1292 ID.AddInteger(LabelID);
1294 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1295 return SDValue(E, 0);
1296 SDNode *N = NodeAllocator.Allocate<LabelSDNode>();
1297 new (N) LabelSDNode(Opcode, dl, Root, LabelID);
1298 CSEMap.InsertNode(N, IP);
1299 AllNodes.push_back(N);
1300 return SDValue(N, 0);
1303 SDValue SelectionDAG::getSrcValue(const Value *V) {
1304 assert((!V || isa<PointerType>(V->getType())) &&
1305 "SrcValue is not a pointer?");
1307 FoldingSetNodeID ID;
1308 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1312 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1313 return SDValue(E, 0);
1315 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>();
1316 new (N) SrcValueSDNode(V);
1317 CSEMap.InsertNode(N, IP);
1318 AllNodes.push_back(N);
1319 return SDValue(N, 0);
1322 SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
1324 const Value *v = MO.getValue();
1325 assert((!v || isa<PointerType>(v->getType())) &&
1326 "SrcValue is not a pointer?");
1329 FoldingSetNodeID ID;
1330 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
1334 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1335 return SDValue(E, 0);
1337 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>();
1338 new (N) MemOperandSDNode(MO);
1339 CSEMap.InsertNode(N, IP);
1340 AllNodes.push_back(N);
1341 return SDValue(N, 0);
1344 /// getShiftAmountOperand - Return the specified value casted to
1345 /// the target's desired shift amount type.
1346 SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
1347 MVT OpTy = Op.getValueType();
1348 MVT ShTy = TLI.getShiftAmountTy();
1349 if (OpTy == ShTy || OpTy.isVector()) return Op;
1351 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1352 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op);
1355 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
1356 /// specified value type.
1357 SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
1358 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1359 unsigned ByteSize = VT.getStoreSizeInBits()/8;
1360 const Type *Ty = VT.getTypeForMVT();
1361 unsigned StackAlign =
1362 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
1364 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
1365 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1368 /// CreateStackTemporary - Create a stack temporary suitable for holding
1369 /// either of the specified value types.
1370 SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
1371 unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
1372 VT2.getStoreSizeInBits())/8;
1373 const Type *Ty1 = VT1.getTypeForMVT();
1374 const Type *Ty2 = VT2.getTypeForMVT();
1375 const TargetData *TD = TLI.getTargetData();
1376 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
1377 TD->getPrefTypeAlignment(Ty2));
1379 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1380 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align);
1381 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1384 SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
1385 SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
1386 // These setcc operations always fold.
1390 case ISD::SETFALSE2: return getConstant(0, VT);
1392 case ISD::SETTRUE2: return getConstant(1, VT);
1404 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!");
1408 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
1409 const APInt &C2 = N2C->getAPIntValue();
1410 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1411 const APInt &C1 = N1C->getAPIntValue();
1414 default: assert(0 && "Unknown integer setcc!");
1415 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1416 case ISD::SETNE: return getConstant(C1 != C2, VT);
1417 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1418 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1419 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1420 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1421 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1422 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1423 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1424 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1428 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1429 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
1430 // No compile time operations on this type yet.
1431 if (N1C->getValueType(0) == MVT::ppcf128)
1434 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
1437 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1438 return getUNDEF(VT);
1440 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1441 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1442 return getUNDEF(VT);
1444 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1445 R==APFloat::cmpLessThan, VT);
1446 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1447 return getUNDEF(VT);
1449 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1450 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1451 return getUNDEF(VT);
1453 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1454 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1455 return getUNDEF(VT);
1457 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1458 R==APFloat::cmpEqual, VT);
1459 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1460 return getUNDEF(VT);
1462 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1463 R==APFloat::cmpEqual, VT);
1464 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1465 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1466 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1467 R==APFloat::cmpEqual, VT);
1468 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1469 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1470 R==APFloat::cmpLessThan, VT);
1471 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1472 R==APFloat::cmpUnordered, VT);
1473 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1474 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1477 // Ensure that the constant occurs on the RHS.
1478 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1482 // Could not fold it.
1486 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
1487 /// use this predicate to simplify operations downstream.
1488 bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
1489 unsigned BitWidth = Op.getValueSizeInBits();
1490 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
1493 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
1494 /// this predicate to simplify operations downstream. Mask is known to be zero
1495 /// for bits that V cannot have.
1496 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
1497 unsigned Depth) const {
1498 APInt KnownZero, KnownOne;
1499 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1501 return (KnownZero & Mask) == Mask;
1504 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
1505 /// known to be either zero or one and return them in the KnownZero/KnownOne
1506 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
1508 void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
1509 APInt &KnownZero, APInt &KnownOne,
1510 unsigned Depth) const {
1511 unsigned BitWidth = Mask.getBitWidth();
1512 assert(BitWidth == Op.getValueType().getSizeInBits() &&
1513 "Mask size mismatches value type size!");
1515 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
1516 if (Depth == 6 || Mask == 0)
1517 return; // Limit search depth.
1519 APInt KnownZero2, KnownOne2;
1521 switch (Op.getOpcode()) {
1523 // We know all of the bits for a constant!
1524 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask;
1525 KnownZero = ~KnownOne & Mask;
1528 // If either the LHS or the RHS are Zero, the result is zero.
1529 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1530 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero,
1531 KnownZero2, KnownOne2, Depth+1);
1532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1533 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1535 // Output known-1 bits are only known if set in both the LHS & RHS.
1536 KnownOne &= KnownOne2;
1537 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1538 KnownZero |= KnownZero2;
1541 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1542 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne,
1543 KnownZero2, KnownOne2, Depth+1);
1544 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1545 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1547 // Output known-0 bits are only known if clear in both the LHS & RHS.
1548 KnownZero &= KnownZero2;
1549 // Output known-1 are known to be set if set in either the LHS | RHS.
1550 KnownOne |= KnownOne2;
1553 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1554 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
1555 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1558 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1559 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1560 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1561 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1562 KnownZero = KnownZeroOut;
1566 APInt Mask2 = APInt::getAllOnesValue(BitWidth);
1567 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1);
1568 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1569 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1570 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1572 // If low bits are zero in either operand, output low known-0 bits.
1573 // Also compute a conserative estimate for high known-0 bits.
1574 // More trickiness is possible, but this is sufficient for the
1575 // interesting case of alignment computation.
1577 unsigned TrailZ = KnownZero.countTrailingOnes() +
1578 KnownZero2.countTrailingOnes();
1579 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() +
1580 KnownZero2.countLeadingOnes(),
1581 BitWidth) - BitWidth;
1583 TrailZ = std::min(TrailZ, BitWidth);
1584 LeadZ = std::min(LeadZ, BitWidth);
1585 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
1586 APInt::getHighBitsSet(BitWidth, LeadZ);
1591 // For the purposes of computing leading zeros we can conservatively
1592 // treat a udiv as a logical right shift by the power of 2 known to
1593 // be less than the denominator.
1594 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1595 ComputeMaskedBits(Op.getOperand(0),
1596 AllOnes, KnownZero2, KnownOne2, Depth+1);
1597 unsigned LeadZ = KnownZero2.countLeadingOnes();
1601 ComputeMaskedBits(Op.getOperand(1),
1602 AllOnes, KnownZero2, KnownOne2, Depth+1);
1603 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
1604 if (RHSUnknownLeadingOnes != BitWidth)
1605 LeadZ = std::min(BitWidth,
1606 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1);
1608 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask;
1612 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
1613 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
1614 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1615 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1617 // Only known if known in both the LHS and RHS.
1618 KnownOne &= KnownOne2;
1619 KnownZero &= KnownZero2;
1621 case ISD::SELECT_CC:
1622 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
1623 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
1624 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1625 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1627 // Only known if known in both the LHS and RHS.
1628 KnownOne &= KnownOne2;
1629 KnownZero &= KnownZero2;
1637 if (Op.getResNo() != 1)
1639 // The boolean result conforms to getBooleanContents. Fall through.
1641 // If we know the result of a setcc has the top bits zero, use this info.
1642 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
1644 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1647 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
1648 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1649 unsigned ShAmt = SA->getZExtValue();
1651 // If the shift count is an invalid immediate, don't do anything.
1652 if (ShAmt >= BitWidth)
1655 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt),
1656 KnownZero, KnownOne, Depth+1);
1657 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1658 KnownZero <<= ShAmt;
1660 // low bits known zero.
1661 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt);
1665 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
1666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1667 unsigned ShAmt = SA->getZExtValue();
1669 // If the shift count is an invalid immediate, don't do anything.
1670 if (ShAmt >= BitWidth)
1673 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt),
1674 KnownZero, KnownOne, Depth+1);
1675 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1676 KnownZero = KnownZero.lshr(ShAmt);
1677 KnownOne = KnownOne.lshr(ShAmt);
1679 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1680 KnownZero |= HighBits; // High bits known zero.
1684 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1685 unsigned ShAmt = SA->getZExtValue();
1687 // If the shift count is an invalid immediate, don't do anything.
1688 if (ShAmt >= BitWidth)
1691 APInt InDemandedMask = (Mask << ShAmt);
1692 // If any of the demanded bits are produced by the sign extension, we also
1693 // demand the input sign bit.
1694 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1695 if (HighBits.getBoolValue())
1696 InDemandedMask |= APInt::getSignBit(BitWidth);
1698 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
1700 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1701 KnownZero = KnownZero.lshr(ShAmt);
1702 KnownOne = KnownOne.lshr(ShAmt);
1704 // Handle the sign bits.
1705 APInt SignBit = APInt::getSignBit(BitWidth);
1706 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask.
1708 if (KnownZero.intersects(SignBit)) {
1709 KnownZero |= HighBits; // New bits are known zero.
1710 } else if (KnownOne.intersects(SignBit)) {
1711 KnownOne |= HighBits; // New bits are known one.
1715 case ISD::SIGN_EXTEND_INREG: {
1716 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1717 unsigned EBits = EVT.getSizeInBits();
1719 // Sign extension. Compute the demanded bits in the result that are not
1720 // present in the input.
1721 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask;
1723 APInt InSignBit = APInt::getSignBit(EBits);
1724 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits);
1726 // If the sign extended bits are demanded, we know that the sign
1728 InSignBit.zext(BitWidth);
1729 if (NewBits.getBoolValue())
1730 InputDemandedBits |= InSignBit;
1732 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
1733 KnownZero, KnownOne, Depth+1);
1734 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1736 // If the sign bit of the input is known set or clear, then we know the
1737 // top bits of the result.
1738 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear
1739 KnownZero |= NewBits;
1740 KnownOne &= ~NewBits;
1741 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1742 KnownOne |= NewBits;
1743 KnownZero &= ~NewBits;
1744 } else { // Input sign bit unknown
1745 KnownZero &= ~NewBits;
1746 KnownOne &= ~NewBits;
1753 unsigned LowBits = Log2_32(BitWidth)+1;
1754 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits);
1759 if (ISD::isZEXTLoad(Op.getNode())) {
1760 LoadSDNode *LD = cast<LoadSDNode>(Op);
1761 MVT VT = LD->getMemoryVT();
1762 unsigned MemBits = VT.getSizeInBits();
1763 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
1767 case ISD::ZERO_EXTEND: {
1768 MVT InVT = Op.getOperand(0).getValueType();
1769 unsigned InBits = InVT.getSizeInBits();
1770 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1771 APInt InMask = Mask;
1772 InMask.trunc(InBits);
1773 KnownZero.trunc(InBits);
1774 KnownOne.trunc(InBits);
1775 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1776 KnownZero.zext(BitWidth);
1777 KnownOne.zext(BitWidth);
1778 KnownZero |= NewBits;
1781 case ISD::SIGN_EXTEND: {
1782 MVT InVT = Op.getOperand(0).getValueType();
1783 unsigned InBits = InVT.getSizeInBits();
1784 APInt InSignBit = APInt::getSignBit(InBits);
1785 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1786 APInt InMask = Mask;
1787 InMask.trunc(InBits);
1789 // If any of the sign extended bits are demanded, we know that the sign
1790 // bit is demanded. Temporarily set this bit in the mask for our callee.
1791 if (NewBits.getBoolValue())
1792 InMask |= InSignBit;
1794 KnownZero.trunc(InBits);
1795 KnownOne.trunc(InBits);
1796 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1798 // Note if the sign bit is known to be zero or one.
1799 bool SignBitKnownZero = KnownZero.isNegative();
1800 bool SignBitKnownOne = KnownOne.isNegative();
1801 assert(!(SignBitKnownZero && SignBitKnownOne) &&
1802 "Sign bit can't be known to be both zero and one!");
1804 // If the sign bit wasn't actually demanded by our caller, we don't
1805 // want it set in the KnownZero and KnownOne result values. Reset the
1806 // mask and reapply it to the result values.
1808 InMask.trunc(InBits);
1809 KnownZero &= InMask;
1812 KnownZero.zext(BitWidth);
1813 KnownOne.zext(BitWidth);
1815 // If the sign bit is known zero or one, the top bits match.
1816 if (SignBitKnownZero)
1817 KnownZero |= NewBits;
1818 else if (SignBitKnownOne)
1819 KnownOne |= NewBits;
1822 case ISD::ANY_EXTEND: {
1823 MVT InVT = Op.getOperand(0).getValueType();
1824 unsigned InBits = InVT.getSizeInBits();
1825 APInt InMask = Mask;
1826 InMask.trunc(InBits);
1827 KnownZero.trunc(InBits);
1828 KnownOne.trunc(InBits);
1829 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1830 KnownZero.zext(BitWidth);
1831 KnownOne.zext(BitWidth);
1834 case ISD::TRUNCATE: {
1835 MVT InVT = Op.getOperand(0).getValueType();
1836 unsigned InBits = InVT.getSizeInBits();
1837 APInt InMask = Mask;
1838 InMask.zext(InBits);
1839 KnownZero.zext(InBits);
1840 KnownOne.zext(InBits);
1841 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1842 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1843 KnownZero.trunc(BitWidth);
1844 KnownOne.trunc(BitWidth);
1847 case ISD::AssertZext: {
1848 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1849 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
1850 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1852 KnownZero |= (~InMask) & Mask;
1856 // All bits are zero except the low bit.
1857 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1861 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
1862 // We know that the top bits of C-X are clear if X contains less bits
1863 // than C (i.e. no wrap-around can happen). For example, 20-X is
1864 // positive if we can prove that X is >= 0 and < 16.
1865 if (CLHS->getAPIntValue().isNonNegative()) {
1866 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
1867 // NLZ can't be BitWidth with no sign bit
1868 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
1869 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2,
1872 // If all of the MaskV bits are known to be zero, then we know the
1873 // output top bits are zero, because we now know that the output is
1875 if ((KnownZero2 & MaskV) == MaskV) {
1876 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros();
1877 // Top bits known zero.
1878 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask;
1885 // Output known-0 bits are known if clear or set in both the low clear bits
1886 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
1887 // low 3 bits clear.
1888 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes());
1889 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1890 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1891 unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
1893 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1);
1894 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1895 KnownZeroOut = std::min(KnownZeroOut,
1896 KnownZero2.countTrailingOnes());
1898 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut);
1902 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1903 const APInt &RA = Rem->getAPIntValue();
1904 if (RA.isPowerOf2() || (-RA).isPowerOf2()) {
1905 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA;
1906 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
1907 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
1909 // If the sign bit of the first operand is zero, the sign bit of
1910 // the result is zero. If the first operand has no one bits below
1911 // the second operand's single 1 bit, its sign will be zero.
1912 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
1913 KnownZero2 |= ~LowBits;
1915 KnownZero |= KnownZero2 & Mask;
1917 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1922 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1923 const APInt &RA = Rem->getAPIntValue();
1924 if (RA.isPowerOf2()) {
1925 APInt LowBits = (RA - 1);
1926 APInt Mask2 = LowBits & Mask;
1927 KnownZero |= ~LowBits & Mask;
1928 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1);
1929 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1934 // Since the result is less than or equal to either operand, any leading
1935 // zero bits in either operand must also exist in the result.
1936 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1937 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne,
1939 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2,
1942 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(),
1943 KnownZero2.countLeadingOnes());
1945 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask;
1949 // Allow the target to implement this method for its nodes.
1950 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1951 case ISD::INTRINSIC_WO_CHAIN:
1952 case ISD::INTRINSIC_W_CHAIN:
1953 case ISD::INTRINSIC_VOID:
1954 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this);
1960 /// ComputeNumSignBits - Return the number of times the sign bit of the
1961 /// register is replicated into the other bits. We know that at least 1 bit
1962 /// is always equal to the sign bit (itself), but other cases can give us
1963 /// information. For example, immediately after an "SRA X, 2", we know that
1964 /// the top 3 bits are all equal to each other, so we return 3.
1965 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
1966 MVT VT = Op.getValueType();
1967 assert(VT.isInteger() && "Invalid VT!");
1968 unsigned VTBits = VT.getSizeInBits();
1970 unsigned FirstAnswer = 1;
1973 return 1; // Limit search depth.
1975 switch (Op.getOpcode()) {
1977 case ISD::AssertSext:
1978 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1979 return VTBits-Tmp+1;
1980 case ISD::AssertZext:
1981 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1984 case ISD::Constant: {
1985 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
1986 // If negative, return # leading ones.
1987 if (Val.isNegative())
1988 return Val.countLeadingOnes();
1990 // Return # leading zeros.
1991 return Val.countLeadingZeros();
1994 case ISD::SIGN_EXTEND:
1995 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
1996 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
1998 case ISD::SIGN_EXTEND_INREG:
1999 // Max of the input and what this extends.
2000 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
2003 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2004 return std::max(Tmp, Tmp2);
2007 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2008 // SRA X, C -> adds C sign bits.
2009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2010 Tmp += C->getZExtValue();
2011 if (Tmp > VTBits) Tmp = VTBits;
2015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2016 // shl destroys sign bits.
2017 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2018 if (C->getZExtValue() >= VTBits || // Bad shift.
2019 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out.
2020 return Tmp - C->getZExtValue();
2025 case ISD::XOR: // NOT is handled here.
2026 // Logical binary ops preserve the number of sign bits at the worst.
2027 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2029 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2030 FirstAnswer = std::min(Tmp, Tmp2);
2031 // We computed what we know about the sign bits as our first
2032 // answer. Now proceed to the generic code that uses
2033 // ComputeMaskedBits, and pick whichever answer is better.
2038 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2039 if (Tmp == 1) return 1; // Early out.
2040 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1);
2041 return std::min(Tmp, Tmp2);
2049 if (Op.getResNo() != 1)
2051 // The boolean result conforms to getBooleanContents. Fall through.
2053 // If setcc returns 0/-1, all bits are sign bits.
2054 if (TLI.getBooleanContents() ==
2055 TargetLowering::ZeroOrNegativeOneBooleanContent)
2060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2061 unsigned RotAmt = C->getZExtValue() & (VTBits-1);
2063 // Handle rotate right by N like a rotate left by 32-N.
2064 if (Op.getOpcode() == ISD::ROTR)
2065 RotAmt = (VTBits-RotAmt) & (VTBits-1);
2067 // If we aren't rotating out all of the known-in sign bits, return the
2068 // number that are left. This handles rotl(sext(x), 1) for example.
2069 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2070 if (Tmp > RotAmt+1) return Tmp-RotAmt;
2074 // Add can have at most one carry bit. Thus we know that the output
2075 // is, at worst, one more bit than the inputs.
2076 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2077 if (Tmp == 1) return 1; // Early out.
2079 // Special case decrementing a value (ADD X, -1):
2080 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
2081 if (CRHS->isAllOnesValue()) {
2082 APInt KnownZero, KnownOne;
2083 APInt Mask = APInt::getAllOnesValue(VTBits);
2084 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2086 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2088 if ((KnownZero | APInt(VTBits, 1)) == Mask)
2091 // If we are subtracting one from a positive number, there is no carry
2092 // out of the result.
2093 if (KnownZero.isNegative())
2097 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2098 if (Tmp2 == 1) return 1;
2099 return std::min(Tmp, Tmp2)-1;
2103 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2104 if (Tmp2 == 1) return 1;
2107 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
2108 if (CLHS->isNullValue()) {
2109 APInt KnownZero, KnownOne;
2110 APInt Mask = APInt::getAllOnesValue(VTBits);
2111 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
2112 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2114 if ((KnownZero | APInt(VTBits, 1)) == Mask)
2117 // If the input is known to be positive (the sign bit is known clear),
2118 // the output of the NEG has the same number of sign bits as the input.
2119 if (KnownZero.isNegative())
2122 // Otherwise, we treat this like a SUB.
2125 // Sub can have at most one carry bit. Thus we know that the output
2126 // is, at worst, one more bit than the inputs.
2127 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2128 if (Tmp == 1) return 1; // Early out.
2129 return std::min(Tmp, Tmp2)-1;
2132 // FIXME: it's tricky to do anything useful for this, but it is an important
2133 // case for targets like X86.
2137 // Handle LOADX separately here. EXTLOAD case will fallthrough.
2138 if (Op.getOpcode() == ISD::LOAD) {
2139 LoadSDNode *LD = cast<LoadSDNode>(Op);
2140 unsigned ExtType = LD->getExtensionType();
2143 case ISD::SEXTLOAD: // '17' bits known
2144 Tmp = LD->getMemoryVT().getSizeInBits();
2145 return VTBits-Tmp+1;
2146 case ISD::ZEXTLOAD: // '16' bits known
2147 Tmp = LD->getMemoryVT().getSizeInBits();
2152 // Allow the target to implement this method for its nodes.
2153 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2154 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2155 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2156 Op.getOpcode() == ISD::INTRINSIC_VOID) {
2157 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth);
2158 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits);
2161 // Finally, if we can prove that the top bits of the result are 0's or 1's,
2162 // use this information.
2163 APInt KnownZero, KnownOne;
2164 APInt Mask = APInt::getAllOnesValue(VTBits);
2165 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
2167 if (KnownZero.isNegative()) { // sign bit is 0
2169 } else if (KnownOne.isNegative()) { // sign bit is 1;
2176 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
2177 // the number of identical bits in the top of the input value.
2179 Mask <<= Mask.getBitWidth()-VTBits;
2180 // Return # leading zeros. We use 'min' here in case Val was zero before
2181 // shifting. We don't want to return '64' as for an i32 "0".
2182 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros()));
2186 bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
2187 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2188 if (!GA) return false;
2189 if (GA->getOffset() != 0) return false;
2190 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal());
2191 if (!GV) return false;
2192 MachineModuleInfo *MMI = getMachineModuleInfo();
2193 return MMI && MMI->hasDebugInfo();
2197 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
2198 /// element of the result of the vector shuffle.
2199 SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N,
2201 MVT VT = N->getValueType(0);
2202 DebugLoc dl = N->getDebugLoc();
2203 if (N->getMaskElt(i) < 0)
2204 return getUNDEF(VT.getVectorElementType());
2205 unsigned Index = N->getMaskElt(i);
2206 unsigned NumElems = VT.getVectorNumElements();
2207 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
2210 if (V.getOpcode() == ISD::BIT_CONVERT) {
2211 V = V.getOperand(0);
2212 MVT VVT = V.getValueType();
2213 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
2216 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
2217 return (Index == 0) ? V.getOperand(0)
2218 : getUNDEF(VT.getVectorElementType());
2219 if (V.getOpcode() == ISD::BUILD_VECTOR)
2220 return V.getOperand(Index);
2221 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V))
2222 return getShuffleScalarElt(SVN, Index);
2227 /// getNode - Gets or creates the specified node.
2229 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
2230 FoldingSetNodeID ID;
2231 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
2233 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2234 return SDValue(E, 0);
2235 SDNode *N = NodeAllocator.Allocate<SDNode>();
2236 new (N) SDNode(Opcode, DL, getVTList(VT));
2237 CSEMap.InsertNode(N, IP);
2239 AllNodes.push_back(N);
2243 return SDValue(N, 0);
2246 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
2247 MVT VT, SDValue Operand) {
2248 // Constant fold unary operations with an integer constant operand.
2249 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
2250 const APInt &Val = C->getAPIntValue();
2251 unsigned BitWidth = VT.getSizeInBits();
2254 case ISD::SIGN_EXTEND:
2255 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT);
2256 case ISD::ANY_EXTEND:
2257 case ISD::ZERO_EXTEND:
2259 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT);
2260 case ISD::UINT_TO_FP:
2261 case ISD::SINT_TO_FP: {
2262 const uint64_t zero[] = {0, 0};
2263 // No compile time operations on this type.
2264 if (VT==MVT::ppcf128)
2266 APFloat apf = APFloat(APInt(BitWidth, 2, zero));
2267 (void)apf.convertFromAPInt(Val,
2268 Opcode==ISD::SINT_TO_FP,
2269 APFloat::rmNearestTiesToEven);
2270 return getConstantFP(apf, VT);
2272 case ISD::BIT_CONVERT:
2273 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
2274 return getConstantFP(Val.bitsToFloat(), VT);
2275 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
2276 return getConstantFP(Val.bitsToDouble(), VT);
2279 return getConstant(Val.byteSwap(), VT);
2281 return getConstant(Val.countPopulation(), VT);
2283 return getConstant(Val.countLeadingZeros(), VT);
2285 return getConstant(Val.countTrailingZeros(), VT);
2289 // Constant fold unary operations with a floating point constant operand.
2290 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
2291 APFloat V = C->getValueAPF(); // make copy
2292 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
2296 return getConstantFP(V, VT);
2299 return getConstantFP(V, VT);
2301 case ISD::FP_EXTEND: {
2303 // This can return overflow, underflow, or inexact; we don't care.
2304 // FIXME need to be more flexible about rounding mode.
2305 (void)V.convert(*MVTToAPFloatSemantics(VT),
2306 APFloat::rmNearestTiesToEven, &ignored);
2307 return getConstantFP(V, VT);
2309 case ISD::FP_TO_SINT:
2310 case ISD::FP_TO_UINT: {
2313 assert(integerPartWidth >= 64);
2314 // FIXME need to be more flexible about rounding mode.
2315 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(),
2316 Opcode==ISD::FP_TO_SINT,
2317 APFloat::rmTowardZero, &ignored);
2318 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual
2320 APInt api(VT.getSizeInBits(), 2, x);
2321 return getConstant(api, VT);
2323 case ISD::BIT_CONVERT:
2324 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
2325 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
2326 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
2327 return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
2333 unsigned OpOpcode = Operand.getNode()->getOpcode();
2335 case ISD::TokenFactor:
2336 case ISD::MERGE_VALUES:
2337 case ISD::CONCAT_VECTORS:
2338 return Operand; // Factor, merge or concat of one node? No need.
2339 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node");
2340 case ISD::FP_EXTEND:
2341 assert(VT.isFloatingPoint() &&
2342 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
2343 if (Operand.getValueType() == VT) return Operand; // noop conversion.
2344 if (Operand.getOpcode() == ISD::UNDEF)
2345 return getUNDEF(VT);
2347 case ISD::SIGN_EXTEND:
2348 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2349 "Invalid SIGN_EXTEND!");
2350 if (Operand.getValueType() == VT) return Operand; // noop extension
2351 assert(Operand.getValueType().bitsLT(VT)
2352 && "Invalid sext node, dst < src!");
2353 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2354 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2356 case ISD::ZERO_EXTEND:
2357 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2358 "Invalid ZERO_EXTEND!");
2359 if (Operand.getValueType() == VT) return Operand; // noop extension
2360 assert(Operand.getValueType().bitsLT(VT)
2361 && "Invalid zext node, dst < src!");
2362 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2363 return getNode(ISD::ZERO_EXTEND, DL, VT,
2364 Operand.getNode()->getOperand(0));
2366 case ISD::ANY_EXTEND:
2367 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2368 "Invalid ANY_EXTEND!");
2369 if (Operand.getValueType() == VT) return Operand; // noop extension
2370 assert(Operand.getValueType().bitsLT(VT)
2371 && "Invalid anyext node, dst < src!");
2372 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
2373 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
2374 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2377 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2378 "Invalid TRUNCATE!");
2379 if (Operand.getValueType() == VT) return Operand; // noop truncate
2380 assert(Operand.getValueType().bitsGT(VT)
2381 && "Invalid truncate node, src < dst!");
2382 if (OpOpcode == ISD::TRUNCATE)
2383 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2384 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2385 OpOpcode == ISD::ANY_EXTEND) {
2386 // If the source is smaller than the dest, we still need an extend.
2387 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
2388 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2389 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
2390 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2392 return Operand.getNode()->getOperand(0);
2395 case ISD::BIT_CONVERT:
2396 // Basic sanity checking.
2397 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits()
2398 && "Cannot BIT_CONVERT between types of different sizes!");
2399 if (VT == Operand.getValueType()) return Operand; // noop conversion.
2400 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
2401 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
2402 if (OpOpcode == ISD::UNDEF)
2403 return getUNDEF(VT);
2405 case ISD::SCALAR_TO_VECTOR:
2406 assert(VT.isVector() && !Operand.getValueType().isVector() &&
2407 (VT.getVectorElementType() == Operand.getValueType() ||
2408 (VT.getVectorElementType().isInteger() &&
2409 Operand.getValueType().isInteger() &&
2410 VT.getVectorElementType().bitsLE(Operand.getValueType()))) &&
2411 "Illegal SCALAR_TO_VECTOR node!");
2412 if (OpOpcode == ISD::UNDEF)
2413 return getUNDEF(VT);
2414 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
2415 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2416 isa<ConstantSDNode>(Operand.getOperand(1)) &&
2417 Operand.getConstantOperandVal(1) == 0 &&
2418 Operand.getOperand(0).getValueType() == VT)
2419 return Operand.getOperand(0);
2422 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
2423 if (UnsafeFPMath && OpOpcode == ISD::FSUB)
2424 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2425 Operand.getNode()->getOperand(0));
2426 if (OpOpcode == ISD::FNEG) // --X -> X
2427 return Operand.getNode()->getOperand(0);
2430 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2431 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
2436 SDVTList VTs = getVTList(VT);
2437 if (VT != MVT::Flag) { // Don't CSE flag producing nodes
2438 FoldingSetNodeID ID;
2439 SDValue Ops[1] = { Operand };
2440 AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
2442 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2443 return SDValue(E, 0);
2444 N = NodeAllocator.Allocate<UnarySDNode>();
2445 new (N) UnarySDNode(Opcode, DL, VTs, Operand);
2446 CSEMap.InsertNode(N, IP);
2448 N = NodeAllocator.Allocate<UnarySDNode>();
2449 new (N) UnarySDNode(Opcode, DL, VTs, Operand);
2452 AllNodes.push_back(N);
2456 return SDValue(N, 0);
2459 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode,
2461 ConstantSDNode *Cst1,
2462 ConstantSDNode *Cst2) {
2463 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue();
2466 case ISD::ADD: return getConstant(C1 + C2, VT);
2467 case ISD::SUB: return getConstant(C1 - C2, VT);
2468 case ISD::MUL: return getConstant(C1 * C2, VT);
2470 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT);
2473 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT);
2476 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT);
2479 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT);
2481 case ISD::AND: return getConstant(C1 & C2, VT);
2482 case ISD::OR: return getConstant(C1 | C2, VT);
2483 case ISD::XOR: return getConstant(C1 ^ C2, VT);
2484 case ISD::SHL: return getConstant(C1 << C2, VT);
2485 case ISD::SRL: return getConstant(C1.lshr(C2), VT);
2486 case ISD::SRA: return getConstant(C1.ashr(C2), VT);
2487 case ISD::ROTL: return getConstant(C1.rotl(C2), VT);
2488 case ISD::ROTR: return getConstant(C1.rotr(C2), VT);
2495 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2496 SDValue N1, SDValue N2) {
2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2498 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2501 case ISD::TokenFactor:
2502 assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
2503 N2.getValueType() == MVT::Other && "Invalid token factor!");
2504 // Fold trivial token factors.
2505 if (N1.getOpcode() == ISD::EntryToken) return N2;
2506 if (N2.getOpcode() == ISD::EntryToken) return N1;
2507 if (N1 == N2) return N1;
2509 case ISD::CONCAT_VECTORS:
2510 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2511 // one big BUILD_VECTOR.
2512 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2513 N2.getOpcode() == ISD::BUILD_VECTOR) {
2514 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2515 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2516 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2520 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2521 N1.getValueType() == VT && "Binary operator types must match!");
2522 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
2523 // worth handling here.
2524 if (N2C && N2C->isNullValue())
2526 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X
2533 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2534 N1.getValueType() == VT && "Binary operator types must match!");
2535 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so
2536 // it's worth handling here.
2537 if (N2C && N2C->isNullValue())
2547 assert(VT.isInteger() && "This operator does not apply to FP types!");
2555 if (Opcode == ISD::FADD) {
2557 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1))
2558 if (CFP->getValueAPF().isZero())
2561 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2))
2562 if (CFP->getValueAPF().isZero())
2564 } else if (Opcode == ISD::FSUB) {
2566 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2))
2567 if (CFP->getValueAPF().isZero())
2571 assert(N1.getValueType() == N2.getValueType() &&
2572 N1.getValueType() == VT && "Binary operator types must match!");
2574 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2575 assert(N1.getValueType() == VT &&
2576 N1.getValueType().isFloatingPoint() &&
2577 N2.getValueType().isFloatingPoint() &&
2578 "Invalid FCOPYSIGN!");
2585 assert(VT == N1.getValueType() &&
2586 "Shift operators return type must be the same as their first arg");
2587 assert(VT.isInteger() && N2.getValueType().isInteger() &&
2588 "Shifts only work on integers");
2590 // Always fold shifts of i1 values so the code generator doesn't need to
2591 // handle them. Since we know the size of the shift has to be less than the
2592 // size of the value, the shift/rotate count is guaranteed to be zero.
2596 case ISD::FP_ROUND_INREG: {
2597 MVT EVT = cast<VTSDNode>(N2)->getVT();
2598 assert(VT == N1.getValueType() && "Not an inreg round!");
2599 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
2600 "Cannot FP_ROUND_INREG integer types");
2601 assert(EVT.bitsLE(VT) && "Not rounding down!");
2602 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
2606 assert(VT.isFloatingPoint() &&
2607 N1.getValueType().isFloatingPoint() &&
2608 VT.bitsLE(N1.getValueType()) &&
2609 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
2610 if (N1.getValueType() == VT) return N1; // noop conversion.
2612 case ISD::AssertSext:
2613 case ISD::AssertZext: {
2614 MVT EVT = cast<VTSDNode>(N2)->getVT();
2615 assert(VT == N1.getValueType() && "Not an inreg extend!");
2616 assert(VT.isInteger() && EVT.isInteger() &&
2617 "Cannot *_EXTEND_INREG FP types");
2618 assert(EVT.bitsLE(VT) && "Not extending!");
2619 if (VT == EVT) return N1; // noop assertion.
2622 case ISD::SIGN_EXTEND_INREG: {
2623 MVT EVT = cast<VTSDNode>(N2)->getVT();
2624 assert(VT == N1.getValueType() && "Not an inreg extend!");
2625 assert(VT.isInteger() && EVT.isInteger() &&
2626 "Cannot *_EXTEND_INREG FP types");
2627 assert(EVT.bitsLE(VT) && "Not extending!");
2628 if (EVT == VT) return N1; // Not actually extending
2631 APInt Val = N1C->getAPIntValue();
2632 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits();
2633 Val <<= Val.getBitWidth()-FromBits;
2634 Val = Val.ashr(Val.getBitWidth()-FromBits);
2635 return getConstant(Val, VT);
2639 case ISD::EXTRACT_VECTOR_ELT:
2640 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
2641 if (N1.getOpcode() == ISD::UNDEF)
2642 return getUNDEF(VT);
2644 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
2645 // expanding copies of large vectors from registers.
2647 N1.getOpcode() == ISD::CONCAT_VECTORS &&
2648 N1.getNumOperands() > 0) {
2650 N1.getOperand(0).getValueType().getVectorNumElements();
2651 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
2652 N1.getOperand(N2C->getZExtValue() / Factor),
2653 getConstant(N2C->getZExtValue() % Factor,
2654 N2.getValueType()));
2657 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
2658 // expanding large vector constants.
2659 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
2660 SDValue Elt = N1.getOperand(N2C->getZExtValue());
2661 if (Elt.getValueType() != VT) {
2662 // If the vector element type is not legal, the BUILD_VECTOR operands
2663 // are promoted and implicitly truncated. Make that explicit here.
2664 assert(VT.isInteger() && Elt.getValueType().isInteger() &&
2665 VT.bitsLE(Elt.getValueType()) &&
2666 "Bad type for BUILD_VECTOR operand");
2667 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt);
2672 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
2673 // operations are lowered to scalars.
2674 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
2675 // If the indices are the same, return the inserted element.
2676 if (N1.getOperand(2) == N2)
2677 return N1.getOperand(1);
2678 // If the indices are known different, extract the element from
2679 // the original vector.
2680 else if (isa<ConstantSDNode>(N1.getOperand(2)) &&
2681 isa<ConstantSDNode>(N2))
2682 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
2685 case ISD::EXTRACT_ELEMENT:
2686 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
2687 assert(!N1.getValueType().isVector() && !VT.isVector() &&
2688 (N1.getValueType().isInteger() == VT.isInteger()) &&
2689 "Wrong types for EXTRACT_ELEMENT!");
2691 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
2692 // 64-bit integers into 32-bit parts. Instead of building the extract of
2693 // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
2694 if (N1.getOpcode() == ISD::BUILD_PAIR)
2695 return N1.getOperand(N2C->getZExtValue());
2697 // EXTRACT_ELEMENT of a constant int is also very common.
2698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2699 unsigned ElementSize = VT.getSizeInBits();
2700 unsigned Shift = ElementSize * N2C->getZExtValue();
2701 APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
2702 return getConstant(ShiftedVal.trunc(ElementSize), VT);
2705 case ISD::EXTRACT_SUBVECTOR:
2706 if (N1.getValueType() == VT) // Trivial extraction.
2713 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C);
2714 if (SV.getNode()) return SV;
2715 } else { // Cannonicalize constant to RHS if commutative
2716 if (isCommutativeBinOp(Opcode)) {
2717 std::swap(N1C, N2C);
2723 // Constant fold FP operations.
2724 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
2725 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
2727 if (!N2CFP && isCommutativeBinOp(Opcode)) {
2728 // Cannonicalize constant to RHS if commutative
2729 std::swap(N1CFP, N2CFP);
2731 } else if (N2CFP && VT != MVT::ppcf128) {
2732 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
2733 APFloat::opStatus s;
2736 s = V1.add(V2, APFloat::rmNearestTiesToEven);
2737 if (s != APFloat::opInvalidOp)
2738 return getConstantFP(V1, VT);
2741 s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
2742 if (s!=APFloat::opInvalidOp)
2743 return getConstantFP(V1, VT);
2746 s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
2747 if (s!=APFloat::opInvalidOp)
2748 return getConstantFP(V1, VT);
2751 s = V1.divide(V2, APFloat::rmNearestTiesToEven);
2752 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2753 return getConstantFP(V1, VT);
2756 s = V1.mod(V2, APFloat::rmNearestTiesToEven);
2757 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2758 return getConstantFP(V1, VT);
2760 case ISD::FCOPYSIGN:
2762 return getConstantFP(V1, VT);
2768 // Canonicalize an UNDEF to the RHS, even over a constant.
2769 if (N1.getOpcode() == ISD::UNDEF) {
2770 if (isCommutativeBinOp(Opcode)) {
2774 case ISD::FP_ROUND_INREG:
2775 case ISD::SIGN_EXTEND_INREG:
2781 return N1; // fold op(undef, arg2) -> undef
2789 return getConstant(0, VT); // fold op(undef, arg2) -> 0
2790 // For vectors, we can't easily build an all zero vector, just return
2797 // Fold a bunch of operators when the RHS is undef.
2798 if (N2.getOpcode() == ISD::UNDEF) {
2801 if (N1.getOpcode() == ISD::UNDEF)
2802 // Handle undef ^ undef -> 0 special case. This is a common
2804 return getConstant(0, VT);
2814 return N2; // fold op(arg1, undef) -> undef
2828 return getConstant(0, VT); // fold op(arg1, undef) -> 0
2829 // For vectors, we can't easily build an all zero vector, just return
2834 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
2835 // For vectors, we can't easily build an all one vector, just return
2843 // Memoize this node if possible.
2845 SDVTList VTs = getVTList(VT);
2846 if (VT != MVT::Flag) {
2847 SDValue Ops[] = { N1, N2 };
2848 FoldingSetNodeID ID;
2849 AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
2851 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2852 return SDValue(E, 0);
2853 N = NodeAllocator.Allocate<BinarySDNode>();
2854 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
2855 CSEMap.InsertNode(N, IP);
2857 N = NodeAllocator.Allocate<BinarySDNode>();
2858 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
2861 AllNodes.push_back(N);
2865 return SDValue(N, 0);
2868 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2869 SDValue N1, SDValue N2, SDValue N3) {
2870 // Perform various simplifications.
2871 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2872 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2874 case ISD::CONCAT_VECTORS:
2875 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2876 // one big BUILD_VECTOR.
2877 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2878 N2.getOpcode() == ISD::BUILD_VECTOR &&
2879 N3.getOpcode() == ISD::BUILD_VECTOR) {
2880 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2881 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2882 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end());
2883 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2887 // Use FoldSetCC to simplify SETCC's.
2888 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL);
2889 if (Simp.getNode()) return Simp;
2894 if (N1C->getZExtValue())
2895 return N2; // select true, X, Y -> X
2897 return N3; // select false, X, Y -> Y
2900 if (N2 == N3) return N2; // select C, X, X -> X
2904 if (N2C->getZExtValue()) // Unconditional branch
2905 return getNode(ISD::BR, DL, MVT::Other, N1, N3);
2907 return N1; // Never-taken branch
2910 case ISD::VECTOR_SHUFFLE:
2911 assert(0 && "should use getVectorShuffle constructor!");
2913 case ISD::BIT_CONVERT:
2914 // Fold bit_convert nodes from a type to themselves.
2915 if (N1.getValueType() == VT)
2920 // Memoize node if it doesn't produce a flag.
2922 SDVTList VTs = getVTList(VT);
2923 if (VT != MVT::Flag) {
2924 SDValue Ops[] = { N1, N2, N3 };
2925 FoldingSetNodeID ID;
2926 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
2928 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2929 return SDValue(E, 0);
2930 N = NodeAllocator.Allocate<TernarySDNode>();
2931 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
2932 CSEMap.InsertNode(N, IP);
2934 N = NodeAllocator.Allocate<TernarySDNode>();
2935 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
2937 AllNodes.push_back(N);
2941 return SDValue(N, 0);
2944 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2945 SDValue N1, SDValue N2, SDValue N3,
2947 SDValue Ops[] = { N1, N2, N3, N4 };
2948 return getNode(Opcode, DL, VT, Ops, 4);
2951 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2952 SDValue N1, SDValue N2, SDValue N3,
2953 SDValue N4, SDValue N5) {
2954 SDValue Ops[] = { N1, N2, N3, N4, N5 };
2955 return getNode(Opcode, DL, VT, Ops, 5);
2958 /// getMemsetValue - Vectorized representation of the memset value
2960 static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
2962 unsigned NumBits = VT.isVector() ?
2963 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
2964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2965 APInt Val = APInt(NumBits, C->getZExtValue() & 255);
2967 for (unsigned i = NumBits; i > 8; i >>= 1) {
2968 Val = (Val << Shift) | Val;
2972 return DAG.getConstant(Val, VT);
2973 return DAG.getConstantFP(APFloat(Val), VT);
2976 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2977 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
2979 for (unsigned i = NumBits; i > 8; i >>= 1) {
2980 Value = DAG.getNode(ISD::OR, dl, VT,
2981 DAG.getNode(ISD::SHL, dl, VT, Value,
2982 DAG.getConstant(Shift,
2983 TLI.getShiftAmountTy())),
2991 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2992 /// used when a memcpy is turned into a memset when the source is a constant
2994 static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
2995 const TargetLowering &TLI,
2996 std::string &Str, unsigned Offset) {
2997 // Handle vector with all elements zero.
3000 return DAG.getConstant(0, VT);
3001 unsigned NumElts = VT.getVectorNumElements();
3002 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
3003 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3004 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
3007 assert(!VT.isVector() && "Can't handle vector type here!");
3008 unsigned NumBits = VT.getSizeInBits();
3009 unsigned MSB = NumBits / 8;
3011 if (TLI.isLittleEndian())
3012 Offset = Offset + MSB - 1;
3013 for (unsigned i = 0; i != MSB; ++i) {
3014 Val = (Val << 8) | (unsigned char)Str[Offset];
3015 Offset += TLI.isLittleEndian() ? -1 : 1;
3017 return DAG.getConstant(Val, VT);
3020 /// getMemBasePlusOffset - Returns base and offset node for the
3022 static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
3023 SelectionDAG &DAG) {
3024 MVT VT = Base.getValueType();
3025 return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
3026 VT, Base, DAG.getConstant(Offset, VT));
3029 /// isMemSrcFromString - Returns true if memcpy source is a string constant.
3031 static bool isMemSrcFromString(SDValue Src, std::string &Str) {
3032 unsigned SrcDelta = 0;
3033 GlobalAddressSDNode *G = NULL;
3034 if (Src.getOpcode() == ISD::GlobalAddress)
3035 G = cast<GlobalAddressSDNode>(Src);
3036 else if (Src.getOpcode() == ISD::ADD &&
3037 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3038 Src.getOperand(1).getOpcode() == ISD::Constant) {
3039 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
3040 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
3045 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3046 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false))
3052 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3053 /// to replace the memset / memcpy is below the threshold. It also returns the
3054 /// types of the sequence of memory ops to perform memset / memcpy.
3056 bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
3057 SDValue Dst, SDValue Src,
3058 unsigned Limit, uint64_t Size, unsigned &Align,
3059 std::string &Str, bool &isSrcStr,
3061 const TargetLowering &TLI) {
3062 isSrcStr = isMemSrcFromString(Src, Str);
3063 bool isSrcConst = isa<ConstantSDNode>(Src);
3064 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
3065 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
3066 if (VT != MVT::iAny) {
3067 unsigned NewAlign = (unsigned)
3068 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
3069 // If source is a string constant, this will require an unaligned load.
3070 if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
3071 if (Dst.getOpcode() != ISD::FrameIndex) {
3072 // Can't change destination alignment. It requires a unaligned store.
3076 int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
3077 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3078 if (MFI->isFixedObjectIndex(FI)) {
3079 // Can't change destination alignment. It requires a unaligned store.
3083 // Give the stack frame object a larger alignment if needed.
3084 if (MFI->getObjectAlignment(FI) < NewAlign)
3085 MFI->setObjectAlignment(FI, NewAlign);
3092 if (VT == MVT::iAny) {
3096 switch (Align & 7) {
3097 case 0: VT = MVT::i64; break;
3098 case 4: VT = MVT::i32; break;
3099 case 2: VT = MVT::i16; break;
3100 default: VT = MVT::i8; break;
3105 while (!TLI.isTypeLegal(LVT))
3106 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
3107 assert(LVT.isInteger());
3113 unsigned NumMemOps = 0;
3115 unsigned VTSize = VT.getSizeInBits() / 8;
3116 while (VTSize > Size) {
3117 // For now, only use non-vector load / store's for the left-over pieces.
3118 if (VT.isVector()) {
3120 while (!TLI.isTypeLegal(VT))
3121 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
3122 VTSize = VT.getSizeInBits() / 8;
3124 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
3129 if (++NumMemOps > Limit)
3131 MemOps.push_back(VT);
3138 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
3139 SDValue Chain, SDValue Dst,
3140 SDValue Src, uint64_t Size,
3141 unsigned Align, bool AlwaysInline,
3142 const Value *DstSV, uint64_t DstSVOff,
3143 const Value *SrcSV, uint64_t SrcSVOff){
3144 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3146 // Expand memcpy to a series of load and store ops if the size operand falls
3147 // below a certain threshold.
3148 std::vector<MVT> MemOps;
3149 uint64_t Limit = -1ULL;
3151 Limit = TLI.getMaxStoresPerMemcpy();
3152 unsigned DstAlign = Align; // Destination alignment can change.
3155 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3156 Str, CopyFromStr, DAG, TLI))
3160 bool isZeroStr = CopyFromStr && Str.empty();
3161 SmallVector<SDValue, 8> OutChains;
3162 unsigned NumMemOps = MemOps.size();
3163 uint64_t SrcOff = 0, DstOff = 0;
3164 for (unsigned i = 0; i < NumMemOps; i++) {
3166 unsigned VTSize = VT.getSizeInBits() / 8;
3167 SDValue Value, Store;
3169 if (CopyFromStr && (isZeroStr || !VT.isVector())) {
3170 // It's unlikely a store of a vector immediate can be done in a single
3171 // instruction. It would require a load from a constantpool first.
3172 // We also handle store a vector with all zero's.
3173 // FIXME: Handle other cases where store of vector immediate is done in
3174 // a single instruction.
3175 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff);
3176 Store = DAG.getStore(Chain, dl, Value,
3177 getMemBasePlusOffset(Dst, DstOff, DAG),
3178 DstSV, DstSVOff + DstOff, false, DstAlign);
3180 Value = DAG.getLoad(VT, dl, Chain,
3181 getMemBasePlusOffset(Src, SrcOff, DAG),
3182 SrcSV, SrcSVOff + SrcOff, false, Align);
3183 Store = DAG.getStore(Chain, dl, Value,
3184 getMemBasePlusOffset(Dst, DstOff, DAG),
3185 DstSV, DstSVOff + DstOff, false, DstAlign);
3187 OutChains.push_back(Store);
3192 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3193 &OutChains[0], OutChains.size());
3196 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
3197 SDValue Chain, SDValue Dst,
3198 SDValue Src, uint64_t Size,
3199 unsigned Align, bool AlwaysInline,
3200 const Value *DstSV, uint64_t DstSVOff,
3201 const Value *SrcSV, uint64_t SrcSVOff){
3202 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3204 // Expand memmove to a series of load and store ops if the size operand falls
3205 // below a certain threshold.
3206 std::vector<MVT> MemOps;
3207 uint64_t Limit = -1ULL;
3209 Limit = TLI.getMaxStoresPerMemmove();
3210 unsigned DstAlign = Align; // Destination alignment can change.
3213 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3214 Str, CopyFromStr, DAG, TLI))
3217 uint64_t SrcOff = 0, DstOff = 0;
3219 SmallVector<SDValue, 8> LoadValues;
3220 SmallVector<SDValue, 8> LoadChains;
3221 SmallVector<SDValue, 8> OutChains;
3222 unsigned NumMemOps = MemOps.size();
3223 for (unsigned i = 0; i < NumMemOps; i++) {
3225 unsigned VTSize = VT.getSizeInBits() / 8;
3226 SDValue Value, Store;
3228 Value = DAG.getLoad(VT, dl, Chain,
3229 getMemBasePlusOffset(Src, SrcOff, DAG),
3230 SrcSV, SrcSVOff + SrcOff, false, Align);
3231 LoadValues.push_back(Value);
3232 LoadChains.push_back(Value.getValue(1));
3235 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3236 &LoadChains[0], LoadChains.size());
3238 for (unsigned i = 0; i < NumMemOps; i++) {
3240 unsigned VTSize = VT.getSizeInBits() / 8;
3241 SDValue Value, Store;
3243 Store = DAG.getStore(Chain, dl, LoadValues[i],
3244 getMemBasePlusOffset(Dst, DstOff, DAG),
3245 DstSV, DstSVOff + DstOff, false, DstAlign);
3246 OutChains.push_back(Store);
3250 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3251 &OutChains[0], OutChains.size());
3254 static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl,
3255 SDValue Chain, SDValue Dst,
3256 SDValue Src, uint64_t Size,
3258 const Value *DstSV, uint64_t DstSVOff) {
3259 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3261 // Expand memset to a series of load/store ops if the size operand
3262 // falls below a certain threshold.
3263 std::vector<MVT> MemOps;
3266 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
3267 Size, Align, Str, CopyFromStr, DAG, TLI))
3270 SmallVector<SDValue, 8> OutChains;
3271 uint64_t DstOff = 0;
3273 unsigned NumMemOps = MemOps.size();
3274 for (unsigned i = 0; i < NumMemOps; i++) {
3276 unsigned VTSize = VT.getSizeInBits() / 8;
3277 SDValue Value = getMemsetValue(Src, VT, DAG, dl);
3278 SDValue Store = DAG.getStore(Chain, dl, Value,
3279 getMemBasePlusOffset(Dst, DstOff, DAG),
3280 DstSV, DstSVOff + DstOff);
3281 OutChains.push_back(Store);
3285 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3286 &OutChains[0], OutChains.size());
3289 SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
3290 SDValue Src, SDValue Size,
3291 unsigned Align, bool AlwaysInline,
3292 const Value *DstSV, uint64_t DstSVOff,
3293 const Value *SrcSV, uint64_t SrcSVOff) {
3295 // Check to see if we should lower the memcpy to loads and stores first.
3296 // For cases within the target-specified limits, this is the best choice.
3297 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3299 // Memcpy with size zero? Just return the original chain.
3300 if (ConstantSize->isNullValue())
3304 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
3305 ConstantSize->getZExtValue(),
3306 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3307 if (Result.getNode())
3311 // Then check to see if we should lower the memcpy with target-specific
3312 // code. If the target chooses to do this, this is the next best.
3314 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align,
3316 DstSV, DstSVOff, SrcSV, SrcSVOff);
3317 if (Result.getNode())
3320 // If we really need inline code and the target declined to provide it,
3321 // use a (potentially long) sequence of loads and stores.
3323 assert(ConstantSize && "AlwaysInline requires a constant size!");
3324 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
3325 ConstantSize->getZExtValue(), Align, true,
3326 DstSV, DstSVOff, SrcSV, SrcSVOff);
3329 // Emit a library call.
3330 TargetLowering::ArgListTy Args;
3331 TargetLowering::ArgListEntry Entry;
3332 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3333 Entry.Node = Dst; Args.push_back(Entry);
3334 Entry.Node = Src; Args.push_back(Entry);
3335 Entry.Node = Size; Args.push_back(Entry);
3336 // FIXME: pass in DebugLoc
3337 std::pair<SDValue,SDValue> CallResult =
3338 TLI.LowerCallTo(Chain, Type::VoidTy,
3339 false, false, false, false, CallingConv::C, false,
3340 getExternalSymbol("memcpy", TLI.getPointerTy()),
3342 return CallResult.second;
3345 SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
3346 SDValue Src, SDValue Size,
3348 const Value *DstSV, uint64_t DstSVOff,
3349 const Value *SrcSV, uint64_t SrcSVOff) {
3351 // Check to see if we should lower the memmove to loads and stores first.
3352 // For cases within the target-specified limits, this is the best choice.
3353 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3355 // Memmove with size zero? Just return the original chain.
3356 if (ConstantSize->isNullValue())
3360 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src,
3361 ConstantSize->getZExtValue(),
3362 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3363 if (Result.getNode())
3367 // Then check to see if we should lower the memmove with target-specific
3368 // code. If the target chooses to do this, this is the next best.
3370 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align,
3371 DstSV, DstSVOff, SrcSV, SrcSVOff);
3372 if (Result.getNode())
3375 // Emit a library call.
3376 TargetLowering::ArgListTy Args;
3377 TargetLowering::ArgListEntry Entry;
3378 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3379 Entry.Node = Dst; Args.push_back(Entry);
3380 Entry.Node = Src; Args.push_back(Entry);
3381 Entry.Node = Size; Args.push_back(Entry);
3382 // FIXME: pass in DebugLoc
3383 std::pair<SDValue,SDValue> CallResult =
3384 TLI.LowerCallTo(Chain, Type::VoidTy,
3385 false, false, false, false, CallingConv::C, false,
3386 getExternalSymbol("memmove", TLI.getPointerTy()),
3388 return CallResult.second;
3391 SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
3392 SDValue Src, SDValue Size,
3394 const Value *DstSV, uint64_t DstSVOff) {
3396 // Check to see if we should lower the memset to stores first.
3397 // For cases within the target-specified limits, this is the best choice.
3398 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3400 // Memset with size zero? Just return the original chain.
3401 if (ConstantSize->isNullValue())
3405 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
3406 Align, DstSV, DstSVOff);
3407 if (Result.getNode())
3411 // Then check to see if we should lower the memset with target-specific
3412 // code. If the target chooses to do this, this is the next best.
3414 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align,
3416 if (Result.getNode())
3419 // Emit a library call.
3420 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
3421 TargetLowering::ArgListTy Args;
3422 TargetLowering::ArgListEntry Entry;
3423 Entry.Node = Dst; Entry.Ty = IntPtrTy;
3424 Args.push_back(Entry);
3425 // Extend or truncate the argument to be an i32 value for the call.
3426 if (Src.getValueType().bitsGT(MVT::i32))
3427 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
3429 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
3430 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
3431 Args.push_back(Entry);
3432 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
3433 Args.push_back(Entry);
3434 // FIXME: pass in DebugLoc
3435 std::pair<SDValue,SDValue> CallResult =
3436 TLI.LowerCallTo(Chain, Type::VoidTy,
3437 false, false, false, false, CallingConv::C, false,
3438 getExternalSymbol("memset", TLI.getPointerTy()),
3440 return CallResult.second;
3443 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
3445 SDValue Ptr, SDValue Cmp,
3446 SDValue Swp, const Value* PtrVal,
3447 unsigned Alignment) {
3448 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
3449 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
3451 MVT VT = Cmp.getValueType();
3453 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3454 Alignment = getMVTAlignment(MemVT);
3456 SDVTList VTs = getVTList(VT, MVT::Other);
3457 FoldingSetNodeID ID;
3458 ID.AddInteger(MemVT.getRawBits());
3459 SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
3460 AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
3462 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3463 return SDValue(E, 0);
3464 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3465 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
3466 Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
3467 CSEMap.InsertNode(N, IP);
3468 AllNodes.push_back(N);
3469 return SDValue(N, 0);
3472 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
3474 SDValue Ptr, SDValue Val,
3475 const Value* PtrVal,
3476 unsigned Alignment) {
3477 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
3478 Opcode == ISD::ATOMIC_LOAD_SUB ||
3479 Opcode == ISD::ATOMIC_LOAD_AND ||
3480 Opcode == ISD::ATOMIC_LOAD_OR ||
3481 Opcode == ISD::ATOMIC_LOAD_XOR ||
3482 Opcode == ISD::ATOMIC_LOAD_NAND ||
3483 Opcode == ISD::ATOMIC_LOAD_MIN ||
3484 Opcode == ISD::ATOMIC_LOAD_MAX ||
3485 Opcode == ISD::ATOMIC_LOAD_UMIN ||
3486 Opcode == ISD::ATOMIC_LOAD_UMAX ||
3487 Opcode == ISD::ATOMIC_SWAP) &&
3488 "Invalid Atomic Op");
3490 MVT VT = Val.getValueType();
3492 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3493 Alignment = getMVTAlignment(MemVT);
3495 SDVTList VTs = getVTList(VT, MVT::Other);
3496 FoldingSetNodeID ID;
3497 ID.AddInteger(MemVT.getRawBits());
3498 SDValue Ops[] = {Chain, Ptr, Val};
3499 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
3501 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3502 return SDValue(E, 0);
3503 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3504 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
3505 Chain, Ptr, Val, PtrVal, Alignment);
3506 CSEMap.InsertNode(N, IP);
3507 AllNodes.push_back(N);
3508 return SDValue(N, 0);
3511 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
3512 /// Allowed to return something different (and simpler) if Simplify is true.
3513 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
3518 SmallVector<MVT, 4> VTs;
3519 VTs.reserve(NumOps);
3520 for (unsigned i = 0; i < NumOps; ++i)
3521 VTs.push_back(Ops[i].getValueType());
3522 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
3527 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
3528 const MVT *VTs, unsigned NumVTs,
3529 const SDValue *Ops, unsigned NumOps,
3530 MVT MemVT, const Value *srcValue, int SVOff,
3531 unsigned Align, bool Vol,
3532 bool ReadMem, bool WriteMem) {
3533 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
3534 MemVT, srcValue, SVOff, Align, Vol,
3539 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
3540 const SDValue *Ops, unsigned NumOps,
3541 MVT MemVT, const Value *srcValue, int SVOff,
3542 unsigned Align, bool Vol,
3543 bool ReadMem, bool WriteMem) {
3544 // Memoize the node unless it returns a flag.
3545 MemIntrinsicSDNode *N;
3546 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3547 FoldingSetNodeID ID;
3548 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3550 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3551 return SDValue(E, 0);
3553 N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
3554 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
3555 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
3556 CSEMap.InsertNode(N, IP);
3558 N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
3559 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
3560 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
3562 AllNodes.push_back(N);
3563 return SDValue(N, 0);
3567 SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
3568 bool IsTailCall, bool IsInreg, SDVTList VTs,
3569 const SDValue *Operands, unsigned NumOperands) {
3570 // Do not include isTailCall in the folding set profile.
3571 FoldingSetNodeID ID;
3572 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
3573 ID.AddInteger(CallingConv);
3574 ID.AddInteger(IsVarArgs);
3576 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
3577 // Instead of including isTailCall in the folding set, we just
3578 // set the flag of the existing node.
3580 cast<CallSDNode>(E)->setNotTailCall();
3581 return SDValue(E, 0);
3583 SDNode *N = NodeAllocator.Allocate<CallSDNode>();
3584 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg,
3585 VTs, Operands, NumOperands);
3586 CSEMap.InsertNode(N, IP);
3587 AllNodes.push_back(N);
3588 return SDValue(N, 0);
3592 SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
3593 ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
3594 SDValue Ptr, SDValue Offset,
3595 const Value *SV, int SVOffset, MVT EVT,
3596 bool isVolatile, unsigned Alignment) {
3597 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3598 Alignment = getMVTAlignment(VT);
3601 ExtType = ISD::NON_EXTLOAD;
3602 } else if (ExtType == ISD::NON_EXTLOAD) {
3603 assert(VT == EVT && "Non-extending load from different memory type!");
3607 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
3608 "Invalid vector extload!");
3610 assert(EVT.bitsLT(VT) &&
3611 "Should only be an extending load, not truncating!");
3612 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
3613 "Cannot sign/zero extend a FP/Vector load!");
3614 assert(VT.isInteger() == EVT.isInteger() &&
3615 "Cannot convert from FP to Int or Int -> FP!");
3618 bool Indexed = AM != ISD::UNINDEXED;
3619 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
3620 "Unindexed load with an offset!");
3622 SDVTList VTs = Indexed ?
3623 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
3624 SDValue Ops[] = { Chain, Ptr, Offset };
3625 FoldingSetNodeID ID;
3626 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
3627 ID.AddInteger(EVT.getRawBits());
3628 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment));
3630 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3631 return SDValue(E, 0);
3632 SDNode *N = NodeAllocator.Allocate<LoadSDNode>();
3633 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
3634 Alignment, isVolatile);
3635 CSEMap.InsertNode(N, IP);
3636 AllNodes.push_back(N);
3637 return SDValue(N, 0);
3640 SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
3641 SDValue Chain, SDValue Ptr,
3642 const Value *SV, int SVOffset,
3643 bool isVolatile, unsigned Alignment) {
3644 SDValue Undef = getUNDEF(Ptr.getValueType());
3645 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
3646 SV, SVOffset, VT, isVolatile, Alignment);
3649 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
3650 SDValue Chain, SDValue Ptr,
3652 int SVOffset, MVT EVT,
3653 bool isVolatile, unsigned Alignment) {
3654 SDValue Undef = getUNDEF(Ptr.getValueType());
3655 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
3656 SV, SVOffset, EVT, isVolatile, Alignment);
3660 SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
3661 SDValue Offset, ISD::MemIndexedMode AM) {
3662 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
3663 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
3664 "Load is already a indexed load!");
3665 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(),
3666 LD->getChain(), Base, Offset, LD->getSrcValue(),
3667 LD->getSrcValueOffset(), LD->getMemoryVT(),
3668 LD->isVolatile(), LD->getAlignment());
3671 SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
3672 SDValue Ptr, const Value *SV, int SVOffset,
3673 bool isVolatile, unsigned Alignment) {
3674 MVT VT = Val.getValueType();
3676 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3677 Alignment = getMVTAlignment(VT);
3679 SDVTList VTs = getVTList(MVT::Other);
3680 SDValue Undef = getUNDEF(Ptr.getValueType());
3681 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3682 FoldingSetNodeID ID;
3683 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3684 ID.AddInteger(VT.getRawBits());
3685 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED,
3686 isVolatile, Alignment));
3688 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3689 return SDValue(E, 0);
3690 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3691 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
3692 VT, SV, SVOffset, Alignment, isVolatile);
3693 CSEMap.InsertNode(N, IP);
3694 AllNodes.push_back(N);
3695 return SDValue(N, 0);
3698 SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
3699 SDValue Ptr, const Value *SV,
3700 int SVOffset, MVT SVT,
3701 bool isVolatile, unsigned Alignment) {
3702 MVT VT = Val.getValueType();
3705 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
3707 assert(VT.bitsGT(SVT) && "Not a truncation?");
3708 assert(VT.isInteger() == SVT.isInteger() &&
3709 "Can't do FP-INT conversion!");
3711 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3712 Alignment = getMVTAlignment(VT);
3714 SDVTList VTs = getVTList(MVT::Other);
3715 SDValue Undef = getUNDEF(Ptr.getValueType());
3716 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3717 FoldingSetNodeID ID;
3718 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3719 ID.AddInteger(SVT.getRawBits());
3720 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED,
3721 isVolatile, Alignment));
3723 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3724 return SDValue(E, 0);
3725 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3726 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
3727 SVT, SV, SVOffset, Alignment, isVolatile);
3728 CSEMap.InsertNode(N, IP);
3729 AllNodes.push_back(N);
3730 return SDValue(N, 0);
3734 SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
3735 SDValue Offset, ISD::MemIndexedMode AM) {
3736 StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
3737 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
3738 "Store is already a indexed store!");
3739 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
3740 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
3741 FoldingSetNodeID ID;
3742 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3743 ID.AddInteger(ST->getMemoryVT().getRawBits());
3744 ID.AddInteger(ST->getRawSubclassData());
3746 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3747 return SDValue(E, 0);
3748 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3749 new (N) StoreSDNode(Ops, dl, VTs, AM,
3750 ST->isTruncatingStore(), ST->getMemoryVT(),
3751 ST->getSrcValue(), ST->getSrcValueOffset(),
3752 ST->getAlignment(), ST->isVolatile());
3753 CSEMap.InsertNode(N, IP);
3754 AllNodes.push_back(N);
3755 return SDValue(N, 0);
3758 SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
3759 SDValue Chain, SDValue Ptr,
3761 SDValue Ops[] = { Chain, Ptr, SV };
3762 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
3765 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
3766 const SDUse *Ops, unsigned NumOps) {
3768 case 0: return getNode(Opcode, DL, VT);
3769 case 1: return getNode(Opcode, DL, VT, Ops[0]);
3770 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
3771 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
3775 // Copy from an SDUse array into an SDValue array for use with
3776 // the regular getNode logic.
3777 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
3778 return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
3781 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
3782 const SDValue *Ops, unsigned NumOps) {
3784 case 0: return getNode(Opcode, DL, VT);
3785 case 1: return getNode(Opcode, DL, VT, Ops[0]);
3786 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
3787 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
3793 case ISD::SELECT_CC: {
3794 assert(NumOps == 5 && "SELECT_CC takes 5 operands!");
3795 assert(Ops[0].getValueType() == Ops[1].getValueType() &&
3796 "LHS and RHS of condition must have same type!");
3797 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3798 "True and False arms of SelectCC must have same type!");
3799 assert(Ops[2].getValueType() == VT &&
3800 "select_cc node must be of same type as true and false value!");
3804 assert(NumOps == 5 && "BR_CC takes 5 operands!");
3805 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3806 "LHS/RHS of comparison should match types!");
3813 SDVTList VTs = getVTList(VT);
3815 if (VT != MVT::Flag) {
3816 FoldingSetNodeID ID;
3817 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
3820 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3821 return SDValue(E, 0);
3823 N = NodeAllocator.Allocate<SDNode>();
3824 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
3825 CSEMap.InsertNode(N, IP);
3827 N = NodeAllocator.Allocate<SDNode>();
3828 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
3831 AllNodes.push_back(N);
3835 return SDValue(N, 0);
3838 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
3839 const std::vector<MVT> &ResultTys,
3840 const SDValue *Ops, unsigned NumOps) {
3841 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
3845 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
3846 const MVT *VTs, unsigned NumVTs,
3847 const SDValue *Ops, unsigned NumOps) {
3849 return getNode(Opcode, DL, VTs[0], Ops, NumOps);
3850 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
3853 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3854 const SDValue *Ops, unsigned NumOps) {
3855 if (VTList.NumVTs == 1)
3856 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps);
3859 // FIXME: figure out how to safely handle things like
3860 // int foo(int x) { return 1 << (x & 255); }
3861 // int bar() { return foo(256); }
3863 case ISD::SRA_PARTS:
3864 case ISD::SRL_PARTS:
3865 case ISD::SHL_PARTS:
3866 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3867 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
3868 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
3869 else if (N3.getOpcode() == ISD::AND)
3870 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
3871 // If the and is only masking out bits that cannot effect the shift,
3872 // eliminate the and.
3873 unsigned NumBits = VT.getSizeInBits()*2;
3874 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
3875 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
3881 // Memoize the node unless it returns a flag.
3883 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3884 FoldingSetNodeID ID;
3885 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3887 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3888 return SDValue(E, 0);
3890 N = NodeAllocator.Allocate<UnarySDNode>();
3891 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
3892 } else if (NumOps == 2) {
3893 N = NodeAllocator.Allocate<BinarySDNode>();
3894 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
3895 } else if (NumOps == 3) {
3896 N = NodeAllocator.Allocate<TernarySDNode>();
3897 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
3899 N = NodeAllocator.Allocate<SDNode>();
3900 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
3902 CSEMap.InsertNode(N, IP);
3905 N = NodeAllocator.Allocate<UnarySDNode>();
3906 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
3907 } else if (NumOps == 2) {
3908 N = NodeAllocator.Allocate<BinarySDNode>();
3909 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
3910 } else if (NumOps == 3) {
3911 N = NodeAllocator.Allocate<TernarySDNode>();
3912 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
3914 N = NodeAllocator.Allocate<SDNode>();
3915 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
3918 AllNodes.push_back(N);
3922 return SDValue(N, 0);
3925 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) {
3926 return getNode(Opcode, DL, VTList, 0, 0);
3929 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3931 SDValue Ops[] = { N1 };
3932 return getNode(Opcode, DL, VTList, Ops, 1);
3935 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3936 SDValue N1, SDValue N2) {
3937 SDValue Ops[] = { N1, N2 };
3938 return getNode(Opcode, DL, VTList, Ops, 2);
3941 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3942 SDValue N1, SDValue N2, SDValue N3) {
3943 SDValue Ops[] = { N1, N2, N3 };
3944 return getNode(Opcode, DL, VTList, Ops, 3);
3947 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3948 SDValue N1, SDValue N2, SDValue N3,
3950 SDValue Ops[] = { N1, N2, N3, N4 };
3951 return getNode(Opcode, DL, VTList, Ops, 4);
3954 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3955 SDValue N1, SDValue N2, SDValue N3,
3956 SDValue N4, SDValue N5) {
3957 SDValue Ops[] = { N1, N2, N3, N4, N5 };
3958 return getNode(Opcode, DL, VTList, Ops, 5);
3961 SDVTList SelectionDAG::getVTList(MVT VT) {
3962 return makeVTList(SDNode::getValueTypeList(VT), 1);
3965 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) {
3966 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3967 E = VTList.rend(); I != E; ++I)
3968 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
3971 MVT *Array = Allocator.Allocate<MVT>(2);
3974 SDVTList Result = makeVTList(Array, 2);
3975 VTList.push_back(Result);
3979 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) {
3980 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3981 E = VTList.rend(); I != E; ++I)
3982 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
3986 MVT *Array = Allocator.Allocate<MVT>(3);
3990 SDVTList Result = makeVTList(Array, 3);
3991 VTList.push_back(Result);
3995 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
3996 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3997 E = VTList.rend(); I != E; ++I)
3998 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
3999 I->VTs[2] == VT3 && I->VTs[3] == VT4)
4002 MVT *Array = Allocator.Allocate<MVT>(3);
4007 SDVTList Result = makeVTList(Array, 4);
4008 VTList.push_back(Result);
4012 SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
4014 case 0: assert(0 && "Cannot have nodes without results!");
4015 case 1: return getVTList(VTs[0]);
4016 case 2: return getVTList(VTs[0], VTs[1]);
4017 case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
4021 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
4022 E = VTList.rend(); I != E; ++I) {
4023 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1])
4026 bool NoMatch = false;
4027 for (unsigned i = 2; i != NumVTs; ++i)
4028 if (VTs[i] != I->VTs[i]) {
4036 MVT *Array = Allocator.Allocate<MVT>(NumVTs);
4037 std::copy(VTs, VTs+NumVTs, Array);
4038 SDVTList Result = makeVTList(Array, NumVTs);
4039 VTList.push_back(Result);
4044 /// UpdateNodeOperands - *Mutate* the specified node in-place to have the
4045 /// specified operands. If the resultant node already exists in the DAG,
4046 /// this does not modify the specified node, instead it returns the node that
4047 /// already exists. If the resultant node does not exist in the DAG, the
4048 /// input node is returned. As a degenerate case, if you specify the same
4049 /// input operands as the node already has, the input node is returned.
4050 SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
4051 SDNode *N = InN.getNode();
4052 assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
4054 // Check to see if there is no change.
4055 if (Op == N->getOperand(0)) return InN;
4057 // See if the modified node already exists.
4058 void *InsertPos = 0;
4059 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
4060 return SDValue(Existing, InN.getResNo());
4062 // Nope it doesn't. Remove the node from its current place in the maps.
4064 if (!RemoveNodeFromCSEMaps(N))
4067 // Now we update the operands.
4068 N->OperandList[0].set(Op);
4070 // If this gets put into a CSE map, add it.
4071 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4075 SDValue SelectionDAG::
4076 UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
4077 SDNode *N = InN.getNode();
4078 assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
4080 // Check to see if there is no change.
4081 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
4082 return InN; // No operands changed, just return the input node.
4084 // See if the modified node already exists.
4085 void *InsertPos = 0;
4086 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
4087 return SDValue(Existing, InN.getResNo());
4089 // Nope it doesn't. Remove the node from its current place in the maps.
4091 if (!RemoveNodeFromCSEMaps(N))
4094 // Now we update the operands.
4095 if (N->OperandList[0] != Op1)
4096 N->OperandList[0].set(Op1);
4097 if (N->OperandList[1] != Op2)
4098 N->OperandList[1].set(Op2);
4100 // If this gets put into a CSE map, add it.
4101 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4105 SDValue SelectionDAG::
4106 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) {
4107 SDValue Ops[] = { Op1, Op2, Op3 };
4108 return UpdateNodeOperands(N, Ops, 3);
4111 SDValue SelectionDAG::
4112 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
4113 SDValue Op3, SDValue Op4) {
4114 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
4115 return UpdateNodeOperands(N, Ops, 4);
4118 SDValue SelectionDAG::
4119 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
4120 SDValue Op3, SDValue Op4, SDValue Op5) {
4121 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
4122 return UpdateNodeOperands(N, Ops, 5);
4125 SDValue SelectionDAG::
4126 UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
4127 SDNode *N = InN.getNode();
4128 assert(N->getNumOperands() == NumOps &&
4129 "Update with wrong number of operands");
4131 // Check to see if there is no change.
4132 bool AnyChange = false;
4133 for (unsigned i = 0; i != NumOps; ++i) {
4134 if (Ops[i] != N->getOperand(i)) {
4140 // No operands changed, just return the input node.
4141 if (!AnyChange) return InN;
4143 // See if the modified node already exists.
4144 void *InsertPos = 0;
4145 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
4146 return SDValue(Existing, InN.getResNo());
4148 // Nope it doesn't. Remove the node from its current place in the maps.
4150 if (!RemoveNodeFromCSEMaps(N))
4153 // Now we update the operands.
4154 for (unsigned i = 0; i != NumOps; ++i)
4155 if (N->OperandList[i] != Ops[i])
4156 N->OperandList[i].set(Ops[i]);
4158 // If this gets put into a CSE map, add it.
4159 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4163 /// DropOperands - Release the operands and set this node to have
4165 void SDNode::DropOperands() {
4166 // Unlike the code in MorphNodeTo that does this, we don't need to
4167 // watch for dead nodes here.
4168 for (op_iterator I = op_begin(), E = op_end(); I != E; ) {
4174 /// SelectNodeTo - These are wrappers around MorphNodeTo that accept a
4177 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4179 SDVTList VTs = getVTList(VT);
4180 return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
4183 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4184 MVT VT, SDValue Op1) {
4185 SDVTList VTs = getVTList(VT);
4186 SDValue Ops[] = { Op1 };
4187 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4190 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4191 MVT VT, SDValue Op1,
4193 SDVTList VTs = getVTList(VT);
4194 SDValue Ops[] = { Op1, Op2 };
4195 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4198 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4199 MVT VT, SDValue Op1,
4200 SDValue Op2, SDValue Op3) {
4201 SDVTList VTs = getVTList(VT);
4202 SDValue Ops[] = { Op1, Op2, Op3 };
4203 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4206 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4207 MVT VT, const SDValue *Ops,
4209 SDVTList VTs = getVTList(VT);
4210 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4213 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4214 MVT VT1, MVT VT2, const SDValue *Ops,
4216 SDVTList VTs = getVTList(VT1, VT2);
4217 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4220 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4222 SDVTList VTs = getVTList(VT1, VT2);
4223 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
4226 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4227 MVT VT1, MVT VT2, MVT VT3,
4228 const SDValue *Ops, unsigned NumOps) {
4229 SDVTList VTs = getVTList(VT1, VT2, VT3);
4230 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4233 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4234 MVT VT1, MVT VT2, MVT VT3, MVT VT4,
4235 const SDValue *Ops, unsigned NumOps) {
4236 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
4237 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4240 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4243 SDVTList VTs = getVTList(VT1, VT2);
4244 SDValue Ops[] = { Op1 };
4245 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4248 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4250 SDValue Op1, SDValue Op2) {
4251 SDVTList VTs = getVTList(VT1, VT2);
4252 SDValue Ops[] = { Op1, Op2 };
4253 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4256 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4258 SDValue Op1, SDValue Op2,
4260 SDVTList VTs = getVTList(VT1, VT2);
4261 SDValue Ops[] = { Op1, Op2, Op3 };
4262 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4265 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4266 MVT VT1, MVT VT2, MVT VT3,
4267 SDValue Op1, SDValue Op2,
4269 SDVTList VTs = getVTList(VT1, VT2, VT3);
4270 SDValue Ops[] = { Op1, Op2, Op3 };
4271 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4274 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4275 SDVTList VTs, const SDValue *Ops,
4277 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps);
4280 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4282 SDVTList VTs = getVTList(VT);
4283 return MorphNodeTo(N, Opc, VTs, 0, 0);
4286 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4287 MVT VT, SDValue Op1) {
4288 SDVTList VTs = getVTList(VT);
4289 SDValue Ops[] = { Op1 };
4290 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4293 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4294 MVT VT, SDValue Op1,
4296 SDVTList VTs = getVTList(VT);
4297 SDValue Ops[] = { Op1, Op2 };
4298 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4301 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4302 MVT VT, SDValue Op1,
4303 SDValue Op2, SDValue Op3) {
4304 SDVTList VTs = getVTList(VT);
4305 SDValue Ops[] = { Op1, Op2, Op3 };
4306 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4309 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4310 MVT VT, const SDValue *Ops,
4312 SDVTList VTs = getVTList(VT);
4313 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4316 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4317 MVT VT1, MVT VT2, const SDValue *Ops,
4319 SDVTList VTs = getVTList(VT1, VT2);
4320 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4323 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4325 SDVTList VTs = getVTList(VT1, VT2);
4326 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
4329 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4330 MVT VT1, MVT VT2, MVT VT3,
4331 const SDValue *Ops, unsigned NumOps) {
4332 SDVTList VTs = getVTList(VT1, VT2, VT3);
4333 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4336 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4339 SDVTList VTs = getVTList(VT1, VT2);
4340 SDValue Ops[] = { Op1 };
4341 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4344 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4346 SDValue Op1, SDValue Op2) {
4347 SDVTList VTs = getVTList(VT1, VT2);
4348 SDValue Ops[] = { Op1, Op2 };
4349 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4352 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4354 SDValue Op1, SDValue Op2,
4356 SDVTList VTs = getVTList(VT1, VT2);
4357 SDValue Ops[] = { Op1, Op2, Op3 };
4358 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4361 /// MorphNodeTo - These *mutate* the specified node to have the specified
4362 /// return type, opcode, and operands.
4364 /// Note that MorphNodeTo returns the resultant node. If there is already a
4365 /// node of the specified opcode and operands, it returns that node instead of
4366 /// the current one. Note that the DebugLoc need not be the same.
4368 /// Using MorphNodeTo is faster than creating a new node and swapping it in
4369 /// with ReplaceAllUsesWith both because it often avoids allocating a new
4370 /// node, and because it doesn't require CSE recalculation for any of
4371 /// the node's users.
4373 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4374 SDVTList VTs, const SDValue *Ops,
4376 // If an identical node already exists, use it.
4378 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
4379 FoldingSetNodeID ID;
4380 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
4381 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
4385 if (!RemoveNodeFromCSEMaps(N))
4388 // Start the morphing.
4390 N->ValueList = VTs.VTs;
4391 N->NumValues = VTs.NumVTs;
4393 // Clear the operands list, updating used nodes to remove this from their
4394 // use list. Keep track of any operands that become dead as a result.
4395 SmallPtrSet<SDNode*, 16> DeadNodeSet;
4396 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
4398 SDNode *Used = Use.getNode();
4400 if (Used->use_empty())
4401 DeadNodeSet.insert(Used);
4404 // If NumOps is larger than the # of operands we currently have, reallocate
4405 // the operand list.
4406 if (NumOps > N->NumOperands) {
4407 if (N->OperandsNeedDelete)
4408 delete[] N->OperandList;
4410 if (N->isMachineOpcode()) {
4411 // We're creating a final node that will live unmorphed for the
4412 // remainder of the current SelectionDAG iteration, so we can allocate
4413 // the operands directly out of a pool with no recycling metadata.
4414 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps);
4415 N->OperandsNeedDelete = false;
4417 N->OperandList = new SDUse[NumOps];
4418 N->OperandsNeedDelete = true;
4422 // Assign the new operands.
4423 N->NumOperands = NumOps;
4424 for (unsigned i = 0, e = NumOps; i != e; ++i) {
4425 N->OperandList[i].setUser(N);
4426 N->OperandList[i].setInitial(Ops[i]);
4429 // Delete any nodes that are still dead after adding the uses for the
4431 SmallVector<SDNode *, 16> DeadNodes;
4432 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(),
4433 E = DeadNodeSet.end(); I != E; ++I)
4434 if ((*I)->use_empty())
4435 DeadNodes.push_back(*I);
4436 RemoveDeadNodes(DeadNodes);
4439 CSEMap.InsertNode(N, IP); // Memoize the new node.
4444 /// getTargetNode - These are used for target selectors to create a new node
4445 /// with specified return type(s), target opcode, and operands.
4447 /// Note that getTargetNode returns the resultant node. If there is already a
4448 /// node of the specified opcode and operands, it returns that node instead of
4449 /// the current one.
4450 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
4451 return getNode(~Opcode, dl, VT).getNode();
4454 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4456 return getNode(~Opcode, dl, VT, Op1).getNode();
4459 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4460 SDValue Op1, SDValue Op2) {
4461 return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
4464 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4465 SDValue Op1, SDValue Op2,
4467 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
4470 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4471 const SDValue *Ops, unsigned NumOps) {
4472 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
4475 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4477 SDVTList VTs = getVTList(VT1, VT2);
4479 return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
4482 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4483 MVT VT2, SDValue Op1) {
4484 SDVTList VTs = getVTList(VT1, VT2);
4485 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
4488 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4489 MVT VT2, SDValue Op1,
4491 SDVTList VTs = getVTList(VT1, VT2);
4492 SDValue Ops[] = { Op1, Op2 };
4493 return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
4496 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4497 MVT VT2, SDValue Op1,
4498 SDValue Op2, SDValue Op3) {
4499 SDVTList VTs = getVTList(VT1, VT2);
4500 SDValue Ops[] = { Op1, Op2, Op3 };
4501 return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
4504 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4506 const SDValue *Ops, unsigned NumOps) {
4507 SDVTList VTs = getVTList(VT1, VT2);
4508 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4511 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4512 MVT VT1, MVT VT2, MVT VT3,
4513 SDValue Op1, SDValue Op2) {
4514 SDVTList VTs = getVTList(VT1, VT2, VT3);
4515 SDValue Ops[] = { Op1, Op2 };
4516 return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
4519 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4520 MVT VT1, MVT VT2, MVT VT3,
4521 SDValue Op1, SDValue Op2,
4523 SDVTList VTs = getVTList(VT1, VT2, VT3);
4524 SDValue Ops[] = { Op1, Op2, Op3 };
4525 return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
4528 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4529 MVT VT1, MVT VT2, MVT VT3,
4530 const SDValue *Ops, unsigned NumOps) {
4531 SDVTList VTs = getVTList(VT1, VT2, VT3);
4532 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4535 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4536 MVT VT2, MVT VT3, MVT VT4,
4537 const SDValue *Ops, unsigned NumOps) {
4538 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
4539 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4542 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4543 const std::vector<MVT> &ResultTys,
4544 const SDValue *Ops, unsigned NumOps) {
4545 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
4548 /// getNodeIfExists - Get the specified node if it's already available, or
4549 /// else return NULL.
4550 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
4551 const SDValue *Ops, unsigned NumOps) {
4552 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
4553 FoldingSetNodeID ID;
4554 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
4556 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
4562 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4563 /// This can cause recursive merging of nodes in the DAG.
4565 /// This version assumes From has a single result value.
4567 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
4568 DAGUpdateListener *UpdateListener) {
4569 SDNode *From = FromN.getNode();
4570 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
4571 "Cannot replace with this method!");
4572 assert(From != To.getNode() && "Cannot replace uses of with self");
4574 // Iterate over all the existing uses of From. New uses will be added
4575 // to the beginning of the use list, which we avoid visiting.
4576 // This specifically avoids visiting uses of From that arise while the
4577 // replacement is happening, because any such uses would be the result
4578 // of CSE: If an existing node looks like From after one of its operands
4579 // is replaced by To, we don't want to replace of all its users with To
4580 // too. See PR3018 for more info.
4581 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4585 // This node is about to morph, remove its old self from the CSE maps.
4586 RemoveNodeFromCSEMaps(User);
4588 // A user can appear in a use list multiple times, and when this
4589 // happens the uses are usually next to each other in the list.
4590 // To help reduce the number of CSE recomputations, process all
4591 // the uses of this user that we can find this way.
4593 SDUse &Use = UI.getUse();
4596 } while (UI != UE && *UI == User);
4598 // Now that we have modified User, add it back to the CSE maps. If it
4599 // already exists there, recursively merge the results together.
4600 AddModifiedNodeToCSEMaps(User, UpdateListener);
4604 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4605 /// This can cause recursive merging of nodes in the DAG.
4607 /// This version assumes that for each value of From, there is a
4608 /// corresponding value in To in the same position with the same type.
4610 void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To,
4611 DAGUpdateListener *UpdateListener) {
4613 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
4614 assert((!From->hasAnyUseOfValue(i) ||
4615 From->getValueType(i) == To->getValueType(i)) &&
4616 "Cannot use this version of ReplaceAllUsesWith!");
4619 // Handle the trivial case.
4623 // Iterate over just the existing users of From. See the comments in
4624 // the ReplaceAllUsesWith above.
4625 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4629 // This node is about to morph, remove its old self from the CSE maps.
4630 RemoveNodeFromCSEMaps(User);
4632 // A user can appear in a use list multiple times, and when this
4633 // happens the uses are usually next to each other in the list.
4634 // To help reduce the number of CSE recomputations, process all
4635 // the uses of this user that we can find this way.
4637 SDUse &Use = UI.getUse();
4640 } while (UI != UE && *UI == User);
4642 // Now that we have modified User, add it back to the CSE maps. If it
4643 // already exists there, recursively merge the results together.
4644 AddModifiedNodeToCSEMaps(User, UpdateListener);
4648 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4649 /// This can cause recursive merging of nodes in the DAG.
4651 /// This version can replace From with any result values. To must match the
4652 /// number and types of values returned by From.
4653 void SelectionDAG::ReplaceAllUsesWith(SDNode *From,
4655 DAGUpdateListener *UpdateListener) {
4656 if (From->getNumValues() == 1) // Handle the simple case efficiently.
4657 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener);
4659 // Iterate over just the existing users of From. See the comments in
4660 // the ReplaceAllUsesWith above.
4661 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4665 // This node is about to morph, remove its old self from the CSE maps.
4666 RemoveNodeFromCSEMaps(User);
4668 // A user can appear in a use list multiple times, and when this
4669 // happens the uses are usually next to each other in the list.
4670 // To help reduce the number of CSE recomputations, process all
4671 // the uses of this user that we can find this way.
4673 SDUse &Use = UI.getUse();
4674 const SDValue &ToOp = To[Use.getResNo()];
4677 } while (UI != UE && *UI == User);
4679 // Now that we have modified User, add it back to the CSE maps. If it
4680 // already exists there, recursively merge the results together.
4681 AddModifiedNodeToCSEMaps(User, UpdateListener);
4685 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
4686 /// uses of other values produced by From.getNode() alone. The Deleted
4687 /// vector is handled the same way as for ReplaceAllUsesWith.
4688 void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
4689 DAGUpdateListener *UpdateListener){
4690 // Handle the really simple, really trivial case efficiently.
4691 if (From == To) return;
4693 // Handle the simple, trivial, case efficiently.
4694 if (From.getNode()->getNumValues() == 1) {
4695 ReplaceAllUsesWith(From, To, UpdateListener);
4699 // Iterate over just the existing users of From. See the comments in
4700 // the ReplaceAllUsesWith above.
4701 SDNode::use_iterator UI = From.getNode()->use_begin(),
4702 UE = From.getNode()->use_end();
4705 bool UserRemovedFromCSEMaps = false;
4707 // A user can appear in a use list multiple times, and when this
4708 // happens the uses are usually next to each other in the list.
4709 // To help reduce the number of CSE recomputations, process all
4710 // the uses of this user that we can find this way.
4712 SDUse &Use = UI.getUse();
4714 // Skip uses of different values from the same node.
4715 if (Use.getResNo() != From.getResNo()) {
4720 // If this node hasn't been modified yet, it's still in the CSE maps,
4721 // so remove its old self from the CSE maps.
4722 if (!UserRemovedFromCSEMaps) {
4723 RemoveNodeFromCSEMaps(User);
4724 UserRemovedFromCSEMaps = true;
4729 } while (UI != UE && *UI == User);
4731 // We are iterating over all uses of the From node, so if a use
4732 // doesn't use the specific value, no changes are made.
4733 if (!UserRemovedFromCSEMaps)
4736 // Now that we have modified User, add it back to the CSE maps. If it
4737 // already exists there, recursively merge the results together.
4738 AddModifiedNodeToCSEMaps(User, UpdateListener);
4743 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith
4744 /// to record information about a use.
4751 /// operator< - Sort Memos by User.
4752 bool operator<(const UseMemo &L, const UseMemo &R) {
4753 return (intptr_t)L.User < (intptr_t)R.User;
4757 /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
4758 /// uses of other values produced by From.getNode() alone. The same value
4759 /// may appear in both the From and To list. The Deleted vector is
4760 /// handled the same way as for ReplaceAllUsesWith.
4761 void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
4764 DAGUpdateListener *UpdateListener){
4765 // Handle the simple, trivial case efficiently.
4767 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener);
4769 // Read up all the uses and make records of them. This helps
4770 // processing new uses that are introduced during the
4771 // replacement process.
4772 SmallVector<UseMemo, 4> Uses;
4773 for (unsigned i = 0; i != Num; ++i) {
4774 unsigned FromResNo = From[i].getResNo();
4775 SDNode *FromNode = From[i].getNode();
4776 for (SDNode::use_iterator UI = FromNode->use_begin(),
4777 E = FromNode->use_end(); UI != E; ++UI) {
4778 SDUse &Use = UI.getUse();
4779 if (Use.getResNo() == FromResNo) {
4780 UseMemo Memo = { *UI, i, &Use };
4781 Uses.push_back(Memo);
4786 // Sort the uses, so that all the uses from a given User are together.
4787 std::sort(Uses.begin(), Uses.end());
4789 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size();
4790 UseIndex != UseIndexEnd; ) {
4791 // We know that this user uses some value of From. If it is the right
4792 // value, update it.
4793 SDNode *User = Uses[UseIndex].User;
4795 // This node is about to morph, remove its old self from the CSE maps.
4796 RemoveNodeFromCSEMaps(User);
4798 // The Uses array is sorted, so all the uses for a given User
4799 // are next to each other in the list.
4800 // To help reduce the number of CSE recomputations, process all
4801 // the uses of this user that we can find this way.
4803 unsigned i = Uses[UseIndex].Index;
4804 SDUse &Use = *Uses[UseIndex].Use;
4808 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User);
4810 // Now that we have modified User, add it back to the CSE maps. If it
4811 // already exists there, recursively merge the results together.
4812 AddModifiedNodeToCSEMaps(User, UpdateListener);
4816 /// AssignTopologicalOrder - Assign a unique node id for each node in the DAG
4817 /// based on their topological order. It returns the maximum id and a vector
4818 /// of the SDNodes* in assigned order by reference.
4819 unsigned SelectionDAG::AssignTopologicalOrder() {
4821 unsigned DAGSize = 0;
4823 // SortedPos tracks the progress of the algorithm. Nodes before it are
4824 // sorted, nodes after it are unsorted. When the algorithm completes
4825 // it is at the end of the list.
4826 allnodes_iterator SortedPos = allnodes_begin();
4828 // Visit all the nodes. Move nodes with no operands to the front of
4829 // the list immediately. Annotate nodes that do have operands with their
4830 // operand count. Before we do this, the Node Id fields of the nodes
4831 // may contain arbitrary values. After, the Node Id fields for nodes
4832 // before SortedPos will contain the topological sort index, and the
4833 // Node Id fields for nodes At SortedPos and after will contain the
4834 // count of outstanding operands.
4835 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) {
4837 unsigned Degree = N->getNumOperands();
4839 // A node with no uses, add it to the result array immediately.
4840 N->setNodeId(DAGSize++);
4841 allnodes_iterator Q = N;
4843 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
4846 // Temporarily use the Node Id as scratch space for the degree count.
4847 N->setNodeId(Degree);
4851 // Visit all the nodes. As we iterate, moves nodes into sorted order,
4852 // such that by the time the end is reached all nodes will be sorted.
4853 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) {
4855 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4858 unsigned Degree = P->getNodeId();
4861 // All of P's operands are sorted, so P may sorted now.
4862 P->setNodeId(DAGSize++);
4864 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P));
4867 // Update P's outstanding operand count.
4868 P->setNodeId(Degree);
4873 assert(SortedPos == AllNodes.end() &&
4874 "Topological sort incomplete!");
4875 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
4876 "First node in topological sort is not the entry token!");
4877 assert(AllNodes.front().getNodeId() == 0 &&
4878 "First node in topological sort has non-zero id!");
4879 assert(AllNodes.front().getNumOperands() == 0 &&
4880 "First node in topological sort has operands!");
4881 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 &&
4882 "Last node in topologic sort has unexpected id!");
4883 assert(AllNodes.back().use_empty() &&
4884 "Last node in topologic sort has users!");
4885 assert(DAGSize == allnodes_size() && "Node count mismatch!");
4891 //===----------------------------------------------------------------------===//
4893 //===----------------------------------------------------------------------===//
4895 HandleSDNode::~HandleSDNode() {
4899 GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA,
4901 : SDNode(isa<GlobalVariable>(GA) &&
4902 cast<GlobalVariable>(GA)->isThreadLocal() ?
4904 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) :
4906 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress),
4907 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) {
4908 TheGlobal = const_cast<GlobalValue*>(GA);
4911 MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
4912 const Value *srcValue, int SVO,
4913 unsigned alignment, bool vol)
4914 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
4915 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
4916 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4917 assert(getAlignment() == alignment && "Alignment representation error!");
4918 assert(isVolatile() == vol && "Volatile representation error!");
4921 MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
4923 unsigned NumOps, MVT memvt, const Value *srcValue,
4924 int SVO, unsigned alignment, bool vol)
4925 : SDNode(Opc, dl, VTs, Ops, NumOps),
4926 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
4927 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
4928 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4929 assert(getAlignment() == alignment && "Alignment representation error!");
4930 assert(isVolatile() == vol && "Volatile representation error!");
4933 /// getMemOperand - Return a MachineMemOperand object describing the memory
4934 /// reference performed by this memory reference.
4935 MachineMemOperand MemSDNode::getMemOperand() const {
4937 if (isa<LoadSDNode>(this))
4938 Flags = MachineMemOperand::MOLoad;
4939 else if (isa<StoreSDNode>(this))
4940 Flags = MachineMemOperand::MOStore;
4941 else if (isa<AtomicSDNode>(this)) {
4942 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
4945 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this);
4946 assert(MemIntrinNode && "Unknown MemSDNode opcode!");
4947 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad;
4948 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore;
4951 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3;
4952 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile;
4954 // Check if the memory reference references a frame index
4955 const FrameIndexSDNode *FI =
4956 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
4957 if (!getSrcValue() && FI)
4958 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
4959 Flags, 0, Size, getAlignment());
4961 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(),
4962 Size, getAlignment());
4965 /// Profile - Gather unique data for the node.
4967 void SDNode::Profile(FoldingSetNodeID &ID) const {
4968 AddNodeIDNode(ID, this);
4971 /// getValueTypeList - Return a pointer to the specified value type.
4973 const MVT *SDNode::getValueTypeList(MVT VT) {
4974 if (VT.isExtended()) {
4975 static std::set<MVT, MVT::compareRawBits> EVTs;
4976 return &(*EVTs.insert(VT).first);
4978 static MVT VTs[MVT::LAST_VALUETYPE];
4979 VTs[VT.getSimpleVT()] = VT;
4980 return &VTs[VT.getSimpleVT()];
4984 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
4985 /// indicated value. This method ignores uses of other values defined by this
4987 bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const {
4988 assert(Value < getNumValues() && "Bad value!");
4990 // TODO: Only iterate over uses of a given value of the node
4991 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
4992 if (UI.getUse().getResNo() == Value) {
4999 // Found exactly the right number of uses?
5004 /// hasAnyUseOfValue - Return true if there are any use of the indicated
5005 /// value. This method ignores uses of other values defined by this operation.
5006 bool SDNode::hasAnyUseOfValue(unsigned Value) const {
5007 assert(Value < getNumValues() && "Bad value!");
5009 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
5010 if (UI.getUse().getResNo() == Value)
5017 /// isOnlyUserOf - Return true if this node is the only use of N.
5019 bool SDNode::isOnlyUserOf(SDNode *N) const {
5021 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
5032 /// isOperand - Return true if this node is an operand of N.
5034 bool SDValue::isOperandOf(SDNode *N) const {
5035 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5036 if (*this == N->getOperand(i))
5041 bool SDNode::isOperandOf(SDNode *N) const {
5042 for (unsigned i = 0, e = N->NumOperands; i != e; ++i)
5043 if (this == N->OperandList[i].getNode())
5048 /// reachesChainWithoutSideEffects - Return true if this operand (which must
5049 /// be a chain) reaches the specified operand without crossing any
5050 /// side-effecting instructions. In practice, this looks through token
5051 /// factors and non-volatile loads. In order to remain efficient, this only
5052 /// looks a couple of nodes in, it does not do an exhaustive search.
5053 bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
5054 unsigned Depth) const {
5055 if (*this == Dest) return true;
5057 // Don't search too deeply, we just want to be able to see through
5058 // TokenFactor's etc.
5059 if (Depth == 0) return false;
5061 // If this is a token factor, all inputs to the TF happen in parallel. If any
5062 // of the operands of the TF reach dest, then we can do the xform.
5063 if (getOpcode() == ISD::TokenFactor) {
5064 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
5065 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1))
5070 // Loads don't have side effects, look through them.
5071 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
5072 if (!Ld->isVolatile())
5073 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
5079 static void findPredecessor(SDNode *N, const SDNode *P, bool &found,
5080 SmallPtrSet<SDNode *, 32> &Visited) {
5081 if (found || !Visited.insert(N))
5084 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) {
5085 SDNode *Op = N->getOperand(i).getNode();
5090 findPredecessor(Op, P, found, Visited);
5094 /// isPredecessorOf - Return true if this node is a predecessor of N. This node
5095 /// is either an operand of N or it can be reached by recursively traversing
5096 /// up the operands.
5097 /// NOTE: this is an expensive method. Use it carefully.
5098 bool SDNode::isPredecessorOf(SDNode *N) const {
5099 SmallPtrSet<SDNode *, 32> Visited;
5101 findPredecessor(N, this, found, Visited);
5105 uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
5106 assert(Num < NumOperands && "Invalid child # of SDNode!");
5107 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue();
5110 std::string SDNode::getOperationName(const SelectionDAG *G) const {
5111 switch (getOpcode()) {
5113 if (getOpcode() < ISD::BUILTIN_OP_END)
5114 return "<<Unknown DAG Node>>";
5115 if (isMachineOpcode()) {
5117 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
5118 if (getMachineOpcode() < TII->getNumOpcodes())
5119 return TII->get(getMachineOpcode()).getName();
5120 return "<<Unknown Machine Node>>";
5123 const TargetLowering &TLI = G->getTargetLoweringInfo();
5124 const char *Name = TLI.getTargetNodeName(getOpcode());
5125 if (Name) return Name;
5126 return "<<Unknown Target Node>>";
5128 return "<<Unknown Node>>";
5131 case ISD::DELETED_NODE:
5132 return "<<Deleted Node!>>";
5134 case ISD::PREFETCH: return "Prefetch";
5135 case ISD::MEMBARRIER: return "MemBarrier";
5136 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
5137 case ISD::ATOMIC_SWAP: return "AtomicSwap";
5138 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
5139 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
5140 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
5141 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
5142 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
5143 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
5144 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
5145 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
5146 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
5147 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
5148 case ISD::PCMARKER: return "PCMarker";
5149 case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
5150 case ISD::SRCVALUE: return "SrcValue";
5151 case ISD::MEMOPERAND: return "MemOperand";
5152 case ISD::EntryToken: return "EntryToken";
5153 case ISD::TokenFactor: return "TokenFactor";
5154 case ISD::AssertSext: return "AssertSext";
5155 case ISD::AssertZext: return "AssertZext";
5157 case ISD::BasicBlock: return "BasicBlock";
5158 case ISD::ARG_FLAGS: return "ArgFlags";
5159 case ISD::VALUETYPE: return "ValueType";
5160 case ISD::Register: return "Register";
5162 case ISD::Constant: return "Constant";
5163 case ISD::ConstantFP: return "ConstantFP";
5164 case ISD::GlobalAddress: return "GlobalAddress";
5165 case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
5166 case ISD::FrameIndex: return "FrameIndex";
5167 case ISD::JumpTable: return "JumpTable";
5168 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
5169 case ISD::RETURNADDR: return "RETURNADDR";
5170 case ISD::FRAMEADDR: return "FRAMEADDR";
5171 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
5172 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
5173 case ISD::EHSELECTION: return "EHSELECTION";
5174 case ISD::EH_RETURN: return "EH_RETURN";
5175 case ISD::ConstantPool: return "ConstantPool";
5176 case ISD::ExternalSymbol: return "ExternalSymbol";
5177 case ISD::INTRINSIC_WO_CHAIN: {
5178 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue();
5179 return Intrinsic::getName((Intrinsic::ID)IID);
5181 case ISD::INTRINSIC_VOID:
5182 case ISD::INTRINSIC_W_CHAIN: {
5183 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue();
5184 return Intrinsic::getName((Intrinsic::ID)IID);
5187 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
5188 case ISD::TargetConstant: return "TargetConstant";
5189 case ISD::TargetConstantFP:return "TargetConstantFP";
5190 case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
5191 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
5192 case ISD::TargetFrameIndex: return "TargetFrameIndex";
5193 case ISD::TargetJumpTable: return "TargetJumpTable";
5194 case ISD::TargetConstantPool: return "TargetConstantPool";
5195 case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
5197 case ISD::CopyToReg: return "CopyToReg";
5198 case ISD::CopyFromReg: return "CopyFromReg";
5199 case ISD::UNDEF: return "undef";
5200 case ISD::MERGE_VALUES: return "merge_values";
5201 case ISD::INLINEASM: return "inlineasm";
5202 case ISD::DBG_LABEL: return "dbg_label";
5203 case ISD::EH_LABEL: return "eh_label";
5204 case ISD::DECLARE: return "declare";
5205 case ISD::HANDLENODE: return "handlenode";
5206 case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
5207 case ISD::CALL: return "call";
5210 case ISD::FABS: return "fabs";
5211 case ISD::FNEG: return "fneg";
5212 case ISD::FSQRT: return "fsqrt";
5213 case ISD::FSIN: return "fsin";
5214 case ISD::FCOS: return "fcos";
5215 case ISD::FPOWI: return "fpowi";
5216 case ISD::FPOW: return "fpow";
5217 case ISD::FTRUNC: return "ftrunc";
5218 case ISD::FFLOOR: return "ffloor";
5219 case ISD::FCEIL: return "fceil";
5220 case ISD::FRINT: return "frint";
5221 case ISD::FNEARBYINT: return "fnearbyint";
5224 case ISD::ADD: return "add";
5225 case ISD::SUB: return "sub";
5226 case ISD::MUL: return "mul";
5227 case ISD::MULHU: return "mulhu";
5228 case ISD::MULHS: return "mulhs";
5229 case ISD::SDIV: return "sdiv";
5230 case ISD::UDIV: return "udiv";
5231 case ISD::SREM: return "srem";
5232 case ISD::UREM: return "urem";
5233 case ISD::SMUL_LOHI: return "smul_lohi";
5234 case ISD::UMUL_LOHI: return "umul_lohi";
5235 case ISD::SDIVREM: return "sdivrem";
5236 case ISD::UDIVREM: return "udivrem";
5237 case ISD::AND: return "and";
5238 case ISD::OR: return "or";
5239 case ISD::XOR: return "xor";
5240 case ISD::SHL: return "shl";
5241 case ISD::SRA: return "sra";
5242 case ISD::SRL: return "srl";
5243 case ISD::ROTL: return "rotl";
5244 case ISD::ROTR: return "rotr";
5245 case ISD::FADD: return "fadd";
5246 case ISD::FSUB: return "fsub";
5247 case ISD::FMUL: return "fmul";
5248 case ISD::FDIV: return "fdiv";
5249 case ISD::FREM: return "frem";
5250 case ISD::FCOPYSIGN: return "fcopysign";
5251 case ISD::FGETSIGN: return "fgetsign";
5253 case ISD::SETCC: return "setcc";
5254 case ISD::VSETCC: return "vsetcc";
5255 case ISD::SELECT: return "select";
5256 case ISD::SELECT_CC: return "select_cc";
5257 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
5258 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
5259 case ISD::CONCAT_VECTORS: return "concat_vectors";
5260 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
5261 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
5262 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
5263 case ISD::CARRY_FALSE: return "carry_false";
5264 case ISD::ADDC: return "addc";
5265 case ISD::ADDE: return "adde";
5266 case ISD::SADDO: return "saddo";
5267 case ISD::UADDO: return "uaddo";
5268 case ISD::SSUBO: return "ssubo";
5269 case ISD::USUBO: return "usubo";
5270 case ISD::SMULO: return "smulo";
5271 case ISD::UMULO: return "umulo";
5272 case ISD::SUBC: return "subc";
5273 case ISD::SUBE: return "sube";
5274 case ISD::SHL_PARTS: return "shl_parts";
5275 case ISD::SRA_PARTS: return "sra_parts";
5276 case ISD::SRL_PARTS: return "srl_parts";
5278 // Conversion operators.
5279 case ISD::SIGN_EXTEND: return "sign_extend";
5280 case ISD::ZERO_EXTEND: return "zero_extend";
5281 case ISD::ANY_EXTEND: return "any_extend";
5282 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
5283 case ISD::TRUNCATE: return "truncate";
5284 case ISD::FP_ROUND: return "fp_round";
5285 case ISD::FLT_ROUNDS_: return "flt_rounds";
5286 case ISD::FP_ROUND_INREG: return "fp_round_inreg";
5287 case ISD::FP_EXTEND: return "fp_extend";
5289 case ISD::SINT_TO_FP: return "sint_to_fp";
5290 case ISD::UINT_TO_FP: return "uint_to_fp";
5291 case ISD::FP_TO_SINT: return "fp_to_sint";
5292 case ISD::FP_TO_UINT: return "fp_to_uint";
5293 case ISD::BIT_CONVERT: return "bit_convert";
5295 case ISD::CONVERT_RNDSAT: {
5296 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) {
5297 default: assert(0 && "Unknown cvt code!");
5298 case ISD::CVT_FF: return "cvt_ff";
5299 case ISD::CVT_FS: return "cvt_fs";
5300 case ISD::CVT_FU: return "cvt_fu";
5301 case ISD::CVT_SF: return "cvt_sf";
5302 case ISD::CVT_UF: return "cvt_uf";
5303 case ISD::CVT_SS: return "cvt_ss";
5304 case ISD::CVT_SU: return "cvt_su";
5305 case ISD::CVT_US: return "cvt_us";
5306 case ISD::CVT_UU: return "cvt_uu";
5310 // Control flow instructions
5311 case ISD::BR: return "br";
5312 case ISD::BRIND: return "brind";
5313 case ISD::BR_JT: return "br_jt";
5314 case ISD::BRCOND: return "brcond";
5315 case ISD::BR_CC: return "br_cc";
5316 case ISD::RET: return "ret";
5317 case ISD::CALLSEQ_START: return "callseq_start";
5318 case ISD::CALLSEQ_END: return "callseq_end";
5321 case ISD::LOAD: return "load";
5322 case ISD::STORE: return "store";
5323 case ISD::VAARG: return "vaarg";
5324 case ISD::VACOPY: return "vacopy";
5325 case ISD::VAEND: return "vaend";
5326 case ISD::VASTART: return "vastart";
5327 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
5328 case ISD::EXTRACT_ELEMENT: return "extract_element";
5329 case ISD::BUILD_PAIR: return "build_pair";
5330 case ISD::STACKSAVE: return "stacksave";
5331 case ISD::STACKRESTORE: return "stackrestore";
5332 case ISD::TRAP: return "trap";
5335 case ISD::BSWAP: return "bswap";
5336 case ISD::CTPOP: return "ctpop";
5337 case ISD::CTTZ: return "cttz";
5338 case ISD::CTLZ: return "ctlz";
5341 case ISD::DBG_STOPPOINT: return "dbg_stoppoint";
5342 case ISD::DEBUG_LOC: return "debug_loc";
5345 case ISD::TRAMPOLINE: return "trampoline";
5348 switch (cast<CondCodeSDNode>(this)->get()) {
5349 default: assert(0 && "Unknown setcc condition!");
5350 case ISD::SETOEQ: return "setoeq";
5351 case ISD::SETOGT: return "setogt";
5352 case ISD::SETOGE: return "setoge";
5353 case ISD::SETOLT: return "setolt";
5354 case ISD::SETOLE: return "setole";
5355 case ISD::SETONE: return "setone";
5357 case ISD::SETO: return "seto";
5358 case ISD::SETUO: return "setuo";
5359 case ISD::SETUEQ: return "setue";
5360 case ISD::SETUGT: return "setugt";
5361 case ISD::SETUGE: return "setuge";
5362 case ISD::SETULT: return "setult";
5363 case ISD::SETULE: return "setule";
5364 case ISD::SETUNE: return "setune";
5366 case ISD::SETEQ: return "seteq";
5367 case ISD::SETGT: return "setgt";
5368 case ISD::SETGE: return "setge";
5369 case ISD::SETLT: return "setlt";
5370 case ISD::SETLE: return "setle";
5371 case ISD::SETNE: return "setne";
5376 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
5385 return "<post-inc>";
5387 return "<post-dec>";
5391 std::string ISD::ArgFlagsTy::getArgFlagsString() {
5392 std::string S = "< ";
5406 if (getByValAlign())
5407 S += "byval-align:" + utostr(getByValAlign()) + " ";
5409 S += "orig-align:" + utostr(getOrigAlign()) + " ";
5411 S += "byval-size:" + utostr(getByValSize()) + " ";
5415 void SDNode::dump() const { dump(0); }
5416 void SDNode::dump(const SelectionDAG *G) const {
5420 void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
5421 OS << (void*)this << ": ";
5423 for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
5425 if (getValueType(i) == MVT::Other)
5428 OS << getValueType(i).getMVTString();
5430 OS << " = " << getOperationName(G);
5433 void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
5434 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
5435 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this);
5437 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
5438 int Idx = SVN->getMaskElt(i);
5448 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
5449 OS << '<' << CSDN->getAPIntValue() << '>';
5450 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
5451 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle)
5452 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
5453 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble)
5454 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
5457 CSDN->getValueAPF().bitcastToAPInt().dump();
5460 } else if (const GlobalAddressSDNode *GADN =
5461 dyn_cast<GlobalAddressSDNode>(this)) {
5462 int64_t offset = GADN->getOffset();
5464 WriteAsOperand(OS, GADN->getGlobal());
5467 OS << " + " << offset;
5469 OS << " " << offset;
5470 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
5471 OS << "<" << FIDN->getIndex() << ">";
5472 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
5473 OS << "<" << JTDN->getIndex() << ">";
5474 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
5475 int offset = CP->getOffset();
5476 if (CP->isMachineConstantPoolEntry())
5477 OS << "<" << *CP->getMachineCPVal() << ">";
5479 OS << "<" << *CP->getConstVal() << ">";
5481 OS << " + " << offset;
5483 OS << " " << offset;
5484 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
5486 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
5488 OS << LBB->getName() << " ";
5489 OS << (const void*)BBDN->getBasicBlock() << ">";
5490 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
5491 if (G && R->getReg() &&
5492 TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
5493 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg());
5495 OS << " #" << R->getReg();
5497 } else if (const ExternalSymbolSDNode *ES =
5498 dyn_cast<ExternalSymbolSDNode>(this)) {
5499 OS << "'" << ES->getSymbol() << "'";
5500 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
5502 OS << "<" << M->getValue() << ">";
5505 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) {
5506 if (M->MO.getValue())
5507 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
5509 OS << "<null:" << M->MO.getOffset() << ">";
5510 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) {
5511 OS << N->getArgFlags().getArgFlagsString();
5512 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
5513 OS << ":" << N->getVT().getMVTString();
5515 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
5516 const Value *SrcValue = LD->getSrcValue();
5517 int SrcOffset = LD->getSrcValueOffset();
5523 OS << ":" << SrcOffset << ">";
5526 switch (LD->getExtensionType()) {
5527 default: doExt = false; break;
5528 case ISD::EXTLOAD: OS << " <anyext "; break;
5529 case ISD::SEXTLOAD: OS << " <sext "; break;
5530 case ISD::ZEXTLOAD: OS << " <zext "; break;
5533 OS << LD->getMemoryVT().getMVTString() << ">";
5535 const char *AM = getIndexedModeName(LD->getAddressingMode());
5538 if (LD->isVolatile())
5539 OS << " <volatile>";
5540 OS << " alignment=" << LD->getAlignment();
5541 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
5542 const Value *SrcValue = ST->getSrcValue();
5543 int SrcOffset = ST->getSrcValueOffset();
5549 OS << ":" << SrcOffset << ">";
5551 if (ST->isTruncatingStore())
5552 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">";
5554 const char *AM = getIndexedModeName(ST->getAddressingMode());
5557 if (ST->isVolatile())
5558 OS << " <volatile>";
5559 OS << " alignment=" << ST->getAlignment();
5560 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) {
5561 const Value *SrcValue = AT->getSrcValue();
5562 int SrcOffset = AT->getSrcValueOffset();
5568 OS << ":" << SrcOffset << ">";
5569 if (AT->isVolatile())
5570 OS << " <volatile>";
5571 OS << " alignment=" << AT->getAlignment();
5575 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
5578 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
5580 OS << (void*)getOperand(i).getNode();
5581 if (unsigned RN = getOperand(i).getResNo())
5584 print_details(OS, G);
5587 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
5588 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5589 if (N->getOperand(i).getNode()->hasOneUse())
5590 DumpNodes(N->getOperand(i).getNode(), indent+2, G);
5592 cerr << "\n" << std::string(indent+2, ' ')
5593 << (void*)N->getOperand(i).getNode() << ": <multiple use>";
5596 cerr << "\n" << std::string(indent, ' ');
5600 void SelectionDAG::dump() const {
5601 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:";
5603 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
5605 const SDNode *N = I;
5606 if (!N->hasOneUse() && N != getRoot().getNode())
5607 DumpNodes(N, 2, this);
5610 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
5615 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
5617 print_details(OS, G);
5620 typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet;
5621 static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
5622 const SelectionDAG *G, VisitedSDNodeSet &once) {
5623 if (!once.insert(N)) // If we've been here before, return now.
5625 // Dump the current SDNode, but don't end the line yet.
5626 OS << std::string(indent, ' ');
5628 // Having printed this SDNode, walk the children:
5629 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5630 const SDNode *child = N->getOperand(i).getNode();
5633 if (child->getNumOperands() == 0) {
5634 // This child has no grandchildren; print it inline right here.
5635 child->printr(OS, G);
5637 } else { // Just the address. FIXME: also print the child's opcode
5639 if (unsigned RN = N->getOperand(i).getResNo())
5644 // Dump children that have grandchildren on their own line(s).
5645 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5646 const SDNode *child = N->getOperand(i).getNode();
5647 DumpNodesr(OS, child, indent+2, G, once);
5651 void SDNode::dumpr() const {
5652 VisitedSDNodeSet once;
5653 DumpNodesr(errs(), this, 0, 0, once);
5657 // getAddressSpace - Return the address space this GlobalAddress belongs to.
5658 unsigned GlobalAddressSDNode::getAddressSpace() const {
5659 return getGlobal()->getType()->getAddressSpace();
5663 const Type *ConstantPoolSDNode::getType() const {
5664 if (isMachineConstantPoolEntry())
5665 return Val.MachineCPVal->getType();
5666 return Val.ConstVal->getType();
5669 bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue,
5671 unsigned &SplatBitSize,
5673 unsigned MinSplatBits) {
5674 MVT VT = getValueType(0);
5675 assert(VT.isVector() && "Expected a vector type");
5676 unsigned sz = VT.getSizeInBits();
5677 if (MinSplatBits > sz)
5680 SplatValue = APInt(sz, 0);
5681 SplatUndef = APInt(sz, 0);
5683 // Get the bits. Bits with undefined values (when the corresponding element
5684 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
5685 // in SplatValue. If any of the values are not constant, give up and return
5687 unsigned int nOps = getNumOperands();
5688 assert(nOps > 0 && "isConstantSplat has 0-size build vector");
5689 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits();
5690 for (unsigned i = 0; i < nOps; ++i) {
5691 SDValue OpVal = getOperand(i);
5692 unsigned BitPos = i * EltBitSize;
5694 if (OpVal.getOpcode() == ISD::UNDEF)
5695 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize);
5696 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal))
5697 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize).
5698 zextOrTrunc(sz) << BitPos);
5699 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal))
5700 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos;
5705 // The build_vector is all constants or undefs. Find the smallest element
5706 // size that splats the vector.
5708 HasAnyUndefs = (SplatUndef != 0);
5711 unsigned HalfSize = sz / 2;
5712 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize);
5713 APInt LowValue = APInt(SplatValue).trunc(HalfSize);
5714 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize);
5715 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize);
5717 // If the two halves do not match (ignoring undef bits), stop here.
5718 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
5719 MinSplatBits > HalfSize)
5722 SplatValue = HighValue | LowValue;
5723 SplatUndef = HighUndef & LowUndef;
5732 bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
5733 // Find the first non-undef value in the shuffle mask.
5735 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
5738 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!");
5740 // Make sure all remaining elements are either undef or the same as the first
5742 for (int Idx = Mask[i]; i != e; ++i)
5743 if (Mask[i] >= 0 && Mask[i] != Idx)