1 //===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAG class.
12 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/SelectionDAG.h"
14 #include "llvm/Constants.h"
15 #include "llvm/Analysis/ValueTracking.h"
16 #include "llvm/GlobalAlias.h"
17 #include "llvm/GlobalVariable.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/ADT/SetVector.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/SmallSet.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/ADT/StringExtras.h"
44 /// makeVTList - Return an instance of the SDVTList struct initialized with the
45 /// specified members.
46 static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
47 SDVTList Res = {VTs, NumVTs};
51 static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
52 switch (VT.getSimpleVT()) {
53 default: assert(0 && "Unknown FP format");
54 case MVT::f32: return &APFloat::IEEEsingle;
55 case MVT::f64: return &APFloat::IEEEdouble;
56 case MVT::f80: return &APFloat::x87DoubleExtended;
57 case MVT::f128: return &APFloat::IEEEquad;
58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
62 SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {}
64 //===----------------------------------------------------------------------===//
65 // ConstantFPSDNode Class
66 //===----------------------------------------------------------------------===//
68 /// isExactlyValue - We don't rely on operator== working on double values, as
69 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
70 /// As such, this method can be used to do an exact bit-for-bit comparison of
71 /// two floating point values.
72 bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const {
73 return getValueAPF().bitwiseIsEqual(V);
76 bool ConstantFPSDNode::isValueValidForType(MVT VT,
78 assert(VT.isFloatingPoint() && "Can only convert between FP types");
80 // PPC long double cannot be converted to any other type.
81 if (VT == MVT::ppcf128 ||
82 &Val.getSemantics() == &APFloat::PPCDoubleDouble)
85 // convert modifies in place, so make a copy.
86 APFloat Val2 = APFloat(Val);
88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
93 //===----------------------------------------------------------------------===//
95 //===----------------------------------------------------------------------===//
97 /// isBuildVectorAllOnes - Return true if the specified node is a
98 /// BUILD_VECTOR where all of the elements are ~0 or undef.
99 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
100 // Look through a bit convert.
101 if (N->getOpcode() == ISD::BIT_CONVERT)
102 N = N->getOperand(0).getNode();
104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
106 unsigned i = 0, e = N->getNumOperands();
108 // Skip over all of the undef values.
109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
112 // Do not accept an all-undef vector.
113 if (i == e) return false;
115 // Do not accept build_vectors that aren't all constants or which have non-~0
117 SDValue NotZero = N->getOperand(i);
118 if (isa<ConstantSDNode>(NotZero)) {
119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
121 } else if (isa<ConstantFPSDNode>(NotZero)) {
122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF().
123 bitcastToAPInt().isAllOnesValue())
128 // Okay, we have at least one ~0 value, check to see if the rest match or are
130 for (++i; i != e; ++i)
131 if (N->getOperand(i) != NotZero &&
132 N->getOperand(i).getOpcode() != ISD::UNDEF)
138 /// isBuildVectorAllZeros - Return true if the specified node is a
139 /// BUILD_VECTOR where all of the elements are 0 or undef.
140 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
141 // Look through a bit convert.
142 if (N->getOpcode() == ISD::BIT_CONVERT)
143 N = N->getOperand(0).getNode();
145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
147 unsigned i = 0, e = N->getNumOperands();
149 // Skip over all of the undef values.
150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
153 // Do not accept an all-undef vector.
154 if (i == e) return false;
156 // Do not accept build_vectors that aren't all constants or which have non-~0
158 SDValue Zero = N->getOperand(i);
159 if (isa<ConstantSDNode>(Zero)) {
160 if (!cast<ConstantSDNode>(Zero)->isNullValue())
162 } else if (isa<ConstantFPSDNode>(Zero)) {
163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero())
168 // Okay, we have at least one ~0 value, check to see if the rest match or are
170 for (++i; i != e; ++i)
171 if (N->getOperand(i) != Zero &&
172 N->getOperand(i).getOpcode() != ISD::UNDEF)
177 /// isScalarToVector - Return true if the specified node is a
178 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
179 /// element is not an undef.
180 bool ISD::isScalarToVector(const SDNode *N) {
181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
184 if (N->getOpcode() != ISD::BUILD_VECTOR)
186 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
188 unsigned NumElems = N->getNumOperands();
189 for (unsigned i = 1; i < NumElems; ++i) {
190 SDValue V = N->getOperand(i);
191 if (V.getOpcode() != ISD::UNDEF)
198 /// isDebugLabel - Return true if the specified node represents a debug
199 /// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
200 bool ISD::isDebugLabel(const SDNode *N) {
202 if (N->getOpcode() == ISD::DBG_LABEL)
204 if (N->isMachineOpcode() &&
205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL)
210 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
211 /// when given the operation for (X op Y).
212 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
213 // To perform this operation, we just need to swap the L and G bits of the
215 unsigned OldL = (Operation >> 2) & 1;
216 unsigned OldG = (Operation >> 1) & 1;
217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
218 (OldL << 1) | // New G bit
219 (OldG << 2)); // New L bit.
222 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
223 /// 'op' is a valid SetCC operation.
224 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
225 unsigned Operation = Op;
227 Operation ^= 7; // Flip L, G, E bits, but not U.
229 Operation ^= 15; // Flip all of the condition bits.
230 if (Operation > ISD::SETTRUE2)
231 Operation &= ~8; // Don't let N and U bits get set.
232 return ISD::CondCode(Operation);
236 /// isSignedOp - For an integer comparison, return 1 if the comparison is a
237 /// signed operation and 2 if the result is an unsigned comparison. Return zero
238 /// if the operation does not depend on the sign of the input (setne and seteq).
239 static int isSignedOp(ISD::CondCode Opcode) {
241 default: assert(0 && "Illegal integer setcc operation!");
243 case ISD::SETNE: return 0;
247 case ISD::SETGE: return 1;
251 case ISD::SETUGE: return 2;
255 /// getSetCCOrOperation - Return the result of a logical OR between different
256 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
257 /// returns SETCC_INVALID if it is not possible to represent the resultant
259 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
261 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
262 // Cannot fold a signed integer setcc with an unsigned integer setcc.
263 return ISD::SETCC_INVALID;
265 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
267 // If the N and U bits get set then the resultant comparison DOES suddenly
268 // care about orderedness, and is true when ordered.
269 if (Op > ISD::SETTRUE2)
270 Op &= ~16; // Clear the U bit if the N bit is set.
272 // Canonicalize illegal integer setcc's.
273 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
276 return ISD::CondCode(Op);
279 /// getSetCCAndOperation - Return the result of a logical AND between different
280 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
281 /// function returns zero if it is not possible to represent the resultant
283 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
285 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
286 // Cannot fold a signed setcc with an unsigned setcc.
287 return ISD::SETCC_INVALID;
289 // Combine all of the condition bits.
290 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
292 // Canonicalize illegal integer setcc's.
296 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
297 case ISD::SETOEQ: // SETEQ & SETU[LG]E
298 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
299 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
300 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
307 const TargetMachine &SelectionDAG::getTarget() const {
308 return MF->getTarget();
311 //===----------------------------------------------------------------------===//
312 // SDNode Profile Support
313 //===----------------------------------------------------------------------===//
315 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
317 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
321 /// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
322 /// solely with their pointer.
323 static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
324 ID.AddPointer(VTList.VTs);
327 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
329 static void AddNodeIDOperands(FoldingSetNodeID &ID,
330 const SDValue *Ops, unsigned NumOps) {
331 for (; NumOps; --NumOps, ++Ops) {
332 ID.AddPointer(Ops->getNode());
333 ID.AddInteger(Ops->getResNo());
337 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
339 static void AddNodeIDOperands(FoldingSetNodeID &ID,
340 const SDUse *Ops, unsigned NumOps) {
341 for (; NumOps; --NumOps, ++Ops) {
342 ID.AddPointer(Ops->getVal());
343 ID.AddInteger(Ops->getSDValue().getResNo());
347 static void AddNodeIDNode(FoldingSetNodeID &ID,
348 unsigned short OpC, SDVTList VTList,
349 const SDValue *OpList, unsigned N) {
350 AddNodeIDOpcode(ID, OpC);
351 AddNodeIDValueTypes(ID, VTList);
352 AddNodeIDOperands(ID, OpList, N);
356 /// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID
358 static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
359 AddNodeIDOpcode(ID, N->getOpcode());
360 // Add the return value info.
361 AddNodeIDValueTypes(ID, N->getVTList());
362 // Add the operand info.
363 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands());
365 // Handle SDNode leafs with special info.
366 switch (N->getOpcode()) {
367 default: break; // Normal nodes don't need extra info.
369 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
371 case ISD::TargetConstant:
373 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue());
375 case ISD::TargetConstantFP:
376 case ISD::ConstantFP: {
377 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue());
380 case ISD::TargetGlobalAddress:
381 case ISD::GlobalAddress:
382 case ISD::TargetGlobalTLSAddress:
383 case ISD::GlobalTLSAddress: {
384 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
385 ID.AddPointer(GA->getGlobal());
386 ID.AddInteger(GA->getOffset());
389 case ISD::BasicBlock:
390 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock());
393 ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
395 case ISD::DBG_STOPPOINT: {
396 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N);
397 ID.AddInteger(DSP->getLine());
398 ID.AddInteger(DSP->getColumn());
399 ID.AddPointer(DSP->getCompileUnit());
403 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
405 case ISD::MEMOPERAND: {
406 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO;
410 case ISD::FrameIndex:
411 case ISD::TargetFrameIndex:
412 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex());
415 case ISD::TargetJumpTable:
416 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex());
418 case ISD::ConstantPool:
419 case ISD::TargetConstantPool: {
420 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
421 ID.AddInteger(CP->getAlignment());
422 ID.AddInteger(CP->getOffset());
423 if (CP->isMachineConstantPoolEntry())
424 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID);
426 ID.AddPointer(CP->getConstVal());
430 const CallSDNode *Call = cast<CallSDNode>(N);
431 ID.AddInteger(Call->getCallingConv());
432 ID.AddInteger(Call->isVarArg());
436 const LoadSDNode *LD = cast<LoadSDNode>(N);
437 ID.AddInteger(LD->getAddressingMode());
438 ID.AddInteger(LD->getExtensionType());
439 ID.AddInteger(LD->getMemoryVT().getRawBits());
440 ID.AddInteger(LD->getRawFlags());
444 const StoreSDNode *ST = cast<StoreSDNode>(N);
445 ID.AddInteger(ST->getAddressingMode());
446 ID.AddInteger(ST->isTruncatingStore());
447 ID.AddInteger(ST->getMemoryVT().getRawBits());
448 ID.AddInteger(ST->getRawFlags());
451 case ISD::ATOMIC_CMP_SWAP_8:
452 case ISD::ATOMIC_SWAP_8:
453 case ISD::ATOMIC_LOAD_ADD_8:
454 case ISD::ATOMIC_LOAD_SUB_8:
455 case ISD::ATOMIC_LOAD_AND_8:
456 case ISD::ATOMIC_LOAD_OR_8:
457 case ISD::ATOMIC_LOAD_XOR_8:
458 case ISD::ATOMIC_LOAD_NAND_8:
459 case ISD::ATOMIC_LOAD_MIN_8:
460 case ISD::ATOMIC_LOAD_MAX_8:
461 case ISD::ATOMIC_LOAD_UMIN_8:
462 case ISD::ATOMIC_LOAD_UMAX_8:
463 case ISD::ATOMIC_CMP_SWAP_16:
464 case ISD::ATOMIC_SWAP_16:
465 case ISD::ATOMIC_LOAD_ADD_16:
466 case ISD::ATOMIC_LOAD_SUB_16:
467 case ISD::ATOMIC_LOAD_AND_16:
468 case ISD::ATOMIC_LOAD_OR_16:
469 case ISD::ATOMIC_LOAD_XOR_16:
470 case ISD::ATOMIC_LOAD_NAND_16:
471 case ISD::ATOMIC_LOAD_MIN_16:
472 case ISD::ATOMIC_LOAD_MAX_16:
473 case ISD::ATOMIC_LOAD_UMIN_16:
474 case ISD::ATOMIC_LOAD_UMAX_16:
475 case ISD::ATOMIC_CMP_SWAP_32:
476 case ISD::ATOMIC_SWAP_32:
477 case ISD::ATOMIC_LOAD_ADD_32:
478 case ISD::ATOMIC_LOAD_SUB_32:
479 case ISD::ATOMIC_LOAD_AND_32:
480 case ISD::ATOMIC_LOAD_OR_32:
481 case ISD::ATOMIC_LOAD_XOR_32:
482 case ISD::ATOMIC_LOAD_NAND_32:
483 case ISD::ATOMIC_LOAD_MIN_32:
484 case ISD::ATOMIC_LOAD_MAX_32:
485 case ISD::ATOMIC_LOAD_UMIN_32:
486 case ISD::ATOMIC_LOAD_UMAX_32:
487 case ISD::ATOMIC_CMP_SWAP_64:
488 case ISD::ATOMIC_SWAP_64:
489 case ISD::ATOMIC_LOAD_ADD_64:
490 case ISD::ATOMIC_LOAD_SUB_64:
491 case ISD::ATOMIC_LOAD_AND_64:
492 case ISD::ATOMIC_LOAD_OR_64:
493 case ISD::ATOMIC_LOAD_XOR_64:
494 case ISD::ATOMIC_LOAD_NAND_64:
495 case ISD::ATOMIC_LOAD_MIN_64:
496 case ISD::ATOMIC_LOAD_MAX_64:
497 case ISD::ATOMIC_LOAD_UMIN_64:
498 case ISD::ATOMIC_LOAD_UMAX_64: {
499 const AtomicSDNode *AT = cast<AtomicSDNode>(N);
500 ID.AddInteger(AT->getRawFlags());
503 } // end switch (N->getOpcode())
506 /// encodeMemSDNodeFlags - Generic routine for computing a value for use in
507 /// the CSE map that carries both alignment and volatility information.
509 static unsigned encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) {
510 return isVolatile | ((Log2_32(Alignment) + 1) << 1);
513 //===----------------------------------------------------------------------===//
514 // SelectionDAG Class
515 //===----------------------------------------------------------------------===//
517 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
519 void SelectionDAG::RemoveDeadNodes() {
520 // Create a dummy node (which is not added to allnodes), that adds a reference
521 // to the root node, preventing it from being deleted.
522 HandleSDNode Dummy(getRoot());
524 SmallVector<SDNode*, 128> DeadNodes;
526 // Add all obviously-dead nodes to the DeadNodes worklist.
527 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I)
529 DeadNodes.push_back(I);
531 RemoveDeadNodes(DeadNodes);
533 // If the root changed (e.g. it was a dead load, update the root).
534 setRoot(Dummy.getValue());
537 /// RemoveDeadNodes - This method deletes the unreachable nodes in the
538 /// given list, and any nodes that become unreachable as a result.
539 void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes,
540 DAGUpdateListener *UpdateListener) {
542 // Process the worklist, deleting the nodes and adding their uses to the
544 while (!DeadNodes.empty()) {
545 SDNode *N = DeadNodes.back();
546 DeadNodes.pop_back();
549 UpdateListener->NodeDeleted(N, 0);
551 // Take the node out of the appropriate CSE map.
552 RemoveNodeFromCSEMaps(N);
554 // Next, brutally remove the operand list. This is safe to do, as there are
555 // no cycles in the graph.
556 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
557 SDNode *Operand = I->getVal();
558 Operand->removeUser(std::distance(N->op_begin(), I), N);
560 // Now that we removed this operand, see if there are no uses of it left.
561 if (Operand->use_empty())
562 DeadNodes.push_back(Operand);
564 if (N->OperandsNeedDelete) {
565 delete[] N->OperandList;
570 // Finally, remove N itself.
571 NodeAllocator.Deallocate(AllNodes.remove(N));
575 void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){
576 SmallVector<SDNode*, 16> DeadNodes(1, N);
577 RemoveDeadNodes(DeadNodes, UpdateListener);
580 void SelectionDAG::DeleteNode(SDNode *N) {
581 assert(N->use_empty() && "Cannot delete a node that is not dead!");
583 // First take this out of the appropriate CSE map.
584 RemoveNodeFromCSEMaps(N);
586 // Finally, remove uses due to operands of this node, remove from the
587 // AllNodes list, and delete the node.
588 DeleteNodeNotInCSEMaps(N);
591 void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
593 // Drop all of the operands and decrement used node's use counts.
594 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
595 I->getVal()->removeUser(std::distance(N->op_begin(), I), N);
596 if (N->OperandsNeedDelete)
597 delete[] N->OperandList;
599 assert(N != AllNodes.begin());
600 NodeAllocator.Deallocate(AllNodes.remove(N));
603 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
604 /// correspond to it. This is useful when we're about to delete or repurpose
605 /// the node. We don't want future request for structurally identical nodes
606 /// to return N anymore.
607 bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
609 switch (N->getOpcode()) {
610 case ISD::EntryToken:
611 assert(0 && "EntryToken should not be in CSEMaps!");
613 case ISD::HANDLENODE: return false; // noop.
615 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
616 "Cond code doesn't exist!");
617 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0;
618 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0;
620 case ISD::ExternalSymbol:
621 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
623 case ISD::TargetExternalSymbol:
625 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
627 case ISD::VALUETYPE: {
628 MVT VT = cast<VTSDNode>(N)->getVT();
629 if (VT.isExtended()) {
630 Erased = ExtendedValueTypeNodes.erase(VT);
632 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
633 ValueTypeNodes[VT.getSimpleVT()] = 0;
638 // Remove it from the CSE Map.
639 Erased = CSEMap.RemoveNode(N);
643 // Verify that the node was actually in one of the CSE maps, unless it has a
644 // flag result (which cannot be CSE'd) or is one of the special cases that are
645 // not subject to CSE.
646 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
647 !N->isMachineOpcode() &&
648 N->getOpcode() != ISD::DBG_LABEL &&
649 N->getOpcode() != ISD::DBG_STOPPOINT &&
650 N->getOpcode() != ISD::EH_LABEL &&
651 N->getOpcode() != ISD::DECLARE) {
654 assert(0 && "Node is not in map!");
660 /// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It
661 /// has been taken out and modified in some way. If the specified node already
662 /// exists in the CSE maps, do not modify the maps, but return the existing node
663 /// instead. If it doesn't exist, add it and return null.
665 SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) {
666 assert(N->getNumOperands() && "This is a leaf node!");
668 if (N->getValueType(0) == MVT::Flag)
669 return 0; // Never CSE anything that produces a flag.
671 switch (N->getOpcode()) {
673 case ISD::HANDLENODE:
675 case ISD::DBG_STOPPOINT:
678 return 0; // Never add these nodes.
681 // Check that remaining values produced are not flags.
682 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
683 if (N->getValueType(i) == MVT::Flag)
684 return 0; // Never CSE anything that produces a flag.
686 SDNode *New = CSEMap.GetOrInsertNode(N);
687 if (New != N) return New; // Node already existed.
691 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
692 /// were replaced with those specified. If this node is never memoized,
693 /// return null, otherwise return a pointer to the slot it would take. If a
694 /// node already exists with these operands, the slot will be non-null.
695 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
697 if (N->getValueType(0) == MVT::Flag)
698 return 0; // Never CSE anything that produces a flag.
700 switch (N->getOpcode()) {
702 case ISD::HANDLENODE:
704 case ISD::DBG_STOPPOINT:
706 return 0; // Never add these nodes.
709 // Check that remaining values produced are not flags.
710 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
711 if (N->getValueType(i) == MVT::Flag)
712 return 0; // Never CSE anything that produces a flag.
714 SDValue Ops[] = { Op };
716 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1);
717 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
720 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
721 /// were replaced with those specified. If this node is never memoized,
722 /// return null, otherwise return a pointer to the slot it would take. If a
723 /// node already exists with these operands, the slot will be non-null.
724 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
725 SDValue Op1, SDValue Op2,
727 if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag)
729 // Check that remaining values produced are not flags.
730 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
731 if (N->getValueType(i) == MVT::Flag)
732 return 0; // Never CSE anything that produces a flag.
734 SDValue Ops[] = { Op1, Op2 };
736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2);
737 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
741 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
742 /// were replaced with those specified. If this node is never memoized,
743 /// return null, otherwise return a pointer to the slot it would take. If a
744 /// node already exists with these operands, the slot will be non-null.
745 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
746 const SDValue *Ops,unsigned NumOps,
748 if (N->getValueType(0) == MVT::Flag)
749 return 0; // Never CSE anything that produces a flag.
751 switch (N->getOpcode()) {
753 case ISD::HANDLENODE:
755 case ISD::DBG_STOPPOINT:
758 return 0; // Never add these nodes.
761 // Check that remaining values produced are not flags.
762 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
763 if (N->getValueType(i) == MVT::Flag)
764 return 0; // Never CSE anything that produces a flag.
767 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps);
769 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
770 ID.AddInteger(LD->getAddressingMode());
771 ID.AddInteger(LD->getExtensionType());
772 ID.AddInteger(LD->getMemoryVT().getRawBits());
773 ID.AddInteger(LD->getRawFlags());
774 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
775 ID.AddInteger(ST->getAddressingMode());
776 ID.AddInteger(ST->isTruncatingStore());
777 ID.AddInteger(ST->getMemoryVT().getRawBits());
778 ID.AddInteger(ST->getRawFlags());
781 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
784 /// VerifyNode - Sanity check the given node. Aborts if it is invalid.
785 void SelectionDAG::VerifyNode(SDNode *N) {
786 switch (N->getOpcode()) {
789 case ISD::BUILD_VECTOR: {
790 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!");
791 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!");
792 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
793 "Wrong number of BUILD_VECTOR operands!");
794 MVT EltVT = N->getValueType(0).getVectorElementType();
795 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
796 assert(I->getSDValue().getValueType() == EltVT &&
797 "Wrong BUILD_VECTOR operand type!");
803 /// getMVTAlignment - Compute the default alignment value for the
806 unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
807 const Type *Ty = VT == MVT::iPTR ?
808 PointerType::get(Type::Int8Ty, 0) :
811 return TLI.getTargetData()->getABITypeAlignment(Ty);
814 SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
815 : TLI(tli), FLI(fli),
816 EntryNode(ISD::EntryToken, getVTList(MVT::Other)),
817 Root(getEntryNode()) {
818 AllNodes.push_back(&EntryNode);
821 void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) {
826 SelectionDAG::~SelectionDAG() {
830 void SelectionDAG::allnodes_clear() {
831 assert(&*AllNodes.begin() == &EntryNode);
832 AllNodes.remove(AllNodes.begin());
833 while (!AllNodes.empty()) {
834 SDNode *N = AllNodes.remove(AllNodes.begin());
835 N->SetNextInBucket(0);
836 if (N->OperandsNeedDelete)
837 delete [] N->OperandList;
838 NodeAllocator.Deallocate(N);
842 void SelectionDAG::clear() {
844 OperandAllocator.Reset();
847 ExtendedValueTypeNodes.clear();
848 ExternalSymbols.clear();
849 TargetExternalSymbols.clear();
850 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
851 static_cast<CondCodeSDNode*>(0));
852 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
853 static_cast<SDNode*>(0));
856 AllNodes.push_back(&EntryNode);
857 Root = getEntryNode();
860 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
861 if (Op.getValueType() == VT) return Op;
862 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
864 return getNode(ISD::AND, Op.getValueType(), Op,
865 getConstant(Imm, Op.getValueType()));
868 SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
869 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
870 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
873 SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
874 return getConstant(*ConstantInt::get(Val), VT, isT);
877 SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) {
878 assert(VT.isInteger() && "Cannot create FP integer constant!");
880 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
881 assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
882 "APInt size does not match type size!");
884 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
886 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
890 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
892 return SDValue(N, 0);
894 N = NodeAllocator.Allocate<ConstantSDNode>();
895 new (N) ConstantSDNode(isT, &Val, EltVT);
896 CSEMap.InsertNode(N, IP);
897 AllNodes.push_back(N);
900 SDValue Result(N, 0);
902 SmallVector<SDValue, 8> Ops;
903 Ops.assign(VT.getVectorNumElements(), Result);
904 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
909 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
910 return getConstant(Val, TLI.getPointerTy(), isTarget);
914 SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
915 return getConstantFP(*ConstantFP::get(V), VT, isTarget);
918 SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
919 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
922 VT.isVector() ? VT.getVectorElementType() : VT;
924 // Do the map lookup using the actual bit pattern for the floating point
925 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and
926 // we don't have issues with SNANs.
927 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
929 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
933 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
935 return SDValue(N, 0);
937 N = NodeAllocator.Allocate<ConstantFPSDNode>();
938 new (N) ConstantFPSDNode(isTarget, &V, EltVT);
939 CSEMap.InsertNode(N, IP);
940 AllNodes.push_back(N);
943 SDValue Result(N, 0);
945 SmallVector<SDValue, 8> Ops;
946 Ops.assign(VT.getVectorNumElements(), Result);
947 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
952 SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
954 VT.isVector() ? VT.getVectorElementType() : VT;
956 return getConstantFP(APFloat((float)Val), VT, isTarget);
958 return getConstantFP(APFloat(Val), VT, isTarget);
961 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
966 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
968 // If GV is an alias then use the aliasee for determining thread-localness.
969 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
970 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
973 if (GVar && GVar->isThreadLocal())
974 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
976 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
979 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
981 ID.AddInteger(Offset);
983 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
984 return SDValue(E, 0);
985 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>();
986 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset);
987 CSEMap.InsertNode(N, IP);
988 AllNodes.push_back(N);
989 return SDValue(N, 0);
992 SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
993 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
995 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
998 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
999 return SDValue(E, 0);
1000 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>();
1001 new (N) FrameIndexSDNode(FI, VT, isTarget);
1002 CSEMap.InsertNode(N, IP);
1003 AllNodes.push_back(N);
1004 return SDValue(N, 0);
1007 SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){
1008 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1009 FoldingSetNodeID ID;
1010 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1013 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1014 return SDValue(E, 0);
1015 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>();
1016 new (N) JumpTableSDNode(JTI, VT, isTarget);
1017 CSEMap.InsertNode(N, IP);
1018 AllNodes.push_back(N);
1019 return SDValue(N, 0);
1022 SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
1023 unsigned Alignment, int Offset,
1027 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType());
1028 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1029 FoldingSetNodeID ID;
1030 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1031 ID.AddInteger(Alignment);
1032 ID.AddInteger(Offset);
1035 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1036 return SDValue(E, 0);
1037 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1038 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
1039 CSEMap.InsertNode(N, IP);
1040 AllNodes.push_back(N);
1041 return SDValue(N, 0);
1045 SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
1046 unsigned Alignment, int Offset,
1050 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType());
1051 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1052 FoldingSetNodeID ID;
1053 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1054 ID.AddInteger(Alignment);
1055 ID.AddInteger(Offset);
1056 C->AddSelectionDAGCSEId(ID);
1058 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1059 return SDValue(E, 0);
1060 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1061 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
1062 CSEMap.InsertNode(N, IP);
1063 AllNodes.push_back(N);
1064 return SDValue(N, 0);
1068 SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
1069 FoldingSetNodeID ID;
1070 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1073 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1074 return SDValue(E, 0);
1075 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>();
1076 new (N) BasicBlockSDNode(MBB);
1077 CSEMap.InsertNode(N, IP);
1078 AllNodes.push_back(N);
1079 return SDValue(N, 0);
1082 SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
1083 FoldingSetNodeID ID;
1084 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
1085 ID.AddInteger(Flags.getRawBits());
1087 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1088 return SDValue(E, 0);
1089 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>();
1090 new (N) ARG_FLAGSSDNode(Flags);
1091 CSEMap.InsertNode(N, IP);
1092 AllNodes.push_back(N);
1093 return SDValue(N, 0);
1096 SDValue SelectionDAG::getValueType(MVT VT) {
1097 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
1098 ValueTypeNodes.resize(VT.getSimpleVT()+1);
1100 SDNode *&N = VT.isExtended() ?
1101 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
1103 if (N) return SDValue(N, 0);
1104 N = NodeAllocator.Allocate<VTSDNode>();
1105 new (N) VTSDNode(VT);
1106 AllNodes.push_back(N);
1107 return SDValue(N, 0);
1110 SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
1111 SDNode *&N = ExternalSymbols[Sym];
1112 if (N) return SDValue(N, 0);
1113 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1114 new (N) ExternalSymbolSDNode(false, Sym, VT);
1115 AllNodes.push_back(N);
1116 return SDValue(N, 0);
1119 SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
1120 SDNode *&N = TargetExternalSymbols[Sym];
1121 if (N) return SDValue(N, 0);
1122 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1123 new (N) ExternalSymbolSDNode(true, Sym, VT);
1124 AllNodes.push_back(N);
1125 return SDValue(N, 0);
1128 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1129 if ((unsigned)Cond >= CondCodeNodes.size())
1130 CondCodeNodes.resize(Cond+1);
1132 if (CondCodeNodes[Cond] == 0) {
1133 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>();
1134 new (N) CondCodeSDNode(Cond);
1135 CondCodeNodes[Cond] = N;
1136 AllNodes.push_back(N);
1138 return SDValue(CondCodeNodes[Cond], 0);
1141 SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
1142 FoldingSetNodeID ID;
1143 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1144 ID.AddInteger(RegNo);
1146 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1147 return SDValue(E, 0);
1148 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>();
1149 new (N) RegisterSDNode(RegNo, VT);
1150 CSEMap.InsertNode(N, IP);
1151 AllNodes.push_back(N);
1152 return SDValue(N, 0);
1155 SDValue SelectionDAG::getDbgStopPoint(SDValue Root,
1156 unsigned Line, unsigned Col,
1157 const CompileUnitDesc *CU) {
1158 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>();
1159 new (N) DbgStopPointSDNode(Root, Line, Col, CU);
1160 AllNodes.push_back(N);
1161 return SDValue(N, 0);
1164 SDValue SelectionDAG::getLabel(unsigned Opcode,
1167 FoldingSetNodeID ID;
1168 SDValue Ops[] = { Root };
1169 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
1170 ID.AddInteger(LabelID);
1172 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1173 return SDValue(E, 0);
1174 SDNode *N = NodeAllocator.Allocate<LabelSDNode>();
1175 new (N) LabelSDNode(Opcode, Root, LabelID);
1176 CSEMap.InsertNode(N, IP);
1177 AllNodes.push_back(N);
1178 return SDValue(N, 0);
1181 SDValue SelectionDAG::getSrcValue(const Value *V) {
1182 assert((!V || isa<PointerType>(V->getType())) &&
1183 "SrcValue is not a pointer?");
1185 FoldingSetNodeID ID;
1186 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1190 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1191 return SDValue(E, 0);
1193 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>();
1194 new (N) SrcValueSDNode(V);
1195 CSEMap.InsertNode(N, IP);
1196 AllNodes.push_back(N);
1197 return SDValue(N, 0);
1200 SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
1201 const Value *v = MO.getValue();
1202 assert((!v || isa<PointerType>(v->getType())) &&
1203 "SrcValue is not a pointer?");
1205 FoldingSetNodeID ID;
1206 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
1210 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1211 return SDValue(E, 0);
1213 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>();
1214 new (N) MemOperandSDNode(MO);
1215 CSEMap.InsertNode(N, IP);
1216 AllNodes.push_back(N);
1217 return SDValue(N, 0);
1220 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
1221 /// specified value type.
1222 SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
1223 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1224 unsigned ByteSize = VT.getSizeInBits()/8;
1225 const Type *Ty = VT.getTypeForMVT();
1226 unsigned StackAlign =
1227 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
1229 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
1230 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1233 SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
1234 SDValue N2, ISD::CondCode Cond) {
1235 // These setcc operations always fold.
1239 case ISD::SETFALSE2: return getConstant(0, VT);
1241 case ISD::SETTRUE2: return getConstant(1, VT);
1253 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!");
1257 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
1258 const APInt &C2 = N2C->getAPIntValue();
1259 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1260 const APInt &C1 = N1C->getAPIntValue();
1263 default: assert(0 && "Unknown integer setcc!");
1264 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1265 case ISD::SETNE: return getConstant(C1 != C2, VT);
1266 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1267 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1268 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1269 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1270 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1271 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1272 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1273 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1277 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1278 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
1279 // No compile time operations on this type yet.
1280 if (N1C->getValueType(0) == MVT::ppcf128)
1283 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
1286 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1287 return getNode(ISD::UNDEF, VT);
1289 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1290 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1291 return getNode(ISD::UNDEF, VT);
1293 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1294 R==APFloat::cmpLessThan, VT);
1295 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1296 return getNode(ISD::UNDEF, VT);
1298 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1299 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1300 return getNode(ISD::UNDEF, VT);
1302 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1303 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1304 return getNode(ISD::UNDEF, VT);
1306 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1307 R==APFloat::cmpEqual, VT);
1308 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1309 return getNode(ISD::UNDEF, VT);
1311 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1312 R==APFloat::cmpEqual, VT);
1313 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1314 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1315 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1316 R==APFloat::cmpEqual, VT);
1317 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1318 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1319 R==APFloat::cmpLessThan, VT);
1320 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1321 R==APFloat::cmpUnordered, VT);
1322 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1323 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1326 // Ensure that the constant occurs on the RHS.
1327 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1331 // Could not fold it.
1335 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
1336 /// use this predicate to simplify operations downstream.
1337 bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
1338 unsigned BitWidth = Op.getValueSizeInBits();
1339 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
1342 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
1343 /// this predicate to simplify operations downstream. Mask is known to be zero
1344 /// for bits that V cannot have.
1345 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
1346 unsigned Depth) const {
1347 APInt KnownZero, KnownOne;
1348 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1349 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1350 return (KnownZero & Mask) == Mask;
1353 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
1354 /// known to be either zero or one and return them in the KnownZero/KnownOne
1355 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
1357 void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
1358 APInt &KnownZero, APInt &KnownOne,
1359 unsigned Depth) const {
1360 unsigned BitWidth = Mask.getBitWidth();
1361 assert(BitWidth == Op.getValueType().getSizeInBits() &&
1362 "Mask size mismatches value type size!");
1364 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
1365 if (Depth == 6 || Mask == 0)
1366 return; // Limit search depth.
1368 APInt KnownZero2, KnownOne2;
1370 switch (Op.getOpcode()) {
1372 // We know all of the bits for a constant!
1373 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask;
1374 KnownZero = ~KnownOne & Mask;
1377 // If either the LHS or the RHS are Zero, the result is zero.
1378 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1379 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero,
1380 KnownZero2, KnownOne2, Depth+1);
1381 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1382 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1384 // Output known-1 bits are only known if set in both the LHS & RHS.
1385 KnownOne &= KnownOne2;
1386 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1387 KnownZero |= KnownZero2;
1390 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1391 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne,
1392 KnownZero2, KnownOne2, Depth+1);
1393 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1394 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1396 // Output known-0 bits are only known if clear in both the LHS & RHS.
1397 KnownZero &= KnownZero2;
1398 // Output known-1 are known to be set if set in either the LHS | RHS.
1399 KnownOne |= KnownOne2;
1402 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1403 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
1404 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1405 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1407 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1408 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1409 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1410 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1411 KnownZero = KnownZeroOut;
1415 APInt Mask2 = APInt::getAllOnesValue(BitWidth);
1416 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1);
1417 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1418 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1419 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1421 // If low bits are zero in either operand, output low known-0 bits.
1422 // Also compute a conserative estimate for high known-0 bits.
1423 // More trickiness is possible, but this is sufficient for the
1424 // interesting case of alignment computation.
1426 unsigned TrailZ = KnownZero.countTrailingOnes() +
1427 KnownZero2.countTrailingOnes();
1428 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() +
1429 KnownZero2.countLeadingOnes(),
1430 BitWidth) - BitWidth;
1432 TrailZ = std::min(TrailZ, BitWidth);
1433 LeadZ = std::min(LeadZ, BitWidth);
1434 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
1435 APInt::getHighBitsSet(BitWidth, LeadZ);
1440 // For the purposes of computing leading zeros we can conservatively
1441 // treat a udiv as a logical right shift by the power of 2 known to
1442 // be less than the denominator.
1443 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1444 ComputeMaskedBits(Op.getOperand(0),
1445 AllOnes, KnownZero2, KnownOne2, Depth+1);
1446 unsigned LeadZ = KnownZero2.countLeadingOnes();
1450 ComputeMaskedBits(Op.getOperand(1),
1451 AllOnes, KnownZero2, KnownOne2, Depth+1);
1452 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
1453 if (RHSUnknownLeadingOnes != BitWidth)
1454 LeadZ = std::min(BitWidth,
1455 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1);
1457 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask;
1461 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
1462 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
1463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1464 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1466 // Only known if known in both the LHS and RHS.
1467 KnownOne &= KnownOne2;
1468 KnownZero &= KnownZero2;
1470 case ISD::SELECT_CC:
1471 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
1472 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
1473 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1474 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1476 // Only known if known in both the LHS and RHS.
1477 KnownOne &= KnownOne2;
1478 KnownZero &= KnownZero2;
1481 // If we know the result of a setcc has the top bits zero, use this info.
1482 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult &&
1484 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1487 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
1488 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1489 unsigned ShAmt = SA->getZExtValue();
1491 // If the shift count is an invalid immediate, don't do anything.
1492 if (ShAmt >= BitWidth)
1495 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt),
1496 KnownZero, KnownOne, Depth+1);
1497 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1498 KnownZero <<= ShAmt;
1500 // low bits known zero.
1501 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt);
1505 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
1506 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1507 unsigned ShAmt = SA->getZExtValue();
1509 // If the shift count is an invalid immediate, don't do anything.
1510 if (ShAmt >= BitWidth)
1513 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt),
1514 KnownZero, KnownOne, Depth+1);
1515 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1516 KnownZero = KnownZero.lshr(ShAmt);
1517 KnownOne = KnownOne.lshr(ShAmt);
1519 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1520 KnownZero |= HighBits; // High bits known zero.
1524 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1525 unsigned ShAmt = SA->getZExtValue();
1527 // If the shift count is an invalid immediate, don't do anything.
1528 if (ShAmt >= BitWidth)
1531 APInt InDemandedMask = (Mask << ShAmt);
1532 // If any of the demanded bits are produced by the sign extension, we also
1533 // demand the input sign bit.
1534 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1535 if (HighBits.getBoolValue())
1536 InDemandedMask |= APInt::getSignBit(BitWidth);
1538 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
1540 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1541 KnownZero = KnownZero.lshr(ShAmt);
1542 KnownOne = KnownOne.lshr(ShAmt);
1544 // Handle the sign bits.
1545 APInt SignBit = APInt::getSignBit(BitWidth);
1546 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask.
1548 if (KnownZero.intersects(SignBit)) {
1549 KnownZero |= HighBits; // New bits are known zero.
1550 } else if (KnownOne.intersects(SignBit)) {
1551 KnownOne |= HighBits; // New bits are known one.
1555 case ISD::SIGN_EXTEND_INREG: {
1556 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1557 unsigned EBits = EVT.getSizeInBits();
1559 // Sign extension. Compute the demanded bits in the result that are not
1560 // present in the input.
1561 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask;
1563 APInt InSignBit = APInt::getSignBit(EBits);
1564 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits);
1566 // If the sign extended bits are demanded, we know that the sign
1568 InSignBit.zext(BitWidth);
1569 if (NewBits.getBoolValue())
1570 InputDemandedBits |= InSignBit;
1572 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
1573 KnownZero, KnownOne, Depth+1);
1574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1576 // If the sign bit of the input is known set or clear, then we know the
1577 // top bits of the result.
1578 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear
1579 KnownZero |= NewBits;
1580 KnownOne &= ~NewBits;
1581 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1582 KnownOne |= NewBits;
1583 KnownZero &= ~NewBits;
1584 } else { // Input sign bit unknown
1585 KnownZero &= ~NewBits;
1586 KnownOne &= ~NewBits;
1593 unsigned LowBits = Log2_32(BitWidth)+1;
1594 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits);
1599 if (ISD::isZEXTLoad(Op.getNode())) {
1600 LoadSDNode *LD = cast<LoadSDNode>(Op);
1601 MVT VT = LD->getMemoryVT();
1602 unsigned MemBits = VT.getSizeInBits();
1603 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
1607 case ISD::ZERO_EXTEND: {
1608 MVT InVT = Op.getOperand(0).getValueType();
1609 unsigned InBits = InVT.getSizeInBits();
1610 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1611 APInt InMask = Mask;
1612 InMask.trunc(InBits);
1613 KnownZero.trunc(InBits);
1614 KnownOne.trunc(InBits);
1615 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1616 KnownZero.zext(BitWidth);
1617 KnownOne.zext(BitWidth);
1618 KnownZero |= NewBits;
1621 case ISD::SIGN_EXTEND: {
1622 MVT InVT = Op.getOperand(0).getValueType();
1623 unsigned InBits = InVT.getSizeInBits();
1624 APInt InSignBit = APInt::getSignBit(InBits);
1625 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1626 APInt InMask = Mask;
1627 InMask.trunc(InBits);
1629 // If any of the sign extended bits are demanded, we know that the sign
1630 // bit is demanded. Temporarily set this bit in the mask for our callee.
1631 if (NewBits.getBoolValue())
1632 InMask |= InSignBit;
1634 KnownZero.trunc(InBits);
1635 KnownOne.trunc(InBits);
1636 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1638 // Note if the sign bit is known to be zero or one.
1639 bool SignBitKnownZero = KnownZero.isNegative();
1640 bool SignBitKnownOne = KnownOne.isNegative();
1641 assert(!(SignBitKnownZero && SignBitKnownOne) &&
1642 "Sign bit can't be known to be both zero and one!");
1644 // If the sign bit wasn't actually demanded by our caller, we don't
1645 // want it set in the KnownZero and KnownOne result values. Reset the
1646 // mask and reapply it to the result values.
1648 InMask.trunc(InBits);
1649 KnownZero &= InMask;
1652 KnownZero.zext(BitWidth);
1653 KnownOne.zext(BitWidth);
1655 // If the sign bit is known zero or one, the top bits match.
1656 if (SignBitKnownZero)
1657 KnownZero |= NewBits;
1658 else if (SignBitKnownOne)
1659 KnownOne |= NewBits;
1662 case ISD::ANY_EXTEND: {
1663 MVT InVT = Op.getOperand(0).getValueType();
1664 unsigned InBits = InVT.getSizeInBits();
1665 APInt InMask = Mask;
1666 InMask.trunc(InBits);
1667 KnownZero.trunc(InBits);
1668 KnownOne.trunc(InBits);
1669 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1670 KnownZero.zext(BitWidth);
1671 KnownOne.zext(BitWidth);
1674 case ISD::TRUNCATE: {
1675 MVT InVT = Op.getOperand(0).getValueType();
1676 unsigned InBits = InVT.getSizeInBits();
1677 APInt InMask = Mask;
1678 InMask.zext(InBits);
1679 KnownZero.zext(InBits);
1680 KnownOne.zext(InBits);
1681 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1683 KnownZero.trunc(BitWidth);
1684 KnownOne.trunc(BitWidth);
1687 case ISD::AssertZext: {
1688 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1689 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
1690 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1692 KnownZero |= (~InMask) & Mask;
1696 // All bits are zero except the low bit.
1697 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1701 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
1702 // We know that the top bits of C-X are clear if X contains less bits
1703 // than C (i.e. no wrap-around can happen). For example, 20-X is
1704 // positive if we can prove that X is >= 0 and < 16.
1705 if (CLHS->getAPIntValue().isNonNegative()) {
1706 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
1707 // NLZ can't be BitWidth with no sign bit
1708 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
1709 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2,
1712 // If all of the MaskV bits are known to be zero, then we know the
1713 // output top bits are zero, because we now know that the output is
1715 if ((KnownZero2 & MaskV) == MaskV) {
1716 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros();
1717 // Top bits known zero.
1718 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask;
1725 // Output known-0 bits are known if clear or set in both the low clear bits
1726 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
1727 // low 3 bits clear.
1728 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes());
1729 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1730 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1731 unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
1733 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1);
1734 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1735 KnownZeroOut = std::min(KnownZeroOut,
1736 KnownZero2.countTrailingOnes());
1738 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut);
1742 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1743 const APInt &RA = Rem->getAPIntValue();
1744 if (RA.isPowerOf2() || (-RA).isPowerOf2()) {
1745 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA;
1746 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
1747 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
1749 // If the sign bit of the first operand is zero, the sign bit of
1750 // the result is zero. If the first operand has no one bits below
1751 // the second operand's single 1 bit, its sign will be zero.
1752 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
1753 KnownZero2 |= ~LowBits;
1755 KnownZero |= KnownZero2 & Mask;
1757 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1762 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1763 const APInt &RA = Rem->getAPIntValue();
1764 if (RA.isPowerOf2()) {
1765 APInt LowBits = (RA - 1);
1766 APInt Mask2 = LowBits & Mask;
1767 KnownZero |= ~LowBits & Mask;
1768 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1);
1769 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1774 // Since the result is less than or equal to either operand, any leading
1775 // zero bits in either operand must also exist in the result.
1776 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1777 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne,
1779 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2,
1782 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(),
1783 KnownZero2.countLeadingOnes());
1785 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask;
1789 // Allow the target to implement this method for its nodes.
1790 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1791 case ISD::INTRINSIC_WO_CHAIN:
1792 case ISD::INTRINSIC_W_CHAIN:
1793 case ISD::INTRINSIC_VOID:
1794 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this);
1800 /// ComputeNumSignBits - Return the number of times the sign bit of the
1801 /// register is replicated into the other bits. We know that at least 1 bit
1802 /// is always equal to the sign bit (itself), but other cases can give us
1803 /// information. For example, immediately after an "SRA X, 2", we know that
1804 /// the top 3 bits are all equal to each other, so we return 3.
1805 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
1806 MVT VT = Op.getValueType();
1807 assert(VT.isInteger() && "Invalid VT!");
1808 unsigned VTBits = VT.getSizeInBits();
1810 unsigned FirstAnswer = 1;
1813 return 1; // Limit search depth.
1815 switch (Op.getOpcode()) {
1817 case ISD::AssertSext:
1818 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1819 return VTBits-Tmp+1;
1820 case ISD::AssertZext:
1821 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1824 case ISD::Constant: {
1825 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
1826 // If negative, return # leading ones.
1827 if (Val.isNegative())
1828 return Val.countLeadingOnes();
1830 // Return # leading zeros.
1831 return Val.countLeadingZeros();
1834 case ISD::SIGN_EXTEND:
1835 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
1836 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
1838 case ISD::SIGN_EXTEND_INREG:
1839 // Max of the input and what this extends.
1840 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1843 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1844 return std::max(Tmp, Tmp2);
1847 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1848 // SRA X, C -> adds C sign bits.
1849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1850 Tmp += C->getZExtValue();
1851 if (Tmp > VTBits) Tmp = VTBits;
1855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1856 // shl destroys sign bits.
1857 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1858 if (C->getZExtValue() >= VTBits || // Bad shift.
1859 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out.
1860 return Tmp - C->getZExtValue();
1865 case ISD::XOR: // NOT is handled here.
1866 // Logical binary ops preserve the number of sign bits at the worst.
1867 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1869 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1870 FirstAnswer = std::min(Tmp, Tmp2);
1871 // We computed what we know about the sign bits as our first
1872 // answer. Now proceed to the generic code that uses
1873 // ComputeMaskedBits, and pick whichever answer is better.
1878 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1879 if (Tmp == 1) return 1; // Early out.
1880 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1);
1881 return std::min(Tmp, Tmp2);
1884 // If setcc returns 0/-1, all bits are sign bits.
1885 if (TLI.getSetCCResultContents() ==
1886 TargetLowering::ZeroOrNegativeOneSetCCResult)
1891 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1892 unsigned RotAmt = C->getZExtValue() & (VTBits-1);
1894 // Handle rotate right by N like a rotate left by 32-N.
1895 if (Op.getOpcode() == ISD::ROTR)
1896 RotAmt = (VTBits-RotAmt) & (VTBits-1);
1898 // If we aren't rotating out all of the known-in sign bits, return the
1899 // number that are left. This handles rotl(sext(x), 1) for example.
1900 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1901 if (Tmp > RotAmt+1) return Tmp-RotAmt;
1905 // Add can have at most one carry bit. Thus we know that the output
1906 // is, at worst, one more bit than the inputs.
1907 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1908 if (Tmp == 1) return 1; // Early out.
1910 // Special case decrementing a value (ADD X, -1):
1911 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1912 if (CRHS->isAllOnesValue()) {
1913 APInt KnownZero, KnownOne;
1914 APInt Mask = APInt::getAllOnesValue(VTBits);
1915 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1917 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1919 if ((KnownZero | APInt(VTBits, 1)) == Mask)
1922 // If we are subtracting one from a positive number, there is no carry
1923 // out of the result.
1924 if (KnownZero.isNegative())
1928 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1929 if (Tmp2 == 1) return 1;
1930 return std::min(Tmp, Tmp2)-1;
1934 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1935 if (Tmp2 == 1) return 1;
1938 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1939 if (CLHS->isNullValue()) {
1940 APInt KnownZero, KnownOne;
1941 APInt Mask = APInt::getAllOnesValue(VTBits);
1942 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1943 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1945 if ((KnownZero | APInt(VTBits, 1)) == Mask)
1948 // If the input is known to be positive (the sign bit is known clear),
1949 // the output of the NEG has the same number of sign bits as the input.
1950 if (KnownZero.isNegative())
1953 // Otherwise, we treat this like a SUB.
1956 // Sub can have at most one carry bit. Thus we know that the output
1957 // is, at worst, one more bit than the inputs.
1958 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1959 if (Tmp == 1) return 1; // Early out.
1960 return std::min(Tmp, Tmp2)-1;
1963 // FIXME: it's tricky to do anything useful for this, but it is an important
1964 // case for targets like X86.
1968 // Handle LOADX separately here. EXTLOAD case will fallthrough.
1969 if (Op.getOpcode() == ISD::LOAD) {
1970 LoadSDNode *LD = cast<LoadSDNode>(Op);
1971 unsigned ExtType = LD->getExtensionType();
1974 case ISD::SEXTLOAD: // '17' bits known
1975 Tmp = LD->getMemoryVT().getSizeInBits();
1976 return VTBits-Tmp+1;
1977 case ISD::ZEXTLOAD: // '16' bits known
1978 Tmp = LD->getMemoryVT().getSizeInBits();
1983 // Allow the target to implement this method for its nodes.
1984 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1985 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1986 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1987 Op.getOpcode() == ISD::INTRINSIC_VOID) {
1988 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth);
1989 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits);
1992 // Finally, if we can prove that the top bits of the result are 0's or 1's,
1993 // use this information.
1994 APInt KnownZero, KnownOne;
1995 APInt Mask = APInt::getAllOnesValue(VTBits);
1996 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1998 if (KnownZero.isNegative()) { // sign bit is 0
2000 } else if (KnownOne.isNegative()) { // sign bit is 1;
2007 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
2008 // the number of identical bits in the top of the input value.
2010 Mask <<= Mask.getBitWidth()-VTBits;
2011 // Return # leading zeros. We use 'min' here in case Val was zero before
2012 // shifting. We don't want to return '64' as for an i32 "0".
2013 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros()));
2017 bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
2018 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2019 if (!GA) return false;
2020 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal());
2021 if (!GV) return false;
2022 MachineModuleInfo *MMI = getMachineModuleInfo();
2023 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV);
2027 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
2028 /// element of the result of the vector shuffle.
2029 SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
2030 MVT VT = N->getValueType(0);
2031 SDValue PermMask = N->getOperand(2);
2032 SDValue Idx = PermMask.getOperand(i);
2033 if (Idx.getOpcode() == ISD::UNDEF)
2034 return getNode(ISD::UNDEF, VT.getVectorElementType());
2035 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
2036 unsigned NumElems = PermMask.getNumOperands();
2037 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
2040 if (V.getOpcode() == ISD::BIT_CONVERT) {
2041 V = V.getOperand(0);
2042 if (V.getValueType().getVectorNumElements() != NumElems)
2045 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
2046 return (Index == 0) ? V.getOperand(0)
2047 : getNode(ISD::UNDEF, VT.getVectorElementType());
2048 if (V.getOpcode() == ISD::BUILD_VECTOR)
2049 return V.getOperand(Index);
2050 if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
2051 return getShuffleScalarElt(V.getNode(), Index);
2056 /// getNode - Gets or creates the specified node.
2058 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) {
2059 FoldingSetNodeID ID;
2060 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
2062 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2063 return SDValue(E, 0);
2064 SDNode *N = NodeAllocator.Allocate<SDNode>();
2065 new (N) SDNode(Opcode, SDNode::getSDVTList(VT));
2066 CSEMap.InsertNode(N, IP);
2068 AllNodes.push_back(N);
2072 return SDValue(N, 0);
2075 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) {
2076 // Constant fold unary operations with an integer constant operand.
2077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
2078 const APInt &Val = C->getAPIntValue();
2079 unsigned BitWidth = VT.getSizeInBits();
2082 case ISD::SIGN_EXTEND:
2083 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT);
2084 case ISD::ANY_EXTEND:
2085 case ISD::ZERO_EXTEND:
2087 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT);
2088 case ISD::UINT_TO_FP:
2089 case ISD::SINT_TO_FP: {
2090 const uint64_t zero[] = {0, 0};
2091 // No compile time operations on this type.
2092 if (VT==MVT::ppcf128)
2094 APFloat apf = APFloat(APInt(BitWidth, 2, zero));
2095 (void)apf.convertFromAPInt(Val,
2096 Opcode==ISD::SINT_TO_FP,
2097 APFloat::rmNearestTiesToEven);
2098 return getConstantFP(apf, VT);
2100 case ISD::BIT_CONVERT:
2101 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
2102 return getConstantFP(Val.bitsToFloat(), VT);
2103 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
2104 return getConstantFP(Val.bitsToDouble(), VT);
2107 return getConstant(Val.byteSwap(), VT);
2109 return getConstant(Val.countPopulation(), VT);
2111 return getConstant(Val.countLeadingZeros(), VT);
2113 return getConstant(Val.countTrailingZeros(), VT);
2117 // Constant fold unary operations with a floating point constant operand.
2118 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
2119 APFloat V = C->getValueAPF(); // make copy
2120 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
2124 return getConstantFP(V, VT);
2127 return getConstantFP(V, VT);
2129 case ISD::FP_EXTEND: {
2131 // This can return overflow, underflow, or inexact; we don't care.
2132 // FIXME need to be more flexible about rounding mode.
2133 (void)V.convert(*MVTToAPFloatSemantics(VT),
2134 APFloat::rmNearestTiesToEven, &ignored);
2135 return getConstantFP(V, VT);
2137 case ISD::FP_TO_SINT:
2138 case ISD::FP_TO_UINT: {
2141 assert(integerPartWidth >= 64);
2142 // FIXME need to be more flexible about rounding mode.
2143 APFloat::opStatus s = V.convertToInteger(&x, 64U,
2144 Opcode==ISD::FP_TO_SINT,
2145 APFloat::rmTowardZero, &ignored);
2146 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual
2148 return getConstant(x, VT);
2150 case ISD::BIT_CONVERT:
2151 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
2152 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
2153 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
2154 return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
2160 unsigned OpOpcode = Operand.getNode()->getOpcode();
2162 case ISD::TokenFactor:
2163 case ISD::CONCAT_VECTORS:
2164 return Operand; // Factor or concat of one node? No need.
2165 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node");
2166 case ISD::FP_EXTEND:
2167 assert(VT.isFloatingPoint() &&
2168 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
2169 if (Operand.getValueType() == VT) return Operand; // noop conversion.
2170 if (Operand.getOpcode() == ISD::UNDEF)
2171 return getNode(ISD::UNDEF, VT);
2173 case ISD::SIGN_EXTEND:
2174 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2175 "Invalid SIGN_EXTEND!");
2176 if (Operand.getValueType() == VT) return Operand; // noop extension
2177 assert(Operand.getValueType().bitsLT(VT)
2178 && "Invalid sext node, dst < src!");
2179 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2180 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
2182 case ISD::ZERO_EXTEND:
2183 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2184 "Invalid ZERO_EXTEND!");
2185 if (Operand.getValueType() == VT) return Operand; // noop extension
2186 assert(Operand.getValueType().bitsLT(VT)
2187 && "Invalid zext node, dst < src!");
2188 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2189 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0));
2191 case ISD::ANY_EXTEND:
2192 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2193 "Invalid ANY_EXTEND!");
2194 if (Operand.getValueType() == VT) return Operand; // noop extension
2195 assert(Operand.getValueType().bitsLT(VT)
2196 && "Invalid anyext node, dst < src!");
2197 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
2198 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
2199 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
2202 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2203 "Invalid TRUNCATE!");
2204 if (Operand.getValueType() == VT) return Operand; // noop truncate
2205 assert(Operand.getValueType().bitsGT(VT)
2206 && "Invalid truncate node, src < dst!");
2207 if (OpOpcode == ISD::TRUNCATE)
2208 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
2209 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2210 OpOpcode == ISD::ANY_EXTEND) {
2211 // If the source is smaller than the dest, we still need an extend.
2212 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
2213 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
2214 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
2215 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
2217 return Operand.getNode()->getOperand(0);
2220 case ISD::BIT_CONVERT:
2221 // Basic sanity checking.
2222 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits()
2223 && "Cannot BIT_CONVERT between types of different sizes!");
2224 if (VT == Operand.getValueType()) return Operand; // noop conversion.
2225 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
2226 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0));
2227 if (OpOpcode == ISD::UNDEF)
2228 return getNode(ISD::UNDEF, VT);
2230 case ISD::SCALAR_TO_VECTOR:
2231 assert(VT.isVector() && !Operand.getValueType().isVector() &&
2232 VT.getVectorElementType() == Operand.getValueType() &&
2233 "Illegal SCALAR_TO_VECTOR node!");
2234 if (OpOpcode == ISD::UNDEF)
2235 return getNode(ISD::UNDEF, VT);
2236 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
2237 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2238 isa<ConstantSDNode>(Operand.getOperand(1)) &&
2239 Operand.getConstantOperandVal(1) == 0 &&
2240 Operand.getOperand(0).getValueType() == VT)
2241 return Operand.getOperand(0);
2244 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X)
2245 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1),
2246 Operand.getNode()->getOperand(0));
2247 if (OpOpcode == ISD::FNEG) // --X -> X
2248 return Operand.getNode()->getOperand(0);
2251 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2252 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0));
2257 SDVTList VTs = getVTList(VT);
2258 if (VT != MVT::Flag) { // Don't CSE flag producing nodes
2259 FoldingSetNodeID ID;
2260 SDValue Ops[1] = { Operand };
2261 AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
2263 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2264 return SDValue(E, 0);
2265 N = NodeAllocator.Allocate<UnarySDNode>();
2266 new (N) UnarySDNode(Opcode, VTs, Operand);
2267 CSEMap.InsertNode(N, IP);
2269 N = NodeAllocator.Allocate<UnarySDNode>();
2270 new (N) UnarySDNode(Opcode, VTs, Operand);
2273 AllNodes.push_back(N);
2277 return SDValue(N, 0);
2280 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode,
2282 ConstantSDNode *Cst1,
2283 ConstantSDNode *Cst2) {
2284 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue();
2287 case ISD::ADD: return getConstant(C1 + C2, VT);
2288 case ISD::SUB: return getConstant(C1 - C2, VT);
2289 case ISD::MUL: return getConstant(C1 * C2, VT);
2291 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT);
2294 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT);
2297 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT);
2300 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT);
2302 case ISD::AND: return getConstant(C1 & C2, VT);
2303 case ISD::OR: return getConstant(C1 | C2, VT);
2304 case ISD::XOR: return getConstant(C1 ^ C2, VT);
2305 case ISD::SHL: return getConstant(C1 << C2, VT);
2306 case ISD::SRL: return getConstant(C1.lshr(C2), VT);
2307 case ISD::SRA: return getConstant(C1.ashr(C2), VT);
2308 case ISD::ROTL: return getConstant(C1.rotl(C2), VT);
2309 case ISD::ROTR: return getConstant(C1.rotr(C2), VT);
2316 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
2317 SDValue N1, SDValue N2) {
2318 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2319 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2322 case ISD::TokenFactor:
2323 assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
2324 N2.getValueType() == MVT::Other && "Invalid token factor!");
2325 // Fold trivial token factors.
2326 if (N1.getOpcode() == ISD::EntryToken) return N2;
2327 if (N2.getOpcode() == ISD::EntryToken) return N1;
2328 if (N1 == N2) return N1;
2330 case ISD::CONCAT_VECTORS:
2331 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2332 // one big BUILD_VECTOR.
2333 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2334 N2.getOpcode() == ISD::BUILD_VECTOR) {
2335 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2336 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2337 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
2341 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2342 N1.getValueType() == VT && "Binary operator types must match!");
2343 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
2344 // worth handling here.
2345 if (N2C && N2C->isNullValue())
2347 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X
2354 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2355 N1.getValueType() == VT && "Binary operator types must match!");
2356 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so
2357 // it's worth handling here.
2358 if (N2C && N2C->isNullValue())
2365 assert(VT.isInteger() && "This operator does not apply to FP types!");
2375 assert(N1.getValueType() == N2.getValueType() &&
2376 N1.getValueType() == VT && "Binary operator types must match!");
2378 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2379 assert(N1.getValueType() == VT &&
2380 N1.getValueType().isFloatingPoint() &&
2381 N2.getValueType().isFloatingPoint() &&
2382 "Invalid FCOPYSIGN!");
2389 assert(VT == N1.getValueType() &&
2390 "Shift operators return type must be the same as their first arg");
2391 assert(VT.isInteger() && N2.getValueType().isInteger() &&
2392 "Shifts only work on integers");
2394 // Always fold shifts of i1 values so the code generator doesn't need to
2395 // handle them. Since we know the size of the shift has to be less than the
2396 // size of the value, the shift/rotate count is guaranteed to be zero.
2400 case ISD::FP_ROUND_INREG: {
2401 MVT EVT = cast<VTSDNode>(N2)->getVT();
2402 assert(VT == N1.getValueType() && "Not an inreg round!");
2403 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
2404 "Cannot FP_ROUND_INREG integer types");
2405 assert(EVT.bitsLE(VT) && "Not rounding down!");
2406 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
2410 assert(VT.isFloatingPoint() &&
2411 N1.getValueType().isFloatingPoint() &&
2412 VT.bitsLE(N1.getValueType()) &&
2413 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
2414 if (N1.getValueType() == VT) return N1; // noop conversion.
2416 case ISD::AssertSext:
2417 case ISD::AssertZext: {
2418 MVT EVT = cast<VTSDNode>(N2)->getVT();
2419 assert(VT == N1.getValueType() && "Not an inreg extend!");
2420 assert(VT.isInteger() && EVT.isInteger() &&
2421 "Cannot *_EXTEND_INREG FP types");
2422 assert(EVT.bitsLE(VT) && "Not extending!");
2423 if (VT == EVT) return N1; // noop assertion.
2426 case ISD::SIGN_EXTEND_INREG: {
2427 MVT EVT = cast<VTSDNode>(N2)->getVT();
2428 assert(VT == N1.getValueType() && "Not an inreg extend!");
2429 assert(VT.isInteger() && EVT.isInteger() &&
2430 "Cannot *_EXTEND_INREG FP types");
2431 assert(EVT.bitsLE(VT) && "Not extending!");
2432 if (EVT == VT) return N1; // Not actually extending
2435 APInt Val = N1C->getAPIntValue();
2436 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits();
2437 Val <<= Val.getBitWidth()-FromBits;
2438 Val = Val.ashr(Val.getBitWidth()-FromBits);
2439 return getConstant(Val, VT);
2443 case ISD::EXTRACT_VECTOR_ELT:
2444 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
2445 if (N1.getOpcode() == ISD::UNDEF)
2446 return getNode(ISD::UNDEF, VT);
2448 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
2449 // expanding copies of large vectors from registers.
2451 N1.getOpcode() == ISD::CONCAT_VECTORS &&
2452 N1.getNumOperands() > 0) {
2454 N1.getOperand(0).getValueType().getVectorNumElements();
2455 return getNode(ISD::EXTRACT_VECTOR_ELT, VT,
2456 N1.getOperand(N2C->getZExtValue() / Factor),
2457 getConstant(N2C->getZExtValue() % Factor,
2458 N2.getValueType()));
2461 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
2462 // expanding large vector constants.
2463 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR)
2464 return N1.getOperand(N2C->getZExtValue());
2466 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
2467 // operations are lowered to scalars.
2468 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
2469 if (N1.getOperand(2) == N2)
2470 return N1.getOperand(1);
2472 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
2475 case ISD::EXTRACT_ELEMENT:
2476 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
2477 assert(!N1.getValueType().isVector() && !VT.isVector() &&
2478 (N1.getValueType().isInteger() == VT.isInteger()) &&
2479 "Wrong types for EXTRACT_ELEMENT!");
2481 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
2482 // 64-bit integers into 32-bit parts. Instead of building the extract of
2483 // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
2484 if (N1.getOpcode() == ISD::BUILD_PAIR)
2485 return N1.getOperand(N2C->getZExtValue());
2487 // EXTRACT_ELEMENT of a constant int is also very common.
2488 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2489 unsigned ElementSize = VT.getSizeInBits();
2490 unsigned Shift = ElementSize * N2C->getZExtValue();
2491 APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
2492 return getConstant(ShiftedVal.trunc(ElementSize), VT);
2495 case ISD::EXTRACT_SUBVECTOR:
2496 if (N1.getValueType() == VT) // Trivial extraction.
2503 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C);
2504 if (SV.getNode()) return SV;
2505 } else { // Cannonicalize constant to RHS if commutative
2506 if (isCommutativeBinOp(Opcode)) {
2507 std::swap(N1C, N2C);
2513 // Constant fold FP operations.
2514 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
2515 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
2517 if (!N2CFP && isCommutativeBinOp(Opcode)) {
2518 // Cannonicalize constant to RHS if commutative
2519 std::swap(N1CFP, N2CFP);
2521 } else if (N2CFP && VT != MVT::ppcf128) {
2522 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
2523 APFloat::opStatus s;
2526 s = V1.add(V2, APFloat::rmNearestTiesToEven);
2527 if (s != APFloat::opInvalidOp)
2528 return getConstantFP(V1, VT);
2531 s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
2532 if (s!=APFloat::opInvalidOp)
2533 return getConstantFP(V1, VT);
2536 s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
2537 if (s!=APFloat::opInvalidOp)
2538 return getConstantFP(V1, VT);
2541 s = V1.divide(V2, APFloat::rmNearestTiesToEven);
2542 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2543 return getConstantFP(V1, VT);
2546 s = V1.mod(V2, APFloat::rmNearestTiesToEven);
2547 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2548 return getConstantFP(V1, VT);
2550 case ISD::FCOPYSIGN:
2552 return getConstantFP(V1, VT);
2558 // Canonicalize an UNDEF to the RHS, even over a constant.
2559 if (N1.getOpcode() == ISD::UNDEF) {
2560 if (isCommutativeBinOp(Opcode)) {
2564 case ISD::FP_ROUND_INREG:
2565 case ISD::SIGN_EXTEND_INREG:
2571 return N1; // fold op(undef, arg2) -> undef
2579 return getConstant(0, VT); // fold op(undef, arg2) -> 0
2580 // For vectors, we can't easily build an all zero vector, just return
2587 // Fold a bunch of operators when the RHS is undef.
2588 if (N2.getOpcode() == ISD::UNDEF) {
2591 if (N1.getOpcode() == ISD::UNDEF)
2592 // Handle undef ^ undef -> 0 special case. This is a common
2594 return getConstant(0, VT);
2609 return N2; // fold op(arg1, undef) -> undef
2615 return getConstant(0, VT); // fold op(arg1, undef) -> 0
2616 // For vectors, we can't easily build an all zero vector, just return
2621 return getConstant(VT.getIntegerVTBitMask(), VT);
2622 // For vectors, we can't easily build an all one vector, just return
2630 // Memoize this node if possible.
2632 SDVTList VTs = getVTList(VT);
2633 if (VT != MVT::Flag) {
2634 SDValue Ops[] = { N1, N2 };
2635 FoldingSetNodeID ID;
2636 AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
2638 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2639 return SDValue(E, 0);
2640 N = NodeAllocator.Allocate<BinarySDNode>();
2641 new (N) BinarySDNode(Opcode, VTs, N1, N2);
2642 CSEMap.InsertNode(N, IP);
2644 N = NodeAllocator.Allocate<BinarySDNode>();
2645 new (N) BinarySDNode(Opcode, VTs, N1, N2);
2648 AllNodes.push_back(N);
2652 return SDValue(N, 0);
2655 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
2656 SDValue N1, SDValue N2, SDValue N3) {
2657 // Perform various simplifications.
2658 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2659 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2661 case ISD::CONCAT_VECTORS:
2662 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2663 // one big BUILD_VECTOR.
2664 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2665 N2.getOpcode() == ISD::BUILD_VECTOR &&
2666 N3.getOpcode() == ISD::BUILD_VECTOR) {
2667 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2668 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2669 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end());
2670 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
2674 // Use FoldSetCC to simplify SETCC's.
2675 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get());
2676 if (Simp.getNode()) return Simp;
2681 if (N1C->getZExtValue())
2682 return N2; // select true, X, Y -> X
2684 return N3; // select false, X, Y -> Y
2687 if (N2 == N3) return N2; // select C, X, X -> X
2691 if (N2C->getZExtValue()) // Unconditional branch
2692 return getNode(ISD::BR, MVT::Other, N1, N3);
2694 return N1; // Never-taken branch
2697 case ISD::VECTOR_SHUFFLE:
2698 assert(VT == N1.getValueType() && VT == N2.getValueType() &&
2699 VT.isVector() && N3.getValueType().isVector() &&
2700 N3.getOpcode() == ISD::BUILD_VECTOR &&
2701 VT.getVectorNumElements() == N3.getNumOperands() &&
2702 "Illegal VECTOR_SHUFFLE node!");
2704 case ISD::BIT_CONVERT:
2705 // Fold bit_convert nodes from a type to themselves.
2706 if (N1.getValueType() == VT)
2711 // Memoize node if it doesn't produce a flag.
2713 SDVTList VTs = getVTList(VT);
2714 if (VT != MVT::Flag) {
2715 SDValue Ops[] = { N1, N2, N3 };
2716 FoldingSetNodeID ID;
2717 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
2719 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2720 return SDValue(E, 0);
2721 N = NodeAllocator.Allocate<TernarySDNode>();
2722 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3);
2723 CSEMap.InsertNode(N, IP);
2725 N = NodeAllocator.Allocate<TernarySDNode>();
2726 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3);
2728 AllNodes.push_back(N);
2732 return SDValue(N, 0);
2735 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
2736 SDValue N1, SDValue N2, SDValue N3,
2738 SDValue Ops[] = { N1, N2, N3, N4 };
2739 return getNode(Opcode, VT, Ops, 4);
2742 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
2743 SDValue N1, SDValue N2, SDValue N3,
2744 SDValue N4, SDValue N5) {
2745 SDValue Ops[] = { N1, N2, N3, N4, N5 };
2746 return getNode(Opcode, VT, Ops, 5);
2749 /// getMemsetValue - Vectorized representation of the memset value
2751 static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) {
2752 unsigned NumBits = VT.isVector() ?
2753 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
2754 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2755 APInt Val = APInt(NumBits, C->getZExtValue() & 255);
2757 for (unsigned i = NumBits; i > 8; i >>= 1) {
2758 Val = (Val << Shift) | Val;
2762 return DAG.getConstant(Val, VT);
2763 return DAG.getConstantFP(APFloat(Val), VT);
2766 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2768 for (unsigned i = NumBits; i > 8; i >>= 1) {
2769 Value = DAG.getNode(ISD::OR, VT,
2770 DAG.getNode(ISD::SHL, VT, Value,
2771 DAG.getConstant(Shift, MVT::i8)), Value);
2778 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2779 /// used when a memcpy is turned into a memset when the source is a constant
2781 static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG,
2782 const TargetLowering &TLI,
2783 std::string &Str, unsigned Offset) {
2784 // Handle vector with all elements zero.
2787 return DAG.getConstant(0, VT);
2788 unsigned NumElts = VT.getVectorNumElements();
2789 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
2790 return DAG.getNode(ISD::BIT_CONVERT, VT,
2791 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
2794 assert(!VT.isVector() && "Can't handle vector type here!");
2795 unsigned NumBits = VT.getSizeInBits();
2796 unsigned MSB = NumBits / 8;
2798 if (TLI.isLittleEndian())
2799 Offset = Offset + MSB - 1;
2800 for (unsigned i = 0; i != MSB; ++i) {
2801 Val = (Val << 8) | (unsigned char)Str[Offset];
2802 Offset += TLI.isLittleEndian() ? -1 : 1;
2804 return DAG.getConstant(Val, VT);
2807 /// getMemBasePlusOffset - Returns base and offset node for the
2809 static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
2810 SelectionDAG &DAG) {
2811 MVT VT = Base.getValueType();
2812 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2815 /// isMemSrcFromString - Returns true if memcpy source is a string constant.
2817 static bool isMemSrcFromString(SDValue Src, std::string &Str) {
2818 unsigned SrcDelta = 0;
2819 GlobalAddressSDNode *G = NULL;
2820 if (Src.getOpcode() == ISD::GlobalAddress)
2821 G = cast<GlobalAddressSDNode>(Src);
2822 else if (Src.getOpcode() == ISD::ADD &&
2823 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2824 Src.getOperand(1).getOpcode() == ISD::Constant) {
2825 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
2826 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
2831 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2832 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false))
2838 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2839 /// to replace the memset / memcpy is below the threshold. It also returns the
2840 /// types of the sequence of memory ops to perform memset / memcpy.
2842 bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
2843 SDValue Dst, SDValue Src,
2844 unsigned Limit, uint64_t Size, unsigned &Align,
2845 std::string &Str, bool &isSrcStr,
2847 const TargetLowering &TLI) {
2848 isSrcStr = isMemSrcFromString(Src, Str);
2849 bool isSrcConst = isa<ConstantSDNode>(Src);
2850 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
2851 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr);
2852 if (VT != MVT::iAny) {
2853 unsigned NewAlign = (unsigned)
2854 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
2855 // If source is a string constant, this will require an unaligned load.
2856 if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
2857 if (Dst.getOpcode() != ISD::FrameIndex) {
2858 // Can't change destination alignment. It requires a unaligned store.
2862 int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
2863 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2864 if (MFI->isFixedObjectIndex(FI)) {
2865 // Can't change destination alignment. It requires a unaligned store.
2869 // Give the stack frame object a larger alignment if needed.
2870 if (MFI->getObjectAlignment(FI) < NewAlign)
2871 MFI->setObjectAlignment(FI, NewAlign);
2878 if (VT == MVT::iAny) {
2882 switch (Align & 7) {
2883 case 0: VT = MVT::i64; break;
2884 case 4: VT = MVT::i32; break;
2885 case 2: VT = MVT::i16; break;
2886 default: VT = MVT::i8; break;
2891 while (!TLI.isTypeLegal(LVT))
2892 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
2893 assert(LVT.isInteger());
2899 unsigned NumMemOps = 0;
2901 unsigned VTSize = VT.getSizeInBits() / 8;
2902 while (VTSize > Size) {
2903 // For now, only use non-vector load / store's for the left-over pieces.
2904 if (VT.isVector()) {
2906 while (!TLI.isTypeLegal(VT))
2907 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
2908 VTSize = VT.getSizeInBits() / 8;
2910 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
2915 if (++NumMemOps > Limit)
2917 MemOps.push_back(VT);
2924 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG,
2925 SDValue Chain, SDValue Dst,
2926 SDValue Src, uint64_t Size,
2927 unsigned Align, bool AlwaysInline,
2928 const Value *DstSV, uint64_t DstSVOff,
2929 const Value *SrcSV, uint64_t SrcSVOff){
2930 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2932 // Expand memcpy to a series of load and store ops if the size operand falls
2933 // below a certain threshold.
2934 std::vector<MVT> MemOps;
2935 uint64_t Limit = -1ULL;
2937 Limit = TLI.getMaxStoresPerMemcpy();
2938 unsigned DstAlign = Align; // Destination alignment can change.
2941 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
2942 Str, CopyFromStr, DAG, TLI))
2946 bool isZeroStr = CopyFromStr && Str.empty();
2947 SmallVector<SDValue, 8> OutChains;
2948 unsigned NumMemOps = MemOps.size();
2949 uint64_t SrcOff = 0, DstOff = 0;
2950 for (unsigned i = 0; i < NumMemOps; i++) {
2952 unsigned VTSize = VT.getSizeInBits() / 8;
2953 SDValue Value, Store;
2955 if (CopyFromStr && (isZeroStr || !VT.isVector())) {
2956 // It's unlikely a store of a vector immediate can be done in a single
2957 // instruction. It would require a load from a constantpool first.
2958 // We also handle store a vector with all zero's.
2959 // FIXME: Handle other cases where store of vector immediate is done in
2960 // a single instruction.
2961 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2962 Store = DAG.getStore(Chain, Value,
2963 getMemBasePlusOffset(Dst, DstOff, DAG),
2964 DstSV, DstSVOff + DstOff, false, DstAlign);
2966 Value = DAG.getLoad(VT, Chain,
2967 getMemBasePlusOffset(Src, SrcOff, DAG),
2968 SrcSV, SrcSVOff + SrcOff, false, Align);
2969 Store = DAG.getStore(Chain, Value,
2970 getMemBasePlusOffset(Dst, DstOff, DAG),
2971 DstSV, DstSVOff + DstOff, false, DstAlign);
2973 OutChains.push_back(Store);
2978 return DAG.getNode(ISD::TokenFactor, MVT::Other,
2979 &OutChains[0], OutChains.size());
2982 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG,
2983 SDValue Chain, SDValue Dst,
2984 SDValue Src, uint64_t Size,
2985 unsigned Align, bool AlwaysInline,
2986 const Value *DstSV, uint64_t DstSVOff,
2987 const Value *SrcSV, uint64_t SrcSVOff){
2988 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2990 // Expand memmove to a series of load and store ops if the size operand falls
2991 // below a certain threshold.
2992 std::vector<MVT> MemOps;
2993 uint64_t Limit = -1ULL;
2995 Limit = TLI.getMaxStoresPerMemmove();
2996 unsigned DstAlign = Align; // Destination alignment can change.
2999 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3000 Str, CopyFromStr, DAG, TLI))
3003 uint64_t SrcOff = 0, DstOff = 0;
3005 SmallVector<SDValue, 8> LoadValues;
3006 SmallVector<SDValue, 8> LoadChains;
3007 SmallVector<SDValue, 8> OutChains;
3008 unsigned NumMemOps = MemOps.size();
3009 for (unsigned i = 0; i < NumMemOps; i++) {
3011 unsigned VTSize = VT.getSizeInBits() / 8;
3012 SDValue Value, Store;
3014 Value = DAG.getLoad(VT, Chain,
3015 getMemBasePlusOffset(Src, SrcOff, DAG),
3016 SrcSV, SrcSVOff + SrcOff, false, Align);
3017 LoadValues.push_back(Value);
3018 LoadChains.push_back(Value.getValue(1));
3021 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3022 &LoadChains[0], LoadChains.size());
3024 for (unsigned i = 0; i < NumMemOps; i++) {
3026 unsigned VTSize = VT.getSizeInBits() / 8;
3027 SDValue Value, Store;
3029 Store = DAG.getStore(Chain, LoadValues[i],
3030 getMemBasePlusOffset(Dst, DstOff, DAG),
3031 DstSV, DstSVOff + DstOff, false, DstAlign);
3032 OutChains.push_back(Store);
3036 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3037 &OutChains[0], OutChains.size());
3040 static SDValue getMemsetStores(SelectionDAG &DAG,
3041 SDValue Chain, SDValue Dst,
3042 SDValue Src, uint64_t Size,
3044 const Value *DstSV, uint64_t DstSVOff) {
3045 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3047 // Expand memset to a series of load/store ops if the size operand
3048 // falls below a certain threshold.
3049 std::vector<MVT> MemOps;
3052 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
3053 Size, Align, Str, CopyFromStr, DAG, TLI))
3056 SmallVector<SDValue, 8> OutChains;
3057 uint64_t DstOff = 0;
3059 unsigned NumMemOps = MemOps.size();
3060 for (unsigned i = 0; i < NumMemOps; i++) {
3062 unsigned VTSize = VT.getSizeInBits() / 8;
3063 SDValue Value = getMemsetValue(Src, VT, DAG);
3064 SDValue Store = DAG.getStore(Chain, Value,
3065 getMemBasePlusOffset(Dst, DstOff, DAG),
3066 DstSV, DstSVOff + DstOff);
3067 OutChains.push_back(Store);
3071 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3072 &OutChains[0], OutChains.size());
3075 SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst,
3076 SDValue Src, SDValue Size,
3077 unsigned Align, bool AlwaysInline,
3078 const Value *DstSV, uint64_t DstSVOff,
3079 const Value *SrcSV, uint64_t SrcSVOff) {
3081 // Check to see if we should lower the memcpy to loads and stores first.
3082 // For cases within the target-specified limits, this is the best choice.
3083 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3085 // Memcpy with size zero? Just return the original chain.
3086 if (ConstantSize->isNullValue())
3090 getMemcpyLoadsAndStores(*this, Chain, Dst, Src,
3091 ConstantSize->getZExtValue(),
3092 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3093 if (Result.getNode())
3097 // Then check to see if we should lower the memcpy with target-specific
3098 // code. If the target chooses to do this, this is the next best.
3100 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
3102 DstSV, DstSVOff, SrcSV, SrcSVOff);
3103 if (Result.getNode())
3106 // If we really need inline code and the target declined to provide it,
3107 // use a (potentially long) sequence of loads and stores.
3109 assert(ConstantSize && "AlwaysInline requires a constant size!");
3110 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src,
3111 ConstantSize->getZExtValue(), Align, true,
3112 DstSV, DstSVOff, SrcSV, SrcSVOff);
3115 // Emit a library call.
3116 TargetLowering::ArgListTy Args;
3117 TargetLowering::ArgListEntry Entry;
3118 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3119 Entry.Node = Dst; Args.push_back(Entry);
3120 Entry.Node = Src; Args.push_back(Entry);
3121 Entry.Node = Size; Args.push_back(Entry);
3122 std::pair<SDValue,SDValue> CallResult =
3123 TLI.LowerCallTo(Chain, Type::VoidTy,
3124 false, false, false, false, CallingConv::C, false,
3125 getExternalSymbol("memcpy", TLI.getPointerTy()),
3127 return CallResult.second;
3130 SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst,
3131 SDValue Src, SDValue Size,
3133 const Value *DstSV, uint64_t DstSVOff,
3134 const Value *SrcSV, uint64_t SrcSVOff) {
3136 // Check to see if we should lower the memmove to loads and stores first.
3137 // For cases within the target-specified limits, this is the best choice.
3138 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3140 // Memmove with size zero? Just return the original chain.
3141 if (ConstantSize->isNullValue())
3145 getMemmoveLoadsAndStores(*this, Chain, Dst, Src,
3146 ConstantSize->getZExtValue(),
3147 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3148 if (Result.getNode())
3152 // Then check to see if we should lower the memmove with target-specific
3153 // code. If the target chooses to do this, this is the next best.
3155 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
3156 DstSV, DstSVOff, SrcSV, SrcSVOff);
3157 if (Result.getNode())
3160 // Emit a library call.
3161 TargetLowering::ArgListTy Args;
3162 TargetLowering::ArgListEntry Entry;
3163 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3164 Entry.Node = Dst; Args.push_back(Entry);
3165 Entry.Node = Src; Args.push_back(Entry);
3166 Entry.Node = Size; Args.push_back(Entry);
3167 std::pair<SDValue,SDValue> CallResult =
3168 TLI.LowerCallTo(Chain, Type::VoidTy,
3169 false, false, false, false, CallingConv::C, false,
3170 getExternalSymbol("memmove", TLI.getPointerTy()),
3172 return CallResult.second;
3175 SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst,
3176 SDValue Src, SDValue Size,
3178 const Value *DstSV, uint64_t DstSVOff) {
3180 // Check to see if we should lower the memset to stores first.
3181 // For cases within the target-specified limits, this is the best choice.
3182 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3184 // Memset with size zero? Just return the original chain.
3185 if (ConstantSize->isNullValue())
3189 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(),
3190 Align, DstSV, DstSVOff);
3191 if (Result.getNode())
3195 // Then check to see if we should lower the memset with target-specific
3196 // code. If the target chooses to do this, this is the next best.
3198 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
3200 if (Result.getNode())
3203 // Emit a library call.
3204 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
3205 TargetLowering::ArgListTy Args;
3206 TargetLowering::ArgListEntry Entry;
3207 Entry.Node = Dst; Entry.Ty = IntPtrTy;
3208 Args.push_back(Entry);
3209 // Extend or truncate the argument to be an i32 value for the call.
3210 if (Src.getValueType().bitsGT(MVT::i32))
3211 Src = getNode(ISD::TRUNCATE, MVT::i32, Src);
3213 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src);
3214 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
3215 Args.push_back(Entry);
3216 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
3217 Args.push_back(Entry);
3218 std::pair<SDValue,SDValue> CallResult =
3219 TLI.LowerCallTo(Chain, Type::VoidTy,
3220 false, false, false, false, CallingConv::C, false,
3221 getExternalSymbol("memset", TLI.getPointerTy()),
3223 return CallResult.second;
3226 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain,
3227 SDValue Ptr, SDValue Cmp,
3228 SDValue Swp, const Value* PtrVal,
3229 unsigned Alignment) {
3230 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 ||
3231 Opcode == ISD::ATOMIC_CMP_SWAP_16 ||
3232 Opcode == ISD::ATOMIC_CMP_SWAP_32 ||
3233 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op");
3234 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
3236 MVT VT = Cmp.getValueType();
3238 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3239 Alignment = getMVTAlignment(VT);
3241 SDVTList VTs = getVTList(VT, MVT::Other);
3242 FoldingSetNodeID ID;
3243 SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
3244 AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
3246 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3247 return SDValue(E, 0);
3248 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3249 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
3250 CSEMap.InsertNode(N, IP);
3251 AllNodes.push_back(N);
3252 return SDValue(N, 0);
3255 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain,
3256 SDValue Ptr, SDValue Val,
3257 const Value* PtrVal,
3258 unsigned Alignment) {
3259 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 ||
3260 Opcode == ISD::ATOMIC_LOAD_SUB_8 ||
3261 Opcode == ISD::ATOMIC_LOAD_AND_8 ||
3262 Opcode == ISD::ATOMIC_LOAD_OR_8 ||
3263 Opcode == ISD::ATOMIC_LOAD_XOR_8 ||
3264 Opcode == ISD::ATOMIC_LOAD_NAND_8 ||
3265 Opcode == ISD::ATOMIC_LOAD_MIN_8 ||
3266 Opcode == ISD::ATOMIC_LOAD_MAX_8 ||
3267 Opcode == ISD::ATOMIC_LOAD_UMIN_8 ||
3268 Opcode == ISD::ATOMIC_LOAD_UMAX_8 ||
3269 Opcode == ISD::ATOMIC_SWAP_8 ||
3270 Opcode == ISD::ATOMIC_LOAD_ADD_16 ||
3271 Opcode == ISD::ATOMIC_LOAD_SUB_16 ||
3272 Opcode == ISD::ATOMIC_LOAD_AND_16 ||
3273 Opcode == ISD::ATOMIC_LOAD_OR_16 ||
3274 Opcode == ISD::ATOMIC_LOAD_XOR_16 ||
3275 Opcode == ISD::ATOMIC_LOAD_NAND_16 ||
3276 Opcode == ISD::ATOMIC_LOAD_MIN_16 ||
3277 Opcode == ISD::ATOMIC_LOAD_MAX_16 ||
3278 Opcode == ISD::ATOMIC_LOAD_UMIN_16 ||
3279 Opcode == ISD::ATOMIC_LOAD_UMAX_16 ||
3280 Opcode == ISD::ATOMIC_SWAP_16 ||
3281 Opcode == ISD::ATOMIC_LOAD_ADD_32 ||
3282 Opcode == ISD::ATOMIC_LOAD_SUB_32 ||
3283 Opcode == ISD::ATOMIC_LOAD_AND_32 ||
3284 Opcode == ISD::ATOMIC_LOAD_OR_32 ||
3285 Opcode == ISD::ATOMIC_LOAD_XOR_32 ||
3286 Opcode == ISD::ATOMIC_LOAD_NAND_32 ||
3287 Opcode == ISD::ATOMIC_LOAD_MIN_32 ||
3288 Opcode == ISD::ATOMIC_LOAD_MAX_32 ||
3289 Opcode == ISD::ATOMIC_LOAD_UMIN_32 ||
3290 Opcode == ISD::ATOMIC_LOAD_UMAX_32 ||
3291 Opcode == ISD::ATOMIC_SWAP_32 ||
3292 Opcode == ISD::ATOMIC_LOAD_ADD_64 ||
3293 Opcode == ISD::ATOMIC_LOAD_SUB_64 ||
3294 Opcode == ISD::ATOMIC_LOAD_AND_64 ||
3295 Opcode == ISD::ATOMIC_LOAD_OR_64 ||
3296 Opcode == ISD::ATOMIC_LOAD_XOR_64 ||
3297 Opcode == ISD::ATOMIC_LOAD_NAND_64 ||
3298 Opcode == ISD::ATOMIC_LOAD_MIN_64 ||
3299 Opcode == ISD::ATOMIC_LOAD_MAX_64 ||
3300 Opcode == ISD::ATOMIC_LOAD_UMIN_64 ||
3301 Opcode == ISD::ATOMIC_LOAD_UMAX_64 ||
3302 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op");
3304 MVT VT = Val.getValueType();
3306 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3307 Alignment = getMVTAlignment(VT);
3309 SDVTList VTs = getVTList(VT, MVT::Other);
3310 FoldingSetNodeID ID;
3311 SDValue Ops[] = {Chain, Ptr, Val};
3312 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
3314 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3315 return SDValue(E, 0);
3316 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3317 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment);
3318 CSEMap.InsertNode(N, IP);
3319 AllNodes.push_back(N);
3320 return SDValue(N, 0);
3323 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
3324 /// Allowed to return something different (and simpler) if Simplify is true.
3325 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
3327 if (Simplify && NumOps == 1)
3330 SmallVector<MVT, 4> VTs;
3331 VTs.reserve(NumOps);
3332 for (unsigned i = 0; i < NumOps; ++i)
3333 VTs.push_back(Ops[i].getValueType());
3334 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps);
3338 SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall,
3339 bool IsInreg, SDVTList VTs,
3340 const SDValue *Operands, unsigned NumOperands) {
3341 // Do not include isTailCall in the folding set profile.
3342 FoldingSetNodeID ID;
3343 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
3344 ID.AddInteger(CallingConv);
3345 ID.AddInteger(IsVarArgs);
3347 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
3348 // Instead of including isTailCall in the folding set, we just
3349 // set the flag of the existing node.
3351 cast<CallSDNode>(E)->setNotTailCall();
3352 return SDValue(E, 0);
3354 SDNode *N = NodeAllocator.Allocate<CallSDNode>();
3355 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg,
3356 VTs, Operands, NumOperands);
3357 CSEMap.InsertNode(N, IP);
3358 AllNodes.push_back(N);
3359 return SDValue(N, 0);
3363 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
3364 MVT VT, SDValue Chain,
3365 SDValue Ptr, SDValue Offset,
3366 const Value *SV, int SVOffset, MVT EVT,
3367 bool isVolatile, unsigned Alignment) {
3368 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3369 Alignment = getMVTAlignment(VT);
3372 ExtType = ISD::NON_EXTLOAD;
3373 } else if (ExtType == ISD::NON_EXTLOAD) {
3374 assert(VT == EVT && "Non-extending load from different memory type!");
3378 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
3379 "Invalid vector extload!");
3381 assert(EVT.bitsLT(VT) &&
3382 "Should only be an extending load, not truncating!");
3383 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
3384 "Cannot sign/zero extend a FP/Vector load!");
3385 assert(VT.isInteger() == EVT.isInteger() &&
3386 "Cannot convert from FP to Int or Int -> FP!");
3389 bool Indexed = AM != ISD::UNINDEXED;
3390 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
3391 "Unindexed load with an offset!");
3393 SDVTList VTs = Indexed ?
3394 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
3395 SDValue Ops[] = { Chain, Ptr, Offset };
3396 FoldingSetNodeID ID;
3397 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
3399 ID.AddInteger(ExtType);
3400 ID.AddInteger(EVT.getRawBits());
3401 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
3403 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3404 return SDValue(E, 0);
3405 SDNode *N = NodeAllocator.Allocate<LoadSDNode>();
3406 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset,
3407 Alignment, isVolatile);
3408 CSEMap.InsertNode(N, IP);
3409 AllNodes.push_back(N);
3410 return SDValue(N, 0);
3413 SDValue SelectionDAG::getLoad(MVT VT,
3414 SDValue Chain, SDValue Ptr,
3415 const Value *SV, int SVOffset,
3416 bool isVolatile, unsigned Alignment) {
3417 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
3418 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
3419 SV, SVOffset, VT, isVolatile, Alignment);
3422 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
3423 SDValue Chain, SDValue Ptr,
3425 int SVOffset, MVT EVT,
3426 bool isVolatile, unsigned Alignment) {
3427 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
3428 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef,
3429 SV, SVOffset, EVT, isVolatile, Alignment);
3433 SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
3434 SDValue Offset, ISD::MemIndexedMode AM) {
3435 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
3436 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
3437 "Load is already a indexed load!");
3438 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(),
3439 LD->getChain(), Base, Offset, LD->getSrcValue(),
3440 LD->getSrcValueOffset(), LD->getMemoryVT(),
3441 LD->isVolatile(), LD->getAlignment());
3444 SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val,
3445 SDValue Ptr, const Value *SV, int SVOffset,
3446 bool isVolatile, unsigned Alignment) {
3447 MVT VT = Val.getValueType();
3449 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3450 Alignment = getMVTAlignment(VT);
3452 SDVTList VTs = getVTList(MVT::Other);
3453 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
3454 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3455 FoldingSetNodeID ID;
3456 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3457 ID.AddInteger(ISD::UNINDEXED);
3458 ID.AddInteger(false);
3459 ID.AddInteger(VT.getRawBits());
3460 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
3462 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3463 return SDValue(E, 0);
3464 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3465 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false,
3466 VT, SV, SVOffset, Alignment, isVolatile);
3467 CSEMap.InsertNode(N, IP);
3468 AllNodes.push_back(N);
3469 return SDValue(N, 0);
3472 SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
3473 SDValue Ptr, const Value *SV,
3474 int SVOffset, MVT SVT,
3475 bool isVolatile, unsigned Alignment) {
3476 MVT VT = Val.getValueType();
3479 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
3481 assert(VT.bitsGT(SVT) && "Not a truncation?");
3482 assert(VT.isInteger() == SVT.isInteger() &&
3483 "Can't do FP-INT conversion!");
3485 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3486 Alignment = getMVTAlignment(VT);
3488 SDVTList VTs = getVTList(MVT::Other);
3489 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
3490 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3491 FoldingSetNodeID ID;
3492 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3493 ID.AddInteger(ISD::UNINDEXED);
3495 ID.AddInteger(SVT.getRawBits());
3496 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
3498 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3499 return SDValue(E, 0);
3500 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3501 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true,
3502 SVT, SV, SVOffset, Alignment, isVolatile);
3503 CSEMap.InsertNode(N, IP);
3504 AllNodes.push_back(N);
3505 return SDValue(N, 0);
3509 SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
3510 SDValue Offset, ISD::MemIndexedMode AM) {
3511 StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
3512 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
3513 "Store is already a indexed store!");
3514 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
3515 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
3516 FoldingSetNodeID ID;
3517 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3519 ID.AddInteger(ST->isTruncatingStore());
3520 ID.AddInteger(ST->getMemoryVT().getRawBits());
3521 ID.AddInteger(ST->getRawFlags());
3523 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3524 return SDValue(E, 0);
3525 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3526 new (N) StoreSDNode(Ops, VTs, AM,
3527 ST->isTruncatingStore(), ST->getMemoryVT(),
3528 ST->getSrcValue(), ST->getSrcValueOffset(),
3529 ST->getAlignment(), ST->isVolatile());
3530 CSEMap.InsertNode(N, IP);
3531 AllNodes.push_back(N);
3532 return SDValue(N, 0);
3535 SDValue SelectionDAG::getVAArg(MVT VT,
3536 SDValue Chain, SDValue Ptr,
3538 SDValue Ops[] = { Chain, Ptr, SV };
3539 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3);
3542 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
3543 const SDUse *Ops, unsigned NumOps) {
3545 case 0: return getNode(Opcode, VT);
3546 case 1: return getNode(Opcode, VT, Ops[0]);
3547 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]);
3548 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]);
3552 // Copy from an SDUse array into an SDValue array for use with
3553 // the regular getNode logic.
3554 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
3555 return getNode(Opcode, VT, &NewOps[0], NumOps);
3558 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
3559 const SDValue *Ops, unsigned NumOps) {
3561 case 0: return getNode(Opcode, VT);
3562 case 1: return getNode(Opcode, VT, Ops[0]);
3563 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]);
3564 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]);
3570 case ISD::SELECT_CC: {
3571 assert(NumOps == 5 && "SELECT_CC takes 5 operands!");
3572 assert(Ops[0].getValueType() == Ops[1].getValueType() &&
3573 "LHS and RHS of condition must have same type!");
3574 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3575 "True and False arms of SelectCC must have same type!");
3576 assert(Ops[2].getValueType() == VT &&
3577 "select_cc node must be of same type as true and false value!");
3581 assert(NumOps == 5 && "BR_CC takes 5 operands!");
3582 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3583 "LHS/RHS of comparison should match types!");
3590 SDVTList VTs = getVTList(VT);
3591 if (VT != MVT::Flag) {
3592 FoldingSetNodeID ID;
3593 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
3595 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3596 return SDValue(E, 0);
3597 N = NodeAllocator.Allocate<SDNode>();
3598 new (N) SDNode(Opcode, VTs, Ops, NumOps);
3599 CSEMap.InsertNode(N, IP);
3601 N = NodeAllocator.Allocate<SDNode>();
3602 new (N) SDNode(Opcode, VTs, Ops, NumOps);
3604 AllNodes.push_back(N);
3608 return SDValue(N, 0);
3611 SDValue SelectionDAG::getNode(unsigned Opcode,
3612 const std::vector<MVT> &ResultTys,
3613 const SDValue *Ops, unsigned NumOps) {
3614 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(),
3618 SDValue SelectionDAG::getNode(unsigned Opcode,
3619 const MVT *VTs, unsigned NumVTs,
3620 const SDValue *Ops, unsigned NumOps) {
3622 return getNode(Opcode, VTs[0], Ops, NumOps);
3623 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps);
3626 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
3627 const SDValue *Ops, unsigned NumOps) {
3628 if (VTList.NumVTs == 1)
3629 return getNode(Opcode, VTList.VTs[0], Ops, NumOps);
3632 // FIXME: figure out how to safely handle things like
3633 // int foo(int x) { return 1 << (x & 255); }
3634 // int bar() { return foo(256); }
3636 case ISD::SRA_PARTS:
3637 case ISD::SRL_PARTS:
3638 case ISD::SHL_PARTS:
3639 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3640 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
3641 return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
3642 else if (N3.getOpcode() == ISD::AND)
3643 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
3644 // If the and is only masking out bits that cannot effect the shift,
3645 // eliminate the and.
3646 unsigned NumBits = VT.getSizeInBits()*2;
3647 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
3648 return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
3654 // Memoize the node unless it returns a flag.
3656 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3657 FoldingSetNodeID ID;
3658 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3660 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3661 return SDValue(E, 0);
3663 N = NodeAllocator.Allocate<UnarySDNode>();
3664 new (N) UnarySDNode(Opcode, VTList, Ops[0]);
3665 } else if (NumOps == 2) {
3666 N = NodeAllocator.Allocate<BinarySDNode>();
3667 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]);
3668 } else if (NumOps == 3) {
3669 N = NodeAllocator.Allocate<TernarySDNode>();
3670 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]);
3672 N = NodeAllocator.Allocate<SDNode>();
3673 new (N) SDNode(Opcode, VTList, Ops, NumOps);
3675 CSEMap.InsertNode(N, IP);
3678 N = NodeAllocator.Allocate<UnarySDNode>();
3679 new (N) UnarySDNode(Opcode, VTList, Ops[0]);
3680 } else if (NumOps == 2) {
3681 N = NodeAllocator.Allocate<BinarySDNode>();
3682 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]);
3683 } else if (NumOps == 3) {
3684 N = NodeAllocator.Allocate<TernarySDNode>();
3685 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]);
3687 N = NodeAllocator.Allocate<SDNode>();
3688 new (N) SDNode(Opcode, VTList, Ops, NumOps);
3691 AllNodes.push_back(N);
3695 return SDValue(N, 0);
3698 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) {
3699 return getNode(Opcode, VTList, 0, 0);
3702 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
3704 SDValue Ops[] = { N1 };
3705 return getNode(Opcode, VTList, Ops, 1);
3708 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
3709 SDValue N1, SDValue N2) {
3710 SDValue Ops[] = { N1, N2 };
3711 return getNode(Opcode, VTList, Ops, 2);
3714 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
3715 SDValue N1, SDValue N2, SDValue N3) {
3716 SDValue Ops[] = { N1, N2, N3 };
3717 return getNode(Opcode, VTList, Ops, 3);
3720 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
3721 SDValue N1, SDValue N2, SDValue N3,
3723 SDValue Ops[] = { N1, N2, N3, N4 };
3724 return getNode(Opcode, VTList, Ops, 4);
3727 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
3728 SDValue N1, SDValue N2, SDValue N3,
3729 SDValue N4, SDValue N5) {
3730 SDValue Ops[] = { N1, N2, N3, N4, N5 };
3731 return getNode(Opcode, VTList, Ops, 5);
3734 SDVTList SelectionDAG::getVTList(MVT VT) {
3735 return makeVTList(SDNode::getValueTypeList(VT), 1);
3738 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) {
3739 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3740 E = VTList.rend(); I != E; ++I)
3741 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
3744 MVT *Array = Allocator.Allocate<MVT>(2);
3747 SDVTList Result = makeVTList(Array, 2);
3748 VTList.push_back(Result);
3752 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) {
3753 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3754 E = VTList.rend(); I != E; ++I)
3755 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
3759 MVT *Array = Allocator.Allocate<MVT>(3);
3763 SDVTList Result = makeVTList(Array, 3);
3764 VTList.push_back(Result);
3768 SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
3770 case 0: assert(0 && "Cannot have nodes without results!");
3771 case 1: return getVTList(VTs[0]);
3772 case 2: return getVTList(VTs[0], VTs[1]);
3773 case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
3777 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3778 E = VTList.rend(); I != E; ++I) {
3779 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1])
3782 bool NoMatch = false;
3783 for (unsigned i = 2; i != NumVTs; ++i)
3784 if (VTs[i] != I->VTs[i]) {
3792 MVT *Array = Allocator.Allocate<MVT>(NumVTs);
3793 std::copy(VTs, VTs+NumVTs, Array);
3794 SDVTList Result = makeVTList(Array, NumVTs);
3795 VTList.push_back(Result);
3800 /// UpdateNodeOperands - *Mutate* the specified node in-place to have the
3801 /// specified operands. If the resultant node already exists in the DAG,
3802 /// this does not modify the specified node, instead it returns the node that
3803 /// already exists. If the resultant node does not exist in the DAG, the
3804 /// input node is returned. As a degenerate case, if you specify the same
3805 /// input operands as the node already has, the input node is returned.
3806 SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
3807 SDNode *N = InN.getNode();
3808 assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
3810 // Check to see if there is no change.
3811 if (Op == N->getOperand(0)) return InN;
3813 // See if the modified node already exists.
3814 void *InsertPos = 0;
3815 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
3816 return SDValue(Existing, InN.getResNo());
3818 // Nope it doesn't. Remove the node from its current place in the maps.
3820 if (!RemoveNodeFromCSEMaps(N))
3823 // Now we update the operands.
3824 N->OperandList[0].getVal()->removeUser(0, N);
3825 N->OperandList[0] = Op;
3826 N->OperandList[0].setUser(N);
3827 Op.getNode()->addUser(0, N);
3829 // If this gets put into a CSE map, add it.
3830 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
3834 SDValue SelectionDAG::
3835 UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
3836 SDNode *N = InN.getNode();
3837 assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
3839 // Check to see if there is no change.
3840 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
3841 return InN; // No operands changed, just return the input node.
3843 // See if the modified node already exists.
3844 void *InsertPos = 0;
3845 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
3846 return SDValue(Existing, InN.getResNo());
3848 // Nope it doesn't. Remove the node from its current place in the maps.
3850 if (!RemoveNodeFromCSEMaps(N))
3853 // Now we update the operands.
3854 if (N->OperandList[0] != Op1) {
3855 N->OperandList[0].getVal()->removeUser(0, N);
3856 N->OperandList[0] = Op1;
3857 N->OperandList[0].setUser(N);
3858 Op1.getNode()->addUser(0, N);
3860 if (N->OperandList[1] != Op2) {
3861 N->OperandList[1].getVal()->removeUser(1, N);
3862 N->OperandList[1] = Op2;
3863 N->OperandList[1].setUser(N);
3864 Op2.getNode()->addUser(1, N);
3867 // If this gets put into a CSE map, add it.
3868 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
3872 SDValue SelectionDAG::
3873 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) {
3874 SDValue Ops[] = { Op1, Op2, Op3 };
3875 return UpdateNodeOperands(N, Ops, 3);
3878 SDValue SelectionDAG::
3879 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
3880 SDValue Op3, SDValue Op4) {
3881 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
3882 return UpdateNodeOperands(N, Ops, 4);
3885 SDValue SelectionDAG::
3886 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
3887 SDValue Op3, SDValue Op4, SDValue Op5) {
3888 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
3889 return UpdateNodeOperands(N, Ops, 5);
3892 SDValue SelectionDAG::
3893 UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
3894 SDNode *N = InN.getNode();
3895 assert(N->getNumOperands() == NumOps &&
3896 "Update with wrong number of operands");
3898 // Check to see if there is no change.
3899 bool AnyChange = false;
3900 for (unsigned i = 0; i != NumOps; ++i) {
3901 if (Ops[i] != N->getOperand(i)) {
3907 // No operands changed, just return the input node.
3908 if (!AnyChange) return InN;
3910 // See if the modified node already exists.
3911 void *InsertPos = 0;
3912 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
3913 return SDValue(Existing, InN.getResNo());
3915 // Nope it doesn't. Remove the node from its current place in the maps.
3917 if (!RemoveNodeFromCSEMaps(N))
3920 // Now we update the operands.
3921 for (unsigned i = 0; i != NumOps; ++i) {
3922 if (N->OperandList[i] != Ops[i]) {
3923 N->OperandList[i].getVal()->removeUser(i, N);
3924 N->OperandList[i] = Ops[i];
3925 N->OperandList[i].setUser(N);
3926 Ops[i].getNode()->addUser(i, N);
3930 // If this gets put into a CSE map, add it.
3931 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
3935 /// DropOperands - Release the operands and set this node to have
3937 void SDNode::DropOperands() {
3938 // Unlike the code in MorphNodeTo that does this, we don't need to
3939 // watch for dead nodes here.
3940 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I)
3941 I->getVal()->removeUser(std::distance(op_begin(), I), this);
3946 /// SelectNodeTo - These are wrappers around MorphNodeTo that accept a
3949 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3951 SDVTList VTs = getVTList(VT);
3952 return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
3955 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3956 MVT VT, SDValue Op1) {
3957 SDVTList VTs = getVTList(VT);
3958 SDValue Ops[] = { Op1 };
3959 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
3962 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3963 MVT VT, SDValue Op1,
3965 SDVTList VTs = getVTList(VT);
3966 SDValue Ops[] = { Op1, Op2 };
3967 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
3970 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3971 MVT VT, SDValue Op1,
3972 SDValue Op2, SDValue Op3) {
3973 SDVTList VTs = getVTList(VT);
3974 SDValue Ops[] = { Op1, Op2, Op3 };
3975 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
3978 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3979 MVT VT, const SDValue *Ops,
3981 SDVTList VTs = getVTList(VT);
3982 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
3985 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3986 MVT VT1, MVT VT2, const SDValue *Ops,
3988 SDVTList VTs = getVTList(VT1, VT2);
3989 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
3992 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3994 SDVTList VTs = getVTList(VT1, VT2);
3995 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
3998 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
3999 MVT VT1, MVT VT2, MVT VT3,
4000 const SDValue *Ops, unsigned NumOps) {
4001 SDVTList VTs = getVTList(VT1, VT2, VT3);
4002 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4005 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4008 SDVTList VTs = getVTList(VT1, VT2);
4009 SDValue Ops[] = { Op1 };
4010 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4013 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4015 SDValue Op1, SDValue Op2) {
4016 SDVTList VTs = getVTList(VT1, VT2);
4017 SDValue Ops[] = { Op1, Op2 };
4018 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4021 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4023 SDValue Op1, SDValue Op2,
4025 SDVTList VTs = getVTList(VT1, VT2);
4026 SDValue Ops[] = { Op1, Op2, Op3 };
4027 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4030 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4031 SDVTList VTs, const SDValue *Ops,
4033 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps);
4036 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4038 SDVTList VTs = getVTList(VT);
4039 return MorphNodeTo(N, Opc, VTs, 0, 0);
4042 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4043 MVT VT, SDValue Op1) {
4044 SDVTList VTs = getVTList(VT);
4045 SDValue Ops[] = { Op1 };
4046 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4049 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4050 MVT VT, SDValue Op1,
4052 SDVTList VTs = getVTList(VT);
4053 SDValue Ops[] = { Op1, Op2 };
4054 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4057 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4058 MVT VT, SDValue Op1,
4059 SDValue Op2, SDValue Op3) {
4060 SDVTList VTs = getVTList(VT);
4061 SDValue Ops[] = { Op1, Op2, Op3 };
4062 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4065 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4066 MVT VT, const SDValue *Ops,
4068 SDVTList VTs = getVTList(VT);
4069 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4072 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4073 MVT VT1, MVT VT2, const SDValue *Ops,
4075 SDVTList VTs = getVTList(VT1, VT2);
4076 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4079 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4081 SDVTList VTs = getVTList(VT1, VT2);
4082 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
4085 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4086 MVT VT1, MVT VT2, MVT VT3,
4087 const SDValue *Ops, unsigned NumOps) {
4088 SDVTList VTs = getVTList(VT1, VT2, VT3);
4089 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4092 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4095 SDVTList VTs = getVTList(VT1, VT2);
4096 SDValue Ops[] = { Op1 };
4097 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4100 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4102 SDValue Op1, SDValue Op2) {
4103 SDVTList VTs = getVTList(VT1, VT2);
4104 SDValue Ops[] = { Op1, Op2 };
4105 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4108 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4110 SDValue Op1, SDValue Op2,
4112 SDVTList VTs = getVTList(VT1, VT2);
4113 SDValue Ops[] = { Op1, Op2, Op3 };
4114 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4117 /// MorphNodeTo - These *mutate* the specified node to have the specified
4118 /// return type, opcode, and operands.
4120 /// Note that MorphNodeTo returns the resultant node. If there is already a
4121 /// node of the specified opcode and operands, it returns that node instead of
4122 /// the current one.
4124 /// Using MorphNodeTo is faster than creating a new node and swapping it in
4125 /// with ReplaceAllUsesWith both because it often avoids allocating a new
4126 /// node, and because it doesn't require CSE recalculation for any of
4127 /// the node's users.
4129 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4130 SDVTList VTs, const SDValue *Ops,
4132 // If an identical node already exists, use it.
4134 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
4135 FoldingSetNodeID ID;
4136 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
4137 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
4141 if (!RemoveNodeFromCSEMaps(N))
4144 // Start the morphing.
4146 N->ValueList = VTs.VTs;
4147 N->NumValues = VTs.NumVTs;
4149 // Clear the operands list, updating used nodes to remove this from their
4150 // use list. Keep track of any operands that become dead as a result.
4151 SmallPtrSet<SDNode*, 16> DeadNodeSet;
4152 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end();
4154 SDNode *Used = I->getVal();
4155 Used->removeUser(std::distance(B, I), N);
4156 if (Used->use_empty())
4157 DeadNodeSet.insert(Used);
4160 // If NumOps is larger than the # of operands we currently have, reallocate
4161 // the operand list.
4162 if (NumOps > N->NumOperands) {
4163 if (N->OperandsNeedDelete)
4164 delete[] N->OperandList;
4165 if (N->isMachineOpcode()) {
4166 // We're creating a final node that will live unmorphed for the
4167 // remainder of the current SelectionDAG iteration, so we can allocate
4168 // the operands directly out of a pool with no recycling metadata.
4169 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps);
4170 N->OperandsNeedDelete = false;
4172 N->OperandList = new SDUse[NumOps];
4173 N->OperandsNeedDelete = true;
4177 // Assign the new operands.
4178 N->NumOperands = NumOps;
4179 for (unsigned i = 0, e = NumOps; i != e; ++i) {
4180 N->OperandList[i] = Ops[i];
4181 N->OperandList[i].setUser(N);
4182 SDNode *ToUse = N->OperandList[i].getVal();
4183 ToUse->addUser(i, N);
4186 // Delete any nodes that are still dead after adding the uses for the
4188 SmallVector<SDNode *, 16> DeadNodes;
4189 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(),
4190 E = DeadNodeSet.end(); I != E; ++I)
4191 if ((*I)->use_empty())
4192 DeadNodes.push_back(*I);
4193 RemoveDeadNodes(DeadNodes);
4196 CSEMap.InsertNode(N, IP); // Memoize the new node.
4201 /// getTargetNode - These are used for target selectors to create a new node
4202 /// with specified return type(s), target opcode, and operands.
4204 /// Note that getTargetNode returns the resultant node. If there is already a
4205 /// node of the specified opcode and operands, it returns that node instead of
4206 /// the current one.
4207 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
4208 return getNode(~Opcode, VT).getNode();
4210 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
4211 return getNode(~Opcode, VT, Op1).getNode();
4213 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
4214 SDValue Op1, SDValue Op2) {
4215 return getNode(~Opcode, VT, Op1, Op2).getNode();
4217 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
4218 SDValue Op1, SDValue Op2,
4220 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
4222 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
4223 const SDValue *Ops, unsigned NumOps) {
4224 return getNode(~Opcode, VT, Ops, NumOps).getNode();
4226 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
4227 const MVT *VTs = getNodeValueTypes(VT1, VT2);
4229 return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
4231 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
4232 MVT VT2, SDValue Op1) {
4233 const MVT *VTs = getNodeValueTypes(VT1, VT2);
4234 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
4236 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
4237 MVT VT2, SDValue Op1,
4239 const MVT *VTs = getNodeValueTypes(VT1, VT2);
4240 SDValue Ops[] = { Op1, Op2 };
4241 return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
4243 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
4244 MVT VT2, SDValue Op1,
4245 SDValue Op2, SDValue Op3) {
4246 const MVT *VTs = getNodeValueTypes(VT1, VT2);
4247 SDValue Ops[] = { Op1, Op2, Op3 };
4248 return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
4250 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
4251 const SDValue *Ops, unsigned NumOps) {
4252 const MVT *VTs = getNodeValueTypes(VT1, VT2);
4253 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
4255 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
4256 SDValue Op1, SDValue Op2) {
4257 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
4258 SDValue Ops[] = { Op1, Op2 };
4259 return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
4261 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
4262 SDValue Op1, SDValue Op2,
4264 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
4265 SDValue Ops[] = { Op1, Op2, Op3 };
4266 return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
4268 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
4269 const SDValue *Ops, unsigned NumOps) {
4270 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
4271 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
4273 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
4274 MVT VT2, MVT VT3, MVT VT4,
4275 const SDValue *Ops, unsigned NumOps) {
4276 std::vector<MVT> VTList;
4277 VTList.push_back(VT1);
4278 VTList.push_back(VT2);
4279 VTList.push_back(VT3);
4280 VTList.push_back(VT4);
4281 const MVT *VTs = getNodeValueTypes(VTList);
4282 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
4284 SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
4285 const std::vector<MVT> &ResultTys,
4286 const SDValue *Ops, unsigned NumOps) {
4287 const MVT *VTs = getNodeValueTypes(ResultTys);
4288 return getNode(~Opcode, VTs, ResultTys.size(),
4289 Ops, NumOps).getNode();
4292 /// getNodeIfExists - Get the specified node if it's already available, or
4293 /// else return NULL.
4294 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
4295 const SDValue *Ops, unsigned NumOps) {
4296 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
4297 FoldingSetNodeID ID;
4298 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
4300 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
4307 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4308 /// This can cause recursive merging of nodes in the DAG.
4310 /// This version assumes From has a single result value.
4312 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
4313 DAGUpdateListener *UpdateListener) {
4314 SDNode *From = FromN.getNode();
4315 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
4316 "Cannot replace with this method!");
4317 assert(From != To.getNode() && "Cannot replace uses of with self");
4319 while (!From->use_empty()) {
4320 SDNode::use_iterator UI = From->use_begin();
4323 // This node is about to morph, remove its old self from the CSE maps.
4324 RemoveNodeFromCSEMaps(U);
4326 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
4327 I != E; ++I, ++operandNum)
4328 if (I->getVal() == From) {
4329 From->removeUser(operandNum, U);
4332 To.getNode()->addUser(operandNum, U);
4335 // Now that we have modified U, add it back to the CSE maps. If it already
4336 // exists there, recursively merge the results together.
4337 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) {
4338 ReplaceAllUsesWith(U, Existing, UpdateListener);
4339 // U is now dead. Inform the listener if it exists and delete it.
4341 UpdateListener->NodeDeleted(U, Existing);
4342 DeleteNodeNotInCSEMaps(U);
4344 // If the node doesn't already exist, we updated it. Inform a listener if
4347 UpdateListener->NodeUpdated(U);
4352 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4353 /// This can cause recursive merging of nodes in the DAG.
4355 /// This version assumes From/To have matching types and numbers of result
4358 void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To,
4359 DAGUpdateListener *UpdateListener) {
4360 assert(From->getVTList().VTs == To->getVTList().VTs &&
4361 From->getNumValues() == To->getNumValues() &&
4362 "Cannot use this version of ReplaceAllUsesWith!");
4364 // Handle the trivial case.
4368 while (!From->use_empty()) {
4369 SDNode::use_iterator UI = From->use_begin();
4372 // This node is about to morph, remove its old self from the CSE maps.
4373 RemoveNodeFromCSEMaps(U);
4375 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
4376 I != E; ++I, ++operandNum)
4377 if (I->getVal() == From) {
4378 From->removeUser(operandNum, U);
4379 I->getSDValue().setNode(To);
4380 To->addUser(operandNum, U);
4383 // Now that we have modified U, add it back to the CSE maps. If it already
4384 // exists there, recursively merge the results together.
4385 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) {
4386 ReplaceAllUsesWith(U, Existing, UpdateListener);
4387 // U is now dead. Inform the listener if it exists and delete it.
4389 UpdateListener->NodeDeleted(U, Existing);
4390 DeleteNodeNotInCSEMaps(U);
4392 // If the node doesn't already exist, we updated it. Inform a listener if
4395 UpdateListener->NodeUpdated(U);
4400 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4401 /// This can cause recursive merging of nodes in the DAG.
4403 /// This version can replace From with any result values. To must match the
4404 /// number and types of values returned by From.
4405 void SelectionDAG::ReplaceAllUsesWith(SDNode *From,
4407 DAGUpdateListener *UpdateListener) {
4408 if (From->getNumValues() == 1) // Handle the simple case efficiently.
4409 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener);
4411 while (!From->use_empty()) {
4412 SDNode::use_iterator UI = From->use_begin();
4415 // This node is about to morph, remove its old self from the CSE maps.
4416 RemoveNodeFromCSEMaps(U);
4418 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
4419 I != E; ++I, ++operandNum)
4420 if (I->getVal() == From) {
4421 const SDValue &ToOp = To[I->getSDValue().getResNo()];
4422 From->removeUser(operandNum, U);
4425 ToOp.getNode()->addUser(operandNum, U);
4428 // Now that we have modified U, add it back to the CSE maps. If it already
4429 // exists there, recursively merge the results together.
4430 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) {
4431 ReplaceAllUsesWith(U, Existing, UpdateListener);
4432 // U is now dead. Inform the listener if it exists and delete it.
4434 UpdateListener->NodeDeleted(U, Existing);
4435 DeleteNodeNotInCSEMaps(U);
4437 // If the node doesn't already exist, we updated it. Inform a listener if
4440 UpdateListener->NodeUpdated(U);
4445 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
4446 /// uses of other values produced by From.getVal() alone. The Deleted vector is
4447 /// handled the same way as for ReplaceAllUsesWith.
4448 void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
4449 DAGUpdateListener *UpdateListener){
4450 // Handle the really simple, really trivial case efficiently.
4451 if (From == To) return;
4453 // Handle the simple, trivial, case efficiently.
4454 if (From.getNode()->getNumValues() == 1) {
4455 ReplaceAllUsesWith(From, To, UpdateListener);
4459 // Get all of the users of From.getNode(). We want these in a nice,
4460 // deterministically ordered and uniqued set, so we use a SmallSetVector.
4461 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end());
4463 while (!Users.empty()) {
4464 // We know that this user uses some value of From. If it is the right
4465 // value, update it.
4466 SDNode *User = Users.back();
4469 // Scan for an operand that matches From.
4470 SDNode::op_iterator Op = User->op_begin(), E = User->op_end();
4471 for (; Op != E; ++Op)
4472 if (*Op == From) break;
4474 // If there are no matches, the user must use some other result of From.
4475 if (Op == E) continue;
4477 // Okay, we know this user needs to be updated. Remove its old self
4478 // from the CSE maps.
4479 RemoveNodeFromCSEMaps(User);
4481 // Update all operands that match "From" in case there are multiple uses.
4482 for (; Op != E; ++Op) {
4484 From.getNode()->removeUser(Op-User->op_begin(), User);
4487 To.getNode()->addUser(Op-User->op_begin(), User);
4491 // Now that we have modified User, add it back to the CSE maps. If it
4492 // already exists there, recursively merge the results together.
4493 SDNode *Existing = AddNonLeafNodeToCSEMaps(User);
4495 if (UpdateListener) UpdateListener->NodeUpdated(User);
4496 continue; // Continue on to next user.
4499 // If there was already an existing matching node, use ReplaceAllUsesWith
4500 // to replace the dead one with the existing one. This can cause
4501 // recursive merging of other unrelated nodes down the line.
4502 ReplaceAllUsesWith(User, Existing, UpdateListener);
4504 // User is now dead. Notify a listener if present.
4505 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing);
4506 DeleteNodeNotInCSEMaps(User);
4510 /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
4511 /// uses of other values produced by From.getVal() alone. The same value may
4512 /// appear in both the From and To list. The Deleted vector is
4513 /// handled the same way as for ReplaceAllUsesWith.
4514 void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
4517 DAGUpdateListener *UpdateListener){
4518 // Handle the simple, trivial case efficiently.
4520 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener);
4522 SmallVector<std::pair<SDNode *, unsigned>, 16> Users;
4523 for (unsigned i = 0; i != Num; ++i)
4524 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(),
4525 E = From[i].getNode()->use_end(); UI != E; ++UI)
4526 Users.push_back(std::make_pair(*UI, i));
4528 while (!Users.empty()) {
4529 // We know that this user uses some value of From. If it is the right
4530 // value, update it.
4531 SDNode *User = Users.back().first;
4532 unsigned i = Users.back().second;
4535 // Scan for an operand that matches From.
4536 SDNode::op_iterator Op = User->op_begin(), E = User->op_end();
4537 for (; Op != E; ++Op)
4538 if (*Op == From[i]) break;
4540 // If there are no matches, the user must use some other result of From.
4541 if (Op == E) continue;
4543 // Okay, we know this user needs to be updated. Remove its old self
4544 // from the CSE maps.
4545 RemoveNodeFromCSEMaps(User);
4547 // Update all operands that match "From" in case there are multiple uses.
4548 for (; Op != E; ++Op) {
4549 if (*Op == From[i]) {
4550 From[i].getNode()->removeUser(Op-User->op_begin(), User);
4553 To[i].getNode()->addUser(Op-User->op_begin(), User);
4557 // Now that we have modified User, add it back to the CSE maps. If it
4558 // already exists there, recursively merge the results together.
4559 SDNode *Existing = AddNonLeafNodeToCSEMaps(User);
4561 if (UpdateListener) UpdateListener->NodeUpdated(User);
4562 continue; // Continue on to next user.
4565 // If there was already an existing matching node, use ReplaceAllUsesWith
4566 // to replace the dead one with the existing one. This can cause
4567 // recursive merging of other unrelated nodes down the line.
4568 ReplaceAllUsesWith(User, Existing, UpdateListener);
4570 // User is now dead. Notify a listener if present.
4571 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing);
4572 DeleteNodeNotInCSEMaps(User);
4576 /// AssignTopologicalOrder - Assign a unique node id for each node in the DAG
4577 /// based on their topological order. It returns the maximum id and a vector
4578 /// of the SDNodes* in assigned order by reference.
4579 unsigned SelectionDAG::AssignTopologicalOrder() {
4581 unsigned DAGSize = 0;
4583 // SortedPos tracks the progress of the algorithm. Nodes before it are
4584 // sorted, nodes after it are unsorted. When the algorithm completes
4585 // it is at the end of the list.
4586 allnodes_iterator SortedPos = allnodes_begin();
4588 // Visit all the nodes. Add nodes with no operands to the TopOrder result
4589 // array immediately. Annotate nodes that do have operands with their
4590 // operand count. Before we do this, the Node Id fields of the nodes
4591 // may contain arbitrary values. After, the Node Id fields for nodes
4592 // before SortedPos will contain the topological sort index, and the
4593 // Node Id fields for nodes At SortedPos and after will contain the
4594 // count of outstanding operands.
4595 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) {
4597 unsigned Degree = N->getNumOperands();
4599 // A node with no uses, add it to the result array immediately.
4600 N->setNodeId(DAGSize++);
4601 allnodes_iterator Q = N;
4603 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
4606 // Temporarily use the Node Id as scratch space for the degree count.
4607 N->setNodeId(Degree);
4611 // Visit all the nodes. As we iterate, moves nodes into sorted order,
4612 // such that by the time the end is reached all nodes will be sorted.
4613 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) {
4615 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4618 unsigned Degree = P->getNodeId();
4621 // All of P's operands are sorted, so P may sorted now.
4622 P->setNodeId(DAGSize++);
4624 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P));
4627 // Update P's outstanding operand count.
4628 P->setNodeId(Degree);
4633 assert(SortedPos == AllNodes.end() &&
4634 "Topological sort incomplete!");
4635 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
4636 "First node in topological sort is not the entry token!");
4637 assert(AllNodes.front().getNodeId() == 0 &&
4638 "First node in topological sort has non-zero id!");
4639 assert(AllNodes.front().getNumOperands() == 0 &&
4640 "First node in topological sort has operands!");
4641 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 &&
4642 "Last node in topologic sort has unexpected id!");
4643 assert(AllNodes.back().use_empty() &&
4644 "Last node in topologic sort has users!");
4645 assert(DAGSize == allnodes_size() && "TopOrder result count mismatch!");
4651 //===----------------------------------------------------------------------===//
4653 //===----------------------------------------------------------------------===//
4655 // Out-of-line virtual method to give class a home.
4656 void SDNode::ANCHOR() {}
4657 void UnarySDNode::ANCHOR() {}
4658 void BinarySDNode::ANCHOR() {}
4659 void TernarySDNode::ANCHOR() {}
4660 void HandleSDNode::ANCHOR() {}
4661 void ConstantSDNode::ANCHOR() {}
4662 void ConstantFPSDNode::ANCHOR() {}
4663 void GlobalAddressSDNode::ANCHOR() {}
4664 void FrameIndexSDNode::ANCHOR() {}
4665 void JumpTableSDNode::ANCHOR() {}
4666 void ConstantPoolSDNode::ANCHOR() {}
4667 void BasicBlockSDNode::ANCHOR() {}
4668 void SrcValueSDNode::ANCHOR() {}
4669 void MemOperandSDNode::ANCHOR() {}
4670 void RegisterSDNode::ANCHOR() {}
4671 void DbgStopPointSDNode::ANCHOR() {}
4672 void LabelSDNode::ANCHOR() {}
4673 void ExternalSymbolSDNode::ANCHOR() {}
4674 void CondCodeSDNode::ANCHOR() {}
4675 void ARG_FLAGSSDNode::ANCHOR() {}
4676 void VTSDNode::ANCHOR() {}
4677 void MemSDNode::ANCHOR() {}
4678 void LoadSDNode::ANCHOR() {}
4679 void StoreSDNode::ANCHOR() {}
4680 void AtomicSDNode::ANCHOR() {}
4681 void CallSDNode::ANCHOR() {}
4683 HandleSDNode::~HandleSDNode() {
4687 GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA,
4689 : SDNode(isa<GlobalVariable>(GA) &&
4690 cast<GlobalVariable>(GA)->isThreadLocal() ?
4692 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) :
4694 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress),
4695 getSDVTList(VT)), Offset(o) {
4696 TheGlobal = const_cast<GlobalValue*>(GA);
4699 MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt,
4700 const Value *srcValue, int SVO,
4701 unsigned alignment, bool vol)
4702 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO),
4703 Flags(encodeMemSDNodeFlags(vol, alignment)) {
4705 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4706 assert(getAlignment() == alignment && "Alignment representation error!");
4707 assert(isVolatile() == vol && "Volatile representation error!");
4710 /// getMemOperand - Return a MachineMemOperand object describing the memory
4711 /// reference performed by this memory reference.
4712 MachineMemOperand MemSDNode::getMemOperand() const {
4714 if (isa<LoadSDNode>(this))
4715 Flags = MachineMemOperand::MOLoad;
4716 else if (isa<StoreSDNode>(this))
4717 Flags = MachineMemOperand::MOStore;
4719 assert(isa<AtomicSDNode>(this) && "Unknown MemSDNode opcode!");
4720 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
4723 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3;
4724 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile;
4726 // Check if the memory reference references a frame index
4727 const FrameIndexSDNode *FI =
4728 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
4729 if (!getSrcValue() && FI)
4730 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
4731 Flags, 0, Size, getAlignment());
4733 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(),
4734 Size, getAlignment());
4737 /// Profile - Gather unique data for the node.
4739 void SDNode::Profile(FoldingSetNodeID &ID) const {
4740 AddNodeIDNode(ID, this);
4743 /// getValueTypeList - Return a pointer to the specified value type.
4745 const MVT *SDNode::getValueTypeList(MVT VT) {
4746 if (VT.isExtended()) {
4747 static std::set<MVT, MVT::compareRawBits> EVTs;
4748 return &(*EVTs.insert(VT).first);
4750 static MVT VTs[MVT::LAST_VALUETYPE];
4751 VTs[VT.getSimpleVT()] = VT;
4752 return &VTs[VT.getSimpleVT()];
4756 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
4757 /// indicated value. This method ignores uses of other values defined by this
4759 bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const {
4760 assert(Value < getNumValues() && "Bad value!");
4762 // TODO: Only iterate over uses of a given value of the node
4763 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
4764 if (UI.getUse().getSDValue().getResNo() == Value) {
4771 // Found exactly the right number of uses?
4776 /// hasAnyUseOfValue - Return true if there are any use of the indicated
4777 /// value. This method ignores uses of other values defined by this operation.
4778 bool SDNode::hasAnyUseOfValue(unsigned Value) const {
4779 assert(Value < getNumValues() && "Bad value!");
4781 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
4782 if (UI.getUse().getSDValue().getResNo() == Value)
4789 /// isOnlyUserOf - Return true if this node is the only use of N.
4791 bool SDNode::isOnlyUserOf(SDNode *N) const {
4793 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
4804 /// isOperand - Return true if this node is an operand of N.
4806 bool SDValue::isOperandOf(SDNode *N) const {
4807 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4808 if (*this == N->getOperand(i))
4813 bool SDNode::isOperandOf(SDNode *N) const {
4814 for (unsigned i = 0, e = N->NumOperands; i != e; ++i)
4815 if (this == N->OperandList[i].getVal())
4820 /// reachesChainWithoutSideEffects - Return true if this operand (which must
4821 /// be a chain) reaches the specified operand without crossing any
4822 /// side-effecting instructions. In practice, this looks through token
4823 /// factors and non-volatile loads. In order to remain efficient, this only
4824 /// looks a couple of nodes in, it does not do an exhaustive search.
4825 bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
4826 unsigned Depth) const {
4827 if (*this == Dest) return true;
4829 // Don't search too deeply, we just want to be able to see through
4830 // TokenFactor's etc.
4831 if (Depth == 0) return false;
4833 // If this is a token factor, all inputs to the TF happen in parallel. If any
4834 // of the operands of the TF reach dest, then we can do the xform.
4835 if (getOpcode() == ISD::TokenFactor) {
4836 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
4837 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1))
4842 // Loads don't have side effects, look through them.
4843 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
4844 if (!Ld->isVolatile())
4845 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
4851 static void findPredecessor(SDNode *N, const SDNode *P, bool &found,
4852 SmallPtrSet<SDNode *, 32> &Visited) {
4853 if (found || !Visited.insert(N))
4856 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) {
4857 SDNode *Op = N->getOperand(i).getNode();
4862 findPredecessor(Op, P, found, Visited);
4866 /// isPredecessorOf - Return true if this node is a predecessor of N. This node
4867 /// is either an operand of N or it can be reached by recursively traversing
4868 /// up the operands.
4869 /// NOTE: this is an expensive method. Use it carefully.
4870 bool SDNode::isPredecessorOf(SDNode *N) const {
4871 SmallPtrSet<SDNode *, 32> Visited;
4873 findPredecessor(N, this, found, Visited);
4877 uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
4878 assert(Num < NumOperands && "Invalid child # of SDNode!");
4879 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue();
4882 std::string SDNode::getOperationName(const SelectionDAG *G) const {
4883 switch (getOpcode()) {
4885 if (getOpcode() < ISD::BUILTIN_OP_END)
4886 return "<<Unknown DAG Node>>";
4887 if (isMachineOpcode()) {
4889 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
4890 if (getMachineOpcode() < TII->getNumOpcodes())
4891 return TII->get(getMachineOpcode()).getName();
4892 return "<<Unknown Machine Node>>";
4895 TargetLowering &TLI = G->getTargetLoweringInfo();
4896 const char *Name = TLI.getTargetNodeName(getOpcode());
4897 if (Name) return Name;
4898 return "<<Unknown Target Node>>";
4900 return "<<Unknown Node>>";
4903 case ISD::DELETED_NODE:
4904 return "<<Deleted Node!>>";
4906 case ISD::PREFETCH: return "Prefetch";
4907 case ISD::MEMBARRIER: return "MemBarrier";
4908 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8";
4909 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8";
4910 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8";
4911 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8";
4912 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8";
4913 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8";
4914 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8";
4915 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8";
4916 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8";
4917 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8";
4918 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8";
4919 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8";
4920 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16";
4921 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16";
4922 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16";
4923 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16";
4924 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16";
4925 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16";
4926 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16";
4927 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16";
4928 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16";
4929 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16";
4930 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16";
4931 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16";
4932 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32";
4933 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32";
4934 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32";
4935 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32";
4936 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32";
4937 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32";
4938 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32";
4939 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32";
4940 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32";
4941 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32";
4942 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32";
4943 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32";
4944 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64";
4945 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64";
4946 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64";
4947 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64";
4948 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64";
4949 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64";
4950 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64";
4951 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64";
4952 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64";
4953 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64";
4954 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64";
4955 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64";
4956 case ISD::PCMARKER: return "PCMarker";
4957 case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
4958 case ISD::SRCVALUE: return "SrcValue";
4959 case ISD::MEMOPERAND: return "MemOperand";
4960 case ISD::EntryToken: return "EntryToken";
4961 case ISD::TokenFactor: return "TokenFactor";
4962 case ISD::AssertSext: return "AssertSext";
4963 case ISD::AssertZext: return "AssertZext";
4965 case ISD::BasicBlock: return "BasicBlock";
4966 case ISD::ARG_FLAGS: return "ArgFlags";
4967 case ISD::VALUETYPE: return "ValueType";
4968 case ISD::Register: return "Register";
4970 case ISD::Constant: return "Constant";
4971 case ISD::ConstantFP: return "ConstantFP";
4972 case ISD::GlobalAddress: return "GlobalAddress";
4973 case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
4974 case ISD::FrameIndex: return "FrameIndex";
4975 case ISD::JumpTable: return "JumpTable";
4976 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
4977 case ISD::RETURNADDR: return "RETURNADDR";
4978 case ISD::FRAMEADDR: return "FRAMEADDR";
4979 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
4980 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
4981 case ISD::EHSELECTION: return "EHSELECTION";
4982 case ISD::EH_RETURN: return "EH_RETURN";
4983 case ISD::ConstantPool: return "ConstantPool";
4984 case ISD::ExternalSymbol: return "ExternalSymbol";
4985 case ISD::INTRINSIC_WO_CHAIN: {
4986 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue();
4987 return Intrinsic::getName((Intrinsic::ID)IID);
4989 case ISD::INTRINSIC_VOID:
4990 case ISD::INTRINSIC_W_CHAIN: {
4991 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue();
4992 return Intrinsic::getName((Intrinsic::ID)IID);
4995 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
4996 case ISD::TargetConstant: return "TargetConstant";
4997 case ISD::TargetConstantFP:return "TargetConstantFP";
4998 case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
4999 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
5000 case ISD::TargetFrameIndex: return "TargetFrameIndex";
5001 case ISD::TargetJumpTable: return "TargetJumpTable";
5002 case ISD::TargetConstantPool: return "TargetConstantPool";
5003 case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
5005 case ISD::CopyToReg: return "CopyToReg";
5006 case ISD::CopyFromReg: return "CopyFromReg";
5007 case ISD::UNDEF: return "undef";
5008 case ISD::MERGE_VALUES: return "merge_values";
5009 case ISD::INLINEASM: return "inlineasm";
5010 case ISD::DBG_LABEL: return "dbg_label";
5011 case ISD::EH_LABEL: return "eh_label";
5012 case ISD::DECLARE: return "declare";
5013 case ISD::HANDLENODE: return "handlenode";
5014 case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
5015 case ISD::CALL: return "call";
5018 case ISD::FABS: return "fabs";
5019 case ISD::FNEG: return "fneg";
5020 case ISD::FSQRT: return "fsqrt";
5021 case ISD::FSIN: return "fsin";
5022 case ISD::FCOS: return "fcos";
5023 case ISD::FPOWI: return "fpowi";
5024 case ISD::FPOW: return "fpow";
5025 case ISD::FTRUNC: return "ftrunc";
5026 case ISD::FFLOOR: return "ffloor";
5027 case ISD::FCEIL: return "fceil";
5028 case ISD::FRINT: return "frint";
5029 case ISD::FNEARBYINT: return "fnearbyint";
5032 case ISD::ADD: return "add";
5033 case ISD::SUB: return "sub";
5034 case ISD::MUL: return "mul";
5035 case ISD::MULHU: return "mulhu";
5036 case ISD::MULHS: return "mulhs";
5037 case ISD::SDIV: return "sdiv";
5038 case ISD::UDIV: return "udiv";
5039 case ISD::SREM: return "srem";
5040 case ISD::UREM: return "urem";
5041 case ISD::SMUL_LOHI: return "smul_lohi";
5042 case ISD::UMUL_LOHI: return "umul_lohi";
5043 case ISD::SDIVREM: return "sdivrem";
5044 case ISD::UDIVREM: return "udivrem";
5045 case ISD::AND: return "and";
5046 case ISD::OR: return "or";
5047 case ISD::XOR: return "xor";
5048 case ISD::SHL: return "shl";
5049 case ISD::SRA: return "sra";
5050 case ISD::SRL: return "srl";
5051 case ISD::ROTL: return "rotl";
5052 case ISD::ROTR: return "rotr";
5053 case ISD::FADD: return "fadd";
5054 case ISD::FSUB: return "fsub";
5055 case ISD::FMUL: return "fmul";
5056 case ISD::FDIV: return "fdiv";
5057 case ISD::FREM: return "frem";
5058 case ISD::FCOPYSIGN: return "fcopysign";
5059 case ISD::FGETSIGN: return "fgetsign";
5061 case ISD::SETCC: return "setcc";
5062 case ISD::VSETCC: return "vsetcc";
5063 case ISD::SELECT: return "select";
5064 case ISD::SELECT_CC: return "select_cc";
5065 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
5066 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
5067 case ISD::CONCAT_VECTORS: return "concat_vectors";
5068 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
5069 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
5070 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
5071 case ISD::CARRY_FALSE: return "carry_false";
5072 case ISD::ADDC: return "addc";
5073 case ISD::ADDE: return "adde";
5074 case ISD::SUBC: return "subc";
5075 case ISD::SUBE: return "sube";
5076 case ISD::SHL_PARTS: return "shl_parts";
5077 case ISD::SRA_PARTS: return "sra_parts";
5078 case ISD::SRL_PARTS: return "srl_parts";
5080 case ISD::EXTRACT_SUBREG: return "extract_subreg";
5081 case ISD::INSERT_SUBREG: return "insert_subreg";
5083 // Conversion operators.
5084 case ISD::SIGN_EXTEND: return "sign_extend";
5085 case ISD::ZERO_EXTEND: return "zero_extend";
5086 case ISD::ANY_EXTEND: return "any_extend";
5087 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
5088 case ISD::TRUNCATE: return "truncate";
5089 case ISD::FP_ROUND: return "fp_round";
5090 case ISD::FLT_ROUNDS_: return "flt_rounds";
5091 case ISD::FP_ROUND_INREG: return "fp_round_inreg";
5092 case ISD::FP_EXTEND: return "fp_extend";
5094 case ISD::SINT_TO_FP: return "sint_to_fp";
5095 case ISD::UINT_TO_FP: return "uint_to_fp";
5096 case ISD::FP_TO_SINT: return "fp_to_sint";
5097 case ISD::FP_TO_UINT: return "fp_to_uint";
5098 case ISD::BIT_CONVERT: return "bit_convert";
5100 // Control flow instructions
5101 case ISD::BR: return "br";
5102 case ISD::BRIND: return "brind";
5103 case ISD::BR_JT: return "br_jt";
5104 case ISD::BRCOND: return "brcond";
5105 case ISD::BR_CC: return "br_cc";
5106 case ISD::RET: return "ret";
5107 case ISD::CALLSEQ_START: return "callseq_start";
5108 case ISD::CALLSEQ_END: return "callseq_end";
5111 case ISD::LOAD: return "load";
5112 case ISD::STORE: return "store";
5113 case ISD::VAARG: return "vaarg";
5114 case ISD::VACOPY: return "vacopy";
5115 case ISD::VAEND: return "vaend";
5116 case ISD::VASTART: return "vastart";
5117 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
5118 case ISD::EXTRACT_ELEMENT: return "extract_element";
5119 case ISD::BUILD_PAIR: return "build_pair";
5120 case ISD::STACKSAVE: return "stacksave";
5121 case ISD::STACKRESTORE: return "stackrestore";
5122 case ISD::TRAP: return "trap";
5125 case ISD::BSWAP: return "bswap";
5126 case ISD::CTPOP: return "ctpop";
5127 case ISD::CTTZ: return "cttz";
5128 case ISD::CTLZ: return "ctlz";
5131 case ISD::DBG_STOPPOINT: return "dbg_stoppoint";
5132 case ISD::DEBUG_LOC: return "debug_loc";
5135 case ISD::TRAMPOLINE: return "trampoline";
5138 switch (cast<CondCodeSDNode>(this)->get()) {
5139 default: assert(0 && "Unknown setcc condition!");
5140 case ISD::SETOEQ: return "setoeq";
5141 case ISD::SETOGT: return "setogt";
5142 case ISD::SETOGE: return "setoge";
5143 case ISD::SETOLT: return "setolt";
5144 case ISD::SETOLE: return "setole";
5145 case ISD::SETONE: return "setone";
5147 case ISD::SETO: return "seto";
5148 case ISD::SETUO: return "setuo";
5149 case ISD::SETUEQ: return "setue";
5150 case ISD::SETUGT: return "setugt";
5151 case ISD::SETUGE: return "setuge";
5152 case ISD::SETULT: return "setult";
5153 case ISD::SETULE: return "setule";
5154 case ISD::SETUNE: return "setune";
5156 case ISD::SETEQ: return "seteq";
5157 case ISD::SETGT: return "setgt";
5158 case ISD::SETGE: return "setge";
5159 case ISD::SETLT: return "setlt";
5160 case ISD::SETLE: return "setle";
5161 case ISD::SETNE: return "setne";
5166 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
5175 return "<post-inc>";
5177 return "<post-dec>";
5181 std::string ISD::ArgFlagsTy::getArgFlagsString() {
5182 std::string S = "< ";
5196 if (getByValAlign())
5197 S += "byval-align:" + utostr(getByValAlign()) + " ";
5199 S += "orig-align:" + utostr(getOrigAlign()) + " ";
5201 S += "byval-size:" + utostr(getByValSize()) + " ";
5205 void SDNode::dump() const { dump(0); }
5206 void SDNode::dump(const SelectionDAG *G) const {
5211 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
5212 OS << (void*)this << ": ";
5214 for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
5216 if (getValueType(i) == MVT::Other)
5219 OS << getValueType(i).getMVTString();
5221 OS << " = " << getOperationName(G);
5224 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
5226 OS << (void*)getOperand(i).getNode();
5227 if (unsigned RN = getOperand(i).getResNo())
5231 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
5232 SDNode *Mask = getOperand(2).getNode();
5234 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
5236 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF)
5239 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue();
5244 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
5245 OS << '<' << CSDN->getAPIntValue() << '>';
5246 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
5247 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle)
5248 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
5249 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble)
5250 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
5253 CSDN->getValueAPF().bitcastToAPInt().dump();
5256 } else if (const GlobalAddressSDNode *GADN =
5257 dyn_cast<GlobalAddressSDNode>(this)) {
5258 int offset = GADN->getOffset();
5260 WriteAsOperand(OS, GADN->getGlobal());
5263 OS << " + " << offset;
5265 OS << " " << offset;
5266 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
5267 OS << "<" << FIDN->getIndex() << ">";
5268 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
5269 OS << "<" << JTDN->getIndex() << ">";
5270 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
5271 int offset = CP->getOffset();
5272 if (CP->isMachineConstantPoolEntry())
5273 OS << "<" << *CP->getMachineCPVal() << ">";
5275 OS << "<" << *CP->getConstVal() << ">";
5277 OS << " + " << offset;
5279 OS << " " << offset;
5280 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
5282 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
5284 OS << LBB->getName() << " ";
5285 OS << (const void*)BBDN->getBasicBlock() << ">";
5286 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
5287 if (G && R->getReg() &&
5288 TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
5289 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg());
5291 OS << " #" << R->getReg();
5293 } else if (const ExternalSymbolSDNode *ES =
5294 dyn_cast<ExternalSymbolSDNode>(this)) {
5295 OS << "'" << ES->getSymbol() << "'";
5296 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
5298 OS << "<" << M->getValue() << ">";
5301 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) {
5302 if (M->MO.getValue())
5303 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
5305 OS << "<null:" << M->MO.getOffset() << ">";
5306 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) {
5307 OS << N->getArgFlags().getArgFlagsString();
5308 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
5309 OS << ":" << N->getVT().getMVTString();
5311 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
5312 const Value *SrcValue = LD->getSrcValue();
5313 int SrcOffset = LD->getSrcValueOffset();
5319 OS << ":" << SrcOffset << ">";
5322 switch (LD->getExtensionType()) {
5323 default: doExt = false; break;
5324 case ISD::EXTLOAD: OS << " <anyext "; break;
5325 case ISD::SEXTLOAD: OS << " <sext "; break;
5326 case ISD::ZEXTLOAD: OS << " <zext "; break;
5329 OS << LD->getMemoryVT().getMVTString() << ">";
5331 const char *AM = getIndexedModeName(LD->getAddressingMode());
5334 if (LD->isVolatile())
5335 OS << " <volatile>";
5336 OS << " alignment=" << LD->getAlignment();
5337 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
5338 const Value *SrcValue = ST->getSrcValue();
5339 int SrcOffset = ST->getSrcValueOffset();
5345 OS << ":" << SrcOffset << ">";
5347 if (ST->isTruncatingStore())
5348 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">";
5350 const char *AM = getIndexedModeName(ST->getAddressingMode());
5353 if (ST->isVolatile())
5354 OS << " <volatile>";
5355 OS << " alignment=" << ST->getAlignment();
5356 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) {
5357 const Value *SrcValue = AT->getSrcValue();
5358 int SrcOffset = AT->getSrcValueOffset();
5364 OS << ":" << SrcOffset << ">";
5365 if (AT->isVolatile())
5366 OS << " <volatile>";
5367 OS << " alignment=" << AT->getAlignment();
5371 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
5372 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5373 if (N->getOperand(i).getNode()->hasOneUse())
5374 DumpNodes(N->getOperand(i).getNode(), indent+2, G);
5376 cerr << "\n" << std::string(indent+2, ' ')
5377 << (void*)N->getOperand(i).getNode() << ": <multiple use>";
5380 cerr << "\n" << std::string(indent, ' ');
5384 void SelectionDAG::dump() const {
5385 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:";
5387 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
5389 const SDNode *N = I;
5390 if (!N->hasOneUse() && N != getRoot().getNode())
5391 DumpNodes(N, 2, this);
5394 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
5399 const Type *ConstantPoolSDNode::getType() const {
5400 if (isMachineConstantPoolEntry())
5401 return Val.MachineCPVal->getType();
5402 return Val.ConstVal->getType();