1 //===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAG class.
12 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/SelectionDAG.h"
14 #include "llvm/Constants.h"
15 #include "llvm/Analysis/ValueTracking.h"
16 #include "llvm/GlobalAlias.h"
17 #include "llvm/GlobalVariable.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/ManagedStatic.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/System/Mutex.h"
39 #include "llvm/ADT/SetVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/SmallVector.h"
43 #include "llvm/ADT/StringExtras.h"
48 /// makeVTList - Return an instance of the SDVTList struct initialized with the
49 /// specified members.
50 static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
51 SDVTList Res = {VTs, NumVTs};
55 static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
56 switch (VT.getSimpleVT()) {
57 default: llvm_unreachable("Unknown FP format");
58 case MVT::f32: return &APFloat::IEEEsingle;
59 case MVT::f64: return &APFloat::IEEEdouble;
60 case MVT::f80: return &APFloat::x87DoubleExtended;
61 case MVT::f128: return &APFloat::IEEEquad;
62 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
66 SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {}
68 //===----------------------------------------------------------------------===//
69 // ConstantFPSDNode Class
70 //===----------------------------------------------------------------------===//
72 /// isExactlyValue - We don't rely on operator== working on double values, as
73 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
74 /// As such, this method can be used to do an exact bit-for-bit comparison of
75 /// two floating point values.
76 bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const {
77 return getValueAPF().bitwiseIsEqual(V);
80 bool ConstantFPSDNode::isValueValidForType(MVT VT,
82 assert(VT.isFloatingPoint() && "Can only convert between FP types");
84 // PPC long double cannot be converted to any other type.
85 if (VT == MVT::ppcf128 ||
86 &Val.getSemantics() == &APFloat::PPCDoubleDouble)
89 // convert modifies in place, so make a copy.
90 APFloat Val2 = APFloat(Val);
92 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
97 //===----------------------------------------------------------------------===//
99 //===----------------------------------------------------------------------===//
101 /// isBuildVectorAllOnes - Return true if the specified node is a
102 /// BUILD_VECTOR where all of the elements are ~0 or undef.
103 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
104 // Look through a bit convert.
105 if (N->getOpcode() == ISD::BIT_CONVERT)
106 N = N->getOperand(0).getNode();
108 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
110 unsigned i = 0, e = N->getNumOperands();
112 // Skip over all of the undef values.
113 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
116 // Do not accept an all-undef vector.
117 if (i == e) return false;
119 // Do not accept build_vectors that aren't all constants or which have non-~0
121 SDValue NotZero = N->getOperand(i);
122 if (isa<ConstantSDNode>(NotZero)) {
123 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
125 } else if (isa<ConstantFPSDNode>(NotZero)) {
126 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF().
127 bitcastToAPInt().isAllOnesValue())
132 // Okay, we have at least one ~0 value, check to see if the rest match or are
134 for (++i; i != e; ++i)
135 if (N->getOperand(i) != NotZero &&
136 N->getOperand(i).getOpcode() != ISD::UNDEF)
142 /// isBuildVectorAllZeros - Return true if the specified node is a
143 /// BUILD_VECTOR where all of the elements are 0 or undef.
144 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
145 // Look through a bit convert.
146 if (N->getOpcode() == ISD::BIT_CONVERT)
147 N = N->getOperand(0).getNode();
149 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
151 unsigned i = 0, e = N->getNumOperands();
153 // Skip over all of the undef values.
154 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
157 // Do not accept an all-undef vector.
158 if (i == e) return false;
160 // Do not accept build_vectors that aren't all constants or which have non-0
162 SDValue Zero = N->getOperand(i);
163 if (isa<ConstantSDNode>(Zero)) {
164 if (!cast<ConstantSDNode>(Zero)->isNullValue())
166 } else if (isa<ConstantFPSDNode>(Zero)) {
167 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero())
172 // Okay, we have at least one 0 value, check to see if the rest match or are
174 for (++i; i != e; ++i)
175 if (N->getOperand(i) != Zero &&
176 N->getOperand(i).getOpcode() != ISD::UNDEF)
181 /// isScalarToVector - Return true if the specified node is a
182 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
183 /// element is not an undef.
184 bool ISD::isScalarToVector(const SDNode *N) {
185 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
188 if (N->getOpcode() != ISD::BUILD_VECTOR)
190 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
192 unsigned NumElems = N->getNumOperands();
193 for (unsigned i = 1; i < NumElems; ++i) {
194 SDValue V = N->getOperand(i);
195 if (V.getOpcode() != ISD::UNDEF)
202 /// isDebugLabel - Return true if the specified node represents a debug
203 /// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
204 bool ISD::isDebugLabel(const SDNode *N) {
206 if (N->getOpcode() == ISD::DBG_LABEL)
208 if (N->isMachineOpcode() &&
209 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL)
214 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
215 /// when given the operation for (X op Y).
216 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
217 // To perform this operation, we just need to swap the L and G bits of the
219 unsigned OldL = (Operation >> 2) & 1;
220 unsigned OldG = (Operation >> 1) & 1;
221 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
222 (OldL << 1) | // New G bit
223 (OldG << 2)); // New L bit.
226 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
227 /// 'op' is a valid SetCC operation.
228 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
229 unsigned Operation = Op;
231 Operation ^= 7; // Flip L, G, E bits, but not U.
233 Operation ^= 15; // Flip all of the condition bits.
235 if (Operation > ISD::SETTRUE2)
236 Operation &= ~8; // Don't let N and U bits get set.
238 return ISD::CondCode(Operation);
242 /// isSignedOp - For an integer comparison, return 1 if the comparison is a
243 /// signed operation and 2 if the result is an unsigned comparison. Return zero
244 /// if the operation does not depend on the sign of the input (setne and seteq).
245 static int isSignedOp(ISD::CondCode Opcode) {
247 default: llvm_unreachable("Illegal integer setcc operation!");
249 case ISD::SETNE: return 0;
253 case ISD::SETGE: return 1;
257 case ISD::SETUGE: return 2;
261 /// getSetCCOrOperation - Return the result of a logical OR between different
262 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
263 /// returns SETCC_INVALID if it is not possible to represent the resultant
265 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
267 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
268 // Cannot fold a signed integer setcc with an unsigned integer setcc.
269 return ISD::SETCC_INVALID;
271 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
273 // If the N and U bits get set then the resultant comparison DOES suddenly
274 // care about orderedness, and is true when ordered.
275 if (Op > ISD::SETTRUE2)
276 Op &= ~16; // Clear the U bit if the N bit is set.
278 // Canonicalize illegal integer setcc's.
279 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
282 return ISD::CondCode(Op);
285 /// getSetCCAndOperation - Return the result of a logical AND between different
286 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
287 /// function returns zero if it is not possible to represent the resultant
289 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
291 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
292 // Cannot fold a signed setcc with an unsigned setcc.
293 return ISD::SETCC_INVALID;
295 // Combine all of the condition bits.
296 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
298 // Canonicalize illegal integer setcc's.
302 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
303 case ISD::SETOEQ: // SETEQ & SETU[LG]E
304 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
305 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
306 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
313 const TargetMachine &SelectionDAG::getTarget() const {
314 return MF->getTarget();
317 //===----------------------------------------------------------------------===//
318 // SDNode Profile Support
319 //===----------------------------------------------------------------------===//
321 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
323 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
327 /// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
328 /// solely with their pointer.
329 static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
330 ID.AddPointer(VTList.VTs);
333 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
335 static void AddNodeIDOperands(FoldingSetNodeID &ID,
336 const SDValue *Ops, unsigned NumOps) {
337 for (; NumOps; --NumOps, ++Ops) {
338 ID.AddPointer(Ops->getNode());
339 ID.AddInteger(Ops->getResNo());
343 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
345 static void AddNodeIDOperands(FoldingSetNodeID &ID,
346 const SDUse *Ops, unsigned NumOps) {
347 for (; NumOps; --NumOps, ++Ops) {
348 ID.AddPointer(Ops->getNode());
349 ID.AddInteger(Ops->getResNo());
353 static void AddNodeIDNode(FoldingSetNodeID &ID,
354 unsigned short OpC, SDVTList VTList,
355 const SDValue *OpList, unsigned N) {
356 AddNodeIDOpcode(ID, OpC);
357 AddNodeIDValueTypes(ID, VTList);
358 AddNodeIDOperands(ID, OpList, N);
361 /// AddNodeIDCustom - If this is an SDNode with special info, add this info to
363 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
364 switch (N->getOpcode()) {
365 case ISD::TargetExternalSymbol:
366 case ISD::ExternalSymbol:
367 llvm_unreachable("Should only be used on nodes with operands");
368 default: break; // Normal nodes don't need extra info.
370 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
372 case ISD::TargetConstant:
374 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue());
376 case ISD::TargetConstantFP:
377 case ISD::ConstantFP: {
378 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue());
381 case ISD::TargetGlobalAddress:
382 case ISD::GlobalAddress:
383 case ISD::TargetGlobalTLSAddress:
384 case ISD::GlobalTLSAddress: {
385 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
386 ID.AddPointer(GA->getGlobal());
387 ID.AddInteger(GA->getOffset());
388 ID.AddInteger(GA->getTargetFlags());
391 case ISD::BasicBlock:
392 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock());
395 ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
397 case ISD::DBG_STOPPOINT: {
398 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N);
399 ID.AddInteger(DSP->getLine());
400 ID.AddInteger(DSP->getColumn());
401 ID.AddPointer(DSP->getCompileUnit());
405 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
407 case ISD::MEMOPERAND: {
408 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO;
412 case ISD::FrameIndex:
413 case ISD::TargetFrameIndex:
414 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex());
417 case ISD::TargetJumpTable:
418 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex());
419 ID.AddInteger(cast<JumpTableSDNode>(N)->getTargetFlags());
421 case ISD::ConstantPool:
422 case ISD::TargetConstantPool: {
423 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
424 ID.AddInteger(CP->getAlignment());
425 ID.AddInteger(CP->getOffset());
426 if (CP->isMachineConstantPoolEntry())
427 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID);
429 ID.AddPointer(CP->getConstVal());
430 ID.AddInteger(CP->getTargetFlags());
434 const CallSDNode *Call = cast<CallSDNode>(N);
435 ID.AddInteger(Call->getCallingConv());
436 ID.AddInteger(Call->isVarArg());
440 const LoadSDNode *LD = cast<LoadSDNode>(N);
441 ID.AddInteger(LD->getMemoryVT().getRawBits());
442 ID.AddInteger(LD->getRawSubclassData());
446 const StoreSDNode *ST = cast<StoreSDNode>(N);
447 ID.AddInteger(ST->getMemoryVT().getRawBits());
448 ID.AddInteger(ST->getRawSubclassData());
451 case ISD::ATOMIC_CMP_SWAP:
452 case ISD::ATOMIC_SWAP:
453 case ISD::ATOMIC_LOAD_ADD:
454 case ISD::ATOMIC_LOAD_SUB:
455 case ISD::ATOMIC_LOAD_AND:
456 case ISD::ATOMIC_LOAD_OR:
457 case ISD::ATOMIC_LOAD_XOR:
458 case ISD::ATOMIC_LOAD_NAND:
459 case ISD::ATOMIC_LOAD_MIN:
460 case ISD::ATOMIC_LOAD_MAX:
461 case ISD::ATOMIC_LOAD_UMIN:
462 case ISD::ATOMIC_LOAD_UMAX: {
463 const AtomicSDNode *AT = cast<AtomicSDNode>(N);
464 ID.AddInteger(AT->getMemoryVT().getRawBits());
465 ID.AddInteger(AT->getRawSubclassData());
468 case ISD::VECTOR_SHUFFLE: {
469 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
470 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements();
472 ID.AddInteger(SVN->getMaskElt(i));
475 } // end switch (N->getOpcode())
478 /// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID
480 static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
481 AddNodeIDOpcode(ID, N->getOpcode());
482 // Add the return value info.
483 AddNodeIDValueTypes(ID, N->getVTList());
484 // Add the operand info.
485 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands());
487 // Handle SDNode leafs with special info.
488 AddNodeIDCustom(ID, N);
491 /// encodeMemSDNodeFlags - Generic routine for computing a value for use in
492 /// the CSE map that carries alignment, volatility, indexing mode, and
493 /// extension/truncation information.
495 static inline unsigned
496 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM,
497 bool isVolatile, unsigned Alignment) {
498 assert((ConvType & 3) == ConvType &&
499 "ConvType may not require more than 2 bits!");
500 assert((AM & 7) == AM &&
501 "AM may not require more than 3 bits!");
505 ((Log2_32(Alignment) + 1) << 6);
508 //===----------------------------------------------------------------------===//
509 // SelectionDAG Class
510 //===----------------------------------------------------------------------===//
512 /// doNotCSE - Return true if CSE should not be performed for this node.
513 static bool doNotCSE(SDNode *N) {
514 if (N->getValueType(0) == MVT::Flag)
515 return true; // Never CSE anything that produces a flag.
517 switch (N->getOpcode()) {
519 case ISD::HANDLENODE:
521 case ISD::DBG_STOPPOINT:
524 return true; // Never CSE these nodes.
527 // Check that remaining values produced are not flags.
528 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
529 if (N->getValueType(i) == MVT::Flag)
530 return true; // Never CSE anything that produces a flag.
535 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
537 void SelectionDAG::RemoveDeadNodes() {
538 // Create a dummy node (which is not added to allnodes), that adds a reference
539 // to the root node, preventing it from being deleted.
540 HandleSDNode Dummy(getRoot());
542 SmallVector<SDNode*, 128> DeadNodes;
544 // Add all obviously-dead nodes to the DeadNodes worklist.
545 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I)
547 DeadNodes.push_back(I);
549 RemoveDeadNodes(DeadNodes);
551 // If the root changed (e.g. it was a dead load, update the root).
552 setRoot(Dummy.getValue());
555 /// RemoveDeadNodes - This method deletes the unreachable nodes in the
556 /// given list, and any nodes that become unreachable as a result.
557 void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes,
558 DAGUpdateListener *UpdateListener) {
560 // Process the worklist, deleting the nodes and adding their uses to the
562 while (!DeadNodes.empty()) {
563 SDNode *N = DeadNodes.pop_back_val();
566 UpdateListener->NodeDeleted(N, 0);
568 // Take the node out of the appropriate CSE map.
569 RemoveNodeFromCSEMaps(N);
571 // Next, brutally remove the operand list. This is safe to do, as there are
572 // no cycles in the graph.
573 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
575 SDNode *Operand = Use.getNode();
578 // Now that we removed this operand, see if there are no uses of it left.
579 if (Operand->use_empty())
580 DeadNodes.push_back(Operand);
587 void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){
588 SmallVector<SDNode*, 16> DeadNodes(1, N);
589 RemoveDeadNodes(DeadNodes, UpdateListener);
592 void SelectionDAG::DeleteNode(SDNode *N) {
593 // First take this out of the appropriate CSE map.
594 RemoveNodeFromCSEMaps(N);
596 // Finally, remove uses due to operands of this node, remove from the
597 // AllNodes list, and delete the node.
598 DeleteNodeNotInCSEMaps(N);
601 void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
602 assert(N != AllNodes.begin() && "Cannot delete the entry node!");
603 assert(N->use_empty() && "Cannot delete a node that is not dead!");
605 // Drop all of the operands and decrement used node's use counts.
611 void SelectionDAG::DeallocateNode(SDNode *N) {
612 if (N->OperandsNeedDelete)
613 delete[] N->OperandList;
615 // Set the opcode to DELETED_NODE to help catch bugs when node
616 // memory is reallocated.
617 N->NodeType = ISD::DELETED_NODE;
619 NodeAllocator.Deallocate(AllNodes.remove(N));
622 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
623 /// correspond to it. This is useful when we're about to delete or repurpose
624 /// the node. We don't want future request for structurally identical nodes
625 /// to return N anymore.
626 bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
628 switch (N->getOpcode()) {
629 case ISD::EntryToken:
630 llvm_unreachable("EntryToken should not be in CSEMaps!");
632 case ISD::HANDLENODE: return false; // noop.
634 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
635 "Cond code doesn't exist!");
636 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0;
637 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0;
639 case ISD::ExternalSymbol:
640 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
642 case ISD::TargetExternalSymbol: {
643 ExternalSymbolSDNode *ESN = cast<ExternalSymbolSDNode>(N);
644 Erased = TargetExternalSymbols.erase(
645 std::pair<std::string,unsigned char>(ESN->getSymbol(),
646 ESN->getTargetFlags()));
649 case ISD::VALUETYPE: {
650 MVT VT = cast<VTSDNode>(N)->getVT();
651 if (VT.isExtended()) {
652 Erased = ExtendedValueTypeNodes.erase(VT);
654 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
655 ValueTypeNodes[VT.getSimpleVT()] = 0;
660 // Remove it from the CSE Map.
661 Erased = CSEMap.RemoveNode(N);
665 // Verify that the node was actually in one of the CSE maps, unless it has a
666 // flag result (which cannot be CSE'd) or is one of the special cases that are
667 // not subject to CSE.
668 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
669 !N->isMachineOpcode() && !doNotCSE(N)) {
672 llvm_unreachable("Node is not in map!");
678 /// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE
679 /// maps and modified in place. Add it back to the CSE maps, unless an identical
680 /// node already exists, in which case transfer all its users to the existing
681 /// node. This transfer can potentially trigger recursive merging.
684 SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N,
685 DAGUpdateListener *UpdateListener) {
686 // For node types that aren't CSE'd, just act as if no identical node
689 SDNode *Existing = CSEMap.GetOrInsertNode(N);
691 // If there was already an existing matching node, use ReplaceAllUsesWith
692 // to replace the dead one with the existing one. This can cause
693 // recursive merging of other unrelated nodes down the line.
694 ReplaceAllUsesWith(N, Existing, UpdateListener);
696 // N is now dead. Inform the listener if it exists and delete it.
698 UpdateListener->NodeDeleted(N, Existing);
699 DeleteNodeNotInCSEMaps(N);
704 // If the node doesn't already exist, we updated it. Inform a listener if
707 UpdateListener->NodeUpdated(N);
710 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
711 /// were replaced with those specified. If this node is never memoized,
712 /// return null, otherwise return a pointer to the slot it would take. If a
713 /// node already exists with these operands, the slot will be non-null.
714 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
719 SDValue Ops[] = { Op };
721 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1);
722 AddNodeIDCustom(ID, N);
723 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
726 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
727 /// were replaced with those specified. If this node is never memoized,
728 /// return null, otherwise return a pointer to the slot it would take. If a
729 /// node already exists with these operands, the slot will be non-null.
730 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
731 SDValue Op1, SDValue Op2,
736 SDValue Ops[] = { Op1, Op2 };
738 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2);
739 AddNodeIDCustom(ID, N);
740 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
744 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
745 /// were replaced with those specified. If this node is never memoized,
746 /// return null, otherwise return a pointer to the slot it would take. If a
747 /// node already exists with these operands, the slot will be non-null.
748 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
749 const SDValue *Ops,unsigned NumOps,
755 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps);
756 AddNodeIDCustom(ID, N);
757 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
760 /// VerifyNode - Sanity check the given node. Aborts if it is invalid.
761 void SelectionDAG::VerifyNode(SDNode *N) {
762 switch (N->getOpcode()) {
765 case ISD::BUILD_PAIR: {
766 MVT VT = N->getValueType(0);
767 assert(N->getNumValues() == 1 && "Too many results!");
768 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
769 "Wrong return type!");
770 assert(N->getNumOperands() == 2 && "Wrong number of operands!");
771 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() &&
772 "Mismatched operand types!");
773 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() &&
774 "Wrong operand type!");
775 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() &&
776 "Wrong return type size");
779 case ISD::BUILD_VECTOR: {
780 assert(N->getNumValues() == 1 && "Too many results!");
781 assert(N->getValueType(0).isVector() && "Wrong return type!");
782 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
783 "Wrong number of operands!");
784 MVT EltVT = N->getValueType(0).getVectorElementType();
785 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
786 assert((I->getValueType() == EltVT ||
787 (EltVT.isInteger() && I->getValueType().isInteger() &&
788 EltVT.bitsLE(I->getValueType()))) &&
789 "Wrong operand type!");
795 /// getMVTAlignment - Compute the default alignment value for the
798 unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
799 const Type *Ty = VT == MVT::iPTR ?
800 PointerType::get(Type::Int8Ty, 0) :
801 VT.getTypeForMVT(*Context);
803 return TLI.getTargetData()->getABITypeAlignment(Ty);
806 // EntryNode could meaningfully have debug info if we can find it...
807 SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
808 : TLI(tli), FLI(fli), DW(0),
809 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
810 getVTList(MVT::Other)), Root(getEntryNode()) {
811 AllNodes.push_back(&EntryNode);
814 void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
819 Context = &mf.getFunction()->getContext();
822 SelectionDAG::~SelectionDAG() {
826 void SelectionDAG::allnodes_clear() {
827 assert(&*AllNodes.begin() == &EntryNode);
828 AllNodes.remove(AllNodes.begin());
829 while (!AllNodes.empty())
830 DeallocateNode(AllNodes.begin());
833 void SelectionDAG::clear() {
835 OperandAllocator.Reset();
838 ExtendedValueTypeNodes.clear();
839 ExternalSymbols.clear();
840 TargetExternalSymbols.clear();
841 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
842 static_cast<CondCodeSDNode*>(0));
843 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
844 static_cast<SDNode*>(0));
846 EntryNode.UseList = 0;
847 AllNodes.push_back(&EntryNode);
848 Root = getEntryNode();
851 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
852 if (Op.getValueType() == VT) return Op;
853 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
855 return getNode(ISD::AND, DL, Op.getValueType(), Op,
856 getConstant(Imm, Op.getValueType()));
859 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
861 SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
862 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
864 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
865 return getNode(ISD::XOR, DL, VT, Val, NegOne);
868 SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
869 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
870 assert((EltVT.getSizeInBits() >= 64 ||
871 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
872 "getConstant with a uint64_t value that doesn't fit in the type!");
873 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
876 SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
877 return getConstant(*ConstantInt::get(*Context, Val), VT, isT);
880 SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) {
881 assert(VT.isInteger() && "Cannot create FP integer constant!");
883 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
884 assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
885 "APInt size does not match type size!");
887 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
889 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
893 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
895 return SDValue(N, 0);
897 N = NodeAllocator.Allocate<ConstantSDNode>();
898 new (N) ConstantSDNode(isT, &Val, EltVT);
899 CSEMap.InsertNode(N, IP);
900 AllNodes.push_back(N);
903 SDValue Result(N, 0);
905 SmallVector<SDValue, 8> Ops;
906 Ops.assign(VT.getVectorNumElements(), Result);
907 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
908 VT, &Ops[0], Ops.size());
913 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
914 return getConstant(Val, TLI.getPointerTy(), isTarget);
918 SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
919 return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget);
922 SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
923 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
926 VT.isVector() ? VT.getVectorElementType() : VT;
928 // Do the map lookup using the actual bit pattern for the floating point
929 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and
930 // we don't have issues with SNANs.
931 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
933 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
937 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
939 return SDValue(N, 0);
941 N = NodeAllocator.Allocate<ConstantFPSDNode>();
942 new (N) ConstantFPSDNode(isTarget, &V, EltVT);
943 CSEMap.InsertNode(N, IP);
944 AllNodes.push_back(N);
947 SDValue Result(N, 0);
949 SmallVector<SDValue, 8> Ops;
950 Ops.assign(VT.getVectorNumElements(), Result);
951 // FIXME DebugLoc info might be appropriate here
952 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
953 VT, &Ops[0], Ops.size());
958 SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
960 VT.isVector() ? VT.getVectorElementType() : VT;
962 return getConstantFP(APFloat((float)Val), VT, isTarget);
964 return getConstantFP(APFloat(Val), VT, isTarget);
967 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
968 MVT VT, int64_t Offset,
970 unsigned char TargetFlags) {
971 assert((TargetFlags == 0 || isTargetGA) &&
972 "Cannot set target flags on target-independent globals");
974 // Truncate (with sign-extension) the offset value to the pointer size.
975 unsigned BitWidth = TLI.getPointerTy().getSizeInBits();
977 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth));
979 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
981 // If GV is an alias then use the aliasee for determining thread-localness.
982 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
983 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
987 if (GVar && GVar->isThreadLocal())
988 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
990 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
995 ID.AddInteger(Offset);
996 ID.AddInteger(TargetFlags);
998 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
999 return SDValue(E, 0);
1000 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>();
1001 new (N) GlobalAddressSDNode(Opc, GV, VT, Offset, TargetFlags);
1002 CSEMap.InsertNode(N, IP);
1003 AllNodes.push_back(N);
1004 return SDValue(N, 0);
1007 SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
1008 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
1009 FoldingSetNodeID ID;
1010 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1013 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1014 return SDValue(E, 0);
1015 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>();
1016 new (N) FrameIndexSDNode(FI, VT, isTarget);
1017 CSEMap.InsertNode(N, IP);
1018 AllNodes.push_back(N);
1019 return SDValue(N, 0);
1022 SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget,
1023 unsigned char TargetFlags) {
1024 assert((TargetFlags == 0 || isTarget) &&
1025 "Cannot set target flags on target-independent jump tables");
1026 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1027 FoldingSetNodeID ID;
1028 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1030 ID.AddInteger(TargetFlags);
1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1033 return SDValue(E, 0);
1034 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>();
1035 new (N) JumpTableSDNode(JTI, VT, isTarget, TargetFlags);
1036 CSEMap.InsertNode(N, IP);
1037 AllNodes.push_back(N);
1038 return SDValue(N, 0);
1041 SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
1042 unsigned Alignment, int Offset,
1044 unsigned char TargetFlags) {
1045 assert((TargetFlags == 0 || isTarget) &&
1046 "Cannot set target flags on target-independent globals");
1048 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType());
1049 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1050 FoldingSetNodeID ID;
1051 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1052 ID.AddInteger(Alignment);
1053 ID.AddInteger(Offset);
1055 ID.AddInteger(TargetFlags);
1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1058 return SDValue(E, 0);
1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags);
1061 CSEMap.InsertNode(N, IP);
1062 AllNodes.push_back(N);
1063 return SDValue(N, 0);
1067 SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
1068 unsigned Alignment, int Offset,
1070 unsigned char TargetFlags) {
1071 assert((TargetFlags == 0 || isTarget) &&
1072 "Cannot set target flags on target-independent globals");
1074 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType());
1075 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1076 FoldingSetNodeID ID;
1077 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1078 ID.AddInteger(Alignment);
1079 ID.AddInteger(Offset);
1080 C->AddSelectionDAGCSEId(ID);
1081 ID.AddInteger(TargetFlags);
1083 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1084 return SDValue(E, 0);
1085 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1086 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags);
1087 CSEMap.InsertNode(N, IP);
1088 AllNodes.push_back(N);
1089 return SDValue(N, 0);
1092 SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
1093 FoldingSetNodeID ID;
1094 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1097 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1098 return SDValue(E, 0);
1099 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>();
1100 new (N) BasicBlockSDNode(MBB);
1101 CSEMap.InsertNode(N, IP);
1102 AllNodes.push_back(N);
1103 return SDValue(N, 0);
1106 SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
1107 FoldingSetNodeID ID;
1108 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
1109 ID.AddInteger(Flags.getRawBits());
1111 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1112 return SDValue(E, 0);
1113 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>();
1114 new (N) ARG_FLAGSSDNode(Flags);
1115 CSEMap.InsertNode(N, IP);
1116 AllNodes.push_back(N);
1117 return SDValue(N, 0);
1120 SDValue SelectionDAG::getValueType(MVT VT) {
1121 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
1122 ValueTypeNodes.resize(VT.getSimpleVT()+1);
1124 SDNode *&N = VT.isExtended() ?
1125 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
1127 if (N) return SDValue(N, 0);
1128 N = NodeAllocator.Allocate<VTSDNode>();
1129 new (N) VTSDNode(VT);
1130 AllNodes.push_back(N);
1131 return SDValue(N, 0);
1134 SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
1135 SDNode *&N = ExternalSymbols[Sym];
1136 if (N) return SDValue(N, 0);
1137 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1138 new (N) ExternalSymbolSDNode(false, Sym, 0, VT);
1139 AllNodes.push_back(N);
1140 return SDValue(N, 0);
1143 SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT,
1144 unsigned char TargetFlags) {
1146 TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym,
1148 if (N) return SDValue(N, 0);
1149 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1150 new (N) ExternalSymbolSDNode(true, Sym, TargetFlags, VT);
1151 AllNodes.push_back(N);
1152 return SDValue(N, 0);
1155 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1156 if ((unsigned)Cond >= CondCodeNodes.size())
1157 CondCodeNodes.resize(Cond+1);
1159 if (CondCodeNodes[Cond] == 0) {
1160 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>();
1161 new (N) CondCodeSDNode(Cond);
1162 CondCodeNodes[Cond] = N;
1163 AllNodes.push_back(N);
1165 return SDValue(CondCodeNodes[Cond], 0);
1168 // commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
1169 // the shuffle mask M that point at N1 to point at N2, and indices that point
1170 // N2 to point at N1.
1171 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
1173 int NElts = M.size();
1174 for (int i = 0; i != NElts; ++i) {
1182 SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1,
1183 SDValue N2, const int *Mask) {
1184 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
1185 assert(VT.isVector() && N1.getValueType().isVector() &&
1186 "Vector Shuffle VTs must be a vectors");
1187 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType()
1188 && "Vector Shuffle VTs must have same element type");
1190 // Canonicalize shuffle undef, undef -> undef
1191 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
1192 return getUNDEF(VT);
1194 // Validate that all indices in Mask are within the range of the elements
1195 // input to the shuffle.
1196 unsigned NElts = VT.getVectorNumElements();
1197 SmallVector<int, 8> MaskVec;
1198 for (unsigned i = 0; i != NElts; ++i) {
1199 assert(Mask[i] < (int)(NElts * 2) && "Index out of range");
1200 MaskVec.push_back(Mask[i]);
1203 // Canonicalize shuffle v, v -> v, undef
1206 for (unsigned i = 0; i != NElts; ++i)
1207 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts;
1210 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
1211 if (N1.getOpcode() == ISD::UNDEF)
1212 commuteShuffle(N1, N2, MaskVec);
1214 // Canonicalize all index into lhs, -> shuffle lhs, undef
1215 // Canonicalize all index into rhs, -> shuffle rhs, undef
1216 bool AllLHS = true, AllRHS = true;
1217 bool N2Undef = N2.getOpcode() == ISD::UNDEF;
1218 for (unsigned i = 0; i != NElts; ++i) {
1219 if (MaskVec[i] >= (int)NElts) {
1224 } else if (MaskVec[i] >= 0) {
1228 if (AllLHS && AllRHS)
1229 return getUNDEF(VT);
1230 if (AllLHS && !N2Undef)
1234 commuteShuffle(N1, N2, MaskVec);
1237 // If Identity shuffle, or all shuffle in to undef, return that node.
1238 bool AllUndef = true;
1239 bool Identity = true;
1240 for (unsigned i = 0; i != NElts; ++i) {
1241 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false;
1242 if (MaskVec[i] >= 0) AllUndef = false;
1244 if (Identity && NElts == N1.getValueType().getVectorNumElements())
1247 return getUNDEF(VT);
1249 FoldingSetNodeID ID;
1250 SDValue Ops[2] = { N1, N2 };
1251 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
1252 for (unsigned i = 0; i != NElts; ++i)
1253 ID.AddInteger(MaskVec[i]);
1256 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1257 return SDValue(E, 0);
1259 // Allocate the mask array for the node out of the BumpPtrAllocator, since
1260 // SDNode doesn't have access to it. This memory will be "leaked" when
1261 // the node is deallocated, but recovered when the NodeAllocator is released.
1262 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts);
1263 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int));
1265 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>();
1266 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc);
1267 CSEMap.InsertNode(N, IP);
1268 AllNodes.push_back(N);
1269 return SDValue(N, 0);
1272 SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
1273 SDValue Val, SDValue DTy,
1274 SDValue STy, SDValue Rnd, SDValue Sat,
1275 ISD::CvtCode Code) {
1276 // If the src and dest types are the same and the conversion is between
1277 // integer types of the same sign or two floats, no conversion is necessary.
1279 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF))
1282 FoldingSetNodeID ID;
1284 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1285 return SDValue(E, 0);
1286 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>();
1287 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat };
1288 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code);
1289 CSEMap.InsertNode(N, IP);
1290 AllNodes.push_back(N);
1291 return SDValue(N, 0);
1294 SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
1295 FoldingSetNodeID ID;
1296 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1297 ID.AddInteger(RegNo);
1299 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1300 return SDValue(E, 0);
1301 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>();
1302 new (N) RegisterSDNode(RegNo, VT);
1303 CSEMap.InsertNode(N, IP);
1304 AllNodes.push_back(N);
1305 return SDValue(N, 0);
1308 SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root,
1309 unsigned Line, unsigned Col,
1311 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>();
1312 new (N) DbgStopPointSDNode(Root, Line, Col, CU);
1314 AllNodes.push_back(N);
1315 return SDValue(N, 0);
1318 SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
1321 FoldingSetNodeID ID;
1322 SDValue Ops[] = { Root };
1323 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
1324 ID.AddInteger(LabelID);
1326 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1327 return SDValue(E, 0);
1328 SDNode *N = NodeAllocator.Allocate<LabelSDNode>();
1329 new (N) LabelSDNode(Opcode, dl, Root, LabelID);
1330 CSEMap.InsertNode(N, IP);
1331 AllNodes.push_back(N);
1332 return SDValue(N, 0);
1335 SDValue SelectionDAG::getSrcValue(const Value *V) {
1336 assert((!V || isa<PointerType>(V->getType())) &&
1337 "SrcValue is not a pointer?");
1339 FoldingSetNodeID ID;
1340 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1344 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1345 return SDValue(E, 0);
1347 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>();
1348 new (N) SrcValueSDNode(V);
1349 CSEMap.InsertNode(N, IP);
1350 AllNodes.push_back(N);
1351 return SDValue(N, 0);
1354 SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
1356 const Value *v = MO.getValue();
1357 assert((!v || isa<PointerType>(v->getType())) &&
1358 "SrcValue is not a pointer?");
1361 FoldingSetNodeID ID;
1362 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
1366 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1367 return SDValue(E, 0);
1369 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>();
1370 new (N) MemOperandSDNode(MO);
1371 CSEMap.InsertNode(N, IP);
1372 AllNodes.push_back(N);
1373 return SDValue(N, 0);
1376 /// getShiftAmountOperand - Return the specified value casted to
1377 /// the target's desired shift amount type.
1378 SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
1379 MVT OpTy = Op.getValueType();
1380 MVT ShTy = TLI.getShiftAmountTy();
1381 if (OpTy == ShTy || OpTy.isVector()) return Op;
1383 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1384 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op);
1387 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
1388 /// specified value type.
1389 SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
1390 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1391 unsigned ByteSize = VT.getStoreSizeInBits()/8;
1392 const Type *Ty = VT.getTypeForMVT(*Context);
1393 unsigned StackAlign =
1394 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
1396 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
1397 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1400 /// CreateStackTemporary - Create a stack temporary suitable for holding
1401 /// either of the specified value types.
1402 SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
1403 unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
1404 VT2.getStoreSizeInBits())/8;
1405 const Type *Ty1 = VT1.getTypeForMVT(*Context);
1406 const Type *Ty2 = VT2.getTypeForMVT(*Context);
1407 const TargetData *TD = TLI.getTargetData();
1408 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
1409 TD->getPrefTypeAlignment(Ty2));
1411 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1412 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align);
1413 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1416 SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
1417 SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
1418 // These setcc operations always fold.
1422 case ISD::SETFALSE2: return getConstant(0, VT);
1424 case ISD::SETTRUE2: return getConstant(1, VT);
1436 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!");
1440 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
1441 const APInt &C2 = N2C->getAPIntValue();
1442 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1443 const APInt &C1 = N1C->getAPIntValue();
1446 default: llvm_unreachable("Unknown integer setcc!");
1447 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1448 case ISD::SETNE: return getConstant(C1 != C2, VT);
1449 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1450 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1451 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1452 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1453 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1454 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1455 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1456 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1460 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1461 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
1462 // No compile time operations on this type yet.
1463 if (N1C->getValueType(0) == MVT::ppcf128)
1466 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
1469 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1470 return getUNDEF(VT);
1472 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1473 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1474 return getUNDEF(VT);
1476 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1477 R==APFloat::cmpLessThan, VT);
1478 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1479 return getUNDEF(VT);
1481 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1482 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1483 return getUNDEF(VT);
1485 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1486 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1487 return getUNDEF(VT);
1489 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1490 R==APFloat::cmpEqual, VT);
1491 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1492 return getUNDEF(VT);
1494 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1495 R==APFloat::cmpEqual, VT);
1496 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1497 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1498 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1499 R==APFloat::cmpEqual, VT);
1500 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1501 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1502 R==APFloat::cmpLessThan, VT);
1503 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1504 R==APFloat::cmpUnordered, VT);
1505 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1506 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1509 // Ensure that the constant occurs on the RHS.
1510 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1514 // Could not fold it.
1518 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
1519 /// use this predicate to simplify operations downstream.
1520 bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
1521 // This predicate is not safe for vector operations.
1522 if (Op.getValueType().isVector())
1525 unsigned BitWidth = Op.getValueSizeInBits();
1526 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
1529 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
1530 /// this predicate to simplify operations downstream. Mask is known to be zero
1531 /// for bits that V cannot have.
1532 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
1533 unsigned Depth) const {
1534 APInt KnownZero, KnownOne;
1535 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1537 return (KnownZero & Mask) == Mask;
1540 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
1541 /// known to be either zero or one and return them in the KnownZero/KnownOne
1542 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
1544 void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
1545 APInt &KnownZero, APInt &KnownOne,
1546 unsigned Depth) const {
1547 unsigned BitWidth = Mask.getBitWidth();
1548 assert(BitWidth == Op.getValueType().getSizeInBits() &&
1549 "Mask size mismatches value type size!");
1551 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
1552 if (Depth == 6 || Mask == 0)
1553 return; // Limit search depth.
1555 APInt KnownZero2, KnownOne2;
1557 switch (Op.getOpcode()) {
1559 // We know all of the bits for a constant!
1560 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask;
1561 KnownZero = ~KnownOne & Mask;
1564 // If either the LHS or the RHS are Zero, the result is zero.
1565 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1566 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero,
1567 KnownZero2, KnownOne2, Depth+1);
1568 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1569 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1571 // Output known-1 bits are only known if set in both the LHS & RHS.
1572 KnownOne &= KnownOne2;
1573 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1574 KnownZero |= KnownZero2;
1577 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1578 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne,
1579 KnownZero2, KnownOne2, Depth+1);
1580 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1581 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1583 // Output known-0 bits are only known if clear in both the LHS & RHS.
1584 KnownZero &= KnownZero2;
1585 // Output known-1 are known to be set if set in either the LHS | RHS.
1586 KnownOne |= KnownOne2;
1589 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1590 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
1591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1592 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1594 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1595 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1596 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1597 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1598 KnownZero = KnownZeroOut;
1602 APInt Mask2 = APInt::getAllOnesValue(BitWidth);
1603 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1);
1604 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1605 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1606 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1608 // If low bits are zero in either operand, output low known-0 bits.
1609 // Also compute a conserative estimate for high known-0 bits.
1610 // More trickiness is possible, but this is sufficient for the
1611 // interesting case of alignment computation.
1613 unsigned TrailZ = KnownZero.countTrailingOnes() +
1614 KnownZero2.countTrailingOnes();
1615 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() +
1616 KnownZero2.countLeadingOnes(),
1617 BitWidth) - BitWidth;
1619 TrailZ = std::min(TrailZ, BitWidth);
1620 LeadZ = std::min(LeadZ, BitWidth);
1621 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
1622 APInt::getHighBitsSet(BitWidth, LeadZ);
1627 // For the purposes of computing leading zeros we can conservatively
1628 // treat a udiv as a logical right shift by the power of 2 known to
1629 // be less than the denominator.
1630 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1631 ComputeMaskedBits(Op.getOperand(0),
1632 AllOnes, KnownZero2, KnownOne2, Depth+1);
1633 unsigned LeadZ = KnownZero2.countLeadingOnes();
1637 ComputeMaskedBits(Op.getOperand(1),
1638 AllOnes, KnownZero2, KnownOne2, Depth+1);
1639 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
1640 if (RHSUnknownLeadingOnes != BitWidth)
1641 LeadZ = std::min(BitWidth,
1642 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1);
1644 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask;
1648 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
1649 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
1650 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1651 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1653 // Only known if known in both the LHS and RHS.
1654 KnownOne &= KnownOne2;
1655 KnownZero &= KnownZero2;
1657 case ISD::SELECT_CC:
1658 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
1659 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
1660 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1661 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1663 // Only known if known in both the LHS and RHS.
1664 KnownOne &= KnownOne2;
1665 KnownZero &= KnownZero2;
1673 if (Op.getResNo() != 1)
1675 // The boolean result conforms to getBooleanContents. Fall through.
1677 // If we know the result of a setcc has the top bits zero, use this info.
1678 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
1680 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1683 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
1684 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1685 unsigned ShAmt = SA->getZExtValue();
1687 // If the shift count is an invalid immediate, don't do anything.
1688 if (ShAmt >= BitWidth)
1691 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt),
1692 KnownZero, KnownOne, Depth+1);
1693 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1694 KnownZero <<= ShAmt;
1696 // low bits known zero.
1697 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt);
1701 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
1702 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1703 unsigned ShAmt = SA->getZExtValue();
1705 // If the shift count is an invalid immediate, don't do anything.
1706 if (ShAmt >= BitWidth)
1709 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt),
1710 KnownZero, KnownOne, Depth+1);
1711 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1712 KnownZero = KnownZero.lshr(ShAmt);
1713 KnownOne = KnownOne.lshr(ShAmt);
1715 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1716 KnownZero |= HighBits; // High bits known zero.
1720 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1721 unsigned ShAmt = SA->getZExtValue();
1723 // If the shift count is an invalid immediate, don't do anything.
1724 if (ShAmt >= BitWidth)
1727 APInt InDemandedMask = (Mask << ShAmt);
1728 // If any of the demanded bits are produced by the sign extension, we also
1729 // demand the input sign bit.
1730 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1731 if (HighBits.getBoolValue())
1732 InDemandedMask |= APInt::getSignBit(BitWidth);
1734 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
1736 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1737 KnownZero = KnownZero.lshr(ShAmt);
1738 KnownOne = KnownOne.lshr(ShAmt);
1740 // Handle the sign bits.
1741 APInt SignBit = APInt::getSignBit(BitWidth);
1742 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask.
1744 if (KnownZero.intersects(SignBit)) {
1745 KnownZero |= HighBits; // New bits are known zero.
1746 } else if (KnownOne.intersects(SignBit)) {
1747 KnownOne |= HighBits; // New bits are known one.
1751 case ISD::SIGN_EXTEND_INREG: {
1752 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1753 unsigned EBits = EVT.getSizeInBits();
1755 // Sign extension. Compute the demanded bits in the result that are not
1756 // present in the input.
1757 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask;
1759 APInt InSignBit = APInt::getSignBit(EBits);
1760 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits);
1762 // If the sign extended bits are demanded, we know that the sign
1764 InSignBit.zext(BitWidth);
1765 if (NewBits.getBoolValue())
1766 InputDemandedBits |= InSignBit;
1768 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
1769 KnownZero, KnownOne, Depth+1);
1770 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1772 // If the sign bit of the input is known set or clear, then we know the
1773 // top bits of the result.
1774 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear
1775 KnownZero |= NewBits;
1776 KnownOne &= ~NewBits;
1777 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1778 KnownOne |= NewBits;
1779 KnownZero &= ~NewBits;
1780 } else { // Input sign bit unknown
1781 KnownZero &= ~NewBits;
1782 KnownOne &= ~NewBits;
1789 unsigned LowBits = Log2_32(BitWidth)+1;
1790 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits);
1795 if (ISD::isZEXTLoad(Op.getNode())) {
1796 LoadSDNode *LD = cast<LoadSDNode>(Op);
1797 MVT VT = LD->getMemoryVT();
1798 unsigned MemBits = VT.getSizeInBits();
1799 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
1803 case ISD::ZERO_EXTEND: {
1804 MVT InVT = Op.getOperand(0).getValueType();
1805 unsigned InBits = InVT.getSizeInBits();
1806 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1807 APInt InMask = Mask;
1808 InMask.trunc(InBits);
1809 KnownZero.trunc(InBits);
1810 KnownOne.trunc(InBits);
1811 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1812 KnownZero.zext(BitWidth);
1813 KnownOne.zext(BitWidth);
1814 KnownZero |= NewBits;
1817 case ISD::SIGN_EXTEND: {
1818 MVT InVT = Op.getOperand(0).getValueType();
1819 unsigned InBits = InVT.getSizeInBits();
1820 APInt InSignBit = APInt::getSignBit(InBits);
1821 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1822 APInt InMask = Mask;
1823 InMask.trunc(InBits);
1825 // If any of the sign extended bits are demanded, we know that the sign
1826 // bit is demanded. Temporarily set this bit in the mask for our callee.
1827 if (NewBits.getBoolValue())
1828 InMask |= InSignBit;
1830 KnownZero.trunc(InBits);
1831 KnownOne.trunc(InBits);
1832 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1834 // Note if the sign bit is known to be zero or one.
1835 bool SignBitKnownZero = KnownZero.isNegative();
1836 bool SignBitKnownOne = KnownOne.isNegative();
1837 assert(!(SignBitKnownZero && SignBitKnownOne) &&
1838 "Sign bit can't be known to be both zero and one!");
1840 // If the sign bit wasn't actually demanded by our caller, we don't
1841 // want it set in the KnownZero and KnownOne result values. Reset the
1842 // mask and reapply it to the result values.
1844 InMask.trunc(InBits);
1845 KnownZero &= InMask;
1848 KnownZero.zext(BitWidth);
1849 KnownOne.zext(BitWidth);
1851 // If the sign bit is known zero or one, the top bits match.
1852 if (SignBitKnownZero)
1853 KnownZero |= NewBits;
1854 else if (SignBitKnownOne)
1855 KnownOne |= NewBits;
1858 case ISD::ANY_EXTEND: {
1859 MVT InVT = Op.getOperand(0).getValueType();
1860 unsigned InBits = InVT.getSizeInBits();
1861 APInt InMask = Mask;
1862 InMask.trunc(InBits);
1863 KnownZero.trunc(InBits);
1864 KnownOne.trunc(InBits);
1865 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1866 KnownZero.zext(BitWidth);
1867 KnownOne.zext(BitWidth);
1870 case ISD::TRUNCATE: {
1871 MVT InVT = Op.getOperand(0).getValueType();
1872 unsigned InBits = InVT.getSizeInBits();
1873 APInt InMask = Mask;
1874 InMask.zext(InBits);
1875 KnownZero.zext(InBits);
1876 KnownOne.zext(InBits);
1877 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1878 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1879 KnownZero.trunc(BitWidth);
1880 KnownOne.trunc(BitWidth);
1883 case ISD::AssertZext: {
1884 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1885 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
1886 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1888 KnownZero |= (~InMask) & Mask;
1892 // All bits are zero except the low bit.
1893 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1897 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
1898 // We know that the top bits of C-X are clear if X contains less bits
1899 // than C (i.e. no wrap-around can happen). For example, 20-X is
1900 // positive if we can prove that X is >= 0 and < 16.
1901 if (CLHS->getAPIntValue().isNonNegative()) {
1902 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
1903 // NLZ can't be BitWidth with no sign bit
1904 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
1905 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2,
1908 // If all of the MaskV bits are known to be zero, then we know the
1909 // output top bits are zero, because we now know that the output is
1911 if ((KnownZero2 & MaskV) == MaskV) {
1912 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros();
1913 // Top bits known zero.
1914 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask;
1921 // Output known-0 bits are known if clear or set in both the low clear bits
1922 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
1923 // low 3 bits clear.
1924 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes());
1925 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1926 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1927 unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
1929 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1);
1930 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1931 KnownZeroOut = std::min(KnownZeroOut,
1932 KnownZero2.countTrailingOnes());
1934 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut);
1938 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1939 const APInt &RA = Rem->getAPIntValue();
1940 if (RA.isPowerOf2() || (-RA).isPowerOf2()) {
1941 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA;
1942 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
1943 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
1945 // If the sign bit of the first operand is zero, the sign bit of
1946 // the result is zero. If the first operand has no one bits below
1947 // the second operand's single 1 bit, its sign will be zero.
1948 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
1949 KnownZero2 |= ~LowBits;
1951 KnownZero |= KnownZero2 & Mask;
1953 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1958 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1959 const APInt &RA = Rem->getAPIntValue();
1960 if (RA.isPowerOf2()) {
1961 APInt LowBits = (RA - 1);
1962 APInt Mask2 = LowBits & Mask;
1963 KnownZero |= ~LowBits & Mask;
1964 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1);
1965 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1970 // Since the result is less than or equal to either operand, any leading
1971 // zero bits in either operand must also exist in the result.
1972 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1973 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne,
1975 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2,
1978 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(),
1979 KnownZero2.countLeadingOnes());
1981 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask;
1985 // Allow the target to implement this method for its nodes.
1986 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1987 case ISD::INTRINSIC_WO_CHAIN:
1988 case ISD::INTRINSIC_W_CHAIN:
1989 case ISD::INTRINSIC_VOID:
1990 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this);
1996 /// ComputeNumSignBits - Return the number of times the sign bit of the
1997 /// register is replicated into the other bits. We know that at least 1 bit
1998 /// is always equal to the sign bit (itself), but other cases can give us
1999 /// information. For example, immediately after an "SRA X, 2", we know that
2000 /// the top 3 bits are all equal to each other, so we return 3.
2001 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
2002 MVT VT = Op.getValueType();
2003 assert(VT.isInteger() && "Invalid VT!");
2004 unsigned VTBits = VT.getSizeInBits();
2006 unsigned FirstAnswer = 1;
2009 return 1; // Limit search depth.
2011 switch (Op.getOpcode()) {
2013 case ISD::AssertSext:
2014 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
2015 return VTBits-Tmp+1;
2016 case ISD::AssertZext:
2017 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
2020 case ISD::Constant: {
2021 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
2022 // If negative, return # leading ones.
2023 if (Val.isNegative())
2024 return Val.countLeadingOnes();
2026 // Return # leading zeros.
2027 return Val.countLeadingZeros();
2030 case ISD::SIGN_EXTEND:
2031 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
2032 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
2034 case ISD::SIGN_EXTEND_INREG:
2035 // Max of the input and what this extends.
2036 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
2039 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2040 return std::max(Tmp, Tmp2);
2043 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2044 // SRA X, C -> adds C sign bits.
2045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2046 Tmp += C->getZExtValue();
2047 if (Tmp > VTBits) Tmp = VTBits;
2051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2052 // shl destroys sign bits.
2053 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2054 if (C->getZExtValue() >= VTBits || // Bad shift.
2055 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out.
2056 return Tmp - C->getZExtValue();
2061 case ISD::XOR: // NOT is handled here.
2062 // Logical binary ops preserve the number of sign bits at the worst.
2063 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2065 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2066 FirstAnswer = std::min(Tmp, Tmp2);
2067 // We computed what we know about the sign bits as our first
2068 // answer. Now proceed to the generic code that uses
2069 // ComputeMaskedBits, and pick whichever answer is better.
2074 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2075 if (Tmp == 1) return 1; // Early out.
2076 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1);
2077 return std::min(Tmp, Tmp2);
2085 if (Op.getResNo() != 1)
2087 // The boolean result conforms to getBooleanContents. Fall through.
2089 // If setcc returns 0/-1, all bits are sign bits.
2090 if (TLI.getBooleanContents() ==
2091 TargetLowering::ZeroOrNegativeOneBooleanContent)
2096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2097 unsigned RotAmt = C->getZExtValue() & (VTBits-1);
2099 // Handle rotate right by N like a rotate left by 32-N.
2100 if (Op.getOpcode() == ISD::ROTR)
2101 RotAmt = (VTBits-RotAmt) & (VTBits-1);
2103 // If we aren't rotating out all of the known-in sign bits, return the
2104 // number that are left. This handles rotl(sext(x), 1) for example.
2105 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2106 if (Tmp > RotAmt+1) return Tmp-RotAmt;
2110 // Add can have at most one carry bit. Thus we know that the output
2111 // is, at worst, one more bit than the inputs.
2112 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2113 if (Tmp == 1) return 1; // Early out.
2115 // Special case decrementing a value (ADD X, -1):
2116 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
2117 if (CRHS->isAllOnesValue()) {
2118 APInt KnownZero, KnownOne;
2119 APInt Mask = APInt::getAllOnesValue(VTBits);
2120 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2122 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2124 if ((KnownZero | APInt(VTBits, 1)) == Mask)
2127 // If we are subtracting one from a positive number, there is no carry
2128 // out of the result.
2129 if (KnownZero.isNegative())
2133 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2134 if (Tmp2 == 1) return 1;
2135 return std::min(Tmp, Tmp2)-1;
2139 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2140 if (Tmp2 == 1) return 1;
2143 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
2144 if (CLHS->isNullValue()) {
2145 APInt KnownZero, KnownOne;
2146 APInt Mask = APInt::getAllOnesValue(VTBits);
2147 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
2148 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2150 if ((KnownZero | APInt(VTBits, 1)) == Mask)
2153 // If the input is known to be positive (the sign bit is known clear),
2154 // the output of the NEG has the same number of sign bits as the input.
2155 if (KnownZero.isNegative())
2158 // Otherwise, we treat this like a SUB.
2161 // Sub can have at most one carry bit. Thus we know that the output
2162 // is, at worst, one more bit than the inputs.
2163 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2164 if (Tmp == 1) return 1; // Early out.
2165 return std::min(Tmp, Tmp2)-1;
2168 // FIXME: it's tricky to do anything useful for this, but it is an important
2169 // case for targets like X86.
2173 // Handle LOADX separately here. EXTLOAD case will fallthrough.
2174 if (Op.getOpcode() == ISD::LOAD) {
2175 LoadSDNode *LD = cast<LoadSDNode>(Op);
2176 unsigned ExtType = LD->getExtensionType();
2179 case ISD::SEXTLOAD: // '17' bits known
2180 Tmp = LD->getMemoryVT().getSizeInBits();
2181 return VTBits-Tmp+1;
2182 case ISD::ZEXTLOAD: // '16' bits known
2183 Tmp = LD->getMemoryVT().getSizeInBits();
2188 // Allow the target to implement this method for its nodes.
2189 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2190 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2191 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2192 Op.getOpcode() == ISD::INTRINSIC_VOID) {
2193 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth);
2194 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits);
2197 // Finally, if we can prove that the top bits of the result are 0's or 1's,
2198 // use this information.
2199 APInt KnownZero, KnownOne;
2200 APInt Mask = APInt::getAllOnesValue(VTBits);
2201 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
2203 if (KnownZero.isNegative()) { // sign bit is 0
2205 } else if (KnownOne.isNegative()) { // sign bit is 1;
2212 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
2213 // the number of identical bits in the top of the input value.
2215 Mask <<= Mask.getBitWidth()-VTBits;
2216 // Return # leading zeros. We use 'min' here in case Val was zero before
2217 // shifting. We don't want to return '64' as for an i32 "0".
2218 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros()));
2222 bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
2223 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2224 if (!GA) return false;
2225 if (GA->getOffset() != 0) return false;
2226 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal());
2227 if (!GV) return false;
2228 MachineModuleInfo *MMI = getMachineModuleInfo();
2229 return MMI && MMI->hasDebugInfo();
2233 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
2234 /// element of the result of the vector shuffle.
2235 SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N,
2237 MVT VT = N->getValueType(0);
2238 DebugLoc dl = N->getDebugLoc();
2239 if (N->getMaskElt(i) < 0)
2240 return getUNDEF(VT.getVectorElementType());
2241 unsigned Index = N->getMaskElt(i);
2242 unsigned NumElems = VT.getVectorNumElements();
2243 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
2246 if (V.getOpcode() == ISD::BIT_CONVERT) {
2247 V = V.getOperand(0);
2248 MVT VVT = V.getValueType();
2249 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
2252 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
2253 return (Index == 0) ? V.getOperand(0)
2254 : getUNDEF(VT.getVectorElementType());
2255 if (V.getOpcode() == ISD::BUILD_VECTOR)
2256 return V.getOperand(Index);
2257 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V))
2258 return getShuffleScalarElt(SVN, Index);
2263 /// getNode - Gets or creates the specified node.
2265 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
2266 FoldingSetNodeID ID;
2267 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
2269 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2270 return SDValue(E, 0);
2271 SDNode *N = NodeAllocator.Allocate<SDNode>();
2272 new (N) SDNode(Opcode, DL, getVTList(VT));
2273 CSEMap.InsertNode(N, IP);
2275 AllNodes.push_back(N);
2279 return SDValue(N, 0);
2282 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
2283 MVT VT, SDValue Operand) {
2284 // Constant fold unary operations with an integer constant operand.
2285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
2286 const APInt &Val = C->getAPIntValue();
2287 unsigned BitWidth = VT.getSizeInBits();
2290 case ISD::SIGN_EXTEND:
2291 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT);
2292 case ISD::ANY_EXTEND:
2293 case ISD::ZERO_EXTEND:
2295 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT);
2296 case ISD::UINT_TO_FP:
2297 case ISD::SINT_TO_FP: {
2298 const uint64_t zero[] = {0, 0};
2299 // No compile time operations on this type.
2300 if (VT==MVT::ppcf128)
2302 APFloat apf = APFloat(APInt(BitWidth, 2, zero));
2303 (void)apf.convertFromAPInt(Val,
2304 Opcode==ISD::SINT_TO_FP,
2305 APFloat::rmNearestTiesToEven);
2306 return getConstantFP(apf, VT);
2308 case ISD::BIT_CONVERT:
2309 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
2310 return getConstantFP(Val.bitsToFloat(), VT);
2311 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
2312 return getConstantFP(Val.bitsToDouble(), VT);
2315 return getConstant(Val.byteSwap(), VT);
2317 return getConstant(Val.countPopulation(), VT);
2319 return getConstant(Val.countLeadingZeros(), VT);
2321 return getConstant(Val.countTrailingZeros(), VT);
2325 // Constant fold unary operations with a floating point constant operand.
2326 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
2327 APFloat V = C->getValueAPF(); // make copy
2328 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
2332 return getConstantFP(V, VT);
2335 return getConstantFP(V, VT);
2337 case ISD::FP_EXTEND: {
2339 // This can return overflow, underflow, or inexact; we don't care.
2340 // FIXME need to be more flexible about rounding mode.
2341 (void)V.convert(*MVTToAPFloatSemantics(VT),
2342 APFloat::rmNearestTiesToEven, &ignored);
2343 return getConstantFP(V, VT);
2345 case ISD::FP_TO_SINT:
2346 case ISD::FP_TO_UINT: {
2349 assert(integerPartWidth >= 64);
2350 // FIXME need to be more flexible about rounding mode.
2351 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(),
2352 Opcode==ISD::FP_TO_SINT,
2353 APFloat::rmTowardZero, &ignored);
2354 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual
2356 APInt api(VT.getSizeInBits(), 2, x);
2357 return getConstant(api, VT);
2359 case ISD::BIT_CONVERT:
2360 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
2361 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
2362 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
2363 return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
2369 unsigned OpOpcode = Operand.getNode()->getOpcode();
2371 case ISD::TokenFactor:
2372 case ISD::MERGE_VALUES:
2373 case ISD::CONCAT_VECTORS:
2374 return Operand; // Factor, merge or concat of one node? No need.
2375 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
2376 case ISD::FP_EXTEND:
2377 assert(VT.isFloatingPoint() &&
2378 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
2379 if (Operand.getValueType() == VT) return Operand; // noop conversion.
2380 if (Operand.getOpcode() == ISD::UNDEF)
2381 return getUNDEF(VT);
2383 case ISD::SIGN_EXTEND:
2384 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2385 "Invalid SIGN_EXTEND!");
2386 if (Operand.getValueType() == VT) return Operand; // noop extension
2387 assert(Operand.getValueType().bitsLT(VT)
2388 && "Invalid sext node, dst < src!");
2389 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2390 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2392 case ISD::ZERO_EXTEND:
2393 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2394 "Invalid ZERO_EXTEND!");
2395 if (Operand.getValueType() == VT) return Operand; // noop extension
2396 assert(Operand.getValueType().bitsLT(VT)
2397 && "Invalid zext node, dst < src!");
2398 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2399 return getNode(ISD::ZERO_EXTEND, DL, VT,
2400 Operand.getNode()->getOperand(0));
2402 case ISD::ANY_EXTEND:
2403 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2404 "Invalid ANY_EXTEND!");
2405 if (Operand.getValueType() == VT) return Operand; // noop extension
2406 assert(Operand.getValueType().bitsLT(VT)
2407 && "Invalid anyext node, dst < src!");
2408 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
2409 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
2410 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2413 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2414 "Invalid TRUNCATE!");
2415 if (Operand.getValueType() == VT) return Operand; // noop truncate
2416 assert(Operand.getValueType().bitsGT(VT)
2417 && "Invalid truncate node, src < dst!");
2418 if (OpOpcode == ISD::TRUNCATE)
2419 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2420 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2421 OpOpcode == ISD::ANY_EXTEND) {
2422 // If the source is smaller than the dest, we still need an extend.
2423 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
2424 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2425 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
2426 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2428 return Operand.getNode()->getOperand(0);
2431 case ISD::BIT_CONVERT:
2432 // Basic sanity checking.
2433 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits()
2434 && "Cannot BIT_CONVERT between types of different sizes!");
2435 if (VT == Operand.getValueType()) return Operand; // noop conversion.
2436 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
2437 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
2438 if (OpOpcode == ISD::UNDEF)
2439 return getUNDEF(VT);
2441 case ISD::SCALAR_TO_VECTOR:
2442 assert(VT.isVector() && !Operand.getValueType().isVector() &&
2443 (VT.getVectorElementType() == Operand.getValueType() ||
2444 (VT.getVectorElementType().isInteger() &&
2445 Operand.getValueType().isInteger() &&
2446 VT.getVectorElementType().bitsLE(Operand.getValueType()))) &&
2447 "Illegal SCALAR_TO_VECTOR node!");
2448 if (OpOpcode == ISD::UNDEF)
2449 return getUNDEF(VT);
2450 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
2451 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2452 isa<ConstantSDNode>(Operand.getOperand(1)) &&
2453 Operand.getConstantOperandVal(1) == 0 &&
2454 Operand.getOperand(0).getValueType() == VT)
2455 return Operand.getOperand(0);
2458 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
2459 if (UnsafeFPMath && OpOpcode == ISD::FSUB)
2460 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2461 Operand.getNode()->getOperand(0));
2462 if (OpOpcode == ISD::FNEG) // --X -> X
2463 return Operand.getNode()->getOperand(0);
2466 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2467 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
2472 SDVTList VTs = getVTList(VT);
2473 if (VT != MVT::Flag) { // Don't CSE flag producing nodes
2474 FoldingSetNodeID ID;
2475 SDValue Ops[1] = { Operand };
2476 AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
2478 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2479 return SDValue(E, 0);
2480 N = NodeAllocator.Allocate<UnarySDNode>();
2481 new (N) UnarySDNode(Opcode, DL, VTs, Operand);
2482 CSEMap.InsertNode(N, IP);
2484 N = NodeAllocator.Allocate<UnarySDNode>();
2485 new (N) UnarySDNode(Opcode, DL, VTs, Operand);
2488 AllNodes.push_back(N);
2492 return SDValue(N, 0);
2495 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode,
2497 ConstantSDNode *Cst1,
2498 ConstantSDNode *Cst2) {
2499 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue();
2502 case ISD::ADD: return getConstant(C1 + C2, VT);
2503 case ISD::SUB: return getConstant(C1 - C2, VT);
2504 case ISD::MUL: return getConstant(C1 * C2, VT);
2506 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT);
2509 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT);
2512 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT);
2515 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT);
2517 case ISD::AND: return getConstant(C1 & C2, VT);
2518 case ISD::OR: return getConstant(C1 | C2, VT);
2519 case ISD::XOR: return getConstant(C1 ^ C2, VT);
2520 case ISD::SHL: return getConstant(C1 << C2, VT);
2521 case ISD::SRL: return getConstant(C1.lshr(C2), VT);
2522 case ISD::SRA: return getConstant(C1.ashr(C2), VT);
2523 case ISD::ROTL: return getConstant(C1.rotl(C2), VT);
2524 case ISD::ROTR: return getConstant(C1.rotr(C2), VT);
2531 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2532 SDValue N1, SDValue N2) {
2533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2534 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2537 case ISD::TokenFactor:
2538 assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
2539 N2.getValueType() == MVT::Other && "Invalid token factor!");
2540 // Fold trivial token factors.
2541 if (N1.getOpcode() == ISD::EntryToken) return N2;
2542 if (N2.getOpcode() == ISD::EntryToken) return N1;
2543 if (N1 == N2) return N1;
2545 case ISD::CONCAT_VECTORS:
2546 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2547 // one big BUILD_VECTOR.
2548 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2549 N2.getOpcode() == ISD::BUILD_VECTOR) {
2550 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2551 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2552 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2556 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2557 N1.getValueType() == VT && "Binary operator types must match!");
2558 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
2559 // worth handling here.
2560 if (N2C && N2C->isNullValue())
2562 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X
2569 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2570 N1.getValueType() == VT && "Binary operator types must match!");
2571 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so
2572 // it's worth handling here.
2573 if (N2C && N2C->isNullValue())
2583 assert(VT.isInteger() && "This operator does not apply to FP types!");
2591 if (Opcode == ISD::FADD) {
2593 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1))
2594 if (CFP->getValueAPF().isZero())
2597 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2))
2598 if (CFP->getValueAPF().isZero())
2600 } else if (Opcode == ISD::FSUB) {
2602 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2))
2603 if (CFP->getValueAPF().isZero())
2607 assert(N1.getValueType() == N2.getValueType() &&
2608 N1.getValueType() == VT && "Binary operator types must match!");
2610 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2611 assert(N1.getValueType() == VT &&
2612 N1.getValueType().isFloatingPoint() &&
2613 N2.getValueType().isFloatingPoint() &&
2614 "Invalid FCOPYSIGN!");
2621 assert(VT == N1.getValueType() &&
2622 "Shift operators return type must be the same as their first arg");
2623 assert(VT.isInteger() && N2.getValueType().isInteger() &&
2624 "Shifts only work on integers");
2626 // Always fold shifts of i1 values so the code generator doesn't need to
2627 // handle them. Since we know the size of the shift has to be less than the
2628 // size of the value, the shift/rotate count is guaranteed to be zero.
2632 case ISD::FP_ROUND_INREG: {
2633 MVT EVT = cast<VTSDNode>(N2)->getVT();
2634 assert(VT == N1.getValueType() && "Not an inreg round!");
2635 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
2636 "Cannot FP_ROUND_INREG integer types");
2637 assert(EVT.bitsLE(VT) && "Not rounding down!");
2638 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
2642 assert(VT.isFloatingPoint() &&
2643 N1.getValueType().isFloatingPoint() &&
2644 VT.bitsLE(N1.getValueType()) &&
2645 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
2646 if (N1.getValueType() == VT) return N1; // noop conversion.
2648 case ISD::AssertSext:
2649 case ISD::AssertZext: {
2650 MVT EVT = cast<VTSDNode>(N2)->getVT();
2651 assert(VT == N1.getValueType() && "Not an inreg extend!");
2652 assert(VT.isInteger() && EVT.isInteger() &&
2653 "Cannot *_EXTEND_INREG FP types");
2654 assert(EVT.bitsLE(VT) && "Not extending!");
2655 if (VT == EVT) return N1; // noop assertion.
2658 case ISD::SIGN_EXTEND_INREG: {
2659 MVT EVT = cast<VTSDNode>(N2)->getVT();
2660 assert(VT == N1.getValueType() && "Not an inreg extend!");
2661 assert(VT.isInteger() && EVT.isInteger() &&
2662 "Cannot *_EXTEND_INREG FP types");
2663 assert(EVT.bitsLE(VT) && "Not extending!");
2664 if (EVT == VT) return N1; // Not actually extending
2667 APInt Val = N1C->getAPIntValue();
2668 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits();
2669 Val <<= Val.getBitWidth()-FromBits;
2670 Val = Val.ashr(Val.getBitWidth()-FromBits);
2671 return getConstant(Val, VT);
2675 case ISD::EXTRACT_VECTOR_ELT:
2676 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
2677 if (N1.getOpcode() == ISD::UNDEF)
2678 return getUNDEF(VT);
2680 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
2681 // expanding copies of large vectors from registers.
2683 N1.getOpcode() == ISD::CONCAT_VECTORS &&
2684 N1.getNumOperands() > 0) {
2686 N1.getOperand(0).getValueType().getVectorNumElements();
2687 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
2688 N1.getOperand(N2C->getZExtValue() / Factor),
2689 getConstant(N2C->getZExtValue() % Factor,
2690 N2.getValueType()));
2693 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
2694 // expanding large vector constants.
2695 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
2696 SDValue Elt = N1.getOperand(N2C->getZExtValue());
2697 MVT VEltTy = N1.getValueType().getVectorElementType();
2698 if (Elt.getValueType() != VEltTy) {
2699 // If the vector element type is not legal, the BUILD_VECTOR operands
2700 // are promoted and implicitly truncated. Make that explicit here.
2701 Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt);
2704 // If the vector element type is not legal, the EXTRACT_VECTOR_ELT
2705 // result is implicitly extended.
2706 Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt);
2711 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
2712 // operations are lowered to scalars.
2713 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
2714 // If the indices are the same, return the inserted element.
2715 if (N1.getOperand(2) == N2)
2716 return N1.getOperand(1);
2717 // If the indices are known different, extract the element from
2718 // the original vector.
2719 else if (isa<ConstantSDNode>(N1.getOperand(2)) &&
2720 isa<ConstantSDNode>(N2))
2721 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
2724 case ISD::EXTRACT_ELEMENT:
2725 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
2726 assert(!N1.getValueType().isVector() && !VT.isVector() &&
2727 (N1.getValueType().isInteger() == VT.isInteger()) &&
2728 "Wrong types for EXTRACT_ELEMENT!");
2730 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
2731 // 64-bit integers into 32-bit parts. Instead of building the extract of
2732 // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
2733 if (N1.getOpcode() == ISD::BUILD_PAIR)
2734 return N1.getOperand(N2C->getZExtValue());
2736 // EXTRACT_ELEMENT of a constant int is also very common.
2737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2738 unsigned ElementSize = VT.getSizeInBits();
2739 unsigned Shift = ElementSize * N2C->getZExtValue();
2740 APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
2741 return getConstant(ShiftedVal.trunc(ElementSize), VT);
2744 case ISD::EXTRACT_SUBVECTOR:
2745 if (N1.getValueType() == VT) // Trivial extraction.
2752 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C);
2753 if (SV.getNode()) return SV;
2754 } else { // Cannonicalize constant to RHS if commutative
2755 if (isCommutativeBinOp(Opcode)) {
2756 std::swap(N1C, N2C);
2762 // Constant fold FP operations.
2763 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
2764 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
2766 if (!N2CFP && isCommutativeBinOp(Opcode)) {
2767 // Cannonicalize constant to RHS if commutative
2768 std::swap(N1CFP, N2CFP);
2770 } else if (N2CFP && VT != MVT::ppcf128) {
2771 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
2772 APFloat::opStatus s;
2775 s = V1.add(V2, APFloat::rmNearestTiesToEven);
2776 if (s != APFloat::opInvalidOp)
2777 return getConstantFP(V1, VT);
2780 s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
2781 if (s!=APFloat::opInvalidOp)
2782 return getConstantFP(V1, VT);
2785 s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
2786 if (s!=APFloat::opInvalidOp)
2787 return getConstantFP(V1, VT);
2790 s = V1.divide(V2, APFloat::rmNearestTiesToEven);
2791 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2792 return getConstantFP(V1, VT);
2795 s = V1.mod(V2, APFloat::rmNearestTiesToEven);
2796 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2797 return getConstantFP(V1, VT);
2799 case ISD::FCOPYSIGN:
2801 return getConstantFP(V1, VT);
2807 // Canonicalize an UNDEF to the RHS, even over a constant.
2808 if (N1.getOpcode() == ISD::UNDEF) {
2809 if (isCommutativeBinOp(Opcode)) {
2813 case ISD::FP_ROUND_INREG:
2814 case ISD::SIGN_EXTEND_INREG:
2820 return N1; // fold op(undef, arg2) -> undef
2828 return getConstant(0, VT); // fold op(undef, arg2) -> 0
2829 // For vectors, we can't easily build an all zero vector, just return
2836 // Fold a bunch of operators when the RHS is undef.
2837 if (N2.getOpcode() == ISD::UNDEF) {
2840 if (N1.getOpcode() == ISD::UNDEF)
2841 // Handle undef ^ undef -> 0 special case. This is a common
2843 return getConstant(0, VT);
2853 return N2; // fold op(arg1, undef) -> undef
2867 return getConstant(0, VT); // fold op(arg1, undef) -> 0
2868 // For vectors, we can't easily build an all zero vector, just return
2873 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
2874 // For vectors, we can't easily build an all one vector, just return
2882 // Memoize this node if possible.
2884 SDVTList VTs = getVTList(VT);
2885 if (VT != MVT::Flag) {
2886 SDValue Ops[] = { N1, N2 };
2887 FoldingSetNodeID ID;
2888 AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
2890 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2891 return SDValue(E, 0);
2892 N = NodeAllocator.Allocate<BinarySDNode>();
2893 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
2894 CSEMap.InsertNode(N, IP);
2896 N = NodeAllocator.Allocate<BinarySDNode>();
2897 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
2900 AllNodes.push_back(N);
2904 return SDValue(N, 0);
2907 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2908 SDValue N1, SDValue N2, SDValue N3) {
2909 // Perform various simplifications.
2910 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2911 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2913 case ISD::CONCAT_VECTORS:
2914 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2915 // one big BUILD_VECTOR.
2916 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2917 N2.getOpcode() == ISD::BUILD_VECTOR &&
2918 N3.getOpcode() == ISD::BUILD_VECTOR) {
2919 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2920 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2921 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end());
2922 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2926 // Use FoldSetCC to simplify SETCC's.
2927 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL);
2928 if (Simp.getNode()) return Simp;
2933 if (N1C->getZExtValue())
2934 return N2; // select true, X, Y -> X
2936 return N3; // select false, X, Y -> Y
2939 if (N2 == N3) return N2; // select C, X, X -> X
2943 if (N2C->getZExtValue()) // Unconditional branch
2944 return getNode(ISD::BR, DL, MVT::Other, N1, N3);
2946 return N1; // Never-taken branch
2949 case ISD::VECTOR_SHUFFLE:
2950 llvm_unreachable("should use getVectorShuffle constructor!");
2952 case ISD::BIT_CONVERT:
2953 // Fold bit_convert nodes from a type to themselves.
2954 if (N1.getValueType() == VT)
2959 // Memoize node if it doesn't produce a flag.
2961 SDVTList VTs = getVTList(VT);
2962 if (VT != MVT::Flag) {
2963 SDValue Ops[] = { N1, N2, N3 };
2964 FoldingSetNodeID ID;
2965 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
2967 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2968 return SDValue(E, 0);
2969 N = NodeAllocator.Allocate<TernarySDNode>();
2970 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
2971 CSEMap.InsertNode(N, IP);
2973 N = NodeAllocator.Allocate<TernarySDNode>();
2974 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
2976 AllNodes.push_back(N);
2980 return SDValue(N, 0);
2983 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2984 SDValue N1, SDValue N2, SDValue N3,
2986 SDValue Ops[] = { N1, N2, N3, N4 };
2987 return getNode(Opcode, DL, VT, Ops, 4);
2990 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2991 SDValue N1, SDValue N2, SDValue N3,
2992 SDValue N4, SDValue N5) {
2993 SDValue Ops[] = { N1, N2, N3, N4, N5 };
2994 return getNode(Opcode, DL, VT, Ops, 5);
2997 /// getMemsetValue - Vectorized representation of the memset value
2999 static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
3001 unsigned NumBits = VT.isVector() ?
3002 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
3003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
3004 APInt Val = APInt(NumBits, C->getZExtValue() & 255);
3006 for (unsigned i = NumBits; i > 8; i >>= 1) {
3007 Val = (Val << Shift) | Val;
3011 return DAG.getConstant(Val, VT);
3012 return DAG.getConstantFP(APFloat(Val), VT);
3015 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3016 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
3018 for (unsigned i = NumBits; i > 8; i >>= 1) {
3019 Value = DAG.getNode(ISD::OR, dl, VT,
3020 DAG.getNode(ISD::SHL, dl, VT, Value,
3021 DAG.getConstant(Shift,
3022 TLI.getShiftAmountTy())),
3030 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
3031 /// used when a memcpy is turned into a memset when the source is a constant
3033 static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
3034 const TargetLowering &TLI,
3035 std::string &Str, unsigned Offset) {
3036 // Handle vector with all elements zero.
3039 return DAG.getConstant(0, VT);
3040 unsigned NumElts = VT.getVectorNumElements();
3041 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
3042 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3043 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
3046 assert(!VT.isVector() && "Can't handle vector type here!");
3047 unsigned NumBits = VT.getSizeInBits();
3048 unsigned MSB = NumBits / 8;
3050 if (TLI.isLittleEndian())
3051 Offset = Offset + MSB - 1;
3052 for (unsigned i = 0; i != MSB; ++i) {
3053 Val = (Val << 8) | (unsigned char)Str[Offset];
3054 Offset += TLI.isLittleEndian() ? -1 : 1;
3056 return DAG.getConstant(Val, VT);
3059 /// getMemBasePlusOffset - Returns base and offset node for the
3061 static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
3062 SelectionDAG &DAG) {
3063 MVT VT = Base.getValueType();
3064 return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
3065 VT, Base, DAG.getConstant(Offset, VT));
3068 /// isMemSrcFromString - Returns true if memcpy source is a string constant.
3070 static bool isMemSrcFromString(SDValue Src, std::string &Str) {
3071 unsigned SrcDelta = 0;
3072 GlobalAddressSDNode *G = NULL;
3073 if (Src.getOpcode() == ISD::GlobalAddress)
3074 G = cast<GlobalAddressSDNode>(Src);
3075 else if (Src.getOpcode() == ISD::ADD &&
3076 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3077 Src.getOperand(1).getOpcode() == ISD::Constant) {
3078 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
3079 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
3084 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3085 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false))
3091 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3092 /// to replace the memset / memcpy is below the threshold. It also returns the
3093 /// types of the sequence of memory ops to perform memset / memcpy.
3095 bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
3096 SDValue Dst, SDValue Src,
3097 unsigned Limit, uint64_t Size, unsigned &Align,
3098 std::string &Str, bool &isSrcStr,
3100 const TargetLowering &TLI) {
3101 isSrcStr = isMemSrcFromString(Src, Str);
3102 bool isSrcConst = isa<ConstantSDNode>(Src);
3103 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
3104 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
3105 if (VT != MVT::iAny) {
3106 unsigned NewAlign = (unsigned)
3107 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT(
3108 *DAG.getContext()));
3109 // If source is a string constant, this will require an unaligned load.
3110 if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
3111 if (Dst.getOpcode() != ISD::FrameIndex) {
3112 // Can't change destination alignment. It requires a unaligned store.
3116 int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
3117 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3118 if (MFI->isFixedObjectIndex(FI)) {
3119 // Can't change destination alignment. It requires a unaligned store.
3123 // Give the stack frame object a larger alignment if needed.
3124 if (MFI->getObjectAlignment(FI) < NewAlign)
3125 MFI->setObjectAlignment(FI, NewAlign);
3132 if (VT == MVT::iAny) {
3136 switch (Align & 7) {
3137 case 0: VT = MVT::i64; break;
3138 case 4: VT = MVT::i32; break;
3139 case 2: VT = MVT::i16; break;
3140 default: VT = MVT::i8; break;
3145 while (!TLI.isTypeLegal(LVT))
3146 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
3147 assert(LVT.isInteger());
3153 unsigned NumMemOps = 0;
3155 unsigned VTSize = VT.getSizeInBits() / 8;
3156 while (VTSize > Size) {
3157 // For now, only use non-vector load / store's for the left-over pieces.
3158 if (VT.isVector()) {
3160 while (!TLI.isTypeLegal(VT))
3161 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
3162 VTSize = VT.getSizeInBits() / 8;
3164 // This can result in a type that is not legal on the target, e.g.
3165 // 1 or 2 bytes on PPC.
3166 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
3171 if (++NumMemOps > Limit)
3173 MemOps.push_back(VT);
3180 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
3181 SDValue Chain, SDValue Dst,
3182 SDValue Src, uint64_t Size,
3183 unsigned Align, bool AlwaysInline,
3184 const Value *DstSV, uint64_t DstSVOff,
3185 const Value *SrcSV, uint64_t SrcSVOff){
3186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3188 // Expand memcpy to a series of load and store ops if the size operand falls
3189 // below a certain threshold.
3190 std::vector<MVT> MemOps;
3191 uint64_t Limit = -1ULL;
3193 Limit = TLI.getMaxStoresPerMemcpy();
3194 unsigned DstAlign = Align; // Destination alignment can change.
3197 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3198 Str, CopyFromStr, DAG, TLI))
3202 bool isZeroStr = CopyFromStr && Str.empty();
3203 SmallVector<SDValue, 8> OutChains;
3204 unsigned NumMemOps = MemOps.size();
3205 uint64_t SrcOff = 0, DstOff = 0;
3206 for (unsigned i = 0; i < NumMemOps; i++) {
3208 unsigned VTSize = VT.getSizeInBits() / 8;
3209 SDValue Value, Store;
3211 if (CopyFromStr && (isZeroStr || !VT.isVector())) {
3212 // It's unlikely a store of a vector immediate can be done in a single
3213 // instruction. It would require a load from a constantpool first.
3214 // We also handle store a vector with all zero's.
3215 // FIXME: Handle other cases where store of vector immediate is done in
3216 // a single instruction.
3217 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff);
3218 Store = DAG.getStore(Chain, dl, Value,
3219 getMemBasePlusOffset(Dst, DstOff, DAG),
3220 DstSV, DstSVOff + DstOff, false, DstAlign);
3222 // The type might not be legal for the target. This should only happen
3223 // if the type is smaller than a legal type, as on PPC, so the right
3224 // thing to do is generate a LoadExt/StoreTrunc pair. These simplify
3225 // to Load/Store if NVT==VT.
3226 // FIXME does the case above also need this?
3227 MVT NVT = TLI.getTypeToTransformTo(VT);
3228 assert(NVT.bitsGE(VT));
3229 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
3230 getMemBasePlusOffset(Src, SrcOff, DAG),
3231 SrcSV, SrcSVOff + SrcOff, VT, false, Align);
3232 Store = DAG.getTruncStore(Chain, dl, Value,
3233 getMemBasePlusOffset(Dst, DstOff, DAG),
3234 DstSV, DstSVOff + DstOff, VT, false, DstAlign);
3236 OutChains.push_back(Store);
3241 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3242 &OutChains[0], OutChains.size());
3245 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
3246 SDValue Chain, SDValue Dst,
3247 SDValue Src, uint64_t Size,
3248 unsigned Align, bool AlwaysInline,
3249 const Value *DstSV, uint64_t DstSVOff,
3250 const Value *SrcSV, uint64_t SrcSVOff){
3251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3253 // Expand memmove to a series of load and store ops if the size operand falls
3254 // below a certain threshold.
3255 std::vector<MVT> MemOps;
3256 uint64_t Limit = -1ULL;
3258 Limit = TLI.getMaxStoresPerMemmove();
3259 unsigned DstAlign = Align; // Destination alignment can change.
3262 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3263 Str, CopyFromStr, DAG, TLI))
3266 uint64_t SrcOff = 0, DstOff = 0;
3268 SmallVector<SDValue, 8> LoadValues;
3269 SmallVector<SDValue, 8> LoadChains;
3270 SmallVector<SDValue, 8> OutChains;
3271 unsigned NumMemOps = MemOps.size();
3272 for (unsigned i = 0; i < NumMemOps; i++) {
3274 unsigned VTSize = VT.getSizeInBits() / 8;
3275 SDValue Value, Store;
3277 Value = DAG.getLoad(VT, dl, Chain,
3278 getMemBasePlusOffset(Src, SrcOff, DAG),
3279 SrcSV, SrcSVOff + SrcOff, false, Align);
3280 LoadValues.push_back(Value);
3281 LoadChains.push_back(Value.getValue(1));
3284 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3285 &LoadChains[0], LoadChains.size());
3287 for (unsigned i = 0; i < NumMemOps; i++) {
3289 unsigned VTSize = VT.getSizeInBits() / 8;
3290 SDValue Value, Store;
3292 Store = DAG.getStore(Chain, dl, LoadValues[i],
3293 getMemBasePlusOffset(Dst, DstOff, DAG),
3294 DstSV, DstSVOff + DstOff, false, DstAlign);
3295 OutChains.push_back(Store);
3299 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3300 &OutChains[0], OutChains.size());
3303 static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl,
3304 SDValue Chain, SDValue Dst,
3305 SDValue Src, uint64_t Size,
3307 const Value *DstSV, uint64_t DstSVOff) {
3308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3310 // Expand memset to a series of load/store ops if the size operand
3311 // falls below a certain threshold.
3312 std::vector<MVT> MemOps;
3315 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
3316 Size, Align, Str, CopyFromStr, DAG, TLI))
3319 SmallVector<SDValue, 8> OutChains;
3320 uint64_t DstOff = 0;
3322 unsigned NumMemOps = MemOps.size();
3323 for (unsigned i = 0; i < NumMemOps; i++) {
3325 unsigned VTSize = VT.getSizeInBits() / 8;
3326 SDValue Value = getMemsetValue(Src, VT, DAG, dl);
3327 SDValue Store = DAG.getStore(Chain, dl, Value,
3328 getMemBasePlusOffset(Dst, DstOff, DAG),
3329 DstSV, DstSVOff + DstOff);
3330 OutChains.push_back(Store);
3334 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3335 &OutChains[0], OutChains.size());
3338 SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
3339 SDValue Src, SDValue Size,
3340 unsigned Align, bool AlwaysInline,
3341 const Value *DstSV, uint64_t DstSVOff,
3342 const Value *SrcSV, uint64_t SrcSVOff) {
3344 // Check to see if we should lower the memcpy to loads and stores first.
3345 // For cases within the target-specified limits, this is the best choice.
3346 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3348 // Memcpy with size zero? Just return the original chain.
3349 if (ConstantSize->isNullValue())
3353 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
3354 ConstantSize->getZExtValue(),
3355 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3356 if (Result.getNode())
3360 // Then check to see if we should lower the memcpy with target-specific
3361 // code. If the target chooses to do this, this is the next best.
3363 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align,
3365 DstSV, DstSVOff, SrcSV, SrcSVOff);
3366 if (Result.getNode())
3369 // If we really need inline code and the target declined to provide it,
3370 // use a (potentially long) sequence of loads and stores.
3372 assert(ConstantSize && "AlwaysInline requires a constant size!");
3373 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
3374 ConstantSize->getZExtValue(), Align, true,
3375 DstSV, DstSVOff, SrcSV, SrcSVOff);
3378 // Emit a library call.
3379 TargetLowering::ArgListTy Args;
3380 TargetLowering::ArgListEntry Entry;
3381 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3382 Entry.Node = Dst; Args.push_back(Entry);
3383 Entry.Node = Src; Args.push_back(Entry);
3384 Entry.Node = Size; Args.push_back(Entry);
3385 // FIXME: pass in DebugLoc
3386 std::pair<SDValue,SDValue> CallResult =
3387 TLI.LowerCallTo(Chain, Type::VoidTy,
3388 false, false, false, false, 0, CallingConv::C, false,
3389 getExternalSymbol("memcpy", TLI.getPointerTy()),
3391 return CallResult.second;
3394 SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
3395 SDValue Src, SDValue Size,
3397 const Value *DstSV, uint64_t DstSVOff,
3398 const Value *SrcSV, uint64_t SrcSVOff) {
3400 // Check to see if we should lower the memmove to loads and stores first.
3401 // For cases within the target-specified limits, this is the best choice.
3402 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3404 // Memmove with size zero? Just return the original chain.
3405 if (ConstantSize->isNullValue())
3409 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src,
3410 ConstantSize->getZExtValue(),
3411 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3412 if (Result.getNode())
3416 // Then check to see if we should lower the memmove with target-specific
3417 // code. If the target chooses to do this, this is the next best.
3419 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align,
3420 DstSV, DstSVOff, SrcSV, SrcSVOff);
3421 if (Result.getNode())
3424 // Emit a library call.
3425 TargetLowering::ArgListTy Args;
3426 TargetLowering::ArgListEntry Entry;
3427 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3428 Entry.Node = Dst; Args.push_back(Entry);
3429 Entry.Node = Src; Args.push_back(Entry);
3430 Entry.Node = Size; Args.push_back(Entry);
3431 // FIXME: pass in DebugLoc
3432 std::pair<SDValue,SDValue> CallResult =
3433 TLI.LowerCallTo(Chain, Type::VoidTy,
3434 false, false, false, false, 0, CallingConv::C, false,
3435 getExternalSymbol("memmove", TLI.getPointerTy()),
3437 return CallResult.second;
3440 SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
3441 SDValue Src, SDValue Size,
3443 const Value *DstSV, uint64_t DstSVOff) {
3445 // Check to see if we should lower the memset to stores first.
3446 // For cases within the target-specified limits, this is the best choice.
3447 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3449 // Memset with size zero? Just return the original chain.
3450 if (ConstantSize->isNullValue())
3454 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
3455 Align, DstSV, DstSVOff);
3456 if (Result.getNode())
3460 // Then check to see if we should lower the memset with target-specific
3461 // code. If the target chooses to do this, this is the next best.
3463 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align,
3465 if (Result.getNode())
3468 // Emit a library call.
3469 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
3470 TargetLowering::ArgListTy Args;
3471 TargetLowering::ArgListEntry Entry;
3472 Entry.Node = Dst; Entry.Ty = IntPtrTy;
3473 Args.push_back(Entry);
3474 // Extend or truncate the argument to be an i32 value for the call.
3475 if (Src.getValueType().bitsGT(MVT::i32))
3476 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
3478 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
3479 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
3480 Args.push_back(Entry);
3481 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
3482 Args.push_back(Entry);
3483 // FIXME: pass in DebugLoc
3484 std::pair<SDValue,SDValue> CallResult =
3485 TLI.LowerCallTo(Chain, Type::VoidTy,
3486 false, false, false, false, 0, CallingConv::C, false,
3487 getExternalSymbol("memset", TLI.getPointerTy()),
3489 return CallResult.second;
3492 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
3494 SDValue Ptr, SDValue Cmp,
3495 SDValue Swp, const Value* PtrVal,
3496 unsigned Alignment) {
3497 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
3498 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
3500 MVT VT = Cmp.getValueType();
3502 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3503 Alignment = getMVTAlignment(MemVT);
3505 SDVTList VTs = getVTList(VT, MVT::Other);
3506 FoldingSetNodeID ID;
3507 ID.AddInteger(MemVT.getRawBits());
3508 SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
3509 AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
3511 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3512 return SDValue(E, 0);
3513 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3514 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
3515 Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
3516 CSEMap.InsertNode(N, IP);
3517 AllNodes.push_back(N);
3518 return SDValue(N, 0);
3521 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
3523 SDValue Ptr, SDValue Val,
3524 const Value* PtrVal,
3525 unsigned Alignment) {
3526 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
3527 Opcode == ISD::ATOMIC_LOAD_SUB ||
3528 Opcode == ISD::ATOMIC_LOAD_AND ||
3529 Opcode == ISD::ATOMIC_LOAD_OR ||
3530 Opcode == ISD::ATOMIC_LOAD_XOR ||
3531 Opcode == ISD::ATOMIC_LOAD_NAND ||
3532 Opcode == ISD::ATOMIC_LOAD_MIN ||
3533 Opcode == ISD::ATOMIC_LOAD_MAX ||
3534 Opcode == ISD::ATOMIC_LOAD_UMIN ||
3535 Opcode == ISD::ATOMIC_LOAD_UMAX ||
3536 Opcode == ISD::ATOMIC_SWAP) &&
3537 "Invalid Atomic Op");
3539 MVT VT = Val.getValueType();
3541 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3542 Alignment = getMVTAlignment(MemVT);
3544 SDVTList VTs = getVTList(VT, MVT::Other);
3545 FoldingSetNodeID ID;
3546 ID.AddInteger(MemVT.getRawBits());
3547 SDValue Ops[] = {Chain, Ptr, Val};
3548 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
3550 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3551 return SDValue(E, 0);
3552 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3553 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
3554 Chain, Ptr, Val, PtrVal, Alignment);
3555 CSEMap.InsertNode(N, IP);
3556 AllNodes.push_back(N);
3557 return SDValue(N, 0);
3560 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
3561 /// Allowed to return something different (and simpler) if Simplify is true.
3562 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
3567 SmallVector<MVT, 4> VTs;
3568 VTs.reserve(NumOps);
3569 for (unsigned i = 0; i < NumOps; ++i)
3570 VTs.push_back(Ops[i].getValueType());
3571 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
3576 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
3577 const MVT *VTs, unsigned NumVTs,
3578 const SDValue *Ops, unsigned NumOps,
3579 MVT MemVT, const Value *srcValue, int SVOff,
3580 unsigned Align, bool Vol,
3581 bool ReadMem, bool WriteMem) {
3582 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
3583 MemVT, srcValue, SVOff, Align, Vol,
3588 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
3589 const SDValue *Ops, unsigned NumOps,
3590 MVT MemVT, const Value *srcValue, int SVOff,
3591 unsigned Align, bool Vol,
3592 bool ReadMem, bool WriteMem) {
3593 // Memoize the node unless it returns a flag.
3594 MemIntrinsicSDNode *N;
3595 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3596 FoldingSetNodeID ID;
3597 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3599 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3600 return SDValue(E, 0);
3602 N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
3603 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
3604 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
3605 CSEMap.InsertNode(N, IP);
3607 N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
3608 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
3609 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
3611 AllNodes.push_back(N);
3612 return SDValue(N, 0);
3616 SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
3617 bool IsTailCall, bool IsInreg, SDVTList VTs,
3618 const SDValue *Operands, unsigned NumOperands,
3619 unsigned NumFixedArgs) {
3620 // Do not include isTailCall in the folding set profile.
3621 FoldingSetNodeID ID;
3622 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
3623 ID.AddInteger(CallingConv);
3624 ID.AddInteger(IsVarArgs);
3626 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
3627 // Instead of including isTailCall in the folding set, we just
3628 // set the flag of the existing node.
3630 cast<CallSDNode>(E)->setNotTailCall();
3631 return SDValue(E, 0);
3633 SDNode *N = NodeAllocator.Allocate<CallSDNode>();
3634 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg,
3635 VTs, Operands, NumOperands, NumFixedArgs);
3636 CSEMap.InsertNode(N, IP);
3637 AllNodes.push_back(N);
3638 return SDValue(N, 0);
3642 SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
3643 ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
3644 SDValue Ptr, SDValue Offset,
3645 const Value *SV, int SVOffset, MVT EVT,
3646 bool isVolatile, unsigned Alignment) {
3647 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3648 Alignment = getMVTAlignment(VT);
3651 ExtType = ISD::NON_EXTLOAD;
3652 } else if (ExtType == ISD::NON_EXTLOAD) {
3653 assert(VT == EVT && "Non-extending load from different memory type!");
3657 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
3658 "Invalid vector extload!");
3660 assert(EVT.bitsLT(VT) &&
3661 "Should only be an extending load, not truncating!");
3662 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
3663 "Cannot sign/zero extend a FP/Vector load!");
3664 assert(VT.isInteger() == EVT.isInteger() &&
3665 "Cannot convert from FP to Int or Int -> FP!");
3668 bool Indexed = AM != ISD::UNINDEXED;
3669 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
3670 "Unindexed load with an offset!");
3672 SDVTList VTs = Indexed ?
3673 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
3674 SDValue Ops[] = { Chain, Ptr, Offset };
3675 FoldingSetNodeID ID;
3676 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
3677 ID.AddInteger(EVT.getRawBits());
3678 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment));
3680 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3681 return SDValue(E, 0);
3682 SDNode *N = NodeAllocator.Allocate<LoadSDNode>();
3683 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
3684 Alignment, isVolatile);
3685 CSEMap.InsertNode(N, IP);
3686 AllNodes.push_back(N);
3687 return SDValue(N, 0);
3690 SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
3691 SDValue Chain, SDValue Ptr,
3692 const Value *SV, int SVOffset,
3693 bool isVolatile, unsigned Alignment) {
3694 SDValue Undef = getUNDEF(Ptr.getValueType());
3695 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
3696 SV, SVOffset, VT, isVolatile, Alignment);
3699 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
3700 SDValue Chain, SDValue Ptr,
3702 int SVOffset, MVT EVT,
3703 bool isVolatile, unsigned Alignment) {
3704 SDValue Undef = getUNDEF(Ptr.getValueType());
3705 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
3706 SV, SVOffset, EVT, isVolatile, Alignment);
3710 SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
3711 SDValue Offset, ISD::MemIndexedMode AM) {
3712 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
3713 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
3714 "Load is already a indexed load!");
3715 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(),
3716 LD->getChain(), Base, Offset, LD->getSrcValue(),
3717 LD->getSrcValueOffset(), LD->getMemoryVT(),
3718 LD->isVolatile(), LD->getAlignment());
3721 SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
3722 SDValue Ptr, const Value *SV, int SVOffset,
3723 bool isVolatile, unsigned Alignment) {
3724 MVT VT = Val.getValueType();
3726 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3727 Alignment = getMVTAlignment(VT);
3729 SDVTList VTs = getVTList(MVT::Other);
3730 SDValue Undef = getUNDEF(Ptr.getValueType());
3731 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3732 FoldingSetNodeID ID;
3733 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3734 ID.AddInteger(VT.getRawBits());
3735 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED,
3736 isVolatile, Alignment));
3738 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3739 return SDValue(E, 0);
3740 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3741 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
3742 VT, SV, SVOffset, Alignment, isVolatile);
3743 CSEMap.InsertNode(N, IP);
3744 AllNodes.push_back(N);
3745 return SDValue(N, 0);
3748 SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
3749 SDValue Ptr, const Value *SV,
3750 int SVOffset, MVT SVT,
3751 bool isVolatile, unsigned Alignment) {
3752 MVT VT = Val.getValueType();
3755 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
3757 assert(VT.bitsGT(SVT) && "Not a truncation?");
3758 assert(VT.isInteger() == SVT.isInteger() &&
3759 "Can't do FP-INT conversion!");
3761 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3762 Alignment = getMVTAlignment(VT);
3764 SDVTList VTs = getVTList(MVT::Other);
3765 SDValue Undef = getUNDEF(Ptr.getValueType());
3766 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3767 FoldingSetNodeID ID;
3768 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3769 ID.AddInteger(SVT.getRawBits());
3770 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED,
3771 isVolatile, Alignment));
3773 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3774 return SDValue(E, 0);
3775 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3776 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
3777 SVT, SV, SVOffset, Alignment, isVolatile);
3778 CSEMap.InsertNode(N, IP);
3779 AllNodes.push_back(N);
3780 return SDValue(N, 0);
3784 SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
3785 SDValue Offset, ISD::MemIndexedMode AM) {
3786 StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
3787 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
3788 "Store is already a indexed store!");
3789 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
3790 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
3791 FoldingSetNodeID ID;
3792 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3793 ID.AddInteger(ST->getMemoryVT().getRawBits());
3794 ID.AddInteger(ST->getRawSubclassData());
3796 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3797 return SDValue(E, 0);
3798 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3799 new (N) StoreSDNode(Ops, dl, VTs, AM,
3800 ST->isTruncatingStore(), ST->getMemoryVT(),
3801 ST->getSrcValue(), ST->getSrcValueOffset(),
3802 ST->getAlignment(), ST->isVolatile());
3803 CSEMap.InsertNode(N, IP);
3804 AllNodes.push_back(N);
3805 return SDValue(N, 0);
3808 SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
3809 SDValue Chain, SDValue Ptr,
3811 SDValue Ops[] = { Chain, Ptr, SV };
3812 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
3815 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
3816 const SDUse *Ops, unsigned NumOps) {
3818 case 0: return getNode(Opcode, DL, VT);
3819 case 1: return getNode(Opcode, DL, VT, Ops[0]);
3820 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
3821 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
3825 // Copy from an SDUse array into an SDValue array for use with
3826 // the regular getNode logic.
3827 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
3828 return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
3831 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
3832 const SDValue *Ops, unsigned NumOps) {
3834 case 0: return getNode(Opcode, DL, VT);
3835 case 1: return getNode(Opcode, DL, VT, Ops[0]);
3836 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
3837 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
3843 case ISD::SELECT_CC: {
3844 assert(NumOps == 5 && "SELECT_CC takes 5 operands!");
3845 assert(Ops[0].getValueType() == Ops[1].getValueType() &&
3846 "LHS and RHS of condition must have same type!");
3847 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3848 "True and False arms of SelectCC must have same type!");
3849 assert(Ops[2].getValueType() == VT &&
3850 "select_cc node must be of same type as true and false value!");
3854 assert(NumOps == 5 && "BR_CC takes 5 operands!");
3855 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3856 "LHS/RHS of comparison should match types!");
3863 SDVTList VTs = getVTList(VT);
3865 if (VT != MVT::Flag) {
3866 FoldingSetNodeID ID;
3867 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
3870 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3871 return SDValue(E, 0);
3873 N = NodeAllocator.Allocate<SDNode>();
3874 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
3875 CSEMap.InsertNode(N, IP);
3877 N = NodeAllocator.Allocate<SDNode>();
3878 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
3881 AllNodes.push_back(N);
3885 return SDValue(N, 0);
3888 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
3889 const std::vector<MVT> &ResultTys,
3890 const SDValue *Ops, unsigned NumOps) {
3891 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
3895 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
3896 const MVT *VTs, unsigned NumVTs,
3897 const SDValue *Ops, unsigned NumOps) {
3899 return getNode(Opcode, DL, VTs[0], Ops, NumOps);
3900 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
3903 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3904 const SDValue *Ops, unsigned NumOps) {
3905 if (VTList.NumVTs == 1)
3906 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps);
3910 // FIXME: figure out how to safely handle things like
3911 // int foo(int x) { return 1 << (x & 255); }
3912 // int bar() { return foo(256); }
3913 case ISD::SRA_PARTS:
3914 case ISD::SRL_PARTS:
3915 case ISD::SHL_PARTS:
3916 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3917 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
3918 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
3919 else if (N3.getOpcode() == ISD::AND)
3920 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
3921 // If the and is only masking out bits that cannot effect the shift,
3922 // eliminate the and.
3923 unsigned NumBits = VT.getSizeInBits()*2;
3924 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
3925 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
3931 // Memoize the node unless it returns a flag.
3933 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3934 FoldingSetNodeID ID;
3935 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3937 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3938 return SDValue(E, 0);
3940 N = NodeAllocator.Allocate<UnarySDNode>();
3941 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
3942 } else if (NumOps == 2) {
3943 N = NodeAllocator.Allocate<BinarySDNode>();
3944 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
3945 } else if (NumOps == 3) {
3946 N = NodeAllocator.Allocate<TernarySDNode>();
3947 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
3949 N = NodeAllocator.Allocate<SDNode>();
3950 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
3952 CSEMap.InsertNode(N, IP);
3955 N = NodeAllocator.Allocate<UnarySDNode>();
3956 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
3957 } else if (NumOps == 2) {
3958 N = NodeAllocator.Allocate<BinarySDNode>();
3959 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
3960 } else if (NumOps == 3) {
3961 N = NodeAllocator.Allocate<TernarySDNode>();
3962 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
3964 N = NodeAllocator.Allocate<SDNode>();
3965 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
3968 AllNodes.push_back(N);
3972 return SDValue(N, 0);
3975 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) {
3976 return getNode(Opcode, DL, VTList, 0, 0);
3979 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3981 SDValue Ops[] = { N1 };
3982 return getNode(Opcode, DL, VTList, Ops, 1);
3985 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3986 SDValue N1, SDValue N2) {
3987 SDValue Ops[] = { N1, N2 };
3988 return getNode(Opcode, DL, VTList, Ops, 2);
3991 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3992 SDValue N1, SDValue N2, SDValue N3) {
3993 SDValue Ops[] = { N1, N2, N3 };
3994 return getNode(Opcode, DL, VTList, Ops, 3);
3997 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3998 SDValue N1, SDValue N2, SDValue N3,
4000 SDValue Ops[] = { N1, N2, N3, N4 };
4001 return getNode(Opcode, DL, VTList, Ops, 4);
4004 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
4005 SDValue N1, SDValue N2, SDValue N3,
4006 SDValue N4, SDValue N5) {
4007 SDValue Ops[] = { N1, N2, N3, N4, N5 };
4008 return getNode(Opcode, DL, VTList, Ops, 5);
4011 SDVTList SelectionDAG::getVTList(MVT VT) {
4012 return makeVTList(SDNode::getValueTypeList(VT), 1);
4015 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) {
4016 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
4017 E = VTList.rend(); I != E; ++I)
4018 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
4021 MVT *Array = Allocator.Allocate<MVT>(2);
4024 SDVTList Result = makeVTList(Array, 2);
4025 VTList.push_back(Result);
4029 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) {
4030 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
4031 E = VTList.rend(); I != E; ++I)
4032 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
4036 MVT *Array = Allocator.Allocate<MVT>(3);
4040 SDVTList Result = makeVTList(Array, 3);
4041 VTList.push_back(Result);
4045 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
4046 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
4047 E = VTList.rend(); I != E; ++I)
4048 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
4049 I->VTs[2] == VT3 && I->VTs[3] == VT4)
4052 MVT *Array = Allocator.Allocate<MVT>(3);
4057 SDVTList Result = makeVTList(Array, 4);
4058 VTList.push_back(Result);
4062 SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
4064 case 0: llvm_unreachable("Cannot have nodes without results!");
4065 case 1: return getVTList(VTs[0]);
4066 case 2: return getVTList(VTs[0], VTs[1]);
4067 case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
4071 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
4072 E = VTList.rend(); I != E; ++I) {
4073 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1])
4076 bool NoMatch = false;
4077 for (unsigned i = 2; i != NumVTs; ++i)
4078 if (VTs[i] != I->VTs[i]) {
4086 MVT *Array = Allocator.Allocate<MVT>(NumVTs);
4087 std::copy(VTs, VTs+NumVTs, Array);
4088 SDVTList Result = makeVTList(Array, NumVTs);
4089 VTList.push_back(Result);
4094 /// UpdateNodeOperands - *Mutate* the specified node in-place to have the
4095 /// specified operands. If the resultant node already exists in the DAG,
4096 /// this does not modify the specified node, instead it returns the node that
4097 /// already exists. If the resultant node does not exist in the DAG, the
4098 /// input node is returned. As a degenerate case, if you specify the same
4099 /// input operands as the node already has, the input node is returned.
4100 SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
4101 SDNode *N = InN.getNode();
4102 assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
4104 // Check to see if there is no change.
4105 if (Op == N->getOperand(0)) return InN;
4107 // See if the modified node already exists.
4108 void *InsertPos = 0;
4109 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
4110 return SDValue(Existing, InN.getResNo());
4112 // Nope it doesn't. Remove the node from its current place in the maps.
4114 if (!RemoveNodeFromCSEMaps(N))
4117 // Now we update the operands.
4118 N->OperandList[0].set(Op);
4120 // If this gets put into a CSE map, add it.
4121 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4125 SDValue SelectionDAG::
4126 UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
4127 SDNode *N = InN.getNode();
4128 assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
4130 // Check to see if there is no change.
4131 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
4132 return InN; // No operands changed, just return the input node.
4134 // See if the modified node already exists.
4135 void *InsertPos = 0;
4136 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
4137 return SDValue(Existing, InN.getResNo());
4139 // Nope it doesn't. Remove the node from its current place in the maps.
4141 if (!RemoveNodeFromCSEMaps(N))
4144 // Now we update the operands.
4145 if (N->OperandList[0] != Op1)
4146 N->OperandList[0].set(Op1);
4147 if (N->OperandList[1] != Op2)
4148 N->OperandList[1].set(Op2);
4150 // If this gets put into a CSE map, add it.
4151 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4155 SDValue SelectionDAG::
4156 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) {
4157 SDValue Ops[] = { Op1, Op2, Op3 };
4158 return UpdateNodeOperands(N, Ops, 3);
4161 SDValue SelectionDAG::
4162 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
4163 SDValue Op3, SDValue Op4) {
4164 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
4165 return UpdateNodeOperands(N, Ops, 4);
4168 SDValue SelectionDAG::
4169 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
4170 SDValue Op3, SDValue Op4, SDValue Op5) {
4171 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
4172 return UpdateNodeOperands(N, Ops, 5);
4175 SDValue SelectionDAG::
4176 UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
4177 SDNode *N = InN.getNode();
4178 assert(N->getNumOperands() == NumOps &&
4179 "Update with wrong number of operands");
4181 // Check to see if there is no change.
4182 bool AnyChange = false;
4183 for (unsigned i = 0; i != NumOps; ++i) {
4184 if (Ops[i] != N->getOperand(i)) {
4190 // No operands changed, just return the input node.
4191 if (!AnyChange) return InN;
4193 // See if the modified node already exists.
4194 void *InsertPos = 0;
4195 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
4196 return SDValue(Existing, InN.getResNo());
4198 // Nope it doesn't. Remove the node from its current place in the maps.
4200 if (!RemoveNodeFromCSEMaps(N))
4203 // Now we update the operands.
4204 for (unsigned i = 0; i != NumOps; ++i)
4205 if (N->OperandList[i] != Ops[i])
4206 N->OperandList[i].set(Ops[i]);
4208 // If this gets put into a CSE map, add it.
4209 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4213 /// DropOperands - Release the operands and set this node to have
4215 void SDNode::DropOperands() {
4216 // Unlike the code in MorphNodeTo that does this, we don't need to
4217 // watch for dead nodes here.
4218 for (op_iterator I = op_begin(), E = op_end(); I != E; ) {
4224 /// SelectNodeTo - These are wrappers around MorphNodeTo that accept a
4227 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4229 SDVTList VTs = getVTList(VT);
4230 return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
4233 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4234 MVT VT, SDValue Op1) {
4235 SDVTList VTs = getVTList(VT);
4236 SDValue Ops[] = { Op1 };
4237 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4240 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4241 MVT VT, SDValue Op1,
4243 SDVTList VTs = getVTList(VT);
4244 SDValue Ops[] = { Op1, Op2 };
4245 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4248 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4249 MVT VT, SDValue Op1,
4250 SDValue Op2, SDValue Op3) {
4251 SDVTList VTs = getVTList(VT);
4252 SDValue Ops[] = { Op1, Op2, Op3 };
4253 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4256 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4257 MVT VT, const SDValue *Ops,
4259 SDVTList VTs = getVTList(VT);
4260 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4263 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4264 MVT VT1, MVT VT2, const SDValue *Ops,
4266 SDVTList VTs = getVTList(VT1, VT2);
4267 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4270 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4272 SDVTList VTs = getVTList(VT1, VT2);
4273 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
4276 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4277 MVT VT1, MVT VT2, MVT VT3,
4278 const SDValue *Ops, unsigned NumOps) {
4279 SDVTList VTs = getVTList(VT1, VT2, VT3);
4280 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4283 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4284 MVT VT1, MVT VT2, MVT VT3, MVT VT4,
4285 const SDValue *Ops, unsigned NumOps) {
4286 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
4287 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4290 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4293 SDVTList VTs = getVTList(VT1, VT2);
4294 SDValue Ops[] = { Op1 };
4295 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4298 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4300 SDValue Op1, SDValue Op2) {
4301 SDVTList VTs = getVTList(VT1, VT2);
4302 SDValue Ops[] = { Op1, Op2 };
4303 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4306 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4308 SDValue Op1, SDValue Op2,
4310 SDVTList VTs = getVTList(VT1, VT2);
4311 SDValue Ops[] = { Op1, Op2, Op3 };
4312 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4315 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4316 MVT VT1, MVT VT2, MVT VT3,
4317 SDValue Op1, SDValue Op2,
4319 SDVTList VTs = getVTList(VT1, VT2, VT3);
4320 SDValue Ops[] = { Op1, Op2, Op3 };
4321 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4324 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4325 SDVTList VTs, const SDValue *Ops,
4327 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps);
4330 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4332 SDVTList VTs = getVTList(VT);
4333 return MorphNodeTo(N, Opc, VTs, 0, 0);
4336 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4337 MVT VT, SDValue Op1) {
4338 SDVTList VTs = getVTList(VT);
4339 SDValue Ops[] = { Op1 };
4340 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4343 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4344 MVT VT, SDValue Op1,
4346 SDVTList VTs = getVTList(VT);
4347 SDValue Ops[] = { Op1, Op2 };
4348 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4351 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4352 MVT VT, SDValue Op1,
4353 SDValue Op2, SDValue Op3) {
4354 SDVTList VTs = getVTList(VT);
4355 SDValue Ops[] = { Op1, Op2, Op3 };
4356 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4359 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4360 MVT VT, const SDValue *Ops,
4362 SDVTList VTs = getVTList(VT);
4363 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4366 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4367 MVT VT1, MVT VT2, const SDValue *Ops,
4369 SDVTList VTs = getVTList(VT1, VT2);
4370 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4373 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4375 SDVTList VTs = getVTList(VT1, VT2);
4376 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
4379 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4380 MVT VT1, MVT VT2, MVT VT3,
4381 const SDValue *Ops, unsigned NumOps) {
4382 SDVTList VTs = getVTList(VT1, VT2, VT3);
4383 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4386 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4389 SDVTList VTs = getVTList(VT1, VT2);
4390 SDValue Ops[] = { Op1 };
4391 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4394 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4396 SDValue Op1, SDValue Op2) {
4397 SDVTList VTs = getVTList(VT1, VT2);
4398 SDValue Ops[] = { Op1, Op2 };
4399 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4402 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4404 SDValue Op1, SDValue Op2,
4406 SDVTList VTs = getVTList(VT1, VT2);
4407 SDValue Ops[] = { Op1, Op2, Op3 };
4408 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4411 /// MorphNodeTo - These *mutate* the specified node to have the specified
4412 /// return type, opcode, and operands.
4414 /// Note that MorphNodeTo returns the resultant node. If there is already a
4415 /// node of the specified opcode and operands, it returns that node instead of
4416 /// the current one. Note that the DebugLoc need not be the same.
4418 /// Using MorphNodeTo is faster than creating a new node and swapping it in
4419 /// with ReplaceAllUsesWith both because it often avoids allocating a new
4420 /// node, and because it doesn't require CSE recalculation for any of
4421 /// the node's users.
4423 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4424 SDVTList VTs, const SDValue *Ops,
4426 // If an identical node already exists, use it.
4428 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
4429 FoldingSetNodeID ID;
4430 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
4431 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
4435 if (!RemoveNodeFromCSEMaps(N))
4438 // Start the morphing.
4440 N->ValueList = VTs.VTs;
4441 N->NumValues = VTs.NumVTs;
4443 // Clear the operands list, updating used nodes to remove this from their
4444 // use list. Keep track of any operands that become dead as a result.
4445 SmallPtrSet<SDNode*, 16> DeadNodeSet;
4446 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
4448 SDNode *Used = Use.getNode();
4450 if (Used->use_empty())
4451 DeadNodeSet.insert(Used);
4454 // If NumOps is larger than the # of operands we currently have, reallocate
4455 // the operand list.
4456 if (NumOps > N->NumOperands) {
4457 if (N->OperandsNeedDelete)
4458 delete[] N->OperandList;
4460 if (N->isMachineOpcode()) {
4461 // We're creating a final node that will live unmorphed for the
4462 // remainder of the current SelectionDAG iteration, so we can allocate
4463 // the operands directly out of a pool with no recycling metadata.
4464 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps);
4465 N->OperandsNeedDelete = false;
4467 N->OperandList = new SDUse[NumOps];
4468 N->OperandsNeedDelete = true;
4472 // Assign the new operands.
4473 N->NumOperands = NumOps;
4474 for (unsigned i = 0, e = NumOps; i != e; ++i) {
4475 N->OperandList[i].setUser(N);
4476 N->OperandList[i].setInitial(Ops[i]);
4479 // Delete any nodes that are still dead after adding the uses for the
4481 SmallVector<SDNode *, 16> DeadNodes;
4482 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(),
4483 E = DeadNodeSet.end(); I != E; ++I)
4484 if ((*I)->use_empty())
4485 DeadNodes.push_back(*I);
4486 RemoveDeadNodes(DeadNodes);
4489 CSEMap.InsertNode(N, IP); // Memoize the new node.
4494 /// getTargetNode - These are used for target selectors to create a new node
4495 /// with specified return type(s), target opcode, and operands.
4497 /// Note that getTargetNode returns the resultant node. If there is already a
4498 /// node of the specified opcode and operands, it returns that node instead of
4499 /// the current one.
4500 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
4501 return getNode(~Opcode, dl, VT).getNode();
4504 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4506 return getNode(~Opcode, dl, VT, Op1).getNode();
4509 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4510 SDValue Op1, SDValue Op2) {
4511 return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
4514 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4515 SDValue Op1, SDValue Op2,
4517 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
4520 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4521 const SDValue *Ops, unsigned NumOps) {
4522 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
4525 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4527 SDVTList VTs = getVTList(VT1, VT2);
4529 return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
4532 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4533 MVT VT2, SDValue Op1) {
4534 SDVTList VTs = getVTList(VT1, VT2);
4535 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
4538 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4539 MVT VT2, SDValue Op1,
4541 SDVTList VTs = getVTList(VT1, VT2);
4542 SDValue Ops[] = { Op1, Op2 };
4543 return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
4546 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4547 MVT VT2, SDValue Op1,
4548 SDValue Op2, SDValue Op3) {
4549 SDVTList VTs = getVTList(VT1, VT2);
4550 SDValue Ops[] = { Op1, Op2, Op3 };
4551 return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
4554 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4556 const SDValue *Ops, unsigned NumOps) {
4557 SDVTList VTs = getVTList(VT1, VT2);
4558 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4561 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4562 MVT VT1, MVT VT2, MVT VT3,
4563 SDValue Op1, SDValue Op2) {
4564 SDVTList VTs = getVTList(VT1, VT2, VT3);
4565 SDValue Ops[] = { Op1, Op2 };
4566 return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
4569 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4570 MVT VT1, MVT VT2, MVT VT3,
4571 SDValue Op1, SDValue Op2,
4573 SDVTList VTs = getVTList(VT1, VT2, VT3);
4574 SDValue Ops[] = { Op1, Op2, Op3 };
4575 return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
4578 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4579 MVT VT1, MVT VT2, MVT VT3,
4580 const SDValue *Ops, unsigned NumOps) {
4581 SDVTList VTs = getVTList(VT1, VT2, VT3);
4582 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4585 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4586 MVT VT2, MVT VT3, MVT VT4,
4587 const SDValue *Ops, unsigned NumOps) {
4588 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
4589 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4592 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4593 const std::vector<MVT> &ResultTys,
4594 const SDValue *Ops, unsigned NumOps) {
4595 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
4598 /// getNodeIfExists - Get the specified node if it's already available, or
4599 /// else return NULL.
4600 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
4601 const SDValue *Ops, unsigned NumOps) {
4602 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
4603 FoldingSetNodeID ID;
4604 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
4606 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
4612 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4613 /// This can cause recursive merging of nodes in the DAG.
4615 /// This version assumes From has a single result value.
4617 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
4618 DAGUpdateListener *UpdateListener) {
4619 SDNode *From = FromN.getNode();
4620 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
4621 "Cannot replace with this method!");
4622 assert(From != To.getNode() && "Cannot replace uses of with self");
4624 // Iterate over all the existing uses of From. New uses will be added
4625 // to the beginning of the use list, which we avoid visiting.
4626 // This specifically avoids visiting uses of From that arise while the
4627 // replacement is happening, because any such uses would be the result
4628 // of CSE: If an existing node looks like From after one of its operands
4629 // is replaced by To, we don't want to replace of all its users with To
4630 // too. See PR3018 for more info.
4631 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4635 // This node is about to morph, remove its old self from the CSE maps.
4636 RemoveNodeFromCSEMaps(User);
4638 // A user can appear in a use list multiple times, and when this
4639 // happens the uses are usually next to each other in the list.
4640 // To help reduce the number of CSE recomputations, process all
4641 // the uses of this user that we can find this way.
4643 SDUse &Use = UI.getUse();
4646 } while (UI != UE && *UI == User);
4648 // Now that we have modified User, add it back to the CSE maps. If it
4649 // already exists there, recursively merge the results together.
4650 AddModifiedNodeToCSEMaps(User, UpdateListener);
4654 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4655 /// This can cause recursive merging of nodes in the DAG.
4657 /// This version assumes that for each value of From, there is a
4658 /// corresponding value in To in the same position with the same type.
4660 void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To,
4661 DAGUpdateListener *UpdateListener) {
4663 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
4664 assert((!From->hasAnyUseOfValue(i) ||
4665 From->getValueType(i) == To->getValueType(i)) &&
4666 "Cannot use this version of ReplaceAllUsesWith!");
4669 // Handle the trivial case.
4673 // Iterate over just the existing users of From. See the comments in
4674 // the ReplaceAllUsesWith above.
4675 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4679 // This node is about to morph, remove its old self from the CSE maps.
4680 RemoveNodeFromCSEMaps(User);
4682 // A user can appear in a use list multiple times, and when this
4683 // happens the uses are usually next to each other in the list.
4684 // To help reduce the number of CSE recomputations, process all
4685 // the uses of this user that we can find this way.
4687 SDUse &Use = UI.getUse();
4690 } while (UI != UE && *UI == User);
4692 // Now that we have modified User, add it back to the CSE maps. If it
4693 // already exists there, recursively merge the results together.
4694 AddModifiedNodeToCSEMaps(User, UpdateListener);
4698 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4699 /// This can cause recursive merging of nodes in the DAG.
4701 /// This version can replace From with any result values. To must match the
4702 /// number and types of values returned by From.
4703 void SelectionDAG::ReplaceAllUsesWith(SDNode *From,
4705 DAGUpdateListener *UpdateListener) {
4706 if (From->getNumValues() == 1) // Handle the simple case efficiently.
4707 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener);
4709 // Iterate over just the existing users of From. See the comments in
4710 // the ReplaceAllUsesWith above.
4711 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4715 // This node is about to morph, remove its old self from the CSE maps.
4716 RemoveNodeFromCSEMaps(User);
4718 // A user can appear in a use list multiple times, and when this
4719 // happens the uses are usually next to each other in the list.
4720 // To help reduce the number of CSE recomputations, process all
4721 // the uses of this user that we can find this way.
4723 SDUse &Use = UI.getUse();
4724 const SDValue &ToOp = To[Use.getResNo()];
4727 } while (UI != UE && *UI == User);
4729 // Now that we have modified User, add it back to the CSE maps. If it
4730 // already exists there, recursively merge the results together.
4731 AddModifiedNodeToCSEMaps(User, UpdateListener);
4735 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
4736 /// uses of other values produced by From.getNode() alone. The Deleted
4737 /// vector is handled the same way as for ReplaceAllUsesWith.
4738 void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
4739 DAGUpdateListener *UpdateListener){
4740 // Handle the really simple, really trivial case efficiently.
4741 if (From == To) return;
4743 // Handle the simple, trivial, case efficiently.
4744 if (From.getNode()->getNumValues() == 1) {
4745 ReplaceAllUsesWith(From, To, UpdateListener);
4749 // Iterate over just the existing users of From. See the comments in
4750 // the ReplaceAllUsesWith above.
4751 SDNode::use_iterator UI = From.getNode()->use_begin(),
4752 UE = From.getNode()->use_end();
4755 bool UserRemovedFromCSEMaps = false;
4757 // A user can appear in a use list multiple times, and when this
4758 // happens the uses are usually next to each other in the list.
4759 // To help reduce the number of CSE recomputations, process all
4760 // the uses of this user that we can find this way.
4762 SDUse &Use = UI.getUse();
4764 // Skip uses of different values from the same node.
4765 if (Use.getResNo() != From.getResNo()) {
4770 // If this node hasn't been modified yet, it's still in the CSE maps,
4771 // so remove its old self from the CSE maps.
4772 if (!UserRemovedFromCSEMaps) {
4773 RemoveNodeFromCSEMaps(User);
4774 UserRemovedFromCSEMaps = true;
4779 } while (UI != UE && *UI == User);
4781 // We are iterating over all uses of the From node, so if a use
4782 // doesn't use the specific value, no changes are made.
4783 if (!UserRemovedFromCSEMaps)
4786 // Now that we have modified User, add it back to the CSE maps. If it
4787 // already exists there, recursively merge the results together.
4788 AddModifiedNodeToCSEMaps(User, UpdateListener);
4793 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith
4794 /// to record information about a use.
4801 /// operator< - Sort Memos by User.
4802 bool operator<(const UseMemo &L, const UseMemo &R) {
4803 return (intptr_t)L.User < (intptr_t)R.User;
4807 /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
4808 /// uses of other values produced by From.getNode() alone. The same value
4809 /// may appear in both the From and To list. The Deleted vector is
4810 /// handled the same way as for ReplaceAllUsesWith.
4811 void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
4814 DAGUpdateListener *UpdateListener){
4815 // Handle the simple, trivial case efficiently.
4817 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener);
4819 // Read up all the uses and make records of them. This helps
4820 // processing new uses that are introduced during the
4821 // replacement process.
4822 SmallVector<UseMemo, 4> Uses;
4823 for (unsigned i = 0; i != Num; ++i) {
4824 unsigned FromResNo = From[i].getResNo();
4825 SDNode *FromNode = From[i].getNode();
4826 for (SDNode::use_iterator UI = FromNode->use_begin(),
4827 E = FromNode->use_end(); UI != E; ++UI) {
4828 SDUse &Use = UI.getUse();
4829 if (Use.getResNo() == FromResNo) {
4830 UseMemo Memo = { *UI, i, &Use };
4831 Uses.push_back(Memo);
4836 // Sort the uses, so that all the uses from a given User are together.
4837 std::sort(Uses.begin(), Uses.end());
4839 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size();
4840 UseIndex != UseIndexEnd; ) {
4841 // We know that this user uses some value of From. If it is the right
4842 // value, update it.
4843 SDNode *User = Uses[UseIndex].User;
4845 // This node is about to morph, remove its old self from the CSE maps.
4846 RemoveNodeFromCSEMaps(User);
4848 // The Uses array is sorted, so all the uses for a given User
4849 // are next to each other in the list.
4850 // To help reduce the number of CSE recomputations, process all
4851 // the uses of this user that we can find this way.
4853 unsigned i = Uses[UseIndex].Index;
4854 SDUse &Use = *Uses[UseIndex].Use;
4858 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User);
4860 // Now that we have modified User, add it back to the CSE maps. If it
4861 // already exists there, recursively merge the results together.
4862 AddModifiedNodeToCSEMaps(User, UpdateListener);
4866 /// AssignTopologicalOrder - Assign a unique node id for each node in the DAG
4867 /// based on their topological order. It returns the maximum id and a vector
4868 /// of the SDNodes* in assigned order by reference.
4869 unsigned SelectionDAG::AssignTopologicalOrder() {
4871 unsigned DAGSize = 0;
4873 // SortedPos tracks the progress of the algorithm. Nodes before it are
4874 // sorted, nodes after it are unsorted. When the algorithm completes
4875 // it is at the end of the list.
4876 allnodes_iterator SortedPos = allnodes_begin();
4878 // Visit all the nodes. Move nodes with no operands to the front of
4879 // the list immediately. Annotate nodes that do have operands with their
4880 // operand count. Before we do this, the Node Id fields of the nodes
4881 // may contain arbitrary values. After, the Node Id fields for nodes
4882 // before SortedPos will contain the topological sort index, and the
4883 // Node Id fields for nodes At SortedPos and after will contain the
4884 // count of outstanding operands.
4885 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) {
4887 unsigned Degree = N->getNumOperands();
4889 // A node with no uses, add it to the result array immediately.
4890 N->setNodeId(DAGSize++);
4891 allnodes_iterator Q = N;
4893 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
4896 // Temporarily use the Node Id as scratch space for the degree count.
4897 N->setNodeId(Degree);
4901 // Visit all the nodes. As we iterate, moves nodes into sorted order,
4902 // such that by the time the end is reached all nodes will be sorted.
4903 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) {
4905 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4908 unsigned Degree = P->getNodeId();
4911 // All of P's operands are sorted, so P may sorted now.
4912 P->setNodeId(DAGSize++);
4914 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P));
4917 // Update P's outstanding operand count.
4918 P->setNodeId(Degree);
4923 assert(SortedPos == AllNodes.end() &&
4924 "Topological sort incomplete!");
4925 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
4926 "First node in topological sort is not the entry token!");
4927 assert(AllNodes.front().getNodeId() == 0 &&
4928 "First node in topological sort has non-zero id!");
4929 assert(AllNodes.front().getNumOperands() == 0 &&
4930 "First node in topological sort has operands!");
4931 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 &&
4932 "Last node in topologic sort has unexpected id!");
4933 assert(AllNodes.back().use_empty() &&
4934 "Last node in topologic sort has users!");
4935 assert(DAGSize == allnodes_size() && "Node count mismatch!");
4941 //===----------------------------------------------------------------------===//
4943 //===----------------------------------------------------------------------===//
4945 HandleSDNode::~HandleSDNode() {
4949 GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA,
4950 MVT VT, int64_t o, unsigned char TF)
4951 : SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)),
4952 Offset(o), TargetFlags(TF) {
4953 TheGlobal = const_cast<GlobalValue*>(GA);
4956 MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
4957 const Value *srcValue, int SVO,
4958 unsigned alignment, bool vol)
4959 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
4960 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
4961 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4962 assert(getAlignment() == alignment && "Alignment representation error!");
4963 assert(isVolatile() == vol && "Volatile representation error!");
4966 MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
4968 unsigned NumOps, MVT memvt, const Value *srcValue,
4969 int SVO, unsigned alignment, bool vol)
4970 : SDNode(Opc, dl, VTs, Ops, NumOps),
4971 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
4972 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
4973 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4974 assert(getAlignment() == alignment && "Alignment representation error!");
4975 assert(isVolatile() == vol && "Volatile representation error!");
4978 /// getMemOperand - Return a MachineMemOperand object describing the memory
4979 /// reference performed by this memory reference.
4980 MachineMemOperand MemSDNode::getMemOperand() const {
4982 if (isa<LoadSDNode>(this))
4983 Flags = MachineMemOperand::MOLoad;
4984 else if (isa<StoreSDNode>(this))
4985 Flags = MachineMemOperand::MOStore;
4986 else if (isa<AtomicSDNode>(this)) {
4987 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
4990 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this);
4991 assert(MemIntrinNode && "Unknown MemSDNode opcode!");
4992 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad;
4993 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore;
4996 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3;
4997 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile;
4999 // Check if the memory reference references a frame index
5000 const FrameIndexSDNode *FI =
5001 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
5002 if (!getSrcValue() && FI)
5003 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
5004 Flags, 0, Size, getAlignment());
5006 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(),
5007 Size, getAlignment());
5010 /// Profile - Gather unique data for the node.
5012 void SDNode::Profile(FoldingSetNodeID &ID) const {
5013 AddNodeIDNode(ID, this);
5016 static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs;
5017 static MVT VTs[MVT::LAST_VALUETYPE];
5018 static ManagedStatic<sys::SmartMutex<true> > VTMutex;
5020 /// getValueTypeList - Return a pointer to the specified value type.
5022 const MVT *SDNode::getValueTypeList(MVT VT) {
5023 sys::SmartScopedLock<true> Lock(*VTMutex);
5024 if (VT.isExtended()) {
5025 return &(*EVTs->insert(VT).first);
5027 VTs[VT.getSimpleVT()] = VT;
5028 return &VTs[VT.getSimpleVT()];
5032 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
5033 /// indicated value. This method ignores uses of other values defined by this
5035 bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const {
5036 assert(Value < getNumValues() && "Bad value!");
5038 // TODO: Only iterate over uses of a given value of the node
5039 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
5040 if (UI.getUse().getResNo() == Value) {
5047 // Found exactly the right number of uses?
5052 /// hasAnyUseOfValue - Return true if there are any use of the indicated
5053 /// value. This method ignores uses of other values defined by this operation.
5054 bool SDNode::hasAnyUseOfValue(unsigned Value) const {
5055 assert(Value < getNumValues() && "Bad value!");
5057 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
5058 if (UI.getUse().getResNo() == Value)
5065 /// isOnlyUserOf - Return true if this node is the only use of N.
5067 bool SDNode::isOnlyUserOf(SDNode *N) const {
5069 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
5080 /// isOperand - Return true if this node is an operand of N.
5082 bool SDValue::isOperandOf(SDNode *N) const {
5083 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5084 if (*this == N->getOperand(i))
5089 bool SDNode::isOperandOf(SDNode *N) const {
5090 for (unsigned i = 0, e = N->NumOperands; i != e; ++i)
5091 if (this == N->OperandList[i].getNode())
5096 /// reachesChainWithoutSideEffects - Return true if this operand (which must
5097 /// be a chain) reaches the specified operand without crossing any
5098 /// side-effecting instructions. In practice, this looks through token
5099 /// factors and non-volatile loads. In order to remain efficient, this only
5100 /// looks a couple of nodes in, it does not do an exhaustive search.
5101 bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
5102 unsigned Depth) const {
5103 if (*this == Dest) return true;
5105 // Don't search too deeply, we just want to be able to see through
5106 // TokenFactor's etc.
5107 if (Depth == 0) return false;
5109 // If this is a token factor, all inputs to the TF happen in parallel. If any
5110 // of the operands of the TF reach dest, then we can do the xform.
5111 if (getOpcode() == ISD::TokenFactor) {
5112 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
5113 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1))
5118 // Loads don't have side effects, look through them.
5119 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
5120 if (!Ld->isVolatile())
5121 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
5127 static void findPredecessor(SDNode *N, const SDNode *P, bool &found,
5128 SmallPtrSet<SDNode *, 32> &Visited) {
5129 if (found || !Visited.insert(N))
5132 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) {
5133 SDNode *Op = N->getOperand(i).getNode();
5138 findPredecessor(Op, P, found, Visited);
5142 /// isPredecessorOf - Return true if this node is a predecessor of N. This node
5143 /// is either an operand of N or it can be reached by recursively traversing
5144 /// up the operands.
5145 /// NOTE: this is an expensive method. Use it carefully.
5146 bool SDNode::isPredecessorOf(SDNode *N) const {
5147 SmallPtrSet<SDNode *, 32> Visited;
5149 findPredecessor(N, this, found, Visited);
5153 uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
5154 assert(Num < NumOperands && "Invalid child # of SDNode!");
5155 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue();
5158 std::string SDNode::getOperationName(const SelectionDAG *G) const {
5159 switch (getOpcode()) {
5161 if (getOpcode() < ISD::BUILTIN_OP_END)
5162 return "<<Unknown DAG Node>>";
5163 if (isMachineOpcode()) {
5165 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
5166 if (getMachineOpcode() < TII->getNumOpcodes())
5167 return TII->get(getMachineOpcode()).getName();
5168 return "<<Unknown Machine Node>>";
5171 const TargetLowering &TLI = G->getTargetLoweringInfo();
5172 const char *Name = TLI.getTargetNodeName(getOpcode());
5173 if (Name) return Name;
5174 return "<<Unknown Target Node>>";
5176 return "<<Unknown Node>>";
5179 case ISD::DELETED_NODE:
5180 return "<<Deleted Node!>>";
5182 case ISD::PREFETCH: return "Prefetch";
5183 case ISD::MEMBARRIER: return "MemBarrier";
5184 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
5185 case ISD::ATOMIC_SWAP: return "AtomicSwap";
5186 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
5187 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
5188 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
5189 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
5190 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
5191 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
5192 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
5193 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
5194 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
5195 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
5196 case ISD::PCMARKER: return "PCMarker";
5197 case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
5198 case ISD::SRCVALUE: return "SrcValue";
5199 case ISD::MEMOPERAND: return "MemOperand";
5200 case ISD::EntryToken: return "EntryToken";
5201 case ISD::TokenFactor: return "TokenFactor";
5202 case ISD::AssertSext: return "AssertSext";
5203 case ISD::AssertZext: return "AssertZext";
5205 case ISD::BasicBlock: return "BasicBlock";
5206 case ISD::ARG_FLAGS: return "ArgFlags";
5207 case ISD::VALUETYPE: return "ValueType";
5208 case ISD::Register: return "Register";
5210 case ISD::Constant: return "Constant";
5211 case ISD::ConstantFP: return "ConstantFP";
5212 case ISD::GlobalAddress: return "GlobalAddress";
5213 case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
5214 case ISD::FrameIndex: return "FrameIndex";
5215 case ISD::JumpTable: return "JumpTable";
5216 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
5217 case ISD::RETURNADDR: return "RETURNADDR";
5218 case ISD::FRAMEADDR: return "FRAMEADDR";
5219 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
5220 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
5221 case ISD::EHSELECTION: return "EHSELECTION";
5222 case ISD::EH_RETURN: return "EH_RETURN";
5223 case ISD::ConstantPool: return "ConstantPool";
5224 case ISD::ExternalSymbol: return "ExternalSymbol";
5225 case ISD::INTRINSIC_WO_CHAIN: {
5226 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue();
5227 return Intrinsic::getName((Intrinsic::ID)IID);
5229 case ISD::INTRINSIC_VOID:
5230 case ISD::INTRINSIC_W_CHAIN: {
5231 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue();
5232 return Intrinsic::getName((Intrinsic::ID)IID);
5235 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
5236 case ISD::TargetConstant: return "TargetConstant";
5237 case ISD::TargetConstantFP:return "TargetConstantFP";
5238 case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
5239 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
5240 case ISD::TargetFrameIndex: return "TargetFrameIndex";
5241 case ISD::TargetJumpTable: return "TargetJumpTable";
5242 case ISD::TargetConstantPool: return "TargetConstantPool";
5243 case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
5245 case ISD::CopyToReg: return "CopyToReg";
5246 case ISD::CopyFromReg: return "CopyFromReg";
5247 case ISD::UNDEF: return "undef";
5248 case ISD::MERGE_VALUES: return "merge_values";
5249 case ISD::INLINEASM: return "inlineasm";
5250 case ISD::DBG_LABEL: return "dbg_label";
5251 case ISD::EH_LABEL: return "eh_label";
5252 case ISD::DECLARE: return "declare";
5253 case ISD::HANDLENODE: return "handlenode";
5254 case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
5255 case ISD::CALL: return "call";
5258 case ISD::FABS: return "fabs";
5259 case ISD::FNEG: return "fneg";
5260 case ISD::FSQRT: return "fsqrt";
5261 case ISD::FSIN: return "fsin";
5262 case ISD::FCOS: return "fcos";
5263 case ISD::FPOWI: return "fpowi";
5264 case ISD::FPOW: return "fpow";
5265 case ISD::FTRUNC: return "ftrunc";
5266 case ISD::FFLOOR: return "ffloor";
5267 case ISD::FCEIL: return "fceil";
5268 case ISD::FRINT: return "frint";
5269 case ISD::FNEARBYINT: return "fnearbyint";
5272 case ISD::ADD: return "add";
5273 case ISD::SUB: return "sub";
5274 case ISD::MUL: return "mul";
5275 case ISD::MULHU: return "mulhu";
5276 case ISD::MULHS: return "mulhs";
5277 case ISD::SDIV: return "sdiv";
5278 case ISD::UDIV: return "udiv";
5279 case ISD::SREM: return "srem";
5280 case ISD::UREM: return "urem";
5281 case ISD::SMUL_LOHI: return "smul_lohi";
5282 case ISD::UMUL_LOHI: return "umul_lohi";
5283 case ISD::SDIVREM: return "sdivrem";
5284 case ISD::UDIVREM: return "udivrem";
5285 case ISD::AND: return "and";
5286 case ISD::OR: return "or";
5287 case ISD::XOR: return "xor";
5288 case ISD::SHL: return "shl";
5289 case ISD::SRA: return "sra";
5290 case ISD::SRL: return "srl";
5291 case ISD::ROTL: return "rotl";
5292 case ISD::ROTR: return "rotr";
5293 case ISD::FADD: return "fadd";
5294 case ISD::FSUB: return "fsub";
5295 case ISD::FMUL: return "fmul";
5296 case ISD::FDIV: return "fdiv";
5297 case ISD::FREM: return "frem";
5298 case ISD::FCOPYSIGN: return "fcopysign";
5299 case ISD::FGETSIGN: return "fgetsign";
5301 case ISD::SETCC: return "setcc";
5302 case ISD::VSETCC: return "vsetcc";
5303 case ISD::SELECT: return "select";
5304 case ISD::SELECT_CC: return "select_cc";
5305 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
5306 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
5307 case ISD::CONCAT_VECTORS: return "concat_vectors";
5308 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
5309 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
5310 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
5311 case ISD::CARRY_FALSE: return "carry_false";
5312 case ISD::ADDC: return "addc";
5313 case ISD::ADDE: return "adde";
5314 case ISD::SADDO: return "saddo";
5315 case ISD::UADDO: return "uaddo";
5316 case ISD::SSUBO: return "ssubo";
5317 case ISD::USUBO: return "usubo";
5318 case ISD::SMULO: return "smulo";
5319 case ISD::UMULO: return "umulo";
5320 case ISD::SUBC: return "subc";
5321 case ISD::SUBE: return "sube";
5322 case ISD::SHL_PARTS: return "shl_parts";
5323 case ISD::SRA_PARTS: return "sra_parts";
5324 case ISD::SRL_PARTS: return "srl_parts";
5326 // Conversion operators.
5327 case ISD::SIGN_EXTEND: return "sign_extend";
5328 case ISD::ZERO_EXTEND: return "zero_extend";
5329 case ISD::ANY_EXTEND: return "any_extend";
5330 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
5331 case ISD::TRUNCATE: return "truncate";
5332 case ISD::FP_ROUND: return "fp_round";
5333 case ISD::FLT_ROUNDS_: return "flt_rounds";
5334 case ISD::FP_ROUND_INREG: return "fp_round_inreg";
5335 case ISD::FP_EXTEND: return "fp_extend";
5337 case ISD::SINT_TO_FP: return "sint_to_fp";
5338 case ISD::UINT_TO_FP: return "uint_to_fp";
5339 case ISD::FP_TO_SINT: return "fp_to_sint";
5340 case ISD::FP_TO_UINT: return "fp_to_uint";
5341 case ISD::BIT_CONVERT: return "bit_convert";
5343 case ISD::CONVERT_RNDSAT: {
5344 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) {
5345 default: llvm_unreachable("Unknown cvt code!");
5346 case ISD::CVT_FF: return "cvt_ff";
5347 case ISD::CVT_FS: return "cvt_fs";
5348 case ISD::CVT_FU: return "cvt_fu";
5349 case ISD::CVT_SF: return "cvt_sf";
5350 case ISD::CVT_UF: return "cvt_uf";
5351 case ISD::CVT_SS: return "cvt_ss";
5352 case ISD::CVT_SU: return "cvt_su";
5353 case ISD::CVT_US: return "cvt_us";
5354 case ISD::CVT_UU: return "cvt_uu";
5358 // Control flow instructions
5359 case ISD::BR: return "br";
5360 case ISD::BRIND: return "brind";
5361 case ISD::BR_JT: return "br_jt";
5362 case ISD::BRCOND: return "brcond";
5363 case ISD::BR_CC: return "br_cc";
5364 case ISD::RET: return "ret";
5365 case ISD::CALLSEQ_START: return "callseq_start";
5366 case ISD::CALLSEQ_END: return "callseq_end";
5369 case ISD::LOAD: return "load";
5370 case ISD::STORE: return "store";
5371 case ISD::VAARG: return "vaarg";
5372 case ISD::VACOPY: return "vacopy";
5373 case ISD::VAEND: return "vaend";
5374 case ISD::VASTART: return "vastart";
5375 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
5376 case ISD::EXTRACT_ELEMENT: return "extract_element";
5377 case ISD::BUILD_PAIR: return "build_pair";
5378 case ISD::STACKSAVE: return "stacksave";
5379 case ISD::STACKRESTORE: return "stackrestore";
5380 case ISD::TRAP: return "trap";
5383 case ISD::BSWAP: return "bswap";
5384 case ISD::CTPOP: return "ctpop";
5385 case ISD::CTTZ: return "cttz";
5386 case ISD::CTLZ: return "ctlz";
5389 case ISD::DBG_STOPPOINT: return "dbg_stoppoint";
5390 case ISD::DEBUG_LOC: return "debug_loc";
5393 case ISD::TRAMPOLINE: return "trampoline";
5396 switch (cast<CondCodeSDNode>(this)->get()) {
5397 default: llvm_unreachable("Unknown setcc condition!");
5398 case ISD::SETOEQ: return "setoeq";
5399 case ISD::SETOGT: return "setogt";
5400 case ISD::SETOGE: return "setoge";
5401 case ISD::SETOLT: return "setolt";
5402 case ISD::SETOLE: return "setole";
5403 case ISD::SETONE: return "setone";
5405 case ISD::SETO: return "seto";
5406 case ISD::SETUO: return "setuo";
5407 case ISD::SETUEQ: return "setue";
5408 case ISD::SETUGT: return "setugt";
5409 case ISD::SETUGE: return "setuge";
5410 case ISD::SETULT: return "setult";
5411 case ISD::SETULE: return "setule";
5412 case ISD::SETUNE: return "setune";
5414 case ISD::SETEQ: return "seteq";
5415 case ISD::SETGT: return "setgt";
5416 case ISD::SETGE: return "setge";
5417 case ISD::SETLT: return "setlt";
5418 case ISD::SETLE: return "setle";
5419 case ISD::SETNE: return "setne";
5424 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
5433 return "<post-inc>";
5435 return "<post-dec>";
5439 std::string ISD::ArgFlagsTy::getArgFlagsString() {
5440 std::string S = "< ";
5454 if (getByValAlign())
5455 S += "byval-align:" + utostr(getByValAlign()) + " ";
5457 S += "orig-align:" + utostr(getOrigAlign()) + " ";
5459 S += "byval-size:" + utostr(getByValSize()) + " ";
5463 void SDNode::dump() const { dump(0); }
5464 void SDNode::dump(const SelectionDAG *G) const {
5468 void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
5469 OS << (void*)this << ": ";
5471 for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
5473 if (getValueType(i) == MVT::Other)
5476 OS << getValueType(i).getMVTString();
5478 OS << " = " << getOperationName(G);
5481 void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
5482 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
5483 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this);
5485 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
5486 int Idx = SVN->getMaskElt(i);
5496 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
5497 OS << '<' << CSDN->getAPIntValue() << '>';
5498 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
5499 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle)
5500 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
5501 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble)
5502 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
5505 CSDN->getValueAPF().bitcastToAPInt().dump();
5508 } else if (const GlobalAddressSDNode *GADN =
5509 dyn_cast<GlobalAddressSDNode>(this)) {
5510 int64_t offset = GADN->getOffset();
5512 WriteAsOperand(OS, GADN->getGlobal());
5515 OS << " + " << offset;
5517 OS << " " << offset;
5518 if (unsigned char TF = GADN->getTargetFlags())
5519 OS << " [TF=" << TF << ']';
5520 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
5521 OS << "<" << FIDN->getIndex() << ">";
5522 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
5523 OS << "<" << JTDN->getIndex() << ">";
5524 if (unsigned char TF = JTDN->getTargetFlags())
5525 OS << " [TF=" << TF << ']';
5526 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
5527 int offset = CP->getOffset();
5528 if (CP->isMachineConstantPoolEntry())
5529 OS << "<" << *CP->getMachineCPVal() << ">";
5531 OS << "<" << *CP->getConstVal() << ">";
5533 OS << " + " << offset;
5535 OS << " " << offset;
5536 if (unsigned char TF = CP->getTargetFlags())
5537 OS << " [TF=" << TF << ']';
5538 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
5540 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
5542 OS << LBB->getName() << " ";
5543 OS << (const void*)BBDN->getBasicBlock() << ">";
5544 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
5545 if (G && R->getReg() &&
5546 TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
5547 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg());
5549 OS << " #" << R->getReg();
5551 } else if (const ExternalSymbolSDNode *ES =
5552 dyn_cast<ExternalSymbolSDNode>(this)) {
5553 OS << "'" << ES->getSymbol() << "'";
5554 if (unsigned char TF = ES->getTargetFlags())
5555 OS << " [TF=" << TF << ']';
5556 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
5558 OS << "<" << M->getValue() << ">";
5561 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) {
5562 if (M->MO.getValue())
5563 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
5565 OS << "<null:" << M->MO.getOffset() << ">";
5566 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) {
5567 OS << N->getArgFlags().getArgFlagsString();
5568 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
5569 OS << ":" << N->getVT().getMVTString();
5571 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
5572 const Value *SrcValue = LD->getSrcValue();
5573 int SrcOffset = LD->getSrcValueOffset();
5579 OS << ":" << SrcOffset << ">";
5582 switch (LD->getExtensionType()) {
5583 default: doExt = false; break;
5584 case ISD::EXTLOAD: OS << " <anyext "; break;
5585 case ISD::SEXTLOAD: OS << " <sext "; break;
5586 case ISD::ZEXTLOAD: OS << " <zext "; break;
5589 OS << LD->getMemoryVT().getMVTString() << ">";
5591 const char *AM = getIndexedModeName(LD->getAddressingMode());
5594 if (LD->isVolatile())
5595 OS << " <volatile>";
5596 OS << " alignment=" << LD->getAlignment();
5597 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
5598 const Value *SrcValue = ST->getSrcValue();
5599 int SrcOffset = ST->getSrcValueOffset();
5605 OS << ":" << SrcOffset << ">";
5607 if (ST->isTruncatingStore())
5608 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">";
5610 const char *AM = getIndexedModeName(ST->getAddressingMode());
5613 if (ST->isVolatile())
5614 OS << " <volatile>";
5615 OS << " alignment=" << ST->getAlignment();
5616 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) {
5617 const Value *SrcValue = AT->getSrcValue();
5618 int SrcOffset = AT->getSrcValueOffset();
5624 OS << ":" << SrcOffset << ">";
5625 if (AT->isVolatile())
5626 OS << " <volatile>";
5627 OS << " alignment=" << AT->getAlignment();
5631 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
5634 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
5636 OS << (void*)getOperand(i).getNode();
5637 if (unsigned RN = getOperand(i).getResNo())
5640 print_details(OS, G);
5643 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
5644 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5645 if (N->getOperand(i).getNode()->hasOneUse())
5646 DumpNodes(N->getOperand(i).getNode(), indent+2, G);
5648 cerr << "\n" << std::string(indent+2, ' ')
5649 << (void*)N->getOperand(i).getNode() << ": <multiple use>";
5652 cerr << "\n" << std::string(indent, ' ');
5656 void SelectionDAG::dump() const {
5657 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:";
5659 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
5661 const SDNode *N = I;
5662 if (!N->hasOneUse() && N != getRoot().getNode())
5663 DumpNodes(N, 2, this);
5666 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
5671 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
5673 print_details(OS, G);
5676 typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet;
5677 static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
5678 const SelectionDAG *G, VisitedSDNodeSet &once) {
5679 if (!once.insert(N)) // If we've been here before, return now.
5681 // Dump the current SDNode, but don't end the line yet.
5682 OS << std::string(indent, ' ');
5684 // Having printed this SDNode, walk the children:
5685 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5686 const SDNode *child = N->getOperand(i).getNode();
5689 if (child->getNumOperands() == 0) {
5690 // This child has no grandchildren; print it inline right here.
5691 child->printr(OS, G);
5693 } else { // Just the address. FIXME: also print the child's opcode
5695 if (unsigned RN = N->getOperand(i).getResNo())
5700 // Dump children that have grandchildren on their own line(s).
5701 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5702 const SDNode *child = N->getOperand(i).getNode();
5703 DumpNodesr(OS, child, indent+2, G, once);
5707 void SDNode::dumpr() const {
5708 VisitedSDNodeSet once;
5709 DumpNodesr(errs(), this, 0, 0, once);
5713 // getAddressSpace - Return the address space this GlobalAddress belongs to.
5714 unsigned GlobalAddressSDNode::getAddressSpace() const {
5715 return getGlobal()->getType()->getAddressSpace();
5719 const Type *ConstantPoolSDNode::getType() const {
5720 if (isMachineConstantPoolEntry())
5721 return Val.MachineCPVal->getType();
5722 return Val.ConstVal->getType();
5725 bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue,
5727 unsigned &SplatBitSize,
5729 unsigned MinSplatBits) {
5730 MVT VT = getValueType(0);
5731 assert(VT.isVector() && "Expected a vector type");
5732 unsigned sz = VT.getSizeInBits();
5733 if (MinSplatBits > sz)
5736 SplatValue = APInt(sz, 0);
5737 SplatUndef = APInt(sz, 0);
5739 // Get the bits. Bits with undefined values (when the corresponding element
5740 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
5741 // in SplatValue. If any of the values are not constant, give up and return
5743 unsigned int nOps = getNumOperands();
5744 assert(nOps > 0 && "isConstantSplat has 0-size build vector");
5745 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits();
5746 for (unsigned i = 0; i < nOps; ++i) {
5747 SDValue OpVal = getOperand(i);
5748 unsigned BitPos = i * EltBitSize;
5750 if (OpVal.getOpcode() == ISD::UNDEF)
5751 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize);
5752 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal))
5753 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize).
5754 zextOrTrunc(sz) << BitPos);
5755 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal))
5756 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos;
5761 // The build_vector is all constants or undefs. Find the smallest element
5762 // size that splats the vector.
5764 HasAnyUndefs = (SplatUndef != 0);
5767 unsigned HalfSize = sz / 2;
5768 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize);
5769 APInt LowValue = APInt(SplatValue).trunc(HalfSize);
5770 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize);
5771 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize);
5773 // If the two halves do not match (ignoring undef bits), stop here.
5774 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
5775 MinSplatBits > HalfSize)
5778 SplatValue = HighValue | LowValue;
5779 SplatUndef = HighUndef & LowUndef;
5788 bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
5789 // Find the first non-undef value in the shuffle mask.
5791 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
5794 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!");
5796 // Make sure all remaining elements are either undef or the same as the first
5798 for (int Idx = Mask[i]; i != e; ++i)
5799 if (Mask[i] >= 0 && Mask[i] != Idx)