1 //===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAG class.
12 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/SelectionDAG.h"
14 #include "llvm/Constants.h"
15 #include "llvm/Analysis/ValueTracking.h"
16 #include "llvm/GlobalAlias.h"
17 #include "llvm/GlobalVariable.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/SetVector.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/StringExtras.h"
45 /// makeVTList - Return an instance of the SDVTList struct initialized with the
46 /// specified members.
47 static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
48 SDVTList Res = {VTs, NumVTs};
52 static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
53 switch (VT.getSimpleVT()) {
54 default: assert(0 && "Unknown FP format");
55 case MVT::f32: return &APFloat::IEEEsingle;
56 case MVT::f64: return &APFloat::IEEEdouble;
57 case MVT::f80: return &APFloat::x87DoubleExtended;
58 case MVT::f128: return &APFloat::IEEEquad;
59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
63 SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {}
65 //===----------------------------------------------------------------------===//
66 // ConstantFPSDNode Class
67 //===----------------------------------------------------------------------===//
69 /// isExactlyValue - We don't rely on operator== working on double values, as
70 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
71 /// As such, this method can be used to do an exact bit-for-bit comparison of
72 /// two floating point values.
73 bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const {
74 return getValueAPF().bitwiseIsEqual(V);
77 bool ConstantFPSDNode::isValueValidForType(MVT VT,
79 assert(VT.isFloatingPoint() && "Can only convert between FP types");
81 // PPC long double cannot be converted to any other type.
82 if (VT == MVT::ppcf128 ||
83 &Val.getSemantics() == &APFloat::PPCDoubleDouble)
86 // convert modifies in place, so make a copy.
87 APFloat Val2 = APFloat(Val);
89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
98 /// isBuildVectorAllOnes - Return true if the specified node is a
99 /// BUILD_VECTOR where all of the elements are ~0 or undef.
100 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
101 // Look through a bit convert.
102 if (N->getOpcode() == ISD::BIT_CONVERT)
103 N = N->getOperand(0).getNode();
105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
107 unsigned i = 0, e = N->getNumOperands();
109 // Skip over all of the undef values.
110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
113 // Do not accept an all-undef vector.
114 if (i == e) return false;
116 // Do not accept build_vectors that aren't all constants or which have non-~0
118 SDValue NotZero = N->getOperand(i);
119 if (isa<ConstantSDNode>(NotZero)) {
120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
122 } else if (isa<ConstantFPSDNode>(NotZero)) {
123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF().
124 bitcastToAPInt().isAllOnesValue())
129 // Okay, we have at least one ~0 value, check to see if the rest match or are
131 for (++i; i != e; ++i)
132 if (N->getOperand(i) != NotZero &&
133 N->getOperand(i).getOpcode() != ISD::UNDEF)
139 /// isBuildVectorAllZeros - Return true if the specified node is a
140 /// BUILD_VECTOR where all of the elements are 0 or undef.
141 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
142 // Look through a bit convert.
143 if (N->getOpcode() == ISD::BIT_CONVERT)
144 N = N->getOperand(0).getNode();
146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
148 unsigned i = 0, e = N->getNumOperands();
150 // Skip over all of the undef values.
151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
154 // Do not accept an all-undef vector.
155 if (i == e) return false;
157 // Do not accept build_vectors that aren't all constants or which have non-~0
159 SDValue Zero = N->getOperand(i);
160 if (isa<ConstantSDNode>(Zero)) {
161 if (!cast<ConstantSDNode>(Zero)->isNullValue())
163 } else if (isa<ConstantFPSDNode>(Zero)) {
164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero())
169 // Okay, we have at least one ~0 value, check to see if the rest match or are
171 for (++i; i != e; ++i)
172 if (N->getOperand(i) != Zero &&
173 N->getOperand(i).getOpcode() != ISD::UNDEF)
178 /// isScalarToVector - Return true if the specified node is a
179 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
180 /// element is not an undef.
181 bool ISD::isScalarToVector(const SDNode *N) {
182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
185 if (N->getOpcode() != ISD::BUILD_VECTOR)
187 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
189 unsigned NumElems = N->getNumOperands();
190 for (unsigned i = 1; i < NumElems; ++i) {
191 SDValue V = N->getOperand(i);
192 if (V.getOpcode() != ISD::UNDEF)
199 /// isDebugLabel - Return true if the specified node represents a debug
200 /// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
201 bool ISD::isDebugLabel(const SDNode *N) {
203 if (N->getOpcode() == ISD::DBG_LABEL)
205 if (N->isMachineOpcode() &&
206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL)
211 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
212 /// when given the operation for (X op Y).
213 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
214 // To perform this operation, we just need to swap the L and G bits of the
216 unsigned OldL = (Operation >> 2) & 1;
217 unsigned OldG = (Operation >> 1) & 1;
218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
219 (OldL << 1) | // New G bit
220 (OldG << 2)); // New L bit.
223 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
224 /// 'op' is a valid SetCC operation.
225 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
226 unsigned Operation = Op;
228 Operation ^= 7; // Flip L, G, E bits, but not U.
230 Operation ^= 15; // Flip all of the condition bits.
232 if (Operation > ISD::SETTRUE2)
233 Operation &= ~8; // Don't let N and U bits get set.
235 return ISD::CondCode(Operation);
239 /// isSignedOp - For an integer comparison, return 1 if the comparison is a
240 /// signed operation and 2 if the result is an unsigned comparison. Return zero
241 /// if the operation does not depend on the sign of the input (setne and seteq).
242 static int isSignedOp(ISD::CondCode Opcode) {
244 default: assert(0 && "Illegal integer setcc operation!");
246 case ISD::SETNE: return 0;
250 case ISD::SETGE: return 1;
254 case ISD::SETUGE: return 2;
258 /// getSetCCOrOperation - Return the result of a logical OR between different
259 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
260 /// returns SETCC_INVALID if it is not possible to represent the resultant
262 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
265 // Cannot fold a signed integer setcc with an unsigned integer setcc.
266 return ISD::SETCC_INVALID;
268 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
270 // If the N and U bits get set then the resultant comparison DOES suddenly
271 // care about orderedness, and is true when ordered.
272 if (Op > ISD::SETTRUE2)
273 Op &= ~16; // Clear the U bit if the N bit is set.
275 // Canonicalize illegal integer setcc's.
276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
279 return ISD::CondCode(Op);
282 /// getSetCCAndOperation - Return the result of a logical AND between different
283 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
284 /// function returns zero if it is not possible to represent the resultant
286 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
289 // Cannot fold a signed setcc with an unsigned setcc.
290 return ISD::SETCC_INVALID;
292 // Combine all of the condition bits.
293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
295 // Canonicalize illegal integer setcc's.
299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
300 case ISD::SETOEQ: // SETEQ & SETU[LG]E
301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
310 const TargetMachine &SelectionDAG::getTarget() const {
311 return MF->getTarget();
314 //===----------------------------------------------------------------------===//
315 // SDNode Profile Support
316 //===----------------------------------------------------------------------===//
318 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
320 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
324 /// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
325 /// solely with their pointer.
326 static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
327 ID.AddPointer(VTList.VTs);
330 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
332 static void AddNodeIDOperands(FoldingSetNodeID &ID,
333 const SDValue *Ops, unsigned NumOps) {
334 for (; NumOps; --NumOps, ++Ops) {
335 ID.AddPointer(Ops->getNode());
336 ID.AddInteger(Ops->getResNo());
340 /// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
342 static void AddNodeIDOperands(FoldingSetNodeID &ID,
343 const SDUse *Ops, unsigned NumOps) {
344 for (; NumOps; --NumOps, ++Ops) {
345 ID.AddPointer(Ops->getNode());
346 ID.AddInteger(Ops->getResNo());
350 static void AddNodeIDNode(FoldingSetNodeID &ID,
351 unsigned short OpC, SDVTList VTList,
352 const SDValue *OpList, unsigned N) {
353 AddNodeIDOpcode(ID, OpC);
354 AddNodeIDValueTypes(ID, VTList);
355 AddNodeIDOperands(ID, OpList, N);
358 /// AddNodeIDCustom - If this is an SDNode with special info, add this info to
360 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
361 switch (N->getOpcode()) {
362 default: break; // Normal nodes don't need extra info.
364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
366 case ISD::TargetConstant:
368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue());
370 case ISD::TargetConstantFP:
371 case ISD::ConstantFP: {
372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue());
375 case ISD::TargetGlobalAddress:
376 case ISD::GlobalAddress:
377 case ISD::TargetGlobalTLSAddress:
378 case ISD::GlobalTLSAddress: {
379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
380 ID.AddPointer(GA->getGlobal());
381 ID.AddInteger(GA->getOffset());
384 case ISD::BasicBlock:
385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock());
388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
390 case ISD::DBG_STOPPOINT: {
391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N);
392 ID.AddInteger(DSP->getLine());
393 ID.AddInteger(DSP->getColumn());
394 ID.AddPointer(DSP->getCompileUnit());
398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
400 case ISD::MEMOPERAND: {
401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO;
405 case ISD::FrameIndex:
406 case ISD::TargetFrameIndex:
407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex());
410 case ISD::TargetJumpTable:
411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex());
413 case ISD::ConstantPool:
414 case ISD::TargetConstantPool: {
415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
416 ID.AddInteger(CP->getAlignment());
417 ID.AddInteger(CP->getOffset());
418 if (CP->isMachineConstantPoolEntry())
419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID);
421 ID.AddPointer(CP->getConstVal());
425 const CallSDNode *Call = cast<CallSDNode>(N);
426 ID.AddInteger(Call->getCallingConv());
427 ID.AddInteger(Call->isVarArg());
431 const LoadSDNode *LD = cast<LoadSDNode>(N);
432 ID.AddInteger(LD->getMemoryVT().getRawBits());
433 ID.AddInteger(LD->getRawSubclassData());
437 const StoreSDNode *ST = cast<StoreSDNode>(N);
438 ID.AddInteger(ST->getMemoryVT().getRawBits());
439 ID.AddInteger(ST->getRawSubclassData());
442 case ISD::ATOMIC_CMP_SWAP:
443 case ISD::ATOMIC_SWAP:
444 case ISD::ATOMIC_LOAD_ADD:
445 case ISD::ATOMIC_LOAD_SUB:
446 case ISD::ATOMIC_LOAD_AND:
447 case ISD::ATOMIC_LOAD_OR:
448 case ISD::ATOMIC_LOAD_XOR:
449 case ISD::ATOMIC_LOAD_NAND:
450 case ISD::ATOMIC_LOAD_MIN:
451 case ISD::ATOMIC_LOAD_MAX:
452 case ISD::ATOMIC_LOAD_UMIN:
453 case ISD::ATOMIC_LOAD_UMAX: {
454 const AtomicSDNode *AT = cast<AtomicSDNode>(N);
455 ID.AddInteger(AT->getMemoryVT().getRawBits());
456 ID.AddInteger(AT->getRawSubclassData());
459 case ISD::VECTOR_SHUFFLE: {
460 const int *Mask = cast<ShuffleVectorSDNode>(N)->getMask();
461 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements();
463 ID.AddInteger(Mask[i]);
466 } // end switch (N->getOpcode())
469 /// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID
471 static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
472 AddNodeIDOpcode(ID, N->getOpcode());
473 // Add the return value info.
474 AddNodeIDValueTypes(ID, N->getVTList());
475 // Add the operand info.
476 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands());
478 // Handle SDNode leafs with special info.
479 AddNodeIDCustom(ID, N);
482 /// encodeMemSDNodeFlags - Generic routine for computing a value for use in
483 /// the CSE map that carries alignment, volatility, indexing mode, and
484 /// extension/truncation information.
486 static inline unsigned
487 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM,
488 bool isVolatile, unsigned Alignment) {
489 assert((ConvType & 3) == ConvType &&
490 "ConvType may not require more than 2 bits!");
491 assert((AM & 7) == AM &&
492 "AM may not require more than 3 bits!");
496 ((Log2_32(Alignment) + 1) << 6);
499 //===----------------------------------------------------------------------===//
500 // SelectionDAG Class
501 //===----------------------------------------------------------------------===//
503 /// doNotCSE - Return true if CSE should not be performed for this node.
504 static bool doNotCSE(SDNode *N) {
505 if (N->getValueType(0) == MVT::Flag)
506 return true; // Never CSE anything that produces a flag.
508 switch (N->getOpcode()) {
510 case ISD::HANDLENODE:
512 case ISD::DBG_STOPPOINT:
515 return true; // Never CSE these nodes.
518 // Check that remaining values produced are not flags.
519 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
520 if (N->getValueType(i) == MVT::Flag)
521 return true; // Never CSE anything that produces a flag.
526 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
528 void SelectionDAG::RemoveDeadNodes() {
529 // Create a dummy node (which is not added to allnodes), that adds a reference
530 // to the root node, preventing it from being deleted.
531 HandleSDNode Dummy(getRoot());
533 SmallVector<SDNode*, 128> DeadNodes;
535 // Add all obviously-dead nodes to the DeadNodes worklist.
536 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I)
538 DeadNodes.push_back(I);
540 RemoveDeadNodes(DeadNodes);
542 // If the root changed (e.g. it was a dead load, update the root).
543 setRoot(Dummy.getValue());
546 /// RemoveDeadNodes - This method deletes the unreachable nodes in the
547 /// given list, and any nodes that become unreachable as a result.
548 void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes,
549 DAGUpdateListener *UpdateListener) {
551 // Process the worklist, deleting the nodes and adding their uses to the
553 while (!DeadNodes.empty()) {
554 SDNode *N = DeadNodes.pop_back_val();
557 UpdateListener->NodeDeleted(N, 0);
559 // Take the node out of the appropriate CSE map.
560 RemoveNodeFromCSEMaps(N);
562 // Next, brutally remove the operand list. This is safe to do, as there are
563 // no cycles in the graph.
564 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
566 SDNode *Operand = Use.getNode();
569 // Now that we removed this operand, see if there are no uses of it left.
570 if (Operand->use_empty())
571 DeadNodes.push_back(Operand);
578 void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){
579 SmallVector<SDNode*, 16> DeadNodes(1, N);
580 RemoveDeadNodes(DeadNodes, UpdateListener);
583 void SelectionDAG::DeleteNode(SDNode *N) {
584 // First take this out of the appropriate CSE map.
585 RemoveNodeFromCSEMaps(N);
587 // Finally, remove uses due to operands of this node, remove from the
588 // AllNodes list, and delete the node.
589 DeleteNodeNotInCSEMaps(N);
592 void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) {
593 assert(N != AllNodes.begin() && "Cannot delete the entry node!");
594 assert(N->use_empty() && "Cannot delete a node that is not dead!");
596 // Drop all of the operands and decrement used node's use counts.
602 void SelectionDAG::DeallocateNode(SDNode *N) {
603 if (N->OperandsNeedDelete)
604 delete[] N->OperandList;
606 // Set the opcode to DELETED_NODE to help catch bugs when node
607 // memory is reallocated.
608 N->NodeType = ISD::DELETED_NODE;
610 NodeAllocator.Deallocate(AllNodes.remove(N));
613 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
614 /// correspond to it. This is useful when we're about to delete or repurpose
615 /// the node. We don't want future request for structurally identical nodes
616 /// to return N anymore.
617 bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
619 switch (N->getOpcode()) {
620 case ISD::EntryToken:
621 assert(0 && "EntryToken should not be in CSEMaps!");
623 case ISD::HANDLENODE: return false; // noop.
625 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
626 "Cond code doesn't exist!");
627 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0;
628 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0;
630 case ISD::ExternalSymbol:
631 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
633 case ISD::TargetExternalSymbol:
635 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol());
637 case ISD::VALUETYPE: {
638 MVT VT = cast<VTSDNode>(N)->getVT();
639 if (VT.isExtended()) {
640 Erased = ExtendedValueTypeNodes.erase(VT);
642 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
643 ValueTypeNodes[VT.getSimpleVT()] = 0;
648 // Remove it from the CSE Map.
649 Erased = CSEMap.RemoveNode(N);
653 // Verify that the node was actually in one of the CSE maps, unless it has a
654 // flag result (which cannot be CSE'd) or is one of the special cases that are
655 // not subject to CSE.
656 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
657 !N->isMachineOpcode() && !doNotCSE(N)) {
660 assert(0 && "Node is not in map!");
666 /// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE
667 /// maps and modified in place. Add it back to the CSE maps, unless an identical
668 /// node already exists, in which case transfer all its users to the existing
669 /// node. This transfer can potentially trigger recursive merging.
672 SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N,
673 DAGUpdateListener *UpdateListener) {
674 // For node types that aren't CSE'd, just act as if no identical node
677 SDNode *Existing = CSEMap.GetOrInsertNode(N);
679 // If there was already an existing matching node, use ReplaceAllUsesWith
680 // to replace the dead one with the existing one. This can cause
681 // recursive merging of other unrelated nodes down the line.
682 ReplaceAllUsesWith(N, Existing, UpdateListener);
684 // N is now dead. Inform the listener if it exists and delete it.
686 UpdateListener->NodeDeleted(N, Existing);
687 DeleteNodeNotInCSEMaps(N);
692 // If the node doesn't already exist, we updated it. Inform a listener if
695 UpdateListener->NodeUpdated(N);
698 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
699 /// were replaced with those specified. If this node is never memoized,
700 /// return null, otherwise return a pointer to the slot it would take. If a
701 /// node already exists with these operands, the slot will be non-null.
702 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
707 SDValue Ops[] = { Op };
709 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1);
710 AddNodeIDCustom(ID, N);
711 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
714 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
715 /// were replaced with those specified. If this node is never memoized,
716 /// return null, otherwise return a pointer to the slot it would take. If a
717 /// node already exists with these operands, the slot will be non-null.
718 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
719 SDValue Op1, SDValue Op2,
724 SDValue Ops[] = { Op1, Op2 };
726 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2);
727 AddNodeIDCustom(ID, N);
728 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
732 /// FindModifiedNodeSlot - Find a slot for the specified node if its operands
733 /// were replaced with those specified. If this node is never memoized,
734 /// return null, otherwise return a pointer to the slot it would take. If a
735 /// node already exists with these operands, the slot will be non-null.
736 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
737 const SDValue *Ops,unsigned NumOps,
743 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps);
744 AddNodeIDCustom(ID, N);
745 return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
748 /// VerifyNode - Sanity check the given node. Aborts if it is invalid.
749 void SelectionDAG::VerifyNode(SDNode *N) {
750 switch (N->getOpcode()) {
753 case ISD::BUILD_PAIR: {
754 MVT VT = N->getValueType(0);
755 assert(N->getNumValues() == 1 && "Too many results!");
756 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
757 "Wrong return type!");
758 assert(N->getNumOperands() == 2 && "Wrong number of operands!");
759 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() &&
760 "Mismatched operand types!");
761 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() &&
762 "Wrong operand type!");
763 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() &&
764 "Wrong return type size");
767 case ISD::BUILD_VECTOR: {
768 assert(N->getNumValues() == 1 && "Too many results!");
769 assert(N->getValueType(0).isVector() && "Wrong return type!");
770 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
771 "Wrong number of operands!");
777 /// getMVTAlignment - Compute the default alignment value for the
780 unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
781 const Type *Ty = VT == MVT::iPTR ?
782 PointerType::get(Type::Int8Ty, 0) :
785 return TLI.getTargetData()->getABITypeAlignment(Ty);
788 // EntryNode could meaningfully have debug info if we can find it...
789 SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
790 : TLI(tli), FLI(fli), DW(0),
791 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
792 getVTList(MVT::Other)), Root(getEntryNode()) {
793 AllNodes.push_back(&EntryNode);
796 void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
803 SelectionDAG::~SelectionDAG() {
807 void SelectionDAG::allnodes_clear() {
808 assert(&*AllNodes.begin() == &EntryNode);
809 AllNodes.remove(AllNodes.begin());
810 while (!AllNodes.empty())
811 DeallocateNode(AllNodes.begin());
814 void SelectionDAG::clear() {
816 OperandAllocator.Reset();
819 ExtendedValueTypeNodes.clear();
820 ExternalSymbols.clear();
821 TargetExternalSymbols.clear();
822 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
823 static_cast<CondCodeSDNode*>(0));
824 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
825 static_cast<SDNode*>(0));
827 EntryNode.UseList = 0;
828 AllNodes.push_back(&EntryNode);
829 Root = getEntryNode();
832 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
833 if (Op.getValueType() == VT) return Op;
834 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
836 return getNode(ISD::AND, DL, Op.getValueType(), Op,
837 getConstant(Imm, Op.getValueType()));
840 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
842 SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
843 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
845 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
846 return getNode(ISD::XOR, DL, VT, Val, NegOne);
849 SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
850 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
851 assert((EltVT.getSizeInBits() >= 64 ||
852 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
853 "getConstant with a uint64_t value that doesn't fit in the type!");
854 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
857 SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
858 return getConstant(*ConstantInt::get(Val), VT, isT);
861 SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) {
862 assert(VT.isInteger() && "Cannot create FP integer constant!");
864 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
865 assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
866 "APInt size does not match type size!");
868 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
870 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
874 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
876 return SDValue(N, 0);
878 N = NodeAllocator.Allocate<ConstantSDNode>();
879 new (N) ConstantSDNode(isT, &Val, EltVT);
880 CSEMap.InsertNode(N, IP);
881 AllNodes.push_back(N);
884 SDValue Result(N, 0);
886 SmallVector<SDValue, 8> Ops;
887 Ops.assign(VT.getVectorNumElements(), Result);
888 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
889 VT, &Ops[0], Ops.size());
894 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
895 return getConstant(Val, TLI.getPointerTy(), isTarget);
899 SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
900 return getConstantFP(*ConstantFP::get(V), VT, isTarget);
903 SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
904 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
907 VT.isVector() ? VT.getVectorElementType() : VT;
909 // Do the map lookup using the actual bit pattern for the floating point
910 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and
911 // we don't have issues with SNANs.
912 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
914 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
918 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
920 return SDValue(N, 0);
922 N = NodeAllocator.Allocate<ConstantFPSDNode>();
923 new (N) ConstantFPSDNode(isTarget, &V, EltVT);
924 CSEMap.InsertNode(N, IP);
925 AllNodes.push_back(N);
928 SDValue Result(N, 0);
930 SmallVector<SDValue, 8> Ops;
931 Ops.assign(VT.getVectorNumElements(), Result);
932 // FIXME DebugLoc info might be appropriate here
933 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
934 VT, &Ops[0], Ops.size());
939 SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
941 VT.isVector() ? VT.getVectorElementType() : VT;
943 return getConstantFP(APFloat((float)Val), VT, isTarget);
945 return getConstantFP(APFloat(Val), VT, isTarget);
948 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
949 MVT VT, int64_t Offset,
953 // Truncate (with sign-extension) the offset value to the pointer size.
954 unsigned BitWidth = TLI.getPointerTy().getSizeInBits();
956 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth));
958 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
960 // If GV is an alias then use the aliasee for determining thread-localness.
961 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
962 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
965 if (GVar && GVar->isThreadLocal())
966 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
968 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
971 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
973 ID.AddInteger(Offset);
975 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
976 return SDValue(E, 0);
977 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>();
978 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset);
979 CSEMap.InsertNode(N, IP);
980 AllNodes.push_back(N);
981 return SDValue(N, 0);
984 SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
985 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
987 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
990 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
991 return SDValue(E, 0);
992 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>();
993 new (N) FrameIndexSDNode(FI, VT, isTarget);
994 CSEMap.InsertNode(N, IP);
995 AllNodes.push_back(N);
996 return SDValue(N, 0);
999 SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){
1000 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1001 FoldingSetNodeID ID;
1002 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1005 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1006 return SDValue(E, 0);
1007 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>();
1008 new (N) JumpTableSDNode(JTI, VT, isTarget);
1009 CSEMap.InsertNode(N, IP);
1010 AllNodes.push_back(N);
1011 return SDValue(N, 0);
1014 SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
1015 unsigned Alignment, int Offset,
1018 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType());
1019 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1020 FoldingSetNodeID ID;
1021 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1022 ID.AddInteger(Alignment);
1023 ID.AddInteger(Offset);
1026 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1027 return SDValue(E, 0);
1028 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1029 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
1030 CSEMap.InsertNode(N, IP);
1031 AllNodes.push_back(N);
1032 return SDValue(N, 0);
1036 SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
1037 unsigned Alignment, int Offset,
1040 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType());
1041 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1042 FoldingSetNodeID ID;
1043 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
1044 ID.AddInteger(Alignment);
1045 ID.AddInteger(Offset);
1046 C->AddSelectionDAGCSEId(ID);
1048 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1049 return SDValue(E, 0);
1050 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>();
1051 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment);
1052 CSEMap.InsertNode(N, IP);
1053 AllNodes.push_back(N);
1054 return SDValue(N, 0);
1057 SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
1058 FoldingSetNodeID ID;
1059 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1062 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1063 return SDValue(E, 0);
1064 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>();
1065 new (N) BasicBlockSDNode(MBB);
1066 CSEMap.InsertNode(N, IP);
1067 AllNodes.push_back(N);
1068 return SDValue(N, 0);
1071 SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
1072 FoldingSetNodeID ID;
1073 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
1074 ID.AddInteger(Flags.getRawBits());
1076 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1077 return SDValue(E, 0);
1078 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>();
1079 new (N) ARG_FLAGSSDNode(Flags);
1080 CSEMap.InsertNode(N, IP);
1081 AllNodes.push_back(N);
1082 return SDValue(N, 0);
1085 SDValue SelectionDAG::getValueType(MVT VT) {
1086 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
1087 ValueTypeNodes.resize(VT.getSimpleVT()+1);
1089 SDNode *&N = VT.isExtended() ?
1090 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
1092 if (N) return SDValue(N, 0);
1093 N = NodeAllocator.Allocate<VTSDNode>();
1094 new (N) VTSDNode(VT);
1095 AllNodes.push_back(N);
1096 return SDValue(N, 0);
1099 SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
1100 SDNode *&N = ExternalSymbols[Sym];
1101 if (N) return SDValue(N, 0);
1102 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1103 new (N) ExternalSymbolSDNode(false, Sym, VT);
1104 AllNodes.push_back(N);
1105 return SDValue(N, 0);
1108 SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
1109 SDNode *&N = TargetExternalSymbols[Sym];
1110 if (N) return SDValue(N, 0);
1111 N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
1112 new (N) ExternalSymbolSDNode(true, Sym, VT);
1113 AllNodes.push_back(N);
1114 return SDValue(N, 0);
1117 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1118 if ((unsigned)Cond >= CondCodeNodes.size())
1119 CondCodeNodes.resize(Cond+1);
1121 if (CondCodeNodes[Cond] == 0) {
1122 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>();
1123 new (N) CondCodeSDNode(Cond);
1124 CondCodeNodes[Cond] = N;
1125 AllNodes.push_back(N);
1127 return SDValue(CondCodeNodes[Cond], 0);
1130 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
1132 int NElts = M.size();
1133 for (int i = 0; i != NElts; ++i) {
1141 SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1,
1142 SDValue N2, const int *Mask) {
1143 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
1144 assert(VT.isVector() && N1.getValueType().isVector() &&
1145 "Vector Shuffle VTs must be a vectors");
1146 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType()
1147 && "Vector Shuffle VTs must have same element type");
1149 // Canonicalize shuffle undef, undef -> undef
1150 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
1153 // Validate that all the indices past in in Mask are within the range of
1154 // elements input to the shuffle.
1155 int NElts = VT.getVectorNumElements();
1156 SmallVector<int, 8> MaskVec;
1157 for (int i = 0; i != NElts; ++i) {
1158 if (Mask[i] >= (NElts * 2)) {
1159 assert(0 && "Index out of range");
1162 MaskVec.push_back(Mask[i]);
1165 // Canonicalize shuffle v, v -> v, undef
1168 for (int i = 0; i != NElts; ++i)
1169 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
1172 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
1173 if (N1.getOpcode() == ISD::UNDEF)
1174 commuteShuffle(N1, N2, MaskVec);
1176 // Canonicalize all index into lhs, -> shuffle lhs, undef
1177 // Canonicalize all index into rhs, -> shuffle rhs, undef
1178 bool AllLHS = true, AllRHS = true;
1179 bool N2Undef = N2.getOpcode() == ISD::UNDEF;
1180 for (int i = 0; i != NElts; ++i) {
1181 if (MaskVec[i] >= NElts) {
1186 } else if (MaskVec[i] >= 0) {
1190 if (AllLHS && AllRHS)
1191 return getUNDEF(VT);
1196 commuteShuffle(N1, N2, MaskVec);
1199 // If Identity shuffle, or all shuffle in to undef, return that node.
1200 bool AllUndef = true;
1201 bool Identity = true;
1202 for (int i = 0; i < NElts; ++i) {
1203 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity = false;
1204 if (MaskVec[i] >= 0) AllUndef = false;
1209 return getUNDEF(VT);
1211 FoldingSetNodeID ID;
1212 SDValue Ops[2] = { N1, N2 };
1213 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
1214 for (int i = 0; i != NElts; ++i)
1215 ID.AddInteger(MaskVec[i]);
1218 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1219 return SDValue(E, 0);
1221 // Allocate the mask array for the node out of the BumpPtrAllocator, since
1222 // SDNode doesn't have access to it. This memory will be "leaked" when
1223 // the node is deallocated, but recovered when the NodeAllocator is released.
1224 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts);
1225 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int));
1227 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>();
1228 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc);
1229 CSEMap.InsertNode(N, IP);
1230 AllNodes.push_back(N);
1231 return SDValue(N, 0);
1234 SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
1235 SDValue Val, SDValue DTy,
1236 SDValue STy, SDValue Rnd, SDValue Sat,
1237 ISD::CvtCode Code) {
1238 // If the src and dest types are the same and the conversion is between
1239 // integer types of the same sign or two floats, no conversion is necessary.
1241 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF))
1244 FoldingSetNodeID ID;
1246 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1247 return SDValue(E, 0);
1248 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>();
1249 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat };
1250 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code);
1251 CSEMap.InsertNode(N, IP);
1252 AllNodes.push_back(N);
1253 return SDValue(N, 0);
1256 SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
1257 FoldingSetNodeID ID;
1258 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1259 ID.AddInteger(RegNo);
1261 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1262 return SDValue(E, 0);
1263 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>();
1264 new (N) RegisterSDNode(RegNo, VT);
1265 CSEMap.InsertNode(N, IP);
1266 AllNodes.push_back(N);
1267 return SDValue(N, 0);
1270 SDValue SelectionDAG::getDbgStopPoint(SDValue Root,
1271 unsigned Line, unsigned Col,
1273 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>();
1274 new (N) DbgStopPointSDNode(Root, Line, Col, CU);
1275 AllNodes.push_back(N);
1276 return SDValue(N, 0);
1279 SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
1282 FoldingSetNodeID ID;
1283 SDValue Ops[] = { Root };
1284 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
1285 ID.AddInteger(LabelID);
1287 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1288 return SDValue(E, 0);
1289 SDNode *N = NodeAllocator.Allocate<LabelSDNode>();
1290 new (N) LabelSDNode(Opcode, dl, Root, LabelID);
1291 CSEMap.InsertNode(N, IP);
1292 AllNodes.push_back(N);
1293 return SDValue(N, 0);
1296 SDValue SelectionDAG::getSrcValue(const Value *V) {
1297 assert((!V || isa<PointerType>(V->getType())) &&
1298 "SrcValue is not a pointer?");
1300 FoldingSetNodeID ID;
1301 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1305 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1306 return SDValue(E, 0);
1308 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>();
1309 new (N) SrcValueSDNode(V);
1310 CSEMap.InsertNode(N, IP);
1311 AllNodes.push_back(N);
1312 return SDValue(N, 0);
1315 SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
1317 const Value *v = MO.getValue();
1318 assert((!v || isa<PointerType>(v->getType())) &&
1319 "SrcValue is not a pointer?");
1322 FoldingSetNodeID ID;
1323 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
1327 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1328 return SDValue(E, 0);
1330 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>();
1331 new (N) MemOperandSDNode(MO);
1332 CSEMap.InsertNode(N, IP);
1333 AllNodes.push_back(N);
1334 return SDValue(N, 0);
1337 /// getShiftAmountOperand - Return the specified value casted to
1338 /// the target's desired shift amount type.
1339 SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
1340 MVT OpTy = Op.getValueType();
1341 MVT ShTy = TLI.getShiftAmountTy();
1342 if (OpTy == ShTy || OpTy.isVector()) return Op;
1344 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1345 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op);
1348 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
1349 /// specified value type.
1350 SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
1351 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1352 unsigned ByteSize = VT.getStoreSizeInBits()/8;
1353 const Type *Ty = VT.getTypeForMVT();
1354 unsigned StackAlign =
1355 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
1357 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
1358 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1361 /// CreateStackTemporary - Create a stack temporary suitable for holding
1362 /// either of the specified value types.
1363 SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
1364 unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
1365 VT2.getStoreSizeInBits())/8;
1366 const Type *Ty1 = VT1.getTypeForMVT();
1367 const Type *Ty2 = VT2.getTypeForMVT();
1368 const TargetData *TD = TLI.getTargetData();
1369 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
1370 TD->getPrefTypeAlignment(Ty2));
1372 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
1373 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align);
1374 return getFrameIndex(FrameIdx, TLI.getPointerTy());
1377 SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
1378 SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
1379 // These setcc operations always fold.
1383 case ISD::SETFALSE2: return getConstant(0, VT);
1385 case ISD::SETTRUE2: return getConstant(1, VT);
1397 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!");
1401 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
1402 const APInt &C2 = N2C->getAPIntValue();
1403 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1404 const APInt &C1 = N1C->getAPIntValue();
1407 default: assert(0 && "Unknown integer setcc!");
1408 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1409 case ISD::SETNE: return getConstant(C1 != C2, VT);
1410 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1411 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1412 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1413 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1414 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1415 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1416 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1417 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1421 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1422 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
1423 // No compile time operations on this type yet.
1424 if (N1C->getValueType(0) == MVT::ppcf128)
1427 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
1430 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1431 return getUNDEF(VT);
1433 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1434 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1435 return getUNDEF(VT);
1437 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1438 R==APFloat::cmpLessThan, VT);
1439 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1440 return getUNDEF(VT);
1442 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1443 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1444 return getUNDEF(VT);
1446 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1447 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1448 return getUNDEF(VT);
1450 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1451 R==APFloat::cmpEqual, VT);
1452 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1453 return getUNDEF(VT);
1455 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1456 R==APFloat::cmpEqual, VT);
1457 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1458 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1459 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1460 R==APFloat::cmpEqual, VT);
1461 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1462 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1463 R==APFloat::cmpLessThan, VT);
1464 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1465 R==APFloat::cmpUnordered, VT);
1466 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1467 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1470 // Ensure that the constant occurs on the RHS.
1471 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1475 // Could not fold it.
1479 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
1480 /// use this predicate to simplify operations downstream.
1481 bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
1482 unsigned BitWidth = Op.getValueSizeInBits();
1483 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
1486 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
1487 /// this predicate to simplify operations downstream. Mask is known to be zero
1488 /// for bits that V cannot have.
1489 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
1490 unsigned Depth) const {
1491 APInt KnownZero, KnownOne;
1492 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1493 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1494 return (KnownZero & Mask) == Mask;
1497 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
1498 /// known to be either zero or one and return them in the KnownZero/KnownOne
1499 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
1501 void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
1502 APInt &KnownZero, APInt &KnownOne,
1503 unsigned Depth) const {
1504 unsigned BitWidth = Mask.getBitWidth();
1505 assert(BitWidth == Op.getValueType().getSizeInBits() &&
1506 "Mask size mismatches value type size!");
1508 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
1509 if (Depth == 6 || Mask == 0)
1510 return; // Limit search depth.
1512 APInt KnownZero2, KnownOne2;
1514 switch (Op.getOpcode()) {
1516 // We know all of the bits for a constant!
1517 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask;
1518 KnownZero = ~KnownOne & Mask;
1521 // If either the LHS or the RHS are Zero, the result is zero.
1522 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1523 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero,
1524 KnownZero2, KnownOne2, Depth+1);
1525 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1526 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1528 // Output known-1 bits are only known if set in both the LHS & RHS.
1529 KnownOne &= KnownOne2;
1530 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1531 KnownZero |= KnownZero2;
1534 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1535 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne,
1536 KnownZero2, KnownOne2, Depth+1);
1537 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1538 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1540 // Output known-0 bits are only known if clear in both the LHS & RHS.
1541 KnownZero &= KnownZero2;
1542 // Output known-1 are known to be set if set in either the LHS | RHS.
1543 KnownOne |= KnownOne2;
1546 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1547 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
1548 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1549 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1551 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1552 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1553 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1554 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1555 KnownZero = KnownZeroOut;
1559 APInt Mask2 = APInt::getAllOnesValue(BitWidth);
1560 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1);
1561 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1562 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1563 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1565 // If low bits are zero in either operand, output low known-0 bits.
1566 // Also compute a conserative estimate for high known-0 bits.
1567 // More trickiness is possible, but this is sufficient for the
1568 // interesting case of alignment computation.
1570 unsigned TrailZ = KnownZero.countTrailingOnes() +
1571 KnownZero2.countTrailingOnes();
1572 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() +
1573 KnownZero2.countLeadingOnes(),
1574 BitWidth) - BitWidth;
1576 TrailZ = std::min(TrailZ, BitWidth);
1577 LeadZ = std::min(LeadZ, BitWidth);
1578 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
1579 APInt::getHighBitsSet(BitWidth, LeadZ);
1584 // For the purposes of computing leading zeros we can conservatively
1585 // treat a udiv as a logical right shift by the power of 2 known to
1586 // be less than the denominator.
1587 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1588 ComputeMaskedBits(Op.getOperand(0),
1589 AllOnes, KnownZero2, KnownOne2, Depth+1);
1590 unsigned LeadZ = KnownZero2.countLeadingOnes();
1594 ComputeMaskedBits(Op.getOperand(1),
1595 AllOnes, KnownZero2, KnownOne2, Depth+1);
1596 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
1597 if (RHSUnknownLeadingOnes != BitWidth)
1598 LeadZ = std::min(BitWidth,
1599 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1);
1601 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask;
1605 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
1606 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
1607 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1608 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1610 // Only known if known in both the LHS and RHS.
1611 KnownOne &= KnownOne2;
1612 KnownZero &= KnownZero2;
1614 case ISD::SELECT_CC:
1615 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
1616 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
1617 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1618 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1620 // Only known if known in both the LHS and RHS.
1621 KnownOne &= KnownOne2;
1622 KnownZero &= KnownZero2;
1630 if (Op.getResNo() != 1)
1632 // The boolean result conforms to getBooleanContents. Fall through.
1634 // If we know the result of a setcc has the top bits zero, use this info.
1635 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
1637 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1640 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
1641 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1642 unsigned ShAmt = SA->getZExtValue();
1644 // If the shift count is an invalid immediate, don't do anything.
1645 if (ShAmt >= BitWidth)
1648 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt),
1649 KnownZero, KnownOne, Depth+1);
1650 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1651 KnownZero <<= ShAmt;
1653 // low bits known zero.
1654 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt);
1658 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
1659 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1660 unsigned ShAmt = SA->getZExtValue();
1662 // If the shift count is an invalid immediate, don't do anything.
1663 if (ShAmt >= BitWidth)
1666 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt),
1667 KnownZero, KnownOne, Depth+1);
1668 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1669 KnownZero = KnownZero.lshr(ShAmt);
1670 KnownOne = KnownOne.lshr(ShAmt);
1672 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1673 KnownZero |= HighBits; // High bits known zero.
1677 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1678 unsigned ShAmt = SA->getZExtValue();
1680 // If the shift count is an invalid immediate, don't do anything.
1681 if (ShAmt >= BitWidth)
1684 APInt InDemandedMask = (Mask << ShAmt);
1685 // If any of the demanded bits are produced by the sign extension, we also
1686 // demand the input sign bit.
1687 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
1688 if (HighBits.getBoolValue())
1689 InDemandedMask |= APInt::getSignBit(BitWidth);
1691 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
1693 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1694 KnownZero = KnownZero.lshr(ShAmt);
1695 KnownOne = KnownOne.lshr(ShAmt);
1697 // Handle the sign bits.
1698 APInt SignBit = APInt::getSignBit(BitWidth);
1699 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask.
1701 if (KnownZero.intersects(SignBit)) {
1702 KnownZero |= HighBits; // New bits are known zero.
1703 } else if (KnownOne.intersects(SignBit)) {
1704 KnownOne |= HighBits; // New bits are known one.
1708 case ISD::SIGN_EXTEND_INREG: {
1709 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1710 unsigned EBits = EVT.getSizeInBits();
1712 // Sign extension. Compute the demanded bits in the result that are not
1713 // present in the input.
1714 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask;
1716 APInt InSignBit = APInt::getSignBit(EBits);
1717 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits);
1719 // If the sign extended bits are demanded, we know that the sign
1721 InSignBit.zext(BitWidth);
1722 if (NewBits.getBoolValue())
1723 InputDemandedBits |= InSignBit;
1725 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
1726 KnownZero, KnownOne, Depth+1);
1727 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1729 // If the sign bit of the input is known set or clear, then we know the
1730 // top bits of the result.
1731 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear
1732 KnownZero |= NewBits;
1733 KnownOne &= ~NewBits;
1734 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1735 KnownOne |= NewBits;
1736 KnownZero &= ~NewBits;
1737 } else { // Input sign bit unknown
1738 KnownZero &= ~NewBits;
1739 KnownOne &= ~NewBits;
1746 unsigned LowBits = Log2_32(BitWidth)+1;
1747 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits);
1752 if (ISD::isZEXTLoad(Op.getNode())) {
1753 LoadSDNode *LD = cast<LoadSDNode>(Op);
1754 MVT VT = LD->getMemoryVT();
1755 unsigned MemBits = VT.getSizeInBits();
1756 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
1760 case ISD::ZERO_EXTEND: {
1761 MVT InVT = Op.getOperand(0).getValueType();
1762 unsigned InBits = InVT.getSizeInBits();
1763 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1764 APInt InMask = Mask;
1765 InMask.trunc(InBits);
1766 KnownZero.trunc(InBits);
1767 KnownOne.trunc(InBits);
1768 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1769 KnownZero.zext(BitWidth);
1770 KnownOne.zext(BitWidth);
1771 KnownZero |= NewBits;
1774 case ISD::SIGN_EXTEND: {
1775 MVT InVT = Op.getOperand(0).getValueType();
1776 unsigned InBits = InVT.getSizeInBits();
1777 APInt InSignBit = APInt::getSignBit(InBits);
1778 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
1779 APInt InMask = Mask;
1780 InMask.trunc(InBits);
1782 // If any of the sign extended bits are demanded, we know that the sign
1783 // bit is demanded. Temporarily set this bit in the mask for our callee.
1784 if (NewBits.getBoolValue())
1785 InMask |= InSignBit;
1787 KnownZero.trunc(InBits);
1788 KnownOne.trunc(InBits);
1789 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1791 // Note if the sign bit is known to be zero or one.
1792 bool SignBitKnownZero = KnownZero.isNegative();
1793 bool SignBitKnownOne = KnownOne.isNegative();
1794 assert(!(SignBitKnownZero && SignBitKnownOne) &&
1795 "Sign bit can't be known to be both zero and one!");
1797 // If the sign bit wasn't actually demanded by our caller, we don't
1798 // want it set in the KnownZero and KnownOne result values. Reset the
1799 // mask and reapply it to the result values.
1801 InMask.trunc(InBits);
1802 KnownZero &= InMask;
1805 KnownZero.zext(BitWidth);
1806 KnownOne.zext(BitWidth);
1808 // If the sign bit is known zero or one, the top bits match.
1809 if (SignBitKnownZero)
1810 KnownZero |= NewBits;
1811 else if (SignBitKnownOne)
1812 KnownOne |= NewBits;
1815 case ISD::ANY_EXTEND: {
1816 MVT InVT = Op.getOperand(0).getValueType();
1817 unsigned InBits = InVT.getSizeInBits();
1818 APInt InMask = Mask;
1819 InMask.trunc(InBits);
1820 KnownZero.trunc(InBits);
1821 KnownOne.trunc(InBits);
1822 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1823 KnownZero.zext(BitWidth);
1824 KnownOne.zext(BitWidth);
1827 case ISD::TRUNCATE: {
1828 MVT InVT = Op.getOperand(0).getValueType();
1829 unsigned InBits = InVT.getSizeInBits();
1830 APInt InMask = Mask;
1831 InMask.zext(InBits);
1832 KnownZero.zext(InBits);
1833 KnownOne.zext(InBits);
1834 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
1835 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1836 KnownZero.trunc(BitWidth);
1837 KnownOne.trunc(BitWidth);
1840 case ISD::AssertZext: {
1841 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1842 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
1843 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1845 KnownZero |= (~InMask) & Mask;
1849 // All bits are zero except the low bit.
1850 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1854 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
1855 // We know that the top bits of C-X are clear if X contains less bits
1856 // than C (i.e. no wrap-around can happen). For example, 20-X is
1857 // positive if we can prove that X is >= 0 and < 16.
1858 if (CLHS->getAPIntValue().isNonNegative()) {
1859 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
1860 // NLZ can't be BitWidth with no sign bit
1861 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
1862 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2,
1865 // If all of the MaskV bits are known to be zero, then we know the
1866 // output top bits are zero, because we now know that the output is
1868 if ((KnownZero2 & MaskV) == MaskV) {
1869 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros();
1870 // Top bits known zero.
1871 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask;
1878 // Output known-0 bits are known if clear or set in both the low clear bits
1879 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
1880 // low 3 bits clear.
1881 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes());
1882 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
1883 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1884 unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
1886 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1);
1887 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1888 KnownZeroOut = std::min(KnownZeroOut,
1889 KnownZero2.countTrailingOnes());
1891 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut);
1895 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1896 const APInt &RA = Rem->getAPIntValue();
1897 if (RA.isPowerOf2() || (-RA).isPowerOf2()) {
1898 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA;
1899 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
1900 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
1902 // If the sign bit of the first operand is zero, the sign bit of
1903 // the result is zero. If the first operand has no one bits below
1904 // the second operand's single 1 bit, its sign will be zero.
1905 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
1906 KnownZero2 |= ~LowBits;
1908 KnownZero |= KnownZero2 & Mask;
1910 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1915 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1916 const APInt &RA = Rem->getAPIntValue();
1917 if (RA.isPowerOf2()) {
1918 APInt LowBits = (RA - 1);
1919 APInt Mask2 = LowBits & Mask;
1920 KnownZero |= ~LowBits & Mask;
1921 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1);
1922 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
1927 // Since the result is less than or equal to either operand, any leading
1928 // zero bits in either operand must also exist in the result.
1929 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
1930 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne,
1932 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2,
1935 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(),
1936 KnownZero2.countLeadingOnes());
1938 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask;
1942 // Allow the target to implement this method for its nodes.
1943 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1944 case ISD::INTRINSIC_WO_CHAIN:
1945 case ISD::INTRINSIC_W_CHAIN:
1946 case ISD::INTRINSIC_VOID:
1947 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this);
1953 /// ComputeNumSignBits - Return the number of times the sign bit of the
1954 /// register is replicated into the other bits. We know that at least 1 bit
1955 /// is always equal to the sign bit (itself), but other cases can give us
1956 /// information. For example, immediately after an "SRA X, 2", we know that
1957 /// the top 3 bits are all equal to each other, so we return 3.
1958 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
1959 MVT VT = Op.getValueType();
1960 assert(VT.isInteger() && "Invalid VT!");
1961 unsigned VTBits = VT.getSizeInBits();
1963 unsigned FirstAnswer = 1;
1966 return 1; // Limit search depth.
1968 switch (Op.getOpcode()) {
1970 case ISD::AssertSext:
1971 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1972 return VTBits-Tmp+1;
1973 case ISD::AssertZext:
1974 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1977 case ISD::Constant: {
1978 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
1979 // If negative, return # leading ones.
1980 if (Val.isNegative())
1981 return Val.countLeadingOnes();
1983 // Return # leading zeros.
1984 return Val.countLeadingZeros();
1987 case ISD::SIGN_EXTEND:
1988 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
1989 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
1991 case ISD::SIGN_EXTEND_INREG:
1992 // Max of the input and what this extends.
1993 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
1996 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1997 return std::max(Tmp, Tmp2);
2000 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2001 // SRA X, C -> adds C sign bits.
2002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2003 Tmp += C->getZExtValue();
2004 if (Tmp > VTBits) Tmp = VTBits;
2008 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2009 // shl destroys sign bits.
2010 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2011 if (C->getZExtValue() >= VTBits || // Bad shift.
2012 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out.
2013 return Tmp - C->getZExtValue();
2018 case ISD::XOR: // NOT is handled here.
2019 // Logical binary ops preserve the number of sign bits at the worst.
2020 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2022 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2023 FirstAnswer = std::min(Tmp, Tmp2);
2024 // We computed what we know about the sign bits as our first
2025 // answer. Now proceed to the generic code that uses
2026 // ComputeMaskedBits, and pick whichever answer is better.
2031 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2032 if (Tmp == 1) return 1; // Early out.
2033 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1);
2034 return std::min(Tmp, Tmp2);
2042 if (Op.getResNo() != 1)
2044 // The boolean result conforms to getBooleanContents. Fall through.
2046 // If setcc returns 0/-1, all bits are sign bits.
2047 if (TLI.getBooleanContents() ==
2048 TargetLowering::ZeroOrNegativeOneBooleanContent)
2053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2054 unsigned RotAmt = C->getZExtValue() & (VTBits-1);
2056 // Handle rotate right by N like a rotate left by 32-N.
2057 if (Op.getOpcode() == ISD::ROTR)
2058 RotAmt = (VTBits-RotAmt) & (VTBits-1);
2060 // If we aren't rotating out all of the known-in sign bits, return the
2061 // number that are left. This handles rotl(sext(x), 1) for example.
2062 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2063 if (Tmp > RotAmt+1) return Tmp-RotAmt;
2067 // Add can have at most one carry bit. Thus we know that the output
2068 // is, at worst, one more bit than the inputs.
2069 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2070 if (Tmp == 1) return 1; // Early out.
2072 // Special case decrementing a value (ADD X, -1):
2073 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
2074 if (CRHS->isAllOnesValue()) {
2075 APInt KnownZero, KnownOne;
2076 APInt Mask = APInt::getAllOnesValue(VTBits);
2077 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2079 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2081 if ((KnownZero | APInt(VTBits, 1)) == Mask)
2084 // If we are subtracting one from a positive number, there is no carry
2085 // out of the result.
2086 if (KnownZero.isNegative())
2090 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2091 if (Tmp2 == 1) return 1;
2092 return std::min(Tmp, Tmp2)-1;
2096 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
2097 if (Tmp2 == 1) return 1;
2100 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
2101 if (CLHS->isNullValue()) {
2102 APInt KnownZero, KnownOne;
2103 APInt Mask = APInt::getAllOnesValue(VTBits);
2104 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
2105 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2107 if ((KnownZero | APInt(VTBits, 1)) == Mask)
2110 // If the input is known to be positive (the sign bit is known clear),
2111 // the output of the NEG has the same number of sign bits as the input.
2112 if (KnownZero.isNegative())
2115 // Otherwise, we treat this like a SUB.
2118 // Sub can have at most one carry bit. Thus we know that the output
2119 // is, at worst, one more bit than the inputs.
2120 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
2121 if (Tmp == 1) return 1; // Early out.
2122 return std::min(Tmp, Tmp2)-1;
2125 // FIXME: it's tricky to do anything useful for this, but it is an important
2126 // case for targets like X86.
2130 // Handle LOADX separately here. EXTLOAD case will fallthrough.
2131 if (Op.getOpcode() == ISD::LOAD) {
2132 LoadSDNode *LD = cast<LoadSDNode>(Op);
2133 unsigned ExtType = LD->getExtensionType();
2136 case ISD::SEXTLOAD: // '17' bits known
2137 Tmp = LD->getMemoryVT().getSizeInBits();
2138 return VTBits-Tmp+1;
2139 case ISD::ZEXTLOAD: // '16' bits known
2140 Tmp = LD->getMemoryVT().getSizeInBits();
2145 // Allow the target to implement this method for its nodes.
2146 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2147 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2148 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2149 Op.getOpcode() == ISD::INTRINSIC_VOID) {
2150 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth);
2151 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits);
2154 // Finally, if we can prove that the top bits of the result are 0's or 1's,
2155 // use this information.
2156 APInt KnownZero, KnownOne;
2157 APInt Mask = APInt::getAllOnesValue(VTBits);
2158 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
2160 if (KnownZero.isNegative()) { // sign bit is 0
2162 } else if (KnownOne.isNegative()) { // sign bit is 1;
2169 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
2170 // the number of identical bits in the top of the input value.
2172 Mask <<= Mask.getBitWidth()-VTBits;
2173 // Return # leading zeros. We use 'min' here in case Val was zero before
2174 // shifting. We don't want to return '64' as for an i32 "0".
2175 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros()));
2179 bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
2180 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2181 if (!GA) return false;
2182 if (GA->getOffset() != 0) return false;
2183 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal());
2184 if (!GV) return false;
2185 MachineModuleInfo *MMI = getMachineModuleInfo();
2186 return MMI && MMI->hasDebugInfo();
2190 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
2191 /// element of the result of the vector shuffle.
2192 SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
2193 MVT VT = N->getValueType(0);
2194 DebugLoc dl = N->getDebugLoc();
2195 const int *PermMask = cast<ShuffleVectorSDNode>(N)->getMask();
2196 if (PermMask[i] < 0)
2197 return getUNDEF(VT.getVectorElementType());
2198 int Index = PermMask[i];
2199 int NumElems = VT.getVectorNumElements();
2200 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
2203 if (V.getOpcode() == ISD::BIT_CONVERT) {
2204 V = V.getOperand(0);
2205 MVT VVT = V.getValueType();
2206 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
2209 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
2210 return (Index == 0) ? V.getOperand(0)
2211 : getUNDEF(VT.getVectorElementType());
2212 if (V.getOpcode() == ISD::BUILD_VECTOR)
2213 return V.getOperand(Index);
2214 if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
2215 return getShuffleScalarElt(V.getNode(), Index);
2220 /// getNode - Gets or creates the specified node.
2222 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
2223 FoldingSetNodeID ID;
2224 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
2226 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2227 return SDValue(E, 0);
2228 SDNode *N = NodeAllocator.Allocate<SDNode>();
2229 new (N) SDNode(Opcode, DL, getVTList(VT));
2230 CSEMap.InsertNode(N, IP);
2232 AllNodes.push_back(N);
2236 return SDValue(N, 0);
2239 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
2240 MVT VT, SDValue Operand) {
2241 // Constant fold unary operations with an integer constant operand.
2242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
2243 const APInt &Val = C->getAPIntValue();
2244 unsigned BitWidth = VT.getSizeInBits();
2247 case ISD::SIGN_EXTEND:
2248 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT);
2249 case ISD::ANY_EXTEND:
2250 case ISD::ZERO_EXTEND:
2252 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT);
2253 case ISD::UINT_TO_FP:
2254 case ISD::SINT_TO_FP: {
2255 const uint64_t zero[] = {0, 0};
2256 // No compile time operations on this type.
2257 if (VT==MVT::ppcf128)
2259 APFloat apf = APFloat(APInt(BitWidth, 2, zero));
2260 (void)apf.convertFromAPInt(Val,
2261 Opcode==ISD::SINT_TO_FP,
2262 APFloat::rmNearestTiesToEven);
2263 return getConstantFP(apf, VT);
2265 case ISD::BIT_CONVERT:
2266 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
2267 return getConstantFP(Val.bitsToFloat(), VT);
2268 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
2269 return getConstantFP(Val.bitsToDouble(), VT);
2272 return getConstant(Val.byteSwap(), VT);
2274 return getConstant(Val.countPopulation(), VT);
2276 return getConstant(Val.countLeadingZeros(), VT);
2278 return getConstant(Val.countTrailingZeros(), VT);
2282 // Constant fold unary operations with a floating point constant operand.
2283 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
2284 APFloat V = C->getValueAPF(); // make copy
2285 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
2289 return getConstantFP(V, VT);
2292 return getConstantFP(V, VT);
2294 case ISD::FP_EXTEND: {
2296 // This can return overflow, underflow, or inexact; we don't care.
2297 // FIXME need to be more flexible about rounding mode.
2298 (void)V.convert(*MVTToAPFloatSemantics(VT),
2299 APFloat::rmNearestTiesToEven, &ignored);
2300 return getConstantFP(V, VT);
2302 case ISD::FP_TO_SINT:
2303 case ISD::FP_TO_UINT: {
2306 assert(integerPartWidth >= 64);
2307 // FIXME need to be more flexible about rounding mode.
2308 APFloat::opStatus s = V.convertToInteger(&x, 64U,
2309 Opcode==ISD::FP_TO_SINT,
2310 APFloat::rmTowardZero, &ignored);
2311 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual
2313 return getConstant(x, VT);
2315 case ISD::BIT_CONVERT:
2316 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
2317 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
2318 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
2319 return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
2325 unsigned OpOpcode = Operand.getNode()->getOpcode();
2327 case ISD::TokenFactor:
2328 case ISD::MERGE_VALUES:
2329 case ISD::CONCAT_VECTORS:
2330 return Operand; // Factor, merge or concat of one node? No need.
2331 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node");
2332 case ISD::FP_EXTEND:
2333 assert(VT.isFloatingPoint() &&
2334 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
2335 if (Operand.getValueType() == VT) return Operand; // noop conversion.
2336 if (Operand.getOpcode() == ISD::UNDEF)
2337 return getUNDEF(VT);
2339 case ISD::SIGN_EXTEND:
2340 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2341 "Invalid SIGN_EXTEND!");
2342 if (Operand.getValueType() == VT) return Operand; // noop extension
2343 assert(Operand.getValueType().bitsLT(VT)
2344 && "Invalid sext node, dst < src!");
2345 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2346 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2348 case ISD::ZERO_EXTEND:
2349 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2350 "Invalid ZERO_EXTEND!");
2351 if (Operand.getValueType() == VT) return Operand; // noop extension
2352 assert(Operand.getValueType().bitsLT(VT)
2353 && "Invalid zext node, dst < src!");
2354 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2355 return getNode(ISD::ZERO_EXTEND, DL, VT,
2356 Operand.getNode()->getOperand(0));
2358 case ISD::ANY_EXTEND:
2359 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2360 "Invalid ANY_EXTEND!");
2361 if (Operand.getValueType() == VT) return Operand; // noop extension
2362 assert(Operand.getValueType().bitsLT(VT)
2363 && "Invalid anyext node, dst < src!");
2364 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
2365 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
2366 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2369 assert(VT.isInteger() && Operand.getValueType().isInteger() &&
2370 "Invalid TRUNCATE!");
2371 if (Operand.getValueType() == VT) return Operand; // noop truncate
2372 assert(Operand.getValueType().bitsGT(VT)
2373 && "Invalid truncate node, src < dst!");
2374 if (OpOpcode == ISD::TRUNCATE)
2375 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2376 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2377 OpOpcode == ISD::ANY_EXTEND) {
2378 // If the source is smaller than the dest, we still need an extend.
2379 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
2380 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
2381 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
2382 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2384 return Operand.getNode()->getOperand(0);
2387 case ISD::BIT_CONVERT:
2388 // Basic sanity checking.
2389 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits()
2390 && "Cannot BIT_CONVERT between types of different sizes!");
2391 if (VT == Operand.getValueType()) return Operand; // noop conversion.
2392 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
2393 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
2394 if (OpOpcode == ISD::UNDEF)
2395 return getUNDEF(VT);
2397 case ISD::SCALAR_TO_VECTOR:
2398 assert(VT.isVector() && !Operand.getValueType().isVector() &&
2399 (VT.getVectorElementType() == Operand.getValueType() ||
2400 (VT.getVectorElementType().isInteger() &&
2401 Operand.getValueType().isInteger() &&
2402 VT.getVectorElementType().bitsLE(Operand.getValueType()))) &&
2403 "Illegal SCALAR_TO_VECTOR node!");
2404 if (OpOpcode == ISD::UNDEF)
2405 return getUNDEF(VT);
2406 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
2407 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2408 isa<ConstantSDNode>(Operand.getOperand(1)) &&
2409 Operand.getConstantOperandVal(1) == 0 &&
2410 Operand.getOperand(0).getValueType() == VT)
2411 return Operand.getOperand(0);
2414 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
2415 if (UnsafeFPMath && OpOpcode == ISD::FSUB)
2416 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2417 Operand.getNode()->getOperand(0));
2418 if (OpOpcode == ISD::FNEG) // --X -> X
2419 return Operand.getNode()->getOperand(0);
2422 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2423 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
2428 SDVTList VTs = getVTList(VT);
2429 if (VT != MVT::Flag) { // Don't CSE flag producing nodes
2430 FoldingSetNodeID ID;
2431 SDValue Ops[1] = { Operand };
2432 AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
2434 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2435 return SDValue(E, 0);
2436 N = NodeAllocator.Allocate<UnarySDNode>();
2437 new (N) UnarySDNode(Opcode, DL, VTs, Operand);
2438 CSEMap.InsertNode(N, IP);
2440 N = NodeAllocator.Allocate<UnarySDNode>();
2441 new (N) UnarySDNode(Opcode, DL, VTs, Operand);
2444 AllNodes.push_back(N);
2448 return SDValue(N, 0);
2451 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode,
2453 ConstantSDNode *Cst1,
2454 ConstantSDNode *Cst2) {
2455 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue();
2458 case ISD::ADD: return getConstant(C1 + C2, VT);
2459 case ISD::SUB: return getConstant(C1 - C2, VT);
2460 case ISD::MUL: return getConstant(C1 * C2, VT);
2462 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT);
2465 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT);
2468 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT);
2471 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT);
2473 case ISD::AND: return getConstant(C1 & C2, VT);
2474 case ISD::OR: return getConstant(C1 | C2, VT);
2475 case ISD::XOR: return getConstant(C1 ^ C2, VT);
2476 case ISD::SHL: return getConstant(C1 << C2, VT);
2477 case ISD::SRL: return getConstant(C1.lshr(C2), VT);
2478 case ISD::SRA: return getConstant(C1.ashr(C2), VT);
2479 case ISD::ROTL: return getConstant(C1.rotl(C2), VT);
2480 case ISD::ROTR: return getConstant(C1.rotr(C2), VT);
2487 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2488 SDValue N1, SDValue N2) {
2489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2490 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2493 case ISD::TokenFactor:
2494 assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
2495 N2.getValueType() == MVT::Other && "Invalid token factor!");
2496 // Fold trivial token factors.
2497 if (N1.getOpcode() == ISD::EntryToken) return N2;
2498 if (N2.getOpcode() == ISD::EntryToken) return N1;
2499 if (N1 == N2) return N1;
2501 case ISD::CONCAT_VECTORS:
2502 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2503 // one big BUILD_VECTOR.
2504 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2505 N2.getOpcode() == ISD::BUILD_VECTOR) {
2506 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2507 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2508 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2512 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2513 N1.getValueType() == VT && "Binary operator types must match!");
2514 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
2515 // worth handling here.
2516 if (N2C && N2C->isNullValue())
2518 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X
2525 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() &&
2526 N1.getValueType() == VT && "Binary operator types must match!");
2527 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so
2528 // it's worth handling here.
2529 if (N2C && N2C->isNullValue())
2539 assert(VT.isInteger() && "This operator does not apply to FP types!");
2547 if (Opcode == ISD::FADD) {
2549 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1))
2550 if (CFP->getValueAPF().isZero())
2553 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2))
2554 if (CFP->getValueAPF().isZero())
2556 } else if (Opcode == ISD::FSUB) {
2558 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2))
2559 if (CFP->getValueAPF().isZero())
2563 assert(N1.getValueType() == N2.getValueType() &&
2564 N1.getValueType() == VT && "Binary operator types must match!");
2566 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2567 assert(N1.getValueType() == VT &&
2568 N1.getValueType().isFloatingPoint() &&
2569 N2.getValueType().isFloatingPoint() &&
2570 "Invalid FCOPYSIGN!");
2577 assert(VT == N1.getValueType() &&
2578 "Shift operators return type must be the same as their first arg");
2579 assert(VT.isInteger() && N2.getValueType().isInteger() &&
2580 "Shifts only work on integers");
2582 // Always fold shifts of i1 values so the code generator doesn't need to
2583 // handle them. Since we know the size of the shift has to be less than the
2584 // size of the value, the shift/rotate count is guaranteed to be zero.
2588 case ISD::FP_ROUND_INREG: {
2589 MVT EVT = cast<VTSDNode>(N2)->getVT();
2590 assert(VT == N1.getValueType() && "Not an inreg round!");
2591 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
2592 "Cannot FP_ROUND_INREG integer types");
2593 assert(EVT.bitsLE(VT) && "Not rounding down!");
2594 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
2598 assert(VT.isFloatingPoint() &&
2599 N1.getValueType().isFloatingPoint() &&
2600 VT.bitsLE(N1.getValueType()) &&
2601 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
2602 if (N1.getValueType() == VT) return N1; // noop conversion.
2604 case ISD::AssertSext:
2605 case ISD::AssertZext: {
2606 MVT EVT = cast<VTSDNode>(N2)->getVT();
2607 assert(VT == N1.getValueType() && "Not an inreg extend!");
2608 assert(VT.isInteger() && EVT.isInteger() &&
2609 "Cannot *_EXTEND_INREG FP types");
2610 assert(EVT.bitsLE(VT) && "Not extending!");
2611 if (VT == EVT) return N1; // noop assertion.
2614 case ISD::SIGN_EXTEND_INREG: {
2615 MVT EVT = cast<VTSDNode>(N2)->getVT();
2616 assert(VT == N1.getValueType() && "Not an inreg extend!");
2617 assert(VT.isInteger() && EVT.isInteger() &&
2618 "Cannot *_EXTEND_INREG FP types");
2619 assert(EVT.bitsLE(VT) && "Not extending!");
2620 if (EVT == VT) return N1; // Not actually extending
2623 APInt Val = N1C->getAPIntValue();
2624 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits();
2625 Val <<= Val.getBitWidth()-FromBits;
2626 Val = Val.ashr(Val.getBitWidth()-FromBits);
2627 return getConstant(Val, VT);
2631 case ISD::EXTRACT_VECTOR_ELT:
2632 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
2633 if (N1.getOpcode() == ISD::UNDEF)
2634 return getUNDEF(VT);
2636 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
2637 // expanding copies of large vectors from registers.
2639 N1.getOpcode() == ISD::CONCAT_VECTORS &&
2640 N1.getNumOperands() > 0) {
2642 N1.getOperand(0).getValueType().getVectorNumElements();
2643 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
2644 N1.getOperand(N2C->getZExtValue() / Factor),
2645 getConstant(N2C->getZExtValue() % Factor,
2646 N2.getValueType()));
2649 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
2650 // expanding large vector constants.
2651 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
2652 SDValue Elt = N1.getOperand(N2C->getZExtValue());
2653 if (Elt.getValueType() != VT) {
2654 // If the vector element type is not legal, the BUILD_VECTOR operands
2655 // are promoted and implicitly truncated. Make that explicit here.
2656 assert(VT.isInteger() && Elt.getValueType().isInteger() &&
2657 VT.bitsLE(Elt.getValueType()) &&
2658 "Bad type for BUILD_VECTOR operand");
2659 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt);
2664 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
2665 // operations are lowered to scalars.
2666 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
2667 // If the indices are the same, return the inserted element.
2668 if (N1.getOperand(2) == N2)
2669 return N1.getOperand(1);
2670 // If the indices are known different, extract the element from
2671 // the original vector.
2672 else if (isa<ConstantSDNode>(N1.getOperand(2)) &&
2673 isa<ConstantSDNode>(N2))
2674 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
2677 case ISD::EXTRACT_ELEMENT:
2678 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
2679 assert(!N1.getValueType().isVector() && !VT.isVector() &&
2680 (N1.getValueType().isInteger() == VT.isInteger()) &&
2681 "Wrong types for EXTRACT_ELEMENT!");
2683 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
2684 // 64-bit integers into 32-bit parts. Instead of building the extract of
2685 // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
2686 if (N1.getOpcode() == ISD::BUILD_PAIR)
2687 return N1.getOperand(N2C->getZExtValue());
2689 // EXTRACT_ELEMENT of a constant int is also very common.
2690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2691 unsigned ElementSize = VT.getSizeInBits();
2692 unsigned Shift = ElementSize * N2C->getZExtValue();
2693 APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
2694 return getConstant(ShiftedVal.trunc(ElementSize), VT);
2697 case ISD::EXTRACT_SUBVECTOR:
2698 if (N1.getValueType() == VT) // Trivial extraction.
2705 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C);
2706 if (SV.getNode()) return SV;
2707 } else { // Cannonicalize constant to RHS if commutative
2708 if (isCommutativeBinOp(Opcode)) {
2709 std::swap(N1C, N2C);
2715 // Constant fold FP operations.
2716 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
2717 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
2719 if (!N2CFP && isCommutativeBinOp(Opcode)) {
2720 // Cannonicalize constant to RHS if commutative
2721 std::swap(N1CFP, N2CFP);
2723 } else if (N2CFP && VT != MVT::ppcf128) {
2724 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
2725 APFloat::opStatus s;
2728 s = V1.add(V2, APFloat::rmNearestTiesToEven);
2729 if (s != APFloat::opInvalidOp)
2730 return getConstantFP(V1, VT);
2733 s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
2734 if (s!=APFloat::opInvalidOp)
2735 return getConstantFP(V1, VT);
2738 s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
2739 if (s!=APFloat::opInvalidOp)
2740 return getConstantFP(V1, VT);
2743 s = V1.divide(V2, APFloat::rmNearestTiesToEven);
2744 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2745 return getConstantFP(V1, VT);
2748 s = V1.mod(V2, APFloat::rmNearestTiesToEven);
2749 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero)
2750 return getConstantFP(V1, VT);
2752 case ISD::FCOPYSIGN:
2754 return getConstantFP(V1, VT);
2760 // Canonicalize an UNDEF to the RHS, even over a constant.
2761 if (N1.getOpcode() == ISD::UNDEF) {
2762 if (isCommutativeBinOp(Opcode)) {
2766 case ISD::FP_ROUND_INREG:
2767 case ISD::SIGN_EXTEND_INREG:
2773 return N1; // fold op(undef, arg2) -> undef
2781 return getConstant(0, VT); // fold op(undef, arg2) -> 0
2782 // For vectors, we can't easily build an all zero vector, just return
2789 // Fold a bunch of operators when the RHS is undef.
2790 if (N2.getOpcode() == ISD::UNDEF) {
2793 if (N1.getOpcode() == ISD::UNDEF)
2794 // Handle undef ^ undef -> 0 special case. This is a common
2796 return getConstant(0, VT);
2811 return N2; // fold op(arg1, undef) -> undef
2817 return getConstant(0, VT); // fold op(arg1, undef) -> 0
2818 // For vectors, we can't easily build an all zero vector, just return
2823 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
2824 // For vectors, we can't easily build an all one vector, just return
2832 // Memoize this node if possible.
2834 SDVTList VTs = getVTList(VT);
2835 if (VT != MVT::Flag) {
2836 SDValue Ops[] = { N1, N2 };
2837 FoldingSetNodeID ID;
2838 AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
2840 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2841 return SDValue(E, 0);
2842 N = NodeAllocator.Allocate<BinarySDNode>();
2843 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
2844 CSEMap.InsertNode(N, IP);
2846 N = NodeAllocator.Allocate<BinarySDNode>();
2847 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
2850 AllNodes.push_back(N);
2854 return SDValue(N, 0);
2857 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2858 SDValue N1, SDValue N2, SDValue N3) {
2859 // Perform various simplifications.
2860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2861 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
2863 case ISD::CONCAT_VECTORS:
2864 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
2865 // one big BUILD_VECTOR.
2866 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2867 N2.getOpcode() == ISD::BUILD_VECTOR &&
2868 N3.getOpcode() == ISD::BUILD_VECTOR) {
2869 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
2870 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2871 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end());
2872 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2876 // Use FoldSetCC to simplify SETCC's.
2877 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL);
2878 if (Simp.getNode()) return Simp;
2883 if (N1C->getZExtValue())
2884 return N2; // select true, X, Y -> X
2886 return N3; // select false, X, Y -> Y
2889 if (N2 == N3) return N2; // select C, X, X -> X
2893 if (N2C->getZExtValue()) // Unconditional branch
2894 return getNode(ISD::BR, DL, MVT::Other, N1, N3);
2896 return N1; // Never-taken branch
2899 case ISD::VECTOR_SHUFFLE:
2900 assert(0 && "should use getVectorShuffle constructor!");
2902 case ISD::BIT_CONVERT:
2903 // Fold bit_convert nodes from a type to themselves.
2904 if (N1.getValueType() == VT)
2909 // Memoize node if it doesn't produce a flag.
2911 SDVTList VTs = getVTList(VT);
2912 if (VT != MVT::Flag) {
2913 SDValue Ops[] = { N1, N2, N3 };
2914 FoldingSetNodeID ID;
2915 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
2917 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
2918 return SDValue(E, 0);
2919 N = NodeAllocator.Allocate<TernarySDNode>();
2920 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
2921 CSEMap.InsertNode(N, IP);
2923 N = NodeAllocator.Allocate<TernarySDNode>();
2924 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
2926 AllNodes.push_back(N);
2930 return SDValue(N, 0);
2933 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2934 SDValue N1, SDValue N2, SDValue N3,
2936 SDValue Ops[] = { N1, N2, N3, N4 };
2937 return getNode(Opcode, DL, VT, Ops, 4);
2940 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
2941 SDValue N1, SDValue N2, SDValue N3,
2942 SDValue N4, SDValue N5) {
2943 SDValue Ops[] = { N1, N2, N3, N4, N5 };
2944 return getNode(Opcode, DL, VT, Ops, 5);
2947 /// getMemsetValue - Vectorized representation of the memset value
2949 static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
2951 unsigned NumBits = VT.isVector() ?
2952 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
2953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2954 APInt Val = APInt(NumBits, C->getZExtValue() & 255);
2956 for (unsigned i = NumBits; i > 8; i >>= 1) {
2957 Val = (Val << Shift) | Val;
2961 return DAG.getConstant(Val, VT);
2962 return DAG.getConstantFP(APFloat(Val), VT);
2965 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2966 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
2968 for (unsigned i = NumBits; i > 8; i >>= 1) {
2969 Value = DAG.getNode(ISD::OR, dl, VT,
2970 DAG.getNode(ISD::SHL, dl, VT, Value,
2971 DAG.getConstant(Shift,
2972 TLI.getShiftAmountTy())),
2980 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2981 /// used when a memcpy is turned into a memset when the source is a constant
2983 static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
2984 const TargetLowering &TLI,
2985 std::string &Str, unsigned Offset) {
2986 // Handle vector with all elements zero.
2989 return DAG.getConstant(0, VT);
2990 unsigned NumElts = VT.getVectorNumElements();
2991 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
2992 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
2993 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
2996 assert(!VT.isVector() && "Can't handle vector type here!");
2997 unsigned NumBits = VT.getSizeInBits();
2998 unsigned MSB = NumBits / 8;
3000 if (TLI.isLittleEndian())
3001 Offset = Offset + MSB - 1;
3002 for (unsigned i = 0; i != MSB; ++i) {
3003 Val = (Val << 8) | (unsigned char)Str[Offset];
3004 Offset += TLI.isLittleEndian() ? -1 : 1;
3006 return DAG.getConstant(Val, VT);
3009 /// getMemBasePlusOffset - Returns base and offset node for the
3011 static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
3012 SelectionDAG &DAG) {
3013 MVT VT = Base.getValueType();
3014 return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
3015 VT, Base, DAG.getConstant(Offset, VT));
3018 /// isMemSrcFromString - Returns true if memcpy source is a string constant.
3020 static bool isMemSrcFromString(SDValue Src, std::string &Str) {
3021 unsigned SrcDelta = 0;
3022 GlobalAddressSDNode *G = NULL;
3023 if (Src.getOpcode() == ISD::GlobalAddress)
3024 G = cast<GlobalAddressSDNode>(Src);
3025 else if (Src.getOpcode() == ISD::ADD &&
3026 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3027 Src.getOperand(1).getOpcode() == ISD::Constant) {
3028 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
3029 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
3034 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3035 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false))
3041 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3042 /// to replace the memset / memcpy is below the threshold. It also returns the
3043 /// types of the sequence of memory ops to perform memset / memcpy.
3045 bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
3046 SDValue Dst, SDValue Src,
3047 unsigned Limit, uint64_t Size, unsigned &Align,
3048 std::string &Str, bool &isSrcStr,
3050 const TargetLowering &TLI) {
3051 isSrcStr = isMemSrcFromString(Src, Str);
3052 bool isSrcConst = isa<ConstantSDNode>(Src);
3053 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
3054 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr);
3055 if (VT != MVT::iAny) {
3056 unsigned NewAlign = (unsigned)
3057 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
3058 // If source is a string constant, this will require an unaligned load.
3059 if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
3060 if (Dst.getOpcode() != ISD::FrameIndex) {
3061 // Can't change destination alignment. It requires a unaligned store.
3065 int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
3066 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3067 if (MFI->isFixedObjectIndex(FI)) {
3068 // Can't change destination alignment. It requires a unaligned store.
3072 // Give the stack frame object a larger alignment if needed.
3073 if (MFI->getObjectAlignment(FI) < NewAlign)
3074 MFI->setObjectAlignment(FI, NewAlign);
3081 if (VT == MVT::iAny) {
3085 switch (Align & 7) {
3086 case 0: VT = MVT::i64; break;
3087 case 4: VT = MVT::i32; break;
3088 case 2: VT = MVT::i16; break;
3089 default: VT = MVT::i8; break;
3094 while (!TLI.isTypeLegal(LVT))
3095 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
3096 assert(LVT.isInteger());
3102 unsigned NumMemOps = 0;
3104 unsigned VTSize = VT.getSizeInBits() / 8;
3105 while (VTSize > Size) {
3106 // For now, only use non-vector load / store's for the left-over pieces.
3107 if (VT.isVector()) {
3109 while (!TLI.isTypeLegal(VT))
3110 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
3111 VTSize = VT.getSizeInBits() / 8;
3113 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
3118 if (++NumMemOps > Limit)
3120 MemOps.push_back(VT);
3127 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
3128 SDValue Chain, SDValue Dst,
3129 SDValue Src, uint64_t Size,
3130 unsigned Align, bool AlwaysInline,
3131 const Value *DstSV, uint64_t DstSVOff,
3132 const Value *SrcSV, uint64_t SrcSVOff){
3133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3135 // Expand memcpy to a series of load and store ops if the size operand falls
3136 // below a certain threshold.
3137 std::vector<MVT> MemOps;
3138 uint64_t Limit = -1ULL;
3140 Limit = TLI.getMaxStoresPerMemcpy();
3141 unsigned DstAlign = Align; // Destination alignment can change.
3144 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3145 Str, CopyFromStr, DAG, TLI))
3149 bool isZeroStr = CopyFromStr && Str.empty();
3150 SmallVector<SDValue, 8> OutChains;
3151 unsigned NumMemOps = MemOps.size();
3152 uint64_t SrcOff = 0, DstOff = 0;
3153 for (unsigned i = 0; i < NumMemOps; i++) {
3155 unsigned VTSize = VT.getSizeInBits() / 8;
3156 SDValue Value, Store;
3158 if (CopyFromStr && (isZeroStr || !VT.isVector())) {
3159 // It's unlikely a store of a vector immediate can be done in a single
3160 // instruction. It would require a load from a constantpool first.
3161 // We also handle store a vector with all zero's.
3162 // FIXME: Handle other cases where store of vector immediate is done in
3163 // a single instruction.
3164 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff);
3165 Store = DAG.getStore(Chain, dl, Value,
3166 getMemBasePlusOffset(Dst, DstOff, DAG),
3167 DstSV, DstSVOff + DstOff, false, DstAlign);
3169 Value = DAG.getLoad(VT, dl, Chain,
3170 getMemBasePlusOffset(Src, SrcOff, DAG),
3171 SrcSV, SrcSVOff + SrcOff, false, Align);
3172 Store = DAG.getStore(Chain, dl, Value,
3173 getMemBasePlusOffset(Dst, DstOff, DAG),
3174 DstSV, DstSVOff + DstOff, false, DstAlign);
3176 OutChains.push_back(Store);
3181 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3182 &OutChains[0], OutChains.size());
3185 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
3186 SDValue Chain, SDValue Dst,
3187 SDValue Src, uint64_t Size,
3188 unsigned Align, bool AlwaysInline,
3189 const Value *DstSV, uint64_t DstSVOff,
3190 const Value *SrcSV, uint64_t SrcSVOff){
3191 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3193 // Expand memmove to a series of load and store ops if the size operand falls
3194 // below a certain threshold.
3195 std::vector<MVT> MemOps;
3196 uint64_t Limit = -1ULL;
3198 Limit = TLI.getMaxStoresPerMemmove();
3199 unsigned DstAlign = Align; // Destination alignment can change.
3202 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign,
3203 Str, CopyFromStr, DAG, TLI))
3206 uint64_t SrcOff = 0, DstOff = 0;
3208 SmallVector<SDValue, 8> LoadValues;
3209 SmallVector<SDValue, 8> LoadChains;
3210 SmallVector<SDValue, 8> OutChains;
3211 unsigned NumMemOps = MemOps.size();
3212 for (unsigned i = 0; i < NumMemOps; i++) {
3214 unsigned VTSize = VT.getSizeInBits() / 8;
3215 SDValue Value, Store;
3217 Value = DAG.getLoad(VT, dl, Chain,
3218 getMemBasePlusOffset(Src, SrcOff, DAG),
3219 SrcSV, SrcSVOff + SrcOff, false, Align);
3220 LoadValues.push_back(Value);
3221 LoadChains.push_back(Value.getValue(1));
3224 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3225 &LoadChains[0], LoadChains.size());
3227 for (unsigned i = 0; i < NumMemOps; i++) {
3229 unsigned VTSize = VT.getSizeInBits() / 8;
3230 SDValue Value, Store;
3232 Store = DAG.getStore(Chain, dl, LoadValues[i],
3233 getMemBasePlusOffset(Dst, DstOff, DAG),
3234 DstSV, DstSVOff + DstOff, false, DstAlign);
3235 OutChains.push_back(Store);
3239 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3240 &OutChains[0], OutChains.size());
3243 static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl,
3244 SDValue Chain, SDValue Dst,
3245 SDValue Src, uint64_t Size,
3247 const Value *DstSV, uint64_t DstSVOff) {
3248 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3250 // Expand memset to a series of load/store ops if the size operand
3251 // falls below a certain threshold.
3252 std::vector<MVT> MemOps;
3255 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
3256 Size, Align, Str, CopyFromStr, DAG, TLI))
3259 SmallVector<SDValue, 8> OutChains;
3260 uint64_t DstOff = 0;
3262 unsigned NumMemOps = MemOps.size();
3263 for (unsigned i = 0; i < NumMemOps; i++) {
3265 unsigned VTSize = VT.getSizeInBits() / 8;
3266 SDValue Value = getMemsetValue(Src, VT, DAG, dl);
3267 SDValue Store = DAG.getStore(Chain, dl, Value,
3268 getMemBasePlusOffset(Dst, DstOff, DAG),
3269 DstSV, DstSVOff + DstOff);
3270 OutChains.push_back(Store);
3274 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3275 &OutChains[0], OutChains.size());
3278 SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
3279 SDValue Src, SDValue Size,
3280 unsigned Align, bool AlwaysInline,
3281 const Value *DstSV, uint64_t DstSVOff,
3282 const Value *SrcSV, uint64_t SrcSVOff) {
3284 // Check to see if we should lower the memcpy to loads and stores first.
3285 // For cases within the target-specified limits, this is the best choice.
3286 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3288 // Memcpy with size zero? Just return the original chain.
3289 if (ConstantSize->isNullValue())
3293 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
3294 ConstantSize->getZExtValue(),
3295 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3296 if (Result.getNode())
3300 // Then check to see if we should lower the memcpy with target-specific
3301 // code. If the target chooses to do this, this is the next best.
3303 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align,
3305 DstSV, DstSVOff, SrcSV, SrcSVOff);
3306 if (Result.getNode())
3309 // If we really need inline code and the target declined to provide it,
3310 // use a (potentially long) sequence of loads and stores.
3312 assert(ConstantSize && "AlwaysInline requires a constant size!");
3313 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
3314 ConstantSize->getZExtValue(), Align, true,
3315 DstSV, DstSVOff, SrcSV, SrcSVOff);
3318 // Emit a library call.
3319 TargetLowering::ArgListTy Args;
3320 TargetLowering::ArgListEntry Entry;
3321 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3322 Entry.Node = Dst; Args.push_back(Entry);
3323 Entry.Node = Src; Args.push_back(Entry);
3324 Entry.Node = Size; Args.push_back(Entry);
3325 // FIXME: pass in DebugLoc
3326 std::pair<SDValue,SDValue> CallResult =
3327 TLI.LowerCallTo(Chain, Type::VoidTy,
3328 false, false, false, false, CallingConv::C, false,
3329 getExternalSymbol("memcpy", TLI.getPointerTy()),
3331 return CallResult.second;
3334 SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
3335 SDValue Src, SDValue Size,
3337 const Value *DstSV, uint64_t DstSVOff,
3338 const Value *SrcSV, uint64_t SrcSVOff) {
3340 // Check to see if we should lower the memmove to loads and stores first.
3341 // For cases within the target-specified limits, this is the best choice.
3342 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3344 // Memmove with size zero? Just return the original chain.
3345 if (ConstantSize->isNullValue())
3349 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src,
3350 ConstantSize->getZExtValue(),
3351 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
3352 if (Result.getNode())
3356 // Then check to see if we should lower the memmove with target-specific
3357 // code. If the target chooses to do this, this is the next best.
3359 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align,
3360 DstSV, DstSVOff, SrcSV, SrcSVOff);
3361 if (Result.getNode())
3364 // Emit a library call.
3365 TargetLowering::ArgListTy Args;
3366 TargetLowering::ArgListEntry Entry;
3367 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3368 Entry.Node = Dst; Args.push_back(Entry);
3369 Entry.Node = Src; Args.push_back(Entry);
3370 Entry.Node = Size; Args.push_back(Entry);
3371 // FIXME: pass in DebugLoc
3372 std::pair<SDValue,SDValue> CallResult =
3373 TLI.LowerCallTo(Chain, Type::VoidTy,
3374 false, false, false, false, CallingConv::C, false,
3375 getExternalSymbol("memmove", TLI.getPointerTy()),
3377 return CallResult.second;
3380 SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
3381 SDValue Src, SDValue Size,
3383 const Value *DstSV, uint64_t DstSVOff) {
3385 // Check to see if we should lower the memset to stores first.
3386 // For cases within the target-specified limits, this is the best choice.
3387 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
3389 // Memset with size zero? Just return the original chain.
3390 if (ConstantSize->isNullValue())
3394 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
3395 Align, DstSV, DstSVOff);
3396 if (Result.getNode())
3400 // Then check to see if we should lower the memset with target-specific
3401 // code. If the target chooses to do this, this is the next best.
3403 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align,
3405 if (Result.getNode())
3408 // Emit a library call.
3409 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
3410 TargetLowering::ArgListTy Args;
3411 TargetLowering::ArgListEntry Entry;
3412 Entry.Node = Dst; Entry.Ty = IntPtrTy;
3413 Args.push_back(Entry);
3414 // Extend or truncate the argument to be an i32 value for the call.
3415 if (Src.getValueType().bitsGT(MVT::i32))
3416 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
3418 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
3419 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
3420 Args.push_back(Entry);
3421 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
3422 Args.push_back(Entry);
3423 // FIXME: pass in DebugLoc
3424 std::pair<SDValue,SDValue> CallResult =
3425 TLI.LowerCallTo(Chain, Type::VoidTy,
3426 false, false, false, false, CallingConv::C, false,
3427 getExternalSymbol("memset", TLI.getPointerTy()),
3429 return CallResult.second;
3432 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
3434 SDValue Ptr, SDValue Cmp,
3435 SDValue Swp, const Value* PtrVal,
3436 unsigned Alignment) {
3437 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
3438 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
3440 MVT VT = Cmp.getValueType();
3442 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3443 Alignment = getMVTAlignment(MemVT);
3445 SDVTList VTs = getVTList(VT, MVT::Other);
3446 FoldingSetNodeID ID;
3447 ID.AddInteger(MemVT.getRawBits());
3448 SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
3449 AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
3451 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3452 return SDValue(E, 0);
3453 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3454 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
3455 Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
3456 CSEMap.InsertNode(N, IP);
3457 AllNodes.push_back(N);
3458 return SDValue(N, 0);
3461 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
3463 SDValue Ptr, SDValue Val,
3464 const Value* PtrVal,
3465 unsigned Alignment) {
3466 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
3467 Opcode == ISD::ATOMIC_LOAD_SUB ||
3468 Opcode == ISD::ATOMIC_LOAD_AND ||
3469 Opcode == ISD::ATOMIC_LOAD_OR ||
3470 Opcode == ISD::ATOMIC_LOAD_XOR ||
3471 Opcode == ISD::ATOMIC_LOAD_NAND ||
3472 Opcode == ISD::ATOMIC_LOAD_MIN ||
3473 Opcode == ISD::ATOMIC_LOAD_MAX ||
3474 Opcode == ISD::ATOMIC_LOAD_UMIN ||
3475 Opcode == ISD::ATOMIC_LOAD_UMAX ||
3476 Opcode == ISD::ATOMIC_SWAP) &&
3477 "Invalid Atomic Op");
3479 MVT VT = Val.getValueType();
3481 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3482 Alignment = getMVTAlignment(MemVT);
3484 SDVTList VTs = getVTList(VT, MVT::Other);
3485 FoldingSetNodeID ID;
3486 ID.AddInteger(MemVT.getRawBits());
3487 SDValue Ops[] = {Chain, Ptr, Val};
3488 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
3490 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3491 return SDValue(E, 0);
3492 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
3493 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
3494 Chain, Ptr, Val, PtrVal, Alignment);
3495 CSEMap.InsertNode(N, IP);
3496 AllNodes.push_back(N);
3497 return SDValue(N, 0);
3500 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
3501 /// Allowed to return something different (and simpler) if Simplify is true.
3502 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
3507 SmallVector<MVT, 4> VTs;
3508 VTs.reserve(NumOps);
3509 for (unsigned i = 0; i < NumOps; ++i)
3510 VTs.push_back(Ops[i].getValueType());
3511 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
3516 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
3517 const MVT *VTs, unsigned NumVTs,
3518 const SDValue *Ops, unsigned NumOps,
3519 MVT MemVT, const Value *srcValue, int SVOff,
3520 unsigned Align, bool Vol,
3521 bool ReadMem, bool WriteMem) {
3522 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
3523 MemVT, srcValue, SVOff, Align, Vol,
3528 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
3529 const SDValue *Ops, unsigned NumOps,
3530 MVT MemVT, const Value *srcValue, int SVOff,
3531 unsigned Align, bool Vol,
3532 bool ReadMem, bool WriteMem) {
3533 // Memoize the node unless it returns a flag.
3534 MemIntrinsicSDNode *N;
3535 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3536 FoldingSetNodeID ID;
3537 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3539 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3540 return SDValue(E, 0);
3542 N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
3543 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
3544 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
3545 CSEMap.InsertNode(N, IP);
3547 N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
3548 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
3549 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
3551 AllNodes.push_back(N);
3552 return SDValue(N, 0);
3556 SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
3557 bool IsTailCall, bool IsInreg, SDVTList VTs,
3558 const SDValue *Operands, unsigned NumOperands) {
3559 // Do not include isTailCall in the folding set profile.
3560 FoldingSetNodeID ID;
3561 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
3562 ID.AddInteger(CallingConv);
3563 ID.AddInteger(IsVarArgs);
3565 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
3566 // Instead of including isTailCall in the folding set, we just
3567 // set the flag of the existing node.
3569 cast<CallSDNode>(E)->setNotTailCall();
3570 return SDValue(E, 0);
3572 SDNode *N = NodeAllocator.Allocate<CallSDNode>();
3573 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg,
3574 VTs, Operands, NumOperands);
3575 CSEMap.InsertNode(N, IP);
3576 AllNodes.push_back(N);
3577 return SDValue(N, 0);
3581 SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
3582 ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
3583 SDValue Ptr, SDValue Offset,
3584 const Value *SV, int SVOffset, MVT EVT,
3585 bool isVolatile, unsigned Alignment) {
3586 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3587 Alignment = getMVTAlignment(VT);
3590 ExtType = ISD::NON_EXTLOAD;
3591 } else if (ExtType == ISD::NON_EXTLOAD) {
3592 assert(VT == EVT && "Non-extending load from different memory type!");
3596 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
3597 "Invalid vector extload!");
3599 assert(EVT.bitsLT(VT) &&
3600 "Should only be an extending load, not truncating!");
3601 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
3602 "Cannot sign/zero extend a FP/Vector load!");
3603 assert(VT.isInteger() == EVT.isInteger() &&
3604 "Cannot convert from FP to Int or Int -> FP!");
3607 bool Indexed = AM != ISD::UNINDEXED;
3608 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
3609 "Unindexed load with an offset!");
3611 SDVTList VTs = Indexed ?
3612 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
3613 SDValue Ops[] = { Chain, Ptr, Offset };
3614 FoldingSetNodeID ID;
3615 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
3616 ID.AddInteger(EVT.getRawBits());
3617 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment));
3619 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3620 return SDValue(E, 0);
3621 SDNode *N = NodeAllocator.Allocate<LoadSDNode>();
3622 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
3623 Alignment, isVolatile);
3624 CSEMap.InsertNode(N, IP);
3625 AllNodes.push_back(N);
3626 return SDValue(N, 0);
3629 SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
3630 SDValue Chain, SDValue Ptr,
3631 const Value *SV, int SVOffset,
3632 bool isVolatile, unsigned Alignment) {
3633 SDValue Undef = getUNDEF(Ptr.getValueType());
3634 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
3635 SV, SVOffset, VT, isVolatile, Alignment);
3638 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
3639 SDValue Chain, SDValue Ptr,
3641 int SVOffset, MVT EVT,
3642 bool isVolatile, unsigned Alignment) {
3643 SDValue Undef = getUNDEF(Ptr.getValueType());
3644 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
3645 SV, SVOffset, EVT, isVolatile, Alignment);
3649 SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
3650 SDValue Offset, ISD::MemIndexedMode AM) {
3651 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
3652 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
3653 "Load is already a indexed load!");
3654 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(),
3655 LD->getChain(), Base, Offset, LD->getSrcValue(),
3656 LD->getSrcValueOffset(), LD->getMemoryVT(),
3657 LD->isVolatile(), LD->getAlignment());
3660 SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
3661 SDValue Ptr, const Value *SV, int SVOffset,
3662 bool isVolatile, unsigned Alignment) {
3663 MVT VT = Val.getValueType();
3665 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3666 Alignment = getMVTAlignment(VT);
3668 SDVTList VTs = getVTList(MVT::Other);
3669 SDValue Undef = getUNDEF(Ptr.getValueType());
3670 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3671 FoldingSetNodeID ID;
3672 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3673 ID.AddInteger(VT.getRawBits());
3674 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED,
3675 isVolatile, Alignment));
3677 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3678 return SDValue(E, 0);
3679 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3680 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
3681 VT, SV, SVOffset, Alignment, isVolatile);
3682 CSEMap.InsertNode(N, IP);
3683 AllNodes.push_back(N);
3684 return SDValue(N, 0);
3687 SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
3688 SDValue Ptr, const Value *SV,
3689 int SVOffset, MVT SVT,
3690 bool isVolatile, unsigned Alignment) {
3691 MVT VT = Val.getValueType();
3694 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
3696 assert(VT.bitsGT(SVT) && "Not a truncation?");
3697 assert(VT.isInteger() == SVT.isInteger() &&
3698 "Can't do FP-INT conversion!");
3700 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3701 Alignment = getMVTAlignment(VT);
3703 SDVTList VTs = getVTList(MVT::Other);
3704 SDValue Undef = getUNDEF(Ptr.getValueType());
3705 SDValue Ops[] = { Chain, Val, Ptr, Undef };
3706 FoldingSetNodeID ID;
3707 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3708 ID.AddInteger(SVT.getRawBits());
3709 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED,
3710 isVolatile, Alignment));
3712 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3713 return SDValue(E, 0);
3714 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3715 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
3716 SVT, SV, SVOffset, Alignment, isVolatile);
3717 CSEMap.InsertNode(N, IP);
3718 AllNodes.push_back(N);
3719 return SDValue(N, 0);
3723 SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
3724 SDValue Offset, ISD::MemIndexedMode AM) {
3725 StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
3726 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
3727 "Store is already a indexed store!");
3728 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
3729 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
3730 FoldingSetNodeID ID;
3731 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
3732 ID.AddInteger(ST->getMemoryVT().getRawBits());
3733 ID.AddInteger(ST->getRawSubclassData());
3735 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3736 return SDValue(E, 0);
3737 SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
3738 new (N) StoreSDNode(Ops, dl, VTs, AM,
3739 ST->isTruncatingStore(), ST->getMemoryVT(),
3740 ST->getSrcValue(), ST->getSrcValueOffset(),
3741 ST->getAlignment(), ST->isVolatile());
3742 CSEMap.InsertNode(N, IP);
3743 AllNodes.push_back(N);
3744 return SDValue(N, 0);
3747 SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
3748 SDValue Chain, SDValue Ptr,
3750 SDValue Ops[] = { Chain, Ptr, SV };
3751 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
3754 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
3755 const SDUse *Ops, unsigned NumOps) {
3757 case 0: return getNode(Opcode, DL, VT);
3758 case 1: return getNode(Opcode, DL, VT, Ops[0]);
3759 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
3760 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
3764 // Copy from an SDUse array into an SDValue array for use with
3765 // the regular getNode logic.
3766 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
3767 return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
3770 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
3771 const SDValue *Ops, unsigned NumOps) {
3773 case 0: return getNode(Opcode, DL, VT);
3774 case 1: return getNode(Opcode, DL, VT, Ops[0]);
3775 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
3776 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
3782 case ISD::SELECT_CC: {
3783 assert(NumOps == 5 && "SELECT_CC takes 5 operands!");
3784 assert(Ops[0].getValueType() == Ops[1].getValueType() &&
3785 "LHS and RHS of condition must have same type!");
3786 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3787 "True and False arms of SelectCC must have same type!");
3788 assert(Ops[2].getValueType() == VT &&
3789 "select_cc node must be of same type as true and false value!");
3793 assert(NumOps == 5 && "BR_CC takes 5 operands!");
3794 assert(Ops[2].getValueType() == Ops[3].getValueType() &&
3795 "LHS/RHS of comparison should match types!");
3802 SDVTList VTs = getVTList(VT);
3804 if (VT != MVT::Flag) {
3805 FoldingSetNodeID ID;
3806 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
3809 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3810 return SDValue(E, 0);
3812 N = NodeAllocator.Allocate<SDNode>();
3813 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
3814 CSEMap.InsertNode(N, IP);
3816 N = NodeAllocator.Allocate<SDNode>();
3817 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
3820 AllNodes.push_back(N);
3824 return SDValue(N, 0);
3827 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
3828 const std::vector<MVT> &ResultTys,
3829 const SDValue *Ops, unsigned NumOps) {
3830 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
3834 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
3835 const MVT *VTs, unsigned NumVTs,
3836 const SDValue *Ops, unsigned NumOps) {
3838 return getNode(Opcode, DL, VTs[0], Ops, NumOps);
3839 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
3842 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3843 const SDValue *Ops, unsigned NumOps) {
3844 if (VTList.NumVTs == 1)
3845 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps);
3848 // FIXME: figure out how to safely handle things like
3849 // int foo(int x) { return 1 << (x & 255); }
3850 // int bar() { return foo(256); }
3852 case ISD::SRA_PARTS:
3853 case ISD::SRL_PARTS:
3854 case ISD::SHL_PARTS:
3855 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3856 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
3857 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
3858 else if (N3.getOpcode() == ISD::AND)
3859 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
3860 // If the and is only masking out bits that cannot effect the shift,
3861 // eliminate the and.
3862 unsigned NumBits = VT.getSizeInBits()*2;
3863 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
3864 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
3870 // Memoize the node unless it returns a flag.
3872 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
3873 FoldingSetNodeID ID;
3874 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
3876 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
3877 return SDValue(E, 0);
3879 N = NodeAllocator.Allocate<UnarySDNode>();
3880 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
3881 } else if (NumOps == 2) {
3882 N = NodeAllocator.Allocate<BinarySDNode>();
3883 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
3884 } else if (NumOps == 3) {
3885 N = NodeAllocator.Allocate<TernarySDNode>();
3886 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
3888 N = NodeAllocator.Allocate<SDNode>();
3889 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
3891 CSEMap.InsertNode(N, IP);
3894 N = NodeAllocator.Allocate<UnarySDNode>();
3895 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
3896 } else if (NumOps == 2) {
3897 N = NodeAllocator.Allocate<BinarySDNode>();
3898 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
3899 } else if (NumOps == 3) {
3900 N = NodeAllocator.Allocate<TernarySDNode>();
3901 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
3903 N = NodeAllocator.Allocate<SDNode>();
3904 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
3907 AllNodes.push_back(N);
3911 return SDValue(N, 0);
3914 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) {
3915 return getNode(Opcode, DL, VTList, 0, 0);
3918 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3920 SDValue Ops[] = { N1 };
3921 return getNode(Opcode, DL, VTList, Ops, 1);
3924 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3925 SDValue N1, SDValue N2) {
3926 SDValue Ops[] = { N1, N2 };
3927 return getNode(Opcode, DL, VTList, Ops, 2);
3930 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3931 SDValue N1, SDValue N2, SDValue N3) {
3932 SDValue Ops[] = { N1, N2, N3 };
3933 return getNode(Opcode, DL, VTList, Ops, 3);
3936 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3937 SDValue N1, SDValue N2, SDValue N3,
3939 SDValue Ops[] = { N1, N2, N3, N4 };
3940 return getNode(Opcode, DL, VTList, Ops, 4);
3943 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
3944 SDValue N1, SDValue N2, SDValue N3,
3945 SDValue N4, SDValue N5) {
3946 SDValue Ops[] = { N1, N2, N3, N4, N5 };
3947 return getNode(Opcode, DL, VTList, Ops, 5);
3950 SDVTList SelectionDAG::getVTList(MVT VT) {
3951 return makeVTList(SDNode::getValueTypeList(VT), 1);
3954 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) {
3955 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3956 E = VTList.rend(); I != E; ++I)
3957 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
3960 MVT *Array = Allocator.Allocate<MVT>(2);
3963 SDVTList Result = makeVTList(Array, 2);
3964 VTList.push_back(Result);
3968 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) {
3969 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3970 E = VTList.rend(); I != E; ++I)
3971 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
3975 MVT *Array = Allocator.Allocate<MVT>(3);
3979 SDVTList Result = makeVTList(Array, 3);
3980 VTList.push_back(Result);
3984 SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
3985 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
3986 E = VTList.rend(); I != E; ++I)
3987 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
3988 I->VTs[2] == VT3 && I->VTs[3] == VT4)
3991 MVT *Array = Allocator.Allocate<MVT>(3);
3996 SDVTList Result = makeVTList(Array, 4);
3997 VTList.push_back(Result);
4001 SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
4003 case 0: assert(0 && "Cannot have nodes without results!");
4004 case 1: return getVTList(VTs[0]);
4005 case 2: return getVTList(VTs[0], VTs[1]);
4006 case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
4010 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
4011 E = VTList.rend(); I != E; ++I) {
4012 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1])
4015 bool NoMatch = false;
4016 for (unsigned i = 2; i != NumVTs; ++i)
4017 if (VTs[i] != I->VTs[i]) {
4025 MVT *Array = Allocator.Allocate<MVT>(NumVTs);
4026 std::copy(VTs, VTs+NumVTs, Array);
4027 SDVTList Result = makeVTList(Array, NumVTs);
4028 VTList.push_back(Result);
4033 /// UpdateNodeOperands - *Mutate* the specified node in-place to have the
4034 /// specified operands. If the resultant node already exists in the DAG,
4035 /// this does not modify the specified node, instead it returns the node that
4036 /// already exists. If the resultant node does not exist in the DAG, the
4037 /// input node is returned. As a degenerate case, if you specify the same
4038 /// input operands as the node already has, the input node is returned.
4039 SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
4040 SDNode *N = InN.getNode();
4041 assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
4043 // Check to see if there is no change.
4044 if (Op == N->getOperand(0)) return InN;
4046 // See if the modified node already exists.
4047 void *InsertPos = 0;
4048 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
4049 return SDValue(Existing, InN.getResNo());
4051 // Nope it doesn't. Remove the node from its current place in the maps.
4053 if (!RemoveNodeFromCSEMaps(N))
4056 // Now we update the operands.
4057 N->OperandList[0].set(Op);
4059 // If this gets put into a CSE map, add it.
4060 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4064 SDValue SelectionDAG::
4065 UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
4066 SDNode *N = InN.getNode();
4067 assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
4069 // Check to see if there is no change.
4070 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
4071 return InN; // No operands changed, just return the input node.
4073 // See if the modified node already exists.
4074 void *InsertPos = 0;
4075 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
4076 return SDValue(Existing, InN.getResNo());
4078 // Nope it doesn't. Remove the node from its current place in the maps.
4080 if (!RemoveNodeFromCSEMaps(N))
4083 // Now we update the operands.
4084 if (N->OperandList[0] != Op1)
4085 N->OperandList[0].set(Op1);
4086 if (N->OperandList[1] != Op2)
4087 N->OperandList[1].set(Op2);
4089 // If this gets put into a CSE map, add it.
4090 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4094 SDValue SelectionDAG::
4095 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) {
4096 SDValue Ops[] = { Op1, Op2, Op3 };
4097 return UpdateNodeOperands(N, Ops, 3);
4100 SDValue SelectionDAG::
4101 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
4102 SDValue Op3, SDValue Op4) {
4103 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
4104 return UpdateNodeOperands(N, Ops, 4);
4107 SDValue SelectionDAG::
4108 UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
4109 SDValue Op3, SDValue Op4, SDValue Op5) {
4110 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
4111 return UpdateNodeOperands(N, Ops, 5);
4114 SDValue SelectionDAG::
4115 UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
4116 SDNode *N = InN.getNode();
4117 assert(N->getNumOperands() == NumOps &&
4118 "Update with wrong number of operands");
4120 // Check to see if there is no change.
4121 bool AnyChange = false;
4122 for (unsigned i = 0; i != NumOps; ++i) {
4123 if (Ops[i] != N->getOperand(i)) {
4129 // No operands changed, just return the input node.
4130 if (!AnyChange) return InN;
4132 // See if the modified node already exists.
4133 void *InsertPos = 0;
4134 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
4135 return SDValue(Existing, InN.getResNo());
4137 // Nope it doesn't. Remove the node from its current place in the maps.
4139 if (!RemoveNodeFromCSEMaps(N))
4142 // Now we update the operands.
4143 for (unsigned i = 0; i != NumOps; ++i)
4144 if (N->OperandList[i] != Ops[i])
4145 N->OperandList[i].set(Ops[i]);
4147 // If this gets put into a CSE map, add it.
4148 if (InsertPos) CSEMap.InsertNode(N, InsertPos);
4152 /// DropOperands - Release the operands and set this node to have
4154 void SDNode::DropOperands() {
4155 // Unlike the code in MorphNodeTo that does this, we don't need to
4156 // watch for dead nodes here.
4157 for (op_iterator I = op_begin(), E = op_end(); I != E; ) {
4163 /// SelectNodeTo - These are wrappers around MorphNodeTo that accept a
4166 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4168 SDVTList VTs = getVTList(VT);
4169 return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
4172 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4173 MVT VT, SDValue Op1) {
4174 SDVTList VTs = getVTList(VT);
4175 SDValue Ops[] = { Op1 };
4176 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4179 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4180 MVT VT, SDValue Op1,
4182 SDVTList VTs = getVTList(VT);
4183 SDValue Ops[] = { Op1, Op2 };
4184 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4187 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4188 MVT VT, SDValue Op1,
4189 SDValue Op2, SDValue Op3) {
4190 SDVTList VTs = getVTList(VT);
4191 SDValue Ops[] = { Op1, Op2, Op3 };
4192 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4195 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4196 MVT VT, const SDValue *Ops,
4198 SDVTList VTs = getVTList(VT);
4199 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4202 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4203 MVT VT1, MVT VT2, const SDValue *Ops,
4205 SDVTList VTs = getVTList(VT1, VT2);
4206 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4209 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4211 SDVTList VTs = getVTList(VT1, VT2);
4212 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
4215 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4216 MVT VT1, MVT VT2, MVT VT3,
4217 const SDValue *Ops, unsigned NumOps) {
4218 SDVTList VTs = getVTList(VT1, VT2, VT3);
4219 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4222 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4223 MVT VT1, MVT VT2, MVT VT3, MVT VT4,
4224 const SDValue *Ops, unsigned NumOps) {
4225 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
4226 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
4229 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4232 SDVTList VTs = getVTList(VT1, VT2);
4233 SDValue Ops[] = { Op1 };
4234 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
4237 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4239 SDValue Op1, SDValue Op2) {
4240 SDVTList VTs = getVTList(VT1, VT2);
4241 SDValue Ops[] = { Op1, Op2 };
4242 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
4245 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4247 SDValue Op1, SDValue Op2,
4249 SDVTList VTs = getVTList(VT1, VT2);
4250 SDValue Ops[] = { Op1, Op2, Op3 };
4251 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4254 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4255 MVT VT1, MVT VT2, MVT VT3,
4256 SDValue Op1, SDValue Op2,
4258 SDVTList VTs = getVTList(VT1, VT2, VT3);
4259 SDValue Ops[] = { Op1, Op2, Op3 };
4260 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
4263 SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
4264 SDVTList VTs, const SDValue *Ops,
4266 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps);
4269 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4271 SDVTList VTs = getVTList(VT);
4272 return MorphNodeTo(N, Opc, VTs, 0, 0);
4275 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4276 MVT VT, SDValue Op1) {
4277 SDVTList VTs = getVTList(VT);
4278 SDValue Ops[] = { Op1 };
4279 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4282 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4283 MVT VT, SDValue Op1,
4285 SDVTList VTs = getVTList(VT);
4286 SDValue Ops[] = { Op1, Op2 };
4287 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4290 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4291 MVT VT, SDValue Op1,
4292 SDValue Op2, SDValue Op3) {
4293 SDVTList VTs = getVTList(VT);
4294 SDValue Ops[] = { Op1, Op2, Op3 };
4295 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4298 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4299 MVT VT, const SDValue *Ops,
4301 SDVTList VTs = getVTList(VT);
4302 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4305 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4306 MVT VT1, MVT VT2, const SDValue *Ops,
4308 SDVTList VTs = getVTList(VT1, VT2);
4309 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4312 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4314 SDVTList VTs = getVTList(VT1, VT2);
4315 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
4318 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4319 MVT VT1, MVT VT2, MVT VT3,
4320 const SDValue *Ops, unsigned NumOps) {
4321 SDVTList VTs = getVTList(VT1, VT2, VT3);
4322 return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
4325 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4328 SDVTList VTs = getVTList(VT1, VT2);
4329 SDValue Ops[] = { Op1 };
4330 return MorphNodeTo(N, Opc, VTs, Ops, 1);
4333 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4335 SDValue Op1, SDValue Op2) {
4336 SDVTList VTs = getVTList(VT1, VT2);
4337 SDValue Ops[] = { Op1, Op2 };
4338 return MorphNodeTo(N, Opc, VTs, Ops, 2);
4341 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4343 SDValue Op1, SDValue Op2,
4345 SDVTList VTs = getVTList(VT1, VT2);
4346 SDValue Ops[] = { Op1, Op2, Op3 };
4347 return MorphNodeTo(N, Opc, VTs, Ops, 3);
4350 /// MorphNodeTo - These *mutate* the specified node to have the specified
4351 /// return type, opcode, and operands.
4353 /// Note that MorphNodeTo returns the resultant node. If there is already a
4354 /// node of the specified opcode and operands, it returns that node instead of
4355 /// the current one. Note that the DebugLoc need not be the same.
4357 /// Using MorphNodeTo is faster than creating a new node and swapping it in
4358 /// with ReplaceAllUsesWith both because it often avoids allocating a new
4359 /// node, and because it doesn't require CSE recalculation for any of
4360 /// the node's users.
4362 SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
4363 SDVTList VTs, const SDValue *Ops,
4365 // If an identical node already exists, use it.
4367 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
4368 FoldingSetNodeID ID;
4369 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
4370 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
4374 if (!RemoveNodeFromCSEMaps(N))
4377 // Start the morphing.
4379 N->ValueList = VTs.VTs;
4380 N->NumValues = VTs.NumVTs;
4382 // Clear the operands list, updating used nodes to remove this from their
4383 // use list. Keep track of any operands that become dead as a result.
4384 SmallPtrSet<SDNode*, 16> DeadNodeSet;
4385 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
4387 SDNode *Used = Use.getNode();
4389 if (Used->use_empty())
4390 DeadNodeSet.insert(Used);
4393 // If NumOps is larger than the # of operands we currently have, reallocate
4394 // the operand list.
4395 if (NumOps > N->NumOperands) {
4396 if (N->OperandsNeedDelete)
4397 delete[] N->OperandList;
4399 if (N->isMachineOpcode()) {
4400 // We're creating a final node that will live unmorphed for the
4401 // remainder of the current SelectionDAG iteration, so we can allocate
4402 // the operands directly out of a pool with no recycling metadata.
4403 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps);
4404 N->OperandsNeedDelete = false;
4406 N->OperandList = new SDUse[NumOps];
4407 N->OperandsNeedDelete = true;
4411 // Assign the new operands.
4412 N->NumOperands = NumOps;
4413 for (unsigned i = 0, e = NumOps; i != e; ++i) {
4414 N->OperandList[i].setUser(N);
4415 N->OperandList[i].setInitial(Ops[i]);
4418 // Delete any nodes that are still dead after adding the uses for the
4420 SmallVector<SDNode *, 16> DeadNodes;
4421 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(),
4422 E = DeadNodeSet.end(); I != E; ++I)
4423 if ((*I)->use_empty())
4424 DeadNodes.push_back(*I);
4425 RemoveDeadNodes(DeadNodes);
4428 CSEMap.InsertNode(N, IP); // Memoize the new node.
4433 /// getTargetNode - These are used for target selectors to create a new node
4434 /// with specified return type(s), target opcode, and operands.
4436 /// Note that getTargetNode returns the resultant node. If there is already a
4437 /// node of the specified opcode and operands, it returns that node instead of
4438 /// the current one.
4439 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
4440 return getNode(~Opcode, dl, VT).getNode();
4443 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4445 return getNode(~Opcode, dl, VT, Op1).getNode();
4448 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4449 SDValue Op1, SDValue Op2) {
4450 return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
4453 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4454 SDValue Op1, SDValue Op2,
4456 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
4459 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
4460 const SDValue *Ops, unsigned NumOps) {
4461 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
4464 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4466 SDVTList VTs = getVTList(VT1, VT2);
4468 return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
4471 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4472 MVT VT2, SDValue Op1) {
4473 SDVTList VTs = getVTList(VT1, VT2);
4474 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
4477 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4478 MVT VT2, SDValue Op1,
4480 SDVTList VTs = getVTList(VT1, VT2);
4481 SDValue Ops[] = { Op1, Op2 };
4482 return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
4485 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4486 MVT VT2, SDValue Op1,
4487 SDValue Op2, SDValue Op3) {
4488 SDVTList VTs = getVTList(VT1, VT2);
4489 SDValue Ops[] = { Op1, Op2, Op3 };
4490 return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
4493 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4495 const SDValue *Ops, unsigned NumOps) {
4496 SDVTList VTs = getVTList(VT1, VT2);
4497 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4500 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4501 MVT VT1, MVT VT2, MVT VT3,
4502 SDValue Op1, SDValue Op2) {
4503 SDVTList VTs = getVTList(VT1, VT2, VT3);
4504 SDValue Ops[] = { Op1, Op2 };
4505 return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
4508 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4509 MVT VT1, MVT VT2, MVT VT3,
4510 SDValue Op1, SDValue Op2,
4512 SDVTList VTs = getVTList(VT1, VT2, VT3);
4513 SDValue Ops[] = { Op1, Op2, Op3 };
4514 return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
4517 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4518 MVT VT1, MVT VT2, MVT VT3,
4519 const SDValue *Ops, unsigned NumOps) {
4520 SDVTList VTs = getVTList(VT1, VT2, VT3);
4521 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4524 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
4525 MVT VT2, MVT VT3, MVT VT4,
4526 const SDValue *Ops, unsigned NumOps) {
4527 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
4528 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
4531 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
4532 const std::vector<MVT> &ResultTys,
4533 const SDValue *Ops, unsigned NumOps) {
4534 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
4537 /// getNodeIfExists - Get the specified node if it's already available, or
4538 /// else return NULL.
4539 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
4540 const SDValue *Ops, unsigned NumOps) {
4541 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
4542 FoldingSetNodeID ID;
4543 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
4545 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
4551 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4552 /// This can cause recursive merging of nodes in the DAG.
4554 /// This version assumes From has a single result value.
4556 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
4557 DAGUpdateListener *UpdateListener) {
4558 SDNode *From = FromN.getNode();
4559 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
4560 "Cannot replace with this method!");
4561 assert(From != To.getNode() && "Cannot replace uses of with self");
4563 // Iterate over all the existing uses of From. New uses will be added
4564 // to the beginning of the use list, which we avoid visiting.
4565 // This specifically avoids visiting uses of From that arise while the
4566 // replacement is happening, because any such uses would be the result
4567 // of CSE: If an existing node looks like From after one of its operands
4568 // is replaced by To, we don't want to replace of all its users with To
4569 // too. See PR3018 for more info.
4570 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4574 // This node is about to morph, remove its old self from the CSE maps.
4575 RemoveNodeFromCSEMaps(User);
4577 // A user can appear in a use list multiple times, and when this
4578 // happens the uses are usually next to each other in the list.
4579 // To help reduce the number of CSE recomputations, process all
4580 // the uses of this user that we can find this way.
4582 SDUse &Use = UI.getUse();
4585 } while (UI != UE && *UI == User);
4587 // Now that we have modified User, add it back to the CSE maps. If it
4588 // already exists there, recursively merge the results together.
4589 AddModifiedNodeToCSEMaps(User, UpdateListener);
4593 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4594 /// This can cause recursive merging of nodes in the DAG.
4596 /// This version assumes that for each value of From, there is a
4597 /// corresponding value in To in the same position with the same type.
4599 void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To,
4600 DAGUpdateListener *UpdateListener) {
4602 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
4603 assert((!From->hasAnyUseOfValue(i) ||
4604 From->getValueType(i) == To->getValueType(i)) &&
4605 "Cannot use this version of ReplaceAllUsesWith!");
4608 // Handle the trivial case.
4612 // Iterate over just the existing users of From. See the comments in
4613 // the ReplaceAllUsesWith above.
4614 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4618 // This node is about to morph, remove its old self from the CSE maps.
4619 RemoveNodeFromCSEMaps(User);
4621 // A user can appear in a use list multiple times, and when this
4622 // happens the uses are usually next to each other in the list.
4623 // To help reduce the number of CSE recomputations, process all
4624 // the uses of this user that we can find this way.
4626 SDUse &Use = UI.getUse();
4629 } while (UI != UE && *UI == User);
4631 // Now that we have modified User, add it back to the CSE maps. If it
4632 // already exists there, recursively merge the results together.
4633 AddModifiedNodeToCSEMaps(User, UpdateListener);
4637 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
4638 /// This can cause recursive merging of nodes in the DAG.
4640 /// This version can replace From with any result values. To must match the
4641 /// number and types of values returned by From.
4642 void SelectionDAG::ReplaceAllUsesWith(SDNode *From,
4644 DAGUpdateListener *UpdateListener) {
4645 if (From->getNumValues() == 1) // Handle the simple case efficiently.
4646 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener);
4648 // Iterate over just the existing users of From. See the comments in
4649 // the ReplaceAllUsesWith above.
4650 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end();
4654 // This node is about to morph, remove its old self from the CSE maps.
4655 RemoveNodeFromCSEMaps(User);
4657 // A user can appear in a use list multiple times, and when this
4658 // happens the uses are usually next to each other in the list.
4659 // To help reduce the number of CSE recomputations, process all
4660 // the uses of this user that we can find this way.
4662 SDUse &Use = UI.getUse();
4663 const SDValue &ToOp = To[Use.getResNo()];
4666 } while (UI != UE && *UI == User);
4668 // Now that we have modified User, add it back to the CSE maps. If it
4669 // already exists there, recursively merge the results together.
4670 AddModifiedNodeToCSEMaps(User, UpdateListener);
4674 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
4675 /// uses of other values produced by From.getNode() alone. The Deleted
4676 /// vector is handled the same way as for ReplaceAllUsesWith.
4677 void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
4678 DAGUpdateListener *UpdateListener){
4679 // Handle the really simple, really trivial case efficiently.
4680 if (From == To) return;
4682 // Handle the simple, trivial, case efficiently.
4683 if (From.getNode()->getNumValues() == 1) {
4684 ReplaceAllUsesWith(From, To, UpdateListener);
4688 // Iterate over just the existing users of From. See the comments in
4689 // the ReplaceAllUsesWith above.
4690 SDNode::use_iterator UI = From.getNode()->use_begin(),
4691 UE = From.getNode()->use_end();
4694 bool UserRemovedFromCSEMaps = false;
4696 // A user can appear in a use list multiple times, and when this
4697 // happens the uses are usually next to each other in the list.
4698 // To help reduce the number of CSE recomputations, process all
4699 // the uses of this user that we can find this way.
4701 SDUse &Use = UI.getUse();
4703 // Skip uses of different values from the same node.
4704 if (Use.getResNo() != From.getResNo()) {
4709 // If this node hasn't been modified yet, it's still in the CSE maps,
4710 // so remove its old self from the CSE maps.
4711 if (!UserRemovedFromCSEMaps) {
4712 RemoveNodeFromCSEMaps(User);
4713 UserRemovedFromCSEMaps = true;
4718 } while (UI != UE && *UI == User);
4720 // We are iterating over all uses of the From node, so if a use
4721 // doesn't use the specific value, no changes are made.
4722 if (!UserRemovedFromCSEMaps)
4725 // Now that we have modified User, add it back to the CSE maps. If it
4726 // already exists there, recursively merge the results together.
4727 AddModifiedNodeToCSEMaps(User, UpdateListener);
4732 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith
4733 /// to record information about a use.
4740 /// operator< - Sort Memos by User.
4741 bool operator<(const UseMemo &L, const UseMemo &R) {
4742 return (intptr_t)L.User < (intptr_t)R.User;
4746 /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
4747 /// uses of other values produced by From.getNode() alone. The same value
4748 /// may appear in both the From and To list. The Deleted vector is
4749 /// handled the same way as for ReplaceAllUsesWith.
4750 void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
4753 DAGUpdateListener *UpdateListener){
4754 // Handle the simple, trivial case efficiently.
4756 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener);
4758 // Read up all the uses and make records of them. This helps
4759 // processing new uses that are introduced during the
4760 // replacement process.
4761 SmallVector<UseMemo, 4> Uses;
4762 for (unsigned i = 0; i != Num; ++i) {
4763 unsigned FromResNo = From[i].getResNo();
4764 SDNode *FromNode = From[i].getNode();
4765 for (SDNode::use_iterator UI = FromNode->use_begin(),
4766 E = FromNode->use_end(); UI != E; ++UI) {
4767 SDUse &Use = UI.getUse();
4768 if (Use.getResNo() == FromResNo) {
4769 UseMemo Memo = { *UI, i, &Use };
4770 Uses.push_back(Memo);
4775 // Sort the uses, so that all the uses from a given User are together.
4776 std::sort(Uses.begin(), Uses.end());
4778 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size();
4779 UseIndex != UseIndexEnd; ) {
4780 // We know that this user uses some value of From. If it is the right
4781 // value, update it.
4782 SDNode *User = Uses[UseIndex].User;
4784 // This node is about to morph, remove its old self from the CSE maps.
4785 RemoveNodeFromCSEMaps(User);
4787 // The Uses array is sorted, so all the uses for a given User
4788 // are next to each other in the list.
4789 // To help reduce the number of CSE recomputations, process all
4790 // the uses of this user that we can find this way.
4792 unsigned i = Uses[UseIndex].Index;
4793 SDUse &Use = *Uses[UseIndex].Use;
4797 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User);
4799 // Now that we have modified User, add it back to the CSE maps. If it
4800 // already exists there, recursively merge the results together.
4801 AddModifiedNodeToCSEMaps(User, UpdateListener);
4805 /// AssignTopologicalOrder - Assign a unique node id for each node in the DAG
4806 /// based on their topological order. It returns the maximum id and a vector
4807 /// of the SDNodes* in assigned order by reference.
4808 unsigned SelectionDAG::AssignTopologicalOrder() {
4810 unsigned DAGSize = 0;
4812 // SortedPos tracks the progress of the algorithm. Nodes before it are
4813 // sorted, nodes after it are unsorted. When the algorithm completes
4814 // it is at the end of the list.
4815 allnodes_iterator SortedPos = allnodes_begin();
4817 // Visit all the nodes. Move nodes with no operands to the front of
4818 // the list immediately. Annotate nodes that do have operands with their
4819 // operand count. Before we do this, the Node Id fields of the nodes
4820 // may contain arbitrary values. After, the Node Id fields for nodes
4821 // before SortedPos will contain the topological sort index, and the
4822 // Node Id fields for nodes At SortedPos and after will contain the
4823 // count of outstanding operands.
4824 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) {
4826 unsigned Degree = N->getNumOperands();
4828 // A node with no uses, add it to the result array immediately.
4829 N->setNodeId(DAGSize++);
4830 allnodes_iterator Q = N;
4832 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
4835 // Temporarily use the Node Id as scratch space for the degree count.
4836 N->setNodeId(Degree);
4840 // Visit all the nodes. As we iterate, moves nodes into sorted order,
4841 // such that by the time the end is reached all nodes will be sorted.
4842 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) {
4844 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4847 unsigned Degree = P->getNodeId();
4850 // All of P's operands are sorted, so P may sorted now.
4851 P->setNodeId(DAGSize++);
4853 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P));
4856 // Update P's outstanding operand count.
4857 P->setNodeId(Degree);
4862 assert(SortedPos == AllNodes.end() &&
4863 "Topological sort incomplete!");
4864 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
4865 "First node in topological sort is not the entry token!");
4866 assert(AllNodes.front().getNodeId() == 0 &&
4867 "First node in topological sort has non-zero id!");
4868 assert(AllNodes.front().getNumOperands() == 0 &&
4869 "First node in topological sort has operands!");
4870 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 &&
4871 "Last node in topologic sort has unexpected id!");
4872 assert(AllNodes.back().use_empty() &&
4873 "Last node in topologic sort has users!");
4874 assert(DAGSize == allnodes_size() && "Node count mismatch!");
4880 //===----------------------------------------------------------------------===//
4882 //===----------------------------------------------------------------------===//
4884 HandleSDNode::~HandleSDNode() {
4888 GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA,
4890 : SDNode(isa<GlobalVariable>(GA) &&
4891 cast<GlobalVariable>(GA)->isThreadLocal() ?
4893 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) :
4895 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress),
4896 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) {
4897 TheGlobal = const_cast<GlobalValue*>(GA);
4900 MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
4901 const Value *srcValue, int SVO,
4902 unsigned alignment, bool vol)
4903 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
4904 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
4905 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4906 assert(getAlignment() == alignment && "Alignment representation error!");
4907 assert(isVolatile() == vol && "Volatile representation error!");
4910 MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
4912 unsigned NumOps, MVT memvt, const Value *srcValue,
4913 int SVO, unsigned alignment, bool vol)
4914 : SDNode(Opc, dl, VTs, Ops, NumOps),
4915 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
4916 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
4917 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
4918 assert(getAlignment() == alignment && "Alignment representation error!");
4919 assert(isVolatile() == vol && "Volatile representation error!");
4922 /// getMemOperand - Return a MachineMemOperand object describing the memory
4923 /// reference performed by this memory reference.
4924 MachineMemOperand MemSDNode::getMemOperand() const {
4926 if (isa<LoadSDNode>(this))
4927 Flags = MachineMemOperand::MOLoad;
4928 else if (isa<StoreSDNode>(this))
4929 Flags = MachineMemOperand::MOStore;
4930 else if (isa<AtomicSDNode>(this)) {
4931 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
4934 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this);
4935 assert(MemIntrinNode && "Unknown MemSDNode opcode!");
4936 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad;
4937 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore;
4940 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3;
4941 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile;
4943 // Check if the memory reference references a frame index
4944 const FrameIndexSDNode *FI =
4945 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
4946 if (!getSrcValue() && FI)
4947 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
4948 Flags, 0, Size, getAlignment());
4950 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(),
4951 Size, getAlignment());
4954 /// Profile - Gather unique data for the node.
4956 void SDNode::Profile(FoldingSetNodeID &ID) const {
4957 AddNodeIDNode(ID, this);
4960 /// getValueTypeList - Return a pointer to the specified value type.
4962 const MVT *SDNode::getValueTypeList(MVT VT) {
4963 if (VT.isExtended()) {
4964 static std::set<MVT, MVT::compareRawBits> EVTs;
4965 return &(*EVTs.insert(VT).first);
4967 static MVT VTs[MVT::LAST_VALUETYPE];
4968 VTs[VT.getSimpleVT()] = VT;
4969 return &VTs[VT.getSimpleVT()];
4973 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
4974 /// indicated value. This method ignores uses of other values defined by this
4976 bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const {
4977 assert(Value < getNumValues() && "Bad value!");
4979 // TODO: Only iterate over uses of a given value of the node
4980 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
4981 if (UI.getUse().getResNo() == Value) {
4988 // Found exactly the right number of uses?
4993 /// hasAnyUseOfValue - Return true if there are any use of the indicated
4994 /// value. This method ignores uses of other values defined by this operation.
4995 bool SDNode::hasAnyUseOfValue(unsigned Value) const {
4996 assert(Value < getNumValues() && "Bad value!");
4998 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
4999 if (UI.getUse().getResNo() == Value)
5006 /// isOnlyUserOf - Return true if this node is the only use of N.
5008 bool SDNode::isOnlyUserOf(SDNode *N) const {
5010 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
5021 /// isOperand - Return true if this node is an operand of N.
5023 bool SDValue::isOperandOf(SDNode *N) const {
5024 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5025 if (*this == N->getOperand(i))
5030 bool SDNode::isOperandOf(SDNode *N) const {
5031 for (unsigned i = 0, e = N->NumOperands; i != e; ++i)
5032 if (this == N->OperandList[i].getNode())
5037 /// reachesChainWithoutSideEffects - Return true if this operand (which must
5038 /// be a chain) reaches the specified operand without crossing any
5039 /// side-effecting instructions. In practice, this looks through token
5040 /// factors and non-volatile loads. In order to remain efficient, this only
5041 /// looks a couple of nodes in, it does not do an exhaustive search.
5042 bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
5043 unsigned Depth) const {
5044 if (*this == Dest) return true;
5046 // Don't search too deeply, we just want to be able to see through
5047 // TokenFactor's etc.
5048 if (Depth == 0) return false;
5050 // If this is a token factor, all inputs to the TF happen in parallel. If any
5051 // of the operands of the TF reach dest, then we can do the xform.
5052 if (getOpcode() == ISD::TokenFactor) {
5053 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
5054 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1))
5059 // Loads don't have side effects, look through them.
5060 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
5061 if (!Ld->isVolatile())
5062 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
5068 static void findPredecessor(SDNode *N, const SDNode *P, bool &found,
5069 SmallPtrSet<SDNode *, 32> &Visited) {
5070 if (found || !Visited.insert(N))
5073 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) {
5074 SDNode *Op = N->getOperand(i).getNode();
5079 findPredecessor(Op, P, found, Visited);
5083 /// isPredecessorOf - Return true if this node is a predecessor of N. This node
5084 /// is either an operand of N or it can be reached by recursively traversing
5085 /// up the operands.
5086 /// NOTE: this is an expensive method. Use it carefully.
5087 bool SDNode::isPredecessorOf(SDNode *N) const {
5088 SmallPtrSet<SDNode *, 32> Visited;
5090 findPredecessor(N, this, found, Visited);
5094 uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
5095 assert(Num < NumOperands && "Invalid child # of SDNode!");
5096 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue();
5099 std::string SDNode::getOperationName(const SelectionDAG *G) const {
5100 switch (getOpcode()) {
5102 if (getOpcode() < ISD::BUILTIN_OP_END)
5103 return "<<Unknown DAG Node>>";
5104 if (isMachineOpcode()) {
5106 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
5107 if (getMachineOpcode() < TII->getNumOpcodes())
5108 return TII->get(getMachineOpcode()).getName();
5109 return "<<Unknown Machine Node>>";
5112 const TargetLowering &TLI = G->getTargetLoweringInfo();
5113 const char *Name = TLI.getTargetNodeName(getOpcode());
5114 if (Name) return Name;
5115 return "<<Unknown Target Node>>";
5117 return "<<Unknown Node>>";
5120 case ISD::DELETED_NODE:
5121 return "<<Deleted Node!>>";
5123 case ISD::PREFETCH: return "Prefetch";
5124 case ISD::MEMBARRIER: return "MemBarrier";
5125 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
5126 case ISD::ATOMIC_SWAP: return "AtomicSwap";
5127 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
5128 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
5129 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
5130 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
5131 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
5132 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
5133 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
5134 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
5135 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
5136 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
5137 case ISD::PCMARKER: return "PCMarker";
5138 case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
5139 case ISD::SRCVALUE: return "SrcValue";
5140 case ISD::MEMOPERAND: return "MemOperand";
5141 case ISD::EntryToken: return "EntryToken";
5142 case ISD::TokenFactor: return "TokenFactor";
5143 case ISD::AssertSext: return "AssertSext";
5144 case ISD::AssertZext: return "AssertZext";
5146 case ISD::BasicBlock: return "BasicBlock";
5147 case ISD::ARG_FLAGS: return "ArgFlags";
5148 case ISD::VALUETYPE: return "ValueType";
5149 case ISD::Register: return "Register";
5151 case ISD::Constant: return "Constant";
5152 case ISD::ConstantFP: return "ConstantFP";
5153 case ISD::GlobalAddress: return "GlobalAddress";
5154 case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
5155 case ISD::FrameIndex: return "FrameIndex";
5156 case ISD::JumpTable: return "JumpTable";
5157 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
5158 case ISD::RETURNADDR: return "RETURNADDR";
5159 case ISD::FRAMEADDR: return "FRAMEADDR";
5160 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
5161 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
5162 case ISD::EHSELECTION: return "EHSELECTION";
5163 case ISD::EH_RETURN: return "EH_RETURN";
5164 case ISD::ConstantPool: return "ConstantPool";
5165 case ISD::ExternalSymbol: return "ExternalSymbol";
5166 case ISD::INTRINSIC_WO_CHAIN: {
5167 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue();
5168 return Intrinsic::getName((Intrinsic::ID)IID);
5170 case ISD::INTRINSIC_VOID:
5171 case ISD::INTRINSIC_W_CHAIN: {
5172 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue();
5173 return Intrinsic::getName((Intrinsic::ID)IID);
5176 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
5177 case ISD::TargetConstant: return "TargetConstant";
5178 case ISD::TargetConstantFP:return "TargetConstantFP";
5179 case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
5180 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
5181 case ISD::TargetFrameIndex: return "TargetFrameIndex";
5182 case ISD::TargetJumpTable: return "TargetJumpTable";
5183 case ISD::TargetConstantPool: return "TargetConstantPool";
5184 case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
5186 case ISD::CopyToReg: return "CopyToReg";
5187 case ISD::CopyFromReg: return "CopyFromReg";
5188 case ISD::UNDEF: return "undef";
5189 case ISD::MERGE_VALUES: return "merge_values";
5190 case ISD::INLINEASM: return "inlineasm";
5191 case ISD::DBG_LABEL: return "dbg_label";
5192 case ISD::EH_LABEL: return "eh_label";
5193 case ISD::DECLARE: return "declare";
5194 case ISD::HANDLENODE: return "handlenode";
5195 case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
5196 case ISD::CALL: return "call";
5199 case ISD::FABS: return "fabs";
5200 case ISD::FNEG: return "fneg";
5201 case ISD::FSQRT: return "fsqrt";
5202 case ISD::FSIN: return "fsin";
5203 case ISD::FCOS: return "fcos";
5204 case ISD::FPOWI: return "fpowi";
5205 case ISD::FPOW: return "fpow";
5206 case ISD::FTRUNC: return "ftrunc";
5207 case ISD::FFLOOR: return "ffloor";
5208 case ISD::FCEIL: return "fceil";
5209 case ISD::FRINT: return "frint";
5210 case ISD::FNEARBYINT: return "fnearbyint";
5213 case ISD::ADD: return "add";
5214 case ISD::SUB: return "sub";
5215 case ISD::MUL: return "mul";
5216 case ISD::MULHU: return "mulhu";
5217 case ISD::MULHS: return "mulhs";
5218 case ISD::SDIV: return "sdiv";
5219 case ISD::UDIV: return "udiv";
5220 case ISD::SREM: return "srem";
5221 case ISD::UREM: return "urem";
5222 case ISD::SMUL_LOHI: return "smul_lohi";
5223 case ISD::UMUL_LOHI: return "umul_lohi";
5224 case ISD::SDIVREM: return "sdivrem";
5225 case ISD::UDIVREM: return "udivrem";
5226 case ISD::AND: return "and";
5227 case ISD::OR: return "or";
5228 case ISD::XOR: return "xor";
5229 case ISD::SHL: return "shl";
5230 case ISD::SRA: return "sra";
5231 case ISD::SRL: return "srl";
5232 case ISD::ROTL: return "rotl";
5233 case ISD::ROTR: return "rotr";
5234 case ISD::FADD: return "fadd";
5235 case ISD::FSUB: return "fsub";
5236 case ISD::FMUL: return "fmul";
5237 case ISD::FDIV: return "fdiv";
5238 case ISD::FREM: return "frem";
5239 case ISD::FCOPYSIGN: return "fcopysign";
5240 case ISD::FGETSIGN: return "fgetsign";
5242 case ISD::SETCC: return "setcc";
5243 case ISD::VSETCC: return "vsetcc";
5244 case ISD::SELECT: return "select";
5245 case ISD::SELECT_CC: return "select_cc";
5246 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
5247 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
5248 case ISD::CONCAT_VECTORS: return "concat_vectors";
5249 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
5250 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
5251 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
5252 case ISD::CARRY_FALSE: return "carry_false";
5253 case ISD::ADDC: return "addc";
5254 case ISD::ADDE: return "adde";
5255 case ISD::SADDO: return "saddo";
5256 case ISD::UADDO: return "uaddo";
5257 case ISD::SSUBO: return "ssubo";
5258 case ISD::USUBO: return "usubo";
5259 case ISD::SMULO: return "smulo";
5260 case ISD::UMULO: return "umulo";
5261 case ISD::SUBC: return "subc";
5262 case ISD::SUBE: return "sube";
5263 case ISD::SHL_PARTS: return "shl_parts";
5264 case ISD::SRA_PARTS: return "sra_parts";
5265 case ISD::SRL_PARTS: return "srl_parts";
5267 // Conversion operators.
5268 case ISD::SIGN_EXTEND: return "sign_extend";
5269 case ISD::ZERO_EXTEND: return "zero_extend";
5270 case ISD::ANY_EXTEND: return "any_extend";
5271 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
5272 case ISD::TRUNCATE: return "truncate";
5273 case ISD::FP_ROUND: return "fp_round";
5274 case ISD::FLT_ROUNDS_: return "flt_rounds";
5275 case ISD::FP_ROUND_INREG: return "fp_round_inreg";
5276 case ISD::FP_EXTEND: return "fp_extend";
5278 case ISD::SINT_TO_FP: return "sint_to_fp";
5279 case ISD::UINT_TO_FP: return "uint_to_fp";
5280 case ISD::FP_TO_SINT: return "fp_to_sint";
5281 case ISD::FP_TO_UINT: return "fp_to_uint";
5282 case ISD::BIT_CONVERT: return "bit_convert";
5284 case ISD::CONVERT_RNDSAT: {
5285 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) {
5286 default: assert(0 && "Unknown cvt code!");
5287 case ISD::CVT_FF: return "cvt_ff";
5288 case ISD::CVT_FS: return "cvt_fs";
5289 case ISD::CVT_FU: return "cvt_fu";
5290 case ISD::CVT_SF: return "cvt_sf";
5291 case ISD::CVT_UF: return "cvt_uf";
5292 case ISD::CVT_SS: return "cvt_ss";
5293 case ISD::CVT_SU: return "cvt_su";
5294 case ISD::CVT_US: return "cvt_us";
5295 case ISD::CVT_UU: return "cvt_uu";
5299 // Control flow instructions
5300 case ISD::BR: return "br";
5301 case ISD::BRIND: return "brind";
5302 case ISD::BR_JT: return "br_jt";
5303 case ISD::BRCOND: return "brcond";
5304 case ISD::BR_CC: return "br_cc";
5305 case ISD::RET: return "ret";
5306 case ISD::CALLSEQ_START: return "callseq_start";
5307 case ISD::CALLSEQ_END: return "callseq_end";
5310 case ISD::LOAD: return "load";
5311 case ISD::STORE: return "store";
5312 case ISD::VAARG: return "vaarg";
5313 case ISD::VACOPY: return "vacopy";
5314 case ISD::VAEND: return "vaend";
5315 case ISD::VASTART: return "vastart";
5316 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
5317 case ISD::EXTRACT_ELEMENT: return "extract_element";
5318 case ISD::BUILD_PAIR: return "build_pair";
5319 case ISD::STACKSAVE: return "stacksave";
5320 case ISD::STACKRESTORE: return "stackrestore";
5321 case ISD::TRAP: return "trap";
5324 case ISD::BSWAP: return "bswap";
5325 case ISD::CTPOP: return "ctpop";
5326 case ISD::CTTZ: return "cttz";
5327 case ISD::CTLZ: return "ctlz";
5330 case ISD::DBG_STOPPOINT: return "dbg_stoppoint";
5331 case ISD::DEBUG_LOC: return "debug_loc";
5334 case ISD::TRAMPOLINE: return "trampoline";
5337 switch (cast<CondCodeSDNode>(this)->get()) {
5338 default: assert(0 && "Unknown setcc condition!");
5339 case ISD::SETOEQ: return "setoeq";
5340 case ISD::SETOGT: return "setogt";
5341 case ISD::SETOGE: return "setoge";
5342 case ISD::SETOLT: return "setolt";
5343 case ISD::SETOLE: return "setole";
5344 case ISD::SETONE: return "setone";
5346 case ISD::SETO: return "seto";
5347 case ISD::SETUO: return "setuo";
5348 case ISD::SETUEQ: return "setue";
5349 case ISD::SETUGT: return "setugt";
5350 case ISD::SETUGE: return "setuge";
5351 case ISD::SETULT: return "setult";
5352 case ISD::SETULE: return "setule";
5353 case ISD::SETUNE: return "setune";
5355 case ISD::SETEQ: return "seteq";
5356 case ISD::SETGT: return "setgt";
5357 case ISD::SETGE: return "setge";
5358 case ISD::SETLT: return "setlt";
5359 case ISD::SETLE: return "setle";
5360 case ISD::SETNE: return "setne";
5365 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
5374 return "<post-inc>";
5376 return "<post-dec>";
5380 std::string ISD::ArgFlagsTy::getArgFlagsString() {
5381 std::string S = "< ";
5395 if (getByValAlign())
5396 S += "byval-align:" + utostr(getByValAlign()) + " ";
5398 S += "orig-align:" + utostr(getOrigAlign()) + " ";
5400 S += "byval-size:" + utostr(getByValSize()) + " ";
5404 void SDNode::dump() const { dump(0); }
5405 void SDNode::dump(const SelectionDAG *G) const {
5409 void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
5410 OS << (void*)this << ": ";
5412 for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
5414 if (getValueType(i) == MVT::Other)
5417 OS << getValueType(i).getMVTString();
5419 OS << " = " << getOperationName(G);
5422 void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
5423 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
5424 const int *Mask = cast<ShuffleVectorSDNode>(this)->getMask();
5426 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
5436 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
5437 OS << '<' << CSDN->getAPIntValue() << '>';
5438 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
5439 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle)
5440 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
5441 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble)
5442 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
5445 CSDN->getValueAPF().bitcastToAPInt().dump();
5448 } else if (const GlobalAddressSDNode *GADN =
5449 dyn_cast<GlobalAddressSDNode>(this)) {
5450 int64_t offset = GADN->getOffset();
5452 WriteAsOperand(OS, GADN->getGlobal());
5455 OS << " + " << offset;
5457 OS << " " << offset;
5458 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
5459 OS << "<" << FIDN->getIndex() << ">";
5460 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
5461 OS << "<" << JTDN->getIndex() << ">";
5462 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
5463 int offset = CP->getOffset();
5464 if (CP->isMachineConstantPoolEntry())
5465 OS << "<" << *CP->getMachineCPVal() << ">";
5467 OS << "<" << *CP->getConstVal() << ">";
5469 OS << " + " << offset;
5471 OS << " " << offset;
5472 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
5474 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
5476 OS << LBB->getName() << " ";
5477 OS << (const void*)BBDN->getBasicBlock() << ">";
5478 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
5479 if (G && R->getReg() &&
5480 TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
5481 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg());
5483 OS << " #" << R->getReg();
5485 } else if (const ExternalSymbolSDNode *ES =
5486 dyn_cast<ExternalSymbolSDNode>(this)) {
5487 OS << "'" << ES->getSymbol() << "'";
5488 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
5490 OS << "<" << M->getValue() << ">";
5493 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) {
5494 if (M->MO.getValue())
5495 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
5497 OS << "<null:" << M->MO.getOffset() << ">";
5498 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) {
5499 OS << N->getArgFlags().getArgFlagsString();
5500 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
5501 OS << ":" << N->getVT().getMVTString();
5503 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
5504 const Value *SrcValue = LD->getSrcValue();
5505 int SrcOffset = LD->getSrcValueOffset();
5511 OS << ":" << SrcOffset << ">";
5514 switch (LD->getExtensionType()) {
5515 default: doExt = false; break;
5516 case ISD::EXTLOAD: OS << " <anyext "; break;
5517 case ISD::SEXTLOAD: OS << " <sext "; break;
5518 case ISD::ZEXTLOAD: OS << " <zext "; break;
5521 OS << LD->getMemoryVT().getMVTString() << ">";
5523 const char *AM = getIndexedModeName(LD->getAddressingMode());
5526 if (LD->isVolatile())
5527 OS << " <volatile>";
5528 OS << " alignment=" << LD->getAlignment();
5529 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
5530 const Value *SrcValue = ST->getSrcValue();
5531 int SrcOffset = ST->getSrcValueOffset();
5537 OS << ":" << SrcOffset << ">";
5539 if (ST->isTruncatingStore())
5540 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">";
5542 const char *AM = getIndexedModeName(ST->getAddressingMode());
5545 if (ST->isVolatile())
5546 OS << " <volatile>";
5547 OS << " alignment=" << ST->getAlignment();
5548 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) {
5549 const Value *SrcValue = AT->getSrcValue();
5550 int SrcOffset = AT->getSrcValueOffset();
5556 OS << ":" << SrcOffset << ">";
5557 if (AT->isVolatile())
5558 OS << " <volatile>";
5559 OS << " alignment=" << AT->getAlignment();
5563 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
5566 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
5568 OS << (void*)getOperand(i).getNode();
5569 if (unsigned RN = getOperand(i).getResNo())
5572 print_details(OS, G);
5575 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
5576 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5577 if (N->getOperand(i).getNode()->hasOneUse())
5578 DumpNodes(N->getOperand(i).getNode(), indent+2, G);
5580 cerr << "\n" << std::string(indent+2, ' ')
5581 << (void*)N->getOperand(i).getNode() << ": <multiple use>";
5584 cerr << "\n" << std::string(indent, ' ');
5588 void SelectionDAG::dump() const {
5589 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:";
5591 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
5593 const SDNode *N = I;
5594 if (!N->hasOneUse() && N != getRoot().getNode())
5595 DumpNodes(N, 2, this);
5598 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
5603 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
5605 print_details(OS, G);
5608 typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet;
5609 static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
5610 const SelectionDAG *G, VisitedSDNodeSet &once) {
5611 if (!once.insert(N)) // If we've been here before, return now.
5613 // Dump the current SDNode, but don't end the line yet.
5614 OS << std::string(indent, ' ');
5616 // Having printed this SDNode, walk the children:
5617 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5618 const SDNode *child = N->getOperand(i).getNode();
5621 if (child->getNumOperands() == 0) {
5622 // This child has no grandchildren; print it inline right here.
5623 child->printr(OS, G);
5625 } else { // Just the address. FIXME: also print the child's opcode
5627 if (unsigned RN = N->getOperand(i).getResNo())
5632 // Dump children that have grandchildren on their own line(s).
5633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5634 const SDNode *child = N->getOperand(i).getNode();
5635 DumpNodesr(OS, child, indent+2, G, once);
5639 void SDNode::dumpr() const {
5640 VisitedSDNodeSet once;
5641 DumpNodesr(errs(), this, 0, 0, once);
5644 const Type *ConstantPoolSDNode::getType() const {
5645 if (isMachineConstantPoolEntry())
5646 return Val.MachineCPVal->getType();
5647 return Val.ConstVal->getType();
5650 bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue,
5652 unsigned &SplatBitSize,
5654 unsigned MinSplatBits) {
5655 MVT VT = getValueType(0);
5656 assert(VT.isVector() && "Expected a vector type");
5657 unsigned sz = VT.getSizeInBits();
5658 if (MinSplatBits > sz)
5661 SplatValue = APInt(sz, 0);
5662 SplatUndef = APInt(sz, 0);
5664 // Get the bits. Bits with undefined values (when the corresponding element
5665 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
5666 // in SplatValue. If any of the values are not constant, give up and return
5668 unsigned int nOps = getNumOperands();
5669 assert(nOps > 0 && "isConstantSplat has 0-size build vector");
5670 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits();
5671 for (unsigned i = 0; i < nOps; ++i) {
5672 SDValue OpVal = getOperand(i);
5673 unsigned BitPos = i * EltBitSize;
5675 if (OpVal.getOpcode() == ISD::UNDEF)
5676 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize);
5677 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal))
5678 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize).
5679 zextOrTrunc(sz) << BitPos);
5680 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal))
5681 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos;
5686 // The build_vector is all constants or undefs. Find the smallest element
5687 // size that splats the vector.
5689 HasAnyUndefs = (SplatUndef != 0);
5692 unsigned HalfSize = sz / 2;
5693 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize);
5694 APInt LowValue = APInt(SplatValue).trunc(HalfSize);
5695 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize);
5696 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize);
5698 // If the two halves do not match (ignoring undef bits), stop here.
5699 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
5700 MinSplatBits > HalfSize)
5703 SplatValue = HighValue | LowValue;
5704 SplatUndef = HighUndef & LowUndef;
5713 bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
5715 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5716 if (Idx < 0) Idx = Mask[i];
5717 if (Mask[i] >= 0 && Mask[i] != Idx)