1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 /// LimitFloatPrecision - Generate low-precision inline sequences for
58 /// some float libcalls (6, 8 or 12 bits).
59 static unsigned LimitFloatPrecision;
61 static cl::opt<unsigned, true>
62 LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
68 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
69 /// of insertvalue or extractvalue indices that identify a member, return
70 /// the linearized index of the start of the member.
72 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
84 EE = STy->element_end();
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 // We haven't found the type we're looking for, so keep searching.
106 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107 /// MVTs that represent all the individual underlying
108 /// non-aggregate types that comprise it.
110 /// If Offsets is non-null, it points to a vector to be filled in
111 /// with the in-memory offsets of each of the individual values.
113 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
122 EE = STy->element_end();
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
137 // Base case: we can get an MVT for this LLVM IR type.
138 ValueVTs.push_back(TLI.getValueType(Ty));
140 Offsets->push_back(StartingOffset);
144 /// RegsForValue - This struct represents the registers (physical or virtual)
145 /// that a particular set of values is assigned, and the type information about
146 /// the value. The most common situation is to represent one value at a time,
147 /// but struct or array values are handled element-wise as multiple values.
148 /// The splitting of aggregates is performed recursively, so that we never
149 /// have aggregate-typed registers. The values at this point do not necessarily
150 /// have legal types, so each value may require one or more registers of some
153 struct VISIBILITY_HIDDEN RegsForValue {
154 /// TLI - The TargetLowering object.
156 const TargetLowering *TLI;
158 /// ValueVTs - The value types of the values, which may not be legal, and
159 /// may need be promoted or synthesized from one or more registers.
161 SmallVector<MVT, 4> ValueVTs;
163 /// RegVTs - The value types of the registers. This is the same size as
164 /// ValueVTs and it records, for each value, what the type of the assigned
165 /// register or registers are. (Individual values are never synthesized
166 /// from more than one type of register.)
168 /// With virtual registers, the contents of RegVTs is redundant with TLI's
169 /// getRegisterType member function, however when with physical registers
170 /// it is necessary to have a separate record of the types.
172 SmallVector<MVT, 4> RegVTs;
174 /// Regs - This list holds the registers assigned to the values.
175 /// Each legal or promoted value requires one register, and each
176 /// expanded value requires multiple registers.
178 SmallVector<unsigned, 4> Regs;
180 RegsForValue() : TLI(0) {}
182 RegsForValue(const TargetLowering &tli,
183 const SmallVector<unsigned, 4> ®s,
184 MVT regvt, MVT valuevt)
185 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 const SmallVector<MVT, 4> ®vts,
189 const SmallVector<MVT, 4> &valuevts)
190 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 unsigned Reg, const Type *Ty) : TLI(&tli) {
193 ComputeValueVTs(tli, Ty, ValueVTs);
195 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
196 MVT ValueVT = ValueVTs[Value];
197 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
198 MVT RegisterVT = TLI->getRegisterType(ValueVT);
199 for (unsigned i = 0; i != NumRegs; ++i)
200 Regs.push_back(Reg + i);
201 RegVTs.push_back(RegisterVT);
206 /// append - Add the specified values to this one.
207 void append(const RegsForValue &RHS) {
209 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
210 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
211 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
215 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
216 /// this value and returns the result as a ValueVTs value. This uses
217 /// Chain/Flag as the input and updates them for the output Chain/Flag.
218 /// If the Flag pointer is NULL, no flag is used.
219 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
220 SDValue &Chain, SDValue *Flag) const;
222 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
223 /// specified value into the registers specified by this object. This uses
224 /// Chain/Flag as the input and updates them for the output Chain/Flag.
225 /// If the Flag pointer is NULL, no flag is used.
226 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
227 SDValue &Chain, SDValue *Flag) const;
229 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
230 /// operand list. This adds the code marker and includes the number of
231 /// values added into it.
232 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
233 std::vector<SDValue> &Ops) const;
237 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
238 /// PHI nodes or outside of the basic block that defines it, or used by a
239 /// switch or atomic instruction, which may expand to multiple basic blocks.
240 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
241 if (isa<PHINode>(I)) return true;
242 BasicBlock *BB = I->getParent();
243 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
244 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
245 // FIXME: Remove switchinst special case.
246 isa<SwitchInst>(*UI))
251 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252 /// entry block, return true. This includes arguments used by switches, since
253 /// the switch may expand into multiple basic blocks.
254 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
260 return A->use_empty();
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
269 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
273 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
274 bool EnableFastISel) {
277 RegInfo = &MF->getRegInfo();
279 // Create a vreg for each argument register that is not dead and is used
280 // outside of the entry block for the function.
281 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
283 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
284 InitializeRegForValue(AI);
286 // Initialize the mapping of values to registers. This is only set up for
287 // instruction values that are used outside of the block that defines
289 Function::iterator BB = Fn->begin(), EB = Fn->end();
290 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
291 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
292 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
293 const Type *Ty = AI->getAllocatedType();
294 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
296 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
299 TySize *= CUI->getZExtValue(); // Get total allocated size.
300 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
301 StaticAllocaMap[AI] =
302 MF->getFrameInfo()->CreateStackObject(TySize, Align);
305 for (; BB != EB; ++BB)
306 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
307 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
308 if (!isa<AllocaInst>(I) ||
309 !StaticAllocaMap.count(cast<AllocaInst>(I)))
310 InitializeRegForValue(I);
312 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
313 // also creates the initial PHI MachineInstrs, though none of the input
314 // operands are populated.
315 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
316 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
320 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
323 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
324 if (PN->use_empty()) continue;
326 unsigned PHIReg = ValueMap[PN];
327 assert(PHIReg && "PHI node does not have an assigned virtual register!");
329 SmallVector<MVT, 4> ValueVTs;
330 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
331 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
332 MVT VT = ValueVTs[vti];
333 unsigned NumRegisters = TLI.getNumRegisters(VT);
334 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
335 for (unsigned i = 0; i != NumRegisters; ++i)
336 BuildMI(MBB, DebugLoc::getUnknownLoc(),
337 TII->get(TargetInstrInfo::PHI), PHIReg + i);
338 PHIReg += NumRegisters;
344 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
345 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
348 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
349 /// the correctly promoted or expanded types. Assign these registers
350 /// consecutive vreg numbers and return the first assigned number.
352 /// In the case that the given value has struct or array type, this function
353 /// will assign registers for each member or element.
355 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
356 SmallVector<MVT, 4> ValueVTs;
357 ComputeValueVTs(TLI, V->getType(), ValueVTs);
359 unsigned FirstReg = 0;
360 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
361 MVT ValueVT = ValueVTs[Value];
362 MVT RegisterVT = TLI.getRegisterType(ValueVT);
364 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
365 for (unsigned i = 0; i != NumRegs; ++i) {
366 unsigned R = MakeReg(RegisterVT);
367 if (!FirstReg) FirstReg = R;
373 /// getCopyFromParts - Create a value that contains the specified legal parts
374 /// combined into the value they represent. If the parts combine to a type
375 /// larger then ValueVT then AssertOp can be used to specify whether the extra
376 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
377 /// (ISD::AssertSext).
378 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
379 const SDValue *Parts,
380 unsigned NumParts, MVT PartVT, MVT ValueVT,
381 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
382 assert(NumParts > 0 && "No parts to assemble!");
383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
384 SDValue Val = Parts[0];
387 // Assemble the value from multiple parts.
388 if (!ValueVT.isVector()) {
389 unsigned PartBits = PartVT.getSizeInBits();
390 unsigned ValueBits = ValueVT.getSizeInBits();
392 // Assemble the power of 2 part.
393 unsigned RoundParts = NumParts & (NumParts - 1) ?
394 1 << Log2_32(NumParts) : NumParts;
395 unsigned RoundBits = PartBits * RoundParts;
396 MVT RoundVT = RoundBits == ValueBits ?
397 ValueVT : MVT::getIntegerVT(RoundBits);
400 MVT HalfVT = ValueVT.isInteger() ?
401 MVT::getIntegerVT(RoundBits/2) :
402 MVT::getFloatingPointVT(RoundBits/2);
404 if (RoundParts > 2) {
405 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
406 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
409 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
410 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
412 if (TLI.isBigEndian())
414 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
416 if (RoundParts < NumParts) {
417 // Assemble the trailing non-power-of-2 part.
418 unsigned OddParts = NumParts - RoundParts;
419 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
420 Hi = getCopyFromParts(DAG, dl,
421 Parts+RoundParts, OddParts, PartVT, OddVT);
423 // Combine the round and odd parts.
425 if (TLI.isBigEndian())
427 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
428 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
429 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
430 DAG.getConstant(Lo.getValueType().getSizeInBits(),
431 TLI.getPointerTy()));
432 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
433 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
436 // Handle a multi-element vector.
437 MVT IntermediateVT, RegisterVT;
438 unsigned NumIntermediates;
440 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
442 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
443 NumParts = NumRegs; // Silence a compiler warning.
444 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
445 assert(RegisterVT == Parts[0].getValueType() &&
446 "Part type doesn't match part!");
448 // Assemble the parts into intermediate operands.
449 SmallVector<SDValue, 8> Ops(NumIntermediates);
450 if (NumIntermediates == NumParts) {
451 // If the register was not expanded, truncate or copy the value,
453 for (unsigned i = 0; i != NumParts; ++i)
454 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
455 PartVT, IntermediateVT);
456 } else if (NumParts > 0) {
457 // If the intermediate type was expanded, build the intermediate operands
459 assert(NumParts % NumIntermediates == 0 &&
460 "Must expand into a divisible number of parts!");
461 unsigned Factor = NumParts / NumIntermediates;
462 for (unsigned i = 0; i != NumIntermediates; ++i)
463 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
464 PartVT, IntermediateVT);
467 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
469 Val = DAG.getNode(IntermediateVT.isVector() ?
470 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
471 ValueVT, &Ops[0], NumIntermediates);
475 // There is now one part, held in Val. Correct it to match ValueVT.
476 PartVT = Val.getValueType();
478 if (PartVT == ValueVT)
481 if (PartVT.isVector()) {
482 assert(ValueVT.isVector() && "Unknown vector conversion!");
483 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
486 if (ValueVT.isVector()) {
487 assert(ValueVT.getVectorElementType() == PartVT &&
488 ValueVT.getVectorNumElements() == 1 &&
489 "Only trivial scalar-to-vector conversions should get here!");
490 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
493 if (PartVT.isInteger() &&
494 ValueVT.isInteger()) {
495 if (ValueVT.bitsLT(PartVT)) {
496 // For a truncate, see if we have any information to
497 // indicate whether the truncated bits will always be
498 // zero or sign-extension.
499 if (AssertOp != ISD::DELETED_NODE)
500 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
501 DAG.getValueType(ValueVT));
502 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
504 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
508 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
509 if (ValueVT.bitsLT(Val.getValueType()))
510 // FP_ROUND's are always exact here.
511 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
512 DAG.getIntPtrConstant(1));
513 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
516 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
517 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
519 assert(0 && "Unknown mismatch!");
523 /// getCopyToParts - Create a series of nodes that contain the specified value
524 /// split into legal parts. If the parts contain more bits than Val, then, for
525 /// integers, ExtendKind can be used to specify how to generate the extra bits.
526 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
527 SDValue *Parts, unsigned NumParts, MVT PartVT,
528 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
530 MVT PtrVT = TLI.getPointerTy();
531 MVT ValueVT = Val.getValueType();
532 unsigned PartBits = PartVT.getSizeInBits();
533 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
538 if (!ValueVT.isVector()) {
539 if (PartVT == ValueVT) {
540 assert(NumParts == 1 && "No-op copy with multiple parts!");
545 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
546 // If the parts cover more bits than the value has, promote the value.
547 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
548 assert(NumParts == 1 && "Do not know what to promote to!");
549 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
550 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
551 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
552 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
554 assert(0 && "Unknown mismatch!");
556 } else if (PartBits == ValueVT.getSizeInBits()) {
557 // Different types of the same size.
558 assert(NumParts == 1 && PartVT != ValueVT);
559 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
560 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
561 // If the parts cover less bits than value has, truncate the value.
562 if (PartVT.isInteger() && ValueVT.isInteger()) {
563 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
564 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
566 assert(0 && "Unknown mismatch!");
570 // The value may have changed - recompute ValueVT.
571 ValueVT = Val.getValueType();
572 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
573 "Failed to tile the value with PartVT!");
576 assert(PartVT == ValueVT && "Type conversion failed!");
581 // Expand the value into multiple parts.
582 if (NumParts & (NumParts - 1)) {
583 // The number of parts is not a power of 2. Split off and copy the tail.
584 assert(PartVT.isInteger() && ValueVT.isInteger() &&
585 "Do not know what to expand to!");
586 unsigned RoundParts = 1 << Log2_32(NumParts);
587 unsigned RoundBits = RoundParts * PartBits;
588 unsigned OddParts = NumParts - RoundParts;
589 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
590 DAG.getConstant(RoundBits,
591 TLI.getPointerTy()));
592 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
593 if (TLI.isBigEndian())
594 // The odd parts were reversed by getCopyToParts - unreverse them.
595 std::reverse(Parts + RoundParts, Parts + NumParts);
596 NumParts = RoundParts;
597 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
598 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
601 // The number of parts is a power of 2. Repeatedly bisect the value using
603 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
604 MVT::getIntegerVT(ValueVT.getSizeInBits()),
606 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
607 for (unsigned i = 0; i < NumParts; i += StepSize) {
608 unsigned ThisBits = StepSize * PartBits / 2;
609 MVT ThisVT = MVT::getIntegerVT (ThisBits);
610 SDValue &Part0 = Parts[i];
611 SDValue &Part1 = Parts[i+StepSize/2];
613 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
615 DAG.getConstant(1, PtrVT));
616 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
618 DAG.getConstant(0, PtrVT));
620 if (ThisBits == PartBits && ThisVT != PartVT) {
621 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
623 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
629 if (TLI.isBigEndian())
630 std::reverse(Parts, Parts + NumParts);
637 if (PartVT != ValueVT) {
638 if (PartVT.isVector()) {
639 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
641 assert(ValueVT.getVectorElementType() == PartVT &&
642 ValueVT.getVectorNumElements() == 1 &&
643 "Only trivial vector-to-scalar conversions should get here!");
644 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
646 DAG.getConstant(0, PtrVT));
654 // Handle a multi-element vector.
655 MVT IntermediateVT, RegisterVT;
656 unsigned NumIntermediates;
657 unsigned NumRegs = TLI
658 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
660 unsigned NumElements = ValueVT.getVectorNumElements();
662 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
663 NumParts = NumRegs; // Silence a compiler warning.
664 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
666 // Split the vector into intermediate operands.
667 SmallVector<SDValue, 8> Ops(NumIntermediates);
668 for (unsigned i = 0; i != NumIntermediates; ++i)
669 if (IntermediateVT.isVector())
670 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
672 DAG.getConstant(i * (NumElements / NumIntermediates),
675 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
677 DAG.getConstant(i, PtrVT));
679 // Split the intermediate operands into legal parts.
680 if (NumParts == NumIntermediates) {
681 // If the register was not expanded, promote or copy the value,
683 for (unsigned i = 0; i != NumParts; ++i)
684 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
685 } else if (NumParts > 0) {
686 // If the intermediate type was expanded, split each the value into
688 assert(NumParts % NumIntermediates == 0 &&
689 "Must expand into a divisible number of parts!");
690 unsigned Factor = NumParts / NumIntermediates;
691 for (unsigned i = 0; i != NumIntermediates; ++i)
692 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
697 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
700 TD = DAG.getTarget().getTargetData();
703 /// clear - Clear out the curret SelectionDAG and the associated
704 /// state and prepare this SelectionDAGLowering object to be used
705 /// for a new block. This doesn't clear out information about
706 /// additional blocks that are needed to complete switch lowering
707 /// or PHI node updating; that information is cleared out as it is
709 void SelectionDAGLowering::clear() {
711 PendingLoads.clear();
712 PendingExports.clear();
716 /// getRoot - Return the current virtual root of the Selection DAG,
717 /// flushing any PendingLoad items. This must be done before emitting
718 /// a store or any other node that may need to be ordered after any
719 /// prior load instructions.
721 SDValue SelectionDAGLowering::getRoot() {
722 if (PendingLoads.empty())
723 return DAG.getRoot();
725 if (PendingLoads.size() == 1) {
726 SDValue Root = PendingLoads[0];
728 PendingLoads.clear();
732 // Otherwise, we have to make a token factor node.
733 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
734 &PendingLoads[0], PendingLoads.size());
735 PendingLoads.clear();
740 /// getControlRoot - Similar to getRoot, but instead of flushing all the
741 /// PendingLoad items, flush all the PendingExports items. It is necessary
742 /// to do this before emitting a terminator instruction.
744 SDValue SelectionDAGLowering::getControlRoot() {
745 SDValue Root = DAG.getRoot();
747 if (PendingExports.empty())
750 // Turn all of the CopyToReg chains into one factored node.
751 if (Root.getOpcode() != ISD::EntryToken) {
752 unsigned i = 0, e = PendingExports.size();
753 for (; i != e; ++i) {
754 assert(PendingExports[i].getNode()->getNumOperands() > 1);
755 if (PendingExports[i].getNode()->getOperand(0) == Root)
756 break; // Don't add the root if we already indirectly depend on it.
760 PendingExports.push_back(Root);
763 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
765 PendingExports.size());
766 PendingExports.clear();
771 void SelectionDAGLowering::visit(Instruction &I) {
772 visit(I.getOpcode(), I);
775 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
776 // Note: this doesn't use InstVisitor, because it has to work with
777 // ConstantExpr's in addition to instructions.
779 default: assert(0 && "Unknown instruction type encountered!");
781 // Build the switch statement using the Instruction.def file.
782 #define HANDLE_INST(NUM, OPCODE, CLASS) \
783 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
784 #include "llvm/Instruction.def"
788 void SelectionDAGLowering::visitAdd(User &I) {
789 if (I.getType()->isFPOrFPVector())
790 visitBinary(I, ISD::FADD);
792 visitBinary(I, ISD::ADD);
795 void SelectionDAGLowering::visitMul(User &I) {
796 if (I.getType()->isFPOrFPVector())
797 visitBinary(I, ISD::FMUL);
799 visitBinary(I, ISD::MUL);
802 SDValue SelectionDAGLowering::getValue(const Value *V) {
803 SDValue &N = NodeMap[V];
804 if (N.getNode()) return N;
806 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
807 MVT VT = TLI.getValueType(V->getType(), true);
809 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
810 return N = DAG.getConstant(*CI, VT);
812 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
813 return N = DAG.getGlobalAddress(GV, VT);
815 if (isa<ConstantPointerNull>(C))
816 return N = DAG.getConstant(0, TLI.getPointerTy());
818 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
819 return N = DAG.getConstantFP(*CFP, VT);
821 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
822 !V->getType()->isAggregateType())
823 return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
825 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
826 visit(CE->getOpcode(), *CE);
827 SDValue N1 = NodeMap[V];
828 assert(N1.getNode() && "visit didn't populate the ValueMap!");
832 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
833 SmallVector<SDValue, 4> Constants;
834 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
836 SDNode *Val = getValue(*OI).getNode();
837 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
838 Constants.push_back(SDValue(Val, i));
840 return DAG.getMergeValues(&Constants[0], Constants.size());
843 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
844 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
845 "Unknown struct or array constant!");
847 SmallVector<MVT, 4> ValueVTs;
848 ComputeValueVTs(TLI, C->getType(), ValueVTs);
849 unsigned NumElts = ValueVTs.size();
851 return SDValue(); // empty struct
852 SmallVector<SDValue, 4> Constants(NumElts);
853 for (unsigned i = 0; i != NumElts; ++i) {
854 MVT EltVT = ValueVTs[i];
855 if (isa<UndefValue>(C))
856 Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
857 else if (EltVT.isFloatingPoint())
858 Constants[i] = DAG.getConstantFP(0, EltVT);
860 Constants[i] = DAG.getConstant(0, EltVT);
862 return DAG.getMergeValues(&Constants[0], NumElts);
865 const VectorType *VecTy = cast<VectorType>(V->getType());
866 unsigned NumElements = VecTy->getNumElements();
868 // Now that we know the number and type of the elements, get that number of
869 // elements into the Ops array based on what kind of constant it is.
870 SmallVector<SDValue, 16> Ops;
871 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
872 for (unsigned i = 0; i != NumElements; ++i)
873 Ops.push_back(getValue(CP->getOperand(i)));
875 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
876 "Unknown vector constant!");
877 MVT EltVT = TLI.getValueType(VecTy->getElementType());
880 if (isa<UndefValue>(C))
881 Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
882 else if (EltVT.isFloatingPoint())
883 Op = DAG.getConstantFP(0, EltVT);
885 Op = DAG.getConstant(0, EltVT);
886 Ops.assign(NumElements, Op);
889 // Create a BUILD_VECTOR node.
890 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
891 VT, &Ops[0], Ops.size());
894 // If this is a static alloca, generate it as the frameindex instead of
896 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
897 DenseMap<const AllocaInst*, int>::iterator SI =
898 FuncInfo.StaticAllocaMap.find(AI);
899 if (SI != FuncInfo.StaticAllocaMap.end())
900 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
903 unsigned InReg = FuncInfo.ValueMap[V];
904 assert(InReg && "Value not in map!");
906 RegsForValue RFV(TLI, InReg, V->getType());
907 SDValue Chain = DAG.getEntryNode();
908 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
912 void SelectionDAGLowering::visitRet(ReturnInst &I) {
913 if (I.getNumOperands() == 0) {
914 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
915 MVT::Other, getControlRoot()));
919 SmallVector<SDValue, 8> NewValues;
920 NewValues.push_back(getControlRoot());
921 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
922 SmallVector<MVT, 4> ValueVTs;
923 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
924 unsigned NumValues = ValueVTs.size();
925 if (NumValues == 0) continue;
927 SDValue RetOp = getValue(I.getOperand(i));
928 for (unsigned j = 0, f = NumValues; j != f; ++j) {
929 MVT VT = ValueVTs[j];
931 // FIXME: C calling convention requires the return type to be promoted to
932 // at least 32-bit. But this is not necessary for non-C calling
934 if (VT.isInteger()) {
935 MVT MinVT = TLI.getRegisterType(MVT::i32);
936 if (VT.bitsLT(MinVT))
940 unsigned NumParts = TLI.getNumRegisters(VT);
941 MVT PartVT = TLI.getRegisterType(VT);
942 SmallVector<SDValue, 4> Parts(NumParts);
943 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
945 const Function *F = I.getParent()->getParent();
946 if (F->paramHasAttr(0, Attribute::SExt))
947 ExtendKind = ISD::SIGN_EXTEND;
948 else if (F->paramHasAttr(0, Attribute::ZExt))
949 ExtendKind = ISD::ZERO_EXTEND;
951 getCopyToParts(DAG, getCurDebugLoc(),
952 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
953 &Parts[0], NumParts, PartVT, ExtendKind);
955 // 'inreg' on function refers to return value
956 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
957 if (F->paramHasAttr(0, Attribute::InReg))
959 for (unsigned i = 0; i < NumParts; ++i) {
960 NewValues.push_back(Parts[i]);
961 NewValues.push_back(DAG.getArgFlags(Flags));
965 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
966 &NewValues[0], NewValues.size()));
969 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
970 /// the current basic block, add it to ValueMap now so that we'll get a
972 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
973 // No need to export constants.
974 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
977 if (FuncInfo.isExportedInst(V)) return;
979 unsigned Reg = FuncInfo.InitializeRegForValue(V);
980 CopyValueToVirtualRegister(V, Reg);
983 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
984 const BasicBlock *FromBB) {
985 // The operands of the setcc have to be in this block. We don't know
986 // how to export them from some other block.
987 if (Instruction *VI = dyn_cast<Instruction>(V)) {
988 // Can export from current BB.
989 if (VI->getParent() == FromBB)
992 // Is already exported, noop.
993 return FuncInfo.isExportedInst(V);
996 // If this is an argument, we can export it if the BB is the entry block or
997 // if it is already exported.
998 if (isa<Argument>(V)) {
999 if (FromBB == &FromBB->getParent()->getEntryBlock())
1002 // Otherwise, can only export this if it is already exported.
1003 return FuncInfo.isExportedInst(V);
1006 // Otherwise, constants can always be exported.
1010 static bool InBlock(const Value *V, const BasicBlock *BB) {
1011 if (const Instruction *I = dyn_cast<Instruction>(V))
1012 return I->getParent() == BB;
1016 /// getFCmpCondCode - Return the ISD condition code corresponding to
1017 /// the given LLVM IR floating-point condition code. This includes
1018 /// consideration of global floating-point math flags.
1020 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1021 ISD::CondCode FPC, FOC;
1023 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1024 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1025 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1026 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1027 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1028 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1029 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1030 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1031 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1032 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1033 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1034 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1035 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1036 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1037 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1038 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1040 assert(0 && "Invalid FCmp predicate opcode!");
1041 FOC = FPC = ISD::SETFALSE;
1044 if (FiniteOnlyFPMath())
1050 /// getICmpCondCode - Return the ISD condition code corresponding to
1051 /// the given LLVM IR integer condition code.
1053 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1055 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1056 case ICmpInst::ICMP_NE: return ISD::SETNE;
1057 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1058 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1059 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1060 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1061 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1062 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1063 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1064 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1066 assert(0 && "Invalid ICmp predicate opcode!");
1071 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1072 /// This function emits a branch and is used at the leaves of an OR or an
1073 /// AND operator tree.
1076 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1077 MachineBasicBlock *TBB,
1078 MachineBasicBlock *FBB,
1079 MachineBasicBlock *CurBB) {
1080 const BasicBlock *BB = CurBB->getBasicBlock();
1082 // If the leaf of the tree is a comparison, merge the condition into
1084 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1085 // The operands of the cmp have to be in this block. We don't know
1086 // how to export them from some other block. If this is the first block
1087 // of the sequence, no exporting is needed.
1088 if (CurBB == CurMBB ||
1089 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1090 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1091 ISD::CondCode Condition;
1092 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1093 Condition = getICmpCondCode(IC->getPredicate());
1094 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1095 Condition = getFCmpCondCode(FC->getPredicate());
1097 Condition = ISD::SETEQ; // silence warning.
1098 assert(0 && "Unknown compare instruction");
1101 CaseBlock CB(Condition, BOp->getOperand(0),
1102 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1103 SwitchCases.push_back(CB);
1108 // Create a CaseBlock record representing this branch.
1109 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1110 NULL, TBB, FBB, CurBB);
1111 SwitchCases.push_back(CB);
1114 /// FindMergedConditions - If Cond is an expression like
1115 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1116 MachineBasicBlock *TBB,
1117 MachineBasicBlock *FBB,
1118 MachineBasicBlock *CurBB,
1120 // If this node is not part of the or/and tree, emit it as a branch.
1121 Instruction *BOp = dyn_cast<Instruction>(Cond);
1122 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1123 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1124 BOp->getParent() != CurBB->getBasicBlock() ||
1125 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1126 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1127 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1131 // Create TmpBB after CurBB.
1132 MachineFunction::iterator BBI = CurBB;
1133 MachineFunction &MF = DAG.getMachineFunction();
1134 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1135 CurBB->getParent()->insert(++BBI, TmpBB);
1137 if (Opc == Instruction::Or) {
1138 // Codegen X | Y as:
1146 // Emit the LHS condition.
1147 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1149 // Emit the RHS condition into TmpBB.
1150 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1152 assert(Opc == Instruction::And && "Unknown merge op!");
1153 // Codegen X & Y as:
1160 // This requires creation of TmpBB after CurBB.
1162 // Emit the LHS condition.
1163 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1165 // Emit the RHS condition into TmpBB.
1166 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1170 /// If the set of cases should be emitted as a series of branches, return true.
1171 /// If we should emit this as a bunch of and/or'd together conditions, return
1174 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1175 if (Cases.size() != 2) return true;
1177 // If this is two comparisons of the same values or'd or and'd together, they
1178 // will get folded into a single comparison, so don't emit two blocks.
1179 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1180 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1181 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1182 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1189 void SelectionDAGLowering::visitBr(BranchInst &I) {
1190 // Update machine-CFG edges.
1191 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1193 // Figure out which block is immediately after the current one.
1194 MachineBasicBlock *NextBlock = 0;
1195 MachineFunction::iterator BBI = CurMBB;
1196 if (++BBI != CurMBB->getParent()->end())
1199 if (I.isUnconditional()) {
1200 // Update machine-CFG edges.
1201 CurMBB->addSuccessor(Succ0MBB);
1203 // If this is not a fall-through branch, emit the branch.
1204 if (Succ0MBB != NextBlock)
1205 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1206 MVT::Other, getControlRoot(),
1207 DAG.getBasicBlock(Succ0MBB)));
1211 // If this condition is one of the special cases we handle, do special stuff
1213 Value *CondVal = I.getCondition();
1214 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1216 // If this is a series of conditions that are or'd or and'd together, emit
1217 // this as a sequence of branches instead of setcc's with and/or operations.
1218 // For example, instead of something like:
1231 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1232 if (BOp->hasOneUse() &&
1233 (BOp->getOpcode() == Instruction::And ||
1234 BOp->getOpcode() == Instruction::Or)) {
1235 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1236 // If the compares in later blocks need to use values not currently
1237 // exported from this block, export them now. This block should always
1238 // be the first entry.
1239 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1241 // Allow some cases to be rejected.
1242 if (ShouldEmitAsBranches(SwitchCases)) {
1243 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1244 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1245 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1248 // Emit the branch for this block.
1249 visitSwitchCase(SwitchCases[0]);
1250 SwitchCases.erase(SwitchCases.begin());
1254 // Okay, we decided not to do this, remove any inserted MBB's and clear
1256 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1257 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1259 SwitchCases.clear();
1263 // Create a CaseBlock record representing this branch.
1264 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1265 NULL, Succ0MBB, Succ1MBB, CurMBB);
1266 // Use visitSwitchCase to actually insert the fast branch sequence for this
1268 visitSwitchCase(CB);
1271 /// visitSwitchCase - Emits the necessary code to represent a single node in
1272 /// the binary search tree resulting from lowering a switch instruction.
1273 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1275 SDValue CondLHS = getValue(CB.CmpLHS);
1277 // Build the setcc now.
1278 if (CB.CmpMHS == NULL) {
1279 // Fold "(X == true)" to X and "(X == false)" to !X to
1280 // handle common cases produced by branch lowering.
1281 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1283 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1284 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1285 Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
1286 CondLHS.getValueType(), CondLHS, True);
1288 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1290 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1292 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1293 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1295 SDValue CmpOp = getValue(CB.CmpMHS);
1296 MVT VT = CmpOp.getValueType();
1298 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1299 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1301 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(),
1302 VT, CmpOp, DAG.getConstant(Low, VT));
1303 Cond = DAG.getSetCC(MVT::i1, SUB,
1304 DAG.getConstant(High-Low, VT), ISD::SETULE);
1308 // Update successor info
1309 CurMBB->addSuccessor(CB.TrueBB);
1310 CurMBB->addSuccessor(CB.FalseBB);
1312 // Set NextBlock to be the MBB immediately after the current one, if any.
1313 // This is used to avoid emitting unnecessary branches to the next block.
1314 MachineBasicBlock *NextBlock = 0;
1315 MachineFunction::iterator BBI = CurMBB;
1316 if (++BBI != CurMBB->getParent()->end())
1319 // If the lhs block is the next block, invert the condition so that we can
1320 // fall through to the lhs instead of the rhs block.
1321 if (CB.TrueBB == NextBlock) {
1322 std::swap(CB.TrueBB, CB.FalseBB);
1323 SDValue True = DAG.getConstant(1, Cond.getValueType());
1324 Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
1325 Cond.getValueType(), Cond, True);
1327 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1328 MVT::Other, getControlRoot(), Cond,
1329 DAG.getBasicBlock(CB.TrueBB));
1331 // If the branch was constant folded, fix up the CFG.
1332 if (BrCond.getOpcode() == ISD::BR) {
1333 CurMBB->removeSuccessor(CB.FalseBB);
1334 DAG.setRoot(BrCond);
1336 // Otherwise, go ahead and insert the false branch.
1337 if (BrCond == getControlRoot())
1338 CurMBB->removeSuccessor(CB.TrueBB);
1340 if (CB.FalseBB == NextBlock)
1341 DAG.setRoot(BrCond);
1343 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1344 DAG.getBasicBlock(CB.FalseBB)));
1348 /// visitJumpTable - Emit JumpTable node in the current MBB
1349 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1350 // Emit the code for the jump table
1351 assert(JT.Reg != -1U && "Should lower JT Header first!");
1352 MVT PTy = TLI.getPointerTy();
1353 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1354 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1355 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1356 MVT::Other, Index.getValue(1),
1360 /// visitJumpTableHeader - This function emits necessary code to produce index
1361 /// in the JumpTable from switch case.
1362 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1363 JumpTableHeader &JTH) {
1364 // Subtract the lowest switch case value from the value being switched on and
1365 // conditional branch to default mbb if the result is greater than the
1366 // difference between smallest and largest cases.
1367 SDValue SwitchOp = getValue(JTH.SValue);
1368 MVT VT = SwitchOp.getValueType();
1369 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1370 DAG.getConstant(JTH.First, VT));
1372 // The SDNode we just created, which holds the value being switched on minus
1373 // the the smallest case value, needs to be copied to a virtual register so it
1374 // can be used as an index into the jump table in a subsequent basic block.
1375 // This value may be smaller or larger than the target's pointer type, and
1376 // therefore require extension or truncating.
1377 if (VT.bitsGT(TLI.getPointerTy()))
1378 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1379 TLI.getPointerTy(), SUB);
1381 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1382 TLI.getPointerTy(), SUB);
1384 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1385 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1386 JT.Reg = JumpTableReg;
1388 // Emit the range check for the jump table, and branch to the default block
1389 // for the switch statement if the value being switched on exceeds the largest
1390 // case in the switch.
1391 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
1392 DAG.getConstant(JTH.Last-JTH.First,VT),
1395 // Set NextBlock to be the MBB immediately after the current one, if any.
1396 // This is used to avoid emitting unnecessary branches to the next block.
1397 MachineBasicBlock *NextBlock = 0;
1398 MachineFunction::iterator BBI = CurMBB;
1399 if (++BBI != CurMBB->getParent()->end())
1402 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1403 MVT::Other, CopyTo, CMP,
1404 DAG.getBasicBlock(JT.Default));
1406 if (JT.MBB == NextBlock)
1407 DAG.setRoot(BrCond);
1409 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1410 DAG.getBasicBlock(JT.MBB)));
1413 /// visitBitTestHeader - This function emits necessary code to produce value
1414 /// suitable for "bit tests"
1415 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1416 // Subtract the minimum value
1417 SDValue SwitchOp = getValue(B.SValue);
1418 MVT VT = SwitchOp.getValueType();
1419 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1420 DAG.getConstant(B.First, VT));
1423 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
1424 DAG.getConstant(B.Range, VT),
1428 if (VT.bitsGT(TLI.getPointerTy()))
1429 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1430 TLI.getPointerTy(), SUB);
1432 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1433 TLI.getPointerTy(), SUB);
1435 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1436 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp);
1438 // Set NextBlock to be the MBB immediately after the current one, if any.
1439 // This is used to avoid emitting unnecessary branches to the next block.
1440 MachineBasicBlock *NextBlock = 0;
1441 MachineFunction::iterator BBI = CurMBB;
1442 if (++BBI != CurMBB->getParent()->end())
1445 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1447 CurMBB->addSuccessor(B.Default);
1448 CurMBB->addSuccessor(MBB);
1450 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1451 MVT::Other, CopyTo, RangeCmp,
1452 DAG.getBasicBlock(B.Default));
1454 if (MBB == NextBlock)
1455 DAG.setRoot(BrRange);
1457 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1458 DAG.getBasicBlock(MBB)));
1461 /// visitBitTestCase - this function produces one "bit test"
1462 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1465 // Make desired shift
1466 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg,
1467 TLI.getPointerTy());
1468 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1470 DAG.getConstant(1, TLI.getPointerTy()),
1473 // Emit bit tests and jumps
1474 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1475 TLI.getPointerTy(), SwitchVal,
1476 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1477 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
1478 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1481 CurMBB->addSuccessor(B.TargetBB);
1482 CurMBB->addSuccessor(NextMBB);
1484 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1485 MVT::Other, getControlRoot(),
1486 AndCmp, DAG.getBasicBlock(B.TargetBB));
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = CurMBB;
1492 if (++BBI != CurMBB->getParent()->end())
1495 if (NextMBB == NextBlock)
1498 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1499 DAG.getBasicBlock(NextMBB)));
1502 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1503 // Retrieve successors.
1504 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1505 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1507 const Value *Callee(I.getCalledValue());
1508 if (isa<InlineAsm>(Callee))
1511 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1513 // If the value of the invoke is used outside of its defining block, make it
1514 // available as a virtual register.
1515 if (!I.use_empty()) {
1516 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1517 if (VMI != FuncInfo.ValueMap.end())
1518 CopyValueToVirtualRegister(&I, VMI->second);
1521 // Update successor info
1522 CurMBB->addSuccessor(Return);
1523 CurMBB->addSuccessor(LandingPad);
1525 // Drop into normal successor.
1526 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1527 MVT::Other, getControlRoot(),
1528 DAG.getBasicBlock(Return)));
1531 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1534 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1535 /// small case ranges).
1536 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1537 CaseRecVector& WorkList,
1539 MachineBasicBlock* Default) {
1540 Case& BackCase = *(CR.Range.second-1);
1542 // Size is the number of Cases represented by this range.
1543 size_t Size = CR.Range.second - CR.Range.first;
1547 // Get the MachineFunction which holds the current MBB. This is used when
1548 // inserting any additional MBBs necessary to represent the switch.
1549 MachineFunction *CurMF = CurMBB->getParent();
1551 // Figure out which block is immediately after the current one.
1552 MachineBasicBlock *NextBlock = 0;
1553 MachineFunction::iterator BBI = CR.CaseBB;
1555 if (++BBI != CurMBB->getParent()->end())
1558 // TODO: If any two of the cases has the same destination, and if one value
1559 // is the same as the other, but has one bit unset that the other has set,
1560 // use bit manipulation to do two compares at once. For example:
1561 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1563 // Rearrange the case blocks so that the last one falls through if possible.
1564 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1565 // The last case block won't fall through into 'NextBlock' if we emit the
1566 // branches in this order. See if rearranging a case value would help.
1567 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1568 if (I->BB == NextBlock) {
1569 std::swap(*I, BackCase);
1575 // Create a CaseBlock record representing a conditional branch to
1576 // the Case's target mbb if the value being switched on SV is equal
1578 MachineBasicBlock *CurBlock = CR.CaseBB;
1579 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1580 MachineBasicBlock *FallThrough;
1582 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1583 CurMF->insert(BBI, FallThrough);
1585 // If the last case doesn't match, go to the default block.
1586 FallThrough = Default;
1589 Value *RHS, *LHS, *MHS;
1591 if (I->High == I->Low) {
1592 // This is just small small case range :) containing exactly 1 case
1594 LHS = SV; RHS = I->High; MHS = NULL;
1597 LHS = I->Low; MHS = SV; RHS = I->High;
1599 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1601 // If emitting the first comparison, just call visitSwitchCase to emit the
1602 // code into the current block. Otherwise, push the CaseBlock onto the
1603 // vector to be later processed by SDISel, and insert the node's MBB
1604 // before the next MBB.
1605 if (CurBlock == CurMBB)
1606 visitSwitchCase(CB);
1608 SwitchCases.push_back(CB);
1610 CurBlock = FallThrough;
1616 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1617 return !DisableJumpTables &&
1618 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1619 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1622 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1623 APInt LastExt(Last), FirstExt(First);
1624 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1625 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1626 return (LastExt - FirstExt + 1ULL);
1629 /// handleJTSwitchCase - Emit jumptable for current switch case range
1630 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1631 CaseRecVector& WorkList,
1633 MachineBasicBlock* Default) {
1634 Case& FrontCase = *CR.Range.first;
1635 Case& BackCase = *(CR.Range.second-1);
1637 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1638 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1641 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1645 if (!areJTsAllowed(TLI) || TSize <= 3)
1648 APInt Range = ComputeRange(First, Last);
1649 double Density = (double)TSize / Range.roundToDouble();
1653 DEBUG(errs() << "Lowering jump table\n"
1654 << "First entry: " << First << ". Last entry: " << Last << '\n'
1655 << "Range: " << Range
1656 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1658 // Get the MachineFunction which holds the current MBB. This is used when
1659 // inserting any additional MBBs necessary to represent the switch.
1660 MachineFunction *CurMF = CurMBB->getParent();
1662 // Figure out which block is immediately after the current one.
1663 MachineBasicBlock *NextBlock = 0;
1664 MachineFunction::iterator BBI = CR.CaseBB;
1666 if (++BBI != CurMBB->getParent()->end())
1669 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1671 // Create a new basic block to hold the code for loading the address
1672 // of the jump table, and jumping to it. Update successor information;
1673 // we will either branch to the default case for the switch, or the jump
1675 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1676 CurMF->insert(BBI, JumpTableBB);
1677 CR.CaseBB->addSuccessor(Default);
1678 CR.CaseBB->addSuccessor(JumpTableBB);
1680 // Build a vector of destination BBs, corresponding to each target
1681 // of the jump table. If the value of the jump table slot corresponds to
1682 // a case statement, push the case's BB onto the vector, otherwise, push
1684 std::vector<MachineBasicBlock*> DestBBs;
1686 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1687 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1688 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1690 if (Low.sle(TEI) && TEI.sle(High)) {
1691 DestBBs.push_back(I->BB);
1695 DestBBs.push_back(Default);
1699 // Update successor info. Add one edge to each unique successor.
1700 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1701 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1702 E = DestBBs.end(); I != E; ++I) {
1703 if (!SuccsHandled[(*I)->getNumber()]) {
1704 SuccsHandled[(*I)->getNumber()] = true;
1705 JumpTableBB->addSuccessor(*I);
1709 // Create a jump table index for this jump table, or return an existing
1711 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1713 // Set the jump table information so that we can codegen it as a second
1714 // MachineBasicBlock
1715 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1716 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1717 if (CR.CaseBB == CurMBB)
1718 visitJumpTableHeader(JT, JTH);
1720 JTCases.push_back(JumpTableBlock(JTH, JT));
1725 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1727 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1728 CaseRecVector& WorkList,
1730 MachineBasicBlock* Default) {
1731 // Get the MachineFunction which holds the current MBB. This is used when
1732 // inserting any additional MBBs necessary to represent the switch.
1733 MachineFunction *CurMF = CurMBB->getParent();
1735 // Figure out which block is immediately after the current one.
1736 MachineBasicBlock *NextBlock = 0;
1737 MachineFunction::iterator BBI = CR.CaseBB;
1739 if (++BBI != CurMBB->getParent()->end())
1742 Case& FrontCase = *CR.Range.first;
1743 Case& BackCase = *(CR.Range.second-1);
1744 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1746 // Size is the number of Cases represented by this range.
1747 unsigned Size = CR.Range.second - CR.Range.first;
1749 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1750 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1752 CaseItr Pivot = CR.Range.first + Size/2;
1754 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1755 // (heuristically) allow us to emit JumpTable's later.
1757 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1761 size_t LSize = FrontCase.size();
1762 size_t RSize = TSize-LSize;
1763 DEBUG(errs() << "Selecting best pivot: \n"
1764 << "First: " << First << ", Last: " << Last <<'\n'
1765 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1766 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1768 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1769 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1770 APInt Range = ComputeRange(LEnd, RBegin);
1771 assert((Range - 2ULL).isNonNegative() &&
1772 "Invalid case distance");
1773 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1774 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1775 double Metric = Range.logBase2()*(LDensity+RDensity);
1776 // Should always split in some non-trivial place
1777 DEBUG(errs() <<"=>Step\n"
1778 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1779 << "LDensity: " << LDensity
1780 << ", RDensity: " << RDensity << '\n'
1781 << "Metric: " << Metric << '\n');
1782 if (FMetric < Metric) {
1785 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1791 if (areJTsAllowed(TLI)) {
1792 // If our case is dense we *really* should handle it earlier!
1793 assert((FMetric > 0) && "Should handle dense range earlier!");
1795 Pivot = CR.Range.first + Size/2;
1798 CaseRange LHSR(CR.Range.first, Pivot);
1799 CaseRange RHSR(Pivot, CR.Range.second);
1800 Constant *C = Pivot->Low;
1801 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1803 // We know that we branch to the LHS if the Value being switched on is
1804 // less than the Pivot value, C. We use this to optimize our binary
1805 // tree a bit, by recognizing that if SV is greater than or equal to the
1806 // LHS's Case Value, and that Case Value is exactly one less than the
1807 // Pivot's Value, then we can branch directly to the LHS's Target,
1808 // rather than creating a leaf node for it.
1809 if ((LHSR.second - LHSR.first) == 1 &&
1810 LHSR.first->High == CR.GE &&
1811 cast<ConstantInt>(C)->getValue() ==
1812 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1813 TrueBB = LHSR.first->BB;
1815 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1816 CurMF->insert(BBI, TrueBB);
1817 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1820 // Similar to the optimization above, if the Value being switched on is
1821 // known to be less than the Constant CR.LT, and the current Case Value
1822 // is CR.LT - 1, then we can branch directly to the target block for
1823 // the current Case Value, rather than emitting a RHS leaf node for it.
1824 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1825 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1826 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1827 FalseBB = RHSR.first->BB;
1829 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1830 CurMF->insert(BBI, FalseBB);
1831 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1834 // Create a CaseBlock record representing a conditional branch to
1835 // the LHS node if the value being switched on SV is less than C.
1836 // Otherwise, branch to LHS.
1837 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1839 if (CR.CaseBB == CurMBB)
1840 visitSwitchCase(CB);
1842 SwitchCases.push_back(CB);
1847 /// handleBitTestsSwitchCase - if current case range has few destination and
1848 /// range span less, than machine word bitwidth, encode case range into series
1849 /// of masks and emit bit tests with these masks.
1850 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1851 CaseRecVector& WorkList,
1853 MachineBasicBlock* Default){
1854 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1856 Case& FrontCase = *CR.Range.first;
1857 Case& BackCase = *(CR.Range.second-1);
1859 // Get the MachineFunction which holds the current MBB. This is used when
1860 // inserting any additional MBBs necessary to represent the switch.
1861 MachineFunction *CurMF = CurMBB->getParent();
1864 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1866 // Single case counts one, case range - two.
1867 numCmps += (I->Low == I->High ? 1 : 2);
1870 // Count unique destinations
1871 SmallSet<MachineBasicBlock*, 4> Dests;
1872 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1873 Dests.insert(I->BB);
1874 if (Dests.size() > 3)
1875 // Don't bother the code below, if there are too much unique destinations
1878 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1879 << "Total number of comparisons: " << numCmps << '\n');
1881 // Compute span of values.
1882 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1883 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1884 APInt cmpRange = maxValue - minValue;
1886 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1887 << "Low bound: " << minValue << '\n'
1888 << "High bound: " << maxValue << '\n');
1890 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1891 (!(Dests.size() == 1 && numCmps >= 3) &&
1892 !(Dests.size() == 2 && numCmps >= 5) &&
1893 !(Dests.size() >= 3 && numCmps >= 6)))
1896 DEBUG(errs() << "Emitting bit tests\n");
1897 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1899 // Optimize the case where all the case values fit in a
1900 // word without having to subtract minValue. In this case,
1901 // we can optimize away the subtraction.
1902 if (minValue.isNonNegative() &&
1903 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1904 cmpRange = maxValue;
1906 lowBound = minValue;
1909 CaseBitsVector CasesBits;
1910 unsigned i, count = 0;
1912 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1913 MachineBasicBlock* Dest = I->BB;
1914 for (i = 0; i < count; ++i)
1915 if (Dest == CasesBits[i].BB)
1919 assert((count < 3) && "Too much destinations to test!");
1920 CasesBits.push_back(CaseBits(0, Dest, 0));
1924 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1925 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1927 uint64_t lo = (lowValue - lowBound).getZExtValue();
1928 uint64_t hi = (highValue - lowBound).getZExtValue();
1930 for (uint64_t j = lo; j <= hi; j++) {
1931 CasesBits[i].Mask |= 1ULL << j;
1932 CasesBits[i].Bits++;
1936 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1940 // Figure out which block is immediately after the current one.
1941 MachineFunction::iterator BBI = CR.CaseBB;
1944 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1946 DEBUG(errs() << "Cases:\n");
1947 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1948 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
1949 << ", Bits: " << CasesBits[i].Bits
1950 << ", BB: " << CasesBits[i].BB << '\n');
1952 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1953 CurMF->insert(BBI, CaseBB);
1954 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1959 BitTestBlock BTB(lowBound, cmpRange, SV,
1960 -1U, (CR.CaseBB == CurMBB),
1961 CR.CaseBB, Default, BTC);
1963 if (CR.CaseBB == CurMBB)
1964 visitBitTestHeader(BTB);
1966 BitTestCases.push_back(BTB);
1972 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1973 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
1974 const SwitchInst& SI) {
1977 // Start with "simple" cases
1978 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1979 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1980 Cases.push_back(Case(SI.getSuccessorValue(i),
1981 SI.getSuccessorValue(i),
1984 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1986 // Merge case into clusters
1987 if (Cases.size() >= 2)
1988 // Must recompute end() each iteration because it may be
1989 // invalidated by erase if we hold on to it
1990 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1991 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1992 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1993 MachineBasicBlock* nextBB = J->BB;
1994 MachineBasicBlock* currentBB = I->BB;
1996 // If the two neighboring cases go to the same destination, merge them
1997 // into a single case.
1998 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2006 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2007 if (I->Low != I->High)
2008 // A range counts double, since it requires two compares.
2015 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2016 // Figure out which block is immediately after the current one.
2017 MachineBasicBlock *NextBlock = 0;
2018 MachineFunction::iterator BBI = CurMBB;
2020 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2022 // If there is only the default destination, branch to it if it is not the
2023 // next basic block. Otherwise, just fall through.
2024 if (SI.getNumOperands() == 2) {
2025 // Update machine-CFG edges.
2027 // If this is not a fall-through branch, emit the branch.
2028 CurMBB->addSuccessor(Default);
2029 if (Default != NextBlock)
2030 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2031 MVT::Other, getControlRoot(),
2032 DAG.getBasicBlock(Default)));
2036 // If there are any non-default case statements, create a vector of Cases
2037 // representing each one, and sort the vector so that we can efficiently
2038 // create a binary search tree from them.
2040 size_t numCmps = Clusterify(Cases, SI);
2041 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2042 << ". Total compares: " << numCmps << '\n');
2045 // Get the Value to be switched on and default basic blocks, which will be
2046 // inserted into CaseBlock records, representing basic blocks in the binary
2048 Value *SV = SI.getOperand(0);
2050 // Push the initial CaseRec onto the worklist
2051 CaseRecVector WorkList;
2052 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2054 while (!WorkList.empty()) {
2055 // Grab a record representing a case range to process off the worklist
2056 CaseRec CR = WorkList.back();
2057 WorkList.pop_back();
2059 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2062 // If the range has few cases (two or less) emit a series of specific
2064 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2067 // If the switch has more than 5 blocks, and at least 40% dense, and the
2068 // target supports indirect branches, then emit a jump table rather than
2069 // lowering the switch to a binary tree of conditional branches.
2070 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2073 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2074 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2075 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2080 void SelectionDAGLowering::visitSub(User &I) {
2081 // -0.0 - X --> fneg
2082 const Type *Ty = I.getType();
2083 if (isa<VectorType>(Ty)) {
2084 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2085 const VectorType *DestTy = cast<VectorType>(I.getType());
2086 const Type *ElTy = DestTy->getElementType();
2087 if (ElTy->isFloatingPoint()) {
2088 unsigned VL = DestTy->getNumElements();
2089 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2090 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2092 SDValue Op2 = getValue(I.getOperand(1));
2093 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2094 Op2.getValueType(), Op2));
2100 if (Ty->isFloatingPoint()) {
2101 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2102 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2103 SDValue Op2 = getValue(I.getOperand(1));
2104 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2105 Op2.getValueType(), Op2));
2110 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2113 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2114 SDValue Op1 = getValue(I.getOperand(0));
2115 SDValue Op2 = getValue(I.getOperand(1));
2117 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2118 Op1.getValueType(), Op1, Op2));
2121 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2122 SDValue Op1 = getValue(I.getOperand(0));
2123 SDValue Op2 = getValue(I.getOperand(1));
2124 if (!isa<VectorType>(I.getType())) {
2125 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2126 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2127 TLI.getPointerTy(), Op2);
2128 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2129 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2130 TLI.getPointerTy(), Op2);
2133 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2134 Op1.getValueType(), Op1, Op2));
2137 void SelectionDAGLowering::visitICmp(User &I) {
2138 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2139 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2140 predicate = IC->getPredicate();
2141 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2142 predicate = ICmpInst::Predicate(IC->getPredicate());
2143 SDValue Op1 = getValue(I.getOperand(0));
2144 SDValue Op2 = getValue(I.getOperand(1));
2145 ISD::CondCode Opcode = getICmpCondCode(predicate);
2146 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2149 void SelectionDAGLowering::visitFCmp(User &I) {
2150 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2151 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2152 predicate = FC->getPredicate();
2153 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2154 predicate = FCmpInst::Predicate(FC->getPredicate());
2155 SDValue Op1 = getValue(I.getOperand(0));
2156 SDValue Op2 = getValue(I.getOperand(1));
2157 ISD::CondCode Condition = getFCmpCondCode(predicate);
2158 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2161 void SelectionDAGLowering::visitVICmp(User &I) {
2162 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2163 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2164 predicate = IC->getPredicate();
2165 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2166 predicate = ICmpInst::Predicate(IC->getPredicate());
2167 SDValue Op1 = getValue(I.getOperand(0));
2168 SDValue Op2 = getValue(I.getOperand(1));
2169 ISD::CondCode Opcode = getICmpCondCode(predicate);
2170 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2173 void SelectionDAGLowering::visitVFCmp(User &I) {
2174 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2175 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2176 predicate = FC->getPredicate();
2177 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2178 predicate = FCmpInst::Predicate(FC->getPredicate());
2179 SDValue Op1 = getValue(I.getOperand(0));
2180 SDValue Op2 = getValue(I.getOperand(1));
2181 ISD::CondCode Condition = getFCmpCondCode(predicate);
2182 MVT DestVT = TLI.getValueType(I.getType());
2184 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2187 void SelectionDAGLowering::visitSelect(User &I) {
2188 SmallVector<MVT, 4> ValueVTs;
2189 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2190 unsigned NumValues = ValueVTs.size();
2191 if (NumValues != 0) {
2192 SmallVector<SDValue, 4> Values(NumValues);
2193 SDValue Cond = getValue(I.getOperand(0));
2194 SDValue TrueVal = getValue(I.getOperand(1));
2195 SDValue FalseVal = getValue(I.getOperand(2));
2197 for (unsigned i = 0; i != NumValues; ++i)
2198 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2199 TrueVal.getValueType(), Cond,
2200 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2201 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2203 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2204 DAG.getVTList(&ValueVTs[0], NumValues),
2205 &Values[0], NumValues));
2210 void SelectionDAGLowering::visitTrunc(User &I) {
2211 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2212 SDValue N = getValue(I.getOperand(0));
2213 MVT DestVT = TLI.getValueType(I.getType());
2214 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2217 void SelectionDAGLowering::visitZExt(User &I) {
2218 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2219 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2220 SDValue N = getValue(I.getOperand(0));
2221 MVT DestVT = TLI.getValueType(I.getType());
2222 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2225 void SelectionDAGLowering::visitSExt(User &I) {
2226 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2227 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2228 SDValue N = getValue(I.getOperand(0));
2229 MVT DestVT = TLI.getValueType(I.getType());
2230 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2233 void SelectionDAGLowering::visitFPTrunc(User &I) {
2234 // FPTrunc is never a no-op cast, no need to check
2235 SDValue N = getValue(I.getOperand(0));
2236 MVT DestVT = TLI.getValueType(I.getType());
2237 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2238 DestVT, N, DAG.getIntPtrConstant(0)));
2241 void SelectionDAGLowering::visitFPExt(User &I){
2242 // FPTrunc is never a no-op cast, no need to check
2243 SDValue N = getValue(I.getOperand(0));
2244 MVT DestVT = TLI.getValueType(I.getType());
2245 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2248 void SelectionDAGLowering::visitFPToUI(User &I) {
2249 // FPToUI is never a no-op cast, no need to check
2250 SDValue N = getValue(I.getOperand(0));
2251 MVT DestVT = TLI.getValueType(I.getType());
2252 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2255 void SelectionDAGLowering::visitFPToSI(User &I) {
2256 // FPToSI is never a no-op cast, no need to check
2257 SDValue N = getValue(I.getOperand(0));
2258 MVT DestVT = TLI.getValueType(I.getType());
2259 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2262 void SelectionDAGLowering::visitUIToFP(User &I) {
2263 // UIToFP is never a no-op cast, no need to check
2264 SDValue N = getValue(I.getOperand(0));
2265 MVT DestVT = TLI.getValueType(I.getType());
2266 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2269 void SelectionDAGLowering::visitSIToFP(User &I){
2270 // SIToFP is never a no-op cast, no need to check
2271 SDValue N = getValue(I.getOperand(0));
2272 MVT DestVT = TLI.getValueType(I.getType());
2273 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2276 void SelectionDAGLowering::visitPtrToInt(User &I) {
2277 // What to do depends on the size of the integer and the size of the pointer.
2278 // We can either truncate, zero extend, or no-op, accordingly.
2279 SDValue N = getValue(I.getOperand(0));
2280 MVT SrcVT = N.getValueType();
2281 MVT DestVT = TLI.getValueType(I.getType());
2283 if (DestVT.bitsLT(SrcVT))
2284 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2286 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2287 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2288 setValue(&I, Result);
2291 void SelectionDAGLowering::visitIntToPtr(User &I) {
2292 // What to do depends on the size of the integer and the size of the pointer.
2293 // We can either truncate, zero extend, or no-op, accordingly.
2294 SDValue N = getValue(I.getOperand(0));
2295 MVT SrcVT = N.getValueType();
2296 MVT DestVT = TLI.getValueType(I.getType());
2297 if (DestVT.bitsLT(SrcVT))
2298 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2300 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2301 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2305 void SelectionDAGLowering::visitBitCast(User &I) {
2306 SDValue N = getValue(I.getOperand(0));
2307 MVT DestVT = TLI.getValueType(I.getType());
2309 // BitCast assures us that source and destination are the same size so this
2310 // is either a BIT_CONVERT or a no-op.
2311 if (DestVT != N.getValueType())
2312 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2313 DestVT, N)); // convert types
2315 setValue(&I, N); // noop cast.
2318 void SelectionDAGLowering::visitInsertElement(User &I) {
2319 SDValue InVec = getValue(I.getOperand(0));
2320 SDValue InVal = getValue(I.getOperand(1));
2321 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2323 getValue(I.getOperand(2)));
2325 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2326 TLI.getValueType(I.getType()),
2327 InVec, InVal, InIdx));
2330 void SelectionDAGLowering::visitExtractElement(User &I) {
2331 SDValue InVec = getValue(I.getOperand(0));
2332 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2334 getValue(I.getOperand(1)));
2335 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2336 TLI.getValueType(I.getType()), InVec, InIdx));
2340 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2341 // from SIndx and increasing to the element length (undefs are allowed).
2342 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2343 unsigned MaskNumElts = Mask.getNumOperands();
2344 for (unsigned i = 0; i != MaskNumElts; ++i) {
2345 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2346 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2347 if (Idx != i + SIndx)
2354 void SelectionDAGLowering::visitShuffleVector(User &I) {
2355 SDValue Src1 = getValue(I.getOperand(0));
2356 SDValue Src2 = getValue(I.getOperand(1));
2357 SDValue Mask = getValue(I.getOperand(2));
2359 MVT VT = TLI.getValueType(I.getType());
2360 MVT SrcVT = Src1.getValueType();
2361 int MaskNumElts = Mask.getNumOperands();
2362 int SrcNumElts = SrcVT.getVectorNumElements();
2364 if (SrcNumElts == MaskNumElts) {
2365 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2366 VT, Src1, Src2, Mask));
2370 // Normalize the shuffle vector since mask and vector length don't match.
2371 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2373 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2374 // Mask is longer than the source vectors and is a multiple of the source
2375 // vectors. We can use concatenate vector to make the mask and vectors
2377 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2378 // The shuffle is concatenating two vectors together.
2379 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2384 // Pad both vectors with undefs to make them the same length as the mask.
2385 unsigned NumConcat = MaskNumElts / SrcNumElts;
2386 SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
2388 SDValue* MOps1 = new SDValue[NumConcat];
2389 SDValue* MOps2 = new SDValue[NumConcat];
2392 for (unsigned i = 1; i != NumConcat; ++i) {
2393 MOps1[i] = UndefVal;
2394 MOps2[i] = UndefVal;
2396 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2397 VT, MOps1, NumConcat);
2398 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2399 VT, MOps2, NumConcat);
2404 // Readjust mask for new input vector length.
2405 SmallVector<SDValue, 8> MappedOps;
2406 for (int i = 0; i != MaskNumElts; ++i) {
2407 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2408 MappedOps.push_back(Mask.getOperand(i));
2410 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2411 if (Idx < SrcNumElts)
2412 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2414 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2418 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2419 Mask.getValueType(),
2420 &MappedOps[0], MappedOps.size());
2422 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2423 VT, Src1, Src2, Mask));
2427 if (SrcNumElts > MaskNumElts) {
2428 // Resulting vector is shorter than the incoming vector.
2429 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2430 // Shuffle extracts 1st vector.
2435 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2436 // Shuffle extracts 2nd vector.
2441 // Analyze the access pattern of the vector to see if we can extract
2442 // two subvectors and do the shuffle. The analysis is done by calculating
2443 // the range of elements the mask access on both vectors.
2444 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2445 int MaxRange[2] = {-1, -1};
2447 for (int i = 0; i != MaskNumElts; ++i) {
2448 SDValue Arg = Mask.getOperand(i);
2449 if (Arg.getOpcode() != ISD::UNDEF) {
2450 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2451 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2453 if (Idx >= SrcNumElts) {
2457 if (Idx > MaxRange[Input])
2458 MaxRange[Input] = Idx;
2459 if (Idx < MinRange[Input])
2460 MinRange[Input] = Idx;
2464 // Check if the access is smaller than the vector size and can we find
2465 // a reasonable extract index.
2466 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2467 int StartIdx[2]; // StartIdx to extract from
2468 for (int Input=0; Input < 2; ++Input) {
2469 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2470 RangeUse[Input] = 0; // Unused
2471 StartIdx[Input] = 0;
2472 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2473 // Fits within range but we should see if we can find a good
2474 // start index that is a multiple of the mask length.
2475 if (MaxRange[Input] < MaskNumElts) {
2476 RangeUse[Input] = 1; // Extract from beginning of the vector
2477 StartIdx[Input] = 0;
2479 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2480 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2481 StartIdx[Input] + MaskNumElts < SrcNumElts)
2482 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2487 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2488 setValue(&I, DAG.getNode(ISD::UNDEF,
2489 getCurDebugLoc(), VT)); // Vectors are not used.
2492 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2493 // Extract appropriate subvector and generate a vector shuffle
2494 for (int Input=0; Input < 2; ++Input) {
2495 SDValue& Src = Input == 0 ? Src1 : Src2;
2496 if (RangeUse[Input] == 0) {
2497 Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
2499 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2500 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2503 // Calculate new mask.
2504 SmallVector<SDValue, 8> MappedOps;
2505 for (int i = 0; i != MaskNumElts; ++i) {
2506 SDValue Arg = Mask.getOperand(i);
2507 if (Arg.getOpcode() == ISD::UNDEF) {
2508 MappedOps.push_back(Arg);
2510 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2511 if (Idx < SrcNumElts)
2512 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2514 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2515 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2519 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2520 Mask.getValueType(),
2521 &MappedOps[0], MappedOps.size());
2522 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2523 VT, Src1, Src2, Mask));
2528 // We can't use either concat vectors or extract subvectors so fall back to
2529 // replacing the shuffle with extract and build vector.
2530 // to insert and build vector.
2531 MVT EltVT = VT.getVectorElementType();
2532 MVT PtrVT = TLI.getPointerTy();
2533 SmallVector<SDValue,8> Ops;
2534 for (int i = 0; i != MaskNumElts; ++i) {
2535 SDValue Arg = Mask.getOperand(i);
2536 if (Arg.getOpcode() == ISD::UNDEF) {
2537 Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
2539 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2540 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2541 if (Idx < SrcNumElts)
2542 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2543 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2545 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2547 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2550 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2551 VT, &Ops[0], Ops.size()));
2554 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2555 const Value *Op0 = I.getOperand(0);
2556 const Value *Op1 = I.getOperand(1);
2557 const Type *AggTy = I.getType();
2558 const Type *ValTy = Op1->getType();
2559 bool IntoUndef = isa<UndefValue>(Op0);
2560 bool FromUndef = isa<UndefValue>(Op1);
2562 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2563 I.idx_begin(), I.idx_end());
2565 SmallVector<MVT, 4> AggValueVTs;
2566 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2567 SmallVector<MVT, 4> ValValueVTs;
2568 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2570 unsigned NumAggValues = AggValueVTs.size();
2571 unsigned NumValValues = ValValueVTs.size();
2572 SmallVector<SDValue, 4> Values(NumAggValues);
2574 SDValue Agg = getValue(Op0);
2575 SDValue Val = getValue(Op1);
2577 // Copy the beginning value(s) from the original aggregate.
2578 for (; i != LinearIndex; ++i)
2579 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2581 SDValue(Agg.getNode(), Agg.getResNo() + i);
2582 // Copy values from the inserted value(s).
2583 for (; i != LinearIndex + NumValValues; ++i)
2584 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2586 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2587 // Copy remaining value(s) from the original aggregate.
2588 for (; i != NumAggValues; ++i)
2589 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2591 SDValue(Agg.getNode(), Agg.getResNo() + i);
2593 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2594 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2595 &Values[0], NumAggValues));
2598 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2599 const Value *Op0 = I.getOperand(0);
2600 const Type *AggTy = Op0->getType();
2601 const Type *ValTy = I.getType();
2602 bool OutOfUndef = isa<UndefValue>(Op0);
2604 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2605 I.idx_begin(), I.idx_end());
2607 SmallVector<MVT, 4> ValValueVTs;
2608 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2610 unsigned NumValValues = ValValueVTs.size();
2611 SmallVector<SDValue, 4> Values(NumValValues);
2613 SDValue Agg = getValue(Op0);
2614 // Copy out the selected value(s).
2615 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2616 Values[i - LinearIndex] =
2618 DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2619 Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2620 SDValue(Agg.getNode(), Agg.getResNo() + i);
2622 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2623 DAG.getVTList(&ValValueVTs[0], NumValValues),
2624 &Values[0], NumValValues));
2628 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2629 SDValue N = getValue(I.getOperand(0));
2630 const Type *Ty = I.getOperand(0)->getType();
2632 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2635 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2636 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2639 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2640 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2641 DAG.getIntPtrConstant(Offset));
2643 Ty = StTy->getElementType(Field);
2645 Ty = cast<SequentialType>(Ty)->getElementType();
2647 // If this is a constant subscript, handle it quickly.
2648 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2649 if (CI->getZExtValue() == 0) continue;
2651 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2652 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2653 DAG.getIntPtrConstant(Offs));
2657 // N = N + Idx * ElementSize;
2658 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2659 SDValue IdxN = getValue(Idx);
2661 // If the index is smaller or larger than intptr_t, truncate or extend
2663 if (IdxN.getValueType().bitsLT(N.getValueType()))
2664 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2665 N.getValueType(), IdxN);
2666 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2667 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2668 N.getValueType(), IdxN);
2670 // If this is a multiply by a power of two, turn it into a shl
2671 // immediately. This is a very common case.
2672 if (ElementSize != 1) {
2673 if (isPowerOf2_64(ElementSize)) {
2674 unsigned Amt = Log2_64(ElementSize);
2675 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2676 N.getValueType(), IdxN,
2677 DAG.getConstant(Amt, TLI.getPointerTy()));
2679 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2680 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2681 N.getValueType(), IdxN, Scale);
2685 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2686 N.getValueType(), N, IdxN);
2692 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2693 // If this is a fixed sized alloca in the entry block of the function,
2694 // allocate it statically on the stack.
2695 if (FuncInfo.StaticAllocaMap.count(&I))
2696 return; // getValue will auto-populate this.
2698 const Type *Ty = I.getAllocatedType();
2699 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2701 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2704 SDValue AllocSize = getValue(I.getArraySize());
2705 MVT IntPtr = TLI.getPointerTy();
2706 if (IntPtr.bitsLT(AllocSize.getValueType()))
2707 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2709 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2710 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2713 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
2714 DAG.getIntPtrConstant(TySize));
2716 // Handle alignment. If the requested alignment is less than or equal to
2717 // the stack alignment, ignore it. If the size is greater than or equal to
2718 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2719 unsigned StackAlign =
2720 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2721 if (Align <= StackAlign)
2724 // Round the size of the allocation up to the stack alignment size
2725 // by add SA-1 to the size.
2726 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2727 AllocSize.getValueType(), AllocSize,
2728 DAG.getIntPtrConstant(StackAlign-1));
2729 // Mask out the low bits for alignment purposes.
2730 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2731 AllocSize.getValueType(), AllocSize,
2732 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2734 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2735 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2737 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2740 DAG.setRoot(DSA.getValue(1));
2742 // Inform the Frame Information that we have just allocated a variable-sized
2744 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2747 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2748 const Value *SV = I.getOperand(0);
2749 SDValue Ptr = getValue(SV);
2751 const Type *Ty = I.getType();
2752 bool isVolatile = I.isVolatile();
2753 unsigned Alignment = I.getAlignment();
2755 SmallVector<MVT, 4> ValueVTs;
2756 SmallVector<uint64_t, 4> Offsets;
2757 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2758 unsigned NumValues = ValueVTs.size();
2763 bool ConstantMemory = false;
2765 // Serialize volatile loads with other side effects.
2767 else if (AA->pointsToConstantMemory(SV)) {
2768 // Do not serialize (non-volatile) loads of constant memory with anything.
2769 Root = DAG.getEntryNode();
2770 ConstantMemory = true;
2772 // Do not serialize non-volatile loads against each other.
2773 Root = DAG.getRoot();
2776 SmallVector<SDValue, 4> Values(NumValues);
2777 SmallVector<SDValue, 4> Chains(NumValues);
2778 MVT PtrVT = Ptr.getValueType();
2779 for (unsigned i = 0; i != NumValues; ++i) {
2780 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2781 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2783 DAG.getConstant(Offsets[i], PtrVT)),
2785 isVolatile, Alignment);
2787 Chains[i] = L.getValue(1);
2790 if (!ConstantMemory) {
2791 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2793 &Chains[0], NumValues);
2797 PendingLoads.push_back(Chain);
2800 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2801 DAG.getVTList(&ValueVTs[0], NumValues),
2802 &Values[0], NumValues));
2806 void SelectionDAGLowering::visitStore(StoreInst &I) {
2807 Value *SrcV = I.getOperand(0);
2808 Value *PtrV = I.getOperand(1);
2810 SmallVector<MVT, 4> ValueVTs;
2811 SmallVector<uint64_t, 4> Offsets;
2812 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2813 unsigned NumValues = ValueVTs.size();
2817 // Get the lowered operands. Note that we do this after
2818 // checking if NumResults is zero, because with zero results
2819 // the operands won't have values in the map.
2820 SDValue Src = getValue(SrcV);
2821 SDValue Ptr = getValue(PtrV);
2823 SDValue Root = getRoot();
2824 SmallVector<SDValue, 4> Chains(NumValues);
2825 MVT PtrVT = Ptr.getValueType();
2826 bool isVolatile = I.isVolatile();
2827 unsigned Alignment = I.getAlignment();
2828 for (unsigned i = 0; i != NumValues; ++i)
2829 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2830 SDValue(Src.getNode(), Src.getResNo() + i),
2831 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2833 DAG.getConstant(Offsets[i], PtrVT)),
2835 isVolatile, Alignment);
2837 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2838 MVT::Other, &Chains[0], NumValues));
2841 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2843 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2844 unsigned Intrinsic) {
2845 bool HasChain = !I.doesNotAccessMemory();
2846 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2848 // Build the operand list.
2849 SmallVector<SDValue, 8> Ops;
2850 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2852 // We don't need to serialize loads against other loads.
2853 Ops.push_back(DAG.getRoot());
2855 Ops.push_back(getRoot());
2859 // Info is set by getTgtMemInstrinsic
2860 TargetLowering::IntrinsicInfo Info;
2861 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2863 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2864 if (!IsTgtIntrinsic)
2865 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2867 // Add all operands of the call to the operand list.
2868 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2869 SDValue Op = getValue(I.getOperand(i));
2870 assert(TLI.isTypeLegal(Op.getValueType()) &&
2871 "Intrinsic uses a non-legal type?");
2875 std::vector<MVT> VTs;
2876 if (I.getType() != Type::VoidTy) {
2877 MVT VT = TLI.getValueType(I.getType());
2878 if (VT.isVector()) {
2879 const VectorType *DestTy = cast<VectorType>(I.getType());
2880 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2882 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2883 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2886 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2890 VTs.push_back(MVT::Other);
2892 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2896 if (IsTgtIntrinsic) {
2897 // This is target intrinsic that touches memory
2898 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2900 &Ops[0], Ops.size(),
2901 Info.memVT, Info.ptrVal, Info.offset,
2902 Info.align, Info.vol,
2903 Info.readMem, Info.writeMem);
2906 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2908 &Ops[0], Ops.size());
2909 else if (I.getType() != Type::VoidTy)
2910 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2912 &Ops[0], Ops.size());
2914 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2916 &Ops[0], Ops.size());
2919 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2921 PendingLoads.push_back(Chain);
2925 if (I.getType() != Type::VoidTy) {
2926 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2927 MVT VT = TLI.getValueType(PTy);
2928 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2930 setValue(&I, Result);
2934 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2935 static GlobalVariable *ExtractTypeInfo(Value *V) {
2936 V = V->stripPointerCasts();
2937 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2938 assert ((GV || isa<ConstantPointerNull>(V)) &&
2939 "TypeInfo must be a global variable or NULL");
2945 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2946 /// call, and add them to the specified machine basic block.
2947 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2948 MachineBasicBlock *MBB) {
2949 // Inform the MachineModuleInfo of the personality for this landing pad.
2950 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2951 assert(CE->getOpcode() == Instruction::BitCast &&
2952 isa<Function>(CE->getOperand(0)) &&
2953 "Personality should be a function");
2954 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2956 // Gather all the type infos for this landing pad and pass them along to
2957 // MachineModuleInfo.
2958 std::vector<GlobalVariable *> TyInfo;
2959 unsigned N = I.getNumOperands();
2961 for (unsigned i = N - 1; i > 2; --i) {
2962 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2963 unsigned FilterLength = CI->getZExtValue();
2964 unsigned FirstCatch = i + FilterLength + !FilterLength;
2965 assert (FirstCatch <= N && "Invalid filter length");
2967 if (FirstCatch < N) {
2968 TyInfo.reserve(N - FirstCatch);
2969 for (unsigned j = FirstCatch; j < N; ++j)
2970 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2971 MMI->addCatchTypeInfo(MBB, TyInfo);
2975 if (!FilterLength) {
2977 MMI->addCleanup(MBB);
2980 TyInfo.reserve(FilterLength - 1);
2981 for (unsigned j = i + 1; j < FirstCatch; ++j)
2982 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2983 MMI->addFilterTypeInfo(MBB, TyInfo);
2992 TyInfo.reserve(N - 3);
2993 for (unsigned j = 3; j < N; ++j)
2994 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2995 MMI->addCatchTypeInfo(MBB, TyInfo);
3001 /// GetSignificand - Get the significand and build it into a floating-point
3002 /// number with exponent of 1:
3004 /// Op = (Op & 0x007fffff) | 0x3f800000;
3006 /// where Op is the hexidecimal representation of floating point value.
3008 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3009 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3010 DAG.getConstant(0x007fffff, MVT::i32));
3011 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3012 DAG.getConstant(0x3f800000, MVT::i32));
3013 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3016 /// GetExponent - Get the exponent:
3018 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3020 /// where Op is the hexidecimal representation of floating point value.
3022 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3024 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3025 DAG.getConstant(0x7f800000, MVT::i32));
3026 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3027 DAG.getConstant(23, TLI.getPointerTy()));
3028 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3029 DAG.getConstant(127, MVT::i32));
3030 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3033 /// getF32Constant - Get 32-bit floating point constant.
3035 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3036 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3039 /// Inlined utility function to implement binary input atomic intrinsics for
3040 /// visitIntrinsicCall: I is a call instruction
3041 /// Op is the associated NodeType for I
3043 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3044 SDValue Root = getRoot();
3046 DAG.getAtomic(Op, getCurDebugLoc(),
3047 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3049 getValue(I.getOperand(1)),
3050 getValue(I.getOperand(2)),
3053 DAG.setRoot(L.getValue(1));
3057 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3059 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3060 SDValue Op1 = getValue(I.getOperand(1));
3061 SDValue Op2 = getValue(I.getOperand(2));
3063 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3064 SDValue Ops[] = { Op1, Op2 };
3066 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
3067 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
3069 setValue(&I, Result);
3073 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3074 /// limited-precision mode.
3076 SelectionDAGLowering::visitExp(CallInst &I) {
3078 DebugLoc dl = getCurDebugLoc();
3080 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3081 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3082 SDValue Op = getValue(I.getOperand(1));
3084 // Put the exponent in the right bit position for later addition to the
3087 // #define LOG2OFe 1.4426950f
3088 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3089 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3090 getF32Constant(DAG, 0x3fb8aa3b));
3091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3093 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3097 // IntegerPartOfX <<= 23;
3098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3099 DAG.getConstant(23, TLI.getPointerTy()));
3101 if (LimitFloatPrecision <= 6) {
3102 // For floating-point precision of 6:
3104 // TwoToFractionalPartOfX =
3106 // (0.735607626f + 0.252464424f * x) * x;
3108 // error 0.0144103317, which is 6 bits
3109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3110 getF32Constant(DAG, 0x3e814304));
3111 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3112 getF32Constant(DAG, 0x3f3c50c8));
3113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3114 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3115 getF32Constant(DAG, 0x3f7f5e7e));
3116 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3118 // Add the exponent into the result in integer domain.
3119 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3120 TwoToFracPartOfX, IntegerPartOfX);
3122 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3123 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3124 // For floating-point precision of 12:
3126 // TwoToFractionalPartOfX =
3129 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3131 // 0.000107046256 error, which is 13 to 14 bits
3132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3133 getF32Constant(DAG, 0x3da235e3));
3134 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3135 getF32Constant(DAG, 0x3e65b8f3));
3136 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3137 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3138 getF32Constant(DAG, 0x3f324b07));
3139 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3140 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3141 getF32Constant(DAG, 0x3f7ff8fd));
3142 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3144 // Add the exponent into the result in integer domain.
3145 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3146 TwoToFracPartOfX, IntegerPartOfX);
3148 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3149 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3150 // For floating-point precision of 18:
3152 // TwoToFractionalPartOfX =
3156 // (0.554906021e-1f +
3157 // (0.961591928e-2f +
3158 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3160 // error 2.47208000*10^(-7), which is better than 18 bits
3161 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3162 getF32Constant(DAG, 0x3924b03e));
3163 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3164 getF32Constant(DAG, 0x3ab24b87));
3165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3167 getF32Constant(DAG, 0x3c1d8c17));
3168 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3169 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3170 getF32Constant(DAG, 0x3d634a1d));
3171 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3172 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3173 getF32Constant(DAG, 0x3e75fe14));
3174 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3175 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3176 getF32Constant(DAG, 0x3f317234));
3177 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3178 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3179 getF32Constant(DAG, 0x3f800000));
3180 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3183 // Add the exponent into the result in integer domain.
3184 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3185 TwoToFracPartOfX, IntegerPartOfX);
3187 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3190 // No special expansion.
3191 result = DAG.getNode(ISD::FEXP, dl,
3192 getValue(I.getOperand(1)).getValueType(),
3193 getValue(I.getOperand(1)));
3196 setValue(&I, result);
3199 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3200 /// limited-precision mode.
3202 SelectionDAGLowering::visitLog(CallInst &I) {
3204 DebugLoc dl = getCurDebugLoc();
3206 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3207 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3208 SDValue Op = getValue(I.getOperand(1));
3209 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3211 // Scale the exponent by log(2) [0.69314718f].
3212 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3213 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3214 getF32Constant(DAG, 0x3f317218));
3216 // Get the significand and build it into a floating-point number with
3218 SDValue X = GetSignificand(DAG, Op1, dl);
3220 if (LimitFloatPrecision <= 6) {
3221 // For floating-point precision of 6:
3225 // (1.4034025f - 0.23903021f * x) * x;
3227 // error 0.0034276066, which is better than 8 bits
3228 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3229 getF32Constant(DAG, 0xbe74c456));
3230 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3231 getF32Constant(DAG, 0x3fb3a2b1));
3232 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3233 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3234 getF32Constant(DAG, 0x3f949a29));
3236 result = DAG.getNode(ISD::FADD, dl,
3237 MVT::f32, LogOfExponent, LogOfMantissa);
3238 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3239 // For floating-point precision of 12:
3245 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3247 // error 0.000061011436, which is 14 bits
3248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3249 getF32Constant(DAG, 0xbd67b6d6));
3250 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3251 getF32Constant(DAG, 0x3ee4f4b8));
3252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3253 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3254 getF32Constant(DAG, 0x3fbc278b));
3255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3257 getF32Constant(DAG, 0x40348e95));
3258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3259 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3260 getF32Constant(DAG, 0x3fdef31a));
3262 result = DAG.getNode(ISD::FADD, dl,
3263 MVT::f32, LogOfExponent, LogOfMantissa);
3264 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3265 // For floating-point precision of 18:
3273 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3275 // error 0.0000023660568, which is better than 18 bits
3276 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3277 getF32Constant(DAG, 0xbc91e5ac));
3278 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3279 getF32Constant(DAG, 0x3e4350aa));
3280 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3281 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3282 getF32Constant(DAG, 0x3f60d3e3));
3283 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3284 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3285 getF32Constant(DAG, 0x4011cdf0));
3286 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3287 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3288 getF32Constant(DAG, 0x406cfd1c));
3289 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3290 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3291 getF32Constant(DAG, 0x408797cb));
3292 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3293 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3294 getF32Constant(DAG, 0x4006dcab));
3296 result = DAG.getNode(ISD::FADD, dl,
3297 MVT::f32, LogOfExponent, LogOfMantissa);
3300 // No special expansion.
3301 result = DAG.getNode(ISD::FLOG, dl,
3302 getValue(I.getOperand(1)).getValueType(),
3303 getValue(I.getOperand(1)));
3306 setValue(&I, result);
3309 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3310 /// limited-precision mode.
3312 SelectionDAGLowering::visitLog2(CallInst &I) {
3314 DebugLoc dl = getCurDebugLoc();
3316 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3317 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3318 SDValue Op = getValue(I.getOperand(1));
3319 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3321 // Get the exponent.
3322 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3324 // Get the significand and build it into a floating-point number with
3326 SDValue X = GetSignificand(DAG, Op1, dl);
3328 // Different possible minimax approximations of significand in
3329 // floating-point for various degrees of accuracy over [1,2].
3330 if (LimitFloatPrecision <= 6) {
3331 // For floating-point precision of 6:
3333 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3335 // error 0.0049451742, which is more than 7 bits
3336 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3337 getF32Constant(DAG, 0xbeb08fe0));
3338 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3339 getF32Constant(DAG, 0x40019463));
3340 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3341 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3342 getF32Constant(DAG, 0x3fd6633d));
3344 result = DAG.getNode(ISD::FADD, dl,
3345 MVT::f32, LogOfExponent, Log2ofMantissa);
3346 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3347 // For floating-point precision of 12:
3353 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3355 // error 0.0000876136000, which is better than 13 bits
3356 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3357 getF32Constant(DAG, 0xbda7262e));
3358 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3359 getF32Constant(DAG, 0x3f25280b));
3360 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3361 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3362 getF32Constant(DAG, 0x4007b923));
3363 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3364 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3365 getF32Constant(DAG, 0x40823e2f));
3366 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3367 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3368 getF32Constant(DAG, 0x4020d29c));
3370 result = DAG.getNode(ISD::FADD, dl,
3371 MVT::f32, LogOfExponent, Log2ofMantissa);
3372 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3373 // For floating-point precision of 18:
3382 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3384 // error 0.0000018516, which is better than 18 bits
3385 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3386 getF32Constant(DAG, 0xbcd2769e));
3387 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3388 getF32Constant(DAG, 0x3e8ce0b9));
3389 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3390 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3391 getF32Constant(DAG, 0x3fa22ae7));
3392 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3393 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3394 getF32Constant(DAG, 0x40525723));
3395 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3396 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3397 getF32Constant(DAG, 0x40aaf200));
3398 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3399 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3400 getF32Constant(DAG, 0x40c39dad));
3401 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3402 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3403 getF32Constant(DAG, 0x4042902c));
3405 result = DAG.getNode(ISD::FADD, dl,
3406 MVT::f32, LogOfExponent, Log2ofMantissa);
3409 // No special expansion.
3410 result = DAG.getNode(ISD::FLOG2, dl,
3411 getValue(I.getOperand(1)).getValueType(),
3412 getValue(I.getOperand(1)));
3415 setValue(&I, result);
3418 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3419 /// limited-precision mode.
3421 SelectionDAGLowering::visitLog10(CallInst &I) {
3423 DebugLoc dl = getCurDebugLoc();
3425 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3426 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3427 SDValue Op = getValue(I.getOperand(1));
3428 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3430 // Scale the exponent by log10(2) [0.30102999f].
3431 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3432 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3433 getF32Constant(DAG, 0x3e9a209a));
3435 // Get the significand and build it into a floating-point number with
3437 SDValue X = GetSignificand(DAG, Op1, dl);
3439 if (LimitFloatPrecision <= 6) {
3440 // For floating-point precision of 6:
3442 // Log10ofMantissa =
3444 // (0.60948995f - 0.10380950f * x) * x;
3446 // error 0.0014886165, which is 6 bits
3447 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3448 getF32Constant(DAG, 0xbdd49a13));
3449 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3450 getF32Constant(DAG, 0x3f1c0789));
3451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3452 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3453 getF32Constant(DAG, 0x3f011300));
3455 result = DAG.getNode(ISD::FADD, dl,
3456 MVT::f32, LogOfExponent, Log10ofMantissa);
3457 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3458 // For floating-point precision of 12:
3460 // Log10ofMantissa =
3463 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3465 // error 0.00019228036, which is better than 12 bits
3466 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3467 getF32Constant(DAG, 0x3d431f31));
3468 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3469 getF32Constant(DAG, 0x3ea21fb2));
3470 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3471 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3472 getF32Constant(DAG, 0x3f6ae232));
3473 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3474 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3475 getF32Constant(DAG, 0x3f25f7c3));
3477 result = DAG.getNode(ISD::FADD, dl,
3478 MVT::f32, LogOfExponent, Log10ofMantissa);
3479 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3480 // For floating-point precision of 18:
3482 // Log10ofMantissa =
3487 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3489 // error 0.0000037995730, which is better than 18 bits
3490 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3491 getF32Constant(DAG, 0x3c5d51ce));
3492 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3493 getF32Constant(DAG, 0x3e00685a));
3494 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3495 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3496 getF32Constant(DAG, 0x3efb6798));
3497 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3498 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3499 getF32Constant(DAG, 0x3f88d192));
3500 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3501 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3502 getF32Constant(DAG, 0x3fc4316c));
3503 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3504 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3505 getF32Constant(DAG, 0x3f57ce70));
3507 result = DAG.getNode(ISD::FADD, dl,
3508 MVT::f32, LogOfExponent, Log10ofMantissa);
3511 // No special expansion.
3512 result = DAG.getNode(ISD::FLOG10, dl,
3513 getValue(I.getOperand(1)).getValueType(),
3514 getValue(I.getOperand(1)));
3517 setValue(&I, result);
3520 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3521 /// limited-precision mode.
3523 SelectionDAGLowering::visitExp2(CallInst &I) {
3525 DebugLoc dl = getCurDebugLoc();
3527 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3528 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3529 SDValue Op = getValue(I.getOperand(1));
3531 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3533 // FractionalPartOfX = x - (float)IntegerPartOfX;
3534 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3535 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3537 // IntegerPartOfX <<= 23;
3538 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3539 DAG.getConstant(23, TLI.getPointerTy()));
3541 if (LimitFloatPrecision <= 6) {
3542 // For floating-point precision of 6:
3544 // TwoToFractionalPartOfX =
3546 // (0.735607626f + 0.252464424f * x) * x;
3548 // error 0.0144103317, which is 6 bits
3549 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3550 getF32Constant(DAG, 0x3e814304));
3551 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3552 getF32Constant(DAG, 0x3f3c50c8));
3553 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3554 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3555 getF32Constant(DAG, 0x3f7f5e7e));
3556 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3557 SDValue TwoToFractionalPartOfX =
3558 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3560 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3561 MVT::f32, TwoToFractionalPartOfX);
3562 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3563 // For floating-point precision of 12:
3565 // TwoToFractionalPartOfX =
3568 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3570 // error 0.000107046256, which is 13 to 14 bits
3571 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3572 getF32Constant(DAG, 0x3da235e3));
3573 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3574 getF32Constant(DAG, 0x3e65b8f3));
3575 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3576 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3577 getF32Constant(DAG, 0x3f324b07));
3578 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3579 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3580 getF32Constant(DAG, 0x3f7ff8fd));
3581 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3582 SDValue TwoToFractionalPartOfX =
3583 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3585 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3586 MVT::f32, TwoToFractionalPartOfX);
3587 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3588 // For floating-point precision of 18:
3590 // TwoToFractionalPartOfX =
3594 // (0.554906021e-1f +
3595 // (0.961591928e-2f +
3596 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3597 // error 2.47208000*10^(-7), which is better than 18 bits
3598 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3599 getF32Constant(DAG, 0x3924b03e));
3600 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3601 getF32Constant(DAG, 0x3ab24b87));
3602 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3603 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3604 getF32Constant(DAG, 0x3c1d8c17));
3605 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3606 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3607 getF32Constant(DAG, 0x3d634a1d));
3608 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3609 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3610 getF32Constant(DAG, 0x3e75fe14));
3611 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3612 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3613 getF32Constant(DAG, 0x3f317234));
3614 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3615 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3616 getF32Constant(DAG, 0x3f800000));
3617 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3618 SDValue TwoToFractionalPartOfX =
3619 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3621 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3622 MVT::f32, TwoToFractionalPartOfX);
3625 // No special expansion.
3626 result = DAG.getNode(ISD::FEXP2, dl,
3627 getValue(I.getOperand(1)).getValueType(),
3628 getValue(I.getOperand(1)));
3631 setValue(&I, result);
3634 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3635 /// limited-precision mode with x == 10.0f.
3637 SelectionDAGLowering::visitPow(CallInst &I) {
3639 Value *Val = I.getOperand(1);
3640 DebugLoc dl = getCurDebugLoc();
3641 bool IsExp10 = false;
3643 if (getValue(Val).getValueType() == MVT::f32 &&
3644 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3645 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3646 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3647 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3649 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3654 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3655 SDValue Op = getValue(I.getOperand(2));
3657 // Put the exponent in the right bit position for later addition to the
3660 // #define LOG2OF10 3.3219281f
3661 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3662 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3663 getF32Constant(DAG, 0x40549a78));
3664 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3666 // FractionalPartOfX = x - (float)IntegerPartOfX;
3667 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3668 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3670 // IntegerPartOfX <<= 23;
3671 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3672 DAG.getConstant(23, TLI.getPointerTy()));
3674 if (LimitFloatPrecision <= 6) {
3675 // For floating-point precision of 6:
3677 // twoToFractionalPartOfX =
3679 // (0.735607626f + 0.252464424f * x) * x;
3681 // error 0.0144103317, which is 6 bits
3682 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3683 getF32Constant(DAG, 0x3e814304));
3684 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3685 getF32Constant(DAG, 0x3f3c50c8));
3686 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3687 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3688 getF32Constant(DAG, 0x3f7f5e7e));
3689 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3690 SDValue TwoToFractionalPartOfX =
3691 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3693 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3694 MVT::f32, TwoToFractionalPartOfX);
3695 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3696 // For floating-point precision of 12:
3698 // TwoToFractionalPartOfX =
3701 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3703 // error 0.000107046256, which is 13 to 14 bits
3704 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3705 getF32Constant(DAG, 0x3da235e3));
3706 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3707 getF32Constant(DAG, 0x3e65b8f3));
3708 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3709 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3710 getF32Constant(DAG, 0x3f324b07));
3711 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3712 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3713 getF32Constant(DAG, 0x3f7ff8fd));
3714 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3715 SDValue TwoToFractionalPartOfX =
3716 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3718 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3719 MVT::f32, TwoToFractionalPartOfX);
3720 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3721 // For floating-point precision of 18:
3723 // TwoToFractionalPartOfX =
3727 // (0.554906021e-1f +
3728 // (0.961591928e-2f +
3729 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3730 // error 2.47208000*10^(-7), which is better than 18 bits
3731 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3732 getF32Constant(DAG, 0x3924b03e));
3733 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3734 getF32Constant(DAG, 0x3ab24b87));
3735 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3736 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3737 getF32Constant(DAG, 0x3c1d8c17));
3738 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3739 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3740 getF32Constant(DAG, 0x3d634a1d));
3741 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3742 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3743 getF32Constant(DAG, 0x3e75fe14));
3744 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3745 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3746 getF32Constant(DAG, 0x3f317234));
3747 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3748 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3749 getF32Constant(DAG, 0x3f800000));
3750 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3751 SDValue TwoToFractionalPartOfX =
3752 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3754 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3755 MVT::f32, TwoToFractionalPartOfX);
3758 // No special expansion.
3759 result = DAG.getNode(ISD::FPOW, dl,
3760 getValue(I.getOperand(1)).getValueType(),
3761 getValue(I.getOperand(1)),
3762 getValue(I.getOperand(2)));
3765 setValue(&I, result);
3768 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3769 /// we want to emit this as a call to a named external function, return the name
3770 /// otherwise lower it and return null.
3772 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3773 DebugLoc dl = getCurDebugLoc();
3774 switch (Intrinsic) {
3776 // By default, turn this into a target intrinsic node.
3777 visitTargetIntrinsic(I, Intrinsic);
3779 case Intrinsic::vastart: visitVAStart(I); return 0;
3780 case Intrinsic::vaend: visitVAEnd(I); return 0;
3781 case Intrinsic::vacopy: visitVACopy(I); return 0;
3782 case Intrinsic::returnaddress:
3783 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3784 getValue(I.getOperand(1))));
3786 case Intrinsic::frameaddress:
3787 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3788 getValue(I.getOperand(1))));
3790 case Intrinsic::setjmp:
3791 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3793 case Intrinsic::longjmp:
3794 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3796 case Intrinsic::memcpy: {
3797 SDValue Op1 = getValue(I.getOperand(1));
3798 SDValue Op2 = getValue(I.getOperand(2));
3799 SDValue Op3 = getValue(I.getOperand(3));
3800 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3801 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3802 I.getOperand(1), 0, I.getOperand(2), 0));
3805 case Intrinsic::memset: {
3806 SDValue Op1 = getValue(I.getOperand(1));
3807 SDValue Op2 = getValue(I.getOperand(2));
3808 SDValue Op3 = getValue(I.getOperand(3));
3809 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3810 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3811 I.getOperand(1), 0));
3814 case Intrinsic::memmove: {
3815 SDValue Op1 = getValue(I.getOperand(1));
3816 SDValue Op2 = getValue(I.getOperand(2));
3817 SDValue Op3 = getValue(I.getOperand(3));
3818 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3820 // If the source and destination are known to not be aliases, we can
3821 // lower memmove as memcpy.
3822 uint64_t Size = -1ULL;
3823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3824 Size = C->getZExtValue();
3825 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3826 AliasAnalysis::NoAlias) {
3827 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3828 I.getOperand(1), 0, I.getOperand(2), 0));
3832 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3833 I.getOperand(1), 0, I.getOperand(2), 0));
3836 case Intrinsic::dbg_stoppoint: {
3837 DwarfWriter *DW = DAG.getDwarfWriter();
3838 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3839 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
3840 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3844 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3845 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3846 unsigned idx = DAG.getMachineFunction().
3847 getOrCreateDebugLocID(SrcFile,
3850 setCurDebugLoc(DebugLoc::get(idx));
3854 case Intrinsic::dbg_region_start: {
3855 DwarfWriter *DW = DAG.getDwarfWriter();
3856 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3857 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
3859 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3860 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3865 case Intrinsic::dbg_region_end: {
3866 DwarfWriter *DW = DAG.getDwarfWriter();
3867 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3868 if (DW && DW->ValidDebugInfo(REI.getContext())) {
3870 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3871 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3876 case Intrinsic::dbg_func_start: {
3877 DwarfWriter *DW = DAG.getDwarfWriter();
3879 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3880 Value *SP = FSI.getSubprogram();
3881 if (SP && DW->ValidDebugInfo(SP)) {
3882 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3883 // what (most?) gdb expects.
3884 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3885 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3886 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3887 CompileUnit.getFilename());
3889 // Record the source line but does not create a label for the normal
3890 // function start. It will be emitted at asm emission time. However,
3891 // create a label if this is a beginning of inlined function.
3892 unsigned Line = Subprogram.getLineNumber();
3893 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3895 if (DW->getRecordSourceLineCount() != 1)
3896 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3898 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
3899 getOrCreateDebugLocID(SrcFile, Line, 0)));
3904 case Intrinsic::dbg_declare: {
3905 DwarfWriter *DW = DAG.getDwarfWriter();
3906 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3907 Value *Variable = DI.getVariable();
3908 if (DW && DW->ValidDebugInfo(Variable))
3909 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3910 getValue(DI.getAddress()), getValue(Variable)));
3914 case Intrinsic::eh_exception: {
3915 if (!CurMBB->isLandingPad()) {
3916 // FIXME: Mark exception register as live in. Hack for PR1508.
3917 unsigned Reg = TLI.getExceptionAddressRegister();
3918 if (Reg) CurMBB->addLiveIn(Reg);
3920 // Insert the EXCEPTIONADDR instruction.
3921 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3923 Ops[0] = DAG.getRoot();
3924 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3926 DAG.setRoot(Op.getValue(1));
3930 case Intrinsic::eh_selector_i32:
3931 case Intrinsic::eh_selector_i64: {
3932 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3933 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3934 MVT::i32 : MVT::i64);
3937 if (CurMBB->isLandingPad())
3938 AddCatchInfo(I, MMI, CurMBB);
3941 FuncInfo.CatchInfoLost.insert(&I);
3943 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3944 unsigned Reg = TLI.getExceptionSelectorRegister();
3945 if (Reg) CurMBB->addLiveIn(Reg);
3948 // Insert the EHSELECTION instruction.
3949 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3951 Ops[0] = getValue(I.getOperand(1));
3953 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3955 DAG.setRoot(Op.getValue(1));
3957 setValue(&I, DAG.getConstant(0, VT));
3963 case Intrinsic::eh_typeid_for_i32:
3964 case Intrinsic::eh_typeid_for_i64: {
3965 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3966 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3967 MVT::i32 : MVT::i64);
3970 // Find the type id for the given typeinfo.
3971 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3973 unsigned TypeID = MMI->getTypeIDFor(GV);
3974 setValue(&I, DAG.getConstant(TypeID, VT));
3976 // Return something different to eh_selector.
3977 setValue(&I, DAG.getConstant(1, VT));
3983 case Intrinsic::eh_return_i32:
3984 case Intrinsic::eh_return_i64:
3985 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3986 MMI->setCallsEHReturn(true);
3987 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3990 getValue(I.getOperand(1)),
3991 getValue(I.getOperand(2))));
3993 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3997 case Intrinsic::eh_unwind_init:
3998 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3999 MMI->setCallsUnwindInit(true);
4004 case Intrinsic::eh_dwarf_cfa: {
4005 MVT VT = getValue(I.getOperand(1)).getValueType();
4007 if (VT.bitsGT(TLI.getPointerTy()))
4008 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4009 TLI.getPointerTy(), getValue(I.getOperand(1)));
4011 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4012 TLI.getPointerTy(), getValue(I.getOperand(1)));
4014 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4016 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4017 TLI.getPointerTy()),
4019 setValue(&I, DAG.getNode(ISD::ADD, dl,
4021 DAG.getNode(ISD::FRAMEADDR, dl,
4024 TLI.getPointerTy())),
4029 case Intrinsic::convertff:
4030 case Intrinsic::convertfsi:
4031 case Intrinsic::convertfui:
4032 case Intrinsic::convertsif:
4033 case Intrinsic::convertuif:
4034 case Intrinsic::convertss:
4035 case Intrinsic::convertsu:
4036 case Intrinsic::convertus:
4037 case Intrinsic::convertuu: {
4038 ISD::CvtCode Code = ISD::CVT_INVALID;
4039 switch (Intrinsic) {
4040 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4041 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4042 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4043 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4044 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4045 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4046 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4047 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4048 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4050 MVT DestVT = TLI.getValueType(I.getType());
4051 Value* Op1 = I.getOperand(1);
4052 setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1),
4053 DAG.getValueType(DestVT),
4054 DAG.getValueType(getValue(Op1).getValueType()),
4055 getValue(I.getOperand(2)),
4056 getValue(I.getOperand(3)),
4061 case Intrinsic::sqrt:
4062 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4063 getValue(I.getOperand(1)).getValueType(),
4064 getValue(I.getOperand(1))));
4066 case Intrinsic::powi:
4067 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4068 getValue(I.getOperand(1)).getValueType(),
4069 getValue(I.getOperand(1)),
4070 getValue(I.getOperand(2))));
4072 case Intrinsic::sin:
4073 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4074 getValue(I.getOperand(1)).getValueType(),
4075 getValue(I.getOperand(1))));
4077 case Intrinsic::cos:
4078 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4079 getValue(I.getOperand(1)).getValueType(),
4080 getValue(I.getOperand(1))));
4082 case Intrinsic::log:
4085 case Intrinsic::log2:
4088 case Intrinsic::log10:
4091 case Intrinsic::exp:
4094 case Intrinsic::exp2:
4097 case Intrinsic::pow:
4100 case Intrinsic::pcmarker: {
4101 SDValue Tmp = getValue(I.getOperand(1));
4102 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4105 case Intrinsic::readcyclecounter: {
4106 SDValue Op = getRoot();
4107 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4108 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4111 DAG.setRoot(Tmp.getValue(1));
4114 case Intrinsic::part_select: {
4115 // Currently not implemented: just abort
4116 assert(0 && "part_select intrinsic not implemented");
4119 case Intrinsic::part_set: {
4120 // Currently not implemented: just abort
4121 assert(0 && "part_set intrinsic not implemented");
4124 case Intrinsic::bswap:
4125 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4126 getValue(I.getOperand(1)).getValueType(),
4127 getValue(I.getOperand(1))));
4129 case Intrinsic::cttz: {
4130 SDValue Arg = getValue(I.getOperand(1));
4131 MVT Ty = Arg.getValueType();
4132 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4133 setValue(&I, result);
4136 case Intrinsic::ctlz: {
4137 SDValue Arg = getValue(I.getOperand(1));
4138 MVT Ty = Arg.getValueType();
4139 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4140 setValue(&I, result);
4143 case Intrinsic::ctpop: {
4144 SDValue Arg = getValue(I.getOperand(1));
4145 MVT Ty = Arg.getValueType();
4146 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4147 setValue(&I, result);
4150 case Intrinsic::stacksave: {
4151 SDValue Op = getRoot();
4152 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4153 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4155 DAG.setRoot(Tmp.getValue(1));
4158 case Intrinsic::stackrestore: {
4159 SDValue Tmp = getValue(I.getOperand(1));
4160 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4163 case Intrinsic::stackprotector: {
4164 // Emit code into the DAG to store the stack guard onto the stack.
4165 MachineFunction &MF = DAG.getMachineFunction();
4166 MachineFrameInfo *MFI = MF.getFrameInfo();
4167 MVT PtrTy = TLI.getPointerTy();
4169 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4170 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4172 int FI = FuncInfo.StaticAllocaMap[Slot];
4173 MFI->setStackProtectorIndex(FI);
4175 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4177 // Store the stack protector onto the stack.
4178 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4179 PseudoSourceValue::getFixedStack(FI),
4181 setValue(&I, Result);
4182 DAG.setRoot(Result);
4185 case Intrinsic::var_annotation:
4186 // Discard annotate attributes
4189 case Intrinsic::init_trampoline: {
4190 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4194 Ops[1] = getValue(I.getOperand(1));
4195 Ops[2] = getValue(I.getOperand(2));
4196 Ops[3] = getValue(I.getOperand(3));
4197 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4198 Ops[5] = DAG.getSrcValue(F);
4200 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4201 DAG.getNodeValueTypes(TLI.getPointerTy(),
4206 DAG.setRoot(Tmp.getValue(1));
4210 case Intrinsic::gcroot:
4212 Value *Alloca = I.getOperand(1);
4213 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4215 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4216 GFI->addStackRoot(FI->getIndex(), TypeMap);
4220 case Intrinsic::gcread:
4221 case Intrinsic::gcwrite:
4222 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4225 case Intrinsic::flt_rounds: {
4226 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4230 case Intrinsic::trap: {
4231 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4235 case Intrinsic::uadd_with_overflow:
4236 return implVisitAluOverflow(I, ISD::UADDO);
4237 case Intrinsic::sadd_with_overflow:
4238 return implVisitAluOverflow(I, ISD::SADDO);
4239 case Intrinsic::usub_with_overflow:
4240 return implVisitAluOverflow(I, ISD::USUBO);
4241 case Intrinsic::ssub_with_overflow:
4242 return implVisitAluOverflow(I, ISD::SSUBO);
4243 case Intrinsic::umul_with_overflow:
4244 return implVisitAluOverflow(I, ISD::UMULO);
4245 case Intrinsic::smul_with_overflow:
4246 return implVisitAluOverflow(I, ISD::SMULO);
4248 case Intrinsic::prefetch: {
4251 Ops[1] = getValue(I.getOperand(1));
4252 Ops[2] = getValue(I.getOperand(2));
4253 Ops[3] = getValue(I.getOperand(3));
4254 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4258 case Intrinsic::memory_barrier: {
4261 for (int x = 1; x < 6; ++x)
4262 Ops[x] = getValue(I.getOperand(x));
4264 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4267 case Intrinsic::atomic_cmp_swap: {
4268 SDValue Root = getRoot();
4270 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4271 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4273 getValue(I.getOperand(1)),
4274 getValue(I.getOperand(2)),
4275 getValue(I.getOperand(3)),
4278 DAG.setRoot(L.getValue(1));
4281 case Intrinsic::atomic_load_add:
4282 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4283 case Intrinsic::atomic_load_sub:
4284 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4285 case Intrinsic::atomic_load_or:
4286 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4287 case Intrinsic::atomic_load_xor:
4288 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4289 case Intrinsic::atomic_load_and:
4290 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4291 case Intrinsic::atomic_load_nand:
4292 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4293 case Intrinsic::atomic_load_max:
4294 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4295 case Intrinsic::atomic_load_min:
4296 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4297 case Intrinsic::atomic_load_umin:
4298 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4299 case Intrinsic::atomic_load_umax:
4300 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4301 case Intrinsic::atomic_swap:
4302 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4307 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4309 MachineBasicBlock *LandingPad) {
4310 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4311 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4312 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4313 unsigned BeginLabel = 0, EndLabel = 0;
4315 TargetLowering::ArgListTy Args;
4316 TargetLowering::ArgListEntry Entry;
4317 Args.reserve(CS.arg_size());
4318 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4320 SDValue ArgNode = getValue(*i);
4321 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4323 unsigned attrInd = i - CS.arg_begin() + 1;
4324 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4325 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4326 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4327 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4328 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4329 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4330 Entry.Alignment = CS.getParamAlignment(attrInd);
4331 Args.push_back(Entry);
4334 if (LandingPad && MMI) {
4335 // Insert a label before the invoke call to mark the try range. This can be
4336 // used to detect deletion of the invoke via the MachineModuleInfo.
4337 BeginLabel = MMI->NextLabelID();
4338 // Both PendingLoads and PendingExports must be flushed here;
4339 // this call might not return.
4341 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
4344 std::pair<SDValue,SDValue> Result =
4345 TLI.LowerCallTo(getRoot(), CS.getType(),
4346 CS.paramHasAttr(0, Attribute::SExt),
4347 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4348 CS.paramHasAttr(0, Attribute::InReg),
4349 CS.getCallingConv(),
4350 IsTailCall && PerformTailCallOpt,
4351 Callee, Args, DAG, getCurDebugLoc());
4352 if (CS.getType() != Type::VoidTy)
4353 setValue(CS.getInstruction(), Result.first);
4354 DAG.setRoot(Result.second);
4356 if (LandingPad && MMI) {
4357 // Insert a label at the end of the invoke call to mark the try range. This
4358 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4359 EndLabel = MMI->NextLabelID();
4360 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
4362 // Inform MachineModuleInfo of range.
4363 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4368 void SelectionDAGLowering::visitCall(CallInst &I) {
4369 const char *RenameFn = 0;
4370 if (Function *F = I.getCalledFunction()) {
4371 if (F->isDeclaration()) {
4372 if (unsigned IID = F->getIntrinsicID()) {
4373 RenameFn = visitIntrinsicCall(I, IID);
4379 // Check for well-known libc/libm calls. If the function is internal, it
4380 // can't be a library call.
4381 unsigned NameLen = F->getNameLen();
4382 if (!F->hasLocalLinkage() && NameLen) {
4383 const char *NameStr = F->getNameStart();
4384 if (NameStr[0] == 'c' &&
4385 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4386 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4387 if (I.getNumOperands() == 3 && // Basic sanity checks.
4388 I.getOperand(1)->getType()->isFloatingPoint() &&
4389 I.getType() == I.getOperand(1)->getType() &&
4390 I.getType() == I.getOperand(2)->getType()) {
4391 SDValue LHS = getValue(I.getOperand(1));
4392 SDValue RHS = getValue(I.getOperand(2));
4393 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4394 LHS.getValueType(), LHS, RHS));
4397 } else if (NameStr[0] == 'f' &&
4398 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4399 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4400 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4401 if (I.getNumOperands() == 2 && // Basic sanity checks.
4402 I.getOperand(1)->getType()->isFloatingPoint() &&
4403 I.getType() == I.getOperand(1)->getType()) {
4404 SDValue Tmp = getValue(I.getOperand(1));
4405 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4406 Tmp.getValueType(), Tmp));
4409 } else if (NameStr[0] == 's' &&
4410 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4411 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4412 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4413 if (I.getNumOperands() == 2 && // Basic sanity checks.
4414 I.getOperand(1)->getType()->isFloatingPoint() &&
4415 I.getType() == I.getOperand(1)->getType()) {
4416 SDValue Tmp = getValue(I.getOperand(1));
4417 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4418 Tmp.getValueType(), Tmp));
4421 } else if (NameStr[0] == 'c' &&
4422 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4423 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4424 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4425 if (I.getNumOperands() == 2 && // Basic sanity checks.
4426 I.getOperand(1)->getType()->isFloatingPoint() &&
4427 I.getType() == I.getOperand(1)->getType()) {
4428 SDValue Tmp = getValue(I.getOperand(1));
4429 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4430 Tmp.getValueType(), Tmp));
4435 } else if (isa<InlineAsm>(I.getOperand(0))) {
4442 Callee = getValue(I.getOperand(0));
4444 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4446 LowerCallTo(&I, Callee, I.isTailCall());
4450 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4451 /// this value and returns the result as a ValueVT value. This uses
4452 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4453 /// If the Flag pointer is NULL, no flag is used.
4454 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4456 SDValue *Flag) const {
4457 // Assemble the legal parts into the final values.
4458 SmallVector<SDValue, 4> Values(ValueVTs.size());
4459 SmallVector<SDValue, 8> Parts;
4460 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4461 // Copy the legal parts from the registers.
4462 MVT ValueVT = ValueVTs[Value];
4463 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4464 MVT RegisterVT = RegVTs[Value];
4466 Parts.resize(NumRegs);
4467 for (unsigned i = 0; i != NumRegs; ++i) {
4470 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4472 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4473 *Flag = P.getValue(2);
4475 Chain = P.getValue(1);
4477 // If the source register was virtual and if we know something about it,
4478 // add an assert node.
4479 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4480 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4481 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4482 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4483 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4484 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4486 unsigned RegSize = RegisterVT.getSizeInBits();
4487 unsigned NumSignBits = LOI.NumSignBits;
4488 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4490 // FIXME: We capture more information than the dag can represent. For
4491 // now, just use the tightest assertzext/assertsext possible.
4493 MVT FromVT(MVT::Other);
4494 if (NumSignBits == RegSize)
4495 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4496 else if (NumZeroBits >= RegSize-1)
4497 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4498 else if (NumSignBits > RegSize-8)
4499 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4500 else if (NumZeroBits >= RegSize-9)
4501 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4502 else if (NumSignBits > RegSize-16)
4503 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4504 else if (NumZeroBits >= RegSize-17)
4505 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4506 else if (NumSignBits > RegSize-32)
4507 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4508 else if (NumZeroBits >= RegSize-33)
4509 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4511 if (FromVT != MVT::Other) {
4512 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4513 RegisterVT, P, DAG.getValueType(FromVT));
4522 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4523 NumRegs, RegisterVT, ValueVT);
4528 return DAG.getNode(ISD::MERGE_VALUES, dl,
4529 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4530 &Values[0], ValueVTs.size());
4533 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4534 /// specified value into the registers specified by this object. This uses
4535 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4536 /// If the Flag pointer is NULL, no flag is used.
4537 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4538 SDValue &Chain, SDValue *Flag) const {
4539 // Get the list of the values's legal parts.
4540 unsigned NumRegs = Regs.size();
4541 SmallVector<SDValue, 8> Parts(NumRegs);
4542 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4543 MVT ValueVT = ValueVTs[Value];
4544 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4545 MVT RegisterVT = RegVTs[Value];
4547 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4548 &Parts[Part], NumParts, RegisterVT);
4552 // Copy the parts into the registers.
4553 SmallVector<SDValue, 8> Chains(NumRegs);
4554 for (unsigned i = 0; i != NumRegs; ++i) {
4557 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4559 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4560 *Flag = Part.getValue(1);
4562 Chains[i] = Part.getValue(0);
4565 if (NumRegs == 1 || Flag)
4566 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4567 // flagged to it. That is the CopyToReg nodes and the user are considered
4568 // a single scheduling unit. If we create a TokenFactor and return it as
4569 // chain, then the TokenFactor is both a predecessor (operand) of the
4570 // user as well as a successor (the TF operands are flagged to the user).
4571 // c1, f1 = CopyToReg
4572 // c2, f2 = CopyToReg
4573 // c3 = TokenFactor c1, c2
4576 Chain = Chains[NumRegs-1];
4578 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4581 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4582 /// operand list. This adds the code marker and includes the number of
4583 /// values added into it.
4584 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4585 std::vector<SDValue> &Ops) const {
4586 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4587 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4588 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4589 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4590 MVT RegisterVT = RegVTs[Value];
4591 for (unsigned i = 0; i != NumRegs; ++i) {
4592 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4593 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4598 /// isAllocatableRegister - If the specified register is safe to allocate,
4599 /// i.e. it isn't a stack pointer or some other special register, return the
4600 /// register class for the register. Otherwise, return null.
4601 static const TargetRegisterClass *
4602 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4603 const TargetLowering &TLI,
4604 const TargetRegisterInfo *TRI) {
4605 MVT FoundVT = MVT::Other;
4606 const TargetRegisterClass *FoundRC = 0;
4607 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4608 E = TRI->regclass_end(); RCI != E; ++RCI) {
4609 MVT ThisVT = MVT::Other;
4611 const TargetRegisterClass *RC = *RCI;
4612 // If none of the the value types for this register class are valid, we
4613 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4614 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4616 if (TLI.isTypeLegal(*I)) {
4617 // If we have already found this register in a different register class,
4618 // choose the one with the largest VT specified. For example, on
4619 // PowerPC, we favor f64 register classes over f32.
4620 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4627 if (ThisVT == MVT::Other) continue;
4629 // NOTE: This isn't ideal. In particular, this might allocate the
4630 // frame pointer in functions that need it (due to them not being taken
4631 // out of allocation, because a variable sized allocation hasn't been seen
4632 // yet). This is a slight code pessimization, but should still work.
4633 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4634 E = RC->allocation_order_end(MF); I != E; ++I)
4636 // We found a matching register class. Keep looking at others in case
4637 // we find one with larger registers that this physreg is also in.
4648 /// AsmOperandInfo - This contains information for each constraint that we are
4650 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4651 public TargetLowering::AsmOperandInfo {
4652 /// CallOperand - If this is the result output operand or a clobber
4653 /// this is null, otherwise it is the incoming operand to the CallInst.
4654 /// This gets modified as the asm is processed.
4655 SDValue CallOperand;
4657 /// AssignedRegs - If this is a register or register class operand, this
4658 /// contains the set of register corresponding to the operand.
4659 RegsForValue AssignedRegs;
4661 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4662 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4665 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4666 /// busy in OutputRegs/InputRegs.
4667 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4668 std::set<unsigned> &OutputRegs,
4669 std::set<unsigned> &InputRegs,
4670 const TargetRegisterInfo &TRI) const {
4672 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4673 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4676 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4677 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4681 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4682 /// corresponds to. If there is no Value* for this operand, it returns
4684 MVT getCallOperandValMVT(const TargetLowering &TLI,
4685 const TargetData *TD) const {
4686 if (CallOperandVal == 0) return MVT::Other;
4688 if (isa<BasicBlock>(CallOperandVal))
4689 return TLI.getPointerTy();
4691 const llvm::Type *OpTy = CallOperandVal->getType();
4693 // If this is an indirect operand, the operand is a pointer to the
4696 OpTy = cast<PointerType>(OpTy)->getElementType();
4698 // If OpTy is not a single value, it may be a struct/union that we
4699 // can tile with integers.
4700 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4701 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4710 OpTy = IntegerType::get(BitSize);
4715 return TLI.getValueType(OpTy, true);
4719 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4721 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4722 const TargetRegisterInfo &TRI) {
4723 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4725 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4726 for (; *Aliases; ++Aliases)
4727 Regs.insert(*Aliases);
4730 } // end llvm namespace.
4733 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4734 /// specified operand. We prefer to assign virtual registers, to allow the
4735 /// register allocator handle the assignment process. However, if the asm uses
4736 /// features that we can't model on machineinstrs, we have SDISel do the
4737 /// allocation. This produces generally horrible, but correct, code.
4739 /// OpInfo describes the operand.
4740 /// Input and OutputRegs are the set of already allocated physical registers.
4742 void SelectionDAGLowering::
4743 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4744 std::set<unsigned> &OutputRegs,
4745 std::set<unsigned> &InputRegs) {
4746 // Compute whether this value requires an input register, an output register,
4748 bool isOutReg = false;
4749 bool isInReg = false;
4750 switch (OpInfo.Type) {
4751 case InlineAsm::isOutput:
4754 // If there is an input constraint that matches this, we need to reserve
4755 // the input register so no other inputs allocate to it.
4756 isInReg = OpInfo.hasMatchingInput();
4758 case InlineAsm::isInput:
4762 case InlineAsm::isClobber:
4769 MachineFunction &MF = DAG.getMachineFunction();
4770 SmallVector<unsigned, 4> Regs;
4772 // If this is a constraint for a single physreg, or a constraint for a
4773 // register class, find it.
4774 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4775 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4776 OpInfo.ConstraintVT);
4778 unsigned NumRegs = 1;
4779 if (OpInfo.ConstraintVT != MVT::Other) {
4780 // If this is a FP input in an integer register (or visa versa) insert a bit
4781 // cast of the input value. More generally, handle any case where the input
4782 // value disagrees with the register class we plan to stick this in.
4783 if (OpInfo.Type == InlineAsm::isInput &&
4784 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4785 // Try to convert to the first MVT that the reg class contains. If the
4786 // types are identical size, use a bitcast to convert (e.g. two differing
4788 MVT RegVT = *PhysReg.second->vt_begin();
4789 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4790 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4791 RegVT, OpInfo.CallOperand);
4792 OpInfo.ConstraintVT = RegVT;
4793 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4794 // If the input is a FP value and we want it in FP registers, do a
4795 // bitcast to the corresponding integer type. This turns an f64 value
4796 // into i64, which can be passed with two i32 values on a 32-bit
4798 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4799 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4800 RegVT, OpInfo.CallOperand);
4801 OpInfo.ConstraintVT = RegVT;
4805 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4809 MVT ValueVT = OpInfo.ConstraintVT;
4811 // If this is a constraint for a specific physical register, like {r17},
4813 if (PhysReg.first) {
4814 if (OpInfo.ConstraintVT == MVT::Other)
4815 ValueVT = *PhysReg.second->vt_begin();
4817 // Get the actual register value type. This is important, because the user
4818 // may have asked for (e.g.) the AX register in i32 type. We need to
4819 // remember that AX is actually i16 to get the right extension.
4820 RegVT = *PhysReg.second->vt_begin();
4822 // This is a explicit reference to a physical register.
4823 Regs.push_back(PhysReg.first);
4825 // If this is an expanded reference, add the rest of the regs to Regs.
4827 TargetRegisterClass::iterator I = PhysReg.second->begin();
4828 for (; *I != PhysReg.first; ++I)
4829 assert(I != PhysReg.second->end() && "Didn't find reg!");
4831 // Already added the first reg.
4833 for (; NumRegs; --NumRegs, ++I) {
4834 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4838 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4839 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4840 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4844 // Otherwise, if this was a reference to an LLVM register class, create vregs
4845 // for this reference.
4846 std::vector<unsigned> RegClassRegs;
4847 const TargetRegisterClass *RC = PhysReg.second;
4849 // If this is a tied register, our regalloc doesn't know how to maintain
4850 // the constraint, so we have to pick a register to pin the input/output to.
4851 // If it isn't a matched constraint, go ahead and create vreg and let the
4852 // regalloc do its thing.
4853 if (!OpInfo.hasMatchingInput()) {
4854 RegVT = *PhysReg.second->vt_begin();
4855 if (OpInfo.ConstraintVT == MVT::Other)
4858 // Create the appropriate number of virtual registers.
4859 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4860 for (; NumRegs; --NumRegs)
4861 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4863 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4867 // Otherwise, we can't allocate it. Let the code below figure out how to
4868 // maintain these constraints.
4869 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4872 // This is a reference to a register class that doesn't directly correspond
4873 // to an LLVM register class. Allocate NumRegs consecutive, available,
4874 // registers from the class.
4875 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4876 OpInfo.ConstraintVT);
4879 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4880 unsigned NumAllocated = 0;
4881 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4882 unsigned Reg = RegClassRegs[i];
4883 // See if this register is available.
4884 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4885 (isInReg && InputRegs.count(Reg))) { // Already used.
4886 // Make sure we find consecutive registers.
4891 // Check to see if this register is allocatable (i.e. don't give out the
4894 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4895 if (!RC) { // Couldn't allocate this register.
4896 // Reset NumAllocated to make sure we return consecutive registers.
4902 // Okay, this register is good, we can use it.
4905 // If we allocated enough consecutive registers, succeed.
4906 if (NumAllocated == NumRegs) {
4907 unsigned RegStart = (i-NumAllocated)+1;
4908 unsigned RegEnd = i+1;
4909 // Mark all of the allocated registers used.
4910 for (unsigned i = RegStart; i != RegEnd; ++i)
4911 Regs.push_back(RegClassRegs[i]);
4913 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4914 OpInfo.ConstraintVT);
4915 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4920 // Otherwise, we couldn't allocate enough registers for this.
4923 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4924 /// processed uses a memory 'm' constraint.
4926 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4927 const TargetLowering &TLI) {
4928 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4929 InlineAsm::ConstraintInfo &CI = CInfos[i];
4930 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4931 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4932 if (CType == TargetLowering::C_Memory)
4940 /// visitInlineAsm - Handle a call to an InlineAsm object.
4942 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4943 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4945 /// ConstraintOperands - Information about all of the constraints.
4946 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4948 SDValue Chain = getRoot();
4951 std::set<unsigned> OutputRegs, InputRegs;
4953 // Do a prepass over the constraints, canonicalizing them, and building up the
4954 // ConstraintOperands list.
4955 std::vector<InlineAsm::ConstraintInfo>
4956 ConstraintInfos = IA->ParseConstraints();
4958 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
4960 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4961 unsigned ResNo = 0; // ResNo - The result number of the next output.
4962 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4963 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4964 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4966 MVT OpVT = MVT::Other;
4968 // Compute the value type for each operand.
4969 switch (OpInfo.Type) {
4970 case InlineAsm::isOutput:
4971 // Indirect outputs just consume an argument.
4972 if (OpInfo.isIndirect) {
4973 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4977 // The return value of the call is this value. As such, there is no
4978 // corresponding argument.
4979 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4980 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4981 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4983 assert(ResNo == 0 && "Asm only has one result!");
4984 OpVT = TLI.getValueType(CS.getType());
4988 case InlineAsm::isInput:
4989 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4991 case InlineAsm::isClobber:
4996 // If this is an input or an indirect output, process the call argument.
4997 // BasicBlocks are labels, currently appearing only in asm's.
4998 if (OpInfo.CallOperandVal) {
4999 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5000 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5002 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5005 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5008 OpInfo.ConstraintVT = OpVT;
5011 // Second pass over the constraints: compute which constraint option to use
5012 // and assign registers to constraints that want a specific physreg.
5013 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5014 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5016 // If this is an output operand with a matching input operand, look up the
5017 // matching input. If their types mismatch, e.g. one is an integer, the
5018 // other is floating point, or their sizes are different, flag it as an
5020 if (OpInfo.hasMatchingInput()) {
5021 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5022 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5023 if ((OpInfo.ConstraintVT.isInteger() !=
5024 Input.ConstraintVT.isInteger()) ||
5025 (OpInfo.ConstraintVT.getSizeInBits() !=
5026 Input.ConstraintVT.getSizeInBits())) {
5027 cerr << "Unsupported asm: input constraint with a matching output "
5028 << "constraint of incompatible type!\n";
5031 Input.ConstraintVT = OpInfo.ConstraintVT;
5035 // Compute the constraint code and ConstraintType to use.
5036 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5038 // If this is a memory input, and if the operand is not indirect, do what we
5039 // need to to provide an address for the memory input.
5040 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5041 !OpInfo.isIndirect) {
5042 assert(OpInfo.Type == InlineAsm::isInput &&
5043 "Can only indirectify direct input operands!");
5045 // Memory operands really want the address of the value. If we don't have
5046 // an indirect input, put it in the constpool if we can, otherwise spill
5047 // it to a stack slot.
5049 // If the operand is a float, integer, or vector constant, spill to a
5050 // constant pool entry to get its address.
5051 Value *OpVal = OpInfo.CallOperandVal;
5052 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5053 isa<ConstantVector>(OpVal)) {
5054 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5055 TLI.getPointerTy());
5057 // Otherwise, create a stack slot and emit a store to it before the
5059 const Type *Ty = OpVal->getType();
5060 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5061 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5062 MachineFunction &MF = DAG.getMachineFunction();
5063 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5064 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5065 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5066 OpInfo.CallOperand, StackSlot, NULL, 0);
5067 OpInfo.CallOperand = StackSlot;
5070 // There is no longer a Value* corresponding to this operand.
5071 OpInfo.CallOperandVal = 0;
5072 // It is now an indirect operand.
5073 OpInfo.isIndirect = true;
5076 // If this constraint is for a specific register, allocate it before
5078 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5079 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5081 ConstraintInfos.clear();
5084 // Second pass - Loop over all of the operands, assigning virtual or physregs
5085 // to register class operands.
5086 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5087 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5089 // C_Register operands have already been allocated, Other/Memory don't need
5091 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5092 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5095 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5096 std::vector<SDValue> AsmNodeOperands;
5097 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5098 AsmNodeOperands.push_back(
5099 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5102 // Loop over all of the inputs, copying the operand values into the
5103 // appropriate registers and processing the output regs.
5104 RegsForValue RetValRegs;
5106 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5107 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5109 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5110 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5112 switch (OpInfo.Type) {
5113 case InlineAsm::isOutput: {
5114 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5115 OpInfo.ConstraintType != TargetLowering::C_Register) {
5116 // Memory output, or 'other' output (e.g. 'X' constraint).
5117 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5119 // Add information to the INLINEASM node to know about this output.
5120 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5121 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5122 TLI.getPointerTy()));
5123 AsmNodeOperands.push_back(OpInfo.CallOperand);
5127 // Otherwise, this is a register or register class output.
5129 // Copy the output from the appropriate register. Find a register that
5131 if (OpInfo.AssignedRegs.Regs.empty()) {
5132 cerr << "Couldn't allocate output reg for constraint '"
5133 << OpInfo.ConstraintCode << "'!\n";
5137 // If this is an indirect operand, store through the pointer after the
5139 if (OpInfo.isIndirect) {
5140 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5141 OpInfo.CallOperandVal));
5143 // This is the result value of the call.
5144 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5145 // Concatenate this output onto the outputs list.
5146 RetValRegs.append(OpInfo.AssignedRegs);
5149 // Add information to the INLINEASM node to know that this register is
5151 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5152 6 /* EARLYCLOBBER REGDEF */ :
5154 DAG, AsmNodeOperands);
5157 case InlineAsm::isInput: {
5158 SDValue InOperandVal = OpInfo.CallOperand;
5160 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5161 // If this is required to match an output register we have already set,
5162 // just use its register.
5163 unsigned OperandNo = OpInfo.getMatchedOperand();
5165 // Scan until we find the definition we already emitted of this operand.
5166 // When we find it, create a RegsForValue operand.
5167 unsigned CurOp = 2; // The first operand.
5168 for (; OperandNo; --OperandNo) {
5169 // Advance to the next operand.
5171 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5172 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
5173 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5174 (NumOps & 7) == 4 /*MEM*/) &&
5175 "Skipped past definitions?");
5176 CurOp += (NumOps>>3)+1;
5180 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5181 if ((NumOps & 7) == 2 /*REGDEF*/
5182 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5183 // Add NumOps>>3 registers to MatchedRegs.
5184 RegsForValue MatchedRegs;
5185 MatchedRegs.TLI = &TLI;
5186 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5187 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5188 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5190 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5191 MatchedRegs.Regs.push_back(Reg);
5194 // Use the produced MatchedRegs object to
5195 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5197 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
5200 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5201 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5202 // Add information to the INLINEASM node to know about this input.
5203 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
5204 TLI.getPointerTy()));
5205 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5210 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5211 assert(!OpInfo.isIndirect &&
5212 "Don't know how to handle indirect other inputs yet!");
5214 std::vector<SDValue> Ops;
5215 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5216 hasMemory, Ops, DAG);
5218 cerr << "Invalid operand for inline asm constraint '"
5219 << OpInfo.ConstraintCode << "'!\n";
5223 // Add information to the INLINEASM node to know about this input.
5224 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5225 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5226 TLI.getPointerTy()));
5227 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5229 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5230 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5231 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5232 "Memory operands expect pointer values");
5234 // Add information to the INLINEASM node to know about this input.
5235 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5236 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5237 TLI.getPointerTy()));
5238 AsmNodeOperands.push_back(InOperandVal);
5242 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5243 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5244 "Unknown constraint type!");
5245 assert(!OpInfo.isIndirect &&
5246 "Don't know how to handle indirect register inputs yet!");
5248 // Copy the input into the appropriate registers.
5249 if (OpInfo.AssignedRegs.Regs.empty()) {
5250 cerr << "Couldn't allocate output reg for constraint '"
5251 << OpInfo.ConstraintCode << "'!\n";
5255 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5258 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5259 DAG, AsmNodeOperands);
5262 case InlineAsm::isClobber: {
5263 // Add the clobbered value to the operand list, so that the register
5264 // allocator is aware that the physreg got clobbered.
5265 if (!OpInfo.AssignedRegs.Regs.empty())
5266 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5267 DAG, AsmNodeOperands);
5273 // Finish up input operands.
5274 AsmNodeOperands[0] = Chain;
5275 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5277 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5278 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5279 &AsmNodeOperands[0], AsmNodeOperands.size());
5280 Flag = Chain.getValue(1);
5282 // If this asm returns a register value, copy the result from that register
5283 // and set it as the value of the call.
5284 if (!RetValRegs.Regs.empty()) {
5285 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5288 // FIXME: Why don't we do this for inline asms with MRVs?
5289 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5290 MVT ResultType = TLI.getValueType(CS.getType());
5292 // If any of the results of the inline asm is a vector, it may have the
5293 // wrong width/num elts. This can happen for register classes that can
5294 // contain multiple different value types. The preg or vreg allocated may
5295 // not have the same VT as was expected. Convert it to the right type
5296 // with bit_convert.
5297 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5298 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5301 } else if (ResultType != Val.getValueType() &&
5302 ResultType.isInteger() && Val.getValueType().isInteger()) {
5303 // If a result value was tied to an input value, the computed result may
5304 // have a wider width than the expected result. Extract the relevant
5306 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5309 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5312 setValue(CS.getInstruction(), Val);
5315 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5317 // Process indirect outputs, first output all of the flagged copies out of
5319 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5320 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5321 Value *Ptr = IndirectStoresToEmit[i].second;
5322 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5324 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5327 // Emit the non-flagged stores from the physregs.
5328 SmallVector<SDValue, 8> OutChains;
5329 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5330 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5331 StoresToEmit[i].first,
5332 getValue(StoresToEmit[i].second),
5333 StoresToEmit[i].second, 0));
5334 if (!OutChains.empty())
5335 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5336 &OutChains[0], OutChains.size());
5341 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5342 SDValue Src = getValue(I.getOperand(0));
5344 MVT IntPtr = TLI.getPointerTy();
5346 if (IntPtr.bitsLT(Src.getValueType()))
5347 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5348 else if (IntPtr.bitsGT(Src.getValueType()))
5349 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5351 // Scale the source by the type size.
5352 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5353 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5354 Src, DAG.getIntPtrConstant(ElementSize));
5356 TargetLowering::ArgListTy Args;
5357 TargetLowering::ArgListEntry Entry;
5359 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5360 Args.push_back(Entry);
5362 std::pair<SDValue,SDValue> Result =
5363 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5364 CallingConv::C, PerformTailCallOpt,
5365 DAG.getExternalSymbol("malloc", IntPtr),
5366 Args, DAG, getCurDebugLoc());
5367 setValue(&I, Result.first); // Pointers always fit in registers
5368 DAG.setRoot(Result.second);
5371 void SelectionDAGLowering::visitFree(FreeInst &I) {
5372 TargetLowering::ArgListTy Args;
5373 TargetLowering::ArgListEntry Entry;
5374 Entry.Node = getValue(I.getOperand(0));
5375 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5376 Args.push_back(Entry);
5377 MVT IntPtr = TLI.getPointerTy();
5378 std::pair<SDValue,SDValue> Result =
5379 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5380 CallingConv::C, PerformTailCallOpt,
5381 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5383 DAG.setRoot(Result.second);
5386 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5387 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5388 MVT::Other, getRoot(),
5389 getValue(I.getOperand(1)),
5390 DAG.getSrcValue(I.getOperand(1))));
5393 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5394 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
5395 getValue(I.getOperand(0)),
5396 DAG.getSrcValue(I.getOperand(0)));
5398 DAG.setRoot(V.getValue(1));
5401 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5402 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5403 MVT::Other, getRoot(),
5404 getValue(I.getOperand(1)),
5405 DAG.getSrcValue(I.getOperand(1))));
5408 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5409 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5410 MVT::Other, getRoot(),
5411 getValue(I.getOperand(1)),
5412 getValue(I.getOperand(2)),
5413 DAG.getSrcValue(I.getOperand(1)),
5414 DAG.getSrcValue(I.getOperand(2))));
5417 /// TargetLowering::LowerArguments - This is the default LowerArguments
5418 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5419 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5420 /// integrated into SDISel.
5421 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5422 SmallVectorImpl<SDValue> &ArgValues,
5424 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5425 SmallVector<SDValue, 3+16> Ops;
5426 Ops.push_back(DAG.getRoot());
5427 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5428 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5430 // Add one result value for each formal argument.
5431 SmallVector<MVT, 16> RetVals;
5433 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5435 SmallVector<MVT, 4> ValueVTs;
5436 ComputeValueVTs(*this, I->getType(), ValueVTs);
5437 for (unsigned Value = 0, NumValues = ValueVTs.size();
5438 Value != NumValues; ++Value) {
5439 MVT VT = ValueVTs[Value];
5440 const Type *ArgTy = VT.getTypeForMVT();
5441 ISD::ArgFlagsTy Flags;
5442 unsigned OriginalAlignment =
5443 getTargetData()->getABITypeAlignment(ArgTy);
5445 if (F.paramHasAttr(j, Attribute::ZExt))
5447 if (F.paramHasAttr(j, Attribute::SExt))
5449 if (F.paramHasAttr(j, Attribute::InReg))
5451 if (F.paramHasAttr(j, Attribute::StructRet))
5453 if (F.paramHasAttr(j, Attribute::ByVal)) {
5455 const PointerType *Ty = cast<PointerType>(I->getType());
5456 const Type *ElementTy = Ty->getElementType();
5457 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5458 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5459 // For ByVal, alignment should be passed from FE. BE will guess if
5460 // this info is not there but there are cases it cannot get right.
5461 if (F.getParamAlignment(j))
5462 FrameAlign = F.getParamAlignment(j);
5463 Flags.setByValAlign(FrameAlign);
5464 Flags.setByValSize(FrameSize);
5466 if (F.paramHasAttr(j, Attribute::Nest))
5468 Flags.setOrigAlign(OriginalAlignment);
5470 MVT RegisterVT = getRegisterType(VT);
5471 unsigned NumRegs = getNumRegisters(VT);
5472 for (unsigned i = 0; i != NumRegs; ++i) {
5473 RetVals.push_back(RegisterVT);
5474 ISD::ArgFlagsTy MyFlags = Flags;
5475 if (NumRegs > 1 && i == 0)
5477 // if it isn't first piece, alignment must be 1
5479 MyFlags.setOrigAlign(1);
5480 Ops.push_back(DAG.getArgFlags(MyFlags));
5485 RetVals.push_back(MVT::Other);
5488 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5489 DAG.getVTList(&RetVals[0], RetVals.size()),
5490 &Ops[0], Ops.size()).getNode();
5492 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5493 // allows exposing the loads that may be part of the argument access to the
5494 // first DAGCombiner pass.
5495 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5497 // The number of results should match up, except that the lowered one may have
5498 // an extra flag result.
5499 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5500 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5501 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5502 && "Lowering produced unexpected number of results!");
5504 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5505 if (Result != TmpRes.getNode() && Result->use_empty()) {
5506 HandleSDNode Dummy(DAG.getRoot());
5507 DAG.RemoveDeadNode(Result);
5510 Result = TmpRes.getNode();
5512 unsigned NumArgRegs = Result->getNumValues() - 1;
5513 DAG.setRoot(SDValue(Result, NumArgRegs));
5515 // Set up the return result vector.
5518 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5520 SmallVector<MVT, 4> ValueVTs;
5521 ComputeValueVTs(*this, I->getType(), ValueVTs);
5522 for (unsigned Value = 0, NumValues = ValueVTs.size();
5523 Value != NumValues; ++Value) {
5524 MVT VT = ValueVTs[Value];
5525 MVT PartVT = getRegisterType(VT);
5527 unsigned NumParts = getNumRegisters(VT);
5528 SmallVector<SDValue, 4> Parts(NumParts);
5529 for (unsigned j = 0; j != NumParts; ++j)
5530 Parts[j] = SDValue(Result, i++);
5532 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5533 if (F.paramHasAttr(Idx, Attribute::SExt))
5534 AssertOp = ISD::AssertSext;
5535 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5536 AssertOp = ISD::AssertZext;
5538 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5539 PartVT, VT, AssertOp));
5542 assert(i == NumArgRegs && "Argument register count mismatch!");
5546 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5547 /// implementation, which just inserts an ISD::CALL node, which is later custom
5548 /// lowered by the target to something concrete. FIXME: When all targets are
5549 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5550 std::pair<SDValue, SDValue>
5551 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5552 bool RetSExt, bool RetZExt, bool isVarArg,
5554 unsigned CallingConv, bool isTailCall,
5556 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5557 assert((!isTailCall || PerformTailCallOpt) &&
5558 "isTailCall set when tail-call optimizations are disabled!");
5560 SmallVector<SDValue, 32> Ops;
5561 Ops.push_back(Chain); // Op#0 - Chain
5562 Ops.push_back(Callee);
5564 // Handle all of the outgoing arguments.
5565 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5566 SmallVector<MVT, 4> ValueVTs;
5567 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5568 for (unsigned Value = 0, NumValues = ValueVTs.size();
5569 Value != NumValues; ++Value) {
5570 MVT VT = ValueVTs[Value];
5571 const Type *ArgTy = VT.getTypeForMVT();
5572 SDValue Op = SDValue(Args[i].Node.getNode(),
5573 Args[i].Node.getResNo() + Value);
5574 ISD::ArgFlagsTy Flags;
5575 unsigned OriginalAlignment =
5576 getTargetData()->getABITypeAlignment(ArgTy);
5582 if (Args[i].isInReg)
5586 if (Args[i].isByVal) {
5588 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5589 const Type *ElementTy = Ty->getElementType();
5590 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5591 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5592 // For ByVal, alignment should come from FE. BE will guess if this
5593 // info is not there but there are cases it cannot get right.
5594 if (Args[i].Alignment)
5595 FrameAlign = Args[i].Alignment;
5596 Flags.setByValAlign(FrameAlign);
5597 Flags.setByValSize(FrameSize);
5601 Flags.setOrigAlign(OriginalAlignment);
5603 MVT PartVT = getRegisterType(VT);
5604 unsigned NumParts = getNumRegisters(VT);
5605 SmallVector<SDValue, 4> Parts(NumParts);
5606 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5609 ExtendKind = ISD::SIGN_EXTEND;
5610 else if (Args[i].isZExt)
5611 ExtendKind = ISD::ZERO_EXTEND;
5613 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5615 for (unsigned i = 0; i != NumParts; ++i) {
5616 // if it isn't first piece, alignment must be 1
5617 ISD::ArgFlagsTy MyFlags = Flags;
5618 if (NumParts > 1 && i == 0)
5621 MyFlags.setOrigAlign(1);
5623 Ops.push_back(Parts[i]);
5624 Ops.push_back(DAG.getArgFlags(MyFlags));
5629 // Figure out the result value types. We start by making a list of
5630 // the potentially illegal return value types.
5631 SmallVector<MVT, 4> LoweredRetTys;
5632 SmallVector<MVT, 4> RetTys;
5633 ComputeValueVTs(*this, RetTy, RetTys);
5635 // Then we translate that to a list of legal types.
5636 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5638 MVT RegisterVT = getRegisterType(VT);
5639 unsigned NumRegs = getNumRegisters(VT);
5640 for (unsigned i = 0; i != NumRegs; ++i)
5641 LoweredRetTys.push_back(RegisterVT);
5644 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5646 // Create the CALL node.
5647 SDValue Res = DAG.getCall(CallingConv, dl,
5648 isVarArg, isTailCall, isInreg,
5649 DAG.getVTList(&LoweredRetTys[0],
5650 LoweredRetTys.size()),
5653 Chain = Res.getValue(LoweredRetTys.size() - 1);
5655 // Gather up the call result into a single value.
5656 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5657 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5660 AssertOp = ISD::AssertSext;
5662 AssertOp = ISD::AssertZext;
5664 SmallVector<SDValue, 4> ReturnValues;
5666 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5668 MVT RegisterVT = getRegisterType(VT);
5669 unsigned NumRegs = getNumRegisters(VT);
5670 unsigned RegNoEnd = NumRegs + RegNo;
5671 SmallVector<SDValue, 4> Results;
5672 for (; RegNo != RegNoEnd; ++RegNo)
5673 Results.push_back(Res.getValue(RegNo));
5674 SDValue ReturnValue =
5675 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5677 ReturnValues.push_back(ReturnValue);
5679 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5680 DAG.getVTList(&RetTys[0], RetTys.size()),
5681 &ReturnValues[0], ReturnValues.size());
5684 return std::make_pair(Res, Chain);
5687 void TargetLowering::LowerOperationWrapper(SDNode *N,
5688 SmallVectorImpl<SDValue> &Results,
5689 SelectionDAG &DAG) {
5690 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5692 Results.push_back(Res);
5695 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5696 assert(0 && "LowerOperation not implemented for this target!");
5702 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5703 SDValue Op = getValue(V);
5704 assert((Op.getOpcode() != ISD::CopyFromReg ||
5705 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5706 "Copy from a reg to the same reg!");
5707 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5709 RegsForValue RFV(TLI, Reg, V->getType());
5710 SDValue Chain = DAG.getEntryNode();
5711 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5712 PendingExports.push_back(Chain);
5715 #include "llvm/CodeGen/SelectionDAGISel.h"
5717 void SelectionDAGISel::
5718 LowerArguments(BasicBlock *LLVMBB) {
5719 // If this is the entry block, emit arguments.
5720 Function &F = *LLVMBB->getParent();
5721 SDValue OldRoot = SDL->DAG.getRoot();
5722 SmallVector<SDValue, 16> Args;
5723 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5726 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5728 SmallVector<MVT, 4> ValueVTs;
5729 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5730 unsigned NumValues = ValueVTs.size();
5731 if (!AI->use_empty()) {
5732 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5733 // If this argument is live outside of the entry block, insert a copy from
5734 // whereever we got it to the vreg that other BB's will reference it as.
5735 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5736 if (VMI != FuncInfo->ValueMap.end()) {
5737 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5743 // Finally, if the target has anything special to do, allow it to do so.
5744 // FIXME: this should insert code into the DAG!
5745 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5748 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5749 /// ensure constants are generated when needed. Remember the virtual registers
5750 /// that need to be added to the Machine PHI nodes as input. We cannot just
5751 /// directly add them, because expansion might result in multiple MBB's for one
5752 /// BB. As such, the start of the BB might correspond to a different MBB than
5756 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5757 TerminatorInst *TI = LLVMBB->getTerminator();
5759 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5761 // Check successor nodes' PHI nodes that expect a constant to be available
5763 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5764 BasicBlock *SuccBB = TI->getSuccessor(succ);
5765 if (!isa<PHINode>(SuccBB->begin())) continue;
5766 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5768 // If this terminator has multiple identical successors (common for
5769 // switches), only handle each succ once.
5770 if (!SuccsHandled.insert(SuccMBB)) continue;
5772 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5775 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5776 // nodes and Machine PHI nodes, but the incoming operands have not been
5778 for (BasicBlock::iterator I = SuccBB->begin();
5779 (PN = dyn_cast<PHINode>(I)); ++I) {
5780 // Ignore dead phi's.
5781 if (PN->use_empty()) continue;
5784 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5786 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5787 unsigned &RegOut = SDL->ConstantsOut[C];
5789 RegOut = FuncInfo->CreateRegForValue(C);
5790 SDL->CopyValueToVirtualRegister(C, RegOut);
5794 Reg = FuncInfo->ValueMap[PHIOp];
5796 assert(isa<AllocaInst>(PHIOp) &&
5797 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5798 "Didn't codegen value into a register!??");
5799 Reg = FuncInfo->CreateRegForValue(PHIOp);
5800 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5804 // Remember that this register needs to added to the machine PHI node as
5805 // the input for this MBB.
5806 SmallVector<MVT, 4> ValueVTs;
5807 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5808 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5809 MVT VT = ValueVTs[vti];
5810 unsigned NumRegisters = TLI.getNumRegisters(VT);
5811 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5812 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5813 Reg += NumRegisters;
5817 SDL->ConstantsOut.clear();
5820 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5821 /// supports legal types, and it emits MachineInstrs directly instead of
5822 /// creating SelectionDAG nodes.
5825 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5827 TerminatorInst *TI = LLVMBB->getTerminator();
5829 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5830 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5832 // Check successor nodes' PHI nodes that expect a constant to be available
5834 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5835 BasicBlock *SuccBB = TI->getSuccessor(succ);
5836 if (!isa<PHINode>(SuccBB->begin())) continue;
5837 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5839 // If this terminator has multiple identical successors (common for
5840 // switches), only handle each succ once.
5841 if (!SuccsHandled.insert(SuccMBB)) continue;
5843 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5846 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5847 // nodes and Machine PHI nodes, but the incoming operands have not been
5849 for (BasicBlock::iterator I = SuccBB->begin();
5850 (PN = dyn_cast<PHINode>(I)); ++I) {
5851 // Ignore dead phi's.
5852 if (PN->use_empty()) continue;
5854 // Only handle legal types. Two interesting things to note here. First,
5855 // by bailing out early, we may leave behind some dead instructions,
5856 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5857 // own moves. Second, this check is necessary becuase FastISel doesn't
5858 // use CreateRegForValue to create registers, so it always creates
5859 // exactly one register for each non-void instruction.
5860 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5861 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5864 VT = TLI.getTypeToTransformTo(VT);
5866 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5871 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5873 unsigned Reg = F->getRegForValue(PHIOp);
5875 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5878 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));