1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/InlineAsm.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "llvm/CodeGen/MachineModuleInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/CodeGen/DwarfWriter.h"
42 #include "llvm/Analysis/DebugInfo.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetFrameInfo.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetLowering.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
59 /// LimitFloatPrecision - Generate low-precision inline sequences for
60 /// some float libcalls (6, 8 or 12 bits).
61 static unsigned LimitFloatPrecision;
63 static cl::opt<unsigned, true>
64 LimitFPPrecision("limit-float-precision",
65 cl::desc("Generate low-precision inline sequences "
66 "for some float libcalls"),
67 cl::location(LimitFloatPrecision),
70 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
71 /// of insertvalue or extractvalue indices that identify a member, return
72 /// the linearized index of the start of the member.
74 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
75 const unsigned *Indices,
76 const unsigned *IndicesEnd,
77 unsigned CurIndex = 0) {
78 // Base case: We're done.
79 if (Indices && Indices == IndicesEnd)
82 // Given a struct type, recursively traverse the elements.
83 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
84 for (StructType::element_iterator EB = STy->element_begin(),
86 EE = STy->element_end();
88 if (Indices && *Indices == unsigned(EI - EB))
89 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
90 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
94 // Given an array type, recursively traverse the elements.
95 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
96 const Type *EltTy = ATy->getElementType();
97 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
98 if (Indices && *Indices == i)
99 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
100 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
104 // We haven't found the type we're looking for, so keep searching.
108 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
109 /// EVTs that represent all the individual underlying
110 /// non-aggregate types that comprise it.
112 /// If Offsets is non-null, it points to a vector to be filled in
113 /// with the in-memory offsets of each of the individual values.
115 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
116 SmallVectorImpl<EVT> &ValueVTs,
117 SmallVectorImpl<uint64_t> *Offsets = 0,
118 uint64_t StartingOffset = 0) {
119 // Given a struct type, recursively traverse the elements.
120 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
121 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
122 for (StructType::element_iterator EB = STy->element_begin(),
124 EE = STy->element_end();
126 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
127 StartingOffset + SL->getElementOffset(EI - EB));
130 // Given an array type, recursively traverse the elements.
131 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
132 const Type *EltTy = ATy->getElementType();
133 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
134 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
135 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
136 StartingOffset + i * EltSize);
139 // Interpret void as zero return values.
140 if (Ty == Type::getVoidTy(Ty->getContext()))
142 // Base case: we can get an EVT for this LLVM IR type.
143 ValueVTs.push_back(TLI.getValueType(Ty));
145 Offsets->push_back(StartingOffset);
149 /// RegsForValue - This struct represents the registers (physical or virtual)
150 /// that a particular set of values is assigned, and the type information about
151 /// the value. The most common situation is to represent one value at a time,
152 /// but struct or array values are handled element-wise as multiple values.
153 /// The splitting of aggregates is performed recursively, so that we never
154 /// have aggregate-typed registers. The values at this point do not necessarily
155 /// have legal types, so each value may require one or more registers of some
158 struct VISIBILITY_HIDDEN RegsForValue {
159 /// TLI - The TargetLowering object.
161 const TargetLowering *TLI;
163 /// ValueVTs - The value types of the values, which may not be legal, and
164 /// may need be promoted or synthesized from one or more registers.
166 SmallVector<EVT, 4> ValueVTs;
168 /// RegVTs - The value types of the registers. This is the same size as
169 /// ValueVTs and it records, for each value, what the type of the assigned
170 /// register or registers are. (Individual values are never synthesized
171 /// from more than one type of register.)
173 /// With virtual registers, the contents of RegVTs is redundant with TLI's
174 /// getRegisterType member function, however when with physical registers
175 /// it is necessary to have a separate record of the types.
177 SmallVector<EVT, 4> RegVTs;
179 /// Regs - This list holds the registers assigned to the values.
180 /// Each legal or promoted value requires one register, and each
181 /// expanded value requires multiple registers.
183 SmallVector<unsigned, 4> Regs;
185 RegsForValue() : TLI(0) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> ®s,
189 EVT regvt, EVT valuevt)
190 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 const SmallVector<unsigned, 4> ®s,
193 const SmallVector<EVT, 4> ®vts,
194 const SmallVector<EVT, 4> &valuevts)
195 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
196 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
197 unsigned Reg, const Type *Ty) : TLI(&tli) {
198 ComputeValueVTs(tli, Ty, ValueVTs);
200 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
201 EVT ValueVT = ValueVTs[Value];
202 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
203 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
204 for (unsigned i = 0; i != NumRegs; ++i)
205 Regs.push_back(Reg + i);
206 RegVTs.push_back(RegisterVT);
211 /// append - Add the specified values to this one.
212 void append(const RegsForValue &RHS) {
214 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
215 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
216 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
220 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
221 /// this value and returns the result as a ValueVTs value. This uses
222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
223 /// If the Flag pointer is NULL, no flag is used.
224 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
225 SDValue &Chain, SDValue *Flag) const;
227 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
228 /// specified value into the registers specified by this object. This uses
229 /// Chain/Flag as the input and updates them for the output Chain/Flag.
230 /// If the Flag pointer is NULL, no flag is used.
231 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
232 SDValue &Chain, SDValue *Flag) const;
234 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
235 /// operand list. This adds the code marker, matching input operand index
236 /// (if applicable), and includes the number of values added into it.
237 void AddInlineAsmOperands(unsigned Code,
238 bool HasMatching, unsigned MatchingIdx,
239 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
243 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
244 /// PHI nodes or outside of the basic block that defines it, or used by a
245 /// switch or atomic instruction, which may expand to multiple basic blocks.
246 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
247 if (isa<PHINode>(I)) return true;
248 BasicBlock *BB = I->getParent();
249 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
250 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
255 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
256 /// entry block, return true. This includes arguments used by switches, since
257 /// the switch may expand into multiple basic blocks.
258 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
259 // With FastISel active, we may be splitting blocks, so force creation
260 // of virtual registers for all non-dead arguments.
261 // Don't force virtual registers for byval arguments though, because
262 // fast-isel can't handle those in all cases.
263 if (EnableFastISel && !A->hasByValAttr())
264 return A->use_empty();
266 BasicBlock *Entry = A->getParent()->begin();
267 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
268 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
269 return false; // Use not in entry block.
273 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
277 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
279 bool EnableFastISel) {
282 RegInfo = &MF->getRegInfo();
284 // Create a vreg for each argument register that is not dead and is used
285 // outside of the entry block for the function.
286 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
288 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
289 InitializeRegForValue(AI);
291 // Initialize the mapping of values to registers. This is only set up for
292 // instruction values that are used outside of the block that defines
294 Function::iterator BB = Fn->begin(), EB = Fn->end();
295 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
296 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
297 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
298 const Type *Ty = AI->getAllocatedType();
299 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
301 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
304 TySize *= CUI->getZExtValue(); // Get total allocated size.
305 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
306 StaticAllocaMap[AI] =
307 MF->getFrameInfo()->CreateStackObject(TySize, Align);
310 for (; BB != EB; ++BB)
311 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
312 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
313 if (!isa<AllocaInst>(I) ||
314 !StaticAllocaMap.count(cast<AllocaInst>(I)))
315 InitializeRegForValue(I);
317 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
318 // also creates the initial PHI MachineInstrs, though none of the input
319 // operands are populated.
320 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
321 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
325 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
329 for (BasicBlock::iterator
330 I = BB->begin(), E = BB->end(); I != E; ++I) {
331 if (CallInst *CI = dyn_cast<CallInst>(I)) {
332 if (Function *F = CI->getCalledFunction()) {
333 switch (F->getIntrinsicID()) {
335 case Intrinsic::dbg_stoppoint: {
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
337 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
338 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
341 case Intrinsic::dbg_func_start: {
342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
343 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
344 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
351 PN = dyn_cast<PHINode>(I);
352 if (!PN || PN->use_empty()) continue;
354 unsigned PHIReg = ValueMap[PN];
355 assert(PHIReg && "PHI node does not have an assigned virtual register!");
357 SmallVector<EVT, 4> ValueVTs;
358 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
359 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
360 EVT VT = ValueVTs[vti];
361 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
362 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
363 for (unsigned i = 0; i != NumRegisters; ++i)
364 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
365 PHIReg += NumRegisters;
371 unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
372 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<EVT, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 EVT ValueVT = ValueVTs[Value];
389 EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
400 /// getCopyFromParts - Create a value that contains the specified legal parts
401 /// combined into the value they represent. If the parts combine to a type
402 /// larger then ValueVT then AssertOp can be used to specify whether the extra
403 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
404 /// (ISD::AssertSext).
405 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
406 const SDValue *Parts,
407 unsigned NumParts, EVT PartVT, EVT ValueVT,
408 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
409 assert(NumParts > 0 && "No parts to assemble!");
410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411 SDValue Val = Parts[0];
414 // Assemble the value from multiple parts.
415 if (!ValueVT.isVector() && ValueVT.isInteger()) {
416 unsigned PartBits = PartVT.getSizeInBits();
417 unsigned ValueBits = ValueVT.getSizeInBits();
419 // Assemble the power of 2 part.
420 unsigned RoundParts = NumParts & (NumParts - 1) ?
421 1 << Log2_32(NumParts) : NumParts;
422 unsigned RoundBits = PartBits * RoundParts;
423 EVT RoundVT = RoundBits == ValueBits ?
424 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
427 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
429 if (RoundParts > 2) {
430 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
431 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
434 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
435 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
437 if (TLI.isBigEndian())
439 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
441 if (RoundParts < NumParts) {
442 // Assemble the trailing non-power-of-2 part.
443 unsigned OddParts = NumParts - RoundParts;
444 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
445 Hi = getCopyFromParts(DAG, dl,
446 Parts+RoundParts, OddParts, PartVT, OddVT);
448 // Combine the round and odd parts.
450 if (TLI.isBigEndian())
452 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
453 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
454 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
455 DAG.getConstant(Lo.getValueType().getSizeInBits(),
456 TLI.getPointerTy()));
457 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
458 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
460 } else if (ValueVT.isVector()) {
461 // Handle a multi-element vector.
462 EVT IntermediateVT, RegisterVT;
463 unsigned NumIntermediates;
465 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
466 NumIntermediates, RegisterVT);
467 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
468 NumParts = NumRegs; // Silence a compiler warning.
469 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
470 assert(RegisterVT == Parts[0].getValueType() &&
471 "Part type doesn't match part!");
473 // Assemble the parts into intermediate operands.
474 SmallVector<SDValue, 8> Ops(NumIntermediates);
475 if (NumIntermediates == NumParts) {
476 // If the register was not expanded, truncate or copy the value,
478 for (unsigned i = 0; i != NumParts; ++i)
479 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
480 PartVT, IntermediateVT);
481 } else if (NumParts > 0) {
482 // If the intermediate type was expanded, build the intermediate operands
484 assert(NumParts % NumIntermediates == 0 &&
485 "Must expand into a divisible number of parts!");
486 unsigned Factor = NumParts / NumIntermediates;
487 for (unsigned i = 0; i != NumIntermediates; ++i)
488 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
489 PartVT, IntermediateVT);
492 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
494 Val = DAG.getNode(IntermediateVT.isVector() ?
495 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
496 ValueVT, &Ops[0], NumIntermediates);
497 } else if (PartVT.isFloatingPoint()) {
498 // FP split into multiple FP parts (for ppcf128)
499 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
502 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
503 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
504 if (TLI.isBigEndian())
506 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
508 // FP split into integer parts (soft fp)
509 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
510 !PartVT.isVector() && "Unexpected split");
511 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
512 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
516 // There is now one part, held in Val. Correct it to match ValueVT.
517 PartVT = Val.getValueType();
519 if (PartVT == ValueVT)
522 if (PartVT.isVector()) {
523 assert(ValueVT.isVector() && "Unknown vector conversion!");
524 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
527 if (ValueVT.isVector()) {
528 assert(ValueVT.getVectorElementType() == PartVT &&
529 ValueVT.getVectorNumElements() == 1 &&
530 "Only trivial scalar-to-vector conversions should get here!");
531 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
534 if (PartVT.isInteger() &&
535 ValueVT.isInteger()) {
536 if (ValueVT.bitsLT(PartVT)) {
537 // For a truncate, see if we have any information to
538 // indicate whether the truncated bits will always be
539 // zero or sign-extension.
540 if (AssertOp != ISD::DELETED_NODE)
541 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
542 DAG.getValueType(ValueVT));
543 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
545 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
549 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
550 if (ValueVT.bitsLT(Val.getValueType()))
551 // FP_ROUND's are always exact here.
552 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
553 DAG.getIntPtrConstant(1));
554 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
557 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
558 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
560 llvm_unreachable("Unknown mismatch!");
564 /// getCopyToParts - Create a series of nodes that contain the specified value
565 /// split into legal parts. If the parts contain more bits than Val, then, for
566 /// integers, ExtendKind can be used to specify how to generate the extra bits.
567 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
568 SDValue *Parts, unsigned NumParts, EVT PartVT,
569 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
571 EVT PtrVT = TLI.getPointerTy();
572 EVT ValueVT = Val.getValueType();
573 unsigned PartBits = PartVT.getSizeInBits();
574 unsigned OrigNumParts = NumParts;
575 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
580 if (!ValueVT.isVector()) {
581 if (PartVT == ValueVT) {
582 assert(NumParts == 1 && "No-op copy with multiple parts!");
587 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
588 // If the parts cover more bits than the value has, promote the value.
589 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
590 assert(NumParts == 1 && "Do not know what to promote to!");
591 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
592 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
593 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
594 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
596 llvm_unreachable("Unknown mismatch!");
598 } else if (PartBits == ValueVT.getSizeInBits()) {
599 // Different types of the same size.
600 assert(NumParts == 1 && PartVT != ValueVT);
601 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
602 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
603 // If the parts cover less bits than value has, truncate the value.
604 if (PartVT.isInteger() && ValueVT.isInteger()) {
605 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
606 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
608 llvm_unreachable("Unknown mismatch!");
612 // The value may have changed - recompute ValueVT.
613 ValueVT = Val.getValueType();
614 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
615 "Failed to tile the value with PartVT!");
618 assert(PartVT == ValueVT && "Type conversion failed!");
623 // Expand the value into multiple parts.
624 if (NumParts & (NumParts - 1)) {
625 // The number of parts is not a power of 2. Split off and copy the tail.
626 assert(PartVT.isInteger() && ValueVT.isInteger() &&
627 "Do not know what to expand to!");
628 unsigned RoundParts = 1 << Log2_32(NumParts);
629 unsigned RoundBits = RoundParts * PartBits;
630 unsigned OddParts = NumParts - RoundParts;
631 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
632 DAG.getConstant(RoundBits,
633 TLI.getPointerTy()));
634 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
635 if (TLI.isBigEndian())
636 // The odd parts were reversed by getCopyToParts - unreverse them.
637 std::reverse(Parts + RoundParts, Parts + NumParts);
638 NumParts = RoundParts;
639 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
640 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
643 // The number of parts is a power of 2. Repeatedly bisect the value using
645 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
646 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()),
648 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
649 for (unsigned i = 0; i < NumParts; i += StepSize) {
650 unsigned ThisBits = StepSize * PartBits / 2;
651 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
652 SDValue &Part0 = Parts[i];
653 SDValue &Part1 = Parts[i+StepSize/2];
655 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
657 DAG.getConstant(1, PtrVT));
658 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(0, PtrVT));
662 if (ThisBits == PartBits && ThisVT != PartVT) {
663 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
665 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
671 if (TLI.isBigEndian())
672 std::reverse(Parts, Parts + OrigNumParts);
679 if (PartVT != ValueVT) {
680 if (PartVT.isVector()) {
681 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
683 assert(ValueVT.getVectorElementType() == PartVT &&
684 ValueVT.getVectorNumElements() == 1 &&
685 "Only trivial vector-to-scalar conversions should get here!");
686 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
688 DAG.getConstant(0, PtrVT));
696 // Handle a multi-element vector.
697 EVT IntermediateVT, RegisterVT;
698 unsigned NumIntermediates;
699 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
700 IntermediateVT, NumIntermediates, RegisterVT);
701 unsigned NumElements = ValueVT.getVectorNumElements();
703 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
704 NumParts = NumRegs; // Silence a compiler warning.
705 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
707 // Split the vector into intermediate operands.
708 SmallVector<SDValue, 8> Ops(NumIntermediates);
709 for (unsigned i = 0; i != NumIntermediates; ++i)
710 if (IntermediateVT.isVector())
711 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
713 DAG.getConstant(i * (NumElements / NumIntermediates),
716 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
718 DAG.getConstant(i, PtrVT));
720 // Split the intermediate operands into legal parts.
721 if (NumParts == NumIntermediates) {
722 // If the register was not expanded, promote or copy the value,
724 for (unsigned i = 0; i != NumParts; ++i)
725 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
726 } else if (NumParts > 0) {
727 // If the intermediate type was expanded, split each the value into
729 assert(NumParts % NumIntermediates == 0 &&
730 "Must expand into a divisible number of parts!");
731 unsigned Factor = NumParts / NumIntermediates;
732 for (unsigned i = 0; i != NumIntermediates; ++i)
733 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
738 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
741 TD = DAG.getTarget().getTargetData();
744 /// clear - Clear out the curret SelectionDAG and the associated
745 /// state and prepare this SelectionDAGLowering object to be used
746 /// for a new block. This doesn't clear out information about
747 /// additional blocks that are needed to complete switch lowering
748 /// or PHI node updating; that information is cleared out as it is
750 void SelectionDAGLowering::clear() {
752 PendingLoads.clear();
753 PendingExports.clear();
755 CurDebugLoc = DebugLoc::getUnknownLoc();
759 /// getRoot - Return the current virtual root of the Selection DAG,
760 /// flushing any PendingLoad items. This must be done before emitting
761 /// a store or any other node that may need to be ordered after any
762 /// prior load instructions.
764 SDValue SelectionDAGLowering::getRoot() {
765 if (PendingLoads.empty())
766 return DAG.getRoot();
768 if (PendingLoads.size() == 1) {
769 SDValue Root = PendingLoads[0];
771 PendingLoads.clear();
775 // Otherwise, we have to make a token factor node.
776 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
777 &PendingLoads[0], PendingLoads.size());
778 PendingLoads.clear();
783 /// getControlRoot - Similar to getRoot, but instead of flushing all the
784 /// PendingLoad items, flush all the PendingExports items. It is necessary
785 /// to do this before emitting a terminator instruction.
787 SDValue SelectionDAGLowering::getControlRoot() {
788 SDValue Root = DAG.getRoot();
790 if (PendingExports.empty())
793 // Turn all of the CopyToReg chains into one factored node.
794 if (Root.getOpcode() != ISD::EntryToken) {
795 unsigned i = 0, e = PendingExports.size();
796 for (; i != e; ++i) {
797 assert(PendingExports[i].getNode()->getNumOperands() > 1);
798 if (PendingExports[i].getNode()->getOperand(0) == Root)
799 break; // Don't add the root if we already indirectly depend on it.
803 PendingExports.push_back(Root);
806 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
808 PendingExports.size());
809 PendingExports.clear();
814 void SelectionDAGLowering::visit(Instruction &I) {
815 visit(I.getOpcode(), I);
818 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
819 // Note: this doesn't use InstVisitor, because it has to work with
820 // ConstantExpr's in addition to instructions.
822 default: llvm_unreachable("Unknown instruction type encountered!");
823 // Build the switch statement using the Instruction.def file.
824 #define HANDLE_INST(NUM, OPCODE, CLASS) \
825 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
826 #include "llvm/Instruction.def"
830 SDValue SelectionDAGLowering::getValue(const Value *V) {
831 SDValue &N = NodeMap[V];
832 if (N.getNode()) return N;
834 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
835 EVT VT = TLI.getValueType(V->getType(), true);
837 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
838 return N = DAG.getConstant(*CI, VT);
840 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
841 return N = DAG.getGlobalAddress(GV, VT);
843 if (isa<ConstantPointerNull>(C))
844 return N = DAG.getConstant(0, TLI.getPointerTy());
846 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
847 return N = DAG.getConstantFP(*CFP, VT);
849 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
850 return N = DAG.getUNDEF(VT);
852 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
853 visit(CE->getOpcode(), *CE);
854 SDValue N1 = NodeMap[V];
855 assert(N1.getNode() && "visit didn't populate the ValueMap!");
859 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
860 SmallVector<SDValue, 4> Constants;
861 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
863 SDNode *Val = getValue(*OI).getNode();
864 // If the operand is an empty aggregate, there are no values.
866 // Add each leaf value from the operand to the Constants list
867 // to form a flattened list of all the values.
868 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
869 Constants.push_back(SDValue(Val, i));
871 return DAG.getMergeValues(&Constants[0], Constants.size(),
875 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
876 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
877 "Unknown struct or array constant!");
879 SmallVector<EVT, 4> ValueVTs;
880 ComputeValueVTs(TLI, C->getType(), ValueVTs);
881 unsigned NumElts = ValueVTs.size();
883 return SDValue(); // empty struct
884 SmallVector<SDValue, 4> Constants(NumElts);
885 for (unsigned i = 0; i != NumElts; ++i) {
886 EVT EltVT = ValueVTs[i];
887 if (isa<UndefValue>(C))
888 Constants[i] = DAG.getUNDEF(EltVT);
889 else if (EltVT.isFloatingPoint())
890 Constants[i] = DAG.getConstantFP(0, EltVT);
892 Constants[i] = DAG.getConstant(0, EltVT);
894 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
897 const VectorType *VecTy = cast<VectorType>(V->getType());
898 unsigned NumElements = VecTy->getNumElements();
900 // Now that we know the number and type of the elements, get that number of
901 // elements into the Ops array based on what kind of constant it is.
902 SmallVector<SDValue, 16> Ops;
903 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
904 for (unsigned i = 0; i != NumElements; ++i)
905 Ops.push_back(getValue(CP->getOperand(i)));
907 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
908 EVT EltVT = TLI.getValueType(VecTy->getElementType());
911 if (EltVT.isFloatingPoint())
912 Op = DAG.getConstantFP(0, EltVT);
914 Op = DAG.getConstant(0, EltVT);
915 Ops.assign(NumElements, Op);
918 // Create a BUILD_VECTOR node.
919 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
920 VT, &Ops[0], Ops.size());
923 // If this is a static alloca, generate it as the frameindex instead of
925 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
926 DenseMap<const AllocaInst*, int>::iterator SI =
927 FuncInfo.StaticAllocaMap.find(AI);
928 if (SI != FuncInfo.StaticAllocaMap.end())
929 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
932 unsigned InReg = FuncInfo.ValueMap[V];
933 assert(InReg && "Value not in map!");
935 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
936 SDValue Chain = DAG.getEntryNode();
937 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
941 void SelectionDAGLowering::visitRet(ReturnInst &I) {
942 SDValue Chain = getControlRoot();
943 SmallVector<ISD::OutputArg, 8> Outs;
944 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
945 SmallVector<EVT, 4> ValueVTs;
946 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
947 unsigned NumValues = ValueVTs.size();
948 if (NumValues == 0) continue;
950 SDValue RetOp = getValue(I.getOperand(i));
951 for (unsigned j = 0, f = NumValues; j != f; ++j) {
952 EVT VT = ValueVTs[j];
954 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
956 const Function *F = I.getParent()->getParent();
957 if (F->paramHasAttr(0, Attribute::SExt))
958 ExtendKind = ISD::SIGN_EXTEND;
959 else if (F->paramHasAttr(0, Attribute::ZExt))
960 ExtendKind = ISD::ZERO_EXTEND;
962 // FIXME: C calling convention requires the return type to be promoted to
963 // at least 32-bit. But this is not necessary for non-C calling
964 // conventions. The frontend should mark functions whose return values
965 // require promoting with signext or zeroext attributes.
966 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
967 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
968 if (VT.bitsLT(MinVT))
972 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
973 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
974 SmallVector<SDValue, 4> Parts(NumParts);
975 getCopyToParts(DAG, getCurDebugLoc(),
976 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
977 &Parts[0], NumParts, PartVT, ExtendKind);
979 // 'inreg' on function refers to return value
980 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
981 if (F->paramHasAttr(0, Attribute::InReg))
984 // Propagate extension type if any
985 if (F->paramHasAttr(0, Attribute::SExt))
987 else if (F->paramHasAttr(0, Attribute::ZExt))
990 for (unsigned i = 0; i < NumParts; ++i)
991 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
995 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
996 CallingConv::ID CallConv =
997 DAG.getMachineFunction().getFunction()->getCallingConv();
998 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
999 Outs, getCurDebugLoc(), DAG);
1001 // Verify that the target's LowerReturn behaved as expected.
1002 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1003 "LowerReturn didn't return a valid chain!");
1005 // Update the DAG with the new chain value resulting from return lowering.
1009 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1010 /// created for it, emit nodes to copy the value into the virtual
1012 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1013 if (!V->use_empty()) {
1014 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1015 if (VMI != FuncInfo.ValueMap.end())
1016 CopyValueToVirtualRegister(V, VMI->second);
1020 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1021 /// the current basic block, add it to ValueMap now so that we'll get a
1023 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1024 // No need to export constants.
1025 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1027 // Already exported?
1028 if (FuncInfo.isExportedInst(V)) return;
1030 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1031 CopyValueToVirtualRegister(V, Reg);
1034 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1035 const BasicBlock *FromBB) {
1036 // The operands of the setcc have to be in this block. We don't know
1037 // how to export them from some other block.
1038 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1039 // Can export from current BB.
1040 if (VI->getParent() == FromBB)
1043 // Is already exported, noop.
1044 return FuncInfo.isExportedInst(V);
1047 // If this is an argument, we can export it if the BB is the entry block or
1048 // if it is already exported.
1049 if (isa<Argument>(V)) {
1050 if (FromBB == &FromBB->getParent()->getEntryBlock())
1053 // Otherwise, can only export this if it is already exported.
1054 return FuncInfo.isExportedInst(V);
1057 // Otherwise, constants can always be exported.
1061 static bool InBlock(const Value *V, const BasicBlock *BB) {
1062 if (const Instruction *I = dyn_cast<Instruction>(V))
1063 return I->getParent() == BB;
1067 /// getFCmpCondCode - Return the ISD condition code corresponding to
1068 /// the given LLVM IR floating-point condition code. This includes
1069 /// consideration of global floating-point math flags.
1071 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1072 ISD::CondCode FPC, FOC;
1074 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1075 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1076 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1077 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1078 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1079 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1080 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1081 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1082 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1083 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1084 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1085 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1086 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1087 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1088 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1089 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1091 llvm_unreachable("Invalid FCmp predicate opcode!");
1092 FOC = FPC = ISD::SETFALSE;
1095 if (FiniteOnlyFPMath())
1101 /// getICmpCondCode - Return the ISD condition code corresponding to
1102 /// the given LLVM IR integer condition code.
1104 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1106 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1107 case ICmpInst::ICMP_NE: return ISD::SETNE;
1108 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1109 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1110 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1111 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1112 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1113 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1114 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1115 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1117 llvm_unreachable("Invalid ICmp predicate opcode!");
1122 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1123 /// This function emits a branch and is used at the leaves of an OR or an
1124 /// AND operator tree.
1127 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1128 MachineBasicBlock *TBB,
1129 MachineBasicBlock *FBB,
1130 MachineBasicBlock *CurBB) {
1131 const BasicBlock *BB = CurBB->getBasicBlock();
1133 // If the leaf of the tree is a comparison, merge the condition into
1135 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1136 // The operands of the cmp have to be in this block. We don't know
1137 // how to export them from some other block. If this is the first block
1138 // of the sequence, no exporting is needed.
1139 if (CurBB == CurMBB ||
1140 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1141 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1142 ISD::CondCode Condition;
1143 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1144 Condition = getICmpCondCode(IC->getPredicate());
1145 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1146 Condition = getFCmpCondCode(FC->getPredicate());
1148 Condition = ISD::SETEQ; // silence warning.
1149 llvm_unreachable("Unknown compare instruction");
1152 CaseBlock CB(Condition, BOp->getOperand(0),
1153 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1154 SwitchCases.push_back(CB);
1159 // Create a CaseBlock record representing this branch.
1160 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1161 NULL, TBB, FBB, CurBB);
1162 SwitchCases.push_back(CB);
1165 /// FindMergedConditions - If Cond is an expression like
1166 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1167 MachineBasicBlock *TBB,
1168 MachineBasicBlock *FBB,
1169 MachineBasicBlock *CurBB,
1171 // If this node is not part of the or/and tree, emit it as a branch.
1172 Instruction *BOp = dyn_cast<Instruction>(Cond);
1173 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1174 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1175 BOp->getParent() != CurBB->getBasicBlock() ||
1176 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1177 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1178 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1182 // Create TmpBB after CurBB.
1183 MachineFunction::iterator BBI = CurBB;
1184 MachineFunction &MF = DAG.getMachineFunction();
1185 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1186 CurBB->getParent()->insert(++BBI, TmpBB);
1188 if (Opc == Instruction::Or) {
1189 // Codegen X | Y as:
1197 // Emit the LHS condition.
1198 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1200 // Emit the RHS condition into TmpBB.
1201 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1203 assert(Opc == Instruction::And && "Unknown merge op!");
1204 // Codegen X & Y as:
1211 // This requires creation of TmpBB after CurBB.
1213 // Emit the LHS condition.
1214 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1216 // Emit the RHS condition into TmpBB.
1217 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1221 /// If the set of cases should be emitted as a series of branches, return true.
1222 /// If we should emit this as a bunch of and/or'd together conditions, return
1225 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1226 if (Cases.size() != 2) return true;
1228 // If this is two comparisons of the same values or'd or and'd together, they
1229 // will get folded into a single comparison, so don't emit two blocks.
1230 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1231 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1232 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1233 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1240 void SelectionDAGLowering::visitBr(BranchInst &I) {
1241 // Update machine-CFG edges.
1242 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1244 // Figure out which block is immediately after the current one.
1245 MachineBasicBlock *NextBlock = 0;
1246 MachineFunction::iterator BBI = CurMBB;
1247 if (++BBI != FuncInfo.MF->end())
1250 if (I.isUnconditional()) {
1251 // Update machine-CFG edges.
1252 CurMBB->addSuccessor(Succ0MBB);
1254 // If this is not a fall-through branch, emit the branch.
1255 if (Succ0MBB != NextBlock)
1256 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1257 MVT::Other, getControlRoot(),
1258 DAG.getBasicBlock(Succ0MBB)));
1262 // If this condition is one of the special cases we handle, do special stuff
1264 Value *CondVal = I.getCondition();
1265 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1267 // If this is a series of conditions that are or'd or and'd together, emit
1268 // this as a sequence of branches instead of setcc's with and/or operations.
1269 // For example, instead of something like:
1282 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1283 if (BOp->hasOneUse() &&
1284 (BOp->getOpcode() == Instruction::And ||
1285 BOp->getOpcode() == Instruction::Or)) {
1286 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1287 // If the compares in later blocks need to use values not currently
1288 // exported from this block, export them now. This block should always
1289 // be the first entry.
1290 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1292 // Allow some cases to be rejected.
1293 if (ShouldEmitAsBranches(SwitchCases)) {
1294 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1295 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1296 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1299 // Emit the branch for this block.
1300 visitSwitchCase(SwitchCases[0]);
1301 SwitchCases.erase(SwitchCases.begin());
1305 // Okay, we decided not to do this, remove any inserted MBB's and clear
1307 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1308 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1310 SwitchCases.clear();
1314 // Create a CaseBlock record representing this branch.
1315 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1316 NULL, Succ0MBB, Succ1MBB, CurMBB);
1317 // Use visitSwitchCase to actually insert the fast branch sequence for this
1319 visitSwitchCase(CB);
1322 /// visitSwitchCase - Emits the necessary code to represent a single node in
1323 /// the binary search tree resulting from lowering a switch instruction.
1324 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1326 SDValue CondLHS = getValue(CB.CmpLHS);
1327 DebugLoc dl = getCurDebugLoc();
1329 // Build the setcc now.
1330 if (CB.CmpMHS == NULL) {
1331 // Fold "(X == true)" to X and "(X == false)" to !X to
1332 // handle common cases produced by branch lowering.
1333 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1334 CB.CC == ISD::SETEQ)
1336 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1337 CB.CC == ISD::SETEQ) {
1338 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1339 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1341 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1343 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1345 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1346 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1348 SDValue CmpOp = getValue(CB.CmpMHS);
1349 EVT VT = CmpOp.getValueType();
1351 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1352 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1355 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1356 VT, CmpOp, DAG.getConstant(Low, VT));
1357 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1358 DAG.getConstant(High-Low, VT), ISD::SETULE);
1362 // Update successor info
1363 CurMBB->addSuccessor(CB.TrueBB);
1364 CurMBB->addSuccessor(CB.FalseBB);
1366 // Set NextBlock to be the MBB immediately after the current one, if any.
1367 // This is used to avoid emitting unnecessary branches to the next block.
1368 MachineBasicBlock *NextBlock = 0;
1369 MachineFunction::iterator BBI = CurMBB;
1370 if (++BBI != FuncInfo.MF->end())
1373 // If the lhs block is the next block, invert the condition so that we can
1374 // fall through to the lhs instead of the rhs block.
1375 if (CB.TrueBB == NextBlock) {
1376 std::swap(CB.TrueBB, CB.FalseBB);
1377 SDValue True = DAG.getConstant(1, Cond.getValueType());
1378 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1380 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1381 MVT::Other, getControlRoot(), Cond,
1382 DAG.getBasicBlock(CB.TrueBB));
1384 // If the branch was constant folded, fix up the CFG.
1385 if (BrCond.getOpcode() == ISD::BR) {
1386 CurMBB->removeSuccessor(CB.FalseBB);
1387 DAG.setRoot(BrCond);
1389 // Otherwise, go ahead and insert the false branch.
1390 if (BrCond == getControlRoot())
1391 CurMBB->removeSuccessor(CB.TrueBB);
1393 if (CB.FalseBB == NextBlock)
1394 DAG.setRoot(BrCond);
1396 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1397 DAG.getBasicBlock(CB.FalseBB)));
1401 /// visitJumpTable - Emit JumpTable node in the current MBB
1402 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1403 // Emit the code for the jump table
1404 assert(JT.Reg != -1U && "Should lower JT Header first!");
1405 EVT PTy = TLI.getPointerTy();
1406 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1408 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1409 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1410 MVT::Other, Index.getValue(1),
1414 /// visitJumpTableHeader - This function emits necessary code to produce index
1415 /// in the JumpTable from switch case.
1416 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1417 JumpTableHeader &JTH) {
1418 // Subtract the lowest switch case value from the value being switched on and
1419 // conditional branch to default mbb if the result is greater than the
1420 // difference between smallest and largest cases.
1421 SDValue SwitchOp = getValue(JTH.SValue);
1422 EVT VT = SwitchOp.getValueType();
1423 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1424 DAG.getConstant(JTH.First, VT));
1426 // The SDNode we just created, which holds the value being switched on minus
1427 // the the smallest case value, needs to be copied to a virtual register so it
1428 // can be used as an index into the jump table in a subsequent basic block.
1429 // This value may be smaller or larger than the target's pointer type, and
1430 // therefore require extension or truncating.
1431 if (VT.bitsGT(TLI.getPointerTy()))
1432 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1433 TLI.getPointerTy(), SUB);
1435 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1436 TLI.getPointerTy(), SUB);
1438 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1439 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1440 JumpTableReg, SwitchOp);
1441 JT.Reg = JumpTableReg;
1443 // Emit the range check for the jump table, and branch to the default block
1444 // for the switch statement if the value being switched on exceeds the largest
1445 // case in the switch.
1446 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1447 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1448 DAG.getConstant(JTH.Last-JTH.First,VT),
1451 // Set NextBlock to be the MBB immediately after the current one, if any.
1452 // This is used to avoid emitting unnecessary branches to the next block.
1453 MachineBasicBlock *NextBlock = 0;
1454 MachineFunction::iterator BBI = CurMBB;
1455 if (++BBI != FuncInfo.MF->end())
1458 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1459 MVT::Other, CopyTo, CMP,
1460 DAG.getBasicBlock(JT.Default));
1462 if (JT.MBB == NextBlock)
1463 DAG.setRoot(BrCond);
1465 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1466 DAG.getBasicBlock(JT.MBB)));
1469 /// visitBitTestHeader - This function emits necessary code to produce value
1470 /// suitable for "bit tests"
1471 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1472 // Subtract the minimum value
1473 SDValue SwitchOp = getValue(B.SValue);
1474 EVT VT = SwitchOp.getValueType();
1475 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1476 DAG.getConstant(B.First, VT));
1479 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1480 TLI.getSetCCResultType(SUB.getValueType()),
1481 SUB, DAG.getConstant(B.Range, VT),
1485 if (VT.bitsGT(TLI.getPointerTy()))
1486 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1487 TLI.getPointerTy(), SUB);
1489 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1490 TLI.getPointerTy(), SUB);
1492 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1493 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1496 // Set NextBlock to be the MBB immediately after the current one, if any.
1497 // This is used to avoid emitting unnecessary branches to the next block.
1498 MachineBasicBlock *NextBlock = 0;
1499 MachineFunction::iterator BBI = CurMBB;
1500 if (++BBI != FuncInfo.MF->end())
1503 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1505 CurMBB->addSuccessor(B.Default);
1506 CurMBB->addSuccessor(MBB);
1508 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1509 MVT::Other, CopyTo, RangeCmp,
1510 DAG.getBasicBlock(B.Default));
1512 if (MBB == NextBlock)
1513 DAG.setRoot(BrRange);
1515 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1516 DAG.getBasicBlock(MBB)));
1519 /// visitBitTestCase - this function produces one "bit test"
1520 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1523 // Make desired shift
1524 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1525 TLI.getPointerTy());
1526 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1528 DAG.getConstant(1, TLI.getPointerTy()),
1531 // Emit bit tests and jumps
1532 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1533 TLI.getPointerTy(), SwitchVal,
1534 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1535 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1536 TLI.getSetCCResultType(AndOp.getValueType()),
1537 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1540 CurMBB->addSuccessor(B.TargetBB);
1541 CurMBB->addSuccessor(NextMBB);
1543 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1544 MVT::Other, getControlRoot(),
1545 AndCmp, DAG.getBasicBlock(B.TargetBB));
1547 // Set NextBlock to be the MBB immediately after the current one, if any.
1548 // This is used to avoid emitting unnecessary branches to the next block.
1549 MachineBasicBlock *NextBlock = 0;
1550 MachineFunction::iterator BBI = CurMBB;
1551 if (++BBI != FuncInfo.MF->end())
1554 if (NextMBB == NextBlock)
1557 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1558 DAG.getBasicBlock(NextMBB)));
1561 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1562 // Retrieve successors.
1563 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1564 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1566 const Value *Callee(I.getCalledValue());
1567 if (isa<InlineAsm>(Callee))
1570 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1572 // If the value of the invoke is used outside of its defining block, make it
1573 // available as a virtual register.
1574 CopyToExportRegsIfNeeded(&I);
1576 // Update successor info
1577 CurMBB->addSuccessor(Return);
1578 CurMBB->addSuccessor(LandingPad);
1580 // Drop into normal successor.
1581 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1582 MVT::Other, getControlRoot(),
1583 DAG.getBasicBlock(Return)));
1586 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1589 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1590 /// small case ranges).
1591 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1592 CaseRecVector& WorkList,
1594 MachineBasicBlock* Default) {
1595 Case& BackCase = *(CR.Range.second-1);
1597 // Size is the number of Cases represented by this range.
1598 size_t Size = CR.Range.second - CR.Range.first;
1602 // Get the MachineFunction which holds the current MBB. This is used when
1603 // inserting any additional MBBs necessary to represent the switch.
1604 MachineFunction *CurMF = FuncInfo.MF;
1606 // Figure out which block is immediately after the current one.
1607 MachineBasicBlock *NextBlock = 0;
1608 MachineFunction::iterator BBI = CR.CaseBB;
1610 if (++BBI != FuncInfo.MF->end())
1613 // TODO: If any two of the cases has the same destination, and if one value
1614 // is the same as the other, but has one bit unset that the other has set,
1615 // use bit manipulation to do two compares at once. For example:
1616 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1618 // Rearrange the case blocks so that the last one falls through if possible.
1619 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1620 // The last case block won't fall through into 'NextBlock' if we emit the
1621 // branches in this order. See if rearranging a case value would help.
1622 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1623 if (I->BB == NextBlock) {
1624 std::swap(*I, BackCase);
1630 // Create a CaseBlock record representing a conditional branch to
1631 // the Case's target mbb if the value being switched on SV is equal
1633 MachineBasicBlock *CurBlock = CR.CaseBB;
1634 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1635 MachineBasicBlock *FallThrough;
1637 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1638 CurMF->insert(BBI, FallThrough);
1640 // Put SV in a virtual register to make it available from the new blocks.
1641 ExportFromCurrentBlock(SV);
1643 // If the last case doesn't match, go to the default block.
1644 FallThrough = Default;
1647 Value *RHS, *LHS, *MHS;
1649 if (I->High == I->Low) {
1650 // This is just small small case range :) containing exactly 1 case
1652 LHS = SV; RHS = I->High; MHS = NULL;
1655 LHS = I->Low; MHS = SV; RHS = I->High;
1657 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1659 // If emitting the first comparison, just call visitSwitchCase to emit the
1660 // code into the current block. Otherwise, push the CaseBlock onto the
1661 // vector to be later processed by SDISel, and insert the node's MBB
1662 // before the next MBB.
1663 if (CurBlock == CurMBB)
1664 visitSwitchCase(CB);
1666 SwitchCases.push_back(CB);
1668 CurBlock = FallThrough;
1674 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1675 return !DisableJumpTables &&
1676 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1677 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1680 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1681 APInt LastExt(Last), FirstExt(First);
1682 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1683 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1684 return (LastExt - FirstExt + 1ULL);
1687 /// handleJTSwitchCase - Emit jumptable for current switch case range
1688 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1689 CaseRecVector& WorkList,
1691 MachineBasicBlock* Default) {
1692 Case& FrontCase = *CR.Range.first;
1693 Case& BackCase = *(CR.Range.second-1);
1695 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1696 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1699 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1703 if (!areJTsAllowed(TLI) || TSize <= 3)
1706 APInt Range = ComputeRange(First, Last);
1707 double Density = (double)TSize / Range.roundToDouble();
1711 DEBUG(errs() << "Lowering jump table\n"
1712 << "First entry: " << First << ". Last entry: " << Last << '\n'
1713 << "Range: " << Range
1714 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1716 // Get the MachineFunction which holds the current MBB. This is used when
1717 // inserting any additional MBBs necessary to represent the switch.
1718 MachineFunction *CurMF = FuncInfo.MF;
1720 // Figure out which block is immediately after the current one.
1721 MachineFunction::iterator BBI = CR.CaseBB;
1724 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1726 // Create a new basic block to hold the code for loading the address
1727 // of the jump table, and jumping to it. Update successor information;
1728 // we will either branch to the default case for the switch, or the jump
1730 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1731 CurMF->insert(BBI, JumpTableBB);
1732 CR.CaseBB->addSuccessor(Default);
1733 CR.CaseBB->addSuccessor(JumpTableBB);
1735 // Build a vector of destination BBs, corresponding to each target
1736 // of the jump table. If the value of the jump table slot corresponds to
1737 // a case statement, push the case's BB onto the vector, otherwise, push
1739 std::vector<MachineBasicBlock*> DestBBs;
1741 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1742 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1743 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1745 if (Low.sle(TEI) && TEI.sle(High)) {
1746 DestBBs.push_back(I->BB);
1750 DestBBs.push_back(Default);
1754 // Update successor info. Add one edge to each unique successor.
1755 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1756 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1757 E = DestBBs.end(); I != E; ++I) {
1758 if (!SuccsHandled[(*I)->getNumber()]) {
1759 SuccsHandled[(*I)->getNumber()] = true;
1760 JumpTableBB->addSuccessor(*I);
1764 // Create a jump table index for this jump table, or return an existing
1766 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1768 // Set the jump table information so that we can codegen it as a second
1769 // MachineBasicBlock
1770 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1771 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1772 if (CR.CaseBB == CurMBB)
1773 visitJumpTableHeader(JT, JTH);
1775 JTCases.push_back(JumpTableBlock(JTH, JT));
1780 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1782 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1783 CaseRecVector& WorkList,
1785 MachineBasicBlock* Default) {
1786 // Get the MachineFunction which holds the current MBB. This is used when
1787 // inserting any additional MBBs necessary to represent the switch.
1788 MachineFunction *CurMF = FuncInfo.MF;
1790 // Figure out which block is immediately after the current one.
1791 MachineFunction::iterator BBI = CR.CaseBB;
1794 Case& FrontCase = *CR.Range.first;
1795 Case& BackCase = *(CR.Range.second-1);
1796 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1798 // Size is the number of Cases represented by this range.
1799 unsigned Size = CR.Range.second - CR.Range.first;
1801 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1802 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1804 CaseItr Pivot = CR.Range.first + Size/2;
1806 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1807 // (heuristically) allow us to emit JumpTable's later.
1809 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1813 size_t LSize = FrontCase.size();
1814 size_t RSize = TSize-LSize;
1815 DEBUG(errs() << "Selecting best pivot: \n"
1816 << "First: " << First << ", Last: " << Last <<'\n'
1817 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1818 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1820 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1821 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1822 APInt Range = ComputeRange(LEnd, RBegin);
1823 assert((Range - 2ULL).isNonNegative() &&
1824 "Invalid case distance");
1825 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1826 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1827 double Metric = Range.logBase2()*(LDensity+RDensity);
1828 // Should always split in some non-trivial place
1829 DEBUG(errs() <<"=>Step\n"
1830 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1831 << "LDensity: " << LDensity
1832 << ", RDensity: " << RDensity << '\n'
1833 << "Metric: " << Metric << '\n');
1834 if (FMetric < Metric) {
1837 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1843 if (areJTsAllowed(TLI)) {
1844 // If our case is dense we *really* should handle it earlier!
1845 assert((FMetric > 0) && "Should handle dense range earlier!");
1847 Pivot = CR.Range.first + Size/2;
1850 CaseRange LHSR(CR.Range.first, Pivot);
1851 CaseRange RHSR(Pivot, CR.Range.second);
1852 Constant *C = Pivot->Low;
1853 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1855 // We know that we branch to the LHS if the Value being switched on is
1856 // less than the Pivot value, C. We use this to optimize our binary
1857 // tree a bit, by recognizing that if SV is greater than or equal to the
1858 // LHS's Case Value, and that Case Value is exactly one less than the
1859 // Pivot's Value, then we can branch directly to the LHS's Target,
1860 // rather than creating a leaf node for it.
1861 if ((LHSR.second - LHSR.first) == 1 &&
1862 LHSR.first->High == CR.GE &&
1863 cast<ConstantInt>(C)->getValue() ==
1864 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1865 TrueBB = LHSR.first->BB;
1867 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1868 CurMF->insert(BBI, TrueBB);
1869 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1871 // Put SV in a virtual register to make it available from the new blocks.
1872 ExportFromCurrentBlock(SV);
1875 // Similar to the optimization above, if the Value being switched on is
1876 // known to be less than the Constant CR.LT, and the current Case Value
1877 // is CR.LT - 1, then we can branch directly to the target block for
1878 // the current Case Value, rather than emitting a RHS leaf node for it.
1879 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1880 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1881 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1882 FalseBB = RHSR.first->BB;
1884 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1885 CurMF->insert(BBI, FalseBB);
1886 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1888 // Put SV in a virtual register to make it available from the new blocks.
1889 ExportFromCurrentBlock(SV);
1892 // Create a CaseBlock record representing a conditional branch to
1893 // the LHS node if the value being switched on SV is less than C.
1894 // Otherwise, branch to LHS.
1895 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1897 if (CR.CaseBB == CurMBB)
1898 visitSwitchCase(CB);
1900 SwitchCases.push_back(CB);
1905 /// handleBitTestsSwitchCase - if current case range has few destination and
1906 /// range span less, than machine word bitwidth, encode case range into series
1907 /// of masks and emit bit tests with these masks.
1908 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1909 CaseRecVector& WorkList,
1911 MachineBasicBlock* Default){
1912 EVT PTy = TLI.getPointerTy();
1913 unsigned IntPtrBits = PTy.getSizeInBits();
1915 Case& FrontCase = *CR.Range.first;
1916 Case& BackCase = *(CR.Range.second-1);
1918 // Get the MachineFunction which holds the current MBB. This is used when
1919 // inserting any additional MBBs necessary to represent the switch.
1920 MachineFunction *CurMF = FuncInfo.MF;
1922 // If target does not have legal shift left, do not emit bit tests at all.
1923 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1927 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1929 // Single case counts one, case range - two.
1930 numCmps += (I->Low == I->High ? 1 : 2);
1933 // Count unique destinations
1934 SmallSet<MachineBasicBlock*, 4> Dests;
1935 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1936 Dests.insert(I->BB);
1937 if (Dests.size() > 3)
1938 // Don't bother the code below, if there are too much unique destinations
1941 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1942 << "Total number of comparisons: " << numCmps << '\n');
1944 // Compute span of values.
1945 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1946 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1947 APInt cmpRange = maxValue - minValue;
1949 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1950 << "Low bound: " << minValue << '\n'
1951 << "High bound: " << maxValue << '\n');
1953 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1954 (!(Dests.size() == 1 && numCmps >= 3) &&
1955 !(Dests.size() == 2 && numCmps >= 5) &&
1956 !(Dests.size() >= 3 && numCmps >= 6)))
1959 DEBUG(errs() << "Emitting bit tests\n");
1960 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1962 // Optimize the case where all the case values fit in a
1963 // word without having to subtract minValue. In this case,
1964 // we can optimize away the subtraction.
1965 if (minValue.isNonNegative() &&
1966 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1967 cmpRange = maxValue;
1969 lowBound = minValue;
1972 CaseBitsVector CasesBits;
1973 unsigned i, count = 0;
1975 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1976 MachineBasicBlock* Dest = I->BB;
1977 for (i = 0; i < count; ++i)
1978 if (Dest == CasesBits[i].BB)
1982 assert((count < 3) && "Too much destinations to test!");
1983 CasesBits.push_back(CaseBits(0, Dest, 0));
1987 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1988 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1990 uint64_t lo = (lowValue - lowBound).getZExtValue();
1991 uint64_t hi = (highValue - lowBound).getZExtValue();
1993 for (uint64_t j = lo; j <= hi; j++) {
1994 CasesBits[i].Mask |= 1ULL << j;
1995 CasesBits[i].Bits++;
1999 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2003 // Figure out which block is immediately after the current one.
2004 MachineFunction::iterator BBI = CR.CaseBB;
2007 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2009 DEBUG(errs() << "Cases:\n");
2010 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2011 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2012 << ", Bits: " << CasesBits[i].Bits
2013 << ", BB: " << CasesBits[i].BB << '\n');
2015 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2016 CurMF->insert(BBI, CaseBB);
2017 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2021 // Put SV in a virtual register to make it available from the new blocks.
2022 ExportFromCurrentBlock(SV);
2025 BitTestBlock BTB(lowBound, cmpRange, SV,
2026 -1U, (CR.CaseBB == CurMBB),
2027 CR.CaseBB, Default, BTC);
2029 if (CR.CaseBB == CurMBB)
2030 visitBitTestHeader(BTB);
2032 BitTestCases.push_back(BTB);
2038 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2039 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2040 const SwitchInst& SI) {
2043 // Start with "simple" cases
2044 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2045 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2046 Cases.push_back(Case(SI.getSuccessorValue(i),
2047 SI.getSuccessorValue(i),
2050 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2052 // Merge case into clusters
2053 if (Cases.size() >= 2)
2054 // Must recompute end() each iteration because it may be
2055 // invalidated by erase if we hold on to it
2056 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2057 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2058 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2059 MachineBasicBlock* nextBB = J->BB;
2060 MachineBasicBlock* currentBB = I->BB;
2062 // If the two neighboring cases go to the same destination, merge them
2063 // into a single case.
2064 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2072 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2073 if (I->Low != I->High)
2074 // A range counts double, since it requires two compares.
2081 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2082 // Figure out which block is immediately after the current one.
2083 MachineBasicBlock *NextBlock = 0;
2085 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2087 // If there is only the default destination, branch to it if it is not the
2088 // next basic block. Otherwise, just fall through.
2089 if (SI.getNumOperands() == 2) {
2090 // Update machine-CFG edges.
2092 // If this is not a fall-through branch, emit the branch.
2093 CurMBB->addSuccessor(Default);
2094 if (Default != NextBlock)
2095 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2096 MVT::Other, getControlRoot(),
2097 DAG.getBasicBlock(Default)));
2101 // If there are any non-default case statements, create a vector of Cases
2102 // representing each one, and sort the vector so that we can efficiently
2103 // create a binary search tree from them.
2105 size_t numCmps = Clusterify(Cases, SI);
2106 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2107 << ". Total compares: " << numCmps << '\n');
2110 // Get the Value to be switched on and default basic blocks, which will be
2111 // inserted into CaseBlock records, representing basic blocks in the binary
2113 Value *SV = SI.getOperand(0);
2115 // Push the initial CaseRec onto the worklist
2116 CaseRecVector WorkList;
2117 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2119 while (!WorkList.empty()) {
2120 // Grab a record representing a case range to process off the worklist
2121 CaseRec CR = WorkList.back();
2122 WorkList.pop_back();
2124 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2127 // If the range has few cases (two or less) emit a series of specific
2129 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2132 // If the switch has more than 5 blocks, and at least 40% dense, and the
2133 // target supports indirect branches, then emit a jump table rather than
2134 // lowering the switch to a binary tree of conditional branches.
2135 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2138 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2139 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2140 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2145 void SelectionDAGLowering::visitFSub(User &I) {
2146 // -0.0 - X --> fneg
2147 const Type *Ty = I.getType();
2148 if (isa<VectorType>(Ty)) {
2149 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2150 const VectorType *DestTy = cast<VectorType>(I.getType());
2151 const Type *ElTy = DestTy->getElementType();
2152 unsigned VL = DestTy->getNumElements();
2153 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2154 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2156 SDValue Op2 = getValue(I.getOperand(1));
2157 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2158 Op2.getValueType(), Op2));
2163 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2164 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2165 SDValue Op2 = getValue(I.getOperand(1));
2166 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2167 Op2.getValueType(), Op2));
2171 visitBinary(I, ISD::FSUB);
2174 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2175 SDValue Op1 = getValue(I.getOperand(0));
2176 SDValue Op2 = getValue(I.getOperand(1));
2178 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2179 Op1.getValueType(), Op1, Op2));
2182 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2183 SDValue Op1 = getValue(I.getOperand(0));
2184 SDValue Op2 = getValue(I.getOperand(1));
2185 if (!isa<VectorType>(I.getType()) &&
2186 Op2.getValueType() != TLI.getShiftAmountTy()) {
2187 // If the operand is smaller than the shift count type, promote it.
2188 EVT PTy = TLI.getPointerTy();
2189 EVT STy = TLI.getShiftAmountTy();
2190 if (STy.bitsGT(Op2.getValueType()))
2191 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2192 TLI.getShiftAmountTy(), Op2);
2193 // If the operand is larger than the shift count type but the shift
2194 // count type has enough bits to represent any shift value, truncate
2195 // it now. This is a common case and it exposes the truncate to
2196 // optimization early.
2197 else if (STy.getSizeInBits() >=
2198 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2199 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2200 TLI.getShiftAmountTy(), Op2);
2201 // Otherwise we'll need to temporarily settle for some other
2202 // convenient type; type legalization will make adjustments as
2204 else if (PTy.bitsLT(Op2.getValueType()))
2205 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2206 TLI.getPointerTy(), Op2);
2207 else if (PTy.bitsGT(Op2.getValueType()))
2208 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2209 TLI.getPointerTy(), Op2);
2212 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2213 Op1.getValueType(), Op1, Op2));
2216 void SelectionDAGLowering::visitICmp(User &I) {
2217 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2218 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2219 predicate = IC->getPredicate();
2220 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2221 predicate = ICmpInst::Predicate(IC->getPredicate());
2222 SDValue Op1 = getValue(I.getOperand(0));
2223 SDValue Op2 = getValue(I.getOperand(1));
2224 ISD::CondCode Opcode = getICmpCondCode(predicate);
2226 EVT DestVT = TLI.getValueType(I.getType());
2227 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2230 void SelectionDAGLowering::visitFCmp(User &I) {
2231 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2232 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2233 predicate = FC->getPredicate();
2234 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2235 predicate = FCmpInst::Predicate(FC->getPredicate());
2236 SDValue Op1 = getValue(I.getOperand(0));
2237 SDValue Op2 = getValue(I.getOperand(1));
2238 ISD::CondCode Condition = getFCmpCondCode(predicate);
2239 EVT DestVT = TLI.getValueType(I.getType());
2240 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2243 void SelectionDAGLowering::visitSelect(User &I) {
2244 SmallVector<EVT, 4> ValueVTs;
2245 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2246 unsigned NumValues = ValueVTs.size();
2247 if (NumValues != 0) {
2248 SmallVector<SDValue, 4> Values(NumValues);
2249 SDValue Cond = getValue(I.getOperand(0));
2250 SDValue TrueVal = getValue(I.getOperand(1));
2251 SDValue FalseVal = getValue(I.getOperand(2));
2253 for (unsigned i = 0; i != NumValues; ++i)
2254 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2255 TrueVal.getValueType(), Cond,
2256 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2257 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2259 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2260 DAG.getVTList(&ValueVTs[0], NumValues),
2261 &Values[0], NumValues));
2266 void SelectionDAGLowering::visitTrunc(User &I) {
2267 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2268 SDValue N = getValue(I.getOperand(0));
2269 EVT DestVT = TLI.getValueType(I.getType());
2270 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2273 void SelectionDAGLowering::visitZExt(User &I) {
2274 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2275 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2276 SDValue N = getValue(I.getOperand(0));
2277 EVT DestVT = TLI.getValueType(I.getType());
2278 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2281 void SelectionDAGLowering::visitSExt(User &I) {
2282 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2283 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2284 SDValue N = getValue(I.getOperand(0));
2285 EVT DestVT = TLI.getValueType(I.getType());
2286 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2289 void SelectionDAGLowering::visitFPTrunc(User &I) {
2290 // FPTrunc is never a no-op cast, no need to check
2291 SDValue N = getValue(I.getOperand(0));
2292 EVT DestVT = TLI.getValueType(I.getType());
2293 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2294 DestVT, N, DAG.getIntPtrConstant(0)));
2297 void SelectionDAGLowering::visitFPExt(User &I){
2298 // FPTrunc is never a no-op cast, no need to check
2299 SDValue N = getValue(I.getOperand(0));
2300 EVT DestVT = TLI.getValueType(I.getType());
2301 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2304 void SelectionDAGLowering::visitFPToUI(User &I) {
2305 // FPToUI is never a no-op cast, no need to check
2306 SDValue N = getValue(I.getOperand(0));
2307 EVT DestVT = TLI.getValueType(I.getType());
2308 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2311 void SelectionDAGLowering::visitFPToSI(User &I) {
2312 // FPToSI is never a no-op cast, no need to check
2313 SDValue N = getValue(I.getOperand(0));
2314 EVT DestVT = TLI.getValueType(I.getType());
2315 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2318 void SelectionDAGLowering::visitUIToFP(User &I) {
2319 // UIToFP is never a no-op cast, no need to check
2320 SDValue N = getValue(I.getOperand(0));
2321 EVT DestVT = TLI.getValueType(I.getType());
2322 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2325 void SelectionDAGLowering::visitSIToFP(User &I){
2326 // SIToFP is never a no-op cast, no need to check
2327 SDValue N = getValue(I.getOperand(0));
2328 EVT DestVT = TLI.getValueType(I.getType());
2329 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2332 void SelectionDAGLowering::visitPtrToInt(User &I) {
2333 // What to do depends on the size of the integer and the size of the pointer.
2334 // We can either truncate, zero extend, or no-op, accordingly.
2335 SDValue N = getValue(I.getOperand(0));
2336 EVT SrcVT = N.getValueType();
2337 EVT DestVT = TLI.getValueType(I.getType());
2339 if (DestVT.bitsLT(SrcVT))
2340 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2342 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2343 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2344 setValue(&I, Result);
2347 void SelectionDAGLowering::visitIntToPtr(User &I) {
2348 // What to do depends on the size of the integer and the size of the pointer.
2349 // We can either truncate, zero extend, or no-op, accordingly.
2350 SDValue N = getValue(I.getOperand(0));
2351 EVT SrcVT = N.getValueType();
2352 EVT DestVT = TLI.getValueType(I.getType());
2353 if (DestVT.bitsLT(SrcVT))
2354 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2356 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2357 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2361 void SelectionDAGLowering::visitBitCast(User &I) {
2362 SDValue N = getValue(I.getOperand(0));
2363 EVT DestVT = TLI.getValueType(I.getType());
2365 // BitCast assures us that source and destination are the same size so this
2366 // is either a BIT_CONVERT or a no-op.
2367 if (DestVT != N.getValueType())
2368 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2369 DestVT, N)); // convert types
2371 setValue(&I, N); // noop cast.
2374 void SelectionDAGLowering::visitInsertElement(User &I) {
2375 SDValue InVec = getValue(I.getOperand(0));
2376 SDValue InVal = getValue(I.getOperand(1));
2377 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2379 getValue(I.getOperand(2)));
2381 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2382 TLI.getValueType(I.getType()),
2383 InVec, InVal, InIdx));
2386 void SelectionDAGLowering::visitExtractElement(User &I) {
2387 SDValue InVec = getValue(I.getOperand(0));
2388 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2390 getValue(I.getOperand(1)));
2391 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2392 TLI.getValueType(I.getType()), InVec, InIdx));
2396 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2397 // from SIndx and increasing to the element length (undefs are allowed).
2398 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2399 unsigned MaskNumElts = Mask.size();
2400 for (unsigned i = 0; i != MaskNumElts; ++i)
2401 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2406 void SelectionDAGLowering::visitShuffleVector(User &I) {
2407 SmallVector<int, 8> Mask;
2408 SDValue Src1 = getValue(I.getOperand(0));
2409 SDValue Src2 = getValue(I.getOperand(1));
2411 // Convert the ConstantVector mask operand into an array of ints, with -1
2412 // representing undef values.
2413 SmallVector<Constant*, 8> MaskElts;
2414 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2416 unsigned MaskNumElts = MaskElts.size();
2417 for (unsigned i = 0; i != MaskNumElts; ++i) {
2418 if (isa<UndefValue>(MaskElts[i]))
2421 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2424 EVT VT = TLI.getValueType(I.getType());
2425 EVT SrcVT = Src1.getValueType();
2426 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2428 if (SrcNumElts == MaskNumElts) {
2429 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2434 // Normalize the shuffle vector since mask and vector length don't match.
2435 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2436 // Mask is longer than the source vectors and is a multiple of the source
2437 // vectors. We can use concatenate vector to make the mask and vectors
2439 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2440 // The shuffle is concatenating two vectors together.
2441 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2446 // Pad both vectors with undefs to make them the same length as the mask.
2447 unsigned NumConcat = MaskNumElts / SrcNumElts;
2448 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2449 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2450 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2452 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2453 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2457 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2458 getCurDebugLoc(), VT,
2459 &MOps1[0], NumConcat);
2460 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2461 getCurDebugLoc(), VT,
2462 &MOps2[0], NumConcat);
2464 // Readjust mask for new input vector length.
2465 SmallVector<int, 8> MappedOps;
2466 for (unsigned i = 0; i != MaskNumElts; ++i) {
2468 if (Idx < (int)SrcNumElts)
2469 MappedOps.push_back(Idx);
2471 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2473 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2478 if (SrcNumElts > MaskNumElts) {
2479 // Analyze the access pattern of the vector to see if we can extract
2480 // two subvectors and do the shuffle. The analysis is done by calculating
2481 // the range of elements the mask access on both vectors.
2482 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2483 int MaxRange[2] = {-1, -1};
2485 for (unsigned i = 0; i != MaskNumElts; ++i) {
2491 if (Idx >= (int)SrcNumElts) {
2495 if (Idx > MaxRange[Input])
2496 MaxRange[Input] = Idx;
2497 if (Idx < MinRange[Input])
2498 MinRange[Input] = Idx;
2501 // Check if the access is smaller than the vector size and can we find
2502 // a reasonable extract index.
2503 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2504 int StartIdx[2]; // StartIdx to extract from
2505 for (int Input=0; Input < 2; ++Input) {
2506 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2507 RangeUse[Input] = 0; // Unused
2508 StartIdx[Input] = 0;
2509 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2510 // Fits within range but we should see if we can find a good
2511 // start index that is a multiple of the mask length.
2512 if (MaxRange[Input] < (int)MaskNumElts) {
2513 RangeUse[Input] = 1; // Extract from beginning of the vector
2514 StartIdx[Input] = 0;
2516 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2517 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2518 StartIdx[Input] + MaskNumElts < SrcNumElts)
2519 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2524 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2525 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2528 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2529 // Extract appropriate subvector and generate a vector shuffle
2530 for (int Input=0; Input < 2; ++Input) {
2531 SDValue& Src = Input == 0 ? Src1 : Src2;
2532 if (RangeUse[Input] == 0) {
2533 Src = DAG.getUNDEF(VT);
2535 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2536 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2539 // Calculate new mask.
2540 SmallVector<int, 8> MappedOps;
2541 for (unsigned i = 0; i != MaskNumElts; ++i) {
2544 MappedOps.push_back(Idx);
2545 else if (Idx < (int)SrcNumElts)
2546 MappedOps.push_back(Idx - StartIdx[0]);
2548 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2550 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2556 // We can't use either concat vectors or extract subvectors so fall back to
2557 // replacing the shuffle with extract and build vector.
2558 // to insert and build vector.
2559 EVT EltVT = VT.getVectorElementType();
2560 EVT PtrVT = TLI.getPointerTy();
2561 SmallVector<SDValue,8> Ops;
2562 for (unsigned i = 0; i != MaskNumElts; ++i) {
2564 Ops.push_back(DAG.getUNDEF(EltVT));
2567 if (Idx < (int)SrcNumElts)
2568 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2569 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2571 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2573 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2576 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2577 VT, &Ops[0], Ops.size()));
2580 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2581 const Value *Op0 = I.getOperand(0);
2582 const Value *Op1 = I.getOperand(1);
2583 const Type *AggTy = I.getType();
2584 const Type *ValTy = Op1->getType();
2585 bool IntoUndef = isa<UndefValue>(Op0);
2586 bool FromUndef = isa<UndefValue>(Op1);
2588 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2589 I.idx_begin(), I.idx_end());
2591 SmallVector<EVT, 4> AggValueVTs;
2592 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2593 SmallVector<EVT, 4> ValValueVTs;
2594 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2596 unsigned NumAggValues = AggValueVTs.size();
2597 unsigned NumValValues = ValValueVTs.size();
2598 SmallVector<SDValue, 4> Values(NumAggValues);
2600 SDValue Agg = getValue(Op0);
2601 SDValue Val = getValue(Op1);
2603 // Copy the beginning value(s) from the original aggregate.
2604 for (; i != LinearIndex; ++i)
2605 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2606 SDValue(Agg.getNode(), Agg.getResNo() + i);
2607 // Copy values from the inserted value(s).
2608 for (; i != LinearIndex + NumValValues; ++i)
2609 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2610 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2611 // Copy remaining value(s) from the original aggregate.
2612 for (; i != NumAggValues; ++i)
2613 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2614 SDValue(Agg.getNode(), Agg.getResNo() + i);
2616 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2617 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2618 &Values[0], NumAggValues));
2621 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2622 const Value *Op0 = I.getOperand(0);
2623 const Type *AggTy = Op0->getType();
2624 const Type *ValTy = I.getType();
2625 bool OutOfUndef = isa<UndefValue>(Op0);
2627 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2628 I.idx_begin(), I.idx_end());
2630 SmallVector<EVT, 4> ValValueVTs;
2631 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2633 unsigned NumValValues = ValValueVTs.size();
2634 SmallVector<SDValue, 4> Values(NumValValues);
2636 SDValue Agg = getValue(Op0);
2637 // Copy out the selected value(s).
2638 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2639 Values[i - LinearIndex] =
2641 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2642 SDValue(Agg.getNode(), Agg.getResNo() + i);
2644 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2645 DAG.getVTList(&ValValueVTs[0], NumValValues),
2646 &Values[0], NumValValues));
2650 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2651 SDValue N = getValue(I.getOperand(0));
2652 const Type *Ty = I.getOperand(0)->getType();
2654 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2657 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2658 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2661 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2662 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2663 DAG.getIntPtrConstant(Offset));
2665 Ty = StTy->getElementType(Field);
2667 Ty = cast<SequentialType>(Ty)->getElementType();
2669 // If this is a constant subscript, handle it quickly.
2670 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2671 if (CI->getZExtValue() == 0) continue;
2673 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2675 EVT PTy = TLI.getPointerTy();
2676 unsigned PtrBits = PTy.getSizeInBits();
2678 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2680 DAG.getConstant(Offs, MVT::i64));
2682 OffsVal = DAG.getIntPtrConstant(Offs);
2683 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2688 // N = N + Idx * ElementSize;
2689 uint64_t ElementSize = TD->getTypeAllocSize(Ty);
2690 SDValue IdxN = getValue(Idx);
2692 // If the index is smaller or larger than intptr_t, truncate or extend
2694 if (IdxN.getValueType().bitsLT(N.getValueType()))
2695 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2696 N.getValueType(), IdxN);
2697 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2698 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2699 N.getValueType(), IdxN);
2701 // If this is a multiply by a power of two, turn it into a shl
2702 // immediately. This is a very common case.
2703 if (ElementSize != 1) {
2704 if (isPowerOf2_64(ElementSize)) {
2705 unsigned Amt = Log2_64(ElementSize);
2706 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2707 N.getValueType(), IdxN,
2708 DAG.getConstant(Amt, TLI.getPointerTy()));
2710 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2711 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2712 N.getValueType(), IdxN, Scale);
2716 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2717 N.getValueType(), N, IdxN);
2723 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2724 // If this is a fixed sized alloca in the entry block of the function,
2725 // allocate it statically on the stack.
2726 if (FuncInfo.StaticAllocaMap.count(&I))
2727 return; // getValue will auto-populate this.
2729 const Type *Ty = I.getAllocatedType();
2730 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2732 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2735 SDValue AllocSize = getValue(I.getArraySize());
2737 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2739 DAG.getConstant(TySize, AllocSize.getValueType()));
2743 EVT IntPtr = TLI.getPointerTy();
2744 if (IntPtr.bitsLT(AllocSize.getValueType()))
2745 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2747 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2748 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2751 // Handle alignment. If the requested alignment is less than or equal to
2752 // the stack alignment, ignore it. If the size is greater than or equal to
2753 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2754 unsigned StackAlign =
2755 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2756 if (Align <= StackAlign)
2759 // Round the size of the allocation up to the stack alignment size
2760 // by add SA-1 to the size.
2761 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2762 AllocSize.getValueType(), AllocSize,
2763 DAG.getIntPtrConstant(StackAlign-1));
2764 // Mask out the low bits for alignment purposes.
2765 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2766 AllocSize.getValueType(), AllocSize,
2767 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2769 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2770 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2771 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2774 DAG.setRoot(DSA.getValue(1));
2776 // Inform the Frame Information that we have just allocated a variable-sized
2778 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2781 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2782 const Value *SV = I.getOperand(0);
2783 SDValue Ptr = getValue(SV);
2785 const Type *Ty = I.getType();
2786 bool isVolatile = I.isVolatile();
2787 unsigned Alignment = I.getAlignment();
2789 SmallVector<EVT, 4> ValueVTs;
2790 SmallVector<uint64_t, 4> Offsets;
2791 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2792 unsigned NumValues = ValueVTs.size();
2797 bool ConstantMemory = false;
2799 // Serialize volatile loads with other side effects.
2801 else if (AA->pointsToConstantMemory(SV)) {
2802 // Do not serialize (non-volatile) loads of constant memory with anything.
2803 Root = DAG.getEntryNode();
2804 ConstantMemory = true;
2806 // Do not serialize non-volatile loads against each other.
2807 Root = DAG.getRoot();
2810 SmallVector<SDValue, 4> Values(NumValues);
2811 SmallVector<SDValue, 4> Chains(NumValues);
2812 EVT PtrVT = Ptr.getValueType();
2813 for (unsigned i = 0; i != NumValues; ++i) {
2814 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2815 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2817 DAG.getConstant(Offsets[i], PtrVT)),
2819 isVolatile, Alignment);
2821 Chains[i] = L.getValue(1);
2824 if (!ConstantMemory) {
2825 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2827 &Chains[0], NumValues);
2831 PendingLoads.push_back(Chain);
2834 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2835 DAG.getVTList(&ValueVTs[0], NumValues),
2836 &Values[0], NumValues));
2840 void SelectionDAGLowering::visitStore(StoreInst &I) {
2841 Value *SrcV = I.getOperand(0);
2842 Value *PtrV = I.getOperand(1);
2844 SmallVector<EVT, 4> ValueVTs;
2845 SmallVector<uint64_t, 4> Offsets;
2846 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2847 unsigned NumValues = ValueVTs.size();
2851 // Get the lowered operands. Note that we do this after
2852 // checking if NumResults is zero, because with zero results
2853 // the operands won't have values in the map.
2854 SDValue Src = getValue(SrcV);
2855 SDValue Ptr = getValue(PtrV);
2857 SDValue Root = getRoot();
2858 SmallVector<SDValue, 4> Chains(NumValues);
2859 EVT PtrVT = Ptr.getValueType();
2860 bool isVolatile = I.isVolatile();
2861 unsigned Alignment = I.getAlignment();
2862 for (unsigned i = 0; i != NumValues; ++i)
2863 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2864 SDValue(Src.getNode(), Src.getResNo() + i),
2865 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2867 DAG.getConstant(Offsets[i], PtrVT)),
2869 isVolatile, Alignment);
2871 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2872 MVT::Other, &Chains[0], NumValues));
2875 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2877 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2878 unsigned Intrinsic) {
2879 bool HasChain = !I.doesNotAccessMemory();
2880 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2882 // Build the operand list.
2883 SmallVector<SDValue, 8> Ops;
2884 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2886 // We don't need to serialize loads against other loads.
2887 Ops.push_back(DAG.getRoot());
2889 Ops.push_back(getRoot());
2893 // Info is set by getTgtMemInstrinsic
2894 TargetLowering::IntrinsicInfo Info;
2895 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2897 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2898 if (!IsTgtIntrinsic)
2899 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2901 // Add all operands of the call to the operand list.
2902 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2903 SDValue Op = getValue(I.getOperand(i));
2904 assert(TLI.isTypeLegal(Op.getValueType()) &&
2905 "Intrinsic uses a non-legal type?");
2909 SmallVector<EVT, 4> ValueVTs;
2910 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2912 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2913 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2914 "Intrinsic uses a non-legal type?");
2918 ValueVTs.push_back(MVT::Other);
2920 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2924 if (IsTgtIntrinsic) {
2925 // This is target intrinsic that touches memory
2926 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2927 VTs, &Ops[0], Ops.size(),
2928 Info.memVT, Info.ptrVal, Info.offset,
2929 Info.align, Info.vol,
2930 Info.readMem, Info.writeMem);
2933 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2934 VTs, &Ops[0], Ops.size());
2935 else if (I.getType() != Type::getVoidTy(*DAG.getContext()))
2936 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2937 VTs, &Ops[0], Ops.size());
2939 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2940 VTs, &Ops[0], Ops.size());
2943 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2945 PendingLoads.push_back(Chain);
2949 if (I.getType() != Type::getVoidTy(*DAG.getContext())) {
2950 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2951 EVT VT = TLI.getValueType(PTy);
2952 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2954 setValue(&I, Result);
2958 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2959 static GlobalVariable *ExtractTypeInfo(Value *V) {
2960 V = V->stripPointerCasts();
2961 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2962 assert ((GV || isa<ConstantPointerNull>(V)) &&
2963 "TypeInfo must be a global variable or NULL");
2969 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2970 /// call, and add them to the specified machine basic block.
2971 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2972 MachineBasicBlock *MBB) {
2973 // Inform the MachineModuleInfo of the personality for this landing pad.
2974 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2975 assert(CE->getOpcode() == Instruction::BitCast &&
2976 isa<Function>(CE->getOperand(0)) &&
2977 "Personality should be a function");
2978 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2980 // Gather all the type infos for this landing pad and pass them along to
2981 // MachineModuleInfo.
2982 std::vector<GlobalVariable *> TyInfo;
2983 unsigned N = I.getNumOperands();
2985 for (unsigned i = N - 1; i > 2; --i) {
2986 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2987 unsigned FilterLength = CI->getZExtValue();
2988 unsigned FirstCatch = i + FilterLength + !FilterLength;
2989 assert (FirstCatch <= N && "Invalid filter length");
2991 if (FirstCatch < N) {
2992 TyInfo.reserve(N - FirstCatch);
2993 for (unsigned j = FirstCatch; j < N; ++j)
2994 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2995 MMI->addCatchTypeInfo(MBB, TyInfo);
2999 if (!FilterLength) {
3001 MMI->addCleanup(MBB);
3004 TyInfo.reserve(FilterLength - 1);
3005 for (unsigned j = i + 1; j < FirstCatch; ++j)
3006 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3007 MMI->addFilterTypeInfo(MBB, TyInfo);
3016 TyInfo.reserve(N - 3);
3017 for (unsigned j = 3; j < N; ++j)
3018 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3019 MMI->addCatchTypeInfo(MBB, TyInfo);
3025 /// GetSignificand - Get the significand and build it into a floating-point
3026 /// number with exponent of 1:
3028 /// Op = (Op & 0x007fffff) | 0x3f800000;
3030 /// where Op is the hexidecimal representation of floating point value.
3032 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3033 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3034 DAG.getConstant(0x007fffff, MVT::i32));
3035 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3036 DAG.getConstant(0x3f800000, MVT::i32));
3037 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3040 /// GetExponent - Get the exponent:
3042 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3044 /// where Op is the hexidecimal representation of floating point value.
3046 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3048 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3049 DAG.getConstant(0x7f800000, MVT::i32));
3050 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3051 DAG.getConstant(23, TLI.getPointerTy()));
3052 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3053 DAG.getConstant(127, MVT::i32));
3054 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3057 /// getF32Constant - Get 32-bit floating point constant.
3059 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3060 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3063 /// Inlined utility function to implement binary input atomic intrinsics for
3064 /// visitIntrinsicCall: I is a call instruction
3065 /// Op is the associated NodeType for I
3067 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3068 SDValue Root = getRoot();
3070 DAG.getAtomic(Op, getCurDebugLoc(),
3071 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3073 getValue(I.getOperand(1)),
3074 getValue(I.getOperand(2)),
3077 DAG.setRoot(L.getValue(1));
3081 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3083 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3084 SDValue Op1 = getValue(I.getOperand(1));
3085 SDValue Op2 = getValue(I.getOperand(2));
3087 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3088 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3090 setValue(&I, Result);
3094 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3095 /// limited-precision mode.
3097 SelectionDAGLowering::visitExp(CallInst &I) {
3099 DebugLoc dl = getCurDebugLoc();
3101 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3102 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3103 SDValue Op = getValue(I.getOperand(1));
3105 // Put the exponent in the right bit position for later addition to the
3108 // #define LOG2OFe 1.4426950f
3109 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3110 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3111 getF32Constant(DAG, 0x3fb8aa3b));
3112 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3114 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3115 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3116 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3118 // IntegerPartOfX <<= 23;
3119 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3120 DAG.getConstant(23, TLI.getPointerTy()));
3122 if (LimitFloatPrecision <= 6) {
3123 // For floating-point precision of 6:
3125 // TwoToFractionalPartOfX =
3127 // (0.735607626f + 0.252464424f * x) * x;
3129 // error 0.0144103317, which is 6 bits
3130 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3131 getF32Constant(DAG, 0x3e814304));
3132 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3133 getF32Constant(DAG, 0x3f3c50c8));
3134 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3135 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3136 getF32Constant(DAG, 0x3f7f5e7e));
3137 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3139 // Add the exponent into the result in integer domain.
3140 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3141 TwoToFracPartOfX, IntegerPartOfX);
3143 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3144 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3145 // For floating-point precision of 12:
3147 // TwoToFractionalPartOfX =
3150 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3152 // 0.000107046256 error, which is 13 to 14 bits
3153 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3154 getF32Constant(DAG, 0x3da235e3));
3155 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3156 getF32Constant(DAG, 0x3e65b8f3));
3157 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3158 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3159 getF32Constant(DAG, 0x3f324b07));
3160 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3161 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3162 getF32Constant(DAG, 0x3f7ff8fd));
3163 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3165 // Add the exponent into the result in integer domain.
3166 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3167 TwoToFracPartOfX, IntegerPartOfX);
3169 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3170 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3171 // For floating-point precision of 18:
3173 // TwoToFractionalPartOfX =
3177 // (0.554906021e-1f +
3178 // (0.961591928e-2f +
3179 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3181 // error 2.47208000*10^(-7), which is better than 18 bits
3182 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3183 getF32Constant(DAG, 0x3924b03e));
3184 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3185 getF32Constant(DAG, 0x3ab24b87));
3186 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3187 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3188 getF32Constant(DAG, 0x3c1d8c17));
3189 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3190 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3191 getF32Constant(DAG, 0x3d634a1d));
3192 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3193 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3194 getF32Constant(DAG, 0x3e75fe14));
3195 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3196 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3197 getF32Constant(DAG, 0x3f317234));
3198 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3199 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3200 getF32Constant(DAG, 0x3f800000));
3201 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3204 // Add the exponent into the result in integer domain.
3205 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3206 TwoToFracPartOfX, IntegerPartOfX);
3208 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3211 // No special expansion.
3212 result = DAG.getNode(ISD::FEXP, dl,
3213 getValue(I.getOperand(1)).getValueType(),
3214 getValue(I.getOperand(1)));
3217 setValue(&I, result);
3220 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3221 /// limited-precision mode.
3223 SelectionDAGLowering::visitLog(CallInst &I) {
3225 DebugLoc dl = getCurDebugLoc();
3227 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3228 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3229 SDValue Op = getValue(I.getOperand(1));
3230 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3232 // Scale the exponent by log(2) [0.69314718f].
3233 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3234 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3235 getF32Constant(DAG, 0x3f317218));
3237 // Get the significand and build it into a floating-point number with
3239 SDValue X = GetSignificand(DAG, Op1, dl);
3241 if (LimitFloatPrecision <= 6) {
3242 // For floating-point precision of 6:
3246 // (1.4034025f - 0.23903021f * x) * x;
3248 // error 0.0034276066, which is better than 8 bits
3249 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3250 getF32Constant(DAG, 0xbe74c456));
3251 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3252 getF32Constant(DAG, 0x3fb3a2b1));
3253 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3254 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3255 getF32Constant(DAG, 0x3f949a29));
3257 result = DAG.getNode(ISD::FADD, dl,
3258 MVT::f32, LogOfExponent, LogOfMantissa);
3259 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3260 // For floating-point precision of 12:
3266 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3268 // error 0.000061011436, which is 14 bits
3269 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3270 getF32Constant(DAG, 0xbd67b6d6));
3271 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3272 getF32Constant(DAG, 0x3ee4f4b8));
3273 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3274 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3275 getF32Constant(DAG, 0x3fbc278b));
3276 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3277 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3278 getF32Constant(DAG, 0x40348e95));
3279 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3280 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3281 getF32Constant(DAG, 0x3fdef31a));
3283 result = DAG.getNode(ISD::FADD, dl,
3284 MVT::f32, LogOfExponent, LogOfMantissa);
3285 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3286 // For floating-point precision of 18:
3294 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3296 // error 0.0000023660568, which is better than 18 bits
3297 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3298 getF32Constant(DAG, 0xbc91e5ac));
3299 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3300 getF32Constant(DAG, 0x3e4350aa));
3301 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3302 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3303 getF32Constant(DAG, 0x3f60d3e3));
3304 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3305 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3306 getF32Constant(DAG, 0x4011cdf0));
3307 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3308 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3309 getF32Constant(DAG, 0x406cfd1c));
3310 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3311 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3312 getF32Constant(DAG, 0x408797cb));
3313 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3314 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3315 getF32Constant(DAG, 0x4006dcab));
3317 result = DAG.getNode(ISD::FADD, dl,
3318 MVT::f32, LogOfExponent, LogOfMantissa);
3321 // No special expansion.
3322 result = DAG.getNode(ISD::FLOG, dl,
3323 getValue(I.getOperand(1)).getValueType(),
3324 getValue(I.getOperand(1)));
3327 setValue(&I, result);
3330 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3331 /// limited-precision mode.
3333 SelectionDAGLowering::visitLog2(CallInst &I) {
3335 DebugLoc dl = getCurDebugLoc();
3337 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3338 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3339 SDValue Op = getValue(I.getOperand(1));
3340 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3342 // Get the exponent.
3343 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3345 // Get the significand and build it into a floating-point number with
3347 SDValue X = GetSignificand(DAG, Op1, dl);
3349 // Different possible minimax approximations of significand in
3350 // floating-point for various degrees of accuracy over [1,2].
3351 if (LimitFloatPrecision <= 6) {
3352 // For floating-point precision of 6:
3354 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3356 // error 0.0049451742, which is more than 7 bits
3357 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3358 getF32Constant(DAG, 0xbeb08fe0));
3359 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3360 getF32Constant(DAG, 0x40019463));
3361 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3362 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3363 getF32Constant(DAG, 0x3fd6633d));
3365 result = DAG.getNode(ISD::FADD, dl,
3366 MVT::f32, LogOfExponent, Log2ofMantissa);
3367 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3368 // For floating-point precision of 12:
3374 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3376 // error 0.0000876136000, which is better than 13 bits
3377 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3378 getF32Constant(DAG, 0xbda7262e));
3379 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3380 getF32Constant(DAG, 0x3f25280b));
3381 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3382 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3383 getF32Constant(DAG, 0x4007b923));
3384 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3385 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3386 getF32Constant(DAG, 0x40823e2f));
3387 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3388 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3389 getF32Constant(DAG, 0x4020d29c));
3391 result = DAG.getNode(ISD::FADD, dl,
3392 MVT::f32, LogOfExponent, Log2ofMantissa);
3393 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3394 // For floating-point precision of 18:
3403 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3405 // error 0.0000018516, which is better than 18 bits
3406 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3407 getF32Constant(DAG, 0xbcd2769e));
3408 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3409 getF32Constant(DAG, 0x3e8ce0b9));
3410 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3411 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3412 getF32Constant(DAG, 0x3fa22ae7));
3413 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3414 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3415 getF32Constant(DAG, 0x40525723));
3416 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3417 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3418 getF32Constant(DAG, 0x40aaf200));
3419 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3420 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3421 getF32Constant(DAG, 0x40c39dad));
3422 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3423 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3424 getF32Constant(DAG, 0x4042902c));
3426 result = DAG.getNode(ISD::FADD, dl,
3427 MVT::f32, LogOfExponent, Log2ofMantissa);
3430 // No special expansion.
3431 result = DAG.getNode(ISD::FLOG2, dl,
3432 getValue(I.getOperand(1)).getValueType(),
3433 getValue(I.getOperand(1)));
3436 setValue(&I, result);
3439 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3440 /// limited-precision mode.
3442 SelectionDAGLowering::visitLog10(CallInst &I) {
3444 DebugLoc dl = getCurDebugLoc();
3446 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3447 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3448 SDValue Op = getValue(I.getOperand(1));
3449 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3451 // Scale the exponent by log10(2) [0.30102999f].
3452 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3453 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3454 getF32Constant(DAG, 0x3e9a209a));
3456 // Get the significand and build it into a floating-point number with
3458 SDValue X = GetSignificand(DAG, Op1, dl);
3460 if (LimitFloatPrecision <= 6) {
3461 // For floating-point precision of 6:
3463 // Log10ofMantissa =
3465 // (0.60948995f - 0.10380950f * x) * x;
3467 // error 0.0014886165, which is 6 bits
3468 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3469 getF32Constant(DAG, 0xbdd49a13));
3470 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3471 getF32Constant(DAG, 0x3f1c0789));
3472 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3473 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3474 getF32Constant(DAG, 0x3f011300));
3476 result = DAG.getNode(ISD::FADD, dl,
3477 MVT::f32, LogOfExponent, Log10ofMantissa);
3478 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3479 // For floating-point precision of 12:
3481 // Log10ofMantissa =
3484 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3486 // error 0.00019228036, which is better than 12 bits
3487 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3488 getF32Constant(DAG, 0x3d431f31));
3489 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3490 getF32Constant(DAG, 0x3ea21fb2));
3491 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3492 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3493 getF32Constant(DAG, 0x3f6ae232));
3494 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3495 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3496 getF32Constant(DAG, 0x3f25f7c3));
3498 result = DAG.getNode(ISD::FADD, dl,
3499 MVT::f32, LogOfExponent, Log10ofMantissa);
3500 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3501 // For floating-point precision of 18:
3503 // Log10ofMantissa =
3508 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3510 // error 0.0000037995730, which is better than 18 bits
3511 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3512 getF32Constant(DAG, 0x3c5d51ce));
3513 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3514 getF32Constant(DAG, 0x3e00685a));
3515 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3516 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3517 getF32Constant(DAG, 0x3efb6798));
3518 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3519 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3520 getF32Constant(DAG, 0x3f88d192));
3521 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3522 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3523 getF32Constant(DAG, 0x3fc4316c));
3524 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3525 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3526 getF32Constant(DAG, 0x3f57ce70));
3528 result = DAG.getNode(ISD::FADD, dl,
3529 MVT::f32, LogOfExponent, Log10ofMantissa);
3532 // No special expansion.
3533 result = DAG.getNode(ISD::FLOG10, dl,
3534 getValue(I.getOperand(1)).getValueType(),
3535 getValue(I.getOperand(1)));
3538 setValue(&I, result);
3541 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3542 /// limited-precision mode.
3544 SelectionDAGLowering::visitExp2(CallInst &I) {
3546 DebugLoc dl = getCurDebugLoc();
3548 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3549 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3550 SDValue Op = getValue(I.getOperand(1));
3552 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3554 // FractionalPartOfX = x - (float)IntegerPartOfX;
3555 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3556 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3558 // IntegerPartOfX <<= 23;
3559 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3560 DAG.getConstant(23, TLI.getPointerTy()));
3562 if (LimitFloatPrecision <= 6) {
3563 // For floating-point precision of 6:
3565 // TwoToFractionalPartOfX =
3567 // (0.735607626f + 0.252464424f * x) * x;
3569 // error 0.0144103317, which is 6 bits
3570 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3571 getF32Constant(DAG, 0x3e814304));
3572 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3573 getF32Constant(DAG, 0x3f3c50c8));
3574 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3575 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3576 getF32Constant(DAG, 0x3f7f5e7e));
3577 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3578 SDValue TwoToFractionalPartOfX =
3579 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3581 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3582 MVT::f32, TwoToFractionalPartOfX);
3583 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3584 // For floating-point precision of 12:
3586 // TwoToFractionalPartOfX =
3589 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3591 // error 0.000107046256, which is 13 to 14 bits
3592 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3593 getF32Constant(DAG, 0x3da235e3));
3594 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3595 getF32Constant(DAG, 0x3e65b8f3));
3596 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3597 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3598 getF32Constant(DAG, 0x3f324b07));
3599 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3600 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3601 getF32Constant(DAG, 0x3f7ff8fd));
3602 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3603 SDValue TwoToFractionalPartOfX =
3604 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3606 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3607 MVT::f32, TwoToFractionalPartOfX);
3608 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3609 // For floating-point precision of 18:
3611 // TwoToFractionalPartOfX =
3615 // (0.554906021e-1f +
3616 // (0.961591928e-2f +
3617 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3618 // error 2.47208000*10^(-7), which is better than 18 bits
3619 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3620 getF32Constant(DAG, 0x3924b03e));
3621 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3622 getF32Constant(DAG, 0x3ab24b87));
3623 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3624 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3625 getF32Constant(DAG, 0x3c1d8c17));
3626 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3627 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3628 getF32Constant(DAG, 0x3d634a1d));
3629 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3630 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3631 getF32Constant(DAG, 0x3e75fe14));
3632 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3633 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3634 getF32Constant(DAG, 0x3f317234));
3635 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3636 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3637 getF32Constant(DAG, 0x3f800000));
3638 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3639 SDValue TwoToFractionalPartOfX =
3640 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3642 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3643 MVT::f32, TwoToFractionalPartOfX);
3646 // No special expansion.
3647 result = DAG.getNode(ISD::FEXP2, dl,
3648 getValue(I.getOperand(1)).getValueType(),
3649 getValue(I.getOperand(1)));
3652 setValue(&I, result);
3655 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3656 /// limited-precision mode with x == 10.0f.
3658 SelectionDAGLowering::visitPow(CallInst &I) {
3660 Value *Val = I.getOperand(1);
3661 DebugLoc dl = getCurDebugLoc();
3662 bool IsExp10 = false;
3664 if (getValue(Val).getValueType() == MVT::f32 &&
3665 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3666 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3667 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3668 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3670 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3675 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3676 SDValue Op = getValue(I.getOperand(2));
3678 // Put the exponent in the right bit position for later addition to the
3681 // #define LOG2OF10 3.3219281f
3682 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3683 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3684 getF32Constant(DAG, 0x40549a78));
3685 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3687 // FractionalPartOfX = x - (float)IntegerPartOfX;
3688 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3689 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3691 // IntegerPartOfX <<= 23;
3692 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3693 DAG.getConstant(23, TLI.getPointerTy()));
3695 if (LimitFloatPrecision <= 6) {
3696 // For floating-point precision of 6:
3698 // twoToFractionalPartOfX =
3700 // (0.735607626f + 0.252464424f * x) * x;
3702 // error 0.0144103317, which is 6 bits
3703 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3704 getF32Constant(DAG, 0x3e814304));
3705 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3706 getF32Constant(DAG, 0x3f3c50c8));
3707 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3708 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3709 getF32Constant(DAG, 0x3f7f5e7e));
3710 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3711 SDValue TwoToFractionalPartOfX =
3712 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3714 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3715 MVT::f32, TwoToFractionalPartOfX);
3716 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3717 // For floating-point precision of 12:
3719 // TwoToFractionalPartOfX =
3722 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3724 // error 0.000107046256, which is 13 to 14 bits
3725 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3726 getF32Constant(DAG, 0x3da235e3));
3727 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3728 getF32Constant(DAG, 0x3e65b8f3));
3729 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3730 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3731 getF32Constant(DAG, 0x3f324b07));
3732 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3733 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3734 getF32Constant(DAG, 0x3f7ff8fd));
3735 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3736 SDValue TwoToFractionalPartOfX =
3737 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3739 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3740 MVT::f32, TwoToFractionalPartOfX);
3741 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3742 // For floating-point precision of 18:
3744 // TwoToFractionalPartOfX =
3748 // (0.554906021e-1f +
3749 // (0.961591928e-2f +
3750 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3751 // error 2.47208000*10^(-7), which is better than 18 bits
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0x3924b03e));
3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3ab24b87));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x3c1d8c17));
3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3760 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3761 getF32Constant(DAG, 0x3d634a1d));
3762 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3763 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3764 getF32Constant(DAG, 0x3e75fe14));
3765 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3766 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3767 getF32Constant(DAG, 0x3f317234));
3768 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3769 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3770 getF32Constant(DAG, 0x3f800000));
3771 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3772 SDValue TwoToFractionalPartOfX =
3773 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3775 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3776 MVT::f32, TwoToFractionalPartOfX);
3779 // No special expansion.
3780 result = DAG.getNode(ISD::FPOW, dl,
3781 getValue(I.getOperand(1)).getValueType(),
3782 getValue(I.getOperand(1)),
3783 getValue(I.getOperand(2)));
3786 setValue(&I, result);
3789 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3790 /// we want to emit this as a call to a named external function, return the name
3791 /// otherwise lower it and return null.
3793 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3794 DebugLoc dl = getCurDebugLoc();
3795 switch (Intrinsic) {
3797 // By default, turn this into a target intrinsic node.
3798 visitTargetIntrinsic(I, Intrinsic);
3800 case Intrinsic::vastart: visitVAStart(I); return 0;
3801 case Intrinsic::vaend: visitVAEnd(I); return 0;
3802 case Intrinsic::vacopy: visitVACopy(I); return 0;
3803 case Intrinsic::returnaddress:
3804 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3805 getValue(I.getOperand(1))));
3807 case Intrinsic::frameaddress:
3808 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3809 getValue(I.getOperand(1))));
3811 case Intrinsic::setjmp:
3812 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3814 case Intrinsic::longjmp:
3815 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3817 case Intrinsic::memcpy: {
3818 SDValue Op1 = getValue(I.getOperand(1));
3819 SDValue Op2 = getValue(I.getOperand(2));
3820 SDValue Op3 = getValue(I.getOperand(3));
3821 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3822 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3823 I.getOperand(1), 0, I.getOperand(2), 0));
3826 case Intrinsic::memset: {
3827 SDValue Op1 = getValue(I.getOperand(1));
3828 SDValue Op2 = getValue(I.getOperand(2));
3829 SDValue Op3 = getValue(I.getOperand(3));
3830 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3831 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3832 I.getOperand(1), 0));
3835 case Intrinsic::memmove: {
3836 SDValue Op1 = getValue(I.getOperand(1));
3837 SDValue Op2 = getValue(I.getOperand(2));
3838 SDValue Op3 = getValue(I.getOperand(3));
3839 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3841 // If the source and destination are known to not be aliases, we can
3842 // lower memmove as memcpy.
3843 uint64_t Size = -1ULL;
3844 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3845 Size = C->getZExtValue();
3846 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3847 AliasAnalysis::NoAlias) {
3848 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3849 I.getOperand(1), 0, I.getOperand(2), 0));
3853 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3854 I.getOperand(1), 0, I.getOperand(2), 0));
3857 case Intrinsic::dbg_stoppoint: {
3858 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3859 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3860 MachineFunction &MF = DAG.getMachineFunction();
3861 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3862 setCurDebugLoc(Loc);
3864 if (OptLevel == CodeGenOpt::None)
3865 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3872 case Intrinsic::dbg_region_start: {
3873 DwarfWriter *DW = DAG.getDwarfWriter();
3874 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3875 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3876 && DW->ShouldEmitDwarfDebug()) {
3878 DW->RecordRegionStart(RSI.getContext());
3879 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3880 getRoot(), LabelID));
3884 case Intrinsic::dbg_region_end: {
3885 DwarfWriter *DW = DAG.getDwarfWriter();
3886 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3888 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3889 || !DW->ShouldEmitDwarfDebug())
3892 MachineFunction &MF = DAG.getMachineFunction();
3893 DISubprogram Subprogram(REI.getContext());
3895 if (isInlinedFnEnd(REI, MF.getFunction())) {
3896 // This is end of inlined function. Debugging information for inlined
3897 // function is not handled yet (only supported by FastISel).
3898 if (OptLevel == CodeGenOpt::None) {
3899 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3901 // Returned ID is 0 if this is unbalanced "end of inlined
3902 // scope". This could happen if optimizer eats dbg intrinsics or
3903 // "beginning of inlined scope" is not recoginized due to missing
3904 // location info. In such cases, do ignore this region.end.
3905 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3912 DW->RecordRegionEnd(REI.getContext());
3913 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3914 getRoot(), LabelID));
3917 case Intrinsic::dbg_func_start: {
3918 DwarfWriter *DW = DAG.getDwarfWriter();
3919 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3920 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3923 MachineFunction &MF = DAG.getMachineFunction();
3924 // This is a beginning of an inlined function.
3925 if (isInlinedFnStart(FSI, MF.getFunction())) {
3926 if (OptLevel != CodeGenOpt::None)
3927 // FIXME: Debugging informaation for inlined function is only
3928 // supported at CodeGenOpt::Node.
3931 DebugLoc PrevLoc = CurDebugLoc;
3932 // If llvm.dbg.func.start is seen in a new block before any
3933 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3934 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3935 if (PrevLoc.isUnknown())
3938 // Record the source line.
3939 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3941 if (!DW || !DW->ShouldEmitDwarfDebug())
3943 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3944 DISubprogram SP(FSI.getSubprogram());
3945 DICompileUnit CU(PrevLocTpl.CompileUnit);
3946 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3949 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3950 getRoot(), LabelID));
3954 // This is a beginning of a new function.
3955 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3957 if (!DW || !DW->ShouldEmitDwarfDebug())
3959 // llvm.dbg.func_start also defines beginning of function scope.
3960 DW->RecordRegionStart(FSI.getSubprogram());
3963 case Intrinsic::dbg_declare: {
3964 if (OptLevel != CodeGenOpt::None)
3965 // FIXME: Variable debug info is not supported here.
3967 DwarfWriter *DW = DAG.getDwarfWriter();
3970 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3971 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3974 Value *Variable = DI.getVariable();
3975 Value *Address = DI.getAddress();
3976 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3977 Address = BCI->getOperand(0);
3978 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3979 // Don't handle byval struct arguments or VLAs, for example.
3982 DenseMap<const AllocaInst*, int>::iterator SI =
3983 FuncInfo.StaticAllocaMap.find(AI);
3984 if (SI == FuncInfo.StaticAllocaMap.end())
3986 int FI = SI->second;
3987 DW->RecordVariable(cast<MDNode>(Variable), FI);
3990 case Intrinsic::eh_exception: {
3991 // Insert the EXCEPTIONADDR instruction.
3992 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3993 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3995 Ops[0] = DAG.getRoot();
3996 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3998 DAG.setRoot(Op.getValue(1));
4002 case Intrinsic::eh_selector_i32:
4003 case Intrinsic::eh_selector_i64: {
4004 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4005 EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64);
4008 if (CurMBB->isLandingPad())
4009 AddCatchInfo(I, MMI, CurMBB);
4012 FuncInfo.CatchInfoLost.insert(&I);
4014 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4015 unsigned Reg = TLI.getExceptionSelectorRegister();
4016 if (Reg) CurMBB->addLiveIn(Reg);
4019 // Insert the EHSELECTION instruction.
4020 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4022 Ops[0] = getValue(I.getOperand(1));
4024 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4026 DAG.setRoot(Op.getValue(1));
4028 setValue(&I, DAG.getConstant(0, VT));
4034 case Intrinsic::eh_typeid_for_i32:
4035 case Intrinsic::eh_typeid_for_i64: {
4036 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4037 EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4038 MVT::i32 : MVT::i64);
4041 // Find the type id for the given typeinfo.
4042 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4044 unsigned TypeID = MMI->getTypeIDFor(GV);
4045 setValue(&I, DAG.getConstant(TypeID, VT));
4047 // Return something different to eh_selector.
4048 setValue(&I, DAG.getConstant(1, VT));
4054 case Intrinsic::eh_return_i32:
4055 case Intrinsic::eh_return_i64:
4056 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4057 MMI->setCallsEHReturn(true);
4058 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4061 getValue(I.getOperand(1)),
4062 getValue(I.getOperand(2))));
4064 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4068 case Intrinsic::eh_unwind_init:
4069 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4070 MMI->setCallsUnwindInit(true);
4075 case Intrinsic::eh_dwarf_cfa: {
4076 EVT VT = getValue(I.getOperand(1)).getValueType();
4078 if (VT.bitsGT(TLI.getPointerTy()))
4079 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4080 TLI.getPointerTy(), getValue(I.getOperand(1)));
4082 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4083 TLI.getPointerTy(), getValue(I.getOperand(1)));
4085 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4087 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4088 TLI.getPointerTy()),
4090 setValue(&I, DAG.getNode(ISD::ADD, dl,
4092 DAG.getNode(ISD::FRAMEADDR, dl,
4095 TLI.getPointerTy())),
4099 case Intrinsic::convertff:
4100 case Intrinsic::convertfsi:
4101 case Intrinsic::convertfui:
4102 case Intrinsic::convertsif:
4103 case Intrinsic::convertuif:
4104 case Intrinsic::convertss:
4105 case Intrinsic::convertsu:
4106 case Intrinsic::convertus:
4107 case Intrinsic::convertuu: {
4108 ISD::CvtCode Code = ISD::CVT_INVALID;
4109 switch (Intrinsic) {
4110 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4111 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4112 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4113 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4114 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4115 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4116 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4117 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4118 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4120 EVT DestVT = TLI.getValueType(I.getType());
4121 Value* Op1 = I.getOperand(1);
4122 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4123 DAG.getValueType(DestVT),
4124 DAG.getValueType(getValue(Op1).getValueType()),
4125 getValue(I.getOperand(2)),
4126 getValue(I.getOperand(3)),
4131 case Intrinsic::sqrt:
4132 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4133 getValue(I.getOperand(1)).getValueType(),
4134 getValue(I.getOperand(1))));
4136 case Intrinsic::powi:
4137 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4138 getValue(I.getOperand(1)).getValueType(),
4139 getValue(I.getOperand(1)),
4140 getValue(I.getOperand(2))));
4142 case Intrinsic::sin:
4143 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4144 getValue(I.getOperand(1)).getValueType(),
4145 getValue(I.getOperand(1))));
4147 case Intrinsic::cos:
4148 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4149 getValue(I.getOperand(1)).getValueType(),
4150 getValue(I.getOperand(1))));
4152 case Intrinsic::log:
4155 case Intrinsic::log2:
4158 case Intrinsic::log10:
4161 case Intrinsic::exp:
4164 case Intrinsic::exp2:
4167 case Intrinsic::pow:
4170 case Intrinsic::pcmarker: {
4171 SDValue Tmp = getValue(I.getOperand(1));
4172 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4175 case Intrinsic::readcyclecounter: {
4176 SDValue Op = getRoot();
4177 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4178 DAG.getVTList(MVT::i64, MVT::Other),
4181 DAG.setRoot(Tmp.getValue(1));
4184 case Intrinsic::bswap:
4185 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4186 getValue(I.getOperand(1)).getValueType(),
4187 getValue(I.getOperand(1))));
4189 case Intrinsic::cttz: {
4190 SDValue Arg = getValue(I.getOperand(1));
4191 EVT Ty = Arg.getValueType();
4192 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4193 setValue(&I, result);
4196 case Intrinsic::ctlz: {
4197 SDValue Arg = getValue(I.getOperand(1));
4198 EVT Ty = Arg.getValueType();
4199 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4200 setValue(&I, result);
4203 case Intrinsic::ctpop: {
4204 SDValue Arg = getValue(I.getOperand(1));
4205 EVT Ty = Arg.getValueType();
4206 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4207 setValue(&I, result);
4210 case Intrinsic::stacksave: {
4211 SDValue Op = getRoot();
4212 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4213 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4215 DAG.setRoot(Tmp.getValue(1));
4218 case Intrinsic::stackrestore: {
4219 SDValue Tmp = getValue(I.getOperand(1));
4220 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4223 case Intrinsic::stackprotector: {
4224 // Emit code into the DAG to store the stack guard onto the stack.
4225 MachineFunction &MF = DAG.getMachineFunction();
4226 MachineFrameInfo *MFI = MF.getFrameInfo();
4227 EVT PtrTy = TLI.getPointerTy();
4229 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4230 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4232 int FI = FuncInfo.StaticAllocaMap[Slot];
4233 MFI->setStackProtectorIndex(FI);
4235 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4237 // Store the stack protector onto the stack.
4238 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4239 PseudoSourceValue::getFixedStack(FI),
4241 setValue(&I, Result);
4242 DAG.setRoot(Result);
4245 case Intrinsic::var_annotation:
4246 // Discard annotate attributes
4249 case Intrinsic::init_trampoline: {
4250 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4254 Ops[1] = getValue(I.getOperand(1));
4255 Ops[2] = getValue(I.getOperand(2));
4256 Ops[3] = getValue(I.getOperand(3));
4257 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4258 Ops[5] = DAG.getSrcValue(F);
4260 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4261 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4265 DAG.setRoot(Tmp.getValue(1));
4269 case Intrinsic::gcroot:
4271 Value *Alloca = I.getOperand(1);
4272 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4274 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4275 GFI->addStackRoot(FI->getIndex(), TypeMap);
4279 case Intrinsic::gcread:
4280 case Intrinsic::gcwrite:
4281 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4284 case Intrinsic::flt_rounds: {
4285 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4289 case Intrinsic::trap: {
4290 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4294 case Intrinsic::uadd_with_overflow:
4295 return implVisitAluOverflow(I, ISD::UADDO);
4296 case Intrinsic::sadd_with_overflow:
4297 return implVisitAluOverflow(I, ISD::SADDO);
4298 case Intrinsic::usub_with_overflow:
4299 return implVisitAluOverflow(I, ISD::USUBO);
4300 case Intrinsic::ssub_with_overflow:
4301 return implVisitAluOverflow(I, ISD::SSUBO);
4302 case Intrinsic::umul_with_overflow:
4303 return implVisitAluOverflow(I, ISD::UMULO);
4304 case Intrinsic::smul_with_overflow:
4305 return implVisitAluOverflow(I, ISD::SMULO);
4307 case Intrinsic::prefetch: {
4310 Ops[1] = getValue(I.getOperand(1));
4311 Ops[2] = getValue(I.getOperand(2));
4312 Ops[3] = getValue(I.getOperand(3));
4313 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4317 case Intrinsic::memory_barrier: {
4320 for (int x = 1; x < 6; ++x)
4321 Ops[x] = getValue(I.getOperand(x));
4323 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4326 case Intrinsic::atomic_cmp_swap: {
4327 SDValue Root = getRoot();
4329 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4330 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4332 getValue(I.getOperand(1)),
4333 getValue(I.getOperand(2)),
4334 getValue(I.getOperand(3)),
4337 DAG.setRoot(L.getValue(1));
4340 case Intrinsic::atomic_load_add:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4342 case Intrinsic::atomic_load_sub:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4344 case Intrinsic::atomic_load_or:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4346 case Intrinsic::atomic_load_xor:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4348 case Intrinsic::atomic_load_and:
4349 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4350 case Intrinsic::atomic_load_nand:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4352 case Intrinsic::atomic_load_max:
4353 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4354 case Intrinsic::atomic_load_min:
4355 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4356 case Intrinsic::atomic_load_umin:
4357 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4358 case Intrinsic::atomic_load_umax:
4359 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4360 case Intrinsic::atomic_swap:
4361 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4365 /// Test if the given instruction is in a position to be optimized
4366 /// with a tail-call. This roughly means that it's in a block with
4367 /// a return and there's nothing that needs to be scheduled
4368 /// between it and the return.
4370 /// This function only tests target-independent requirements.
4371 /// For target-dependent requirements, a target should override
4372 /// TargetLowering::IsEligibleForTailCallOptimization.
4375 isInTailCallPosition(const Instruction *I, Attributes RetAttr,
4376 const TargetLowering &TLI) {
4377 const BasicBlock *ExitBB = I->getParent();
4378 const TerminatorInst *Term = ExitBB->getTerminator();
4379 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4380 const Function *F = ExitBB->getParent();
4382 // The block must end in a return statement or an unreachable.
4383 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4385 // If I will have a chain, make sure no other instruction that will have a
4386 // chain interposes between I and the return.
4387 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4388 !I->isSafeToSpeculativelyExecute())
4389 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4393 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4394 !BBI->isSafeToSpeculativelyExecute())
4398 // If the block ends with a void return or unreachable, it doesn't matter
4399 // what the call's return type is.
4400 if (!Ret || Ret->getNumOperands() == 0) return true;
4402 // Conservatively require the attributes of the call to match those of
4404 if (F->getAttributes().getRetAttributes() != RetAttr)
4407 // Otherwise, make sure the unmodified return value of I is the return value.
4408 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4409 U = dyn_cast<Instruction>(U->getOperand(0))) {
4412 if (!U->hasOneUse())
4416 // Check for a truly no-op truncate.
4417 if (isa<TruncInst>(U) &&
4418 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4420 // Check for a truly no-op bitcast.
4421 if (isa<BitCastInst>(U) &&
4422 (U->getOperand(0)->getType() == U->getType() ||
4423 (isa<PointerType>(U->getOperand(0)->getType()) &&
4424 isa<PointerType>(U->getType()))))
4426 // Otherwise it's not a true no-op.
4433 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4435 MachineBasicBlock *LandingPad) {
4436 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4437 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4438 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4439 unsigned BeginLabel = 0, EndLabel = 0;
4441 TargetLowering::ArgListTy Args;
4442 TargetLowering::ArgListEntry Entry;
4443 Args.reserve(CS.arg_size());
4445 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4447 SDValue ArgNode = getValue(*i);
4448 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4450 unsigned attrInd = i - CS.arg_begin() + 1;
4451 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4452 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4453 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4454 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4455 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4456 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4457 Entry.Alignment = CS.getParamAlignment(attrInd);
4458 Args.push_back(Entry);
4461 if (LandingPad && MMI) {
4462 // Insert a label before the invoke call to mark the try range. This can be
4463 // used to detect deletion of the invoke via the MachineModuleInfo.
4464 BeginLabel = MMI->NextLabelID();
4466 // Both PendingLoads and PendingExports must be flushed here;
4467 // this call might not return.
4469 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4470 getControlRoot(), BeginLabel));
4473 // Check if target-independent constraints permit a tail call here.
4474 // Target-dependent constraints are checked within TLI.LowerCallTo.
4476 !isInTailCallPosition(CS.getInstruction(),
4477 CS.getAttributes().getRetAttributes(),
4481 std::pair<SDValue,SDValue> Result =
4482 TLI.LowerCallTo(getRoot(), CS.getType(),
4483 CS.paramHasAttr(0, Attribute::SExt),
4484 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4485 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4486 CS.getCallingConv(),
4488 !CS.getInstruction()->use_empty(),
4489 Callee, Args, DAG, getCurDebugLoc());
4490 assert((isTailCall || Result.second.getNode()) &&
4491 "Non-null chain expected with non-tail call!");
4492 assert((Result.second.getNode() || !Result.first.getNode()) &&
4493 "Null value expected with tail call!");
4494 if (Result.first.getNode())
4495 setValue(CS.getInstruction(), Result.first);
4496 // As a special case, a null chain means that a tail call has
4497 // been emitted and the DAG root is already updated.
4498 if (Result.second.getNode())
4499 DAG.setRoot(Result.second);
4503 if (LandingPad && MMI) {
4504 // Insert a label at the end of the invoke call to mark the try range. This
4505 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4506 EndLabel = MMI->NextLabelID();
4507 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4508 getRoot(), EndLabel));
4510 // Inform MachineModuleInfo of range.
4511 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4516 void SelectionDAGLowering::visitCall(CallInst &I) {
4517 const char *RenameFn = 0;
4518 if (Function *F = I.getCalledFunction()) {
4519 if (F->isDeclaration()) {
4520 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4522 if (unsigned IID = II->getIntrinsicID(F)) {
4523 RenameFn = visitIntrinsicCall(I, IID);
4528 if (unsigned IID = F->getIntrinsicID()) {
4529 RenameFn = visitIntrinsicCall(I, IID);
4535 // Check for well-known libc/libm calls. If the function is internal, it
4536 // can't be a library call.
4537 if (!F->hasLocalLinkage() && F->hasName()) {
4538 StringRef Name = F->getName();
4539 if (Name == "copysign" || Name == "copysignf") {
4540 if (I.getNumOperands() == 3 && // Basic sanity checks.
4541 I.getOperand(1)->getType()->isFloatingPoint() &&
4542 I.getType() == I.getOperand(1)->getType() &&
4543 I.getType() == I.getOperand(2)->getType()) {
4544 SDValue LHS = getValue(I.getOperand(1));
4545 SDValue RHS = getValue(I.getOperand(2));
4546 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4547 LHS.getValueType(), LHS, RHS));
4550 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4551 if (I.getNumOperands() == 2 && // Basic sanity checks.
4552 I.getOperand(1)->getType()->isFloatingPoint() &&
4553 I.getType() == I.getOperand(1)->getType()) {
4554 SDValue Tmp = getValue(I.getOperand(1));
4555 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4556 Tmp.getValueType(), Tmp));
4559 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4560 if (I.getNumOperands() == 2 && // Basic sanity checks.
4561 I.getOperand(1)->getType()->isFloatingPoint() &&
4562 I.getType() == I.getOperand(1)->getType()) {
4563 SDValue Tmp = getValue(I.getOperand(1));
4564 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4565 Tmp.getValueType(), Tmp));
4568 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4569 if (I.getNumOperands() == 2 && // Basic sanity checks.
4570 I.getOperand(1)->getType()->isFloatingPoint() &&
4571 I.getType() == I.getOperand(1)->getType()) {
4572 SDValue Tmp = getValue(I.getOperand(1));
4573 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4574 Tmp.getValueType(), Tmp));
4579 } else if (isa<InlineAsm>(I.getOperand(0))) {
4586 Callee = getValue(I.getOperand(0));
4588 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4590 // Check if we can potentially perform a tail call. More detailed
4591 // checking is be done within LowerCallTo, after more information
4592 // about the call is known.
4593 bool isTailCall = PerformTailCallOpt && I.isTailCall();
4595 LowerCallTo(&I, Callee, isTailCall);
4599 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4600 /// this value and returns the result as a ValueVT value. This uses
4601 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4602 /// If the Flag pointer is NULL, no flag is used.
4603 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4605 SDValue *Flag) const {
4606 // Assemble the legal parts into the final values.
4607 SmallVector<SDValue, 4> Values(ValueVTs.size());
4608 SmallVector<SDValue, 8> Parts;
4609 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4610 // Copy the legal parts from the registers.
4611 EVT ValueVT = ValueVTs[Value];
4612 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4613 EVT RegisterVT = RegVTs[Value];
4615 Parts.resize(NumRegs);
4616 for (unsigned i = 0; i != NumRegs; ++i) {
4619 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4621 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4622 *Flag = P.getValue(2);
4624 Chain = P.getValue(1);
4626 // If the source register was virtual and if we know something about it,
4627 // add an assert node.
4628 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4629 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4630 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4631 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4632 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4633 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4635 unsigned RegSize = RegisterVT.getSizeInBits();
4636 unsigned NumSignBits = LOI.NumSignBits;
4637 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4639 // FIXME: We capture more information than the dag can represent. For
4640 // now, just use the tightest assertzext/assertsext possible.
4642 EVT FromVT(MVT::Other);
4643 if (NumSignBits == RegSize)
4644 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4645 else if (NumZeroBits >= RegSize-1)
4646 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4647 else if (NumSignBits > RegSize-8)
4648 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4649 else if (NumZeroBits >= RegSize-8)
4650 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4651 else if (NumSignBits > RegSize-16)
4652 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4653 else if (NumZeroBits >= RegSize-16)
4654 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4655 else if (NumSignBits > RegSize-32)
4656 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4657 else if (NumZeroBits >= RegSize-32)
4658 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4660 if (FromVT != MVT::Other) {
4661 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4662 RegisterVT, P, DAG.getValueType(FromVT));
4671 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4672 NumRegs, RegisterVT, ValueVT);
4677 return DAG.getNode(ISD::MERGE_VALUES, dl,
4678 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4679 &Values[0], ValueVTs.size());
4682 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4683 /// specified value into the registers specified by this object. This uses
4684 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4685 /// If the Flag pointer is NULL, no flag is used.
4686 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4687 SDValue &Chain, SDValue *Flag) const {
4688 // Get the list of the values's legal parts.
4689 unsigned NumRegs = Regs.size();
4690 SmallVector<SDValue, 8> Parts(NumRegs);
4691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4692 EVT ValueVT = ValueVTs[Value];
4693 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4694 EVT RegisterVT = RegVTs[Value];
4696 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4697 &Parts[Part], NumParts, RegisterVT);
4701 // Copy the parts into the registers.
4702 SmallVector<SDValue, 8> Chains(NumRegs);
4703 for (unsigned i = 0; i != NumRegs; ++i) {
4706 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4708 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4709 *Flag = Part.getValue(1);
4711 Chains[i] = Part.getValue(0);
4714 if (NumRegs == 1 || Flag)
4715 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4716 // flagged to it. That is the CopyToReg nodes and the user are considered
4717 // a single scheduling unit. If we create a TokenFactor and return it as
4718 // chain, then the TokenFactor is both a predecessor (operand) of the
4719 // user as well as a successor (the TF operands are flagged to the user).
4720 // c1, f1 = CopyToReg
4721 // c2, f2 = CopyToReg
4722 // c3 = TokenFactor c1, c2
4725 Chain = Chains[NumRegs-1];
4727 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4730 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4731 /// operand list. This adds the code marker and includes the number of
4732 /// values added into it.
4733 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4734 bool HasMatching,unsigned MatchingIdx,
4736 std::vector<SDValue> &Ops) const {
4737 EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4738 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4739 unsigned Flag = Code | (Regs.size() << 3);
4741 Flag |= 0x80000000 | (MatchingIdx << 16);
4742 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4743 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4744 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4745 EVT RegisterVT = RegVTs[Value];
4746 for (unsigned i = 0; i != NumRegs; ++i) {
4747 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4748 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4753 /// isAllocatableRegister - If the specified register is safe to allocate,
4754 /// i.e. it isn't a stack pointer or some other special register, return the
4755 /// register class for the register. Otherwise, return null.
4756 static const TargetRegisterClass *
4757 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4758 const TargetLowering &TLI,
4759 const TargetRegisterInfo *TRI) {
4760 EVT FoundVT = MVT::Other;
4761 const TargetRegisterClass *FoundRC = 0;
4762 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4763 E = TRI->regclass_end(); RCI != E; ++RCI) {
4764 EVT ThisVT = MVT::Other;
4766 const TargetRegisterClass *RC = *RCI;
4767 // If none of the the value types for this register class are valid, we
4768 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4769 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4771 if (TLI.isTypeLegal(*I)) {
4772 // If we have already found this register in a different register class,
4773 // choose the one with the largest VT specified. For example, on
4774 // PowerPC, we favor f64 register classes over f32.
4775 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4782 if (ThisVT == MVT::Other) continue;
4784 // NOTE: This isn't ideal. In particular, this might allocate the
4785 // frame pointer in functions that need it (due to them not being taken
4786 // out of allocation, because a variable sized allocation hasn't been seen
4787 // yet). This is a slight code pessimization, but should still work.
4788 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4789 E = RC->allocation_order_end(MF); I != E; ++I)
4791 // We found a matching register class. Keep looking at others in case
4792 // we find one with larger registers that this physreg is also in.
4803 /// AsmOperandInfo - This contains information for each constraint that we are
4805 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4806 public TargetLowering::AsmOperandInfo {
4808 /// CallOperand - If this is the result output operand or a clobber
4809 /// this is null, otherwise it is the incoming operand to the CallInst.
4810 /// This gets modified as the asm is processed.
4811 SDValue CallOperand;
4813 /// AssignedRegs - If this is a register or register class operand, this
4814 /// contains the set of register corresponding to the operand.
4815 RegsForValue AssignedRegs;
4817 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4818 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4821 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4822 /// busy in OutputRegs/InputRegs.
4823 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4824 std::set<unsigned> &OutputRegs,
4825 std::set<unsigned> &InputRegs,
4826 const TargetRegisterInfo &TRI) const {
4828 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4829 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4832 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4833 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4837 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4838 /// corresponds to. If there is no Value* for this operand, it returns
4840 EVT getCallOperandValEVT(LLVMContext &Context,
4841 const TargetLowering &TLI,
4842 const TargetData *TD) const {
4843 if (CallOperandVal == 0) return MVT::Other;
4845 if (isa<BasicBlock>(CallOperandVal))
4846 return TLI.getPointerTy();
4848 const llvm::Type *OpTy = CallOperandVal->getType();
4850 // If this is an indirect operand, the operand is a pointer to the
4853 OpTy = cast<PointerType>(OpTy)->getElementType();
4855 // If OpTy is not a single value, it may be a struct/union that we
4856 // can tile with integers.
4857 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4858 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4867 OpTy = IntegerType::get(Context, BitSize);
4872 return TLI.getValueType(OpTy, true);
4876 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4878 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4879 const TargetRegisterInfo &TRI) {
4880 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4882 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4883 for (; *Aliases; ++Aliases)
4884 Regs.insert(*Aliases);
4887 } // end llvm namespace.
4890 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4891 /// specified operand. We prefer to assign virtual registers, to allow the
4892 /// register allocator handle the assignment process. However, if the asm uses
4893 /// features that we can't model on machineinstrs, we have SDISel do the
4894 /// allocation. This produces generally horrible, but correct, code.
4896 /// OpInfo describes the operand.
4897 /// Input and OutputRegs are the set of already allocated physical registers.
4899 void SelectionDAGLowering::
4900 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4901 std::set<unsigned> &OutputRegs,
4902 std::set<unsigned> &InputRegs) {
4903 LLVMContext &Context = FuncInfo.Fn->getContext();
4905 // Compute whether this value requires an input register, an output register,
4907 bool isOutReg = false;
4908 bool isInReg = false;
4909 switch (OpInfo.Type) {
4910 case InlineAsm::isOutput:
4913 // If there is an input constraint that matches this, we need to reserve
4914 // the input register so no other inputs allocate to it.
4915 isInReg = OpInfo.hasMatchingInput();
4917 case InlineAsm::isInput:
4921 case InlineAsm::isClobber:
4928 MachineFunction &MF = DAG.getMachineFunction();
4929 SmallVector<unsigned, 4> Regs;
4931 // If this is a constraint for a single physreg, or a constraint for a
4932 // register class, find it.
4933 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4934 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4935 OpInfo.ConstraintVT);
4937 unsigned NumRegs = 1;
4938 if (OpInfo.ConstraintVT != MVT::Other) {
4939 // If this is a FP input in an integer register (or visa versa) insert a bit
4940 // cast of the input value. More generally, handle any case where the input
4941 // value disagrees with the register class we plan to stick this in.
4942 if (OpInfo.Type == InlineAsm::isInput &&
4943 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4944 // Try to convert to the first EVT that the reg class contains. If the
4945 // types are identical size, use a bitcast to convert (e.g. two differing
4947 EVT RegVT = *PhysReg.second->vt_begin();
4948 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4949 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4950 RegVT, OpInfo.CallOperand);
4951 OpInfo.ConstraintVT = RegVT;
4952 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4953 // If the input is a FP value and we want it in FP registers, do a
4954 // bitcast to the corresponding integer type. This turns an f64 value
4955 // into i64, which can be passed with two i32 values on a 32-bit
4957 RegVT = EVT::getIntegerVT(Context,
4958 OpInfo.ConstraintVT.getSizeInBits());
4959 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4960 RegVT, OpInfo.CallOperand);
4961 OpInfo.ConstraintVT = RegVT;
4965 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
4969 EVT ValueVT = OpInfo.ConstraintVT;
4971 // If this is a constraint for a specific physical register, like {r17},
4973 if (unsigned AssignedReg = PhysReg.first) {
4974 const TargetRegisterClass *RC = PhysReg.second;
4975 if (OpInfo.ConstraintVT == MVT::Other)
4976 ValueVT = *RC->vt_begin();
4978 // Get the actual register value type. This is important, because the user
4979 // may have asked for (e.g.) the AX register in i32 type. We need to
4980 // remember that AX is actually i16 to get the right extension.
4981 RegVT = *RC->vt_begin();
4983 // This is a explicit reference to a physical register.
4984 Regs.push_back(AssignedReg);
4986 // If this is an expanded reference, add the rest of the regs to Regs.
4988 TargetRegisterClass::iterator I = RC->begin();
4989 for (; *I != AssignedReg; ++I)
4990 assert(I != RC->end() && "Didn't find reg!");
4992 // Already added the first reg.
4994 for (; NumRegs; --NumRegs, ++I) {
4995 assert(I != RC->end() && "Ran out of registers to allocate!");
4999 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5000 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5001 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5005 // Otherwise, if this was a reference to an LLVM register class, create vregs
5006 // for this reference.
5007 if (const TargetRegisterClass *RC = PhysReg.second) {
5008 RegVT = *RC->vt_begin();
5009 if (OpInfo.ConstraintVT == MVT::Other)
5012 // Create the appropriate number of virtual registers.
5013 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5014 for (; NumRegs; --NumRegs)
5015 Regs.push_back(RegInfo.createVirtualRegister(RC));
5017 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5021 // This is a reference to a register class that doesn't directly correspond
5022 // to an LLVM register class. Allocate NumRegs consecutive, available,
5023 // registers from the class.
5024 std::vector<unsigned> RegClassRegs
5025 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5026 OpInfo.ConstraintVT);
5028 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5029 unsigned NumAllocated = 0;
5030 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5031 unsigned Reg = RegClassRegs[i];
5032 // See if this register is available.
5033 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5034 (isInReg && InputRegs.count(Reg))) { // Already used.
5035 // Make sure we find consecutive registers.
5040 // Check to see if this register is allocatable (i.e. don't give out the
5042 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5043 if (!RC) { // Couldn't allocate this register.
5044 // Reset NumAllocated to make sure we return consecutive registers.
5049 // Okay, this register is good, we can use it.
5052 // If we allocated enough consecutive registers, succeed.
5053 if (NumAllocated == NumRegs) {
5054 unsigned RegStart = (i-NumAllocated)+1;
5055 unsigned RegEnd = i+1;
5056 // Mark all of the allocated registers used.
5057 for (unsigned i = RegStart; i != RegEnd; ++i)
5058 Regs.push_back(RegClassRegs[i]);
5060 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5061 OpInfo.ConstraintVT);
5062 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5067 // Otherwise, we couldn't allocate enough registers for this.
5070 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5071 /// processed uses a memory 'm' constraint.
5073 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5074 const TargetLowering &TLI) {
5075 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5076 InlineAsm::ConstraintInfo &CI = CInfos[i];
5077 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5078 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5079 if (CType == TargetLowering::C_Memory)
5083 // Indirect operand accesses access memory.
5091 /// visitInlineAsm - Handle a call to an InlineAsm object.
5093 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5094 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5096 /// ConstraintOperands - Information about all of the constraints.
5097 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5099 std::set<unsigned> OutputRegs, InputRegs;
5101 // Do a prepass over the constraints, canonicalizing them, and building up the
5102 // ConstraintOperands list.
5103 std::vector<InlineAsm::ConstraintInfo>
5104 ConstraintInfos = IA->ParseConstraints();
5106 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5108 SDValue Chain, Flag;
5110 // We won't need to flush pending loads if this asm doesn't touch
5111 // memory and is nonvolatile.
5112 if (hasMemory || IA->hasSideEffects())
5115 Chain = DAG.getRoot();
5117 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5118 unsigned ResNo = 0; // ResNo - The result number of the next output.
5119 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5120 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5121 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5123 EVT OpVT = MVT::Other;
5125 // Compute the value type for each operand.
5126 switch (OpInfo.Type) {
5127 case InlineAsm::isOutput:
5128 // Indirect outputs just consume an argument.
5129 if (OpInfo.isIndirect) {
5130 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5134 // The return value of the call is this value. As such, there is no
5135 // corresponding argument.
5136 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5138 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5139 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5141 assert(ResNo == 0 && "Asm only has one result!");
5142 OpVT = TLI.getValueType(CS.getType());
5146 case InlineAsm::isInput:
5147 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5149 case InlineAsm::isClobber:
5154 // If this is an input or an indirect output, process the call argument.
5155 // BasicBlocks are labels, currently appearing only in asm's.
5156 if (OpInfo.CallOperandVal) {
5157 // Strip bitcasts, if any. This mostly comes up for functions.
5158 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5160 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5161 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5163 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5166 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5169 OpInfo.ConstraintVT = OpVT;
5172 // Second pass over the constraints: compute which constraint option to use
5173 // and assign registers to constraints that want a specific physreg.
5174 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5175 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5177 // If this is an output operand with a matching input operand, look up the
5178 // matching input. If their types mismatch, e.g. one is an integer, the
5179 // other is floating point, or their sizes are different, flag it as an
5181 if (OpInfo.hasMatchingInput()) {
5182 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5183 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5184 if ((OpInfo.ConstraintVT.isInteger() !=
5185 Input.ConstraintVT.isInteger()) ||
5186 (OpInfo.ConstraintVT.getSizeInBits() !=
5187 Input.ConstraintVT.getSizeInBits())) {
5188 llvm_report_error("Unsupported asm: input constraint"
5189 " with a matching output constraint of incompatible"
5192 Input.ConstraintVT = OpInfo.ConstraintVT;
5196 // Compute the constraint code and ConstraintType to use.
5197 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5199 // If this is a memory input, and if the operand is not indirect, do what we
5200 // need to to provide an address for the memory input.
5201 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5202 !OpInfo.isIndirect) {
5203 assert(OpInfo.Type == InlineAsm::isInput &&
5204 "Can only indirectify direct input operands!");
5206 // Memory operands really want the address of the value. If we don't have
5207 // an indirect input, put it in the constpool if we can, otherwise spill
5208 // it to a stack slot.
5210 // If the operand is a float, integer, or vector constant, spill to a
5211 // constant pool entry to get its address.
5212 Value *OpVal = OpInfo.CallOperandVal;
5213 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5214 isa<ConstantVector>(OpVal)) {
5215 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5216 TLI.getPointerTy());
5218 // Otherwise, create a stack slot and emit a store to it before the
5220 const Type *Ty = OpVal->getType();
5221 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5222 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5223 MachineFunction &MF = DAG.getMachineFunction();
5224 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5225 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5226 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5227 OpInfo.CallOperand, StackSlot, NULL, 0);
5228 OpInfo.CallOperand = StackSlot;
5231 // There is no longer a Value* corresponding to this operand.
5232 OpInfo.CallOperandVal = 0;
5233 // It is now an indirect operand.
5234 OpInfo.isIndirect = true;
5237 // If this constraint is for a specific register, allocate it before
5239 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5240 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5242 ConstraintInfos.clear();
5245 // Second pass - Loop over all of the operands, assigning virtual or physregs
5246 // to register class operands.
5247 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5248 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5250 // C_Register operands have already been allocated, Other/Memory don't need
5252 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5253 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5256 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5257 std::vector<SDValue> AsmNodeOperands;
5258 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5259 AsmNodeOperands.push_back(
5260 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5263 // Loop over all of the inputs, copying the operand values into the
5264 // appropriate registers and processing the output regs.
5265 RegsForValue RetValRegs;
5267 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5268 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5270 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5271 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5273 switch (OpInfo.Type) {
5274 case InlineAsm::isOutput: {
5275 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5276 OpInfo.ConstraintType != TargetLowering::C_Register) {
5277 // Memory output, or 'other' output (e.g. 'X' constraint).
5278 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5280 // Add information to the INLINEASM node to know about this output.
5281 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5282 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5283 TLI.getPointerTy()));
5284 AsmNodeOperands.push_back(OpInfo.CallOperand);
5288 // Otherwise, this is a register or register class output.
5290 // Copy the output from the appropriate register. Find a register that
5292 if (OpInfo.AssignedRegs.Regs.empty()) {
5293 llvm_report_error("Couldn't allocate output reg for"
5294 " constraint '" + OpInfo.ConstraintCode + "'!");
5297 // If this is an indirect operand, store through the pointer after the
5299 if (OpInfo.isIndirect) {
5300 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5301 OpInfo.CallOperandVal));
5303 // This is the result value of the call.
5304 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5306 // Concatenate this output onto the outputs list.
5307 RetValRegs.append(OpInfo.AssignedRegs);
5310 // Add information to the INLINEASM node to know that this register is
5312 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5313 6 /* EARLYCLOBBER REGDEF */ :
5317 DAG, AsmNodeOperands);
5320 case InlineAsm::isInput: {
5321 SDValue InOperandVal = OpInfo.CallOperand;
5323 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5324 // If this is required to match an output register we have already set,
5325 // just use its register.
5326 unsigned OperandNo = OpInfo.getMatchedOperand();
5328 // Scan until we find the definition we already emitted of this operand.
5329 // When we find it, create a RegsForValue operand.
5330 unsigned CurOp = 2; // The first operand.
5331 for (; OperandNo; --OperandNo) {
5332 // Advance to the next operand.
5334 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5335 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5336 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5337 (OpFlag & 7) == 4 /*MEM*/) &&
5338 "Skipped past definitions?");
5339 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5343 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5344 if ((OpFlag & 7) == 2 /*REGDEF*/
5345 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5346 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5347 if (OpInfo.isIndirect) {
5348 llvm_report_error("Don't know how to handle tied indirect "
5349 "register inputs yet!");
5351 RegsForValue MatchedRegs;
5352 MatchedRegs.TLI = &TLI;
5353 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5354 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5355 MatchedRegs.RegVTs.push_back(RegVT);
5356 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5357 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5360 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5362 // Use the produced MatchedRegs object to
5363 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5365 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5366 true, OpInfo.getMatchedOperand(),
5367 DAG, AsmNodeOperands);
5370 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5371 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5372 "Unexpected number of operands");
5373 // Add information to the INLINEASM node to know about this input.
5374 // See InlineAsm.h isUseOperandTiedToDef.
5375 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5376 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5377 TLI.getPointerTy()));
5378 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5383 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5384 assert(!OpInfo.isIndirect &&
5385 "Don't know how to handle indirect other inputs yet!");
5387 std::vector<SDValue> Ops;
5388 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5389 hasMemory, Ops, DAG);
5391 llvm_report_error("Invalid operand for inline asm"
5392 " constraint '" + OpInfo.ConstraintCode + "'!");
5395 // Add information to the INLINEASM node to know about this input.
5396 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5397 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5398 TLI.getPointerTy()));
5399 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5401 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5402 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5403 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5404 "Memory operands expect pointer values");
5406 // Add information to the INLINEASM node to know about this input.
5407 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5408 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5409 TLI.getPointerTy()));
5410 AsmNodeOperands.push_back(InOperandVal);
5414 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5415 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5416 "Unknown constraint type!");
5417 assert(!OpInfo.isIndirect &&
5418 "Don't know how to handle indirect register inputs yet!");
5420 // Copy the input into the appropriate registers.
5421 if (OpInfo.AssignedRegs.Regs.empty()) {
5422 llvm_report_error("Couldn't allocate input reg for"
5423 " constraint '"+ OpInfo.ConstraintCode +"'!");
5426 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5429 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5430 DAG, AsmNodeOperands);
5433 case InlineAsm::isClobber: {
5434 // Add the clobbered value to the operand list, so that the register
5435 // allocator is aware that the physreg got clobbered.
5436 if (!OpInfo.AssignedRegs.Regs.empty())
5437 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5438 false, 0, DAG,AsmNodeOperands);
5444 // Finish up input operands.
5445 AsmNodeOperands[0] = Chain;
5446 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5448 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5449 DAG.getVTList(MVT::Other, MVT::Flag),
5450 &AsmNodeOperands[0], AsmNodeOperands.size());
5451 Flag = Chain.getValue(1);
5453 // If this asm returns a register value, copy the result from that register
5454 // and set it as the value of the call.
5455 if (!RetValRegs.Regs.empty()) {
5456 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5459 // FIXME: Why don't we do this for inline asms with MRVs?
5460 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5461 EVT ResultType = TLI.getValueType(CS.getType());
5463 // If any of the results of the inline asm is a vector, it may have the
5464 // wrong width/num elts. This can happen for register classes that can
5465 // contain multiple different value types. The preg or vreg allocated may
5466 // not have the same VT as was expected. Convert it to the right type
5467 // with bit_convert.
5468 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5469 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5472 } else if (ResultType != Val.getValueType() &&
5473 ResultType.isInteger() && Val.getValueType().isInteger()) {
5474 // If a result value was tied to an input value, the computed result may
5475 // have a wider width than the expected result. Extract the relevant
5477 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5480 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5483 setValue(CS.getInstruction(), Val);
5484 // Don't need to use this as a chain in this case.
5485 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5489 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5491 // Process indirect outputs, first output all of the flagged copies out of
5493 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5494 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5495 Value *Ptr = IndirectStoresToEmit[i].second;
5496 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5498 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5502 // Emit the non-flagged stores from the physregs.
5503 SmallVector<SDValue, 8> OutChains;
5504 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5505 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5506 StoresToEmit[i].first,
5507 getValue(StoresToEmit[i].second),
5508 StoresToEmit[i].second, 0));
5509 if (!OutChains.empty())
5510 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5511 &OutChains[0], OutChains.size());
5516 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5517 SDValue Src = getValue(I.getOperand(0));
5519 // Scale up by the type size in the original i32 type width. Various
5520 // mid-level optimizers may make assumptions about demanded bits etc from the
5521 // i32-ness of the optimizer: we do not want to promote to i64 and then
5522 // multiply on 64-bit targets.
5523 // FIXME: Malloc inst should go away: PR715.
5524 uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
5525 if (ElementSize != 1) {
5526 // Src is always 32-bits, make sure the constant fits.
5527 assert(Src.getValueType() == MVT::i32);
5528 ElementSize = (uint32_t)ElementSize;
5529 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5530 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5533 EVT IntPtr = TLI.getPointerTy();
5535 if (IntPtr.bitsLT(Src.getValueType()))
5536 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5537 else if (IntPtr.bitsGT(Src.getValueType()))
5538 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5540 TargetLowering::ArgListTy Args;
5541 TargetLowering::ArgListEntry Entry;
5543 Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext());
5544 Args.push_back(Entry);
5546 bool isTailCall = PerformTailCallOpt &&
5547 isInTailCallPosition(&I, Attribute::None, TLI);
5548 std::pair<SDValue,SDValue> Result =
5549 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5550 0, CallingConv::C, isTailCall,
5551 /*isReturnValueUsed=*/true,
5552 DAG.getExternalSymbol("malloc", IntPtr),
5553 Args, DAG, getCurDebugLoc());
5554 if (Result.first.getNode())
5555 setValue(&I, Result.first); // Pointers always fit in registers
5556 if (Result.second.getNode())
5557 DAG.setRoot(Result.second);
5560 void SelectionDAGLowering::visitFree(FreeInst &I) {
5561 TargetLowering::ArgListTy Args;
5562 TargetLowering::ArgListEntry Entry;
5563 Entry.Node = getValue(I.getOperand(0));
5564 Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext());
5565 Args.push_back(Entry);
5566 EVT IntPtr = TLI.getPointerTy();
5567 bool isTailCall = PerformTailCallOpt &&
5568 isInTailCallPosition(&I, Attribute::None, TLI);
5569 std::pair<SDValue,SDValue> Result =
5570 TLI.LowerCallTo(getRoot(), Type::getVoidTy(*DAG.getContext()),
5571 false, false, false, false,
5572 0, CallingConv::C, isTailCall,
5573 /*isReturnValueUsed=*/true,
5574 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5576 if (Result.second.getNode())
5577 DAG.setRoot(Result.second);
5580 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5581 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5582 MVT::Other, getRoot(),
5583 getValue(I.getOperand(1)),
5584 DAG.getSrcValue(I.getOperand(1))));
5587 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5588 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5589 getRoot(), getValue(I.getOperand(0)),
5590 DAG.getSrcValue(I.getOperand(0)));
5592 DAG.setRoot(V.getValue(1));
5595 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5596 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5597 MVT::Other, getRoot(),
5598 getValue(I.getOperand(1)),
5599 DAG.getSrcValue(I.getOperand(1))));
5602 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5603 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5604 MVT::Other, getRoot(),
5605 getValue(I.getOperand(1)),
5606 getValue(I.getOperand(2)),
5607 DAG.getSrcValue(I.getOperand(1)),
5608 DAG.getSrcValue(I.getOperand(2))));
5611 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5612 /// implementation, which just calls LowerCall.
5613 /// FIXME: When all targets are
5614 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5615 std::pair<SDValue, SDValue>
5616 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5617 bool RetSExt, bool RetZExt, bool isVarArg,
5618 bool isInreg, unsigned NumFixedArgs,
5619 CallingConv::ID CallConv, bool isTailCall,
5620 bool isReturnValueUsed,
5622 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5624 assert((!isTailCall || PerformTailCallOpt) &&
5625 "isTailCall set when tail-call optimizations are disabled!");
5627 // Handle all of the outgoing arguments.
5628 SmallVector<ISD::OutputArg, 32> Outs;
5629 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5630 SmallVector<EVT, 4> ValueVTs;
5631 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5632 for (unsigned Value = 0, NumValues = ValueVTs.size();
5633 Value != NumValues; ++Value) {
5634 EVT VT = ValueVTs[Value];
5635 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5636 SDValue Op = SDValue(Args[i].Node.getNode(),
5637 Args[i].Node.getResNo() + Value);
5638 ISD::ArgFlagsTy Flags;
5639 unsigned OriginalAlignment =
5640 getTargetData()->getABITypeAlignment(ArgTy);
5646 if (Args[i].isInReg)
5650 if (Args[i].isByVal) {
5652 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5653 const Type *ElementTy = Ty->getElementType();
5654 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5655 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5656 // For ByVal, alignment should come from FE. BE will guess if this
5657 // info is not there but there are cases it cannot get right.
5658 if (Args[i].Alignment)
5659 FrameAlign = Args[i].Alignment;
5660 Flags.setByValAlign(FrameAlign);
5661 Flags.setByValSize(FrameSize);
5665 Flags.setOrigAlign(OriginalAlignment);
5667 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5668 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5669 SmallVector<SDValue, 4> Parts(NumParts);
5670 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5673 ExtendKind = ISD::SIGN_EXTEND;
5674 else if (Args[i].isZExt)
5675 ExtendKind = ISD::ZERO_EXTEND;
5677 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5679 for (unsigned j = 0; j != NumParts; ++j) {
5680 // if it isn't first piece, alignment must be 1
5681 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5682 if (NumParts > 1 && j == 0)
5683 MyFlags.Flags.setSplit();
5685 MyFlags.Flags.setOrigAlign(1);
5687 Outs.push_back(MyFlags);
5692 // Handle the incoming return values from the call.
5693 SmallVector<ISD::InputArg, 32> Ins;
5694 SmallVector<EVT, 4> RetTys;
5695 ComputeValueVTs(*this, RetTy, RetTys);
5696 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5698 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5699 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5700 for (unsigned i = 0; i != NumRegs; ++i) {
5701 ISD::InputArg MyFlags;
5702 MyFlags.VT = RegisterVT;
5703 MyFlags.Used = isReturnValueUsed;
5705 MyFlags.Flags.setSExt();
5707 MyFlags.Flags.setZExt();
5709 MyFlags.Flags.setInReg();
5710 Ins.push_back(MyFlags);
5714 // Check if target-dependent constraints permit a tail call here.
5715 // Target-independent constraints should be checked by the caller.
5717 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
5720 SmallVector<SDValue, 4> InVals;
5721 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5722 Outs, Ins, dl, DAG, InVals);
5724 // Verify that the target's LowerCall behaved as expected.
5725 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5726 "LowerCall didn't return a valid chain!");
5727 assert((!isTailCall || InVals.empty()) &&
5728 "LowerCall emitted a return value for a tail call!");
5729 assert((isTailCall || InVals.size() == Ins.size()) &&
5730 "LowerCall didn't emit the correct number of values!");
5731 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5732 assert(InVals[i].getNode() &&
5733 "LowerCall emitted a null value!");
5734 assert(Ins[i].VT == InVals[i].getValueType() &&
5735 "LowerCall emitted a value with the wrong type!");
5738 // For a tail call, the return value is merely live-out and there aren't
5739 // any nodes in the DAG representing it. Return a special value to
5740 // indicate that a tail call has been emitted and no more Instructions
5741 // should be processed in the current block.
5744 return std::make_pair(SDValue(), SDValue());
5747 // Collect the legal value parts into potentially illegal values
5748 // that correspond to the original function's return values.
5749 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5751 AssertOp = ISD::AssertSext;
5753 AssertOp = ISD::AssertZext;
5754 SmallVector<SDValue, 4> ReturnValues;
5755 unsigned CurReg = 0;
5756 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5758 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5759 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5761 SDValue ReturnValue =
5762 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
5764 ReturnValues.push_back(ReturnValue);
5768 // For a function returning void, there is no return value. We can't create
5769 // such a node, so we just return a null return value in that case. In
5770 // that case, nothing will actualy look at the value.
5771 if (ReturnValues.empty())
5772 return std::make_pair(SDValue(), Chain);
5774 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5775 DAG.getVTList(&RetTys[0], RetTys.size()),
5776 &ReturnValues[0], ReturnValues.size());
5778 return std::make_pair(Res, Chain);
5781 void TargetLowering::LowerOperationWrapper(SDNode *N,
5782 SmallVectorImpl<SDValue> &Results,
5783 SelectionDAG &DAG) {
5784 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5786 Results.push_back(Res);
5789 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5790 llvm_unreachable("LowerOperation not implemented for this target!");
5795 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5796 SDValue Op = getValue(V);
5797 assert((Op.getOpcode() != ISD::CopyFromReg ||
5798 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5799 "Copy from a reg to the same reg!");
5800 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5802 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5803 SDValue Chain = DAG.getEntryNode();
5804 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5805 PendingExports.push_back(Chain);
5808 #include "llvm/CodeGen/SelectionDAGISel.h"
5810 void SelectionDAGISel::
5811 LowerArguments(BasicBlock *LLVMBB) {
5812 // If this is the entry block, emit arguments.
5813 Function &F = *LLVMBB->getParent();
5814 SelectionDAG &DAG = SDL->DAG;
5815 SDValue OldRoot = DAG.getRoot();
5816 DebugLoc dl = SDL->getCurDebugLoc();
5817 const TargetData *TD = TLI.getTargetData();
5819 // Set up the incoming argument description vector.
5820 SmallVector<ISD::InputArg, 16> Ins;
5822 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5823 I != E; ++I, ++Idx) {
5824 SmallVector<EVT, 4> ValueVTs;
5825 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5826 bool isArgValueUsed = !I->use_empty();
5827 for (unsigned Value = 0, NumValues = ValueVTs.size();
5828 Value != NumValues; ++Value) {
5829 EVT VT = ValueVTs[Value];
5830 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5831 ISD::ArgFlagsTy Flags;
5832 unsigned OriginalAlignment =
5833 TD->getABITypeAlignment(ArgTy);
5835 if (F.paramHasAttr(Idx, Attribute::ZExt))
5837 if (F.paramHasAttr(Idx, Attribute::SExt))
5839 if (F.paramHasAttr(Idx, Attribute::InReg))
5841 if (F.paramHasAttr(Idx, Attribute::StructRet))
5843 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5845 const PointerType *Ty = cast<PointerType>(I->getType());
5846 const Type *ElementTy = Ty->getElementType();
5847 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5848 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5849 // For ByVal, alignment should be passed from FE. BE will guess if
5850 // this info is not there but there are cases it cannot get right.
5851 if (F.getParamAlignment(Idx))
5852 FrameAlign = F.getParamAlignment(Idx);
5853 Flags.setByValAlign(FrameAlign);
5854 Flags.setByValSize(FrameSize);
5856 if (F.paramHasAttr(Idx, Attribute::Nest))
5858 Flags.setOrigAlign(OriginalAlignment);
5860 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5861 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5862 for (unsigned i = 0; i != NumRegs; ++i) {
5863 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5864 if (NumRegs > 1 && i == 0)
5865 MyFlags.Flags.setSplit();
5866 // if it isn't first piece, alignment must be 1
5868 MyFlags.Flags.setOrigAlign(1);
5869 Ins.push_back(MyFlags);
5874 // Call the target to set up the argument values.
5875 SmallVector<SDValue, 8> InVals;
5876 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5880 // Verify that the target's LowerFormalArguments behaved as expected.
5881 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5882 "LowerFormalArguments didn't return a valid chain!");
5883 assert(InVals.size() == Ins.size() &&
5884 "LowerFormalArguments didn't emit the correct number of values!");
5885 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5886 assert(InVals[i].getNode() &&
5887 "LowerFormalArguments emitted a null value!");
5888 assert(Ins[i].VT == InVals[i].getValueType() &&
5889 "LowerFormalArguments emitted a value with the wrong type!");
5892 // Update the DAG with the new chain value resulting from argument lowering.
5893 DAG.setRoot(NewRoot);
5895 // Set up the argument values.
5898 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5900 SmallVector<SDValue, 4> ArgValues;
5901 SmallVector<EVT, 4> ValueVTs;
5902 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5903 unsigned NumValues = ValueVTs.size();
5904 for (unsigned Value = 0; Value != NumValues; ++Value) {
5905 EVT VT = ValueVTs[Value];
5906 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5907 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5909 if (!I->use_empty()) {
5910 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5911 if (F.paramHasAttr(Idx, Attribute::SExt))
5912 AssertOp = ISD::AssertSext;
5913 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5914 AssertOp = ISD::AssertZext;
5916 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
5917 PartVT, VT, AssertOp));
5921 if (!I->use_empty()) {
5922 SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
5923 SDL->getCurDebugLoc()));
5924 // If this argument is live outside of the entry block, insert a copy from
5925 // whereever we got it to the vreg that other BB's will reference it as.
5926 SDL->CopyToExportRegsIfNeeded(I);
5929 assert(i == InVals.size() && "Argument register count mismatch!");
5931 // Finally, if the target has anything special to do, allow it to do so.
5932 // FIXME: this should insert code into the DAG!
5933 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5936 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5937 /// ensure constants are generated when needed. Remember the virtual registers
5938 /// that need to be added to the Machine PHI nodes as input. We cannot just
5939 /// directly add them, because expansion might result in multiple MBB's for one
5940 /// BB. As such, the start of the BB might correspond to a different MBB than
5944 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5945 TerminatorInst *TI = LLVMBB->getTerminator();
5947 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5949 // Check successor nodes' PHI nodes that expect a constant to be available
5951 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5952 BasicBlock *SuccBB = TI->getSuccessor(succ);
5953 if (!isa<PHINode>(SuccBB->begin())) continue;
5954 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5956 // If this terminator has multiple identical successors (common for
5957 // switches), only handle each succ once.
5958 if (!SuccsHandled.insert(SuccMBB)) continue;
5960 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5963 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5964 // nodes and Machine PHI nodes, but the incoming operands have not been
5966 for (BasicBlock::iterator I = SuccBB->begin();
5967 (PN = dyn_cast<PHINode>(I)); ++I) {
5968 // Ignore dead phi's.
5969 if (PN->use_empty()) continue;
5972 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5974 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5975 unsigned &RegOut = SDL->ConstantsOut[C];
5977 RegOut = FuncInfo->CreateRegForValue(C);
5978 SDL->CopyValueToVirtualRegister(C, RegOut);
5982 Reg = FuncInfo->ValueMap[PHIOp];
5984 assert(isa<AllocaInst>(PHIOp) &&
5985 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5986 "Didn't codegen value into a register!??");
5987 Reg = FuncInfo->CreateRegForValue(PHIOp);
5988 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5992 // Remember that this register needs to added to the machine PHI node as
5993 // the input for this MBB.
5994 SmallVector<EVT, 4> ValueVTs;
5995 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5996 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5997 EVT VT = ValueVTs[vti];
5998 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5999 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6000 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6001 Reg += NumRegisters;
6005 SDL->ConstantsOut.clear();
6008 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6009 /// supports legal types, and it emits MachineInstrs directly instead of
6010 /// creating SelectionDAG nodes.
6013 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6015 TerminatorInst *TI = LLVMBB->getTerminator();
6017 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6018 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6020 // Check successor nodes' PHI nodes that expect a constant to be available
6022 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6023 BasicBlock *SuccBB = TI->getSuccessor(succ);
6024 if (!isa<PHINode>(SuccBB->begin())) continue;
6025 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6027 // If this terminator has multiple identical successors (common for
6028 // switches), only handle each succ once.
6029 if (!SuccsHandled.insert(SuccMBB)) continue;
6031 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6034 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6035 // nodes and Machine PHI nodes, but the incoming operands have not been
6037 for (BasicBlock::iterator I = SuccBB->begin();
6038 (PN = dyn_cast<PHINode>(I)); ++I) {
6039 // Ignore dead phi's.
6040 if (PN->use_empty()) continue;
6042 // Only handle legal types. Two interesting things to note here. First,
6043 // by bailing out early, we may leave behind some dead instructions,
6044 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6045 // own moves. Second, this check is necessary becuase FastISel doesn't
6046 // use CreateRegForValue to create registers, so it always creates
6047 // exactly one register for each non-void instruction.
6048 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6049 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6052 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6054 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6059 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6061 unsigned Reg = F->getRegForValue(PHIOp);
6063 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6066 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));