1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
51 /// LimitFloatPrecision - Generate low-precision inline sequences for
52 /// some float libcalls (6, 8 or 12 bits).
53 static unsigned LimitFloatPrecision;
55 static cl::opt<unsigned, true>
56 LimitFPPrecision("limit-float-precision",
57 cl::desc("Generate low-precision inline sequences "
58 "for some float libcalls"),
59 cl::location(LimitFloatPrecision),
62 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
63 /// insertvalue or extractvalue indices that identify a member, return
64 /// the linearized index of the start of the member.
66 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
67 const unsigned *Indices,
68 const unsigned *IndicesEnd,
69 unsigned CurIndex = 0) {
70 // Base case: We're done.
71 if (Indices && Indices == IndicesEnd)
74 // Given a struct type, recursively traverse the elements.
75 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
76 for (StructType::element_iterator EB = STy->element_begin(),
78 EE = STy->element_end();
80 if (Indices && *Indices == unsigned(EI - EB))
81 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
82 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
85 // Given an array type, recursively traverse the elements.
86 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
87 const Type *EltTy = ATy->getElementType();
88 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
89 if (Indices && *Indices == i)
90 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
91 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
94 // We haven't found the type we're looking for, so keep searching.
98 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
99 /// MVTs that represent all the individual underlying
100 /// non-aggregate types that comprise it.
102 /// If Offsets is non-null, it points to a vector to be filled in
103 /// with the in-memory offsets of each of the individual values.
105 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
106 SmallVectorImpl<MVT> &ValueVTs,
107 SmallVectorImpl<uint64_t> *Offsets = 0,
108 uint64_t StartingOffset = 0) {
109 // Given a struct type, recursively traverse the elements.
110 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
111 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
112 for (StructType::element_iterator EB = STy->element_begin(),
114 EE = STy->element_end();
116 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
117 StartingOffset + SL->getElementOffset(EI - EB));
120 // Given an array type, recursively traverse the elements.
121 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
122 const Type *EltTy = ATy->getElementType();
123 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
124 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
125 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
126 StartingOffset + i * EltSize);
129 // Base case: we can get an MVT for this LLVM IR type.
130 ValueVTs.push_back(TLI.getValueType(Ty));
132 Offsets->push_back(StartingOffset);
136 /// RegsForValue - This struct represents the registers (physical or virtual)
137 /// that a particular set of values is assigned, and the type information about
138 /// the value. The most common situation is to represent one value at a time,
139 /// but struct or array values are handled element-wise as multiple values.
140 /// The splitting of aggregates is performed recursively, so that we never
141 /// have aggregate-typed registers. The values at this point do not necessarily
142 /// have legal types, so each value may require one or more registers of some
145 struct VISIBILITY_HIDDEN RegsForValue {
146 /// TLI - The TargetLowering object.
148 const TargetLowering *TLI;
150 /// ValueVTs - The value types of the values, which may not be legal, and
151 /// may need be promoted or synthesized from one or more registers.
153 SmallVector<MVT, 4> ValueVTs;
155 /// RegVTs - The value types of the registers. This is the same size as
156 /// ValueVTs and it records, for each value, what the type of the assigned
157 /// register or registers are. (Individual values are never synthesized
158 /// from more than one type of register.)
160 /// With virtual registers, the contents of RegVTs is redundant with TLI's
161 /// getRegisterType member function, however when with physical registers
162 /// it is necessary to have a separate record of the types.
164 SmallVector<MVT, 4> RegVTs;
166 /// Regs - This list holds the registers assigned to the values.
167 /// Each legal or promoted value requires one register, and each
168 /// expanded value requires multiple registers.
170 SmallVector<unsigned, 4> Regs;
172 RegsForValue() : TLI(0) {}
174 RegsForValue(const TargetLowering &tli,
175 const SmallVector<unsigned, 4> ®s,
176 MVT regvt, MVT valuevt)
177 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
178 RegsForValue(const TargetLowering &tli,
179 const SmallVector<unsigned, 4> ®s,
180 const SmallVector<MVT, 4> ®vts,
181 const SmallVector<MVT, 4> &valuevts)
182 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
183 RegsForValue(const TargetLowering &tli,
184 unsigned Reg, const Type *Ty) : TLI(&tli) {
185 ComputeValueVTs(tli, Ty, ValueVTs);
187 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
188 MVT ValueVT = ValueVTs[Value];
189 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
190 MVT RegisterVT = TLI->getRegisterType(ValueVT);
191 for (unsigned i = 0; i != NumRegs; ++i)
192 Regs.push_back(Reg + i);
193 RegVTs.push_back(RegisterVT);
198 /// append - Add the specified values to this one.
199 void append(const RegsForValue &RHS) {
201 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
202 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
203 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
207 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
208 /// this value and returns the result as a ValueVTs value. This uses
209 /// Chain/Flag as the input and updates them for the output Chain/Flag.
210 /// If the Flag pointer is NULL, no flag is used.
211 SDValue getCopyFromRegs(SelectionDAG &DAG,
212 SDValue &Chain, SDValue *Flag) const;
214 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
215 /// specified value into the registers specified by this object. This uses
216 /// Chain/Flag as the input and updates them for the output Chain/Flag.
217 /// If the Flag pointer is NULL, no flag is used.
218 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
219 SDValue &Chain, SDValue *Flag) const;
221 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
222 /// operand list. This adds the code marker and includes the number of
223 /// values added into it.
224 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
225 std::vector<SDValue> &Ops) const;
229 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
230 /// PHI nodes or outside of the basic block that defines it, or used by a
231 /// switch or atomic instruction, which may expand to multiple basic blocks.
232 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
233 if (isa<PHINode>(I)) return true;
234 BasicBlock *BB = I->getParent();
235 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
236 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
237 // FIXME: Remove switchinst special case.
238 isa<SwitchInst>(*UI))
243 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
244 /// entry block, return true. This includes arguments used by switches, since
245 /// the switch may expand into multiple basic blocks.
246 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
247 // With FastISel active, we may be splitting blocks, so force creation
248 // of virtual registers for all non-dead arguments.
249 // Don't force virtual registers for byval arguments though, because
250 // fast-isel can't handle those in all cases.
251 if (EnableFastISel && !A->hasByValAttr())
252 return A->use_empty();
254 BasicBlock *Entry = A->getParent()->begin();
255 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
256 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
257 return false; // Use not in entry block.
261 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
265 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
266 bool EnableFastISel) {
269 RegInfo = &MF->getRegInfo();
271 // Create a vreg for each argument register that is not dead and is used
272 // outside of the entry block for the function.
273 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
275 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
276 InitializeRegForValue(AI);
278 // Initialize the mapping of values to registers. This is only set up for
279 // instruction values that are used outside of the block that defines
281 Function::iterator BB = Fn->begin(), EB = Fn->end();
282 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
283 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
284 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
285 const Type *Ty = AI->getAllocatedType();
286 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
288 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
291 TySize *= CUI->getZExtValue(); // Get total allocated size.
292 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
293 StaticAllocaMap[AI] =
294 MF->getFrameInfo()->CreateStackObject(TySize, Align);
297 for (; BB != EB; ++BB)
298 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
299 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
300 if (!isa<AllocaInst>(I) ||
301 !StaticAllocaMap.count(cast<AllocaInst>(I)))
302 InitializeRegForValue(I);
304 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
305 // also creates the initial PHI MachineInstrs, though none of the input
306 // operands are populated.
307 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
308 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
312 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
315 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
316 if (PN->use_empty()) continue;
318 unsigned PHIReg = ValueMap[PN];
319 assert(PHIReg && "PHI node does not have an assigned virtual register!");
321 SmallVector<MVT, 4> ValueVTs;
322 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
323 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
324 MVT VT = ValueVTs[vti];
325 unsigned NumRegisters = TLI.getNumRegisters(VT);
326 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
327 for (unsigned i = 0; i != NumRegisters; ++i)
328 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
329 PHIReg += NumRegisters;
335 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
336 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
339 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
340 /// the correctly promoted or expanded types. Assign these registers
341 /// consecutive vreg numbers and return the first assigned number.
343 /// In the case that the given value has struct or array type, this function
344 /// will assign registers for each member or element.
346 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
347 SmallVector<MVT, 4> ValueVTs;
348 ComputeValueVTs(TLI, V->getType(), ValueVTs);
350 unsigned FirstReg = 0;
351 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
352 MVT ValueVT = ValueVTs[Value];
353 MVT RegisterVT = TLI.getRegisterType(ValueVT);
355 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
356 for (unsigned i = 0; i != NumRegs; ++i) {
357 unsigned R = MakeReg(RegisterVT);
358 if (!FirstReg) FirstReg = R;
364 /// getCopyFromParts - Create a value that contains the specified legal parts
365 /// combined into the value they represent. If the parts combine to a type
366 /// larger then ValueVT then AssertOp can be used to specify whether the extra
367 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
368 /// (ISD::AssertSext).
369 static SDValue getCopyFromParts(SelectionDAG &DAG,
370 const SDValue *Parts,
374 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
375 assert(NumParts > 0 && "No parts to assemble!");
376 TargetLowering &TLI = DAG.getTargetLoweringInfo();
377 SDValue Val = Parts[0];
380 // Assemble the value from multiple parts.
381 if (!ValueVT.isVector()) {
382 unsigned PartBits = PartVT.getSizeInBits();
383 unsigned ValueBits = ValueVT.getSizeInBits();
385 // Assemble the power of 2 part.
386 unsigned RoundParts = NumParts & (NumParts - 1) ?
387 1 << Log2_32(NumParts) : NumParts;
388 unsigned RoundBits = PartBits * RoundParts;
389 MVT RoundVT = RoundBits == ValueBits ?
390 ValueVT : MVT::getIntegerVT(RoundBits);
393 if (RoundParts > 2) {
394 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
395 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
396 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
402 if (TLI.isBigEndian())
404 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
406 if (RoundParts < NumParts) {
407 // Assemble the trailing non-power-of-2 part.
408 unsigned OddParts = NumParts - RoundParts;
409 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
410 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
412 // Combine the round and odd parts.
414 if (TLI.isBigEndian())
416 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
417 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
418 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
419 DAG.getConstant(Lo.getValueType().getSizeInBits(),
420 TLI.getShiftAmountTy()));
421 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
422 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
425 // Handle a multi-element vector.
426 MVT IntermediateVT, RegisterVT;
427 unsigned NumIntermediates;
429 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
431 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
432 NumParts = NumRegs; // Silence a compiler warning.
433 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
434 assert(RegisterVT == Parts[0].getValueType() &&
435 "Part type doesn't match part!");
437 // Assemble the parts into intermediate operands.
438 SmallVector<SDValue, 8> Ops(NumIntermediates);
439 if (NumIntermediates == NumParts) {
440 // If the register was not expanded, truncate or copy the value,
442 for (unsigned i = 0; i != NumParts; ++i)
443 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
444 PartVT, IntermediateVT);
445 } else if (NumParts > 0) {
446 // If the intermediate type was expanded, build the intermediate operands
448 assert(NumParts % NumIntermediates == 0 &&
449 "Must expand into a divisible number of parts!");
450 unsigned Factor = NumParts / NumIntermediates;
451 for (unsigned i = 0; i != NumIntermediates; ++i)
452 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
453 PartVT, IntermediateVT);
456 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
458 Val = DAG.getNode(IntermediateVT.isVector() ?
459 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
460 ValueVT, &Ops[0], NumIntermediates);
464 // There is now one part, held in Val. Correct it to match ValueVT.
465 PartVT = Val.getValueType();
467 if (PartVT == ValueVT)
470 if (PartVT.isVector()) {
471 assert(ValueVT.isVector() && "Unknown vector conversion!");
472 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
475 if (ValueVT.isVector()) {
476 assert(ValueVT.getVectorElementType() == PartVT &&
477 ValueVT.getVectorNumElements() == 1 &&
478 "Only trivial scalar-to-vector conversions should get here!");
479 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
482 if (PartVT.isInteger() &&
483 ValueVT.isInteger()) {
484 if (ValueVT.bitsLT(PartVT)) {
485 // For a truncate, see if we have any information to
486 // indicate whether the truncated bits will always be
487 // zero or sign-extension.
488 if (AssertOp != ISD::DELETED_NODE)
489 Val = DAG.getNode(AssertOp, PartVT, Val,
490 DAG.getValueType(ValueVT));
491 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
493 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
497 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
498 if (ValueVT.bitsLT(Val.getValueType()))
499 // FP_ROUND's are always exact here.
500 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
501 DAG.getIntPtrConstant(1));
502 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
505 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
506 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
508 assert(0 && "Unknown mismatch!");
512 /// getCopyToParts - Create a series of nodes that contain the specified value
513 /// split into legal parts. If the parts contain more bits than Val, then, for
514 /// integers, ExtendKind can be used to specify how to generate the extra bits.
515 static void getCopyToParts(SelectionDAG &DAG,
520 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
521 TargetLowering &TLI = DAG.getTargetLoweringInfo();
522 MVT PtrVT = TLI.getPointerTy();
523 MVT ValueVT = Val.getValueType();
524 unsigned PartBits = PartVT.getSizeInBits();
525 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
530 if (!ValueVT.isVector()) {
531 if (PartVT == ValueVT) {
532 assert(NumParts == 1 && "No-op copy with multiple parts!");
537 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
538 // If the parts cover more bits than the value has, promote the value.
539 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
540 assert(NumParts == 1 && "Do not know what to promote to!");
541 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
542 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
543 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
544 Val = DAG.getNode(ExtendKind, ValueVT, Val);
546 assert(0 && "Unknown mismatch!");
548 } else if (PartBits == ValueVT.getSizeInBits()) {
549 // Different types of the same size.
550 assert(NumParts == 1 && PartVT != ValueVT);
551 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
552 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
553 // If the parts cover less bits than value has, truncate the value.
554 if (PartVT.isInteger() && ValueVT.isInteger()) {
555 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
556 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
558 assert(0 && "Unknown mismatch!");
562 // The value may have changed - recompute ValueVT.
563 ValueVT = Val.getValueType();
564 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
565 "Failed to tile the value with PartVT!");
568 assert(PartVT == ValueVT && "Type conversion failed!");
573 // Expand the value into multiple parts.
574 if (NumParts & (NumParts - 1)) {
575 // The number of parts is not a power of 2. Split off and copy the tail.
576 assert(PartVT.isInteger() && ValueVT.isInteger() &&
577 "Do not know what to expand to!");
578 unsigned RoundParts = 1 << Log2_32(NumParts);
579 unsigned RoundBits = RoundParts * PartBits;
580 unsigned OddParts = NumParts - RoundParts;
581 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
582 DAG.getConstant(RoundBits,
583 TLI.getShiftAmountTy()));
584 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
585 if (TLI.isBigEndian())
586 // The odd parts were reversed by getCopyToParts - unreverse them.
587 std::reverse(Parts + RoundParts, Parts + NumParts);
588 NumParts = RoundParts;
589 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
590 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
593 // The number of parts is a power of 2. Repeatedly bisect the value using
595 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
596 MVT::getIntegerVT(ValueVT.getSizeInBits()),
598 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
599 for (unsigned i = 0; i < NumParts; i += StepSize) {
600 unsigned ThisBits = StepSize * PartBits / 2;
601 MVT ThisVT = MVT::getIntegerVT (ThisBits);
602 SDValue &Part0 = Parts[i];
603 SDValue &Part1 = Parts[i+StepSize/2];
605 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
606 DAG.getConstant(1, PtrVT));
607 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
608 DAG.getConstant(0, PtrVT));
610 if (ThisBits == PartBits && ThisVT != PartVT) {
611 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
612 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
617 if (TLI.isBigEndian())
618 std::reverse(Parts, Parts + NumParts);
625 if (PartVT != ValueVT) {
626 if (PartVT.isVector()) {
627 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
629 assert(ValueVT.getVectorElementType() == PartVT &&
630 ValueVT.getVectorNumElements() == 1 &&
631 "Only trivial vector-to-scalar conversions should get here!");
632 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
633 DAG.getConstant(0, PtrVT));
641 // Handle a multi-element vector.
642 MVT IntermediateVT, RegisterVT;
643 unsigned NumIntermediates;
645 DAG.getTargetLoweringInfo()
646 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
648 unsigned NumElements = ValueVT.getVectorNumElements();
650 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
651 NumParts = NumRegs; // Silence a compiler warning.
652 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
654 // Split the vector into intermediate operands.
655 SmallVector<SDValue, 8> Ops(NumIntermediates);
656 for (unsigned i = 0; i != NumIntermediates; ++i)
657 if (IntermediateVT.isVector())
658 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
660 DAG.getConstant(i * (NumElements / NumIntermediates),
663 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
665 DAG.getConstant(i, PtrVT));
667 // Split the intermediate operands into legal parts.
668 if (NumParts == NumIntermediates) {
669 // If the register was not expanded, promote or copy the value,
671 for (unsigned i = 0; i != NumParts; ++i)
672 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
673 } else if (NumParts > 0) {
674 // If the intermediate type was expanded, split each the value into
676 assert(NumParts % NumIntermediates == 0 &&
677 "Must expand into a divisible number of parts!");
678 unsigned Factor = NumParts / NumIntermediates;
679 for (unsigned i = 0; i != NumIntermediates; ++i)
680 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
685 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
688 TD = DAG.getTarget().getTargetData();
691 /// clear - Clear out the curret SelectionDAG and the associated
692 /// state and prepare this SelectionDAGLowering object to be used
693 /// for a new block. This doesn't clear out information about
694 /// additional blocks that are needed to complete switch lowering
695 /// or PHI node updating; that information is cleared out as it is
697 void SelectionDAGLowering::clear() {
699 PendingLoads.clear();
700 PendingExports.clear();
704 /// getRoot - Return the current virtual root of the Selection DAG,
705 /// flushing any PendingLoad items. This must be done before emitting
706 /// a store or any other node that may need to be ordered after any
707 /// prior load instructions.
709 SDValue SelectionDAGLowering::getRoot() {
710 if (PendingLoads.empty())
711 return DAG.getRoot();
713 if (PendingLoads.size() == 1) {
714 SDValue Root = PendingLoads[0];
716 PendingLoads.clear();
720 // Otherwise, we have to make a token factor node.
721 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
722 &PendingLoads[0], PendingLoads.size());
723 PendingLoads.clear();
728 /// getControlRoot - Similar to getRoot, but instead of flushing all the
729 /// PendingLoad items, flush all the PendingExports items. It is necessary
730 /// to do this before emitting a terminator instruction.
732 SDValue SelectionDAGLowering::getControlRoot() {
733 SDValue Root = DAG.getRoot();
735 if (PendingExports.empty())
738 // Turn all of the CopyToReg chains into one factored node.
739 if (Root.getOpcode() != ISD::EntryToken) {
740 unsigned i = 0, e = PendingExports.size();
741 for (; i != e; ++i) {
742 assert(PendingExports[i].getNode()->getNumOperands() > 1);
743 if (PendingExports[i].getNode()->getOperand(0) == Root)
744 break; // Don't add the root if we already indirectly depend on it.
748 PendingExports.push_back(Root);
751 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
753 PendingExports.size());
754 PendingExports.clear();
759 void SelectionDAGLowering::visit(Instruction &I) {
760 visit(I.getOpcode(), I);
763 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
764 // Note: this doesn't use InstVisitor, because it has to work with
765 // ConstantExpr's in addition to instructions.
767 default: assert(0 && "Unknown instruction type encountered!");
769 // Build the switch statement using the Instruction.def file.
770 #define HANDLE_INST(NUM, OPCODE, CLASS) \
771 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
772 #include "llvm/Instruction.def"
776 void SelectionDAGLowering::visitAdd(User &I) {
777 if (I.getType()->isFPOrFPVector())
778 visitBinary(I, ISD::FADD);
780 visitBinary(I, ISD::ADD);
783 void SelectionDAGLowering::visitMul(User &I) {
784 if (I.getType()->isFPOrFPVector())
785 visitBinary(I, ISD::FMUL);
787 visitBinary(I, ISD::MUL);
790 SDValue SelectionDAGLowering::getValue(const Value *V) {
791 SDValue &N = NodeMap[V];
792 if (N.getNode()) return N;
794 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
795 MVT VT = TLI.getValueType(V->getType(), true);
797 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
798 return N = DAG.getConstant(*CI, VT);
800 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
801 return N = DAG.getGlobalAddress(GV, VT);
803 if (isa<ConstantPointerNull>(C))
804 return N = DAG.getConstant(0, TLI.getPointerTy());
806 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
807 return N = DAG.getConstantFP(*CFP, VT);
809 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
810 !V->getType()->isAggregateType())
811 return N = DAG.getNode(ISD::UNDEF, VT);
813 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
814 visit(CE->getOpcode(), *CE);
815 SDValue N1 = NodeMap[V];
816 assert(N1.getNode() && "visit didn't populate the ValueMap!");
820 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
821 SmallVector<SDValue, 4> Constants;
822 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
824 SDNode *Val = getValue(*OI).getNode();
825 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
826 Constants.push_back(SDValue(Val, i));
828 return DAG.getMergeValues(&Constants[0], Constants.size());
831 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
832 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
833 "Unknown struct or array constant!");
835 SmallVector<MVT, 4> ValueVTs;
836 ComputeValueVTs(TLI, C->getType(), ValueVTs);
837 unsigned NumElts = ValueVTs.size();
839 return SDValue(); // empty struct
840 SmallVector<SDValue, 4> Constants(NumElts);
841 for (unsigned i = 0; i != NumElts; ++i) {
842 MVT EltVT = ValueVTs[i];
843 if (isa<UndefValue>(C))
844 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
845 else if (EltVT.isFloatingPoint())
846 Constants[i] = DAG.getConstantFP(0, EltVT);
848 Constants[i] = DAG.getConstant(0, EltVT);
850 return DAG.getMergeValues(&Constants[0], NumElts);
853 const VectorType *VecTy = cast<VectorType>(V->getType());
854 unsigned NumElements = VecTy->getNumElements();
856 // Now that we know the number and type of the elements, get that number of
857 // elements into the Ops array based on what kind of constant it is.
858 SmallVector<SDValue, 16> Ops;
859 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
860 for (unsigned i = 0; i != NumElements; ++i)
861 Ops.push_back(getValue(CP->getOperand(i)));
863 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
864 "Unknown vector constant!");
865 MVT EltVT = TLI.getValueType(VecTy->getElementType());
868 if (isa<UndefValue>(C))
869 Op = DAG.getNode(ISD::UNDEF, EltVT);
870 else if (EltVT.isFloatingPoint())
871 Op = DAG.getConstantFP(0, EltVT);
873 Op = DAG.getConstant(0, EltVT);
874 Ops.assign(NumElements, Op);
877 // Create a BUILD_VECTOR node.
878 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
881 // If this is a static alloca, generate it as the frameindex instead of
883 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
884 DenseMap<const AllocaInst*, int>::iterator SI =
885 FuncInfo.StaticAllocaMap.find(AI);
886 if (SI != FuncInfo.StaticAllocaMap.end())
887 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
890 unsigned InReg = FuncInfo.ValueMap[V];
891 assert(InReg && "Value not in map!");
893 RegsForValue RFV(TLI, InReg, V->getType());
894 SDValue Chain = DAG.getEntryNode();
895 return RFV.getCopyFromRegs(DAG, Chain, NULL);
899 void SelectionDAGLowering::visitRet(ReturnInst &I) {
900 if (I.getNumOperands() == 0) {
901 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
905 SmallVector<SDValue, 8> NewValues;
906 NewValues.push_back(getControlRoot());
907 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
908 SDValue RetOp = getValue(I.getOperand(i));
910 SmallVector<MVT, 4> ValueVTs;
911 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
912 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
913 MVT VT = ValueVTs[j];
915 // FIXME: C calling convention requires the return type to be promoted to
916 // at least 32-bit. But this is not necessary for non-C calling conventions.
917 if (VT.isInteger()) {
918 MVT MinVT = TLI.getRegisterType(MVT::i32);
919 if (VT.bitsLT(MinVT))
923 unsigned NumParts = TLI.getNumRegisters(VT);
924 MVT PartVT = TLI.getRegisterType(VT);
925 SmallVector<SDValue, 4> Parts(NumParts);
926 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
928 const Function *F = I.getParent()->getParent();
929 if (F->paramHasAttr(0, ParamAttr::SExt))
930 ExtendKind = ISD::SIGN_EXTEND;
931 else if (F->paramHasAttr(0, ParamAttr::ZExt))
932 ExtendKind = ISD::ZERO_EXTEND;
934 getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j),
935 &Parts[0], NumParts, PartVT, ExtendKind);
937 for (unsigned i = 0; i < NumParts; ++i) {
938 NewValues.push_back(Parts[i]);
939 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
943 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
944 &NewValues[0], NewValues.size()));
947 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
948 /// the current basic block, add it to ValueMap now so that we'll get a
950 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
951 // No need to export constants.
952 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
955 if (FuncInfo.isExportedInst(V)) return;
957 unsigned Reg = FuncInfo.InitializeRegForValue(V);
958 CopyValueToVirtualRegister(V, Reg);
961 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
962 const BasicBlock *FromBB) {
963 // The operands of the setcc have to be in this block. We don't know
964 // how to export them from some other block.
965 if (Instruction *VI = dyn_cast<Instruction>(V)) {
966 // Can export from current BB.
967 if (VI->getParent() == FromBB)
970 // Is already exported, noop.
971 return FuncInfo.isExportedInst(V);
974 // If this is an argument, we can export it if the BB is the entry block or
975 // if it is already exported.
976 if (isa<Argument>(V)) {
977 if (FromBB == &FromBB->getParent()->getEntryBlock())
980 // Otherwise, can only export this if it is already exported.
981 return FuncInfo.isExportedInst(V);
984 // Otherwise, constants can always be exported.
988 static bool InBlock(const Value *V, const BasicBlock *BB) {
989 if (const Instruction *I = dyn_cast<Instruction>(V))
990 return I->getParent() == BB;
994 /// FindMergedConditions - If Cond is an expression like
995 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
996 MachineBasicBlock *TBB,
997 MachineBasicBlock *FBB,
998 MachineBasicBlock *CurBB,
1000 // If this node is not part of the or/and tree, emit it as a branch.
1001 Instruction *BOp = dyn_cast<Instruction>(Cond);
1003 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1004 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1005 BOp->getParent() != CurBB->getBasicBlock() ||
1006 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1007 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1008 const BasicBlock *BB = CurBB->getBasicBlock();
1010 // If the leaf of the tree is a comparison, merge the condition into
1012 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1013 // The operands of the cmp have to be in this block. We don't know
1014 // how to export them from some other block. If this is the first block
1015 // of the sequence, no exporting is needed.
1017 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1018 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1019 BOp = cast<Instruction>(Cond);
1020 ISD::CondCode Condition;
1021 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1022 switch (IC->getPredicate()) {
1023 default: assert(0 && "Unknown icmp predicate opcode!");
1024 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1025 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1026 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1027 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1028 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1029 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1030 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1031 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1032 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1033 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1035 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1036 ISD::CondCode FPC, FOC;
1037 switch (FC->getPredicate()) {
1038 default: assert(0 && "Unknown fcmp predicate opcode!");
1039 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1040 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1041 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1042 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1043 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1044 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1045 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1046 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1047 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1048 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1049 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1050 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1051 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1052 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1053 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1054 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1056 if (FiniteOnlyFPMath())
1061 Condition = ISD::SETEQ; // silence warning.
1062 assert(0 && "Unknown compare instruction");
1065 CaseBlock CB(Condition, BOp->getOperand(0),
1066 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1067 SwitchCases.push_back(CB);
1071 // Create a CaseBlock record representing this branch.
1072 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1073 NULL, TBB, FBB, CurBB);
1074 SwitchCases.push_back(CB);
1079 // Create TmpBB after CurBB.
1080 MachineFunction::iterator BBI = CurBB;
1081 MachineFunction &MF = DAG.getMachineFunction();
1082 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1083 CurBB->getParent()->insert(++BBI, TmpBB);
1085 if (Opc == Instruction::Or) {
1086 // Codegen X | Y as:
1094 // Emit the LHS condition.
1095 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1097 // Emit the RHS condition into TmpBB.
1098 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1100 assert(Opc == Instruction::And && "Unknown merge op!");
1101 // Codegen X & Y as:
1108 // This requires creation of TmpBB after CurBB.
1110 // Emit the LHS condition.
1111 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1113 // Emit the RHS condition into TmpBB.
1114 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1118 /// If the set of cases should be emitted as a series of branches, return true.
1119 /// If we should emit this as a bunch of and/or'd together conditions, return
1122 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1123 if (Cases.size() != 2) return true;
1125 // If this is two comparisons of the same values or'd or and'd together, they
1126 // will get folded into a single comparison, so don't emit two blocks.
1127 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1128 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1129 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1130 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1137 void SelectionDAGLowering::visitBr(BranchInst &I) {
1138 // Update machine-CFG edges.
1139 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1141 // Figure out which block is immediately after the current one.
1142 MachineBasicBlock *NextBlock = 0;
1143 MachineFunction::iterator BBI = CurMBB;
1144 if (++BBI != CurMBB->getParent()->end())
1147 if (I.isUnconditional()) {
1148 // Update machine-CFG edges.
1149 CurMBB->addSuccessor(Succ0MBB);
1151 // If this is not a fall-through branch, emit the branch.
1152 if (Succ0MBB != NextBlock)
1153 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1154 DAG.getBasicBlock(Succ0MBB)));
1158 // If this condition is one of the special cases we handle, do special stuff
1160 Value *CondVal = I.getCondition();
1161 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1163 // If this is a series of conditions that are or'd or and'd together, emit
1164 // this as a sequence of branches instead of setcc's with and/or operations.
1165 // For example, instead of something like:
1178 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1179 if (BOp->hasOneUse() &&
1180 (BOp->getOpcode() == Instruction::And ||
1181 BOp->getOpcode() == Instruction::Or)) {
1182 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1183 // If the compares in later blocks need to use values not currently
1184 // exported from this block, export them now. This block should always
1185 // be the first entry.
1186 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1188 // Allow some cases to be rejected.
1189 if (ShouldEmitAsBranches(SwitchCases)) {
1190 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1191 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1192 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1195 // Emit the branch for this block.
1196 visitSwitchCase(SwitchCases[0]);
1197 SwitchCases.erase(SwitchCases.begin());
1201 // Okay, we decided not to do this, remove any inserted MBB's and clear
1203 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1204 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1206 SwitchCases.clear();
1210 // Create a CaseBlock record representing this branch.
1211 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1212 NULL, Succ0MBB, Succ1MBB, CurMBB);
1213 // Use visitSwitchCase to actually insert the fast branch sequence for this
1215 visitSwitchCase(CB);
1218 /// visitSwitchCase - Emits the necessary code to represent a single node in
1219 /// the binary search tree resulting from lowering a switch instruction.
1220 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1222 SDValue CondLHS = getValue(CB.CmpLHS);
1224 // Build the setcc now.
1225 if (CB.CmpMHS == NULL) {
1226 // Fold "(X == true)" to X and "(X == false)" to !X to
1227 // handle common cases produced by branch lowering.
1228 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1230 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1231 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1232 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1234 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1236 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1238 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1239 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1241 SDValue CmpOp = getValue(CB.CmpMHS);
1242 MVT VT = CmpOp.getValueType();
1244 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1245 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1247 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1248 Cond = DAG.getSetCC(MVT::i1, SUB,
1249 DAG.getConstant(High-Low, VT), ISD::SETULE);
1253 // Update successor info
1254 CurMBB->addSuccessor(CB.TrueBB);
1255 CurMBB->addSuccessor(CB.FalseBB);
1257 // Set NextBlock to be the MBB immediately after the current one, if any.
1258 // This is used to avoid emitting unnecessary branches to the next block.
1259 MachineBasicBlock *NextBlock = 0;
1260 MachineFunction::iterator BBI = CurMBB;
1261 if (++BBI != CurMBB->getParent()->end())
1264 // If the lhs block is the next block, invert the condition so that we can
1265 // fall through to the lhs instead of the rhs block.
1266 if (CB.TrueBB == NextBlock) {
1267 std::swap(CB.TrueBB, CB.FalseBB);
1268 SDValue True = DAG.getConstant(1, Cond.getValueType());
1269 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1271 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1272 DAG.getBasicBlock(CB.TrueBB));
1274 // If the branch was constant folded, fix up the CFG.
1275 if (BrCond.getOpcode() == ISD::BR) {
1276 CurMBB->removeSuccessor(CB.FalseBB);
1277 DAG.setRoot(BrCond);
1279 // Otherwise, go ahead and insert the false branch.
1280 if (BrCond == getControlRoot())
1281 CurMBB->removeSuccessor(CB.TrueBB);
1283 if (CB.FalseBB == NextBlock)
1284 DAG.setRoot(BrCond);
1286 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1287 DAG.getBasicBlock(CB.FalseBB)));
1291 /// visitJumpTable - Emit JumpTable node in the current MBB
1292 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1293 // Emit the code for the jump table
1294 assert(JT.Reg != -1U && "Should lower JT Header first!");
1295 MVT PTy = TLI.getPointerTy();
1296 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1297 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1298 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1303 /// visitJumpTableHeader - This function emits necessary code to produce index
1304 /// in the JumpTable from switch case.
1305 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1306 JumpTableHeader &JTH) {
1307 // Subtract the lowest switch case value from the value being switched on
1308 // and conditional branch to default mbb if the result is greater than the
1309 // difference between smallest and largest cases.
1310 SDValue SwitchOp = getValue(JTH.SValue);
1311 MVT VT = SwitchOp.getValueType();
1312 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1313 DAG.getConstant(JTH.First, VT));
1315 // The SDNode we just created, which holds the value being switched on
1316 // minus the the smallest case value, needs to be copied to a virtual
1317 // register so it can be used as an index into the jump table in a
1318 // subsequent basic block. This value may be smaller or larger than the
1319 // target's pointer type, and therefore require extension or truncating.
1320 if (VT.bitsGT(TLI.getPointerTy()))
1321 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1323 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1325 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1326 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1327 JT.Reg = JumpTableReg;
1329 // Emit the range check for the jump table, and branch to the default
1330 // block for the switch statement if the value being switched on exceeds
1331 // the largest case in the switch.
1332 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1333 DAG.getConstant(JTH.Last-JTH.First,VT),
1336 // Set NextBlock to be the MBB immediately after the current one, if any.
1337 // This is used to avoid emitting unnecessary branches to the next block.
1338 MachineBasicBlock *NextBlock = 0;
1339 MachineFunction::iterator BBI = CurMBB;
1340 if (++BBI != CurMBB->getParent()->end())
1343 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1344 DAG.getBasicBlock(JT.Default));
1346 if (JT.MBB == NextBlock)
1347 DAG.setRoot(BrCond);
1349 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1350 DAG.getBasicBlock(JT.MBB)));
1355 /// visitBitTestHeader - This function emits necessary code to produce value
1356 /// suitable for "bit tests"
1357 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1358 // Subtract the minimum value
1359 SDValue SwitchOp = getValue(B.SValue);
1360 MVT VT = SwitchOp.getValueType();
1361 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1362 DAG.getConstant(B.First, VT));
1365 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1366 DAG.getConstant(B.Range, VT),
1370 if (VT.bitsGT(TLI.getShiftAmountTy()))
1371 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1373 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1375 // Make desired shift
1376 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1377 DAG.getConstant(1, TLI.getPointerTy()),
1380 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1381 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1384 // Set NextBlock to be the MBB immediately after the current one, if any.
1385 // This is used to avoid emitting unnecessary branches to the next block.
1386 MachineBasicBlock *NextBlock = 0;
1387 MachineFunction::iterator BBI = CurMBB;
1388 if (++BBI != CurMBB->getParent()->end())
1391 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1393 CurMBB->addSuccessor(B.Default);
1394 CurMBB->addSuccessor(MBB);
1396 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1397 DAG.getBasicBlock(B.Default));
1399 if (MBB == NextBlock)
1400 DAG.setRoot(BrRange);
1402 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1403 DAG.getBasicBlock(MBB)));
1408 /// visitBitTestCase - this function produces one "bit test"
1409 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1412 // Emit bit tests and jumps
1413 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1414 TLI.getPointerTy());
1416 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1417 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1418 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1419 DAG.getConstant(0, TLI.getPointerTy()),
1422 CurMBB->addSuccessor(B.TargetBB);
1423 CurMBB->addSuccessor(NextMBB);
1425 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1426 AndCmp, DAG.getBasicBlock(B.TargetBB));
1428 // Set NextBlock to be the MBB immediately after the current one, if any.
1429 // This is used to avoid emitting unnecessary branches to the next block.
1430 MachineBasicBlock *NextBlock = 0;
1431 MachineFunction::iterator BBI = CurMBB;
1432 if (++BBI != CurMBB->getParent()->end())
1435 if (NextMBB == NextBlock)
1438 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1439 DAG.getBasicBlock(NextMBB)));
1444 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1445 // Retrieve successors.
1446 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1447 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1449 if (isa<InlineAsm>(I.getCalledValue()))
1452 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1454 // If the value of the invoke is used outside of its defining block, make it
1455 // available as a virtual register.
1456 if (!I.use_empty()) {
1457 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1458 if (VMI != FuncInfo.ValueMap.end())
1459 CopyValueToVirtualRegister(&I, VMI->second);
1462 // Update successor info
1463 CurMBB->addSuccessor(Return);
1464 CurMBB->addSuccessor(LandingPad);
1466 // Drop into normal successor.
1467 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1468 DAG.getBasicBlock(Return)));
1471 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1474 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1475 /// small case ranges).
1476 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1477 CaseRecVector& WorkList,
1479 MachineBasicBlock* Default) {
1480 Case& BackCase = *(CR.Range.second-1);
1482 // Size is the number of Cases represented by this range.
1483 unsigned Size = CR.Range.second - CR.Range.first;
1487 // Get the MachineFunction which holds the current MBB. This is used when
1488 // inserting any additional MBBs necessary to represent the switch.
1489 MachineFunction *CurMF = CurMBB->getParent();
1491 // Figure out which block is immediately after the current one.
1492 MachineBasicBlock *NextBlock = 0;
1493 MachineFunction::iterator BBI = CR.CaseBB;
1495 if (++BBI != CurMBB->getParent()->end())
1498 // TODO: If any two of the cases has the same destination, and if one value
1499 // is the same as the other, but has one bit unset that the other has set,
1500 // use bit manipulation to do two compares at once. For example:
1501 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1503 // Rearrange the case blocks so that the last one falls through if possible.
1504 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1505 // The last case block won't fall through into 'NextBlock' if we emit the
1506 // branches in this order. See if rearranging a case value would help.
1507 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1508 if (I->BB == NextBlock) {
1509 std::swap(*I, BackCase);
1515 // Create a CaseBlock record representing a conditional branch to
1516 // the Case's target mbb if the value being switched on SV is equal
1518 MachineBasicBlock *CurBlock = CR.CaseBB;
1519 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1520 MachineBasicBlock *FallThrough;
1522 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1523 CurMF->insert(BBI, FallThrough);
1525 // If the last case doesn't match, go to the default block.
1526 FallThrough = Default;
1529 Value *RHS, *LHS, *MHS;
1531 if (I->High == I->Low) {
1532 // This is just small small case range :) containing exactly 1 case
1534 LHS = SV; RHS = I->High; MHS = NULL;
1537 LHS = I->Low; MHS = SV; RHS = I->High;
1539 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1541 // If emitting the first comparison, just call visitSwitchCase to emit the
1542 // code into the current block. Otherwise, push the CaseBlock onto the
1543 // vector to be later processed by SDISel, and insert the node's MBB
1544 // before the next MBB.
1545 if (CurBlock == CurMBB)
1546 visitSwitchCase(CB);
1548 SwitchCases.push_back(CB);
1550 CurBlock = FallThrough;
1556 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1557 return !DisableJumpTables &&
1558 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1559 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1562 /// handleJTSwitchCase - Emit jumptable for current switch case range
1563 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1564 CaseRecVector& WorkList,
1566 MachineBasicBlock* Default) {
1567 Case& FrontCase = *CR.Range.first;
1568 Case& BackCase = *(CR.Range.second-1);
1570 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1571 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1574 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1578 if (!areJTsAllowed(TLI) || TSize <= 3)
1581 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1585 DOUT << "Lowering jump table\n"
1586 << "First entry: " << First << ". Last entry: " << Last << "\n"
1587 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1589 // Get the MachineFunction which holds the current MBB. This is used when
1590 // inserting any additional MBBs necessary to represent the switch.
1591 MachineFunction *CurMF = CurMBB->getParent();
1593 // Figure out which block is immediately after the current one.
1594 MachineBasicBlock *NextBlock = 0;
1595 MachineFunction::iterator BBI = CR.CaseBB;
1597 if (++BBI != CurMBB->getParent()->end())
1600 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1602 // Create a new basic block to hold the code for loading the address
1603 // of the jump table, and jumping to it. Update successor information;
1604 // we will either branch to the default case for the switch, or the jump
1606 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1607 CurMF->insert(BBI, JumpTableBB);
1608 CR.CaseBB->addSuccessor(Default);
1609 CR.CaseBB->addSuccessor(JumpTableBB);
1611 // Build a vector of destination BBs, corresponding to each target
1612 // of the jump table. If the value of the jump table slot corresponds to
1613 // a case statement, push the case's BB onto the vector, otherwise, push
1615 std::vector<MachineBasicBlock*> DestBBs;
1616 int64_t TEI = First;
1617 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1618 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1619 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1621 if ((Low <= TEI) && (TEI <= High)) {
1622 DestBBs.push_back(I->BB);
1626 DestBBs.push_back(Default);
1630 // Update successor info. Add one edge to each unique successor.
1631 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1632 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1633 E = DestBBs.end(); I != E; ++I) {
1634 if (!SuccsHandled[(*I)->getNumber()]) {
1635 SuccsHandled[(*I)->getNumber()] = true;
1636 JumpTableBB->addSuccessor(*I);
1640 // Create a jump table index for this jump table, or return an existing
1642 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1644 // Set the jump table information so that we can codegen it as a second
1645 // MachineBasicBlock
1646 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1647 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1648 if (CR.CaseBB == CurMBB)
1649 visitJumpTableHeader(JT, JTH);
1651 JTCases.push_back(JumpTableBlock(JTH, JT));
1656 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1658 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1659 CaseRecVector& WorkList,
1661 MachineBasicBlock* Default) {
1662 // Get the MachineFunction which holds the current MBB. This is used when
1663 // inserting any additional MBBs necessary to represent the switch.
1664 MachineFunction *CurMF = CurMBB->getParent();
1666 // Figure out which block is immediately after the current one.
1667 MachineBasicBlock *NextBlock = 0;
1668 MachineFunction::iterator BBI = CR.CaseBB;
1670 if (++BBI != CurMBB->getParent()->end())
1673 Case& FrontCase = *CR.Range.first;
1674 Case& BackCase = *(CR.Range.second-1);
1675 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1677 // Size is the number of Cases represented by this range.
1678 unsigned Size = CR.Range.second - CR.Range.first;
1680 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1681 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1683 CaseItr Pivot = CR.Range.first + Size/2;
1685 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1686 // (heuristically) allow us to emit JumpTable's later.
1688 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1692 uint64_t LSize = FrontCase.size();
1693 uint64_t RSize = TSize-LSize;
1694 DOUT << "Selecting best pivot: \n"
1695 << "First: " << First << ", Last: " << Last <<"\n"
1696 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1697 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1699 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1700 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1701 assert((RBegin-LEnd>=1) && "Invalid case distance");
1702 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1703 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1704 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1705 // Should always split in some non-trivial place
1707 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1708 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1709 << "Metric: " << Metric << "\n";
1710 if (FMetric < Metric) {
1713 DOUT << "Current metric set to: " << FMetric << "\n";
1719 if (areJTsAllowed(TLI)) {
1720 // If our case is dense we *really* should handle it earlier!
1721 assert((FMetric > 0) && "Should handle dense range earlier!");
1723 Pivot = CR.Range.first + Size/2;
1726 CaseRange LHSR(CR.Range.first, Pivot);
1727 CaseRange RHSR(Pivot, CR.Range.second);
1728 Constant *C = Pivot->Low;
1729 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1731 // We know that we branch to the LHS if the Value being switched on is
1732 // less than the Pivot value, C. We use this to optimize our binary
1733 // tree a bit, by recognizing that if SV is greater than or equal to the
1734 // LHS's Case Value, and that Case Value is exactly one less than the
1735 // Pivot's Value, then we can branch directly to the LHS's Target,
1736 // rather than creating a leaf node for it.
1737 if ((LHSR.second - LHSR.first) == 1 &&
1738 LHSR.first->High == CR.GE &&
1739 cast<ConstantInt>(C)->getSExtValue() ==
1740 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1741 TrueBB = LHSR.first->BB;
1743 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1744 CurMF->insert(BBI, TrueBB);
1745 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1748 // Similar to the optimization above, if the Value being switched on is
1749 // known to be less than the Constant CR.LT, and the current Case Value
1750 // is CR.LT - 1, then we can branch directly to the target block for
1751 // the current Case Value, rather than emitting a RHS leaf node for it.
1752 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1753 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1754 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1755 FalseBB = RHSR.first->BB;
1757 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1758 CurMF->insert(BBI, FalseBB);
1759 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1762 // Create a CaseBlock record representing a conditional branch to
1763 // the LHS node if the value being switched on SV is less than C.
1764 // Otherwise, branch to LHS.
1765 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1767 if (CR.CaseBB == CurMBB)
1768 visitSwitchCase(CB);
1770 SwitchCases.push_back(CB);
1775 /// handleBitTestsSwitchCase - if current case range has few destination and
1776 /// range span less, than machine word bitwidth, encode case range into series
1777 /// of masks and emit bit tests with these masks.
1778 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1779 CaseRecVector& WorkList,
1781 MachineBasicBlock* Default){
1782 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1784 Case& FrontCase = *CR.Range.first;
1785 Case& BackCase = *(CR.Range.second-1);
1787 // Get the MachineFunction which holds the current MBB. This is used when
1788 // inserting any additional MBBs necessary to represent the switch.
1789 MachineFunction *CurMF = CurMBB->getParent();
1791 unsigned numCmps = 0;
1792 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1794 // Single case counts one, case range - two.
1795 if (I->Low == I->High)
1801 // Count unique destinations
1802 SmallSet<MachineBasicBlock*, 4> Dests;
1803 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1804 Dests.insert(I->BB);
1805 if (Dests.size() > 3)
1806 // Don't bother the code below, if there are too much unique destinations
1809 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1810 << "Total number of comparisons: " << numCmps << "\n";
1812 // Compute span of values.
1813 Constant* minValue = FrontCase.Low;
1814 Constant* maxValue = BackCase.High;
1815 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1816 cast<ConstantInt>(minValue)->getSExtValue();
1817 DOUT << "Compare range: " << range << "\n"
1818 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1819 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1821 if (range>=IntPtrBits ||
1822 (!(Dests.size() == 1 && numCmps >= 3) &&
1823 !(Dests.size() == 2 && numCmps >= 5) &&
1824 !(Dests.size() >= 3 && numCmps >= 6)))
1827 DOUT << "Emitting bit tests\n";
1828 int64_t lowBound = 0;
1830 // Optimize the case where all the case values fit in a
1831 // word without having to subtract minValue. In this case,
1832 // we can optimize away the subtraction.
1833 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1834 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1835 range = cast<ConstantInt>(maxValue)->getSExtValue();
1837 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1840 CaseBitsVector CasesBits;
1841 unsigned i, count = 0;
1843 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1844 MachineBasicBlock* Dest = I->BB;
1845 for (i = 0; i < count; ++i)
1846 if (Dest == CasesBits[i].BB)
1850 assert((count < 3) && "Too much destinations to test!");
1851 CasesBits.push_back(CaseBits(0, Dest, 0));
1855 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1856 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1858 for (uint64_t j = lo; j <= hi; j++) {
1859 CasesBits[i].Mask |= 1ULL << j;
1860 CasesBits[i].Bits++;
1864 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1868 // Figure out which block is immediately after the current one.
1869 MachineFunction::iterator BBI = CR.CaseBB;
1872 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1875 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1876 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1877 << ", BB: " << CasesBits[i].BB << "\n";
1879 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1880 CurMF->insert(BBI, CaseBB);
1881 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1886 BitTestBlock BTB(lowBound, range, SV,
1887 -1U, (CR.CaseBB == CurMBB),
1888 CR.CaseBB, Default, BTC);
1890 if (CR.CaseBB == CurMBB)
1891 visitBitTestHeader(BTB);
1893 BitTestCases.push_back(BTB);
1899 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1900 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1901 const SwitchInst& SI) {
1902 unsigned numCmps = 0;
1904 // Start with "simple" cases
1905 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1906 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1907 Cases.push_back(Case(SI.getSuccessorValue(i),
1908 SI.getSuccessorValue(i),
1911 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1913 // Merge case into clusters
1914 if (Cases.size()>=2)
1915 // Must recompute end() each iteration because it may be
1916 // invalidated by erase if we hold on to it
1917 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1918 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1919 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1920 MachineBasicBlock* nextBB = J->BB;
1921 MachineBasicBlock* currentBB = I->BB;
1923 // If the two neighboring cases go to the same destination, merge them
1924 // into a single case.
1925 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1933 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1934 if (I->Low != I->High)
1935 // A range counts double, since it requires two compares.
1942 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1943 // Figure out which block is immediately after the current one.
1944 MachineBasicBlock *NextBlock = 0;
1945 MachineFunction::iterator BBI = CurMBB;
1947 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1949 // If there is only the default destination, branch to it if it is not the
1950 // next basic block. Otherwise, just fall through.
1951 if (SI.getNumOperands() == 2) {
1952 // Update machine-CFG edges.
1954 // If this is not a fall-through branch, emit the branch.
1955 CurMBB->addSuccessor(Default);
1956 if (Default != NextBlock)
1957 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1958 DAG.getBasicBlock(Default)));
1963 // If there are any non-default case statements, create a vector of Cases
1964 // representing each one, and sort the vector so that we can efficiently
1965 // create a binary search tree from them.
1967 unsigned numCmps = Clusterify(Cases, SI);
1968 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1969 << ". Total compares: " << numCmps << "\n";
1971 // Get the Value to be switched on and default basic blocks, which will be
1972 // inserted into CaseBlock records, representing basic blocks in the binary
1974 Value *SV = SI.getOperand(0);
1976 // Push the initial CaseRec onto the worklist
1977 CaseRecVector WorkList;
1978 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1980 while (!WorkList.empty()) {
1981 // Grab a record representing a case range to process off the worklist
1982 CaseRec CR = WorkList.back();
1983 WorkList.pop_back();
1985 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1988 // If the range has few cases (two or less) emit a series of specific
1990 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1993 // If the switch has more than 5 blocks, and at least 40% dense, and the
1994 // target supports indirect branches, then emit a jump table rather than
1995 // lowering the switch to a binary tree of conditional branches.
1996 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1999 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2000 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2001 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2006 void SelectionDAGLowering::visitSub(User &I) {
2007 // -0.0 - X --> fneg
2008 const Type *Ty = I.getType();
2009 if (isa<VectorType>(Ty)) {
2010 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2011 const VectorType *DestTy = cast<VectorType>(I.getType());
2012 const Type *ElTy = DestTy->getElementType();
2013 if (ElTy->isFloatingPoint()) {
2014 unsigned VL = DestTy->getNumElements();
2015 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2016 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2018 SDValue Op2 = getValue(I.getOperand(1));
2019 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2025 if (Ty->isFloatingPoint()) {
2026 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2027 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2028 SDValue Op2 = getValue(I.getOperand(1));
2029 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2034 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2037 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2038 SDValue Op1 = getValue(I.getOperand(0));
2039 SDValue Op2 = getValue(I.getOperand(1));
2041 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2044 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2045 SDValue Op1 = getValue(I.getOperand(0));
2046 SDValue Op2 = getValue(I.getOperand(1));
2047 if (!isa<VectorType>(I.getType())) {
2048 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2049 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2050 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2051 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2054 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2057 void SelectionDAGLowering::visitICmp(User &I) {
2058 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2059 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2060 predicate = IC->getPredicate();
2061 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2062 predicate = ICmpInst::Predicate(IC->getPredicate());
2063 SDValue Op1 = getValue(I.getOperand(0));
2064 SDValue Op2 = getValue(I.getOperand(1));
2065 ISD::CondCode Opcode;
2066 switch (predicate) {
2067 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2068 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2069 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2070 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2071 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2072 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2073 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2074 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2075 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2076 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2078 assert(!"Invalid ICmp predicate value");
2079 Opcode = ISD::SETEQ;
2082 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2085 void SelectionDAGLowering::visitFCmp(User &I) {
2086 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2087 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2088 predicate = FC->getPredicate();
2089 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2090 predicate = FCmpInst::Predicate(FC->getPredicate());
2091 SDValue Op1 = getValue(I.getOperand(0));
2092 SDValue Op2 = getValue(I.getOperand(1));
2093 ISD::CondCode Condition, FOC, FPC;
2094 switch (predicate) {
2095 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2096 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2097 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2098 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2099 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2100 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2101 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2102 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2103 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2104 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2105 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2106 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2107 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2108 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2109 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2110 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2112 assert(!"Invalid FCmp predicate value");
2113 FOC = FPC = ISD::SETFALSE;
2116 if (FiniteOnlyFPMath())
2120 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2123 void SelectionDAGLowering::visitVICmp(User &I) {
2124 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2125 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2126 predicate = IC->getPredicate();
2127 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2128 predicate = ICmpInst::Predicate(IC->getPredicate());
2129 SDValue Op1 = getValue(I.getOperand(0));
2130 SDValue Op2 = getValue(I.getOperand(1));
2131 ISD::CondCode Opcode;
2132 switch (predicate) {
2133 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2134 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2135 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2136 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2137 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2138 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2139 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2140 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2141 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2142 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2144 assert(!"Invalid ICmp predicate value");
2145 Opcode = ISD::SETEQ;
2148 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2151 void SelectionDAGLowering::visitVFCmp(User &I) {
2152 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2153 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2154 predicate = FC->getPredicate();
2155 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2156 predicate = FCmpInst::Predicate(FC->getPredicate());
2157 SDValue Op1 = getValue(I.getOperand(0));
2158 SDValue Op2 = getValue(I.getOperand(1));
2159 ISD::CondCode Condition, FOC, FPC;
2160 switch (predicate) {
2161 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2162 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2163 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2164 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2165 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2166 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2167 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2168 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2169 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2170 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2171 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2172 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2173 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2174 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2175 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2176 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2178 assert(!"Invalid VFCmp predicate value");
2179 FOC = FPC = ISD::SETFALSE;
2182 if (FiniteOnlyFPMath())
2187 MVT DestVT = TLI.getValueType(I.getType());
2189 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2192 void SelectionDAGLowering::visitSelect(User &I) {
2193 SDValue Cond = getValue(I.getOperand(0));
2194 SDValue TrueVal = getValue(I.getOperand(1));
2195 SDValue FalseVal = getValue(I.getOperand(2));
2196 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2197 TrueVal, FalseVal));
2201 void SelectionDAGLowering::visitTrunc(User &I) {
2202 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2203 SDValue N = getValue(I.getOperand(0));
2204 MVT DestVT = TLI.getValueType(I.getType());
2205 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2208 void SelectionDAGLowering::visitZExt(User &I) {
2209 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2210 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2211 SDValue N = getValue(I.getOperand(0));
2212 MVT DestVT = TLI.getValueType(I.getType());
2213 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2216 void SelectionDAGLowering::visitSExt(User &I) {
2217 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2218 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2219 SDValue N = getValue(I.getOperand(0));
2220 MVT DestVT = TLI.getValueType(I.getType());
2221 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2224 void SelectionDAGLowering::visitFPTrunc(User &I) {
2225 // FPTrunc is never a no-op cast, no need to check
2226 SDValue N = getValue(I.getOperand(0));
2227 MVT DestVT = TLI.getValueType(I.getType());
2228 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2231 void SelectionDAGLowering::visitFPExt(User &I){
2232 // FPTrunc is never a no-op cast, no need to check
2233 SDValue N = getValue(I.getOperand(0));
2234 MVT DestVT = TLI.getValueType(I.getType());
2235 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2238 void SelectionDAGLowering::visitFPToUI(User &I) {
2239 // FPToUI is never a no-op cast, no need to check
2240 SDValue N = getValue(I.getOperand(0));
2241 MVT DestVT = TLI.getValueType(I.getType());
2242 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2245 void SelectionDAGLowering::visitFPToSI(User &I) {
2246 // FPToSI is never a no-op cast, no need to check
2247 SDValue N = getValue(I.getOperand(0));
2248 MVT DestVT = TLI.getValueType(I.getType());
2249 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2252 void SelectionDAGLowering::visitUIToFP(User &I) {
2253 // UIToFP is never a no-op cast, no need to check
2254 SDValue N = getValue(I.getOperand(0));
2255 MVT DestVT = TLI.getValueType(I.getType());
2256 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2259 void SelectionDAGLowering::visitSIToFP(User &I){
2260 // UIToFP is never a no-op cast, no need to check
2261 SDValue N = getValue(I.getOperand(0));
2262 MVT DestVT = TLI.getValueType(I.getType());
2263 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2266 void SelectionDAGLowering::visitPtrToInt(User &I) {
2267 // What to do depends on the size of the integer and the size of the pointer.
2268 // We can either truncate, zero extend, or no-op, accordingly.
2269 SDValue N = getValue(I.getOperand(0));
2270 MVT SrcVT = N.getValueType();
2271 MVT DestVT = TLI.getValueType(I.getType());
2273 if (DestVT.bitsLT(SrcVT))
2274 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2276 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2277 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2278 setValue(&I, Result);
2281 void SelectionDAGLowering::visitIntToPtr(User &I) {
2282 // What to do depends on the size of the integer and the size of the pointer.
2283 // We can either truncate, zero extend, or no-op, accordingly.
2284 SDValue N = getValue(I.getOperand(0));
2285 MVT SrcVT = N.getValueType();
2286 MVT DestVT = TLI.getValueType(I.getType());
2287 if (DestVT.bitsLT(SrcVT))
2288 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2290 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2291 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2294 void SelectionDAGLowering::visitBitCast(User &I) {
2295 SDValue N = getValue(I.getOperand(0));
2296 MVT DestVT = TLI.getValueType(I.getType());
2298 // BitCast assures us that source and destination are the same size so this
2299 // is either a BIT_CONVERT or a no-op.
2300 if (DestVT != N.getValueType())
2301 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2303 setValue(&I, N); // noop cast.
2306 void SelectionDAGLowering::visitInsertElement(User &I) {
2307 SDValue InVec = getValue(I.getOperand(0));
2308 SDValue InVal = getValue(I.getOperand(1));
2309 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2310 getValue(I.getOperand(2)));
2312 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2313 TLI.getValueType(I.getType()),
2314 InVec, InVal, InIdx));
2317 void SelectionDAGLowering::visitExtractElement(User &I) {
2318 SDValue InVec = getValue(I.getOperand(0));
2319 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2320 getValue(I.getOperand(1)));
2321 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2322 TLI.getValueType(I.getType()), InVec, InIdx));
2325 void SelectionDAGLowering::visitShuffleVector(User &I) {
2326 SDValue V1 = getValue(I.getOperand(0));
2327 SDValue V2 = getValue(I.getOperand(1));
2328 SDValue Mask = getValue(I.getOperand(2));
2330 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2331 TLI.getValueType(I.getType()),
2335 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2336 const Value *Op0 = I.getOperand(0);
2337 const Value *Op1 = I.getOperand(1);
2338 const Type *AggTy = I.getType();
2339 const Type *ValTy = Op1->getType();
2340 bool IntoUndef = isa<UndefValue>(Op0);
2341 bool FromUndef = isa<UndefValue>(Op1);
2343 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2344 I.idx_begin(), I.idx_end());
2346 SmallVector<MVT, 4> AggValueVTs;
2347 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2348 SmallVector<MVT, 4> ValValueVTs;
2349 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2351 unsigned NumAggValues = AggValueVTs.size();
2352 unsigned NumValValues = ValValueVTs.size();
2353 SmallVector<SDValue, 4> Values(NumAggValues);
2355 SDValue Agg = getValue(Op0);
2356 SDValue Val = getValue(Op1);
2358 // Copy the beginning value(s) from the original aggregate.
2359 for (; i != LinearIndex; ++i)
2360 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2361 SDValue(Agg.getNode(), Agg.getResNo() + i);
2362 // Copy values from the inserted value(s).
2363 for (; i != LinearIndex + NumValValues; ++i)
2364 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2365 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2366 // Copy remaining value(s) from the original aggregate.
2367 for (; i != NumAggValues; ++i)
2368 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2369 SDValue(Agg.getNode(), Agg.getResNo() + i);
2371 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2372 &Values[0], NumAggValues));
2375 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2376 const Value *Op0 = I.getOperand(0);
2377 const Type *AggTy = Op0->getType();
2378 const Type *ValTy = I.getType();
2379 bool OutOfUndef = isa<UndefValue>(Op0);
2381 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2382 I.idx_begin(), I.idx_end());
2384 SmallVector<MVT, 4> ValValueVTs;
2385 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2387 unsigned NumValValues = ValValueVTs.size();
2388 SmallVector<SDValue, 4> Values(NumValValues);
2390 SDValue Agg = getValue(Op0);
2391 // Copy out the selected value(s).
2392 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2393 Values[i - LinearIndex] =
2394 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2395 SDValue(Agg.getNode(), Agg.getResNo() + i);
2397 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2398 &Values[0], NumValValues));
2402 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2403 SDValue N = getValue(I.getOperand(0));
2404 const Type *Ty = I.getOperand(0)->getType();
2406 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2409 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2410 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2413 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2414 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2415 DAG.getIntPtrConstant(Offset));
2417 Ty = StTy->getElementType(Field);
2419 Ty = cast<SequentialType>(Ty)->getElementType();
2421 // If this is a constant subscript, handle it quickly.
2422 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2423 if (CI->getZExtValue() == 0) continue;
2425 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2426 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2427 DAG.getIntPtrConstant(Offs));
2431 // N = N + Idx * ElementSize;
2432 uint64_t ElementSize = TD->getABITypeSize(Ty);
2433 SDValue IdxN = getValue(Idx);
2435 // If the index is smaller or larger than intptr_t, truncate or extend
2437 if (IdxN.getValueType().bitsLT(N.getValueType()))
2438 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2439 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2440 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2442 // If this is a multiply by a power of two, turn it into a shl
2443 // immediately. This is a very common case.
2444 if (ElementSize != 1) {
2445 if (isPowerOf2_64(ElementSize)) {
2446 unsigned Amt = Log2_64(ElementSize);
2447 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2448 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2450 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2451 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2455 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2461 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2462 // If this is a fixed sized alloca in the entry block of the function,
2463 // allocate it statically on the stack.
2464 if (FuncInfo.StaticAllocaMap.count(&I))
2465 return; // getValue will auto-populate this.
2467 const Type *Ty = I.getAllocatedType();
2468 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2470 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2473 SDValue AllocSize = getValue(I.getArraySize());
2474 MVT IntPtr = TLI.getPointerTy();
2475 if (IntPtr.bitsLT(AllocSize.getValueType()))
2476 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2477 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2478 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2480 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2481 DAG.getIntPtrConstant(TySize));
2483 // Handle alignment. If the requested alignment is less than or equal to
2484 // the stack alignment, ignore it. If the size is greater than or equal to
2485 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2486 unsigned StackAlign =
2487 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2488 if (Align <= StackAlign)
2491 // Round the size of the allocation up to the stack alignment size
2492 // by add SA-1 to the size.
2493 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2494 DAG.getIntPtrConstant(StackAlign-1));
2495 // Mask out the low bits for alignment purposes.
2496 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2497 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2499 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2500 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2502 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2504 DAG.setRoot(DSA.getValue(1));
2506 // Inform the Frame Information that we have just allocated a variable-sized
2508 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2511 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2512 const Value *SV = I.getOperand(0);
2513 SDValue Ptr = getValue(SV);
2515 const Type *Ty = I.getType();
2516 bool isVolatile = I.isVolatile();
2517 unsigned Alignment = I.getAlignment();
2519 SmallVector<MVT, 4> ValueVTs;
2520 SmallVector<uint64_t, 4> Offsets;
2521 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2522 unsigned NumValues = ValueVTs.size();
2527 bool ConstantMemory = false;
2529 // Serialize volatile loads with other side effects.
2531 else if (AA->pointsToConstantMemory(SV)) {
2532 // Do not serialize (non-volatile) loads of constant memory with anything.
2533 Root = DAG.getEntryNode();
2534 ConstantMemory = true;
2536 // Do not serialize non-volatile loads against each other.
2537 Root = DAG.getRoot();
2540 SmallVector<SDValue, 4> Values(NumValues);
2541 SmallVector<SDValue, 4> Chains(NumValues);
2542 MVT PtrVT = Ptr.getValueType();
2543 for (unsigned i = 0; i != NumValues; ++i) {
2544 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2545 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2546 DAG.getConstant(Offsets[i], PtrVT)),
2548 isVolatile, Alignment);
2550 Chains[i] = L.getValue(1);
2553 if (!ConstantMemory) {
2554 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2555 &Chains[0], NumValues);
2559 PendingLoads.push_back(Chain);
2562 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2563 &Values[0], NumValues));
2567 void SelectionDAGLowering::visitStore(StoreInst &I) {
2568 Value *SrcV = I.getOperand(0);
2569 Value *PtrV = I.getOperand(1);
2571 SmallVector<MVT, 4> ValueVTs;
2572 SmallVector<uint64_t, 4> Offsets;
2573 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2574 unsigned NumValues = ValueVTs.size();
2578 // Get the lowered operands. Note that we do this after
2579 // checking if NumResults is zero, because with zero results
2580 // the operands won't have values in the map.
2581 SDValue Src = getValue(SrcV);
2582 SDValue Ptr = getValue(PtrV);
2584 SDValue Root = getRoot();
2585 SmallVector<SDValue, 4> Chains(NumValues);
2586 MVT PtrVT = Ptr.getValueType();
2587 bool isVolatile = I.isVolatile();
2588 unsigned Alignment = I.getAlignment();
2589 for (unsigned i = 0; i != NumValues; ++i)
2590 Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(), Src.getResNo() + i),
2591 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2592 DAG.getConstant(Offsets[i], PtrVT)),
2594 isVolatile, Alignment);
2596 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2599 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2601 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2602 unsigned Intrinsic) {
2603 bool HasChain = !I.doesNotAccessMemory();
2604 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2606 // Build the operand list.
2607 SmallVector<SDValue, 8> Ops;
2608 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2610 // We don't need to serialize loads against other loads.
2611 Ops.push_back(DAG.getRoot());
2613 Ops.push_back(getRoot());
2617 // Add the intrinsic ID as an integer operand.
2618 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2620 // Add all operands of the call to the operand list.
2621 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2622 SDValue Op = getValue(I.getOperand(i));
2623 assert(TLI.isTypeLegal(Op.getValueType()) &&
2624 "Intrinsic uses a non-legal type?");
2628 std::vector<MVT> VTs;
2629 if (I.getType() != Type::VoidTy) {
2630 MVT VT = TLI.getValueType(I.getType());
2631 if (VT.isVector()) {
2632 const VectorType *DestTy = cast<VectorType>(I.getType());
2633 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2635 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2636 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2639 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2643 VTs.push_back(MVT::Other);
2645 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2650 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2651 &Ops[0], Ops.size());
2652 else if (I.getType() != Type::VoidTy)
2653 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2654 &Ops[0], Ops.size());
2656 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2657 &Ops[0], Ops.size());
2660 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2662 PendingLoads.push_back(Chain);
2666 if (I.getType() != Type::VoidTy) {
2667 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2668 MVT VT = TLI.getValueType(PTy);
2669 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2671 setValue(&I, Result);
2675 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2676 static GlobalVariable *ExtractTypeInfo(Value *V) {
2677 V = V->stripPointerCasts();
2678 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2679 assert ((GV || isa<ConstantPointerNull>(V)) &&
2680 "TypeInfo must be a global variable or NULL");
2686 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2687 /// call, and add them to the specified machine basic block.
2688 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2689 MachineBasicBlock *MBB) {
2690 // Inform the MachineModuleInfo of the personality for this landing pad.
2691 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2692 assert(CE->getOpcode() == Instruction::BitCast &&
2693 isa<Function>(CE->getOperand(0)) &&
2694 "Personality should be a function");
2695 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2697 // Gather all the type infos for this landing pad and pass them along to
2698 // MachineModuleInfo.
2699 std::vector<GlobalVariable *> TyInfo;
2700 unsigned N = I.getNumOperands();
2702 for (unsigned i = N - 1; i > 2; --i) {
2703 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2704 unsigned FilterLength = CI->getZExtValue();
2705 unsigned FirstCatch = i + FilterLength + !FilterLength;
2706 assert (FirstCatch <= N && "Invalid filter length");
2708 if (FirstCatch < N) {
2709 TyInfo.reserve(N - FirstCatch);
2710 for (unsigned j = FirstCatch; j < N; ++j)
2711 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2712 MMI->addCatchTypeInfo(MBB, TyInfo);
2716 if (!FilterLength) {
2718 MMI->addCleanup(MBB);
2721 TyInfo.reserve(FilterLength - 1);
2722 for (unsigned j = i + 1; j < FirstCatch; ++j)
2723 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2724 MMI->addFilterTypeInfo(MBB, TyInfo);
2733 TyInfo.reserve(N - 3);
2734 for (unsigned j = 3; j < N; ++j)
2735 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2736 MMI->addCatchTypeInfo(MBB, TyInfo);
2742 /// GetSignificand - Get the significand and build it into a floating-point
2743 /// number with exponent of 1:
2745 /// Op = (Op & 0x007fffff) | 0x3f800000;
2747 /// where Op is the hexidecimal representation of floating point value.
2749 GetSignificand(SelectionDAG &DAG, SDValue Op) {
2750 SDValue t1 = DAG.getNode(ISD::AND, MVT::i32, Op,
2751 DAG.getConstant(0x007fffff, MVT::i32));
2752 SDValue t2 = DAG.getNode(ISD::OR, MVT::i32, t1,
2753 DAG.getConstant(0x3f800000, MVT::i32));
2754 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t2);
2757 /// GetExponent - Get the exponent:
2759 /// (float)((Op1 >> 23) - 127);
2761 /// where Op is the hexidecimal representation of floating point value.
2763 GetExponent(SelectionDAG &DAG, SDValue Op) {
2764 SDValue t1 = DAG.getNode(ISD::SRL, MVT::i32, Op,
2765 DAG.getConstant(23, MVT::i32));
2766 SDValue t2 = DAG.getNode(ISD::SUB, MVT::i32, t1,
2767 DAG.getConstant(127, MVT::i32));
2768 return DAG.getNode(ISD::UINT_TO_FP, MVT::f32, t2);
2771 /// getF32Constant - Get 32-bit floating point constant.
2773 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2774 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2777 /// Inlined utility function to implement binary input atomic intrinsics for
2778 /// visitIntrinsicCall: I is a call instruction
2779 /// Op is the associated NodeType for I
2781 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2782 SDValue Root = getRoot();
2783 SDValue L = DAG.getAtomic(Op, Root,
2784 getValue(I.getOperand(1)),
2785 getValue(I.getOperand(2)),
2788 DAG.setRoot(L.getValue(1));
2792 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2793 /// limited-precision mode.
2795 SelectionDAGLowering::visitExp(CallInst &I) {
2798 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2799 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2800 SDValue Op = getValue(I.getOperand(1));
2802 // Put the exponent in the right bit position for later addition to the
2805 // #define LOG2OFe 1.4426950f
2806 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2807 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
2808 getF32Constant(DAG, 0x3fb8aa3b));
2809 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
2811 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2812 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
2813 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
2815 // IntegerPartOfX <<= 23;
2816 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
2817 DAG.getConstant(23, MVT::i32));
2819 if (LimitFloatPrecision <= 6) {
2820 // For floating-point precision of 6:
2822 // TwoToFractionalPartOfX =
2824 // (0.735607626f + 0.252464424f * x) * x;
2826 // error 0.0144103317, which is 6 bits
2827 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2828 getF32Constant(DAG, 0x3e814304));
2829 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2830 getF32Constant(DAG, 0x3f3c50c8));
2831 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2832 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2833 getF32Constant(DAG, 0x3f7f5e7e));
2834 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
2836 // Add the exponent into the result in integer domain.
2837 SDValue t6 = DAG.getNode(ISD::ADD, MVT::i32,
2838 TwoToFracPartOfX, IntegerPartOfX);
2840 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t6);
2841 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2842 // For floating-point precision of 12:
2844 // TwoToFractionalPartOfX =
2847 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2849 // 0.000107046256 error, which is 13 to 14 bits
2850 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2851 getF32Constant(DAG, 0x3da235e3));
2852 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2853 getF32Constant(DAG, 0x3e65b8f3));
2854 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2855 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2856 getF32Constant(DAG, 0x3f324b07));
2857 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2858 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
2859 getF32Constant(DAG, 0x3f7ff8fd));
2860 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
2862 // Add the exponent into the result in integer domain.
2863 SDValue t8 = DAG.getNode(ISD::ADD, MVT::i32,
2864 TwoToFracPartOfX, IntegerPartOfX);
2866 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t8);
2867 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2868 // For floating-point precision of 18:
2870 // TwoToFractionalPartOfX =
2874 // (0.554906021e-1f +
2875 // (0.961591928e-2f +
2876 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
2878 // error 2.47208000*10^(-7), which is better than 18 bits
2879 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2880 getF32Constant(DAG, 0x3924b03e));
2881 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2882 getF32Constant(DAG, 0x3ab24b87));
2883 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2884 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2885 getF32Constant(DAG, 0x3c1d8c17));
2886 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2887 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
2888 getF32Constant(DAG, 0x3d634a1d));
2889 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
2890 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
2891 getF32Constant(DAG, 0x3e75fe14));
2892 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
2893 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
2894 getF32Constant(DAG, 0x3f317234));
2895 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
2896 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
2897 getF32Constant(DAG, 0x3f800000));
2898 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
2900 // Add the exponent into the result in integer domain.
2901 SDValue t14 = DAG.getNode(ISD::ADD, MVT::i32,
2902 TwoToFracPartOfX, IntegerPartOfX);
2904 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t14);
2907 // No special expansion.
2908 result = DAG.getNode(ISD::FEXP,
2909 getValue(I.getOperand(1)).getValueType(),
2910 getValue(I.getOperand(1)));
2913 setValue(&I, result);
2916 /// visitLog - Lower a log intrinsic. Handles the special sequences for
2917 /// limited-precision mode.
2919 SelectionDAGLowering::visitLog(CallInst &I) {
2922 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2923 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2924 SDValue Op = getValue(I.getOperand(1));
2925 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
2927 // Scale the exponent by log(2) [0.69314718f].
2928 SDValue Exp = GetExponent(DAG, Op1);
2929 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
2930 getF32Constant(DAG, 0x3f317218));
2932 // Get the significand and build it into a floating-point number with
2934 SDValue X = GetSignificand(DAG, Op1);
2936 if (LimitFloatPrecision <= 6) {
2937 // For floating-point precision of 6:
2941 // (1.4034025f - 0.23903021f * x) * x;
2943 // error 0.0034276066, which is better than 8 bits
2944 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2945 getF32Constant(DAG, 0xbe74c456));
2946 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2947 getF32Constant(DAG, 0x3fb3a2b1));
2948 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2949 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2950 getF32Constant(DAG, 0x3f949a29));
2952 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2953 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2954 // For floating-point precision of 12:
2960 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
2962 // error 0.000061011436, which is 14 bits
2963 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2964 getF32Constant(DAG, 0xbd67b6d6));
2965 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2966 getF32Constant(DAG, 0x3ee4f4b8));
2967 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2968 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2969 getF32Constant(DAG, 0x3fbc278b));
2970 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2971 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2972 getF32Constant(DAG, 0x40348e95));
2973 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2974 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
2975 getF32Constant(DAG, 0x3fdef31a));
2977 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2978 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2979 // For floating-point precision of 18:
2987 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
2989 // error 0.0000023660568, which is better than 18 bits
2990 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2991 getF32Constant(DAG, 0xbc91e5ac));
2992 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2993 getF32Constant(DAG, 0x3e4350aa));
2994 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2995 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2996 getF32Constant(DAG, 0x3f60d3e3));
2997 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2998 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2999 getF32Constant(DAG, 0x4011cdf0));
3000 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3001 SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3002 getF32Constant(DAG, 0x406cfd1c));
3003 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3004 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3005 getF32Constant(DAG, 0x408797cb));
3006 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3007 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
3008 getF32Constant(DAG, 0x4006dcab));
3010 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
3013 // No special expansion.
3014 result = DAG.getNode(ISD::FLOG,
3015 getValue(I.getOperand(1)).getValueType(),
3016 getValue(I.getOperand(1)));
3019 setValue(&I, result);
3022 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3023 /// limited-precision mode.
3025 SelectionDAGLowering::visitLog2(CallInst &I) {
3028 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3029 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3030 SDValue Op = getValue(I.getOperand(1));
3031 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
3033 // Get the exponent.
3034 SDValue LogOfExponent = GetExponent(DAG, Op1);
3036 // Get the significand and build it into a floating-point number with
3038 SDValue X = GetSignificand(DAG, Op1);
3040 // Different possible minimax approximations of significand in
3041 // floating-point for various degrees of accuracy over [1,2].
3042 if (LimitFloatPrecision <= 6) {
3043 // For floating-point precision of 6:
3045 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3047 // error 0.0049451742, which is more than 7 bits
3048 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3049 getF32Constant(DAG, 0xbeb08fe0));
3050 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3051 getF32Constant(DAG, 0x40019463));
3052 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3053 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3054 getF32Constant(DAG, 0x3fd6633d));
3056 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3057 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3058 // For floating-point precision of 12:
3064 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3066 // error 0.0000876136000, which is better than 13 bits
3067 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3068 getF32Constant(DAG, 0xbda7262e));
3069 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3070 getF32Constant(DAG, 0x3f25280b));
3071 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3072 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3073 getF32Constant(DAG, 0x4007b923));
3074 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3075 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3076 getF32Constant(DAG, 0x40823e2f));
3077 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3078 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3079 getF32Constant(DAG, 0x4020d29c));
3081 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3082 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3083 // For floating-point precision of 18:
3092 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3094 // error 0.0000018516, which is better than 18 bits
3095 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3096 getF32Constant(DAG, 0xbcd2769e));
3097 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3098 getF32Constant(DAG, 0x3e8ce0b9));
3099 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3100 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3101 getF32Constant(DAG, 0x3fa22ae7));
3102 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3103 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3104 getF32Constant(DAG, 0x40525723));
3105 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3106 SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3107 getF32Constant(DAG, 0x40aaf200));
3108 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3109 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3110 getF32Constant(DAG, 0x40c39dad));
3111 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3112 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
3113 getF32Constant(DAG, 0x4042902c));
3115 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3118 // No special expansion.
3119 result = DAG.getNode(ISD::FLOG2,
3120 getValue(I.getOperand(1)).getValueType(),
3121 getValue(I.getOperand(1)));
3124 setValue(&I, result);
3127 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3128 /// limited-precision mode.
3130 SelectionDAGLowering::visitLog10(CallInst &I) {
3132 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3133 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3134 SDValue Op = getValue(I.getOperand(1));
3135 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
3137 // Scale the exponent by log10(2) [0.30102999f].
3138 SDValue Exp = GetExponent(DAG, Op1);
3139 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
3140 getF32Constant(DAG, 0x3e9a209a));
3142 // Get the significand and build it into a floating-point number with
3144 SDValue X = GetSignificand(DAG, Op1);
3146 if (LimitFloatPrecision <= 6) {
3147 // For floating-point precision of 6:
3149 // Log10ofMantissa =
3151 // (0.60948995f - 0.10380950f * x) * x;
3153 // error 0.0014886165, which is 6 bits
3154 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3155 getF32Constant(DAG, 0xbdd49a13));
3156 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3157 getF32Constant(DAG, 0x3f1c0789));
3158 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3159 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3160 getF32Constant(DAG, 0x3f011300));
3162 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3163 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3164 // For floating-point precision of 12:
3166 // Log10ofMantissa =
3169 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3171 // error 0.00019228036, which is better than 12 bits
3172 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3173 getF32Constant(DAG, 0x3d431f31));
3174 SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
3175 getF32Constant(DAG, 0x3ea21fb2));
3176 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3177 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3178 getF32Constant(DAG, 0x3f6ae232));
3179 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3180 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t4,
3181 getF32Constant(DAG, 0x3f25f7c3));
3183 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3184 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3185 // For floating-point precision of 18:
3187 // Log10ofMantissa =
3192 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3194 // error 0.0000037995730, which is better than 18 bits
3195 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3196 getF32Constant(DAG, 0x3c5d51ce));
3197 SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
3198 getF32Constant(DAG, 0x3e00685a));
3199 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3200 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3201 getF32Constant(DAG, 0x3efb6798));
3202 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3203 SDValue t5 = DAG.getNode(ISD::FSUB, MVT::f32, t4,
3204 getF32Constant(DAG, 0x3f88d192));
3205 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3206 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3207 getF32Constant(DAG, 0x3fc4316c));
3208 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3209 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t8,
3210 getF32Constant(DAG, 0x3f57ce70));
3212 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3215 // No special expansion.
3216 result = DAG.getNode(ISD::FLOG10,
3217 getValue(I.getOperand(1)).getValueType(),
3218 getValue(I.getOperand(1)));
3221 setValue(&I, result);
3224 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3225 /// limited-precision mode.
3227 SelectionDAGLowering::visitExp2(CallInst &I) {
3230 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3231 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3232 SDValue Op = getValue(I.getOperand(1));
3234 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Op);
3236 // FractionalPartOfX = x - (float)IntegerPartOfX;
3237 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
3238 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, Op, t1);
3240 // IntegerPartOfX <<= 23;
3241 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
3242 DAG.getConstant(23, MVT::i32));
3244 if (LimitFloatPrecision <= 6) {
3245 // For floating-point precision of 6:
3247 // TwoToFractionalPartOfX =
3249 // (0.735607626f + 0.252464424f * x) * x;
3251 // error 0.0144103317, which is 6 bits
3252 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3253 getF32Constant(DAG, 0x3e814304));
3254 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3255 getF32Constant(DAG, 0x3f3c50c8));
3256 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3257 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3258 getF32Constant(DAG, 0x3f7f5e7e));
3259 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
3260 SDValue TwoToFractionalPartOfX =
3261 DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
3263 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3264 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3265 // For floating-point precision of 12:
3267 // TwoToFractionalPartOfX =
3270 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3272 // error 0.000107046256, which is 13 to 14 bits
3273 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3274 getF32Constant(DAG, 0x3da235e3));
3275 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3276 getF32Constant(DAG, 0x3e65b8f3));
3277 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3278 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3279 getF32Constant(DAG, 0x3f324b07));
3280 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3281 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3282 getF32Constant(DAG, 0x3f7ff8fd));
3283 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
3284 SDValue TwoToFractionalPartOfX =
3285 DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
3287 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3288 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3289 // For floating-point precision of 18:
3291 // TwoToFractionalPartOfX =
3295 // (0.554906021e-1f +
3296 // (0.961591928e-2f +
3297 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3298 // error 2.47208000*10^(-7), which is better than 18 bits
3299 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3300 getF32Constant(DAG, 0x3924b03e));
3301 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3302 getF32Constant(DAG, 0x3ab24b87));
3303 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3304 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3305 getF32Constant(DAG, 0x3c1d8c17));
3306 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3307 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3308 getF32Constant(DAG, 0x3d634a1d));
3309 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3310 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3311 getF32Constant(DAG, 0x3e75fe14));
3312 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3313 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
3314 getF32Constant(DAG, 0x3f317234));
3315 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
3316 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
3317 getF32Constant(DAG, 0x3f800000));
3318 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
3319 SDValue TwoToFractionalPartOfX =
3320 DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
3322 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3325 // No special expansion.
3326 result = DAG.getNode(ISD::FEXP2,
3327 getValue(I.getOperand(1)).getValueType(),
3328 getValue(I.getOperand(1)));
3331 setValue(&I, result);
3334 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3335 /// limited-precision mode with x == 10.0f.
3337 SelectionDAGLowering::visitPow(CallInst &I) {
3339 Value *Val = I.getOperand(1);
3340 bool IsExp10 = false;
3342 if (getValue(Val).getValueType() == MVT::f32 &&
3343 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3344 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3345 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3346 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3348 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3353 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3354 SDValue Op = getValue(I.getOperand(2));
3356 // Put the exponent in the right bit position for later addition to the
3359 // #define LOG2OF10 3.3219281f
3360 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3361 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
3362 getF32Constant(DAG, 0x40549a78));
3363 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
3365 // FractionalPartOfX = x - (float)IntegerPartOfX;
3366 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
3367 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
3369 // IntegerPartOfX <<= 23;
3370 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
3371 DAG.getConstant(23, MVT::i32));
3373 if (LimitFloatPrecision <= 6) {
3374 // For floating-point precision of 6:
3376 // twoToFractionalPartOfX =
3378 // (0.735607626f + 0.252464424f * x) * x;
3380 // error 0.0144103317, which is 6 bits
3381 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3382 getF32Constant(DAG, 0x3e814304));
3383 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3384 getF32Constant(DAG, 0x3f3c50c8));
3385 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3386 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3387 getF32Constant(DAG, 0x3f7f5e7e));
3388 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
3389 SDValue TwoToFractionalPartOfX =
3390 DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
3392 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3393 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3394 // For floating-point precision of 12:
3396 // TwoToFractionalPartOfX =
3399 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3401 // error 0.000107046256, which is 13 to 14 bits
3402 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3403 getF32Constant(DAG, 0x3da235e3));
3404 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3405 getF32Constant(DAG, 0x3e65b8f3));
3406 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3407 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3408 getF32Constant(DAG, 0x3f324b07));
3409 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3410 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3411 getF32Constant(DAG, 0x3f7ff8fd));
3412 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
3413 SDValue TwoToFractionalPartOfX =
3414 DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
3416 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3417 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3418 // For floating-point precision of 18:
3420 // TwoToFractionalPartOfX =
3424 // (0.554906021e-1f +
3425 // (0.961591928e-2f +
3426 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3427 // error 2.47208000*10^(-7), which is better than 18 bits
3428 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3429 getF32Constant(DAG, 0x3924b03e));
3430 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3431 getF32Constant(DAG, 0x3ab24b87));
3432 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3433 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3434 getF32Constant(DAG, 0x3c1d8c17));
3435 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3436 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3437 getF32Constant(DAG, 0x3d634a1d));
3438 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3439 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3440 getF32Constant(DAG, 0x3e75fe14));
3441 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3442 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
3443 getF32Constant(DAG, 0x3f317234));
3444 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
3445 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
3446 getF32Constant(DAG, 0x3f800000));
3447 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
3448 SDValue TwoToFractionalPartOfX =
3449 DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
3451 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3454 // No special expansion.
3455 result = DAG.getNode(ISD::FPOW,
3456 getValue(I.getOperand(1)).getValueType(),
3457 getValue(I.getOperand(1)),
3458 getValue(I.getOperand(2)));
3461 setValue(&I, result);
3464 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3465 /// we want to emit this as a call to a named external function, return the name
3466 /// otherwise lower it and return null.
3468 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3469 switch (Intrinsic) {
3471 // By default, turn this into a target intrinsic node.
3472 visitTargetIntrinsic(I, Intrinsic);
3474 case Intrinsic::vastart: visitVAStart(I); return 0;
3475 case Intrinsic::vaend: visitVAEnd(I); return 0;
3476 case Intrinsic::vacopy: visitVACopy(I); return 0;
3477 case Intrinsic::returnaddress:
3478 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3479 getValue(I.getOperand(1))));
3481 case Intrinsic::frameaddress:
3482 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3483 getValue(I.getOperand(1))));
3485 case Intrinsic::setjmp:
3486 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3488 case Intrinsic::longjmp:
3489 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3491 case Intrinsic::memcpy_i32:
3492 case Intrinsic::memcpy_i64: {
3493 SDValue Op1 = getValue(I.getOperand(1));
3494 SDValue Op2 = getValue(I.getOperand(2));
3495 SDValue Op3 = getValue(I.getOperand(3));
3496 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3497 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3498 I.getOperand(1), 0, I.getOperand(2), 0));
3501 case Intrinsic::memset_i32:
3502 case Intrinsic::memset_i64: {
3503 SDValue Op1 = getValue(I.getOperand(1));
3504 SDValue Op2 = getValue(I.getOperand(2));
3505 SDValue Op3 = getValue(I.getOperand(3));
3506 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3507 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3508 I.getOperand(1), 0));
3511 case Intrinsic::memmove_i32:
3512 case Intrinsic::memmove_i64: {
3513 SDValue Op1 = getValue(I.getOperand(1));
3514 SDValue Op2 = getValue(I.getOperand(2));
3515 SDValue Op3 = getValue(I.getOperand(3));
3516 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3518 // If the source and destination are known to not be aliases, we can
3519 // lower memmove as memcpy.
3520 uint64_t Size = -1ULL;
3521 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3522 Size = C->getZExtValue();
3523 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3524 AliasAnalysis::NoAlias) {
3525 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3526 I.getOperand(1), 0, I.getOperand(2), 0));
3530 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3531 I.getOperand(1), 0, I.getOperand(2), 0));
3534 case Intrinsic::dbg_stoppoint: {
3535 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3536 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3537 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3538 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3539 assert(DD && "Not a debug information descriptor");
3540 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3543 cast<CompileUnitDesc>(DD)));
3548 case Intrinsic::dbg_region_start: {
3549 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3550 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3551 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3552 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3553 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3558 case Intrinsic::dbg_region_end: {
3559 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3560 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3561 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3562 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3563 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3568 case Intrinsic::dbg_func_start: {
3569 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3571 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3572 Value *SP = FSI.getSubprogram();
3573 if (SP && MMI->Verify(SP)) {
3574 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3575 // what (most?) gdb expects.
3576 DebugInfoDesc *DD = MMI->getDescFor(SP);
3577 assert(DD && "Not a debug information descriptor");
3578 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3579 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3580 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3581 // Record the source line but does create a label. It will be emitted
3582 // at asm emission time.
3583 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3588 case Intrinsic::dbg_declare: {
3589 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3590 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3591 Value *Variable = DI.getVariable();
3592 if (MMI && Variable && MMI->Verify(Variable))
3593 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3594 getValue(DI.getAddress()), getValue(Variable)));
3598 case Intrinsic::eh_exception: {
3599 if (!CurMBB->isLandingPad()) {
3600 // FIXME: Mark exception register as live in. Hack for PR1508.
3601 unsigned Reg = TLI.getExceptionAddressRegister();
3602 if (Reg) CurMBB->addLiveIn(Reg);
3604 // Insert the EXCEPTIONADDR instruction.
3605 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3607 Ops[0] = DAG.getRoot();
3608 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3610 DAG.setRoot(Op.getValue(1));
3614 case Intrinsic::eh_selector_i32:
3615 case Intrinsic::eh_selector_i64: {
3616 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3617 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3618 MVT::i32 : MVT::i64);
3621 if (CurMBB->isLandingPad())
3622 AddCatchInfo(I, MMI, CurMBB);
3625 FuncInfo.CatchInfoLost.insert(&I);
3627 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3628 unsigned Reg = TLI.getExceptionSelectorRegister();
3629 if (Reg) CurMBB->addLiveIn(Reg);
3632 // Insert the EHSELECTION instruction.
3633 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3635 Ops[0] = getValue(I.getOperand(1));
3637 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3639 DAG.setRoot(Op.getValue(1));
3641 setValue(&I, DAG.getConstant(0, VT));
3647 case Intrinsic::eh_typeid_for_i32:
3648 case Intrinsic::eh_typeid_for_i64: {
3649 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3650 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3651 MVT::i32 : MVT::i64);
3654 // Find the type id for the given typeinfo.
3655 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3657 unsigned TypeID = MMI->getTypeIDFor(GV);
3658 setValue(&I, DAG.getConstant(TypeID, VT));
3660 // Return something different to eh_selector.
3661 setValue(&I, DAG.getConstant(1, VT));
3667 case Intrinsic::eh_return_i32:
3668 case Intrinsic::eh_return_i64:
3669 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3670 MMI->setCallsEHReturn(true);
3671 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3674 getValue(I.getOperand(1)),
3675 getValue(I.getOperand(2))));
3677 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3681 case Intrinsic::eh_unwind_init:
3682 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3683 MMI->setCallsUnwindInit(true);
3688 case Intrinsic::eh_dwarf_cfa: {
3689 MVT VT = getValue(I.getOperand(1)).getValueType();
3691 if (VT.bitsGT(TLI.getPointerTy()))
3692 CfaArg = DAG.getNode(ISD::TRUNCATE,
3693 TLI.getPointerTy(), getValue(I.getOperand(1)));
3695 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3696 TLI.getPointerTy(), getValue(I.getOperand(1)));
3698 SDValue Offset = DAG.getNode(ISD::ADD,
3700 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3701 TLI.getPointerTy()),
3703 setValue(&I, DAG.getNode(ISD::ADD,
3705 DAG.getNode(ISD::FRAMEADDR,
3708 TLI.getPointerTy())),
3713 case Intrinsic::sqrt:
3714 setValue(&I, DAG.getNode(ISD::FSQRT,
3715 getValue(I.getOperand(1)).getValueType(),
3716 getValue(I.getOperand(1))));
3718 case Intrinsic::powi:
3719 setValue(&I, DAG.getNode(ISD::FPOWI,
3720 getValue(I.getOperand(1)).getValueType(),
3721 getValue(I.getOperand(1)),
3722 getValue(I.getOperand(2))));
3724 case Intrinsic::sin:
3725 setValue(&I, DAG.getNode(ISD::FSIN,
3726 getValue(I.getOperand(1)).getValueType(),
3727 getValue(I.getOperand(1))));
3729 case Intrinsic::cos:
3730 setValue(&I, DAG.getNode(ISD::FCOS,
3731 getValue(I.getOperand(1)).getValueType(),
3732 getValue(I.getOperand(1))));
3734 case Intrinsic::log:
3737 case Intrinsic::log2:
3740 case Intrinsic::log10:
3743 case Intrinsic::exp:
3746 case Intrinsic::exp2:
3749 case Intrinsic::pow:
3752 case Intrinsic::pcmarker: {
3753 SDValue Tmp = getValue(I.getOperand(1));
3754 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3757 case Intrinsic::readcyclecounter: {
3758 SDValue Op = getRoot();
3759 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3760 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3763 DAG.setRoot(Tmp.getValue(1));
3766 case Intrinsic::part_select: {
3767 // Currently not implemented: just abort
3768 assert(0 && "part_select intrinsic not implemented");
3771 case Intrinsic::part_set: {
3772 // Currently not implemented: just abort
3773 assert(0 && "part_set intrinsic not implemented");
3776 case Intrinsic::bswap:
3777 setValue(&I, DAG.getNode(ISD::BSWAP,
3778 getValue(I.getOperand(1)).getValueType(),
3779 getValue(I.getOperand(1))));
3781 case Intrinsic::cttz: {
3782 SDValue Arg = getValue(I.getOperand(1));
3783 MVT Ty = Arg.getValueType();
3784 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3785 setValue(&I, result);
3788 case Intrinsic::ctlz: {
3789 SDValue Arg = getValue(I.getOperand(1));
3790 MVT Ty = Arg.getValueType();
3791 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3792 setValue(&I, result);
3795 case Intrinsic::ctpop: {
3796 SDValue Arg = getValue(I.getOperand(1));
3797 MVT Ty = Arg.getValueType();
3798 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3799 setValue(&I, result);
3802 case Intrinsic::stacksave: {
3803 SDValue Op = getRoot();
3804 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3805 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3807 DAG.setRoot(Tmp.getValue(1));
3810 case Intrinsic::stackrestore: {
3811 SDValue Tmp = getValue(I.getOperand(1));
3812 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3815 case Intrinsic::var_annotation:
3816 // Discard annotate attributes
3819 case Intrinsic::init_trampoline: {
3820 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3824 Ops[1] = getValue(I.getOperand(1));
3825 Ops[2] = getValue(I.getOperand(2));
3826 Ops[3] = getValue(I.getOperand(3));
3827 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3828 Ops[5] = DAG.getSrcValue(F);
3830 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3831 DAG.getNodeValueTypes(TLI.getPointerTy(),
3836 DAG.setRoot(Tmp.getValue(1));
3840 case Intrinsic::gcroot:
3842 Value *Alloca = I.getOperand(1);
3843 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3845 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
3846 GFI->addStackRoot(FI->getIndex(), TypeMap);
3850 case Intrinsic::gcread:
3851 case Intrinsic::gcwrite:
3852 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
3855 case Intrinsic::flt_rounds: {
3856 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3860 case Intrinsic::trap: {
3861 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3864 case Intrinsic::prefetch: {
3867 Ops[1] = getValue(I.getOperand(1));
3868 Ops[2] = getValue(I.getOperand(2));
3869 Ops[3] = getValue(I.getOperand(3));
3870 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3874 case Intrinsic::memory_barrier: {
3877 for (int x = 1; x < 6; ++x)
3878 Ops[x] = getValue(I.getOperand(x));
3880 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3883 case Intrinsic::atomic_cmp_swap: {
3884 SDValue Root = getRoot();
3886 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3888 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_8, Root,
3889 getValue(I.getOperand(1)),
3890 getValue(I.getOperand(2)),
3891 getValue(I.getOperand(3)),
3895 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_16, Root,
3896 getValue(I.getOperand(1)),
3897 getValue(I.getOperand(2)),
3898 getValue(I.getOperand(3)),
3902 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_32, Root,
3903 getValue(I.getOperand(1)),
3904 getValue(I.getOperand(2)),
3905 getValue(I.getOperand(3)),
3909 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_64, Root,
3910 getValue(I.getOperand(1)),
3911 getValue(I.getOperand(2)),
3912 getValue(I.getOperand(3)),
3916 assert(0 && "Invalid atomic type");
3920 DAG.setRoot(L.getValue(1));
3923 case Intrinsic::atomic_load_add:
3924 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3926 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_8);
3928 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_16);
3930 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_32);
3932 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_64);
3934 assert(0 && "Invalid atomic type");
3937 case Intrinsic::atomic_load_sub:
3938 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3940 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_8);
3942 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_16);
3944 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_32);
3946 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_64);
3948 assert(0 && "Invalid atomic type");
3951 case Intrinsic::atomic_load_or:
3952 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3954 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_8);
3956 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_16);
3958 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_32);
3960 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_64);
3962 assert(0 && "Invalid atomic type");
3965 case Intrinsic::atomic_load_xor:
3966 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3968 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_8);
3970 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_16);
3972 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_32);
3974 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_64);
3976 assert(0 && "Invalid atomic type");
3979 case Intrinsic::atomic_load_and:
3980 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3982 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_8);
3984 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_16);
3986 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_32);
3988 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_64);
3990 assert(0 && "Invalid atomic type");
3993 case Intrinsic::atomic_load_nand:
3994 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3996 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_8);
3998 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_16);
4000 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_32);
4002 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_64);
4004 assert(0 && "Invalid atomic type");
4007 case Intrinsic::atomic_load_max:
4008 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4010 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_8);
4012 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_16);
4014 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_32);
4016 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_64);
4018 assert(0 && "Invalid atomic type");
4021 case Intrinsic::atomic_load_min:
4022 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4024 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_8);
4026 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_16);
4028 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_32);
4030 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_64);
4032 assert(0 && "Invalid atomic type");
4035 case Intrinsic::atomic_load_umin:
4036 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4038 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_8);
4040 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_16);
4042 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_32);
4044 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_64);
4046 assert(0 && "Invalid atomic type");
4049 case Intrinsic::atomic_load_umax:
4050 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4052 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_8);
4054 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_16);
4056 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_32);
4058 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_64);
4060 assert(0 && "Invalid atomic type");
4063 case Intrinsic::atomic_swap:
4064 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4066 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_8);
4068 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_16);
4070 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_32);
4072 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_64);
4074 assert(0 && "Invalid atomic type");
4081 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4083 MachineBasicBlock *LandingPad) {
4084 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4085 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4086 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4087 unsigned BeginLabel = 0, EndLabel = 0;
4089 TargetLowering::ArgListTy Args;
4090 TargetLowering::ArgListEntry Entry;
4091 Args.reserve(CS.arg_size());
4092 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4094 SDValue ArgNode = getValue(*i);
4095 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4097 unsigned attrInd = i - CS.arg_begin() + 1;
4098 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
4099 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
4100 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
4101 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
4102 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
4103 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
4104 Entry.Alignment = CS.getParamAlignment(attrInd);
4105 Args.push_back(Entry);
4108 if (LandingPad && MMI) {
4109 // Insert a label before the invoke call to mark the try range. This can be
4110 // used to detect deletion of the invoke via the MachineModuleInfo.
4111 BeginLabel = MMI->NextLabelID();
4112 // Both PendingLoads and PendingExports must be flushed here;
4113 // this call might not return.
4115 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
4118 std::pair<SDValue,SDValue> Result =
4119 TLI.LowerCallTo(getRoot(), CS.getType(),
4120 CS.paramHasAttr(0, ParamAttr::SExt),
4121 CS.paramHasAttr(0, ParamAttr::ZExt),
4122 FTy->isVarArg(), CS.getCallingConv(),
4123 IsTailCall && PerformTailCallOpt,
4125 if (CS.getType() != Type::VoidTy)
4126 setValue(CS.getInstruction(), Result.first);
4127 DAG.setRoot(Result.second);
4129 if (LandingPad && MMI) {
4130 // Insert a label at the end of the invoke call to mark the try range. This
4131 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4132 EndLabel = MMI->NextLabelID();
4133 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
4135 // Inform MachineModuleInfo of range.
4136 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4141 void SelectionDAGLowering::visitCall(CallInst &I) {
4142 const char *RenameFn = 0;
4143 if (Function *F = I.getCalledFunction()) {
4144 if (F->isDeclaration()) {
4145 if (unsigned IID = F->getIntrinsicID()) {
4146 RenameFn = visitIntrinsicCall(I, IID);
4152 // Check for well-known libc/libm calls. If the function is internal, it
4153 // can't be a library call.
4154 unsigned NameLen = F->getNameLen();
4155 if (!F->hasInternalLinkage() && NameLen) {
4156 const char *NameStr = F->getNameStart();
4157 if (NameStr[0] == 'c' &&
4158 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4159 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4160 if (I.getNumOperands() == 3 && // Basic sanity checks.
4161 I.getOperand(1)->getType()->isFloatingPoint() &&
4162 I.getType() == I.getOperand(1)->getType() &&
4163 I.getType() == I.getOperand(2)->getType()) {
4164 SDValue LHS = getValue(I.getOperand(1));
4165 SDValue RHS = getValue(I.getOperand(2));
4166 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
4170 } else if (NameStr[0] == 'f' &&
4171 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4172 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4173 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4174 if (I.getNumOperands() == 2 && // Basic sanity checks.
4175 I.getOperand(1)->getType()->isFloatingPoint() &&
4176 I.getType() == I.getOperand(1)->getType()) {
4177 SDValue Tmp = getValue(I.getOperand(1));
4178 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
4181 } else if (NameStr[0] == 's' &&
4182 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4183 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4184 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4185 if (I.getNumOperands() == 2 && // Basic sanity checks.
4186 I.getOperand(1)->getType()->isFloatingPoint() &&
4187 I.getType() == I.getOperand(1)->getType()) {
4188 SDValue Tmp = getValue(I.getOperand(1));
4189 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
4192 } else if (NameStr[0] == 'c' &&
4193 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4194 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4195 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4196 if (I.getNumOperands() == 2 && // Basic sanity checks.
4197 I.getOperand(1)->getType()->isFloatingPoint() &&
4198 I.getType() == I.getOperand(1)->getType()) {
4199 SDValue Tmp = getValue(I.getOperand(1));
4200 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
4205 } else if (isa<InlineAsm>(I.getOperand(0))) {
4212 Callee = getValue(I.getOperand(0));
4214 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4216 LowerCallTo(&I, Callee, I.isTailCall());
4220 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4221 /// this value and returns the result as a ValueVT value. This uses
4222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4223 /// If the Flag pointer is NULL, no flag is used.
4224 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
4226 SDValue *Flag) const {
4227 // Assemble the legal parts into the final values.
4228 SmallVector<SDValue, 4> Values(ValueVTs.size());
4229 SmallVector<SDValue, 8> Parts;
4230 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4231 // Copy the legal parts from the registers.
4232 MVT ValueVT = ValueVTs[Value];
4233 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4234 MVT RegisterVT = RegVTs[Value];
4236 Parts.resize(NumRegs);
4237 for (unsigned i = 0; i != NumRegs; ++i) {
4240 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4242 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4243 *Flag = P.getValue(2);
4245 Chain = P.getValue(1);
4247 // If the source register was virtual and if we know something about it,
4248 // add an assert node.
4249 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4250 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4251 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4252 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4253 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4254 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4256 unsigned RegSize = RegisterVT.getSizeInBits();
4257 unsigned NumSignBits = LOI.NumSignBits;
4258 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4260 // FIXME: We capture more information than the dag can represent. For
4261 // now, just use the tightest assertzext/assertsext possible.
4263 MVT FromVT(MVT::Other);
4264 if (NumSignBits == RegSize)
4265 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4266 else if (NumZeroBits >= RegSize-1)
4267 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4268 else if (NumSignBits > RegSize-8)
4269 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4270 else if (NumZeroBits >= RegSize-9)
4271 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4272 else if (NumSignBits > RegSize-16)
4273 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4274 else if (NumZeroBits >= RegSize-17)
4275 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4276 else if (NumSignBits > RegSize-32)
4277 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4278 else if (NumZeroBits >= RegSize-33)
4279 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4281 if (FromVT != MVT::Other) {
4282 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
4283 RegisterVT, P, DAG.getValueType(FromVT));
4292 Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT,
4298 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4299 &Values[0], ValueVTs.size());
4302 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4303 /// specified value into the registers specified by this object. This uses
4304 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4305 /// If the Flag pointer is NULL, no flag is used.
4306 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
4307 SDValue &Chain, SDValue *Flag) const {
4308 // Get the list of the values's legal parts.
4309 unsigned NumRegs = Regs.size();
4310 SmallVector<SDValue, 8> Parts(NumRegs);
4311 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4312 MVT ValueVT = ValueVTs[Value];
4313 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4314 MVT RegisterVT = RegVTs[Value];
4316 getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
4317 &Parts[Part], NumParts, RegisterVT);
4321 // Copy the parts into the registers.
4322 SmallVector<SDValue, 8> Chains(NumRegs);
4323 for (unsigned i = 0; i != NumRegs; ++i) {
4326 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4328 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4329 *Flag = Part.getValue(1);
4331 Chains[i] = Part.getValue(0);
4334 if (NumRegs == 1 || Flag)
4335 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4336 // flagged to it. That is the CopyToReg nodes and the user are considered
4337 // a single scheduling unit. If we create a TokenFactor and return it as
4338 // chain, then the TokenFactor is both a predecessor (operand) of the
4339 // user as well as a successor (the TF operands are flagged to the user).
4340 // c1, f1 = CopyToReg
4341 // c2, f2 = CopyToReg
4342 // c3 = TokenFactor c1, c2
4345 Chain = Chains[NumRegs-1];
4347 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4350 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4351 /// operand list. This adds the code marker and includes the number of
4352 /// values added into it.
4353 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4354 std::vector<SDValue> &Ops) const {
4355 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4356 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4357 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4358 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4359 MVT RegisterVT = RegVTs[Value];
4360 for (unsigned i = 0; i != NumRegs; ++i)
4361 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4365 /// isAllocatableRegister - If the specified register is safe to allocate,
4366 /// i.e. it isn't a stack pointer or some other special register, return the
4367 /// register class for the register. Otherwise, return null.
4368 static const TargetRegisterClass *
4369 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4370 const TargetLowering &TLI,
4371 const TargetRegisterInfo *TRI) {
4372 MVT FoundVT = MVT::Other;
4373 const TargetRegisterClass *FoundRC = 0;
4374 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4375 E = TRI->regclass_end(); RCI != E; ++RCI) {
4376 MVT ThisVT = MVT::Other;
4378 const TargetRegisterClass *RC = *RCI;
4379 // If none of the the value types for this register class are valid, we
4380 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4381 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4383 if (TLI.isTypeLegal(*I)) {
4384 // If we have already found this register in a different register class,
4385 // choose the one with the largest VT specified. For example, on
4386 // PowerPC, we favor f64 register classes over f32.
4387 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4394 if (ThisVT == MVT::Other) continue;
4396 // NOTE: This isn't ideal. In particular, this might allocate the
4397 // frame pointer in functions that need it (due to them not being taken
4398 // out of allocation, because a variable sized allocation hasn't been seen
4399 // yet). This is a slight code pessimization, but should still work.
4400 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4401 E = RC->allocation_order_end(MF); I != E; ++I)
4403 // We found a matching register class. Keep looking at others in case
4404 // we find one with larger registers that this physreg is also in.
4415 /// AsmOperandInfo - This contains information for each constraint that we are
4417 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4418 public TargetLowering::AsmOperandInfo {
4419 /// CallOperand - If this is the result output operand or a clobber
4420 /// this is null, otherwise it is the incoming operand to the CallInst.
4421 /// This gets modified as the asm is processed.
4422 SDValue CallOperand;
4424 /// AssignedRegs - If this is a register or register class operand, this
4425 /// contains the set of register corresponding to the operand.
4426 RegsForValue AssignedRegs;
4428 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4429 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4432 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4433 /// busy in OutputRegs/InputRegs.
4434 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4435 std::set<unsigned> &OutputRegs,
4436 std::set<unsigned> &InputRegs,
4437 const TargetRegisterInfo &TRI) const {
4439 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4440 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4443 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4444 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4449 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4451 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4452 const TargetRegisterInfo &TRI) {
4453 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4455 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4456 for (; *Aliases; ++Aliases)
4457 Regs.insert(*Aliases);
4460 } // end llvm namespace.
4463 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4464 /// specified operand. We prefer to assign virtual registers, to allow the
4465 /// register allocator handle the assignment process. However, if the asm uses
4466 /// features that we can't model on machineinstrs, we have SDISel do the
4467 /// allocation. This produces generally horrible, but correct, code.
4469 /// OpInfo describes the operand.
4470 /// Input and OutputRegs are the set of already allocated physical registers.
4472 void SelectionDAGLowering::
4473 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4474 std::set<unsigned> &OutputRegs,
4475 std::set<unsigned> &InputRegs) {
4476 // Compute whether this value requires an input register, an output register,
4478 bool isOutReg = false;
4479 bool isInReg = false;
4480 switch (OpInfo.Type) {
4481 case InlineAsm::isOutput:
4484 // If there is an input constraint that matches this, we need to reserve
4485 // the input register so no other inputs allocate to it.
4486 isInReg = OpInfo.hasMatchingInput;
4488 case InlineAsm::isInput:
4492 case InlineAsm::isClobber:
4499 MachineFunction &MF = DAG.getMachineFunction();
4500 SmallVector<unsigned, 4> Regs;
4502 // If this is a constraint for a single physreg, or a constraint for a
4503 // register class, find it.
4504 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4505 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4506 OpInfo.ConstraintVT);
4508 unsigned NumRegs = 1;
4509 if (OpInfo.ConstraintVT != MVT::Other)
4510 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4512 MVT ValueVT = OpInfo.ConstraintVT;
4515 // If this is a constraint for a specific physical register, like {r17},
4517 if (PhysReg.first) {
4518 if (OpInfo.ConstraintVT == MVT::Other)
4519 ValueVT = *PhysReg.second->vt_begin();
4521 // Get the actual register value type. This is important, because the user
4522 // may have asked for (e.g.) the AX register in i32 type. We need to
4523 // remember that AX is actually i16 to get the right extension.
4524 RegVT = *PhysReg.second->vt_begin();
4526 // This is a explicit reference to a physical register.
4527 Regs.push_back(PhysReg.first);
4529 // If this is an expanded reference, add the rest of the regs to Regs.
4531 TargetRegisterClass::iterator I = PhysReg.second->begin();
4532 for (; *I != PhysReg.first; ++I)
4533 assert(I != PhysReg.second->end() && "Didn't find reg!");
4535 // Already added the first reg.
4537 for (; NumRegs; --NumRegs, ++I) {
4538 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4542 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4543 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4544 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4548 // Otherwise, if this was a reference to an LLVM register class, create vregs
4549 // for this reference.
4550 std::vector<unsigned> RegClassRegs;
4551 const TargetRegisterClass *RC = PhysReg.second;
4553 // If this is a tied register, our regalloc doesn't know how to maintain
4554 // the constraint. If it isn't, go ahead and create vreg
4555 // and let the regalloc do the right thing.
4556 if (!OpInfo.hasMatchingInput) {
4557 RegVT = *PhysReg.second->vt_begin();
4558 if (OpInfo.ConstraintVT == MVT::Other)
4561 // Create the appropriate number of virtual registers.
4562 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4563 for (; NumRegs; --NumRegs)
4564 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4566 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4570 // Otherwise, we can't allocate it. Let the code below figure out how to
4571 // maintain these constraints.
4572 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4575 // This is a reference to a register class that doesn't directly correspond
4576 // to an LLVM register class. Allocate NumRegs consecutive, available,
4577 // registers from the class.
4578 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4579 OpInfo.ConstraintVT);
4582 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4583 unsigned NumAllocated = 0;
4584 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4585 unsigned Reg = RegClassRegs[i];
4586 // See if this register is available.
4587 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4588 (isInReg && InputRegs.count(Reg))) { // Already used.
4589 // Make sure we find consecutive registers.
4594 // Check to see if this register is allocatable (i.e. don't give out the
4597 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4598 if (!RC) { // Couldn't allocate this register.
4599 // Reset NumAllocated to make sure we return consecutive registers.
4605 // Okay, this register is good, we can use it.
4608 // If we allocated enough consecutive registers, succeed.
4609 if (NumAllocated == NumRegs) {
4610 unsigned RegStart = (i-NumAllocated)+1;
4611 unsigned RegEnd = i+1;
4612 // Mark all of the allocated registers used.
4613 for (unsigned i = RegStart; i != RegEnd; ++i)
4614 Regs.push_back(RegClassRegs[i]);
4616 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4617 OpInfo.ConstraintVT);
4618 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4623 // Otherwise, we couldn't allocate enough registers for this.
4626 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4627 /// processed uses a memory 'm' constraint.
4629 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4630 TargetLowering &TLI) {
4631 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4632 InlineAsm::ConstraintInfo &CI = CInfos[i];
4633 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4634 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4635 if (CType == TargetLowering::C_Memory)
4643 /// visitInlineAsm - Handle a call to an InlineAsm object.
4645 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4646 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4648 /// ConstraintOperands - Information about all of the constraints.
4649 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4651 SDValue Chain = getRoot();
4654 std::set<unsigned> OutputRegs, InputRegs;
4656 // Do a prepass over the constraints, canonicalizing them, and building up the
4657 // ConstraintOperands list.
4658 std::vector<InlineAsm::ConstraintInfo>
4659 ConstraintInfos = IA->ParseConstraints();
4661 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
4663 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4664 unsigned ResNo = 0; // ResNo - The result number of the next output.
4665 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4666 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4667 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4669 MVT OpVT = MVT::Other;
4671 // Compute the value type for each operand.
4672 switch (OpInfo.Type) {
4673 case InlineAsm::isOutput:
4674 // Indirect outputs just consume an argument.
4675 if (OpInfo.isIndirect) {
4676 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4679 // The return value of the call is this value. As such, there is no
4680 // corresponding argument.
4681 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4682 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4683 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4685 assert(ResNo == 0 && "Asm only has one result!");
4686 OpVT = TLI.getValueType(CS.getType());
4690 case InlineAsm::isInput:
4691 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4693 case InlineAsm::isClobber:
4698 // If this is an input or an indirect output, process the call argument.
4699 // BasicBlocks are labels, currently appearing only in asm's.
4700 if (OpInfo.CallOperandVal) {
4701 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4702 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4704 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4705 const Type *OpTy = OpInfo.CallOperandVal->getType();
4706 // If this is an indirect operand, the operand is a pointer to the
4708 if (OpInfo.isIndirect)
4709 OpTy = cast<PointerType>(OpTy)->getElementType();
4711 // If OpTy is not a single value, it may be a struct/union that we
4712 // can tile with integers.
4713 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4714 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4722 OpTy = IntegerType::get(BitSize);
4727 OpVT = TLI.getValueType(OpTy, true);
4731 OpInfo.ConstraintVT = OpVT;
4733 // Compute the constraint code and ConstraintType to use.
4734 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
4736 // If this is a memory input, and if the operand is not indirect, do what we
4737 // need to to provide an address for the memory input.
4738 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4739 !OpInfo.isIndirect) {
4740 assert(OpInfo.Type == InlineAsm::isInput &&
4741 "Can only indirectify direct input operands!");
4743 // Memory operands really want the address of the value. If we don't have
4744 // an indirect input, put it in the constpool if we can, otherwise spill
4745 // it to a stack slot.
4747 // If the operand is a float, integer, or vector constant, spill to a
4748 // constant pool entry to get its address.
4749 Value *OpVal = OpInfo.CallOperandVal;
4750 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4751 isa<ConstantVector>(OpVal)) {
4752 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4753 TLI.getPointerTy());
4755 // Otherwise, create a stack slot and emit a store to it before the
4757 const Type *Ty = OpVal->getType();
4758 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4759 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4760 MachineFunction &MF = DAG.getMachineFunction();
4761 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4762 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4763 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4764 OpInfo.CallOperand = StackSlot;
4767 // There is no longer a Value* corresponding to this operand.
4768 OpInfo.CallOperandVal = 0;
4769 // It is now an indirect operand.
4770 OpInfo.isIndirect = true;
4773 // If this constraint is for a specific register, allocate it before
4775 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4776 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4778 ConstraintInfos.clear();
4781 // Second pass - Loop over all of the operands, assigning virtual or physregs
4782 // to registerclass operands.
4783 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4784 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4786 // C_Register operands have already been allocated, Other/Memory don't need
4788 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4789 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4792 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4793 std::vector<SDValue> AsmNodeOperands;
4794 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4795 AsmNodeOperands.push_back(
4796 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4799 // Loop over all of the inputs, copying the operand values into the
4800 // appropriate registers and processing the output regs.
4801 RegsForValue RetValRegs;
4803 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4804 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4806 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4807 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4809 switch (OpInfo.Type) {
4810 case InlineAsm::isOutput: {
4811 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4812 OpInfo.ConstraintType != TargetLowering::C_Register) {
4813 // Memory output, or 'other' output (e.g. 'X' constraint).
4814 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4816 // Add information to the INLINEASM node to know about this output.
4817 unsigned ResOpType = 4/*MEM*/ | (1<<3);
4818 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4819 TLI.getPointerTy()));
4820 AsmNodeOperands.push_back(OpInfo.CallOperand);
4824 // Otherwise, this is a register or register class output.
4826 // Copy the output from the appropriate register. Find a register that
4828 if (OpInfo.AssignedRegs.Regs.empty()) {
4829 cerr << "Couldn't allocate output reg for constraint '"
4830 << OpInfo.ConstraintCode << "'!\n";
4834 // If this is an indirect operand, store through the pointer after the
4836 if (OpInfo.isIndirect) {
4837 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4838 OpInfo.CallOperandVal));
4840 // This is the result value of the call.
4841 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4842 // Concatenate this output onto the outputs list.
4843 RetValRegs.append(OpInfo.AssignedRegs);
4846 // Add information to the INLINEASM node to know that this register is
4848 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
4849 6 /* EARLYCLOBBER REGDEF */ :
4851 DAG, AsmNodeOperands);
4854 case InlineAsm::isInput: {
4855 SDValue InOperandVal = OpInfo.CallOperand;
4857 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4858 // If this is required to match an output register we have already set,
4859 // just use its register.
4860 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4862 // Scan until we find the definition we already emitted of this operand.
4863 // When we find it, create a RegsForValue operand.
4864 unsigned CurOp = 2; // The first operand.
4865 for (; OperandNo; --OperandNo) {
4866 // Advance to the next operand.
4868 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
4869 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4870 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
4871 (NumOps & 7) == 4 /*MEM*/) &&
4872 "Skipped past definitions?");
4873 CurOp += (NumOps>>3)+1;
4877 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
4878 if ((NumOps & 7) == 2 /*REGDEF*/
4879 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
4880 // Add NumOps>>3 registers to MatchedRegs.
4881 RegsForValue MatchedRegs;
4882 MatchedRegs.TLI = &TLI;
4883 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4884 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4885 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4887 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4888 MatchedRegs.Regs.push_back(Reg);
4891 // Use the produced MatchedRegs object to
4892 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4893 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4896 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
4897 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4898 // Add information to the INLINEASM node to know about this input.
4899 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
4900 TLI.getPointerTy()));
4901 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4906 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4907 assert(!OpInfo.isIndirect &&
4908 "Don't know how to handle indirect other inputs yet!");
4910 std::vector<SDValue> Ops;
4911 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4912 hasMemory, Ops, DAG);
4914 cerr << "Invalid operand for inline asm constraint '"
4915 << OpInfo.ConstraintCode << "'!\n";
4919 // Add information to the INLINEASM node to know about this input.
4920 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4921 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4922 TLI.getPointerTy()));
4923 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4925 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4926 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4927 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4928 "Memory operands expect pointer values");
4930 // Add information to the INLINEASM node to know about this input.
4931 unsigned ResOpType = 4/*MEM*/ | (1<<3);
4932 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4933 TLI.getPointerTy()));
4934 AsmNodeOperands.push_back(InOperandVal);
4938 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4939 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4940 "Unknown constraint type!");
4941 assert(!OpInfo.isIndirect &&
4942 "Don't know how to handle indirect register inputs yet!");
4944 // Copy the input into the appropriate registers.
4945 if (OpInfo.AssignedRegs.Regs.empty()) {
4946 cerr << "Couldn't allocate output reg for constraint '"
4947 << OpInfo.ConstraintCode << "'!\n";
4951 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4953 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
4954 DAG, AsmNodeOperands);
4957 case InlineAsm::isClobber: {
4958 // Add the clobbered value to the operand list, so that the register
4959 // allocator is aware that the physreg got clobbered.
4960 if (!OpInfo.AssignedRegs.Regs.empty())
4961 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
4962 DAG, AsmNodeOperands);
4968 // Finish up input operands.
4969 AsmNodeOperands[0] = Chain;
4970 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
4972 Chain = DAG.getNode(ISD::INLINEASM,
4973 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4974 &AsmNodeOperands[0], AsmNodeOperands.size());
4975 Flag = Chain.getValue(1);
4977 // If this asm returns a register value, copy the result from that register
4978 // and set it as the value of the call.
4979 if (!RetValRegs.Regs.empty()) {
4980 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4982 // If any of the results of the inline asm is a vector, it may have the
4983 // wrong width/num elts. This can happen for register classes that can
4984 // contain multiple different value types. The preg or vreg allocated may
4985 // not have the same VT as was expected. Convert it to the right type with
4987 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4988 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4989 if (Val.getNode()->getValueType(i).isVector())
4990 Val = DAG.getNode(ISD::BIT_CONVERT,
4991 TLI.getValueType(ResSTy->getElementType(i)), Val);
4994 if (Val.getValueType().isVector())
4995 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4999 setValue(CS.getInstruction(), Val);
5002 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5004 // Process indirect outputs, first output all of the flagged copies out of
5006 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5007 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5008 Value *Ptr = IndirectStoresToEmit[i].second;
5009 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
5010 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5013 // Emit the non-flagged stores from the physregs.
5014 SmallVector<SDValue, 8> OutChains;
5015 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5016 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
5017 getValue(StoresToEmit[i].second),
5018 StoresToEmit[i].second, 0));
5019 if (!OutChains.empty())
5020 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5021 &OutChains[0], OutChains.size());
5026 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5027 SDValue Src = getValue(I.getOperand(0));
5029 MVT IntPtr = TLI.getPointerTy();
5031 if (IntPtr.bitsLT(Src.getValueType()))
5032 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
5033 else if (IntPtr.bitsGT(Src.getValueType()))
5034 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
5036 // Scale the source by the type size.
5037 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
5038 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
5039 Src, DAG.getIntPtrConstant(ElementSize));
5041 TargetLowering::ArgListTy Args;
5042 TargetLowering::ArgListEntry Entry;
5044 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5045 Args.push_back(Entry);
5047 std::pair<SDValue,SDValue> Result =
5048 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
5049 PerformTailCallOpt, DAG.getExternalSymbol("malloc", IntPtr),
5051 setValue(&I, Result.first); // Pointers always fit in registers
5052 DAG.setRoot(Result.second);
5055 void SelectionDAGLowering::visitFree(FreeInst &I) {
5056 TargetLowering::ArgListTy Args;
5057 TargetLowering::ArgListEntry Entry;
5058 Entry.Node = getValue(I.getOperand(0));
5059 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5060 Args.push_back(Entry);
5061 MVT IntPtr = TLI.getPointerTy();
5062 std::pair<SDValue,SDValue> Result =
5063 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
5064 CallingConv::C, PerformTailCallOpt,
5065 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
5066 DAG.setRoot(Result.second);
5069 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5070 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
5071 getValue(I.getOperand(1)),
5072 DAG.getSrcValue(I.getOperand(1))));
5075 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5076 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
5077 getValue(I.getOperand(0)),
5078 DAG.getSrcValue(I.getOperand(0)));
5080 DAG.setRoot(V.getValue(1));
5083 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5084 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
5085 getValue(I.getOperand(1)),
5086 DAG.getSrcValue(I.getOperand(1))));
5089 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5090 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
5091 getValue(I.getOperand(1)),
5092 getValue(I.getOperand(2)),
5093 DAG.getSrcValue(I.getOperand(1)),
5094 DAG.getSrcValue(I.getOperand(2))));
5097 /// TargetLowering::LowerArguments - This is the default LowerArguments
5098 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5099 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5100 /// integrated into SDISel.
5101 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5102 SmallVectorImpl<SDValue> &ArgValues) {
5103 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5104 SmallVector<SDValue, 3+16> Ops;
5105 Ops.push_back(DAG.getRoot());
5106 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5107 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5109 // Add one result value for each formal argument.
5110 SmallVector<MVT, 16> RetVals;
5112 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5114 SmallVector<MVT, 4> ValueVTs;
5115 ComputeValueVTs(*this, I->getType(), ValueVTs);
5116 for (unsigned Value = 0, NumValues = ValueVTs.size();
5117 Value != NumValues; ++Value) {
5118 MVT VT = ValueVTs[Value];
5119 const Type *ArgTy = VT.getTypeForMVT();
5120 ISD::ArgFlagsTy Flags;
5121 unsigned OriginalAlignment =
5122 getTargetData()->getABITypeAlignment(ArgTy);
5124 if (F.paramHasAttr(j, ParamAttr::ZExt))
5126 if (F.paramHasAttr(j, ParamAttr::SExt))
5128 if (F.paramHasAttr(j, ParamAttr::InReg))
5130 if (F.paramHasAttr(j, ParamAttr::StructRet))
5132 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
5134 const PointerType *Ty = cast<PointerType>(I->getType());
5135 const Type *ElementTy = Ty->getElementType();
5136 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5137 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5138 // For ByVal, alignment should be passed from FE. BE will guess if
5139 // this info is not there but there are cases it cannot get right.
5140 if (F.getParamAlignment(j))
5141 FrameAlign = F.getParamAlignment(j);
5142 Flags.setByValAlign(FrameAlign);
5143 Flags.setByValSize(FrameSize);
5145 if (F.paramHasAttr(j, ParamAttr::Nest))
5147 Flags.setOrigAlign(OriginalAlignment);
5149 MVT RegisterVT = getRegisterType(VT);
5150 unsigned NumRegs = getNumRegisters(VT);
5151 for (unsigned i = 0; i != NumRegs; ++i) {
5152 RetVals.push_back(RegisterVT);
5153 ISD::ArgFlagsTy MyFlags = Flags;
5154 if (NumRegs > 1 && i == 0)
5156 // if it isn't first piece, alignment must be 1
5158 MyFlags.setOrigAlign(1);
5159 Ops.push_back(DAG.getArgFlags(MyFlags));
5164 RetVals.push_back(MVT::Other);
5167 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
5168 DAG.getVTList(&RetVals[0], RetVals.size()),
5169 &Ops[0], Ops.size()).getNode();
5171 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5172 // allows exposing the loads that may be part of the argument access to the
5173 // first DAGCombiner pass.
5174 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5176 // The number of results should match up, except that the lowered one may have
5177 // an extra flag result.
5178 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5179 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5180 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5181 && "Lowering produced unexpected number of results!");
5183 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5184 if (Result != TmpRes.getNode() && Result->use_empty()) {
5185 HandleSDNode Dummy(DAG.getRoot());
5186 DAG.RemoveDeadNode(Result);
5189 Result = TmpRes.getNode();
5191 unsigned NumArgRegs = Result->getNumValues() - 1;
5192 DAG.setRoot(SDValue(Result, NumArgRegs));
5194 // Set up the return result vector.
5197 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5199 SmallVector<MVT, 4> ValueVTs;
5200 ComputeValueVTs(*this, I->getType(), ValueVTs);
5201 for (unsigned Value = 0, NumValues = ValueVTs.size();
5202 Value != NumValues; ++Value) {
5203 MVT VT = ValueVTs[Value];
5204 MVT PartVT = getRegisterType(VT);
5206 unsigned NumParts = getNumRegisters(VT);
5207 SmallVector<SDValue, 4> Parts(NumParts);
5208 for (unsigned j = 0; j != NumParts; ++j)
5209 Parts[j] = SDValue(Result, i++);
5211 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5212 if (F.paramHasAttr(Idx, ParamAttr::SExt))
5213 AssertOp = ISD::AssertSext;
5214 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
5215 AssertOp = ISD::AssertZext;
5217 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
5221 assert(i == NumArgRegs && "Argument register count mismatch!");
5225 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5226 /// implementation, which just inserts an ISD::CALL node, which is later custom
5227 /// lowered by the target to something concrete. FIXME: When all targets are
5228 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5229 std::pair<SDValue, SDValue>
5230 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5231 bool RetSExt, bool RetZExt, bool isVarArg,
5232 unsigned CallingConv, bool isTailCall,
5234 ArgListTy &Args, SelectionDAG &DAG) {
5235 assert((!isTailCall || PerformTailCallOpt) &&
5236 "isTailCall set when tail-call optimizations are disabled!");
5238 SmallVector<SDValue, 32> Ops;
5239 Ops.push_back(Chain); // Op#0 - Chain
5240 Ops.push_back(Callee);
5242 // Handle all of the outgoing arguments.
5243 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5244 SmallVector<MVT, 4> ValueVTs;
5245 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5246 for (unsigned Value = 0, NumValues = ValueVTs.size();
5247 Value != NumValues; ++Value) {
5248 MVT VT = ValueVTs[Value];
5249 const Type *ArgTy = VT.getTypeForMVT();
5250 SDValue Op = SDValue(Args[i].Node.getNode(), Args[i].Node.getResNo() + Value);
5251 ISD::ArgFlagsTy Flags;
5252 unsigned OriginalAlignment =
5253 getTargetData()->getABITypeAlignment(ArgTy);
5259 if (Args[i].isInReg)
5263 if (Args[i].isByVal) {
5265 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5266 const Type *ElementTy = Ty->getElementType();
5267 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5268 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5269 // For ByVal, alignment should come from FE. BE will guess if this
5270 // info is not there but there are cases it cannot get right.
5271 if (Args[i].Alignment)
5272 FrameAlign = Args[i].Alignment;
5273 Flags.setByValAlign(FrameAlign);
5274 Flags.setByValSize(FrameSize);
5278 Flags.setOrigAlign(OriginalAlignment);
5280 MVT PartVT = getRegisterType(VT);
5281 unsigned NumParts = getNumRegisters(VT);
5282 SmallVector<SDValue, 4> Parts(NumParts);
5283 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5286 ExtendKind = ISD::SIGN_EXTEND;
5287 else if (Args[i].isZExt)
5288 ExtendKind = ISD::ZERO_EXTEND;
5290 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5292 for (unsigned i = 0; i != NumParts; ++i) {
5293 // if it isn't first piece, alignment must be 1
5294 ISD::ArgFlagsTy MyFlags = Flags;
5295 if (NumParts > 1 && i == 0)
5298 MyFlags.setOrigAlign(1);
5300 Ops.push_back(Parts[i]);
5301 Ops.push_back(DAG.getArgFlags(MyFlags));
5306 // Figure out the result value types. We start by making a list of
5307 // the potentially illegal return value types.
5308 SmallVector<MVT, 4> LoweredRetTys;
5309 SmallVector<MVT, 4> RetTys;
5310 ComputeValueVTs(*this, RetTy, RetTys);
5312 // Then we translate that to a list of legal types.
5313 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5315 MVT RegisterVT = getRegisterType(VT);
5316 unsigned NumRegs = getNumRegisters(VT);
5317 for (unsigned i = 0; i != NumRegs; ++i)
5318 LoweredRetTys.push_back(RegisterVT);
5321 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5323 // Create the CALL node.
5324 SDValue Res = DAG.getCall(CallingConv, isVarArg, isTailCall,
5325 DAG.getVTList(&LoweredRetTys[0],
5326 LoweredRetTys.size()),
5327 &Ops[0], Ops.size());
5328 Chain = Res.getValue(LoweredRetTys.size() - 1);
5330 // Gather up the call result into a single value.
5331 if (RetTy != Type::VoidTy) {
5332 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5335 AssertOp = ISD::AssertSext;
5337 AssertOp = ISD::AssertZext;
5339 SmallVector<SDValue, 4> ReturnValues;
5341 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5343 MVT RegisterVT = getRegisterType(VT);
5344 unsigned NumRegs = getNumRegisters(VT);
5345 unsigned RegNoEnd = NumRegs + RegNo;
5346 SmallVector<SDValue, 4> Results;
5347 for (; RegNo != RegNoEnd; ++RegNo)
5348 Results.push_back(Res.getValue(RegNo));
5349 SDValue ReturnValue =
5350 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
5352 ReturnValues.push_back(ReturnValue);
5354 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
5355 &ReturnValues[0], ReturnValues.size());
5358 return std::make_pair(Res, Chain);
5361 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5362 assert(0 && "LowerOperation not implemented for this target!");
5368 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5369 SDValue Op = getValue(V);
5370 assert((Op.getOpcode() != ISD::CopyFromReg ||
5371 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5372 "Copy from a reg to the same reg!");
5373 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5375 RegsForValue RFV(TLI, Reg, V->getType());
5376 SDValue Chain = DAG.getEntryNode();
5377 RFV.getCopyToRegs(Op, DAG, Chain, 0);
5378 PendingExports.push_back(Chain);
5381 #include "llvm/CodeGen/SelectionDAGISel.h"
5383 void SelectionDAGISel::
5384 LowerArguments(BasicBlock *LLVMBB) {
5385 // If this is the entry block, emit arguments.
5386 Function &F = *LLVMBB->getParent();
5387 SDValue OldRoot = SDL->DAG.getRoot();
5388 SmallVector<SDValue, 16> Args;
5389 TLI.LowerArguments(F, SDL->DAG, Args);
5392 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5394 SmallVector<MVT, 4> ValueVTs;
5395 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5396 unsigned NumValues = ValueVTs.size();
5397 if (!AI->use_empty()) {
5398 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5399 // If this argument is live outside of the entry block, insert a copy from
5400 // whereever we got it to the vreg that other BB's will reference it as.
5401 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5402 if (VMI != FuncInfo->ValueMap.end()) {
5403 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5409 // Finally, if the target has anything special to do, allow it to do so.
5410 // FIXME: this should insert code into the DAG!
5411 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5414 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5415 /// ensure constants are generated when needed. Remember the virtual registers
5416 /// that need to be added to the Machine PHI nodes as input. We cannot just
5417 /// directly add them, because expansion might result in multiple MBB's for one
5418 /// BB. As such, the start of the BB might correspond to a different MBB than
5422 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5423 TerminatorInst *TI = LLVMBB->getTerminator();
5425 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5427 // Check successor nodes' PHI nodes that expect a constant to be available
5429 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5430 BasicBlock *SuccBB = TI->getSuccessor(succ);
5431 if (!isa<PHINode>(SuccBB->begin())) continue;
5432 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5434 // If this terminator has multiple identical successors (common for
5435 // switches), only handle each succ once.
5436 if (!SuccsHandled.insert(SuccMBB)) continue;
5438 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5441 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5442 // nodes and Machine PHI nodes, but the incoming operands have not been
5444 for (BasicBlock::iterator I = SuccBB->begin();
5445 (PN = dyn_cast<PHINode>(I)); ++I) {
5446 // Ignore dead phi's.
5447 if (PN->use_empty()) continue;
5450 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5452 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5453 unsigned &RegOut = SDL->ConstantsOut[C];
5455 RegOut = FuncInfo->CreateRegForValue(C);
5456 SDL->CopyValueToVirtualRegister(C, RegOut);
5460 Reg = FuncInfo->ValueMap[PHIOp];
5462 assert(isa<AllocaInst>(PHIOp) &&
5463 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5464 "Didn't codegen value into a register!??");
5465 Reg = FuncInfo->CreateRegForValue(PHIOp);
5466 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5470 // Remember that this register needs to added to the machine PHI node as
5471 // the input for this MBB.
5472 SmallVector<MVT, 4> ValueVTs;
5473 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5474 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5475 MVT VT = ValueVTs[vti];
5476 unsigned NumRegisters = TLI.getNumRegisters(VT);
5477 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5478 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5479 Reg += NumRegisters;
5483 SDL->ConstantsOut.clear();
5486 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5487 /// supports legal types, and it emits MachineInstrs directly instead of
5488 /// creating SelectionDAG nodes.
5491 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5493 TerminatorInst *TI = LLVMBB->getTerminator();
5495 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5496 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5498 // Check successor nodes' PHI nodes that expect a constant to be available
5500 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5501 BasicBlock *SuccBB = TI->getSuccessor(succ);
5502 if (!isa<PHINode>(SuccBB->begin())) continue;
5503 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5505 // If this terminator has multiple identical successors (common for
5506 // switches), only handle each succ once.
5507 if (!SuccsHandled.insert(SuccMBB)) continue;
5509 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5512 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5513 // nodes and Machine PHI nodes, but the incoming operands have not been
5515 for (BasicBlock::iterator I = SuccBB->begin();
5516 (PN = dyn_cast<PHINode>(I)); ++I) {
5517 // Ignore dead phi's.
5518 if (PN->use_empty()) continue;
5520 // Only handle legal types. Two interesting things to note here. First,
5521 // by bailing out early, we may leave behind some dead instructions,
5522 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5523 // own moves. Second, this check is necessary becuase FastISel doesn't
5524 // use CreateRegForValue to create registers, so it always creates
5525 // exactly one register for each non-void instruction.
5526 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5527 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5530 VT = TLI.getTypeToTransformTo(VT);
5532 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5537 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5539 unsigned Reg = F->getRegForValue(PHIOp);
5541 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5544 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));