1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Base case: we can get an MVT for this LLVM IR type.
139 ValueVTs.push_back(TLI.getValueType(Ty));
141 Offsets->push_back(StartingOffset);
145 /// RegsForValue - This struct represents the registers (physical or virtual)
146 /// that a particular set of values is assigned, and the type information about
147 /// the value. The most common situation is to represent one value at a time,
148 /// but struct or array values are handled element-wise as multiple values.
149 /// The splitting of aggregates is performed recursively, so that we never
150 /// have aggregate-typed registers. The values at this point do not necessarily
151 /// have legal types, so each value may require one or more registers of some
154 struct VISIBILITY_HIDDEN RegsForValue {
155 /// TLI - The TargetLowering object.
157 const TargetLowering *TLI;
159 /// ValueVTs - The value types of the values, which may not be legal, and
160 /// may need be promoted or synthesized from one or more registers.
162 SmallVector<MVT, 4> ValueVTs;
164 /// RegVTs - The value types of the registers. This is the same size as
165 /// ValueVTs and it records, for each value, what the type of the assigned
166 /// register or registers are. (Individual values are never synthesized
167 /// from more than one type of register.)
169 /// With virtual registers, the contents of RegVTs is redundant with TLI's
170 /// getRegisterType member function, however when with physical registers
171 /// it is necessary to have a separate record of the types.
173 SmallVector<MVT, 4> RegVTs;
175 /// Regs - This list holds the registers assigned to the values.
176 /// Each legal or promoted value requires one register, and each
177 /// expanded value requires multiple registers.
179 SmallVector<unsigned, 4> Regs;
181 RegsForValue() : TLI(0) {}
183 RegsForValue(const TargetLowering &tli,
184 const SmallVector<unsigned, 4> ®s,
185 MVT regvt, MVT valuevt)
186 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> ®s,
189 const SmallVector<MVT, 4> ®vts,
190 const SmallVector<MVT, 4> &valuevts)
191 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
192 RegsForValue(const TargetLowering &tli,
193 unsigned Reg, const Type *Ty) : TLI(&tli) {
194 ComputeValueVTs(tli, Ty, ValueVTs);
196 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
197 MVT ValueVT = ValueVTs[Value];
198 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
199 MVT RegisterVT = TLI->getRegisterType(ValueVT);
200 for (unsigned i = 0; i != NumRegs; ++i)
201 Regs.push_back(Reg + i);
202 RegVTs.push_back(RegisterVT);
207 /// append - Add the specified values to this one.
208 void append(const RegsForValue &RHS) {
210 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
211 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
212 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
216 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
217 /// this value and returns the result as a ValueVTs value. This uses
218 /// Chain/Flag as the input and updates them for the output Chain/Flag.
219 /// If the Flag pointer is NULL, no flag is used.
220 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
221 SDValue &Chain, SDValue *Flag) const;
223 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
224 /// specified value into the registers specified by this object. This uses
225 /// Chain/Flag as the input and updates them for the output Chain/Flag.
226 /// If the Flag pointer is NULL, no flag is used.
227 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
228 SDValue &Chain, SDValue *Flag) const;
230 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
231 /// operand list. This adds the code marker and includes the number of
232 /// values added into it.
233 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
234 std::vector<SDValue> &Ops) const;
238 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
239 /// PHI nodes or outside of the basic block that defines it, or used by a
240 /// switch or atomic instruction, which may expand to multiple basic blocks.
241 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
242 if (isa<PHINode>(I)) return true;
243 BasicBlock *BB = I->getParent();
244 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
245 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
246 // FIXME: Remove switchinst special case.
247 isa<SwitchInst>(*UI))
252 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
253 /// entry block, return true. This includes arguments used by switches, since
254 /// the switch may expand into multiple basic blocks.
255 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
256 // With FastISel active, we may be splitting blocks, so force creation
257 // of virtual registers for all non-dead arguments.
258 // Don't force virtual registers for byval arguments though, because
259 // fast-isel can't handle those in all cases.
260 if (EnableFastISel && !A->hasByValAttr())
261 return A->use_empty();
263 BasicBlock *Entry = A->getParent()->begin();
264 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
265 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
266 return false; // Use not in entry block.
270 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
274 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
276 bool EnableFastISel) {
279 RegInfo = &MF->getRegInfo();
281 // Create a vreg for each argument register that is not dead and is used
282 // outside of the entry block for the function.
283 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
285 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
286 InitializeRegForValue(AI);
288 // Initialize the mapping of values to registers. This is only set up for
289 // instruction values that are used outside of the block that defines
291 Function::iterator BB = Fn->begin(), EB = Fn->end();
292 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
293 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
294 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
295 const Type *Ty = AI->getAllocatedType();
296 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
298 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
301 TySize *= CUI->getZExtValue(); // Get total allocated size.
302 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
303 StaticAllocaMap[AI] =
304 MF->getFrameInfo()->CreateStackObject(TySize, Align);
307 for (; BB != EB; ++BB)
308 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
309 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
310 if (!isa<AllocaInst>(I) ||
311 !StaticAllocaMap.count(cast<AllocaInst>(I)))
312 InitializeRegForValue(I);
314 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
315 // also creates the initial PHI MachineInstrs, though none of the input
316 // operands are populated.
317 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
318 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
322 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
326 for (BasicBlock::iterator
327 I = BB->begin(), E = BB->end(); I != E; ++I) {
328 if (CallInst *CI = dyn_cast<CallInst>(I)) {
329 if (Function *F = CI->getCalledFunction()) {
330 switch (F->getIntrinsicID()) {
332 case Intrinsic::dbg_stoppoint: {
333 DwarfWriter *DW = DAG.getDwarfWriter();
334 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
336 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
337 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
338 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
340 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
343 DL = DebugLoc::get(idx);
348 case Intrinsic::dbg_func_start: {
349 DwarfWriter *DW = DAG.getDwarfWriter();
351 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
352 Value *SP = FSI->getSubprogram();
354 if (DW->ValidDebugInfo(SP)) {
355 DISubprogram Subprogram(cast<GlobalVariable>(SP));
356 DICompileUnit CU(Subprogram.getCompileUnit());
357 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
359 unsigned Line = Subprogram.getLineNumber();
360 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
370 PN = dyn_cast<PHINode>(I);
371 if (!PN || PN->use_empty()) continue;
373 unsigned PHIReg = ValueMap[PN];
374 assert(PHIReg && "PHI node does not have an assigned virtual register!");
376 SmallVector<MVT, 4> ValueVTs;
377 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
378 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
379 MVT VT = ValueVTs[vti];
380 unsigned NumRegisters = TLI.getNumRegisters(VT);
381 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
382 for (unsigned i = 0; i != NumRegisters; ++i)
383 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
384 PHIReg += NumRegisters;
390 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
391 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
394 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
395 /// the correctly promoted or expanded types. Assign these registers
396 /// consecutive vreg numbers and return the first assigned number.
398 /// In the case that the given value has struct or array type, this function
399 /// will assign registers for each member or element.
401 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
402 SmallVector<MVT, 4> ValueVTs;
403 ComputeValueVTs(TLI, V->getType(), ValueVTs);
405 unsigned FirstReg = 0;
406 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
407 MVT ValueVT = ValueVTs[Value];
408 MVT RegisterVT = TLI.getRegisterType(ValueVT);
410 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
411 for (unsigned i = 0; i != NumRegs; ++i) {
412 unsigned R = MakeReg(RegisterVT);
413 if (!FirstReg) FirstReg = R;
419 /// getCopyFromParts - Create a value that contains the specified legal parts
420 /// combined into the value they represent. If the parts combine to a type
421 /// larger then ValueVT then AssertOp can be used to specify whether the extra
422 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
423 /// (ISD::AssertSext).
424 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
425 const SDValue *Parts,
426 unsigned NumParts, MVT PartVT, MVT ValueVT,
427 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
428 assert(NumParts > 0 && "No parts to assemble!");
429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
430 SDValue Val = Parts[0];
433 // Assemble the value from multiple parts.
434 if (!ValueVT.isVector()) {
435 unsigned PartBits = PartVT.getSizeInBits();
436 unsigned ValueBits = ValueVT.getSizeInBits();
438 // Assemble the power of 2 part.
439 unsigned RoundParts = NumParts & (NumParts - 1) ?
440 1 << Log2_32(NumParts) : NumParts;
441 unsigned RoundBits = PartBits * RoundParts;
442 MVT RoundVT = RoundBits == ValueBits ?
443 ValueVT : MVT::getIntegerVT(RoundBits);
446 MVT HalfVT = ValueVT.isInteger() ?
447 MVT::getIntegerVT(RoundBits/2) :
448 MVT::getFloatingPointVT(RoundBits/2);
450 if (RoundParts > 2) {
451 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
452 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
455 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
456 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
458 if (TLI.isBigEndian())
460 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
462 if (RoundParts < NumParts) {
463 // Assemble the trailing non-power-of-2 part.
464 unsigned OddParts = NumParts - RoundParts;
465 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
466 Hi = getCopyFromParts(DAG, dl,
467 Parts+RoundParts, OddParts, PartVT, OddVT);
469 // Combine the round and odd parts.
471 if (TLI.isBigEndian())
473 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
474 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
475 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
476 DAG.getConstant(Lo.getValueType().getSizeInBits(),
477 TLI.getPointerTy()));
478 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
479 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
482 // Handle a multi-element vector.
483 MVT IntermediateVT, RegisterVT;
484 unsigned NumIntermediates;
486 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
488 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
489 NumParts = NumRegs; // Silence a compiler warning.
490 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
491 assert(RegisterVT == Parts[0].getValueType() &&
492 "Part type doesn't match part!");
494 // Assemble the parts into intermediate operands.
495 SmallVector<SDValue, 8> Ops(NumIntermediates);
496 if (NumIntermediates == NumParts) {
497 // If the register was not expanded, truncate or copy the value,
499 for (unsigned i = 0; i != NumParts; ++i)
500 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
501 PartVT, IntermediateVT);
502 } else if (NumParts > 0) {
503 // If the intermediate type was expanded, build the intermediate operands
505 assert(NumParts % NumIntermediates == 0 &&
506 "Must expand into a divisible number of parts!");
507 unsigned Factor = NumParts / NumIntermediates;
508 for (unsigned i = 0; i != NumIntermediates; ++i)
509 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
510 PartVT, IntermediateVT);
513 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
515 Val = DAG.getNode(IntermediateVT.isVector() ?
516 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
517 ValueVT, &Ops[0], NumIntermediates);
521 // There is now one part, held in Val. Correct it to match ValueVT.
522 PartVT = Val.getValueType();
524 if (PartVT == ValueVT)
527 if (PartVT.isVector()) {
528 assert(ValueVT.isVector() && "Unknown vector conversion!");
529 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
532 if (ValueVT.isVector()) {
533 assert(ValueVT.getVectorElementType() == PartVT &&
534 ValueVT.getVectorNumElements() == 1 &&
535 "Only trivial scalar-to-vector conversions should get here!");
536 return DAG.getBUILD_VECTOR(ValueVT, dl, Val);
539 if (PartVT.isInteger() &&
540 ValueVT.isInteger()) {
541 if (ValueVT.bitsLT(PartVT)) {
542 // For a truncate, see if we have any information to
543 // indicate whether the truncated bits will always be
544 // zero or sign-extension.
545 if (AssertOp != ISD::DELETED_NODE)
546 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
547 DAG.getValueType(ValueVT));
548 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
550 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
554 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
555 if (ValueVT.bitsLT(Val.getValueType()))
556 // FP_ROUND's are always exact here.
557 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
558 DAG.getIntPtrConstant(1));
559 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
562 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
563 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
565 assert(0 && "Unknown mismatch!");
569 /// getCopyToParts - Create a series of nodes that contain the specified value
570 /// split into legal parts. If the parts contain more bits than Val, then, for
571 /// integers, ExtendKind can be used to specify how to generate the extra bits.
572 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
573 SDValue *Parts, unsigned NumParts, MVT PartVT,
574 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
575 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
576 MVT PtrVT = TLI.getPointerTy();
577 MVT ValueVT = Val.getValueType();
578 unsigned PartBits = PartVT.getSizeInBits();
579 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
584 if (!ValueVT.isVector()) {
585 if (PartVT == ValueVT) {
586 assert(NumParts == 1 && "No-op copy with multiple parts!");
591 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
592 // If the parts cover more bits than the value has, promote the value.
593 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
594 assert(NumParts == 1 && "Do not know what to promote to!");
595 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
596 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
597 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
598 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
600 assert(0 && "Unknown mismatch!");
602 } else if (PartBits == ValueVT.getSizeInBits()) {
603 // Different types of the same size.
604 assert(NumParts == 1 && PartVT != ValueVT);
605 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
606 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
607 // If the parts cover less bits than value has, truncate the value.
608 if (PartVT.isInteger() && ValueVT.isInteger()) {
609 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
610 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
612 assert(0 && "Unknown mismatch!");
616 // The value may have changed - recompute ValueVT.
617 ValueVT = Val.getValueType();
618 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
619 "Failed to tile the value with PartVT!");
622 assert(PartVT == ValueVT && "Type conversion failed!");
627 // Expand the value into multiple parts.
628 if (NumParts & (NumParts - 1)) {
629 // The number of parts is not a power of 2. Split off and copy the tail.
630 assert(PartVT.isInteger() && ValueVT.isInteger() &&
631 "Do not know what to expand to!");
632 unsigned RoundParts = 1 << Log2_32(NumParts);
633 unsigned RoundBits = RoundParts * PartBits;
634 unsigned OddParts = NumParts - RoundParts;
635 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
636 DAG.getConstant(RoundBits,
637 TLI.getPointerTy()));
638 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
639 if (TLI.isBigEndian())
640 // The odd parts were reversed by getCopyToParts - unreverse them.
641 std::reverse(Parts + RoundParts, Parts + NumParts);
642 NumParts = RoundParts;
643 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
644 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
647 // The number of parts is a power of 2. Repeatedly bisect the value using
649 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
650 MVT::getIntegerVT(ValueVT.getSizeInBits()),
652 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
653 for (unsigned i = 0; i < NumParts; i += StepSize) {
654 unsigned ThisBits = StepSize * PartBits / 2;
655 MVT ThisVT = MVT::getIntegerVT (ThisBits);
656 SDValue &Part0 = Parts[i];
657 SDValue &Part1 = Parts[i+StepSize/2];
659 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
661 DAG.getConstant(1, PtrVT));
662 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
664 DAG.getConstant(0, PtrVT));
666 if (ThisBits == PartBits && ThisVT != PartVT) {
667 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
669 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
675 if (TLI.isBigEndian())
676 std::reverse(Parts, Parts + NumParts);
683 if (PartVT != ValueVT) {
684 if (PartVT.isVector()) {
685 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
687 assert(ValueVT.getVectorElementType() == PartVT &&
688 ValueVT.getVectorNumElements() == 1 &&
689 "Only trivial vector-to-scalar conversions should get here!");
690 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
692 DAG.getConstant(0, PtrVT));
700 // Handle a multi-element vector.
701 MVT IntermediateVT, RegisterVT;
702 unsigned NumIntermediates;
703 unsigned NumRegs = TLI
704 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
706 unsigned NumElements = ValueVT.getVectorNumElements();
708 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
709 NumParts = NumRegs; // Silence a compiler warning.
710 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
712 // Split the vector into intermediate operands.
713 SmallVector<SDValue, 8> Ops(NumIntermediates);
714 for (unsigned i = 0; i != NumIntermediates; ++i)
715 if (IntermediateVT.isVector())
716 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
718 DAG.getConstant(i * (NumElements / NumIntermediates),
721 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
723 DAG.getConstant(i, PtrVT));
725 // Split the intermediate operands into legal parts.
726 if (NumParts == NumIntermediates) {
727 // If the register was not expanded, promote or copy the value,
729 for (unsigned i = 0; i != NumParts; ++i)
730 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
731 } else if (NumParts > 0) {
732 // If the intermediate type was expanded, split each the value into
734 assert(NumParts % NumIntermediates == 0 &&
735 "Must expand into a divisible number of parts!");
736 unsigned Factor = NumParts / NumIntermediates;
737 for (unsigned i = 0; i != NumIntermediates; ++i)
738 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
743 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
746 TD = DAG.getTarget().getTargetData();
749 /// clear - Clear out the curret SelectionDAG and the associated
750 /// state and prepare this SelectionDAGLowering object to be used
751 /// for a new block. This doesn't clear out information about
752 /// additional blocks that are needed to complete switch lowering
753 /// or PHI node updating; that information is cleared out as it is
755 void SelectionDAGLowering::clear() {
757 PendingLoads.clear();
758 PendingExports.clear();
760 CurDebugLoc = DebugLoc::getUnknownLoc();
763 /// getRoot - Return the current virtual root of the Selection DAG,
764 /// flushing any PendingLoad items. This must be done before emitting
765 /// a store or any other node that may need to be ordered after any
766 /// prior load instructions.
768 SDValue SelectionDAGLowering::getRoot() {
769 if (PendingLoads.empty())
770 return DAG.getRoot();
772 if (PendingLoads.size() == 1) {
773 SDValue Root = PendingLoads[0];
775 PendingLoads.clear();
779 // Otherwise, we have to make a token factor node.
780 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
781 &PendingLoads[0], PendingLoads.size());
782 PendingLoads.clear();
787 /// getControlRoot - Similar to getRoot, but instead of flushing all the
788 /// PendingLoad items, flush all the PendingExports items. It is necessary
789 /// to do this before emitting a terminator instruction.
791 SDValue SelectionDAGLowering::getControlRoot() {
792 SDValue Root = DAG.getRoot();
794 if (PendingExports.empty())
797 // Turn all of the CopyToReg chains into one factored node.
798 if (Root.getOpcode() != ISD::EntryToken) {
799 unsigned i = 0, e = PendingExports.size();
800 for (; i != e; ++i) {
801 assert(PendingExports[i].getNode()->getNumOperands() > 1);
802 if (PendingExports[i].getNode()->getOperand(0) == Root)
803 break; // Don't add the root if we already indirectly depend on it.
807 PendingExports.push_back(Root);
810 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
812 PendingExports.size());
813 PendingExports.clear();
818 void SelectionDAGLowering::visit(Instruction &I) {
819 visit(I.getOpcode(), I);
822 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
823 // Note: this doesn't use InstVisitor, because it has to work with
824 // ConstantExpr's in addition to instructions.
826 default: assert(0 && "Unknown instruction type encountered!");
828 // Build the switch statement using the Instruction.def file.
829 #define HANDLE_INST(NUM, OPCODE, CLASS) \
830 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
831 #include "llvm/Instruction.def"
835 void SelectionDAGLowering::visitAdd(User &I) {
836 if (I.getType()->isFPOrFPVector())
837 visitBinary(I, ISD::FADD);
839 visitBinary(I, ISD::ADD);
842 void SelectionDAGLowering::visitMul(User &I) {
843 if (I.getType()->isFPOrFPVector())
844 visitBinary(I, ISD::FMUL);
846 visitBinary(I, ISD::MUL);
849 SDValue SelectionDAGLowering::getValue(const Value *V) {
850 SDValue &N = NodeMap[V];
851 if (N.getNode()) return N;
853 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
854 MVT VT = TLI.getValueType(V->getType(), true);
856 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
857 return N = DAG.getConstant(*CI, VT);
859 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
860 return N = DAG.getGlobalAddress(GV, VT);
862 if (isa<ConstantPointerNull>(C))
863 return N = DAG.getConstant(0, TLI.getPointerTy());
865 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
866 return N = DAG.getConstantFP(*CFP, VT);
868 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
869 !V->getType()->isAggregateType())
870 return N = DAG.getUNDEF(VT);
872 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
873 visit(CE->getOpcode(), *CE);
874 SDValue N1 = NodeMap[V];
875 assert(N1.getNode() && "visit didn't populate the ValueMap!");
879 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
880 SmallVector<SDValue, 4> Constants;
881 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
883 SDNode *Val = getValue(*OI).getNode();
884 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
885 Constants.push_back(SDValue(Val, i));
887 return DAG.getMergeValues(&Constants[0], Constants.size(),
891 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
892 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
893 "Unknown struct or array constant!");
895 SmallVector<MVT, 4> ValueVTs;
896 ComputeValueVTs(TLI, C->getType(), ValueVTs);
897 unsigned NumElts = ValueVTs.size();
899 return SDValue(); // empty struct
900 SmallVector<SDValue, 4> Constants(NumElts);
901 for (unsigned i = 0; i != NumElts; ++i) {
902 MVT EltVT = ValueVTs[i];
903 if (isa<UndefValue>(C))
904 Constants[i] = DAG.getUNDEF(EltVT);
905 else if (EltVT.isFloatingPoint())
906 Constants[i] = DAG.getConstantFP(0, EltVT);
908 Constants[i] = DAG.getConstant(0, EltVT);
910 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
913 const VectorType *VecTy = cast<VectorType>(V->getType());
914 unsigned NumElements = VecTy->getNumElements();
916 // Now that we know the number and type of the elements, get that number of
917 // elements into the Ops array based on what kind of constant it is.
918 SmallVector<SDValue, 16> Ops;
919 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
920 for (unsigned i = 0; i != NumElements; ++i)
921 Ops.push_back(getValue(CP->getOperand(i)));
923 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
924 "Unknown vector constant!");
925 MVT EltVT = TLI.getValueType(VecTy->getElementType());
928 if (isa<UndefValue>(C))
929 Op = DAG.getUNDEF(EltVT);
930 else if (EltVT.isFloatingPoint())
931 Op = DAG.getConstantFP(0, EltVT);
933 Op = DAG.getConstant(0, EltVT);
934 Ops.assign(NumElements, Op);
937 // Create a BUILD_VECTOR node.
938 return NodeMap[V] = DAG.getBUILD_VECTOR(VT, getCurDebugLoc(),
939 &Ops[0], Ops.size());
942 // If this is a static alloca, generate it as the frameindex instead of
944 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
945 DenseMap<const AllocaInst*, int>::iterator SI =
946 FuncInfo.StaticAllocaMap.find(AI);
947 if (SI != FuncInfo.StaticAllocaMap.end())
948 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
951 unsigned InReg = FuncInfo.ValueMap[V];
952 assert(InReg && "Value not in map!");
954 RegsForValue RFV(TLI, InReg, V->getType());
955 SDValue Chain = DAG.getEntryNode();
956 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
960 void SelectionDAGLowering::visitRet(ReturnInst &I) {
961 if (I.getNumOperands() == 0) {
962 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
963 MVT::Other, getControlRoot()));
967 SmallVector<SDValue, 8> NewValues;
968 NewValues.push_back(getControlRoot());
969 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
970 SmallVector<MVT, 4> ValueVTs;
971 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
972 unsigned NumValues = ValueVTs.size();
973 if (NumValues == 0) continue;
975 SDValue RetOp = getValue(I.getOperand(i));
976 for (unsigned j = 0, f = NumValues; j != f; ++j) {
977 MVT VT = ValueVTs[j];
979 // FIXME: C calling convention requires the return type to be promoted to
980 // at least 32-bit. But this is not necessary for non-C calling
982 if (VT.isInteger()) {
983 MVT MinVT = TLI.getRegisterType(MVT::i32);
984 if (VT.bitsLT(MinVT))
988 unsigned NumParts = TLI.getNumRegisters(VT);
989 MVT PartVT = TLI.getRegisterType(VT);
990 SmallVector<SDValue, 4> Parts(NumParts);
991 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
993 const Function *F = I.getParent()->getParent();
994 if (F->paramHasAttr(0, Attribute::SExt))
995 ExtendKind = ISD::SIGN_EXTEND;
996 else if (F->paramHasAttr(0, Attribute::ZExt))
997 ExtendKind = ISD::ZERO_EXTEND;
999 getCopyToParts(DAG, getCurDebugLoc(),
1000 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1001 &Parts[0], NumParts, PartVT, ExtendKind);
1003 // 'inreg' on function refers to return value
1004 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1005 if (F->paramHasAttr(0, Attribute::InReg))
1007 for (unsigned i = 0; i < NumParts; ++i) {
1008 NewValues.push_back(Parts[i]);
1009 NewValues.push_back(DAG.getArgFlags(Flags));
1013 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1014 &NewValues[0], NewValues.size()));
1017 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1018 /// the current basic block, add it to ValueMap now so that we'll get a
1020 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1021 // No need to export constants.
1022 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1024 // Already exported?
1025 if (FuncInfo.isExportedInst(V)) return;
1027 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1028 CopyValueToVirtualRegister(V, Reg);
1031 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1032 const BasicBlock *FromBB) {
1033 // The operands of the setcc have to be in this block. We don't know
1034 // how to export them from some other block.
1035 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1036 // Can export from current BB.
1037 if (VI->getParent() == FromBB)
1040 // Is already exported, noop.
1041 return FuncInfo.isExportedInst(V);
1044 // If this is an argument, we can export it if the BB is the entry block or
1045 // if it is already exported.
1046 if (isa<Argument>(V)) {
1047 if (FromBB == &FromBB->getParent()->getEntryBlock())
1050 // Otherwise, can only export this if it is already exported.
1051 return FuncInfo.isExportedInst(V);
1054 // Otherwise, constants can always be exported.
1058 static bool InBlock(const Value *V, const BasicBlock *BB) {
1059 if (const Instruction *I = dyn_cast<Instruction>(V))
1060 return I->getParent() == BB;
1064 /// getFCmpCondCode - Return the ISD condition code corresponding to
1065 /// the given LLVM IR floating-point condition code. This includes
1066 /// consideration of global floating-point math flags.
1068 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1069 ISD::CondCode FPC, FOC;
1071 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1072 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1073 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1074 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1075 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1076 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1077 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1078 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1079 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1080 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1081 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1082 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1083 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1084 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1085 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1086 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1088 assert(0 && "Invalid FCmp predicate opcode!");
1089 FOC = FPC = ISD::SETFALSE;
1092 if (FiniteOnlyFPMath())
1098 /// getICmpCondCode - Return the ISD condition code corresponding to
1099 /// the given LLVM IR integer condition code.
1101 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1103 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1104 case ICmpInst::ICMP_NE: return ISD::SETNE;
1105 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1106 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1107 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1108 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1109 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1110 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1111 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1112 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1114 assert(0 && "Invalid ICmp predicate opcode!");
1119 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1120 /// This function emits a branch and is used at the leaves of an OR or an
1121 /// AND operator tree.
1124 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1125 MachineBasicBlock *TBB,
1126 MachineBasicBlock *FBB,
1127 MachineBasicBlock *CurBB) {
1128 const BasicBlock *BB = CurBB->getBasicBlock();
1130 // If the leaf of the tree is a comparison, merge the condition into
1132 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1133 // The operands of the cmp have to be in this block. We don't know
1134 // how to export them from some other block. If this is the first block
1135 // of the sequence, no exporting is needed.
1136 if (CurBB == CurMBB ||
1137 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1138 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1139 ISD::CondCode Condition;
1140 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1141 Condition = getICmpCondCode(IC->getPredicate());
1142 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1143 Condition = getFCmpCondCode(FC->getPredicate());
1145 Condition = ISD::SETEQ; // silence warning.
1146 assert(0 && "Unknown compare instruction");
1149 CaseBlock CB(Condition, BOp->getOperand(0),
1150 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1151 SwitchCases.push_back(CB);
1156 // Create a CaseBlock record representing this branch.
1157 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1158 NULL, TBB, FBB, CurBB);
1159 SwitchCases.push_back(CB);
1162 /// FindMergedConditions - If Cond is an expression like
1163 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1164 MachineBasicBlock *TBB,
1165 MachineBasicBlock *FBB,
1166 MachineBasicBlock *CurBB,
1168 // If this node is not part of the or/and tree, emit it as a branch.
1169 Instruction *BOp = dyn_cast<Instruction>(Cond);
1170 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1171 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1172 BOp->getParent() != CurBB->getBasicBlock() ||
1173 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1174 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1175 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1179 // Create TmpBB after CurBB.
1180 MachineFunction::iterator BBI = CurBB;
1181 MachineFunction &MF = DAG.getMachineFunction();
1182 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1183 CurBB->getParent()->insert(++BBI, TmpBB);
1185 if (Opc == Instruction::Or) {
1186 // Codegen X | Y as:
1194 // Emit the LHS condition.
1195 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1197 // Emit the RHS condition into TmpBB.
1198 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1200 assert(Opc == Instruction::And && "Unknown merge op!");
1201 // Codegen X & Y as:
1208 // This requires creation of TmpBB after CurBB.
1210 // Emit the LHS condition.
1211 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1213 // Emit the RHS condition into TmpBB.
1214 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1218 /// If the set of cases should be emitted as a series of branches, return true.
1219 /// If we should emit this as a bunch of and/or'd together conditions, return
1222 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1223 if (Cases.size() != 2) return true;
1225 // If this is two comparisons of the same values or'd or and'd together, they
1226 // will get folded into a single comparison, so don't emit two blocks.
1227 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1228 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1229 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1230 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1237 void SelectionDAGLowering::visitBr(BranchInst &I) {
1238 // Update machine-CFG edges.
1239 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1241 // Figure out which block is immediately after the current one.
1242 MachineBasicBlock *NextBlock = 0;
1243 MachineFunction::iterator BBI = CurMBB;
1244 if (++BBI != CurMBB->getParent()->end())
1247 if (I.isUnconditional()) {
1248 // Update machine-CFG edges.
1249 CurMBB->addSuccessor(Succ0MBB);
1251 // If this is not a fall-through branch, emit the branch.
1252 if (Succ0MBB != NextBlock)
1253 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1254 MVT::Other, getControlRoot(),
1255 DAG.getBasicBlock(Succ0MBB)));
1259 // If this condition is one of the special cases we handle, do special stuff
1261 Value *CondVal = I.getCondition();
1262 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1264 // If this is a series of conditions that are or'd or and'd together, emit
1265 // this as a sequence of branches instead of setcc's with and/or operations.
1266 // For example, instead of something like:
1279 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1280 if (BOp->hasOneUse() &&
1281 (BOp->getOpcode() == Instruction::And ||
1282 BOp->getOpcode() == Instruction::Or)) {
1283 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1284 // If the compares in later blocks need to use values not currently
1285 // exported from this block, export them now. This block should always
1286 // be the first entry.
1287 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1289 // Allow some cases to be rejected.
1290 if (ShouldEmitAsBranches(SwitchCases)) {
1291 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1292 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1293 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1296 // Emit the branch for this block.
1297 visitSwitchCase(SwitchCases[0]);
1298 SwitchCases.erase(SwitchCases.begin());
1302 // Okay, we decided not to do this, remove any inserted MBB's and clear
1304 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1305 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1307 SwitchCases.clear();
1311 // Create a CaseBlock record representing this branch.
1312 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1313 NULL, Succ0MBB, Succ1MBB, CurMBB);
1314 // Use visitSwitchCase to actually insert the fast branch sequence for this
1316 visitSwitchCase(CB);
1319 /// visitSwitchCase - Emits the necessary code to represent a single node in
1320 /// the binary search tree resulting from lowering a switch instruction.
1321 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1323 SDValue CondLHS = getValue(CB.CmpLHS);
1324 DebugLoc dl = getCurDebugLoc();
1326 // Build the setcc now.
1327 if (CB.CmpMHS == NULL) {
1328 // Fold "(X == true)" to X and "(X == false)" to !X to
1329 // handle common cases produced by branch lowering.
1330 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1332 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1333 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1334 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1336 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1338 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1340 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1341 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1343 SDValue CmpOp = getValue(CB.CmpMHS);
1344 MVT VT = CmpOp.getValueType();
1346 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1347 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1350 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1351 VT, CmpOp, DAG.getConstant(Low, VT));
1352 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1353 DAG.getConstant(High-Low, VT), ISD::SETULE);
1357 // Update successor info
1358 CurMBB->addSuccessor(CB.TrueBB);
1359 CurMBB->addSuccessor(CB.FalseBB);
1361 // Set NextBlock to be the MBB immediately after the current one, if any.
1362 // This is used to avoid emitting unnecessary branches to the next block.
1363 MachineBasicBlock *NextBlock = 0;
1364 MachineFunction::iterator BBI = CurMBB;
1365 if (++BBI != CurMBB->getParent()->end())
1368 // If the lhs block is the next block, invert the condition so that we can
1369 // fall through to the lhs instead of the rhs block.
1370 if (CB.TrueBB == NextBlock) {
1371 std::swap(CB.TrueBB, CB.FalseBB);
1372 SDValue True = DAG.getConstant(1, Cond.getValueType());
1373 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1375 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1376 MVT::Other, getControlRoot(), Cond,
1377 DAG.getBasicBlock(CB.TrueBB));
1379 // If the branch was constant folded, fix up the CFG.
1380 if (BrCond.getOpcode() == ISD::BR) {
1381 CurMBB->removeSuccessor(CB.FalseBB);
1382 DAG.setRoot(BrCond);
1384 // Otherwise, go ahead and insert the false branch.
1385 if (BrCond == getControlRoot())
1386 CurMBB->removeSuccessor(CB.TrueBB);
1388 if (CB.FalseBB == NextBlock)
1389 DAG.setRoot(BrCond);
1391 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1392 DAG.getBasicBlock(CB.FalseBB)));
1396 /// visitJumpTable - Emit JumpTable node in the current MBB
1397 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1398 // Emit the code for the jump table
1399 assert(JT.Reg != -1U && "Should lower JT Header first!");
1400 MVT PTy = TLI.getPointerTy();
1401 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1403 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1404 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1405 MVT::Other, Index.getValue(1),
1409 /// visitJumpTableHeader - This function emits necessary code to produce index
1410 /// in the JumpTable from switch case.
1411 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1412 JumpTableHeader &JTH) {
1413 // Subtract the lowest switch case value from the value being switched on and
1414 // conditional branch to default mbb if the result is greater than the
1415 // difference between smallest and largest cases.
1416 SDValue SwitchOp = getValue(JTH.SValue);
1417 MVT VT = SwitchOp.getValueType();
1418 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1419 DAG.getConstant(JTH.First, VT));
1421 // The SDNode we just created, which holds the value being switched on minus
1422 // the the smallest case value, needs to be copied to a virtual register so it
1423 // can be used as an index into the jump table in a subsequent basic block.
1424 // This value may be smaller or larger than the target's pointer type, and
1425 // therefore require extension or truncating.
1426 if (VT.bitsGT(TLI.getPointerTy()))
1427 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1428 TLI.getPointerTy(), SUB);
1430 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1431 TLI.getPointerTy(), SUB);
1433 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1434 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1435 JumpTableReg, SwitchOp);
1436 JT.Reg = JumpTableReg;
1438 // Emit the range check for the jump table, and branch to the default block
1439 // for the switch statement if the value being switched on exceeds the largest
1440 // case in the switch.
1441 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1442 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1443 DAG.getConstant(JTH.Last-JTH.First,VT),
1446 // Set NextBlock to be the MBB immediately after the current one, if any.
1447 // This is used to avoid emitting unnecessary branches to the next block.
1448 MachineBasicBlock *NextBlock = 0;
1449 MachineFunction::iterator BBI = CurMBB;
1450 if (++BBI != CurMBB->getParent()->end())
1453 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1454 MVT::Other, CopyTo, CMP,
1455 DAG.getBasicBlock(JT.Default));
1457 if (JT.MBB == NextBlock)
1458 DAG.setRoot(BrCond);
1460 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1461 DAG.getBasicBlock(JT.MBB)));
1464 /// visitBitTestHeader - This function emits necessary code to produce value
1465 /// suitable for "bit tests"
1466 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1467 // Subtract the minimum value
1468 SDValue SwitchOp = getValue(B.SValue);
1469 MVT VT = SwitchOp.getValueType();
1470 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1471 DAG.getConstant(B.First, VT));
1474 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1475 TLI.getSetCCResultType(SUB.getValueType()),
1476 SUB, DAG.getConstant(B.Range, VT),
1480 if (VT.bitsGT(TLI.getPointerTy()))
1481 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1482 TLI.getPointerTy(), SUB);
1484 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1485 TLI.getPointerTy(), SUB);
1487 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1488 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1491 // Set NextBlock to be the MBB immediately after the current one, if any.
1492 // This is used to avoid emitting unnecessary branches to the next block.
1493 MachineBasicBlock *NextBlock = 0;
1494 MachineFunction::iterator BBI = CurMBB;
1495 if (++BBI != CurMBB->getParent()->end())
1498 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1500 CurMBB->addSuccessor(B.Default);
1501 CurMBB->addSuccessor(MBB);
1503 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1504 MVT::Other, CopyTo, RangeCmp,
1505 DAG.getBasicBlock(B.Default));
1507 if (MBB == NextBlock)
1508 DAG.setRoot(BrRange);
1510 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1511 DAG.getBasicBlock(MBB)));
1514 /// visitBitTestCase - this function produces one "bit test"
1515 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1518 // Make desired shift
1519 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1520 TLI.getPointerTy());
1521 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1523 DAG.getConstant(1, TLI.getPointerTy()),
1526 // Emit bit tests and jumps
1527 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1528 TLI.getPointerTy(), SwitchVal,
1529 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1530 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1531 TLI.getSetCCResultType(AndOp.getValueType()),
1532 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1535 CurMBB->addSuccessor(B.TargetBB);
1536 CurMBB->addSuccessor(NextMBB);
1538 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1539 MVT::Other, getControlRoot(),
1540 AndCmp, DAG.getBasicBlock(B.TargetBB));
1542 // Set NextBlock to be the MBB immediately after the current one, if any.
1543 // This is used to avoid emitting unnecessary branches to the next block.
1544 MachineBasicBlock *NextBlock = 0;
1545 MachineFunction::iterator BBI = CurMBB;
1546 if (++BBI != CurMBB->getParent()->end())
1549 if (NextMBB == NextBlock)
1552 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1553 DAG.getBasicBlock(NextMBB)));
1556 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1557 // Retrieve successors.
1558 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1559 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1561 const Value *Callee(I.getCalledValue());
1562 if (isa<InlineAsm>(Callee))
1565 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1567 // If the value of the invoke is used outside of its defining block, make it
1568 // available as a virtual register.
1569 if (!I.use_empty()) {
1570 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1571 if (VMI != FuncInfo.ValueMap.end())
1572 CopyValueToVirtualRegister(&I, VMI->second);
1575 // Update successor info
1576 CurMBB->addSuccessor(Return);
1577 CurMBB->addSuccessor(LandingPad);
1579 // Drop into normal successor.
1580 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1581 MVT::Other, getControlRoot(),
1582 DAG.getBasicBlock(Return)));
1585 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1588 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1589 /// small case ranges).
1590 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1591 CaseRecVector& WorkList,
1593 MachineBasicBlock* Default) {
1594 Case& BackCase = *(CR.Range.second-1);
1596 // Size is the number of Cases represented by this range.
1597 size_t Size = CR.Range.second - CR.Range.first;
1601 // Get the MachineFunction which holds the current MBB. This is used when
1602 // inserting any additional MBBs necessary to represent the switch.
1603 MachineFunction *CurMF = CurMBB->getParent();
1605 // Figure out which block is immediately after the current one.
1606 MachineBasicBlock *NextBlock = 0;
1607 MachineFunction::iterator BBI = CR.CaseBB;
1609 if (++BBI != CurMBB->getParent()->end())
1612 // TODO: If any two of the cases has the same destination, and if one value
1613 // is the same as the other, but has one bit unset that the other has set,
1614 // use bit manipulation to do two compares at once. For example:
1615 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1617 // Rearrange the case blocks so that the last one falls through if possible.
1618 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1619 // The last case block won't fall through into 'NextBlock' if we emit the
1620 // branches in this order. See if rearranging a case value would help.
1621 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1622 if (I->BB == NextBlock) {
1623 std::swap(*I, BackCase);
1629 // Create a CaseBlock record representing a conditional branch to
1630 // the Case's target mbb if the value being switched on SV is equal
1632 MachineBasicBlock *CurBlock = CR.CaseBB;
1633 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1634 MachineBasicBlock *FallThrough;
1636 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1637 CurMF->insert(BBI, FallThrough);
1639 // If the last case doesn't match, go to the default block.
1640 FallThrough = Default;
1643 Value *RHS, *LHS, *MHS;
1645 if (I->High == I->Low) {
1646 // This is just small small case range :) containing exactly 1 case
1648 LHS = SV; RHS = I->High; MHS = NULL;
1651 LHS = I->Low; MHS = SV; RHS = I->High;
1653 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1655 // If emitting the first comparison, just call visitSwitchCase to emit the
1656 // code into the current block. Otherwise, push the CaseBlock onto the
1657 // vector to be later processed by SDISel, and insert the node's MBB
1658 // before the next MBB.
1659 if (CurBlock == CurMBB)
1660 visitSwitchCase(CB);
1662 SwitchCases.push_back(CB);
1664 CurBlock = FallThrough;
1670 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1671 return !DisableJumpTables &&
1672 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1673 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1676 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1677 APInt LastExt(Last), FirstExt(First);
1678 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1679 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1680 return (LastExt - FirstExt + 1ULL);
1683 /// handleJTSwitchCase - Emit jumptable for current switch case range
1684 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1685 CaseRecVector& WorkList,
1687 MachineBasicBlock* Default) {
1688 Case& FrontCase = *CR.Range.first;
1689 Case& BackCase = *(CR.Range.second-1);
1691 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1692 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1695 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1699 if (!areJTsAllowed(TLI) || TSize <= 3)
1702 APInt Range = ComputeRange(First, Last);
1703 double Density = (double)TSize / Range.roundToDouble();
1707 DEBUG(errs() << "Lowering jump table\n"
1708 << "First entry: " << First << ". Last entry: " << Last << '\n'
1709 << "Range: " << Range
1710 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1712 // Get the MachineFunction which holds the current MBB. This is used when
1713 // inserting any additional MBBs necessary to represent the switch.
1714 MachineFunction *CurMF = CurMBB->getParent();
1716 // Figure out which block is immediately after the current one.
1717 MachineBasicBlock *NextBlock = 0;
1718 MachineFunction::iterator BBI = CR.CaseBB;
1720 if (++BBI != CurMBB->getParent()->end())
1723 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1725 // Create a new basic block to hold the code for loading the address
1726 // of the jump table, and jumping to it. Update successor information;
1727 // we will either branch to the default case for the switch, or the jump
1729 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1730 CurMF->insert(BBI, JumpTableBB);
1731 CR.CaseBB->addSuccessor(Default);
1732 CR.CaseBB->addSuccessor(JumpTableBB);
1734 // Build a vector of destination BBs, corresponding to each target
1735 // of the jump table. If the value of the jump table slot corresponds to
1736 // a case statement, push the case's BB onto the vector, otherwise, push
1738 std::vector<MachineBasicBlock*> DestBBs;
1740 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1741 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1742 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1744 if (Low.sle(TEI) && TEI.sle(High)) {
1745 DestBBs.push_back(I->BB);
1749 DestBBs.push_back(Default);
1753 // Update successor info. Add one edge to each unique successor.
1754 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1755 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1756 E = DestBBs.end(); I != E; ++I) {
1757 if (!SuccsHandled[(*I)->getNumber()]) {
1758 SuccsHandled[(*I)->getNumber()] = true;
1759 JumpTableBB->addSuccessor(*I);
1763 // Create a jump table index for this jump table, or return an existing
1765 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1767 // Set the jump table information so that we can codegen it as a second
1768 // MachineBasicBlock
1769 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1770 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1771 if (CR.CaseBB == CurMBB)
1772 visitJumpTableHeader(JT, JTH);
1774 JTCases.push_back(JumpTableBlock(JTH, JT));
1779 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1781 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1782 CaseRecVector& WorkList,
1784 MachineBasicBlock* Default) {
1785 // Get the MachineFunction which holds the current MBB. This is used when
1786 // inserting any additional MBBs necessary to represent the switch.
1787 MachineFunction *CurMF = CurMBB->getParent();
1789 // Figure out which block is immediately after the current one.
1790 MachineBasicBlock *NextBlock = 0;
1791 MachineFunction::iterator BBI = CR.CaseBB;
1793 if (++BBI != CurMBB->getParent()->end())
1796 Case& FrontCase = *CR.Range.first;
1797 Case& BackCase = *(CR.Range.second-1);
1798 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1800 // Size is the number of Cases represented by this range.
1801 unsigned Size = CR.Range.second - CR.Range.first;
1803 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1804 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1806 CaseItr Pivot = CR.Range.first + Size/2;
1808 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1809 // (heuristically) allow us to emit JumpTable's later.
1811 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1815 size_t LSize = FrontCase.size();
1816 size_t RSize = TSize-LSize;
1817 DEBUG(errs() << "Selecting best pivot: \n"
1818 << "First: " << First << ", Last: " << Last <<'\n'
1819 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1820 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1822 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1823 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1824 APInt Range = ComputeRange(LEnd, RBegin);
1825 assert((Range - 2ULL).isNonNegative() &&
1826 "Invalid case distance");
1827 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1828 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1829 double Metric = Range.logBase2()*(LDensity+RDensity);
1830 // Should always split in some non-trivial place
1831 DEBUG(errs() <<"=>Step\n"
1832 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1833 << "LDensity: " << LDensity
1834 << ", RDensity: " << RDensity << '\n'
1835 << "Metric: " << Metric << '\n');
1836 if (FMetric < Metric) {
1839 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1845 if (areJTsAllowed(TLI)) {
1846 // If our case is dense we *really* should handle it earlier!
1847 assert((FMetric > 0) && "Should handle dense range earlier!");
1849 Pivot = CR.Range.first + Size/2;
1852 CaseRange LHSR(CR.Range.first, Pivot);
1853 CaseRange RHSR(Pivot, CR.Range.second);
1854 Constant *C = Pivot->Low;
1855 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1857 // We know that we branch to the LHS if the Value being switched on is
1858 // less than the Pivot value, C. We use this to optimize our binary
1859 // tree a bit, by recognizing that if SV is greater than or equal to the
1860 // LHS's Case Value, and that Case Value is exactly one less than the
1861 // Pivot's Value, then we can branch directly to the LHS's Target,
1862 // rather than creating a leaf node for it.
1863 if ((LHSR.second - LHSR.first) == 1 &&
1864 LHSR.first->High == CR.GE &&
1865 cast<ConstantInt>(C)->getValue() ==
1866 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1867 TrueBB = LHSR.first->BB;
1869 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1870 CurMF->insert(BBI, TrueBB);
1871 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1874 // Similar to the optimization above, if the Value being switched on is
1875 // known to be less than the Constant CR.LT, and the current Case Value
1876 // is CR.LT - 1, then we can branch directly to the target block for
1877 // the current Case Value, rather than emitting a RHS leaf node for it.
1878 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1879 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1880 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1881 FalseBB = RHSR.first->BB;
1883 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1884 CurMF->insert(BBI, FalseBB);
1885 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1888 // Create a CaseBlock record representing a conditional branch to
1889 // the LHS node if the value being switched on SV is less than C.
1890 // Otherwise, branch to LHS.
1891 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1893 if (CR.CaseBB == CurMBB)
1894 visitSwitchCase(CB);
1896 SwitchCases.push_back(CB);
1901 /// handleBitTestsSwitchCase - if current case range has few destination and
1902 /// range span less, than machine word bitwidth, encode case range into series
1903 /// of masks and emit bit tests with these masks.
1904 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1905 CaseRecVector& WorkList,
1907 MachineBasicBlock* Default){
1908 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1910 Case& FrontCase = *CR.Range.first;
1911 Case& BackCase = *(CR.Range.second-1);
1913 // Get the MachineFunction which holds the current MBB. This is used when
1914 // inserting any additional MBBs necessary to represent the switch.
1915 MachineFunction *CurMF = CurMBB->getParent();
1918 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1920 // Single case counts one, case range - two.
1921 numCmps += (I->Low == I->High ? 1 : 2);
1924 // Count unique destinations
1925 SmallSet<MachineBasicBlock*, 4> Dests;
1926 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1927 Dests.insert(I->BB);
1928 if (Dests.size() > 3)
1929 // Don't bother the code below, if there are too much unique destinations
1932 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1933 << "Total number of comparisons: " << numCmps << '\n');
1935 // Compute span of values.
1936 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1937 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1938 APInt cmpRange = maxValue - minValue;
1940 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1941 << "Low bound: " << minValue << '\n'
1942 << "High bound: " << maxValue << '\n');
1944 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1945 (!(Dests.size() == 1 && numCmps >= 3) &&
1946 !(Dests.size() == 2 && numCmps >= 5) &&
1947 !(Dests.size() >= 3 && numCmps >= 6)))
1950 DEBUG(errs() << "Emitting bit tests\n");
1951 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1953 // Optimize the case where all the case values fit in a
1954 // word without having to subtract minValue. In this case,
1955 // we can optimize away the subtraction.
1956 if (minValue.isNonNegative() &&
1957 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1958 cmpRange = maxValue;
1960 lowBound = minValue;
1963 CaseBitsVector CasesBits;
1964 unsigned i, count = 0;
1966 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1967 MachineBasicBlock* Dest = I->BB;
1968 for (i = 0; i < count; ++i)
1969 if (Dest == CasesBits[i].BB)
1973 assert((count < 3) && "Too much destinations to test!");
1974 CasesBits.push_back(CaseBits(0, Dest, 0));
1978 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1979 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1981 uint64_t lo = (lowValue - lowBound).getZExtValue();
1982 uint64_t hi = (highValue - lowBound).getZExtValue();
1984 for (uint64_t j = lo; j <= hi; j++) {
1985 CasesBits[i].Mask |= 1ULL << j;
1986 CasesBits[i].Bits++;
1990 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1994 // Figure out which block is immediately after the current one.
1995 MachineFunction::iterator BBI = CR.CaseBB;
1998 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2000 DEBUG(errs() << "Cases:\n");
2001 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2002 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2003 << ", Bits: " << CasesBits[i].Bits
2004 << ", BB: " << CasesBits[i].BB << '\n');
2006 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2007 CurMF->insert(BBI, CaseBB);
2008 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2013 BitTestBlock BTB(lowBound, cmpRange, SV,
2014 -1U, (CR.CaseBB == CurMBB),
2015 CR.CaseBB, Default, BTC);
2017 if (CR.CaseBB == CurMBB)
2018 visitBitTestHeader(BTB);
2020 BitTestCases.push_back(BTB);
2026 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2027 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2028 const SwitchInst& SI) {
2031 // Start with "simple" cases
2032 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2033 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2034 Cases.push_back(Case(SI.getSuccessorValue(i),
2035 SI.getSuccessorValue(i),
2038 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2040 // Merge case into clusters
2041 if (Cases.size() >= 2)
2042 // Must recompute end() each iteration because it may be
2043 // invalidated by erase if we hold on to it
2044 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2045 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2046 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2047 MachineBasicBlock* nextBB = J->BB;
2048 MachineBasicBlock* currentBB = I->BB;
2050 // If the two neighboring cases go to the same destination, merge them
2051 // into a single case.
2052 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2060 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2061 if (I->Low != I->High)
2062 // A range counts double, since it requires two compares.
2069 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2070 // Figure out which block is immediately after the current one.
2071 MachineBasicBlock *NextBlock = 0;
2072 MachineFunction::iterator BBI = CurMBB;
2074 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2076 // If there is only the default destination, branch to it if it is not the
2077 // next basic block. Otherwise, just fall through.
2078 if (SI.getNumOperands() == 2) {
2079 // Update machine-CFG edges.
2081 // If this is not a fall-through branch, emit the branch.
2082 CurMBB->addSuccessor(Default);
2083 if (Default != NextBlock)
2084 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2085 MVT::Other, getControlRoot(),
2086 DAG.getBasicBlock(Default)));
2090 // If there are any non-default case statements, create a vector of Cases
2091 // representing each one, and sort the vector so that we can efficiently
2092 // create a binary search tree from them.
2094 size_t numCmps = Clusterify(Cases, SI);
2095 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2096 << ". Total compares: " << numCmps << '\n');
2099 // Get the Value to be switched on and default basic blocks, which will be
2100 // inserted into CaseBlock records, representing basic blocks in the binary
2102 Value *SV = SI.getOperand(0);
2104 // Push the initial CaseRec onto the worklist
2105 CaseRecVector WorkList;
2106 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2108 while (!WorkList.empty()) {
2109 // Grab a record representing a case range to process off the worklist
2110 CaseRec CR = WorkList.back();
2111 WorkList.pop_back();
2113 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2116 // If the range has few cases (two or less) emit a series of specific
2118 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2121 // If the switch has more than 5 blocks, and at least 40% dense, and the
2122 // target supports indirect branches, then emit a jump table rather than
2123 // lowering the switch to a binary tree of conditional branches.
2124 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2127 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2128 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2129 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2134 void SelectionDAGLowering::visitSub(User &I) {
2135 // -0.0 - X --> fneg
2136 const Type *Ty = I.getType();
2137 if (isa<VectorType>(Ty)) {
2138 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2139 const VectorType *DestTy = cast<VectorType>(I.getType());
2140 const Type *ElTy = DestTy->getElementType();
2141 if (ElTy->isFloatingPoint()) {
2142 unsigned VL = DestTy->getNumElements();
2143 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2144 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2146 SDValue Op2 = getValue(I.getOperand(1));
2147 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2148 Op2.getValueType(), Op2));
2154 if (Ty->isFloatingPoint()) {
2155 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2156 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2157 SDValue Op2 = getValue(I.getOperand(1));
2158 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2159 Op2.getValueType(), Op2));
2164 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2167 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2168 SDValue Op1 = getValue(I.getOperand(0));
2169 SDValue Op2 = getValue(I.getOperand(1));
2171 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2172 Op1.getValueType(), Op1, Op2));
2175 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2176 SDValue Op1 = getValue(I.getOperand(0));
2177 SDValue Op2 = getValue(I.getOperand(1));
2178 if (!isa<VectorType>(I.getType())) {
2179 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2180 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2181 TLI.getPointerTy(), Op2);
2182 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2183 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2184 TLI.getPointerTy(), Op2);
2187 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2188 Op1.getValueType(), Op1, Op2));
2191 void SelectionDAGLowering::visitICmp(User &I) {
2192 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2193 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2194 predicate = IC->getPredicate();
2195 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2196 predicate = ICmpInst::Predicate(IC->getPredicate());
2197 SDValue Op1 = getValue(I.getOperand(0));
2198 SDValue Op2 = getValue(I.getOperand(1));
2199 ISD::CondCode Opcode = getICmpCondCode(predicate);
2200 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2203 void SelectionDAGLowering::visitFCmp(User &I) {
2204 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2205 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2206 predicate = FC->getPredicate();
2207 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2208 predicate = FCmpInst::Predicate(FC->getPredicate());
2209 SDValue Op1 = getValue(I.getOperand(0));
2210 SDValue Op2 = getValue(I.getOperand(1));
2211 ISD::CondCode Condition = getFCmpCondCode(predicate);
2212 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2215 void SelectionDAGLowering::visitVICmp(User &I) {
2216 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2217 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2218 predicate = IC->getPredicate();
2219 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2220 predicate = ICmpInst::Predicate(IC->getPredicate());
2221 SDValue Op1 = getValue(I.getOperand(0));
2222 SDValue Op2 = getValue(I.getOperand(1));
2223 ISD::CondCode Opcode = getICmpCondCode(predicate);
2224 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2228 void SelectionDAGLowering::visitVFCmp(User &I) {
2229 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2230 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2231 predicate = FC->getPredicate();
2232 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2233 predicate = FCmpInst::Predicate(FC->getPredicate());
2234 SDValue Op1 = getValue(I.getOperand(0));
2235 SDValue Op2 = getValue(I.getOperand(1));
2236 ISD::CondCode Condition = getFCmpCondCode(predicate);
2237 MVT DestVT = TLI.getValueType(I.getType());
2239 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2242 void SelectionDAGLowering::visitSelect(User &I) {
2243 SmallVector<MVT, 4> ValueVTs;
2244 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2245 unsigned NumValues = ValueVTs.size();
2246 if (NumValues != 0) {
2247 SmallVector<SDValue, 4> Values(NumValues);
2248 SDValue Cond = getValue(I.getOperand(0));
2249 SDValue TrueVal = getValue(I.getOperand(1));
2250 SDValue FalseVal = getValue(I.getOperand(2));
2252 for (unsigned i = 0; i != NumValues; ++i)
2253 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2254 TrueVal.getValueType(), Cond,
2255 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2256 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2258 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2259 DAG.getVTList(&ValueVTs[0], NumValues),
2260 &Values[0], NumValues));
2265 void SelectionDAGLowering::visitTrunc(User &I) {
2266 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2267 SDValue N = getValue(I.getOperand(0));
2268 MVT DestVT = TLI.getValueType(I.getType());
2269 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2272 void SelectionDAGLowering::visitZExt(User &I) {
2273 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2274 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2275 SDValue N = getValue(I.getOperand(0));
2276 MVT DestVT = TLI.getValueType(I.getType());
2277 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2280 void SelectionDAGLowering::visitSExt(User &I) {
2281 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2282 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2283 SDValue N = getValue(I.getOperand(0));
2284 MVT DestVT = TLI.getValueType(I.getType());
2285 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2288 void SelectionDAGLowering::visitFPTrunc(User &I) {
2289 // FPTrunc is never a no-op cast, no need to check
2290 SDValue N = getValue(I.getOperand(0));
2291 MVT DestVT = TLI.getValueType(I.getType());
2292 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2293 DestVT, N, DAG.getIntPtrConstant(0)));
2296 void SelectionDAGLowering::visitFPExt(User &I){
2297 // FPTrunc is never a no-op cast, no need to check
2298 SDValue N = getValue(I.getOperand(0));
2299 MVT DestVT = TLI.getValueType(I.getType());
2300 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2303 void SelectionDAGLowering::visitFPToUI(User &I) {
2304 // FPToUI is never a no-op cast, no need to check
2305 SDValue N = getValue(I.getOperand(0));
2306 MVT DestVT = TLI.getValueType(I.getType());
2307 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2310 void SelectionDAGLowering::visitFPToSI(User &I) {
2311 // FPToSI is never a no-op cast, no need to check
2312 SDValue N = getValue(I.getOperand(0));
2313 MVT DestVT = TLI.getValueType(I.getType());
2314 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2317 void SelectionDAGLowering::visitUIToFP(User &I) {
2318 // UIToFP is never a no-op cast, no need to check
2319 SDValue N = getValue(I.getOperand(0));
2320 MVT DestVT = TLI.getValueType(I.getType());
2321 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2324 void SelectionDAGLowering::visitSIToFP(User &I){
2325 // SIToFP is never a no-op cast, no need to check
2326 SDValue N = getValue(I.getOperand(0));
2327 MVT DestVT = TLI.getValueType(I.getType());
2328 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2331 void SelectionDAGLowering::visitPtrToInt(User &I) {
2332 // What to do depends on the size of the integer and the size of the pointer.
2333 // We can either truncate, zero extend, or no-op, accordingly.
2334 SDValue N = getValue(I.getOperand(0));
2335 MVT SrcVT = N.getValueType();
2336 MVT DestVT = TLI.getValueType(I.getType());
2338 if (DestVT.bitsLT(SrcVT))
2339 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2341 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2342 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2343 setValue(&I, Result);
2346 void SelectionDAGLowering::visitIntToPtr(User &I) {
2347 // What to do depends on the size of the integer and the size of the pointer.
2348 // We can either truncate, zero extend, or no-op, accordingly.
2349 SDValue N = getValue(I.getOperand(0));
2350 MVT SrcVT = N.getValueType();
2351 MVT DestVT = TLI.getValueType(I.getType());
2352 if (DestVT.bitsLT(SrcVT))
2353 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2355 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2356 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2360 void SelectionDAGLowering::visitBitCast(User &I) {
2361 SDValue N = getValue(I.getOperand(0));
2362 MVT DestVT = TLI.getValueType(I.getType());
2364 // BitCast assures us that source and destination are the same size so this
2365 // is either a BIT_CONVERT or a no-op.
2366 if (DestVT != N.getValueType())
2367 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2368 DestVT, N)); // convert types
2370 setValue(&I, N); // noop cast.
2373 void SelectionDAGLowering::visitInsertElement(User &I) {
2374 SDValue InVec = getValue(I.getOperand(0));
2375 SDValue InVal = getValue(I.getOperand(1));
2376 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2378 getValue(I.getOperand(2)));
2380 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2381 TLI.getValueType(I.getType()),
2382 InVec, InVal, InIdx));
2385 void SelectionDAGLowering::visitExtractElement(User &I) {
2386 SDValue InVec = getValue(I.getOperand(0));
2387 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2389 getValue(I.getOperand(1)));
2390 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2391 TLI.getValueType(I.getType()), InVec, InIdx));
2395 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2396 // from SIndx and increasing to the element length (undefs are allowed).
2397 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2398 unsigned MaskNumElts = Mask.getNumOperands();
2399 for (unsigned i = 0; i != MaskNumElts; ++i) {
2400 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2401 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2402 if (Idx != i + SIndx)
2409 void SelectionDAGLowering::visitShuffleVector(User &I) {
2410 SDValue Src1 = getValue(I.getOperand(0));
2411 SDValue Src2 = getValue(I.getOperand(1));
2412 SDValue Mask = getValue(I.getOperand(2));
2414 MVT VT = TLI.getValueType(I.getType());
2415 MVT SrcVT = Src1.getValueType();
2416 int MaskNumElts = Mask.getNumOperands();
2417 int SrcNumElts = SrcVT.getVectorNumElements();
2419 if (SrcNumElts == MaskNumElts) {
2420 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2421 VT, Src1, Src2, Mask));
2425 // Normalize the shuffle vector since mask and vector length don't match.
2426 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2428 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2429 // Mask is longer than the source vectors and is a multiple of the source
2430 // vectors. We can use concatenate vector to make the mask and vectors
2432 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2433 // The shuffle is concatenating two vectors together.
2434 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2439 // Pad both vectors with undefs to make them the same length as the mask.
2440 unsigned NumConcat = MaskNumElts / SrcNumElts;
2441 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2443 SDValue* MOps1 = new SDValue[NumConcat];
2444 SDValue* MOps2 = new SDValue[NumConcat];
2447 for (unsigned i = 1; i != NumConcat; ++i) {
2448 MOps1[i] = UndefVal;
2449 MOps2[i] = UndefVal;
2451 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2452 VT, MOps1, NumConcat);
2453 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2454 VT, MOps2, NumConcat);
2459 // Readjust mask for new input vector length.
2460 SmallVector<SDValue, 8> MappedOps;
2461 for (int i = 0; i != MaskNumElts; ++i) {
2462 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2463 MappedOps.push_back(Mask.getOperand(i));
2465 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2466 if (Idx < SrcNumElts)
2467 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2469 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2473 Mask = DAG.getBUILD_VECTOR(Mask.getValueType(), getCurDebugLoc(),
2474 &MappedOps[0], MappedOps.size());
2476 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2477 VT, Src1, Src2, Mask));
2481 if (SrcNumElts > MaskNumElts) {
2482 // Resulting vector is shorter than the incoming vector.
2483 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2484 // Shuffle extracts 1st vector.
2489 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2490 // Shuffle extracts 2nd vector.
2495 // Analyze the access pattern of the vector to see if we can extract
2496 // two subvectors and do the shuffle. The analysis is done by calculating
2497 // the range of elements the mask access on both vectors.
2498 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2499 int MaxRange[2] = {-1, -1};
2501 for (int i = 0; i != MaskNumElts; ++i) {
2502 SDValue Arg = Mask.getOperand(i);
2503 if (Arg.getOpcode() != ISD::UNDEF) {
2504 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2505 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2507 if (Idx >= SrcNumElts) {
2511 if (Idx > MaxRange[Input])
2512 MaxRange[Input] = Idx;
2513 if (Idx < MinRange[Input])
2514 MinRange[Input] = Idx;
2518 // Check if the access is smaller than the vector size and can we find
2519 // a reasonable extract index.
2520 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2521 int StartIdx[2]; // StartIdx to extract from
2522 for (int Input=0; Input < 2; ++Input) {
2523 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2524 RangeUse[Input] = 0; // Unused
2525 StartIdx[Input] = 0;
2526 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2527 // Fits within range but we should see if we can find a good
2528 // start index that is a multiple of the mask length.
2529 if (MaxRange[Input] < MaskNumElts) {
2530 RangeUse[Input] = 1; // Extract from beginning of the vector
2531 StartIdx[Input] = 0;
2533 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2534 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2535 StartIdx[Input] + MaskNumElts < SrcNumElts)
2536 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2541 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2542 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2545 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2546 // Extract appropriate subvector and generate a vector shuffle
2547 for (int Input=0; Input < 2; ++Input) {
2548 SDValue& Src = Input == 0 ? Src1 : Src2;
2549 if (RangeUse[Input] == 0) {
2550 Src = DAG.getUNDEF(VT);
2552 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2553 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2556 // Calculate new mask.
2557 SmallVector<SDValue, 8> MappedOps;
2558 for (int i = 0; i != MaskNumElts; ++i) {
2559 SDValue Arg = Mask.getOperand(i);
2560 if (Arg.getOpcode() == ISD::UNDEF) {
2561 MappedOps.push_back(Arg);
2563 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2564 if (Idx < SrcNumElts)
2565 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2567 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2568 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2572 Mask = DAG.getBUILD_VECTOR(Mask.getValueType(), getCurDebugLoc(),
2573 &MappedOps[0], MappedOps.size());
2574 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2575 VT, Src1, Src2, Mask));
2580 // We can't use either concat vectors or extract subvectors so fall back to
2581 // replacing the shuffle with extract and build vector.
2582 // to insert and build vector.
2583 MVT EltVT = VT.getVectorElementType();
2584 MVT PtrVT = TLI.getPointerTy();
2585 SmallVector<SDValue,8> Ops;
2586 for (int i = 0; i != MaskNumElts; ++i) {
2587 SDValue Arg = Mask.getOperand(i);
2588 if (Arg.getOpcode() == ISD::UNDEF) {
2589 Ops.push_back(DAG.getUNDEF(EltVT));
2591 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2592 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2593 if (Idx < SrcNumElts)
2594 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2595 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2597 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2599 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2602 setValue(&I, DAG.getBUILD_VECTOR(VT, getCurDebugLoc(), &Ops[0], Ops.size()));
2605 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2606 const Value *Op0 = I.getOperand(0);
2607 const Value *Op1 = I.getOperand(1);
2608 const Type *AggTy = I.getType();
2609 const Type *ValTy = Op1->getType();
2610 bool IntoUndef = isa<UndefValue>(Op0);
2611 bool FromUndef = isa<UndefValue>(Op1);
2613 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2614 I.idx_begin(), I.idx_end());
2616 SmallVector<MVT, 4> AggValueVTs;
2617 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2618 SmallVector<MVT, 4> ValValueVTs;
2619 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2621 unsigned NumAggValues = AggValueVTs.size();
2622 unsigned NumValValues = ValValueVTs.size();
2623 SmallVector<SDValue, 4> Values(NumAggValues);
2625 SDValue Agg = getValue(Op0);
2626 SDValue Val = getValue(Op1);
2628 // Copy the beginning value(s) from the original aggregate.
2629 for (; i != LinearIndex; ++i)
2630 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2631 SDValue(Agg.getNode(), Agg.getResNo() + i);
2632 // Copy values from the inserted value(s).
2633 for (; i != LinearIndex + NumValValues; ++i)
2634 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2635 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2636 // Copy remaining value(s) from the original aggregate.
2637 for (; i != NumAggValues; ++i)
2638 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2639 SDValue(Agg.getNode(), Agg.getResNo() + i);
2641 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2642 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2643 &Values[0], NumAggValues));
2646 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2647 const Value *Op0 = I.getOperand(0);
2648 const Type *AggTy = Op0->getType();
2649 const Type *ValTy = I.getType();
2650 bool OutOfUndef = isa<UndefValue>(Op0);
2652 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2653 I.idx_begin(), I.idx_end());
2655 SmallVector<MVT, 4> ValValueVTs;
2656 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2658 unsigned NumValValues = ValValueVTs.size();
2659 SmallVector<SDValue, 4> Values(NumValValues);
2661 SDValue Agg = getValue(Op0);
2662 // Copy out the selected value(s).
2663 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2664 Values[i - LinearIndex] =
2666 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2667 SDValue(Agg.getNode(), Agg.getResNo() + i);
2669 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2670 DAG.getVTList(&ValValueVTs[0], NumValValues),
2671 &Values[0], NumValValues));
2675 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2676 SDValue N = getValue(I.getOperand(0));
2677 const Type *Ty = I.getOperand(0)->getType();
2679 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2682 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2683 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2686 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2687 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2688 DAG.getIntPtrConstant(Offset));
2690 Ty = StTy->getElementType(Field);
2692 Ty = cast<SequentialType>(Ty)->getElementType();
2694 // If this is a constant subscript, handle it quickly.
2695 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2696 if (CI->getZExtValue() == 0) continue;
2698 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2700 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2702 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2704 DAG.getConstant(Offs, MVT::i64));
2706 OffsVal = DAG.getIntPtrConstant(Offs);
2707 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2712 // N = N + Idx * ElementSize;
2713 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2714 SDValue IdxN = getValue(Idx);
2716 // If the index is smaller or larger than intptr_t, truncate or extend
2718 if (IdxN.getValueType().bitsLT(N.getValueType()))
2719 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2720 N.getValueType(), IdxN);
2721 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2722 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2723 N.getValueType(), IdxN);
2725 // If this is a multiply by a power of two, turn it into a shl
2726 // immediately. This is a very common case.
2727 if (ElementSize != 1) {
2728 if (isPowerOf2_64(ElementSize)) {
2729 unsigned Amt = Log2_64(ElementSize);
2730 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2731 N.getValueType(), IdxN,
2732 DAG.getConstant(Amt, TLI.getPointerTy()));
2734 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2735 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2736 N.getValueType(), IdxN, Scale);
2740 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2741 N.getValueType(), N, IdxN);
2747 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2748 // If this is a fixed sized alloca in the entry block of the function,
2749 // allocate it statically on the stack.
2750 if (FuncInfo.StaticAllocaMap.count(&I))
2751 return; // getValue will auto-populate this.
2753 const Type *Ty = I.getAllocatedType();
2754 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2756 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2759 SDValue AllocSize = getValue(I.getArraySize());
2760 MVT IntPtr = TLI.getPointerTy();
2761 if (IntPtr.bitsLT(AllocSize.getValueType()))
2762 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2764 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2765 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2768 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
2769 DAG.getIntPtrConstant(TySize));
2771 // Handle alignment. If the requested alignment is less than or equal to
2772 // the stack alignment, ignore it. If the size is greater than or equal to
2773 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2774 unsigned StackAlign =
2775 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2776 if (Align <= StackAlign)
2779 // Round the size of the allocation up to the stack alignment size
2780 // by add SA-1 to the size.
2781 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2782 AllocSize.getValueType(), AllocSize,
2783 DAG.getIntPtrConstant(StackAlign-1));
2784 // Mask out the low bits for alignment purposes.
2785 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2786 AllocSize.getValueType(), AllocSize,
2787 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2789 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2790 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2792 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2795 DAG.setRoot(DSA.getValue(1));
2797 // Inform the Frame Information that we have just allocated a variable-sized
2799 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2802 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2803 const Value *SV = I.getOperand(0);
2804 SDValue Ptr = getValue(SV);
2806 const Type *Ty = I.getType();
2807 bool isVolatile = I.isVolatile();
2808 unsigned Alignment = I.getAlignment();
2810 SmallVector<MVT, 4> ValueVTs;
2811 SmallVector<uint64_t, 4> Offsets;
2812 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2813 unsigned NumValues = ValueVTs.size();
2818 bool ConstantMemory = false;
2820 // Serialize volatile loads with other side effects.
2822 else if (AA->pointsToConstantMemory(SV)) {
2823 // Do not serialize (non-volatile) loads of constant memory with anything.
2824 Root = DAG.getEntryNode();
2825 ConstantMemory = true;
2827 // Do not serialize non-volatile loads against each other.
2828 Root = DAG.getRoot();
2831 SmallVector<SDValue, 4> Values(NumValues);
2832 SmallVector<SDValue, 4> Chains(NumValues);
2833 MVT PtrVT = Ptr.getValueType();
2834 for (unsigned i = 0; i != NumValues; ++i) {
2835 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2836 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2838 DAG.getConstant(Offsets[i], PtrVT)),
2840 isVolatile, Alignment);
2842 Chains[i] = L.getValue(1);
2845 if (!ConstantMemory) {
2846 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2848 &Chains[0], NumValues);
2852 PendingLoads.push_back(Chain);
2855 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2856 DAG.getVTList(&ValueVTs[0], NumValues),
2857 &Values[0], NumValues));
2861 void SelectionDAGLowering::visitStore(StoreInst &I) {
2862 Value *SrcV = I.getOperand(0);
2863 Value *PtrV = I.getOperand(1);
2865 SmallVector<MVT, 4> ValueVTs;
2866 SmallVector<uint64_t, 4> Offsets;
2867 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2868 unsigned NumValues = ValueVTs.size();
2872 // Get the lowered operands. Note that we do this after
2873 // checking if NumResults is zero, because with zero results
2874 // the operands won't have values in the map.
2875 SDValue Src = getValue(SrcV);
2876 SDValue Ptr = getValue(PtrV);
2878 SDValue Root = getRoot();
2879 SmallVector<SDValue, 4> Chains(NumValues);
2880 MVT PtrVT = Ptr.getValueType();
2881 bool isVolatile = I.isVolatile();
2882 unsigned Alignment = I.getAlignment();
2883 for (unsigned i = 0; i != NumValues; ++i)
2884 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2885 SDValue(Src.getNode(), Src.getResNo() + i),
2886 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2888 DAG.getConstant(Offsets[i], PtrVT)),
2890 isVolatile, Alignment);
2892 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2893 MVT::Other, &Chains[0], NumValues));
2896 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2898 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2899 unsigned Intrinsic) {
2900 bool HasChain = !I.doesNotAccessMemory();
2901 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2903 // Build the operand list.
2904 SmallVector<SDValue, 8> Ops;
2905 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2907 // We don't need to serialize loads against other loads.
2908 Ops.push_back(DAG.getRoot());
2910 Ops.push_back(getRoot());
2914 // Info is set by getTgtMemInstrinsic
2915 TargetLowering::IntrinsicInfo Info;
2916 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2918 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2919 if (!IsTgtIntrinsic)
2920 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2922 // Add all operands of the call to the operand list.
2923 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2924 SDValue Op = getValue(I.getOperand(i));
2925 assert(TLI.isTypeLegal(Op.getValueType()) &&
2926 "Intrinsic uses a non-legal type?");
2930 std::vector<MVT> VTs;
2931 if (I.getType() != Type::VoidTy) {
2932 MVT VT = TLI.getValueType(I.getType());
2933 if (VT.isVector()) {
2934 const VectorType *DestTy = cast<VectorType>(I.getType());
2935 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2937 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2938 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2941 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2945 VTs.push_back(MVT::Other);
2947 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2951 if (IsTgtIntrinsic) {
2952 // This is target intrinsic that touches memory
2953 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2955 &Ops[0], Ops.size(),
2956 Info.memVT, Info.ptrVal, Info.offset,
2957 Info.align, Info.vol,
2958 Info.readMem, Info.writeMem);
2961 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2963 &Ops[0], Ops.size());
2964 else if (I.getType() != Type::VoidTy)
2965 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2967 &Ops[0], Ops.size());
2969 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2971 &Ops[0], Ops.size());
2974 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2976 PendingLoads.push_back(Chain);
2980 if (I.getType() != Type::VoidTy) {
2981 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2982 MVT VT = TLI.getValueType(PTy);
2983 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2985 setValue(&I, Result);
2989 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2990 static GlobalVariable *ExtractTypeInfo(Value *V) {
2991 V = V->stripPointerCasts();
2992 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2993 assert ((GV || isa<ConstantPointerNull>(V)) &&
2994 "TypeInfo must be a global variable or NULL");
3000 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3001 /// call, and add them to the specified machine basic block.
3002 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3003 MachineBasicBlock *MBB) {
3004 // Inform the MachineModuleInfo of the personality for this landing pad.
3005 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3006 assert(CE->getOpcode() == Instruction::BitCast &&
3007 isa<Function>(CE->getOperand(0)) &&
3008 "Personality should be a function");
3009 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3011 // Gather all the type infos for this landing pad and pass them along to
3012 // MachineModuleInfo.
3013 std::vector<GlobalVariable *> TyInfo;
3014 unsigned N = I.getNumOperands();
3016 for (unsigned i = N - 1; i > 2; --i) {
3017 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3018 unsigned FilterLength = CI->getZExtValue();
3019 unsigned FirstCatch = i + FilterLength + !FilterLength;
3020 assert (FirstCatch <= N && "Invalid filter length");
3022 if (FirstCatch < N) {
3023 TyInfo.reserve(N - FirstCatch);
3024 for (unsigned j = FirstCatch; j < N; ++j)
3025 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3026 MMI->addCatchTypeInfo(MBB, TyInfo);
3030 if (!FilterLength) {
3032 MMI->addCleanup(MBB);
3035 TyInfo.reserve(FilterLength - 1);
3036 for (unsigned j = i + 1; j < FirstCatch; ++j)
3037 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3038 MMI->addFilterTypeInfo(MBB, TyInfo);
3047 TyInfo.reserve(N - 3);
3048 for (unsigned j = 3; j < N; ++j)
3049 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3050 MMI->addCatchTypeInfo(MBB, TyInfo);
3056 /// GetSignificand - Get the significand and build it into a floating-point
3057 /// number with exponent of 1:
3059 /// Op = (Op & 0x007fffff) | 0x3f800000;
3061 /// where Op is the hexidecimal representation of floating point value.
3063 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3064 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3065 DAG.getConstant(0x007fffff, MVT::i32));
3066 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3067 DAG.getConstant(0x3f800000, MVT::i32));
3068 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3071 /// GetExponent - Get the exponent:
3073 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3075 /// where Op is the hexidecimal representation of floating point value.
3077 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3079 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3080 DAG.getConstant(0x7f800000, MVT::i32));
3081 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3082 DAG.getConstant(23, TLI.getPointerTy()));
3083 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3084 DAG.getConstant(127, MVT::i32));
3085 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3088 /// getF32Constant - Get 32-bit floating point constant.
3090 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3091 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3094 /// Inlined utility function to implement binary input atomic intrinsics for
3095 /// visitIntrinsicCall: I is a call instruction
3096 /// Op is the associated NodeType for I
3098 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3099 SDValue Root = getRoot();
3101 DAG.getAtomic(Op, getCurDebugLoc(),
3102 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3104 getValue(I.getOperand(1)),
3105 getValue(I.getOperand(2)),
3108 DAG.setRoot(L.getValue(1));
3112 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3114 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3115 SDValue Op1 = getValue(I.getOperand(1));
3116 SDValue Op2 = getValue(I.getOperand(2));
3118 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3119 SDValue Ops[] = { Op1, Op2 };
3121 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
3122 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
3124 setValue(&I, Result);
3128 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3129 /// limited-precision mode.
3131 SelectionDAGLowering::visitExp(CallInst &I) {
3133 DebugLoc dl = getCurDebugLoc();
3135 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3136 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3137 SDValue Op = getValue(I.getOperand(1));
3139 // Put the exponent in the right bit position for later addition to the
3142 // #define LOG2OFe 1.4426950f
3143 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3144 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3145 getF32Constant(DAG, 0x3fb8aa3b));
3146 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3148 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3149 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3150 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3152 // IntegerPartOfX <<= 23;
3153 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3154 DAG.getConstant(23, TLI.getPointerTy()));
3156 if (LimitFloatPrecision <= 6) {
3157 // For floating-point precision of 6:
3159 // TwoToFractionalPartOfX =
3161 // (0.735607626f + 0.252464424f * x) * x;
3163 // error 0.0144103317, which is 6 bits
3164 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3165 getF32Constant(DAG, 0x3e814304));
3166 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3167 getF32Constant(DAG, 0x3f3c50c8));
3168 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3169 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3170 getF32Constant(DAG, 0x3f7f5e7e));
3171 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3173 // Add the exponent into the result in integer domain.
3174 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3175 TwoToFracPartOfX, IntegerPartOfX);
3177 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3178 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3179 // For floating-point precision of 12:
3181 // TwoToFractionalPartOfX =
3184 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3186 // 0.000107046256 error, which is 13 to 14 bits
3187 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3188 getF32Constant(DAG, 0x3da235e3));
3189 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3190 getF32Constant(DAG, 0x3e65b8f3));
3191 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3192 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3193 getF32Constant(DAG, 0x3f324b07));
3194 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3195 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3196 getF32Constant(DAG, 0x3f7ff8fd));
3197 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3199 // Add the exponent into the result in integer domain.
3200 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3201 TwoToFracPartOfX, IntegerPartOfX);
3203 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3204 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3205 // For floating-point precision of 18:
3207 // TwoToFractionalPartOfX =
3211 // (0.554906021e-1f +
3212 // (0.961591928e-2f +
3213 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3215 // error 2.47208000*10^(-7), which is better than 18 bits
3216 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3217 getF32Constant(DAG, 0x3924b03e));
3218 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3219 getF32Constant(DAG, 0x3ab24b87));
3220 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3221 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3222 getF32Constant(DAG, 0x3c1d8c17));
3223 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3224 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3225 getF32Constant(DAG, 0x3d634a1d));
3226 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3227 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3228 getF32Constant(DAG, 0x3e75fe14));
3229 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3230 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3231 getF32Constant(DAG, 0x3f317234));
3232 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3233 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3234 getF32Constant(DAG, 0x3f800000));
3235 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3238 // Add the exponent into the result in integer domain.
3239 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3240 TwoToFracPartOfX, IntegerPartOfX);
3242 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3245 // No special expansion.
3246 result = DAG.getNode(ISD::FEXP, dl,
3247 getValue(I.getOperand(1)).getValueType(),
3248 getValue(I.getOperand(1)));
3251 setValue(&I, result);
3254 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3255 /// limited-precision mode.
3257 SelectionDAGLowering::visitLog(CallInst &I) {
3259 DebugLoc dl = getCurDebugLoc();
3261 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3262 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3263 SDValue Op = getValue(I.getOperand(1));
3264 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3266 // Scale the exponent by log(2) [0.69314718f].
3267 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3268 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3269 getF32Constant(DAG, 0x3f317218));
3271 // Get the significand and build it into a floating-point number with
3273 SDValue X = GetSignificand(DAG, Op1, dl);
3275 if (LimitFloatPrecision <= 6) {
3276 // For floating-point precision of 6:
3280 // (1.4034025f - 0.23903021f * x) * x;
3282 // error 0.0034276066, which is better than 8 bits
3283 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3284 getF32Constant(DAG, 0xbe74c456));
3285 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3286 getF32Constant(DAG, 0x3fb3a2b1));
3287 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3288 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3289 getF32Constant(DAG, 0x3f949a29));
3291 result = DAG.getNode(ISD::FADD, dl,
3292 MVT::f32, LogOfExponent, LogOfMantissa);
3293 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3294 // For floating-point precision of 12:
3300 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3302 // error 0.000061011436, which is 14 bits
3303 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3304 getF32Constant(DAG, 0xbd67b6d6));
3305 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3306 getF32Constant(DAG, 0x3ee4f4b8));
3307 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3308 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3309 getF32Constant(DAG, 0x3fbc278b));
3310 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3311 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3312 getF32Constant(DAG, 0x40348e95));
3313 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3314 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3315 getF32Constant(DAG, 0x3fdef31a));
3317 result = DAG.getNode(ISD::FADD, dl,
3318 MVT::f32, LogOfExponent, LogOfMantissa);
3319 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3320 // For floating-point precision of 18:
3328 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3330 // error 0.0000023660568, which is better than 18 bits
3331 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3332 getF32Constant(DAG, 0xbc91e5ac));
3333 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3334 getF32Constant(DAG, 0x3e4350aa));
3335 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3336 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3337 getF32Constant(DAG, 0x3f60d3e3));
3338 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3339 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3340 getF32Constant(DAG, 0x4011cdf0));
3341 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3342 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3343 getF32Constant(DAG, 0x406cfd1c));
3344 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3345 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3346 getF32Constant(DAG, 0x408797cb));
3347 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3348 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3349 getF32Constant(DAG, 0x4006dcab));
3351 result = DAG.getNode(ISD::FADD, dl,
3352 MVT::f32, LogOfExponent, LogOfMantissa);
3355 // No special expansion.
3356 result = DAG.getNode(ISD::FLOG, dl,
3357 getValue(I.getOperand(1)).getValueType(),
3358 getValue(I.getOperand(1)));
3361 setValue(&I, result);
3364 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3365 /// limited-precision mode.
3367 SelectionDAGLowering::visitLog2(CallInst &I) {
3369 DebugLoc dl = getCurDebugLoc();
3371 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3372 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3373 SDValue Op = getValue(I.getOperand(1));
3374 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3376 // Get the exponent.
3377 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3379 // Get the significand and build it into a floating-point number with
3381 SDValue X = GetSignificand(DAG, Op1, dl);
3383 // Different possible minimax approximations of significand in
3384 // floating-point for various degrees of accuracy over [1,2].
3385 if (LimitFloatPrecision <= 6) {
3386 // For floating-point precision of 6:
3388 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3390 // error 0.0049451742, which is more than 7 bits
3391 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3392 getF32Constant(DAG, 0xbeb08fe0));
3393 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3394 getF32Constant(DAG, 0x40019463));
3395 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3396 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3397 getF32Constant(DAG, 0x3fd6633d));
3399 result = DAG.getNode(ISD::FADD, dl,
3400 MVT::f32, LogOfExponent, Log2ofMantissa);
3401 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3402 // For floating-point precision of 12:
3408 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3410 // error 0.0000876136000, which is better than 13 bits
3411 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3412 getF32Constant(DAG, 0xbda7262e));
3413 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3414 getF32Constant(DAG, 0x3f25280b));
3415 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3416 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3417 getF32Constant(DAG, 0x4007b923));
3418 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3419 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3420 getF32Constant(DAG, 0x40823e2f));
3421 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3422 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3423 getF32Constant(DAG, 0x4020d29c));
3425 result = DAG.getNode(ISD::FADD, dl,
3426 MVT::f32, LogOfExponent, Log2ofMantissa);
3427 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3428 // For floating-point precision of 18:
3437 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3439 // error 0.0000018516, which is better than 18 bits
3440 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3441 getF32Constant(DAG, 0xbcd2769e));
3442 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3443 getF32Constant(DAG, 0x3e8ce0b9));
3444 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3445 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3446 getF32Constant(DAG, 0x3fa22ae7));
3447 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3448 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3449 getF32Constant(DAG, 0x40525723));
3450 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3451 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3452 getF32Constant(DAG, 0x40aaf200));
3453 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3454 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3455 getF32Constant(DAG, 0x40c39dad));
3456 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3457 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3458 getF32Constant(DAG, 0x4042902c));
3460 result = DAG.getNode(ISD::FADD, dl,
3461 MVT::f32, LogOfExponent, Log2ofMantissa);
3464 // No special expansion.
3465 result = DAG.getNode(ISD::FLOG2, dl,
3466 getValue(I.getOperand(1)).getValueType(),
3467 getValue(I.getOperand(1)));
3470 setValue(&I, result);
3473 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3474 /// limited-precision mode.
3476 SelectionDAGLowering::visitLog10(CallInst &I) {
3478 DebugLoc dl = getCurDebugLoc();
3480 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3481 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3482 SDValue Op = getValue(I.getOperand(1));
3483 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3485 // Scale the exponent by log10(2) [0.30102999f].
3486 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3487 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3488 getF32Constant(DAG, 0x3e9a209a));
3490 // Get the significand and build it into a floating-point number with
3492 SDValue X = GetSignificand(DAG, Op1, dl);
3494 if (LimitFloatPrecision <= 6) {
3495 // For floating-point precision of 6:
3497 // Log10ofMantissa =
3499 // (0.60948995f - 0.10380950f * x) * x;
3501 // error 0.0014886165, which is 6 bits
3502 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3503 getF32Constant(DAG, 0xbdd49a13));
3504 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3505 getF32Constant(DAG, 0x3f1c0789));
3506 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3507 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3508 getF32Constant(DAG, 0x3f011300));
3510 result = DAG.getNode(ISD::FADD, dl,
3511 MVT::f32, LogOfExponent, Log10ofMantissa);
3512 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3513 // For floating-point precision of 12:
3515 // Log10ofMantissa =
3518 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3520 // error 0.00019228036, which is better than 12 bits
3521 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3522 getF32Constant(DAG, 0x3d431f31));
3523 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3524 getF32Constant(DAG, 0x3ea21fb2));
3525 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3526 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3527 getF32Constant(DAG, 0x3f6ae232));
3528 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3529 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3530 getF32Constant(DAG, 0x3f25f7c3));
3532 result = DAG.getNode(ISD::FADD, dl,
3533 MVT::f32, LogOfExponent, Log10ofMantissa);
3534 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3535 // For floating-point precision of 18:
3537 // Log10ofMantissa =
3542 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3544 // error 0.0000037995730, which is better than 18 bits
3545 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3546 getF32Constant(DAG, 0x3c5d51ce));
3547 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3548 getF32Constant(DAG, 0x3e00685a));
3549 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3550 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3551 getF32Constant(DAG, 0x3efb6798));
3552 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3553 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3554 getF32Constant(DAG, 0x3f88d192));
3555 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3556 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3557 getF32Constant(DAG, 0x3fc4316c));
3558 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3559 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3560 getF32Constant(DAG, 0x3f57ce70));
3562 result = DAG.getNode(ISD::FADD, dl,
3563 MVT::f32, LogOfExponent, Log10ofMantissa);
3566 // No special expansion.
3567 result = DAG.getNode(ISD::FLOG10, dl,
3568 getValue(I.getOperand(1)).getValueType(),
3569 getValue(I.getOperand(1)));
3572 setValue(&I, result);
3575 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3576 /// limited-precision mode.
3578 SelectionDAGLowering::visitExp2(CallInst &I) {
3580 DebugLoc dl = getCurDebugLoc();
3582 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3583 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3584 SDValue Op = getValue(I.getOperand(1));
3586 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3588 // FractionalPartOfX = x - (float)IntegerPartOfX;
3589 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3590 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3592 // IntegerPartOfX <<= 23;
3593 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3594 DAG.getConstant(23, TLI.getPointerTy()));
3596 if (LimitFloatPrecision <= 6) {
3597 // For floating-point precision of 6:
3599 // TwoToFractionalPartOfX =
3601 // (0.735607626f + 0.252464424f * x) * x;
3603 // error 0.0144103317, which is 6 bits
3604 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3605 getF32Constant(DAG, 0x3e814304));
3606 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3607 getF32Constant(DAG, 0x3f3c50c8));
3608 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3609 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3610 getF32Constant(DAG, 0x3f7f5e7e));
3611 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3612 SDValue TwoToFractionalPartOfX =
3613 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3615 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3616 MVT::f32, TwoToFractionalPartOfX);
3617 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3618 // For floating-point precision of 12:
3620 // TwoToFractionalPartOfX =
3623 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3625 // error 0.000107046256, which is 13 to 14 bits
3626 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3627 getF32Constant(DAG, 0x3da235e3));
3628 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3629 getF32Constant(DAG, 0x3e65b8f3));
3630 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3631 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3632 getF32Constant(DAG, 0x3f324b07));
3633 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3634 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3635 getF32Constant(DAG, 0x3f7ff8fd));
3636 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3637 SDValue TwoToFractionalPartOfX =
3638 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3640 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3641 MVT::f32, TwoToFractionalPartOfX);
3642 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3643 // For floating-point precision of 18:
3645 // TwoToFractionalPartOfX =
3649 // (0.554906021e-1f +
3650 // (0.961591928e-2f +
3651 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3652 // error 2.47208000*10^(-7), which is better than 18 bits
3653 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3654 getF32Constant(DAG, 0x3924b03e));
3655 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3656 getF32Constant(DAG, 0x3ab24b87));
3657 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3658 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3659 getF32Constant(DAG, 0x3c1d8c17));
3660 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3661 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3662 getF32Constant(DAG, 0x3d634a1d));
3663 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3664 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3665 getF32Constant(DAG, 0x3e75fe14));
3666 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3667 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3668 getF32Constant(DAG, 0x3f317234));
3669 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3670 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3671 getF32Constant(DAG, 0x3f800000));
3672 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3673 SDValue TwoToFractionalPartOfX =
3674 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3676 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3677 MVT::f32, TwoToFractionalPartOfX);
3680 // No special expansion.
3681 result = DAG.getNode(ISD::FEXP2, dl,
3682 getValue(I.getOperand(1)).getValueType(),
3683 getValue(I.getOperand(1)));
3686 setValue(&I, result);
3689 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3690 /// limited-precision mode with x == 10.0f.
3692 SelectionDAGLowering::visitPow(CallInst &I) {
3694 Value *Val = I.getOperand(1);
3695 DebugLoc dl = getCurDebugLoc();
3696 bool IsExp10 = false;
3698 if (getValue(Val).getValueType() == MVT::f32 &&
3699 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3700 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3701 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3702 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3704 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3709 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3710 SDValue Op = getValue(I.getOperand(2));
3712 // Put the exponent in the right bit position for later addition to the
3715 // #define LOG2OF10 3.3219281f
3716 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3717 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3718 getF32Constant(DAG, 0x40549a78));
3719 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3721 // FractionalPartOfX = x - (float)IntegerPartOfX;
3722 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3723 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3725 // IntegerPartOfX <<= 23;
3726 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3727 DAG.getConstant(23, TLI.getPointerTy()));
3729 if (LimitFloatPrecision <= 6) {
3730 // For floating-point precision of 6:
3732 // twoToFractionalPartOfX =
3734 // (0.735607626f + 0.252464424f * x) * x;
3736 // error 0.0144103317, which is 6 bits
3737 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3738 getF32Constant(DAG, 0x3e814304));
3739 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3740 getF32Constant(DAG, 0x3f3c50c8));
3741 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3742 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3743 getF32Constant(DAG, 0x3f7f5e7e));
3744 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3745 SDValue TwoToFractionalPartOfX =
3746 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3748 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3749 MVT::f32, TwoToFractionalPartOfX);
3750 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3751 // For floating-point precision of 12:
3753 // TwoToFractionalPartOfX =
3756 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3758 // error 0.000107046256, which is 13 to 14 bits
3759 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3760 getF32Constant(DAG, 0x3da235e3));
3761 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3762 getF32Constant(DAG, 0x3e65b8f3));
3763 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3764 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3765 getF32Constant(DAG, 0x3f324b07));
3766 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3767 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3768 getF32Constant(DAG, 0x3f7ff8fd));
3769 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3770 SDValue TwoToFractionalPartOfX =
3771 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3773 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3774 MVT::f32, TwoToFractionalPartOfX);
3775 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3776 // For floating-point precision of 18:
3778 // TwoToFractionalPartOfX =
3782 // (0.554906021e-1f +
3783 // (0.961591928e-2f +
3784 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3785 // error 2.47208000*10^(-7), which is better than 18 bits
3786 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3787 getF32Constant(DAG, 0x3924b03e));
3788 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3789 getF32Constant(DAG, 0x3ab24b87));
3790 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3791 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3792 getF32Constant(DAG, 0x3c1d8c17));
3793 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3794 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3795 getF32Constant(DAG, 0x3d634a1d));
3796 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3797 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3798 getF32Constant(DAG, 0x3e75fe14));
3799 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3800 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3801 getF32Constant(DAG, 0x3f317234));
3802 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3803 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3804 getF32Constant(DAG, 0x3f800000));
3805 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3806 SDValue TwoToFractionalPartOfX =
3807 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3809 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3810 MVT::f32, TwoToFractionalPartOfX);
3813 // No special expansion.
3814 result = DAG.getNode(ISD::FPOW, dl,
3815 getValue(I.getOperand(1)).getValueType(),
3816 getValue(I.getOperand(1)),
3817 getValue(I.getOperand(2)));
3820 setValue(&I, result);
3823 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3824 /// we want to emit this as a call to a named external function, return the name
3825 /// otherwise lower it and return null.
3827 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3828 DebugLoc dl = getCurDebugLoc();
3829 switch (Intrinsic) {
3831 // By default, turn this into a target intrinsic node.
3832 visitTargetIntrinsic(I, Intrinsic);
3834 case Intrinsic::vastart: visitVAStart(I); return 0;
3835 case Intrinsic::vaend: visitVAEnd(I); return 0;
3836 case Intrinsic::vacopy: visitVACopy(I); return 0;
3837 case Intrinsic::returnaddress:
3838 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3839 getValue(I.getOperand(1))));
3841 case Intrinsic::frameaddress:
3842 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3843 getValue(I.getOperand(1))));
3845 case Intrinsic::setjmp:
3846 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3848 case Intrinsic::longjmp:
3849 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3851 case Intrinsic::memcpy: {
3852 SDValue Op1 = getValue(I.getOperand(1));
3853 SDValue Op2 = getValue(I.getOperand(2));
3854 SDValue Op3 = getValue(I.getOperand(3));
3855 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3856 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3857 I.getOperand(1), 0, I.getOperand(2), 0));
3860 case Intrinsic::memset: {
3861 SDValue Op1 = getValue(I.getOperand(1));
3862 SDValue Op2 = getValue(I.getOperand(2));
3863 SDValue Op3 = getValue(I.getOperand(3));
3864 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3865 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3866 I.getOperand(1), 0));
3869 case Intrinsic::memmove: {
3870 SDValue Op1 = getValue(I.getOperand(1));
3871 SDValue Op2 = getValue(I.getOperand(2));
3872 SDValue Op3 = getValue(I.getOperand(3));
3873 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3875 // If the source and destination are known to not be aliases, we can
3876 // lower memmove as memcpy.
3877 uint64_t Size = -1ULL;
3878 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3879 Size = C->getZExtValue();
3880 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3881 AliasAnalysis::NoAlias) {
3882 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3883 I.getOperand(1), 0, I.getOperand(2), 0));
3887 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3888 I.getOperand(1), 0, I.getOperand(2), 0));
3891 case Intrinsic::dbg_stoppoint: {
3892 DwarfWriter *DW = DAG.getDwarfWriter();
3893 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3894 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
3895 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3899 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3900 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3901 unsigned idx = DAG.getMachineFunction().
3902 getOrCreateDebugLocID(SrcFile,
3905 setCurDebugLoc(DebugLoc::get(idx));
3909 case Intrinsic::dbg_region_start: {
3910 DwarfWriter *DW = DAG.getDwarfWriter();
3911 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3912 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
3914 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3916 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3917 getRoot(), LabelID));
3918 DW->setFastCodeGen(Fast);
3923 case Intrinsic::dbg_region_end: {
3924 DwarfWriter *DW = DAG.getDwarfWriter();
3925 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3926 if (DW && DW->ValidDebugInfo(REI.getContext())) {
3928 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3930 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3931 getRoot(), LabelID));
3936 case Intrinsic::dbg_func_start: {
3937 DwarfWriter *DW = DAG.getDwarfWriter();
3939 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3940 Value *SP = FSI.getSubprogram();
3941 if (SP && DW->ValidDebugInfo(SP)) {
3942 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3943 // what (most?) gdb expects.
3944 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3945 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3946 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3947 CompileUnit.getFilename());
3949 // Record the source line but does not create a label for the normal
3950 // function start. It will be emitted at asm emission time. However,
3951 // create a label if this is a beginning of inlined function.
3952 unsigned Line = Subprogram.getLineNumber();
3955 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3956 if (DW->getRecordSourceLineCount() != 1)
3957 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3958 getRoot(), LabelID));
3961 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
3962 getOrCreateDebugLocID(SrcFile, Line, 0)));
3967 case Intrinsic::dbg_declare: {
3969 DwarfWriter *DW = DAG.getDwarfWriter();
3970 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3971 Value *Variable = DI.getVariable();
3972 if (DW && DW->ValidDebugInfo(Variable))
3973 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3974 getValue(DI.getAddress()), getValue(Variable)));
3976 // FIXME: Do something sensible here when we support debug declare.
3980 case Intrinsic::eh_exception: {
3981 if (!CurMBB->isLandingPad()) {
3982 // FIXME: Mark exception register as live in. Hack for PR1508.
3983 unsigned Reg = TLI.getExceptionAddressRegister();
3984 if (Reg) CurMBB->addLiveIn(Reg);
3986 // Insert the EXCEPTIONADDR instruction.
3987 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3989 Ops[0] = DAG.getRoot();
3990 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3992 DAG.setRoot(Op.getValue(1));
3996 case Intrinsic::eh_selector_i32:
3997 case Intrinsic::eh_selector_i64: {
3998 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3999 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4000 MVT::i32 : MVT::i64);
4003 if (CurMBB->isLandingPad())
4004 AddCatchInfo(I, MMI, CurMBB);
4007 FuncInfo.CatchInfoLost.insert(&I);
4009 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4010 unsigned Reg = TLI.getExceptionSelectorRegister();
4011 if (Reg) CurMBB->addLiveIn(Reg);
4014 // Insert the EHSELECTION instruction.
4015 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4017 Ops[0] = getValue(I.getOperand(1));
4019 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4021 DAG.setRoot(Op.getValue(1));
4023 setValue(&I, DAG.getConstant(0, VT));
4029 case Intrinsic::eh_typeid_for_i32:
4030 case Intrinsic::eh_typeid_for_i64: {
4031 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4032 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4033 MVT::i32 : MVT::i64);
4036 // Find the type id for the given typeinfo.
4037 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4039 unsigned TypeID = MMI->getTypeIDFor(GV);
4040 setValue(&I, DAG.getConstant(TypeID, VT));
4042 // Return something different to eh_selector.
4043 setValue(&I, DAG.getConstant(1, VT));
4049 case Intrinsic::eh_return_i32:
4050 case Intrinsic::eh_return_i64:
4051 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4052 MMI->setCallsEHReturn(true);
4053 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4056 getValue(I.getOperand(1)),
4057 getValue(I.getOperand(2))));
4059 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4063 case Intrinsic::eh_unwind_init:
4064 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4065 MMI->setCallsUnwindInit(true);
4070 case Intrinsic::eh_dwarf_cfa: {
4071 MVT VT = getValue(I.getOperand(1)).getValueType();
4073 if (VT.bitsGT(TLI.getPointerTy()))
4074 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4075 TLI.getPointerTy(), getValue(I.getOperand(1)));
4077 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4078 TLI.getPointerTy(), getValue(I.getOperand(1)));
4080 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4082 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4083 TLI.getPointerTy()),
4085 setValue(&I, DAG.getNode(ISD::ADD, dl,
4087 DAG.getNode(ISD::FRAMEADDR, dl,
4090 TLI.getPointerTy())),
4095 case Intrinsic::convertff:
4096 case Intrinsic::convertfsi:
4097 case Intrinsic::convertfui:
4098 case Intrinsic::convertsif:
4099 case Intrinsic::convertuif:
4100 case Intrinsic::convertss:
4101 case Intrinsic::convertsu:
4102 case Intrinsic::convertus:
4103 case Intrinsic::convertuu: {
4104 ISD::CvtCode Code = ISD::CVT_INVALID;
4105 switch (Intrinsic) {
4106 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4107 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4108 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4109 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4110 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4111 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4112 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4113 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4114 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4116 MVT DestVT = TLI.getValueType(I.getType());
4117 Value* Op1 = I.getOperand(1);
4118 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4119 DAG.getValueType(DestVT),
4120 DAG.getValueType(getValue(Op1).getValueType()),
4121 getValue(I.getOperand(2)),
4122 getValue(I.getOperand(3)),
4127 case Intrinsic::sqrt:
4128 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4129 getValue(I.getOperand(1)).getValueType(),
4130 getValue(I.getOperand(1))));
4132 case Intrinsic::powi:
4133 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4134 getValue(I.getOperand(1)).getValueType(),
4135 getValue(I.getOperand(1)),
4136 getValue(I.getOperand(2))));
4138 case Intrinsic::sin:
4139 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4140 getValue(I.getOperand(1)).getValueType(),
4141 getValue(I.getOperand(1))));
4143 case Intrinsic::cos:
4144 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4145 getValue(I.getOperand(1)).getValueType(),
4146 getValue(I.getOperand(1))));
4148 case Intrinsic::log:
4151 case Intrinsic::log2:
4154 case Intrinsic::log10:
4157 case Intrinsic::exp:
4160 case Intrinsic::exp2:
4163 case Intrinsic::pow:
4166 case Intrinsic::pcmarker: {
4167 SDValue Tmp = getValue(I.getOperand(1));
4168 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4171 case Intrinsic::readcyclecounter: {
4172 SDValue Op = getRoot();
4173 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4174 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4177 DAG.setRoot(Tmp.getValue(1));
4180 case Intrinsic::part_select: {
4181 // Currently not implemented: just abort
4182 assert(0 && "part_select intrinsic not implemented");
4185 case Intrinsic::part_set: {
4186 // Currently not implemented: just abort
4187 assert(0 && "part_set intrinsic not implemented");
4190 case Intrinsic::bswap:
4191 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4192 getValue(I.getOperand(1)).getValueType(),
4193 getValue(I.getOperand(1))));
4195 case Intrinsic::cttz: {
4196 SDValue Arg = getValue(I.getOperand(1));
4197 MVT Ty = Arg.getValueType();
4198 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4199 setValue(&I, result);
4202 case Intrinsic::ctlz: {
4203 SDValue Arg = getValue(I.getOperand(1));
4204 MVT Ty = Arg.getValueType();
4205 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4206 setValue(&I, result);
4209 case Intrinsic::ctpop: {
4210 SDValue Arg = getValue(I.getOperand(1));
4211 MVT Ty = Arg.getValueType();
4212 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4213 setValue(&I, result);
4216 case Intrinsic::stacksave: {
4217 SDValue Op = getRoot();
4218 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4219 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4221 DAG.setRoot(Tmp.getValue(1));
4224 case Intrinsic::stackrestore: {
4225 SDValue Tmp = getValue(I.getOperand(1));
4226 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4229 case Intrinsic::stackprotector: {
4230 // Emit code into the DAG to store the stack guard onto the stack.
4231 MachineFunction &MF = DAG.getMachineFunction();
4232 MachineFrameInfo *MFI = MF.getFrameInfo();
4233 MVT PtrTy = TLI.getPointerTy();
4235 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4236 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4238 int FI = FuncInfo.StaticAllocaMap[Slot];
4239 MFI->setStackProtectorIndex(FI);
4241 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4243 // Store the stack protector onto the stack.
4244 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4245 PseudoSourceValue::getFixedStack(FI),
4247 setValue(&I, Result);
4248 DAG.setRoot(Result);
4251 case Intrinsic::var_annotation:
4252 // Discard annotate attributes
4255 case Intrinsic::init_trampoline: {
4256 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4260 Ops[1] = getValue(I.getOperand(1));
4261 Ops[2] = getValue(I.getOperand(2));
4262 Ops[3] = getValue(I.getOperand(3));
4263 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4264 Ops[5] = DAG.getSrcValue(F);
4266 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4267 DAG.getNodeValueTypes(TLI.getPointerTy(),
4272 DAG.setRoot(Tmp.getValue(1));
4276 case Intrinsic::gcroot:
4278 Value *Alloca = I.getOperand(1);
4279 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4281 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4282 GFI->addStackRoot(FI->getIndex(), TypeMap);
4286 case Intrinsic::gcread:
4287 case Intrinsic::gcwrite:
4288 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4291 case Intrinsic::flt_rounds: {
4292 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4296 case Intrinsic::trap: {
4297 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4301 case Intrinsic::uadd_with_overflow:
4302 return implVisitAluOverflow(I, ISD::UADDO);
4303 case Intrinsic::sadd_with_overflow:
4304 return implVisitAluOverflow(I, ISD::SADDO);
4305 case Intrinsic::usub_with_overflow:
4306 return implVisitAluOverflow(I, ISD::USUBO);
4307 case Intrinsic::ssub_with_overflow:
4308 return implVisitAluOverflow(I, ISD::SSUBO);
4309 case Intrinsic::umul_with_overflow:
4310 return implVisitAluOverflow(I, ISD::UMULO);
4311 case Intrinsic::smul_with_overflow:
4312 return implVisitAluOverflow(I, ISD::SMULO);
4314 case Intrinsic::prefetch: {
4317 Ops[1] = getValue(I.getOperand(1));
4318 Ops[2] = getValue(I.getOperand(2));
4319 Ops[3] = getValue(I.getOperand(3));
4320 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4324 case Intrinsic::memory_barrier: {
4327 for (int x = 1; x < 6; ++x)
4328 Ops[x] = getValue(I.getOperand(x));
4330 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4333 case Intrinsic::atomic_cmp_swap: {
4334 SDValue Root = getRoot();
4336 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4337 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4339 getValue(I.getOperand(1)),
4340 getValue(I.getOperand(2)),
4341 getValue(I.getOperand(3)),
4344 DAG.setRoot(L.getValue(1));
4347 case Intrinsic::atomic_load_add:
4348 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4349 case Intrinsic::atomic_load_sub:
4350 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4351 case Intrinsic::atomic_load_or:
4352 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4353 case Intrinsic::atomic_load_xor:
4354 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4355 case Intrinsic::atomic_load_and:
4356 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4357 case Intrinsic::atomic_load_nand:
4358 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4359 case Intrinsic::atomic_load_max:
4360 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4361 case Intrinsic::atomic_load_min:
4362 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4363 case Intrinsic::atomic_load_umin:
4364 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4365 case Intrinsic::atomic_load_umax:
4366 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4367 case Intrinsic::atomic_swap:
4368 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4373 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4375 MachineBasicBlock *LandingPad) {
4376 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4377 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4378 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4379 unsigned BeginLabel = 0, EndLabel = 0;
4381 TargetLowering::ArgListTy Args;
4382 TargetLowering::ArgListEntry Entry;
4383 Args.reserve(CS.arg_size());
4384 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4386 SDValue ArgNode = getValue(*i);
4387 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4389 unsigned attrInd = i - CS.arg_begin() + 1;
4390 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4391 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4392 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4393 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4394 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4395 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4396 Entry.Alignment = CS.getParamAlignment(attrInd);
4397 Args.push_back(Entry);
4400 if (LandingPad && MMI) {
4401 // Insert a label before the invoke call to mark the try range. This can be
4402 // used to detect deletion of the invoke via the MachineModuleInfo.
4403 BeginLabel = MMI->NextLabelID();
4404 // Both PendingLoads and PendingExports must be flushed here;
4405 // this call might not return.
4407 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4408 getControlRoot(), BeginLabel));
4411 std::pair<SDValue,SDValue> Result =
4412 TLI.LowerCallTo(getRoot(), CS.getType(),
4413 CS.paramHasAttr(0, Attribute::SExt),
4414 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4415 CS.paramHasAttr(0, Attribute::InReg),
4416 CS.getCallingConv(),
4417 IsTailCall && PerformTailCallOpt,
4418 Callee, Args, DAG, getCurDebugLoc());
4419 if (CS.getType() != Type::VoidTy)
4420 setValue(CS.getInstruction(), Result.first);
4421 DAG.setRoot(Result.second);
4423 if (LandingPad && MMI) {
4424 // Insert a label at the end of the invoke call to mark the try range. This
4425 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4426 EndLabel = MMI->NextLabelID();
4427 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4428 getRoot(), EndLabel));
4430 // Inform MachineModuleInfo of range.
4431 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4436 void SelectionDAGLowering::visitCall(CallInst &I) {
4437 const char *RenameFn = 0;
4438 if (Function *F = I.getCalledFunction()) {
4439 if (F->isDeclaration()) {
4440 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4442 if (unsigned IID = II->getIntrinsicID(F)) {
4443 RenameFn = visitIntrinsicCall(I, IID);
4448 if (unsigned IID = F->getIntrinsicID()) {
4449 RenameFn = visitIntrinsicCall(I, IID);
4455 // Check for well-known libc/libm calls. If the function is internal, it
4456 // can't be a library call.
4457 unsigned NameLen = F->getNameLen();
4458 if (!F->hasLocalLinkage() && NameLen) {
4459 const char *NameStr = F->getNameStart();
4460 if (NameStr[0] == 'c' &&
4461 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4462 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4463 if (I.getNumOperands() == 3 && // Basic sanity checks.
4464 I.getOperand(1)->getType()->isFloatingPoint() &&
4465 I.getType() == I.getOperand(1)->getType() &&
4466 I.getType() == I.getOperand(2)->getType()) {
4467 SDValue LHS = getValue(I.getOperand(1));
4468 SDValue RHS = getValue(I.getOperand(2));
4469 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4470 LHS.getValueType(), LHS, RHS));
4473 } else if (NameStr[0] == 'f' &&
4474 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4475 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4476 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4477 if (I.getNumOperands() == 2 && // Basic sanity checks.
4478 I.getOperand(1)->getType()->isFloatingPoint() &&
4479 I.getType() == I.getOperand(1)->getType()) {
4480 SDValue Tmp = getValue(I.getOperand(1));
4481 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4482 Tmp.getValueType(), Tmp));
4485 } else if (NameStr[0] == 's' &&
4486 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4487 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4488 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4489 if (I.getNumOperands() == 2 && // Basic sanity checks.
4490 I.getOperand(1)->getType()->isFloatingPoint() &&
4491 I.getType() == I.getOperand(1)->getType()) {
4492 SDValue Tmp = getValue(I.getOperand(1));
4493 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4494 Tmp.getValueType(), Tmp));
4497 } else if (NameStr[0] == 'c' &&
4498 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4499 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4500 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4501 if (I.getNumOperands() == 2 && // Basic sanity checks.
4502 I.getOperand(1)->getType()->isFloatingPoint() &&
4503 I.getType() == I.getOperand(1)->getType()) {
4504 SDValue Tmp = getValue(I.getOperand(1));
4505 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4506 Tmp.getValueType(), Tmp));
4511 } else if (isa<InlineAsm>(I.getOperand(0))) {
4518 Callee = getValue(I.getOperand(0));
4520 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4522 LowerCallTo(&I, Callee, I.isTailCall());
4526 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4527 /// this value and returns the result as a ValueVT value. This uses
4528 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4529 /// If the Flag pointer is NULL, no flag is used.
4530 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4532 SDValue *Flag) const {
4533 // Assemble the legal parts into the final values.
4534 SmallVector<SDValue, 4> Values(ValueVTs.size());
4535 SmallVector<SDValue, 8> Parts;
4536 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4537 // Copy the legal parts from the registers.
4538 MVT ValueVT = ValueVTs[Value];
4539 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4540 MVT RegisterVT = RegVTs[Value];
4542 Parts.resize(NumRegs);
4543 for (unsigned i = 0; i != NumRegs; ++i) {
4546 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4548 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4549 *Flag = P.getValue(2);
4551 Chain = P.getValue(1);
4553 // If the source register was virtual and if we know something about it,
4554 // add an assert node.
4555 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4556 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4557 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4558 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4559 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4560 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4562 unsigned RegSize = RegisterVT.getSizeInBits();
4563 unsigned NumSignBits = LOI.NumSignBits;
4564 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4566 // FIXME: We capture more information than the dag can represent. For
4567 // now, just use the tightest assertzext/assertsext possible.
4569 MVT FromVT(MVT::Other);
4570 if (NumSignBits == RegSize)
4571 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4572 else if (NumZeroBits >= RegSize-1)
4573 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4574 else if (NumSignBits > RegSize-8)
4575 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4576 else if (NumZeroBits >= RegSize-9)
4577 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4578 else if (NumSignBits > RegSize-16)
4579 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4580 else if (NumZeroBits >= RegSize-17)
4581 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4582 else if (NumSignBits > RegSize-32)
4583 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4584 else if (NumZeroBits >= RegSize-33)
4585 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4587 if (FromVT != MVT::Other) {
4588 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4589 RegisterVT, P, DAG.getValueType(FromVT));
4598 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4599 NumRegs, RegisterVT, ValueVT);
4604 return DAG.getNode(ISD::MERGE_VALUES, dl,
4605 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4606 &Values[0], ValueVTs.size());
4609 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4610 /// specified value into the registers specified by this object. This uses
4611 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4612 /// If the Flag pointer is NULL, no flag is used.
4613 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4614 SDValue &Chain, SDValue *Flag) const {
4615 // Get the list of the values's legal parts.
4616 unsigned NumRegs = Regs.size();
4617 SmallVector<SDValue, 8> Parts(NumRegs);
4618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4619 MVT ValueVT = ValueVTs[Value];
4620 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4621 MVT RegisterVT = RegVTs[Value];
4623 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4624 &Parts[Part], NumParts, RegisterVT);
4628 // Copy the parts into the registers.
4629 SmallVector<SDValue, 8> Chains(NumRegs);
4630 for (unsigned i = 0; i != NumRegs; ++i) {
4633 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4635 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4636 *Flag = Part.getValue(1);
4638 Chains[i] = Part.getValue(0);
4641 if (NumRegs == 1 || Flag)
4642 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4643 // flagged to it. That is the CopyToReg nodes and the user are considered
4644 // a single scheduling unit. If we create a TokenFactor and return it as
4645 // chain, then the TokenFactor is both a predecessor (operand) of the
4646 // user as well as a successor (the TF operands are flagged to the user).
4647 // c1, f1 = CopyToReg
4648 // c2, f2 = CopyToReg
4649 // c3 = TokenFactor c1, c2
4652 Chain = Chains[NumRegs-1];
4654 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4657 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4658 /// operand list. This adds the code marker and includes the number of
4659 /// values added into it.
4660 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4661 std::vector<SDValue> &Ops) const {
4662 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4663 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4664 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4665 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4666 MVT RegisterVT = RegVTs[Value];
4667 for (unsigned i = 0; i != NumRegs; ++i) {
4668 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4669 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4674 /// isAllocatableRegister - If the specified register is safe to allocate,
4675 /// i.e. it isn't a stack pointer or some other special register, return the
4676 /// register class for the register. Otherwise, return null.
4677 static const TargetRegisterClass *
4678 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4679 const TargetLowering &TLI,
4680 const TargetRegisterInfo *TRI) {
4681 MVT FoundVT = MVT::Other;
4682 const TargetRegisterClass *FoundRC = 0;
4683 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4684 E = TRI->regclass_end(); RCI != E; ++RCI) {
4685 MVT ThisVT = MVT::Other;
4687 const TargetRegisterClass *RC = *RCI;
4688 // If none of the the value types for this register class are valid, we
4689 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4690 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4692 if (TLI.isTypeLegal(*I)) {
4693 // If we have already found this register in a different register class,
4694 // choose the one with the largest VT specified. For example, on
4695 // PowerPC, we favor f64 register classes over f32.
4696 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4703 if (ThisVT == MVT::Other) continue;
4705 // NOTE: This isn't ideal. In particular, this might allocate the
4706 // frame pointer in functions that need it (due to them not being taken
4707 // out of allocation, because a variable sized allocation hasn't been seen
4708 // yet). This is a slight code pessimization, but should still work.
4709 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4710 E = RC->allocation_order_end(MF); I != E; ++I)
4712 // We found a matching register class. Keep looking at others in case
4713 // we find one with larger registers that this physreg is also in.
4724 /// AsmOperandInfo - This contains information for each constraint that we are
4726 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4727 public TargetLowering::AsmOperandInfo {
4729 /// CallOperand - If this is the result output operand or a clobber
4730 /// this is null, otherwise it is the incoming operand to the CallInst.
4731 /// This gets modified as the asm is processed.
4732 SDValue CallOperand;
4734 /// AssignedRegs - If this is a register or register class operand, this
4735 /// contains the set of register corresponding to the operand.
4736 RegsForValue AssignedRegs;
4738 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4739 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4742 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4743 /// busy in OutputRegs/InputRegs.
4744 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4745 std::set<unsigned> &OutputRegs,
4746 std::set<unsigned> &InputRegs,
4747 const TargetRegisterInfo &TRI) const {
4749 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4750 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4753 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4754 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4758 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4759 /// corresponds to. If there is no Value* for this operand, it returns
4761 MVT getCallOperandValMVT(const TargetLowering &TLI,
4762 const TargetData *TD) const {
4763 if (CallOperandVal == 0) return MVT::Other;
4765 if (isa<BasicBlock>(CallOperandVal))
4766 return TLI.getPointerTy();
4768 const llvm::Type *OpTy = CallOperandVal->getType();
4770 // If this is an indirect operand, the operand is a pointer to the
4773 OpTy = cast<PointerType>(OpTy)->getElementType();
4775 // If OpTy is not a single value, it may be a struct/union that we
4776 // can tile with integers.
4777 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4778 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4787 OpTy = IntegerType::get(BitSize);
4792 return TLI.getValueType(OpTy, true);
4796 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4798 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4799 const TargetRegisterInfo &TRI) {
4800 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4802 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4803 for (; *Aliases; ++Aliases)
4804 Regs.insert(*Aliases);
4807 } // end llvm namespace.
4810 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4811 /// specified operand. We prefer to assign virtual registers, to allow the
4812 /// register allocator handle the assignment process. However, if the asm uses
4813 /// features that we can't model on machineinstrs, we have SDISel do the
4814 /// allocation. This produces generally horrible, but correct, code.
4816 /// OpInfo describes the operand.
4817 /// Input and OutputRegs are the set of already allocated physical registers.
4819 void SelectionDAGLowering::
4820 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4821 std::set<unsigned> &OutputRegs,
4822 std::set<unsigned> &InputRegs) {
4823 // Compute whether this value requires an input register, an output register,
4825 bool isOutReg = false;
4826 bool isInReg = false;
4827 switch (OpInfo.Type) {
4828 case InlineAsm::isOutput:
4831 // If there is an input constraint that matches this, we need to reserve
4832 // the input register so no other inputs allocate to it.
4833 isInReg = OpInfo.hasMatchingInput();
4835 case InlineAsm::isInput:
4839 case InlineAsm::isClobber:
4846 MachineFunction &MF = DAG.getMachineFunction();
4847 SmallVector<unsigned, 4> Regs;
4849 // If this is a constraint for a single physreg, or a constraint for a
4850 // register class, find it.
4851 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4852 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4853 OpInfo.ConstraintVT);
4855 unsigned NumRegs = 1;
4856 if (OpInfo.ConstraintVT != MVT::Other) {
4857 // If this is a FP input in an integer register (or visa versa) insert a bit
4858 // cast of the input value. More generally, handle any case where the input
4859 // value disagrees with the register class we plan to stick this in.
4860 if (OpInfo.Type == InlineAsm::isInput &&
4861 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4862 // Try to convert to the first MVT that the reg class contains. If the
4863 // types are identical size, use a bitcast to convert (e.g. two differing
4865 MVT RegVT = *PhysReg.second->vt_begin();
4866 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4867 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4868 RegVT, OpInfo.CallOperand);
4869 OpInfo.ConstraintVT = RegVT;
4870 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4871 // If the input is a FP value and we want it in FP registers, do a
4872 // bitcast to the corresponding integer type. This turns an f64 value
4873 // into i64, which can be passed with two i32 values on a 32-bit
4875 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4876 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4877 RegVT, OpInfo.CallOperand);
4878 OpInfo.ConstraintVT = RegVT;
4882 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4886 MVT ValueVT = OpInfo.ConstraintVT;
4888 // If this is a constraint for a specific physical register, like {r17},
4890 if (PhysReg.first) {
4891 if (OpInfo.ConstraintVT == MVT::Other)
4892 ValueVT = *PhysReg.second->vt_begin();
4894 // Get the actual register value type. This is important, because the user
4895 // may have asked for (e.g.) the AX register in i32 type. We need to
4896 // remember that AX is actually i16 to get the right extension.
4897 RegVT = *PhysReg.second->vt_begin();
4899 // This is a explicit reference to a physical register.
4900 Regs.push_back(PhysReg.first);
4902 // If this is an expanded reference, add the rest of the regs to Regs.
4904 TargetRegisterClass::iterator I = PhysReg.second->begin();
4905 for (; *I != PhysReg.first; ++I)
4906 assert(I != PhysReg.second->end() && "Didn't find reg!");
4908 // Already added the first reg.
4910 for (; NumRegs; --NumRegs, ++I) {
4911 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4915 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4916 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4917 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4921 // Otherwise, if this was a reference to an LLVM register class, create vregs
4922 // for this reference.
4923 std::vector<unsigned> RegClassRegs;
4924 const TargetRegisterClass *RC = PhysReg.second;
4926 // If this is a tied register, our regalloc doesn't know how to maintain
4927 // the constraint, so we have to pick a register to pin the input/output to.
4928 // If it isn't a matched constraint, go ahead and create vreg and let the
4929 // regalloc do its thing.
4930 if (!OpInfo.hasMatchingInput()) {
4931 RegVT = *PhysReg.second->vt_begin();
4932 if (OpInfo.ConstraintVT == MVT::Other)
4935 // Create the appropriate number of virtual registers.
4936 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4937 for (; NumRegs; --NumRegs)
4938 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4940 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4944 // Otherwise, we can't allocate it. Let the code below figure out how to
4945 // maintain these constraints.
4946 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4949 // This is a reference to a register class that doesn't directly correspond
4950 // to an LLVM register class. Allocate NumRegs consecutive, available,
4951 // registers from the class.
4952 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4953 OpInfo.ConstraintVT);
4956 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4957 unsigned NumAllocated = 0;
4958 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4959 unsigned Reg = RegClassRegs[i];
4960 // See if this register is available.
4961 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4962 (isInReg && InputRegs.count(Reg))) { // Already used.
4963 // Make sure we find consecutive registers.
4968 // Check to see if this register is allocatable (i.e. don't give out the
4971 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4972 if (!RC) { // Couldn't allocate this register.
4973 // Reset NumAllocated to make sure we return consecutive registers.
4979 // Okay, this register is good, we can use it.
4982 // If we allocated enough consecutive registers, succeed.
4983 if (NumAllocated == NumRegs) {
4984 unsigned RegStart = (i-NumAllocated)+1;
4985 unsigned RegEnd = i+1;
4986 // Mark all of the allocated registers used.
4987 for (unsigned i = RegStart; i != RegEnd; ++i)
4988 Regs.push_back(RegClassRegs[i]);
4990 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4991 OpInfo.ConstraintVT);
4992 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4997 // Otherwise, we couldn't allocate enough registers for this.
5000 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5001 /// processed uses a memory 'm' constraint.
5003 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5004 const TargetLowering &TLI) {
5005 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5006 InlineAsm::ConstraintInfo &CI = CInfos[i];
5007 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5008 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5009 if (CType == TargetLowering::C_Memory)
5017 /// visitInlineAsm - Handle a call to an InlineAsm object.
5019 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5020 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5022 /// ConstraintOperands - Information about all of the constraints.
5023 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5025 SDValue Chain = getRoot();
5028 std::set<unsigned> OutputRegs, InputRegs;
5030 // Do a prepass over the constraints, canonicalizing them, and building up the
5031 // ConstraintOperands list.
5032 std::vector<InlineAsm::ConstraintInfo>
5033 ConstraintInfos = IA->ParseConstraints();
5035 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5037 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5038 unsigned ResNo = 0; // ResNo - The result number of the next output.
5039 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5040 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5041 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5043 MVT OpVT = MVT::Other;
5045 // Compute the value type for each operand.
5046 switch (OpInfo.Type) {
5047 case InlineAsm::isOutput:
5048 // Indirect outputs just consume an argument.
5049 if (OpInfo.isIndirect) {
5050 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5054 // The return value of the call is this value. As such, there is no
5055 // corresponding argument.
5056 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5057 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5058 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5060 assert(ResNo == 0 && "Asm only has one result!");
5061 OpVT = TLI.getValueType(CS.getType());
5065 case InlineAsm::isInput:
5066 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5068 case InlineAsm::isClobber:
5073 // If this is an input or an indirect output, process the call argument.
5074 // BasicBlocks are labels, currently appearing only in asm's.
5075 if (OpInfo.CallOperandVal) {
5076 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5077 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5079 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5082 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5085 OpInfo.ConstraintVT = OpVT;
5088 // Second pass over the constraints: compute which constraint option to use
5089 // and assign registers to constraints that want a specific physreg.
5090 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5091 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5093 // If this is an output operand with a matching input operand, look up the
5094 // matching input. If their types mismatch, e.g. one is an integer, the
5095 // other is floating point, or their sizes are different, flag it as an
5097 if (OpInfo.hasMatchingInput()) {
5098 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5099 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5100 if ((OpInfo.ConstraintVT.isInteger() !=
5101 Input.ConstraintVT.isInteger()) ||
5102 (OpInfo.ConstraintVT.getSizeInBits() !=
5103 Input.ConstraintVT.getSizeInBits())) {
5104 cerr << "Unsupported asm: input constraint with a matching output "
5105 << "constraint of incompatible type!\n";
5108 Input.ConstraintVT = OpInfo.ConstraintVT;
5112 // Compute the constraint code and ConstraintType to use.
5113 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5115 // If this is a memory input, and if the operand is not indirect, do what we
5116 // need to to provide an address for the memory input.
5117 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5118 !OpInfo.isIndirect) {
5119 assert(OpInfo.Type == InlineAsm::isInput &&
5120 "Can only indirectify direct input operands!");
5122 // Memory operands really want the address of the value. If we don't have
5123 // an indirect input, put it in the constpool if we can, otherwise spill
5124 // it to a stack slot.
5126 // If the operand is a float, integer, or vector constant, spill to a
5127 // constant pool entry to get its address.
5128 Value *OpVal = OpInfo.CallOperandVal;
5129 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5130 isa<ConstantVector>(OpVal)) {
5131 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5132 TLI.getPointerTy());
5134 // Otherwise, create a stack slot and emit a store to it before the
5136 const Type *Ty = OpVal->getType();
5137 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5138 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5139 MachineFunction &MF = DAG.getMachineFunction();
5140 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5141 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5142 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5143 OpInfo.CallOperand, StackSlot, NULL, 0);
5144 OpInfo.CallOperand = StackSlot;
5147 // There is no longer a Value* corresponding to this operand.
5148 OpInfo.CallOperandVal = 0;
5149 // It is now an indirect operand.
5150 OpInfo.isIndirect = true;
5153 // If this constraint is for a specific register, allocate it before
5155 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5156 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5158 ConstraintInfos.clear();
5161 // Second pass - Loop over all of the operands, assigning virtual or physregs
5162 // to register class operands.
5163 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5164 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5166 // C_Register operands have already been allocated, Other/Memory don't need
5168 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5169 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5172 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5173 std::vector<SDValue> AsmNodeOperands;
5174 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5175 AsmNodeOperands.push_back(
5176 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5179 // Loop over all of the inputs, copying the operand values into the
5180 // appropriate registers and processing the output regs.
5181 RegsForValue RetValRegs;
5183 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5184 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5186 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5187 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5189 switch (OpInfo.Type) {
5190 case InlineAsm::isOutput: {
5191 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5192 OpInfo.ConstraintType != TargetLowering::C_Register) {
5193 // Memory output, or 'other' output (e.g. 'X' constraint).
5194 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5196 // Add information to the INLINEASM node to know about this output.
5197 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5198 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5199 TLI.getPointerTy()));
5200 AsmNodeOperands.push_back(OpInfo.CallOperand);
5204 // Otherwise, this is a register or register class output.
5206 // Copy the output from the appropriate register. Find a register that
5208 if (OpInfo.AssignedRegs.Regs.empty()) {
5209 cerr << "Couldn't allocate output reg for constraint '"
5210 << OpInfo.ConstraintCode << "'!\n";
5214 // If this is an indirect operand, store through the pointer after the
5216 if (OpInfo.isIndirect) {
5217 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5218 OpInfo.CallOperandVal));
5220 // This is the result value of the call.
5221 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5222 // Concatenate this output onto the outputs list.
5223 RetValRegs.append(OpInfo.AssignedRegs);
5226 // Add information to the INLINEASM node to know that this register is
5228 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5229 6 /* EARLYCLOBBER REGDEF */ :
5231 DAG, AsmNodeOperands);
5234 case InlineAsm::isInput: {
5235 SDValue InOperandVal = OpInfo.CallOperand;
5237 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5238 // If this is required to match an output register we have already set,
5239 // just use its register.
5240 unsigned OperandNo = OpInfo.getMatchedOperand();
5242 // Scan until we find the definition we already emitted of this operand.
5243 // When we find it, create a RegsForValue operand.
5244 unsigned CurOp = 2; // The first operand.
5245 for (; OperandNo; --OperandNo) {
5246 // Advance to the next operand.
5248 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5249 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
5250 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5251 (NumOps & 7) == 4 /*MEM*/) &&
5252 "Skipped past definitions?");
5253 CurOp += (NumOps>>3)+1;
5257 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5258 if ((NumOps & 7) == 2 /*REGDEF*/
5259 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5260 // Add NumOps>>3 registers to MatchedRegs.
5261 RegsForValue MatchedRegs;
5262 MatchedRegs.TLI = &TLI;
5263 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5264 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5265 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5267 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5268 MatchedRegs.Regs.push_back(Reg);
5271 // Use the produced MatchedRegs object to
5272 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5274 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
5277 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5278 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5279 // Add information to the INLINEASM node to know about this input.
5280 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
5281 TLI.getPointerTy()));
5282 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5287 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5288 assert(!OpInfo.isIndirect &&
5289 "Don't know how to handle indirect other inputs yet!");
5291 std::vector<SDValue> Ops;
5292 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5293 hasMemory, Ops, DAG);
5295 cerr << "Invalid operand for inline asm constraint '"
5296 << OpInfo.ConstraintCode << "'!\n";
5300 // Add information to the INLINEASM node to know about this input.
5301 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5302 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5303 TLI.getPointerTy()));
5304 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5306 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5307 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5308 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5309 "Memory operands expect pointer values");
5311 // Add information to the INLINEASM node to know about this input.
5312 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5313 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5314 TLI.getPointerTy()));
5315 AsmNodeOperands.push_back(InOperandVal);
5319 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5320 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5321 "Unknown constraint type!");
5322 assert(!OpInfo.isIndirect &&
5323 "Don't know how to handle indirect register inputs yet!");
5325 // Copy the input into the appropriate registers.
5326 if (OpInfo.AssignedRegs.Regs.empty()) {
5327 cerr << "Couldn't allocate output reg for constraint '"
5328 << OpInfo.ConstraintCode << "'!\n";
5332 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5335 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5336 DAG, AsmNodeOperands);
5339 case InlineAsm::isClobber: {
5340 // Add the clobbered value to the operand list, so that the register
5341 // allocator is aware that the physreg got clobbered.
5342 if (!OpInfo.AssignedRegs.Regs.empty())
5343 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5344 DAG, AsmNodeOperands);
5350 // Finish up input operands.
5351 AsmNodeOperands[0] = Chain;
5352 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5354 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5355 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5356 &AsmNodeOperands[0], AsmNodeOperands.size());
5357 Flag = Chain.getValue(1);
5359 // If this asm returns a register value, copy the result from that register
5360 // and set it as the value of the call.
5361 if (!RetValRegs.Regs.empty()) {
5362 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5365 // FIXME: Why don't we do this for inline asms with MRVs?
5366 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5367 MVT ResultType = TLI.getValueType(CS.getType());
5369 // If any of the results of the inline asm is a vector, it may have the
5370 // wrong width/num elts. This can happen for register classes that can
5371 // contain multiple different value types. The preg or vreg allocated may
5372 // not have the same VT as was expected. Convert it to the right type
5373 // with bit_convert.
5374 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5375 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5378 } else if (ResultType != Val.getValueType() &&
5379 ResultType.isInteger() && Val.getValueType().isInteger()) {
5380 // If a result value was tied to an input value, the computed result may
5381 // have a wider width than the expected result. Extract the relevant
5383 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5386 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5389 setValue(CS.getInstruction(), Val);
5392 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5394 // Process indirect outputs, first output all of the flagged copies out of
5396 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5397 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5398 Value *Ptr = IndirectStoresToEmit[i].second;
5399 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5401 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5404 // Emit the non-flagged stores from the physregs.
5405 SmallVector<SDValue, 8> OutChains;
5406 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5407 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5408 StoresToEmit[i].first,
5409 getValue(StoresToEmit[i].second),
5410 StoresToEmit[i].second, 0));
5411 if (!OutChains.empty())
5412 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5413 &OutChains[0], OutChains.size());
5418 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5419 SDValue Src = getValue(I.getOperand(0));
5421 MVT IntPtr = TLI.getPointerTy();
5423 if (IntPtr.bitsLT(Src.getValueType()))
5424 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5425 else if (IntPtr.bitsGT(Src.getValueType()))
5426 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5428 // Scale the source by the type size.
5429 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5430 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5431 Src, DAG.getIntPtrConstant(ElementSize));
5433 TargetLowering::ArgListTy Args;
5434 TargetLowering::ArgListEntry Entry;
5436 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5437 Args.push_back(Entry);
5439 std::pair<SDValue,SDValue> Result =
5440 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5441 CallingConv::C, PerformTailCallOpt,
5442 DAG.getExternalSymbol("malloc", IntPtr),
5443 Args, DAG, getCurDebugLoc());
5444 setValue(&I, Result.first); // Pointers always fit in registers
5445 DAG.setRoot(Result.second);
5448 void SelectionDAGLowering::visitFree(FreeInst &I) {
5449 TargetLowering::ArgListTy Args;
5450 TargetLowering::ArgListEntry Entry;
5451 Entry.Node = getValue(I.getOperand(0));
5452 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5453 Args.push_back(Entry);
5454 MVT IntPtr = TLI.getPointerTy();
5455 std::pair<SDValue,SDValue> Result =
5456 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5457 CallingConv::C, PerformTailCallOpt,
5458 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5460 DAG.setRoot(Result.second);
5463 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5464 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5465 MVT::Other, getRoot(),
5466 getValue(I.getOperand(1)),
5467 DAG.getSrcValue(I.getOperand(1))));
5470 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5471 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5472 getRoot(), getValue(I.getOperand(0)),
5473 DAG.getSrcValue(I.getOperand(0)));
5475 DAG.setRoot(V.getValue(1));
5478 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5479 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5480 MVT::Other, getRoot(),
5481 getValue(I.getOperand(1)),
5482 DAG.getSrcValue(I.getOperand(1))));
5485 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5486 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5487 MVT::Other, getRoot(),
5488 getValue(I.getOperand(1)),
5489 getValue(I.getOperand(2)),
5490 DAG.getSrcValue(I.getOperand(1)),
5491 DAG.getSrcValue(I.getOperand(2))));
5494 /// TargetLowering::LowerArguments - This is the default LowerArguments
5495 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5496 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5497 /// integrated into SDISel.
5498 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5499 SmallVectorImpl<SDValue> &ArgValues,
5501 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5502 SmallVector<SDValue, 3+16> Ops;
5503 Ops.push_back(DAG.getRoot());
5504 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5505 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5507 // Add one result value for each formal argument.
5508 SmallVector<MVT, 16> RetVals;
5510 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5512 SmallVector<MVT, 4> ValueVTs;
5513 ComputeValueVTs(*this, I->getType(), ValueVTs);
5514 for (unsigned Value = 0, NumValues = ValueVTs.size();
5515 Value != NumValues; ++Value) {
5516 MVT VT = ValueVTs[Value];
5517 const Type *ArgTy = VT.getTypeForMVT();
5518 ISD::ArgFlagsTy Flags;
5519 unsigned OriginalAlignment =
5520 getTargetData()->getABITypeAlignment(ArgTy);
5522 if (F.paramHasAttr(j, Attribute::ZExt))
5524 if (F.paramHasAttr(j, Attribute::SExt))
5526 if (F.paramHasAttr(j, Attribute::InReg))
5528 if (F.paramHasAttr(j, Attribute::StructRet))
5530 if (F.paramHasAttr(j, Attribute::ByVal)) {
5532 const PointerType *Ty = cast<PointerType>(I->getType());
5533 const Type *ElementTy = Ty->getElementType();
5534 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5535 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5536 // For ByVal, alignment should be passed from FE. BE will guess if
5537 // this info is not there but there are cases it cannot get right.
5538 if (F.getParamAlignment(j))
5539 FrameAlign = F.getParamAlignment(j);
5540 Flags.setByValAlign(FrameAlign);
5541 Flags.setByValSize(FrameSize);
5543 if (F.paramHasAttr(j, Attribute::Nest))
5545 Flags.setOrigAlign(OriginalAlignment);
5547 MVT RegisterVT = getRegisterType(VT);
5548 unsigned NumRegs = getNumRegisters(VT);
5549 for (unsigned i = 0; i != NumRegs; ++i) {
5550 RetVals.push_back(RegisterVT);
5551 ISD::ArgFlagsTy MyFlags = Flags;
5552 if (NumRegs > 1 && i == 0)
5554 // if it isn't first piece, alignment must be 1
5556 MyFlags.setOrigAlign(1);
5557 Ops.push_back(DAG.getArgFlags(MyFlags));
5562 RetVals.push_back(MVT::Other);
5565 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5566 DAG.getVTList(&RetVals[0], RetVals.size()),
5567 &Ops[0], Ops.size()).getNode();
5569 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5570 // allows exposing the loads that may be part of the argument access to the
5571 // first DAGCombiner pass.
5572 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5574 // The number of results should match up, except that the lowered one may have
5575 // an extra flag result.
5576 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5577 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5578 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5579 && "Lowering produced unexpected number of results!");
5581 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5582 if (Result != TmpRes.getNode() && Result->use_empty()) {
5583 HandleSDNode Dummy(DAG.getRoot());
5584 DAG.RemoveDeadNode(Result);
5587 Result = TmpRes.getNode();
5589 unsigned NumArgRegs = Result->getNumValues() - 1;
5590 DAG.setRoot(SDValue(Result, NumArgRegs));
5592 // Set up the return result vector.
5595 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5597 SmallVector<MVT, 4> ValueVTs;
5598 ComputeValueVTs(*this, I->getType(), ValueVTs);
5599 for (unsigned Value = 0, NumValues = ValueVTs.size();
5600 Value != NumValues; ++Value) {
5601 MVT VT = ValueVTs[Value];
5602 MVT PartVT = getRegisterType(VT);
5604 unsigned NumParts = getNumRegisters(VT);
5605 SmallVector<SDValue, 4> Parts(NumParts);
5606 for (unsigned j = 0; j != NumParts; ++j)
5607 Parts[j] = SDValue(Result, i++);
5609 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5610 if (F.paramHasAttr(Idx, Attribute::SExt))
5611 AssertOp = ISD::AssertSext;
5612 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5613 AssertOp = ISD::AssertZext;
5615 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5616 PartVT, VT, AssertOp));
5619 assert(i == NumArgRegs && "Argument register count mismatch!");
5623 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5624 /// implementation, which just inserts an ISD::CALL node, which is later custom
5625 /// lowered by the target to something concrete. FIXME: When all targets are
5626 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5627 std::pair<SDValue, SDValue>
5628 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5629 bool RetSExt, bool RetZExt, bool isVarArg,
5631 unsigned CallingConv, bool isTailCall,
5633 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5634 assert((!isTailCall || PerformTailCallOpt) &&
5635 "isTailCall set when tail-call optimizations are disabled!");
5637 SmallVector<SDValue, 32> Ops;
5638 Ops.push_back(Chain); // Op#0 - Chain
5639 Ops.push_back(Callee);
5641 // Handle all of the outgoing arguments.
5642 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5643 SmallVector<MVT, 4> ValueVTs;
5644 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5645 for (unsigned Value = 0, NumValues = ValueVTs.size();
5646 Value != NumValues; ++Value) {
5647 MVT VT = ValueVTs[Value];
5648 const Type *ArgTy = VT.getTypeForMVT();
5649 SDValue Op = SDValue(Args[i].Node.getNode(),
5650 Args[i].Node.getResNo() + Value);
5651 ISD::ArgFlagsTy Flags;
5652 unsigned OriginalAlignment =
5653 getTargetData()->getABITypeAlignment(ArgTy);
5659 if (Args[i].isInReg)
5663 if (Args[i].isByVal) {
5665 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5666 const Type *ElementTy = Ty->getElementType();
5667 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5668 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5669 // For ByVal, alignment should come from FE. BE will guess if this
5670 // info is not there but there are cases it cannot get right.
5671 if (Args[i].Alignment)
5672 FrameAlign = Args[i].Alignment;
5673 Flags.setByValAlign(FrameAlign);
5674 Flags.setByValSize(FrameSize);
5678 Flags.setOrigAlign(OriginalAlignment);
5680 MVT PartVT = getRegisterType(VT);
5681 unsigned NumParts = getNumRegisters(VT);
5682 SmallVector<SDValue, 4> Parts(NumParts);
5683 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5686 ExtendKind = ISD::SIGN_EXTEND;
5687 else if (Args[i].isZExt)
5688 ExtendKind = ISD::ZERO_EXTEND;
5690 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5692 for (unsigned i = 0; i != NumParts; ++i) {
5693 // if it isn't first piece, alignment must be 1
5694 ISD::ArgFlagsTy MyFlags = Flags;
5695 if (NumParts > 1 && i == 0)
5698 MyFlags.setOrigAlign(1);
5700 Ops.push_back(Parts[i]);
5701 Ops.push_back(DAG.getArgFlags(MyFlags));
5706 // Figure out the result value types. We start by making a list of
5707 // the potentially illegal return value types.
5708 SmallVector<MVT, 4> LoweredRetTys;
5709 SmallVector<MVT, 4> RetTys;
5710 ComputeValueVTs(*this, RetTy, RetTys);
5712 // Then we translate that to a list of legal types.
5713 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5715 MVT RegisterVT = getRegisterType(VT);
5716 unsigned NumRegs = getNumRegisters(VT);
5717 for (unsigned i = 0; i != NumRegs; ++i)
5718 LoweredRetTys.push_back(RegisterVT);
5721 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5723 // Create the CALL node.
5724 SDValue Res = DAG.getCall(CallingConv, dl,
5725 isVarArg, isTailCall, isInreg,
5726 DAG.getVTList(&LoweredRetTys[0],
5727 LoweredRetTys.size()),
5730 Chain = Res.getValue(LoweredRetTys.size() - 1);
5732 // Gather up the call result into a single value.
5733 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5734 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5737 AssertOp = ISD::AssertSext;
5739 AssertOp = ISD::AssertZext;
5741 SmallVector<SDValue, 4> ReturnValues;
5743 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5745 MVT RegisterVT = getRegisterType(VT);
5746 unsigned NumRegs = getNumRegisters(VT);
5747 unsigned RegNoEnd = NumRegs + RegNo;
5748 SmallVector<SDValue, 4> Results;
5749 for (; RegNo != RegNoEnd; ++RegNo)
5750 Results.push_back(Res.getValue(RegNo));
5751 SDValue ReturnValue =
5752 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5754 ReturnValues.push_back(ReturnValue);
5756 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5757 DAG.getVTList(&RetTys[0], RetTys.size()),
5758 &ReturnValues[0], ReturnValues.size());
5761 return std::make_pair(Res, Chain);
5764 void TargetLowering::LowerOperationWrapper(SDNode *N,
5765 SmallVectorImpl<SDValue> &Results,
5766 SelectionDAG &DAG) {
5767 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5769 Results.push_back(Res);
5772 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5773 assert(0 && "LowerOperation not implemented for this target!");
5779 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5780 SDValue Op = getValue(V);
5781 assert((Op.getOpcode() != ISD::CopyFromReg ||
5782 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5783 "Copy from a reg to the same reg!");
5784 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5786 RegsForValue RFV(TLI, Reg, V->getType());
5787 SDValue Chain = DAG.getEntryNode();
5788 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5789 PendingExports.push_back(Chain);
5792 #include "llvm/CodeGen/SelectionDAGISel.h"
5794 void SelectionDAGISel::
5795 LowerArguments(BasicBlock *LLVMBB) {
5796 // If this is the entry block, emit arguments.
5797 Function &F = *LLVMBB->getParent();
5798 SDValue OldRoot = SDL->DAG.getRoot();
5799 SmallVector<SDValue, 16> Args;
5800 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5803 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5805 SmallVector<MVT, 4> ValueVTs;
5806 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5807 unsigned NumValues = ValueVTs.size();
5808 if (!AI->use_empty()) {
5809 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5810 SDL->getCurDebugLoc()));
5811 // If this argument is live outside of the entry block, insert a copy from
5812 // whereever we got it to the vreg that other BB's will reference it as.
5813 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5814 if (VMI != FuncInfo->ValueMap.end()) {
5815 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5821 // Finally, if the target has anything special to do, allow it to do so.
5822 // FIXME: this should insert code into the DAG!
5823 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5826 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5827 /// ensure constants are generated when needed. Remember the virtual registers
5828 /// that need to be added to the Machine PHI nodes as input. We cannot just
5829 /// directly add them, because expansion might result in multiple MBB's for one
5830 /// BB. As such, the start of the BB might correspond to a different MBB than
5834 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5835 TerminatorInst *TI = LLVMBB->getTerminator();
5837 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5839 // Check successor nodes' PHI nodes that expect a constant to be available
5841 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5842 BasicBlock *SuccBB = TI->getSuccessor(succ);
5843 if (!isa<PHINode>(SuccBB->begin())) continue;
5844 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5846 // If this terminator has multiple identical successors (common for
5847 // switches), only handle each succ once.
5848 if (!SuccsHandled.insert(SuccMBB)) continue;
5850 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5853 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5854 // nodes and Machine PHI nodes, but the incoming operands have not been
5856 for (BasicBlock::iterator I = SuccBB->begin();
5857 (PN = dyn_cast<PHINode>(I)); ++I) {
5858 // Ignore dead phi's.
5859 if (PN->use_empty()) continue;
5862 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5864 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5865 unsigned &RegOut = SDL->ConstantsOut[C];
5867 RegOut = FuncInfo->CreateRegForValue(C);
5868 SDL->CopyValueToVirtualRegister(C, RegOut);
5872 Reg = FuncInfo->ValueMap[PHIOp];
5874 assert(isa<AllocaInst>(PHIOp) &&
5875 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5876 "Didn't codegen value into a register!??");
5877 Reg = FuncInfo->CreateRegForValue(PHIOp);
5878 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5882 // Remember that this register needs to added to the machine PHI node as
5883 // the input for this MBB.
5884 SmallVector<MVT, 4> ValueVTs;
5885 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5886 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5887 MVT VT = ValueVTs[vti];
5888 unsigned NumRegisters = TLI.getNumRegisters(VT);
5889 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5890 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5891 Reg += NumRegisters;
5895 SDL->ConstantsOut.clear();
5898 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5899 /// supports legal types, and it emits MachineInstrs directly instead of
5900 /// creating SelectionDAG nodes.
5903 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5905 TerminatorInst *TI = LLVMBB->getTerminator();
5907 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5908 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5910 // Check successor nodes' PHI nodes that expect a constant to be available
5912 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5913 BasicBlock *SuccBB = TI->getSuccessor(succ);
5914 if (!isa<PHINode>(SuccBB->begin())) continue;
5915 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5917 // If this terminator has multiple identical successors (common for
5918 // switches), only handle each succ once.
5919 if (!SuccsHandled.insert(SuccMBB)) continue;
5921 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5924 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5925 // nodes and Machine PHI nodes, but the incoming operands have not been
5927 for (BasicBlock::iterator I = SuccBB->begin();
5928 (PN = dyn_cast<PHINode>(I)); ++I) {
5929 // Ignore dead phi's.
5930 if (PN->use_empty()) continue;
5932 // Only handle legal types. Two interesting things to note here. First,
5933 // by bailing out early, we may leave behind some dead instructions,
5934 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5935 // own moves. Second, this check is necessary becuase FastISel doesn't
5936 // use CreateRegForValue to create registers, so it always creates
5937 // exactly one register for each non-void instruction.
5938 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5939 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5942 VT = TLI.getTypeToTransformTo(VT);
5944 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5949 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5951 unsigned Reg = F->getRegForValue(PHIOp);
5953 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5956 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));