1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 /// LimitFloatPrecision - Generate low-precision inline sequences for
58 /// some float libcalls (6, 8 or 12 bits).
59 static unsigned LimitFloatPrecision;
61 static cl::opt<unsigned, true>
62 LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
68 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
69 /// of insertvalue or extractvalue indices that identify a member, return
70 /// the linearized index of the start of the member.
72 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
84 EE = STy->element_end();
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 // We haven't found the type we're looking for, so keep searching.
106 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107 /// MVTs that represent all the individual underlying
108 /// non-aggregate types that comprise it.
110 /// If Offsets is non-null, it points to a vector to be filled in
111 /// with the in-memory offsets of each of the individual values.
113 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
122 EE = STy->element_end();
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
137 // Base case: we can get an MVT for this LLVM IR type.
138 ValueVTs.push_back(TLI.getValueType(Ty));
140 Offsets->push_back(StartingOffset);
144 /// RegsForValue - This struct represents the registers (physical or virtual)
145 /// that a particular set of values is assigned, and the type information about
146 /// the value. The most common situation is to represent one value at a time,
147 /// but struct or array values are handled element-wise as multiple values.
148 /// The splitting of aggregates is performed recursively, so that we never
149 /// have aggregate-typed registers. The values at this point do not necessarily
150 /// have legal types, so each value may require one or more registers of some
153 struct VISIBILITY_HIDDEN RegsForValue {
154 /// TLI - The TargetLowering object.
156 const TargetLowering *TLI;
158 /// ValueVTs - The value types of the values, which may not be legal, and
159 /// may need be promoted or synthesized from one or more registers.
161 SmallVector<MVT, 4> ValueVTs;
163 /// RegVTs - The value types of the registers. This is the same size as
164 /// ValueVTs and it records, for each value, what the type of the assigned
165 /// register or registers are. (Individual values are never synthesized
166 /// from more than one type of register.)
168 /// With virtual registers, the contents of RegVTs is redundant with TLI's
169 /// getRegisterType member function, however when with physical registers
170 /// it is necessary to have a separate record of the types.
172 SmallVector<MVT, 4> RegVTs;
174 /// Regs - This list holds the registers assigned to the values.
175 /// Each legal or promoted value requires one register, and each
176 /// expanded value requires multiple registers.
178 SmallVector<unsigned, 4> Regs;
180 RegsForValue() : TLI(0) {}
182 RegsForValue(const TargetLowering &tli,
183 const SmallVector<unsigned, 4> ®s,
184 MVT regvt, MVT valuevt)
185 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 const SmallVector<MVT, 4> ®vts,
189 const SmallVector<MVT, 4> &valuevts)
190 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 unsigned Reg, const Type *Ty) : TLI(&tli) {
193 ComputeValueVTs(tli, Ty, ValueVTs);
195 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
196 MVT ValueVT = ValueVTs[Value];
197 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
198 MVT RegisterVT = TLI->getRegisterType(ValueVT);
199 for (unsigned i = 0; i != NumRegs; ++i)
200 Regs.push_back(Reg + i);
201 RegVTs.push_back(RegisterVT);
206 /// append - Add the specified values to this one.
207 void append(const RegsForValue &RHS) {
209 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
210 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
211 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
215 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
216 /// this value and returns the result as a ValueVTs value. This uses
217 /// Chain/Flag as the input and updates them for the output Chain/Flag.
218 /// If the Flag pointer is NULL, no flag is used.
219 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
220 SDValue &Chain, SDValue *Flag) const;
222 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
223 /// specified value into the registers specified by this object. This uses
224 /// Chain/Flag as the input and updates them for the output Chain/Flag.
225 /// If the Flag pointer is NULL, no flag is used.
226 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
227 SDValue &Chain, SDValue *Flag) const;
229 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
230 /// operand list. This adds the code marker and includes the number of
231 /// values added into it.
232 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
233 std::vector<SDValue> &Ops) const;
237 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
238 /// PHI nodes or outside of the basic block that defines it, or used by a
239 /// switch or atomic instruction, which may expand to multiple basic blocks.
240 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
241 if (isa<PHINode>(I)) return true;
242 BasicBlock *BB = I->getParent();
243 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
244 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
245 // FIXME: Remove switchinst special case.
246 isa<SwitchInst>(*UI))
251 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252 /// entry block, return true. This includes arguments used by switches, since
253 /// the switch may expand into multiple basic blocks.
254 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
260 return A->use_empty();
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
269 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
273 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
275 bool EnableFastISel) {
278 RegInfo = &MF->getRegInfo();
280 // Create a vreg for each argument register that is not dead and is used
281 // outside of the entry block for the function.
282 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
284 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
285 InitializeRegForValue(AI);
287 // Initialize the mapping of values to registers. This is only set up for
288 // instruction values that are used outside of the block that defines
290 Function::iterator BB = Fn->begin(), EB = Fn->end();
291 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
292 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
293 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
294 const Type *Ty = AI->getAllocatedType();
295 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
297 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
300 TySize *= CUI->getZExtValue(); // Get total allocated size.
301 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
302 StaticAllocaMap[AI] =
303 MF->getFrameInfo()->CreateStackObject(TySize, Align);
306 for (; BB != EB; ++BB)
307 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
308 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
309 if (!isa<AllocaInst>(I) ||
310 !StaticAllocaMap.count(cast<AllocaInst>(I)))
311 InitializeRegForValue(I);
313 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
314 // also creates the initial PHI MachineInstrs, though none of the input
315 // operands are populated.
316 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
317 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
321 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
325 for (BasicBlock::iterator
326 I = BB->begin(), E = BB->end(); I != E; ++I) {
327 if (CallInst *CI = dyn_cast<CallInst>(I)) {
328 if (Function *F = CI->getCalledFunction()) {
329 switch (F->getIntrinsicID()) {
331 case Intrinsic::dbg_stoppoint: {
332 DwarfWriter *DW = DAG.getDwarfWriter();
333 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
335 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
336 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
337 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
339 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
342 DL = DebugLoc::get(idx);
347 case Intrinsic::dbg_func_start: {
348 DwarfWriter *DW = DAG.getDwarfWriter();
350 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
351 Value *SP = FSI->getSubprogram();
353 if (DW->ValidDebugInfo(SP)) {
354 DISubprogram Subprogram(cast<GlobalVariable>(SP));
355 DICompileUnit CU(Subprogram.getCompileUnit());
356 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
358 unsigned Line = Subprogram.getLineNumber();
359 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
369 PN = dyn_cast<PHINode>(I);
370 if (!PN || PN->use_empty()) continue;
372 unsigned PHIReg = ValueMap[PN];
373 assert(PHIReg && "PHI node does not have an assigned virtual register!");
375 SmallVector<MVT, 4> ValueVTs;
376 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
377 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
378 MVT VT = ValueVTs[vti];
379 unsigned NumRegisters = TLI.getNumRegisters(VT);
380 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
381 for (unsigned i = 0; i != NumRegisters; ++i)
382 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
383 PHIReg += NumRegisters;
389 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
390 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
393 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
394 /// the correctly promoted or expanded types. Assign these registers
395 /// consecutive vreg numbers and return the first assigned number.
397 /// In the case that the given value has struct or array type, this function
398 /// will assign registers for each member or element.
400 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
401 SmallVector<MVT, 4> ValueVTs;
402 ComputeValueVTs(TLI, V->getType(), ValueVTs);
404 unsigned FirstReg = 0;
405 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
406 MVT ValueVT = ValueVTs[Value];
407 MVT RegisterVT = TLI.getRegisterType(ValueVT);
409 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
410 for (unsigned i = 0; i != NumRegs; ++i) {
411 unsigned R = MakeReg(RegisterVT);
412 if (!FirstReg) FirstReg = R;
418 /// getCopyFromParts - Create a value that contains the specified legal parts
419 /// combined into the value they represent. If the parts combine to a type
420 /// larger then ValueVT then AssertOp can be used to specify whether the extra
421 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
422 /// (ISD::AssertSext).
423 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
424 const SDValue *Parts,
425 unsigned NumParts, MVT PartVT, MVT ValueVT,
426 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
427 assert(NumParts > 0 && "No parts to assemble!");
428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
429 SDValue Val = Parts[0];
432 // Assemble the value from multiple parts.
433 if (!ValueVT.isVector()) {
434 unsigned PartBits = PartVT.getSizeInBits();
435 unsigned ValueBits = ValueVT.getSizeInBits();
437 // Assemble the power of 2 part.
438 unsigned RoundParts = NumParts & (NumParts - 1) ?
439 1 << Log2_32(NumParts) : NumParts;
440 unsigned RoundBits = PartBits * RoundParts;
441 MVT RoundVT = RoundBits == ValueBits ?
442 ValueVT : MVT::getIntegerVT(RoundBits);
445 MVT HalfVT = ValueVT.isInteger() ?
446 MVT::getIntegerVT(RoundBits/2) :
447 MVT::getFloatingPointVT(RoundBits/2);
449 if (RoundParts > 2) {
450 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
451 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
454 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
455 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
457 if (TLI.isBigEndian())
459 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
461 if (RoundParts < NumParts) {
462 // Assemble the trailing non-power-of-2 part.
463 unsigned OddParts = NumParts - RoundParts;
464 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
465 Hi = getCopyFromParts(DAG, dl,
466 Parts+RoundParts, OddParts, PartVT, OddVT);
468 // Combine the round and odd parts.
470 if (TLI.isBigEndian())
472 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
473 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
474 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
475 DAG.getConstant(Lo.getValueType().getSizeInBits(),
476 TLI.getPointerTy()));
477 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
478 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
481 // Handle a multi-element vector.
482 MVT IntermediateVT, RegisterVT;
483 unsigned NumIntermediates;
485 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
487 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
488 NumParts = NumRegs; // Silence a compiler warning.
489 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
490 assert(RegisterVT == Parts[0].getValueType() &&
491 "Part type doesn't match part!");
493 // Assemble the parts into intermediate operands.
494 SmallVector<SDValue, 8> Ops(NumIntermediates);
495 if (NumIntermediates == NumParts) {
496 // If the register was not expanded, truncate or copy the value,
498 for (unsigned i = 0; i != NumParts; ++i)
499 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
500 PartVT, IntermediateVT);
501 } else if (NumParts > 0) {
502 // If the intermediate type was expanded, build the intermediate operands
504 assert(NumParts % NumIntermediates == 0 &&
505 "Must expand into a divisible number of parts!");
506 unsigned Factor = NumParts / NumIntermediates;
507 for (unsigned i = 0; i != NumIntermediates; ++i)
508 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
509 PartVT, IntermediateVT);
512 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
514 Val = DAG.getNode(IntermediateVT.isVector() ?
515 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
516 ValueVT, &Ops[0], NumIntermediates);
520 // There is now one part, held in Val. Correct it to match ValueVT.
521 PartVT = Val.getValueType();
523 if (PartVT == ValueVT)
526 if (PartVT.isVector()) {
527 assert(ValueVT.isVector() && "Unknown vector conversion!");
528 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
531 if (ValueVT.isVector()) {
532 assert(ValueVT.getVectorElementType() == PartVT &&
533 ValueVT.getVectorNumElements() == 1 &&
534 "Only trivial scalar-to-vector conversions should get here!");
535 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
538 if (PartVT.isInteger() &&
539 ValueVT.isInteger()) {
540 if (ValueVT.bitsLT(PartVT)) {
541 // For a truncate, see if we have any information to
542 // indicate whether the truncated bits will always be
543 // zero or sign-extension.
544 if (AssertOp != ISD::DELETED_NODE)
545 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
546 DAG.getValueType(ValueVT));
547 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
549 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
553 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
554 if (ValueVT.bitsLT(Val.getValueType()))
555 // FP_ROUND's are always exact here.
556 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
557 DAG.getIntPtrConstant(1));
558 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
561 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
562 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
564 assert(0 && "Unknown mismatch!");
568 /// getCopyToParts - Create a series of nodes that contain the specified value
569 /// split into legal parts. If the parts contain more bits than Val, then, for
570 /// integers, ExtendKind can be used to specify how to generate the extra bits.
571 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
572 SDValue *Parts, unsigned NumParts, MVT PartVT,
573 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
575 MVT PtrVT = TLI.getPointerTy();
576 MVT ValueVT = Val.getValueType();
577 unsigned PartBits = PartVT.getSizeInBits();
578 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
583 if (!ValueVT.isVector()) {
584 if (PartVT == ValueVT) {
585 assert(NumParts == 1 && "No-op copy with multiple parts!");
590 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
591 // If the parts cover more bits than the value has, promote the value.
592 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
593 assert(NumParts == 1 && "Do not know what to promote to!");
594 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
595 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
596 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
597 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
599 assert(0 && "Unknown mismatch!");
601 } else if (PartBits == ValueVT.getSizeInBits()) {
602 // Different types of the same size.
603 assert(NumParts == 1 && PartVT != ValueVT);
604 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
605 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
606 // If the parts cover less bits than value has, truncate the value.
607 if (PartVT.isInteger() && ValueVT.isInteger()) {
608 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
609 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
611 assert(0 && "Unknown mismatch!");
615 // The value may have changed - recompute ValueVT.
616 ValueVT = Val.getValueType();
617 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
618 "Failed to tile the value with PartVT!");
621 assert(PartVT == ValueVT && "Type conversion failed!");
626 // Expand the value into multiple parts.
627 if (NumParts & (NumParts - 1)) {
628 // The number of parts is not a power of 2. Split off and copy the tail.
629 assert(PartVT.isInteger() && ValueVT.isInteger() &&
630 "Do not know what to expand to!");
631 unsigned RoundParts = 1 << Log2_32(NumParts);
632 unsigned RoundBits = RoundParts * PartBits;
633 unsigned OddParts = NumParts - RoundParts;
634 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
635 DAG.getConstant(RoundBits,
636 TLI.getPointerTy()));
637 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
638 if (TLI.isBigEndian())
639 // The odd parts were reversed by getCopyToParts - unreverse them.
640 std::reverse(Parts + RoundParts, Parts + NumParts);
641 NumParts = RoundParts;
642 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
643 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
646 // The number of parts is a power of 2. Repeatedly bisect the value using
648 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
649 MVT::getIntegerVT(ValueVT.getSizeInBits()),
651 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
652 for (unsigned i = 0; i < NumParts; i += StepSize) {
653 unsigned ThisBits = StepSize * PartBits / 2;
654 MVT ThisVT = MVT::getIntegerVT (ThisBits);
655 SDValue &Part0 = Parts[i];
656 SDValue &Part1 = Parts[i+StepSize/2];
658 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(1, PtrVT));
661 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
663 DAG.getConstant(0, PtrVT));
665 if (ThisBits == PartBits && ThisVT != PartVT) {
666 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
668 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 if (TLI.isBigEndian())
675 std::reverse(Parts, Parts + NumParts);
682 if (PartVT != ValueVT) {
683 if (PartVT.isVector()) {
684 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
686 assert(ValueVT.getVectorElementType() == PartVT &&
687 ValueVT.getVectorNumElements() == 1 &&
688 "Only trivial vector-to-scalar conversions should get here!");
689 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
691 DAG.getConstant(0, PtrVT));
699 // Handle a multi-element vector.
700 MVT IntermediateVT, RegisterVT;
701 unsigned NumIntermediates;
702 unsigned NumRegs = TLI
703 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
705 unsigned NumElements = ValueVT.getVectorNumElements();
707 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
708 NumParts = NumRegs; // Silence a compiler warning.
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
711 // Split the vector into intermediate operands.
712 SmallVector<SDValue, 8> Ops(NumIntermediates);
713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 if (IntermediateVT.isVector())
715 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
717 DAG.getConstant(i * (NumElements / NumIntermediates),
720 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
722 DAG.getConstant(i, PtrVT));
724 // Split the intermediate operands into legal parts.
725 if (NumParts == NumIntermediates) {
726 // If the register was not expanded, promote or copy the value,
728 for (unsigned i = 0; i != NumParts; ++i)
729 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
730 } else if (NumParts > 0) {
731 // If the intermediate type was expanded, split each the value into
733 assert(NumParts % NumIntermediates == 0 &&
734 "Must expand into a divisible number of parts!");
735 unsigned Factor = NumParts / NumIntermediates;
736 for (unsigned i = 0; i != NumIntermediates; ++i)
737 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
742 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
745 TD = DAG.getTarget().getTargetData();
748 /// clear - Clear out the curret SelectionDAG and the associated
749 /// state and prepare this SelectionDAGLowering object to be used
750 /// for a new block. This doesn't clear out information about
751 /// additional blocks that are needed to complete switch lowering
752 /// or PHI node updating; that information is cleared out as it is
754 void SelectionDAGLowering::clear() {
756 PendingLoads.clear();
757 PendingExports.clear();
761 /// getRoot - Return the current virtual root of the Selection DAG,
762 /// flushing any PendingLoad items. This must be done before emitting
763 /// a store or any other node that may need to be ordered after any
764 /// prior load instructions.
766 SDValue SelectionDAGLowering::getRoot() {
767 if (PendingLoads.empty())
768 return DAG.getRoot();
770 if (PendingLoads.size() == 1) {
771 SDValue Root = PendingLoads[0];
773 PendingLoads.clear();
777 // Otherwise, we have to make a token factor node.
778 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
779 &PendingLoads[0], PendingLoads.size());
780 PendingLoads.clear();
785 /// getControlRoot - Similar to getRoot, but instead of flushing all the
786 /// PendingLoad items, flush all the PendingExports items. It is necessary
787 /// to do this before emitting a terminator instruction.
789 SDValue SelectionDAGLowering::getControlRoot() {
790 SDValue Root = DAG.getRoot();
792 if (PendingExports.empty())
795 // Turn all of the CopyToReg chains into one factored node.
796 if (Root.getOpcode() != ISD::EntryToken) {
797 unsigned i = 0, e = PendingExports.size();
798 for (; i != e; ++i) {
799 assert(PendingExports[i].getNode()->getNumOperands() > 1);
800 if (PendingExports[i].getNode()->getOperand(0) == Root)
801 break; // Don't add the root if we already indirectly depend on it.
805 PendingExports.push_back(Root);
808 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
810 PendingExports.size());
811 PendingExports.clear();
816 void SelectionDAGLowering::visit(Instruction &I) {
817 visit(I.getOpcode(), I);
820 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
821 // Note: this doesn't use InstVisitor, because it has to work with
822 // ConstantExpr's in addition to instructions.
824 default: assert(0 && "Unknown instruction type encountered!");
826 // Build the switch statement using the Instruction.def file.
827 #define HANDLE_INST(NUM, OPCODE, CLASS) \
828 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
829 #include "llvm/Instruction.def"
833 void SelectionDAGLowering::visitAdd(User &I) {
834 if (I.getType()->isFPOrFPVector())
835 visitBinary(I, ISD::FADD);
837 visitBinary(I, ISD::ADD);
840 void SelectionDAGLowering::visitMul(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FMUL);
844 visitBinary(I, ISD::MUL);
847 SDValue SelectionDAGLowering::getValue(const Value *V) {
848 SDValue &N = NodeMap[V];
849 if (N.getNode()) return N;
851 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
852 MVT VT = TLI.getValueType(V->getType(), true);
854 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
855 return N = DAG.getConstant(*CI, VT);
857 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
858 return N = DAG.getGlobalAddress(GV, VT);
860 if (isa<ConstantPointerNull>(C))
861 return N = DAG.getConstant(0, TLI.getPointerTy());
863 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
864 return N = DAG.getConstantFP(*CFP, VT);
866 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
867 !V->getType()->isAggregateType())
868 return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
870 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
871 visit(CE->getOpcode(), *CE);
872 SDValue N1 = NodeMap[V];
873 assert(N1.getNode() && "visit didn't populate the ValueMap!");
877 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
878 SmallVector<SDValue, 4> Constants;
879 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
881 SDNode *Val = getValue(*OI).getNode();
882 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
883 Constants.push_back(SDValue(Val, i));
885 return DAG.getMergeValues(&Constants[0], Constants.size());
888 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
889 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
890 "Unknown struct or array constant!");
892 SmallVector<MVT, 4> ValueVTs;
893 ComputeValueVTs(TLI, C->getType(), ValueVTs);
894 unsigned NumElts = ValueVTs.size();
896 return SDValue(); // empty struct
897 SmallVector<SDValue, 4> Constants(NumElts);
898 for (unsigned i = 0; i != NumElts; ++i) {
899 MVT EltVT = ValueVTs[i];
900 if (isa<UndefValue>(C))
901 Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
902 else if (EltVT.isFloatingPoint())
903 Constants[i] = DAG.getConstantFP(0, EltVT);
905 Constants[i] = DAG.getConstant(0, EltVT);
907 return DAG.getMergeValues(&Constants[0], NumElts);
910 const VectorType *VecTy = cast<VectorType>(V->getType());
911 unsigned NumElements = VecTy->getNumElements();
913 // Now that we know the number and type of the elements, get that number of
914 // elements into the Ops array based on what kind of constant it is.
915 SmallVector<SDValue, 16> Ops;
916 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
917 for (unsigned i = 0; i != NumElements; ++i)
918 Ops.push_back(getValue(CP->getOperand(i)));
920 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
921 "Unknown vector constant!");
922 MVT EltVT = TLI.getValueType(VecTy->getElementType());
925 if (isa<UndefValue>(C))
926 Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
927 else if (EltVT.isFloatingPoint())
928 Op = DAG.getConstantFP(0, EltVT);
930 Op = DAG.getConstant(0, EltVT);
931 Ops.assign(NumElements, Op);
934 // Create a BUILD_VECTOR node.
935 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
936 VT, &Ops[0], Ops.size());
939 // If this is a static alloca, generate it as the frameindex instead of
941 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
942 DenseMap<const AllocaInst*, int>::iterator SI =
943 FuncInfo.StaticAllocaMap.find(AI);
944 if (SI != FuncInfo.StaticAllocaMap.end())
945 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
948 unsigned InReg = FuncInfo.ValueMap[V];
949 assert(InReg && "Value not in map!");
951 RegsForValue RFV(TLI, InReg, V->getType());
952 SDValue Chain = DAG.getEntryNode();
953 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
957 void SelectionDAGLowering::visitRet(ReturnInst &I) {
958 if (I.getNumOperands() == 0) {
959 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
960 MVT::Other, getControlRoot()));
964 SmallVector<SDValue, 8> NewValues;
965 NewValues.push_back(getControlRoot());
966 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
967 SmallVector<MVT, 4> ValueVTs;
968 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
969 unsigned NumValues = ValueVTs.size();
970 if (NumValues == 0) continue;
972 SDValue RetOp = getValue(I.getOperand(i));
973 for (unsigned j = 0, f = NumValues; j != f; ++j) {
974 MVT VT = ValueVTs[j];
976 // FIXME: C calling convention requires the return type to be promoted to
977 // at least 32-bit. But this is not necessary for non-C calling
979 if (VT.isInteger()) {
980 MVT MinVT = TLI.getRegisterType(MVT::i32);
981 if (VT.bitsLT(MinVT))
985 unsigned NumParts = TLI.getNumRegisters(VT);
986 MVT PartVT = TLI.getRegisterType(VT);
987 SmallVector<SDValue, 4> Parts(NumParts);
988 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
990 const Function *F = I.getParent()->getParent();
991 if (F->paramHasAttr(0, Attribute::SExt))
992 ExtendKind = ISD::SIGN_EXTEND;
993 else if (F->paramHasAttr(0, Attribute::ZExt))
994 ExtendKind = ISD::ZERO_EXTEND;
996 getCopyToParts(DAG, getCurDebugLoc(),
997 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
998 &Parts[0], NumParts, PartVT, ExtendKind);
1000 // 'inreg' on function refers to return value
1001 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1002 if (F->paramHasAttr(0, Attribute::InReg))
1004 for (unsigned i = 0; i < NumParts; ++i) {
1005 NewValues.push_back(Parts[i]);
1006 NewValues.push_back(DAG.getArgFlags(Flags));
1010 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1011 &NewValues[0], NewValues.size()));
1014 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1015 /// the current basic block, add it to ValueMap now so that we'll get a
1017 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1018 // No need to export constants.
1019 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1021 // Already exported?
1022 if (FuncInfo.isExportedInst(V)) return;
1024 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1025 CopyValueToVirtualRegister(V, Reg);
1028 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1029 const BasicBlock *FromBB) {
1030 // The operands of the setcc have to be in this block. We don't know
1031 // how to export them from some other block.
1032 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1033 // Can export from current BB.
1034 if (VI->getParent() == FromBB)
1037 // Is already exported, noop.
1038 return FuncInfo.isExportedInst(V);
1041 // If this is an argument, we can export it if the BB is the entry block or
1042 // if it is already exported.
1043 if (isa<Argument>(V)) {
1044 if (FromBB == &FromBB->getParent()->getEntryBlock())
1047 // Otherwise, can only export this if it is already exported.
1048 return FuncInfo.isExportedInst(V);
1051 // Otherwise, constants can always be exported.
1055 static bool InBlock(const Value *V, const BasicBlock *BB) {
1056 if (const Instruction *I = dyn_cast<Instruction>(V))
1057 return I->getParent() == BB;
1061 /// getFCmpCondCode - Return the ISD condition code corresponding to
1062 /// the given LLVM IR floating-point condition code. This includes
1063 /// consideration of global floating-point math flags.
1065 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1066 ISD::CondCode FPC, FOC;
1068 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1069 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1070 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1071 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1072 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1073 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1074 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1075 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1076 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1077 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1078 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1079 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1080 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1081 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1082 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1083 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1085 assert(0 && "Invalid FCmp predicate opcode!");
1086 FOC = FPC = ISD::SETFALSE;
1089 if (FiniteOnlyFPMath())
1095 /// getICmpCondCode - Return the ISD condition code corresponding to
1096 /// the given LLVM IR integer condition code.
1098 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1100 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1101 case ICmpInst::ICMP_NE: return ISD::SETNE;
1102 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1103 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1104 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1105 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1106 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1107 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1108 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1109 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1111 assert(0 && "Invalid ICmp predicate opcode!");
1116 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1117 /// This function emits a branch and is used at the leaves of an OR or an
1118 /// AND operator tree.
1121 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1122 MachineBasicBlock *TBB,
1123 MachineBasicBlock *FBB,
1124 MachineBasicBlock *CurBB) {
1125 const BasicBlock *BB = CurBB->getBasicBlock();
1127 // If the leaf of the tree is a comparison, merge the condition into
1129 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1130 // The operands of the cmp have to be in this block. We don't know
1131 // how to export them from some other block. If this is the first block
1132 // of the sequence, no exporting is needed.
1133 if (CurBB == CurMBB ||
1134 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1135 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1136 ISD::CondCode Condition;
1137 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1138 Condition = getICmpCondCode(IC->getPredicate());
1139 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1140 Condition = getFCmpCondCode(FC->getPredicate());
1142 Condition = ISD::SETEQ; // silence warning.
1143 assert(0 && "Unknown compare instruction");
1146 CaseBlock CB(Condition, BOp->getOperand(0),
1147 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1148 SwitchCases.push_back(CB);
1153 // Create a CaseBlock record representing this branch.
1154 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1155 NULL, TBB, FBB, CurBB);
1156 SwitchCases.push_back(CB);
1159 /// FindMergedConditions - If Cond is an expression like
1160 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1161 MachineBasicBlock *TBB,
1162 MachineBasicBlock *FBB,
1163 MachineBasicBlock *CurBB,
1165 // If this node is not part of the or/and tree, emit it as a branch.
1166 Instruction *BOp = dyn_cast<Instruction>(Cond);
1167 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1168 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1169 BOp->getParent() != CurBB->getBasicBlock() ||
1170 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1171 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1172 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1176 // Create TmpBB after CurBB.
1177 MachineFunction::iterator BBI = CurBB;
1178 MachineFunction &MF = DAG.getMachineFunction();
1179 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1180 CurBB->getParent()->insert(++BBI, TmpBB);
1182 if (Opc == Instruction::Or) {
1183 // Codegen X | Y as:
1191 // Emit the LHS condition.
1192 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1194 // Emit the RHS condition into TmpBB.
1195 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1197 assert(Opc == Instruction::And && "Unknown merge op!");
1198 // Codegen X & Y as:
1205 // This requires creation of TmpBB after CurBB.
1207 // Emit the LHS condition.
1208 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1210 // Emit the RHS condition into TmpBB.
1211 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1215 /// If the set of cases should be emitted as a series of branches, return true.
1216 /// If we should emit this as a bunch of and/or'd together conditions, return
1219 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1220 if (Cases.size() != 2) return true;
1222 // If this is two comparisons of the same values or'd or and'd together, they
1223 // will get folded into a single comparison, so don't emit two blocks.
1224 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1225 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1226 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1227 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1234 void SelectionDAGLowering::visitBr(BranchInst &I) {
1235 // Update machine-CFG edges.
1236 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1238 // Figure out which block is immediately after the current one.
1239 MachineBasicBlock *NextBlock = 0;
1240 MachineFunction::iterator BBI = CurMBB;
1241 if (++BBI != CurMBB->getParent()->end())
1244 if (I.isUnconditional()) {
1245 // Update machine-CFG edges.
1246 CurMBB->addSuccessor(Succ0MBB);
1248 // If this is not a fall-through branch, emit the branch.
1249 if (Succ0MBB != NextBlock)
1250 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1251 MVT::Other, getControlRoot(),
1252 DAG.getBasicBlock(Succ0MBB)));
1256 // If this condition is one of the special cases we handle, do special stuff
1258 Value *CondVal = I.getCondition();
1259 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1261 // If this is a series of conditions that are or'd or and'd together, emit
1262 // this as a sequence of branches instead of setcc's with and/or operations.
1263 // For example, instead of something like:
1276 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1277 if (BOp->hasOneUse() &&
1278 (BOp->getOpcode() == Instruction::And ||
1279 BOp->getOpcode() == Instruction::Or)) {
1280 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1281 // If the compares in later blocks need to use values not currently
1282 // exported from this block, export them now. This block should always
1283 // be the first entry.
1284 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1286 // Allow some cases to be rejected.
1287 if (ShouldEmitAsBranches(SwitchCases)) {
1288 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1289 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1290 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1293 // Emit the branch for this block.
1294 visitSwitchCase(SwitchCases[0]);
1295 SwitchCases.erase(SwitchCases.begin());
1299 // Okay, we decided not to do this, remove any inserted MBB's and clear
1301 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1302 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1304 SwitchCases.clear();
1308 // Create a CaseBlock record representing this branch.
1309 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1310 NULL, Succ0MBB, Succ1MBB, CurMBB);
1311 // Use visitSwitchCase to actually insert the fast branch sequence for this
1313 visitSwitchCase(CB);
1316 /// visitSwitchCase - Emits the necessary code to represent a single node in
1317 /// the binary search tree resulting from lowering a switch instruction.
1318 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1320 SDValue CondLHS = getValue(CB.CmpLHS);
1321 DebugLoc dl = getCurDebugLoc();
1323 // Build the setcc now.
1324 if (CB.CmpMHS == NULL) {
1325 // Fold "(X == true)" to X and "(X == false)" to !X to
1326 // handle common cases produced by branch lowering.
1327 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1329 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1330 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1331 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1333 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1335 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1337 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1338 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1340 SDValue CmpOp = getValue(CB.CmpMHS);
1341 MVT VT = CmpOp.getValueType();
1343 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1344 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1347 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1348 VT, CmpOp, DAG.getConstant(Low, VT));
1349 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1350 DAG.getConstant(High-Low, VT), ISD::SETULE);
1354 // Update successor info
1355 CurMBB->addSuccessor(CB.TrueBB);
1356 CurMBB->addSuccessor(CB.FalseBB);
1358 // Set NextBlock to be the MBB immediately after the current one, if any.
1359 // This is used to avoid emitting unnecessary branches to the next block.
1360 MachineBasicBlock *NextBlock = 0;
1361 MachineFunction::iterator BBI = CurMBB;
1362 if (++BBI != CurMBB->getParent()->end())
1365 // If the lhs block is the next block, invert the condition so that we can
1366 // fall through to the lhs instead of the rhs block.
1367 if (CB.TrueBB == NextBlock) {
1368 std::swap(CB.TrueBB, CB.FalseBB);
1369 SDValue True = DAG.getConstant(1, Cond.getValueType());
1370 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1372 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1373 MVT::Other, getControlRoot(), Cond,
1374 DAG.getBasicBlock(CB.TrueBB));
1376 // If the branch was constant folded, fix up the CFG.
1377 if (BrCond.getOpcode() == ISD::BR) {
1378 CurMBB->removeSuccessor(CB.FalseBB);
1379 DAG.setRoot(BrCond);
1381 // Otherwise, go ahead and insert the false branch.
1382 if (BrCond == getControlRoot())
1383 CurMBB->removeSuccessor(CB.TrueBB);
1385 if (CB.FalseBB == NextBlock)
1386 DAG.setRoot(BrCond);
1388 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1389 DAG.getBasicBlock(CB.FalseBB)));
1393 /// visitJumpTable - Emit JumpTable node in the current MBB
1394 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1395 // Emit the code for the jump table
1396 assert(JT.Reg != -1U && "Should lower JT Header first!");
1397 MVT PTy = TLI.getPointerTy();
1398 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1400 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1401 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1402 MVT::Other, Index.getValue(1),
1406 /// visitJumpTableHeader - This function emits necessary code to produce index
1407 /// in the JumpTable from switch case.
1408 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1409 JumpTableHeader &JTH) {
1410 // Subtract the lowest switch case value from the value being switched on and
1411 // conditional branch to default mbb if the result is greater than the
1412 // difference between smallest and largest cases.
1413 SDValue SwitchOp = getValue(JTH.SValue);
1414 MVT VT = SwitchOp.getValueType();
1415 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1416 DAG.getConstant(JTH.First, VT));
1418 // The SDNode we just created, which holds the value being switched on minus
1419 // the the smallest case value, needs to be copied to a virtual register so it
1420 // can be used as an index into the jump table in a subsequent basic block.
1421 // This value may be smaller or larger than the target's pointer type, and
1422 // therefore require extension or truncating.
1423 if (VT.bitsGT(TLI.getPointerTy()))
1424 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1425 TLI.getPointerTy(), SUB);
1427 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1428 TLI.getPointerTy(), SUB);
1430 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1431 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1432 JumpTableReg, SwitchOp);
1433 JT.Reg = JumpTableReg;
1435 // Emit the range check for the jump table, and branch to the default block
1436 // for the switch statement if the value being switched on exceeds the largest
1437 // case in the switch.
1438 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1439 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1440 DAG.getConstant(JTH.Last-JTH.First,VT),
1443 // Set NextBlock to be the MBB immediately after the current one, if any.
1444 // This is used to avoid emitting unnecessary branches to the next block.
1445 MachineBasicBlock *NextBlock = 0;
1446 MachineFunction::iterator BBI = CurMBB;
1447 if (++BBI != CurMBB->getParent()->end())
1450 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1451 MVT::Other, CopyTo, CMP,
1452 DAG.getBasicBlock(JT.Default));
1454 if (JT.MBB == NextBlock)
1455 DAG.setRoot(BrCond);
1457 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1458 DAG.getBasicBlock(JT.MBB)));
1461 /// visitBitTestHeader - This function emits necessary code to produce value
1462 /// suitable for "bit tests"
1463 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1464 // Subtract the minimum value
1465 SDValue SwitchOp = getValue(B.SValue);
1466 MVT VT = SwitchOp.getValueType();
1467 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1468 DAG.getConstant(B.First, VT));
1471 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1472 TLI.getSetCCResultType(SUB.getValueType()),
1473 SUB, DAG.getConstant(B.Range, VT),
1477 if (VT.bitsGT(TLI.getPointerTy()))
1478 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1479 TLI.getPointerTy(), SUB);
1481 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1482 TLI.getPointerTy(), SUB);
1484 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1485 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = CurMBB;
1492 if (++BBI != CurMBB->getParent()->end())
1495 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1497 CurMBB->addSuccessor(B.Default);
1498 CurMBB->addSuccessor(MBB);
1500 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1501 MVT::Other, CopyTo, RangeCmp,
1502 DAG.getBasicBlock(B.Default));
1504 if (MBB == NextBlock)
1505 DAG.setRoot(BrRange);
1507 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1508 DAG.getBasicBlock(MBB)));
1511 /// visitBitTestCase - this function produces one "bit test"
1512 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1515 // Make desired shift
1516 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1517 TLI.getPointerTy());
1518 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1520 DAG.getConstant(1, TLI.getPointerTy()),
1523 // Emit bit tests and jumps
1524 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1525 TLI.getPointerTy(), SwitchVal,
1526 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1527 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1528 TLI.getSetCCResultType(AndOp.getValueType()),
1529 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1532 CurMBB->addSuccessor(B.TargetBB);
1533 CurMBB->addSuccessor(NextMBB);
1535 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1536 MVT::Other, getControlRoot(),
1537 AndCmp, DAG.getBasicBlock(B.TargetBB));
1539 // Set NextBlock to be the MBB immediately after the current one, if any.
1540 // This is used to avoid emitting unnecessary branches to the next block.
1541 MachineBasicBlock *NextBlock = 0;
1542 MachineFunction::iterator BBI = CurMBB;
1543 if (++BBI != CurMBB->getParent()->end())
1546 if (NextMBB == NextBlock)
1549 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1550 DAG.getBasicBlock(NextMBB)));
1553 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1554 // Retrieve successors.
1555 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1556 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1558 const Value *Callee(I.getCalledValue());
1559 if (isa<InlineAsm>(Callee))
1562 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1564 // If the value of the invoke is used outside of its defining block, make it
1565 // available as a virtual register.
1566 if (!I.use_empty()) {
1567 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1568 if (VMI != FuncInfo.ValueMap.end())
1569 CopyValueToVirtualRegister(&I, VMI->second);
1572 // Update successor info
1573 CurMBB->addSuccessor(Return);
1574 CurMBB->addSuccessor(LandingPad);
1576 // Drop into normal successor.
1577 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1578 MVT::Other, getControlRoot(),
1579 DAG.getBasicBlock(Return)));
1582 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1585 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1586 /// small case ranges).
1587 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1588 CaseRecVector& WorkList,
1590 MachineBasicBlock* Default) {
1591 Case& BackCase = *(CR.Range.second-1);
1593 // Size is the number of Cases represented by this range.
1594 size_t Size = CR.Range.second - CR.Range.first;
1598 // Get the MachineFunction which holds the current MBB. This is used when
1599 // inserting any additional MBBs necessary to represent the switch.
1600 MachineFunction *CurMF = CurMBB->getParent();
1602 // Figure out which block is immediately after the current one.
1603 MachineBasicBlock *NextBlock = 0;
1604 MachineFunction::iterator BBI = CR.CaseBB;
1606 if (++BBI != CurMBB->getParent()->end())
1609 // TODO: If any two of the cases has the same destination, and if one value
1610 // is the same as the other, but has one bit unset that the other has set,
1611 // use bit manipulation to do two compares at once. For example:
1612 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1614 // Rearrange the case blocks so that the last one falls through if possible.
1615 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1616 // The last case block won't fall through into 'NextBlock' if we emit the
1617 // branches in this order. See if rearranging a case value would help.
1618 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1619 if (I->BB == NextBlock) {
1620 std::swap(*I, BackCase);
1626 // Create a CaseBlock record representing a conditional branch to
1627 // the Case's target mbb if the value being switched on SV is equal
1629 MachineBasicBlock *CurBlock = CR.CaseBB;
1630 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1631 MachineBasicBlock *FallThrough;
1633 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1634 CurMF->insert(BBI, FallThrough);
1636 // If the last case doesn't match, go to the default block.
1637 FallThrough = Default;
1640 Value *RHS, *LHS, *MHS;
1642 if (I->High == I->Low) {
1643 // This is just small small case range :) containing exactly 1 case
1645 LHS = SV; RHS = I->High; MHS = NULL;
1648 LHS = I->Low; MHS = SV; RHS = I->High;
1650 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1652 // If emitting the first comparison, just call visitSwitchCase to emit the
1653 // code into the current block. Otherwise, push the CaseBlock onto the
1654 // vector to be later processed by SDISel, and insert the node's MBB
1655 // before the next MBB.
1656 if (CurBlock == CurMBB)
1657 visitSwitchCase(CB);
1659 SwitchCases.push_back(CB);
1661 CurBlock = FallThrough;
1667 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1668 return !DisableJumpTables &&
1669 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1670 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1673 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1674 APInt LastExt(Last), FirstExt(First);
1675 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1676 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1677 return (LastExt - FirstExt + 1ULL);
1680 /// handleJTSwitchCase - Emit jumptable for current switch case range
1681 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1682 CaseRecVector& WorkList,
1684 MachineBasicBlock* Default) {
1685 Case& FrontCase = *CR.Range.first;
1686 Case& BackCase = *(CR.Range.second-1);
1688 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1689 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1692 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1696 if (!areJTsAllowed(TLI) || TSize <= 3)
1699 APInt Range = ComputeRange(First, Last);
1700 double Density = (double)TSize / Range.roundToDouble();
1704 DEBUG(errs() << "Lowering jump table\n"
1705 << "First entry: " << First << ". Last entry: " << Last << '\n'
1706 << "Range: " << Range
1707 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1709 // Get the MachineFunction which holds the current MBB. This is used when
1710 // inserting any additional MBBs necessary to represent the switch.
1711 MachineFunction *CurMF = CurMBB->getParent();
1713 // Figure out which block is immediately after the current one.
1714 MachineBasicBlock *NextBlock = 0;
1715 MachineFunction::iterator BBI = CR.CaseBB;
1717 if (++BBI != CurMBB->getParent()->end())
1720 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1722 // Create a new basic block to hold the code for loading the address
1723 // of the jump table, and jumping to it. Update successor information;
1724 // we will either branch to the default case for the switch, or the jump
1726 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1727 CurMF->insert(BBI, JumpTableBB);
1728 CR.CaseBB->addSuccessor(Default);
1729 CR.CaseBB->addSuccessor(JumpTableBB);
1731 // Build a vector of destination BBs, corresponding to each target
1732 // of the jump table. If the value of the jump table slot corresponds to
1733 // a case statement, push the case's BB onto the vector, otherwise, push
1735 std::vector<MachineBasicBlock*> DestBBs;
1737 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1738 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1739 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1741 if (Low.sle(TEI) && TEI.sle(High)) {
1742 DestBBs.push_back(I->BB);
1746 DestBBs.push_back(Default);
1750 // Update successor info. Add one edge to each unique successor.
1751 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1752 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1753 E = DestBBs.end(); I != E; ++I) {
1754 if (!SuccsHandled[(*I)->getNumber()]) {
1755 SuccsHandled[(*I)->getNumber()] = true;
1756 JumpTableBB->addSuccessor(*I);
1760 // Create a jump table index for this jump table, or return an existing
1762 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1764 // Set the jump table information so that we can codegen it as a second
1765 // MachineBasicBlock
1766 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1767 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1768 if (CR.CaseBB == CurMBB)
1769 visitJumpTableHeader(JT, JTH);
1771 JTCases.push_back(JumpTableBlock(JTH, JT));
1776 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1778 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1779 CaseRecVector& WorkList,
1781 MachineBasicBlock* Default) {
1782 // Get the MachineFunction which holds the current MBB. This is used when
1783 // inserting any additional MBBs necessary to represent the switch.
1784 MachineFunction *CurMF = CurMBB->getParent();
1786 // Figure out which block is immediately after the current one.
1787 MachineBasicBlock *NextBlock = 0;
1788 MachineFunction::iterator BBI = CR.CaseBB;
1790 if (++BBI != CurMBB->getParent()->end())
1793 Case& FrontCase = *CR.Range.first;
1794 Case& BackCase = *(CR.Range.second-1);
1795 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1797 // Size is the number of Cases represented by this range.
1798 unsigned Size = CR.Range.second - CR.Range.first;
1800 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1801 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1803 CaseItr Pivot = CR.Range.first + Size/2;
1805 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1806 // (heuristically) allow us to emit JumpTable's later.
1808 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1812 size_t LSize = FrontCase.size();
1813 size_t RSize = TSize-LSize;
1814 DEBUG(errs() << "Selecting best pivot: \n"
1815 << "First: " << First << ", Last: " << Last <<'\n'
1816 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1817 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1819 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1820 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1821 APInt Range = ComputeRange(LEnd, RBegin);
1822 assert((Range - 2ULL).isNonNegative() &&
1823 "Invalid case distance");
1824 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1825 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1826 double Metric = Range.logBase2()*(LDensity+RDensity);
1827 // Should always split in some non-trivial place
1828 DEBUG(errs() <<"=>Step\n"
1829 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1830 << "LDensity: " << LDensity
1831 << ", RDensity: " << RDensity << '\n'
1832 << "Metric: " << Metric << '\n');
1833 if (FMetric < Metric) {
1836 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1842 if (areJTsAllowed(TLI)) {
1843 // If our case is dense we *really* should handle it earlier!
1844 assert((FMetric > 0) && "Should handle dense range earlier!");
1846 Pivot = CR.Range.first + Size/2;
1849 CaseRange LHSR(CR.Range.first, Pivot);
1850 CaseRange RHSR(Pivot, CR.Range.second);
1851 Constant *C = Pivot->Low;
1852 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1854 // We know that we branch to the LHS if the Value being switched on is
1855 // less than the Pivot value, C. We use this to optimize our binary
1856 // tree a bit, by recognizing that if SV is greater than or equal to the
1857 // LHS's Case Value, and that Case Value is exactly one less than the
1858 // Pivot's Value, then we can branch directly to the LHS's Target,
1859 // rather than creating a leaf node for it.
1860 if ((LHSR.second - LHSR.first) == 1 &&
1861 LHSR.first->High == CR.GE &&
1862 cast<ConstantInt>(C)->getValue() ==
1863 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1864 TrueBB = LHSR.first->BB;
1866 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1867 CurMF->insert(BBI, TrueBB);
1868 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1871 // Similar to the optimization above, if the Value being switched on is
1872 // known to be less than the Constant CR.LT, and the current Case Value
1873 // is CR.LT - 1, then we can branch directly to the target block for
1874 // the current Case Value, rather than emitting a RHS leaf node for it.
1875 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1876 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1877 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1878 FalseBB = RHSR.first->BB;
1880 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1881 CurMF->insert(BBI, FalseBB);
1882 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1885 // Create a CaseBlock record representing a conditional branch to
1886 // the LHS node if the value being switched on SV is less than C.
1887 // Otherwise, branch to LHS.
1888 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1890 if (CR.CaseBB == CurMBB)
1891 visitSwitchCase(CB);
1893 SwitchCases.push_back(CB);
1898 /// handleBitTestsSwitchCase - if current case range has few destination and
1899 /// range span less, than machine word bitwidth, encode case range into series
1900 /// of masks and emit bit tests with these masks.
1901 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1902 CaseRecVector& WorkList,
1904 MachineBasicBlock* Default){
1905 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1907 Case& FrontCase = *CR.Range.first;
1908 Case& BackCase = *(CR.Range.second-1);
1910 // Get the MachineFunction which holds the current MBB. This is used when
1911 // inserting any additional MBBs necessary to represent the switch.
1912 MachineFunction *CurMF = CurMBB->getParent();
1915 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1917 // Single case counts one, case range - two.
1918 numCmps += (I->Low == I->High ? 1 : 2);
1921 // Count unique destinations
1922 SmallSet<MachineBasicBlock*, 4> Dests;
1923 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1924 Dests.insert(I->BB);
1925 if (Dests.size() > 3)
1926 // Don't bother the code below, if there are too much unique destinations
1929 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1930 << "Total number of comparisons: " << numCmps << '\n');
1932 // Compute span of values.
1933 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1934 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1935 APInt cmpRange = maxValue - minValue;
1937 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1938 << "Low bound: " << minValue << '\n'
1939 << "High bound: " << maxValue << '\n');
1941 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1942 (!(Dests.size() == 1 && numCmps >= 3) &&
1943 !(Dests.size() == 2 && numCmps >= 5) &&
1944 !(Dests.size() >= 3 && numCmps >= 6)))
1947 DEBUG(errs() << "Emitting bit tests\n");
1948 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1950 // Optimize the case where all the case values fit in a
1951 // word without having to subtract minValue. In this case,
1952 // we can optimize away the subtraction.
1953 if (minValue.isNonNegative() &&
1954 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1955 cmpRange = maxValue;
1957 lowBound = minValue;
1960 CaseBitsVector CasesBits;
1961 unsigned i, count = 0;
1963 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1964 MachineBasicBlock* Dest = I->BB;
1965 for (i = 0; i < count; ++i)
1966 if (Dest == CasesBits[i].BB)
1970 assert((count < 3) && "Too much destinations to test!");
1971 CasesBits.push_back(CaseBits(0, Dest, 0));
1975 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1976 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1978 uint64_t lo = (lowValue - lowBound).getZExtValue();
1979 uint64_t hi = (highValue - lowBound).getZExtValue();
1981 for (uint64_t j = lo; j <= hi; j++) {
1982 CasesBits[i].Mask |= 1ULL << j;
1983 CasesBits[i].Bits++;
1987 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1991 // Figure out which block is immediately after the current one.
1992 MachineFunction::iterator BBI = CR.CaseBB;
1995 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1997 DEBUG(errs() << "Cases:\n");
1998 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1999 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2000 << ", Bits: " << CasesBits[i].Bits
2001 << ", BB: " << CasesBits[i].BB << '\n');
2003 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2004 CurMF->insert(BBI, CaseBB);
2005 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2010 BitTestBlock BTB(lowBound, cmpRange, SV,
2011 -1U, (CR.CaseBB == CurMBB),
2012 CR.CaseBB, Default, BTC);
2014 if (CR.CaseBB == CurMBB)
2015 visitBitTestHeader(BTB);
2017 BitTestCases.push_back(BTB);
2023 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2024 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2025 const SwitchInst& SI) {
2028 // Start with "simple" cases
2029 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2030 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2031 Cases.push_back(Case(SI.getSuccessorValue(i),
2032 SI.getSuccessorValue(i),
2035 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2037 // Merge case into clusters
2038 if (Cases.size() >= 2)
2039 // Must recompute end() each iteration because it may be
2040 // invalidated by erase if we hold on to it
2041 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2042 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2043 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2044 MachineBasicBlock* nextBB = J->BB;
2045 MachineBasicBlock* currentBB = I->BB;
2047 // If the two neighboring cases go to the same destination, merge them
2048 // into a single case.
2049 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2057 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2058 if (I->Low != I->High)
2059 // A range counts double, since it requires two compares.
2066 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2067 // Figure out which block is immediately after the current one.
2068 MachineBasicBlock *NextBlock = 0;
2069 MachineFunction::iterator BBI = CurMBB;
2071 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2073 // If there is only the default destination, branch to it if it is not the
2074 // next basic block. Otherwise, just fall through.
2075 if (SI.getNumOperands() == 2) {
2076 // Update machine-CFG edges.
2078 // If this is not a fall-through branch, emit the branch.
2079 CurMBB->addSuccessor(Default);
2080 if (Default != NextBlock)
2081 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2082 MVT::Other, getControlRoot(),
2083 DAG.getBasicBlock(Default)));
2087 // If there are any non-default case statements, create a vector of Cases
2088 // representing each one, and sort the vector so that we can efficiently
2089 // create a binary search tree from them.
2091 size_t numCmps = Clusterify(Cases, SI);
2092 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2093 << ". Total compares: " << numCmps << '\n');
2096 // Get the Value to be switched on and default basic blocks, which will be
2097 // inserted into CaseBlock records, representing basic blocks in the binary
2099 Value *SV = SI.getOperand(0);
2101 // Push the initial CaseRec onto the worklist
2102 CaseRecVector WorkList;
2103 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2105 while (!WorkList.empty()) {
2106 // Grab a record representing a case range to process off the worklist
2107 CaseRec CR = WorkList.back();
2108 WorkList.pop_back();
2110 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2113 // If the range has few cases (two or less) emit a series of specific
2115 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2118 // If the switch has more than 5 blocks, and at least 40% dense, and the
2119 // target supports indirect branches, then emit a jump table rather than
2120 // lowering the switch to a binary tree of conditional branches.
2121 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2124 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2125 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2126 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2131 void SelectionDAGLowering::visitSub(User &I) {
2132 // -0.0 - X --> fneg
2133 const Type *Ty = I.getType();
2134 if (isa<VectorType>(Ty)) {
2135 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2136 const VectorType *DestTy = cast<VectorType>(I.getType());
2137 const Type *ElTy = DestTy->getElementType();
2138 if (ElTy->isFloatingPoint()) {
2139 unsigned VL = DestTy->getNumElements();
2140 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2141 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2143 SDValue Op2 = getValue(I.getOperand(1));
2144 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2145 Op2.getValueType(), Op2));
2151 if (Ty->isFloatingPoint()) {
2152 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2153 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2154 SDValue Op2 = getValue(I.getOperand(1));
2155 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2156 Op2.getValueType(), Op2));
2161 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2164 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2165 SDValue Op1 = getValue(I.getOperand(0));
2166 SDValue Op2 = getValue(I.getOperand(1));
2168 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2169 Op1.getValueType(), Op1, Op2));
2172 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2173 SDValue Op1 = getValue(I.getOperand(0));
2174 SDValue Op2 = getValue(I.getOperand(1));
2175 if (!isa<VectorType>(I.getType())) {
2176 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2177 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2178 TLI.getPointerTy(), Op2);
2179 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2180 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2181 TLI.getPointerTy(), Op2);
2184 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2185 Op1.getValueType(), Op1, Op2));
2188 void SelectionDAGLowering::visitICmp(User &I) {
2189 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2190 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2191 predicate = IC->getPredicate();
2192 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2193 predicate = ICmpInst::Predicate(IC->getPredicate());
2194 SDValue Op1 = getValue(I.getOperand(0));
2195 SDValue Op2 = getValue(I.getOperand(1));
2196 ISD::CondCode Opcode = getICmpCondCode(predicate);
2197 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2200 void SelectionDAGLowering::visitFCmp(User &I) {
2201 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2202 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2203 predicate = FC->getPredicate();
2204 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2205 predicate = FCmpInst::Predicate(FC->getPredicate());
2206 SDValue Op1 = getValue(I.getOperand(0));
2207 SDValue Op2 = getValue(I.getOperand(1));
2208 ISD::CondCode Condition = getFCmpCondCode(predicate);
2209 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2212 void SelectionDAGLowering::visitVICmp(User &I) {
2213 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2214 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2215 predicate = IC->getPredicate();
2216 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2217 predicate = ICmpInst::Predicate(IC->getPredicate());
2218 SDValue Op1 = getValue(I.getOperand(0));
2219 SDValue Op2 = getValue(I.getOperand(1));
2220 ISD::CondCode Opcode = getICmpCondCode(predicate);
2221 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2225 void SelectionDAGLowering::visitVFCmp(User &I) {
2226 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2227 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2228 predicate = FC->getPredicate();
2229 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2230 predicate = FCmpInst::Predicate(FC->getPredicate());
2231 SDValue Op1 = getValue(I.getOperand(0));
2232 SDValue Op2 = getValue(I.getOperand(1));
2233 ISD::CondCode Condition = getFCmpCondCode(predicate);
2234 MVT DestVT = TLI.getValueType(I.getType());
2236 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2239 void SelectionDAGLowering::visitSelect(User &I) {
2240 SmallVector<MVT, 4> ValueVTs;
2241 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2242 unsigned NumValues = ValueVTs.size();
2243 if (NumValues != 0) {
2244 SmallVector<SDValue, 4> Values(NumValues);
2245 SDValue Cond = getValue(I.getOperand(0));
2246 SDValue TrueVal = getValue(I.getOperand(1));
2247 SDValue FalseVal = getValue(I.getOperand(2));
2249 for (unsigned i = 0; i != NumValues; ++i)
2250 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2251 TrueVal.getValueType(), Cond,
2252 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2253 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2255 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2256 DAG.getVTList(&ValueVTs[0], NumValues),
2257 &Values[0], NumValues));
2262 void SelectionDAGLowering::visitTrunc(User &I) {
2263 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2264 SDValue N = getValue(I.getOperand(0));
2265 MVT DestVT = TLI.getValueType(I.getType());
2266 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2269 void SelectionDAGLowering::visitZExt(User &I) {
2270 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2271 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2272 SDValue N = getValue(I.getOperand(0));
2273 MVT DestVT = TLI.getValueType(I.getType());
2274 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2277 void SelectionDAGLowering::visitSExt(User &I) {
2278 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2279 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2280 SDValue N = getValue(I.getOperand(0));
2281 MVT DestVT = TLI.getValueType(I.getType());
2282 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2285 void SelectionDAGLowering::visitFPTrunc(User &I) {
2286 // FPTrunc is never a no-op cast, no need to check
2287 SDValue N = getValue(I.getOperand(0));
2288 MVT DestVT = TLI.getValueType(I.getType());
2289 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2290 DestVT, N, DAG.getIntPtrConstant(0)));
2293 void SelectionDAGLowering::visitFPExt(User &I){
2294 // FPTrunc is never a no-op cast, no need to check
2295 SDValue N = getValue(I.getOperand(0));
2296 MVT DestVT = TLI.getValueType(I.getType());
2297 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2300 void SelectionDAGLowering::visitFPToUI(User &I) {
2301 // FPToUI is never a no-op cast, no need to check
2302 SDValue N = getValue(I.getOperand(0));
2303 MVT DestVT = TLI.getValueType(I.getType());
2304 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2307 void SelectionDAGLowering::visitFPToSI(User &I) {
2308 // FPToSI is never a no-op cast, no need to check
2309 SDValue N = getValue(I.getOperand(0));
2310 MVT DestVT = TLI.getValueType(I.getType());
2311 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2314 void SelectionDAGLowering::visitUIToFP(User &I) {
2315 // UIToFP is never a no-op cast, no need to check
2316 SDValue N = getValue(I.getOperand(0));
2317 MVT DestVT = TLI.getValueType(I.getType());
2318 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2321 void SelectionDAGLowering::visitSIToFP(User &I){
2322 // SIToFP is never a no-op cast, no need to check
2323 SDValue N = getValue(I.getOperand(0));
2324 MVT DestVT = TLI.getValueType(I.getType());
2325 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2328 void SelectionDAGLowering::visitPtrToInt(User &I) {
2329 // What to do depends on the size of the integer and the size of the pointer.
2330 // We can either truncate, zero extend, or no-op, accordingly.
2331 SDValue N = getValue(I.getOperand(0));
2332 MVT SrcVT = N.getValueType();
2333 MVT DestVT = TLI.getValueType(I.getType());
2335 if (DestVT.bitsLT(SrcVT))
2336 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2338 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2339 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2340 setValue(&I, Result);
2343 void SelectionDAGLowering::visitIntToPtr(User &I) {
2344 // What to do depends on the size of the integer and the size of the pointer.
2345 // We can either truncate, zero extend, or no-op, accordingly.
2346 SDValue N = getValue(I.getOperand(0));
2347 MVT SrcVT = N.getValueType();
2348 MVT DestVT = TLI.getValueType(I.getType());
2349 if (DestVT.bitsLT(SrcVT))
2350 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2352 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2353 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2357 void SelectionDAGLowering::visitBitCast(User &I) {
2358 SDValue N = getValue(I.getOperand(0));
2359 MVT DestVT = TLI.getValueType(I.getType());
2361 // BitCast assures us that source and destination are the same size so this
2362 // is either a BIT_CONVERT or a no-op.
2363 if (DestVT != N.getValueType())
2364 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2365 DestVT, N)); // convert types
2367 setValue(&I, N); // noop cast.
2370 void SelectionDAGLowering::visitInsertElement(User &I) {
2371 SDValue InVec = getValue(I.getOperand(0));
2372 SDValue InVal = getValue(I.getOperand(1));
2373 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2375 getValue(I.getOperand(2)));
2377 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2378 TLI.getValueType(I.getType()),
2379 InVec, InVal, InIdx));
2382 void SelectionDAGLowering::visitExtractElement(User &I) {
2383 SDValue InVec = getValue(I.getOperand(0));
2384 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2386 getValue(I.getOperand(1)));
2387 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2388 TLI.getValueType(I.getType()), InVec, InIdx));
2392 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2393 // from SIndx and increasing to the element length (undefs are allowed).
2394 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2395 unsigned MaskNumElts = Mask.getNumOperands();
2396 for (unsigned i = 0; i != MaskNumElts; ++i) {
2397 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2398 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2399 if (Idx != i + SIndx)
2406 void SelectionDAGLowering::visitShuffleVector(User &I) {
2407 SDValue Src1 = getValue(I.getOperand(0));
2408 SDValue Src2 = getValue(I.getOperand(1));
2409 SDValue Mask = getValue(I.getOperand(2));
2411 MVT VT = TLI.getValueType(I.getType());
2412 MVT SrcVT = Src1.getValueType();
2413 int MaskNumElts = Mask.getNumOperands();
2414 int SrcNumElts = SrcVT.getVectorNumElements();
2416 if (SrcNumElts == MaskNumElts) {
2417 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2418 VT, Src1, Src2, Mask));
2422 // Normalize the shuffle vector since mask and vector length don't match.
2423 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2425 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2426 // Mask is longer than the source vectors and is a multiple of the source
2427 // vectors. We can use concatenate vector to make the mask and vectors
2429 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2430 // The shuffle is concatenating two vectors together.
2431 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2436 // Pad both vectors with undefs to make them the same length as the mask.
2437 unsigned NumConcat = MaskNumElts / SrcNumElts;
2438 SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
2440 SDValue* MOps1 = new SDValue[NumConcat];
2441 SDValue* MOps2 = new SDValue[NumConcat];
2444 for (unsigned i = 1; i != NumConcat; ++i) {
2445 MOps1[i] = UndefVal;
2446 MOps2[i] = UndefVal;
2448 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2449 VT, MOps1, NumConcat);
2450 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2451 VT, MOps2, NumConcat);
2456 // Readjust mask for new input vector length.
2457 SmallVector<SDValue, 8> MappedOps;
2458 for (int i = 0; i != MaskNumElts; ++i) {
2459 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2460 MappedOps.push_back(Mask.getOperand(i));
2462 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2463 if (Idx < SrcNumElts)
2464 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2466 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2470 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2471 Mask.getValueType(),
2472 &MappedOps[0], MappedOps.size());
2474 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2475 VT, Src1, Src2, Mask));
2479 if (SrcNumElts > MaskNumElts) {
2480 // Resulting vector is shorter than the incoming vector.
2481 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2482 // Shuffle extracts 1st vector.
2487 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2488 // Shuffle extracts 2nd vector.
2493 // Analyze the access pattern of the vector to see if we can extract
2494 // two subvectors and do the shuffle. The analysis is done by calculating
2495 // the range of elements the mask access on both vectors.
2496 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2497 int MaxRange[2] = {-1, -1};
2499 for (int i = 0; i != MaskNumElts; ++i) {
2500 SDValue Arg = Mask.getOperand(i);
2501 if (Arg.getOpcode() != ISD::UNDEF) {
2502 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2503 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2505 if (Idx >= SrcNumElts) {
2509 if (Idx > MaxRange[Input])
2510 MaxRange[Input] = Idx;
2511 if (Idx < MinRange[Input])
2512 MinRange[Input] = Idx;
2516 // Check if the access is smaller than the vector size and can we find
2517 // a reasonable extract index.
2518 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2519 int StartIdx[2]; // StartIdx to extract from
2520 for (int Input=0; Input < 2; ++Input) {
2521 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2522 RangeUse[Input] = 0; // Unused
2523 StartIdx[Input] = 0;
2524 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2525 // Fits within range but we should see if we can find a good
2526 // start index that is a multiple of the mask length.
2527 if (MaxRange[Input] < MaskNumElts) {
2528 RangeUse[Input] = 1; // Extract from beginning of the vector
2529 StartIdx[Input] = 0;
2531 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2532 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2533 StartIdx[Input] + MaskNumElts < SrcNumElts)
2534 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2539 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2540 setValue(&I, DAG.getNode(ISD::UNDEF,
2541 getCurDebugLoc(), VT)); // Vectors are not used.
2544 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2545 // Extract appropriate subvector and generate a vector shuffle
2546 for (int Input=0; Input < 2; ++Input) {
2547 SDValue& Src = Input == 0 ? Src1 : Src2;
2548 if (RangeUse[Input] == 0) {
2549 Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
2551 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2552 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2555 // Calculate new mask.
2556 SmallVector<SDValue, 8> MappedOps;
2557 for (int i = 0; i != MaskNumElts; ++i) {
2558 SDValue Arg = Mask.getOperand(i);
2559 if (Arg.getOpcode() == ISD::UNDEF) {
2560 MappedOps.push_back(Arg);
2562 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2563 if (Idx < SrcNumElts)
2564 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2566 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2567 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2571 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2572 Mask.getValueType(),
2573 &MappedOps[0], MappedOps.size());
2574 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2575 VT, Src1, Src2, Mask));
2580 // We can't use either concat vectors or extract subvectors so fall back to
2581 // replacing the shuffle with extract and build vector.
2582 // to insert and build vector.
2583 MVT EltVT = VT.getVectorElementType();
2584 MVT PtrVT = TLI.getPointerTy();
2585 SmallVector<SDValue,8> Ops;
2586 for (int i = 0; i != MaskNumElts; ++i) {
2587 SDValue Arg = Mask.getOperand(i);
2588 if (Arg.getOpcode() == ISD::UNDEF) {
2589 Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
2591 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2592 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2593 if (Idx < SrcNumElts)
2594 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2595 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2597 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2599 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2602 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2603 VT, &Ops[0], Ops.size()));
2606 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2607 const Value *Op0 = I.getOperand(0);
2608 const Value *Op1 = I.getOperand(1);
2609 const Type *AggTy = I.getType();
2610 const Type *ValTy = Op1->getType();
2611 bool IntoUndef = isa<UndefValue>(Op0);
2612 bool FromUndef = isa<UndefValue>(Op1);
2614 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2615 I.idx_begin(), I.idx_end());
2617 SmallVector<MVT, 4> AggValueVTs;
2618 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2619 SmallVector<MVT, 4> ValValueVTs;
2620 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2622 unsigned NumAggValues = AggValueVTs.size();
2623 unsigned NumValValues = ValValueVTs.size();
2624 SmallVector<SDValue, 4> Values(NumAggValues);
2626 SDValue Agg = getValue(Op0);
2627 SDValue Val = getValue(Op1);
2629 // Copy the beginning value(s) from the original aggregate.
2630 for (; i != LinearIndex; ++i)
2631 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2633 SDValue(Agg.getNode(), Agg.getResNo() + i);
2634 // Copy values from the inserted value(s).
2635 for (; i != LinearIndex + NumValValues; ++i)
2636 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2638 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2639 // Copy remaining value(s) from the original aggregate.
2640 for (; i != NumAggValues; ++i)
2641 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2643 SDValue(Agg.getNode(), Agg.getResNo() + i);
2645 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2646 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2647 &Values[0], NumAggValues));
2650 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2651 const Value *Op0 = I.getOperand(0);
2652 const Type *AggTy = Op0->getType();
2653 const Type *ValTy = I.getType();
2654 bool OutOfUndef = isa<UndefValue>(Op0);
2656 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2657 I.idx_begin(), I.idx_end());
2659 SmallVector<MVT, 4> ValValueVTs;
2660 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2662 unsigned NumValValues = ValValueVTs.size();
2663 SmallVector<SDValue, 4> Values(NumValValues);
2665 SDValue Agg = getValue(Op0);
2666 // Copy out the selected value(s).
2667 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2668 Values[i - LinearIndex] =
2670 DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2671 Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2672 SDValue(Agg.getNode(), Agg.getResNo() + i);
2674 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2675 DAG.getVTList(&ValValueVTs[0], NumValValues),
2676 &Values[0], NumValValues));
2680 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2681 SDValue N = getValue(I.getOperand(0));
2682 const Type *Ty = I.getOperand(0)->getType();
2684 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2687 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2688 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2691 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2692 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2693 DAG.getIntPtrConstant(Offset));
2695 Ty = StTy->getElementType(Field);
2697 Ty = cast<SequentialType>(Ty)->getElementType();
2699 // If this is a constant subscript, handle it quickly.
2700 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2701 if (CI->getZExtValue() == 0) continue;
2703 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2704 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2705 DAG.getIntPtrConstant(Offs));
2709 // N = N + Idx * ElementSize;
2710 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2711 SDValue IdxN = getValue(Idx);
2713 // If the index is smaller or larger than intptr_t, truncate or extend
2715 if (IdxN.getValueType().bitsLT(N.getValueType()))
2716 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2717 N.getValueType(), IdxN);
2718 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2719 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2720 N.getValueType(), IdxN);
2722 // If this is a multiply by a power of two, turn it into a shl
2723 // immediately. This is a very common case.
2724 if (ElementSize != 1) {
2725 if (isPowerOf2_64(ElementSize)) {
2726 unsigned Amt = Log2_64(ElementSize);
2727 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2728 N.getValueType(), IdxN,
2729 DAG.getConstant(Amt, TLI.getPointerTy()));
2731 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2732 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2733 N.getValueType(), IdxN, Scale);
2737 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2738 N.getValueType(), N, IdxN);
2744 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2745 // If this is a fixed sized alloca in the entry block of the function,
2746 // allocate it statically on the stack.
2747 if (FuncInfo.StaticAllocaMap.count(&I))
2748 return; // getValue will auto-populate this.
2750 const Type *Ty = I.getAllocatedType();
2751 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2753 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2756 SDValue AllocSize = getValue(I.getArraySize());
2757 MVT IntPtr = TLI.getPointerTy();
2758 if (IntPtr.bitsLT(AllocSize.getValueType()))
2759 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2761 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2762 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2765 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
2766 DAG.getIntPtrConstant(TySize));
2768 // Handle alignment. If the requested alignment is less than or equal to
2769 // the stack alignment, ignore it. If the size is greater than or equal to
2770 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2771 unsigned StackAlign =
2772 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2773 if (Align <= StackAlign)
2776 // Round the size of the allocation up to the stack alignment size
2777 // by add SA-1 to the size.
2778 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2779 AllocSize.getValueType(), AllocSize,
2780 DAG.getIntPtrConstant(StackAlign-1));
2781 // Mask out the low bits for alignment purposes.
2782 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2783 AllocSize.getValueType(), AllocSize,
2784 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2786 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2787 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2789 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2792 DAG.setRoot(DSA.getValue(1));
2794 // Inform the Frame Information that we have just allocated a variable-sized
2796 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2799 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2800 const Value *SV = I.getOperand(0);
2801 SDValue Ptr = getValue(SV);
2803 const Type *Ty = I.getType();
2804 bool isVolatile = I.isVolatile();
2805 unsigned Alignment = I.getAlignment();
2807 SmallVector<MVT, 4> ValueVTs;
2808 SmallVector<uint64_t, 4> Offsets;
2809 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2810 unsigned NumValues = ValueVTs.size();
2815 bool ConstantMemory = false;
2817 // Serialize volatile loads with other side effects.
2819 else if (AA->pointsToConstantMemory(SV)) {
2820 // Do not serialize (non-volatile) loads of constant memory with anything.
2821 Root = DAG.getEntryNode();
2822 ConstantMemory = true;
2824 // Do not serialize non-volatile loads against each other.
2825 Root = DAG.getRoot();
2828 SmallVector<SDValue, 4> Values(NumValues);
2829 SmallVector<SDValue, 4> Chains(NumValues);
2830 MVT PtrVT = Ptr.getValueType();
2831 for (unsigned i = 0; i != NumValues; ++i) {
2832 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2833 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2835 DAG.getConstant(Offsets[i], PtrVT)),
2837 isVolatile, Alignment);
2839 Chains[i] = L.getValue(1);
2842 if (!ConstantMemory) {
2843 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2845 &Chains[0], NumValues);
2849 PendingLoads.push_back(Chain);
2852 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2853 DAG.getVTList(&ValueVTs[0], NumValues),
2854 &Values[0], NumValues));
2858 void SelectionDAGLowering::visitStore(StoreInst &I) {
2859 Value *SrcV = I.getOperand(0);
2860 Value *PtrV = I.getOperand(1);
2862 SmallVector<MVT, 4> ValueVTs;
2863 SmallVector<uint64_t, 4> Offsets;
2864 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2865 unsigned NumValues = ValueVTs.size();
2869 // Get the lowered operands. Note that we do this after
2870 // checking if NumResults is zero, because with zero results
2871 // the operands won't have values in the map.
2872 SDValue Src = getValue(SrcV);
2873 SDValue Ptr = getValue(PtrV);
2875 SDValue Root = getRoot();
2876 SmallVector<SDValue, 4> Chains(NumValues);
2877 MVT PtrVT = Ptr.getValueType();
2878 bool isVolatile = I.isVolatile();
2879 unsigned Alignment = I.getAlignment();
2880 for (unsigned i = 0; i != NumValues; ++i)
2881 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2882 SDValue(Src.getNode(), Src.getResNo() + i),
2883 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2885 DAG.getConstant(Offsets[i], PtrVT)),
2887 isVolatile, Alignment);
2889 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2890 MVT::Other, &Chains[0], NumValues));
2893 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2895 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2896 unsigned Intrinsic) {
2897 bool HasChain = !I.doesNotAccessMemory();
2898 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2900 // Build the operand list.
2901 SmallVector<SDValue, 8> Ops;
2902 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2904 // We don't need to serialize loads against other loads.
2905 Ops.push_back(DAG.getRoot());
2907 Ops.push_back(getRoot());
2911 // Info is set by getTgtMemInstrinsic
2912 TargetLowering::IntrinsicInfo Info;
2913 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2915 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2916 if (!IsTgtIntrinsic)
2917 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2919 // Add all operands of the call to the operand list.
2920 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2921 SDValue Op = getValue(I.getOperand(i));
2922 assert(TLI.isTypeLegal(Op.getValueType()) &&
2923 "Intrinsic uses a non-legal type?");
2927 std::vector<MVT> VTs;
2928 if (I.getType() != Type::VoidTy) {
2929 MVT VT = TLI.getValueType(I.getType());
2930 if (VT.isVector()) {
2931 const VectorType *DestTy = cast<VectorType>(I.getType());
2932 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2934 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2935 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2938 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2942 VTs.push_back(MVT::Other);
2944 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2948 if (IsTgtIntrinsic) {
2949 // This is target intrinsic that touches memory
2950 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2952 &Ops[0], Ops.size(),
2953 Info.memVT, Info.ptrVal, Info.offset,
2954 Info.align, Info.vol,
2955 Info.readMem, Info.writeMem);
2958 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2960 &Ops[0], Ops.size());
2961 else if (I.getType() != Type::VoidTy)
2962 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2964 &Ops[0], Ops.size());
2966 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2968 &Ops[0], Ops.size());
2971 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2973 PendingLoads.push_back(Chain);
2977 if (I.getType() != Type::VoidTy) {
2978 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2979 MVT VT = TLI.getValueType(PTy);
2980 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2982 setValue(&I, Result);
2986 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2987 static GlobalVariable *ExtractTypeInfo(Value *V) {
2988 V = V->stripPointerCasts();
2989 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2990 assert ((GV || isa<ConstantPointerNull>(V)) &&
2991 "TypeInfo must be a global variable or NULL");
2997 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2998 /// call, and add them to the specified machine basic block.
2999 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3000 MachineBasicBlock *MBB) {
3001 // Inform the MachineModuleInfo of the personality for this landing pad.
3002 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3003 assert(CE->getOpcode() == Instruction::BitCast &&
3004 isa<Function>(CE->getOperand(0)) &&
3005 "Personality should be a function");
3006 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3008 // Gather all the type infos for this landing pad and pass them along to
3009 // MachineModuleInfo.
3010 std::vector<GlobalVariable *> TyInfo;
3011 unsigned N = I.getNumOperands();
3013 for (unsigned i = N - 1; i > 2; --i) {
3014 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3015 unsigned FilterLength = CI->getZExtValue();
3016 unsigned FirstCatch = i + FilterLength + !FilterLength;
3017 assert (FirstCatch <= N && "Invalid filter length");
3019 if (FirstCatch < N) {
3020 TyInfo.reserve(N - FirstCatch);
3021 for (unsigned j = FirstCatch; j < N; ++j)
3022 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3023 MMI->addCatchTypeInfo(MBB, TyInfo);
3027 if (!FilterLength) {
3029 MMI->addCleanup(MBB);
3032 TyInfo.reserve(FilterLength - 1);
3033 for (unsigned j = i + 1; j < FirstCatch; ++j)
3034 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3035 MMI->addFilterTypeInfo(MBB, TyInfo);
3044 TyInfo.reserve(N - 3);
3045 for (unsigned j = 3; j < N; ++j)
3046 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3047 MMI->addCatchTypeInfo(MBB, TyInfo);
3053 /// GetSignificand - Get the significand and build it into a floating-point
3054 /// number with exponent of 1:
3056 /// Op = (Op & 0x007fffff) | 0x3f800000;
3058 /// where Op is the hexidecimal representation of floating point value.
3060 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3061 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3062 DAG.getConstant(0x007fffff, MVT::i32));
3063 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3064 DAG.getConstant(0x3f800000, MVT::i32));
3065 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3068 /// GetExponent - Get the exponent:
3070 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3072 /// where Op is the hexidecimal representation of floating point value.
3074 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3076 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3077 DAG.getConstant(0x7f800000, MVT::i32));
3078 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3079 DAG.getConstant(23, TLI.getPointerTy()));
3080 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3081 DAG.getConstant(127, MVT::i32));
3082 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3085 /// getF32Constant - Get 32-bit floating point constant.
3087 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3088 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3091 /// Inlined utility function to implement binary input atomic intrinsics for
3092 /// visitIntrinsicCall: I is a call instruction
3093 /// Op is the associated NodeType for I
3095 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3096 SDValue Root = getRoot();
3098 DAG.getAtomic(Op, getCurDebugLoc(),
3099 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3101 getValue(I.getOperand(1)),
3102 getValue(I.getOperand(2)),
3105 DAG.setRoot(L.getValue(1));
3109 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3111 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3112 SDValue Op1 = getValue(I.getOperand(1));
3113 SDValue Op2 = getValue(I.getOperand(2));
3115 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3116 SDValue Ops[] = { Op1, Op2 };
3118 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
3119 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
3121 setValue(&I, Result);
3125 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3126 /// limited-precision mode.
3128 SelectionDAGLowering::visitExp(CallInst &I) {
3130 DebugLoc dl = getCurDebugLoc();
3132 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3133 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3134 SDValue Op = getValue(I.getOperand(1));
3136 // Put the exponent in the right bit position for later addition to the
3139 // #define LOG2OFe 1.4426950f
3140 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3141 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3142 getF32Constant(DAG, 0x3fb8aa3b));
3143 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3145 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3146 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3147 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3149 // IntegerPartOfX <<= 23;
3150 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3151 DAG.getConstant(23, TLI.getPointerTy()));
3153 if (LimitFloatPrecision <= 6) {
3154 // For floating-point precision of 6:
3156 // TwoToFractionalPartOfX =
3158 // (0.735607626f + 0.252464424f * x) * x;
3160 // error 0.0144103317, which is 6 bits
3161 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3162 getF32Constant(DAG, 0x3e814304));
3163 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3164 getF32Constant(DAG, 0x3f3c50c8));
3165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3167 getF32Constant(DAG, 0x3f7f5e7e));
3168 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3170 // Add the exponent into the result in integer domain.
3171 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3172 TwoToFracPartOfX, IntegerPartOfX);
3174 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3175 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3176 // For floating-point precision of 12:
3178 // TwoToFractionalPartOfX =
3181 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3183 // 0.000107046256 error, which is 13 to 14 bits
3184 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3185 getF32Constant(DAG, 0x3da235e3));
3186 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3187 getF32Constant(DAG, 0x3e65b8f3));
3188 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3189 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3190 getF32Constant(DAG, 0x3f324b07));
3191 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3192 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3193 getF32Constant(DAG, 0x3f7ff8fd));
3194 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3196 // Add the exponent into the result in integer domain.
3197 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3198 TwoToFracPartOfX, IntegerPartOfX);
3200 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3201 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3202 // For floating-point precision of 18:
3204 // TwoToFractionalPartOfX =
3208 // (0.554906021e-1f +
3209 // (0.961591928e-2f +
3210 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3212 // error 2.47208000*10^(-7), which is better than 18 bits
3213 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3214 getF32Constant(DAG, 0x3924b03e));
3215 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3216 getF32Constant(DAG, 0x3ab24b87));
3217 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3218 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3219 getF32Constant(DAG, 0x3c1d8c17));
3220 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3221 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3222 getF32Constant(DAG, 0x3d634a1d));
3223 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3224 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3225 getF32Constant(DAG, 0x3e75fe14));
3226 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3227 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3228 getF32Constant(DAG, 0x3f317234));
3229 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3230 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3231 getF32Constant(DAG, 0x3f800000));
3232 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3235 // Add the exponent into the result in integer domain.
3236 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3237 TwoToFracPartOfX, IntegerPartOfX);
3239 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3242 // No special expansion.
3243 result = DAG.getNode(ISD::FEXP, dl,
3244 getValue(I.getOperand(1)).getValueType(),
3245 getValue(I.getOperand(1)));
3248 setValue(&I, result);
3251 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3252 /// limited-precision mode.
3254 SelectionDAGLowering::visitLog(CallInst &I) {
3256 DebugLoc dl = getCurDebugLoc();
3258 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3259 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3260 SDValue Op = getValue(I.getOperand(1));
3261 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3263 // Scale the exponent by log(2) [0.69314718f].
3264 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3265 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3266 getF32Constant(DAG, 0x3f317218));
3268 // Get the significand and build it into a floating-point number with
3270 SDValue X = GetSignificand(DAG, Op1, dl);
3272 if (LimitFloatPrecision <= 6) {
3273 // For floating-point precision of 6:
3277 // (1.4034025f - 0.23903021f * x) * x;
3279 // error 0.0034276066, which is better than 8 bits
3280 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3281 getF32Constant(DAG, 0xbe74c456));
3282 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3283 getF32Constant(DAG, 0x3fb3a2b1));
3284 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3285 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3286 getF32Constant(DAG, 0x3f949a29));
3288 result = DAG.getNode(ISD::FADD, dl,
3289 MVT::f32, LogOfExponent, LogOfMantissa);
3290 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3291 // For floating-point precision of 12:
3297 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3299 // error 0.000061011436, which is 14 bits
3300 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3301 getF32Constant(DAG, 0xbd67b6d6));
3302 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3303 getF32Constant(DAG, 0x3ee4f4b8));
3304 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3305 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3306 getF32Constant(DAG, 0x3fbc278b));
3307 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3308 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3309 getF32Constant(DAG, 0x40348e95));
3310 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3311 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3312 getF32Constant(DAG, 0x3fdef31a));
3314 result = DAG.getNode(ISD::FADD, dl,
3315 MVT::f32, LogOfExponent, LogOfMantissa);
3316 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3317 // For floating-point precision of 18:
3325 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3327 // error 0.0000023660568, which is better than 18 bits
3328 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3329 getF32Constant(DAG, 0xbc91e5ac));
3330 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3331 getF32Constant(DAG, 0x3e4350aa));
3332 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3333 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3334 getF32Constant(DAG, 0x3f60d3e3));
3335 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3336 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3337 getF32Constant(DAG, 0x4011cdf0));
3338 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3339 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3340 getF32Constant(DAG, 0x406cfd1c));
3341 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3342 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3343 getF32Constant(DAG, 0x408797cb));
3344 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3345 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3346 getF32Constant(DAG, 0x4006dcab));
3348 result = DAG.getNode(ISD::FADD, dl,
3349 MVT::f32, LogOfExponent, LogOfMantissa);
3352 // No special expansion.
3353 result = DAG.getNode(ISD::FLOG, dl,
3354 getValue(I.getOperand(1)).getValueType(),
3355 getValue(I.getOperand(1)));
3358 setValue(&I, result);
3361 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3362 /// limited-precision mode.
3364 SelectionDAGLowering::visitLog2(CallInst &I) {
3366 DebugLoc dl = getCurDebugLoc();
3368 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3369 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3370 SDValue Op = getValue(I.getOperand(1));
3371 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3373 // Get the exponent.
3374 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3376 // Get the significand and build it into a floating-point number with
3378 SDValue X = GetSignificand(DAG, Op1, dl);
3380 // Different possible minimax approximations of significand in
3381 // floating-point for various degrees of accuracy over [1,2].
3382 if (LimitFloatPrecision <= 6) {
3383 // For floating-point precision of 6:
3385 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3387 // error 0.0049451742, which is more than 7 bits
3388 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3389 getF32Constant(DAG, 0xbeb08fe0));
3390 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3391 getF32Constant(DAG, 0x40019463));
3392 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3393 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3394 getF32Constant(DAG, 0x3fd6633d));
3396 result = DAG.getNode(ISD::FADD, dl,
3397 MVT::f32, LogOfExponent, Log2ofMantissa);
3398 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3399 // For floating-point precision of 12:
3405 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3407 // error 0.0000876136000, which is better than 13 bits
3408 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3409 getF32Constant(DAG, 0xbda7262e));
3410 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3411 getF32Constant(DAG, 0x3f25280b));
3412 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3413 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3414 getF32Constant(DAG, 0x4007b923));
3415 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3416 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3417 getF32Constant(DAG, 0x40823e2f));
3418 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3419 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3420 getF32Constant(DAG, 0x4020d29c));
3422 result = DAG.getNode(ISD::FADD, dl,
3423 MVT::f32, LogOfExponent, Log2ofMantissa);
3424 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3425 // For floating-point precision of 18:
3434 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3436 // error 0.0000018516, which is better than 18 bits
3437 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3438 getF32Constant(DAG, 0xbcd2769e));
3439 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3440 getF32Constant(DAG, 0x3e8ce0b9));
3441 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3442 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3443 getF32Constant(DAG, 0x3fa22ae7));
3444 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3445 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3446 getF32Constant(DAG, 0x40525723));
3447 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3448 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3449 getF32Constant(DAG, 0x40aaf200));
3450 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3451 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3452 getF32Constant(DAG, 0x40c39dad));
3453 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3454 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3455 getF32Constant(DAG, 0x4042902c));
3457 result = DAG.getNode(ISD::FADD, dl,
3458 MVT::f32, LogOfExponent, Log2ofMantissa);
3461 // No special expansion.
3462 result = DAG.getNode(ISD::FLOG2, dl,
3463 getValue(I.getOperand(1)).getValueType(),
3464 getValue(I.getOperand(1)));
3467 setValue(&I, result);
3470 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3471 /// limited-precision mode.
3473 SelectionDAGLowering::visitLog10(CallInst &I) {
3475 DebugLoc dl = getCurDebugLoc();
3477 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3478 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3479 SDValue Op = getValue(I.getOperand(1));
3480 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3482 // Scale the exponent by log10(2) [0.30102999f].
3483 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3484 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3485 getF32Constant(DAG, 0x3e9a209a));
3487 // Get the significand and build it into a floating-point number with
3489 SDValue X = GetSignificand(DAG, Op1, dl);
3491 if (LimitFloatPrecision <= 6) {
3492 // For floating-point precision of 6:
3494 // Log10ofMantissa =
3496 // (0.60948995f - 0.10380950f * x) * x;
3498 // error 0.0014886165, which is 6 bits
3499 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3500 getF32Constant(DAG, 0xbdd49a13));
3501 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3502 getF32Constant(DAG, 0x3f1c0789));
3503 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3504 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3505 getF32Constant(DAG, 0x3f011300));
3507 result = DAG.getNode(ISD::FADD, dl,
3508 MVT::f32, LogOfExponent, Log10ofMantissa);
3509 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3510 // For floating-point precision of 12:
3512 // Log10ofMantissa =
3515 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3517 // error 0.00019228036, which is better than 12 bits
3518 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3519 getF32Constant(DAG, 0x3d431f31));
3520 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3521 getF32Constant(DAG, 0x3ea21fb2));
3522 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3523 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3524 getF32Constant(DAG, 0x3f6ae232));
3525 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3526 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3527 getF32Constant(DAG, 0x3f25f7c3));
3529 result = DAG.getNode(ISD::FADD, dl,
3530 MVT::f32, LogOfExponent, Log10ofMantissa);
3531 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3532 // For floating-point precision of 18:
3534 // Log10ofMantissa =
3539 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3541 // error 0.0000037995730, which is better than 18 bits
3542 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3543 getF32Constant(DAG, 0x3c5d51ce));
3544 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3545 getF32Constant(DAG, 0x3e00685a));
3546 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3547 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3548 getF32Constant(DAG, 0x3efb6798));
3549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3550 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3551 getF32Constant(DAG, 0x3f88d192));
3552 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3553 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3554 getF32Constant(DAG, 0x3fc4316c));
3555 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3556 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3557 getF32Constant(DAG, 0x3f57ce70));
3559 result = DAG.getNode(ISD::FADD, dl,
3560 MVT::f32, LogOfExponent, Log10ofMantissa);
3563 // No special expansion.
3564 result = DAG.getNode(ISD::FLOG10, dl,
3565 getValue(I.getOperand(1)).getValueType(),
3566 getValue(I.getOperand(1)));
3569 setValue(&I, result);
3572 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3573 /// limited-precision mode.
3575 SelectionDAGLowering::visitExp2(CallInst &I) {
3577 DebugLoc dl = getCurDebugLoc();
3579 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3580 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3581 SDValue Op = getValue(I.getOperand(1));
3583 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3585 // FractionalPartOfX = x - (float)IntegerPartOfX;
3586 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3587 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3589 // IntegerPartOfX <<= 23;
3590 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3591 DAG.getConstant(23, TLI.getPointerTy()));
3593 if (LimitFloatPrecision <= 6) {
3594 // For floating-point precision of 6:
3596 // TwoToFractionalPartOfX =
3598 // (0.735607626f + 0.252464424f * x) * x;
3600 // error 0.0144103317, which is 6 bits
3601 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3602 getF32Constant(DAG, 0x3e814304));
3603 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3604 getF32Constant(DAG, 0x3f3c50c8));
3605 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3606 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3607 getF32Constant(DAG, 0x3f7f5e7e));
3608 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3609 SDValue TwoToFractionalPartOfX =
3610 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3612 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3613 MVT::f32, TwoToFractionalPartOfX);
3614 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3615 // For floating-point precision of 12:
3617 // TwoToFractionalPartOfX =
3620 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3622 // error 0.000107046256, which is 13 to 14 bits
3623 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3624 getF32Constant(DAG, 0x3da235e3));
3625 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3626 getF32Constant(DAG, 0x3e65b8f3));
3627 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3628 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3629 getF32Constant(DAG, 0x3f324b07));
3630 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3631 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3632 getF32Constant(DAG, 0x3f7ff8fd));
3633 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3634 SDValue TwoToFractionalPartOfX =
3635 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3637 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3638 MVT::f32, TwoToFractionalPartOfX);
3639 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3640 // For floating-point precision of 18:
3642 // TwoToFractionalPartOfX =
3646 // (0.554906021e-1f +
3647 // (0.961591928e-2f +
3648 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3649 // error 2.47208000*10^(-7), which is better than 18 bits
3650 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3651 getF32Constant(DAG, 0x3924b03e));
3652 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3653 getF32Constant(DAG, 0x3ab24b87));
3654 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3655 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3656 getF32Constant(DAG, 0x3c1d8c17));
3657 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3658 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3659 getF32Constant(DAG, 0x3d634a1d));
3660 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3661 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3662 getF32Constant(DAG, 0x3e75fe14));
3663 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3664 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3665 getF32Constant(DAG, 0x3f317234));
3666 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3667 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3668 getF32Constant(DAG, 0x3f800000));
3669 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3670 SDValue TwoToFractionalPartOfX =
3671 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3673 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3674 MVT::f32, TwoToFractionalPartOfX);
3677 // No special expansion.
3678 result = DAG.getNode(ISD::FEXP2, dl,
3679 getValue(I.getOperand(1)).getValueType(),
3680 getValue(I.getOperand(1)));
3683 setValue(&I, result);
3686 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3687 /// limited-precision mode with x == 10.0f.
3689 SelectionDAGLowering::visitPow(CallInst &I) {
3691 Value *Val = I.getOperand(1);
3692 DebugLoc dl = getCurDebugLoc();
3693 bool IsExp10 = false;
3695 if (getValue(Val).getValueType() == MVT::f32 &&
3696 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3697 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3698 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3699 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3701 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3706 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3707 SDValue Op = getValue(I.getOperand(2));
3709 // Put the exponent in the right bit position for later addition to the
3712 // #define LOG2OF10 3.3219281f
3713 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3714 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3715 getF32Constant(DAG, 0x40549a78));
3716 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3718 // FractionalPartOfX = x - (float)IntegerPartOfX;
3719 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3720 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3722 // IntegerPartOfX <<= 23;
3723 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3724 DAG.getConstant(23, TLI.getPointerTy()));
3726 if (LimitFloatPrecision <= 6) {
3727 // For floating-point precision of 6:
3729 // twoToFractionalPartOfX =
3731 // (0.735607626f + 0.252464424f * x) * x;
3733 // error 0.0144103317, which is 6 bits
3734 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3735 getF32Constant(DAG, 0x3e814304));
3736 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3737 getF32Constant(DAG, 0x3f3c50c8));
3738 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3739 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3740 getF32Constant(DAG, 0x3f7f5e7e));
3741 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3742 SDValue TwoToFractionalPartOfX =
3743 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3745 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3746 MVT::f32, TwoToFractionalPartOfX);
3747 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3748 // For floating-point precision of 12:
3750 // TwoToFractionalPartOfX =
3753 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3755 // error 0.000107046256, which is 13 to 14 bits
3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3757 getF32Constant(DAG, 0x3da235e3));
3758 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3e65b8f3));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x3f324b07));
3763 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3764 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3765 getF32Constant(DAG, 0x3f7ff8fd));
3766 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3767 SDValue TwoToFractionalPartOfX =
3768 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3770 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3771 MVT::f32, TwoToFractionalPartOfX);
3772 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3773 // For floating-point precision of 18:
3775 // TwoToFractionalPartOfX =
3779 // (0.554906021e-1f +
3780 // (0.961591928e-2f +
3781 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3782 // error 2.47208000*10^(-7), which is better than 18 bits
3783 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3784 getF32Constant(DAG, 0x3924b03e));
3785 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3786 getF32Constant(DAG, 0x3ab24b87));
3787 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3788 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3789 getF32Constant(DAG, 0x3c1d8c17));
3790 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3791 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3792 getF32Constant(DAG, 0x3d634a1d));
3793 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3794 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3795 getF32Constant(DAG, 0x3e75fe14));
3796 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3797 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3798 getF32Constant(DAG, 0x3f317234));
3799 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3800 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3801 getF32Constant(DAG, 0x3f800000));
3802 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3803 SDValue TwoToFractionalPartOfX =
3804 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3806 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3807 MVT::f32, TwoToFractionalPartOfX);
3810 // No special expansion.
3811 result = DAG.getNode(ISD::FPOW, dl,
3812 getValue(I.getOperand(1)).getValueType(),
3813 getValue(I.getOperand(1)),
3814 getValue(I.getOperand(2)));
3817 setValue(&I, result);
3820 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3821 /// we want to emit this as a call to a named external function, return the name
3822 /// otherwise lower it and return null.
3824 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3825 DebugLoc dl = getCurDebugLoc();
3826 switch (Intrinsic) {
3828 // By default, turn this into a target intrinsic node.
3829 visitTargetIntrinsic(I, Intrinsic);
3831 case Intrinsic::vastart: visitVAStart(I); return 0;
3832 case Intrinsic::vaend: visitVAEnd(I); return 0;
3833 case Intrinsic::vacopy: visitVACopy(I); return 0;
3834 case Intrinsic::returnaddress:
3835 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3836 getValue(I.getOperand(1))));
3838 case Intrinsic::frameaddress:
3839 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3840 getValue(I.getOperand(1))));
3842 case Intrinsic::setjmp:
3843 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3845 case Intrinsic::longjmp:
3846 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3848 case Intrinsic::memcpy: {
3849 SDValue Op1 = getValue(I.getOperand(1));
3850 SDValue Op2 = getValue(I.getOperand(2));
3851 SDValue Op3 = getValue(I.getOperand(3));
3852 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3853 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3854 I.getOperand(1), 0, I.getOperand(2), 0));
3857 case Intrinsic::memset: {
3858 SDValue Op1 = getValue(I.getOperand(1));
3859 SDValue Op2 = getValue(I.getOperand(2));
3860 SDValue Op3 = getValue(I.getOperand(3));
3861 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3862 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3863 I.getOperand(1), 0));
3866 case Intrinsic::memmove: {
3867 SDValue Op1 = getValue(I.getOperand(1));
3868 SDValue Op2 = getValue(I.getOperand(2));
3869 SDValue Op3 = getValue(I.getOperand(3));
3870 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3872 // If the source and destination are known to not be aliases, we can
3873 // lower memmove as memcpy.
3874 uint64_t Size = -1ULL;
3875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3876 Size = C->getZExtValue();
3877 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3878 AliasAnalysis::NoAlias) {
3879 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3880 I.getOperand(1), 0, I.getOperand(2), 0));
3884 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3885 I.getOperand(1), 0, I.getOperand(2), 0));
3888 case Intrinsic::dbg_stoppoint: {
3889 DwarfWriter *DW = DAG.getDwarfWriter();
3890 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3891 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
3892 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3896 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3897 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3898 unsigned idx = DAG.getMachineFunction().
3899 getOrCreateDebugLocID(SrcFile,
3902 setCurDebugLoc(DebugLoc::get(idx));
3906 case Intrinsic::dbg_region_start: {
3907 DwarfWriter *DW = DAG.getDwarfWriter();
3908 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3909 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
3911 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3912 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3913 getRoot(), LabelID));
3918 case Intrinsic::dbg_region_end: {
3919 DwarfWriter *DW = DAG.getDwarfWriter();
3920 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3921 if (DW && DW->ValidDebugInfo(REI.getContext())) {
3923 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3924 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3925 getRoot(), LabelID));
3930 case Intrinsic::dbg_func_start: {
3931 DwarfWriter *DW = DAG.getDwarfWriter();
3933 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3934 Value *SP = FSI.getSubprogram();
3935 if (SP && DW->ValidDebugInfo(SP)) {
3936 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3937 // what (most?) gdb expects.
3938 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3939 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3940 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3941 CompileUnit.getFilename());
3943 // Record the source line but does not create a label for the normal
3944 // function start. It will be emitted at asm emission time. However,
3945 // create a label if this is a beginning of inlined function.
3946 unsigned Line = Subprogram.getLineNumber();
3947 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3949 if (DW->getRecordSourceLineCount() != 1)
3950 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3951 getRoot(), LabelID));
3953 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
3954 getOrCreateDebugLocID(SrcFile, Line, 0)));
3959 case Intrinsic::dbg_declare: {
3960 DwarfWriter *DW = DAG.getDwarfWriter();
3961 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3962 Value *Variable = DI.getVariable();
3963 if (DW && DW->ValidDebugInfo(Variable))
3964 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3965 getValue(DI.getAddress()), getValue(Variable)));
3969 case Intrinsic::eh_exception: {
3970 if (!CurMBB->isLandingPad()) {
3971 // FIXME: Mark exception register as live in. Hack for PR1508.
3972 unsigned Reg = TLI.getExceptionAddressRegister();
3973 if (Reg) CurMBB->addLiveIn(Reg);
3975 // Insert the EXCEPTIONADDR instruction.
3976 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3978 Ops[0] = DAG.getRoot();
3979 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3981 DAG.setRoot(Op.getValue(1));
3985 case Intrinsic::eh_selector_i32:
3986 case Intrinsic::eh_selector_i64: {
3987 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3988 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3989 MVT::i32 : MVT::i64);
3992 if (CurMBB->isLandingPad())
3993 AddCatchInfo(I, MMI, CurMBB);
3996 FuncInfo.CatchInfoLost.insert(&I);
3998 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3999 unsigned Reg = TLI.getExceptionSelectorRegister();
4000 if (Reg) CurMBB->addLiveIn(Reg);
4003 // Insert the EHSELECTION instruction.
4004 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4006 Ops[0] = getValue(I.getOperand(1));
4008 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4010 DAG.setRoot(Op.getValue(1));
4012 setValue(&I, DAG.getConstant(0, VT));
4018 case Intrinsic::eh_typeid_for_i32:
4019 case Intrinsic::eh_typeid_for_i64: {
4020 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4021 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4022 MVT::i32 : MVT::i64);
4025 // Find the type id for the given typeinfo.
4026 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4028 unsigned TypeID = MMI->getTypeIDFor(GV);
4029 setValue(&I, DAG.getConstant(TypeID, VT));
4031 // Return something different to eh_selector.
4032 setValue(&I, DAG.getConstant(1, VT));
4038 case Intrinsic::eh_return_i32:
4039 case Intrinsic::eh_return_i64:
4040 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4041 MMI->setCallsEHReturn(true);
4042 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4045 getValue(I.getOperand(1)),
4046 getValue(I.getOperand(2))));
4048 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4052 case Intrinsic::eh_unwind_init:
4053 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4054 MMI->setCallsUnwindInit(true);
4059 case Intrinsic::eh_dwarf_cfa: {
4060 MVT VT = getValue(I.getOperand(1)).getValueType();
4062 if (VT.bitsGT(TLI.getPointerTy()))
4063 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4064 TLI.getPointerTy(), getValue(I.getOperand(1)));
4066 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4067 TLI.getPointerTy(), getValue(I.getOperand(1)));
4069 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4071 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4072 TLI.getPointerTy()),
4074 setValue(&I, DAG.getNode(ISD::ADD, dl,
4076 DAG.getNode(ISD::FRAMEADDR, dl,
4079 TLI.getPointerTy())),
4084 case Intrinsic::convertff:
4085 case Intrinsic::convertfsi:
4086 case Intrinsic::convertfui:
4087 case Intrinsic::convertsif:
4088 case Intrinsic::convertuif:
4089 case Intrinsic::convertss:
4090 case Intrinsic::convertsu:
4091 case Intrinsic::convertus:
4092 case Intrinsic::convertuu: {
4093 ISD::CvtCode Code = ISD::CVT_INVALID;
4094 switch (Intrinsic) {
4095 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4096 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4097 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4098 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4099 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4100 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4101 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4102 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4103 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4105 MVT DestVT = TLI.getValueType(I.getType());
4106 Value* Op1 = I.getOperand(1);
4107 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4108 DAG.getValueType(DestVT),
4109 DAG.getValueType(getValue(Op1).getValueType()),
4110 getValue(I.getOperand(2)),
4111 getValue(I.getOperand(3)),
4116 case Intrinsic::sqrt:
4117 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4118 getValue(I.getOperand(1)).getValueType(),
4119 getValue(I.getOperand(1))));
4121 case Intrinsic::powi:
4122 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4123 getValue(I.getOperand(1)).getValueType(),
4124 getValue(I.getOperand(1)),
4125 getValue(I.getOperand(2))));
4127 case Intrinsic::sin:
4128 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4129 getValue(I.getOperand(1)).getValueType(),
4130 getValue(I.getOperand(1))));
4132 case Intrinsic::cos:
4133 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4134 getValue(I.getOperand(1)).getValueType(),
4135 getValue(I.getOperand(1))));
4137 case Intrinsic::log:
4140 case Intrinsic::log2:
4143 case Intrinsic::log10:
4146 case Intrinsic::exp:
4149 case Intrinsic::exp2:
4152 case Intrinsic::pow:
4155 case Intrinsic::pcmarker: {
4156 SDValue Tmp = getValue(I.getOperand(1));
4157 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4160 case Intrinsic::readcyclecounter: {
4161 SDValue Op = getRoot();
4162 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4163 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4166 DAG.setRoot(Tmp.getValue(1));
4169 case Intrinsic::part_select: {
4170 // Currently not implemented: just abort
4171 assert(0 && "part_select intrinsic not implemented");
4174 case Intrinsic::part_set: {
4175 // Currently not implemented: just abort
4176 assert(0 && "part_set intrinsic not implemented");
4179 case Intrinsic::bswap:
4180 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4181 getValue(I.getOperand(1)).getValueType(),
4182 getValue(I.getOperand(1))));
4184 case Intrinsic::cttz: {
4185 SDValue Arg = getValue(I.getOperand(1));
4186 MVT Ty = Arg.getValueType();
4187 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4188 setValue(&I, result);
4191 case Intrinsic::ctlz: {
4192 SDValue Arg = getValue(I.getOperand(1));
4193 MVT Ty = Arg.getValueType();
4194 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4195 setValue(&I, result);
4198 case Intrinsic::ctpop: {
4199 SDValue Arg = getValue(I.getOperand(1));
4200 MVT Ty = Arg.getValueType();
4201 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4202 setValue(&I, result);
4205 case Intrinsic::stacksave: {
4206 SDValue Op = getRoot();
4207 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4208 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4210 DAG.setRoot(Tmp.getValue(1));
4213 case Intrinsic::stackrestore: {
4214 SDValue Tmp = getValue(I.getOperand(1));
4215 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4218 case Intrinsic::stackprotector: {
4219 // Emit code into the DAG to store the stack guard onto the stack.
4220 MachineFunction &MF = DAG.getMachineFunction();
4221 MachineFrameInfo *MFI = MF.getFrameInfo();
4222 MVT PtrTy = TLI.getPointerTy();
4224 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4225 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4227 int FI = FuncInfo.StaticAllocaMap[Slot];
4228 MFI->setStackProtectorIndex(FI);
4230 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4232 // Store the stack protector onto the stack.
4233 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4234 PseudoSourceValue::getFixedStack(FI),
4236 setValue(&I, Result);
4237 DAG.setRoot(Result);
4240 case Intrinsic::var_annotation:
4241 // Discard annotate attributes
4244 case Intrinsic::init_trampoline: {
4245 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4249 Ops[1] = getValue(I.getOperand(1));
4250 Ops[2] = getValue(I.getOperand(2));
4251 Ops[3] = getValue(I.getOperand(3));
4252 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4253 Ops[5] = DAG.getSrcValue(F);
4255 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4256 DAG.getNodeValueTypes(TLI.getPointerTy(),
4261 DAG.setRoot(Tmp.getValue(1));
4265 case Intrinsic::gcroot:
4267 Value *Alloca = I.getOperand(1);
4268 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4270 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4271 GFI->addStackRoot(FI->getIndex(), TypeMap);
4275 case Intrinsic::gcread:
4276 case Intrinsic::gcwrite:
4277 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4280 case Intrinsic::flt_rounds: {
4281 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4285 case Intrinsic::trap: {
4286 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4290 case Intrinsic::uadd_with_overflow:
4291 return implVisitAluOverflow(I, ISD::UADDO);
4292 case Intrinsic::sadd_with_overflow:
4293 return implVisitAluOverflow(I, ISD::SADDO);
4294 case Intrinsic::usub_with_overflow:
4295 return implVisitAluOverflow(I, ISD::USUBO);
4296 case Intrinsic::ssub_with_overflow:
4297 return implVisitAluOverflow(I, ISD::SSUBO);
4298 case Intrinsic::umul_with_overflow:
4299 return implVisitAluOverflow(I, ISD::UMULO);
4300 case Intrinsic::smul_with_overflow:
4301 return implVisitAluOverflow(I, ISD::SMULO);
4303 case Intrinsic::prefetch: {
4306 Ops[1] = getValue(I.getOperand(1));
4307 Ops[2] = getValue(I.getOperand(2));
4308 Ops[3] = getValue(I.getOperand(3));
4309 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4313 case Intrinsic::memory_barrier: {
4316 for (int x = 1; x < 6; ++x)
4317 Ops[x] = getValue(I.getOperand(x));
4319 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4322 case Intrinsic::atomic_cmp_swap: {
4323 SDValue Root = getRoot();
4325 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4326 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4328 getValue(I.getOperand(1)),
4329 getValue(I.getOperand(2)),
4330 getValue(I.getOperand(3)),
4333 DAG.setRoot(L.getValue(1));
4336 case Intrinsic::atomic_load_add:
4337 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4338 case Intrinsic::atomic_load_sub:
4339 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4340 case Intrinsic::atomic_load_or:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4342 case Intrinsic::atomic_load_xor:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4344 case Intrinsic::atomic_load_and:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4346 case Intrinsic::atomic_load_nand:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4348 case Intrinsic::atomic_load_max:
4349 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4350 case Intrinsic::atomic_load_min:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4352 case Intrinsic::atomic_load_umin:
4353 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4354 case Intrinsic::atomic_load_umax:
4355 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4356 case Intrinsic::atomic_swap:
4357 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4362 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4364 MachineBasicBlock *LandingPad) {
4365 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4366 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4367 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4368 unsigned BeginLabel = 0, EndLabel = 0;
4370 TargetLowering::ArgListTy Args;
4371 TargetLowering::ArgListEntry Entry;
4372 Args.reserve(CS.arg_size());
4373 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4375 SDValue ArgNode = getValue(*i);
4376 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4378 unsigned attrInd = i - CS.arg_begin() + 1;
4379 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4380 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4381 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4382 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4383 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4384 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4385 Entry.Alignment = CS.getParamAlignment(attrInd);
4386 Args.push_back(Entry);
4389 if (LandingPad && MMI) {
4390 // Insert a label before the invoke call to mark the try range. This can be
4391 // used to detect deletion of the invoke via the MachineModuleInfo.
4392 BeginLabel = MMI->NextLabelID();
4393 // Both PendingLoads and PendingExports must be flushed here;
4394 // this call might not return.
4396 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4397 getControlRoot(), BeginLabel));
4400 std::pair<SDValue,SDValue> Result =
4401 TLI.LowerCallTo(getRoot(), CS.getType(),
4402 CS.paramHasAttr(0, Attribute::SExt),
4403 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4404 CS.paramHasAttr(0, Attribute::InReg),
4405 CS.getCallingConv(),
4406 IsTailCall && PerformTailCallOpt,
4407 Callee, Args, DAG, getCurDebugLoc());
4408 if (CS.getType() != Type::VoidTy)
4409 setValue(CS.getInstruction(), Result.first);
4410 DAG.setRoot(Result.second);
4412 if (LandingPad && MMI) {
4413 // Insert a label at the end of the invoke call to mark the try range. This
4414 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4415 EndLabel = MMI->NextLabelID();
4416 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4417 getRoot(), EndLabel));
4419 // Inform MachineModuleInfo of range.
4420 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4425 void SelectionDAGLowering::visitCall(CallInst &I) {
4426 const char *RenameFn = 0;
4427 if (Function *F = I.getCalledFunction()) {
4428 if (F->isDeclaration()) {
4429 if (unsigned IID = F->getIntrinsicID()) {
4430 RenameFn = visitIntrinsicCall(I, IID);
4436 // Check for well-known libc/libm calls. If the function is internal, it
4437 // can't be a library call.
4438 unsigned NameLen = F->getNameLen();
4439 if (!F->hasLocalLinkage() && NameLen) {
4440 const char *NameStr = F->getNameStart();
4441 if (NameStr[0] == 'c' &&
4442 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4443 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4444 if (I.getNumOperands() == 3 && // Basic sanity checks.
4445 I.getOperand(1)->getType()->isFloatingPoint() &&
4446 I.getType() == I.getOperand(1)->getType() &&
4447 I.getType() == I.getOperand(2)->getType()) {
4448 SDValue LHS = getValue(I.getOperand(1));
4449 SDValue RHS = getValue(I.getOperand(2));
4450 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4451 LHS.getValueType(), LHS, RHS));
4454 } else if (NameStr[0] == 'f' &&
4455 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4456 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4457 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4458 if (I.getNumOperands() == 2 && // Basic sanity checks.
4459 I.getOperand(1)->getType()->isFloatingPoint() &&
4460 I.getType() == I.getOperand(1)->getType()) {
4461 SDValue Tmp = getValue(I.getOperand(1));
4462 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4463 Tmp.getValueType(), Tmp));
4466 } else if (NameStr[0] == 's' &&
4467 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4468 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4469 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4470 if (I.getNumOperands() == 2 && // Basic sanity checks.
4471 I.getOperand(1)->getType()->isFloatingPoint() &&
4472 I.getType() == I.getOperand(1)->getType()) {
4473 SDValue Tmp = getValue(I.getOperand(1));
4474 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4475 Tmp.getValueType(), Tmp));
4478 } else if (NameStr[0] == 'c' &&
4479 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4480 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4481 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4482 if (I.getNumOperands() == 2 && // Basic sanity checks.
4483 I.getOperand(1)->getType()->isFloatingPoint() &&
4484 I.getType() == I.getOperand(1)->getType()) {
4485 SDValue Tmp = getValue(I.getOperand(1));
4486 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4487 Tmp.getValueType(), Tmp));
4492 } else if (isa<InlineAsm>(I.getOperand(0))) {
4499 Callee = getValue(I.getOperand(0));
4501 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4503 LowerCallTo(&I, Callee, I.isTailCall());
4507 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4508 /// this value and returns the result as a ValueVT value. This uses
4509 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4510 /// If the Flag pointer is NULL, no flag is used.
4511 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4513 SDValue *Flag) const {
4514 // Assemble the legal parts into the final values.
4515 SmallVector<SDValue, 4> Values(ValueVTs.size());
4516 SmallVector<SDValue, 8> Parts;
4517 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4518 // Copy the legal parts from the registers.
4519 MVT ValueVT = ValueVTs[Value];
4520 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4521 MVT RegisterVT = RegVTs[Value];
4523 Parts.resize(NumRegs);
4524 for (unsigned i = 0; i != NumRegs; ++i) {
4527 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4529 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4530 *Flag = P.getValue(2);
4532 Chain = P.getValue(1);
4534 // If the source register was virtual and if we know something about it,
4535 // add an assert node.
4536 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4537 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4538 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4539 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4540 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4541 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4543 unsigned RegSize = RegisterVT.getSizeInBits();
4544 unsigned NumSignBits = LOI.NumSignBits;
4545 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4547 // FIXME: We capture more information than the dag can represent. For
4548 // now, just use the tightest assertzext/assertsext possible.
4550 MVT FromVT(MVT::Other);
4551 if (NumSignBits == RegSize)
4552 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4553 else if (NumZeroBits >= RegSize-1)
4554 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4555 else if (NumSignBits > RegSize-8)
4556 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4557 else if (NumZeroBits >= RegSize-9)
4558 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4559 else if (NumSignBits > RegSize-16)
4560 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4561 else if (NumZeroBits >= RegSize-17)
4562 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4563 else if (NumSignBits > RegSize-32)
4564 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4565 else if (NumZeroBits >= RegSize-33)
4566 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4568 if (FromVT != MVT::Other) {
4569 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4570 RegisterVT, P, DAG.getValueType(FromVT));
4579 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4580 NumRegs, RegisterVT, ValueVT);
4585 return DAG.getNode(ISD::MERGE_VALUES, dl,
4586 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4587 &Values[0], ValueVTs.size());
4590 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4591 /// specified value into the registers specified by this object. This uses
4592 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4593 /// If the Flag pointer is NULL, no flag is used.
4594 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4595 SDValue &Chain, SDValue *Flag) const {
4596 // Get the list of the values's legal parts.
4597 unsigned NumRegs = Regs.size();
4598 SmallVector<SDValue, 8> Parts(NumRegs);
4599 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4600 MVT ValueVT = ValueVTs[Value];
4601 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4602 MVT RegisterVT = RegVTs[Value];
4604 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4605 &Parts[Part], NumParts, RegisterVT);
4609 // Copy the parts into the registers.
4610 SmallVector<SDValue, 8> Chains(NumRegs);
4611 for (unsigned i = 0; i != NumRegs; ++i) {
4614 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4616 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4617 *Flag = Part.getValue(1);
4619 Chains[i] = Part.getValue(0);
4622 if (NumRegs == 1 || Flag)
4623 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4624 // flagged to it. That is the CopyToReg nodes and the user are considered
4625 // a single scheduling unit. If we create a TokenFactor and return it as
4626 // chain, then the TokenFactor is both a predecessor (operand) of the
4627 // user as well as a successor (the TF operands are flagged to the user).
4628 // c1, f1 = CopyToReg
4629 // c2, f2 = CopyToReg
4630 // c3 = TokenFactor c1, c2
4633 Chain = Chains[NumRegs-1];
4635 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4638 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4639 /// operand list. This adds the code marker and includes the number of
4640 /// values added into it.
4641 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4642 std::vector<SDValue> &Ops) const {
4643 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4644 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4645 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4646 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4647 MVT RegisterVT = RegVTs[Value];
4648 for (unsigned i = 0; i != NumRegs; ++i) {
4649 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4650 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4655 /// isAllocatableRegister - If the specified register is safe to allocate,
4656 /// i.e. it isn't a stack pointer or some other special register, return the
4657 /// register class for the register. Otherwise, return null.
4658 static const TargetRegisterClass *
4659 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4660 const TargetLowering &TLI,
4661 const TargetRegisterInfo *TRI) {
4662 MVT FoundVT = MVT::Other;
4663 const TargetRegisterClass *FoundRC = 0;
4664 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4665 E = TRI->regclass_end(); RCI != E; ++RCI) {
4666 MVT ThisVT = MVT::Other;
4668 const TargetRegisterClass *RC = *RCI;
4669 // If none of the the value types for this register class are valid, we
4670 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4671 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4673 if (TLI.isTypeLegal(*I)) {
4674 // If we have already found this register in a different register class,
4675 // choose the one with the largest VT specified. For example, on
4676 // PowerPC, we favor f64 register classes over f32.
4677 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4684 if (ThisVT == MVT::Other) continue;
4686 // NOTE: This isn't ideal. In particular, this might allocate the
4687 // frame pointer in functions that need it (due to them not being taken
4688 // out of allocation, because a variable sized allocation hasn't been seen
4689 // yet). This is a slight code pessimization, but should still work.
4690 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4691 E = RC->allocation_order_end(MF); I != E; ++I)
4693 // We found a matching register class. Keep looking at others in case
4694 // we find one with larger registers that this physreg is also in.
4705 /// AsmOperandInfo - This contains information for each constraint that we are
4707 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4708 public TargetLowering::AsmOperandInfo {
4709 /// CallOperand - If this is the result output operand or a clobber
4710 /// this is null, otherwise it is the incoming operand to the CallInst.
4711 /// This gets modified as the asm is processed.
4712 SDValue CallOperand;
4714 /// AssignedRegs - If this is a register or register class operand, this
4715 /// contains the set of register corresponding to the operand.
4716 RegsForValue AssignedRegs;
4718 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4719 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4722 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4723 /// busy in OutputRegs/InputRegs.
4724 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4725 std::set<unsigned> &OutputRegs,
4726 std::set<unsigned> &InputRegs,
4727 const TargetRegisterInfo &TRI) const {
4729 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4730 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4733 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4734 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4738 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4739 /// corresponds to. If there is no Value* for this operand, it returns
4741 MVT getCallOperandValMVT(const TargetLowering &TLI,
4742 const TargetData *TD) const {
4743 if (CallOperandVal == 0) return MVT::Other;
4745 if (isa<BasicBlock>(CallOperandVal))
4746 return TLI.getPointerTy();
4748 const llvm::Type *OpTy = CallOperandVal->getType();
4750 // If this is an indirect operand, the operand is a pointer to the
4753 OpTy = cast<PointerType>(OpTy)->getElementType();
4755 // If OpTy is not a single value, it may be a struct/union that we
4756 // can tile with integers.
4757 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4758 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4767 OpTy = IntegerType::get(BitSize);
4772 return TLI.getValueType(OpTy, true);
4776 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4778 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4779 const TargetRegisterInfo &TRI) {
4780 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4782 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4783 for (; *Aliases; ++Aliases)
4784 Regs.insert(*Aliases);
4787 } // end llvm namespace.
4790 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4791 /// specified operand. We prefer to assign virtual registers, to allow the
4792 /// register allocator handle the assignment process. However, if the asm uses
4793 /// features that we can't model on machineinstrs, we have SDISel do the
4794 /// allocation. This produces generally horrible, but correct, code.
4796 /// OpInfo describes the operand.
4797 /// Input and OutputRegs are the set of already allocated physical registers.
4799 void SelectionDAGLowering::
4800 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4801 std::set<unsigned> &OutputRegs,
4802 std::set<unsigned> &InputRegs) {
4803 // Compute whether this value requires an input register, an output register,
4805 bool isOutReg = false;
4806 bool isInReg = false;
4807 switch (OpInfo.Type) {
4808 case InlineAsm::isOutput:
4811 // If there is an input constraint that matches this, we need to reserve
4812 // the input register so no other inputs allocate to it.
4813 isInReg = OpInfo.hasMatchingInput();
4815 case InlineAsm::isInput:
4819 case InlineAsm::isClobber:
4826 MachineFunction &MF = DAG.getMachineFunction();
4827 SmallVector<unsigned, 4> Regs;
4829 // If this is a constraint for a single physreg, or a constraint for a
4830 // register class, find it.
4831 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4832 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4833 OpInfo.ConstraintVT);
4835 unsigned NumRegs = 1;
4836 if (OpInfo.ConstraintVT != MVT::Other) {
4837 // If this is a FP input in an integer register (or visa versa) insert a bit
4838 // cast of the input value. More generally, handle any case where the input
4839 // value disagrees with the register class we plan to stick this in.
4840 if (OpInfo.Type == InlineAsm::isInput &&
4841 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4842 // Try to convert to the first MVT that the reg class contains. If the
4843 // types are identical size, use a bitcast to convert (e.g. two differing
4845 MVT RegVT = *PhysReg.second->vt_begin();
4846 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4847 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4848 RegVT, OpInfo.CallOperand);
4849 OpInfo.ConstraintVT = RegVT;
4850 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4851 // If the input is a FP value and we want it in FP registers, do a
4852 // bitcast to the corresponding integer type. This turns an f64 value
4853 // into i64, which can be passed with two i32 values on a 32-bit
4855 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4856 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4857 RegVT, OpInfo.CallOperand);
4858 OpInfo.ConstraintVT = RegVT;
4862 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4866 MVT ValueVT = OpInfo.ConstraintVT;
4868 // If this is a constraint for a specific physical register, like {r17},
4870 if (PhysReg.first) {
4871 if (OpInfo.ConstraintVT == MVT::Other)
4872 ValueVT = *PhysReg.second->vt_begin();
4874 // Get the actual register value type. This is important, because the user
4875 // may have asked for (e.g.) the AX register in i32 type. We need to
4876 // remember that AX is actually i16 to get the right extension.
4877 RegVT = *PhysReg.second->vt_begin();
4879 // This is a explicit reference to a physical register.
4880 Regs.push_back(PhysReg.first);
4882 // If this is an expanded reference, add the rest of the regs to Regs.
4884 TargetRegisterClass::iterator I = PhysReg.second->begin();
4885 for (; *I != PhysReg.first; ++I)
4886 assert(I != PhysReg.second->end() && "Didn't find reg!");
4888 // Already added the first reg.
4890 for (; NumRegs; --NumRegs, ++I) {
4891 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4895 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4896 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4897 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4901 // Otherwise, if this was a reference to an LLVM register class, create vregs
4902 // for this reference.
4903 std::vector<unsigned> RegClassRegs;
4904 const TargetRegisterClass *RC = PhysReg.second;
4906 // If this is a tied register, our regalloc doesn't know how to maintain
4907 // the constraint, so we have to pick a register to pin the input/output to.
4908 // If it isn't a matched constraint, go ahead and create vreg and let the
4909 // regalloc do its thing.
4910 if (!OpInfo.hasMatchingInput()) {
4911 RegVT = *PhysReg.second->vt_begin();
4912 if (OpInfo.ConstraintVT == MVT::Other)
4915 // Create the appropriate number of virtual registers.
4916 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4917 for (; NumRegs; --NumRegs)
4918 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4920 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4924 // Otherwise, we can't allocate it. Let the code below figure out how to
4925 // maintain these constraints.
4926 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4929 // This is a reference to a register class that doesn't directly correspond
4930 // to an LLVM register class. Allocate NumRegs consecutive, available,
4931 // registers from the class.
4932 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4933 OpInfo.ConstraintVT);
4936 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4937 unsigned NumAllocated = 0;
4938 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4939 unsigned Reg = RegClassRegs[i];
4940 // See if this register is available.
4941 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4942 (isInReg && InputRegs.count(Reg))) { // Already used.
4943 // Make sure we find consecutive registers.
4948 // Check to see if this register is allocatable (i.e. don't give out the
4951 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4952 if (!RC) { // Couldn't allocate this register.
4953 // Reset NumAllocated to make sure we return consecutive registers.
4959 // Okay, this register is good, we can use it.
4962 // If we allocated enough consecutive registers, succeed.
4963 if (NumAllocated == NumRegs) {
4964 unsigned RegStart = (i-NumAllocated)+1;
4965 unsigned RegEnd = i+1;
4966 // Mark all of the allocated registers used.
4967 for (unsigned i = RegStart; i != RegEnd; ++i)
4968 Regs.push_back(RegClassRegs[i]);
4970 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4971 OpInfo.ConstraintVT);
4972 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4977 // Otherwise, we couldn't allocate enough registers for this.
4980 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4981 /// processed uses a memory 'm' constraint.
4983 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4984 const TargetLowering &TLI) {
4985 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4986 InlineAsm::ConstraintInfo &CI = CInfos[i];
4987 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4988 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4989 if (CType == TargetLowering::C_Memory)
4997 /// visitInlineAsm - Handle a call to an InlineAsm object.
4999 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5000 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5002 /// ConstraintOperands - Information about all of the constraints.
5003 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5005 SDValue Chain = getRoot();
5008 std::set<unsigned> OutputRegs, InputRegs;
5010 // Do a prepass over the constraints, canonicalizing them, and building up the
5011 // ConstraintOperands list.
5012 std::vector<InlineAsm::ConstraintInfo>
5013 ConstraintInfos = IA->ParseConstraints();
5015 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5017 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5018 unsigned ResNo = 0; // ResNo - The result number of the next output.
5019 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5020 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5021 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5023 MVT OpVT = MVT::Other;
5025 // Compute the value type for each operand.
5026 switch (OpInfo.Type) {
5027 case InlineAsm::isOutput:
5028 // Indirect outputs just consume an argument.
5029 if (OpInfo.isIndirect) {
5030 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5034 // The return value of the call is this value. As such, there is no
5035 // corresponding argument.
5036 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5037 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5038 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5040 assert(ResNo == 0 && "Asm only has one result!");
5041 OpVT = TLI.getValueType(CS.getType());
5045 case InlineAsm::isInput:
5046 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5048 case InlineAsm::isClobber:
5053 // If this is an input or an indirect output, process the call argument.
5054 // BasicBlocks are labels, currently appearing only in asm's.
5055 if (OpInfo.CallOperandVal) {
5056 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5057 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5059 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5062 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5065 OpInfo.ConstraintVT = OpVT;
5068 // Second pass over the constraints: compute which constraint option to use
5069 // and assign registers to constraints that want a specific physreg.
5070 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5071 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5073 // If this is an output operand with a matching input operand, look up the
5074 // matching input. If their types mismatch, e.g. one is an integer, the
5075 // other is floating point, or their sizes are different, flag it as an
5077 if (OpInfo.hasMatchingInput()) {
5078 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5079 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5080 if ((OpInfo.ConstraintVT.isInteger() !=
5081 Input.ConstraintVT.isInteger()) ||
5082 (OpInfo.ConstraintVT.getSizeInBits() !=
5083 Input.ConstraintVT.getSizeInBits())) {
5084 cerr << "Unsupported asm: input constraint with a matching output "
5085 << "constraint of incompatible type!\n";
5088 Input.ConstraintVT = OpInfo.ConstraintVT;
5092 // Compute the constraint code and ConstraintType to use.
5093 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5095 // If this is a memory input, and if the operand is not indirect, do what we
5096 // need to to provide an address for the memory input.
5097 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5098 !OpInfo.isIndirect) {
5099 assert(OpInfo.Type == InlineAsm::isInput &&
5100 "Can only indirectify direct input operands!");
5102 // Memory operands really want the address of the value. If we don't have
5103 // an indirect input, put it in the constpool if we can, otherwise spill
5104 // it to a stack slot.
5106 // If the operand is a float, integer, or vector constant, spill to a
5107 // constant pool entry to get its address.
5108 Value *OpVal = OpInfo.CallOperandVal;
5109 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5110 isa<ConstantVector>(OpVal)) {
5111 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5112 TLI.getPointerTy());
5114 // Otherwise, create a stack slot and emit a store to it before the
5116 const Type *Ty = OpVal->getType();
5117 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5118 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5119 MachineFunction &MF = DAG.getMachineFunction();
5120 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5121 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5122 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5123 OpInfo.CallOperand, StackSlot, NULL, 0);
5124 OpInfo.CallOperand = StackSlot;
5127 // There is no longer a Value* corresponding to this operand.
5128 OpInfo.CallOperandVal = 0;
5129 // It is now an indirect operand.
5130 OpInfo.isIndirect = true;
5133 // If this constraint is for a specific register, allocate it before
5135 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5136 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5138 ConstraintInfos.clear();
5141 // Second pass - Loop over all of the operands, assigning virtual or physregs
5142 // to register class operands.
5143 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5144 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5146 // C_Register operands have already been allocated, Other/Memory don't need
5148 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5149 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5152 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5153 std::vector<SDValue> AsmNodeOperands;
5154 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5155 AsmNodeOperands.push_back(
5156 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5159 // Loop over all of the inputs, copying the operand values into the
5160 // appropriate registers and processing the output regs.
5161 RegsForValue RetValRegs;
5163 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5164 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5166 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5167 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5169 switch (OpInfo.Type) {
5170 case InlineAsm::isOutput: {
5171 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5172 OpInfo.ConstraintType != TargetLowering::C_Register) {
5173 // Memory output, or 'other' output (e.g. 'X' constraint).
5174 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5176 // Add information to the INLINEASM node to know about this output.
5177 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5178 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5179 TLI.getPointerTy()));
5180 AsmNodeOperands.push_back(OpInfo.CallOperand);
5184 // Otherwise, this is a register or register class output.
5186 // Copy the output from the appropriate register. Find a register that
5188 if (OpInfo.AssignedRegs.Regs.empty()) {
5189 cerr << "Couldn't allocate output reg for constraint '"
5190 << OpInfo.ConstraintCode << "'!\n";
5194 // If this is an indirect operand, store through the pointer after the
5196 if (OpInfo.isIndirect) {
5197 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5198 OpInfo.CallOperandVal));
5200 // This is the result value of the call.
5201 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5202 // Concatenate this output onto the outputs list.
5203 RetValRegs.append(OpInfo.AssignedRegs);
5206 // Add information to the INLINEASM node to know that this register is
5208 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5209 6 /* EARLYCLOBBER REGDEF */ :
5211 DAG, AsmNodeOperands);
5214 case InlineAsm::isInput: {
5215 SDValue InOperandVal = OpInfo.CallOperand;
5217 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5218 // If this is required to match an output register we have already set,
5219 // just use its register.
5220 unsigned OperandNo = OpInfo.getMatchedOperand();
5222 // Scan until we find the definition we already emitted of this operand.
5223 // When we find it, create a RegsForValue operand.
5224 unsigned CurOp = 2; // The first operand.
5225 for (; OperandNo; --OperandNo) {
5226 // Advance to the next operand.
5228 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5229 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
5230 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5231 (NumOps & 7) == 4 /*MEM*/) &&
5232 "Skipped past definitions?");
5233 CurOp += (NumOps>>3)+1;
5237 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5238 if ((NumOps & 7) == 2 /*REGDEF*/
5239 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5240 // Add NumOps>>3 registers to MatchedRegs.
5241 RegsForValue MatchedRegs;
5242 MatchedRegs.TLI = &TLI;
5243 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5244 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5245 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5247 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5248 MatchedRegs.Regs.push_back(Reg);
5251 // Use the produced MatchedRegs object to
5252 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5254 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
5257 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5258 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5259 // Add information to the INLINEASM node to know about this input.
5260 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
5261 TLI.getPointerTy()));
5262 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5267 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5268 assert(!OpInfo.isIndirect &&
5269 "Don't know how to handle indirect other inputs yet!");
5271 std::vector<SDValue> Ops;
5272 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5273 hasMemory, Ops, DAG);
5275 cerr << "Invalid operand for inline asm constraint '"
5276 << OpInfo.ConstraintCode << "'!\n";
5280 // Add information to the INLINEASM node to know about this input.
5281 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5282 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5283 TLI.getPointerTy()));
5284 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5286 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5287 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5288 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5289 "Memory operands expect pointer values");
5291 // Add information to the INLINEASM node to know about this input.
5292 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5293 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5294 TLI.getPointerTy()));
5295 AsmNodeOperands.push_back(InOperandVal);
5299 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5300 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5301 "Unknown constraint type!");
5302 assert(!OpInfo.isIndirect &&
5303 "Don't know how to handle indirect register inputs yet!");
5305 // Copy the input into the appropriate registers.
5306 if (OpInfo.AssignedRegs.Regs.empty()) {
5307 cerr << "Couldn't allocate output reg for constraint '"
5308 << OpInfo.ConstraintCode << "'!\n";
5312 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5315 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5316 DAG, AsmNodeOperands);
5319 case InlineAsm::isClobber: {
5320 // Add the clobbered value to the operand list, so that the register
5321 // allocator is aware that the physreg got clobbered.
5322 if (!OpInfo.AssignedRegs.Regs.empty())
5323 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5324 DAG, AsmNodeOperands);
5330 // Finish up input operands.
5331 AsmNodeOperands[0] = Chain;
5332 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5334 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5335 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5336 &AsmNodeOperands[0], AsmNodeOperands.size());
5337 Flag = Chain.getValue(1);
5339 // If this asm returns a register value, copy the result from that register
5340 // and set it as the value of the call.
5341 if (!RetValRegs.Regs.empty()) {
5342 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5345 // FIXME: Why don't we do this for inline asms with MRVs?
5346 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5347 MVT ResultType = TLI.getValueType(CS.getType());
5349 // If any of the results of the inline asm is a vector, it may have the
5350 // wrong width/num elts. This can happen for register classes that can
5351 // contain multiple different value types. The preg or vreg allocated may
5352 // not have the same VT as was expected. Convert it to the right type
5353 // with bit_convert.
5354 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5355 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5358 } else if (ResultType != Val.getValueType() &&
5359 ResultType.isInteger() && Val.getValueType().isInteger()) {
5360 // If a result value was tied to an input value, the computed result may
5361 // have a wider width than the expected result. Extract the relevant
5363 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5366 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5369 setValue(CS.getInstruction(), Val);
5372 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5374 // Process indirect outputs, first output all of the flagged copies out of
5376 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5377 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5378 Value *Ptr = IndirectStoresToEmit[i].second;
5379 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5381 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5384 // Emit the non-flagged stores from the physregs.
5385 SmallVector<SDValue, 8> OutChains;
5386 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5387 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5388 StoresToEmit[i].first,
5389 getValue(StoresToEmit[i].second),
5390 StoresToEmit[i].second, 0));
5391 if (!OutChains.empty())
5392 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5393 &OutChains[0], OutChains.size());
5398 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5399 SDValue Src = getValue(I.getOperand(0));
5401 MVT IntPtr = TLI.getPointerTy();
5403 if (IntPtr.bitsLT(Src.getValueType()))
5404 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5405 else if (IntPtr.bitsGT(Src.getValueType()))
5406 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5408 // Scale the source by the type size.
5409 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5410 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5411 Src, DAG.getIntPtrConstant(ElementSize));
5413 TargetLowering::ArgListTy Args;
5414 TargetLowering::ArgListEntry Entry;
5416 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5417 Args.push_back(Entry);
5419 std::pair<SDValue,SDValue> Result =
5420 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5421 CallingConv::C, PerformTailCallOpt,
5422 DAG.getExternalSymbol("malloc", IntPtr),
5423 Args, DAG, getCurDebugLoc());
5424 setValue(&I, Result.first); // Pointers always fit in registers
5425 DAG.setRoot(Result.second);
5428 void SelectionDAGLowering::visitFree(FreeInst &I) {
5429 TargetLowering::ArgListTy Args;
5430 TargetLowering::ArgListEntry Entry;
5431 Entry.Node = getValue(I.getOperand(0));
5432 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5433 Args.push_back(Entry);
5434 MVT IntPtr = TLI.getPointerTy();
5435 std::pair<SDValue,SDValue> Result =
5436 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5437 CallingConv::C, PerformTailCallOpt,
5438 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5440 DAG.setRoot(Result.second);
5443 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5444 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5445 MVT::Other, getRoot(),
5446 getValue(I.getOperand(1)),
5447 DAG.getSrcValue(I.getOperand(1))));
5450 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5451 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5452 getRoot(), getValue(I.getOperand(0)),
5453 DAG.getSrcValue(I.getOperand(0)));
5455 DAG.setRoot(V.getValue(1));
5458 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5459 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5460 MVT::Other, getRoot(),
5461 getValue(I.getOperand(1)),
5462 DAG.getSrcValue(I.getOperand(1))));
5465 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5466 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5467 MVT::Other, getRoot(),
5468 getValue(I.getOperand(1)),
5469 getValue(I.getOperand(2)),
5470 DAG.getSrcValue(I.getOperand(1)),
5471 DAG.getSrcValue(I.getOperand(2))));
5474 /// TargetLowering::LowerArguments - This is the default LowerArguments
5475 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5476 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5477 /// integrated into SDISel.
5478 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5479 SmallVectorImpl<SDValue> &ArgValues,
5481 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5482 SmallVector<SDValue, 3+16> Ops;
5483 Ops.push_back(DAG.getRoot());
5484 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5485 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5487 // Add one result value for each formal argument.
5488 SmallVector<MVT, 16> RetVals;
5490 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5492 SmallVector<MVT, 4> ValueVTs;
5493 ComputeValueVTs(*this, I->getType(), ValueVTs);
5494 for (unsigned Value = 0, NumValues = ValueVTs.size();
5495 Value != NumValues; ++Value) {
5496 MVT VT = ValueVTs[Value];
5497 const Type *ArgTy = VT.getTypeForMVT();
5498 ISD::ArgFlagsTy Flags;
5499 unsigned OriginalAlignment =
5500 getTargetData()->getABITypeAlignment(ArgTy);
5502 if (F.paramHasAttr(j, Attribute::ZExt))
5504 if (F.paramHasAttr(j, Attribute::SExt))
5506 if (F.paramHasAttr(j, Attribute::InReg))
5508 if (F.paramHasAttr(j, Attribute::StructRet))
5510 if (F.paramHasAttr(j, Attribute::ByVal)) {
5512 const PointerType *Ty = cast<PointerType>(I->getType());
5513 const Type *ElementTy = Ty->getElementType();
5514 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5515 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5516 // For ByVal, alignment should be passed from FE. BE will guess if
5517 // this info is not there but there are cases it cannot get right.
5518 if (F.getParamAlignment(j))
5519 FrameAlign = F.getParamAlignment(j);
5520 Flags.setByValAlign(FrameAlign);
5521 Flags.setByValSize(FrameSize);
5523 if (F.paramHasAttr(j, Attribute::Nest))
5525 Flags.setOrigAlign(OriginalAlignment);
5527 MVT RegisterVT = getRegisterType(VT);
5528 unsigned NumRegs = getNumRegisters(VT);
5529 for (unsigned i = 0; i != NumRegs; ++i) {
5530 RetVals.push_back(RegisterVT);
5531 ISD::ArgFlagsTy MyFlags = Flags;
5532 if (NumRegs > 1 && i == 0)
5534 // if it isn't first piece, alignment must be 1
5536 MyFlags.setOrigAlign(1);
5537 Ops.push_back(DAG.getArgFlags(MyFlags));
5542 RetVals.push_back(MVT::Other);
5545 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5546 DAG.getVTList(&RetVals[0], RetVals.size()),
5547 &Ops[0], Ops.size()).getNode();
5549 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5550 // allows exposing the loads that may be part of the argument access to the
5551 // first DAGCombiner pass.
5552 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5554 // The number of results should match up, except that the lowered one may have
5555 // an extra flag result.
5556 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5557 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5558 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5559 && "Lowering produced unexpected number of results!");
5561 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5562 if (Result != TmpRes.getNode() && Result->use_empty()) {
5563 HandleSDNode Dummy(DAG.getRoot());
5564 DAG.RemoveDeadNode(Result);
5567 Result = TmpRes.getNode();
5569 unsigned NumArgRegs = Result->getNumValues() - 1;
5570 DAG.setRoot(SDValue(Result, NumArgRegs));
5572 // Set up the return result vector.
5575 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5577 SmallVector<MVT, 4> ValueVTs;
5578 ComputeValueVTs(*this, I->getType(), ValueVTs);
5579 for (unsigned Value = 0, NumValues = ValueVTs.size();
5580 Value != NumValues; ++Value) {
5581 MVT VT = ValueVTs[Value];
5582 MVT PartVT = getRegisterType(VT);
5584 unsigned NumParts = getNumRegisters(VT);
5585 SmallVector<SDValue, 4> Parts(NumParts);
5586 for (unsigned j = 0; j != NumParts; ++j)
5587 Parts[j] = SDValue(Result, i++);
5589 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5590 if (F.paramHasAttr(Idx, Attribute::SExt))
5591 AssertOp = ISD::AssertSext;
5592 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5593 AssertOp = ISD::AssertZext;
5595 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5596 PartVT, VT, AssertOp));
5599 assert(i == NumArgRegs && "Argument register count mismatch!");
5603 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5604 /// implementation, which just inserts an ISD::CALL node, which is later custom
5605 /// lowered by the target to something concrete. FIXME: When all targets are
5606 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5607 std::pair<SDValue, SDValue>
5608 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5609 bool RetSExt, bool RetZExt, bool isVarArg,
5611 unsigned CallingConv, bool isTailCall,
5613 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5614 assert((!isTailCall || PerformTailCallOpt) &&
5615 "isTailCall set when tail-call optimizations are disabled!");
5617 SmallVector<SDValue, 32> Ops;
5618 Ops.push_back(Chain); // Op#0 - Chain
5619 Ops.push_back(Callee);
5621 // Handle all of the outgoing arguments.
5622 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5623 SmallVector<MVT, 4> ValueVTs;
5624 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5625 for (unsigned Value = 0, NumValues = ValueVTs.size();
5626 Value != NumValues; ++Value) {
5627 MVT VT = ValueVTs[Value];
5628 const Type *ArgTy = VT.getTypeForMVT();
5629 SDValue Op = SDValue(Args[i].Node.getNode(),
5630 Args[i].Node.getResNo() + Value);
5631 ISD::ArgFlagsTy Flags;
5632 unsigned OriginalAlignment =
5633 getTargetData()->getABITypeAlignment(ArgTy);
5639 if (Args[i].isInReg)
5643 if (Args[i].isByVal) {
5645 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5646 const Type *ElementTy = Ty->getElementType();
5647 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5648 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5649 // For ByVal, alignment should come from FE. BE will guess if this
5650 // info is not there but there are cases it cannot get right.
5651 if (Args[i].Alignment)
5652 FrameAlign = Args[i].Alignment;
5653 Flags.setByValAlign(FrameAlign);
5654 Flags.setByValSize(FrameSize);
5658 Flags.setOrigAlign(OriginalAlignment);
5660 MVT PartVT = getRegisterType(VT);
5661 unsigned NumParts = getNumRegisters(VT);
5662 SmallVector<SDValue, 4> Parts(NumParts);
5663 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5666 ExtendKind = ISD::SIGN_EXTEND;
5667 else if (Args[i].isZExt)
5668 ExtendKind = ISD::ZERO_EXTEND;
5670 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5672 for (unsigned i = 0; i != NumParts; ++i) {
5673 // if it isn't first piece, alignment must be 1
5674 ISD::ArgFlagsTy MyFlags = Flags;
5675 if (NumParts > 1 && i == 0)
5678 MyFlags.setOrigAlign(1);
5680 Ops.push_back(Parts[i]);
5681 Ops.push_back(DAG.getArgFlags(MyFlags));
5686 // Figure out the result value types. We start by making a list of
5687 // the potentially illegal return value types.
5688 SmallVector<MVT, 4> LoweredRetTys;
5689 SmallVector<MVT, 4> RetTys;
5690 ComputeValueVTs(*this, RetTy, RetTys);
5692 // Then we translate that to a list of legal types.
5693 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5695 MVT RegisterVT = getRegisterType(VT);
5696 unsigned NumRegs = getNumRegisters(VT);
5697 for (unsigned i = 0; i != NumRegs; ++i)
5698 LoweredRetTys.push_back(RegisterVT);
5701 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5703 // Create the CALL node.
5704 SDValue Res = DAG.getCall(CallingConv, dl,
5705 isVarArg, isTailCall, isInreg,
5706 DAG.getVTList(&LoweredRetTys[0],
5707 LoweredRetTys.size()),
5710 Chain = Res.getValue(LoweredRetTys.size() - 1);
5712 // Gather up the call result into a single value.
5713 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5714 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5717 AssertOp = ISD::AssertSext;
5719 AssertOp = ISD::AssertZext;
5721 SmallVector<SDValue, 4> ReturnValues;
5723 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5725 MVT RegisterVT = getRegisterType(VT);
5726 unsigned NumRegs = getNumRegisters(VT);
5727 unsigned RegNoEnd = NumRegs + RegNo;
5728 SmallVector<SDValue, 4> Results;
5729 for (; RegNo != RegNoEnd; ++RegNo)
5730 Results.push_back(Res.getValue(RegNo));
5731 SDValue ReturnValue =
5732 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5734 ReturnValues.push_back(ReturnValue);
5736 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5737 DAG.getVTList(&RetTys[0], RetTys.size()),
5738 &ReturnValues[0], ReturnValues.size());
5741 return std::make_pair(Res, Chain);
5744 void TargetLowering::LowerOperationWrapper(SDNode *N,
5745 SmallVectorImpl<SDValue> &Results,
5746 SelectionDAG &DAG) {
5747 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5749 Results.push_back(Res);
5752 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5753 assert(0 && "LowerOperation not implemented for this target!");
5759 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5760 SDValue Op = getValue(V);
5761 assert((Op.getOpcode() != ISD::CopyFromReg ||
5762 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5763 "Copy from a reg to the same reg!");
5764 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5766 RegsForValue RFV(TLI, Reg, V->getType());
5767 SDValue Chain = DAG.getEntryNode();
5768 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5769 PendingExports.push_back(Chain);
5772 #include "llvm/CodeGen/SelectionDAGISel.h"
5774 void SelectionDAGISel::
5775 LowerArguments(BasicBlock *LLVMBB) {
5776 // If this is the entry block, emit arguments.
5777 Function &F = *LLVMBB->getParent();
5778 SDValue OldRoot = SDL->DAG.getRoot();
5779 SmallVector<SDValue, 16> Args;
5780 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5783 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5785 SmallVector<MVT, 4> ValueVTs;
5786 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5787 unsigned NumValues = ValueVTs.size();
5788 if (!AI->use_empty()) {
5789 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5790 // If this argument is live outside of the entry block, insert a copy from
5791 // whereever we got it to the vreg that other BB's will reference it as.
5792 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5793 if (VMI != FuncInfo->ValueMap.end()) {
5794 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5800 // Finally, if the target has anything special to do, allow it to do so.
5801 // FIXME: this should insert code into the DAG!
5802 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5805 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5806 /// ensure constants are generated when needed. Remember the virtual registers
5807 /// that need to be added to the Machine PHI nodes as input. We cannot just
5808 /// directly add them, because expansion might result in multiple MBB's for one
5809 /// BB. As such, the start of the BB might correspond to a different MBB than
5813 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5814 TerminatorInst *TI = LLVMBB->getTerminator();
5816 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5818 // Check successor nodes' PHI nodes that expect a constant to be available
5820 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5821 BasicBlock *SuccBB = TI->getSuccessor(succ);
5822 if (!isa<PHINode>(SuccBB->begin())) continue;
5823 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5825 // If this terminator has multiple identical successors (common for
5826 // switches), only handle each succ once.
5827 if (!SuccsHandled.insert(SuccMBB)) continue;
5829 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5832 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5833 // nodes and Machine PHI nodes, but the incoming operands have not been
5835 for (BasicBlock::iterator I = SuccBB->begin();
5836 (PN = dyn_cast<PHINode>(I)); ++I) {
5837 // Ignore dead phi's.
5838 if (PN->use_empty()) continue;
5841 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5843 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5844 unsigned &RegOut = SDL->ConstantsOut[C];
5846 RegOut = FuncInfo->CreateRegForValue(C);
5847 SDL->CopyValueToVirtualRegister(C, RegOut);
5851 Reg = FuncInfo->ValueMap[PHIOp];
5853 assert(isa<AllocaInst>(PHIOp) &&
5854 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5855 "Didn't codegen value into a register!??");
5856 Reg = FuncInfo->CreateRegForValue(PHIOp);
5857 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5861 // Remember that this register needs to added to the machine PHI node as
5862 // the input for this MBB.
5863 SmallVector<MVT, 4> ValueVTs;
5864 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5865 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5866 MVT VT = ValueVTs[vti];
5867 unsigned NumRegisters = TLI.getNumRegisters(VT);
5868 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5869 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5870 Reg += NumRegisters;
5874 SDL->ConstantsOut.clear();
5877 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5878 /// supports legal types, and it emits MachineInstrs directly instead of
5879 /// creating SelectionDAG nodes.
5882 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5884 TerminatorInst *TI = LLVMBB->getTerminator();
5886 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5887 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5889 // Check successor nodes' PHI nodes that expect a constant to be available
5891 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5892 BasicBlock *SuccBB = TI->getSuccessor(succ);
5893 if (!isa<PHINode>(SuccBB->begin())) continue;
5894 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5896 // If this terminator has multiple identical successors (common for
5897 // switches), only handle each succ once.
5898 if (!SuccsHandled.insert(SuccMBB)) continue;
5900 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5903 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5904 // nodes and Machine PHI nodes, but the incoming operands have not been
5906 for (BasicBlock::iterator I = SuccBB->begin();
5907 (PN = dyn_cast<PHINode>(I)); ++I) {
5908 // Ignore dead phi's.
5909 if (PN->use_empty()) continue;
5911 // Only handle legal types. Two interesting things to note here. First,
5912 // by bailing out early, we may leave behind some dead instructions,
5913 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5914 // own moves. Second, this check is necessary becuase FastISel doesn't
5915 // use CreateRegForValue to create registers, so it always creates
5916 // exactly one register for each non-void instruction.
5917 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5918 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5921 VT = TLI.getTypeToTransformTo(VT);
5923 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5928 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5930 unsigned Reg = F->getRegForValue(PHIOp);
5932 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5935 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));