1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
51 /// LimitFloatPrecision - Generate low-precision inline sequences for
52 /// some float libcalls (6, 8 or 12 bits).
53 static unsigned LimitFloatPrecision;
55 static cl::opt<unsigned, true>
56 LimitFPPrecision("limit-float-precision",
57 cl::desc("Generate low-precision inline sequences "
58 "for some float libcalls"),
59 cl::location(LimitFloatPrecision),
62 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
63 /// insertvalue or extractvalue indices that identify a member, return
64 /// the linearized index of the start of the member.
66 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
67 const unsigned *Indices,
68 const unsigned *IndicesEnd,
69 unsigned CurIndex = 0) {
70 // Base case: We're done.
71 if (Indices && Indices == IndicesEnd)
74 // Given a struct type, recursively traverse the elements.
75 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
76 for (StructType::element_iterator EB = STy->element_begin(),
78 EE = STy->element_end();
80 if (Indices && *Indices == unsigned(EI - EB))
81 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
82 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
85 // Given an array type, recursively traverse the elements.
86 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
87 const Type *EltTy = ATy->getElementType();
88 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
89 if (Indices && *Indices == i)
90 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
91 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
94 // We haven't found the type we're looking for, so keep searching.
98 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
99 /// MVTs that represent all the individual underlying
100 /// non-aggregate types that comprise it.
102 /// If Offsets is non-null, it points to a vector to be filled in
103 /// with the in-memory offsets of each of the individual values.
105 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
106 SmallVectorImpl<MVT> &ValueVTs,
107 SmallVectorImpl<uint64_t> *Offsets = 0,
108 uint64_t StartingOffset = 0) {
109 // Given a struct type, recursively traverse the elements.
110 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
111 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
112 for (StructType::element_iterator EB = STy->element_begin(),
114 EE = STy->element_end();
116 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
117 StartingOffset + SL->getElementOffset(EI - EB));
120 // Given an array type, recursively traverse the elements.
121 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
122 const Type *EltTy = ATy->getElementType();
123 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
124 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
125 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
126 StartingOffset + i * EltSize);
129 // Base case: we can get an MVT for this LLVM IR type.
130 ValueVTs.push_back(TLI.getValueType(Ty));
132 Offsets->push_back(StartingOffset);
136 /// RegsForValue - This struct represents the registers (physical or virtual)
137 /// that a particular set of values is assigned, and the type information about
138 /// the value. The most common situation is to represent one value at a time,
139 /// but struct or array values are handled element-wise as multiple values.
140 /// The splitting of aggregates is performed recursively, so that we never
141 /// have aggregate-typed registers. The values at this point do not necessarily
142 /// have legal types, so each value may require one or more registers of some
145 struct VISIBILITY_HIDDEN RegsForValue {
146 /// TLI - The TargetLowering object.
148 const TargetLowering *TLI;
150 /// ValueVTs - The value types of the values, which may not be legal, and
151 /// may need be promoted or synthesized from one or more registers.
153 SmallVector<MVT, 4> ValueVTs;
155 /// RegVTs - The value types of the registers. This is the same size as
156 /// ValueVTs and it records, for each value, what the type of the assigned
157 /// register or registers are. (Individual values are never synthesized
158 /// from more than one type of register.)
160 /// With virtual registers, the contents of RegVTs is redundant with TLI's
161 /// getRegisterType member function, however when with physical registers
162 /// it is necessary to have a separate record of the types.
164 SmallVector<MVT, 4> RegVTs;
166 /// Regs - This list holds the registers assigned to the values.
167 /// Each legal or promoted value requires one register, and each
168 /// expanded value requires multiple registers.
170 SmallVector<unsigned, 4> Regs;
172 RegsForValue() : TLI(0) {}
174 RegsForValue(const TargetLowering &tli,
175 const SmallVector<unsigned, 4> ®s,
176 MVT regvt, MVT valuevt)
177 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
178 RegsForValue(const TargetLowering &tli,
179 const SmallVector<unsigned, 4> ®s,
180 const SmallVector<MVT, 4> ®vts,
181 const SmallVector<MVT, 4> &valuevts)
182 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
183 RegsForValue(const TargetLowering &tli,
184 unsigned Reg, const Type *Ty) : TLI(&tli) {
185 ComputeValueVTs(tli, Ty, ValueVTs);
187 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
188 MVT ValueVT = ValueVTs[Value];
189 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
190 MVT RegisterVT = TLI->getRegisterType(ValueVT);
191 for (unsigned i = 0; i != NumRegs; ++i)
192 Regs.push_back(Reg + i);
193 RegVTs.push_back(RegisterVT);
198 /// append - Add the specified values to this one.
199 void append(const RegsForValue &RHS) {
201 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
202 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
203 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
207 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
208 /// this value and returns the result as a ValueVTs value. This uses
209 /// Chain/Flag as the input and updates them for the output Chain/Flag.
210 /// If the Flag pointer is NULL, no flag is used.
211 SDValue getCopyFromRegs(SelectionDAG &DAG,
212 SDValue &Chain, SDValue *Flag) const;
214 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
215 /// specified value into the registers specified by this object. This uses
216 /// Chain/Flag as the input and updates them for the output Chain/Flag.
217 /// If the Flag pointer is NULL, no flag is used.
218 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
219 SDValue &Chain, SDValue *Flag) const;
221 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
222 /// operand list. This adds the code marker and includes the number of
223 /// values added into it.
224 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
225 std::vector<SDValue> &Ops) const;
229 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
230 /// PHI nodes or outside of the basic block that defines it, or used by a
231 /// switch or atomic instruction, which may expand to multiple basic blocks.
232 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
233 if (isa<PHINode>(I)) return true;
234 BasicBlock *BB = I->getParent();
235 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
236 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
237 // FIXME: Remove switchinst special case.
238 isa<SwitchInst>(*UI))
243 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
244 /// entry block, return true. This includes arguments used by switches, since
245 /// the switch may expand into multiple basic blocks.
246 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
247 // With FastISel active, we may be splitting blocks, so force creation
248 // of virtual registers for all non-dead arguments.
249 // Don't force virtual registers for byval arguments though, because
250 // fast-isel can't handle those in all cases.
251 if (EnableFastISel && !A->hasByValAttr())
252 return A->use_empty();
254 BasicBlock *Entry = A->getParent()->begin();
255 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
256 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
257 return false; // Use not in entry block.
261 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
265 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
266 bool EnableFastISel) {
269 RegInfo = &MF->getRegInfo();
271 // Create a vreg for each argument register that is not dead and is used
272 // outside of the entry block for the function.
273 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
275 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
276 InitializeRegForValue(AI);
278 // Initialize the mapping of values to registers. This is only set up for
279 // instruction values that are used outside of the block that defines
281 Function::iterator BB = Fn->begin(), EB = Fn->end();
282 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
283 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
284 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
285 const Type *Ty = AI->getAllocatedType();
286 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
288 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
291 TySize *= CUI->getZExtValue(); // Get total allocated size.
292 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
293 StaticAllocaMap[AI] =
294 MF->getFrameInfo()->CreateStackObject(TySize, Align);
297 for (; BB != EB; ++BB)
298 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
299 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
300 if (!isa<AllocaInst>(I) ||
301 !StaticAllocaMap.count(cast<AllocaInst>(I)))
302 InitializeRegForValue(I);
304 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
305 // also creates the initial PHI MachineInstrs, though none of the input
306 // operands are populated.
307 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
308 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
312 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
315 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
316 if (PN->use_empty()) continue;
318 unsigned PHIReg = ValueMap[PN];
319 assert(PHIReg && "PHI node does not have an assigned virtual register!");
321 SmallVector<MVT, 4> ValueVTs;
322 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
323 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
324 MVT VT = ValueVTs[vti];
325 unsigned NumRegisters = TLI.getNumRegisters(VT);
326 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
327 for (unsigned i = 0; i != NumRegisters; ++i)
328 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
329 PHIReg += NumRegisters;
335 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
336 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
339 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
340 /// the correctly promoted or expanded types. Assign these registers
341 /// consecutive vreg numbers and return the first assigned number.
343 /// In the case that the given value has struct or array type, this function
344 /// will assign registers for each member or element.
346 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
347 SmallVector<MVT, 4> ValueVTs;
348 ComputeValueVTs(TLI, V->getType(), ValueVTs);
350 unsigned FirstReg = 0;
351 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
352 MVT ValueVT = ValueVTs[Value];
353 MVT RegisterVT = TLI.getRegisterType(ValueVT);
355 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
356 for (unsigned i = 0; i != NumRegs; ++i) {
357 unsigned R = MakeReg(RegisterVT);
358 if (!FirstReg) FirstReg = R;
364 /// getCopyFromParts - Create a value that contains the specified legal parts
365 /// combined into the value they represent. If the parts combine to a type
366 /// larger then ValueVT then AssertOp can be used to specify whether the extra
367 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
368 /// (ISD::AssertSext).
369 static SDValue getCopyFromParts(SelectionDAG &DAG,
370 const SDValue *Parts,
374 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
375 assert(NumParts > 0 && "No parts to assemble!");
376 TargetLowering &TLI = DAG.getTargetLoweringInfo();
377 SDValue Val = Parts[0];
380 // Assemble the value from multiple parts.
381 if (!ValueVT.isVector()) {
382 unsigned PartBits = PartVT.getSizeInBits();
383 unsigned ValueBits = ValueVT.getSizeInBits();
385 // Assemble the power of 2 part.
386 unsigned RoundParts = NumParts & (NumParts - 1) ?
387 1 << Log2_32(NumParts) : NumParts;
388 unsigned RoundBits = PartBits * RoundParts;
389 MVT RoundVT = RoundBits == ValueBits ?
390 ValueVT : MVT::getIntegerVT(RoundBits);
393 MVT HalfVT = ValueVT.isInteger() ?
394 MVT::getIntegerVT(RoundBits/2) :
395 MVT::getFloatingPointVT(RoundBits/2);
397 if (RoundParts > 2) {
398 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
399 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
402 Lo = DAG.getNode(ISD::BIT_CONVERT, HalfVT, Parts[0]);
403 Hi = DAG.getNode(ISD::BIT_CONVERT, HalfVT, Parts[1]);
405 if (TLI.isBigEndian())
407 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
409 if (RoundParts < NumParts) {
410 // Assemble the trailing non-power-of-2 part.
411 unsigned OddParts = NumParts - RoundParts;
412 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
413 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
415 // Combine the round and odd parts.
417 if (TLI.isBigEndian())
419 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
420 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
421 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
422 DAG.getConstant(Lo.getValueType().getSizeInBits(),
423 TLI.getShiftAmountTy()));
424 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
425 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
428 // Handle a multi-element vector.
429 MVT IntermediateVT, RegisterVT;
430 unsigned NumIntermediates;
432 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
434 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
435 NumParts = NumRegs; // Silence a compiler warning.
436 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
437 assert(RegisterVT == Parts[0].getValueType() &&
438 "Part type doesn't match part!");
440 // Assemble the parts into intermediate operands.
441 SmallVector<SDValue, 8> Ops(NumIntermediates);
442 if (NumIntermediates == NumParts) {
443 // If the register was not expanded, truncate or copy the value,
445 for (unsigned i = 0; i != NumParts; ++i)
446 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
447 PartVT, IntermediateVT);
448 } else if (NumParts > 0) {
449 // If the intermediate type was expanded, build the intermediate operands
451 assert(NumParts % NumIntermediates == 0 &&
452 "Must expand into a divisible number of parts!");
453 unsigned Factor = NumParts / NumIntermediates;
454 for (unsigned i = 0; i != NumIntermediates; ++i)
455 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
456 PartVT, IntermediateVT);
459 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
461 Val = DAG.getNode(IntermediateVT.isVector() ?
462 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
463 ValueVT, &Ops[0], NumIntermediates);
467 // There is now one part, held in Val. Correct it to match ValueVT.
468 PartVT = Val.getValueType();
470 if (PartVT == ValueVT)
473 if (PartVT.isVector()) {
474 assert(ValueVT.isVector() && "Unknown vector conversion!");
475 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
478 if (ValueVT.isVector()) {
479 assert(ValueVT.getVectorElementType() == PartVT &&
480 ValueVT.getVectorNumElements() == 1 &&
481 "Only trivial scalar-to-vector conversions should get here!");
482 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
485 if (PartVT.isInteger() &&
486 ValueVT.isInteger()) {
487 if (ValueVT.bitsLT(PartVT)) {
488 // For a truncate, see if we have any information to
489 // indicate whether the truncated bits will always be
490 // zero or sign-extension.
491 if (AssertOp != ISD::DELETED_NODE)
492 Val = DAG.getNode(AssertOp, PartVT, Val,
493 DAG.getValueType(ValueVT));
494 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
496 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
500 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
501 if (ValueVT.bitsLT(Val.getValueType()))
502 // FP_ROUND's are always exact here.
503 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
504 DAG.getIntPtrConstant(1));
505 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
508 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
509 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
511 assert(0 && "Unknown mismatch!");
515 /// getCopyToParts - Create a series of nodes that contain the specified value
516 /// split into legal parts. If the parts contain more bits than Val, then, for
517 /// integers, ExtendKind can be used to specify how to generate the extra bits.
518 static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
519 SDValue *Parts, unsigned NumParts, MVT PartVT,
520 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
521 TargetLowering &TLI = DAG.getTargetLoweringInfo();
522 MVT PtrVT = TLI.getPointerTy();
523 MVT ValueVT = Val.getValueType();
524 unsigned PartBits = PartVT.getSizeInBits();
525 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
530 if (!ValueVT.isVector()) {
531 if (PartVT == ValueVT) {
532 assert(NumParts == 1 && "No-op copy with multiple parts!");
537 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
538 // If the parts cover more bits than the value has, promote the value.
539 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
540 assert(NumParts == 1 && "Do not know what to promote to!");
541 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
542 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
543 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
544 Val = DAG.getNode(ExtendKind, ValueVT, Val);
546 assert(0 && "Unknown mismatch!");
548 } else if (PartBits == ValueVT.getSizeInBits()) {
549 // Different types of the same size.
550 assert(NumParts == 1 && PartVT != ValueVT);
551 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
552 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
553 // If the parts cover less bits than value has, truncate the value.
554 if (PartVT.isInteger() && ValueVT.isInteger()) {
555 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
556 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
558 assert(0 && "Unknown mismatch!");
562 // The value may have changed - recompute ValueVT.
563 ValueVT = Val.getValueType();
564 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
565 "Failed to tile the value with PartVT!");
568 assert(PartVT == ValueVT && "Type conversion failed!");
573 // Expand the value into multiple parts.
574 if (NumParts & (NumParts - 1)) {
575 // The number of parts is not a power of 2. Split off and copy the tail.
576 assert(PartVT.isInteger() && ValueVT.isInteger() &&
577 "Do not know what to expand to!");
578 unsigned RoundParts = 1 << Log2_32(NumParts);
579 unsigned RoundBits = RoundParts * PartBits;
580 unsigned OddParts = NumParts - RoundParts;
581 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
582 DAG.getConstant(RoundBits,
583 TLI.getShiftAmountTy()));
584 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
585 if (TLI.isBigEndian())
586 // The odd parts were reversed by getCopyToParts - unreverse them.
587 std::reverse(Parts + RoundParts, Parts + NumParts);
588 NumParts = RoundParts;
589 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
590 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
593 // The number of parts is a power of 2. Repeatedly bisect the value using
595 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
596 MVT::getIntegerVT(ValueVT.getSizeInBits()),
598 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
599 for (unsigned i = 0; i < NumParts; i += StepSize) {
600 unsigned ThisBits = StepSize * PartBits / 2;
601 MVT ThisVT = MVT::getIntegerVT (ThisBits);
602 SDValue &Part0 = Parts[i];
603 SDValue &Part1 = Parts[i+StepSize/2];
605 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
606 DAG.getConstant(1, PtrVT));
607 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
608 DAG.getConstant(0, PtrVT));
610 if (ThisBits == PartBits && ThisVT != PartVT) {
611 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
612 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
617 if (TLI.isBigEndian())
618 std::reverse(Parts, Parts + NumParts);
625 if (PartVT != ValueVT) {
626 if (PartVT.isVector()) {
627 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
629 assert(ValueVT.getVectorElementType() == PartVT &&
630 ValueVT.getVectorNumElements() == 1 &&
631 "Only trivial vector-to-scalar conversions should get here!");
632 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
633 DAG.getConstant(0, PtrVT));
641 // Handle a multi-element vector.
642 MVT IntermediateVT, RegisterVT;
643 unsigned NumIntermediates;
645 DAG.getTargetLoweringInfo()
646 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
648 unsigned NumElements = ValueVT.getVectorNumElements();
650 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
651 NumParts = NumRegs; // Silence a compiler warning.
652 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
654 // Split the vector into intermediate operands.
655 SmallVector<SDValue, 8> Ops(NumIntermediates);
656 for (unsigned i = 0; i != NumIntermediates; ++i)
657 if (IntermediateVT.isVector())
658 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
660 DAG.getConstant(i * (NumElements / NumIntermediates),
663 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
665 DAG.getConstant(i, PtrVT));
667 // Split the intermediate operands into legal parts.
668 if (NumParts == NumIntermediates) {
669 // If the register was not expanded, promote or copy the value,
671 for (unsigned i = 0; i != NumParts; ++i)
672 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
673 } else if (NumParts > 0) {
674 // If the intermediate type was expanded, split each the value into
676 assert(NumParts % NumIntermediates == 0 &&
677 "Must expand into a divisible number of parts!");
678 unsigned Factor = NumParts / NumIntermediates;
679 for (unsigned i = 0; i != NumIntermediates; ++i)
680 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
685 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
688 TD = DAG.getTarget().getTargetData();
691 /// clear - Clear out the curret SelectionDAG and the associated
692 /// state and prepare this SelectionDAGLowering object to be used
693 /// for a new block. This doesn't clear out information about
694 /// additional blocks that are needed to complete switch lowering
695 /// or PHI node updating; that information is cleared out as it is
697 void SelectionDAGLowering::clear() {
699 PendingLoads.clear();
700 PendingExports.clear();
704 /// getRoot - Return the current virtual root of the Selection DAG,
705 /// flushing any PendingLoad items. This must be done before emitting
706 /// a store or any other node that may need to be ordered after any
707 /// prior load instructions.
709 SDValue SelectionDAGLowering::getRoot() {
710 if (PendingLoads.empty())
711 return DAG.getRoot();
713 if (PendingLoads.size() == 1) {
714 SDValue Root = PendingLoads[0];
716 PendingLoads.clear();
720 // Otherwise, we have to make a token factor node.
721 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
722 &PendingLoads[0], PendingLoads.size());
723 PendingLoads.clear();
728 /// getControlRoot - Similar to getRoot, but instead of flushing all the
729 /// PendingLoad items, flush all the PendingExports items. It is necessary
730 /// to do this before emitting a terminator instruction.
732 SDValue SelectionDAGLowering::getControlRoot() {
733 SDValue Root = DAG.getRoot();
735 if (PendingExports.empty())
738 // Turn all of the CopyToReg chains into one factored node.
739 if (Root.getOpcode() != ISD::EntryToken) {
740 unsigned i = 0, e = PendingExports.size();
741 for (; i != e; ++i) {
742 assert(PendingExports[i].getNode()->getNumOperands() > 1);
743 if (PendingExports[i].getNode()->getOperand(0) == Root)
744 break; // Don't add the root if we already indirectly depend on it.
748 PendingExports.push_back(Root);
751 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
753 PendingExports.size());
754 PendingExports.clear();
759 void SelectionDAGLowering::visit(Instruction &I) {
760 visit(I.getOpcode(), I);
763 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
764 // Note: this doesn't use InstVisitor, because it has to work with
765 // ConstantExpr's in addition to instructions.
767 default: assert(0 && "Unknown instruction type encountered!");
769 // Build the switch statement using the Instruction.def file.
770 #define HANDLE_INST(NUM, OPCODE, CLASS) \
771 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
772 #include "llvm/Instruction.def"
776 void SelectionDAGLowering::visitAdd(User &I) {
777 if (I.getType()->isFPOrFPVector())
778 visitBinary(I, ISD::FADD);
780 visitBinary(I, ISD::ADD);
783 void SelectionDAGLowering::visitMul(User &I) {
784 if (I.getType()->isFPOrFPVector())
785 visitBinary(I, ISD::FMUL);
787 visitBinary(I, ISD::MUL);
790 SDValue SelectionDAGLowering::getValue(const Value *V) {
791 SDValue &N = NodeMap[V];
792 if (N.getNode()) return N;
794 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
795 MVT VT = TLI.getValueType(V->getType(), true);
797 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
798 return N = DAG.getConstant(*CI, VT);
800 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
801 return N = DAG.getGlobalAddress(GV, VT);
803 if (isa<ConstantPointerNull>(C))
804 return N = DAG.getConstant(0, TLI.getPointerTy());
806 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
807 return N = DAG.getConstantFP(*CFP, VT);
809 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
810 !V->getType()->isAggregateType())
811 return N = DAG.getNode(ISD::UNDEF, VT);
813 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
814 visit(CE->getOpcode(), *CE);
815 SDValue N1 = NodeMap[V];
816 assert(N1.getNode() && "visit didn't populate the ValueMap!");
820 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
821 SmallVector<SDValue, 4> Constants;
822 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
824 SDNode *Val = getValue(*OI).getNode();
825 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
826 Constants.push_back(SDValue(Val, i));
828 return DAG.getMergeValues(&Constants[0], Constants.size());
831 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
832 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
833 "Unknown struct or array constant!");
835 SmallVector<MVT, 4> ValueVTs;
836 ComputeValueVTs(TLI, C->getType(), ValueVTs);
837 unsigned NumElts = ValueVTs.size();
839 return SDValue(); // empty struct
840 SmallVector<SDValue, 4> Constants(NumElts);
841 for (unsigned i = 0; i != NumElts; ++i) {
842 MVT EltVT = ValueVTs[i];
843 if (isa<UndefValue>(C))
844 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
845 else if (EltVT.isFloatingPoint())
846 Constants[i] = DAG.getConstantFP(0, EltVT);
848 Constants[i] = DAG.getConstant(0, EltVT);
850 return DAG.getMergeValues(&Constants[0], NumElts);
853 const VectorType *VecTy = cast<VectorType>(V->getType());
854 unsigned NumElements = VecTy->getNumElements();
856 // Now that we know the number and type of the elements, get that number of
857 // elements into the Ops array based on what kind of constant it is.
858 SmallVector<SDValue, 16> Ops;
859 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
860 for (unsigned i = 0; i != NumElements; ++i)
861 Ops.push_back(getValue(CP->getOperand(i)));
863 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
864 "Unknown vector constant!");
865 MVT EltVT = TLI.getValueType(VecTy->getElementType());
868 if (isa<UndefValue>(C))
869 Op = DAG.getNode(ISD::UNDEF, EltVT);
870 else if (EltVT.isFloatingPoint())
871 Op = DAG.getConstantFP(0, EltVT);
873 Op = DAG.getConstant(0, EltVT);
874 Ops.assign(NumElements, Op);
877 // Create a BUILD_VECTOR node.
878 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
881 // If this is a static alloca, generate it as the frameindex instead of
883 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
884 DenseMap<const AllocaInst*, int>::iterator SI =
885 FuncInfo.StaticAllocaMap.find(AI);
886 if (SI != FuncInfo.StaticAllocaMap.end())
887 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
890 unsigned InReg = FuncInfo.ValueMap[V];
891 assert(InReg && "Value not in map!");
893 RegsForValue RFV(TLI, InReg, V->getType());
894 SDValue Chain = DAG.getEntryNode();
895 return RFV.getCopyFromRegs(DAG, Chain, NULL);
899 void SelectionDAGLowering::visitRet(ReturnInst &I) {
900 if (I.getNumOperands() == 0) {
901 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
905 SmallVector<SDValue, 8> NewValues;
906 NewValues.push_back(getControlRoot());
907 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
908 SmallVector<MVT, 4> ValueVTs;
909 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
910 unsigned NumValues = ValueVTs.size();
911 if (NumValues == 0) continue;
913 SDValue RetOp = getValue(I.getOperand(i));
914 for (unsigned j = 0, f = NumValues; j != f; ++j) {
915 MVT VT = ValueVTs[j];
917 // FIXME: C calling convention requires the return type to be promoted to
918 // at least 32-bit. But this is not necessary for non-C calling
920 if (VT.isInteger()) {
921 MVT MinVT = TLI.getRegisterType(MVT::i32);
922 if (VT.bitsLT(MinVT))
926 unsigned NumParts = TLI.getNumRegisters(VT);
927 MVT PartVT = TLI.getRegisterType(VT);
928 SmallVector<SDValue, 4> Parts(NumParts);
929 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
931 const Function *F = I.getParent()->getParent();
932 if (F->paramHasAttr(0, Attribute::SExt))
933 ExtendKind = ISD::SIGN_EXTEND;
934 else if (F->paramHasAttr(0, Attribute::ZExt))
935 ExtendKind = ISD::ZERO_EXTEND;
937 getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j),
938 &Parts[0], NumParts, PartVT, ExtendKind);
940 // 'inreg' on function refers to return value
941 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
942 if (F->paramHasAttr(0, Attribute::InReg))
944 for (unsigned i = 0; i < NumParts; ++i) {
945 NewValues.push_back(Parts[i]);
946 NewValues.push_back(DAG.getArgFlags(Flags));
950 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
951 &NewValues[0], NewValues.size()));
954 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
955 /// the current basic block, add it to ValueMap now so that we'll get a
957 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
958 // No need to export constants.
959 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
962 if (FuncInfo.isExportedInst(V)) return;
964 unsigned Reg = FuncInfo.InitializeRegForValue(V);
965 CopyValueToVirtualRegister(V, Reg);
968 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
969 const BasicBlock *FromBB) {
970 // The operands of the setcc have to be in this block. We don't know
971 // how to export them from some other block.
972 if (Instruction *VI = dyn_cast<Instruction>(V)) {
973 // Can export from current BB.
974 if (VI->getParent() == FromBB)
977 // Is already exported, noop.
978 return FuncInfo.isExportedInst(V);
981 // If this is an argument, we can export it if the BB is the entry block or
982 // if it is already exported.
983 if (isa<Argument>(V)) {
984 if (FromBB == &FromBB->getParent()->getEntryBlock())
987 // Otherwise, can only export this if it is already exported.
988 return FuncInfo.isExportedInst(V);
991 // Otherwise, constants can always be exported.
995 static bool InBlock(const Value *V, const BasicBlock *BB) {
996 if (const Instruction *I = dyn_cast<Instruction>(V))
997 return I->getParent() == BB;
1001 /// getFCmpCondCode - Return the ISD condition code corresponding to
1002 /// the given LLVM IR floating-point condition code. This includes
1003 /// consideration of global floating-point math flags.
1005 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1006 ISD::CondCode FPC, FOC;
1008 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1009 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1010 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1011 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1012 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1013 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1014 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1015 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1016 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1017 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1018 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1019 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1020 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1021 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1022 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1023 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1025 assert(0 && "Invalid FCmp predicate opcode!");
1026 FOC = FPC = ISD::SETFALSE;
1029 if (FiniteOnlyFPMath())
1035 /// getICmpCondCode - Return the ISD condition code corresponding to
1036 /// the given LLVM IR integer condition code.
1038 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1040 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1041 case ICmpInst::ICMP_NE: return ISD::SETNE;
1042 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1043 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1044 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1045 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1046 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1047 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1048 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1049 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1051 assert(0 && "Invalid ICmp predicate opcode!");
1056 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1057 /// This function emits a branch and is used at the leaves of an OR or an
1058 /// AND operator tree.
1061 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1062 MachineBasicBlock *TBB,
1063 MachineBasicBlock *FBB,
1064 MachineBasicBlock *CurBB) {
1065 const BasicBlock *BB = CurBB->getBasicBlock();
1067 // If the leaf of the tree is a comparison, merge the condition into
1069 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1070 // The operands of the cmp have to be in this block. We don't know
1071 // how to export them from some other block. If this is the first block
1072 // of the sequence, no exporting is needed.
1073 if (CurBB == CurMBB ||
1074 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1075 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1076 ISD::CondCode Condition;
1077 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1078 Condition = getICmpCondCode(IC->getPredicate());
1079 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1080 Condition = getFCmpCondCode(FC->getPredicate());
1082 Condition = ISD::SETEQ; // silence warning.
1083 assert(0 && "Unknown compare instruction");
1086 CaseBlock CB(Condition, BOp->getOperand(0),
1087 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1088 SwitchCases.push_back(CB);
1093 // Create a CaseBlock record representing this branch.
1094 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1095 NULL, TBB, FBB, CurBB);
1096 SwitchCases.push_back(CB);
1099 /// FindMergedConditions - If Cond is an expression like
1100 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1101 MachineBasicBlock *TBB,
1102 MachineBasicBlock *FBB,
1103 MachineBasicBlock *CurBB,
1105 // If this node is not part of the or/and tree, emit it as a branch.
1106 Instruction *BOp = dyn_cast<Instruction>(Cond);
1107 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1108 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1109 BOp->getParent() != CurBB->getBasicBlock() ||
1110 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1111 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1112 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1116 // Create TmpBB after CurBB.
1117 MachineFunction::iterator BBI = CurBB;
1118 MachineFunction &MF = DAG.getMachineFunction();
1119 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1120 CurBB->getParent()->insert(++BBI, TmpBB);
1122 if (Opc == Instruction::Or) {
1123 // Codegen X | Y as:
1131 // Emit the LHS condition.
1132 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1134 // Emit the RHS condition into TmpBB.
1135 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1137 assert(Opc == Instruction::And && "Unknown merge op!");
1138 // Codegen X & Y as:
1145 // This requires creation of TmpBB after CurBB.
1147 // Emit the LHS condition.
1148 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1150 // Emit the RHS condition into TmpBB.
1151 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1155 /// If the set of cases should be emitted as a series of branches, return true.
1156 /// If we should emit this as a bunch of and/or'd together conditions, return
1159 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1160 if (Cases.size() != 2) return true;
1162 // If this is two comparisons of the same values or'd or and'd together, they
1163 // will get folded into a single comparison, so don't emit two blocks.
1164 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1165 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1166 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1167 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1174 void SelectionDAGLowering::visitBr(BranchInst &I) {
1175 // Update machine-CFG edges.
1176 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1178 // Figure out which block is immediately after the current one.
1179 MachineBasicBlock *NextBlock = 0;
1180 MachineFunction::iterator BBI = CurMBB;
1181 if (++BBI != CurMBB->getParent()->end())
1184 if (I.isUnconditional()) {
1185 // Update machine-CFG edges.
1186 CurMBB->addSuccessor(Succ0MBB);
1188 // If this is not a fall-through branch, emit the branch.
1189 if (Succ0MBB != NextBlock)
1190 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1191 DAG.getBasicBlock(Succ0MBB)));
1195 // If this condition is one of the special cases we handle, do special stuff
1197 Value *CondVal = I.getCondition();
1198 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1200 // If this is a series of conditions that are or'd or and'd together, emit
1201 // this as a sequence of branches instead of setcc's with and/or operations.
1202 // For example, instead of something like:
1215 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1216 if (BOp->hasOneUse() &&
1217 (BOp->getOpcode() == Instruction::And ||
1218 BOp->getOpcode() == Instruction::Or)) {
1219 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1220 // If the compares in later blocks need to use values not currently
1221 // exported from this block, export them now. This block should always
1222 // be the first entry.
1223 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1225 // Allow some cases to be rejected.
1226 if (ShouldEmitAsBranches(SwitchCases)) {
1227 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1228 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1229 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1232 // Emit the branch for this block.
1233 visitSwitchCase(SwitchCases[0]);
1234 SwitchCases.erase(SwitchCases.begin());
1238 // Okay, we decided not to do this, remove any inserted MBB's and clear
1240 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1241 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1243 SwitchCases.clear();
1247 // Create a CaseBlock record representing this branch.
1248 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1249 NULL, Succ0MBB, Succ1MBB, CurMBB);
1250 // Use visitSwitchCase to actually insert the fast branch sequence for this
1252 visitSwitchCase(CB);
1255 /// visitSwitchCase - Emits the necessary code to represent a single node in
1256 /// the binary search tree resulting from lowering a switch instruction.
1257 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1259 SDValue CondLHS = getValue(CB.CmpLHS);
1261 // Build the setcc now.
1262 if (CB.CmpMHS == NULL) {
1263 // Fold "(X == true)" to X and "(X == false)" to !X to
1264 // handle common cases produced by branch lowering.
1265 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1267 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1268 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1269 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1271 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1273 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1275 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1276 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1278 SDValue CmpOp = getValue(CB.CmpMHS);
1279 MVT VT = CmpOp.getValueType();
1281 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1282 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1284 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1285 Cond = DAG.getSetCC(MVT::i1, SUB,
1286 DAG.getConstant(High-Low, VT), ISD::SETULE);
1290 // Update successor info
1291 CurMBB->addSuccessor(CB.TrueBB);
1292 CurMBB->addSuccessor(CB.FalseBB);
1294 // Set NextBlock to be the MBB immediately after the current one, if any.
1295 // This is used to avoid emitting unnecessary branches to the next block.
1296 MachineBasicBlock *NextBlock = 0;
1297 MachineFunction::iterator BBI = CurMBB;
1298 if (++BBI != CurMBB->getParent()->end())
1301 // If the lhs block is the next block, invert the condition so that we can
1302 // fall through to the lhs instead of the rhs block.
1303 if (CB.TrueBB == NextBlock) {
1304 std::swap(CB.TrueBB, CB.FalseBB);
1305 SDValue True = DAG.getConstant(1, Cond.getValueType());
1306 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1308 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1309 DAG.getBasicBlock(CB.TrueBB));
1311 // If the branch was constant folded, fix up the CFG.
1312 if (BrCond.getOpcode() == ISD::BR) {
1313 CurMBB->removeSuccessor(CB.FalseBB);
1314 DAG.setRoot(BrCond);
1316 // Otherwise, go ahead and insert the false branch.
1317 if (BrCond == getControlRoot())
1318 CurMBB->removeSuccessor(CB.TrueBB);
1320 if (CB.FalseBB == NextBlock)
1321 DAG.setRoot(BrCond);
1323 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1324 DAG.getBasicBlock(CB.FalseBB)));
1328 /// visitJumpTable - Emit JumpTable node in the current MBB
1329 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1330 // Emit the code for the jump table
1331 assert(JT.Reg != -1U && "Should lower JT Header first!");
1332 MVT PTy = TLI.getPointerTy();
1333 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1334 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1335 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1340 /// visitJumpTableHeader - This function emits necessary code to produce index
1341 /// in the JumpTable from switch case.
1342 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1343 JumpTableHeader &JTH) {
1344 // Subtract the lowest switch case value from the value being switched on
1345 // and conditional branch to default mbb if the result is greater than the
1346 // difference between smallest and largest cases.
1347 SDValue SwitchOp = getValue(JTH.SValue);
1348 MVT VT = SwitchOp.getValueType();
1349 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1350 DAG.getConstant(JTH.First, VT));
1352 // The SDNode we just created, which holds the value being switched on
1353 // minus the the smallest case value, needs to be copied to a virtual
1354 // register so it can be used as an index into the jump table in a
1355 // subsequent basic block. This value may be smaller or larger than the
1356 // target's pointer type, and therefore require extension or truncating.
1357 if (VT.bitsGT(TLI.getPointerTy()))
1358 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1360 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1362 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1363 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1364 JT.Reg = JumpTableReg;
1366 // Emit the range check for the jump table, and branch to the default
1367 // block for the switch statement if the value being switched on exceeds
1368 // the largest case in the switch.
1369 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1370 DAG.getConstant(JTH.Last-JTH.First,VT),
1373 // Set NextBlock to be the MBB immediately after the current one, if any.
1374 // This is used to avoid emitting unnecessary branches to the next block.
1375 MachineBasicBlock *NextBlock = 0;
1376 MachineFunction::iterator BBI = CurMBB;
1377 if (++BBI != CurMBB->getParent()->end())
1380 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1381 DAG.getBasicBlock(JT.Default));
1383 if (JT.MBB == NextBlock)
1384 DAG.setRoot(BrCond);
1386 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1387 DAG.getBasicBlock(JT.MBB)));
1392 /// visitBitTestHeader - This function emits necessary code to produce value
1393 /// suitable for "bit tests"
1394 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1395 // Subtract the minimum value
1396 SDValue SwitchOp = getValue(B.SValue);
1397 MVT VT = SwitchOp.getValueType();
1398 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1399 DAG.getConstant(B.First, VT));
1402 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1403 DAG.getConstant(B.Range, VT),
1407 if (VT.bitsGT(TLI.getShiftAmountTy()))
1408 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1410 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1412 // Make desired shift
1413 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1414 DAG.getConstant(1, TLI.getPointerTy()),
1417 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1418 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1421 // Set NextBlock to be the MBB immediately after the current one, if any.
1422 // This is used to avoid emitting unnecessary branches to the next block.
1423 MachineBasicBlock *NextBlock = 0;
1424 MachineFunction::iterator BBI = CurMBB;
1425 if (++BBI != CurMBB->getParent()->end())
1428 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1430 CurMBB->addSuccessor(B.Default);
1431 CurMBB->addSuccessor(MBB);
1433 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1434 DAG.getBasicBlock(B.Default));
1436 if (MBB == NextBlock)
1437 DAG.setRoot(BrRange);
1439 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1440 DAG.getBasicBlock(MBB)));
1445 /// visitBitTestCase - this function produces one "bit test"
1446 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1449 // Emit bit tests and jumps
1450 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1451 TLI.getPointerTy());
1453 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1454 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1455 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1456 DAG.getConstant(0, TLI.getPointerTy()),
1459 CurMBB->addSuccessor(B.TargetBB);
1460 CurMBB->addSuccessor(NextMBB);
1462 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1463 AndCmp, DAG.getBasicBlock(B.TargetBB));
1465 // Set NextBlock to be the MBB immediately after the current one, if any.
1466 // This is used to avoid emitting unnecessary branches to the next block.
1467 MachineBasicBlock *NextBlock = 0;
1468 MachineFunction::iterator BBI = CurMBB;
1469 if (++BBI != CurMBB->getParent()->end())
1472 if (NextMBB == NextBlock)
1475 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1476 DAG.getBasicBlock(NextMBB)));
1481 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1482 // Retrieve successors.
1483 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1484 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1486 if (isa<InlineAsm>(I.getCalledValue()))
1489 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1491 // If the value of the invoke is used outside of its defining block, make it
1492 // available as a virtual register.
1493 if (!I.use_empty()) {
1494 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1495 if (VMI != FuncInfo.ValueMap.end())
1496 CopyValueToVirtualRegister(&I, VMI->second);
1499 // Update successor info
1500 CurMBB->addSuccessor(Return);
1501 CurMBB->addSuccessor(LandingPad);
1503 // Drop into normal successor.
1504 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1505 DAG.getBasicBlock(Return)));
1508 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1511 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1512 /// small case ranges).
1513 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1514 CaseRecVector& WorkList,
1516 MachineBasicBlock* Default) {
1517 Case& BackCase = *(CR.Range.second-1);
1519 // Size is the number of Cases represented by this range.
1520 unsigned Size = CR.Range.second - CR.Range.first;
1524 // Get the MachineFunction which holds the current MBB. This is used when
1525 // inserting any additional MBBs necessary to represent the switch.
1526 MachineFunction *CurMF = CurMBB->getParent();
1528 // Figure out which block is immediately after the current one.
1529 MachineBasicBlock *NextBlock = 0;
1530 MachineFunction::iterator BBI = CR.CaseBB;
1532 if (++BBI != CurMBB->getParent()->end())
1535 // TODO: If any two of the cases has the same destination, and if one value
1536 // is the same as the other, but has one bit unset that the other has set,
1537 // use bit manipulation to do two compares at once. For example:
1538 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1540 // Rearrange the case blocks so that the last one falls through if possible.
1541 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1542 // The last case block won't fall through into 'NextBlock' if we emit the
1543 // branches in this order. See if rearranging a case value would help.
1544 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1545 if (I->BB == NextBlock) {
1546 std::swap(*I, BackCase);
1552 // Create a CaseBlock record representing a conditional branch to
1553 // the Case's target mbb if the value being switched on SV is equal
1555 MachineBasicBlock *CurBlock = CR.CaseBB;
1556 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1557 MachineBasicBlock *FallThrough;
1559 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1560 CurMF->insert(BBI, FallThrough);
1562 // If the last case doesn't match, go to the default block.
1563 FallThrough = Default;
1566 Value *RHS, *LHS, *MHS;
1568 if (I->High == I->Low) {
1569 // This is just small small case range :) containing exactly 1 case
1571 LHS = SV; RHS = I->High; MHS = NULL;
1574 LHS = I->Low; MHS = SV; RHS = I->High;
1576 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1578 // If emitting the first comparison, just call visitSwitchCase to emit the
1579 // code into the current block. Otherwise, push the CaseBlock onto the
1580 // vector to be later processed by SDISel, and insert the node's MBB
1581 // before the next MBB.
1582 if (CurBlock == CurMBB)
1583 visitSwitchCase(CB);
1585 SwitchCases.push_back(CB);
1587 CurBlock = FallThrough;
1593 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1594 return !DisableJumpTables &&
1595 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1596 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1599 /// handleJTSwitchCase - Emit jumptable for current switch case range
1600 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1601 CaseRecVector& WorkList,
1603 MachineBasicBlock* Default) {
1604 Case& FrontCase = *CR.Range.first;
1605 Case& BackCase = *(CR.Range.second-1);
1607 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1608 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1611 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1615 if (!areJTsAllowed(TLI) || TSize <= 3)
1618 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1622 DOUT << "Lowering jump table\n"
1623 << "First entry: " << First << ". Last entry: " << Last << "\n"
1624 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1626 // Get the MachineFunction which holds the current MBB. This is used when
1627 // inserting any additional MBBs necessary to represent the switch.
1628 MachineFunction *CurMF = CurMBB->getParent();
1630 // Figure out which block is immediately after the current one.
1631 MachineBasicBlock *NextBlock = 0;
1632 MachineFunction::iterator BBI = CR.CaseBB;
1634 if (++BBI != CurMBB->getParent()->end())
1637 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1639 // Create a new basic block to hold the code for loading the address
1640 // of the jump table, and jumping to it. Update successor information;
1641 // we will either branch to the default case for the switch, or the jump
1643 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1644 CurMF->insert(BBI, JumpTableBB);
1645 CR.CaseBB->addSuccessor(Default);
1646 CR.CaseBB->addSuccessor(JumpTableBB);
1648 // Build a vector of destination BBs, corresponding to each target
1649 // of the jump table. If the value of the jump table slot corresponds to
1650 // a case statement, push the case's BB onto the vector, otherwise, push
1652 std::vector<MachineBasicBlock*> DestBBs;
1653 int64_t TEI = First;
1654 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1655 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1656 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1658 if ((Low <= TEI) && (TEI <= High)) {
1659 DestBBs.push_back(I->BB);
1663 DestBBs.push_back(Default);
1667 // Update successor info. Add one edge to each unique successor.
1668 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1669 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1670 E = DestBBs.end(); I != E; ++I) {
1671 if (!SuccsHandled[(*I)->getNumber()]) {
1672 SuccsHandled[(*I)->getNumber()] = true;
1673 JumpTableBB->addSuccessor(*I);
1677 // Create a jump table index for this jump table, or return an existing
1679 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1681 // Set the jump table information so that we can codegen it as a second
1682 // MachineBasicBlock
1683 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1684 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1685 if (CR.CaseBB == CurMBB)
1686 visitJumpTableHeader(JT, JTH);
1688 JTCases.push_back(JumpTableBlock(JTH, JT));
1693 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1695 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1696 CaseRecVector& WorkList,
1698 MachineBasicBlock* Default) {
1699 // Get the MachineFunction which holds the current MBB. This is used when
1700 // inserting any additional MBBs necessary to represent the switch.
1701 MachineFunction *CurMF = CurMBB->getParent();
1703 // Figure out which block is immediately after the current one.
1704 MachineBasicBlock *NextBlock = 0;
1705 MachineFunction::iterator BBI = CR.CaseBB;
1707 if (++BBI != CurMBB->getParent()->end())
1710 Case& FrontCase = *CR.Range.first;
1711 Case& BackCase = *(CR.Range.second-1);
1712 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1714 // Size is the number of Cases represented by this range.
1715 unsigned Size = CR.Range.second - CR.Range.first;
1717 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1718 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1720 CaseItr Pivot = CR.Range.first + Size/2;
1722 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1723 // (heuristically) allow us to emit JumpTable's later.
1725 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1729 uint64_t LSize = FrontCase.size();
1730 uint64_t RSize = TSize-LSize;
1731 DOUT << "Selecting best pivot: \n"
1732 << "First: " << First << ", Last: " << Last <<"\n"
1733 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1734 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1736 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1737 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1738 assert((RBegin-LEnd>=1) && "Invalid case distance");
1739 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1740 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1741 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1742 // Should always split in some non-trivial place
1744 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1745 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1746 << "Metric: " << Metric << "\n";
1747 if (FMetric < Metric) {
1750 DOUT << "Current metric set to: " << FMetric << "\n";
1756 if (areJTsAllowed(TLI)) {
1757 // If our case is dense we *really* should handle it earlier!
1758 assert((FMetric > 0) && "Should handle dense range earlier!");
1760 Pivot = CR.Range.first + Size/2;
1763 CaseRange LHSR(CR.Range.first, Pivot);
1764 CaseRange RHSR(Pivot, CR.Range.second);
1765 Constant *C = Pivot->Low;
1766 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1768 // We know that we branch to the LHS if the Value being switched on is
1769 // less than the Pivot value, C. We use this to optimize our binary
1770 // tree a bit, by recognizing that if SV is greater than or equal to the
1771 // LHS's Case Value, and that Case Value is exactly one less than the
1772 // Pivot's Value, then we can branch directly to the LHS's Target,
1773 // rather than creating a leaf node for it.
1774 if ((LHSR.second - LHSR.first) == 1 &&
1775 LHSR.first->High == CR.GE &&
1776 cast<ConstantInt>(C)->getSExtValue() ==
1777 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1778 TrueBB = LHSR.first->BB;
1780 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1781 CurMF->insert(BBI, TrueBB);
1782 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1785 // Similar to the optimization above, if the Value being switched on is
1786 // known to be less than the Constant CR.LT, and the current Case Value
1787 // is CR.LT - 1, then we can branch directly to the target block for
1788 // the current Case Value, rather than emitting a RHS leaf node for it.
1789 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1790 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1791 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1792 FalseBB = RHSR.first->BB;
1794 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1795 CurMF->insert(BBI, FalseBB);
1796 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1799 // Create a CaseBlock record representing a conditional branch to
1800 // the LHS node if the value being switched on SV is less than C.
1801 // Otherwise, branch to LHS.
1802 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1804 if (CR.CaseBB == CurMBB)
1805 visitSwitchCase(CB);
1807 SwitchCases.push_back(CB);
1812 /// handleBitTestsSwitchCase - if current case range has few destination and
1813 /// range span less, than machine word bitwidth, encode case range into series
1814 /// of masks and emit bit tests with these masks.
1815 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1816 CaseRecVector& WorkList,
1818 MachineBasicBlock* Default){
1819 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1821 Case& FrontCase = *CR.Range.first;
1822 Case& BackCase = *(CR.Range.second-1);
1824 // Get the MachineFunction which holds the current MBB. This is used when
1825 // inserting any additional MBBs necessary to represent the switch.
1826 MachineFunction *CurMF = CurMBB->getParent();
1828 unsigned numCmps = 0;
1829 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1831 // Single case counts one, case range - two.
1832 if (I->Low == I->High)
1838 // Count unique destinations
1839 SmallSet<MachineBasicBlock*, 4> Dests;
1840 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1841 Dests.insert(I->BB);
1842 if (Dests.size() > 3)
1843 // Don't bother the code below, if there are too much unique destinations
1846 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1847 << "Total number of comparisons: " << numCmps << "\n";
1849 // Compute span of values.
1850 Constant* minValue = FrontCase.Low;
1851 Constant* maxValue = BackCase.High;
1852 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1853 cast<ConstantInt>(minValue)->getSExtValue();
1854 DOUT << "Compare range: " << range << "\n"
1855 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1856 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1858 if (range>=IntPtrBits ||
1859 (!(Dests.size() == 1 && numCmps >= 3) &&
1860 !(Dests.size() == 2 && numCmps >= 5) &&
1861 !(Dests.size() >= 3 && numCmps >= 6)))
1864 DOUT << "Emitting bit tests\n";
1865 int64_t lowBound = 0;
1867 // Optimize the case where all the case values fit in a
1868 // word without having to subtract minValue. In this case,
1869 // we can optimize away the subtraction.
1870 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1871 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1872 range = cast<ConstantInt>(maxValue)->getSExtValue();
1874 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1877 CaseBitsVector CasesBits;
1878 unsigned i, count = 0;
1880 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1881 MachineBasicBlock* Dest = I->BB;
1882 for (i = 0; i < count; ++i)
1883 if (Dest == CasesBits[i].BB)
1887 assert((count < 3) && "Too much destinations to test!");
1888 CasesBits.push_back(CaseBits(0, Dest, 0));
1892 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1893 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1895 for (uint64_t j = lo; j <= hi; j++) {
1896 CasesBits[i].Mask |= 1ULL << j;
1897 CasesBits[i].Bits++;
1901 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1905 // Figure out which block is immediately after the current one.
1906 MachineFunction::iterator BBI = CR.CaseBB;
1909 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1912 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1913 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1914 << ", BB: " << CasesBits[i].BB << "\n";
1916 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1917 CurMF->insert(BBI, CaseBB);
1918 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1923 BitTestBlock BTB(lowBound, range, SV,
1924 -1U, (CR.CaseBB == CurMBB),
1925 CR.CaseBB, Default, BTC);
1927 if (CR.CaseBB == CurMBB)
1928 visitBitTestHeader(BTB);
1930 BitTestCases.push_back(BTB);
1936 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1937 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1938 const SwitchInst& SI) {
1939 unsigned numCmps = 0;
1941 // Start with "simple" cases
1942 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1943 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1944 Cases.push_back(Case(SI.getSuccessorValue(i),
1945 SI.getSuccessorValue(i),
1948 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1950 // Merge case into clusters
1951 if (Cases.size()>=2)
1952 // Must recompute end() each iteration because it may be
1953 // invalidated by erase if we hold on to it
1954 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1955 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1956 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1957 MachineBasicBlock* nextBB = J->BB;
1958 MachineBasicBlock* currentBB = I->BB;
1960 // If the two neighboring cases go to the same destination, merge them
1961 // into a single case.
1962 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1970 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1971 if (I->Low != I->High)
1972 // A range counts double, since it requires two compares.
1979 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1980 // Figure out which block is immediately after the current one.
1981 MachineBasicBlock *NextBlock = 0;
1982 MachineFunction::iterator BBI = CurMBB;
1984 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1986 // If there is only the default destination, branch to it if it is not the
1987 // next basic block. Otherwise, just fall through.
1988 if (SI.getNumOperands() == 2) {
1989 // Update machine-CFG edges.
1991 // If this is not a fall-through branch, emit the branch.
1992 CurMBB->addSuccessor(Default);
1993 if (Default != NextBlock)
1994 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1995 DAG.getBasicBlock(Default)));
2000 // If there are any non-default case statements, create a vector of Cases
2001 // representing each one, and sort the vector so that we can efficiently
2002 // create a binary search tree from them.
2004 unsigned numCmps = Clusterify(Cases, SI);
2005 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2006 << ". Total compares: " << numCmps << "\n";
2008 // Get the Value to be switched on and default basic blocks, which will be
2009 // inserted into CaseBlock records, representing basic blocks in the binary
2011 Value *SV = SI.getOperand(0);
2013 // Push the initial CaseRec onto the worklist
2014 CaseRecVector WorkList;
2015 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2017 while (!WorkList.empty()) {
2018 // Grab a record representing a case range to process off the worklist
2019 CaseRec CR = WorkList.back();
2020 WorkList.pop_back();
2022 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2025 // If the range has few cases (two or less) emit a series of specific
2027 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2030 // If the switch has more than 5 blocks, and at least 40% dense, and the
2031 // target supports indirect branches, then emit a jump table rather than
2032 // lowering the switch to a binary tree of conditional branches.
2033 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2036 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2037 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2038 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2043 void SelectionDAGLowering::visitSub(User &I) {
2044 // -0.0 - X --> fneg
2045 const Type *Ty = I.getType();
2046 if (isa<VectorType>(Ty)) {
2047 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2048 const VectorType *DestTy = cast<VectorType>(I.getType());
2049 const Type *ElTy = DestTy->getElementType();
2050 if (ElTy->isFloatingPoint()) {
2051 unsigned VL = DestTy->getNumElements();
2052 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2053 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2055 SDValue Op2 = getValue(I.getOperand(1));
2056 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2062 if (Ty->isFloatingPoint()) {
2063 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2064 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2065 SDValue Op2 = getValue(I.getOperand(1));
2066 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2071 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2074 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2075 SDValue Op1 = getValue(I.getOperand(0));
2076 SDValue Op2 = getValue(I.getOperand(1));
2078 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2081 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2082 SDValue Op1 = getValue(I.getOperand(0));
2083 SDValue Op2 = getValue(I.getOperand(1));
2084 if (!isa<VectorType>(I.getType())) {
2085 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2086 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2087 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2088 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2091 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2094 void SelectionDAGLowering::visitICmp(User &I) {
2095 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2096 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2097 predicate = IC->getPredicate();
2098 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2099 predicate = ICmpInst::Predicate(IC->getPredicate());
2100 SDValue Op1 = getValue(I.getOperand(0));
2101 SDValue Op2 = getValue(I.getOperand(1));
2102 ISD::CondCode Opcode = getICmpCondCode(predicate);
2103 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2106 void SelectionDAGLowering::visitFCmp(User &I) {
2107 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2108 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2109 predicate = FC->getPredicate();
2110 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2111 predicate = FCmpInst::Predicate(FC->getPredicate());
2112 SDValue Op1 = getValue(I.getOperand(0));
2113 SDValue Op2 = getValue(I.getOperand(1));
2114 ISD::CondCode Condition = getFCmpCondCode(predicate);
2115 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2118 void SelectionDAGLowering::visitVICmp(User &I) {
2119 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2120 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2121 predicate = IC->getPredicate();
2122 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2123 predicate = ICmpInst::Predicate(IC->getPredicate());
2124 SDValue Op1 = getValue(I.getOperand(0));
2125 SDValue Op2 = getValue(I.getOperand(1));
2126 ISD::CondCode Opcode = getICmpCondCode(predicate);
2127 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2130 void SelectionDAGLowering::visitVFCmp(User &I) {
2131 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2132 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2133 predicate = FC->getPredicate();
2134 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2135 predicate = FCmpInst::Predicate(FC->getPredicate());
2136 SDValue Op1 = getValue(I.getOperand(0));
2137 SDValue Op2 = getValue(I.getOperand(1));
2138 ISD::CondCode Condition = getFCmpCondCode(predicate);
2139 MVT DestVT = TLI.getValueType(I.getType());
2141 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2144 void SelectionDAGLowering::visitSelect(User &I) {
2145 SmallVector<MVT, 4> ValueVTs;
2146 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2147 unsigned NumValues = ValueVTs.size();
2148 if (NumValues != 0) {
2149 SmallVector<SDValue, 4> Values(NumValues);
2150 SDValue Cond = getValue(I.getOperand(0));
2151 SDValue TrueVal = getValue(I.getOperand(1));
2152 SDValue FalseVal = getValue(I.getOperand(2));
2154 for (unsigned i = 0; i != NumValues; ++i)
2155 Values[i] = DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2156 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2157 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2159 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2160 &Values[0], NumValues));
2165 void SelectionDAGLowering::visitTrunc(User &I) {
2166 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2167 SDValue N = getValue(I.getOperand(0));
2168 MVT DestVT = TLI.getValueType(I.getType());
2169 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2172 void SelectionDAGLowering::visitZExt(User &I) {
2173 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2174 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2175 SDValue N = getValue(I.getOperand(0));
2176 MVT DestVT = TLI.getValueType(I.getType());
2177 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2180 void SelectionDAGLowering::visitSExt(User &I) {
2181 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2182 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2183 SDValue N = getValue(I.getOperand(0));
2184 MVT DestVT = TLI.getValueType(I.getType());
2185 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2188 void SelectionDAGLowering::visitFPTrunc(User &I) {
2189 // FPTrunc is never a no-op cast, no need to check
2190 SDValue N = getValue(I.getOperand(0));
2191 MVT DestVT = TLI.getValueType(I.getType());
2192 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2195 void SelectionDAGLowering::visitFPExt(User &I){
2196 // FPTrunc is never a no-op cast, no need to check
2197 SDValue N = getValue(I.getOperand(0));
2198 MVT DestVT = TLI.getValueType(I.getType());
2199 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2202 void SelectionDAGLowering::visitFPToUI(User &I) {
2203 // FPToUI is never a no-op cast, no need to check
2204 SDValue N = getValue(I.getOperand(0));
2205 MVT DestVT = TLI.getValueType(I.getType());
2206 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2209 void SelectionDAGLowering::visitFPToSI(User &I) {
2210 // FPToSI is never a no-op cast, no need to check
2211 SDValue N = getValue(I.getOperand(0));
2212 MVT DestVT = TLI.getValueType(I.getType());
2213 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2216 void SelectionDAGLowering::visitUIToFP(User &I) {
2217 // UIToFP is never a no-op cast, no need to check
2218 SDValue N = getValue(I.getOperand(0));
2219 MVT DestVT = TLI.getValueType(I.getType());
2220 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2223 void SelectionDAGLowering::visitSIToFP(User &I){
2224 // SIToFP is never a no-op cast, no need to check
2225 SDValue N = getValue(I.getOperand(0));
2226 MVT DestVT = TLI.getValueType(I.getType());
2227 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2230 void SelectionDAGLowering::visitPtrToInt(User &I) {
2231 // What to do depends on the size of the integer and the size of the pointer.
2232 // We can either truncate, zero extend, or no-op, accordingly.
2233 SDValue N = getValue(I.getOperand(0));
2234 MVT SrcVT = N.getValueType();
2235 MVT DestVT = TLI.getValueType(I.getType());
2237 if (DestVT.bitsLT(SrcVT))
2238 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2240 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2241 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2242 setValue(&I, Result);
2245 void SelectionDAGLowering::visitIntToPtr(User &I) {
2246 // What to do depends on the size of the integer and the size of the pointer.
2247 // We can either truncate, zero extend, or no-op, accordingly.
2248 SDValue N = getValue(I.getOperand(0));
2249 MVT SrcVT = N.getValueType();
2250 MVT DestVT = TLI.getValueType(I.getType());
2251 if (DestVT.bitsLT(SrcVT))
2252 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2254 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2255 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2258 void SelectionDAGLowering::visitBitCast(User &I) {
2259 SDValue N = getValue(I.getOperand(0));
2260 MVT DestVT = TLI.getValueType(I.getType());
2262 // BitCast assures us that source and destination are the same size so this
2263 // is either a BIT_CONVERT or a no-op.
2264 if (DestVT != N.getValueType())
2265 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2267 setValue(&I, N); // noop cast.
2270 void SelectionDAGLowering::visitInsertElement(User &I) {
2271 SDValue InVec = getValue(I.getOperand(0));
2272 SDValue InVal = getValue(I.getOperand(1));
2273 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2274 getValue(I.getOperand(2)));
2276 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2277 TLI.getValueType(I.getType()),
2278 InVec, InVal, InIdx));
2281 void SelectionDAGLowering::visitExtractElement(User &I) {
2282 SDValue InVec = getValue(I.getOperand(0));
2283 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2284 getValue(I.getOperand(1)));
2285 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2286 TLI.getValueType(I.getType()), InVec, InIdx));
2289 void SelectionDAGLowering::visitShuffleVector(User &I) {
2290 SDValue V1 = getValue(I.getOperand(0));
2291 SDValue V2 = getValue(I.getOperand(1));
2292 SDValue Mask = getValue(I.getOperand(2));
2294 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2295 TLI.getValueType(I.getType()),
2299 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2300 const Value *Op0 = I.getOperand(0);
2301 const Value *Op1 = I.getOperand(1);
2302 const Type *AggTy = I.getType();
2303 const Type *ValTy = Op1->getType();
2304 bool IntoUndef = isa<UndefValue>(Op0);
2305 bool FromUndef = isa<UndefValue>(Op1);
2307 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2308 I.idx_begin(), I.idx_end());
2310 SmallVector<MVT, 4> AggValueVTs;
2311 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2312 SmallVector<MVT, 4> ValValueVTs;
2313 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2315 unsigned NumAggValues = AggValueVTs.size();
2316 unsigned NumValValues = ValValueVTs.size();
2317 SmallVector<SDValue, 4> Values(NumAggValues);
2319 SDValue Agg = getValue(Op0);
2320 SDValue Val = getValue(Op1);
2322 // Copy the beginning value(s) from the original aggregate.
2323 for (; i != LinearIndex; ++i)
2324 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2325 SDValue(Agg.getNode(), Agg.getResNo() + i);
2326 // Copy values from the inserted value(s).
2327 for (; i != LinearIndex + NumValValues; ++i)
2328 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2329 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2330 // Copy remaining value(s) from the original aggregate.
2331 for (; i != NumAggValues; ++i)
2332 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2333 SDValue(Agg.getNode(), Agg.getResNo() + i);
2335 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2336 &Values[0], NumAggValues));
2339 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2340 const Value *Op0 = I.getOperand(0);
2341 const Type *AggTy = Op0->getType();
2342 const Type *ValTy = I.getType();
2343 bool OutOfUndef = isa<UndefValue>(Op0);
2345 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2346 I.idx_begin(), I.idx_end());
2348 SmallVector<MVT, 4> ValValueVTs;
2349 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2351 unsigned NumValValues = ValValueVTs.size();
2352 SmallVector<SDValue, 4> Values(NumValValues);
2354 SDValue Agg = getValue(Op0);
2355 // Copy out the selected value(s).
2356 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2357 Values[i - LinearIndex] =
2358 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2359 SDValue(Agg.getNode(), Agg.getResNo() + i);
2361 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2362 &Values[0], NumValValues));
2366 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2367 SDValue N = getValue(I.getOperand(0));
2368 const Type *Ty = I.getOperand(0)->getType();
2370 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2373 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2374 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2377 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2378 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2379 DAG.getIntPtrConstant(Offset));
2381 Ty = StTy->getElementType(Field);
2383 Ty = cast<SequentialType>(Ty)->getElementType();
2385 // If this is a constant subscript, handle it quickly.
2386 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2387 if (CI->getZExtValue() == 0) continue;
2389 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2390 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2391 DAG.getIntPtrConstant(Offs));
2395 // N = N + Idx * ElementSize;
2396 uint64_t ElementSize = TD->getABITypeSize(Ty);
2397 SDValue IdxN = getValue(Idx);
2399 // If the index is smaller or larger than intptr_t, truncate or extend
2401 if (IdxN.getValueType().bitsLT(N.getValueType()))
2402 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2403 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2404 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2406 // If this is a multiply by a power of two, turn it into a shl
2407 // immediately. This is a very common case.
2408 if (ElementSize != 1) {
2409 if (isPowerOf2_64(ElementSize)) {
2410 unsigned Amt = Log2_64(ElementSize);
2411 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2412 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2414 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2415 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2419 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2425 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2426 // If this is a fixed sized alloca in the entry block of the function,
2427 // allocate it statically on the stack.
2428 if (FuncInfo.StaticAllocaMap.count(&I))
2429 return; // getValue will auto-populate this.
2431 const Type *Ty = I.getAllocatedType();
2432 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2434 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2437 SDValue AllocSize = getValue(I.getArraySize());
2438 MVT IntPtr = TLI.getPointerTy();
2439 if (IntPtr.bitsLT(AllocSize.getValueType()))
2440 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2441 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2442 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2444 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2445 DAG.getIntPtrConstant(TySize));
2447 // Handle alignment. If the requested alignment is less than or equal to
2448 // the stack alignment, ignore it. If the size is greater than or equal to
2449 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2450 unsigned StackAlign =
2451 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2452 if (Align <= StackAlign)
2455 // Round the size of the allocation up to the stack alignment size
2456 // by add SA-1 to the size.
2457 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2458 DAG.getIntPtrConstant(StackAlign-1));
2459 // Mask out the low bits for alignment purposes.
2460 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2461 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2463 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2464 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2466 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2468 DAG.setRoot(DSA.getValue(1));
2470 // Inform the Frame Information that we have just allocated a variable-sized
2472 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2475 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2476 const Value *SV = I.getOperand(0);
2477 SDValue Ptr = getValue(SV);
2479 const Type *Ty = I.getType();
2480 bool isVolatile = I.isVolatile();
2481 unsigned Alignment = I.getAlignment();
2483 SmallVector<MVT, 4> ValueVTs;
2484 SmallVector<uint64_t, 4> Offsets;
2485 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2486 unsigned NumValues = ValueVTs.size();
2491 bool ConstantMemory = false;
2493 // Serialize volatile loads with other side effects.
2495 else if (AA->pointsToConstantMemory(SV)) {
2496 // Do not serialize (non-volatile) loads of constant memory with anything.
2497 Root = DAG.getEntryNode();
2498 ConstantMemory = true;
2500 // Do not serialize non-volatile loads against each other.
2501 Root = DAG.getRoot();
2504 SmallVector<SDValue, 4> Values(NumValues);
2505 SmallVector<SDValue, 4> Chains(NumValues);
2506 MVT PtrVT = Ptr.getValueType();
2507 for (unsigned i = 0; i != NumValues; ++i) {
2508 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2509 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2510 DAG.getConstant(Offsets[i], PtrVT)),
2512 isVolatile, Alignment);
2514 Chains[i] = L.getValue(1);
2517 if (!ConstantMemory) {
2518 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2519 &Chains[0], NumValues);
2523 PendingLoads.push_back(Chain);
2526 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2527 &Values[0], NumValues));
2531 void SelectionDAGLowering::visitStore(StoreInst &I) {
2532 Value *SrcV = I.getOperand(0);
2533 Value *PtrV = I.getOperand(1);
2535 SmallVector<MVT, 4> ValueVTs;
2536 SmallVector<uint64_t, 4> Offsets;
2537 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2538 unsigned NumValues = ValueVTs.size();
2542 // Get the lowered operands. Note that we do this after
2543 // checking if NumResults is zero, because with zero results
2544 // the operands won't have values in the map.
2545 SDValue Src = getValue(SrcV);
2546 SDValue Ptr = getValue(PtrV);
2548 SDValue Root = getRoot();
2549 SmallVector<SDValue, 4> Chains(NumValues);
2550 MVT PtrVT = Ptr.getValueType();
2551 bool isVolatile = I.isVolatile();
2552 unsigned Alignment = I.getAlignment();
2553 for (unsigned i = 0; i != NumValues; ++i)
2554 Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(), Src.getResNo() + i),
2555 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2556 DAG.getConstant(Offsets[i], PtrVT)),
2558 isVolatile, Alignment);
2560 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2563 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2565 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2566 unsigned Intrinsic) {
2567 bool HasChain = !I.doesNotAccessMemory();
2568 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2570 // Build the operand list.
2571 SmallVector<SDValue, 8> Ops;
2572 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2574 // We don't need to serialize loads against other loads.
2575 Ops.push_back(DAG.getRoot());
2577 Ops.push_back(getRoot());
2581 // Add the intrinsic ID as an integer operand.
2582 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2584 // Add all operands of the call to the operand list.
2585 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2586 SDValue Op = getValue(I.getOperand(i));
2587 assert(TLI.isTypeLegal(Op.getValueType()) &&
2588 "Intrinsic uses a non-legal type?");
2592 std::vector<MVT> VTs;
2593 if (I.getType() != Type::VoidTy) {
2594 MVT VT = TLI.getValueType(I.getType());
2595 if (VT.isVector()) {
2596 const VectorType *DestTy = cast<VectorType>(I.getType());
2597 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2599 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2600 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2603 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2607 VTs.push_back(MVT::Other);
2609 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2614 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2615 &Ops[0], Ops.size());
2616 else if (I.getType() != Type::VoidTy)
2617 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2618 &Ops[0], Ops.size());
2620 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2621 &Ops[0], Ops.size());
2624 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2626 PendingLoads.push_back(Chain);
2630 if (I.getType() != Type::VoidTy) {
2631 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2632 MVT VT = TLI.getValueType(PTy);
2633 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2635 setValue(&I, Result);
2639 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2640 static GlobalVariable *ExtractTypeInfo(Value *V) {
2641 V = V->stripPointerCasts();
2642 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2643 assert ((GV || isa<ConstantPointerNull>(V)) &&
2644 "TypeInfo must be a global variable or NULL");
2650 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2651 /// call, and add them to the specified machine basic block.
2652 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2653 MachineBasicBlock *MBB) {
2654 // Inform the MachineModuleInfo of the personality for this landing pad.
2655 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2656 assert(CE->getOpcode() == Instruction::BitCast &&
2657 isa<Function>(CE->getOperand(0)) &&
2658 "Personality should be a function");
2659 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2661 // Gather all the type infos for this landing pad and pass them along to
2662 // MachineModuleInfo.
2663 std::vector<GlobalVariable *> TyInfo;
2664 unsigned N = I.getNumOperands();
2666 for (unsigned i = N - 1; i > 2; --i) {
2667 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2668 unsigned FilterLength = CI->getZExtValue();
2669 unsigned FirstCatch = i + FilterLength + !FilterLength;
2670 assert (FirstCatch <= N && "Invalid filter length");
2672 if (FirstCatch < N) {
2673 TyInfo.reserve(N - FirstCatch);
2674 for (unsigned j = FirstCatch; j < N; ++j)
2675 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2676 MMI->addCatchTypeInfo(MBB, TyInfo);
2680 if (!FilterLength) {
2682 MMI->addCleanup(MBB);
2685 TyInfo.reserve(FilterLength - 1);
2686 for (unsigned j = i + 1; j < FirstCatch; ++j)
2687 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2688 MMI->addFilterTypeInfo(MBB, TyInfo);
2697 TyInfo.reserve(N - 3);
2698 for (unsigned j = 3; j < N; ++j)
2699 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2700 MMI->addCatchTypeInfo(MBB, TyInfo);
2706 /// GetSignificand - Get the significand and build it into a floating-point
2707 /// number with exponent of 1:
2709 /// Op = (Op & 0x007fffff) | 0x3f800000;
2711 /// where Op is the hexidecimal representation of floating point value.
2713 GetSignificand(SelectionDAG &DAG, SDValue Op) {
2714 SDValue t1 = DAG.getNode(ISD::AND, MVT::i32, Op,
2715 DAG.getConstant(0x007fffff, MVT::i32));
2716 SDValue t2 = DAG.getNode(ISD::OR, MVT::i32, t1,
2717 DAG.getConstant(0x3f800000, MVT::i32));
2718 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t2);
2721 /// GetExponent - Get the exponent:
2723 /// (float)((Op1 >> 23) - 127);
2725 /// where Op is the hexidecimal representation of floating point value.
2727 GetExponent(SelectionDAG &DAG, SDValue Op) {
2728 SDValue t1 = DAG.getNode(ISD::SRL, MVT::i32, Op,
2729 DAG.getConstant(23, MVT::i32));
2730 SDValue t2 = DAG.getNode(ISD::SUB, MVT::i32, t1,
2731 DAG.getConstant(127, MVT::i32));
2732 return DAG.getNode(ISD::UINT_TO_FP, MVT::f32, t2);
2735 /// getF32Constant - Get 32-bit floating point constant.
2737 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2738 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2741 /// Inlined utility function to implement binary input atomic intrinsics for
2742 /// visitIntrinsicCall: I is a call instruction
2743 /// Op is the associated NodeType for I
2745 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2746 SDValue Root = getRoot();
2747 SDValue L = DAG.getAtomic(Op, Root,
2748 getValue(I.getOperand(1)),
2749 getValue(I.getOperand(2)),
2752 DAG.setRoot(L.getValue(1));
2756 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2757 /// limited-precision mode.
2759 SelectionDAGLowering::visitExp(CallInst &I) {
2762 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2763 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2764 SDValue Op = getValue(I.getOperand(1));
2766 // Put the exponent in the right bit position for later addition to the
2769 // #define LOG2OFe 1.4426950f
2770 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2771 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
2772 getF32Constant(DAG, 0x3fb8aa3b));
2773 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
2775 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2776 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
2777 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
2779 // IntegerPartOfX <<= 23;
2780 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
2781 DAG.getConstant(23, MVT::i32));
2783 if (LimitFloatPrecision <= 6) {
2784 // For floating-point precision of 6:
2786 // TwoToFractionalPartOfX =
2788 // (0.735607626f + 0.252464424f * x) * x;
2790 // error 0.0144103317, which is 6 bits
2791 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2792 getF32Constant(DAG, 0x3e814304));
2793 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2794 getF32Constant(DAG, 0x3f3c50c8));
2795 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2796 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2797 getF32Constant(DAG, 0x3f7f5e7e));
2798 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
2800 // Add the exponent into the result in integer domain.
2801 SDValue t6 = DAG.getNode(ISD::ADD, MVT::i32,
2802 TwoToFracPartOfX, IntegerPartOfX);
2804 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t6);
2805 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2806 // For floating-point precision of 12:
2808 // TwoToFractionalPartOfX =
2811 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2813 // 0.000107046256 error, which is 13 to 14 bits
2814 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2815 getF32Constant(DAG, 0x3da235e3));
2816 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2817 getF32Constant(DAG, 0x3e65b8f3));
2818 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2819 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2820 getF32Constant(DAG, 0x3f324b07));
2821 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2822 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
2823 getF32Constant(DAG, 0x3f7ff8fd));
2824 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
2826 // Add the exponent into the result in integer domain.
2827 SDValue t8 = DAG.getNode(ISD::ADD, MVT::i32,
2828 TwoToFracPartOfX, IntegerPartOfX);
2830 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t8);
2831 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2832 // For floating-point precision of 18:
2834 // TwoToFractionalPartOfX =
2838 // (0.554906021e-1f +
2839 // (0.961591928e-2f +
2840 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
2842 // error 2.47208000*10^(-7), which is better than 18 bits
2843 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2844 getF32Constant(DAG, 0x3924b03e));
2845 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2846 getF32Constant(DAG, 0x3ab24b87));
2847 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2848 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2849 getF32Constant(DAG, 0x3c1d8c17));
2850 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2851 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
2852 getF32Constant(DAG, 0x3d634a1d));
2853 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
2854 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
2855 getF32Constant(DAG, 0x3e75fe14));
2856 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
2857 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
2858 getF32Constant(DAG, 0x3f317234));
2859 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
2860 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
2861 getF32Constant(DAG, 0x3f800000));
2862 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
2864 // Add the exponent into the result in integer domain.
2865 SDValue t14 = DAG.getNode(ISD::ADD, MVT::i32,
2866 TwoToFracPartOfX, IntegerPartOfX);
2868 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t14);
2871 // No special expansion.
2872 result = DAG.getNode(ISD::FEXP,
2873 getValue(I.getOperand(1)).getValueType(),
2874 getValue(I.getOperand(1)));
2877 setValue(&I, result);
2880 /// visitLog - Lower a log intrinsic. Handles the special sequences for
2881 /// limited-precision mode.
2883 SelectionDAGLowering::visitLog(CallInst &I) {
2886 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2887 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2888 SDValue Op = getValue(I.getOperand(1));
2889 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
2891 // Scale the exponent by log(2) [0.69314718f].
2892 SDValue Exp = GetExponent(DAG, Op1);
2893 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
2894 getF32Constant(DAG, 0x3f317218));
2896 // Get the significand and build it into a floating-point number with
2898 SDValue X = GetSignificand(DAG, Op1);
2900 if (LimitFloatPrecision <= 6) {
2901 // For floating-point precision of 6:
2905 // (1.4034025f - 0.23903021f * x) * x;
2907 // error 0.0034276066, which is better than 8 bits
2908 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2909 getF32Constant(DAG, 0xbe74c456));
2910 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2911 getF32Constant(DAG, 0x3fb3a2b1));
2912 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2913 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2914 getF32Constant(DAG, 0x3f949a29));
2916 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2917 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2918 // For floating-point precision of 12:
2924 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
2926 // error 0.000061011436, which is 14 bits
2927 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2928 getF32Constant(DAG, 0xbd67b6d6));
2929 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2930 getF32Constant(DAG, 0x3ee4f4b8));
2931 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2932 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2933 getF32Constant(DAG, 0x3fbc278b));
2934 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2935 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2936 getF32Constant(DAG, 0x40348e95));
2937 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2938 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
2939 getF32Constant(DAG, 0x3fdef31a));
2941 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2942 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2943 // For floating-point precision of 18:
2951 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
2953 // error 0.0000023660568, which is better than 18 bits
2954 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2955 getF32Constant(DAG, 0xbc91e5ac));
2956 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2957 getF32Constant(DAG, 0x3e4350aa));
2958 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2959 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2960 getF32Constant(DAG, 0x3f60d3e3));
2961 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2962 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2963 getF32Constant(DAG, 0x4011cdf0));
2964 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2965 SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
2966 getF32Constant(DAG, 0x406cfd1c));
2967 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
2968 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
2969 getF32Constant(DAG, 0x408797cb));
2970 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
2971 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
2972 getF32Constant(DAG, 0x4006dcab));
2974 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2977 // No special expansion.
2978 result = DAG.getNode(ISD::FLOG,
2979 getValue(I.getOperand(1)).getValueType(),
2980 getValue(I.getOperand(1)));
2983 setValue(&I, result);
2986 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
2987 /// limited-precision mode.
2989 SelectionDAGLowering::visitLog2(CallInst &I) {
2992 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2993 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2994 SDValue Op = getValue(I.getOperand(1));
2995 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
2997 // Get the exponent.
2998 SDValue LogOfExponent = GetExponent(DAG, Op1);
3000 // Get the significand and build it into a floating-point number with
3002 SDValue X = GetSignificand(DAG, Op1);
3004 // Different possible minimax approximations of significand in
3005 // floating-point for various degrees of accuracy over [1,2].
3006 if (LimitFloatPrecision <= 6) {
3007 // For floating-point precision of 6:
3009 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3011 // error 0.0049451742, which is more than 7 bits
3012 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3013 getF32Constant(DAG, 0xbeb08fe0));
3014 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3015 getF32Constant(DAG, 0x40019463));
3016 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3017 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3018 getF32Constant(DAG, 0x3fd6633d));
3020 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3021 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3022 // For floating-point precision of 12:
3028 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3030 // error 0.0000876136000, which is better than 13 bits
3031 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3032 getF32Constant(DAG, 0xbda7262e));
3033 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3034 getF32Constant(DAG, 0x3f25280b));
3035 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3036 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3037 getF32Constant(DAG, 0x4007b923));
3038 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3039 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3040 getF32Constant(DAG, 0x40823e2f));
3041 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3042 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3043 getF32Constant(DAG, 0x4020d29c));
3045 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3046 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3047 // For floating-point precision of 18:
3056 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3058 // error 0.0000018516, which is better than 18 bits
3059 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3060 getF32Constant(DAG, 0xbcd2769e));
3061 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3062 getF32Constant(DAG, 0x3e8ce0b9));
3063 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3064 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3065 getF32Constant(DAG, 0x3fa22ae7));
3066 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3067 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3068 getF32Constant(DAG, 0x40525723));
3069 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3070 SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3071 getF32Constant(DAG, 0x40aaf200));
3072 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3073 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3074 getF32Constant(DAG, 0x40c39dad));
3075 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3076 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
3077 getF32Constant(DAG, 0x4042902c));
3079 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3082 // No special expansion.
3083 result = DAG.getNode(ISD::FLOG2,
3084 getValue(I.getOperand(1)).getValueType(),
3085 getValue(I.getOperand(1)));
3088 setValue(&I, result);
3091 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3092 /// limited-precision mode.
3094 SelectionDAGLowering::visitLog10(CallInst &I) {
3097 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3098 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3099 SDValue Op = getValue(I.getOperand(1));
3100 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
3102 // Scale the exponent by log10(2) [0.30102999f].
3103 SDValue Exp = GetExponent(DAG, Op1);
3104 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
3105 getF32Constant(DAG, 0x3e9a209a));
3107 // Get the significand and build it into a floating-point number with
3109 SDValue X = GetSignificand(DAG, Op1);
3111 if (LimitFloatPrecision <= 6) {
3112 // For floating-point precision of 6:
3114 // Log10ofMantissa =
3116 // (0.60948995f - 0.10380950f * x) * x;
3118 // error 0.0014886165, which is 6 bits
3119 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3120 getF32Constant(DAG, 0xbdd49a13));
3121 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3122 getF32Constant(DAG, 0x3f1c0789));
3123 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3124 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3125 getF32Constant(DAG, 0x3f011300));
3127 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3128 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3129 // For floating-point precision of 12:
3131 // Log10ofMantissa =
3134 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3136 // error 0.00019228036, which is better than 12 bits
3137 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3138 getF32Constant(DAG, 0x3d431f31));
3139 SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
3140 getF32Constant(DAG, 0x3ea21fb2));
3141 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3142 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3143 getF32Constant(DAG, 0x3f6ae232));
3144 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3145 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t4,
3146 getF32Constant(DAG, 0x3f25f7c3));
3148 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3149 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3150 // For floating-point precision of 18:
3152 // Log10ofMantissa =
3157 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3159 // error 0.0000037995730, which is better than 18 bits
3160 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3161 getF32Constant(DAG, 0x3c5d51ce));
3162 SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
3163 getF32Constant(DAG, 0x3e00685a));
3164 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3165 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3166 getF32Constant(DAG, 0x3efb6798));
3167 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3168 SDValue t5 = DAG.getNode(ISD::FSUB, MVT::f32, t4,
3169 getF32Constant(DAG, 0x3f88d192));
3170 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3171 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3172 getF32Constant(DAG, 0x3fc4316c));
3173 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3174 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t8,
3175 getF32Constant(DAG, 0x3f57ce70));
3177 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3180 // No special expansion.
3181 result = DAG.getNode(ISD::FLOG10,
3182 getValue(I.getOperand(1)).getValueType(),
3183 getValue(I.getOperand(1)));
3186 setValue(&I, result);
3189 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3190 /// limited-precision mode.
3192 SelectionDAGLowering::visitExp2(CallInst &I) {
3195 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3196 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3197 SDValue Op = getValue(I.getOperand(1));
3199 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Op);
3201 // FractionalPartOfX = x - (float)IntegerPartOfX;
3202 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
3203 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, Op, t1);
3205 // IntegerPartOfX <<= 23;
3206 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
3207 DAG.getConstant(23, MVT::i32));
3209 if (LimitFloatPrecision <= 6) {
3210 // For floating-point precision of 6:
3212 // TwoToFractionalPartOfX =
3214 // (0.735607626f + 0.252464424f * x) * x;
3216 // error 0.0144103317, which is 6 bits
3217 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3218 getF32Constant(DAG, 0x3e814304));
3219 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3220 getF32Constant(DAG, 0x3f3c50c8));
3221 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3222 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3223 getF32Constant(DAG, 0x3f7f5e7e));
3224 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
3225 SDValue TwoToFractionalPartOfX =
3226 DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
3228 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3229 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3230 // For floating-point precision of 12:
3232 // TwoToFractionalPartOfX =
3235 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3237 // error 0.000107046256, which is 13 to 14 bits
3238 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3239 getF32Constant(DAG, 0x3da235e3));
3240 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3241 getF32Constant(DAG, 0x3e65b8f3));
3242 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3243 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3244 getF32Constant(DAG, 0x3f324b07));
3245 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3246 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3247 getF32Constant(DAG, 0x3f7ff8fd));
3248 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
3249 SDValue TwoToFractionalPartOfX =
3250 DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
3252 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3253 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3254 // For floating-point precision of 18:
3256 // TwoToFractionalPartOfX =
3260 // (0.554906021e-1f +
3261 // (0.961591928e-2f +
3262 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3263 // error 2.47208000*10^(-7), which is better than 18 bits
3264 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3265 getF32Constant(DAG, 0x3924b03e));
3266 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3267 getF32Constant(DAG, 0x3ab24b87));
3268 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3269 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3270 getF32Constant(DAG, 0x3c1d8c17));
3271 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3272 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3273 getF32Constant(DAG, 0x3d634a1d));
3274 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3275 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3276 getF32Constant(DAG, 0x3e75fe14));
3277 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3278 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
3279 getF32Constant(DAG, 0x3f317234));
3280 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
3281 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
3282 getF32Constant(DAG, 0x3f800000));
3283 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
3284 SDValue TwoToFractionalPartOfX =
3285 DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
3287 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3290 // No special expansion.
3291 result = DAG.getNode(ISD::FEXP2,
3292 getValue(I.getOperand(1)).getValueType(),
3293 getValue(I.getOperand(1)));
3296 setValue(&I, result);
3299 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3300 /// limited-precision mode with x == 10.0f.
3302 SelectionDAGLowering::visitPow(CallInst &I) {
3304 Value *Val = I.getOperand(1);
3305 bool IsExp10 = false;
3307 if (getValue(Val).getValueType() == MVT::f32 &&
3308 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3309 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3310 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3311 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3313 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3318 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3319 SDValue Op = getValue(I.getOperand(2));
3321 // Put the exponent in the right bit position for later addition to the
3324 // #define LOG2OF10 3.3219281f
3325 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3326 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
3327 getF32Constant(DAG, 0x40549a78));
3328 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
3330 // FractionalPartOfX = x - (float)IntegerPartOfX;
3331 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
3332 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
3334 // IntegerPartOfX <<= 23;
3335 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
3336 DAG.getConstant(23, MVT::i32));
3338 if (LimitFloatPrecision <= 6) {
3339 // For floating-point precision of 6:
3341 // twoToFractionalPartOfX =
3343 // (0.735607626f + 0.252464424f * x) * x;
3345 // error 0.0144103317, which is 6 bits
3346 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3347 getF32Constant(DAG, 0x3e814304));
3348 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3349 getF32Constant(DAG, 0x3f3c50c8));
3350 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3351 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3352 getF32Constant(DAG, 0x3f7f5e7e));
3353 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
3354 SDValue TwoToFractionalPartOfX =
3355 DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
3357 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3358 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3359 // For floating-point precision of 12:
3361 // TwoToFractionalPartOfX =
3364 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3366 // error 0.000107046256, which is 13 to 14 bits
3367 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3368 getF32Constant(DAG, 0x3da235e3));
3369 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3370 getF32Constant(DAG, 0x3e65b8f3));
3371 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3372 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3373 getF32Constant(DAG, 0x3f324b07));
3374 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3375 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3376 getF32Constant(DAG, 0x3f7ff8fd));
3377 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
3378 SDValue TwoToFractionalPartOfX =
3379 DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
3381 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3382 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3383 // For floating-point precision of 18:
3385 // TwoToFractionalPartOfX =
3389 // (0.554906021e-1f +
3390 // (0.961591928e-2f +
3391 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3392 // error 2.47208000*10^(-7), which is better than 18 bits
3393 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3394 getF32Constant(DAG, 0x3924b03e));
3395 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3396 getF32Constant(DAG, 0x3ab24b87));
3397 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3398 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3399 getF32Constant(DAG, 0x3c1d8c17));
3400 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3401 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3402 getF32Constant(DAG, 0x3d634a1d));
3403 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3404 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3405 getF32Constant(DAG, 0x3e75fe14));
3406 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3407 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
3408 getF32Constant(DAG, 0x3f317234));
3409 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
3410 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
3411 getF32Constant(DAG, 0x3f800000));
3412 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
3413 SDValue TwoToFractionalPartOfX =
3414 DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
3416 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3419 // No special expansion.
3420 result = DAG.getNode(ISD::FPOW,
3421 getValue(I.getOperand(1)).getValueType(),
3422 getValue(I.getOperand(1)),
3423 getValue(I.getOperand(2)));
3426 setValue(&I, result);
3429 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3430 /// we want to emit this as a call to a named external function, return the name
3431 /// otherwise lower it and return null.
3433 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3434 switch (Intrinsic) {
3436 // By default, turn this into a target intrinsic node.
3437 visitTargetIntrinsic(I, Intrinsic);
3439 case Intrinsic::vastart: visitVAStart(I); return 0;
3440 case Intrinsic::vaend: visitVAEnd(I); return 0;
3441 case Intrinsic::vacopy: visitVACopy(I); return 0;
3442 case Intrinsic::returnaddress:
3443 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3444 getValue(I.getOperand(1))));
3446 case Intrinsic::frameaddress:
3447 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3448 getValue(I.getOperand(1))));
3450 case Intrinsic::setjmp:
3451 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3453 case Intrinsic::longjmp:
3454 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3456 case Intrinsic::memcpy_i32:
3457 case Intrinsic::memcpy_i64: {
3458 SDValue Op1 = getValue(I.getOperand(1));
3459 SDValue Op2 = getValue(I.getOperand(2));
3460 SDValue Op3 = getValue(I.getOperand(3));
3461 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3462 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3463 I.getOperand(1), 0, I.getOperand(2), 0));
3466 case Intrinsic::memset_i32:
3467 case Intrinsic::memset_i64: {
3468 SDValue Op1 = getValue(I.getOperand(1));
3469 SDValue Op2 = getValue(I.getOperand(2));
3470 SDValue Op3 = getValue(I.getOperand(3));
3471 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3472 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3473 I.getOperand(1), 0));
3476 case Intrinsic::memmove_i32:
3477 case Intrinsic::memmove_i64: {
3478 SDValue Op1 = getValue(I.getOperand(1));
3479 SDValue Op2 = getValue(I.getOperand(2));
3480 SDValue Op3 = getValue(I.getOperand(3));
3481 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3483 // If the source and destination are known to not be aliases, we can
3484 // lower memmove as memcpy.
3485 uint64_t Size = -1ULL;
3486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3487 Size = C->getZExtValue();
3488 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3489 AliasAnalysis::NoAlias) {
3490 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3491 I.getOperand(1), 0, I.getOperand(2), 0));
3495 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3496 I.getOperand(1), 0, I.getOperand(2), 0));
3499 case Intrinsic::dbg_stoppoint: {
3500 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3501 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3502 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3503 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3504 assert(DD && "Not a debug information descriptor");
3505 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3508 cast<CompileUnitDesc>(DD)));
3513 case Intrinsic::dbg_region_start: {
3514 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3515 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3516 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3517 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3518 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3523 case Intrinsic::dbg_region_end: {
3524 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3525 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3526 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3527 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3528 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3533 case Intrinsic::dbg_func_start: {
3534 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3536 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3537 Value *SP = FSI.getSubprogram();
3538 if (SP && MMI->Verify(SP)) {
3539 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3540 // what (most?) gdb expects.
3541 DebugInfoDesc *DD = MMI->getDescFor(SP);
3542 assert(DD && "Not a debug information descriptor");
3543 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3544 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3545 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3546 // Record the source line but does create a label. It will be emitted
3547 // at asm emission time.
3548 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3553 case Intrinsic::dbg_declare: {
3554 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3555 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3556 Value *Variable = DI.getVariable();
3557 if (MMI && Variable && MMI->Verify(Variable))
3558 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3559 getValue(DI.getAddress()), getValue(Variable)));
3563 case Intrinsic::eh_exception: {
3564 if (!CurMBB->isLandingPad()) {
3565 // FIXME: Mark exception register as live in. Hack for PR1508.
3566 unsigned Reg = TLI.getExceptionAddressRegister();
3567 if (Reg) CurMBB->addLiveIn(Reg);
3569 // Insert the EXCEPTIONADDR instruction.
3570 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3572 Ops[0] = DAG.getRoot();
3573 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3575 DAG.setRoot(Op.getValue(1));
3579 case Intrinsic::eh_selector_i32:
3580 case Intrinsic::eh_selector_i64: {
3581 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3582 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3583 MVT::i32 : MVT::i64);
3586 if (CurMBB->isLandingPad())
3587 AddCatchInfo(I, MMI, CurMBB);
3590 FuncInfo.CatchInfoLost.insert(&I);
3592 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3593 unsigned Reg = TLI.getExceptionSelectorRegister();
3594 if (Reg) CurMBB->addLiveIn(Reg);
3597 // Insert the EHSELECTION instruction.
3598 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3600 Ops[0] = getValue(I.getOperand(1));
3602 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3604 DAG.setRoot(Op.getValue(1));
3606 setValue(&I, DAG.getConstant(0, VT));
3612 case Intrinsic::eh_typeid_for_i32:
3613 case Intrinsic::eh_typeid_for_i64: {
3614 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3615 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3616 MVT::i32 : MVT::i64);
3619 // Find the type id for the given typeinfo.
3620 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3622 unsigned TypeID = MMI->getTypeIDFor(GV);
3623 setValue(&I, DAG.getConstant(TypeID, VT));
3625 // Return something different to eh_selector.
3626 setValue(&I, DAG.getConstant(1, VT));
3632 case Intrinsic::eh_return_i32:
3633 case Intrinsic::eh_return_i64:
3634 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3635 MMI->setCallsEHReturn(true);
3636 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3639 getValue(I.getOperand(1)),
3640 getValue(I.getOperand(2))));
3642 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3646 case Intrinsic::eh_unwind_init:
3647 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3648 MMI->setCallsUnwindInit(true);
3653 case Intrinsic::eh_dwarf_cfa: {
3654 MVT VT = getValue(I.getOperand(1)).getValueType();
3656 if (VT.bitsGT(TLI.getPointerTy()))
3657 CfaArg = DAG.getNode(ISD::TRUNCATE,
3658 TLI.getPointerTy(), getValue(I.getOperand(1)));
3660 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3661 TLI.getPointerTy(), getValue(I.getOperand(1)));
3663 SDValue Offset = DAG.getNode(ISD::ADD,
3665 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3666 TLI.getPointerTy()),
3668 setValue(&I, DAG.getNode(ISD::ADD,
3670 DAG.getNode(ISD::FRAMEADDR,
3673 TLI.getPointerTy())),
3678 case Intrinsic::sqrt:
3679 setValue(&I, DAG.getNode(ISD::FSQRT,
3680 getValue(I.getOperand(1)).getValueType(),
3681 getValue(I.getOperand(1))));
3683 case Intrinsic::powi:
3684 setValue(&I, DAG.getNode(ISD::FPOWI,
3685 getValue(I.getOperand(1)).getValueType(),
3686 getValue(I.getOperand(1)),
3687 getValue(I.getOperand(2))));
3689 case Intrinsic::sin:
3690 setValue(&I, DAG.getNode(ISD::FSIN,
3691 getValue(I.getOperand(1)).getValueType(),
3692 getValue(I.getOperand(1))));
3694 case Intrinsic::cos:
3695 setValue(&I, DAG.getNode(ISD::FCOS,
3696 getValue(I.getOperand(1)).getValueType(),
3697 getValue(I.getOperand(1))));
3699 case Intrinsic::log:
3702 case Intrinsic::log2:
3705 case Intrinsic::log10:
3708 case Intrinsic::exp:
3711 case Intrinsic::exp2:
3714 case Intrinsic::pow:
3717 case Intrinsic::pcmarker: {
3718 SDValue Tmp = getValue(I.getOperand(1));
3719 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3722 case Intrinsic::readcyclecounter: {
3723 SDValue Op = getRoot();
3724 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3725 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3728 DAG.setRoot(Tmp.getValue(1));
3731 case Intrinsic::part_select: {
3732 // Currently not implemented: just abort
3733 assert(0 && "part_select intrinsic not implemented");
3736 case Intrinsic::part_set: {
3737 // Currently not implemented: just abort
3738 assert(0 && "part_set intrinsic not implemented");
3741 case Intrinsic::bswap:
3742 setValue(&I, DAG.getNode(ISD::BSWAP,
3743 getValue(I.getOperand(1)).getValueType(),
3744 getValue(I.getOperand(1))));
3746 case Intrinsic::cttz: {
3747 SDValue Arg = getValue(I.getOperand(1));
3748 MVT Ty = Arg.getValueType();
3749 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3750 setValue(&I, result);
3753 case Intrinsic::ctlz: {
3754 SDValue Arg = getValue(I.getOperand(1));
3755 MVT Ty = Arg.getValueType();
3756 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3757 setValue(&I, result);
3760 case Intrinsic::ctpop: {
3761 SDValue Arg = getValue(I.getOperand(1));
3762 MVT Ty = Arg.getValueType();
3763 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3764 setValue(&I, result);
3767 case Intrinsic::stacksave: {
3768 SDValue Op = getRoot();
3769 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3770 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3772 DAG.setRoot(Tmp.getValue(1));
3775 case Intrinsic::stackrestore: {
3776 SDValue Tmp = getValue(I.getOperand(1));
3777 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3780 case Intrinsic::var_annotation:
3781 // Discard annotate attributes
3784 case Intrinsic::init_trampoline: {
3785 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3789 Ops[1] = getValue(I.getOperand(1));
3790 Ops[2] = getValue(I.getOperand(2));
3791 Ops[3] = getValue(I.getOperand(3));
3792 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3793 Ops[5] = DAG.getSrcValue(F);
3795 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3796 DAG.getNodeValueTypes(TLI.getPointerTy(),
3801 DAG.setRoot(Tmp.getValue(1));
3805 case Intrinsic::gcroot:
3807 Value *Alloca = I.getOperand(1);
3808 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3810 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
3811 GFI->addStackRoot(FI->getIndex(), TypeMap);
3815 case Intrinsic::gcread:
3816 case Intrinsic::gcwrite:
3817 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
3820 case Intrinsic::flt_rounds: {
3821 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3825 case Intrinsic::trap: {
3826 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3829 case Intrinsic::prefetch: {
3832 Ops[1] = getValue(I.getOperand(1));
3833 Ops[2] = getValue(I.getOperand(2));
3834 Ops[3] = getValue(I.getOperand(3));
3835 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3839 case Intrinsic::memory_barrier: {
3842 for (int x = 1; x < 6; ++x)
3843 Ops[x] = getValue(I.getOperand(x));
3845 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3848 case Intrinsic::atomic_cmp_swap: {
3849 SDValue Root = getRoot();
3851 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3853 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_8, Root,
3854 getValue(I.getOperand(1)),
3855 getValue(I.getOperand(2)),
3856 getValue(I.getOperand(3)),
3860 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_16, Root,
3861 getValue(I.getOperand(1)),
3862 getValue(I.getOperand(2)),
3863 getValue(I.getOperand(3)),
3867 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_32, Root,
3868 getValue(I.getOperand(1)),
3869 getValue(I.getOperand(2)),
3870 getValue(I.getOperand(3)),
3874 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_64, Root,
3875 getValue(I.getOperand(1)),
3876 getValue(I.getOperand(2)),
3877 getValue(I.getOperand(3)),
3881 assert(0 && "Invalid atomic type");
3885 DAG.setRoot(L.getValue(1));
3888 case Intrinsic::atomic_load_add:
3889 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3891 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_8);
3893 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_16);
3895 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_32);
3897 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_64);
3899 assert(0 && "Invalid atomic type");
3902 case Intrinsic::atomic_load_sub:
3903 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3905 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_8);
3907 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_16);
3909 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_32);
3911 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_64);
3913 assert(0 && "Invalid atomic type");
3916 case Intrinsic::atomic_load_or:
3917 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3919 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_8);
3921 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_16);
3923 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_32);
3925 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_64);
3927 assert(0 && "Invalid atomic type");
3930 case Intrinsic::atomic_load_xor:
3931 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3933 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_8);
3935 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_16);
3937 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_32);
3939 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_64);
3941 assert(0 && "Invalid atomic type");
3944 case Intrinsic::atomic_load_and:
3945 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3947 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_8);
3949 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_16);
3951 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_32);
3953 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_64);
3955 assert(0 && "Invalid atomic type");
3958 case Intrinsic::atomic_load_nand:
3959 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3961 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_8);
3963 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_16);
3965 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_32);
3967 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_64);
3969 assert(0 && "Invalid atomic type");
3972 case Intrinsic::atomic_load_max:
3973 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3975 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_8);
3977 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_16);
3979 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_32);
3981 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_64);
3983 assert(0 && "Invalid atomic type");
3986 case Intrinsic::atomic_load_min:
3987 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3989 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_8);
3991 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_16);
3993 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_32);
3995 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_64);
3997 assert(0 && "Invalid atomic type");
4000 case Intrinsic::atomic_load_umin:
4001 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4003 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_8);
4005 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_16);
4007 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_32);
4009 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_64);
4011 assert(0 && "Invalid atomic type");
4014 case Intrinsic::atomic_load_umax:
4015 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4017 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_8);
4019 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_16);
4021 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_32);
4023 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_64);
4025 assert(0 && "Invalid atomic type");
4028 case Intrinsic::atomic_swap:
4029 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4031 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_8);
4033 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_16);
4035 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_32);
4037 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_64);
4039 assert(0 && "Invalid atomic type");
4046 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4048 MachineBasicBlock *LandingPad) {
4049 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4050 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4051 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4052 unsigned BeginLabel = 0, EndLabel = 0;
4054 TargetLowering::ArgListTy Args;
4055 TargetLowering::ArgListEntry Entry;
4056 Args.reserve(CS.arg_size());
4057 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4059 SDValue ArgNode = getValue(*i);
4060 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4062 unsigned attrInd = i - CS.arg_begin() + 1;
4063 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4064 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4065 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4066 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4067 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4068 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4069 Entry.Alignment = CS.getParamAlignment(attrInd);
4070 Args.push_back(Entry);
4073 if (LandingPad && MMI) {
4074 // Insert a label before the invoke call to mark the try range. This can be
4075 // used to detect deletion of the invoke via the MachineModuleInfo.
4076 BeginLabel = MMI->NextLabelID();
4077 // Both PendingLoads and PendingExports must be flushed here;
4078 // this call might not return.
4080 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
4083 std::pair<SDValue,SDValue> Result =
4084 TLI.LowerCallTo(getRoot(), CS.getType(),
4085 CS.paramHasAttr(0, Attribute::SExt),
4086 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4087 CS.paramHasAttr(0, Attribute::InReg),
4088 CS.getCallingConv(),
4089 IsTailCall && PerformTailCallOpt,
4091 if (CS.getType() != Type::VoidTy)
4092 setValue(CS.getInstruction(), Result.first);
4093 DAG.setRoot(Result.second);
4095 if (LandingPad && MMI) {
4096 // Insert a label at the end of the invoke call to mark the try range. This
4097 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4098 EndLabel = MMI->NextLabelID();
4099 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
4101 // Inform MachineModuleInfo of range.
4102 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4107 void SelectionDAGLowering::visitCall(CallInst &I) {
4108 const char *RenameFn = 0;
4109 if (Function *F = I.getCalledFunction()) {
4110 if (F->isDeclaration()) {
4111 if (unsigned IID = F->getIntrinsicID()) {
4112 RenameFn = visitIntrinsicCall(I, IID);
4118 // Check for well-known libc/libm calls. If the function is internal, it
4119 // can't be a library call.
4120 unsigned NameLen = F->getNameLen();
4121 if (!F->hasInternalLinkage() && NameLen) {
4122 const char *NameStr = F->getNameStart();
4123 if (NameStr[0] == 'c' &&
4124 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4125 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4126 if (I.getNumOperands() == 3 && // Basic sanity checks.
4127 I.getOperand(1)->getType()->isFloatingPoint() &&
4128 I.getType() == I.getOperand(1)->getType() &&
4129 I.getType() == I.getOperand(2)->getType()) {
4130 SDValue LHS = getValue(I.getOperand(1));
4131 SDValue RHS = getValue(I.getOperand(2));
4132 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
4136 } else if (NameStr[0] == 'f' &&
4137 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4138 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4139 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4140 if (I.getNumOperands() == 2 && // Basic sanity checks.
4141 I.getOperand(1)->getType()->isFloatingPoint() &&
4142 I.getType() == I.getOperand(1)->getType()) {
4143 SDValue Tmp = getValue(I.getOperand(1));
4144 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
4147 } else if (NameStr[0] == 's' &&
4148 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4149 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4150 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4151 if (I.getNumOperands() == 2 && // Basic sanity checks.
4152 I.getOperand(1)->getType()->isFloatingPoint() &&
4153 I.getType() == I.getOperand(1)->getType()) {
4154 SDValue Tmp = getValue(I.getOperand(1));
4155 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
4158 } else if (NameStr[0] == 'c' &&
4159 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4160 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4161 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4162 if (I.getNumOperands() == 2 && // Basic sanity checks.
4163 I.getOperand(1)->getType()->isFloatingPoint() &&
4164 I.getType() == I.getOperand(1)->getType()) {
4165 SDValue Tmp = getValue(I.getOperand(1));
4166 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
4171 } else if (isa<InlineAsm>(I.getOperand(0))) {
4178 Callee = getValue(I.getOperand(0));
4180 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4182 LowerCallTo(&I, Callee, I.isTailCall());
4186 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4187 /// this value and returns the result as a ValueVT value. This uses
4188 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4189 /// If the Flag pointer is NULL, no flag is used.
4190 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
4192 SDValue *Flag) const {
4193 // Assemble the legal parts into the final values.
4194 SmallVector<SDValue, 4> Values(ValueVTs.size());
4195 SmallVector<SDValue, 8> Parts;
4196 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4197 // Copy the legal parts from the registers.
4198 MVT ValueVT = ValueVTs[Value];
4199 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4200 MVT RegisterVT = RegVTs[Value];
4202 Parts.resize(NumRegs);
4203 for (unsigned i = 0; i != NumRegs; ++i) {
4206 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4208 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4209 *Flag = P.getValue(2);
4211 Chain = P.getValue(1);
4213 // If the source register was virtual and if we know something about it,
4214 // add an assert node.
4215 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4216 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4217 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4218 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4219 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4220 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4222 unsigned RegSize = RegisterVT.getSizeInBits();
4223 unsigned NumSignBits = LOI.NumSignBits;
4224 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4226 // FIXME: We capture more information than the dag can represent. For
4227 // now, just use the tightest assertzext/assertsext possible.
4229 MVT FromVT(MVT::Other);
4230 if (NumSignBits == RegSize)
4231 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4232 else if (NumZeroBits >= RegSize-1)
4233 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4234 else if (NumSignBits > RegSize-8)
4235 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4236 else if (NumZeroBits >= RegSize-9)
4237 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4238 else if (NumSignBits > RegSize-16)
4239 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4240 else if (NumZeroBits >= RegSize-17)
4241 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4242 else if (NumSignBits > RegSize-32)
4243 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4244 else if (NumZeroBits >= RegSize-33)
4245 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4247 if (FromVT != MVT::Other) {
4248 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
4249 RegisterVT, P, DAG.getValueType(FromVT));
4258 Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT,
4264 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4265 &Values[0], ValueVTs.size());
4268 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4269 /// specified value into the registers specified by this object. This uses
4270 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4271 /// If the Flag pointer is NULL, no flag is used.
4272 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
4273 SDValue &Chain, SDValue *Flag) const {
4274 // Get the list of the values's legal parts.
4275 unsigned NumRegs = Regs.size();
4276 SmallVector<SDValue, 8> Parts(NumRegs);
4277 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4278 MVT ValueVT = ValueVTs[Value];
4279 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4280 MVT RegisterVT = RegVTs[Value];
4282 getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
4283 &Parts[Part], NumParts, RegisterVT);
4287 // Copy the parts into the registers.
4288 SmallVector<SDValue, 8> Chains(NumRegs);
4289 for (unsigned i = 0; i != NumRegs; ++i) {
4292 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4294 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4295 *Flag = Part.getValue(1);
4297 Chains[i] = Part.getValue(0);
4300 if (NumRegs == 1 || Flag)
4301 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4302 // flagged to it. That is the CopyToReg nodes and the user are considered
4303 // a single scheduling unit. If we create a TokenFactor and return it as
4304 // chain, then the TokenFactor is both a predecessor (operand) of the
4305 // user as well as a successor (the TF operands are flagged to the user).
4306 // c1, f1 = CopyToReg
4307 // c2, f2 = CopyToReg
4308 // c3 = TokenFactor c1, c2
4311 Chain = Chains[NumRegs-1];
4313 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4316 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4317 /// operand list. This adds the code marker and includes the number of
4318 /// values added into it.
4319 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4320 std::vector<SDValue> &Ops) const {
4321 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4322 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4323 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4324 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4325 MVT RegisterVT = RegVTs[Value];
4326 for (unsigned i = 0; i != NumRegs; ++i) {
4327 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4328 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4333 /// isAllocatableRegister - If the specified register is safe to allocate,
4334 /// i.e. it isn't a stack pointer or some other special register, return the
4335 /// register class for the register. Otherwise, return null.
4336 static const TargetRegisterClass *
4337 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4338 const TargetLowering &TLI,
4339 const TargetRegisterInfo *TRI) {
4340 MVT FoundVT = MVT::Other;
4341 const TargetRegisterClass *FoundRC = 0;
4342 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4343 E = TRI->regclass_end(); RCI != E; ++RCI) {
4344 MVT ThisVT = MVT::Other;
4346 const TargetRegisterClass *RC = *RCI;
4347 // If none of the the value types for this register class are valid, we
4348 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4349 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4351 if (TLI.isTypeLegal(*I)) {
4352 // If we have already found this register in a different register class,
4353 // choose the one with the largest VT specified. For example, on
4354 // PowerPC, we favor f64 register classes over f32.
4355 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4362 if (ThisVT == MVT::Other) continue;
4364 // NOTE: This isn't ideal. In particular, this might allocate the
4365 // frame pointer in functions that need it (due to them not being taken
4366 // out of allocation, because a variable sized allocation hasn't been seen
4367 // yet). This is a slight code pessimization, but should still work.
4368 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4369 E = RC->allocation_order_end(MF); I != E; ++I)
4371 // We found a matching register class. Keep looking at others in case
4372 // we find one with larger registers that this physreg is also in.
4383 /// AsmOperandInfo - This contains information for each constraint that we are
4385 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4386 public TargetLowering::AsmOperandInfo {
4387 /// CallOperand - If this is the result output operand or a clobber
4388 /// this is null, otherwise it is the incoming operand to the CallInst.
4389 /// This gets modified as the asm is processed.
4390 SDValue CallOperand;
4392 /// AssignedRegs - If this is a register or register class operand, this
4393 /// contains the set of register corresponding to the operand.
4394 RegsForValue AssignedRegs;
4396 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4397 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4400 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4401 /// busy in OutputRegs/InputRegs.
4402 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4403 std::set<unsigned> &OutputRegs,
4404 std::set<unsigned> &InputRegs,
4405 const TargetRegisterInfo &TRI) const {
4407 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4408 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4411 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4412 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4416 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4417 /// corresponds to. If there is no Value* for this operand, it returns
4419 MVT getCallOperandValMVT(const TargetLowering &TLI,
4420 const TargetData *TD) const {
4421 if (CallOperandVal == 0) return MVT::Other;
4423 if (isa<BasicBlock>(CallOperandVal))
4424 return TLI.getPointerTy();
4426 const llvm::Type *OpTy = CallOperandVal->getType();
4428 // If this is an indirect operand, the operand is a pointer to the
4431 OpTy = cast<PointerType>(OpTy)->getElementType();
4433 // If OpTy is not a single value, it may be a struct/union that we
4434 // can tile with integers.
4435 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4436 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4445 OpTy = IntegerType::get(BitSize);
4450 return TLI.getValueType(OpTy, true);
4454 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4456 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4457 const TargetRegisterInfo &TRI) {
4458 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4460 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4461 for (; *Aliases; ++Aliases)
4462 Regs.insert(*Aliases);
4465 } // end llvm namespace.
4468 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4469 /// specified operand. We prefer to assign virtual registers, to allow the
4470 /// register allocator handle the assignment process. However, if the asm uses
4471 /// features that we can't model on machineinstrs, we have SDISel do the
4472 /// allocation. This produces generally horrible, but correct, code.
4474 /// OpInfo describes the operand.
4475 /// Input and OutputRegs are the set of already allocated physical registers.
4477 void SelectionDAGLowering::
4478 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4479 std::set<unsigned> &OutputRegs,
4480 std::set<unsigned> &InputRegs) {
4481 // Compute whether this value requires an input register, an output register,
4483 bool isOutReg = false;
4484 bool isInReg = false;
4485 switch (OpInfo.Type) {
4486 case InlineAsm::isOutput:
4489 // If there is an input constraint that matches this, we need to reserve
4490 // the input register so no other inputs allocate to it.
4491 isInReg = OpInfo.hasMatchingInput();
4493 case InlineAsm::isInput:
4497 case InlineAsm::isClobber:
4504 MachineFunction &MF = DAG.getMachineFunction();
4505 SmallVector<unsigned, 4> Regs;
4507 // If this is a constraint for a single physreg, or a constraint for a
4508 // register class, find it.
4509 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4510 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4511 OpInfo.ConstraintVT);
4513 unsigned NumRegs = 1;
4514 if (OpInfo.ConstraintVT != MVT::Other) {
4515 // If this is a FP input in an integer register (or visa versa) insert a bit
4516 // cast of the input value. More generally, handle any case where the input
4517 // value disagrees with the register class we plan to stick this in.
4518 if (OpInfo.Type == InlineAsm::isInput &&
4519 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4520 // Try to convert to the first MVT that the reg class contains. If the
4521 // types are identical size, use a bitcast to convert (e.g. two differing
4523 MVT RegVT = *PhysReg.second->vt_begin();
4524 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4525 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, RegVT,
4526 OpInfo.CallOperand);
4527 OpInfo.ConstraintVT = RegVT;
4528 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4529 // If the input is a FP value and we want it in FP registers, do a
4530 // bitcast to the corresponding integer type. This turns an f64 value
4531 // into i64, which can be passed with two i32 values on a 32-bit
4533 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4534 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, RegVT,
4535 OpInfo.CallOperand);
4536 OpInfo.ConstraintVT = RegVT;
4540 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4544 MVT ValueVT = OpInfo.ConstraintVT;
4546 // If this is a constraint for a specific physical register, like {r17},
4548 if (PhysReg.first) {
4549 if (OpInfo.ConstraintVT == MVT::Other)
4550 ValueVT = *PhysReg.second->vt_begin();
4552 // Get the actual register value type. This is important, because the user
4553 // may have asked for (e.g.) the AX register in i32 type. We need to
4554 // remember that AX is actually i16 to get the right extension.
4555 RegVT = *PhysReg.second->vt_begin();
4557 // This is a explicit reference to a physical register.
4558 Regs.push_back(PhysReg.first);
4560 // If this is an expanded reference, add the rest of the regs to Regs.
4562 TargetRegisterClass::iterator I = PhysReg.second->begin();
4563 for (; *I != PhysReg.first; ++I)
4564 assert(I != PhysReg.second->end() && "Didn't find reg!");
4566 // Already added the first reg.
4568 for (; NumRegs; --NumRegs, ++I) {
4569 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4573 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4574 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4575 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4579 // Otherwise, if this was a reference to an LLVM register class, create vregs
4580 // for this reference.
4581 std::vector<unsigned> RegClassRegs;
4582 const TargetRegisterClass *RC = PhysReg.second;
4584 // If this is a tied register, our regalloc doesn't know how to maintain
4585 // the constraint, so we have to pick a register to pin the input/output to.
4586 // If it isn't a matched constraint, go ahead and create vreg and let the
4587 // regalloc do its thing.
4588 if (!OpInfo.hasMatchingInput()) {
4589 RegVT = *PhysReg.second->vt_begin();
4590 if (OpInfo.ConstraintVT == MVT::Other)
4593 // Create the appropriate number of virtual registers.
4594 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4595 for (; NumRegs; --NumRegs)
4596 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4598 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4602 // Otherwise, we can't allocate it. Let the code below figure out how to
4603 // maintain these constraints.
4604 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4607 // This is a reference to a register class that doesn't directly correspond
4608 // to an LLVM register class. Allocate NumRegs consecutive, available,
4609 // registers from the class.
4610 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4611 OpInfo.ConstraintVT);
4614 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4615 unsigned NumAllocated = 0;
4616 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4617 unsigned Reg = RegClassRegs[i];
4618 // See if this register is available.
4619 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4620 (isInReg && InputRegs.count(Reg))) { // Already used.
4621 // Make sure we find consecutive registers.
4626 // Check to see if this register is allocatable (i.e. don't give out the
4629 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4630 if (!RC) { // Couldn't allocate this register.
4631 // Reset NumAllocated to make sure we return consecutive registers.
4637 // Okay, this register is good, we can use it.
4640 // If we allocated enough consecutive registers, succeed.
4641 if (NumAllocated == NumRegs) {
4642 unsigned RegStart = (i-NumAllocated)+1;
4643 unsigned RegEnd = i+1;
4644 // Mark all of the allocated registers used.
4645 for (unsigned i = RegStart; i != RegEnd; ++i)
4646 Regs.push_back(RegClassRegs[i]);
4648 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4649 OpInfo.ConstraintVT);
4650 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4655 // Otherwise, we couldn't allocate enough registers for this.
4658 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4659 /// processed uses a memory 'm' constraint.
4661 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4662 TargetLowering &TLI) {
4663 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4664 InlineAsm::ConstraintInfo &CI = CInfos[i];
4665 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4666 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4667 if (CType == TargetLowering::C_Memory)
4675 /// visitInlineAsm - Handle a call to an InlineAsm object.
4677 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4678 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4680 /// ConstraintOperands - Information about all of the constraints.
4681 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4683 SDValue Chain = getRoot();
4686 std::set<unsigned> OutputRegs, InputRegs;
4688 // Do a prepass over the constraints, canonicalizing them, and building up the
4689 // ConstraintOperands list.
4690 std::vector<InlineAsm::ConstraintInfo>
4691 ConstraintInfos = IA->ParseConstraints();
4693 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
4695 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4696 unsigned ResNo = 0; // ResNo - The result number of the next output.
4697 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4698 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4699 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4701 MVT OpVT = MVT::Other;
4703 // Compute the value type for each operand.
4704 switch (OpInfo.Type) {
4705 case InlineAsm::isOutput:
4706 // Indirect outputs just consume an argument.
4707 if (OpInfo.isIndirect) {
4708 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4712 // The return value of the call is this value. As such, there is no
4713 // corresponding argument.
4714 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4715 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4716 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4718 assert(ResNo == 0 && "Asm only has one result!");
4719 OpVT = TLI.getValueType(CS.getType());
4723 case InlineAsm::isInput:
4724 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4726 case InlineAsm::isClobber:
4731 // If this is an input or an indirect output, process the call argument.
4732 // BasicBlocks are labels, currently appearing only in asm's.
4733 if (OpInfo.CallOperandVal) {
4734 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
4735 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4737 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4740 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
4743 OpInfo.ConstraintVT = OpVT;
4746 // Second pass over the constraints: compute which constraint option to use
4747 // and assign registers to constraints that want a specific physreg.
4748 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4749 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4751 // If this is an output operand with a matching input operand, look up the
4752 // matching input. It might have a different type (e.g. the output might be
4753 // i32 and the input i64) and we need to pick the larger width to ensure we
4754 // reserve the right number of registers.
4755 if (OpInfo.hasMatchingInput()) {
4756 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
4757 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
4758 assert(OpInfo.ConstraintVT.isInteger() &&
4759 Input.ConstraintVT.isInteger() &&
4760 "Asm constraints must be the same or different sized integers");
4761 if (OpInfo.ConstraintVT.getSizeInBits() <
4762 Input.ConstraintVT.getSizeInBits())
4763 OpInfo.ConstraintVT = Input.ConstraintVT;
4765 Input.ConstraintVT = OpInfo.ConstraintVT;
4769 // Compute the constraint code and ConstraintType to use.
4770 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
4772 // If this is a memory input, and if the operand is not indirect, do what we
4773 // need to to provide an address for the memory input.
4774 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4775 !OpInfo.isIndirect) {
4776 assert(OpInfo.Type == InlineAsm::isInput &&
4777 "Can only indirectify direct input operands!");
4779 // Memory operands really want the address of the value. If we don't have
4780 // an indirect input, put it in the constpool if we can, otherwise spill
4781 // it to a stack slot.
4783 // If the operand is a float, integer, or vector constant, spill to a
4784 // constant pool entry to get its address.
4785 Value *OpVal = OpInfo.CallOperandVal;
4786 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4787 isa<ConstantVector>(OpVal)) {
4788 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4789 TLI.getPointerTy());
4791 // Otherwise, create a stack slot and emit a store to it before the
4793 const Type *Ty = OpVal->getType();
4794 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4795 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4796 MachineFunction &MF = DAG.getMachineFunction();
4797 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4798 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4799 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4800 OpInfo.CallOperand = StackSlot;
4803 // There is no longer a Value* corresponding to this operand.
4804 OpInfo.CallOperandVal = 0;
4805 // It is now an indirect operand.
4806 OpInfo.isIndirect = true;
4809 // If this constraint is for a specific register, allocate it before
4811 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4812 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4814 ConstraintInfos.clear();
4817 // Second pass - Loop over all of the operands, assigning virtual or physregs
4818 // to register class operands.
4819 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4820 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4822 // C_Register operands have already been allocated, Other/Memory don't need
4824 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4825 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4828 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4829 std::vector<SDValue> AsmNodeOperands;
4830 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4831 AsmNodeOperands.push_back(
4832 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4835 // Loop over all of the inputs, copying the operand values into the
4836 // appropriate registers and processing the output regs.
4837 RegsForValue RetValRegs;
4839 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4840 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4842 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4843 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4845 switch (OpInfo.Type) {
4846 case InlineAsm::isOutput: {
4847 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4848 OpInfo.ConstraintType != TargetLowering::C_Register) {
4849 // Memory output, or 'other' output (e.g. 'X' constraint).
4850 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4852 // Add information to the INLINEASM node to know about this output.
4853 unsigned ResOpType = 4/*MEM*/ | (1<<3);
4854 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4855 TLI.getPointerTy()));
4856 AsmNodeOperands.push_back(OpInfo.CallOperand);
4860 // Otherwise, this is a register or register class output.
4862 // Copy the output from the appropriate register. Find a register that
4864 if (OpInfo.AssignedRegs.Regs.empty()) {
4865 cerr << "Couldn't allocate output reg for constraint '"
4866 << OpInfo.ConstraintCode << "'!\n";
4870 // If this is an indirect operand, store through the pointer after the
4872 if (OpInfo.isIndirect) {
4873 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4874 OpInfo.CallOperandVal));
4876 // This is the result value of the call.
4877 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4878 // Concatenate this output onto the outputs list.
4879 RetValRegs.append(OpInfo.AssignedRegs);
4882 // Add information to the INLINEASM node to know that this register is
4884 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
4885 6 /* EARLYCLOBBER REGDEF */ :
4887 DAG, AsmNodeOperands);
4890 case InlineAsm::isInput: {
4891 SDValue InOperandVal = OpInfo.CallOperand;
4893 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
4894 // If this is required to match an output register we have already set,
4895 // just use its register.
4896 unsigned OperandNo = OpInfo.getMatchedOperand();
4898 // Scan until we find the definition we already emitted of this operand.
4899 // When we find it, create a RegsForValue operand.
4900 unsigned CurOp = 2; // The first operand.
4901 for (; OperandNo; --OperandNo) {
4902 // Advance to the next operand.
4904 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
4905 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4906 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
4907 (NumOps & 7) == 4 /*MEM*/) &&
4908 "Skipped past definitions?");
4909 CurOp += (NumOps>>3)+1;
4913 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
4914 if ((NumOps & 7) == 2 /*REGDEF*/
4915 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
4916 // Add NumOps>>3 registers to MatchedRegs.
4917 RegsForValue MatchedRegs;
4918 MatchedRegs.TLI = &TLI;
4919 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4920 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4921 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4923 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4924 MatchedRegs.Regs.push_back(Reg);
4927 // Use the produced MatchedRegs object to
4928 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4929 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4932 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
4933 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4934 // Add information to the INLINEASM node to know about this input.
4935 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
4936 TLI.getPointerTy()));
4937 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4942 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4943 assert(!OpInfo.isIndirect &&
4944 "Don't know how to handle indirect other inputs yet!");
4946 std::vector<SDValue> Ops;
4947 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4948 hasMemory, Ops, DAG);
4950 cerr << "Invalid operand for inline asm constraint '"
4951 << OpInfo.ConstraintCode << "'!\n";
4955 // Add information to the INLINEASM node to know about this input.
4956 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4957 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4958 TLI.getPointerTy()));
4959 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4961 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4962 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4963 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4964 "Memory operands expect pointer values");
4966 // Add information to the INLINEASM node to know about this input.
4967 unsigned ResOpType = 4/*MEM*/ | (1<<3);
4968 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4969 TLI.getPointerTy()));
4970 AsmNodeOperands.push_back(InOperandVal);
4974 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4975 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4976 "Unknown constraint type!");
4977 assert(!OpInfo.isIndirect &&
4978 "Don't know how to handle indirect register inputs yet!");
4980 // Copy the input into the appropriate registers.
4981 if (OpInfo.AssignedRegs.Regs.empty()) {
4982 cerr << "Couldn't allocate output reg for constraint '"
4983 << OpInfo.ConstraintCode << "'!\n";
4987 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4989 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
4990 DAG, AsmNodeOperands);
4993 case InlineAsm::isClobber: {
4994 // Add the clobbered value to the operand list, so that the register
4995 // allocator is aware that the physreg got clobbered.
4996 if (!OpInfo.AssignedRegs.Regs.empty())
4997 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
4998 DAG, AsmNodeOperands);
5004 // Finish up input operands.
5005 AsmNodeOperands[0] = Chain;
5006 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5008 Chain = DAG.getNode(ISD::INLINEASM,
5009 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5010 &AsmNodeOperands[0], AsmNodeOperands.size());
5011 Flag = Chain.getValue(1);
5013 // If this asm returns a register value, copy the result from that register
5014 // and set it as the value of the call.
5015 if (!RetValRegs.Regs.empty()) {
5016 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
5018 // FIXME: Why don't we do this for inline asms with MRVs?
5019 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5020 MVT ResultType = TLI.getValueType(CS.getType());
5022 // If any of the results of the inline asm is a vector, it may have the
5023 // wrong width/num elts. This can happen for register classes that can
5024 // contain multiple different value types. The preg or vreg allocated may
5025 // not have the same VT as was expected. Convert it to the right type
5026 // with bit_convert.
5027 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5028 Val = DAG.getNode(ISD::BIT_CONVERT, ResultType, Val);
5030 } else if (ResultType != Val.getValueType() &&
5031 ResultType.isInteger() && Val.getValueType().isInteger()) {
5032 // If a result value was tied to an input value, the computed result may
5033 // have a wider width than the expected result. Extract the relevant
5035 Val = DAG.getNode(ISD::TRUNCATE, ResultType, Val);
5038 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5041 setValue(CS.getInstruction(), Val);
5044 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5046 // Process indirect outputs, first output all of the flagged copies out of
5048 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5049 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5050 Value *Ptr = IndirectStoresToEmit[i].second;
5051 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
5052 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5055 // Emit the non-flagged stores from the physregs.
5056 SmallVector<SDValue, 8> OutChains;
5057 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5058 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
5059 getValue(StoresToEmit[i].second),
5060 StoresToEmit[i].second, 0));
5061 if (!OutChains.empty())
5062 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5063 &OutChains[0], OutChains.size());
5068 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5069 SDValue Src = getValue(I.getOperand(0));
5071 MVT IntPtr = TLI.getPointerTy();
5073 if (IntPtr.bitsLT(Src.getValueType()))
5074 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
5075 else if (IntPtr.bitsGT(Src.getValueType()))
5076 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
5078 // Scale the source by the type size.
5079 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
5080 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
5081 Src, DAG.getIntPtrConstant(ElementSize));
5083 TargetLowering::ArgListTy Args;
5084 TargetLowering::ArgListEntry Entry;
5086 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5087 Args.push_back(Entry);
5089 std::pair<SDValue,SDValue> Result =
5090 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5091 CallingConv::C, PerformTailCallOpt,
5092 DAG.getExternalSymbol("malloc", IntPtr),
5094 setValue(&I, Result.first); // Pointers always fit in registers
5095 DAG.setRoot(Result.second);
5098 void SelectionDAGLowering::visitFree(FreeInst &I) {
5099 TargetLowering::ArgListTy Args;
5100 TargetLowering::ArgListEntry Entry;
5101 Entry.Node = getValue(I.getOperand(0));
5102 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5103 Args.push_back(Entry);
5104 MVT IntPtr = TLI.getPointerTy();
5105 std::pair<SDValue,SDValue> Result =
5106 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5107 CallingConv::C, PerformTailCallOpt,
5108 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
5109 DAG.setRoot(Result.second);
5112 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5113 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
5114 getValue(I.getOperand(1)),
5115 DAG.getSrcValue(I.getOperand(1))));
5118 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5119 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
5120 getValue(I.getOperand(0)),
5121 DAG.getSrcValue(I.getOperand(0)));
5123 DAG.setRoot(V.getValue(1));
5126 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5127 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
5128 getValue(I.getOperand(1)),
5129 DAG.getSrcValue(I.getOperand(1))));
5132 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5133 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
5134 getValue(I.getOperand(1)),
5135 getValue(I.getOperand(2)),
5136 DAG.getSrcValue(I.getOperand(1)),
5137 DAG.getSrcValue(I.getOperand(2))));
5140 /// TargetLowering::LowerArguments - This is the default LowerArguments
5141 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5142 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5143 /// integrated into SDISel.
5144 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5145 SmallVectorImpl<SDValue> &ArgValues) {
5146 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5147 SmallVector<SDValue, 3+16> Ops;
5148 Ops.push_back(DAG.getRoot());
5149 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5150 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5152 // Add one result value for each formal argument.
5153 SmallVector<MVT, 16> RetVals;
5155 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5157 SmallVector<MVT, 4> ValueVTs;
5158 ComputeValueVTs(*this, I->getType(), ValueVTs);
5159 for (unsigned Value = 0, NumValues = ValueVTs.size();
5160 Value != NumValues; ++Value) {
5161 MVT VT = ValueVTs[Value];
5162 const Type *ArgTy = VT.getTypeForMVT();
5163 ISD::ArgFlagsTy Flags;
5164 unsigned OriginalAlignment =
5165 getTargetData()->getABITypeAlignment(ArgTy);
5167 if (F.paramHasAttr(j, Attribute::ZExt))
5169 if (F.paramHasAttr(j, Attribute::SExt))
5171 if (F.paramHasAttr(j, Attribute::InReg))
5173 if (F.paramHasAttr(j, Attribute::StructRet))
5175 if (F.paramHasAttr(j, Attribute::ByVal)) {
5177 const PointerType *Ty = cast<PointerType>(I->getType());
5178 const Type *ElementTy = Ty->getElementType();
5179 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5180 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5181 // For ByVal, alignment should be passed from FE. BE will guess if
5182 // this info is not there but there are cases it cannot get right.
5183 if (F.getParamAlignment(j))
5184 FrameAlign = F.getParamAlignment(j);
5185 Flags.setByValAlign(FrameAlign);
5186 Flags.setByValSize(FrameSize);
5188 if (F.paramHasAttr(j, Attribute::Nest))
5190 Flags.setOrigAlign(OriginalAlignment);
5192 MVT RegisterVT = getRegisterType(VT);
5193 unsigned NumRegs = getNumRegisters(VT);
5194 for (unsigned i = 0; i != NumRegs; ++i) {
5195 RetVals.push_back(RegisterVT);
5196 ISD::ArgFlagsTy MyFlags = Flags;
5197 if (NumRegs > 1 && i == 0)
5199 // if it isn't first piece, alignment must be 1
5201 MyFlags.setOrigAlign(1);
5202 Ops.push_back(DAG.getArgFlags(MyFlags));
5207 RetVals.push_back(MVT::Other);
5210 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
5211 DAG.getVTList(&RetVals[0], RetVals.size()),
5212 &Ops[0], Ops.size()).getNode();
5214 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5215 // allows exposing the loads that may be part of the argument access to the
5216 // first DAGCombiner pass.
5217 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5219 // The number of results should match up, except that the lowered one may have
5220 // an extra flag result.
5221 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5222 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5223 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5224 && "Lowering produced unexpected number of results!");
5226 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5227 if (Result != TmpRes.getNode() && Result->use_empty()) {
5228 HandleSDNode Dummy(DAG.getRoot());
5229 DAG.RemoveDeadNode(Result);
5232 Result = TmpRes.getNode();
5234 unsigned NumArgRegs = Result->getNumValues() - 1;
5235 DAG.setRoot(SDValue(Result, NumArgRegs));
5237 // Set up the return result vector.
5240 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5242 SmallVector<MVT, 4> ValueVTs;
5243 ComputeValueVTs(*this, I->getType(), ValueVTs);
5244 for (unsigned Value = 0, NumValues = ValueVTs.size();
5245 Value != NumValues; ++Value) {
5246 MVT VT = ValueVTs[Value];
5247 MVT PartVT = getRegisterType(VT);
5249 unsigned NumParts = getNumRegisters(VT);
5250 SmallVector<SDValue, 4> Parts(NumParts);
5251 for (unsigned j = 0; j != NumParts; ++j)
5252 Parts[j] = SDValue(Result, i++);
5254 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5255 if (F.paramHasAttr(Idx, Attribute::SExt))
5256 AssertOp = ISD::AssertSext;
5257 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5258 AssertOp = ISD::AssertZext;
5260 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
5264 assert(i == NumArgRegs && "Argument register count mismatch!");
5268 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5269 /// implementation, which just inserts an ISD::CALL node, which is later custom
5270 /// lowered by the target to something concrete. FIXME: When all targets are
5271 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5272 std::pair<SDValue, SDValue>
5273 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5274 bool RetSExt, bool RetZExt, bool isVarArg,
5276 unsigned CallingConv, bool isTailCall,
5278 ArgListTy &Args, SelectionDAG &DAG) {
5279 assert((!isTailCall || PerformTailCallOpt) &&
5280 "isTailCall set when tail-call optimizations are disabled!");
5282 SmallVector<SDValue, 32> Ops;
5283 Ops.push_back(Chain); // Op#0 - Chain
5284 Ops.push_back(Callee);
5286 // Handle all of the outgoing arguments.
5287 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5288 SmallVector<MVT, 4> ValueVTs;
5289 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5290 for (unsigned Value = 0, NumValues = ValueVTs.size();
5291 Value != NumValues; ++Value) {
5292 MVT VT = ValueVTs[Value];
5293 const Type *ArgTy = VT.getTypeForMVT();
5294 SDValue Op = SDValue(Args[i].Node.getNode(),
5295 Args[i].Node.getResNo() + Value);
5296 ISD::ArgFlagsTy Flags;
5297 unsigned OriginalAlignment =
5298 getTargetData()->getABITypeAlignment(ArgTy);
5304 if (Args[i].isInReg)
5308 if (Args[i].isByVal) {
5310 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5311 const Type *ElementTy = Ty->getElementType();
5312 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5313 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5314 // For ByVal, alignment should come from FE. BE will guess if this
5315 // info is not there but there are cases it cannot get right.
5316 if (Args[i].Alignment)
5317 FrameAlign = Args[i].Alignment;
5318 Flags.setByValAlign(FrameAlign);
5319 Flags.setByValSize(FrameSize);
5323 Flags.setOrigAlign(OriginalAlignment);
5325 MVT PartVT = getRegisterType(VT);
5326 unsigned NumParts = getNumRegisters(VT);
5327 SmallVector<SDValue, 4> Parts(NumParts);
5328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5331 ExtendKind = ISD::SIGN_EXTEND;
5332 else if (Args[i].isZExt)
5333 ExtendKind = ISD::ZERO_EXTEND;
5335 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5337 for (unsigned i = 0; i != NumParts; ++i) {
5338 // if it isn't first piece, alignment must be 1
5339 ISD::ArgFlagsTy MyFlags = Flags;
5340 if (NumParts > 1 && i == 0)
5343 MyFlags.setOrigAlign(1);
5345 Ops.push_back(Parts[i]);
5346 Ops.push_back(DAG.getArgFlags(MyFlags));
5351 // Figure out the result value types. We start by making a list of
5352 // the potentially illegal return value types.
5353 SmallVector<MVT, 4> LoweredRetTys;
5354 SmallVector<MVT, 4> RetTys;
5355 ComputeValueVTs(*this, RetTy, RetTys);
5357 // Then we translate that to a list of legal types.
5358 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5360 MVT RegisterVT = getRegisterType(VT);
5361 unsigned NumRegs = getNumRegisters(VT);
5362 for (unsigned i = 0; i != NumRegs; ++i)
5363 LoweredRetTys.push_back(RegisterVT);
5366 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5368 // Create the CALL node.
5369 SDValue Res = DAG.getCall(CallingConv, isVarArg, isTailCall, isInreg,
5370 DAG.getVTList(&LoweredRetTys[0],
5371 LoweredRetTys.size()),
5374 Chain = Res.getValue(LoweredRetTys.size() - 1);
5376 // Gather up the call result into a single value.
5377 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5378 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5381 AssertOp = ISD::AssertSext;
5383 AssertOp = ISD::AssertZext;
5385 SmallVector<SDValue, 4> ReturnValues;
5387 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5389 MVT RegisterVT = getRegisterType(VT);
5390 unsigned NumRegs = getNumRegisters(VT);
5391 unsigned RegNoEnd = NumRegs + RegNo;
5392 SmallVector<SDValue, 4> Results;
5393 for (; RegNo != RegNoEnd; ++RegNo)
5394 Results.push_back(Res.getValue(RegNo));
5395 SDValue ReturnValue =
5396 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
5398 ReturnValues.push_back(ReturnValue);
5400 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
5401 &ReturnValues[0], ReturnValues.size());
5404 return std::make_pair(Res, Chain);
5407 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5408 assert(0 && "LowerOperation not implemented for this target!");
5414 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5415 SDValue Op = getValue(V);
5416 assert((Op.getOpcode() != ISD::CopyFromReg ||
5417 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5418 "Copy from a reg to the same reg!");
5419 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5421 RegsForValue RFV(TLI, Reg, V->getType());
5422 SDValue Chain = DAG.getEntryNode();
5423 RFV.getCopyToRegs(Op, DAG, Chain, 0);
5424 PendingExports.push_back(Chain);
5427 #include "llvm/CodeGen/SelectionDAGISel.h"
5429 void SelectionDAGISel::
5430 LowerArguments(BasicBlock *LLVMBB) {
5431 // If this is the entry block, emit arguments.
5432 Function &F = *LLVMBB->getParent();
5433 SDValue OldRoot = SDL->DAG.getRoot();
5434 SmallVector<SDValue, 16> Args;
5435 TLI.LowerArguments(F, SDL->DAG, Args);
5438 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5440 SmallVector<MVT, 4> ValueVTs;
5441 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5442 unsigned NumValues = ValueVTs.size();
5443 if (!AI->use_empty()) {
5444 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5445 // If this argument is live outside of the entry block, insert a copy from
5446 // whereever we got it to the vreg that other BB's will reference it as.
5447 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5448 if (VMI != FuncInfo->ValueMap.end()) {
5449 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5455 // Finally, if the target has anything special to do, allow it to do so.
5456 // FIXME: this should insert code into the DAG!
5457 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5460 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5461 /// ensure constants are generated when needed. Remember the virtual registers
5462 /// that need to be added to the Machine PHI nodes as input. We cannot just
5463 /// directly add them, because expansion might result in multiple MBB's for one
5464 /// BB. As such, the start of the BB might correspond to a different MBB than
5468 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5469 TerminatorInst *TI = LLVMBB->getTerminator();
5471 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5473 // Check successor nodes' PHI nodes that expect a constant to be available
5475 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5476 BasicBlock *SuccBB = TI->getSuccessor(succ);
5477 if (!isa<PHINode>(SuccBB->begin())) continue;
5478 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5480 // If this terminator has multiple identical successors (common for
5481 // switches), only handle each succ once.
5482 if (!SuccsHandled.insert(SuccMBB)) continue;
5484 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5487 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5488 // nodes and Machine PHI nodes, but the incoming operands have not been
5490 for (BasicBlock::iterator I = SuccBB->begin();
5491 (PN = dyn_cast<PHINode>(I)); ++I) {
5492 // Ignore dead phi's.
5493 if (PN->use_empty()) continue;
5496 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5498 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5499 unsigned &RegOut = SDL->ConstantsOut[C];
5501 RegOut = FuncInfo->CreateRegForValue(C);
5502 SDL->CopyValueToVirtualRegister(C, RegOut);
5506 Reg = FuncInfo->ValueMap[PHIOp];
5508 assert(isa<AllocaInst>(PHIOp) &&
5509 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5510 "Didn't codegen value into a register!??");
5511 Reg = FuncInfo->CreateRegForValue(PHIOp);
5512 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5516 // Remember that this register needs to added to the machine PHI node as
5517 // the input for this MBB.
5518 SmallVector<MVT, 4> ValueVTs;
5519 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5520 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5521 MVT VT = ValueVTs[vti];
5522 unsigned NumRegisters = TLI.getNumRegisters(VT);
5523 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5524 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5525 Reg += NumRegisters;
5529 SDL->ConstantsOut.clear();
5532 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5533 /// supports legal types, and it emits MachineInstrs directly instead of
5534 /// creating SelectionDAG nodes.
5537 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5539 TerminatorInst *TI = LLVMBB->getTerminator();
5541 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5542 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5544 // Check successor nodes' PHI nodes that expect a constant to be available
5546 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5547 BasicBlock *SuccBB = TI->getSuccessor(succ);
5548 if (!isa<PHINode>(SuccBB->begin())) continue;
5549 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5551 // If this terminator has multiple identical successors (common for
5552 // switches), only handle each succ once.
5553 if (!SuccsHandled.insert(SuccMBB)) continue;
5555 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5558 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5559 // nodes and Machine PHI nodes, but the incoming operands have not been
5561 for (BasicBlock::iterator I = SuccBB->begin();
5562 (PN = dyn_cast<PHINode>(I)); ++I) {
5563 // Ignore dead phi's.
5564 if (PN->use_empty()) continue;
5566 // Only handle legal types. Two interesting things to note here. First,
5567 // by bailing out early, we may leave behind some dead instructions,
5568 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5569 // own moves. Second, this check is necessary becuase FastISel doesn't
5570 // use CreateRegForValue to create registers, so it always creates
5571 // exactly one register for each non-void instruction.
5572 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5573 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5576 VT = TLI.getTypeToTransformTo(VT);
5578 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5583 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5585 unsigned Reg = F->getRegForValue(PHIOp);
5587 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5590 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));