1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/InlineAsm.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "llvm/CodeGen/MachineModuleInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/CodeGen/DwarfWriter.h"
42 #include "llvm/Analysis/DebugInfo.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetFrameInfo.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetLowering.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
59 /// LimitFloatPrecision - Generate low-precision inline sequences for
60 /// some float libcalls (6, 8 or 12 bits).
61 static unsigned LimitFloatPrecision;
63 static cl::opt<unsigned, true>
64 LimitFPPrecision("limit-float-precision",
65 cl::desc("Generate low-precision inline sequences "
66 "for some float libcalls"),
67 cl::location(LimitFloatPrecision),
70 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
71 /// of insertvalue or extractvalue indices that identify a member, return
72 /// the linearized index of the start of the member.
74 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
75 const unsigned *Indices,
76 const unsigned *IndicesEnd,
77 unsigned CurIndex = 0) {
78 // Base case: We're done.
79 if (Indices && Indices == IndicesEnd)
82 // Given a struct type, recursively traverse the elements.
83 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
84 for (StructType::element_iterator EB = STy->element_begin(),
86 EE = STy->element_end();
88 if (Indices && *Indices == unsigned(EI - EB))
89 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
90 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
94 // Given an array type, recursively traverse the elements.
95 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
96 const Type *EltTy = ATy->getElementType();
97 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
98 if (Indices && *Indices == i)
99 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
100 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
104 // We haven't found the type we're looking for, so keep searching.
108 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
109 /// EVTs that represent all the individual underlying
110 /// non-aggregate types that comprise it.
112 /// If Offsets is non-null, it points to a vector to be filled in
113 /// with the in-memory offsets of each of the individual values.
115 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
116 SmallVectorImpl<EVT> &ValueVTs,
117 SmallVectorImpl<uint64_t> *Offsets = 0,
118 uint64_t StartingOffset = 0) {
119 // Given a struct type, recursively traverse the elements.
120 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
121 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
122 for (StructType::element_iterator EB = STy->element_begin(),
124 EE = STy->element_end();
126 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
127 StartingOffset + SL->getElementOffset(EI - EB));
130 // Given an array type, recursively traverse the elements.
131 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
132 const Type *EltTy = ATy->getElementType();
133 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
134 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
135 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
136 StartingOffset + i * EltSize);
139 // Interpret void as zero return values.
140 if (Ty == Type::VoidTy)
142 // Base case: we can get an EVT for this LLVM IR type.
143 ValueVTs.push_back(TLI.getValueType(Ty));
145 Offsets->push_back(StartingOffset);
149 /// RegsForValue - This struct represents the registers (physical or virtual)
150 /// that a particular set of values is assigned, and the type information about
151 /// the value. The most common situation is to represent one value at a time,
152 /// but struct or array values are handled element-wise as multiple values.
153 /// The splitting of aggregates is performed recursively, so that we never
154 /// have aggregate-typed registers. The values at this point do not necessarily
155 /// have legal types, so each value may require one or more registers of some
158 struct VISIBILITY_HIDDEN RegsForValue {
159 /// TLI - The TargetLowering object.
161 const TargetLowering *TLI;
163 /// ValueVTs - The value types of the values, which may not be legal, and
164 /// may need be promoted or synthesized from one or more registers.
166 SmallVector<EVT, 4> ValueVTs;
168 /// RegVTs - The value types of the registers. This is the same size as
169 /// ValueVTs and it records, for each value, what the type of the assigned
170 /// register or registers are. (Individual values are never synthesized
171 /// from more than one type of register.)
173 /// With virtual registers, the contents of RegVTs is redundant with TLI's
174 /// getRegisterType member function, however when with physical registers
175 /// it is necessary to have a separate record of the types.
177 SmallVector<EVT, 4> RegVTs;
179 /// Regs - This list holds the registers assigned to the values.
180 /// Each legal or promoted value requires one register, and each
181 /// expanded value requires multiple registers.
183 SmallVector<unsigned, 4> Regs;
185 RegsForValue() : TLI(0) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> ®s,
189 EVT regvt, EVT valuevt)
190 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 const SmallVector<unsigned, 4> ®s,
193 const SmallVector<EVT, 4> ®vts,
194 const SmallVector<EVT, 4> &valuevts)
195 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
196 RegsForValue(const TargetLowering &tli,
197 unsigned Reg, const Type *Ty) : TLI(&tli) {
198 ComputeValueVTs(tli, Ty, ValueVTs);
200 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
201 EVT ValueVT = ValueVTs[Value];
202 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
203 EVT RegisterVT = TLI->getRegisterType(ValueVT);
204 for (unsigned i = 0; i != NumRegs; ++i)
205 Regs.push_back(Reg + i);
206 RegVTs.push_back(RegisterVT);
211 /// append - Add the specified values to this one.
212 void append(const RegsForValue &RHS) {
214 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
215 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
216 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
220 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
221 /// this value and returns the result as a ValueVTs value. This uses
222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
223 /// If the Flag pointer is NULL, no flag is used.
224 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
225 SDValue &Chain, SDValue *Flag) const;
227 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
228 /// specified value into the registers specified by this object. This uses
229 /// Chain/Flag as the input and updates them for the output Chain/Flag.
230 /// If the Flag pointer is NULL, no flag is used.
231 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
232 SDValue &Chain, SDValue *Flag) const;
234 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
235 /// operand list. This adds the code marker, matching input operand index
236 /// (if applicable), and includes the number of values added into it.
237 void AddInlineAsmOperands(unsigned Code,
238 bool HasMatching, unsigned MatchingIdx,
239 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
243 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
244 /// PHI nodes or outside of the basic block that defines it, or used by a
245 /// switch or atomic instruction, which may expand to multiple basic blocks.
246 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
247 if (isa<PHINode>(I)) return true;
248 BasicBlock *BB = I->getParent();
249 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
250 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
255 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
256 /// entry block, return true. This includes arguments used by switches, since
257 /// the switch may expand into multiple basic blocks.
258 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
259 // With FastISel active, we may be splitting blocks, so force creation
260 // of virtual registers for all non-dead arguments.
261 // Don't force virtual registers for byval arguments though, because
262 // fast-isel can't handle those in all cases.
263 if (EnableFastISel && !A->hasByValAttr())
264 return A->use_empty();
266 BasicBlock *Entry = A->getParent()->begin();
267 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
268 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
269 return false; // Use not in entry block.
273 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
277 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
279 bool EnableFastISel) {
282 RegInfo = &MF->getRegInfo();
284 // Create a vreg for each argument register that is not dead and is used
285 // outside of the entry block for the function.
286 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
288 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
289 InitializeRegForValue(AI);
291 // Initialize the mapping of values to registers. This is only set up for
292 // instruction values that are used outside of the block that defines
294 Function::iterator BB = Fn->begin(), EB = Fn->end();
295 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
296 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
297 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
298 const Type *Ty = AI->getAllocatedType();
299 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
301 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
304 TySize *= CUI->getZExtValue(); // Get total allocated size.
305 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
306 StaticAllocaMap[AI] =
307 MF->getFrameInfo()->CreateStackObject(TySize, Align);
310 for (; BB != EB; ++BB)
311 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
312 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
313 if (!isa<AllocaInst>(I) ||
314 !StaticAllocaMap.count(cast<AllocaInst>(I)))
315 InitializeRegForValue(I);
317 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
318 // also creates the initial PHI MachineInstrs, though none of the input
319 // operands are populated.
320 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
321 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
325 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
329 for (BasicBlock::iterator
330 I = BB->begin(), E = BB->end(); I != E; ++I) {
331 if (CallInst *CI = dyn_cast<CallInst>(I)) {
332 if (Function *F = CI->getCalledFunction()) {
333 switch (F->getIntrinsicID()) {
335 case Intrinsic::dbg_stoppoint: {
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
337 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
338 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
341 case Intrinsic::dbg_func_start: {
342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
343 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
344 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
351 PN = dyn_cast<PHINode>(I);
352 if (!PN || PN->use_empty()) continue;
354 unsigned PHIReg = ValueMap[PN];
355 assert(PHIReg && "PHI node does not have an assigned virtual register!");
357 SmallVector<EVT, 4> ValueVTs;
358 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
359 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
360 EVT VT = ValueVTs[vti];
361 unsigned NumRegisters = TLI.getNumRegisters(VT);
362 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
363 for (unsigned i = 0; i != NumRegisters; ++i)
364 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
365 PHIReg += NumRegisters;
371 unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
372 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<EVT, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 EVT ValueVT = ValueVTs[Value];
389 EVT RegisterVT = TLI.getRegisterType(ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
400 /// getCopyFromParts - Create a value that contains the specified legal parts
401 /// combined into the value they represent. If the parts combine to a type
402 /// larger then ValueVT then AssertOp can be used to specify whether the extra
403 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
404 /// (ISD::AssertSext).
405 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
406 const SDValue *Parts,
407 unsigned NumParts, EVT PartVT, EVT ValueVT,
408 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
409 assert(NumParts > 0 && "No parts to assemble!");
410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411 SDValue Val = Parts[0];
414 // Assemble the value from multiple parts.
415 if (!ValueVT.isVector() && ValueVT.isInteger()) {
416 unsigned PartBits = PartVT.getSizeInBits();
417 unsigned ValueBits = ValueVT.getSizeInBits();
419 // Assemble the power of 2 part.
420 unsigned RoundParts = NumParts & (NumParts - 1) ?
421 1 << Log2_32(NumParts) : NumParts;
422 unsigned RoundBits = PartBits * RoundParts;
423 EVT RoundVT = RoundBits == ValueBits ?
424 ValueVT : EVT::getIntegerVT(RoundBits);
427 EVT HalfVT = EVT::getIntegerVT(RoundBits/2);
429 if (RoundParts > 2) {
430 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
431 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
434 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
435 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
437 if (TLI.isBigEndian())
439 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
441 if (RoundParts < NumParts) {
442 // Assemble the trailing non-power-of-2 part.
443 unsigned OddParts = NumParts - RoundParts;
444 EVT OddVT = EVT::getIntegerVT(OddParts * PartBits);
445 Hi = getCopyFromParts(DAG, dl,
446 Parts+RoundParts, OddParts, PartVT, OddVT);
448 // Combine the round and odd parts.
450 if (TLI.isBigEndian())
452 EVT TotalVT = EVT::getIntegerVT(NumParts * PartBits);
453 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
454 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
455 DAG.getConstant(Lo.getValueType().getSizeInBits(),
456 TLI.getPointerTy()));
457 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
458 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
460 } else if (ValueVT.isVector()) {
461 // Handle a multi-element vector.
462 EVT IntermediateVT, RegisterVT;
463 unsigned NumIntermediates;
465 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
467 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
468 NumParts = NumRegs; // Silence a compiler warning.
469 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
470 assert(RegisterVT == Parts[0].getValueType() &&
471 "Part type doesn't match part!");
473 // Assemble the parts into intermediate operands.
474 SmallVector<SDValue, 8> Ops(NumIntermediates);
475 if (NumIntermediates == NumParts) {
476 // If the register was not expanded, truncate or copy the value,
478 for (unsigned i = 0; i != NumParts; ++i)
479 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
480 PartVT, IntermediateVT);
481 } else if (NumParts > 0) {
482 // If the intermediate type was expanded, build the intermediate operands
484 assert(NumParts % NumIntermediates == 0 &&
485 "Must expand into a divisible number of parts!");
486 unsigned Factor = NumParts / NumIntermediates;
487 for (unsigned i = 0; i != NumIntermediates; ++i)
488 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
489 PartVT, IntermediateVT);
492 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
494 Val = DAG.getNode(IntermediateVT.isVector() ?
495 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
496 ValueVT, &Ops[0], NumIntermediates);
497 } else if (PartVT.isFloatingPoint()) {
498 // FP split into multiple FP parts (for ppcf128)
499 assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
502 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
503 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
504 if (TLI.isBigEndian())
506 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
508 // FP split into integer parts (soft fp)
509 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
510 !PartVT.isVector() && "Unexpected split");
511 EVT IntVT = EVT::getIntegerVT(ValueVT.getSizeInBits());
512 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
516 // There is now one part, held in Val. Correct it to match ValueVT.
517 PartVT = Val.getValueType();
519 if (PartVT == ValueVT)
522 if (PartVT.isVector()) {
523 assert(ValueVT.isVector() && "Unknown vector conversion!");
524 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
527 if (ValueVT.isVector()) {
528 assert(ValueVT.getVectorElementType() == PartVT &&
529 ValueVT.getVectorNumElements() == 1 &&
530 "Only trivial scalar-to-vector conversions should get here!");
531 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
534 if (PartVT.isInteger() &&
535 ValueVT.isInteger()) {
536 if (ValueVT.bitsLT(PartVT)) {
537 // For a truncate, see if we have any information to
538 // indicate whether the truncated bits will always be
539 // zero or sign-extension.
540 if (AssertOp != ISD::DELETED_NODE)
541 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
542 DAG.getValueType(ValueVT));
543 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
545 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
549 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
550 if (ValueVT.bitsLT(Val.getValueType()))
551 // FP_ROUND's are always exact here.
552 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
553 DAG.getIntPtrConstant(1));
554 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
557 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
558 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
560 llvm_unreachable("Unknown mismatch!");
564 /// getCopyToParts - Create a series of nodes that contain the specified value
565 /// split into legal parts. If the parts contain more bits than Val, then, for
566 /// integers, ExtendKind can be used to specify how to generate the extra bits.
567 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
568 SDValue *Parts, unsigned NumParts, EVT PartVT,
569 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
571 EVT PtrVT = TLI.getPointerTy();
572 EVT ValueVT = Val.getValueType();
573 unsigned PartBits = PartVT.getSizeInBits();
574 unsigned OrigNumParts = NumParts;
575 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
580 if (!ValueVT.isVector()) {
581 if (PartVT == ValueVT) {
582 assert(NumParts == 1 && "No-op copy with multiple parts!");
587 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
588 // If the parts cover more bits than the value has, promote the value.
589 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
590 assert(NumParts == 1 && "Do not know what to promote to!");
591 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
592 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
593 ValueVT = EVT::getIntegerVT(NumParts * PartBits);
594 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
596 llvm_unreachable("Unknown mismatch!");
598 } else if (PartBits == ValueVT.getSizeInBits()) {
599 // Different types of the same size.
600 assert(NumParts == 1 && PartVT != ValueVT);
601 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
602 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
603 // If the parts cover less bits than value has, truncate the value.
604 if (PartVT.isInteger() && ValueVT.isInteger()) {
605 ValueVT = EVT::getIntegerVT(NumParts * PartBits);
606 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
608 llvm_unreachable("Unknown mismatch!");
612 // The value may have changed - recompute ValueVT.
613 ValueVT = Val.getValueType();
614 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
615 "Failed to tile the value with PartVT!");
618 assert(PartVT == ValueVT && "Type conversion failed!");
623 // Expand the value into multiple parts.
624 if (NumParts & (NumParts - 1)) {
625 // The number of parts is not a power of 2. Split off and copy the tail.
626 assert(PartVT.isInteger() && ValueVT.isInteger() &&
627 "Do not know what to expand to!");
628 unsigned RoundParts = 1 << Log2_32(NumParts);
629 unsigned RoundBits = RoundParts * PartBits;
630 unsigned OddParts = NumParts - RoundParts;
631 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
632 DAG.getConstant(RoundBits,
633 TLI.getPointerTy()));
634 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
635 if (TLI.isBigEndian())
636 // The odd parts were reversed by getCopyToParts - unreverse them.
637 std::reverse(Parts + RoundParts, Parts + NumParts);
638 NumParts = RoundParts;
639 ValueVT = EVT::getIntegerVT(NumParts * PartBits);
640 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
643 // The number of parts is a power of 2. Repeatedly bisect the value using
645 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
646 EVT::getIntegerVT(ValueVT.getSizeInBits()),
648 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
649 for (unsigned i = 0; i < NumParts; i += StepSize) {
650 unsigned ThisBits = StepSize * PartBits / 2;
651 EVT ThisVT = EVT::getIntegerVT (ThisBits);
652 SDValue &Part0 = Parts[i];
653 SDValue &Part1 = Parts[i+StepSize/2];
655 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
657 DAG.getConstant(1, PtrVT));
658 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(0, PtrVT));
662 if (ThisBits == PartBits && ThisVT != PartVT) {
663 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
665 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
671 if (TLI.isBigEndian())
672 std::reverse(Parts, Parts + OrigNumParts);
679 if (PartVT != ValueVT) {
680 if (PartVT.isVector()) {
681 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
683 assert(ValueVT.getVectorElementType() == PartVT &&
684 ValueVT.getVectorNumElements() == 1 &&
685 "Only trivial vector-to-scalar conversions should get here!");
686 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
688 DAG.getConstant(0, PtrVT));
696 // Handle a multi-element vector.
697 EVT IntermediateVT, RegisterVT;
698 unsigned NumIntermediates;
699 unsigned NumRegs = TLI
700 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
702 unsigned NumElements = ValueVT.getVectorNumElements();
704 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
705 NumParts = NumRegs; // Silence a compiler warning.
706 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
708 // Split the vector into intermediate operands.
709 SmallVector<SDValue, 8> Ops(NumIntermediates);
710 for (unsigned i = 0; i != NumIntermediates; ++i)
711 if (IntermediateVT.isVector())
712 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
714 DAG.getConstant(i * (NumElements / NumIntermediates),
717 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
719 DAG.getConstant(i, PtrVT));
721 // Split the intermediate operands into legal parts.
722 if (NumParts == NumIntermediates) {
723 // If the register was not expanded, promote or copy the value,
725 for (unsigned i = 0; i != NumParts; ++i)
726 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
727 } else if (NumParts > 0) {
728 // If the intermediate type was expanded, split each the value into
730 assert(NumParts % NumIntermediates == 0 &&
731 "Must expand into a divisible number of parts!");
732 unsigned Factor = NumParts / NumIntermediates;
733 for (unsigned i = 0; i != NumIntermediates; ++i)
734 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
739 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
742 TD = DAG.getTarget().getTargetData();
745 /// clear - Clear out the curret SelectionDAG and the associated
746 /// state and prepare this SelectionDAGLowering object to be used
747 /// for a new block. This doesn't clear out information about
748 /// additional blocks that are needed to complete switch lowering
749 /// or PHI node updating; that information is cleared out as it is
751 void SelectionDAGLowering::clear() {
753 PendingLoads.clear();
754 PendingExports.clear();
756 CurDebugLoc = DebugLoc::getUnknownLoc();
760 /// getRoot - Return the current virtual root of the Selection DAG,
761 /// flushing any PendingLoad items. This must be done before emitting
762 /// a store or any other node that may need to be ordered after any
763 /// prior load instructions.
765 SDValue SelectionDAGLowering::getRoot() {
766 if (PendingLoads.empty())
767 return DAG.getRoot();
769 if (PendingLoads.size() == 1) {
770 SDValue Root = PendingLoads[0];
772 PendingLoads.clear();
776 // Otherwise, we have to make a token factor node.
777 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
778 &PendingLoads[0], PendingLoads.size());
779 PendingLoads.clear();
784 /// getControlRoot - Similar to getRoot, but instead of flushing all the
785 /// PendingLoad items, flush all the PendingExports items. It is necessary
786 /// to do this before emitting a terminator instruction.
788 SDValue SelectionDAGLowering::getControlRoot() {
789 SDValue Root = DAG.getRoot();
791 if (PendingExports.empty())
794 // Turn all of the CopyToReg chains into one factored node.
795 if (Root.getOpcode() != ISD::EntryToken) {
796 unsigned i = 0, e = PendingExports.size();
797 for (; i != e; ++i) {
798 assert(PendingExports[i].getNode()->getNumOperands() > 1);
799 if (PendingExports[i].getNode()->getOperand(0) == Root)
800 break; // Don't add the root if we already indirectly depend on it.
804 PendingExports.push_back(Root);
807 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
809 PendingExports.size());
810 PendingExports.clear();
815 void SelectionDAGLowering::visit(Instruction &I) {
816 visit(I.getOpcode(), I);
819 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
820 // Note: this doesn't use InstVisitor, because it has to work with
821 // ConstantExpr's in addition to instructions.
823 default: llvm_unreachable("Unknown instruction type encountered!");
824 // Build the switch statement using the Instruction.def file.
825 #define HANDLE_INST(NUM, OPCODE, CLASS) \
826 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
827 #include "llvm/Instruction.def"
831 SDValue SelectionDAGLowering::getValue(const Value *V) {
832 SDValue &N = NodeMap[V];
833 if (N.getNode()) return N;
835 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
836 EVT VT = TLI.getValueType(V->getType(), true);
838 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
839 return N = DAG.getConstant(*CI, VT);
841 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
842 return N = DAG.getGlobalAddress(GV, VT);
844 if (isa<ConstantPointerNull>(C))
845 return N = DAG.getConstant(0, TLI.getPointerTy());
847 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
848 return N = DAG.getConstantFP(*CFP, VT);
850 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
851 return N = DAG.getUNDEF(VT);
853 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
854 visit(CE->getOpcode(), *CE);
855 SDValue N1 = NodeMap[V];
856 assert(N1.getNode() && "visit didn't populate the ValueMap!");
860 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
861 SmallVector<SDValue, 4> Constants;
862 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
864 SDNode *Val = getValue(*OI).getNode();
865 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
866 Constants.push_back(SDValue(Val, i));
868 return DAG.getMergeValues(&Constants[0], Constants.size(),
872 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
873 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
874 "Unknown struct or array constant!");
876 SmallVector<EVT, 4> ValueVTs;
877 ComputeValueVTs(TLI, C->getType(), ValueVTs);
878 unsigned NumElts = ValueVTs.size();
880 return SDValue(); // empty struct
881 SmallVector<SDValue, 4> Constants(NumElts);
882 for (unsigned i = 0; i != NumElts; ++i) {
883 EVT EltVT = ValueVTs[i];
884 if (isa<UndefValue>(C))
885 Constants[i] = DAG.getUNDEF(EltVT);
886 else if (EltVT.isFloatingPoint())
887 Constants[i] = DAG.getConstantFP(0, EltVT);
889 Constants[i] = DAG.getConstant(0, EltVT);
891 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
894 const VectorType *VecTy = cast<VectorType>(V->getType());
895 unsigned NumElements = VecTy->getNumElements();
897 // Now that we know the number and type of the elements, get that number of
898 // elements into the Ops array based on what kind of constant it is.
899 SmallVector<SDValue, 16> Ops;
900 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
901 for (unsigned i = 0; i != NumElements; ++i)
902 Ops.push_back(getValue(CP->getOperand(i)));
904 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
905 EVT EltVT = TLI.getValueType(VecTy->getElementType());
908 if (EltVT.isFloatingPoint())
909 Op = DAG.getConstantFP(0, EltVT);
911 Op = DAG.getConstant(0, EltVT);
912 Ops.assign(NumElements, Op);
915 // Create a BUILD_VECTOR node.
916 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
917 VT, &Ops[0], Ops.size());
920 // If this is a static alloca, generate it as the frameindex instead of
922 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
923 DenseMap<const AllocaInst*, int>::iterator SI =
924 FuncInfo.StaticAllocaMap.find(AI);
925 if (SI != FuncInfo.StaticAllocaMap.end())
926 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
929 unsigned InReg = FuncInfo.ValueMap[V];
930 assert(InReg && "Value not in map!");
932 RegsForValue RFV(TLI, InReg, V->getType());
933 SDValue Chain = DAG.getEntryNode();
934 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
938 void SelectionDAGLowering::visitRet(ReturnInst &I) {
939 SDValue Chain = getControlRoot();
940 SmallVector<ISD::OutputArg, 8> Outs;
941 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
942 SmallVector<EVT, 4> ValueVTs;
943 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
944 unsigned NumValues = ValueVTs.size();
945 if (NumValues == 0) continue;
947 SDValue RetOp = getValue(I.getOperand(i));
948 for (unsigned j = 0, f = NumValues; j != f; ++j) {
949 EVT VT = ValueVTs[j];
951 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
953 const Function *F = I.getParent()->getParent();
954 if (F->paramHasAttr(0, Attribute::SExt))
955 ExtendKind = ISD::SIGN_EXTEND;
956 else if (F->paramHasAttr(0, Attribute::ZExt))
957 ExtendKind = ISD::ZERO_EXTEND;
959 // FIXME: C calling convention requires the return type to be promoted to
960 // at least 32-bit. But this is not necessary for non-C calling
961 // conventions. The frontend should mark functions whose return values
962 // require promoting with signext or zeroext attributes.
963 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
964 EVT MinVT = TLI.getRegisterType(EVT::i32);
965 if (VT.bitsLT(MinVT))
969 unsigned NumParts = TLI.getNumRegisters(VT);
970 EVT PartVT = TLI.getRegisterType(VT);
971 SmallVector<SDValue, 4> Parts(NumParts);
972 getCopyToParts(DAG, getCurDebugLoc(),
973 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
974 &Parts[0], NumParts, PartVT, ExtendKind);
976 // 'inreg' on function refers to return value
977 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
978 if (F->paramHasAttr(0, Attribute::InReg))
981 // Propagate extension type if any
982 if (F->paramHasAttr(0, Attribute::SExt))
984 else if (F->paramHasAttr(0, Attribute::ZExt))
987 for (unsigned i = 0; i < NumParts; ++i)
988 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
992 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
993 unsigned CallConv = DAG.getMachineFunction().getFunction()->getCallingConv();
994 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
995 Outs, getCurDebugLoc(), DAG);
997 // Verify that the target's LowerReturn behaved as expected.
998 assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
999 "LowerReturn didn't return a valid chain!");
1001 // Update the DAG with the new chain value resulting from return lowering.
1005 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1006 /// created for it, emit nodes to copy the value into the virtual
1008 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1009 if (!V->use_empty()) {
1010 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1011 if (VMI != FuncInfo.ValueMap.end())
1012 CopyValueToVirtualRegister(V, VMI->second);
1016 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1017 /// the current basic block, add it to ValueMap now so that we'll get a
1019 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1020 // No need to export constants.
1021 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1023 // Already exported?
1024 if (FuncInfo.isExportedInst(V)) return;
1026 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1027 CopyValueToVirtualRegister(V, Reg);
1030 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1031 const BasicBlock *FromBB) {
1032 // The operands of the setcc have to be in this block. We don't know
1033 // how to export them from some other block.
1034 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1035 // Can export from current BB.
1036 if (VI->getParent() == FromBB)
1039 // Is already exported, noop.
1040 return FuncInfo.isExportedInst(V);
1043 // If this is an argument, we can export it if the BB is the entry block or
1044 // if it is already exported.
1045 if (isa<Argument>(V)) {
1046 if (FromBB == &FromBB->getParent()->getEntryBlock())
1049 // Otherwise, can only export this if it is already exported.
1050 return FuncInfo.isExportedInst(V);
1053 // Otherwise, constants can always be exported.
1057 static bool InBlock(const Value *V, const BasicBlock *BB) {
1058 if (const Instruction *I = dyn_cast<Instruction>(V))
1059 return I->getParent() == BB;
1063 /// getFCmpCondCode - Return the ISD condition code corresponding to
1064 /// the given LLVM IR floating-point condition code. This includes
1065 /// consideration of global floating-point math flags.
1067 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1068 ISD::CondCode FPC, FOC;
1070 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1071 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1072 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1073 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1074 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1075 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1076 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1077 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1078 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1079 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1080 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1081 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1082 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1083 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1084 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1085 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1087 llvm_unreachable("Invalid FCmp predicate opcode!");
1088 FOC = FPC = ISD::SETFALSE;
1091 if (FiniteOnlyFPMath())
1097 /// getICmpCondCode - Return the ISD condition code corresponding to
1098 /// the given LLVM IR integer condition code.
1100 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1102 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1103 case ICmpInst::ICMP_NE: return ISD::SETNE;
1104 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1105 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1106 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1107 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1108 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1109 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1110 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1111 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1113 llvm_unreachable("Invalid ICmp predicate opcode!");
1118 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1119 /// This function emits a branch and is used at the leaves of an OR or an
1120 /// AND operator tree.
1123 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1124 MachineBasicBlock *TBB,
1125 MachineBasicBlock *FBB,
1126 MachineBasicBlock *CurBB) {
1127 const BasicBlock *BB = CurBB->getBasicBlock();
1129 // If the leaf of the tree is a comparison, merge the condition into
1131 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1132 // The operands of the cmp have to be in this block. We don't know
1133 // how to export them from some other block. If this is the first block
1134 // of the sequence, no exporting is needed.
1135 if (CurBB == CurMBB ||
1136 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1137 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1138 ISD::CondCode Condition;
1139 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1140 Condition = getICmpCondCode(IC->getPredicate());
1141 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1142 Condition = getFCmpCondCode(FC->getPredicate());
1144 Condition = ISD::SETEQ; // silence warning.
1145 llvm_unreachable("Unknown compare instruction");
1148 CaseBlock CB(Condition, BOp->getOperand(0),
1149 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1150 SwitchCases.push_back(CB);
1155 // Create a CaseBlock record representing this branch.
1156 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1157 NULL, TBB, FBB, CurBB);
1158 SwitchCases.push_back(CB);
1161 /// FindMergedConditions - If Cond is an expression like
1162 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1163 MachineBasicBlock *TBB,
1164 MachineBasicBlock *FBB,
1165 MachineBasicBlock *CurBB,
1167 // If this node is not part of the or/and tree, emit it as a branch.
1168 Instruction *BOp = dyn_cast<Instruction>(Cond);
1169 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1170 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1171 BOp->getParent() != CurBB->getBasicBlock() ||
1172 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1173 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1174 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1178 // Create TmpBB after CurBB.
1179 MachineFunction::iterator BBI = CurBB;
1180 MachineFunction &MF = DAG.getMachineFunction();
1181 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1182 CurBB->getParent()->insert(++BBI, TmpBB);
1184 if (Opc == Instruction::Or) {
1185 // Codegen X | Y as:
1193 // Emit the LHS condition.
1194 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1196 // Emit the RHS condition into TmpBB.
1197 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1199 assert(Opc == Instruction::And && "Unknown merge op!");
1200 // Codegen X & Y as:
1207 // This requires creation of TmpBB after CurBB.
1209 // Emit the LHS condition.
1210 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1212 // Emit the RHS condition into TmpBB.
1213 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1217 /// If the set of cases should be emitted as a series of branches, return true.
1218 /// If we should emit this as a bunch of and/or'd together conditions, return
1221 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1222 if (Cases.size() != 2) return true;
1224 // If this is two comparisons of the same values or'd or and'd together, they
1225 // will get folded into a single comparison, so don't emit two blocks.
1226 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1227 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1228 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1229 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1236 void SelectionDAGLowering::visitBr(BranchInst &I) {
1237 // Update machine-CFG edges.
1238 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1240 // Figure out which block is immediately after the current one.
1241 MachineBasicBlock *NextBlock = 0;
1242 MachineFunction::iterator BBI = CurMBB;
1243 if (++BBI != CurMBB->getParent()->end())
1246 if (I.isUnconditional()) {
1247 // Update machine-CFG edges.
1248 CurMBB->addSuccessor(Succ0MBB);
1250 // If this is not a fall-through branch, emit the branch.
1251 if (Succ0MBB != NextBlock)
1252 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1253 EVT::Other, getControlRoot(),
1254 DAG.getBasicBlock(Succ0MBB)));
1258 // If this condition is one of the special cases we handle, do special stuff
1260 Value *CondVal = I.getCondition();
1261 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1263 // If this is a series of conditions that are or'd or and'd together, emit
1264 // this as a sequence of branches instead of setcc's with and/or operations.
1265 // For example, instead of something like:
1278 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1279 if (BOp->hasOneUse() &&
1280 (BOp->getOpcode() == Instruction::And ||
1281 BOp->getOpcode() == Instruction::Or)) {
1282 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1283 // If the compares in later blocks need to use values not currently
1284 // exported from this block, export them now. This block should always
1285 // be the first entry.
1286 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1288 // Allow some cases to be rejected.
1289 if (ShouldEmitAsBranches(SwitchCases)) {
1290 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1291 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1292 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1295 // Emit the branch for this block.
1296 visitSwitchCase(SwitchCases[0]);
1297 SwitchCases.erase(SwitchCases.begin());
1301 // Okay, we decided not to do this, remove any inserted MBB's and clear
1303 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1304 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1306 SwitchCases.clear();
1310 // Create a CaseBlock record representing this branch.
1311 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1312 NULL, Succ0MBB, Succ1MBB, CurMBB);
1313 // Use visitSwitchCase to actually insert the fast branch sequence for this
1315 visitSwitchCase(CB);
1318 /// visitSwitchCase - Emits the necessary code to represent a single node in
1319 /// the binary search tree resulting from lowering a switch instruction.
1320 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1322 SDValue CondLHS = getValue(CB.CmpLHS);
1323 DebugLoc dl = getCurDebugLoc();
1325 // Build the setcc now.
1326 if (CB.CmpMHS == NULL) {
1327 // Fold "(X == true)" to X and "(X == false)" to !X to
1328 // handle common cases produced by branch lowering.
1329 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1330 CB.CC == ISD::SETEQ)
1332 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1333 CB.CC == ISD::SETEQ) {
1334 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1335 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1337 Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1339 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1341 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1342 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1344 SDValue CmpOp = getValue(CB.CmpMHS);
1345 EVT VT = CmpOp.getValueType();
1347 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1348 Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
1351 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1352 VT, CmpOp, DAG.getConstant(Low, VT));
1353 Cond = DAG.getSetCC(dl, EVT::i1, SUB,
1354 DAG.getConstant(High-Low, VT), ISD::SETULE);
1358 // Update successor info
1359 CurMBB->addSuccessor(CB.TrueBB);
1360 CurMBB->addSuccessor(CB.FalseBB);
1362 // Set NextBlock to be the MBB immediately after the current one, if any.
1363 // This is used to avoid emitting unnecessary branches to the next block.
1364 MachineBasicBlock *NextBlock = 0;
1365 MachineFunction::iterator BBI = CurMBB;
1366 if (++BBI != CurMBB->getParent()->end())
1369 // If the lhs block is the next block, invert the condition so that we can
1370 // fall through to the lhs instead of the rhs block.
1371 if (CB.TrueBB == NextBlock) {
1372 std::swap(CB.TrueBB, CB.FalseBB);
1373 SDValue True = DAG.getConstant(1, Cond.getValueType());
1374 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1376 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1377 EVT::Other, getControlRoot(), Cond,
1378 DAG.getBasicBlock(CB.TrueBB));
1380 // If the branch was constant folded, fix up the CFG.
1381 if (BrCond.getOpcode() == ISD::BR) {
1382 CurMBB->removeSuccessor(CB.FalseBB);
1383 DAG.setRoot(BrCond);
1385 // Otherwise, go ahead and insert the false branch.
1386 if (BrCond == getControlRoot())
1387 CurMBB->removeSuccessor(CB.TrueBB);
1389 if (CB.FalseBB == NextBlock)
1390 DAG.setRoot(BrCond);
1392 DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
1393 DAG.getBasicBlock(CB.FalseBB)));
1397 /// visitJumpTable - Emit JumpTable node in the current MBB
1398 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1399 // Emit the code for the jump table
1400 assert(JT.Reg != -1U && "Should lower JT Header first!");
1401 EVT PTy = TLI.getPointerTy();
1402 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1404 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1405 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1406 EVT::Other, Index.getValue(1),
1410 /// visitJumpTableHeader - This function emits necessary code to produce index
1411 /// in the JumpTable from switch case.
1412 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1413 JumpTableHeader &JTH) {
1414 // Subtract the lowest switch case value from the value being switched on and
1415 // conditional branch to default mbb if the result is greater than the
1416 // difference between smallest and largest cases.
1417 SDValue SwitchOp = getValue(JTH.SValue);
1418 EVT VT = SwitchOp.getValueType();
1419 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1420 DAG.getConstant(JTH.First, VT));
1422 // The SDNode we just created, which holds the value being switched on minus
1423 // the the smallest case value, needs to be copied to a virtual register so it
1424 // can be used as an index into the jump table in a subsequent basic block.
1425 // This value may be smaller or larger than the target's pointer type, and
1426 // therefore require extension or truncating.
1427 if (VT.bitsGT(TLI.getPointerTy()))
1428 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1429 TLI.getPointerTy(), SUB);
1431 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1432 TLI.getPointerTy(), SUB);
1434 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1435 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1436 JumpTableReg, SwitchOp);
1437 JT.Reg = JumpTableReg;
1439 // Emit the range check for the jump table, and branch to the default block
1440 // for the switch statement if the value being switched on exceeds the largest
1441 // case in the switch.
1442 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1443 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1444 DAG.getConstant(JTH.Last-JTH.First,VT),
1447 // Set NextBlock to be the MBB immediately after the current one, if any.
1448 // This is used to avoid emitting unnecessary branches to the next block.
1449 MachineBasicBlock *NextBlock = 0;
1450 MachineFunction::iterator BBI = CurMBB;
1451 if (++BBI != CurMBB->getParent()->end())
1454 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1455 EVT::Other, CopyTo, CMP,
1456 DAG.getBasicBlock(JT.Default));
1458 if (JT.MBB == NextBlock)
1459 DAG.setRoot(BrCond);
1461 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
1462 DAG.getBasicBlock(JT.MBB)));
1465 /// visitBitTestHeader - This function emits necessary code to produce value
1466 /// suitable for "bit tests"
1467 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1468 // Subtract the minimum value
1469 SDValue SwitchOp = getValue(B.SValue);
1470 EVT VT = SwitchOp.getValueType();
1471 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1472 DAG.getConstant(B.First, VT));
1475 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1476 TLI.getSetCCResultType(SUB.getValueType()),
1477 SUB, DAG.getConstant(B.Range, VT),
1481 if (VT.bitsGT(TLI.getPointerTy()))
1482 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1483 TLI.getPointerTy(), SUB);
1485 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1486 TLI.getPointerTy(), SUB);
1488 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1489 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1492 // Set NextBlock to be the MBB immediately after the current one, if any.
1493 // This is used to avoid emitting unnecessary branches to the next block.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CurMBB;
1496 if (++BBI != CurMBB->getParent()->end())
1499 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1501 CurMBB->addSuccessor(B.Default);
1502 CurMBB->addSuccessor(MBB);
1504 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1505 EVT::Other, CopyTo, RangeCmp,
1506 DAG.getBasicBlock(B.Default));
1508 if (MBB == NextBlock)
1509 DAG.setRoot(BrRange);
1511 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
1512 DAG.getBasicBlock(MBB)));
1515 /// visitBitTestCase - this function produces one "bit test"
1516 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1519 // Make desired shift
1520 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1521 TLI.getPointerTy());
1522 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1524 DAG.getConstant(1, TLI.getPointerTy()),
1527 // Emit bit tests and jumps
1528 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1529 TLI.getPointerTy(), SwitchVal,
1530 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1531 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1532 TLI.getSetCCResultType(AndOp.getValueType()),
1533 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1536 CurMBB->addSuccessor(B.TargetBB);
1537 CurMBB->addSuccessor(NextMBB);
1539 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1540 EVT::Other, getControlRoot(),
1541 AndCmp, DAG.getBasicBlock(B.TargetBB));
1543 // Set NextBlock to be the MBB immediately after the current one, if any.
1544 // This is used to avoid emitting unnecessary branches to the next block.
1545 MachineBasicBlock *NextBlock = 0;
1546 MachineFunction::iterator BBI = CurMBB;
1547 if (++BBI != CurMBB->getParent()->end())
1550 if (NextMBB == NextBlock)
1553 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
1554 DAG.getBasicBlock(NextMBB)));
1557 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1558 // Retrieve successors.
1559 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1560 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1562 const Value *Callee(I.getCalledValue());
1563 if (isa<InlineAsm>(Callee))
1566 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1568 // If the value of the invoke is used outside of its defining block, make it
1569 // available as a virtual register.
1570 CopyToExportRegsIfNeeded(&I);
1572 // Update successor info
1573 CurMBB->addSuccessor(Return);
1574 CurMBB->addSuccessor(LandingPad);
1576 // Drop into normal successor.
1577 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1578 EVT::Other, getControlRoot(),
1579 DAG.getBasicBlock(Return)));
1582 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1585 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1586 /// small case ranges).
1587 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1588 CaseRecVector& WorkList,
1590 MachineBasicBlock* Default) {
1591 Case& BackCase = *(CR.Range.second-1);
1593 // Size is the number of Cases represented by this range.
1594 size_t Size = CR.Range.second - CR.Range.first;
1598 // Get the MachineFunction which holds the current MBB. This is used when
1599 // inserting any additional MBBs necessary to represent the switch.
1600 MachineFunction *CurMF = CurMBB->getParent();
1602 // Figure out which block is immediately after the current one.
1603 MachineBasicBlock *NextBlock = 0;
1604 MachineFunction::iterator BBI = CR.CaseBB;
1606 if (++BBI != CurMBB->getParent()->end())
1609 // TODO: If any two of the cases has the same destination, and if one value
1610 // is the same as the other, but has one bit unset that the other has set,
1611 // use bit manipulation to do two compares at once. For example:
1612 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1614 // Rearrange the case blocks so that the last one falls through if possible.
1615 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1616 // The last case block won't fall through into 'NextBlock' if we emit the
1617 // branches in this order. See if rearranging a case value would help.
1618 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1619 if (I->BB == NextBlock) {
1620 std::swap(*I, BackCase);
1626 // Create a CaseBlock record representing a conditional branch to
1627 // the Case's target mbb if the value being switched on SV is equal
1629 MachineBasicBlock *CurBlock = CR.CaseBB;
1630 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1631 MachineBasicBlock *FallThrough;
1633 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1634 CurMF->insert(BBI, FallThrough);
1636 // Put SV in a virtual register to make it available from the new blocks.
1637 ExportFromCurrentBlock(SV);
1639 // If the last case doesn't match, go to the default block.
1640 FallThrough = Default;
1643 Value *RHS, *LHS, *MHS;
1645 if (I->High == I->Low) {
1646 // This is just small small case range :) containing exactly 1 case
1648 LHS = SV; RHS = I->High; MHS = NULL;
1651 LHS = I->Low; MHS = SV; RHS = I->High;
1653 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1655 // If emitting the first comparison, just call visitSwitchCase to emit the
1656 // code into the current block. Otherwise, push the CaseBlock onto the
1657 // vector to be later processed by SDISel, and insert the node's MBB
1658 // before the next MBB.
1659 if (CurBlock == CurMBB)
1660 visitSwitchCase(CB);
1662 SwitchCases.push_back(CB);
1664 CurBlock = FallThrough;
1670 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1671 return !DisableJumpTables &&
1672 (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
1673 TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
1676 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1677 APInt LastExt(Last), FirstExt(First);
1678 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1679 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1680 return (LastExt - FirstExt + 1ULL);
1683 /// handleJTSwitchCase - Emit jumptable for current switch case range
1684 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1685 CaseRecVector& WorkList,
1687 MachineBasicBlock* Default) {
1688 Case& FrontCase = *CR.Range.first;
1689 Case& BackCase = *(CR.Range.second-1);
1691 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1692 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1695 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1699 if (!areJTsAllowed(TLI) || TSize <= 3)
1702 APInt Range = ComputeRange(First, Last);
1703 double Density = (double)TSize / Range.roundToDouble();
1707 DEBUG(errs() << "Lowering jump table\n"
1708 << "First entry: " << First << ". Last entry: " << Last << '\n'
1709 << "Range: " << Range
1710 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1712 // Get the MachineFunction which holds the current MBB. This is used when
1713 // inserting any additional MBBs necessary to represent the switch.
1714 MachineFunction *CurMF = CurMBB->getParent();
1716 // Figure out which block is immediately after the current one.
1717 MachineBasicBlock *NextBlock = 0;
1718 MachineFunction::iterator BBI = CR.CaseBB;
1720 if (++BBI != CurMBB->getParent()->end())
1723 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1725 // Create a new basic block to hold the code for loading the address
1726 // of the jump table, and jumping to it. Update successor information;
1727 // we will either branch to the default case for the switch, or the jump
1729 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1730 CurMF->insert(BBI, JumpTableBB);
1731 CR.CaseBB->addSuccessor(Default);
1732 CR.CaseBB->addSuccessor(JumpTableBB);
1734 // Build a vector of destination BBs, corresponding to each target
1735 // of the jump table. If the value of the jump table slot corresponds to
1736 // a case statement, push the case's BB onto the vector, otherwise, push
1738 std::vector<MachineBasicBlock*> DestBBs;
1740 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1741 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1742 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1744 if (Low.sle(TEI) && TEI.sle(High)) {
1745 DestBBs.push_back(I->BB);
1749 DestBBs.push_back(Default);
1753 // Update successor info. Add one edge to each unique successor.
1754 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1755 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1756 E = DestBBs.end(); I != E; ++I) {
1757 if (!SuccsHandled[(*I)->getNumber()]) {
1758 SuccsHandled[(*I)->getNumber()] = true;
1759 JumpTableBB->addSuccessor(*I);
1763 // Create a jump table index for this jump table, or return an existing
1765 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1767 // Set the jump table information so that we can codegen it as a second
1768 // MachineBasicBlock
1769 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1770 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1771 if (CR.CaseBB == CurMBB)
1772 visitJumpTableHeader(JT, JTH);
1774 JTCases.push_back(JumpTableBlock(JTH, JT));
1779 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1781 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1782 CaseRecVector& WorkList,
1784 MachineBasicBlock* Default) {
1785 // Get the MachineFunction which holds the current MBB. This is used when
1786 // inserting any additional MBBs necessary to represent the switch.
1787 MachineFunction *CurMF = CurMBB->getParent();
1789 // Figure out which block is immediately after the current one.
1790 MachineBasicBlock *NextBlock = 0;
1791 MachineFunction::iterator BBI = CR.CaseBB;
1793 if (++BBI != CurMBB->getParent()->end())
1796 Case& FrontCase = *CR.Range.first;
1797 Case& BackCase = *(CR.Range.second-1);
1798 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1800 // Size is the number of Cases represented by this range.
1801 unsigned Size = CR.Range.second - CR.Range.first;
1803 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1804 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1806 CaseItr Pivot = CR.Range.first + Size/2;
1808 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1809 // (heuristically) allow us to emit JumpTable's later.
1811 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1815 size_t LSize = FrontCase.size();
1816 size_t RSize = TSize-LSize;
1817 DEBUG(errs() << "Selecting best pivot: \n"
1818 << "First: " << First << ", Last: " << Last <<'\n'
1819 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1820 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1822 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1823 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1824 APInt Range = ComputeRange(LEnd, RBegin);
1825 assert((Range - 2ULL).isNonNegative() &&
1826 "Invalid case distance");
1827 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1828 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1829 double Metric = Range.logBase2()*(LDensity+RDensity);
1830 // Should always split in some non-trivial place
1831 DEBUG(errs() <<"=>Step\n"
1832 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1833 << "LDensity: " << LDensity
1834 << ", RDensity: " << RDensity << '\n'
1835 << "Metric: " << Metric << '\n');
1836 if (FMetric < Metric) {
1839 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1845 if (areJTsAllowed(TLI)) {
1846 // If our case is dense we *really* should handle it earlier!
1847 assert((FMetric > 0) && "Should handle dense range earlier!");
1849 Pivot = CR.Range.first + Size/2;
1852 CaseRange LHSR(CR.Range.first, Pivot);
1853 CaseRange RHSR(Pivot, CR.Range.second);
1854 Constant *C = Pivot->Low;
1855 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1857 // We know that we branch to the LHS if the Value being switched on is
1858 // less than the Pivot value, C. We use this to optimize our binary
1859 // tree a bit, by recognizing that if SV is greater than or equal to the
1860 // LHS's Case Value, and that Case Value is exactly one less than the
1861 // Pivot's Value, then we can branch directly to the LHS's Target,
1862 // rather than creating a leaf node for it.
1863 if ((LHSR.second - LHSR.first) == 1 &&
1864 LHSR.first->High == CR.GE &&
1865 cast<ConstantInt>(C)->getValue() ==
1866 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1867 TrueBB = LHSR.first->BB;
1869 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1870 CurMF->insert(BBI, TrueBB);
1871 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1873 // Put SV in a virtual register to make it available from the new blocks.
1874 ExportFromCurrentBlock(SV);
1877 // Similar to the optimization above, if the Value being switched on is
1878 // known to be less than the Constant CR.LT, and the current Case Value
1879 // is CR.LT - 1, then we can branch directly to the target block for
1880 // the current Case Value, rather than emitting a RHS leaf node for it.
1881 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1882 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1883 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1884 FalseBB = RHSR.first->BB;
1886 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1887 CurMF->insert(BBI, FalseBB);
1888 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1890 // Put SV in a virtual register to make it available from the new blocks.
1891 ExportFromCurrentBlock(SV);
1894 // Create a CaseBlock record representing a conditional branch to
1895 // the LHS node if the value being switched on SV is less than C.
1896 // Otherwise, branch to LHS.
1897 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1899 if (CR.CaseBB == CurMBB)
1900 visitSwitchCase(CB);
1902 SwitchCases.push_back(CB);
1907 /// handleBitTestsSwitchCase - if current case range has few destination and
1908 /// range span less, than machine word bitwidth, encode case range into series
1909 /// of masks and emit bit tests with these masks.
1910 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1911 CaseRecVector& WorkList,
1913 MachineBasicBlock* Default){
1914 EVT PTy = TLI.getPointerTy();
1915 unsigned IntPtrBits = PTy.getSizeInBits();
1917 Case& FrontCase = *CR.Range.first;
1918 Case& BackCase = *(CR.Range.second-1);
1920 // Get the MachineFunction which holds the current MBB. This is used when
1921 // inserting any additional MBBs necessary to represent the switch.
1922 MachineFunction *CurMF = CurMBB->getParent();
1924 // If target does not have legal shift left, do not emit bit tests at all.
1925 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1929 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1931 // Single case counts one, case range - two.
1932 numCmps += (I->Low == I->High ? 1 : 2);
1935 // Count unique destinations
1936 SmallSet<MachineBasicBlock*, 4> Dests;
1937 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1938 Dests.insert(I->BB);
1939 if (Dests.size() > 3)
1940 // Don't bother the code below, if there are too much unique destinations
1943 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1944 << "Total number of comparisons: " << numCmps << '\n');
1946 // Compute span of values.
1947 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1948 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1949 APInt cmpRange = maxValue - minValue;
1951 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1952 << "Low bound: " << minValue << '\n'
1953 << "High bound: " << maxValue << '\n');
1955 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1956 (!(Dests.size() == 1 && numCmps >= 3) &&
1957 !(Dests.size() == 2 && numCmps >= 5) &&
1958 !(Dests.size() >= 3 && numCmps >= 6)))
1961 DEBUG(errs() << "Emitting bit tests\n");
1962 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1964 // Optimize the case where all the case values fit in a
1965 // word without having to subtract minValue. In this case,
1966 // we can optimize away the subtraction.
1967 if (minValue.isNonNegative() &&
1968 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1969 cmpRange = maxValue;
1971 lowBound = minValue;
1974 CaseBitsVector CasesBits;
1975 unsigned i, count = 0;
1977 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1978 MachineBasicBlock* Dest = I->BB;
1979 for (i = 0; i < count; ++i)
1980 if (Dest == CasesBits[i].BB)
1984 assert((count < 3) && "Too much destinations to test!");
1985 CasesBits.push_back(CaseBits(0, Dest, 0));
1989 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1990 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1992 uint64_t lo = (lowValue - lowBound).getZExtValue();
1993 uint64_t hi = (highValue - lowBound).getZExtValue();
1995 for (uint64_t j = lo; j <= hi; j++) {
1996 CasesBits[i].Mask |= 1ULL << j;
1997 CasesBits[i].Bits++;
2001 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2005 // Figure out which block is immediately after the current one.
2006 MachineFunction::iterator BBI = CR.CaseBB;
2009 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2011 DEBUG(errs() << "Cases:\n");
2012 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2013 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2014 << ", Bits: " << CasesBits[i].Bits
2015 << ", BB: " << CasesBits[i].BB << '\n');
2017 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2018 CurMF->insert(BBI, CaseBB);
2019 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2023 // Put SV in a virtual register to make it available from the new blocks.
2024 ExportFromCurrentBlock(SV);
2027 BitTestBlock BTB(lowBound, cmpRange, SV,
2028 -1U, (CR.CaseBB == CurMBB),
2029 CR.CaseBB, Default, BTC);
2031 if (CR.CaseBB == CurMBB)
2032 visitBitTestHeader(BTB);
2034 BitTestCases.push_back(BTB);
2040 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2041 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2042 const SwitchInst& SI) {
2045 // Start with "simple" cases
2046 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2047 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2048 Cases.push_back(Case(SI.getSuccessorValue(i),
2049 SI.getSuccessorValue(i),
2052 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2054 // Merge case into clusters
2055 if (Cases.size() >= 2)
2056 // Must recompute end() each iteration because it may be
2057 // invalidated by erase if we hold on to it
2058 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2059 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2060 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2061 MachineBasicBlock* nextBB = J->BB;
2062 MachineBasicBlock* currentBB = I->BB;
2064 // If the two neighboring cases go to the same destination, merge them
2065 // into a single case.
2066 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2074 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2075 if (I->Low != I->High)
2076 // A range counts double, since it requires two compares.
2083 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2084 // Figure out which block is immediately after the current one.
2085 MachineBasicBlock *NextBlock = 0;
2086 MachineFunction::iterator BBI = CurMBB;
2088 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2090 // If there is only the default destination, branch to it if it is not the
2091 // next basic block. Otherwise, just fall through.
2092 if (SI.getNumOperands() == 2) {
2093 // Update machine-CFG edges.
2095 // If this is not a fall-through branch, emit the branch.
2096 CurMBB->addSuccessor(Default);
2097 if (Default != NextBlock)
2098 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2099 EVT::Other, getControlRoot(),
2100 DAG.getBasicBlock(Default)));
2104 // If there are any non-default case statements, create a vector of Cases
2105 // representing each one, and sort the vector so that we can efficiently
2106 // create a binary search tree from them.
2108 size_t numCmps = Clusterify(Cases, SI);
2109 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2110 << ". Total compares: " << numCmps << '\n');
2113 // Get the Value to be switched on and default basic blocks, which will be
2114 // inserted into CaseBlock records, representing basic blocks in the binary
2116 Value *SV = SI.getOperand(0);
2118 // Push the initial CaseRec onto the worklist
2119 CaseRecVector WorkList;
2120 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2122 while (!WorkList.empty()) {
2123 // Grab a record representing a case range to process off the worklist
2124 CaseRec CR = WorkList.back();
2125 WorkList.pop_back();
2127 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2130 // If the range has few cases (two or less) emit a series of specific
2132 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2135 // If the switch has more than 5 blocks, and at least 40% dense, and the
2136 // target supports indirect branches, then emit a jump table rather than
2137 // lowering the switch to a binary tree of conditional branches.
2138 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2141 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2142 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2143 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2148 void SelectionDAGLowering::visitFSub(User &I) {
2149 // -0.0 - X --> fneg
2150 const Type *Ty = I.getType();
2151 if (isa<VectorType>(Ty)) {
2152 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2153 const VectorType *DestTy = cast<VectorType>(I.getType());
2154 const Type *ElTy = DestTy->getElementType();
2155 unsigned VL = DestTy->getNumElements();
2156 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2157 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2159 SDValue Op2 = getValue(I.getOperand(1));
2160 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2161 Op2.getValueType(), Op2));
2166 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2167 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2168 SDValue Op2 = getValue(I.getOperand(1));
2169 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2170 Op2.getValueType(), Op2));
2174 visitBinary(I, ISD::FSUB);
2177 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2178 SDValue Op1 = getValue(I.getOperand(0));
2179 SDValue Op2 = getValue(I.getOperand(1));
2181 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2182 Op1.getValueType(), Op1, Op2));
2185 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2186 SDValue Op1 = getValue(I.getOperand(0));
2187 SDValue Op2 = getValue(I.getOperand(1));
2188 if (!isa<VectorType>(I.getType()) &&
2189 Op2.getValueType() != TLI.getShiftAmountTy()) {
2190 // If the operand is smaller than the shift count type, promote it.
2191 EVT PTy = TLI.getPointerTy();
2192 EVT STy = TLI.getShiftAmountTy();
2193 if (STy.bitsGT(Op2.getValueType()))
2194 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2195 TLI.getShiftAmountTy(), Op2);
2196 // If the operand is larger than the shift count type but the shift
2197 // count type has enough bits to represent any shift value, truncate
2198 // it now. This is a common case and it exposes the truncate to
2199 // optimization early.
2200 else if (STy.getSizeInBits() >=
2201 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2202 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2203 TLI.getShiftAmountTy(), Op2);
2204 // Otherwise we'll need to temporarily settle for some other
2205 // convenient type; type legalization will make adjustments as
2207 else if (PTy.bitsLT(Op2.getValueType()))
2208 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2209 TLI.getPointerTy(), Op2);
2210 else if (PTy.bitsGT(Op2.getValueType()))
2211 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2212 TLI.getPointerTy(), Op2);
2215 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2216 Op1.getValueType(), Op1, Op2));
2219 void SelectionDAGLowering::visitICmp(User &I) {
2220 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2221 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2222 predicate = IC->getPredicate();
2223 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2224 predicate = ICmpInst::Predicate(IC->getPredicate());
2225 SDValue Op1 = getValue(I.getOperand(0));
2226 SDValue Op2 = getValue(I.getOperand(1));
2227 ISD::CondCode Opcode = getICmpCondCode(predicate);
2229 EVT DestVT = TLI.getValueType(I.getType());
2230 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2233 void SelectionDAGLowering::visitFCmp(User &I) {
2234 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2235 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2236 predicate = FC->getPredicate();
2237 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2238 predicate = FCmpInst::Predicate(FC->getPredicate());
2239 SDValue Op1 = getValue(I.getOperand(0));
2240 SDValue Op2 = getValue(I.getOperand(1));
2241 ISD::CondCode Condition = getFCmpCondCode(predicate);
2242 EVT DestVT = TLI.getValueType(I.getType());
2243 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2246 void SelectionDAGLowering::visitSelect(User &I) {
2247 SmallVector<EVT, 4> ValueVTs;
2248 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2249 unsigned NumValues = ValueVTs.size();
2250 if (NumValues != 0) {
2251 SmallVector<SDValue, 4> Values(NumValues);
2252 SDValue Cond = getValue(I.getOperand(0));
2253 SDValue TrueVal = getValue(I.getOperand(1));
2254 SDValue FalseVal = getValue(I.getOperand(2));
2256 for (unsigned i = 0; i != NumValues; ++i)
2257 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2258 TrueVal.getValueType(), Cond,
2259 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2260 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2262 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2263 DAG.getVTList(&ValueVTs[0], NumValues),
2264 &Values[0], NumValues));
2269 void SelectionDAGLowering::visitTrunc(User &I) {
2270 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2271 SDValue N = getValue(I.getOperand(0));
2272 EVT DestVT = TLI.getValueType(I.getType());
2273 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2276 void SelectionDAGLowering::visitZExt(User &I) {
2277 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2278 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2279 SDValue N = getValue(I.getOperand(0));
2280 EVT DestVT = TLI.getValueType(I.getType());
2281 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2284 void SelectionDAGLowering::visitSExt(User &I) {
2285 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2286 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2287 SDValue N = getValue(I.getOperand(0));
2288 EVT DestVT = TLI.getValueType(I.getType());
2289 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2292 void SelectionDAGLowering::visitFPTrunc(User &I) {
2293 // FPTrunc is never a no-op cast, no need to check
2294 SDValue N = getValue(I.getOperand(0));
2295 EVT DestVT = TLI.getValueType(I.getType());
2296 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2297 DestVT, N, DAG.getIntPtrConstant(0)));
2300 void SelectionDAGLowering::visitFPExt(User &I){
2301 // FPTrunc is never a no-op cast, no need to check
2302 SDValue N = getValue(I.getOperand(0));
2303 EVT DestVT = TLI.getValueType(I.getType());
2304 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2307 void SelectionDAGLowering::visitFPToUI(User &I) {
2308 // FPToUI is never a no-op cast, no need to check
2309 SDValue N = getValue(I.getOperand(0));
2310 EVT DestVT = TLI.getValueType(I.getType());
2311 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2314 void SelectionDAGLowering::visitFPToSI(User &I) {
2315 // FPToSI is never a no-op cast, no need to check
2316 SDValue N = getValue(I.getOperand(0));
2317 EVT DestVT = TLI.getValueType(I.getType());
2318 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2321 void SelectionDAGLowering::visitUIToFP(User &I) {
2322 // UIToFP is never a no-op cast, no need to check
2323 SDValue N = getValue(I.getOperand(0));
2324 EVT DestVT = TLI.getValueType(I.getType());
2325 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2328 void SelectionDAGLowering::visitSIToFP(User &I){
2329 // SIToFP is never a no-op cast, no need to check
2330 SDValue N = getValue(I.getOperand(0));
2331 EVT DestVT = TLI.getValueType(I.getType());
2332 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2335 void SelectionDAGLowering::visitPtrToInt(User &I) {
2336 // What to do depends on the size of the integer and the size of the pointer.
2337 // We can either truncate, zero extend, or no-op, accordingly.
2338 SDValue N = getValue(I.getOperand(0));
2339 EVT SrcVT = N.getValueType();
2340 EVT DestVT = TLI.getValueType(I.getType());
2342 if (DestVT.bitsLT(SrcVT))
2343 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2345 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2346 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2347 setValue(&I, Result);
2350 void SelectionDAGLowering::visitIntToPtr(User &I) {
2351 // What to do depends on the size of the integer and the size of the pointer.
2352 // We can either truncate, zero extend, or no-op, accordingly.
2353 SDValue N = getValue(I.getOperand(0));
2354 EVT SrcVT = N.getValueType();
2355 EVT DestVT = TLI.getValueType(I.getType());
2356 if (DestVT.bitsLT(SrcVT))
2357 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2359 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2360 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2364 void SelectionDAGLowering::visitBitCast(User &I) {
2365 SDValue N = getValue(I.getOperand(0));
2366 EVT DestVT = TLI.getValueType(I.getType());
2368 // BitCast assures us that source and destination are the same size so this
2369 // is either a BIT_CONVERT or a no-op.
2370 if (DestVT != N.getValueType())
2371 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2372 DestVT, N)); // convert types
2374 setValue(&I, N); // noop cast.
2377 void SelectionDAGLowering::visitInsertElement(User &I) {
2378 SDValue InVec = getValue(I.getOperand(0));
2379 SDValue InVal = getValue(I.getOperand(1));
2380 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2382 getValue(I.getOperand(2)));
2384 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2385 TLI.getValueType(I.getType()),
2386 InVec, InVal, InIdx));
2389 void SelectionDAGLowering::visitExtractElement(User &I) {
2390 SDValue InVec = getValue(I.getOperand(0));
2391 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2393 getValue(I.getOperand(1)));
2394 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2395 TLI.getValueType(I.getType()), InVec, InIdx));
2399 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2400 // from SIndx and increasing to the element length (undefs are allowed).
2401 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2402 unsigned MaskNumElts = Mask.size();
2403 for (unsigned i = 0; i != MaskNumElts; ++i)
2404 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2409 void SelectionDAGLowering::visitShuffleVector(User &I) {
2410 SmallVector<int, 8> Mask;
2411 SDValue Src1 = getValue(I.getOperand(0));
2412 SDValue Src2 = getValue(I.getOperand(1));
2414 // Convert the ConstantVector mask operand into an array of ints, with -1
2415 // representing undef values.
2416 SmallVector<Constant*, 8> MaskElts;
2417 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2419 unsigned MaskNumElts = MaskElts.size();
2420 for (unsigned i = 0; i != MaskNumElts; ++i) {
2421 if (isa<UndefValue>(MaskElts[i]))
2424 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2427 EVT VT = TLI.getValueType(I.getType());
2428 EVT SrcVT = Src1.getValueType();
2429 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2431 if (SrcNumElts == MaskNumElts) {
2432 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2437 // Normalize the shuffle vector since mask and vector length don't match.
2438 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2439 // Mask is longer than the source vectors and is a multiple of the source
2440 // vectors. We can use concatenate vector to make the mask and vectors
2442 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2443 // The shuffle is concatenating two vectors together.
2444 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2449 // Pad both vectors with undefs to make them the same length as the mask.
2450 unsigned NumConcat = MaskNumElts / SrcNumElts;
2451 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2452 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2453 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2455 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2456 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2460 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2461 getCurDebugLoc(), VT,
2462 &MOps1[0], NumConcat);
2463 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2464 getCurDebugLoc(), VT,
2465 &MOps2[0], NumConcat);
2467 // Readjust mask for new input vector length.
2468 SmallVector<int, 8> MappedOps;
2469 for (unsigned i = 0; i != MaskNumElts; ++i) {
2471 if (Idx < (int)SrcNumElts)
2472 MappedOps.push_back(Idx);
2474 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2476 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2481 if (SrcNumElts > MaskNumElts) {
2482 // Analyze the access pattern of the vector to see if we can extract
2483 // two subvectors and do the shuffle. The analysis is done by calculating
2484 // the range of elements the mask access on both vectors.
2485 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2486 int MaxRange[2] = {-1, -1};
2488 for (unsigned i = 0; i != MaskNumElts; ++i) {
2494 if (Idx >= (int)SrcNumElts) {
2498 if (Idx > MaxRange[Input])
2499 MaxRange[Input] = Idx;
2500 if (Idx < MinRange[Input])
2501 MinRange[Input] = Idx;
2504 // Check if the access is smaller than the vector size and can we find
2505 // a reasonable extract index.
2506 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2507 int StartIdx[2]; // StartIdx to extract from
2508 for (int Input=0; Input < 2; ++Input) {
2509 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2510 RangeUse[Input] = 0; // Unused
2511 StartIdx[Input] = 0;
2512 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2513 // Fits within range but we should see if we can find a good
2514 // start index that is a multiple of the mask length.
2515 if (MaxRange[Input] < (int)MaskNumElts) {
2516 RangeUse[Input] = 1; // Extract from beginning of the vector
2517 StartIdx[Input] = 0;
2519 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2520 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2521 StartIdx[Input] + MaskNumElts < SrcNumElts)
2522 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2527 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2528 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2531 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2532 // Extract appropriate subvector and generate a vector shuffle
2533 for (int Input=0; Input < 2; ++Input) {
2534 SDValue& Src = Input == 0 ? Src1 : Src2;
2535 if (RangeUse[Input] == 0) {
2536 Src = DAG.getUNDEF(VT);
2538 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2539 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2542 // Calculate new mask.
2543 SmallVector<int, 8> MappedOps;
2544 for (unsigned i = 0; i != MaskNumElts; ++i) {
2547 MappedOps.push_back(Idx);
2548 else if (Idx < (int)SrcNumElts)
2549 MappedOps.push_back(Idx - StartIdx[0]);
2551 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2553 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2559 // We can't use either concat vectors or extract subvectors so fall back to
2560 // replacing the shuffle with extract and build vector.
2561 // to insert and build vector.
2562 EVT EltVT = VT.getVectorElementType();
2563 EVT PtrVT = TLI.getPointerTy();
2564 SmallVector<SDValue,8> Ops;
2565 for (unsigned i = 0; i != MaskNumElts; ++i) {
2567 Ops.push_back(DAG.getUNDEF(EltVT));
2570 if (Idx < (int)SrcNumElts)
2571 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2572 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2574 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2576 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2579 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2580 VT, &Ops[0], Ops.size()));
2583 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2584 const Value *Op0 = I.getOperand(0);
2585 const Value *Op1 = I.getOperand(1);
2586 const Type *AggTy = I.getType();
2587 const Type *ValTy = Op1->getType();
2588 bool IntoUndef = isa<UndefValue>(Op0);
2589 bool FromUndef = isa<UndefValue>(Op1);
2591 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2592 I.idx_begin(), I.idx_end());
2594 SmallVector<EVT, 4> AggValueVTs;
2595 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2596 SmallVector<EVT, 4> ValValueVTs;
2597 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2599 unsigned NumAggValues = AggValueVTs.size();
2600 unsigned NumValValues = ValValueVTs.size();
2601 SmallVector<SDValue, 4> Values(NumAggValues);
2603 SDValue Agg = getValue(Op0);
2604 SDValue Val = getValue(Op1);
2606 // Copy the beginning value(s) from the original aggregate.
2607 for (; i != LinearIndex; ++i)
2608 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2609 SDValue(Agg.getNode(), Agg.getResNo() + i);
2610 // Copy values from the inserted value(s).
2611 for (; i != LinearIndex + NumValValues; ++i)
2612 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2613 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2614 // Copy remaining value(s) from the original aggregate.
2615 for (; i != NumAggValues; ++i)
2616 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2617 SDValue(Agg.getNode(), Agg.getResNo() + i);
2619 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2620 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2621 &Values[0], NumAggValues));
2624 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2625 const Value *Op0 = I.getOperand(0);
2626 const Type *AggTy = Op0->getType();
2627 const Type *ValTy = I.getType();
2628 bool OutOfUndef = isa<UndefValue>(Op0);
2630 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2631 I.idx_begin(), I.idx_end());
2633 SmallVector<EVT, 4> ValValueVTs;
2634 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2636 unsigned NumValValues = ValValueVTs.size();
2637 SmallVector<SDValue, 4> Values(NumValValues);
2639 SDValue Agg = getValue(Op0);
2640 // Copy out the selected value(s).
2641 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2642 Values[i - LinearIndex] =
2644 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2645 SDValue(Agg.getNode(), Agg.getResNo() + i);
2647 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2648 DAG.getVTList(&ValValueVTs[0], NumValValues),
2649 &Values[0], NumValValues));
2653 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2654 SDValue N = getValue(I.getOperand(0));
2655 const Type *Ty = I.getOperand(0)->getType();
2657 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2660 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2661 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2664 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2665 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2666 DAG.getIntPtrConstant(Offset));
2668 Ty = StTy->getElementType(Field);
2670 Ty = cast<SequentialType>(Ty)->getElementType();
2672 // If this is a constant subscript, handle it quickly.
2673 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2674 if (CI->getZExtValue() == 0) continue;
2676 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2678 EVT PTy = TLI.getPointerTy();
2679 unsigned PtrBits = PTy.getSizeInBits();
2681 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2683 DAG.getConstant(Offs, EVT::i64));
2685 OffsVal = DAG.getIntPtrConstant(Offs);
2686 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2691 // N = N + Idx * ElementSize;
2692 uint64_t ElementSize = TD->getTypeAllocSize(Ty);
2693 SDValue IdxN = getValue(Idx);
2695 // If the index is smaller or larger than intptr_t, truncate or extend
2697 if (IdxN.getValueType().bitsLT(N.getValueType()))
2698 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2699 N.getValueType(), IdxN);
2700 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2701 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2702 N.getValueType(), IdxN);
2704 // If this is a multiply by a power of two, turn it into a shl
2705 // immediately. This is a very common case.
2706 if (ElementSize != 1) {
2707 if (isPowerOf2_64(ElementSize)) {
2708 unsigned Amt = Log2_64(ElementSize);
2709 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2710 N.getValueType(), IdxN,
2711 DAG.getConstant(Amt, TLI.getPointerTy()));
2713 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2714 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2715 N.getValueType(), IdxN, Scale);
2719 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2720 N.getValueType(), N, IdxN);
2726 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2727 // If this is a fixed sized alloca in the entry block of the function,
2728 // allocate it statically on the stack.
2729 if (FuncInfo.StaticAllocaMap.count(&I))
2730 return; // getValue will auto-populate this.
2732 const Type *Ty = I.getAllocatedType();
2733 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2735 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2738 SDValue AllocSize = getValue(I.getArraySize());
2740 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2742 DAG.getConstant(TySize, AllocSize.getValueType()));
2746 EVT IntPtr = TLI.getPointerTy();
2747 if (IntPtr.bitsLT(AllocSize.getValueType()))
2748 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2750 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2751 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2754 // Handle alignment. If the requested alignment is less than or equal to
2755 // the stack alignment, ignore it. If the size is greater than or equal to
2756 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2757 unsigned StackAlign =
2758 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2759 if (Align <= StackAlign)
2762 // Round the size of the allocation up to the stack alignment size
2763 // by add SA-1 to the size.
2764 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2765 AllocSize.getValueType(), AllocSize,
2766 DAG.getIntPtrConstant(StackAlign-1));
2767 // Mask out the low bits for alignment purposes.
2768 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2769 AllocSize.getValueType(), AllocSize,
2770 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2772 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2773 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
2774 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2777 DAG.setRoot(DSA.getValue(1));
2779 // Inform the Frame Information that we have just allocated a variable-sized
2781 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2784 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2785 const Value *SV = I.getOperand(0);
2786 SDValue Ptr = getValue(SV);
2788 const Type *Ty = I.getType();
2789 bool isVolatile = I.isVolatile();
2790 unsigned Alignment = I.getAlignment();
2792 SmallVector<EVT, 4> ValueVTs;
2793 SmallVector<uint64_t, 4> Offsets;
2794 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2795 unsigned NumValues = ValueVTs.size();
2800 bool ConstantMemory = false;
2802 // Serialize volatile loads with other side effects.
2804 else if (AA->pointsToConstantMemory(SV)) {
2805 // Do not serialize (non-volatile) loads of constant memory with anything.
2806 Root = DAG.getEntryNode();
2807 ConstantMemory = true;
2809 // Do not serialize non-volatile loads against each other.
2810 Root = DAG.getRoot();
2813 SmallVector<SDValue, 4> Values(NumValues);
2814 SmallVector<SDValue, 4> Chains(NumValues);
2815 EVT PtrVT = Ptr.getValueType();
2816 for (unsigned i = 0; i != NumValues; ++i) {
2817 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2818 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2820 DAG.getConstant(Offsets[i], PtrVT)),
2822 isVolatile, Alignment);
2824 Chains[i] = L.getValue(1);
2827 if (!ConstantMemory) {
2828 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2830 &Chains[0], NumValues);
2834 PendingLoads.push_back(Chain);
2837 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2838 DAG.getVTList(&ValueVTs[0], NumValues),
2839 &Values[0], NumValues));
2843 void SelectionDAGLowering::visitStore(StoreInst &I) {
2844 Value *SrcV = I.getOperand(0);
2845 Value *PtrV = I.getOperand(1);
2847 SmallVector<EVT, 4> ValueVTs;
2848 SmallVector<uint64_t, 4> Offsets;
2849 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2850 unsigned NumValues = ValueVTs.size();
2854 // Get the lowered operands. Note that we do this after
2855 // checking if NumResults is zero, because with zero results
2856 // the operands won't have values in the map.
2857 SDValue Src = getValue(SrcV);
2858 SDValue Ptr = getValue(PtrV);
2860 SDValue Root = getRoot();
2861 SmallVector<SDValue, 4> Chains(NumValues);
2862 EVT PtrVT = Ptr.getValueType();
2863 bool isVolatile = I.isVolatile();
2864 unsigned Alignment = I.getAlignment();
2865 for (unsigned i = 0; i != NumValues; ++i)
2866 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2867 SDValue(Src.getNode(), Src.getResNo() + i),
2868 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2870 DAG.getConstant(Offsets[i], PtrVT)),
2872 isVolatile, Alignment);
2874 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2875 EVT::Other, &Chains[0], NumValues));
2878 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2880 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2881 unsigned Intrinsic) {
2882 bool HasChain = !I.doesNotAccessMemory();
2883 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2885 // Build the operand list.
2886 SmallVector<SDValue, 8> Ops;
2887 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2889 // We don't need to serialize loads against other loads.
2890 Ops.push_back(DAG.getRoot());
2892 Ops.push_back(getRoot());
2896 // Info is set by getTgtMemInstrinsic
2897 TargetLowering::IntrinsicInfo Info;
2898 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2900 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2901 if (!IsTgtIntrinsic)
2902 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2904 // Add all operands of the call to the operand list.
2905 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2906 SDValue Op = getValue(I.getOperand(i));
2907 assert(TLI.isTypeLegal(Op.getValueType()) &&
2908 "Intrinsic uses a non-legal type?");
2912 SmallVector<EVT, 4> ValueVTs;
2913 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2915 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2916 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2917 "Intrinsic uses a non-legal type?");
2921 ValueVTs.push_back(EVT::Other);
2923 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2927 if (IsTgtIntrinsic) {
2928 // This is target intrinsic that touches memory
2929 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2930 VTs, &Ops[0], Ops.size(),
2931 Info.memVT, Info.ptrVal, Info.offset,
2932 Info.align, Info.vol,
2933 Info.readMem, Info.writeMem);
2936 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2937 VTs, &Ops[0], Ops.size());
2938 else if (I.getType() != Type::VoidTy)
2939 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2940 VTs, &Ops[0], Ops.size());
2942 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2943 VTs, &Ops[0], Ops.size());
2946 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2948 PendingLoads.push_back(Chain);
2952 if (I.getType() != Type::VoidTy) {
2953 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2954 EVT VT = TLI.getValueType(PTy);
2955 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2957 setValue(&I, Result);
2961 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2962 static GlobalVariable *ExtractTypeInfo(Value *V) {
2963 V = V->stripPointerCasts();
2964 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2965 assert ((GV || isa<ConstantPointerNull>(V)) &&
2966 "TypeInfo must be a global variable or NULL");
2972 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2973 /// call, and add them to the specified machine basic block.
2974 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2975 MachineBasicBlock *MBB) {
2976 // Inform the MachineModuleInfo of the personality for this landing pad.
2977 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2978 assert(CE->getOpcode() == Instruction::BitCast &&
2979 isa<Function>(CE->getOperand(0)) &&
2980 "Personality should be a function");
2981 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2983 // Gather all the type infos for this landing pad and pass them along to
2984 // MachineModuleInfo.
2985 std::vector<GlobalVariable *> TyInfo;
2986 unsigned N = I.getNumOperands();
2988 for (unsigned i = N - 1; i > 2; --i) {
2989 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2990 unsigned FilterLength = CI->getZExtValue();
2991 unsigned FirstCatch = i + FilterLength + !FilterLength;
2992 assert (FirstCatch <= N && "Invalid filter length");
2994 if (FirstCatch < N) {
2995 TyInfo.reserve(N - FirstCatch);
2996 for (unsigned j = FirstCatch; j < N; ++j)
2997 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2998 MMI->addCatchTypeInfo(MBB, TyInfo);
3002 if (!FilterLength) {
3004 MMI->addCleanup(MBB);
3007 TyInfo.reserve(FilterLength - 1);
3008 for (unsigned j = i + 1; j < FirstCatch; ++j)
3009 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3010 MMI->addFilterTypeInfo(MBB, TyInfo);
3019 TyInfo.reserve(N - 3);
3020 for (unsigned j = 3; j < N; ++j)
3021 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3022 MMI->addCatchTypeInfo(MBB, TyInfo);
3028 /// GetSignificand - Get the significand and build it into a floating-point
3029 /// number with exponent of 1:
3031 /// Op = (Op & 0x007fffff) | 0x3f800000;
3033 /// where Op is the hexidecimal representation of floating point value.
3035 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3036 SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
3037 DAG.getConstant(0x007fffff, EVT::i32));
3038 SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
3039 DAG.getConstant(0x3f800000, EVT::i32));
3040 return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
3043 /// GetExponent - Get the exponent:
3045 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3047 /// where Op is the hexidecimal representation of floating point value.
3049 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3051 SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
3052 DAG.getConstant(0x7f800000, EVT::i32));
3053 SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
3054 DAG.getConstant(23, TLI.getPointerTy()));
3055 SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
3056 DAG.getConstant(127, EVT::i32));
3057 return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
3060 /// getF32Constant - Get 32-bit floating point constant.
3062 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3063 return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
3066 /// Inlined utility function to implement binary input atomic intrinsics for
3067 /// visitIntrinsicCall: I is a call instruction
3068 /// Op is the associated NodeType for I
3070 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3071 SDValue Root = getRoot();
3073 DAG.getAtomic(Op, getCurDebugLoc(),
3074 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3076 getValue(I.getOperand(1)),
3077 getValue(I.getOperand(2)),
3080 DAG.setRoot(L.getValue(1));
3084 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3086 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3087 SDValue Op1 = getValue(I.getOperand(1));
3088 SDValue Op2 = getValue(I.getOperand(2));
3090 SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
3091 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3093 setValue(&I, Result);
3097 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3098 /// limited-precision mode.
3100 SelectionDAGLowering::visitExp(CallInst &I) {
3102 DebugLoc dl = getCurDebugLoc();
3104 if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
3105 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3106 SDValue Op = getValue(I.getOperand(1));
3108 // Put the exponent in the right bit position for later addition to the
3111 // #define LOG2OFe 1.4426950f
3112 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3113 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
3114 getF32Constant(DAG, 0x3fb8aa3b));
3115 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
3117 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3118 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
3119 SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
3121 // IntegerPartOfX <<= 23;
3122 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
3123 DAG.getConstant(23, TLI.getPointerTy()));
3125 if (LimitFloatPrecision <= 6) {
3126 // For floating-point precision of 6:
3128 // TwoToFractionalPartOfX =
3130 // (0.735607626f + 0.252464424f * x) * x;
3132 // error 0.0144103317, which is 6 bits
3133 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3134 getF32Constant(DAG, 0x3e814304));
3135 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3136 getF32Constant(DAG, 0x3f3c50c8));
3137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3138 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3139 getF32Constant(DAG, 0x3f7f5e7e));
3140 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
3142 // Add the exponent into the result in integer domain.
3143 SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
3144 TwoToFracPartOfX, IntegerPartOfX);
3146 result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
3147 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3148 // For floating-point precision of 12:
3150 // TwoToFractionalPartOfX =
3153 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3155 // 0.000107046256 error, which is 13 to 14 bits
3156 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3157 getF32Constant(DAG, 0x3da235e3));
3158 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3159 getF32Constant(DAG, 0x3e65b8f3));
3160 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3161 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3162 getF32Constant(DAG, 0x3f324b07));
3163 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3164 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3165 getF32Constant(DAG, 0x3f7ff8fd));
3166 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
3168 // Add the exponent into the result in integer domain.
3169 SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
3170 TwoToFracPartOfX, IntegerPartOfX);
3172 result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
3173 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3174 // For floating-point precision of 18:
3176 // TwoToFractionalPartOfX =
3180 // (0.554906021e-1f +
3181 // (0.961591928e-2f +
3182 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3184 // error 2.47208000*10^(-7), which is better than 18 bits
3185 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3186 getF32Constant(DAG, 0x3924b03e));
3187 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3188 getF32Constant(DAG, 0x3ab24b87));
3189 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3190 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3191 getF32Constant(DAG, 0x3c1d8c17));
3192 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3193 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3194 getF32Constant(DAG, 0x3d634a1d));
3195 SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
3196 SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
3197 getF32Constant(DAG, 0x3e75fe14));
3198 SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
3199 SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
3200 getF32Constant(DAG, 0x3f317234));
3201 SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
3202 SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
3203 getF32Constant(DAG, 0x3f800000));
3204 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3207 // Add the exponent into the result in integer domain.
3208 SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
3209 TwoToFracPartOfX, IntegerPartOfX);
3211 result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
3214 // No special expansion.
3215 result = DAG.getNode(ISD::FEXP, dl,
3216 getValue(I.getOperand(1)).getValueType(),
3217 getValue(I.getOperand(1)));
3220 setValue(&I, result);
3223 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3224 /// limited-precision mode.
3226 SelectionDAGLowering::visitLog(CallInst &I) {
3228 DebugLoc dl = getCurDebugLoc();
3230 if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
3231 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3232 SDValue Op = getValue(I.getOperand(1));
3233 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
3235 // Scale the exponent by log(2) [0.69314718f].
3236 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3237 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
3238 getF32Constant(DAG, 0x3f317218));
3240 // Get the significand and build it into a floating-point number with
3242 SDValue X = GetSignificand(DAG, Op1, dl);
3244 if (LimitFloatPrecision <= 6) {
3245 // For floating-point precision of 6:
3249 // (1.4034025f - 0.23903021f * x) * x;
3251 // error 0.0034276066, which is better than 8 bits
3252 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3253 getF32Constant(DAG, 0xbe74c456));
3254 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3255 getF32Constant(DAG, 0x3fb3a2b1));
3256 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3257 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3258 getF32Constant(DAG, 0x3f949a29));
3260 result = DAG.getNode(ISD::FADD, dl,
3261 EVT::f32, LogOfExponent, LogOfMantissa);
3262 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3263 // For floating-point precision of 12:
3269 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3271 // error 0.000061011436, which is 14 bits
3272 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3273 getF32Constant(DAG, 0xbd67b6d6));
3274 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3275 getF32Constant(DAG, 0x3ee4f4b8));
3276 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3277 SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3278 getF32Constant(DAG, 0x3fbc278b));
3279 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3280 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3281 getF32Constant(DAG, 0x40348e95));
3282 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3283 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
3284 getF32Constant(DAG, 0x3fdef31a));
3286 result = DAG.getNode(ISD::FADD, dl,
3287 EVT::f32, LogOfExponent, LogOfMantissa);
3288 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3289 // For floating-point precision of 18:
3297 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3299 // error 0.0000023660568, which is better than 18 bits
3300 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3301 getF32Constant(DAG, 0xbc91e5ac));
3302 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3303 getF32Constant(DAG, 0x3e4350aa));
3304 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3305 SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3306 getF32Constant(DAG, 0x3f60d3e3));
3307 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3308 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3309 getF32Constant(DAG, 0x4011cdf0));
3310 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3311 SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
3312 getF32Constant(DAG, 0x406cfd1c));
3313 SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
3314 SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
3315 getF32Constant(DAG, 0x408797cb));
3316 SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
3317 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
3318 getF32Constant(DAG, 0x4006dcab));
3320 result = DAG.getNode(ISD::FADD, dl,
3321 EVT::f32, LogOfExponent, LogOfMantissa);
3324 // No special expansion.
3325 result = DAG.getNode(ISD::FLOG, dl,
3326 getValue(I.getOperand(1)).getValueType(),
3327 getValue(I.getOperand(1)));
3330 setValue(&I, result);
3333 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3334 /// limited-precision mode.
3336 SelectionDAGLowering::visitLog2(CallInst &I) {
3338 DebugLoc dl = getCurDebugLoc();
3340 if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
3341 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3342 SDValue Op = getValue(I.getOperand(1));
3343 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
3345 // Get the exponent.
3346 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3348 // Get the significand and build it into a floating-point number with
3350 SDValue X = GetSignificand(DAG, Op1, dl);
3352 // Different possible minimax approximations of significand in
3353 // floating-point for various degrees of accuracy over [1,2].
3354 if (LimitFloatPrecision <= 6) {
3355 // For floating-point precision of 6:
3357 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3359 // error 0.0049451742, which is more than 7 bits
3360 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3361 getF32Constant(DAG, 0xbeb08fe0));
3362 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3363 getF32Constant(DAG, 0x40019463));
3364 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3365 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3366 getF32Constant(DAG, 0x3fd6633d));
3368 result = DAG.getNode(ISD::FADD, dl,
3369 EVT::f32, LogOfExponent, Log2ofMantissa);
3370 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3371 // For floating-point precision of 12:
3377 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3379 // error 0.0000876136000, which is better than 13 bits
3380 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3381 getF32Constant(DAG, 0xbda7262e));
3382 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3383 getF32Constant(DAG, 0x3f25280b));
3384 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3385 SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3386 getF32Constant(DAG, 0x4007b923));
3387 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3388 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3389 getF32Constant(DAG, 0x40823e2f));
3390 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3391 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
3392 getF32Constant(DAG, 0x4020d29c));
3394 result = DAG.getNode(ISD::FADD, dl,
3395 EVT::f32, LogOfExponent, Log2ofMantissa);
3396 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3397 // For floating-point precision of 18:
3406 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3408 // error 0.0000018516, which is better than 18 bits
3409 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3410 getF32Constant(DAG, 0xbcd2769e));
3411 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3412 getF32Constant(DAG, 0x3e8ce0b9));
3413 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3414 SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3415 getF32Constant(DAG, 0x3fa22ae7));
3416 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3417 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3418 getF32Constant(DAG, 0x40525723));
3419 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3420 SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
3421 getF32Constant(DAG, 0x40aaf200));
3422 SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
3423 SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
3424 getF32Constant(DAG, 0x40c39dad));
3425 SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
3426 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
3427 getF32Constant(DAG, 0x4042902c));
3429 result = DAG.getNode(ISD::FADD, dl,
3430 EVT::f32, LogOfExponent, Log2ofMantissa);
3433 // No special expansion.
3434 result = DAG.getNode(ISD::FLOG2, dl,
3435 getValue(I.getOperand(1)).getValueType(),
3436 getValue(I.getOperand(1)));
3439 setValue(&I, result);
3442 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3443 /// limited-precision mode.
3445 SelectionDAGLowering::visitLog10(CallInst &I) {
3447 DebugLoc dl = getCurDebugLoc();
3449 if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
3450 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3451 SDValue Op = getValue(I.getOperand(1));
3452 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
3454 // Scale the exponent by log10(2) [0.30102999f].
3455 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3456 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
3457 getF32Constant(DAG, 0x3e9a209a));
3459 // Get the significand and build it into a floating-point number with
3461 SDValue X = GetSignificand(DAG, Op1, dl);
3463 if (LimitFloatPrecision <= 6) {
3464 // For floating-point precision of 6:
3466 // Log10ofMantissa =
3468 // (0.60948995f - 0.10380950f * x) * x;
3470 // error 0.0014886165, which is 6 bits
3471 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3472 getF32Constant(DAG, 0xbdd49a13));
3473 SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
3474 getF32Constant(DAG, 0x3f1c0789));
3475 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3476 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
3477 getF32Constant(DAG, 0x3f011300));
3479 result = DAG.getNode(ISD::FADD, dl,
3480 EVT::f32, LogOfExponent, Log10ofMantissa);
3481 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3482 // For floating-point precision of 12:
3484 // Log10ofMantissa =
3487 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3489 // error 0.00019228036, which is better than 12 bits
3490 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3491 getF32Constant(DAG, 0x3d431f31));
3492 SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
3493 getF32Constant(DAG, 0x3ea21fb2));
3494 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3495 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3496 getF32Constant(DAG, 0x3f6ae232));
3497 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3498 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
3499 getF32Constant(DAG, 0x3f25f7c3));
3501 result = DAG.getNode(ISD::FADD, dl,
3502 EVT::f32, LogOfExponent, Log10ofMantissa);
3503 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3504 // For floating-point precision of 18:
3506 // Log10ofMantissa =
3511 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3513 // error 0.0000037995730, which is better than 18 bits
3514 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3515 getF32Constant(DAG, 0x3c5d51ce));
3516 SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
3517 getF32Constant(DAG, 0x3e00685a));
3518 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
3519 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3520 getF32Constant(DAG, 0x3efb6798));
3521 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3522 SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
3523 getF32Constant(DAG, 0x3f88d192));
3524 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3525 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3526 getF32Constant(DAG, 0x3fc4316c));
3527 SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
3528 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
3529 getF32Constant(DAG, 0x3f57ce70));
3531 result = DAG.getNode(ISD::FADD, dl,
3532 EVT::f32, LogOfExponent, Log10ofMantissa);
3535 // No special expansion.
3536 result = DAG.getNode(ISD::FLOG10, dl,
3537 getValue(I.getOperand(1)).getValueType(),
3538 getValue(I.getOperand(1)));
3541 setValue(&I, result);
3544 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3545 /// limited-precision mode.
3547 SelectionDAGLowering::visitExp2(CallInst &I) {
3549 DebugLoc dl = getCurDebugLoc();
3551 if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
3552 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3553 SDValue Op = getValue(I.getOperand(1));
3555 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
3557 // FractionalPartOfX = x - (float)IntegerPartOfX;
3558 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
3559 SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
3561 // IntegerPartOfX <<= 23;
3562 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
3563 DAG.getConstant(23, TLI.getPointerTy()));
3565 if (LimitFloatPrecision <= 6) {
3566 // For floating-point precision of 6:
3568 // TwoToFractionalPartOfX =
3570 // (0.735607626f + 0.252464424f * x) * x;
3572 // error 0.0144103317, which is 6 bits
3573 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3574 getF32Constant(DAG, 0x3e814304));
3575 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3576 getF32Constant(DAG, 0x3f3c50c8));
3577 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3578 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3579 getF32Constant(DAG, 0x3f7f5e7e));
3580 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
3581 SDValue TwoToFractionalPartOfX =
3582 DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
3584 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3585 EVT::f32, TwoToFractionalPartOfX);
3586 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3587 // For floating-point precision of 12:
3589 // TwoToFractionalPartOfX =
3592 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3594 // error 0.000107046256, which is 13 to 14 bits
3595 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3596 getF32Constant(DAG, 0x3da235e3));
3597 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3598 getF32Constant(DAG, 0x3e65b8f3));
3599 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3600 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3601 getF32Constant(DAG, 0x3f324b07));
3602 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3603 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3604 getF32Constant(DAG, 0x3f7ff8fd));
3605 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
3606 SDValue TwoToFractionalPartOfX =
3607 DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
3609 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3610 EVT::f32, TwoToFractionalPartOfX);
3611 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3612 // For floating-point precision of 18:
3614 // TwoToFractionalPartOfX =
3618 // (0.554906021e-1f +
3619 // (0.961591928e-2f +
3620 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3621 // error 2.47208000*10^(-7), which is better than 18 bits
3622 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3623 getF32Constant(DAG, 0x3924b03e));
3624 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3625 getF32Constant(DAG, 0x3ab24b87));
3626 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3627 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3628 getF32Constant(DAG, 0x3c1d8c17));
3629 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3630 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3631 getF32Constant(DAG, 0x3d634a1d));
3632 SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
3633 SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
3634 getF32Constant(DAG, 0x3e75fe14));
3635 SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
3636 SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
3637 getF32Constant(DAG, 0x3f317234));
3638 SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
3639 SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
3640 getF32Constant(DAG, 0x3f800000));
3641 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
3642 SDValue TwoToFractionalPartOfX =
3643 DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
3645 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3646 EVT::f32, TwoToFractionalPartOfX);
3649 // No special expansion.
3650 result = DAG.getNode(ISD::FEXP2, dl,
3651 getValue(I.getOperand(1)).getValueType(),
3652 getValue(I.getOperand(1)));
3655 setValue(&I, result);
3658 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3659 /// limited-precision mode with x == 10.0f.
3661 SelectionDAGLowering::visitPow(CallInst &I) {
3663 Value *Val = I.getOperand(1);
3664 DebugLoc dl = getCurDebugLoc();
3665 bool IsExp10 = false;
3667 if (getValue(Val).getValueType() == EVT::f32 &&
3668 getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
3669 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3670 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3671 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3673 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3678 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3679 SDValue Op = getValue(I.getOperand(2));
3681 // Put the exponent in the right bit position for later addition to the
3684 // #define LOG2OF10 3.3219281f
3685 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3686 SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
3687 getF32Constant(DAG, 0x40549a78));
3688 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
3690 // FractionalPartOfX = x - (float)IntegerPartOfX;
3691 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
3692 SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
3694 // IntegerPartOfX <<= 23;
3695 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
3696 DAG.getConstant(23, TLI.getPointerTy()));
3698 if (LimitFloatPrecision <= 6) {
3699 // For floating-point precision of 6:
3701 // twoToFractionalPartOfX =
3703 // (0.735607626f + 0.252464424f * x) * x;
3705 // error 0.0144103317, which is 6 bits
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3707 getF32Constant(DAG, 0x3e814304));
3708 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3709 getF32Constant(DAG, 0x3f3c50c8));
3710 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3711 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3712 getF32Constant(DAG, 0x3f7f5e7e));
3713 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
3714 SDValue TwoToFractionalPartOfX =
3715 DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
3717 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3718 EVT::f32, TwoToFractionalPartOfX);
3719 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3720 // For floating-point precision of 12:
3722 // TwoToFractionalPartOfX =
3725 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3727 // error 0.000107046256, which is 13 to 14 bits
3728 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3729 getF32Constant(DAG, 0x3da235e3));
3730 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3731 getF32Constant(DAG, 0x3e65b8f3));
3732 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3733 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3734 getF32Constant(DAG, 0x3f324b07));
3735 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3736 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3737 getF32Constant(DAG, 0x3f7ff8fd));
3738 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
3739 SDValue TwoToFractionalPartOfX =
3740 DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
3742 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3743 EVT::f32, TwoToFractionalPartOfX);
3744 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3745 // For floating-point precision of 18:
3747 // TwoToFractionalPartOfX =
3751 // (0.554906021e-1f +
3752 // (0.961591928e-2f +
3753 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3754 // error 2.47208000*10^(-7), which is better than 18 bits
3755 SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
3756 getF32Constant(DAG, 0x3924b03e));
3757 SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
3758 getF32Constant(DAG, 0x3ab24b87));
3759 SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
3760 SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
3761 getF32Constant(DAG, 0x3c1d8c17));
3762 SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
3763 SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
3764 getF32Constant(DAG, 0x3d634a1d));
3765 SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
3766 SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
3767 getF32Constant(DAG, 0x3e75fe14));
3768 SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
3769 SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
3770 getF32Constant(DAG, 0x3f317234));
3771 SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
3772 SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
3773 getF32Constant(DAG, 0x3f800000));
3774 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
3775 SDValue TwoToFractionalPartOfX =
3776 DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
3778 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3779 EVT::f32, TwoToFractionalPartOfX);
3782 // No special expansion.
3783 result = DAG.getNode(ISD::FPOW, dl,
3784 getValue(I.getOperand(1)).getValueType(),
3785 getValue(I.getOperand(1)),
3786 getValue(I.getOperand(2)));
3789 setValue(&I, result);
3792 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3793 /// we want to emit this as a call to a named external function, return the name
3794 /// otherwise lower it and return null.
3796 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3797 DebugLoc dl = getCurDebugLoc();
3798 switch (Intrinsic) {
3800 // By default, turn this into a target intrinsic node.
3801 visitTargetIntrinsic(I, Intrinsic);
3803 case Intrinsic::vastart: visitVAStart(I); return 0;
3804 case Intrinsic::vaend: visitVAEnd(I); return 0;
3805 case Intrinsic::vacopy: visitVACopy(I); return 0;
3806 case Intrinsic::returnaddress:
3807 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3808 getValue(I.getOperand(1))));
3810 case Intrinsic::frameaddress:
3811 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3812 getValue(I.getOperand(1))));
3814 case Intrinsic::setjmp:
3815 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3817 case Intrinsic::longjmp:
3818 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3820 case Intrinsic::memcpy: {
3821 SDValue Op1 = getValue(I.getOperand(1));
3822 SDValue Op2 = getValue(I.getOperand(2));
3823 SDValue Op3 = getValue(I.getOperand(3));
3824 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3825 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3826 I.getOperand(1), 0, I.getOperand(2), 0));
3829 case Intrinsic::memset: {
3830 SDValue Op1 = getValue(I.getOperand(1));
3831 SDValue Op2 = getValue(I.getOperand(2));
3832 SDValue Op3 = getValue(I.getOperand(3));
3833 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3834 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3835 I.getOperand(1), 0));
3838 case Intrinsic::memmove: {
3839 SDValue Op1 = getValue(I.getOperand(1));
3840 SDValue Op2 = getValue(I.getOperand(2));
3841 SDValue Op3 = getValue(I.getOperand(3));
3842 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3844 // If the source and destination are known to not be aliases, we can
3845 // lower memmove as memcpy.
3846 uint64_t Size = -1ULL;
3847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3848 Size = C->getZExtValue();
3849 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3850 AliasAnalysis::NoAlias) {
3851 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3852 I.getOperand(1), 0, I.getOperand(2), 0));
3856 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3857 I.getOperand(1), 0, I.getOperand(2), 0));
3860 case Intrinsic::dbg_stoppoint: {
3861 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3862 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3863 MachineFunction &MF = DAG.getMachineFunction();
3864 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3865 setCurDebugLoc(Loc);
3867 if (OptLevel == CodeGenOpt::None)
3868 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3875 case Intrinsic::dbg_region_start: {
3876 DwarfWriter *DW = DAG.getDwarfWriter();
3877 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3878 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3879 && DW->ShouldEmitDwarfDebug()) {
3881 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3882 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3883 getRoot(), LabelID));
3887 case Intrinsic::dbg_region_end: {
3888 DwarfWriter *DW = DAG.getDwarfWriter();
3889 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3891 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3892 || !DW->ShouldEmitDwarfDebug())
3895 MachineFunction &MF = DAG.getMachineFunction();
3896 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3898 if (isInlinedFnEnd(REI, MF.getFunction())) {
3899 // This is end of inlined function. Debugging information for inlined
3900 // function is not handled yet (only supported by FastISel).
3901 if (OptLevel == CodeGenOpt::None) {
3902 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3904 // Returned ID is 0 if this is unbalanced "end of inlined
3905 // scope". This could happen if optimizer eats dbg intrinsics or
3906 // "beginning of inlined scope" is not recoginized due to missing
3907 // location info. In such cases, do ignore this region.end.
3908 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3915 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3916 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3917 getRoot(), LabelID));
3920 case Intrinsic::dbg_func_start: {
3921 DwarfWriter *DW = DAG.getDwarfWriter();
3922 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3923 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3926 MachineFunction &MF = DAG.getMachineFunction();
3927 // This is a beginning of an inlined function.
3928 if (isInlinedFnStart(FSI, MF.getFunction())) {
3929 if (OptLevel != CodeGenOpt::None)
3930 // FIXME: Debugging informaation for inlined function is only
3931 // supported at CodeGenOpt::Node.
3934 DebugLoc PrevLoc = CurDebugLoc;
3935 // If llvm.dbg.func.start is seen in a new block before any
3936 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3937 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3938 if (PrevLoc.isUnknown())
3941 // Record the source line.
3942 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3944 if (!DW || !DW->ShouldEmitDwarfDebug())
3946 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3947 DISubprogram SP(cast<GlobalVariable>(FSI.getSubprogram()));
3948 DICompileUnit CU(PrevLocTpl.CompileUnit);
3949 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3952 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3953 getRoot(), LabelID));
3957 // This is a beginning of a new function.
3958 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3960 if (!DW || !DW->ShouldEmitDwarfDebug())
3962 // llvm.dbg.func_start also defines beginning of function scope.
3963 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
3966 case Intrinsic::dbg_declare: {
3967 if (OptLevel != CodeGenOpt::None)
3968 // FIXME: Variable debug info is not supported here.
3971 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3972 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3975 Value *Variable = DI.getVariable();
3976 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
3977 getValue(DI.getAddress()), getValue(Variable)));
3980 case Intrinsic::eh_exception: {
3981 // Insert the EXCEPTIONADDR instruction.
3982 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3983 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
3985 Ops[0] = DAG.getRoot();
3986 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3988 DAG.setRoot(Op.getValue(1));
3992 case Intrinsic::eh_selector_i32:
3993 case Intrinsic::eh_selector_i64: {
3994 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3995 EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3996 EVT::i32 : EVT::i64);
3999 if (CurMBB->isLandingPad())
4000 AddCatchInfo(I, MMI, CurMBB);
4003 FuncInfo.CatchInfoLost.insert(&I);
4005 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4006 unsigned Reg = TLI.getExceptionSelectorRegister();
4007 if (Reg) CurMBB->addLiveIn(Reg);
4010 // Insert the EHSELECTION instruction.
4011 SDVTList VTs = DAG.getVTList(VT, EVT::Other);
4013 Ops[0] = getValue(I.getOperand(1));
4015 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4017 DAG.setRoot(Op.getValue(1));
4019 setValue(&I, DAG.getConstant(0, VT));
4025 case Intrinsic::eh_typeid_for_i32:
4026 case Intrinsic::eh_typeid_for_i64: {
4027 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4028 EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4029 EVT::i32 : EVT::i64);
4032 // Find the type id for the given typeinfo.
4033 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4035 unsigned TypeID = MMI->getTypeIDFor(GV);
4036 setValue(&I, DAG.getConstant(TypeID, VT));
4038 // Return something different to eh_selector.
4039 setValue(&I, DAG.getConstant(1, VT));
4045 case Intrinsic::eh_return_i32:
4046 case Intrinsic::eh_return_i64:
4047 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4048 MMI->setCallsEHReturn(true);
4049 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4052 getValue(I.getOperand(1)),
4053 getValue(I.getOperand(2))));
4055 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4059 case Intrinsic::eh_unwind_init:
4060 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4061 MMI->setCallsUnwindInit(true);
4066 case Intrinsic::eh_dwarf_cfa: {
4067 EVT VT = getValue(I.getOperand(1)).getValueType();
4069 if (VT.bitsGT(TLI.getPointerTy()))
4070 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4071 TLI.getPointerTy(), getValue(I.getOperand(1)));
4073 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4074 TLI.getPointerTy(), getValue(I.getOperand(1)));
4076 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4078 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4079 TLI.getPointerTy()),
4081 setValue(&I, DAG.getNode(ISD::ADD, dl,
4083 DAG.getNode(ISD::FRAMEADDR, dl,
4086 TLI.getPointerTy())),
4090 case Intrinsic::eh_sjlj_callsite: {
4091 MachineFunction &MF = DAG.getMachineFunction();
4092 MF.setCallSiteIndex(cast<ConstantSDNode>(getValue(I.getOperand(1)))->getZExtValue());
4095 case Intrinsic::convertff:
4096 case Intrinsic::convertfsi:
4097 case Intrinsic::convertfui:
4098 case Intrinsic::convertsif:
4099 case Intrinsic::convertuif:
4100 case Intrinsic::convertss:
4101 case Intrinsic::convertsu:
4102 case Intrinsic::convertus:
4103 case Intrinsic::convertuu: {
4104 ISD::CvtCode Code = ISD::CVT_INVALID;
4105 switch (Intrinsic) {
4106 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4107 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4108 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4109 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4110 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4111 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4112 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4113 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4114 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4116 EVT DestVT = TLI.getValueType(I.getType());
4117 Value* Op1 = I.getOperand(1);
4118 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4119 DAG.getValueType(DestVT),
4120 DAG.getValueType(getValue(Op1).getValueType()),
4121 getValue(I.getOperand(2)),
4122 getValue(I.getOperand(3)),
4127 case Intrinsic::sqrt:
4128 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4129 getValue(I.getOperand(1)).getValueType(),
4130 getValue(I.getOperand(1))));
4132 case Intrinsic::powi:
4133 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4134 getValue(I.getOperand(1)).getValueType(),
4135 getValue(I.getOperand(1)),
4136 getValue(I.getOperand(2))));
4138 case Intrinsic::sin:
4139 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4140 getValue(I.getOperand(1)).getValueType(),
4141 getValue(I.getOperand(1))));
4143 case Intrinsic::cos:
4144 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4145 getValue(I.getOperand(1)).getValueType(),
4146 getValue(I.getOperand(1))));
4148 case Intrinsic::log:
4151 case Intrinsic::log2:
4154 case Intrinsic::log10:
4157 case Intrinsic::exp:
4160 case Intrinsic::exp2:
4163 case Intrinsic::pow:
4166 case Intrinsic::pcmarker: {
4167 SDValue Tmp = getValue(I.getOperand(1));
4168 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
4171 case Intrinsic::readcyclecounter: {
4172 SDValue Op = getRoot();
4173 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4174 DAG.getVTList(EVT::i64, EVT::Other),
4177 DAG.setRoot(Tmp.getValue(1));
4180 case Intrinsic::bswap:
4181 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4182 getValue(I.getOperand(1)).getValueType(),
4183 getValue(I.getOperand(1))));
4185 case Intrinsic::cttz: {
4186 SDValue Arg = getValue(I.getOperand(1));
4187 EVT Ty = Arg.getValueType();
4188 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4189 setValue(&I, result);
4192 case Intrinsic::ctlz: {
4193 SDValue Arg = getValue(I.getOperand(1));
4194 EVT Ty = Arg.getValueType();
4195 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4196 setValue(&I, result);
4199 case Intrinsic::ctpop: {
4200 SDValue Arg = getValue(I.getOperand(1));
4201 EVT Ty = Arg.getValueType();
4202 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4203 setValue(&I, result);
4206 case Intrinsic::stacksave: {
4207 SDValue Op = getRoot();
4208 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4209 DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
4211 DAG.setRoot(Tmp.getValue(1));
4214 case Intrinsic::stackrestore: {
4215 SDValue Tmp = getValue(I.getOperand(1));
4216 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
4219 case Intrinsic::stackprotector: {
4220 // Emit code into the DAG to store the stack guard onto the stack.
4221 MachineFunction &MF = DAG.getMachineFunction();
4222 MachineFrameInfo *MFI = MF.getFrameInfo();
4223 EVT PtrTy = TLI.getPointerTy();
4225 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4226 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4228 int FI = FuncInfo.StaticAllocaMap[Slot];
4229 MFI->setStackProtectorIndex(FI);
4231 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4233 // Store the stack protector onto the stack.
4234 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4235 PseudoSourceValue::getFixedStack(FI),
4237 setValue(&I, Result);
4238 DAG.setRoot(Result);
4241 case Intrinsic::var_annotation:
4242 // Discard annotate attributes
4245 case Intrinsic::init_trampoline: {
4246 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4250 Ops[1] = getValue(I.getOperand(1));
4251 Ops[2] = getValue(I.getOperand(2));
4252 Ops[3] = getValue(I.getOperand(3));
4253 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4254 Ops[5] = DAG.getSrcValue(F);
4256 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4257 DAG.getVTList(TLI.getPointerTy(), EVT::Other),
4261 DAG.setRoot(Tmp.getValue(1));
4265 case Intrinsic::gcroot:
4267 Value *Alloca = I.getOperand(1);
4268 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4270 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4271 GFI->addStackRoot(FI->getIndex(), TypeMap);
4275 case Intrinsic::gcread:
4276 case Intrinsic::gcwrite:
4277 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4280 case Intrinsic::flt_rounds: {
4281 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
4285 case Intrinsic::trap: {
4286 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
4290 case Intrinsic::uadd_with_overflow:
4291 return implVisitAluOverflow(I, ISD::UADDO);
4292 case Intrinsic::sadd_with_overflow:
4293 return implVisitAluOverflow(I, ISD::SADDO);
4294 case Intrinsic::usub_with_overflow:
4295 return implVisitAluOverflow(I, ISD::USUBO);
4296 case Intrinsic::ssub_with_overflow:
4297 return implVisitAluOverflow(I, ISD::SSUBO);
4298 case Intrinsic::umul_with_overflow:
4299 return implVisitAluOverflow(I, ISD::UMULO);
4300 case Intrinsic::smul_with_overflow:
4301 return implVisitAluOverflow(I, ISD::SMULO);
4303 case Intrinsic::prefetch: {
4306 Ops[1] = getValue(I.getOperand(1));
4307 Ops[2] = getValue(I.getOperand(2));
4308 Ops[3] = getValue(I.getOperand(3));
4309 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
4313 case Intrinsic::memory_barrier: {
4316 for (int x = 1; x < 6; ++x)
4317 Ops[x] = getValue(I.getOperand(x));
4319 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
4322 case Intrinsic::atomic_cmp_swap: {
4323 SDValue Root = getRoot();
4325 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4326 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4328 getValue(I.getOperand(1)),
4329 getValue(I.getOperand(2)),
4330 getValue(I.getOperand(3)),
4333 DAG.setRoot(L.getValue(1));
4336 case Intrinsic::atomic_load_add:
4337 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4338 case Intrinsic::atomic_load_sub:
4339 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4340 case Intrinsic::atomic_load_or:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4342 case Intrinsic::atomic_load_xor:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4344 case Intrinsic::atomic_load_and:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4346 case Intrinsic::atomic_load_nand:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4348 case Intrinsic::atomic_load_max:
4349 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4350 case Intrinsic::atomic_load_min:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4352 case Intrinsic::atomic_load_umin:
4353 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4354 case Intrinsic::atomic_load_umax:
4355 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4356 case Intrinsic::atomic_swap:
4357 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4361 /// Test if the given instruction is in a position to be optimized
4362 /// with a tail-call. This roughly means that it's in a block with
4363 /// a return and there's nothing that needs to be scheduled
4364 /// between it and the return.
4366 /// This function only tests target-independent requirements.
4367 /// For target-dependent requirements, a target should override
4368 /// TargetLowering::IsEligibleForTailCallOptimization.
4371 isInTailCallPosition(const Instruction *I, Attributes RetAttr,
4372 const TargetLowering &TLI) {
4373 const BasicBlock *ExitBB = I->getParent();
4374 const TerminatorInst *Term = ExitBB->getTerminator();
4375 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4376 const Function *F = ExitBB->getParent();
4378 // The block must end in a return statement or an unreachable.
4379 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4381 // If I will have a chain, make sure no other instruction that will have a
4382 // chain interposes between I and the return.
4383 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4384 !I->isSafeToSpeculativelyExecute())
4385 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4389 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4390 !BBI->isSafeToSpeculativelyExecute())
4394 // If the block ends with a void return or unreachable, it doesn't matter
4395 // what the call's return type is.
4396 if (!Ret || Ret->getNumOperands() == 0) return true;
4398 // Conservatively require the attributes of the call to match those of
4400 if (F->getAttributes().getRetAttributes() != RetAttr)
4403 // Otherwise, make sure the unmodified return value of I is the return value.
4404 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4405 U = dyn_cast<Instruction>(U->getOperand(0))) {
4408 if (!U->hasOneUse())
4412 // Check for a truly no-op truncate.
4413 if (isa<TruncInst>(U) &&
4414 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4416 // Check for a truly no-op bitcast.
4417 if (isa<BitCastInst>(U) &&
4418 (U->getOperand(0)->getType() == U->getType() ||
4419 (isa<PointerType>(U->getOperand(0)->getType()) &&
4420 isa<PointerType>(U->getType()))))
4422 // Otherwise it's not a true no-op.
4429 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4431 MachineBasicBlock *LandingPad) {
4432 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4433 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4434 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4435 unsigned BeginLabel = 0, EndLabel = 0;
4437 TargetLowering::ArgListTy Args;
4438 TargetLowering::ArgListEntry Entry;
4439 Args.reserve(CS.arg_size());
4441 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4443 SDValue ArgNode = getValue(*i);
4444 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4446 unsigned attrInd = i - CS.arg_begin() + 1;
4447 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4448 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4449 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4450 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4451 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4452 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4453 Entry.Alignment = CS.getParamAlignment(attrInd);
4454 Args.push_back(Entry);
4457 if (LandingPad && MMI) {
4458 MachineFunction &MF = DAG.getMachineFunction();
4459 // Insert a label before the invoke call to mark the try range. This can be
4460 // used to detect deletion of the invoke via the MachineModuleInfo.
4461 BeginLabel = MMI->NextLabelID();
4463 // Map this landing pad to the current call site entry
4464 MF.setLandingPadCallSiteIndex(LandingPad, MF.getCallSiteIndex());
4466 // Both PendingLoads and PendingExports must be flushed here;
4467 // this call might not return.
4469 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4470 getControlRoot(), BeginLabel));
4473 // Check if target-independent constraints permit a tail call here.
4474 // Target-dependent constraints are checked within TLI.LowerCallTo.
4476 !isInTailCallPosition(CS.getInstruction(),
4477 CS.getAttributes().getRetAttributes(),
4481 std::pair<SDValue,SDValue> Result =
4482 TLI.LowerCallTo(getRoot(), CS.getType(),
4483 CS.paramHasAttr(0, Attribute::SExt),
4484 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4485 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4486 CS.getCallingConv(),
4488 !CS.getInstruction()->use_empty(),
4489 Callee, Args, DAG, getCurDebugLoc());
4490 assert((isTailCall || Result.second.getNode()) &&
4491 "Non-null chain expected with non-tail call!");
4492 assert((Result.second.getNode() || !Result.first.getNode()) &&
4493 "Null value expected with tail call!");
4494 if (Result.first.getNode())
4495 setValue(CS.getInstruction(), Result.first);
4496 // As a special case, a null chain means that a tail call has
4497 // been emitted and the DAG root is already updated.
4498 if (Result.second.getNode())
4499 DAG.setRoot(Result.second);
4503 if (LandingPad && MMI) {
4504 // Insert a label at the end of the invoke call to mark the try range. This
4505 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4506 EndLabel = MMI->NextLabelID();
4507 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4508 getRoot(), EndLabel));
4510 // Inform MachineModuleInfo of range.
4511 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4516 void SelectionDAGLowering::visitCall(CallInst &I) {
4517 const char *RenameFn = 0;
4518 if (Function *F = I.getCalledFunction()) {
4519 if (F->isDeclaration()) {
4520 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4522 if (unsigned IID = II->getIntrinsicID(F)) {
4523 RenameFn = visitIntrinsicCall(I, IID);
4528 if (unsigned IID = F->getIntrinsicID()) {
4529 RenameFn = visitIntrinsicCall(I, IID);
4535 // Check for well-known libc/libm calls. If the function is internal, it
4536 // can't be a library call.
4537 if (!F->hasLocalLinkage() && F->hasName()) {
4538 StringRef Name = F->getName();
4539 if (Name == "copysign" || Name == "copysignf") {
4540 if (I.getNumOperands() == 3 && // Basic sanity checks.
4541 I.getOperand(1)->getType()->isFloatingPoint() &&
4542 I.getType() == I.getOperand(1)->getType() &&
4543 I.getType() == I.getOperand(2)->getType()) {
4544 SDValue LHS = getValue(I.getOperand(1));
4545 SDValue RHS = getValue(I.getOperand(2));
4546 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4547 LHS.getValueType(), LHS, RHS));
4550 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4551 if (I.getNumOperands() == 2 && // Basic sanity checks.
4552 I.getOperand(1)->getType()->isFloatingPoint() &&
4553 I.getType() == I.getOperand(1)->getType()) {
4554 SDValue Tmp = getValue(I.getOperand(1));
4555 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4556 Tmp.getValueType(), Tmp));
4559 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4560 if (I.getNumOperands() == 2 && // Basic sanity checks.
4561 I.getOperand(1)->getType()->isFloatingPoint() &&
4562 I.getType() == I.getOperand(1)->getType()) {
4563 SDValue Tmp = getValue(I.getOperand(1));
4564 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4565 Tmp.getValueType(), Tmp));
4568 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4569 if (I.getNumOperands() == 2 && // Basic sanity checks.
4570 I.getOperand(1)->getType()->isFloatingPoint() &&
4571 I.getType() == I.getOperand(1)->getType()) {
4572 SDValue Tmp = getValue(I.getOperand(1));
4573 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4574 Tmp.getValueType(), Tmp));
4579 } else if (isa<InlineAsm>(I.getOperand(0))) {
4586 Callee = getValue(I.getOperand(0));
4588 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4590 // Check if we can potentially perform a tail call. More detailed
4591 // checking is be done within LowerCallTo, after more information
4592 // about the call is known.
4593 bool isTailCall = PerformTailCallOpt && I.isTailCall();
4595 LowerCallTo(&I, Callee, isTailCall);
4599 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4600 /// this value and returns the result as a ValueVT value. This uses
4601 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4602 /// If the Flag pointer is NULL, no flag is used.
4603 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4605 SDValue *Flag) const {
4606 // Assemble the legal parts into the final values.
4607 SmallVector<SDValue, 4> Values(ValueVTs.size());
4608 SmallVector<SDValue, 8> Parts;
4609 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4610 // Copy the legal parts from the registers.
4611 EVT ValueVT = ValueVTs[Value];
4612 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4613 EVT RegisterVT = RegVTs[Value];
4615 Parts.resize(NumRegs);
4616 for (unsigned i = 0; i != NumRegs; ++i) {
4619 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4621 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4622 *Flag = P.getValue(2);
4624 Chain = P.getValue(1);
4626 // If the source register was virtual and if we know something about it,
4627 // add an assert node.
4628 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4629 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4630 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4631 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4632 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4633 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4635 unsigned RegSize = RegisterVT.getSizeInBits();
4636 unsigned NumSignBits = LOI.NumSignBits;
4637 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4639 // FIXME: We capture more information than the dag can represent. For
4640 // now, just use the tightest assertzext/assertsext possible.
4642 EVT FromVT(EVT::Other);
4643 if (NumSignBits == RegSize)
4644 isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1
4645 else if (NumZeroBits >= RegSize-1)
4646 isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1
4647 else if (NumSignBits > RegSize-8)
4648 isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8
4649 else if (NumZeroBits >= RegSize-8)
4650 isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8
4651 else if (NumSignBits > RegSize-16)
4652 isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16
4653 else if (NumZeroBits >= RegSize-16)
4654 isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
4655 else if (NumSignBits > RegSize-32)
4656 isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32
4657 else if (NumZeroBits >= RegSize-32)
4658 isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
4660 if (FromVT != EVT::Other) {
4661 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4662 RegisterVT, P, DAG.getValueType(FromVT));
4671 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4672 NumRegs, RegisterVT, ValueVT);
4677 return DAG.getNode(ISD::MERGE_VALUES, dl,
4678 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4679 &Values[0], ValueVTs.size());
4682 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4683 /// specified value into the registers specified by this object. This uses
4684 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4685 /// If the Flag pointer is NULL, no flag is used.
4686 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4687 SDValue &Chain, SDValue *Flag) const {
4688 // Get the list of the values's legal parts.
4689 unsigned NumRegs = Regs.size();
4690 SmallVector<SDValue, 8> Parts(NumRegs);
4691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4692 EVT ValueVT = ValueVTs[Value];
4693 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4694 EVT RegisterVT = RegVTs[Value];
4696 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4697 &Parts[Part], NumParts, RegisterVT);
4701 // Copy the parts into the registers.
4702 SmallVector<SDValue, 8> Chains(NumRegs);
4703 for (unsigned i = 0; i != NumRegs; ++i) {
4706 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4708 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4709 *Flag = Part.getValue(1);
4711 Chains[i] = Part.getValue(0);
4714 if (NumRegs == 1 || Flag)
4715 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4716 // flagged to it. That is the CopyToReg nodes and the user are considered
4717 // a single scheduling unit. If we create a TokenFactor and return it as
4718 // chain, then the TokenFactor is both a predecessor (operand) of the
4719 // user as well as a successor (the TF operands are flagged to the user).
4720 // c1, f1 = CopyToReg
4721 // c2, f2 = CopyToReg
4722 // c3 = TokenFactor c1, c2
4725 Chain = Chains[NumRegs-1];
4727 Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
4730 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4731 /// operand list. This adds the code marker and includes the number of
4732 /// values added into it.
4733 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4734 bool HasMatching,unsigned MatchingIdx,
4736 std::vector<SDValue> &Ops) const {
4737 EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4738 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4739 unsigned Flag = Code | (Regs.size() << 3);
4741 Flag |= 0x80000000 | (MatchingIdx << 16);
4742 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4743 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4744 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4745 EVT RegisterVT = RegVTs[Value];
4746 for (unsigned i = 0; i != NumRegs; ++i) {
4747 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4748 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4753 /// isAllocatableRegister - If the specified register is safe to allocate,
4754 /// i.e. it isn't a stack pointer or some other special register, return the
4755 /// register class for the register. Otherwise, return null.
4756 static const TargetRegisterClass *
4757 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4758 const TargetLowering &TLI,
4759 const TargetRegisterInfo *TRI) {
4760 EVT FoundVT = EVT::Other;
4761 const TargetRegisterClass *FoundRC = 0;
4762 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4763 E = TRI->regclass_end(); RCI != E; ++RCI) {
4764 EVT ThisVT = EVT::Other;
4766 const TargetRegisterClass *RC = *RCI;
4767 // If none of the the value types for this register class are valid, we
4768 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4769 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4771 if (TLI.isTypeLegal(*I)) {
4772 // If we have already found this register in a different register class,
4773 // choose the one with the largest VT specified. For example, on
4774 // PowerPC, we favor f64 register classes over f32.
4775 if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
4782 if (ThisVT == EVT::Other) continue;
4784 // NOTE: This isn't ideal. In particular, this might allocate the
4785 // frame pointer in functions that need it (due to them not being taken
4786 // out of allocation, because a variable sized allocation hasn't been seen
4787 // yet). This is a slight code pessimization, but should still work.
4788 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4789 E = RC->allocation_order_end(MF); I != E; ++I)
4791 // We found a matching register class. Keep looking at others in case
4792 // we find one with larger registers that this physreg is also in.
4803 /// AsmOperandInfo - This contains information for each constraint that we are
4805 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4806 public TargetLowering::AsmOperandInfo {
4808 /// CallOperand - If this is the result output operand or a clobber
4809 /// this is null, otherwise it is the incoming operand to the CallInst.
4810 /// This gets modified as the asm is processed.
4811 SDValue CallOperand;
4813 /// AssignedRegs - If this is a register or register class operand, this
4814 /// contains the set of register corresponding to the operand.
4815 RegsForValue AssignedRegs;
4817 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4818 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4821 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4822 /// busy in OutputRegs/InputRegs.
4823 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4824 std::set<unsigned> &OutputRegs,
4825 std::set<unsigned> &InputRegs,
4826 const TargetRegisterInfo &TRI) const {
4828 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4829 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4832 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4833 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4837 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4838 /// corresponds to. If there is no Value* for this operand, it returns
4840 EVT getCallOperandValEVT(const TargetLowering &TLI,
4841 const TargetData *TD) const {
4842 if (CallOperandVal == 0) return EVT::Other;
4844 if (isa<BasicBlock>(CallOperandVal))
4845 return TLI.getPointerTy();
4847 const llvm::Type *OpTy = CallOperandVal->getType();
4849 // If this is an indirect operand, the operand is a pointer to the
4852 OpTy = cast<PointerType>(OpTy)->getElementType();
4854 // If OpTy is not a single value, it may be a struct/union that we
4855 // can tile with integers.
4856 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4857 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4866 OpTy = IntegerType::get(BitSize);
4871 return TLI.getValueType(OpTy, true);
4875 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4877 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4878 const TargetRegisterInfo &TRI) {
4879 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4881 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4882 for (; *Aliases; ++Aliases)
4883 Regs.insert(*Aliases);
4886 } // end llvm namespace.
4889 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4890 /// specified operand. We prefer to assign virtual registers, to allow the
4891 /// register allocator handle the assignment process. However, if the asm uses
4892 /// features that we can't model on machineinstrs, we have SDISel do the
4893 /// allocation. This produces generally horrible, but correct, code.
4895 /// OpInfo describes the operand.
4896 /// Input and OutputRegs are the set of already allocated physical registers.
4898 void SelectionDAGLowering::
4899 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4900 std::set<unsigned> &OutputRegs,
4901 std::set<unsigned> &InputRegs) {
4902 // Compute whether this value requires an input register, an output register,
4904 bool isOutReg = false;
4905 bool isInReg = false;
4906 switch (OpInfo.Type) {
4907 case InlineAsm::isOutput:
4910 // If there is an input constraint that matches this, we need to reserve
4911 // the input register so no other inputs allocate to it.
4912 isInReg = OpInfo.hasMatchingInput();
4914 case InlineAsm::isInput:
4918 case InlineAsm::isClobber:
4925 MachineFunction &MF = DAG.getMachineFunction();
4926 SmallVector<unsigned, 4> Regs;
4928 // If this is a constraint for a single physreg, or a constraint for a
4929 // register class, find it.
4930 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4931 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4932 OpInfo.ConstraintVT);
4934 unsigned NumRegs = 1;
4935 if (OpInfo.ConstraintVT != EVT::Other) {
4936 // If this is a FP input in an integer register (or visa versa) insert a bit
4937 // cast of the input value. More generally, handle any case where the input
4938 // value disagrees with the register class we plan to stick this in.
4939 if (OpInfo.Type == InlineAsm::isInput &&
4940 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4941 // Try to convert to the first EVT that the reg class contains. If the
4942 // types are identical size, use a bitcast to convert (e.g. two differing
4944 EVT RegVT = *PhysReg.second->vt_begin();
4945 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4946 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4947 RegVT, OpInfo.CallOperand);
4948 OpInfo.ConstraintVT = RegVT;
4949 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4950 // If the input is a FP value and we want it in FP registers, do a
4951 // bitcast to the corresponding integer type. This turns an f64 value
4952 // into i64, which can be passed with two i32 values on a 32-bit
4954 RegVT = EVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4955 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4956 RegVT, OpInfo.CallOperand);
4957 OpInfo.ConstraintVT = RegVT;
4961 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4965 EVT ValueVT = OpInfo.ConstraintVT;
4967 // If this is a constraint for a specific physical register, like {r17},
4969 if (unsigned AssignedReg = PhysReg.first) {
4970 const TargetRegisterClass *RC = PhysReg.second;
4971 if (OpInfo.ConstraintVT == EVT::Other)
4972 ValueVT = *RC->vt_begin();
4974 // Get the actual register value type. This is important, because the user
4975 // may have asked for (e.g.) the AX register in i32 type. We need to
4976 // remember that AX is actually i16 to get the right extension.
4977 RegVT = *RC->vt_begin();
4979 // This is a explicit reference to a physical register.
4980 Regs.push_back(AssignedReg);
4982 // If this is an expanded reference, add the rest of the regs to Regs.
4984 TargetRegisterClass::iterator I = RC->begin();
4985 for (; *I != AssignedReg; ++I)
4986 assert(I != RC->end() && "Didn't find reg!");
4988 // Already added the first reg.
4990 for (; NumRegs; --NumRegs, ++I) {
4991 assert(I != RC->end() && "Ran out of registers to allocate!");
4995 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4996 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4997 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5001 // Otherwise, if this was a reference to an LLVM register class, create vregs
5002 // for this reference.
5003 if (const TargetRegisterClass *RC = PhysReg.second) {
5004 RegVT = *RC->vt_begin();
5005 if (OpInfo.ConstraintVT == EVT::Other)
5008 // Create the appropriate number of virtual registers.
5009 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5010 for (; NumRegs; --NumRegs)
5011 Regs.push_back(RegInfo.createVirtualRegister(RC));
5013 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5017 // This is a reference to a register class that doesn't directly correspond
5018 // to an LLVM register class. Allocate NumRegs consecutive, available,
5019 // registers from the class.
5020 std::vector<unsigned> RegClassRegs
5021 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5022 OpInfo.ConstraintVT);
5024 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5025 unsigned NumAllocated = 0;
5026 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5027 unsigned Reg = RegClassRegs[i];
5028 // See if this register is available.
5029 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5030 (isInReg && InputRegs.count(Reg))) { // Already used.
5031 // Make sure we find consecutive registers.
5036 // Check to see if this register is allocatable (i.e. don't give out the
5038 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5039 if (!RC) { // Couldn't allocate this register.
5040 // Reset NumAllocated to make sure we return consecutive registers.
5045 // Okay, this register is good, we can use it.
5048 // If we allocated enough consecutive registers, succeed.
5049 if (NumAllocated == NumRegs) {
5050 unsigned RegStart = (i-NumAllocated)+1;
5051 unsigned RegEnd = i+1;
5052 // Mark all of the allocated registers used.
5053 for (unsigned i = RegStart; i != RegEnd; ++i)
5054 Regs.push_back(RegClassRegs[i]);
5056 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5057 OpInfo.ConstraintVT);
5058 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5063 // Otherwise, we couldn't allocate enough registers for this.
5066 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5067 /// processed uses a memory 'm' constraint.
5069 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5070 const TargetLowering &TLI) {
5071 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5072 InlineAsm::ConstraintInfo &CI = CInfos[i];
5073 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5074 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5075 if (CType == TargetLowering::C_Memory)
5079 // Indirect operand accesses access memory.
5087 /// visitInlineAsm - Handle a call to an InlineAsm object.
5089 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5090 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5092 /// ConstraintOperands - Information about all of the constraints.
5093 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5095 std::set<unsigned> OutputRegs, InputRegs;
5097 // Do a prepass over the constraints, canonicalizing them, and building up the
5098 // ConstraintOperands list.
5099 std::vector<InlineAsm::ConstraintInfo>
5100 ConstraintInfos = IA->ParseConstraints();
5102 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5104 SDValue Chain, Flag;
5106 // We won't need to flush pending loads if this asm doesn't touch
5107 // memory and is nonvolatile.
5108 if (hasMemory || IA->hasSideEffects())
5111 Chain = DAG.getRoot();
5113 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5114 unsigned ResNo = 0; // ResNo - The result number of the next output.
5115 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5116 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5117 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5119 EVT OpVT = EVT::Other;
5121 // Compute the value type for each operand.
5122 switch (OpInfo.Type) {
5123 case InlineAsm::isOutput:
5124 // Indirect outputs just consume an argument.
5125 if (OpInfo.isIndirect) {
5126 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5130 // The return value of the call is this value. As such, there is no
5131 // corresponding argument.
5132 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5133 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5134 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5136 assert(ResNo == 0 && "Asm only has one result!");
5137 OpVT = TLI.getValueType(CS.getType());
5141 case InlineAsm::isInput:
5142 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5144 case InlineAsm::isClobber:
5149 // If this is an input or an indirect output, process the call argument.
5150 // BasicBlocks are labels, currently appearing only in asm's.
5151 if (OpInfo.CallOperandVal) {
5152 // Strip bitcasts, if any. This mostly comes up for functions.
5153 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5155 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5156 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5158 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5161 OpVT = OpInfo.getCallOperandValEVT(TLI, TD);
5164 OpInfo.ConstraintVT = OpVT;
5167 // Second pass over the constraints: compute which constraint option to use
5168 // and assign registers to constraints that want a specific physreg.
5169 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5170 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5172 // If this is an output operand with a matching input operand, look up the
5173 // matching input. If their types mismatch, e.g. one is an integer, the
5174 // other is floating point, or their sizes are different, flag it as an
5176 if (OpInfo.hasMatchingInput()) {
5177 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5178 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5179 if ((OpInfo.ConstraintVT.isInteger() !=
5180 Input.ConstraintVT.isInteger()) ||
5181 (OpInfo.ConstraintVT.getSizeInBits() !=
5182 Input.ConstraintVT.getSizeInBits())) {
5183 llvm_report_error("Unsupported asm: input constraint"
5184 " with a matching output constraint of incompatible"
5187 Input.ConstraintVT = OpInfo.ConstraintVT;
5191 // Compute the constraint code and ConstraintType to use.
5192 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5194 // If this is a memory input, and if the operand is not indirect, do what we
5195 // need to to provide an address for the memory input.
5196 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5197 !OpInfo.isIndirect) {
5198 assert(OpInfo.Type == InlineAsm::isInput &&
5199 "Can only indirectify direct input operands!");
5201 // Memory operands really want the address of the value. If we don't have
5202 // an indirect input, put it in the constpool if we can, otherwise spill
5203 // it to a stack slot.
5205 // If the operand is a float, integer, or vector constant, spill to a
5206 // constant pool entry to get its address.
5207 Value *OpVal = OpInfo.CallOperandVal;
5208 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5209 isa<ConstantVector>(OpVal)) {
5210 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5211 TLI.getPointerTy());
5213 // Otherwise, create a stack slot and emit a store to it before the
5215 const Type *Ty = OpVal->getType();
5216 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5217 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5218 MachineFunction &MF = DAG.getMachineFunction();
5219 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5220 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5221 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5222 OpInfo.CallOperand, StackSlot, NULL, 0);
5223 OpInfo.CallOperand = StackSlot;
5226 // There is no longer a Value* corresponding to this operand.
5227 OpInfo.CallOperandVal = 0;
5228 // It is now an indirect operand.
5229 OpInfo.isIndirect = true;
5232 // If this constraint is for a specific register, allocate it before
5234 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5235 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5237 ConstraintInfos.clear();
5240 // Second pass - Loop over all of the operands, assigning virtual or physregs
5241 // to register class operands.
5242 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5243 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5245 // C_Register operands have already been allocated, Other/Memory don't need
5247 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5248 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5251 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5252 std::vector<SDValue> AsmNodeOperands;
5253 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5254 AsmNodeOperands.push_back(
5255 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
5258 // Loop over all of the inputs, copying the operand values into the
5259 // appropriate registers and processing the output regs.
5260 RegsForValue RetValRegs;
5262 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5263 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5265 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5266 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5268 switch (OpInfo.Type) {
5269 case InlineAsm::isOutput: {
5270 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5271 OpInfo.ConstraintType != TargetLowering::C_Register) {
5272 // Memory output, or 'other' output (e.g. 'X' constraint).
5273 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5275 // Add information to the INLINEASM node to know about this output.
5276 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5277 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5278 TLI.getPointerTy()));
5279 AsmNodeOperands.push_back(OpInfo.CallOperand);
5283 // Otherwise, this is a register or register class output.
5285 // Copy the output from the appropriate register. Find a register that
5287 if (OpInfo.AssignedRegs.Regs.empty()) {
5288 llvm_report_error("Couldn't allocate output reg for"
5289 " constraint '" + OpInfo.ConstraintCode + "'!");
5292 // If this is an indirect operand, store through the pointer after the
5294 if (OpInfo.isIndirect) {
5295 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5296 OpInfo.CallOperandVal));
5298 // This is the result value of the call.
5299 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5300 // Concatenate this output onto the outputs list.
5301 RetValRegs.append(OpInfo.AssignedRegs);
5304 // Add information to the INLINEASM node to know that this register is
5306 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5307 6 /* EARLYCLOBBER REGDEF */ :
5311 DAG, AsmNodeOperands);
5314 case InlineAsm::isInput: {
5315 SDValue InOperandVal = OpInfo.CallOperand;
5317 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5318 // If this is required to match an output register we have already set,
5319 // just use its register.
5320 unsigned OperandNo = OpInfo.getMatchedOperand();
5322 // Scan until we find the definition we already emitted of this operand.
5323 // When we find it, create a RegsForValue operand.
5324 unsigned CurOp = 2; // The first operand.
5325 for (; OperandNo; --OperandNo) {
5326 // Advance to the next operand.
5328 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5329 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5330 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5331 (OpFlag & 7) == 4 /*MEM*/) &&
5332 "Skipped past definitions?");
5333 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5337 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5338 if ((OpFlag & 7) == 2 /*REGDEF*/
5339 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5340 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5341 if (OpInfo.isIndirect) {
5342 llvm_report_error("Don't know how to handle tied indirect "
5343 "register inputs yet!");
5345 RegsForValue MatchedRegs;
5346 MatchedRegs.TLI = &TLI;
5347 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5348 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5349 MatchedRegs.RegVTs.push_back(RegVT);
5350 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5351 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5354 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5356 // Use the produced MatchedRegs object to
5357 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5359 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5360 true, OpInfo.getMatchedOperand(),
5361 DAG, AsmNodeOperands);
5364 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5365 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5366 "Unexpected number of operands");
5367 // Add information to the INLINEASM node to know about this input.
5368 // See InlineAsm.h isUseOperandTiedToDef.
5369 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5370 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5371 TLI.getPointerTy()));
5372 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5377 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5378 assert(!OpInfo.isIndirect &&
5379 "Don't know how to handle indirect other inputs yet!");
5381 std::vector<SDValue> Ops;
5382 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5383 hasMemory, Ops, DAG);
5385 llvm_report_error("Invalid operand for inline asm"
5386 " constraint '" + OpInfo.ConstraintCode + "'!");
5389 // Add information to the INLINEASM node to know about this input.
5390 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5391 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5392 TLI.getPointerTy()));
5393 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5395 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5396 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5397 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5398 "Memory operands expect pointer values");
5400 // Add information to the INLINEASM node to know about this input.
5401 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5402 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5403 TLI.getPointerTy()));
5404 AsmNodeOperands.push_back(InOperandVal);
5408 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5409 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5410 "Unknown constraint type!");
5411 assert(!OpInfo.isIndirect &&
5412 "Don't know how to handle indirect register inputs yet!");
5414 // Copy the input into the appropriate registers.
5415 if (OpInfo.AssignedRegs.Regs.empty()) {
5416 llvm_report_error("Couldn't allocate input reg for"
5417 " constraint '"+ OpInfo.ConstraintCode +"'!");
5420 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5423 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5424 DAG, AsmNodeOperands);
5427 case InlineAsm::isClobber: {
5428 // Add the clobbered value to the operand list, so that the register
5429 // allocator is aware that the physreg got clobbered.
5430 if (!OpInfo.AssignedRegs.Regs.empty())
5431 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5432 false, 0, DAG,AsmNodeOperands);
5438 // Finish up input operands.
5439 AsmNodeOperands[0] = Chain;
5440 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5442 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5443 DAG.getVTList(EVT::Other, EVT::Flag),
5444 &AsmNodeOperands[0], AsmNodeOperands.size());
5445 Flag = Chain.getValue(1);
5447 // If this asm returns a register value, copy the result from that register
5448 // and set it as the value of the call.
5449 if (!RetValRegs.Regs.empty()) {
5450 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5453 // FIXME: Why don't we do this for inline asms with MRVs?
5454 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5455 EVT ResultType = TLI.getValueType(CS.getType());
5457 // If any of the results of the inline asm is a vector, it may have the
5458 // wrong width/num elts. This can happen for register classes that can
5459 // contain multiple different value types. The preg or vreg allocated may
5460 // not have the same VT as was expected. Convert it to the right type
5461 // with bit_convert.
5462 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5463 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5466 } else if (ResultType != Val.getValueType() &&
5467 ResultType.isInteger() && Val.getValueType().isInteger()) {
5468 // If a result value was tied to an input value, the computed result may
5469 // have a wider width than the expected result. Extract the relevant
5471 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5474 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5477 setValue(CS.getInstruction(), Val);
5478 // Don't need to use this as a chain in this case.
5479 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5483 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5485 // Process indirect outputs, first output all of the flagged copies out of
5487 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5488 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5489 Value *Ptr = IndirectStoresToEmit[i].second;
5490 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5492 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5496 // Emit the non-flagged stores from the physregs.
5497 SmallVector<SDValue, 8> OutChains;
5498 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5499 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5500 StoresToEmit[i].first,
5501 getValue(StoresToEmit[i].second),
5502 StoresToEmit[i].second, 0));
5503 if (!OutChains.empty())
5504 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
5505 &OutChains[0], OutChains.size());
5510 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5511 SDValue Src = getValue(I.getOperand(0));
5513 // Scale up by the type size in the original i32 type width. Various
5514 // mid-level optimizers may make assumptions about demanded bits etc from the
5515 // i32-ness of the optimizer: we do not want to promote to i64 and then
5516 // multiply on 64-bit targets.
5517 // FIXME: Malloc inst should go away: PR715.
5518 uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
5519 if (ElementSize != 1) {
5520 // Src is always 32-bits, make sure the constant fits.
5521 assert(Src.getValueType() == EVT::i32);
5522 ElementSize = (uint32_t)ElementSize;
5523 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5524 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5527 EVT IntPtr = TLI.getPointerTy();
5529 if (IntPtr.bitsLT(Src.getValueType()))
5530 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5531 else if (IntPtr.bitsGT(Src.getValueType()))
5532 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5534 TargetLowering::ArgListTy Args;
5535 TargetLowering::ArgListEntry Entry;
5537 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5538 Args.push_back(Entry);
5540 bool isTailCall = PerformTailCallOpt &&
5541 isInTailCallPosition(&I, Attribute::None, TLI);
5542 std::pair<SDValue,SDValue> Result =
5543 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5544 0, CallingConv::C, isTailCall,
5545 /*isReturnValueUsed=*/true,
5546 DAG.getExternalSymbol("malloc", IntPtr),
5547 Args, DAG, getCurDebugLoc());
5548 if (Result.first.getNode())
5549 setValue(&I, Result.first); // Pointers always fit in registers
5550 if (Result.second.getNode())
5551 DAG.setRoot(Result.second);
5554 void SelectionDAGLowering::visitFree(FreeInst &I) {
5555 TargetLowering::ArgListTy Args;
5556 TargetLowering::ArgListEntry Entry;
5557 Entry.Node = getValue(I.getOperand(0));
5558 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5559 Args.push_back(Entry);
5560 EVT IntPtr = TLI.getPointerTy();
5561 bool isTailCall = PerformTailCallOpt &&
5562 isInTailCallPosition(&I, Attribute::None, TLI);
5563 std::pair<SDValue,SDValue> Result =
5564 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5565 0, CallingConv::C, isTailCall,
5566 /*isReturnValueUsed=*/true,
5567 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5569 if (Result.second.getNode())
5570 DAG.setRoot(Result.second);
5573 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5574 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5575 EVT::Other, getRoot(),
5576 getValue(I.getOperand(1)),
5577 DAG.getSrcValue(I.getOperand(1))));
5580 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5581 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5582 getRoot(), getValue(I.getOperand(0)),
5583 DAG.getSrcValue(I.getOperand(0)));
5585 DAG.setRoot(V.getValue(1));
5588 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5589 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5590 EVT::Other, getRoot(),
5591 getValue(I.getOperand(1)),
5592 DAG.getSrcValue(I.getOperand(1))));
5595 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5596 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5597 EVT::Other, getRoot(),
5598 getValue(I.getOperand(1)),
5599 getValue(I.getOperand(2)),
5600 DAG.getSrcValue(I.getOperand(1)),
5601 DAG.getSrcValue(I.getOperand(2))));
5604 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5605 /// implementation, which just calls LowerCall.
5606 /// FIXME: When all targets are
5607 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5608 std::pair<SDValue, SDValue>
5609 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5610 bool RetSExt, bool RetZExt, bool isVarArg,
5611 bool isInreg, unsigned NumFixedArgs,
5612 unsigned CallConv, bool isTailCall,
5613 bool isReturnValueUsed,
5615 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5617 assert((!isTailCall || PerformTailCallOpt) &&
5618 "isTailCall set when tail-call optimizations are disabled!");
5620 // Handle all of the outgoing arguments.
5621 SmallVector<ISD::OutputArg, 32> Outs;
5622 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5623 SmallVector<EVT, 4> ValueVTs;
5624 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5625 for (unsigned Value = 0, NumValues = ValueVTs.size();
5626 Value != NumValues; ++Value) {
5627 EVT VT = ValueVTs[Value];
5628 const Type *ArgTy = VT.getTypeForEVT();
5629 SDValue Op = SDValue(Args[i].Node.getNode(),
5630 Args[i].Node.getResNo() + Value);
5631 ISD::ArgFlagsTy Flags;
5632 unsigned OriginalAlignment =
5633 getTargetData()->getABITypeAlignment(ArgTy);
5639 if (Args[i].isInReg)
5643 if (Args[i].isByVal) {
5645 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5646 const Type *ElementTy = Ty->getElementType();
5647 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5648 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5649 // For ByVal, alignment should come from FE. BE will guess if this
5650 // info is not there but there are cases it cannot get right.
5651 if (Args[i].Alignment)
5652 FrameAlign = Args[i].Alignment;
5653 Flags.setByValAlign(FrameAlign);
5654 Flags.setByValSize(FrameSize);
5658 Flags.setOrigAlign(OriginalAlignment);
5660 EVT PartVT = getRegisterType(VT);
5661 unsigned NumParts = getNumRegisters(VT);
5662 SmallVector<SDValue, 4> Parts(NumParts);
5663 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5666 ExtendKind = ISD::SIGN_EXTEND;
5667 else if (Args[i].isZExt)
5668 ExtendKind = ISD::ZERO_EXTEND;
5670 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5672 for (unsigned j = 0; j != NumParts; ++j) {
5673 // if it isn't first piece, alignment must be 1
5674 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5675 if (NumParts > 1 && j == 0)
5676 MyFlags.Flags.setSplit();
5678 MyFlags.Flags.setOrigAlign(1);
5680 Outs.push_back(MyFlags);
5685 // Handle the incoming return values from the call.
5686 SmallVector<ISD::InputArg, 32> Ins;
5687 SmallVector<EVT, 4> RetTys;
5688 ComputeValueVTs(*this, RetTy, RetTys);
5689 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5691 EVT RegisterVT = getRegisterType(VT);
5692 unsigned NumRegs = getNumRegisters(VT);
5693 for (unsigned i = 0; i != NumRegs; ++i) {
5694 ISD::InputArg MyFlags;
5695 MyFlags.VT = RegisterVT;
5696 MyFlags.Used = isReturnValueUsed;
5698 MyFlags.Flags.setSExt();
5700 MyFlags.Flags.setZExt();
5702 MyFlags.Flags.setInReg();
5703 Ins.push_back(MyFlags);
5707 // Check if target-dependent constraints permit a tail call here.
5708 // Target-independent constraints should be checked by the caller.
5710 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
5713 SmallVector<SDValue, 4> InVals;
5714 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5715 Outs, Ins, dl, DAG, InVals);
5717 // Verify that the target's LowerCall behaved as expected.
5718 assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
5719 "LowerCall didn't return a valid chain!");
5720 assert((!isTailCall || InVals.empty()) &&
5721 "LowerCall emitted a return value for a tail call!");
5722 assert((isTailCall || InVals.size() == Ins.size()) &&
5723 "LowerCall didn't emit the correct number of values!");
5724 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5725 assert(InVals[i].getNode() &&
5726 "LowerCall emitted a null value!");
5727 assert(Ins[i].VT == InVals[i].getValueType() &&
5728 "LowerCall emitted a value with the wrong type!");
5731 // For a tail call, the return value is merely live-out and there aren't
5732 // any nodes in the DAG representing it. Return a special value to
5733 // indicate that a tail call has been emitted and no more Instructions
5734 // should be processed in the current block.
5737 return std::make_pair(SDValue(), SDValue());
5740 // Collect the legal value parts into potentially illegal values
5741 // that correspond to the original function's return values.
5742 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5744 AssertOp = ISD::AssertSext;
5746 AssertOp = ISD::AssertZext;
5747 SmallVector<SDValue, 4> ReturnValues;
5748 unsigned CurReg = 0;
5749 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5751 EVT RegisterVT = getRegisterType(VT);
5752 unsigned NumRegs = getNumRegisters(VT);
5754 SDValue ReturnValue =
5755 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
5757 ReturnValues.push_back(ReturnValue);
5761 // For a function returning void, there is no return value. We can't create
5762 // such a node, so we just return a null return value in that case. In
5763 // that case, nothing will actualy look at the value.
5764 if (ReturnValues.empty())
5765 return std::make_pair(SDValue(), Chain);
5767 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5768 DAG.getVTList(&RetTys[0], RetTys.size()),
5769 &ReturnValues[0], ReturnValues.size());
5771 return std::make_pair(Res, Chain);
5774 void TargetLowering::LowerOperationWrapper(SDNode *N,
5775 SmallVectorImpl<SDValue> &Results,
5776 SelectionDAG &DAG) {
5777 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5779 Results.push_back(Res);
5782 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5783 llvm_unreachable("LowerOperation not implemented for this target!");
5788 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5789 SDValue Op = getValue(V);
5790 assert((Op.getOpcode() != ISD::CopyFromReg ||
5791 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5792 "Copy from a reg to the same reg!");
5793 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5795 RegsForValue RFV(TLI, Reg, V->getType());
5796 SDValue Chain = DAG.getEntryNode();
5797 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5798 PendingExports.push_back(Chain);
5801 #include "llvm/CodeGen/SelectionDAGISel.h"
5803 void SelectionDAGISel::
5804 LowerArguments(BasicBlock *LLVMBB) {
5805 // If this is the entry block, emit arguments.
5806 Function &F = *LLVMBB->getParent();
5807 SelectionDAG &DAG = SDL->DAG;
5808 SDValue OldRoot = DAG.getRoot();
5809 DebugLoc dl = SDL->getCurDebugLoc();
5810 const TargetData *TD = TLI.getTargetData();
5812 // Set up the incoming argument description vector.
5813 SmallVector<ISD::InputArg, 16> Ins;
5815 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5816 I != E; ++I, ++Idx) {
5817 SmallVector<EVT, 4> ValueVTs;
5818 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5819 bool isArgValueUsed = !I->use_empty();
5820 for (unsigned Value = 0, NumValues = ValueVTs.size();
5821 Value != NumValues; ++Value) {
5822 EVT VT = ValueVTs[Value];
5823 const Type *ArgTy = VT.getTypeForEVT();
5824 ISD::ArgFlagsTy Flags;
5825 unsigned OriginalAlignment =
5826 TD->getABITypeAlignment(ArgTy);
5828 if (F.paramHasAttr(Idx, Attribute::ZExt))
5830 if (F.paramHasAttr(Idx, Attribute::SExt))
5832 if (F.paramHasAttr(Idx, Attribute::InReg))
5834 if (F.paramHasAttr(Idx, Attribute::StructRet))
5836 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5838 const PointerType *Ty = cast<PointerType>(I->getType());
5839 const Type *ElementTy = Ty->getElementType();
5840 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5841 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5842 // For ByVal, alignment should be passed from FE. BE will guess if
5843 // this info is not there but there are cases it cannot get right.
5844 if (F.getParamAlignment(Idx))
5845 FrameAlign = F.getParamAlignment(Idx);
5846 Flags.setByValAlign(FrameAlign);
5847 Flags.setByValSize(FrameSize);
5849 if (F.paramHasAttr(Idx, Attribute::Nest))
5851 Flags.setOrigAlign(OriginalAlignment);
5853 EVT RegisterVT = TLI.getRegisterType(VT);
5854 unsigned NumRegs = TLI.getNumRegisters(VT);
5855 for (unsigned i = 0; i != NumRegs; ++i) {
5856 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5857 if (NumRegs > 1 && i == 0)
5858 MyFlags.Flags.setSplit();
5859 // if it isn't first piece, alignment must be 1
5861 MyFlags.Flags.setOrigAlign(1);
5862 Ins.push_back(MyFlags);
5867 // Call the target to set up the argument values.
5868 SmallVector<SDValue, 8> InVals;
5869 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5873 // Verify that the target's LowerFormalArguments behaved as expected.
5874 assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
5875 "LowerFormalArguments didn't return a valid chain!");
5876 assert(InVals.size() == Ins.size() &&
5877 "LowerFormalArguments didn't emit the correct number of values!");
5878 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5879 assert(InVals[i].getNode() &&
5880 "LowerFormalArguments emitted a null value!");
5881 assert(Ins[i].VT == InVals[i].getValueType() &&
5882 "LowerFormalArguments emitted a value with the wrong type!");
5885 // Update the DAG with the new chain value resulting from argument lowering.
5886 DAG.setRoot(NewRoot);
5888 // Set up the argument values.
5891 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5893 SmallVector<SDValue, 4> ArgValues;
5894 SmallVector<EVT, 4> ValueVTs;
5895 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5896 unsigned NumValues = ValueVTs.size();
5897 for (unsigned Value = 0; Value != NumValues; ++Value) {
5898 EVT VT = ValueVTs[Value];
5899 EVT PartVT = TLI.getRegisterType(VT);
5900 unsigned NumParts = TLI.getNumRegisters(VT);
5902 if (!I->use_empty()) {
5903 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5904 if (F.paramHasAttr(Idx, Attribute::SExt))
5905 AssertOp = ISD::AssertSext;
5906 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5907 AssertOp = ISD::AssertZext;
5909 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
5910 PartVT, VT, AssertOp));
5914 if (!I->use_empty()) {
5915 SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
5916 SDL->getCurDebugLoc()));
5917 // If this argument is live outside of the entry block, insert a copy from
5918 // whereever we got it to the vreg that other BB's will reference it as.
5919 SDL->CopyToExportRegsIfNeeded(I);
5922 assert(i == InVals.size() && "Argument register count mismatch!");
5924 // Finally, if the target has anything special to do, allow it to do so.
5925 // FIXME: this should insert code into the DAG!
5926 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5929 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5930 /// ensure constants are generated when needed. Remember the virtual registers
5931 /// that need to be added to the Machine PHI nodes as input. We cannot just
5932 /// directly add them, because expansion might result in multiple MBB's for one
5933 /// BB. As such, the start of the BB might correspond to a different MBB than
5937 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5938 TerminatorInst *TI = LLVMBB->getTerminator();
5940 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5942 // Check successor nodes' PHI nodes that expect a constant to be available
5944 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5945 BasicBlock *SuccBB = TI->getSuccessor(succ);
5946 if (!isa<PHINode>(SuccBB->begin())) continue;
5947 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5949 // If this terminator has multiple identical successors (common for
5950 // switches), only handle each succ once.
5951 if (!SuccsHandled.insert(SuccMBB)) continue;
5953 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5956 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5957 // nodes and Machine PHI nodes, but the incoming operands have not been
5959 for (BasicBlock::iterator I = SuccBB->begin();
5960 (PN = dyn_cast<PHINode>(I)); ++I) {
5961 // Ignore dead phi's.
5962 if (PN->use_empty()) continue;
5965 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5967 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5968 unsigned &RegOut = SDL->ConstantsOut[C];
5970 RegOut = FuncInfo->CreateRegForValue(C);
5971 SDL->CopyValueToVirtualRegister(C, RegOut);
5975 Reg = FuncInfo->ValueMap[PHIOp];
5977 assert(isa<AllocaInst>(PHIOp) &&
5978 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5979 "Didn't codegen value into a register!??");
5980 Reg = FuncInfo->CreateRegForValue(PHIOp);
5981 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5985 // Remember that this register needs to added to the machine PHI node as
5986 // the input for this MBB.
5987 SmallVector<EVT, 4> ValueVTs;
5988 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5989 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5990 EVT VT = ValueVTs[vti];
5991 unsigned NumRegisters = TLI.getNumRegisters(VT);
5992 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5993 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5994 Reg += NumRegisters;
5998 SDL->ConstantsOut.clear();
6001 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6002 /// supports legal types, and it emits MachineInstrs directly instead of
6003 /// creating SelectionDAG nodes.
6006 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6008 TerminatorInst *TI = LLVMBB->getTerminator();
6010 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6011 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6013 // Check successor nodes' PHI nodes that expect a constant to be available
6015 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6016 BasicBlock *SuccBB = TI->getSuccessor(succ);
6017 if (!isa<PHINode>(SuccBB->begin())) continue;
6018 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6020 // If this terminator has multiple identical successors (common for
6021 // switches), only handle each succ once.
6022 if (!SuccsHandled.insert(SuccMBB)) continue;
6024 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6027 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6028 // nodes and Machine PHI nodes, but the incoming operands have not been
6030 for (BasicBlock::iterator I = SuccBB->begin();
6031 (PN = dyn_cast<PHINode>(I)); ++I) {
6032 // Ignore dead phi's.
6033 if (PN->use_empty()) continue;
6035 // Only handle legal types. Two interesting things to note here. First,
6036 // by bailing out early, we may leave behind some dead instructions,
6037 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6038 // own moves. Second, this check is necessary becuase FastISel doesn't
6039 // use CreateRegForValue to create registers, so it always creates
6040 // exactly one register for each non-void instruction.
6041 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6042 if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
6045 VT = TLI.getTypeToTransformTo(VT);
6047 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6052 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6054 unsigned Reg = F->getRegForValue(PHIOp);
6056 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6059 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));