1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 /// LimitFloatPrecision - Generate low-precision inline sequences for
58 /// some float libcalls (6, 8 or 12 bits).
59 static unsigned LimitFloatPrecision;
61 static cl::opt<unsigned, true>
62 LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
68 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
69 /// of insertvalue or extractvalue indices that identify a member, return
70 /// the linearized index of the start of the member.
72 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
84 EE = STy->element_end();
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 // We haven't found the type we're looking for, so keep searching.
106 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107 /// MVTs that represent all the individual underlying
108 /// non-aggregate types that comprise it.
110 /// If Offsets is non-null, it points to a vector to be filled in
111 /// with the in-memory offsets of each of the individual values.
113 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
122 EE = STy->element_end();
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
137 // Base case: we can get an MVT for this LLVM IR type.
138 ValueVTs.push_back(TLI.getValueType(Ty));
140 Offsets->push_back(StartingOffset);
144 /// RegsForValue - This struct represents the registers (physical or virtual)
145 /// that a particular set of values is assigned, and the type information about
146 /// the value. The most common situation is to represent one value at a time,
147 /// but struct or array values are handled element-wise as multiple values.
148 /// The splitting of aggregates is performed recursively, so that we never
149 /// have aggregate-typed registers. The values at this point do not necessarily
150 /// have legal types, so each value may require one or more registers of some
153 struct VISIBILITY_HIDDEN RegsForValue {
154 /// TLI - The TargetLowering object.
156 const TargetLowering *TLI;
158 /// ValueVTs - The value types of the values, which may not be legal, and
159 /// may need be promoted or synthesized from one or more registers.
161 SmallVector<MVT, 4> ValueVTs;
163 /// RegVTs - The value types of the registers. This is the same size as
164 /// ValueVTs and it records, for each value, what the type of the assigned
165 /// register or registers are. (Individual values are never synthesized
166 /// from more than one type of register.)
168 /// With virtual registers, the contents of RegVTs is redundant with TLI's
169 /// getRegisterType member function, however when with physical registers
170 /// it is necessary to have a separate record of the types.
172 SmallVector<MVT, 4> RegVTs;
174 /// Regs - This list holds the registers assigned to the values.
175 /// Each legal or promoted value requires one register, and each
176 /// expanded value requires multiple registers.
178 SmallVector<unsigned, 4> Regs;
180 RegsForValue() : TLI(0) {}
182 RegsForValue(const TargetLowering &tli,
183 const SmallVector<unsigned, 4> ®s,
184 MVT regvt, MVT valuevt)
185 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 const SmallVector<MVT, 4> ®vts,
189 const SmallVector<MVT, 4> &valuevts)
190 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 unsigned Reg, const Type *Ty) : TLI(&tli) {
193 ComputeValueVTs(tli, Ty, ValueVTs);
195 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
196 MVT ValueVT = ValueVTs[Value];
197 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
198 MVT RegisterVT = TLI->getRegisterType(ValueVT);
199 for (unsigned i = 0; i != NumRegs; ++i)
200 Regs.push_back(Reg + i);
201 RegVTs.push_back(RegisterVT);
206 /// append - Add the specified values to this one.
207 void append(const RegsForValue &RHS) {
209 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
210 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
211 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
215 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
216 /// this value and returns the result as a ValueVTs value. This uses
217 /// Chain/Flag as the input and updates them for the output Chain/Flag.
218 /// If the Flag pointer is NULL, no flag is used.
219 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
220 SDValue &Chain, SDValue *Flag) const;
222 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
223 /// specified value into the registers specified by this object. This uses
224 /// Chain/Flag as the input and updates them for the output Chain/Flag.
225 /// If the Flag pointer is NULL, no flag is used.
226 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
227 SDValue &Chain, SDValue *Flag) const;
229 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
230 /// operand list. This adds the code marker and includes the number of
231 /// values added into it.
232 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
233 std::vector<SDValue> &Ops) const;
237 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
238 /// PHI nodes or outside of the basic block that defines it, or used by a
239 /// switch or atomic instruction, which may expand to multiple basic blocks.
240 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
241 if (isa<PHINode>(I)) return true;
242 BasicBlock *BB = I->getParent();
243 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
244 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
245 // FIXME: Remove switchinst special case.
246 isa<SwitchInst>(*UI))
251 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252 /// entry block, return true. This includes arguments used by switches, since
253 /// the switch may expand into multiple basic blocks.
254 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
260 return A->use_empty();
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
269 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
273 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
275 bool EnableFastISel) {
278 RegInfo = &MF->getRegInfo();
280 // Create a vreg for each argument register that is not dead and is used
281 // outside of the entry block for the function.
282 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
284 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
285 InitializeRegForValue(AI);
287 // Initialize the mapping of values to registers. This is only set up for
288 // instruction values that are used outside of the block that defines
290 Function::iterator BB = Fn->begin(), EB = Fn->end();
291 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
292 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
293 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
294 const Type *Ty = AI->getAllocatedType();
295 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
297 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
300 TySize *= CUI->getZExtValue(); // Get total allocated size.
301 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
302 StaticAllocaMap[AI] =
303 MF->getFrameInfo()->CreateStackObject(TySize, Align);
306 for (; BB != EB; ++BB)
307 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
308 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
309 if (!isa<AllocaInst>(I) ||
310 !StaticAllocaMap.count(cast<AllocaInst>(I)))
311 InitializeRegForValue(I);
313 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
314 // also creates the initial PHI MachineInstrs, though none of the input
315 // operands are populated.
316 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
317 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
321 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
325 for (BasicBlock::iterator
326 I = BB->begin(), E = BB->end(); I != E; ++I) {
327 if (CallInst *CI = dyn_cast<CallInst>(I)) {
328 if (Function *F = CI->getCalledFunction()) {
329 switch (F->getIntrinsicID()) {
331 case Intrinsic::dbg_stoppoint: {
332 DwarfWriter *DW = DAG.getDwarfWriter();
333 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
335 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
336 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
337 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
339 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
342 DL = DebugLoc::get(idx);
347 case Intrinsic::dbg_func_start: {
348 DwarfWriter *DW = DAG.getDwarfWriter();
350 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
351 Value *SP = FSI->getSubprogram();
353 if (DW->ValidDebugInfo(SP)) {
354 DISubprogram Subprogram(cast<GlobalVariable>(SP));
355 DICompileUnit CU(Subprogram.getCompileUnit());
356 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
358 unsigned Line = Subprogram.getLineNumber();
359 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
369 PN = dyn_cast<PHINode>(I);
370 if (!PN || PN->use_empty()) continue;
372 unsigned PHIReg = ValueMap[PN];
373 assert(PHIReg && "PHI node does not have an assigned virtual register!");
375 SmallVector<MVT, 4> ValueVTs;
376 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
377 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
378 MVT VT = ValueVTs[vti];
379 unsigned NumRegisters = TLI.getNumRegisters(VT);
380 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
381 for (unsigned i = 0; i != NumRegisters; ++i)
382 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
383 PHIReg += NumRegisters;
389 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
390 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
393 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
394 /// the correctly promoted or expanded types. Assign these registers
395 /// consecutive vreg numbers and return the first assigned number.
397 /// In the case that the given value has struct or array type, this function
398 /// will assign registers for each member or element.
400 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
401 SmallVector<MVT, 4> ValueVTs;
402 ComputeValueVTs(TLI, V->getType(), ValueVTs);
404 unsigned FirstReg = 0;
405 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
406 MVT ValueVT = ValueVTs[Value];
407 MVT RegisterVT = TLI.getRegisterType(ValueVT);
409 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
410 for (unsigned i = 0; i != NumRegs; ++i) {
411 unsigned R = MakeReg(RegisterVT);
412 if (!FirstReg) FirstReg = R;
418 /// getCopyFromParts - Create a value that contains the specified legal parts
419 /// combined into the value they represent. If the parts combine to a type
420 /// larger then ValueVT then AssertOp can be used to specify whether the extra
421 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
422 /// (ISD::AssertSext).
423 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
424 const SDValue *Parts,
425 unsigned NumParts, MVT PartVT, MVT ValueVT,
426 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
427 assert(NumParts > 0 && "No parts to assemble!");
428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
429 SDValue Val = Parts[0];
432 // Assemble the value from multiple parts.
433 if (!ValueVT.isVector()) {
434 unsigned PartBits = PartVT.getSizeInBits();
435 unsigned ValueBits = ValueVT.getSizeInBits();
437 // Assemble the power of 2 part.
438 unsigned RoundParts = NumParts & (NumParts - 1) ?
439 1 << Log2_32(NumParts) : NumParts;
440 unsigned RoundBits = PartBits * RoundParts;
441 MVT RoundVT = RoundBits == ValueBits ?
442 ValueVT : MVT::getIntegerVT(RoundBits);
445 MVT HalfVT = ValueVT.isInteger() ?
446 MVT::getIntegerVT(RoundBits/2) :
447 MVT::getFloatingPointVT(RoundBits/2);
449 if (RoundParts > 2) {
450 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
451 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
454 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
455 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
457 if (TLI.isBigEndian())
459 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
461 if (RoundParts < NumParts) {
462 // Assemble the trailing non-power-of-2 part.
463 unsigned OddParts = NumParts - RoundParts;
464 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
465 Hi = getCopyFromParts(DAG, dl,
466 Parts+RoundParts, OddParts, PartVT, OddVT);
468 // Combine the round and odd parts.
470 if (TLI.isBigEndian())
472 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
473 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
474 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
475 DAG.getConstant(Lo.getValueType().getSizeInBits(),
476 TLI.getPointerTy()));
477 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
478 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
481 // Handle a multi-element vector.
482 MVT IntermediateVT, RegisterVT;
483 unsigned NumIntermediates;
485 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
487 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
488 NumParts = NumRegs; // Silence a compiler warning.
489 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
490 assert(RegisterVT == Parts[0].getValueType() &&
491 "Part type doesn't match part!");
493 // Assemble the parts into intermediate operands.
494 SmallVector<SDValue, 8> Ops(NumIntermediates);
495 if (NumIntermediates == NumParts) {
496 // If the register was not expanded, truncate or copy the value,
498 for (unsigned i = 0; i != NumParts; ++i)
499 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
500 PartVT, IntermediateVT);
501 } else if (NumParts > 0) {
502 // If the intermediate type was expanded, build the intermediate operands
504 assert(NumParts % NumIntermediates == 0 &&
505 "Must expand into a divisible number of parts!");
506 unsigned Factor = NumParts / NumIntermediates;
507 for (unsigned i = 0; i != NumIntermediates; ++i)
508 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
509 PartVT, IntermediateVT);
512 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
514 Val = DAG.getNode(IntermediateVT.isVector() ?
515 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
516 ValueVT, &Ops[0], NumIntermediates);
520 // There is now one part, held in Val. Correct it to match ValueVT.
521 PartVT = Val.getValueType();
523 if (PartVT == ValueVT)
526 if (PartVT.isVector()) {
527 assert(ValueVT.isVector() && "Unknown vector conversion!");
528 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
531 if (ValueVT.isVector()) {
532 assert(ValueVT.getVectorElementType() == PartVT &&
533 ValueVT.getVectorNumElements() == 1 &&
534 "Only trivial scalar-to-vector conversions should get here!");
535 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
538 if (PartVT.isInteger() &&
539 ValueVT.isInteger()) {
540 if (ValueVT.bitsLT(PartVT)) {
541 // For a truncate, see if we have any information to
542 // indicate whether the truncated bits will always be
543 // zero or sign-extension.
544 if (AssertOp != ISD::DELETED_NODE)
545 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
546 DAG.getValueType(ValueVT));
547 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
549 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
553 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
554 if (ValueVT.bitsLT(Val.getValueType()))
555 // FP_ROUND's are always exact here.
556 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
557 DAG.getIntPtrConstant(1));
558 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
561 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
562 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
564 assert(0 && "Unknown mismatch!");
568 /// getCopyToParts - Create a series of nodes that contain the specified value
569 /// split into legal parts. If the parts contain more bits than Val, then, for
570 /// integers, ExtendKind can be used to specify how to generate the extra bits.
571 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
572 SDValue *Parts, unsigned NumParts, MVT PartVT,
573 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
575 MVT PtrVT = TLI.getPointerTy();
576 MVT ValueVT = Val.getValueType();
577 unsigned PartBits = PartVT.getSizeInBits();
578 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
583 if (!ValueVT.isVector()) {
584 if (PartVT == ValueVT) {
585 assert(NumParts == 1 && "No-op copy with multiple parts!");
590 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
591 // If the parts cover more bits than the value has, promote the value.
592 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
593 assert(NumParts == 1 && "Do not know what to promote to!");
594 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
595 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
596 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
597 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
599 assert(0 && "Unknown mismatch!");
601 } else if (PartBits == ValueVT.getSizeInBits()) {
602 // Different types of the same size.
603 assert(NumParts == 1 && PartVT != ValueVT);
604 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
605 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
606 // If the parts cover less bits than value has, truncate the value.
607 if (PartVT.isInteger() && ValueVT.isInteger()) {
608 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
609 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
611 assert(0 && "Unknown mismatch!");
615 // The value may have changed - recompute ValueVT.
616 ValueVT = Val.getValueType();
617 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
618 "Failed to tile the value with PartVT!");
621 assert(PartVT == ValueVT && "Type conversion failed!");
626 // Expand the value into multiple parts.
627 if (NumParts & (NumParts - 1)) {
628 // The number of parts is not a power of 2. Split off and copy the tail.
629 assert(PartVT.isInteger() && ValueVT.isInteger() &&
630 "Do not know what to expand to!");
631 unsigned RoundParts = 1 << Log2_32(NumParts);
632 unsigned RoundBits = RoundParts * PartBits;
633 unsigned OddParts = NumParts - RoundParts;
634 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
635 DAG.getConstant(RoundBits,
636 TLI.getPointerTy()));
637 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
638 if (TLI.isBigEndian())
639 // The odd parts were reversed by getCopyToParts - unreverse them.
640 std::reverse(Parts + RoundParts, Parts + NumParts);
641 NumParts = RoundParts;
642 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
643 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
646 // The number of parts is a power of 2. Repeatedly bisect the value using
648 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
649 MVT::getIntegerVT(ValueVT.getSizeInBits()),
651 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
652 for (unsigned i = 0; i < NumParts; i += StepSize) {
653 unsigned ThisBits = StepSize * PartBits / 2;
654 MVT ThisVT = MVT::getIntegerVT (ThisBits);
655 SDValue &Part0 = Parts[i];
656 SDValue &Part1 = Parts[i+StepSize/2];
658 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(1, PtrVT));
661 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
663 DAG.getConstant(0, PtrVT));
665 if (ThisBits == PartBits && ThisVT != PartVT) {
666 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
668 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 if (TLI.isBigEndian())
675 std::reverse(Parts, Parts + NumParts);
682 if (PartVT != ValueVT) {
683 if (PartVT.isVector()) {
684 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
686 assert(ValueVT.getVectorElementType() == PartVT &&
687 ValueVT.getVectorNumElements() == 1 &&
688 "Only trivial vector-to-scalar conversions should get here!");
689 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
691 DAG.getConstant(0, PtrVT));
699 // Handle a multi-element vector.
700 MVT IntermediateVT, RegisterVT;
701 unsigned NumIntermediates;
702 unsigned NumRegs = TLI
703 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
705 unsigned NumElements = ValueVT.getVectorNumElements();
707 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
708 NumParts = NumRegs; // Silence a compiler warning.
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
711 // Split the vector into intermediate operands.
712 SmallVector<SDValue, 8> Ops(NumIntermediates);
713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 if (IntermediateVT.isVector())
715 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
717 DAG.getConstant(i * (NumElements / NumIntermediates),
720 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
722 DAG.getConstant(i, PtrVT));
724 // Split the intermediate operands into legal parts.
725 if (NumParts == NumIntermediates) {
726 // If the register was not expanded, promote or copy the value,
728 for (unsigned i = 0; i != NumParts; ++i)
729 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
730 } else if (NumParts > 0) {
731 // If the intermediate type was expanded, split each the value into
733 assert(NumParts % NumIntermediates == 0 &&
734 "Must expand into a divisible number of parts!");
735 unsigned Factor = NumParts / NumIntermediates;
736 for (unsigned i = 0; i != NumIntermediates; ++i)
737 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
742 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
745 TD = DAG.getTarget().getTargetData();
748 /// clear - Clear out the curret SelectionDAG and the associated
749 /// state and prepare this SelectionDAGLowering object to be used
750 /// for a new block. This doesn't clear out information about
751 /// additional blocks that are needed to complete switch lowering
752 /// or PHI node updating; that information is cleared out as it is
754 void SelectionDAGLowering::clear() {
756 PendingLoads.clear();
757 PendingExports.clear();
761 /// getRoot - Return the current virtual root of the Selection DAG,
762 /// flushing any PendingLoad items. This must be done before emitting
763 /// a store or any other node that may need to be ordered after any
764 /// prior load instructions.
766 SDValue SelectionDAGLowering::getRoot() {
767 if (PendingLoads.empty())
768 return DAG.getRoot();
770 if (PendingLoads.size() == 1) {
771 SDValue Root = PendingLoads[0];
773 PendingLoads.clear();
777 // Otherwise, we have to make a token factor node.
778 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
779 &PendingLoads[0], PendingLoads.size());
780 PendingLoads.clear();
785 /// getControlRoot - Similar to getRoot, but instead of flushing all the
786 /// PendingLoad items, flush all the PendingExports items. It is necessary
787 /// to do this before emitting a terminator instruction.
789 SDValue SelectionDAGLowering::getControlRoot() {
790 SDValue Root = DAG.getRoot();
792 if (PendingExports.empty())
795 // Turn all of the CopyToReg chains into one factored node.
796 if (Root.getOpcode() != ISD::EntryToken) {
797 unsigned i = 0, e = PendingExports.size();
798 for (; i != e; ++i) {
799 assert(PendingExports[i].getNode()->getNumOperands() > 1);
800 if (PendingExports[i].getNode()->getOperand(0) == Root)
801 break; // Don't add the root if we already indirectly depend on it.
805 PendingExports.push_back(Root);
808 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
810 PendingExports.size());
811 PendingExports.clear();
816 void SelectionDAGLowering::visit(Instruction &I) {
817 visit(I.getOpcode(), I);
820 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
821 // Note: this doesn't use InstVisitor, because it has to work with
822 // ConstantExpr's in addition to instructions.
824 default: assert(0 && "Unknown instruction type encountered!");
826 // Build the switch statement using the Instruction.def file.
827 #define HANDLE_INST(NUM, OPCODE, CLASS) \
828 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
829 #include "llvm/Instruction.def"
833 void SelectionDAGLowering::visitAdd(User &I) {
834 if (I.getType()->isFPOrFPVector())
835 visitBinary(I, ISD::FADD);
837 visitBinary(I, ISD::ADD);
840 void SelectionDAGLowering::visitMul(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FMUL);
844 visitBinary(I, ISD::MUL);
847 SDValue SelectionDAGLowering::getValue(const Value *V) {
848 SDValue &N = NodeMap[V];
849 if (N.getNode()) return N;
851 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
852 MVT VT = TLI.getValueType(V->getType(), true);
854 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
855 return N = DAG.getConstant(*CI, VT);
857 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
858 return N = DAG.getGlobalAddress(GV, VT);
860 if (isa<ConstantPointerNull>(C))
861 return N = DAG.getConstant(0, TLI.getPointerTy());
863 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
864 return N = DAG.getConstantFP(*CFP, VT);
866 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
867 !V->getType()->isAggregateType())
868 return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
870 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
871 visit(CE->getOpcode(), *CE);
872 SDValue N1 = NodeMap[V];
873 assert(N1.getNode() && "visit didn't populate the ValueMap!");
877 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
878 SmallVector<SDValue, 4> Constants;
879 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
881 SDNode *Val = getValue(*OI).getNode();
882 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
883 Constants.push_back(SDValue(Val, i));
885 return DAG.getMergeValues(&Constants[0], Constants.size(),
889 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
890 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
891 "Unknown struct or array constant!");
893 SmallVector<MVT, 4> ValueVTs;
894 ComputeValueVTs(TLI, C->getType(), ValueVTs);
895 unsigned NumElts = ValueVTs.size();
897 return SDValue(); // empty struct
898 SmallVector<SDValue, 4> Constants(NumElts);
899 for (unsigned i = 0; i != NumElts; ++i) {
900 MVT EltVT = ValueVTs[i];
901 if (isa<UndefValue>(C))
902 Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
903 else if (EltVT.isFloatingPoint())
904 Constants[i] = DAG.getConstantFP(0, EltVT);
906 Constants[i] = DAG.getConstant(0, EltVT);
908 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
911 const VectorType *VecTy = cast<VectorType>(V->getType());
912 unsigned NumElements = VecTy->getNumElements();
914 // Now that we know the number and type of the elements, get that number of
915 // elements into the Ops array based on what kind of constant it is.
916 SmallVector<SDValue, 16> Ops;
917 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
918 for (unsigned i = 0; i != NumElements; ++i)
919 Ops.push_back(getValue(CP->getOperand(i)));
921 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
922 "Unknown vector constant!");
923 MVT EltVT = TLI.getValueType(VecTy->getElementType());
926 if (isa<UndefValue>(C))
927 Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
928 else if (EltVT.isFloatingPoint())
929 Op = DAG.getConstantFP(0, EltVT);
931 Op = DAG.getConstant(0, EltVT);
932 Ops.assign(NumElements, Op);
935 // Create a BUILD_VECTOR node.
936 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
937 VT, &Ops[0], Ops.size());
940 // If this is a static alloca, generate it as the frameindex instead of
942 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
943 DenseMap<const AllocaInst*, int>::iterator SI =
944 FuncInfo.StaticAllocaMap.find(AI);
945 if (SI != FuncInfo.StaticAllocaMap.end())
946 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
949 unsigned InReg = FuncInfo.ValueMap[V];
950 assert(InReg && "Value not in map!");
952 RegsForValue RFV(TLI, InReg, V->getType());
953 SDValue Chain = DAG.getEntryNode();
954 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
958 void SelectionDAGLowering::visitRet(ReturnInst &I) {
959 if (I.getNumOperands() == 0) {
960 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
961 MVT::Other, getControlRoot()));
965 SmallVector<SDValue, 8> NewValues;
966 NewValues.push_back(getControlRoot());
967 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
968 SmallVector<MVT, 4> ValueVTs;
969 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
970 unsigned NumValues = ValueVTs.size();
971 if (NumValues == 0) continue;
973 SDValue RetOp = getValue(I.getOperand(i));
974 for (unsigned j = 0, f = NumValues; j != f; ++j) {
975 MVT VT = ValueVTs[j];
977 // FIXME: C calling convention requires the return type to be promoted to
978 // at least 32-bit. But this is not necessary for non-C calling
980 if (VT.isInteger()) {
981 MVT MinVT = TLI.getRegisterType(MVT::i32);
982 if (VT.bitsLT(MinVT))
986 unsigned NumParts = TLI.getNumRegisters(VT);
987 MVT PartVT = TLI.getRegisterType(VT);
988 SmallVector<SDValue, 4> Parts(NumParts);
989 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
991 const Function *F = I.getParent()->getParent();
992 if (F->paramHasAttr(0, Attribute::SExt))
993 ExtendKind = ISD::SIGN_EXTEND;
994 else if (F->paramHasAttr(0, Attribute::ZExt))
995 ExtendKind = ISD::ZERO_EXTEND;
997 getCopyToParts(DAG, getCurDebugLoc(),
998 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
999 &Parts[0], NumParts, PartVT, ExtendKind);
1001 // 'inreg' on function refers to return value
1002 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1003 if (F->paramHasAttr(0, Attribute::InReg))
1005 for (unsigned i = 0; i < NumParts; ++i) {
1006 NewValues.push_back(Parts[i]);
1007 NewValues.push_back(DAG.getArgFlags(Flags));
1011 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1012 &NewValues[0], NewValues.size()));
1015 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1016 /// the current basic block, add it to ValueMap now so that we'll get a
1018 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1019 // No need to export constants.
1020 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1022 // Already exported?
1023 if (FuncInfo.isExportedInst(V)) return;
1025 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1026 CopyValueToVirtualRegister(V, Reg);
1029 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1030 const BasicBlock *FromBB) {
1031 // The operands of the setcc have to be in this block. We don't know
1032 // how to export them from some other block.
1033 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1034 // Can export from current BB.
1035 if (VI->getParent() == FromBB)
1038 // Is already exported, noop.
1039 return FuncInfo.isExportedInst(V);
1042 // If this is an argument, we can export it if the BB is the entry block or
1043 // if it is already exported.
1044 if (isa<Argument>(V)) {
1045 if (FromBB == &FromBB->getParent()->getEntryBlock())
1048 // Otherwise, can only export this if it is already exported.
1049 return FuncInfo.isExportedInst(V);
1052 // Otherwise, constants can always be exported.
1056 static bool InBlock(const Value *V, const BasicBlock *BB) {
1057 if (const Instruction *I = dyn_cast<Instruction>(V))
1058 return I->getParent() == BB;
1062 /// getFCmpCondCode - Return the ISD condition code corresponding to
1063 /// the given LLVM IR floating-point condition code. This includes
1064 /// consideration of global floating-point math flags.
1066 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1067 ISD::CondCode FPC, FOC;
1069 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1070 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1071 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1072 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1073 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1074 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1075 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1076 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1077 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1078 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1079 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1080 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1081 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1082 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1083 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1084 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1086 assert(0 && "Invalid FCmp predicate opcode!");
1087 FOC = FPC = ISD::SETFALSE;
1090 if (FiniteOnlyFPMath())
1096 /// getICmpCondCode - Return the ISD condition code corresponding to
1097 /// the given LLVM IR integer condition code.
1099 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1101 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1102 case ICmpInst::ICMP_NE: return ISD::SETNE;
1103 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1104 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1105 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1106 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1107 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1108 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1109 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1110 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1112 assert(0 && "Invalid ICmp predicate opcode!");
1117 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1118 /// This function emits a branch and is used at the leaves of an OR or an
1119 /// AND operator tree.
1122 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1123 MachineBasicBlock *TBB,
1124 MachineBasicBlock *FBB,
1125 MachineBasicBlock *CurBB) {
1126 const BasicBlock *BB = CurBB->getBasicBlock();
1128 // If the leaf of the tree is a comparison, merge the condition into
1130 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1131 // The operands of the cmp have to be in this block. We don't know
1132 // how to export them from some other block. If this is the first block
1133 // of the sequence, no exporting is needed.
1134 if (CurBB == CurMBB ||
1135 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1136 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1137 ISD::CondCode Condition;
1138 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1139 Condition = getICmpCondCode(IC->getPredicate());
1140 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1141 Condition = getFCmpCondCode(FC->getPredicate());
1143 Condition = ISD::SETEQ; // silence warning.
1144 assert(0 && "Unknown compare instruction");
1147 CaseBlock CB(Condition, BOp->getOperand(0),
1148 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1149 SwitchCases.push_back(CB);
1154 // Create a CaseBlock record representing this branch.
1155 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1156 NULL, TBB, FBB, CurBB);
1157 SwitchCases.push_back(CB);
1160 /// FindMergedConditions - If Cond is an expression like
1161 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1162 MachineBasicBlock *TBB,
1163 MachineBasicBlock *FBB,
1164 MachineBasicBlock *CurBB,
1166 // If this node is not part of the or/and tree, emit it as a branch.
1167 Instruction *BOp = dyn_cast<Instruction>(Cond);
1168 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1169 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1170 BOp->getParent() != CurBB->getBasicBlock() ||
1171 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1172 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1173 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1177 // Create TmpBB after CurBB.
1178 MachineFunction::iterator BBI = CurBB;
1179 MachineFunction &MF = DAG.getMachineFunction();
1180 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1181 CurBB->getParent()->insert(++BBI, TmpBB);
1183 if (Opc == Instruction::Or) {
1184 // Codegen X | Y as:
1192 // Emit the LHS condition.
1193 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1195 // Emit the RHS condition into TmpBB.
1196 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1198 assert(Opc == Instruction::And && "Unknown merge op!");
1199 // Codegen X & Y as:
1206 // This requires creation of TmpBB after CurBB.
1208 // Emit the LHS condition.
1209 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1211 // Emit the RHS condition into TmpBB.
1212 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1216 /// If the set of cases should be emitted as a series of branches, return true.
1217 /// If we should emit this as a bunch of and/or'd together conditions, return
1220 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1221 if (Cases.size() != 2) return true;
1223 // If this is two comparisons of the same values or'd or and'd together, they
1224 // will get folded into a single comparison, so don't emit two blocks.
1225 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1226 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1227 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1228 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1235 void SelectionDAGLowering::visitBr(BranchInst &I) {
1236 // Update machine-CFG edges.
1237 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1239 // Figure out which block is immediately after the current one.
1240 MachineBasicBlock *NextBlock = 0;
1241 MachineFunction::iterator BBI = CurMBB;
1242 if (++BBI != CurMBB->getParent()->end())
1245 if (I.isUnconditional()) {
1246 // Update machine-CFG edges.
1247 CurMBB->addSuccessor(Succ0MBB);
1249 // If this is not a fall-through branch, emit the branch.
1250 if (Succ0MBB != NextBlock)
1251 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1252 MVT::Other, getControlRoot(),
1253 DAG.getBasicBlock(Succ0MBB)));
1257 // If this condition is one of the special cases we handle, do special stuff
1259 Value *CondVal = I.getCondition();
1260 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1262 // If this is a series of conditions that are or'd or and'd together, emit
1263 // this as a sequence of branches instead of setcc's with and/or operations.
1264 // For example, instead of something like:
1277 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1278 if (BOp->hasOneUse() &&
1279 (BOp->getOpcode() == Instruction::And ||
1280 BOp->getOpcode() == Instruction::Or)) {
1281 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1282 // If the compares in later blocks need to use values not currently
1283 // exported from this block, export them now. This block should always
1284 // be the first entry.
1285 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1287 // Allow some cases to be rejected.
1288 if (ShouldEmitAsBranches(SwitchCases)) {
1289 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1290 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1291 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1294 // Emit the branch for this block.
1295 visitSwitchCase(SwitchCases[0]);
1296 SwitchCases.erase(SwitchCases.begin());
1300 // Okay, we decided not to do this, remove any inserted MBB's and clear
1302 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1303 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1305 SwitchCases.clear();
1309 // Create a CaseBlock record representing this branch.
1310 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1311 NULL, Succ0MBB, Succ1MBB, CurMBB);
1312 // Use visitSwitchCase to actually insert the fast branch sequence for this
1314 visitSwitchCase(CB);
1317 /// visitSwitchCase - Emits the necessary code to represent a single node in
1318 /// the binary search tree resulting from lowering a switch instruction.
1319 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1321 SDValue CondLHS = getValue(CB.CmpLHS);
1322 DebugLoc dl = getCurDebugLoc();
1324 // Build the setcc now.
1325 if (CB.CmpMHS == NULL) {
1326 // Fold "(X == true)" to X and "(X == false)" to !X to
1327 // handle common cases produced by branch lowering.
1328 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1330 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1331 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1332 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1334 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1336 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1338 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1339 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1341 SDValue CmpOp = getValue(CB.CmpMHS);
1342 MVT VT = CmpOp.getValueType();
1344 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1345 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1348 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1349 VT, CmpOp, DAG.getConstant(Low, VT));
1350 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1351 DAG.getConstant(High-Low, VT), ISD::SETULE);
1355 // Update successor info
1356 CurMBB->addSuccessor(CB.TrueBB);
1357 CurMBB->addSuccessor(CB.FalseBB);
1359 // Set NextBlock to be the MBB immediately after the current one, if any.
1360 // This is used to avoid emitting unnecessary branches to the next block.
1361 MachineBasicBlock *NextBlock = 0;
1362 MachineFunction::iterator BBI = CurMBB;
1363 if (++BBI != CurMBB->getParent()->end())
1366 // If the lhs block is the next block, invert the condition so that we can
1367 // fall through to the lhs instead of the rhs block.
1368 if (CB.TrueBB == NextBlock) {
1369 std::swap(CB.TrueBB, CB.FalseBB);
1370 SDValue True = DAG.getConstant(1, Cond.getValueType());
1371 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1373 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1374 MVT::Other, getControlRoot(), Cond,
1375 DAG.getBasicBlock(CB.TrueBB));
1377 // If the branch was constant folded, fix up the CFG.
1378 if (BrCond.getOpcode() == ISD::BR) {
1379 CurMBB->removeSuccessor(CB.FalseBB);
1380 DAG.setRoot(BrCond);
1382 // Otherwise, go ahead and insert the false branch.
1383 if (BrCond == getControlRoot())
1384 CurMBB->removeSuccessor(CB.TrueBB);
1386 if (CB.FalseBB == NextBlock)
1387 DAG.setRoot(BrCond);
1389 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1390 DAG.getBasicBlock(CB.FalseBB)));
1394 /// visitJumpTable - Emit JumpTable node in the current MBB
1395 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1396 // Emit the code for the jump table
1397 assert(JT.Reg != -1U && "Should lower JT Header first!");
1398 MVT PTy = TLI.getPointerTy();
1399 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1401 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1402 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1403 MVT::Other, Index.getValue(1),
1407 /// visitJumpTableHeader - This function emits necessary code to produce index
1408 /// in the JumpTable from switch case.
1409 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1410 JumpTableHeader &JTH) {
1411 // Subtract the lowest switch case value from the value being switched on and
1412 // conditional branch to default mbb if the result is greater than the
1413 // difference between smallest and largest cases.
1414 SDValue SwitchOp = getValue(JTH.SValue);
1415 MVT VT = SwitchOp.getValueType();
1416 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1417 DAG.getConstant(JTH.First, VT));
1419 // The SDNode we just created, which holds the value being switched on minus
1420 // the the smallest case value, needs to be copied to a virtual register so it
1421 // can be used as an index into the jump table in a subsequent basic block.
1422 // This value may be smaller or larger than the target's pointer type, and
1423 // therefore require extension or truncating.
1424 if (VT.bitsGT(TLI.getPointerTy()))
1425 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1426 TLI.getPointerTy(), SUB);
1428 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1429 TLI.getPointerTy(), SUB);
1431 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1432 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1433 JumpTableReg, SwitchOp);
1434 JT.Reg = JumpTableReg;
1436 // Emit the range check for the jump table, and branch to the default block
1437 // for the switch statement if the value being switched on exceeds the largest
1438 // case in the switch.
1439 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1440 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1441 DAG.getConstant(JTH.Last-JTH.First,VT),
1444 // Set NextBlock to be the MBB immediately after the current one, if any.
1445 // This is used to avoid emitting unnecessary branches to the next block.
1446 MachineBasicBlock *NextBlock = 0;
1447 MachineFunction::iterator BBI = CurMBB;
1448 if (++BBI != CurMBB->getParent()->end())
1451 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1452 MVT::Other, CopyTo, CMP,
1453 DAG.getBasicBlock(JT.Default));
1455 if (JT.MBB == NextBlock)
1456 DAG.setRoot(BrCond);
1458 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1459 DAG.getBasicBlock(JT.MBB)));
1462 /// visitBitTestHeader - This function emits necessary code to produce value
1463 /// suitable for "bit tests"
1464 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1465 // Subtract the minimum value
1466 SDValue SwitchOp = getValue(B.SValue);
1467 MVT VT = SwitchOp.getValueType();
1468 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1469 DAG.getConstant(B.First, VT));
1472 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1473 TLI.getSetCCResultType(SUB.getValueType()),
1474 SUB, DAG.getConstant(B.Range, VT),
1478 if (VT.bitsGT(TLI.getPointerTy()))
1479 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1480 TLI.getPointerTy(), SUB);
1482 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1483 TLI.getPointerTy(), SUB);
1485 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1486 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1489 // Set NextBlock to be the MBB immediately after the current one, if any.
1490 // This is used to avoid emitting unnecessary branches to the next block.
1491 MachineBasicBlock *NextBlock = 0;
1492 MachineFunction::iterator BBI = CurMBB;
1493 if (++BBI != CurMBB->getParent()->end())
1496 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1498 CurMBB->addSuccessor(B.Default);
1499 CurMBB->addSuccessor(MBB);
1501 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1502 MVT::Other, CopyTo, RangeCmp,
1503 DAG.getBasicBlock(B.Default));
1505 if (MBB == NextBlock)
1506 DAG.setRoot(BrRange);
1508 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1509 DAG.getBasicBlock(MBB)));
1512 /// visitBitTestCase - this function produces one "bit test"
1513 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1516 // Make desired shift
1517 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1518 TLI.getPointerTy());
1519 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1521 DAG.getConstant(1, TLI.getPointerTy()),
1524 // Emit bit tests and jumps
1525 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1526 TLI.getPointerTy(), SwitchVal,
1527 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1528 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1529 TLI.getSetCCResultType(AndOp.getValueType()),
1530 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1533 CurMBB->addSuccessor(B.TargetBB);
1534 CurMBB->addSuccessor(NextMBB);
1536 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1537 MVT::Other, getControlRoot(),
1538 AndCmp, DAG.getBasicBlock(B.TargetBB));
1540 // Set NextBlock to be the MBB immediately after the current one, if any.
1541 // This is used to avoid emitting unnecessary branches to the next block.
1542 MachineBasicBlock *NextBlock = 0;
1543 MachineFunction::iterator BBI = CurMBB;
1544 if (++BBI != CurMBB->getParent()->end())
1547 if (NextMBB == NextBlock)
1550 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1551 DAG.getBasicBlock(NextMBB)));
1554 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1555 // Retrieve successors.
1556 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1557 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1559 const Value *Callee(I.getCalledValue());
1560 if (isa<InlineAsm>(Callee))
1563 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1565 // If the value of the invoke is used outside of its defining block, make it
1566 // available as a virtual register.
1567 if (!I.use_empty()) {
1568 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1569 if (VMI != FuncInfo.ValueMap.end())
1570 CopyValueToVirtualRegister(&I, VMI->second);
1573 // Update successor info
1574 CurMBB->addSuccessor(Return);
1575 CurMBB->addSuccessor(LandingPad);
1577 // Drop into normal successor.
1578 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1579 MVT::Other, getControlRoot(),
1580 DAG.getBasicBlock(Return)));
1583 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1586 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1587 /// small case ranges).
1588 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1589 CaseRecVector& WorkList,
1591 MachineBasicBlock* Default) {
1592 Case& BackCase = *(CR.Range.second-1);
1594 // Size is the number of Cases represented by this range.
1595 size_t Size = CR.Range.second - CR.Range.first;
1599 // Get the MachineFunction which holds the current MBB. This is used when
1600 // inserting any additional MBBs necessary to represent the switch.
1601 MachineFunction *CurMF = CurMBB->getParent();
1603 // Figure out which block is immediately after the current one.
1604 MachineBasicBlock *NextBlock = 0;
1605 MachineFunction::iterator BBI = CR.CaseBB;
1607 if (++BBI != CurMBB->getParent()->end())
1610 // TODO: If any two of the cases has the same destination, and if one value
1611 // is the same as the other, but has one bit unset that the other has set,
1612 // use bit manipulation to do two compares at once. For example:
1613 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1615 // Rearrange the case blocks so that the last one falls through if possible.
1616 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1617 // The last case block won't fall through into 'NextBlock' if we emit the
1618 // branches in this order. See if rearranging a case value would help.
1619 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1620 if (I->BB == NextBlock) {
1621 std::swap(*I, BackCase);
1627 // Create a CaseBlock record representing a conditional branch to
1628 // the Case's target mbb if the value being switched on SV is equal
1630 MachineBasicBlock *CurBlock = CR.CaseBB;
1631 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1632 MachineBasicBlock *FallThrough;
1634 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1635 CurMF->insert(BBI, FallThrough);
1637 // If the last case doesn't match, go to the default block.
1638 FallThrough = Default;
1641 Value *RHS, *LHS, *MHS;
1643 if (I->High == I->Low) {
1644 // This is just small small case range :) containing exactly 1 case
1646 LHS = SV; RHS = I->High; MHS = NULL;
1649 LHS = I->Low; MHS = SV; RHS = I->High;
1651 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1653 // If emitting the first comparison, just call visitSwitchCase to emit the
1654 // code into the current block. Otherwise, push the CaseBlock onto the
1655 // vector to be later processed by SDISel, and insert the node's MBB
1656 // before the next MBB.
1657 if (CurBlock == CurMBB)
1658 visitSwitchCase(CB);
1660 SwitchCases.push_back(CB);
1662 CurBlock = FallThrough;
1668 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1669 return !DisableJumpTables &&
1670 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1671 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1674 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1675 APInt LastExt(Last), FirstExt(First);
1676 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1677 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1678 return (LastExt - FirstExt + 1ULL);
1681 /// handleJTSwitchCase - Emit jumptable for current switch case range
1682 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1683 CaseRecVector& WorkList,
1685 MachineBasicBlock* Default) {
1686 Case& FrontCase = *CR.Range.first;
1687 Case& BackCase = *(CR.Range.second-1);
1689 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1690 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1693 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1697 if (!areJTsAllowed(TLI) || TSize <= 3)
1700 APInt Range = ComputeRange(First, Last);
1701 double Density = (double)TSize / Range.roundToDouble();
1705 DEBUG(errs() << "Lowering jump table\n"
1706 << "First entry: " << First << ". Last entry: " << Last << '\n'
1707 << "Range: " << Range
1708 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1710 // Get the MachineFunction which holds the current MBB. This is used when
1711 // inserting any additional MBBs necessary to represent the switch.
1712 MachineFunction *CurMF = CurMBB->getParent();
1714 // Figure out which block is immediately after the current one.
1715 MachineBasicBlock *NextBlock = 0;
1716 MachineFunction::iterator BBI = CR.CaseBB;
1718 if (++BBI != CurMBB->getParent()->end())
1721 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1723 // Create a new basic block to hold the code for loading the address
1724 // of the jump table, and jumping to it. Update successor information;
1725 // we will either branch to the default case for the switch, or the jump
1727 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1728 CurMF->insert(BBI, JumpTableBB);
1729 CR.CaseBB->addSuccessor(Default);
1730 CR.CaseBB->addSuccessor(JumpTableBB);
1732 // Build a vector of destination BBs, corresponding to each target
1733 // of the jump table. If the value of the jump table slot corresponds to
1734 // a case statement, push the case's BB onto the vector, otherwise, push
1736 std::vector<MachineBasicBlock*> DestBBs;
1738 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1739 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1740 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1742 if (Low.sle(TEI) && TEI.sle(High)) {
1743 DestBBs.push_back(I->BB);
1747 DestBBs.push_back(Default);
1751 // Update successor info. Add one edge to each unique successor.
1752 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1753 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1754 E = DestBBs.end(); I != E; ++I) {
1755 if (!SuccsHandled[(*I)->getNumber()]) {
1756 SuccsHandled[(*I)->getNumber()] = true;
1757 JumpTableBB->addSuccessor(*I);
1761 // Create a jump table index for this jump table, or return an existing
1763 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1765 // Set the jump table information so that we can codegen it as a second
1766 // MachineBasicBlock
1767 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1768 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1769 if (CR.CaseBB == CurMBB)
1770 visitJumpTableHeader(JT, JTH);
1772 JTCases.push_back(JumpTableBlock(JTH, JT));
1777 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1779 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1780 CaseRecVector& WorkList,
1782 MachineBasicBlock* Default) {
1783 // Get the MachineFunction which holds the current MBB. This is used when
1784 // inserting any additional MBBs necessary to represent the switch.
1785 MachineFunction *CurMF = CurMBB->getParent();
1787 // Figure out which block is immediately after the current one.
1788 MachineBasicBlock *NextBlock = 0;
1789 MachineFunction::iterator BBI = CR.CaseBB;
1791 if (++BBI != CurMBB->getParent()->end())
1794 Case& FrontCase = *CR.Range.first;
1795 Case& BackCase = *(CR.Range.second-1);
1796 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1798 // Size is the number of Cases represented by this range.
1799 unsigned Size = CR.Range.second - CR.Range.first;
1801 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1802 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1804 CaseItr Pivot = CR.Range.first + Size/2;
1806 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1807 // (heuristically) allow us to emit JumpTable's later.
1809 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1813 size_t LSize = FrontCase.size();
1814 size_t RSize = TSize-LSize;
1815 DEBUG(errs() << "Selecting best pivot: \n"
1816 << "First: " << First << ", Last: " << Last <<'\n'
1817 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1818 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1820 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1821 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1822 APInt Range = ComputeRange(LEnd, RBegin);
1823 assert((Range - 2ULL).isNonNegative() &&
1824 "Invalid case distance");
1825 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1826 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1827 double Metric = Range.logBase2()*(LDensity+RDensity);
1828 // Should always split in some non-trivial place
1829 DEBUG(errs() <<"=>Step\n"
1830 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1831 << "LDensity: " << LDensity
1832 << ", RDensity: " << RDensity << '\n'
1833 << "Metric: " << Metric << '\n');
1834 if (FMetric < Metric) {
1837 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1843 if (areJTsAllowed(TLI)) {
1844 // If our case is dense we *really* should handle it earlier!
1845 assert((FMetric > 0) && "Should handle dense range earlier!");
1847 Pivot = CR.Range.first + Size/2;
1850 CaseRange LHSR(CR.Range.first, Pivot);
1851 CaseRange RHSR(Pivot, CR.Range.second);
1852 Constant *C = Pivot->Low;
1853 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1855 // We know that we branch to the LHS if the Value being switched on is
1856 // less than the Pivot value, C. We use this to optimize our binary
1857 // tree a bit, by recognizing that if SV is greater than or equal to the
1858 // LHS's Case Value, and that Case Value is exactly one less than the
1859 // Pivot's Value, then we can branch directly to the LHS's Target,
1860 // rather than creating a leaf node for it.
1861 if ((LHSR.second - LHSR.first) == 1 &&
1862 LHSR.first->High == CR.GE &&
1863 cast<ConstantInt>(C)->getValue() ==
1864 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1865 TrueBB = LHSR.first->BB;
1867 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1868 CurMF->insert(BBI, TrueBB);
1869 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1872 // Similar to the optimization above, if the Value being switched on is
1873 // known to be less than the Constant CR.LT, and the current Case Value
1874 // is CR.LT - 1, then we can branch directly to the target block for
1875 // the current Case Value, rather than emitting a RHS leaf node for it.
1876 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1877 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1878 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1879 FalseBB = RHSR.first->BB;
1881 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1882 CurMF->insert(BBI, FalseBB);
1883 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1886 // Create a CaseBlock record representing a conditional branch to
1887 // the LHS node if the value being switched on SV is less than C.
1888 // Otherwise, branch to LHS.
1889 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1891 if (CR.CaseBB == CurMBB)
1892 visitSwitchCase(CB);
1894 SwitchCases.push_back(CB);
1899 /// handleBitTestsSwitchCase - if current case range has few destination and
1900 /// range span less, than machine word bitwidth, encode case range into series
1901 /// of masks and emit bit tests with these masks.
1902 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1903 CaseRecVector& WorkList,
1905 MachineBasicBlock* Default){
1906 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1908 Case& FrontCase = *CR.Range.first;
1909 Case& BackCase = *(CR.Range.second-1);
1911 // Get the MachineFunction which holds the current MBB. This is used when
1912 // inserting any additional MBBs necessary to represent the switch.
1913 MachineFunction *CurMF = CurMBB->getParent();
1916 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1918 // Single case counts one, case range - two.
1919 numCmps += (I->Low == I->High ? 1 : 2);
1922 // Count unique destinations
1923 SmallSet<MachineBasicBlock*, 4> Dests;
1924 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1925 Dests.insert(I->BB);
1926 if (Dests.size() > 3)
1927 // Don't bother the code below, if there are too much unique destinations
1930 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1931 << "Total number of comparisons: " << numCmps << '\n');
1933 // Compute span of values.
1934 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1935 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1936 APInt cmpRange = maxValue - minValue;
1938 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1939 << "Low bound: " << minValue << '\n'
1940 << "High bound: " << maxValue << '\n');
1942 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1943 (!(Dests.size() == 1 && numCmps >= 3) &&
1944 !(Dests.size() == 2 && numCmps >= 5) &&
1945 !(Dests.size() >= 3 && numCmps >= 6)))
1948 DEBUG(errs() << "Emitting bit tests\n");
1949 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1951 // Optimize the case where all the case values fit in a
1952 // word without having to subtract minValue. In this case,
1953 // we can optimize away the subtraction.
1954 if (minValue.isNonNegative() &&
1955 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1956 cmpRange = maxValue;
1958 lowBound = minValue;
1961 CaseBitsVector CasesBits;
1962 unsigned i, count = 0;
1964 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1965 MachineBasicBlock* Dest = I->BB;
1966 for (i = 0; i < count; ++i)
1967 if (Dest == CasesBits[i].BB)
1971 assert((count < 3) && "Too much destinations to test!");
1972 CasesBits.push_back(CaseBits(0, Dest, 0));
1976 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1977 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1979 uint64_t lo = (lowValue - lowBound).getZExtValue();
1980 uint64_t hi = (highValue - lowBound).getZExtValue();
1982 for (uint64_t j = lo; j <= hi; j++) {
1983 CasesBits[i].Mask |= 1ULL << j;
1984 CasesBits[i].Bits++;
1988 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1992 // Figure out which block is immediately after the current one.
1993 MachineFunction::iterator BBI = CR.CaseBB;
1996 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1998 DEBUG(errs() << "Cases:\n");
1999 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2000 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2001 << ", Bits: " << CasesBits[i].Bits
2002 << ", BB: " << CasesBits[i].BB << '\n');
2004 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2005 CurMF->insert(BBI, CaseBB);
2006 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2011 BitTestBlock BTB(lowBound, cmpRange, SV,
2012 -1U, (CR.CaseBB == CurMBB),
2013 CR.CaseBB, Default, BTC);
2015 if (CR.CaseBB == CurMBB)
2016 visitBitTestHeader(BTB);
2018 BitTestCases.push_back(BTB);
2024 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2025 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2026 const SwitchInst& SI) {
2029 // Start with "simple" cases
2030 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2031 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2032 Cases.push_back(Case(SI.getSuccessorValue(i),
2033 SI.getSuccessorValue(i),
2036 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2038 // Merge case into clusters
2039 if (Cases.size() >= 2)
2040 // Must recompute end() each iteration because it may be
2041 // invalidated by erase if we hold on to it
2042 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2043 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2044 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2045 MachineBasicBlock* nextBB = J->BB;
2046 MachineBasicBlock* currentBB = I->BB;
2048 // If the two neighboring cases go to the same destination, merge them
2049 // into a single case.
2050 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2058 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2059 if (I->Low != I->High)
2060 // A range counts double, since it requires two compares.
2067 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2068 // Figure out which block is immediately after the current one.
2069 MachineBasicBlock *NextBlock = 0;
2070 MachineFunction::iterator BBI = CurMBB;
2072 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2074 // If there is only the default destination, branch to it if it is not the
2075 // next basic block. Otherwise, just fall through.
2076 if (SI.getNumOperands() == 2) {
2077 // Update machine-CFG edges.
2079 // If this is not a fall-through branch, emit the branch.
2080 CurMBB->addSuccessor(Default);
2081 if (Default != NextBlock)
2082 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2083 MVT::Other, getControlRoot(),
2084 DAG.getBasicBlock(Default)));
2088 // If there are any non-default case statements, create a vector of Cases
2089 // representing each one, and sort the vector so that we can efficiently
2090 // create a binary search tree from them.
2092 size_t numCmps = Clusterify(Cases, SI);
2093 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2094 << ". Total compares: " << numCmps << '\n');
2097 // Get the Value to be switched on and default basic blocks, which will be
2098 // inserted into CaseBlock records, representing basic blocks in the binary
2100 Value *SV = SI.getOperand(0);
2102 // Push the initial CaseRec onto the worklist
2103 CaseRecVector WorkList;
2104 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2106 while (!WorkList.empty()) {
2107 // Grab a record representing a case range to process off the worklist
2108 CaseRec CR = WorkList.back();
2109 WorkList.pop_back();
2111 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2114 // If the range has few cases (two or less) emit a series of specific
2116 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2119 // If the switch has more than 5 blocks, and at least 40% dense, and the
2120 // target supports indirect branches, then emit a jump table rather than
2121 // lowering the switch to a binary tree of conditional branches.
2122 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2125 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2126 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2127 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2132 void SelectionDAGLowering::visitSub(User &I) {
2133 // -0.0 - X --> fneg
2134 const Type *Ty = I.getType();
2135 if (isa<VectorType>(Ty)) {
2136 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2137 const VectorType *DestTy = cast<VectorType>(I.getType());
2138 const Type *ElTy = DestTy->getElementType();
2139 if (ElTy->isFloatingPoint()) {
2140 unsigned VL = DestTy->getNumElements();
2141 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2142 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2144 SDValue Op2 = getValue(I.getOperand(1));
2145 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2146 Op2.getValueType(), Op2));
2152 if (Ty->isFloatingPoint()) {
2153 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2154 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2155 SDValue Op2 = getValue(I.getOperand(1));
2156 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2157 Op2.getValueType(), Op2));
2162 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2165 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2166 SDValue Op1 = getValue(I.getOperand(0));
2167 SDValue Op2 = getValue(I.getOperand(1));
2169 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2170 Op1.getValueType(), Op1, Op2));
2173 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2174 SDValue Op1 = getValue(I.getOperand(0));
2175 SDValue Op2 = getValue(I.getOperand(1));
2176 if (!isa<VectorType>(I.getType())) {
2177 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2178 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2179 TLI.getPointerTy(), Op2);
2180 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2181 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2182 TLI.getPointerTy(), Op2);
2185 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2186 Op1.getValueType(), Op1, Op2));
2189 void SelectionDAGLowering::visitICmp(User &I) {
2190 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2191 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2192 predicate = IC->getPredicate();
2193 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2194 predicate = ICmpInst::Predicate(IC->getPredicate());
2195 SDValue Op1 = getValue(I.getOperand(0));
2196 SDValue Op2 = getValue(I.getOperand(1));
2197 ISD::CondCode Opcode = getICmpCondCode(predicate);
2198 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2201 void SelectionDAGLowering::visitFCmp(User &I) {
2202 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2203 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2204 predicate = FC->getPredicate();
2205 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2206 predicate = FCmpInst::Predicate(FC->getPredicate());
2207 SDValue Op1 = getValue(I.getOperand(0));
2208 SDValue Op2 = getValue(I.getOperand(1));
2209 ISD::CondCode Condition = getFCmpCondCode(predicate);
2210 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2213 void SelectionDAGLowering::visitVICmp(User &I) {
2214 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2215 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2216 predicate = IC->getPredicate();
2217 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2218 predicate = ICmpInst::Predicate(IC->getPredicate());
2219 SDValue Op1 = getValue(I.getOperand(0));
2220 SDValue Op2 = getValue(I.getOperand(1));
2221 ISD::CondCode Opcode = getICmpCondCode(predicate);
2222 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2226 void SelectionDAGLowering::visitVFCmp(User &I) {
2227 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2228 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2229 predicate = FC->getPredicate();
2230 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2231 predicate = FCmpInst::Predicate(FC->getPredicate());
2232 SDValue Op1 = getValue(I.getOperand(0));
2233 SDValue Op2 = getValue(I.getOperand(1));
2234 ISD::CondCode Condition = getFCmpCondCode(predicate);
2235 MVT DestVT = TLI.getValueType(I.getType());
2237 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2240 void SelectionDAGLowering::visitSelect(User &I) {
2241 SmallVector<MVT, 4> ValueVTs;
2242 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2243 unsigned NumValues = ValueVTs.size();
2244 if (NumValues != 0) {
2245 SmallVector<SDValue, 4> Values(NumValues);
2246 SDValue Cond = getValue(I.getOperand(0));
2247 SDValue TrueVal = getValue(I.getOperand(1));
2248 SDValue FalseVal = getValue(I.getOperand(2));
2250 for (unsigned i = 0; i != NumValues; ++i)
2251 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2252 TrueVal.getValueType(), Cond,
2253 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2254 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2256 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2257 DAG.getVTList(&ValueVTs[0], NumValues),
2258 &Values[0], NumValues));
2263 void SelectionDAGLowering::visitTrunc(User &I) {
2264 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2265 SDValue N = getValue(I.getOperand(0));
2266 MVT DestVT = TLI.getValueType(I.getType());
2267 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2270 void SelectionDAGLowering::visitZExt(User &I) {
2271 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2272 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2273 SDValue N = getValue(I.getOperand(0));
2274 MVT DestVT = TLI.getValueType(I.getType());
2275 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2278 void SelectionDAGLowering::visitSExt(User &I) {
2279 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2280 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2281 SDValue N = getValue(I.getOperand(0));
2282 MVT DestVT = TLI.getValueType(I.getType());
2283 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2286 void SelectionDAGLowering::visitFPTrunc(User &I) {
2287 // FPTrunc is never a no-op cast, no need to check
2288 SDValue N = getValue(I.getOperand(0));
2289 MVT DestVT = TLI.getValueType(I.getType());
2290 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2291 DestVT, N, DAG.getIntPtrConstant(0)));
2294 void SelectionDAGLowering::visitFPExt(User &I){
2295 // FPTrunc is never a no-op cast, no need to check
2296 SDValue N = getValue(I.getOperand(0));
2297 MVT DestVT = TLI.getValueType(I.getType());
2298 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2301 void SelectionDAGLowering::visitFPToUI(User &I) {
2302 // FPToUI is never a no-op cast, no need to check
2303 SDValue N = getValue(I.getOperand(0));
2304 MVT DestVT = TLI.getValueType(I.getType());
2305 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2308 void SelectionDAGLowering::visitFPToSI(User &I) {
2309 // FPToSI is never a no-op cast, no need to check
2310 SDValue N = getValue(I.getOperand(0));
2311 MVT DestVT = TLI.getValueType(I.getType());
2312 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2315 void SelectionDAGLowering::visitUIToFP(User &I) {
2316 // UIToFP is never a no-op cast, no need to check
2317 SDValue N = getValue(I.getOperand(0));
2318 MVT DestVT = TLI.getValueType(I.getType());
2319 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2322 void SelectionDAGLowering::visitSIToFP(User &I){
2323 // SIToFP is never a no-op cast, no need to check
2324 SDValue N = getValue(I.getOperand(0));
2325 MVT DestVT = TLI.getValueType(I.getType());
2326 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2329 void SelectionDAGLowering::visitPtrToInt(User &I) {
2330 // What to do depends on the size of the integer and the size of the pointer.
2331 // We can either truncate, zero extend, or no-op, accordingly.
2332 SDValue N = getValue(I.getOperand(0));
2333 MVT SrcVT = N.getValueType();
2334 MVT DestVT = TLI.getValueType(I.getType());
2336 if (DestVT.bitsLT(SrcVT))
2337 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2339 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2340 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2341 setValue(&I, Result);
2344 void SelectionDAGLowering::visitIntToPtr(User &I) {
2345 // What to do depends on the size of the integer and the size of the pointer.
2346 // We can either truncate, zero extend, or no-op, accordingly.
2347 SDValue N = getValue(I.getOperand(0));
2348 MVT SrcVT = N.getValueType();
2349 MVT DestVT = TLI.getValueType(I.getType());
2350 if (DestVT.bitsLT(SrcVT))
2351 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2353 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2354 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2358 void SelectionDAGLowering::visitBitCast(User &I) {
2359 SDValue N = getValue(I.getOperand(0));
2360 MVT DestVT = TLI.getValueType(I.getType());
2362 // BitCast assures us that source and destination are the same size so this
2363 // is either a BIT_CONVERT or a no-op.
2364 if (DestVT != N.getValueType())
2365 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2366 DestVT, N)); // convert types
2368 setValue(&I, N); // noop cast.
2371 void SelectionDAGLowering::visitInsertElement(User &I) {
2372 SDValue InVec = getValue(I.getOperand(0));
2373 SDValue InVal = getValue(I.getOperand(1));
2374 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2376 getValue(I.getOperand(2)));
2378 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2379 TLI.getValueType(I.getType()),
2380 InVec, InVal, InIdx));
2383 void SelectionDAGLowering::visitExtractElement(User &I) {
2384 SDValue InVec = getValue(I.getOperand(0));
2385 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2387 getValue(I.getOperand(1)));
2388 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2389 TLI.getValueType(I.getType()), InVec, InIdx));
2393 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2394 // from SIndx and increasing to the element length (undefs are allowed).
2395 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2396 unsigned MaskNumElts = Mask.getNumOperands();
2397 for (unsigned i = 0; i != MaskNumElts; ++i) {
2398 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2399 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2400 if (Idx != i + SIndx)
2407 void SelectionDAGLowering::visitShuffleVector(User &I) {
2408 SDValue Src1 = getValue(I.getOperand(0));
2409 SDValue Src2 = getValue(I.getOperand(1));
2410 SDValue Mask = getValue(I.getOperand(2));
2412 MVT VT = TLI.getValueType(I.getType());
2413 MVT SrcVT = Src1.getValueType();
2414 int MaskNumElts = Mask.getNumOperands();
2415 int SrcNumElts = SrcVT.getVectorNumElements();
2417 if (SrcNumElts == MaskNumElts) {
2418 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2419 VT, Src1, Src2, Mask));
2423 // Normalize the shuffle vector since mask and vector length don't match.
2424 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2426 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2427 // Mask is longer than the source vectors and is a multiple of the source
2428 // vectors. We can use concatenate vector to make the mask and vectors
2430 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2431 // The shuffle is concatenating two vectors together.
2432 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2437 // Pad both vectors with undefs to make them the same length as the mask.
2438 unsigned NumConcat = MaskNumElts / SrcNumElts;
2439 SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
2441 SDValue* MOps1 = new SDValue[NumConcat];
2442 SDValue* MOps2 = new SDValue[NumConcat];
2445 for (unsigned i = 1; i != NumConcat; ++i) {
2446 MOps1[i] = UndefVal;
2447 MOps2[i] = UndefVal;
2449 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2450 VT, MOps1, NumConcat);
2451 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2452 VT, MOps2, NumConcat);
2457 // Readjust mask for new input vector length.
2458 SmallVector<SDValue, 8> MappedOps;
2459 for (int i = 0; i != MaskNumElts; ++i) {
2460 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2461 MappedOps.push_back(Mask.getOperand(i));
2463 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2464 if (Idx < SrcNumElts)
2465 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2467 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2471 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2472 Mask.getValueType(),
2473 &MappedOps[0], MappedOps.size());
2475 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2476 VT, Src1, Src2, Mask));
2480 if (SrcNumElts > MaskNumElts) {
2481 // Resulting vector is shorter than the incoming vector.
2482 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2483 // Shuffle extracts 1st vector.
2488 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2489 // Shuffle extracts 2nd vector.
2494 // Analyze the access pattern of the vector to see if we can extract
2495 // two subvectors and do the shuffle. The analysis is done by calculating
2496 // the range of elements the mask access on both vectors.
2497 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2498 int MaxRange[2] = {-1, -1};
2500 for (int i = 0; i != MaskNumElts; ++i) {
2501 SDValue Arg = Mask.getOperand(i);
2502 if (Arg.getOpcode() != ISD::UNDEF) {
2503 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2504 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2506 if (Idx >= SrcNumElts) {
2510 if (Idx > MaxRange[Input])
2511 MaxRange[Input] = Idx;
2512 if (Idx < MinRange[Input])
2513 MinRange[Input] = Idx;
2517 // Check if the access is smaller than the vector size and can we find
2518 // a reasonable extract index.
2519 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2520 int StartIdx[2]; // StartIdx to extract from
2521 for (int Input=0; Input < 2; ++Input) {
2522 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2523 RangeUse[Input] = 0; // Unused
2524 StartIdx[Input] = 0;
2525 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2526 // Fits within range but we should see if we can find a good
2527 // start index that is a multiple of the mask length.
2528 if (MaxRange[Input] < MaskNumElts) {
2529 RangeUse[Input] = 1; // Extract from beginning of the vector
2530 StartIdx[Input] = 0;
2532 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2533 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2534 StartIdx[Input] + MaskNumElts < SrcNumElts)
2535 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2540 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2541 setValue(&I, DAG.getNode(ISD::UNDEF,
2542 getCurDebugLoc(), VT)); // Vectors are not used.
2545 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2546 // Extract appropriate subvector and generate a vector shuffle
2547 for (int Input=0; Input < 2; ++Input) {
2548 SDValue& Src = Input == 0 ? Src1 : Src2;
2549 if (RangeUse[Input] == 0) {
2550 Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
2552 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2553 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2556 // Calculate new mask.
2557 SmallVector<SDValue, 8> MappedOps;
2558 for (int i = 0; i != MaskNumElts; ++i) {
2559 SDValue Arg = Mask.getOperand(i);
2560 if (Arg.getOpcode() == ISD::UNDEF) {
2561 MappedOps.push_back(Arg);
2563 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2564 if (Idx < SrcNumElts)
2565 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2567 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2568 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2572 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2573 Mask.getValueType(),
2574 &MappedOps[0], MappedOps.size());
2575 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2576 VT, Src1, Src2, Mask));
2581 // We can't use either concat vectors or extract subvectors so fall back to
2582 // replacing the shuffle with extract and build vector.
2583 // to insert and build vector.
2584 MVT EltVT = VT.getVectorElementType();
2585 MVT PtrVT = TLI.getPointerTy();
2586 SmallVector<SDValue,8> Ops;
2587 for (int i = 0; i != MaskNumElts; ++i) {
2588 SDValue Arg = Mask.getOperand(i);
2589 if (Arg.getOpcode() == ISD::UNDEF) {
2590 Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
2592 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2593 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2594 if (Idx < SrcNumElts)
2595 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2596 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2598 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2600 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2603 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2604 VT, &Ops[0], Ops.size()));
2607 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2608 const Value *Op0 = I.getOperand(0);
2609 const Value *Op1 = I.getOperand(1);
2610 const Type *AggTy = I.getType();
2611 const Type *ValTy = Op1->getType();
2612 bool IntoUndef = isa<UndefValue>(Op0);
2613 bool FromUndef = isa<UndefValue>(Op1);
2615 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2616 I.idx_begin(), I.idx_end());
2618 SmallVector<MVT, 4> AggValueVTs;
2619 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2620 SmallVector<MVT, 4> ValValueVTs;
2621 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2623 unsigned NumAggValues = AggValueVTs.size();
2624 unsigned NumValValues = ValValueVTs.size();
2625 SmallVector<SDValue, 4> Values(NumAggValues);
2627 SDValue Agg = getValue(Op0);
2628 SDValue Val = getValue(Op1);
2630 // Copy the beginning value(s) from the original aggregate.
2631 for (; i != LinearIndex; ++i)
2632 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2634 SDValue(Agg.getNode(), Agg.getResNo() + i);
2635 // Copy values from the inserted value(s).
2636 for (; i != LinearIndex + NumValValues; ++i)
2637 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2639 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2640 // Copy remaining value(s) from the original aggregate.
2641 for (; i != NumAggValues; ++i)
2642 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2644 SDValue(Agg.getNode(), Agg.getResNo() + i);
2646 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2647 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2648 &Values[0], NumAggValues));
2651 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2652 const Value *Op0 = I.getOperand(0);
2653 const Type *AggTy = Op0->getType();
2654 const Type *ValTy = I.getType();
2655 bool OutOfUndef = isa<UndefValue>(Op0);
2657 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2658 I.idx_begin(), I.idx_end());
2660 SmallVector<MVT, 4> ValValueVTs;
2661 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2663 unsigned NumValValues = ValValueVTs.size();
2664 SmallVector<SDValue, 4> Values(NumValValues);
2666 SDValue Agg = getValue(Op0);
2667 // Copy out the selected value(s).
2668 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2669 Values[i - LinearIndex] =
2671 DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2672 Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2673 SDValue(Agg.getNode(), Agg.getResNo() + i);
2675 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2676 DAG.getVTList(&ValValueVTs[0], NumValValues),
2677 &Values[0], NumValValues));
2681 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2682 SDValue N = getValue(I.getOperand(0));
2683 const Type *Ty = I.getOperand(0)->getType();
2685 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2688 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2689 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2692 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2693 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2694 DAG.getIntPtrConstant(Offset));
2696 Ty = StTy->getElementType(Field);
2698 Ty = cast<SequentialType>(Ty)->getElementType();
2700 // If this is a constant subscript, handle it quickly.
2701 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2702 if (CI->getZExtValue() == 0) continue;
2704 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2705 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2706 DAG.getIntPtrConstant(Offs));
2710 // N = N + Idx * ElementSize;
2711 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2712 SDValue IdxN = getValue(Idx);
2714 // If the index is smaller or larger than intptr_t, truncate or extend
2716 if (IdxN.getValueType().bitsLT(N.getValueType()))
2717 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2718 N.getValueType(), IdxN);
2719 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2720 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2721 N.getValueType(), IdxN);
2723 // If this is a multiply by a power of two, turn it into a shl
2724 // immediately. This is a very common case.
2725 if (ElementSize != 1) {
2726 if (isPowerOf2_64(ElementSize)) {
2727 unsigned Amt = Log2_64(ElementSize);
2728 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2729 N.getValueType(), IdxN,
2730 DAG.getConstant(Amt, TLI.getPointerTy()));
2732 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2733 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2734 N.getValueType(), IdxN, Scale);
2738 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2739 N.getValueType(), N, IdxN);
2745 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2746 // If this is a fixed sized alloca in the entry block of the function,
2747 // allocate it statically on the stack.
2748 if (FuncInfo.StaticAllocaMap.count(&I))
2749 return; // getValue will auto-populate this.
2751 const Type *Ty = I.getAllocatedType();
2752 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2754 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2757 SDValue AllocSize = getValue(I.getArraySize());
2758 MVT IntPtr = TLI.getPointerTy();
2759 if (IntPtr.bitsLT(AllocSize.getValueType()))
2760 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2762 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2763 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2766 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
2767 DAG.getIntPtrConstant(TySize));
2769 // Handle alignment. If the requested alignment is less than or equal to
2770 // the stack alignment, ignore it. If the size is greater than or equal to
2771 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2772 unsigned StackAlign =
2773 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2774 if (Align <= StackAlign)
2777 // Round the size of the allocation up to the stack alignment size
2778 // by add SA-1 to the size.
2779 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2780 AllocSize.getValueType(), AllocSize,
2781 DAG.getIntPtrConstant(StackAlign-1));
2782 // Mask out the low bits for alignment purposes.
2783 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2784 AllocSize.getValueType(), AllocSize,
2785 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2787 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2788 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2790 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2793 DAG.setRoot(DSA.getValue(1));
2795 // Inform the Frame Information that we have just allocated a variable-sized
2797 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2800 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2801 const Value *SV = I.getOperand(0);
2802 SDValue Ptr = getValue(SV);
2804 const Type *Ty = I.getType();
2805 bool isVolatile = I.isVolatile();
2806 unsigned Alignment = I.getAlignment();
2808 SmallVector<MVT, 4> ValueVTs;
2809 SmallVector<uint64_t, 4> Offsets;
2810 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2811 unsigned NumValues = ValueVTs.size();
2816 bool ConstantMemory = false;
2818 // Serialize volatile loads with other side effects.
2820 else if (AA->pointsToConstantMemory(SV)) {
2821 // Do not serialize (non-volatile) loads of constant memory with anything.
2822 Root = DAG.getEntryNode();
2823 ConstantMemory = true;
2825 // Do not serialize non-volatile loads against each other.
2826 Root = DAG.getRoot();
2829 SmallVector<SDValue, 4> Values(NumValues);
2830 SmallVector<SDValue, 4> Chains(NumValues);
2831 MVT PtrVT = Ptr.getValueType();
2832 for (unsigned i = 0; i != NumValues; ++i) {
2833 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2834 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2836 DAG.getConstant(Offsets[i], PtrVT)),
2838 isVolatile, Alignment);
2840 Chains[i] = L.getValue(1);
2843 if (!ConstantMemory) {
2844 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2846 &Chains[0], NumValues);
2850 PendingLoads.push_back(Chain);
2853 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2854 DAG.getVTList(&ValueVTs[0], NumValues),
2855 &Values[0], NumValues));
2859 void SelectionDAGLowering::visitStore(StoreInst &I) {
2860 Value *SrcV = I.getOperand(0);
2861 Value *PtrV = I.getOperand(1);
2863 SmallVector<MVT, 4> ValueVTs;
2864 SmallVector<uint64_t, 4> Offsets;
2865 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2866 unsigned NumValues = ValueVTs.size();
2870 // Get the lowered operands. Note that we do this after
2871 // checking if NumResults is zero, because with zero results
2872 // the operands won't have values in the map.
2873 SDValue Src = getValue(SrcV);
2874 SDValue Ptr = getValue(PtrV);
2876 SDValue Root = getRoot();
2877 SmallVector<SDValue, 4> Chains(NumValues);
2878 MVT PtrVT = Ptr.getValueType();
2879 bool isVolatile = I.isVolatile();
2880 unsigned Alignment = I.getAlignment();
2881 for (unsigned i = 0; i != NumValues; ++i)
2882 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2883 SDValue(Src.getNode(), Src.getResNo() + i),
2884 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2886 DAG.getConstant(Offsets[i], PtrVT)),
2888 isVolatile, Alignment);
2890 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2891 MVT::Other, &Chains[0], NumValues));
2894 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2896 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2897 unsigned Intrinsic) {
2898 bool HasChain = !I.doesNotAccessMemory();
2899 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2901 // Build the operand list.
2902 SmallVector<SDValue, 8> Ops;
2903 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2905 // We don't need to serialize loads against other loads.
2906 Ops.push_back(DAG.getRoot());
2908 Ops.push_back(getRoot());
2912 // Info is set by getTgtMemInstrinsic
2913 TargetLowering::IntrinsicInfo Info;
2914 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2916 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2917 if (!IsTgtIntrinsic)
2918 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2920 // Add all operands of the call to the operand list.
2921 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2922 SDValue Op = getValue(I.getOperand(i));
2923 assert(TLI.isTypeLegal(Op.getValueType()) &&
2924 "Intrinsic uses a non-legal type?");
2928 std::vector<MVT> VTs;
2929 if (I.getType() != Type::VoidTy) {
2930 MVT VT = TLI.getValueType(I.getType());
2931 if (VT.isVector()) {
2932 const VectorType *DestTy = cast<VectorType>(I.getType());
2933 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2935 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2936 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2939 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2943 VTs.push_back(MVT::Other);
2945 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2949 if (IsTgtIntrinsic) {
2950 // This is target intrinsic that touches memory
2951 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2953 &Ops[0], Ops.size(),
2954 Info.memVT, Info.ptrVal, Info.offset,
2955 Info.align, Info.vol,
2956 Info.readMem, Info.writeMem);
2959 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2961 &Ops[0], Ops.size());
2962 else if (I.getType() != Type::VoidTy)
2963 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2965 &Ops[0], Ops.size());
2967 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2969 &Ops[0], Ops.size());
2972 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2974 PendingLoads.push_back(Chain);
2978 if (I.getType() != Type::VoidTy) {
2979 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2980 MVT VT = TLI.getValueType(PTy);
2981 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2983 setValue(&I, Result);
2987 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2988 static GlobalVariable *ExtractTypeInfo(Value *V) {
2989 V = V->stripPointerCasts();
2990 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2991 assert ((GV || isa<ConstantPointerNull>(V)) &&
2992 "TypeInfo must be a global variable or NULL");
2998 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2999 /// call, and add them to the specified machine basic block.
3000 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3001 MachineBasicBlock *MBB) {
3002 // Inform the MachineModuleInfo of the personality for this landing pad.
3003 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3004 assert(CE->getOpcode() == Instruction::BitCast &&
3005 isa<Function>(CE->getOperand(0)) &&
3006 "Personality should be a function");
3007 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3009 // Gather all the type infos for this landing pad and pass them along to
3010 // MachineModuleInfo.
3011 std::vector<GlobalVariable *> TyInfo;
3012 unsigned N = I.getNumOperands();
3014 for (unsigned i = N - 1; i > 2; --i) {
3015 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3016 unsigned FilterLength = CI->getZExtValue();
3017 unsigned FirstCatch = i + FilterLength + !FilterLength;
3018 assert (FirstCatch <= N && "Invalid filter length");
3020 if (FirstCatch < N) {
3021 TyInfo.reserve(N - FirstCatch);
3022 for (unsigned j = FirstCatch; j < N; ++j)
3023 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3024 MMI->addCatchTypeInfo(MBB, TyInfo);
3028 if (!FilterLength) {
3030 MMI->addCleanup(MBB);
3033 TyInfo.reserve(FilterLength - 1);
3034 for (unsigned j = i + 1; j < FirstCatch; ++j)
3035 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3036 MMI->addFilterTypeInfo(MBB, TyInfo);
3045 TyInfo.reserve(N - 3);
3046 for (unsigned j = 3; j < N; ++j)
3047 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3048 MMI->addCatchTypeInfo(MBB, TyInfo);
3054 /// GetSignificand - Get the significand and build it into a floating-point
3055 /// number with exponent of 1:
3057 /// Op = (Op & 0x007fffff) | 0x3f800000;
3059 /// where Op is the hexidecimal representation of floating point value.
3061 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3062 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3063 DAG.getConstant(0x007fffff, MVT::i32));
3064 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3065 DAG.getConstant(0x3f800000, MVT::i32));
3066 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3069 /// GetExponent - Get the exponent:
3071 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3073 /// where Op is the hexidecimal representation of floating point value.
3075 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3077 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3078 DAG.getConstant(0x7f800000, MVT::i32));
3079 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3080 DAG.getConstant(23, TLI.getPointerTy()));
3081 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3082 DAG.getConstant(127, MVT::i32));
3083 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3086 /// getF32Constant - Get 32-bit floating point constant.
3088 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3089 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3092 /// Inlined utility function to implement binary input atomic intrinsics for
3093 /// visitIntrinsicCall: I is a call instruction
3094 /// Op is the associated NodeType for I
3096 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3097 SDValue Root = getRoot();
3099 DAG.getAtomic(Op, getCurDebugLoc(),
3100 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3102 getValue(I.getOperand(1)),
3103 getValue(I.getOperand(2)),
3106 DAG.setRoot(L.getValue(1));
3110 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3112 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3113 SDValue Op1 = getValue(I.getOperand(1));
3114 SDValue Op2 = getValue(I.getOperand(2));
3116 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3117 SDValue Ops[] = { Op1, Op2 };
3119 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
3120 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
3122 setValue(&I, Result);
3126 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3127 /// limited-precision mode.
3129 SelectionDAGLowering::visitExp(CallInst &I) {
3131 DebugLoc dl = getCurDebugLoc();
3133 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3134 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3135 SDValue Op = getValue(I.getOperand(1));
3137 // Put the exponent in the right bit position for later addition to the
3140 // #define LOG2OFe 1.4426950f
3141 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3142 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3143 getF32Constant(DAG, 0x3fb8aa3b));
3144 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3146 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3147 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3148 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3150 // IntegerPartOfX <<= 23;
3151 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3152 DAG.getConstant(23, TLI.getPointerTy()));
3154 if (LimitFloatPrecision <= 6) {
3155 // For floating-point precision of 6:
3157 // TwoToFractionalPartOfX =
3159 // (0.735607626f + 0.252464424f * x) * x;
3161 // error 0.0144103317, which is 6 bits
3162 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3163 getF32Constant(DAG, 0x3e814304));
3164 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3165 getF32Constant(DAG, 0x3f3c50c8));
3166 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3167 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3168 getF32Constant(DAG, 0x3f7f5e7e));
3169 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3171 // Add the exponent into the result in integer domain.
3172 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3173 TwoToFracPartOfX, IntegerPartOfX);
3175 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3176 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3177 // For floating-point precision of 12:
3179 // TwoToFractionalPartOfX =
3182 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3184 // 0.000107046256 error, which is 13 to 14 bits
3185 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3186 getF32Constant(DAG, 0x3da235e3));
3187 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3188 getF32Constant(DAG, 0x3e65b8f3));
3189 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3190 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3191 getF32Constant(DAG, 0x3f324b07));
3192 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3193 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3194 getF32Constant(DAG, 0x3f7ff8fd));
3195 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3197 // Add the exponent into the result in integer domain.
3198 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3199 TwoToFracPartOfX, IntegerPartOfX);
3201 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3202 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3203 // For floating-point precision of 18:
3205 // TwoToFractionalPartOfX =
3209 // (0.554906021e-1f +
3210 // (0.961591928e-2f +
3211 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3213 // error 2.47208000*10^(-7), which is better than 18 bits
3214 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3215 getF32Constant(DAG, 0x3924b03e));
3216 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3217 getF32Constant(DAG, 0x3ab24b87));
3218 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3219 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3220 getF32Constant(DAG, 0x3c1d8c17));
3221 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3222 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3223 getF32Constant(DAG, 0x3d634a1d));
3224 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3225 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3226 getF32Constant(DAG, 0x3e75fe14));
3227 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3228 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3229 getF32Constant(DAG, 0x3f317234));
3230 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3231 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3232 getF32Constant(DAG, 0x3f800000));
3233 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3236 // Add the exponent into the result in integer domain.
3237 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3238 TwoToFracPartOfX, IntegerPartOfX);
3240 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3243 // No special expansion.
3244 result = DAG.getNode(ISD::FEXP, dl,
3245 getValue(I.getOperand(1)).getValueType(),
3246 getValue(I.getOperand(1)));
3249 setValue(&I, result);
3252 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3253 /// limited-precision mode.
3255 SelectionDAGLowering::visitLog(CallInst &I) {
3257 DebugLoc dl = getCurDebugLoc();
3259 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3260 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3261 SDValue Op = getValue(I.getOperand(1));
3262 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3264 // Scale the exponent by log(2) [0.69314718f].
3265 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3266 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3267 getF32Constant(DAG, 0x3f317218));
3269 // Get the significand and build it into a floating-point number with
3271 SDValue X = GetSignificand(DAG, Op1, dl);
3273 if (LimitFloatPrecision <= 6) {
3274 // For floating-point precision of 6:
3278 // (1.4034025f - 0.23903021f * x) * x;
3280 // error 0.0034276066, which is better than 8 bits
3281 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3282 getF32Constant(DAG, 0xbe74c456));
3283 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3284 getF32Constant(DAG, 0x3fb3a2b1));
3285 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3286 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3287 getF32Constant(DAG, 0x3f949a29));
3289 result = DAG.getNode(ISD::FADD, dl,
3290 MVT::f32, LogOfExponent, LogOfMantissa);
3291 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3292 // For floating-point precision of 12:
3298 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3300 // error 0.000061011436, which is 14 bits
3301 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3302 getF32Constant(DAG, 0xbd67b6d6));
3303 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3304 getF32Constant(DAG, 0x3ee4f4b8));
3305 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3306 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3307 getF32Constant(DAG, 0x3fbc278b));
3308 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3309 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3310 getF32Constant(DAG, 0x40348e95));
3311 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3312 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3313 getF32Constant(DAG, 0x3fdef31a));
3315 result = DAG.getNode(ISD::FADD, dl,
3316 MVT::f32, LogOfExponent, LogOfMantissa);
3317 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3318 // For floating-point precision of 18:
3326 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3328 // error 0.0000023660568, which is better than 18 bits
3329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3330 getF32Constant(DAG, 0xbc91e5ac));
3331 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3332 getF32Constant(DAG, 0x3e4350aa));
3333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3334 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3335 getF32Constant(DAG, 0x3f60d3e3));
3336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3337 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3338 getF32Constant(DAG, 0x4011cdf0));
3339 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3340 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3341 getF32Constant(DAG, 0x406cfd1c));
3342 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3343 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3344 getF32Constant(DAG, 0x408797cb));
3345 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3346 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3347 getF32Constant(DAG, 0x4006dcab));
3349 result = DAG.getNode(ISD::FADD, dl,
3350 MVT::f32, LogOfExponent, LogOfMantissa);
3353 // No special expansion.
3354 result = DAG.getNode(ISD::FLOG, dl,
3355 getValue(I.getOperand(1)).getValueType(),
3356 getValue(I.getOperand(1)));
3359 setValue(&I, result);
3362 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3363 /// limited-precision mode.
3365 SelectionDAGLowering::visitLog2(CallInst &I) {
3367 DebugLoc dl = getCurDebugLoc();
3369 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3370 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3371 SDValue Op = getValue(I.getOperand(1));
3372 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3374 // Get the exponent.
3375 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3377 // Get the significand and build it into a floating-point number with
3379 SDValue X = GetSignificand(DAG, Op1, dl);
3381 // Different possible minimax approximations of significand in
3382 // floating-point for various degrees of accuracy over [1,2].
3383 if (LimitFloatPrecision <= 6) {
3384 // For floating-point precision of 6:
3386 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3388 // error 0.0049451742, which is more than 7 bits
3389 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3390 getF32Constant(DAG, 0xbeb08fe0));
3391 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3392 getF32Constant(DAG, 0x40019463));
3393 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3394 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3395 getF32Constant(DAG, 0x3fd6633d));
3397 result = DAG.getNode(ISD::FADD, dl,
3398 MVT::f32, LogOfExponent, Log2ofMantissa);
3399 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3400 // For floating-point precision of 12:
3406 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3408 // error 0.0000876136000, which is better than 13 bits
3409 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3410 getF32Constant(DAG, 0xbda7262e));
3411 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3412 getF32Constant(DAG, 0x3f25280b));
3413 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3414 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3415 getF32Constant(DAG, 0x4007b923));
3416 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3417 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3418 getF32Constant(DAG, 0x40823e2f));
3419 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3420 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3421 getF32Constant(DAG, 0x4020d29c));
3423 result = DAG.getNode(ISD::FADD, dl,
3424 MVT::f32, LogOfExponent, Log2ofMantissa);
3425 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3426 // For floating-point precision of 18:
3435 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3437 // error 0.0000018516, which is better than 18 bits
3438 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3439 getF32Constant(DAG, 0xbcd2769e));
3440 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3441 getF32Constant(DAG, 0x3e8ce0b9));
3442 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3443 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3444 getF32Constant(DAG, 0x3fa22ae7));
3445 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3446 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3447 getF32Constant(DAG, 0x40525723));
3448 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3449 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3450 getF32Constant(DAG, 0x40aaf200));
3451 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3452 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3453 getF32Constant(DAG, 0x40c39dad));
3454 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3455 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3456 getF32Constant(DAG, 0x4042902c));
3458 result = DAG.getNode(ISD::FADD, dl,
3459 MVT::f32, LogOfExponent, Log2ofMantissa);
3462 // No special expansion.
3463 result = DAG.getNode(ISD::FLOG2, dl,
3464 getValue(I.getOperand(1)).getValueType(),
3465 getValue(I.getOperand(1)));
3468 setValue(&I, result);
3471 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3472 /// limited-precision mode.
3474 SelectionDAGLowering::visitLog10(CallInst &I) {
3476 DebugLoc dl = getCurDebugLoc();
3478 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3479 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3480 SDValue Op = getValue(I.getOperand(1));
3481 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3483 // Scale the exponent by log10(2) [0.30102999f].
3484 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3485 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3486 getF32Constant(DAG, 0x3e9a209a));
3488 // Get the significand and build it into a floating-point number with
3490 SDValue X = GetSignificand(DAG, Op1, dl);
3492 if (LimitFloatPrecision <= 6) {
3493 // For floating-point precision of 6:
3495 // Log10ofMantissa =
3497 // (0.60948995f - 0.10380950f * x) * x;
3499 // error 0.0014886165, which is 6 bits
3500 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3501 getF32Constant(DAG, 0xbdd49a13));
3502 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3503 getF32Constant(DAG, 0x3f1c0789));
3504 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3505 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3506 getF32Constant(DAG, 0x3f011300));
3508 result = DAG.getNode(ISD::FADD, dl,
3509 MVT::f32, LogOfExponent, Log10ofMantissa);
3510 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3511 // For floating-point precision of 12:
3513 // Log10ofMantissa =
3516 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3518 // error 0.00019228036, which is better than 12 bits
3519 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3520 getF32Constant(DAG, 0x3d431f31));
3521 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3522 getF32Constant(DAG, 0x3ea21fb2));
3523 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3524 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3525 getF32Constant(DAG, 0x3f6ae232));
3526 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3527 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3528 getF32Constant(DAG, 0x3f25f7c3));
3530 result = DAG.getNode(ISD::FADD, dl,
3531 MVT::f32, LogOfExponent, Log10ofMantissa);
3532 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3533 // For floating-point precision of 18:
3535 // Log10ofMantissa =
3540 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3542 // error 0.0000037995730, which is better than 18 bits
3543 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3544 getF32Constant(DAG, 0x3c5d51ce));
3545 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3546 getF32Constant(DAG, 0x3e00685a));
3547 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3548 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3549 getF32Constant(DAG, 0x3efb6798));
3550 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3551 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3552 getF32Constant(DAG, 0x3f88d192));
3553 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3554 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3555 getF32Constant(DAG, 0x3fc4316c));
3556 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3557 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3558 getF32Constant(DAG, 0x3f57ce70));
3560 result = DAG.getNode(ISD::FADD, dl,
3561 MVT::f32, LogOfExponent, Log10ofMantissa);
3564 // No special expansion.
3565 result = DAG.getNode(ISD::FLOG10, dl,
3566 getValue(I.getOperand(1)).getValueType(),
3567 getValue(I.getOperand(1)));
3570 setValue(&I, result);
3573 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3574 /// limited-precision mode.
3576 SelectionDAGLowering::visitExp2(CallInst &I) {
3578 DebugLoc dl = getCurDebugLoc();
3580 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3581 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3582 SDValue Op = getValue(I.getOperand(1));
3584 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3586 // FractionalPartOfX = x - (float)IntegerPartOfX;
3587 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3588 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3590 // IntegerPartOfX <<= 23;
3591 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3592 DAG.getConstant(23, TLI.getPointerTy()));
3594 if (LimitFloatPrecision <= 6) {
3595 // For floating-point precision of 6:
3597 // TwoToFractionalPartOfX =
3599 // (0.735607626f + 0.252464424f * x) * x;
3601 // error 0.0144103317, which is 6 bits
3602 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3603 getF32Constant(DAG, 0x3e814304));
3604 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3605 getF32Constant(DAG, 0x3f3c50c8));
3606 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3607 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3608 getF32Constant(DAG, 0x3f7f5e7e));
3609 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3610 SDValue TwoToFractionalPartOfX =
3611 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3613 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3614 MVT::f32, TwoToFractionalPartOfX);
3615 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3616 // For floating-point precision of 12:
3618 // TwoToFractionalPartOfX =
3621 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3623 // error 0.000107046256, which is 13 to 14 bits
3624 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3625 getF32Constant(DAG, 0x3da235e3));
3626 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3627 getF32Constant(DAG, 0x3e65b8f3));
3628 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3629 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3630 getF32Constant(DAG, 0x3f324b07));
3631 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3632 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3633 getF32Constant(DAG, 0x3f7ff8fd));
3634 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3635 SDValue TwoToFractionalPartOfX =
3636 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3638 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3639 MVT::f32, TwoToFractionalPartOfX);
3640 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3641 // For floating-point precision of 18:
3643 // TwoToFractionalPartOfX =
3647 // (0.554906021e-1f +
3648 // (0.961591928e-2f +
3649 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3650 // error 2.47208000*10^(-7), which is better than 18 bits
3651 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3652 getF32Constant(DAG, 0x3924b03e));
3653 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3654 getF32Constant(DAG, 0x3ab24b87));
3655 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3656 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3657 getF32Constant(DAG, 0x3c1d8c17));
3658 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3659 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3660 getF32Constant(DAG, 0x3d634a1d));
3661 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3662 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3663 getF32Constant(DAG, 0x3e75fe14));
3664 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3665 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3666 getF32Constant(DAG, 0x3f317234));
3667 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3668 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3669 getF32Constant(DAG, 0x3f800000));
3670 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3671 SDValue TwoToFractionalPartOfX =
3672 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3674 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3675 MVT::f32, TwoToFractionalPartOfX);
3678 // No special expansion.
3679 result = DAG.getNode(ISD::FEXP2, dl,
3680 getValue(I.getOperand(1)).getValueType(),
3681 getValue(I.getOperand(1)));
3684 setValue(&I, result);
3687 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3688 /// limited-precision mode with x == 10.0f.
3690 SelectionDAGLowering::visitPow(CallInst &I) {
3692 Value *Val = I.getOperand(1);
3693 DebugLoc dl = getCurDebugLoc();
3694 bool IsExp10 = false;
3696 if (getValue(Val).getValueType() == MVT::f32 &&
3697 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3698 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3699 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3700 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3702 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3707 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3708 SDValue Op = getValue(I.getOperand(2));
3710 // Put the exponent in the right bit position for later addition to the
3713 // #define LOG2OF10 3.3219281f
3714 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3715 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3716 getF32Constant(DAG, 0x40549a78));
3717 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3719 // FractionalPartOfX = x - (float)IntegerPartOfX;
3720 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3721 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3723 // IntegerPartOfX <<= 23;
3724 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3725 DAG.getConstant(23, TLI.getPointerTy()));
3727 if (LimitFloatPrecision <= 6) {
3728 // For floating-point precision of 6:
3730 // twoToFractionalPartOfX =
3732 // (0.735607626f + 0.252464424f * x) * x;
3734 // error 0.0144103317, which is 6 bits
3735 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3736 getF32Constant(DAG, 0x3e814304));
3737 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3738 getF32Constant(DAG, 0x3f3c50c8));
3739 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3740 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3741 getF32Constant(DAG, 0x3f7f5e7e));
3742 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3743 SDValue TwoToFractionalPartOfX =
3744 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3746 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3747 MVT::f32, TwoToFractionalPartOfX);
3748 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3749 // For floating-point precision of 12:
3751 // TwoToFractionalPartOfX =
3754 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3756 // error 0.000107046256, which is 13 to 14 bits
3757 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3758 getF32Constant(DAG, 0x3da235e3));
3759 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3760 getF32Constant(DAG, 0x3e65b8f3));
3761 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3762 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3763 getF32Constant(DAG, 0x3f324b07));
3764 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3765 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3766 getF32Constant(DAG, 0x3f7ff8fd));
3767 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3768 SDValue TwoToFractionalPartOfX =
3769 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3771 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3772 MVT::f32, TwoToFractionalPartOfX);
3773 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3774 // For floating-point precision of 18:
3776 // TwoToFractionalPartOfX =
3780 // (0.554906021e-1f +
3781 // (0.961591928e-2f +
3782 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3783 // error 2.47208000*10^(-7), which is better than 18 bits
3784 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3785 getF32Constant(DAG, 0x3924b03e));
3786 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3787 getF32Constant(DAG, 0x3ab24b87));
3788 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3789 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3790 getF32Constant(DAG, 0x3c1d8c17));
3791 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3792 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3793 getF32Constant(DAG, 0x3d634a1d));
3794 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3795 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3796 getF32Constant(DAG, 0x3e75fe14));
3797 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3798 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3799 getF32Constant(DAG, 0x3f317234));
3800 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3801 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3802 getF32Constant(DAG, 0x3f800000));
3803 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3804 SDValue TwoToFractionalPartOfX =
3805 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3807 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3808 MVT::f32, TwoToFractionalPartOfX);
3811 // No special expansion.
3812 result = DAG.getNode(ISD::FPOW, dl,
3813 getValue(I.getOperand(1)).getValueType(),
3814 getValue(I.getOperand(1)),
3815 getValue(I.getOperand(2)));
3818 setValue(&I, result);
3821 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3822 /// we want to emit this as a call to a named external function, return the name
3823 /// otherwise lower it and return null.
3825 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3826 DebugLoc dl = getCurDebugLoc();
3827 switch (Intrinsic) {
3829 // By default, turn this into a target intrinsic node.
3830 visitTargetIntrinsic(I, Intrinsic);
3832 case Intrinsic::vastart: visitVAStart(I); return 0;
3833 case Intrinsic::vaend: visitVAEnd(I); return 0;
3834 case Intrinsic::vacopy: visitVACopy(I); return 0;
3835 case Intrinsic::returnaddress:
3836 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3837 getValue(I.getOperand(1))));
3839 case Intrinsic::frameaddress:
3840 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3841 getValue(I.getOperand(1))));
3843 case Intrinsic::setjmp:
3844 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3846 case Intrinsic::longjmp:
3847 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3849 case Intrinsic::memcpy: {
3850 SDValue Op1 = getValue(I.getOperand(1));
3851 SDValue Op2 = getValue(I.getOperand(2));
3852 SDValue Op3 = getValue(I.getOperand(3));
3853 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3854 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3855 I.getOperand(1), 0, I.getOperand(2), 0));
3858 case Intrinsic::memset: {
3859 SDValue Op1 = getValue(I.getOperand(1));
3860 SDValue Op2 = getValue(I.getOperand(2));
3861 SDValue Op3 = getValue(I.getOperand(3));
3862 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3863 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3864 I.getOperand(1), 0));
3867 case Intrinsic::memmove: {
3868 SDValue Op1 = getValue(I.getOperand(1));
3869 SDValue Op2 = getValue(I.getOperand(2));
3870 SDValue Op3 = getValue(I.getOperand(3));
3871 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3873 // If the source and destination are known to not be aliases, we can
3874 // lower memmove as memcpy.
3875 uint64_t Size = -1ULL;
3876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3877 Size = C->getZExtValue();
3878 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3879 AliasAnalysis::NoAlias) {
3880 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3881 I.getOperand(1), 0, I.getOperand(2), 0));
3885 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3886 I.getOperand(1), 0, I.getOperand(2), 0));
3889 case Intrinsic::dbg_stoppoint: {
3890 DwarfWriter *DW = DAG.getDwarfWriter();
3891 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3892 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
3893 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3897 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3898 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3899 unsigned idx = DAG.getMachineFunction().
3900 getOrCreateDebugLocID(SrcFile,
3903 setCurDebugLoc(DebugLoc::get(idx));
3907 case Intrinsic::dbg_region_start: {
3908 DwarfWriter *DW = DAG.getDwarfWriter();
3909 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3910 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
3912 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3913 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3914 getRoot(), LabelID));
3919 case Intrinsic::dbg_region_end: {
3920 DwarfWriter *DW = DAG.getDwarfWriter();
3921 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3922 if (DW && DW->ValidDebugInfo(REI.getContext())) {
3924 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3925 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3926 getRoot(), LabelID));
3931 case Intrinsic::dbg_func_start: {
3932 DwarfWriter *DW = DAG.getDwarfWriter();
3934 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3935 Value *SP = FSI.getSubprogram();
3936 if (SP && DW->ValidDebugInfo(SP)) {
3937 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3938 // what (most?) gdb expects.
3939 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3940 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3941 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3942 CompileUnit.getFilename());
3944 // Record the source line but does not create a label for the normal
3945 // function start. It will be emitted at asm emission time. However,
3946 // create a label if this is a beginning of inlined function.
3947 unsigned Line = Subprogram.getLineNumber();
3948 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3950 if (DW->getRecordSourceLineCount() != 1)
3951 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3952 getRoot(), LabelID));
3954 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
3955 getOrCreateDebugLocID(SrcFile, Line, 0)));
3960 case Intrinsic::dbg_declare: {
3961 DwarfWriter *DW = DAG.getDwarfWriter();
3962 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3963 Value *Variable = DI.getVariable();
3964 if (DW && DW->ValidDebugInfo(Variable))
3965 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3966 getValue(DI.getAddress()), getValue(Variable)));
3970 case Intrinsic::eh_exception: {
3971 if (!CurMBB->isLandingPad()) {
3972 // FIXME: Mark exception register as live in. Hack for PR1508.
3973 unsigned Reg = TLI.getExceptionAddressRegister();
3974 if (Reg) CurMBB->addLiveIn(Reg);
3976 // Insert the EXCEPTIONADDR instruction.
3977 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3979 Ops[0] = DAG.getRoot();
3980 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3982 DAG.setRoot(Op.getValue(1));
3986 case Intrinsic::eh_selector_i32:
3987 case Intrinsic::eh_selector_i64: {
3988 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3989 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3990 MVT::i32 : MVT::i64);
3993 if (CurMBB->isLandingPad())
3994 AddCatchInfo(I, MMI, CurMBB);
3997 FuncInfo.CatchInfoLost.insert(&I);
3999 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4000 unsigned Reg = TLI.getExceptionSelectorRegister();
4001 if (Reg) CurMBB->addLiveIn(Reg);
4004 // Insert the EHSELECTION instruction.
4005 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4007 Ops[0] = getValue(I.getOperand(1));
4009 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4011 DAG.setRoot(Op.getValue(1));
4013 setValue(&I, DAG.getConstant(0, VT));
4019 case Intrinsic::eh_typeid_for_i32:
4020 case Intrinsic::eh_typeid_for_i64: {
4021 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4022 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4023 MVT::i32 : MVT::i64);
4026 // Find the type id for the given typeinfo.
4027 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4029 unsigned TypeID = MMI->getTypeIDFor(GV);
4030 setValue(&I, DAG.getConstant(TypeID, VT));
4032 // Return something different to eh_selector.
4033 setValue(&I, DAG.getConstant(1, VT));
4039 case Intrinsic::eh_return_i32:
4040 case Intrinsic::eh_return_i64:
4041 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4042 MMI->setCallsEHReturn(true);
4043 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4046 getValue(I.getOperand(1)),
4047 getValue(I.getOperand(2))));
4049 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4053 case Intrinsic::eh_unwind_init:
4054 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4055 MMI->setCallsUnwindInit(true);
4060 case Intrinsic::eh_dwarf_cfa: {
4061 MVT VT = getValue(I.getOperand(1)).getValueType();
4063 if (VT.bitsGT(TLI.getPointerTy()))
4064 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4065 TLI.getPointerTy(), getValue(I.getOperand(1)));
4067 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4068 TLI.getPointerTy(), getValue(I.getOperand(1)));
4070 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4072 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4073 TLI.getPointerTy()),
4075 setValue(&I, DAG.getNode(ISD::ADD, dl,
4077 DAG.getNode(ISD::FRAMEADDR, dl,
4080 TLI.getPointerTy())),
4085 case Intrinsic::convertff:
4086 case Intrinsic::convertfsi:
4087 case Intrinsic::convertfui:
4088 case Intrinsic::convertsif:
4089 case Intrinsic::convertuif:
4090 case Intrinsic::convertss:
4091 case Intrinsic::convertsu:
4092 case Intrinsic::convertus:
4093 case Intrinsic::convertuu: {
4094 ISD::CvtCode Code = ISD::CVT_INVALID;
4095 switch (Intrinsic) {
4096 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4097 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4098 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4099 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4100 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4101 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4102 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4103 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4104 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4106 MVT DestVT = TLI.getValueType(I.getType());
4107 Value* Op1 = I.getOperand(1);
4108 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4109 DAG.getValueType(DestVT),
4110 DAG.getValueType(getValue(Op1).getValueType()),
4111 getValue(I.getOperand(2)),
4112 getValue(I.getOperand(3)),
4117 case Intrinsic::sqrt:
4118 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4119 getValue(I.getOperand(1)).getValueType(),
4120 getValue(I.getOperand(1))));
4122 case Intrinsic::powi:
4123 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4124 getValue(I.getOperand(1)).getValueType(),
4125 getValue(I.getOperand(1)),
4126 getValue(I.getOperand(2))));
4128 case Intrinsic::sin:
4129 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4130 getValue(I.getOperand(1)).getValueType(),
4131 getValue(I.getOperand(1))));
4133 case Intrinsic::cos:
4134 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4135 getValue(I.getOperand(1)).getValueType(),
4136 getValue(I.getOperand(1))));
4138 case Intrinsic::log:
4141 case Intrinsic::log2:
4144 case Intrinsic::log10:
4147 case Intrinsic::exp:
4150 case Intrinsic::exp2:
4153 case Intrinsic::pow:
4156 case Intrinsic::pcmarker: {
4157 SDValue Tmp = getValue(I.getOperand(1));
4158 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4161 case Intrinsic::readcyclecounter: {
4162 SDValue Op = getRoot();
4163 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4164 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4167 DAG.setRoot(Tmp.getValue(1));
4170 case Intrinsic::part_select: {
4171 // Currently not implemented: just abort
4172 assert(0 && "part_select intrinsic not implemented");
4175 case Intrinsic::part_set: {
4176 // Currently not implemented: just abort
4177 assert(0 && "part_set intrinsic not implemented");
4180 case Intrinsic::bswap:
4181 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4182 getValue(I.getOperand(1)).getValueType(),
4183 getValue(I.getOperand(1))));
4185 case Intrinsic::cttz: {
4186 SDValue Arg = getValue(I.getOperand(1));
4187 MVT Ty = Arg.getValueType();
4188 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4189 setValue(&I, result);
4192 case Intrinsic::ctlz: {
4193 SDValue Arg = getValue(I.getOperand(1));
4194 MVT Ty = Arg.getValueType();
4195 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4196 setValue(&I, result);
4199 case Intrinsic::ctpop: {
4200 SDValue Arg = getValue(I.getOperand(1));
4201 MVT Ty = Arg.getValueType();
4202 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4203 setValue(&I, result);
4206 case Intrinsic::stacksave: {
4207 SDValue Op = getRoot();
4208 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4209 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4211 DAG.setRoot(Tmp.getValue(1));
4214 case Intrinsic::stackrestore: {
4215 SDValue Tmp = getValue(I.getOperand(1));
4216 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4219 case Intrinsic::stackprotector: {
4220 // Emit code into the DAG to store the stack guard onto the stack.
4221 MachineFunction &MF = DAG.getMachineFunction();
4222 MachineFrameInfo *MFI = MF.getFrameInfo();
4223 MVT PtrTy = TLI.getPointerTy();
4225 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4226 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4228 int FI = FuncInfo.StaticAllocaMap[Slot];
4229 MFI->setStackProtectorIndex(FI);
4231 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4233 // Store the stack protector onto the stack.
4234 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4235 PseudoSourceValue::getFixedStack(FI),
4237 setValue(&I, Result);
4238 DAG.setRoot(Result);
4241 case Intrinsic::var_annotation:
4242 // Discard annotate attributes
4245 case Intrinsic::init_trampoline: {
4246 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4250 Ops[1] = getValue(I.getOperand(1));
4251 Ops[2] = getValue(I.getOperand(2));
4252 Ops[3] = getValue(I.getOperand(3));
4253 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4254 Ops[5] = DAG.getSrcValue(F);
4256 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4257 DAG.getNodeValueTypes(TLI.getPointerTy(),
4262 DAG.setRoot(Tmp.getValue(1));
4266 case Intrinsic::gcroot:
4268 Value *Alloca = I.getOperand(1);
4269 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4271 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4272 GFI->addStackRoot(FI->getIndex(), TypeMap);
4276 case Intrinsic::gcread:
4277 case Intrinsic::gcwrite:
4278 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4281 case Intrinsic::flt_rounds: {
4282 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4286 case Intrinsic::trap: {
4287 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4291 case Intrinsic::uadd_with_overflow:
4292 return implVisitAluOverflow(I, ISD::UADDO);
4293 case Intrinsic::sadd_with_overflow:
4294 return implVisitAluOverflow(I, ISD::SADDO);
4295 case Intrinsic::usub_with_overflow:
4296 return implVisitAluOverflow(I, ISD::USUBO);
4297 case Intrinsic::ssub_with_overflow:
4298 return implVisitAluOverflow(I, ISD::SSUBO);
4299 case Intrinsic::umul_with_overflow:
4300 return implVisitAluOverflow(I, ISD::UMULO);
4301 case Intrinsic::smul_with_overflow:
4302 return implVisitAluOverflow(I, ISD::SMULO);
4304 case Intrinsic::prefetch: {
4307 Ops[1] = getValue(I.getOperand(1));
4308 Ops[2] = getValue(I.getOperand(2));
4309 Ops[3] = getValue(I.getOperand(3));
4310 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4314 case Intrinsic::memory_barrier: {
4317 for (int x = 1; x < 6; ++x)
4318 Ops[x] = getValue(I.getOperand(x));
4320 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4323 case Intrinsic::atomic_cmp_swap: {
4324 SDValue Root = getRoot();
4326 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4327 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4329 getValue(I.getOperand(1)),
4330 getValue(I.getOperand(2)),
4331 getValue(I.getOperand(3)),
4334 DAG.setRoot(L.getValue(1));
4337 case Intrinsic::atomic_load_add:
4338 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4339 case Intrinsic::atomic_load_sub:
4340 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4341 case Intrinsic::atomic_load_or:
4342 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4343 case Intrinsic::atomic_load_xor:
4344 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4345 case Intrinsic::atomic_load_and:
4346 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4347 case Intrinsic::atomic_load_nand:
4348 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4349 case Intrinsic::atomic_load_max:
4350 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4351 case Intrinsic::atomic_load_min:
4352 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4353 case Intrinsic::atomic_load_umin:
4354 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4355 case Intrinsic::atomic_load_umax:
4356 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4357 case Intrinsic::atomic_swap:
4358 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4363 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4365 MachineBasicBlock *LandingPad) {
4366 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4367 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4368 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4369 unsigned BeginLabel = 0, EndLabel = 0;
4371 TargetLowering::ArgListTy Args;
4372 TargetLowering::ArgListEntry Entry;
4373 Args.reserve(CS.arg_size());
4374 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4376 SDValue ArgNode = getValue(*i);
4377 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4379 unsigned attrInd = i - CS.arg_begin() + 1;
4380 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4381 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4382 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4383 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4384 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4385 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4386 Entry.Alignment = CS.getParamAlignment(attrInd);
4387 Args.push_back(Entry);
4390 if (LandingPad && MMI) {
4391 // Insert a label before the invoke call to mark the try range. This can be
4392 // used to detect deletion of the invoke via the MachineModuleInfo.
4393 BeginLabel = MMI->NextLabelID();
4394 // Both PendingLoads and PendingExports must be flushed here;
4395 // this call might not return.
4397 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4398 getControlRoot(), BeginLabel));
4401 std::pair<SDValue,SDValue> Result =
4402 TLI.LowerCallTo(getRoot(), CS.getType(),
4403 CS.paramHasAttr(0, Attribute::SExt),
4404 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4405 CS.paramHasAttr(0, Attribute::InReg),
4406 CS.getCallingConv(),
4407 IsTailCall && PerformTailCallOpt,
4408 Callee, Args, DAG, getCurDebugLoc());
4409 if (CS.getType() != Type::VoidTy)
4410 setValue(CS.getInstruction(), Result.first);
4411 DAG.setRoot(Result.second);
4413 if (LandingPad && MMI) {
4414 // Insert a label at the end of the invoke call to mark the try range. This
4415 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4416 EndLabel = MMI->NextLabelID();
4417 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4418 getRoot(), EndLabel));
4420 // Inform MachineModuleInfo of range.
4421 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4426 void SelectionDAGLowering::visitCall(CallInst &I) {
4427 const char *RenameFn = 0;
4428 if (Function *F = I.getCalledFunction()) {
4429 if (F->isDeclaration()) {
4430 if (unsigned IID = F->getIntrinsicID()) {
4431 RenameFn = visitIntrinsicCall(I, IID);
4437 // Check for well-known libc/libm calls. If the function is internal, it
4438 // can't be a library call.
4439 unsigned NameLen = F->getNameLen();
4440 if (!F->hasLocalLinkage() && NameLen) {
4441 const char *NameStr = F->getNameStart();
4442 if (NameStr[0] == 'c' &&
4443 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4444 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4445 if (I.getNumOperands() == 3 && // Basic sanity checks.
4446 I.getOperand(1)->getType()->isFloatingPoint() &&
4447 I.getType() == I.getOperand(1)->getType() &&
4448 I.getType() == I.getOperand(2)->getType()) {
4449 SDValue LHS = getValue(I.getOperand(1));
4450 SDValue RHS = getValue(I.getOperand(2));
4451 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4452 LHS.getValueType(), LHS, RHS));
4455 } else if (NameStr[0] == 'f' &&
4456 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4457 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4458 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4459 if (I.getNumOperands() == 2 && // Basic sanity checks.
4460 I.getOperand(1)->getType()->isFloatingPoint() &&
4461 I.getType() == I.getOperand(1)->getType()) {
4462 SDValue Tmp = getValue(I.getOperand(1));
4463 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4464 Tmp.getValueType(), Tmp));
4467 } else if (NameStr[0] == 's' &&
4468 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4469 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4470 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4471 if (I.getNumOperands() == 2 && // Basic sanity checks.
4472 I.getOperand(1)->getType()->isFloatingPoint() &&
4473 I.getType() == I.getOperand(1)->getType()) {
4474 SDValue Tmp = getValue(I.getOperand(1));
4475 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4476 Tmp.getValueType(), Tmp));
4479 } else if (NameStr[0] == 'c' &&
4480 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4481 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4482 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4483 if (I.getNumOperands() == 2 && // Basic sanity checks.
4484 I.getOperand(1)->getType()->isFloatingPoint() &&
4485 I.getType() == I.getOperand(1)->getType()) {
4486 SDValue Tmp = getValue(I.getOperand(1));
4487 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4488 Tmp.getValueType(), Tmp));
4493 } else if (isa<InlineAsm>(I.getOperand(0))) {
4500 Callee = getValue(I.getOperand(0));
4502 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4504 LowerCallTo(&I, Callee, I.isTailCall());
4508 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4509 /// this value and returns the result as a ValueVT value. This uses
4510 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4511 /// If the Flag pointer is NULL, no flag is used.
4512 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4514 SDValue *Flag) const {
4515 // Assemble the legal parts into the final values.
4516 SmallVector<SDValue, 4> Values(ValueVTs.size());
4517 SmallVector<SDValue, 8> Parts;
4518 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4519 // Copy the legal parts from the registers.
4520 MVT ValueVT = ValueVTs[Value];
4521 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4522 MVT RegisterVT = RegVTs[Value];
4524 Parts.resize(NumRegs);
4525 for (unsigned i = 0; i != NumRegs; ++i) {
4528 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4530 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4531 *Flag = P.getValue(2);
4533 Chain = P.getValue(1);
4535 // If the source register was virtual and if we know something about it,
4536 // add an assert node.
4537 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4538 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4539 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4540 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4541 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4542 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4544 unsigned RegSize = RegisterVT.getSizeInBits();
4545 unsigned NumSignBits = LOI.NumSignBits;
4546 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4548 // FIXME: We capture more information than the dag can represent. For
4549 // now, just use the tightest assertzext/assertsext possible.
4551 MVT FromVT(MVT::Other);
4552 if (NumSignBits == RegSize)
4553 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4554 else if (NumZeroBits >= RegSize-1)
4555 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4556 else if (NumSignBits > RegSize-8)
4557 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4558 else if (NumZeroBits >= RegSize-9)
4559 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4560 else if (NumSignBits > RegSize-16)
4561 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4562 else if (NumZeroBits >= RegSize-17)
4563 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4564 else if (NumSignBits > RegSize-32)
4565 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4566 else if (NumZeroBits >= RegSize-33)
4567 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4569 if (FromVT != MVT::Other) {
4570 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4571 RegisterVT, P, DAG.getValueType(FromVT));
4580 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4581 NumRegs, RegisterVT, ValueVT);
4586 return DAG.getNode(ISD::MERGE_VALUES, dl,
4587 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4588 &Values[0], ValueVTs.size());
4591 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4592 /// specified value into the registers specified by this object. This uses
4593 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4594 /// If the Flag pointer is NULL, no flag is used.
4595 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4596 SDValue &Chain, SDValue *Flag) const {
4597 // Get the list of the values's legal parts.
4598 unsigned NumRegs = Regs.size();
4599 SmallVector<SDValue, 8> Parts(NumRegs);
4600 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4601 MVT ValueVT = ValueVTs[Value];
4602 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4603 MVT RegisterVT = RegVTs[Value];
4605 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4606 &Parts[Part], NumParts, RegisterVT);
4610 // Copy the parts into the registers.
4611 SmallVector<SDValue, 8> Chains(NumRegs);
4612 for (unsigned i = 0; i != NumRegs; ++i) {
4615 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4617 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4618 *Flag = Part.getValue(1);
4620 Chains[i] = Part.getValue(0);
4623 if (NumRegs == 1 || Flag)
4624 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4625 // flagged to it. That is the CopyToReg nodes and the user are considered
4626 // a single scheduling unit. If we create a TokenFactor and return it as
4627 // chain, then the TokenFactor is both a predecessor (operand) of the
4628 // user as well as a successor (the TF operands are flagged to the user).
4629 // c1, f1 = CopyToReg
4630 // c2, f2 = CopyToReg
4631 // c3 = TokenFactor c1, c2
4634 Chain = Chains[NumRegs-1];
4636 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4639 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4640 /// operand list. This adds the code marker and includes the number of
4641 /// values added into it.
4642 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4643 std::vector<SDValue> &Ops) const {
4644 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4645 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4646 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4647 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4648 MVT RegisterVT = RegVTs[Value];
4649 for (unsigned i = 0; i != NumRegs; ++i) {
4650 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4651 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4656 /// isAllocatableRegister - If the specified register is safe to allocate,
4657 /// i.e. it isn't a stack pointer or some other special register, return the
4658 /// register class for the register. Otherwise, return null.
4659 static const TargetRegisterClass *
4660 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4661 const TargetLowering &TLI,
4662 const TargetRegisterInfo *TRI) {
4663 MVT FoundVT = MVT::Other;
4664 const TargetRegisterClass *FoundRC = 0;
4665 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4666 E = TRI->regclass_end(); RCI != E; ++RCI) {
4667 MVT ThisVT = MVT::Other;
4669 const TargetRegisterClass *RC = *RCI;
4670 // If none of the the value types for this register class are valid, we
4671 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4672 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4674 if (TLI.isTypeLegal(*I)) {
4675 // If we have already found this register in a different register class,
4676 // choose the one with the largest VT specified. For example, on
4677 // PowerPC, we favor f64 register classes over f32.
4678 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4685 if (ThisVT == MVT::Other) continue;
4687 // NOTE: This isn't ideal. In particular, this might allocate the
4688 // frame pointer in functions that need it (due to them not being taken
4689 // out of allocation, because a variable sized allocation hasn't been seen
4690 // yet). This is a slight code pessimization, but should still work.
4691 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4692 E = RC->allocation_order_end(MF); I != E; ++I)
4694 // We found a matching register class. Keep looking at others in case
4695 // we find one with larger registers that this physreg is also in.
4706 /// AsmOperandInfo - This contains information for each constraint that we are
4708 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4709 public TargetLowering::AsmOperandInfo {
4710 /// CallOperand - If this is the result output operand or a clobber
4711 /// this is null, otherwise it is the incoming operand to the CallInst.
4712 /// This gets modified as the asm is processed.
4713 SDValue CallOperand;
4715 /// AssignedRegs - If this is a register or register class operand, this
4716 /// contains the set of register corresponding to the operand.
4717 RegsForValue AssignedRegs;
4719 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4720 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4723 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4724 /// busy in OutputRegs/InputRegs.
4725 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4726 std::set<unsigned> &OutputRegs,
4727 std::set<unsigned> &InputRegs,
4728 const TargetRegisterInfo &TRI) const {
4730 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4731 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4734 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4735 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4739 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4740 /// corresponds to. If there is no Value* for this operand, it returns
4742 MVT getCallOperandValMVT(const TargetLowering &TLI,
4743 const TargetData *TD) const {
4744 if (CallOperandVal == 0) return MVT::Other;
4746 if (isa<BasicBlock>(CallOperandVal))
4747 return TLI.getPointerTy();
4749 const llvm::Type *OpTy = CallOperandVal->getType();
4751 // If this is an indirect operand, the operand is a pointer to the
4754 OpTy = cast<PointerType>(OpTy)->getElementType();
4756 // If OpTy is not a single value, it may be a struct/union that we
4757 // can tile with integers.
4758 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4759 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4768 OpTy = IntegerType::get(BitSize);
4773 return TLI.getValueType(OpTy, true);
4777 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4779 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4780 const TargetRegisterInfo &TRI) {
4781 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4783 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4784 for (; *Aliases; ++Aliases)
4785 Regs.insert(*Aliases);
4788 } // end llvm namespace.
4791 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4792 /// specified operand. We prefer to assign virtual registers, to allow the
4793 /// register allocator handle the assignment process. However, if the asm uses
4794 /// features that we can't model on machineinstrs, we have SDISel do the
4795 /// allocation. This produces generally horrible, but correct, code.
4797 /// OpInfo describes the operand.
4798 /// Input and OutputRegs are the set of already allocated physical registers.
4800 void SelectionDAGLowering::
4801 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4802 std::set<unsigned> &OutputRegs,
4803 std::set<unsigned> &InputRegs) {
4804 // Compute whether this value requires an input register, an output register,
4806 bool isOutReg = false;
4807 bool isInReg = false;
4808 switch (OpInfo.Type) {
4809 case InlineAsm::isOutput:
4812 // If there is an input constraint that matches this, we need to reserve
4813 // the input register so no other inputs allocate to it.
4814 isInReg = OpInfo.hasMatchingInput();
4816 case InlineAsm::isInput:
4820 case InlineAsm::isClobber:
4827 MachineFunction &MF = DAG.getMachineFunction();
4828 SmallVector<unsigned, 4> Regs;
4830 // If this is a constraint for a single physreg, or a constraint for a
4831 // register class, find it.
4832 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4833 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4834 OpInfo.ConstraintVT);
4836 unsigned NumRegs = 1;
4837 if (OpInfo.ConstraintVT != MVT::Other) {
4838 // If this is a FP input in an integer register (or visa versa) insert a bit
4839 // cast of the input value. More generally, handle any case where the input
4840 // value disagrees with the register class we plan to stick this in.
4841 if (OpInfo.Type == InlineAsm::isInput &&
4842 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4843 // Try to convert to the first MVT that the reg class contains. If the
4844 // types are identical size, use a bitcast to convert (e.g. two differing
4846 MVT RegVT = *PhysReg.second->vt_begin();
4847 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4848 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4849 RegVT, OpInfo.CallOperand);
4850 OpInfo.ConstraintVT = RegVT;
4851 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4852 // If the input is a FP value and we want it in FP registers, do a
4853 // bitcast to the corresponding integer type. This turns an f64 value
4854 // into i64, which can be passed with two i32 values on a 32-bit
4856 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4857 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4858 RegVT, OpInfo.CallOperand);
4859 OpInfo.ConstraintVT = RegVT;
4863 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4867 MVT ValueVT = OpInfo.ConstraintVT;
4869 // If this is a constraint for a specific physical register, like {r17},
4871 if (PhysReg.first) {
4872 if (OpInfo.ConstraintVT == MVT::Other)
4873 ValueVT = *PhysReg.second->vt_begin();
4875 // Get the actual register value type. This is important, because the user
4876 // may have asked for (e.g.) the AX register in i32 type. We need to
4877 // remember that AX is actually i16 to get the right extension.
4878 RegVT = *PhysReg.second->vt_begin();
4880 // This is a explicit reference to a physical register.
4881 Regs.push_back(PhysReg.first);
4883 // If this is an expanded reference, add the rest of the regs to Regs.
4885 TargetRegisterClass::iterator I = PhysReg.second->begin();
4886 for (; *I != PhysReg.first; ++I)
4887 assert(I != PhysReg.second->end() && "Didn't find reg!");
4889 // Already added the first reg.
4891 for (; NumRegs; --NumRegs, ++I) {
4892 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4896 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4897 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4898 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4902 // Otherwise, if this was a reference to an LLVM register class, create vregs
4903 // for this reference.
4904 std::vector<unsigned> RegClassRegs;
4905 const TargetRegisterClass *RC = PhysReg.second;
4907 // If this is a tied register, our regalloc doesn't know how to maintain
4908 // the constraint, so we have to pick a register to pin the input/output to.
4909 // If it isn't a matched constraint, go ahead and create vreg and let the
4910 // regalloc do its thing.
4911 if (!OpInfo.hasMatchingInput()) {
4912 RegVT = *PhysReg.second->vt_begin();
4913 if (OpInfo.ConstraintVT == MVT::Other)
4916 // Create the appropriate number of virtual registers.
4917 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4918 for (; NumRegs; --NumRegs)
4919 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4921 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4925 // Otherwise, we can't allocate it. Let the code below figure out how to
4926 // maintain these constraints.
4927 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4930 // This is a reference to a register class that doesn't directly correspond
4931 // to an LLVM register class. Allocate NumRegs consecutive, available,
4932 // registers from the class.
4933 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4934 OpInfo.ConstraintVT);
4937 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4938 unsigned NumAllocated = 0;
4939 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4940 unsigned Reg = RegClassRegs[i];
4941 // See if this register is available.
4942 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4943 (isInReg && InputRegs.count(Reg))) { // Already used.
4944 // Make sure we find consecutive registers.
4949 // Check to see if this register is allocatable (i.e. don't give out the
4952 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4953 if (!RC) { // Couldn't allocate this register.
4954 // Reset NumAllocated to make sure we return consecutive registers.
4960 // Okay, this register is good, we can use it.
4963 // If we allocated enough consecutive registers, succeed.
4964 if (NumAllocated == NumRegs) {
4965 unsigned RegStart = (i-NumAllocated)+1;
4966 unsigned RegEnd = i+1;
4967 // Mark all of the allocated registers used.
4968 for (unsigned i = RegStart; i != RegEnd; ++i)
4969 Regs.push_back(RegClassRegs[i]);
4971 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4972 OpInfo.ConstraintVT);
4973 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4978 // Otherwise, we couldn't allocate enough registers for this.
4981 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4982 /// processed uses a memory 'm' constraint.
4984 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4985 const TargetLowering &TLI) {
4986 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4987 InlineAsm::ConstraintInfo &CI = CInfos[i];
4988 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4989 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4990 if (CType == TargetLowering::C_Memory)
4998 /// visitInlineAsm - Handle a call to an InlineAsm object.
5000 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5001 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5003 /// ConstraintOperands - Information about all of the constraints.
5004 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5006 SDValue Chain = getRoot();
5009 std::set<unsigned> OutputRegs, InputRegs;
5011 // Do a prepass over the constraints, canonicalizing them, and building up the
5012 // ConstraintOperands list.
5013 std::vector<InlineAsm::ConstraintInfo>
5014 ConstraintInfos = IA->ParseConstraints();
5016 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5018 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5019 unsigned ResNo = 0; // ResNo - The result number of the next output.
5020 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5021 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5022 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5024 MVT OpVT = MVT::Other;
5026 // Compute the value type for each operand.
5027 switch (OpInfo.Type) {
5028 case InlineAsm::isOutput:
5029 // Indirect outputs just consume an argument.
5030 if (OpInfo.isIndirect) {
5031 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5035 // The return value of the call is this value. As such, there is no
5036 // corresponding argument.
5037 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5038 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5039 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5041 assert(ResNo == 0 && "Asm only has one result!");
5042 OpVT = TLI.getValueType(CS.getType());
5046 case InlineAsm::isInput:
5047 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5049 case InlineAsm::isClobber:
5054 // If this is an input or an indirect output, process the call argument.
5055 // BasicBlocks are labels, currently appearing only in asm's.
5056 if (OpInfo.CallOperandVal) {
5057 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5058 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5060 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5063 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5066 OpInfo.ConstraintVT = OpVT;
5069 // Second pass over the constraints: compute which constraint option to use
5070 // and assign registers to constraints that want a specific physreg.
5071 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5072 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5074 // If this is an output operand with a matching input operand, look up the
5075 // matching input. If their types mismatch, e.g. one is an integer, the
5076 // other is floating point, or their sizes are different, flag it as an
5078 if (OpInfo.hasMatchingInput()) {
5079 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5080 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5081 if ((OpInfo.ConstraintVT.isInteger() !=
5082 Input.ConstraintVT.isInteger()) ||
5083 (OpInfo.ConstraintVT.getSizeInBits() !=
5084 Input.ConstraintVT.getSizeInBits())) {
5085 cerr << "Unsupported asm: input constraint with a matching output "
5086 << "constraint of incompatible type!\n";
5089 Input.ConstraintVT = OpInfo.ConstraintVT;
5093 // Compute the constraint code and ConstraintType to use.
5094 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5096 // If this is a memory input, and if the operand is not indirect, do what we
5097 // need to to provide an address for the memory input.
5098 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5099 !OpInfo.isIndirect) {
5100 assert(OpInfo.Type == InlineAsm::isInput &&
5101 "Can only indirectify direct input operands!");
5103 // Memory operands really want the address of the value. If we don't have
5104 // an indirect input, put it in the constpool if we can, otherwise spill
5105 // it to a stack slot.
5107 // If the operand is a float, integer, or vector constant, spill to a
5108 // constant pool entry to get its address.
5109 Value *OpVal = OpInfo.CallOperandVal;
5110 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5111 isa<ConstantVector>(OpVal)) {
5112 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5113 TLI.getPointerTy());
5115 // Otherwise, create a stack slot and emit a store to it before the
5117 const Type *Ty = OpVal->getType();
5118 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5119 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5120 MachineFunction &MF = DAG.getMachineFunction();
5121 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5122 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5123 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5124 OpInfo.CallOperand, StackSlot, NULL, 0);
5125 OpInfo.CallOperand = StackSlot;
5128 // There is no longer a Value* corresponding to this operand.
5129 OpInfo.CallOperandVal = 0;
5130 // It is now an indirect operand.
5131 OpInfo.isIndirect = true;
5134 // If this constraint is for a specific register, allocate it before
5136 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5137 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5139 ConstraintInfos.clear();
5142 // Second pass - Loop over all of the operands, assigning virtual or physregs
5143 // to register class operands.
5144 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5145 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5147 // C_Register operands have already been allocated, Other/Memory don't need
5149 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5150 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5153 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5154 std::vector<SDValue> AsmNodeOperands;
5155 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5156 AsmNodeOperands.push_back(
5157 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5160 // Loop over all of the inputs, copying the operand values into the
5161 // appropriate registers and processing the output regs.
5162 RegsForValue RetValRegs;
5164 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5165 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5167 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5168 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5170 switch (OpInfo.Type) {
5171 case InlineAsm::isOutput: {
5172 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5173 OpInfo.ConstraintType != TargetLowering::C_Register) {
5174 // Memory output, or 'other' output (e.g. 'X' constraint).
5175 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5177 // Add information to the INLINEASM node to know about this output.
5178 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5179 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5180 TLI.getPointerTy()));
5181 AsmNodeOperands.push_back(OpInfo.CallOperand);
5185 // Otherwise, this is a register or register class output.
5187 // Copy the output from the appropriate register. Find a register that
5189 if (OpInfo.AssignedRegs.Regs.empty()) {
5190 cerr << "Couldn't allocate output reg for constraint '"
5191 << OpInfo.ConstraintCode << "'!\n";
5195 // If this is an indirect operand, store through the pointer after the
5197 if (OpInfo.isIndirect) {
5198 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5199 OpInfo.CallOperandVal));
5201 // This is the result value of the call.
5202 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5203 // Concatenate this output onto the outputs list.
5204 RetValRegs.append(OpInfo.AssignedRegs);
5207 // Add information to the INLINEASM node to know that this register is
5209 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5210 6 /* EARLYCLOBBER REGDEF */ :
5212 DAG, AsmNodeOperands);
5215 case InlineAsm::isInput: {
5216 SDValue InOperandVal = OpInfo.CallOperand;
5218 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5219 // If this is required to match an output register we have already set,
5220 // just use its register.
5221 unsigned OperandNo = OpInfo.getMatchedOperand();
5223 // Scan until we find the definition we already emitted of this operand.
5224 // When we find it, create a RegsForValue operand.
5225 unsigned CurOp = 2; // The first operand.
5226 for (; OperandNo; --OperandNo) {
5227 // Advance to the next operand.
5229 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5230 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
5231 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5232 (NumOps & 7) == 4 /*MEM*/) &&
5233 "Skipped past definitions?");
5234 CurOp += (NumOps>>3)+1;
5238 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5239 if ((NumOps & 7) == 2 /*REGDEF*/
5240 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5241 // Add NumOps>>3 registers to MatchedRegs.
5242 RegsForValue MatchedRegs;
5243 MatchedRegs.TLI = &TLI;
5244 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5245 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5246 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5248 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5249 MatchedRegs.Regs.push_back(Reg);
5252 // Use the produced MatchedRegs object to
5253 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5255 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
5258 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5259 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5260 // Add information to the INLINEASM node to know about this input.
5261 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
5262 TLI.getPointerTy()));
5263 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5268 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5269 assert(!OpInfo.isIndirect &&
5270 "Don't know how to handle indirect other inputs yet!");
5272 std::vector<SDValue> Ops;
5273 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5274 hasMemory, Ops, DAG);
5276 cerr << "Invalid operand for inline asm constraint '"
5277 << OpInfo.ConstraintCode << "'!\n";
5281 // Add information to the INLINEASM node to know about this input.
5282 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5283 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5284 TLI.getPointerTy()));
5285 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5287 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5288 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5289 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5290 "Memory operands expect pointer values");
5292 // Add information to the INLINEASM node to know about this input.
5293 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5294 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5295 TLI.getPointerTy()));
5296 AsmNodeOperands.push_back(InOperandVal);
5300 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5301 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5302 "Unknown constraint type!");
5303 assert(!OpInfo.isIndirect &&
5304 "Don't know how to handle indirect register inputs yet!");
5306 // Copy the input into the appropriate registers.
5307 if (OpInfo.AssignedRegs.Regs.empty()) {
5308 cerr << "Couldn't allocate output reg for constraint '"
5309 << OpInfo.ConstraintCode << "'!\n";
5313 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5316 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5317 DAG, AsmNodeOperands);
5320 case InlineAsm::isClobber: {
5321 // Add the clobbered value to the operand list, so that the register
5322 // allocator is aware that the physreg got clobbered.
5323 if (!OpInfo.AssignedRegs.Regs.empty())
5324 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5325 DAG, AsmNodeOperands);
5331 // Finish up input operands.
5332 AsmNodeOperands[0] = Chain;
5333 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5335 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5336 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5337 &AsmNodeOperands[0], AsmNodeOperands.size());
5338 Flag = Chain.getValue(1);
5340 // If this asm returns a register value, copy the result from that register
5341 // and set it as the value of the call.
5342 if (!RetValRegs.Regs.empty()) {
5343 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5346 // FIXME: Why don't we do this for inline asms with MRVs?
5347 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5348 MVT ResultType = TLI.getValueType(CS.getType());
5350 // If any of the results of the inline asm is a vector, it may have the
5351 // wrong width/num elts. This can happen for register classes that can
5352 // contain multiple different value types. The preg or vreg allocated may
5353 // not have the same VT as was expected. Convert it to the right type
5354 // with bit_convert.
5355 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5356 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5359 } else if (ResultType != Val.getValueType() &&
5360 ResultType.isInteger() && Val.getValueType().isInteger()) {
5361 // If a result value was tied to an input value, the computed result may
5362 // have a wider width than the expected result. Extract the relevant
5364 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5367 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5370 setValue(CS.getInstruction(), Val);
5373 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5375 // Process indirect outputs, first output all of the flagged copies out of
5377 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5378 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5379 Value *Ptr = IndirectStoresToEmit[i].second;
5380 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5382 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5385 // Emit the non-flagged stores from the physregs.
5386 SmallVector<SDValue, 8> OutChains;
5387 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5388 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5389 StoresToEmit[i].first,
5390 getValue(StoresToEmit[i].second),
5391 StoresToEmit[i].second, 0));
5392 if (!OutChains.empty())
5393 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5394 &OutChains[0], OutChains.size());
5399 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5400 SDValue Src = getValue(I.getOperand(0));
5402 MVT IntPtr = TLI.getPointerTy();
5404 if (IntPtr.bitsLT(Src.getValueType()))
5405 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5406 else if (IntPtr.bitsGT(Src.getValueType()))
5407 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5409 // Scale the source by the type size.
5410 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5411 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5412 Src, DAG.getIntPtrConstant(ElementSize));
5414 TargetLowering::ArgListTy Args;
5415 TargetLowering::ArgListEntry Entry;
5417 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5418 Args.push_back(Entry);
5420 std::pair<SDValue,SDValue> Result =
5421 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5422 CallingConv::C, PerformTailCallOpt,
5423 DAG.getExternalSymbol("malloc", IntPtr),
5424 Args, DAG, getCurDebugLoc());
5425 setValue(&I, Result.first); // Pointers always fit in registers
5426 DAG.setRoot(Result.second);
5429 void SelectionDAGLowering::visitFree(FreeInst &I) {
5430 TargetLowering::ArgListTy Args;
5431 TargetLowering::ArgListEntry Entry;
5432 Entry.Node = getValue(I.getOperand(0));
5433 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5434 Args.push_back(Entry);
5435 MVT IntPtr = TLI.getPointerTy();
5436 std::pair<SDValue,SDValue> Result =
5437 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5438 CallingConv::C, PerformTailCallOpt,
5439 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5441 DAG.setRoot(Result.second);
5444 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5445 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5446 MVT::Other, getRoot(),
5447 getValue(I.getOperand(1)),
5448 DAG.getSrcValue(I.getOperand(1))));
5451 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5452 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5453 getRoot(), getValue(I.getOperand(0)),
5454 DAG.getSrcValue(I.getOperand(0)));
5456 DAG.setRoot(V.getValue(1));
5459 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5460 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5461 MVT::Other, getRoot(),
5462 getValue(I.getOperand(1)),
5463 DAG.getSrcValue(I.getOperand(1))));
5466 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5467 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5468 MVT::Other, getRoot(),
5469 getValue(I.getOperand(1)),
5470 getValue(I.getOperand(2)),
5471 DAG.getSrcValue(I.getOperand(1)),
5472 DAG.getSrcValue(I.getOperand(2))));
5475 /// TargetLowering::LowerArguments - This is the default LowerArguments
5476 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5477 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5478 /// integrated into SDISel.
5479 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5480 SmallVectorImpl<SDValue> &ArgValues,
5482 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5483 SmallVector<SDValue, 3+16> Ops;
5484 Ops.push_back(DAG.getRoot());
5485 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5486 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5488 // Add one result value for each formal argument.
5489 SmallVector<MVT, 16> RetVals;
5491 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5493 SmallVector<MVT, 4> ValueVTs;
5494 ComputeValueVTs(*this, I->getType(), ValueVTs);
5495 for (unsigned Value = 0, NumValues = ValueVTs.size();
5496 Value != NumValues; ++Value) {
5497 MVT VT = ValueVTs[Value];
5498 const Type *ArgTy = VT.getTypeForMVT();
5499 ISD::ArgFlagsTy Flags;
5500 unsigned OriginalAlignment =
5501 getTargetData()->getABITypeAlignment(ArgTy);
5503 if (F.paramHasAttr(j, Attribute::ZExt))
5505 if (F.paramHasAttr(j, Attribute::SExt))
5507 if (F.paramHasAttr(j, Attribute::InReg))
5509 if (F.paramHasAttr(j, Attribute::StructRet))
5511 if (F.paramHasAttr(j, Attribute::ByVal)) {
5513 const PointerType *Ty = cast<PointerType>(I->getType());
5514 const Type *ElementTy = Ty->getElementType();
5515 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5516 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5517 // For ByVal, alignment should be passed from FE. BE will guess if
5518 // this info is not there but there are cases it cannot get right.
5519 if (F.getParamAlignment(j))
5520 FrameAlign = F.getParamAlignment(j);
5521 Flags.setByValAlign(FrameAlign);
5522 Flags.setByValSize(FrameSize);
5524 if (F.paramHasAttr(j, Attribute::Nest))
5526 Flags.setOrigAlign(OriginalAlignment);
5528 MVT RegisterVT = getRegisterType(VT);
5529 unsigned NumRegs = getNumRegisters(VT);
5530 for (unsigned i = 0; i != NumRegs; ++i) {
5531 RetVals.push_back(RegisterVT);
5532 ISD::ArgFlagsTy MyFlags = Flags;
5533 if (NumRegs > 1 && i == 0)
5535 // if it isn't first piece, alignment must be 1
5537 MyFlags.setOrigAlign(1);
5538 Ops.push_back(DAG.getArgFlags(MyFlags));
5543 RetVals.push_back(MVT::Other);
5546 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5547 DAG.getVTList(&RetVals[0], RetVals.size()),
5548 &Ops[0], Ops.size()).getNode();
5550 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5551 // allows exposing the loads that may be part of the argument access to the
5552 // first DAGCombiner pass.
5553 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5555 // The number of results should match up, except that the lowered one may have
5556 // an extra flag result.
5557 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5558 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5559 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5560 && "Lowering produced unexpected number of results!");
5562 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5563 if (Result != TmpRes.getNode() && Result->use_empty()) {
5564 HandleSDNode Dummy(DAG.getRoot());
5565 DAG.RemoveDeadNode(Result);
5568 Result = TmpRes.getNode();
5570 unsigned NumArgRegs = Result->getNumValues() - 1;
5571 DAG.setRoot(SDValue(Result, NumArgRegs));
5573 // Set up the return result vector.
5576 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5578 SmallVector<MVT, 4> ValueVTs;
5579 ComputeValueVTs(*this, I->getType(), ValueVTs);
5580 for (unsigned Value = 0, NumValues = ValueVTs.size();
5581 Value != NumValues; ++Value) {
5582 MVT VT = ValueVTs[Value];
5583 MVT PartVT = getRegisterType(VT);
5585 unsigned NumParts = getNumRegisters(VT);
5586 SmallVector<SDValue, 4> Parts(NumParts);
5587 for (unsigned j = 0; j != NumParts; ++j)
5588 Parts[j] = SDValue(Result, i++);
5590 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5591 if (F.paramHasAttr(Idx, Attribute::SExt))
5592 AssertOp = ISD::AssertSext;
5593 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5594 AssertOp = ISD::AssertZext;
5596 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5597 PartVT, VT, AssertOp));
5600 assert(i == NumArgRegs && "Argument register count mismatch!");
5604 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5605 /// implementation, which just inserts an ISD::CALL node, which is later custom
5606 /// lowered by the target to something concrete. FIXME: When all targets are
5607 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5608 std::pair<SDValue, SDValue>
5609 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5610 bool RetSExt, bool RetZExt, bool isVarArg,
5612 unsigned CallingConv, bool isTailCall,
5614 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5615 assert((!isTailCall || PerformTailCallOpt) &&
5616 "isTailCall set when tail-call optimizations are disabled!");
5618 SmallVector<SDValue, 32> Ops;
5619 Ops.push_back(Chain); // Op#0 - Chain
5620 Ops.push_back(Callee);
5622 // Handle all of the outgoing arguments.
5623 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5624 SmallVector<MVT, 4> ValueVTs;
5625 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5626 for (unsigned Value = 0, NumValues = ValueVTs.size();
5627 Value != NumValues; ++Value) {
5628 MVT VT = ValueVTs[Value];
5629 const Type *ArgTy = VT.getTypeForMVT();
5630 SDValue Op = SDValue(Args[i].Node.getNode(),
5631 Args[i].Node.getResNo() + Value);
5632 ISD::ArgFlagsTy Flags;
5633 unsigned OriginalAlignment =
5634 getTargetData()->getABITypeAlignment(ArgTy);
5640 if (Args[i].isInReg)
5644 if (Args[i].isByVal) {
5646 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5647 const Type *ElementTy = Ty->getElementType();
5648 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5649 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5650 // For ByVal, alignment should come from FE. BE will guess if this
5651 // info is not there but there are cases it cannot get right.
5652 if (Args[i].Alignment)
5653 FrameAlign = Args[i].Alignment;
5654 Flags.setByValAlign(FrameAlign);
5655 Flags.setByValSize(FrameSize);
5659 Flags.setOrigAlign(OriginalAlignment);
5661 MVT PartVT = getRegisterType(VT);
5662 unsigned NumParts = getNumRegisters(VT);
5663 SmallVector<SDValue, 4> Parts(NumParts);
5664 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5667 ExtendKind = ISD::SIGN_EXTEND;
5668 else if (Args[i].isZExt)
5669 ExtendKind = ISD::ZERO_EXTEND;
5671 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5673 for (unsigned i = 0; i != NumParts; ++i) {
5674 // if it isn't first piece, alignment must be 1
5675 ISD::ArgFlagsTy MyFlags = Flags;
5676 if (NumParts > 1 && i == 0)
5679 MyFlags.setOrigAlign(1);
5681 Ops.push_back(Parts[i]);
5682 Ops.push_back(DAG.getArgFlags(MyFlags));
5687 // Figure out the result value types. We start by making a list of
5688 // the potentially illegal return value types.
5689 SmallVector<MVT, 4> LoweredRetTys;
5690 SmallVector<MVT, 4> RetTys;
5691 ComputeValueVTs(*this, RetTy, RetTys);
5693 // Then we translate that to a list of legal types.
5694 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5696 MVT RegisterVT = getRegisterType(VT);
5697 unsigned NumRegs = getNumRegisters(VT);
5698 for (unsigned i = 0; i != NumRegs; ++i)
5699 LoweredRetTys.push_back(RegisterVT);
5702 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5704 // Create the CALL node.
5705 SDValue Res = DAG.getCall(CallingConv, dl,
5706 isVarArg, isTailCall, isInreg,
5707 DAG.getVTList(&LoweredRetTys[0],
5708 LoweredRetTys.size()),
5711 Chain = Res.getValue(LoweredRetTys.size() - 1);
5713 // Gather up the call result into a single value.
5714 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5715 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5718 AssertOp = ISD::AssertSext;
5720 AssertOp = ISD::AssertZext;
5722 SmallVector<SDValue, 4> ReturnValues;
5724 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5726 MVT RegisterVT = getRegisterType(VT);
5727 unsigned NumRegs = getNumRegisters(VT);
5728 unsigned RegNoEnd = NumRegs + RegNo;
5729 SmallVector<SDValue, 4> Results;
5730 for (; RegNo != RegNoEnd; ++RegNo)
5731 Results.push_back(Res.getValue(RegNo));
5732 SDValue ReturnValue =
5733 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5735 ReturnValues.push_back(ReturnValue);
5737 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5738 DAG.getVTList(&RetTys[0], RetTys.size()),
5739 &ReturnValues[0], ReturnValues.size());
5742 return std::make_pair(Res, Chain);
5745 void TargetLowering::LowerOperationWrapper(SDNode *N,
5746 SmallVectorImpl<SDValue> &Results,
5747 SelectionDAG &DAG) {
5748 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5750 Results.push_back(Res);
5753 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5754 assert(0 && "LowerOperation not implemented for this target!");
5760 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5761 SDValue Op = getValue(V);
5762 assert((Op.getOpcode() != ISD::CopyFromReg ||
5763 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5764 "Copy from a reg to the same reg!");
5765 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5767 RegsForValue RFV(TLI, Reg, V->getType());
5768 SDValue Chain = DAG.getEntryNode();
5769 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5770 PendingExports.push_back(Chain);
5773 #include "llvm/CodeGen/SelectionDAGISel.h"
5775 void SelectionDAGISel::
5776 LowerArguments(BasicBlock *LLVMBB) {
5777 // If this is the entry block, emit arguments.
5778 Function &F = *LLVMBB->getParent();
5779 SDValue OldRoot = SDL->DAG.getRoot();
5780 SmallVector<SDValue, 16> Args;
5781 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5784 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5786 SmallVector<MVT, 4> ValueVTs;
5787 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5788 unsigned NumValues = ValueVTs.size();
5789 if (!AI->use_empty()) {
5790 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5791 SDL->getCurDebugLoc()));
5792 // If this argument is live outside of the entry block, insert a copy from
5793 // whereever we got it to the vreg that other BB's will reference it as.
5794 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5795 if (VMI != FuncInfo->ValueMap.end()) {
5796 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5802 // Finally, if the target has anything special to do, allow it to do so.
5803 // FIXME: this should insert code into the DAG!
5804 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5807 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5808 /// ensure constants are generated when needed. Remember the virtual registers
5809 /// that need to be added to the Machine PHI nodes as input. We cannot just
5810 /// directly add them, because expansion might result in multiple MBB's for one
5811 /// BB. As such, the start of the BB might correspond to a different MBB than
5815 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5816 TerminatorInst *TI = LLVMBB->getTerminator();
5818 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5820 // Check successor nodes' PHI nodes that expect a constant to be available
5822 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5823 BasicBlock *SuccBB = TI->getSuccessor(succ);
5824 if (!isa<PHINode>(SuccBB->begin())) continue;
5825 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5827 // If this terminator has multiple identical successors (common for
5828 // switches), only handle each succ once.
5829 if (!SuccsHandled.insert(SuccMBB)) continue;
5831 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5834 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5835 // nodes and Machine PHI nodes, but the incoming operands have not been
5837 for (BasicBlock::iterator I = SuccBB->begin();
5838 (PN = dyn_cast<PHINode>(I)); ++I) {
5839 // Ignore dead phi's.
5840 if (PN->use_empty()) continue;
5843 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5845 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5846 unsigned &RegOut = SDL->ConstantsOut[C];
5848 RegOut = FuncInfo->CreateRegForValue(C);
5849 SDL->CopyValueToVirtualRegister(C, RegOut);
5853 Reg = FuncInfo->ValueMap[PHIOp];
5855 assert(isa<AllocaInst>(PHIOp) &&
5856 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5857 "Didn't codegen value into a register!??");
5858 Reg = FuncInfo->CreateRegForValue(PHIOp);
5859 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5863 // Remember that this register needs to added to the machine PHI node as
5864 // the input for this MBB.
5865 SmallVector<MVT, 4> ValueVTs;
5866 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5867 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5868 MVT VT = ValueVTs[vti];
5869 unsigned NumRegisters = TLI.getNumRegisters(VT);
5870 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5871 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5872 Reg += NumRegisters;
5876 SDL->ConstantsOut.clear();
5879 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5880 /// supports legal types, and it emits MachineInstrs directly instead of
5881 /// creating SelectionDAG nodes.
5884 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5886 TerminatorInst *TI = LLVMBB->getTerminator();
5888 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5889 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5891 // Check successor nodes' PHI nodes that expect a constant to be available
5893 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5894 BasicBlock *SuccBB = TI->getSuccessor(succ);
5895 if (!isa<PHINode>(SuccBB->begin())) continue;
5896 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5898 // If this terminator has multiple identical successors (common for
5899 // switches), only handle each succ once.
5900 if (!SuccsHandled.insert(SuccMBB)) continue;
5902 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5905 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5906 // nodes and Machine PHI nodes, but the incoming operands have not been
5908 for (BasicBlock::iterator I = SuccBB->begin();
5909 (PN = dyn_cast<PHINode>(I)); ++I) {
5910 // Ignore dead phi's.
5911 if (PN->use_empty()) continue;
5913 // Only handle legal types. Two interesting things to note here. First,
5914 // by bailing out early, we may leave behind some dead instructions,
5915 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5916 // own moves. Second, this check is necessary becuase FastISel doesn't
5917 // use CreateRegForValue to create registers, so it always creates
5918 // exactly one register for each non-void instruction.
5919 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5920 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5923 VT = TLI.getTypeToTransformTo(VT);
5925 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5930 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5932 unsigned Reg = F->getRegForValue(PHIOp);
5934 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5937 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));