1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 /// LimitFloatPrecision - Generate low-precision inline sequences for
58 /// some float libcalls (6, 8 or 12 bits).
59 static unsigned LimitFloatPrecision;
61 static cl::opt<unsigned, true>
62 LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
68 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
69 /// of insertvalue or extractvalue indices that identify a member, return
70 /// the linearized index of the start of the member.
72 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
84 EE = STy->element_end();
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 // We haven't found the type we're looking for, so keep searching.
106 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107 /// MVTs that represent all the individual underlying
108 /// non-aggregate types that comprise it.
110 /// If Offsets is non-null, it points to a vector to be filled in
111 /// with the in-memory offsets of each of the individual values.
113 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
122 EE = STy->element_end();
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
137 // Interpret void as zero return values.
138 if (Ty == Type::VoidTy)
140 // Base case: we can get an MVT for this LLVM IR type.
141 ValueVTs.push_back(TLI.getValueType(Ty));
143 Offsets->push_back(StartingOffset);
147 /// RegsForValue - This struct represents the registers (physical or virtual)
148 /// that a particular set of values is assigned, and the type information about
149 /// the value. The most common situation is to represent one value at a time,
150 /// but struct or array values are handled element-wise as multiple values.
151 /// The splitting of aggregates is performed recursively, so that we never
152 /// have aggregate-typed registers. The values at this point do not necessarily
153 /// have legal types, so each value may require one or more registers of some
156 struct VISIBILITY_HIDDEN RegsForValue {
157 /// TLI - The TargetLowering object.
159 const TargetLowering *TLI;
161 /// ValueVTs - The value types of the values, which may not be legal, and
162 /// may need be promoted or synthesized from one or more registers.
164 SmallVector<MVT, 4> ValueVTs;
166 /// RegVTs - The value types of the registers. This is the same size as
167 /// ValueVTs and it records, for each value, what the type of the assigned
168 /// register or registers are. (Individual values are never synthesized
169 /// from more than one type of register.)
171 /// With virtual registers, the contents of RegVTs is redundant with TLI's
172 /// getRegisterType member function, however when with physical registers
173 /// it is necessary to have a separate record of the types.
175 SmallVector<MVT, 4> RegVTs;
177 /// Regs - This list holds the registers assigned to the values.
178 /// Each legal or promoted value requires one register, and each
179 /// expanded value requires multiple registers.
181 SmallVector<unsigned, 4> Regs;
183 RegsForValue() : TLI(0) {}
185 RegsForValue(const TargetLowering &tli,
186 const SmallVector<unsigned, 4> ®s,
187 MVT regvt, MVT valuevt)
188 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
189 RegsForValue(const TargetLowering &tli,
190 const SmallVector<unsigned, 4> ®s,
191 const SmallVector<MVT, 4> ®vts,
192 const SmallVector<MVT, 4> &valuevts)
193 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
194 RegsForValue(const TargetLowering &tli,
195 unsigned Reg, const Type *Ty) : TLI(&tli) {
196 ComputeValueVTs(tli, Ty, ValueVTs);
198 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
199 MVT ValueVT = ValueVTs[Value];
200 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
201 MVT RegisterVT = TLI->getRegisterType(ValueVT);
202 for (unsigned i = 0; i != NumRegs; ++i)
203 Regs.push_back(Reg + i);
204 RegVTs.push_back(RegisterVT);
209 /// append - Add the specified values to this one.
210 void append(const RegsForValue &RHS) {
212 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
213 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
214 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
218 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
219 /// this value and returns the result as a ValueVTs value. This uses
220 /// Chain/Flag as the input and updates them for the output Chain/Flag.
221 /// If the Flag pointer is NULL, no flag is used.
222 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
223 SDValue &Chain, SDValue *Flag) const;
225 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
226 /// specified value into the registers specified by this object. This uses
227 /// Chain/Flag as the input and updates them for the output Chain/Flag.
228 /// If the Flag pointer is NULL, no flag is used.
229 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
230 SDValue &Chain, SDValue *Flag) const;
232 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
233 /// operand list. This adds the code marker, matching input operand index
234 /// (if applicable), and includes the number of values added into it.
235 void AddInlineAsmOperands(unsigned Code,
236 bool HasMatching, unsigned MatchingIdx,
237 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
241 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
242 /// PHI nodes or outside of the basic block that defines it, or used by a
243 /// switch or atomic instruction, which may expand to multiple basic blocks.
244 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
245 if (isa<PHINode>(I)) return true;
246 BasicBlock *BB = I->getParent();
247 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
248 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
253 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
254 /// entry block, return true. This includes arguments used by switches, since
255 /// the switch may expand into multiple basic blocks.
256 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
257 // With FastISel active, we may be splitting blocks, so force creation
258 // of virtual registers for all non-dead arguments.
259 // Don't force virtual registers for byval arguments though, because
260 // fast-isel can't handle those in all cases.
261 if (EnableFastISel && !A->hasByValAttr())
262 return A->use_empty();
264 BasicBlock *Entry = A->getParent()->begin();
265 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
266 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
267 return false; // Use not in entry block.
271 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
275 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
277 bool EnableFastISel) {
280 RegInfo = &MF->getRegInfo();
282 // Create a vreg for each argument register that is not dead and is used
283 // outside of the entry block for the function.
284 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
286 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
287 InitializeRegForValue(AI);
289 // Initialize the mapping of values to registers. This is only set up for
290 // instruction values that are used outside of the block that defines
292 Function::iterator BB = Fn->begin(), EB = Fn->end();
293 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
294 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
295 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
296 const Type *Ty = AI->getAllocatedType();
297 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
299 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
302 TySize *= CUI->getZExtValue(); // Get total allocated size.
303 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
304 StaticAllocaMap[AI] =
305 MF->getFrameInfo()->CreateStackObject(TySize, Align);
308 for (; BB != EB; ++BB)
309 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
310 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
311 if (!isa<AllocaInst>(I) ||
312 !StaticAllocaMap.count(cast<AllocaInst>(I)))
313 InitializeRegForValue(I);
315 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
316 // also creates the initial PHI MachineInstrs, though none of the input
317 // operands are populated.
318 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
319 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
323 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
327 for (BasicBlock::iterator
328 I = BB->begin(), E = BB->end(); I != E; ++I) {
329 if (CallInst *CI = dyn_cast<CallInst>(I)) {
330 if (Function *F = CI->getCalledFunction()) {
331 switch (F->getIntrinsicID()) {
333 case Intrinsic::dbg_stoppoint: {
334 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
336 if (DIDescriptor::ValidDebugInfo(SPI->getContext(),
337 CodeGenOpt::Default)) {
338 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
339 unsigned idx = MF->getOrCreateDebugLocID(CU.getGV(),
342 DL = DebugLoc::get(idx);
347 case Intrinsic::dbg_func_start: {
348 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
349 Value *SP = FSI->getSubprogram();
351 if (DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::Default)) {
352 DISubprogram Subprogram(cast<GlobalVariable>(SP));
353 DICompileUnit CU(Subprogram.getCompileUnit());
354 unsigned Line = Subprogram.getLineNumber();
355 DL = DebugLoc::get(MF->getOrCreateDebugLocID(CU.getGV(),
365 PN = dyn_cast<PHINode>(I);
366 if (!PN || PN->use_empty()) continue;
368 unsigned PHIReg = ValueMap[PN];
369 assert(PHIReg && "PHI node does not have an assigned virtual register!");
371 SmallVector<MVT, 4> ValueVTs;
372 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
373 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
374 MVT VT = ValueVTs[vti];
375 unsigned NumRegisters = TLI.getNumRegisters(VT);
376 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
377 for (unsigned i = 0; i != NumRegisters; ++i)
378 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
379 PHIReg += NumRegisters;
385 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
386 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
389 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
390 /// the correctly promoted or expanded types. Assign these registers
391 /// consecutive vreg numbers and return the first assigned number.
393 /// In the case that the given value has struct or array type, this function
394 /// will assign registers for each member or element.
396 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
397 SmallVector<MVT, 4> ValueVTs;
398 ComputeValueVTs(TLI, V->getType(), ValueVTs);
400 unsigned FirstReg = 0;
401 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
402 MVT ValueVT = ValueVTs[Value];
403 MVT RegisterVT = TLI.getRegisterType(ValueVT);
405 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
406 for (unsigned i = 0; i != NumRegs; ++i) {
407 unsigned R = MakeReg(RegisterVT);
408 if (!FirstReg) FirstReg = R;
414 /// getCopyFromParts - Create a value that contains the specified legal parts
415 /// combined into the value they represent. If the parts combine to a type
416 /// larger then ValueVT then AssertOp can be used to specify whether the extra
417 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
418 /// (ISD::AssertSext).
419 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
420 const SDValue *Parts,
421 unsigned NumParts, MVT PartVT, MVT ValueVT,
422 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
423 assert(NumParts > 0 && "No parts to assemble!");
424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
425 SDValue Val = Parts[0];
428 // Assemble the value from multiple parts.
429 if (!ValueVT.isVector()) {
430 unsigned PartBits = PartVT.getSizeInBits();
431 unsigned ValueBits = ValueVT.getSizeInBits();
433 // Assemble the power of 2 part.
434 unsigned RoundParts = NumParts & (NumParts - 1) ?
435 1 << Log2_32(NumParts) : NumParts;
436 unsigned RoundBits = PartBits * RoundParts;
437 MVT RoundVT = RoundBits == ValueBits ?
438 ValueVT : MVT::getIntegerVT(RoundBits);
441 MVT HalfVT = ValueVT.isInteger() ?
442 MVT::getIntegerVT(RoundBits/2) :
443 MVT::getFloatingPointVT(RoundBits/2);
445 if (RoundParts > 2) {
446 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
447 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
450 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
451 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
453 if (TLI.isBigEndian())
455 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
457 if (RoundParts < NumParts) {
458 // Assemble the trailing non-power-of-2 part.
459 unsigned OddParts = NumParts - RoundParts;
460 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
461 Hi = getCopyFromParts(DAG, dl,
462 Parts+RoundParts, OddParts, PartVT, OddVT);
464 // Combine the round and odd parts.
466 if (TLI.isBigEndian())
468 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
469 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
470 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
471 DAG.getConstant(Lo.getValueType().getSizeInBits(),
472 TLI.getPointerTy()));
473 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
474 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
477 // Handle a multi-element vector.
478 MVT IntermediateVT, RegisterVT;
479 unsigned NumIntermediates;
481 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
483 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
484 NumParts = NumRegs; // Silence a compiler warning.
485 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
486 assert(RegisterVT == Parts[0].getValueType() &&
487 "Part type doesn't match part!");
489 // Assemble the parts into intermediate operands.
490 SmallVector<SDValue, 8> Ops(NumIntermediates);
491 if (NumIntermediates == NumParts) {
492 // If the register was not expanded, truncate or copy the value,
494 for (unsigned i = 0; i != NumParts; ++i)
495 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
496 PartVT, IntermediateVT);
497 } else if (NumParts > 0) {
498 // If the intermediate type was expanded, build the intermediate operands
500 assert(NumParts % NumIntermediates == 0 &&
501 "Must expand into a divisible number of parts!");
502 unsigned Factor = NumParts / NumIntermediates;
503 for (unsigned i = 0; i != NumIntermediates; ++i)
504 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
505 PartVT, IntermediateVT);
508 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
510 Val = DAG.getNode(IntermediateVT.isVector() ?
511 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
512 ValueVT, &Ops[0], NumIntermediates);
516 // There is now one part, held in Val. Correct it to match ValueVT.
517 PartVT = Val.getValueType();
519 if (PartVT == ValueVT)
522 if (PartVT.isVector()) {
523 assert(ValueVT.isVector() && "Unknown vector conversion!");
524 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
527 if (ValueVT.isVector()) {
528 assert(ValueVT.getVectorElementType() == PartVT &&
529 ValueVT.getVectorNumElements() == 1 &&
530 "Only trivial scalar-to-vector conversions should get here!");
531 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
534 if (PartVT.isInteger() &&
535 ValueVT.isInteger()) {
536 if (ValueVT.bitsLT(PartVT)) {
537 // For a truncate, see if we have any information to
538 // indicate whether the truncated bits will always be
539 // zero or sign-extension.
540 if (AssertOp != ISD::DELETED_NODE)
541 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
542 DAG.getValueType(ValueVT));
543 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
545 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
549 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
550 if (ValueVT.bitsLT(Val.getValueType()))
551 // FP_ROUND's are always exact here.
552 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
553 DAG.getIntPtrConstant(1));
554 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
557 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
558 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
560 assert(0 && "Unknown mismatch!");
564 /// getCopyToParts - Create a series of nodes that contain the specified value
565 /// split into legal parts. If the parts contain more bits than Val, then, for
566 /// integers, ExtendKind can be used to specify how to generate the extra bits.
567 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
568 SDValue *Parts, unsigned NumParts, MVT PartVT,
569 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
571 MVT PtrVT = TLI.getPointerTy();
572 MVT ValueVT = Val.getValueType();
573 unsigned PartBits = PartVT.getSizeInBits();
574 unsigned OrigNumParts = NumParts;
575 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
580 if (!ValueVT.isVector()) {
581 if (PartVT == ValueVT) {
582 assert(NumParts == 1 && "No-op copy with multiple parts!");
587 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
588 // If the parts cover more bits than the value has, promote the value.
589 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
590 assert(NumParts == 1 && "Do not know what to promote to!");
591 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
592 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
593 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
594 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
596 assert(0 && "Unknown mismatch!");
598 } else if (PartBits == ValueVT.getSizeInBits()) {
599 // Different types of the same size.
600 assert(NumParts == 1 && PartVT != ValueVT);
601 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
602 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
603 // If the parts cover less bits than value has, truncate the value.
604 if (PartVT.isInteger() && ValueVT.isInteger()) {
605 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
606 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
608 assert(0 && "Unknown mismatch!");
612 // The value may have changed - recompute ValueVT.
613 ValueVT = Val.getValueType();
614 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
615 "Failed to tile the value with PartVT!");
618 assert(PartVT == ValueVT && "Type conversion failed!");
623 // Expand the value into multiple parts.
624 if (NumParts & (NumParts - 1)) {
625 // The number of parts is not a power of 2. Split off and copy the tail.
626 assert(PartVT.isInteger() && ValueVT.isInteger() &&
627 "Do not know what to expand to!");
628 unsigned RoundParts = 1 << Log2_32(NumParts);
629 unsigned RoundBits = RoundParts * PartBits;
630 unsigned OddParts = NumParts - RoundParts;
631 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
632 DAG.getConstant(RoundBits,
633 TLI.getPointerTy()));
634 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
635 if (TLI.isBigEndian())
636 // The odd parts were reversed by getCopyToParts - unreverse them.
637 std::reverse(Parts + RoundParts, Parts + NumParts);
638 NumParts = RoundParts;
639 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
640 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
643 // The number of parts is a power of 2. Repeatedly bisect the value using
645 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
646 MVT::getIntegerVT(ValueVT.getSizeInBits()),
648 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
649 for (unsigned i = 0; i < NumParts; i += StepSize) {
650 unsigned ThisBits = StepSize * PartBits / 2;
651 MVT ThisVT = MVT::getIntegerVT (ThisBits);
652 SDValue &Part0 = Parts[i];
653 SDValue &Part1 = Parts[i+StepSize/2];
655 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
657 DAG.getConstant(1, PtrVT));
658 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(0, PtrVT));
662 if (ThisBits == PartBits && ThisVT != PartVT) {
663 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
665 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
671 if (TLI.isBigEndian())
672 std::reverse(Parts, Parts + OrigNumParts);
679 if (PartVT != ValueVT) {
680 if (PartVT.isVector()) {
681 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
683 assert(ValueVT.getVectorElementType() == PartVT &&
684 ValueVT.getVectorNumElements() == 1 &&
685 "Only trivial vector-to-scalar conversions should get here!");
686 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
688 DAG.getConstant(0, PtrVT));
696 // Handle a multi-element vector.
697 MVT IntermediateVT, RegisterVT;
698 unsigned NumIntermediates;
699 unsigned NumRegs = TLI
700 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
702 unsigned NumElements = ValueVT.getVectorNumElements();
704 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
705 NumParts = NumRegs; // Silence a compiler warning.
706 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
708 // Split the vector into intermediate operands.
709 SmallVector<SDValue, 8> Ops(NumIntermediates);
710 for (unsigned i = 0; i != NumIntermediates; ++i)
711 if (IntermediateVT.isVector())
712 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
714 DAG.getConstant(i * (NumElements / NumIntermediates),
717 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
719 DAG.getConstant(i, PtrVT));
721 // Split the intermediate operands into legal parts.
722 if (NumParts == NumIntermediates) {
723 // If the register was not expanded, promote or copy the value,
725 for (unsigned i = 0; i != NumParts; ++i)
726 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
727 } else if (NumParts > 0) {
728 // If the intermediate type was expanded, split each the value into
730 assert(NumParts % NumIntermediates == 0 &&
731 "Must expand into a divisible number of parts!");
732 unsigned Factor = NumParts / NumIntermediates;
733 for (unsigned i = 0; i != NumIntermediates; ++i)
734 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
739 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
742 TD = DAG.getTarget().getTargetData();
745 /// clear - Clear out the curret SelectionDAG and the associated
746 /// state and prepare this SelectionDAGLowering object to be used
747 /// for a new block. This doesn't clear out information about
748 /// additional blocks that are needed to complete switch lowering
749 /// or PHI node updating; that information is cleared out as it is
751 void SelectionDAGLowering::clear() {
753 PendingLoads.clear();
754 PendingExports.clear();
756 CurDebugLoc = DebugLoc::getUnknownLoc();
759 /// getRoot - Return the current virtual root of the Selection DAG,
760 /// flushing any PendingLoad items. This must be done before emitting
761 /// a store or any other node that may need to be ordered after any
762 /// prior load instructions.
764 SDValue SelectionDAGLowering::getRoot() {
765 if (PendingLoads.empty())
766 return DAG.getRoot();
768 if (PendingLoads.size() == 1) {
769 SDValue Root = PendingLoads[0];
771 PendingLoads.clear();
775 // Otherwise, we have to make a token factor node.
776 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
777 &PendingLoads[0], PendingLoads.size());
778 PendingLoads.clear();
783 /// getControlRoot - Similar to getRoot, but instead of flushing all the
784 /// PendingLoad items, flush all the PendingExports items. It is necessary
785 /// to do this before emitting a terminator instruction.
787 SDValue SelectionDAGLowering::getControlRoot() {
788 SDValue Root = DAG.getRoot();
790 if (PendingExports.empty())
793 // Turn all of the CopyToReg chains into one factored node.
794 if (Root.getOpcode() != ISD::EntryToken) {
795 unsigned i = 0, e = PendingExports.size();
796 for (; i != e; ++i) {
797 assert(PendingExports[i].getNode()->getNumOperands() > 1);
798 if (PendingExports[i].getNode()->getOperand(0) == Root)
799 break; // Don't add the root if we already indirectly depend on it.
803 PendingExports.push_back(Root);
806 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
808 PendingExports.size());
809 PendingExports.clear();
814 void SelectionDAGLowering::visit(Instruction &I) {
815 visit(I.getOpcode(), I);
818 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
819 // Note: this doesn't use InstVisitor, because it has to work with
820 // ConstantExpr's in addition to instructions.
822 default: assert(0 && "Unknown instruction type encountered!");
824 // Build the switch statement using the Instruction.def file.
825 #define HANDLE_INST(NUM, OPCODE, CLASS) \
826 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
827 #include "llvm/Instruction.def"
831 void SelectionDAGLowering::visitAdd(User &I) {
832 if (I.getType()->isFPOrFPVector())
833 visitBinary(I, ISD::FADD);
835 visitBinary(I, ISD::ADD);
838 void SelectionDAGLowering::visitMul(User &I) {
839 if (I.getType()->isFPOrFPVector())
840 visitBinary(I, ISD::FMUL);
842 visitBinary(I, ISD::MUL);
845 SDValue SelectionDAGLowering::getValue(const Value *V) {
846 SDValue &N = NodeMap[V];
847 if (N.getNode()) return N;
849 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
850 MVT VT = TLI.getValueType(V->getType(), true);
852 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
853 return N = DAG.getConstant(*CI, VT);
855 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
856 return N = DAG.getGlobalAddress(GV, VT);
858 if (isa<ConstantPointerNull>(C))
859 return N = DAG.getConstant(0, TLI.getPointerTy());
861 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
862 return N = DAG.getConstantFP(*CFP, VT);
864 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
865 return N = DAG.getUNDEF(VT);
867 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
868 visit(CE->getOpcode(), *CE);
869 SDValue N1 = NodeMap[V];
870 assert(N1.getNode() && "visit didn't populate the ValueMap!");
874 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
875 SmallVector<SDValue, 4> Constants;
876 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
878 SDNode *Val = getValue(*OI).getNode();
879 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
880 Constants.push_back(SDValue(Val, i));
882 return DAG.getMergeValues(&Constants[0], Constants.size(),
886 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
887 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
888 "Unknown struct or array constant!");
890 SmallVector<MVT, 4> ValueVTs;
891 ComputeValueVTs(TLI, C->getType(), ValueVTs);
892 unsigned NumElts = ValueVTs.size();
894 return SDValue(); // empty struct
895 SmallVector<SDValue, 4> Constants(NumElts);
896 for (unsigned i = 0; i != NumElts; ++i) {
897 MVT EltVT = ValueVTs[i];
898 if (isa<UndefValue>(C))
899 Constants[i] = DAG.getUNDEF(EltVT);
900 else if (EltVT.isFloatingPoint())
901 Constants[i] = DAG.getConstantFP(0, EltVT);
903 Constants[i] = DAG.getConstant(0, EltVT);
905 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
908 const VectorType *VecTy = cast<VectorType>(V->getType());
909 unsigned NumElements = VecTy->getNumElements();
911 // Now that we know the number and type of the elements, get that number of
912 // elements into the Ops array based on what kind of constant it is.
913 SmallVector<SDValue, 16> Ops;
914 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
915 for (unsigned i = 0; i != NumElements; ++i)
916 Ops.push_back(getValue(CP->getOperand(i)));
918 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
919 MVT EltVT = TLI.getValueType(VecTy->getElementType());
922 if (EltVT.isFloatingPoint())
923 Op = DAG.getConstantFP(0, EltVT);
925 Op = DAG.getConstant(0, EltVT);
926 Ops.assign(NumElements, Op);
929 // Create a BUILD_VECTOR node.
930 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
931 VT, &Ops[0], Ops.size());
934 // If this is a static alloca, generate it as the frameindex instead of
936 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
937 DenseMap<const AllocaInst*, int>::iterator SI =
938 FuncInfo.StaticAllocaMap.find(AI);
939 if (SI != FuncInfo.StaticAllocaMap.end())
940 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
943 unsigned InReg = FuncInfo.ValueMap[V];
944 assert(InReg && "Value not in map!");
946 RegsForValue RFV(TLI, InReg, V->getType());
947 SDValue Chain = DAG.getEntryNode();
948 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
952 void SelectionDAGLowering::visitRet(ReturnInst &I) {
953 if (I.getNumOperands() == 0) {
954 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
955 MVT::Other, getControlRoot()));
959 SmallVector<SDValue, 8> NewValues;
960 NewValues.push_back(getControlRoot());
961 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
962 SmallVector<MVT, 4> ValueVTs;
963 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
964 unsigned NumValues = ValueVTs.size();
965 if (NumValues == 0) continue;
967 SDValue RetOp = getValue(I.getOperand(i));
968 for (unsigned j = 0, f = NumValues; j != f; ++j) {
969 MVT VT = ValueVTs[j];
971 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
973 const Function *F = I.getParent()->getParent();
974 if (F->paramHasAttr(0, Attribute::SExt))
975 ExtendKind = ISD::SIGN_EXTEND;
976 else if (F->paramHasAttr(0, Attribute::ZExt))
977 ExtendKind = ISD::ZERO_EXTEND;
979 // FIXME: C calling convention requires the return type to be promoted to
980 // at least 32-bit. But this is not necessary for non-C calling
981 // conventions. The frontend should mark functions whose return values
982 // require promoting with signext or zeroext attributes.
983 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
984 MVT MinVT = TLI.getRegisterType(MVT::i32);
985 if (VT.bitsLT(MinVT))
989 unsigned NumParts = TLI.getNumRegisters(VT);
990 MVT PartVT = TLI.getRegisterType(VT);
991 SmallVector<SDValue, 4> Parts(NumParts);
992 getCopyToParts(DAG, getCurDebugLoc(),
993 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
994 &Parts[0], NumParts, PartVT, ExtendKind);
996 // 'inreg' on function refers to return value
997 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
998 if (F->paramHasAttr(0, Attribute::InReg))
1000 for (unsigned i = 0; i < NumParts; ++i) {
1001 NewValues.push_back(Parts[i]);
1002 NewValues.push_back(DAG.getArgFlags(Flags));
1006 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1007 &NewValues[0], NewValues.size()));
1010 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1011 /// created for it, emit nodes to copy the value into the virtual
1013 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1014 if (!V->use_empty()) {
1015 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1016 if (VMI != FuncInfo.ValueMap.end())
1017 CopyValueToVirtualRegister(V, VMI->second);
1021 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1022 /// the current basic block, add it to ValueMap now so that we'll get a
1024 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1025 // No need to export constants.
1026 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1028 // Already exported?
1029 if (FuncInfo.isExportedInst(V)) return;
1031 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1032 CopyValueToVirtualRegister(V, Reg);
1035 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1036 const BasicBlock *FromBB) {
1037 // The operands of the setcc have to be in this block. We don't know
1038 // how to export them from some other block.
1039 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1040 // Can export from current BB.
1041 if (VI->getParent() == FromBB)
1044 // Is already exported, noop.
1045 return FuncInfo.isExportedInst(V);
1048 // If this is an argument, we can export it if the BB is the entry block or
1049 // if it is already exported.
1050 if (isa<Argument>(V)) {
1051 if (FromBB == &FromBB->getParent()->getEntryBlock())
1054 // Otherwise, can only export this if it is already exported.
1055 return FuncInfo.isExportedInst(V);
1058 // Otherwise, constants can always be exported.
1062 static bool InBlock(const Value *V, const BasicBlock *BB) {
1063 if (const Instruction *I = dyn_cast<Instruction>(V))
1064 return I->getParent() == BB;
1068 /// getFCmpCondCode - Return the ISD condition code corresponding to
1069 /// the given LLVM IR floating-point condition code. This includes
1070 /// consideration of global floating-point math flags.
1072 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1073 ISD::CondCode FPC, FOC;
1075 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1076 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1077 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1078 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1079 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1080 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1081 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1082 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1083 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1084 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1085 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1086 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1087 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1088 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1089 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1090 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1092 assert(0 && "Invalid FCmp predicate opcode!");
1093 FOC = FPC = ISD::SETFALSE;
1096 if (FiniteOnlyFPMath())
1102 /// getICmpCondCode - Return the ISD condition code corresponding to
1103 /// the given LLVM IR integer condition code.
1105 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1107 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1108 case ICmpInst::ICMP_NE: return ISD::SETNE;
1109 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1110 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1111 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1112 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1113 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1114 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1115 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1116 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1118 assert(0 && "Invalid ICmp predicate opcode!");
1123 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1124 /// This function emits a branch and is used at the leaves of an OR or an
1125 /// AND operator tree.
1128 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1129 MachineBasicBlock *TBB,
1130 MachineBasicBlock *FBB,
1131 MachineBasicBlock *CurBB) {
1132 const BasicBlock *BB = CurBB->getBasicBlock();
1134 // If the leaf of the tree is a comparison, merge the condition into
1136 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1137 // The operands of the cmp have to be in this block. We don't know
1138 // how to export them from some other block. If this is the first block
1139 // of the sequence, no exporting is needed.
1140 if (CurBB == CurMBB ||
1141 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1142 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1143 ISD::CondCode Condition;
1144 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1145 Condition = getICmpCondCode(IC->getPredicate());
1146 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1147 Condition = getFCmpCondCode(FC->getPredicate());
1149 Condition = ISD::SETEQ; // silence warning.
1150 assert(0 && "Unknown compare instruction");
1153 CaseBlock CB(Condition, BOp->getOperand(0),
1154 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1155 SwitchCases.push_back(CB);
1160 // Create a CaseBlock record representing this branch.
1161 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1162 NULL, TBB, FBB, CurBB);
1163 SwitchCases.push_back(CB);
1166 /// FindMergedConditions - If Cond is an expression like
1167 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1168 MachineBasicBlock *TBB,
1169 MachineBasicBlock *FBB,
1170 MachineBasicBlock *CurBB,
1172 // If this node is not part of the or/and tree, emit it as a branch.
1173 Instruction *BOp = dyn_cast<Instruction>(Cond);
1174 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1175 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1176 BOp->getParent() != CurBB->getBasicBlock() ||
1177 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1178 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1179 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1183 // Create TmpBB after CurBB.
1184 MachineFunction::iterator BBI = CurBB;
1185 MachineFunction &MF = DAG.getMachineFunction();
1186 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1187 CurBB->getParent()->insert(++BBI, TmpBB);
1189 if (Opc == Instruction::Or) {
1190 // Codegen X | Y as:
1198 // Emit the LHS condition.
1199 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1201 // Emit the RHS condition into TmpBB.
1202 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1204 assert(Opc == Instruction::And && "Unknown merge op!");
1205 // Codegen X & Y as:
1212 // This requires creation of TmpBB after CurBB.
1214 // Emit the LHS condition.
1215 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1217 // Emit the RHS condition into TmpBB.
1218 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1222 /// If the set of cases should be emitted as a series of branches, return true.
1223 /// If we should emit this as a bunch of and/or'd together conditions, return
1226 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1227 if (Cases.size() != 2) return true;
1229 // If this is two comparisons of the same values or'd or and'd together, they
1230 // will get folded into a single comparison, so don't emit two blocks.
1231 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1232 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1233 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1234 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1241 void SelectionDAGLowering::visitBr(BranchInst &I) {
1242 // Update machine-CFG edges.
1243 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1245 // Figure out which block is immediately after the current one.
1246 MachineBasicBlock *NextBlock = 0;
1247 MachineFunction::iterator BBI = CurMBB;
1248 if (++BBI != CurMBB->getParent()->end())
1251 if (I.isUnconditional()) {
1252 // Update machine-CFG edges.
1253 CurMBB->addSuccessor(Succ0MBB);
1255 // If this is not a fall-through branch, emit the branch.
1256 if (Succ0MBB != NextBlock)
1257 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1258 MVT::Other, getControlRoot(),
1259 DAG.getBasicBlock(Succ0MBB)));
1263 // If this condition is one of the special cases we handle, do special stuff
1265 Value *CondVal = I.getCondition();
1266 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1268 // If this is a series of conditions that are or'd or and'd together, emit
1269 // this as a sequence of branches instead of setcc's with and/or operations.
1270 // For example, instead of something like:
1283 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1284 if (BOp->hasOneUse() &&
1285 (BOp->getOpcode() == Instruction::And ||
1286 BOp->getOpcode() == Instruction::Or)) {
1287 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1288 // If the compares in later blocks need to use values not currently
1289 // exported from this block, export them now. This block should always
1290 // be the first entry.
1291 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1293 // Allow some cases to be rejected.
1294 if (ShouldEmitAsBranches(SwitchCases)) {
1295 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1296 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1297 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1300 // Emit the branch for this block.
1301 visitSwitchCase(SwitchCases[0]);
1302 SwitchCases.erase(SwitchCases.begin());
1306 // Okay, we decided not to do this, remove any inserted MBB's and clear
1308 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1309 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1311 SwitchCases.clear();
1315 // Create a CaseBlock record representing this branch.
1316 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1317 NULL, Succ0MBB, Succ1MBB, CurMBB);
1318 // Use visitSwitchCase to actually insert the fast branch sequence for this
1320 visitSwitchCase(CB);
1323 /// visitSwitchCase - Emits the necessary code to represent a single node in
1324 /// the binary search tree resulting from lowering a switch instruction.
1325 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1327 SDValue CondLHS = getValue(CB.CmpLHS);
1328 DebugLoc dl = getCurDebugLoc();
1330 // Build the setcc now.
1331 if (CB.CmpMHS == NULL) {
1332 // Fold "(X == true)" to X and "(X == false)" to !X to
1333 // handle common cases produced by branch lowering.
1334 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1336 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1337 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1338 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1340 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1342 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1344 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1345 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1347 SDValue CmpOp = getValue(CB.CmpMHS);
1348 MVT VT = CmpOp.getValueType();
1350 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1351 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1354 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1355 VT, CmpOp, DAG.getConstant(Low, VT));
1356 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1357 DAG.getConstant(High-Low, VT), ISD::SETULE);
1361 // Update successor info
1362 CurMBB->addSuccessor(CB.TrueBB);
1363 CurMBB->addSuccessor(CB.FalseBB);
1365 // Set NextBlock to be the MBB immediately after the current one, if any.
1366 // This is used to avoid emitting unnecessary branches to the next block.
1367 MachineBasicBlock *NextBlock = 0;
1368 MachineFunction::iterator BBI = CurMBB;
1369 if (++BBI != CurMBB->getParent()->end())
1372 // If the lhs block is the next block, invert the condition so that we can
1373 // fall through to the lhs instead of the rhs block.
1374 if (CB.TrueBB == NextBlock) {
1375 std::swap(CB.TrueBB, CB.FalseBB);
1376 SDValue True = DAG.getConstant(1, Cond.getValueType());
1377 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1379 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1380 MVT::Other, getControlRoot(), Cond,
1381 DAG.getBasicBlock(CB.TrueBB));
1383 // If the branch was constant folded, fix up the CFG.
1384 if (BrCond.getOpcode() == ISD::BR) {
1385 CurMBB->removeSuccessor(CB.FalseBB);
1386 DAG.setRoot(BrCond);
1388 // Otherwise, go ahead and insert the false branch.
1389 if (BrCond == getControlRoot())
1390 CurMBB->removeSuccessor(CB.TrueBB);
1392 if (CB.FalseBB == NextBlock)
1393 DAG.setRoot(BrCond);
1395 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1396 DAG.getBasicBlock(CB.FalseBB)));
1400 /// visitJumpTable - Emit JumpTable node in the current MBB
1401 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1402 // Emit the code for the jump table
1403 assert(JT.Reg != -1U && "Should lower JT Header first!");
1404 MVT PTy = TLI.getPointerTy();
1405 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1407 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1408 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1409 MVT::Other, Index.getValue(1),
1413 /// visitJumpTableHeader - This function emits necessary code to produce index
1414 /// in the JumpTable from switch case.
1415 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1416 JumpTableHeader &JTH) {
1417 // Subtract the lowest switch case value from the value being switched on and
1418 // conditional branch to default mbb if the result is greater than the
1419 // difference between smallest and largest cases.
1420 SDValue SwitchOp = getValue(JTH.SValue);
1421 MVT VT = SwitchOp.getValueType();
1422 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1423 DAG.getConstant(JTH.First, VT));
1425 // The SDNode we just created, which holds the value being switched on minus
1426 // the the smallest case value, needs to be copied to a virtual register so it
1427 // can be used as an index into the jump table in a subsequent basic block.
1428 // This value may be smaller or larger than the target's pointer type, and
1429 // therefore require extension or truncating.
1430 if (VT.bitsGT(TLI.getPointerTy()))
1431 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1432 TLI.getPointerTy(), SUB);
1434 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1435 TLI.getPointerTy(), SUB);
1437 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1438 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1439 JumpTableReg, SwitchOp);
1440 JT.Reg = JumpTableReg;
1442 // Emit the range check for the jump table, and branch to the default block
1443 // for the switch statement if the value being switched on exceeds the largest
1444 // case in the switch.
1445 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1446 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1447 DAG.getConstant(JTH.Last-JTH.First,VT),
1450 // Set NextBlock to be the MBB immediately after the current one, if any.
1451 // This is used to avoid emitting unnecessary branches to the next block.
1452 MachineBasicBlock *NextBlock = 0;
1453 MachineFunction::iterator BBI = CurMBB;
1454 if (++BBI != CurMBB->getParent()->end())
1457 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1458 MVT::Other, CopyTo, CMP,
1459 DAG.getBasicBlock(JT.Default));
1461 if (JT.MBB == NextBlock)
1462 DAG.setRoot(BrCond);
1464 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1465 DAG.getBasicBlock(JT.MBB)));
1468 /// visitBitTestHeader - This function emits necessary code to produce value
1469 /// suitable for "bit tests"
1470 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1471 // Subtract the minimum value
1472 SDValue SwitchOp = getValue(B.SValue);
1473 MVT VT = SwitchOp.getValueType();
1474 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1475 DAG.getConstant(B.First, VT));
1478 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1479 TLI.getSetCCResultType(SUB.getValueType()),
1480 SUB, DAG.getConstant(B.Range, VT),
1484 if (VT.bitsGT(TLI.getPointerTy()))
1485 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1486 TLI.getPointerTy(), SUB);
1488 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1489 TLI.getPointerTy(), SUB);
1491 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1492 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1495 // Set NextBlock to be the MBB immediately after the current one, if any.
1496 // This is used to avoid emitting unnecessary branches to the next block.
1497 MachineBasicBlock *NextBlock = 0;
1498 MachineFunction::iterator BBI = CurMBB;
1499 if (++BBI != CurMBB->getParent()->end())
1502 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1504 CurMBB->addSuccessor(B.Default);
1505 CurMBB->addSuccessor(MBB);
1507 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1508 MVT::Other, CopyTo, RangeCmp,
1509 DAG.getBasicBlock(B.Default));
1511 if (MBB == NextBlock)
1512 DAG.setRoot(BrRange);
1514 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1515 DAG.getBasicBlock(MBB)));
1518 /// visitBitTestCase - this function produces one "bit test"
1519 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1522 // Make desired shift
1523 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1524 TLI.getPointerTy());
1525 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1527 DAG.getConstant(1, TLI.getPointerTy()),
1530 // Emit bit tests and jumps
1531 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1532 TLI.getPointerTy(), SwitchVal,
1533 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1534 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1535 TLI.getSetCCResultType(AndOp.getValueType()),
1536 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1539 CurMBB->addSuccessor(B.TargetBB);
1540 CurMBB->addSuccessor(NextMBB);
1542 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1543 MVT::Other, getControlRoot(),
1544 AndCmp, DAG.getBasicBlock(B.TargetBB));
1546 // Set NextBlock to be the MBB immediately after the current one, if any.
1547 // This is used to avoid emitting unnecessary branches to the next block.
1548 MachineBasicBlock *NextBlock = 0;
1549 MachineFunction::iterator BBI = CurMBB;
1550 if (++BBI != CurMBB->getParent()->end())
1553 if (NextMBB == NextBlock)
1556 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1557 DAG.getBasicBlock(NextMBB)));
1560 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1561 // Retrieve successors.
1562 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1563 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1565 const Value *Callee(I.getCalledValue());
1566 if (isa<InlineAsm>(Callee))
1569 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1571 // If the value of the invoke is used outside of its defining block, make it
1572 // available as a virtual register.
1573 CopyToExportRegsIfNeeded(&I);
1575 // Update successor info
1576 CurMBB->addSuccessor(Return);
1577 CurMBB->addSuccessor(LandingPad);
1579 // Drop into normal successor.
1580 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1581 MVT::Other, getControlRoot(),
1582 DAG.getBasicBlock(Return)));
1585 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1588 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1589 /// small case ranges).
1590 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1591 CaseRecVector& WorkList,
1593 MachineBasicBlock* Default) {
1594 Case& BackCase = *(CR.Range.second-1);
1596 // Size is the number of Cases represented by this range.
1597 size_t Size = CR.Range.second - CR.Range.first;
1601 // Get the MachineFunction which holds the current MBB. This is used when
1602 // inserting any additional MBBs necessary to represent the switch.
1603 MachineFunction *CurMF = CurMBB->getParent();
1605 // Figure out which block is immediately after the current one.
1606 MachineBasicBlock *NextBlock = 0;
1607 MachineFunction::iterator BBI = CR.CaseBB;
1609 if (++BBI != CurMBB->getParent()->end())
1612 // TODO: If any two of the cases has the same destination, and if one value
1613 // is the same as the other, but has one bit unset that the other has set,
1614 // use bit manipulation to do two compares at once. For example:
1615 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1617 // Rearrange the case blocks so that the last one falls through if possible.
1618 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1619 // The last case block won't fall through into 'NextBlock' if we emit the
1620 // branches in this order. See if rearranging a case value would help.
1621 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1622 if (I->BB == NextBlock) {
1623 std::swap(*I, BackCase);
1629 // Create a CaseBlock record representing a conditional branch to
1630 // the Case's target mbb if the value being switched on SV is equal
1632 MachineBasicBlock *CurBlock = CR.CaseBB;
1633 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1634 MachineBasicBlock *FallThrough;
1636 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1637 CurMF->insert(BBI, FallThrough);
1639 // Put SV in a virtual register to make it available from the new blocks.
1640 ExportFromCurrentBlock(SV);
1642 // If the last case doesn't match, go to the default block.
1643 FallThrough = Default;
1646 Value *RHS, *LHS, *MHS;
1648 if (I->High == I->Low) {
1649 // This is just small small case range :) containing exactly 1 case
1651 LHS = SV; RHS = I->High; MHS = NULL;
1654 LHS = I->Low; MHS = SV; RHS = I->High;
1656 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1658 // If emitting the first comparison, just call visitSwitchCase to emit the
1659 // code into the current block. Otherwise, push the CaseBlock onto the
1660 // vector to be later processed by SDISel, and insert the node's MBB
1661 // before the next MBB.
1662 if (CurBlock == CurMBB)
1663 visitSwitchCase(CB);
1665 SwitchCases.push_back(CB);
1667 CurBlock = FallThrough;
1673 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1674 return !DisableJumpTables &&
1675 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1676 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1679 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1680 APInt LastExt(Last), FirstExt(First);
1681 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1682 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1683 return (LastExt - FirstExt + 1ULL);
1686 /// handleJTSwitchCase - Emit jumptable for current switch case range
1687 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1688 CaseRecVector& WorkList,
1690 MachineBasicBlock* Default) {
1691 Case& FrontCase = *CR.Range.first;
1692 Case& BackCase = *(CR.Range.second-1);
1694 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1695 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1698 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1702 if (!areJTsAllowed(TLI) || TSize <= 3)
1705 APInt Range = ComputeRange(First, Last);
1706 double Density = (double)TSize / Range.roundToDouble();
1710 DEBUG(errs() << "Lowering jump table\n"
1711 << "First entry: " << First << ". Last entry: " << Last << '\n'
1712 << "Range: " << Range
1713 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1715 // Get the MachineFunction which holds the current MBB. This is used when
1716 // inserting any additional MBBs necessary to represent the switch.
1717 MachineFunction *CurMF = CurMBB->getParent();
1719 // Figure out which block is immediately after the current one.
1720 MachineBasicBlock *NextBlock = 0;
1721 MachineFunction::iterator BBI = CR.CaseBB;
1723 if (++BBI != CurMBB->getParent()->end())
1726 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1728 // Create a new basic block to hold the code for loading the address
1729 // of the jump table, and jumping to it. Update successor information;
1730 // we will either branch to the default case for the switch, or the jump
1732 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1733 CurMF->insert(BBI, JumpTableBB);
1734 CR.CaseBB->addSuccessor(Default);
1735 CR.CaseBB->addSuccessor(JumpTableBB);
1737 // Build a vector of destination BBs, corresponding to each target
1738 // of the jump table. If the value of the jump table slot corresponds to
1739 // a case statement, push the case's BB onto the vector, otherwise, push
1741 std::vector<MachineBasicBlock*> DestBBs;
1743 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1744 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1745 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1747 if (Low.sle(TEI) && TEI.sle(High)) {
1748 DestBBs.push_back(I->BB);
1752 DestBBs.push_back(Default);
1756 // Update successor info. Add one edge to each unique successor.
1757 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1758 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1759 E = DestBBs.end(); I != E; ++I) {
1760 if (!SuccsHandled[(*I)->getNumber()]) {
1761 SuccsHandled[(*I)->getNumber()] = true;
1762 JumpTableBB->addSuccessor(*I);
1766 // Create a jump table index for this jump table, or return an existing
1768 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1770 // Set the jump table information so that we can codegen it as a second
1771 // MachineBasicBlock
1772 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1773 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1774 if (CR.CaseBB == CurMBB)
1775 visitJumpTableHeader(JT, JTH);
1777 JTCases.push_back(JumpTableBlock(JTH, JT));
1782 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1784 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1785 CaseRecVector& WorkList,
1787 MachineBasicBlock* Default) {
1788 // Get the MachineFunction which holds the current MBB. This is used when
1789 // inserting any additional MBBs necessary to represent the switch.
1790 MachineFunction *CurMF = CurMBB->getParent();
1792 // Figure out which block is immediately after the current one.
1793 MachineBasicBlock *NextBlock = 0;
1794 MachineFunction::iterator BBI = CR.CaseBB;
1796 if (++BBI != CurMBB->getParent()->end())
1799 Case& FrontCase = *CR.Range.first;
1800 Case& BackCase = *(CR.Range.second-1);
1801 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1803 // Size is the number of Cases represented by this range.
1804 unsigned Size = CR.Range.second - CR.Range.first;
1806 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1807 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1809 CaseItr Pivot = CR.Range.first + Size/2;
1811 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1812 // (heuristically) allow us to emit JumpTable's later.
1814 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1818 size_t LSize = FrontCase.size();
1819 size_t RSize = TSize-LSize;
1820 DEBUG(errs() << "Selecting best pivot: \n"
1821 << "First: " << First << ", Last: " << Last <<'\n'
1822 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1823 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1825 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1826 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1827 APInt Range = ComputeRange(LEnd, RBegin);
1828 assert((Range - 2ULL).isNonNegative() &&
1829 "Invalid case distance");
1830 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1831 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1832 double Metric = Range.logBase2()*(LDensity+RDensity);
1833 // Should always split in some non-trivial place
1834 DEBUG(errs() <<"=>Step\n"
1835 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1836 << "LDensity: " << LDensity
1837 << ", RDensity: " << RDensity << '\n'
1838 << "Metric: " << Metric << '\n');
1839 if (FMetric < Metric) {
1842 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1848 if (areJTsAllowed(TLI)) {
1849 // If our case is dense we *really* should handle it earlier!
1850 assert((FMetric > 0) && "Should handle dense range earlier!");
1852 Pivot = CR.Range.first + Size/2;
1855 CaseRange LHSR(CR.Range.first, Pivot);
1856 CaseRange RHSR(Pivot, CR.Range.second);
1857 Constant *C = Pivot->Low;
1858 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1860 // We know that we branch to the LHS if the Value being switched on is
1861 // less than the Pivot value, C. We use this to optimize our binary
1862 // tree a bit, by recognizing that if SV is greater than or equal to the
1863 // LHS's Case Value, and that Case Value is exactly one less than the
1864 // Pivot's Value, then we can branch directly to the LHS's Target,
1865 // rather than creating a leaf node for it.
1866 if ((LHSR.second - LHSR.first) == 1 &&
1867 LHSR.first->High == CR.GE &&
1868 cast<ConstantInt>(C)->getValue() ==
1869 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1870 TrueBB = LHSR.first->BB;
1872 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1873 CurMF->insert(BBI, TrueBB);
1874 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1876 // Put SV in a virtual register to make it available from the new blocks.
1877 ExportFromCurrentBlock(SV);
1880 // Similar to the optimization above, if the Value being switched on is
1881 // known to be less than the Constant CR.LT, and the current Case Value
1882 // is CR.LT - 1, then we can branch directly to the target block for
1883 // the current Case Value, rather than emitting a RHS leaf node for it.
1884 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1885 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1886 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1887 FalseBB = RHSR.first->BB;
1889 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1890 CurMF->insert(BBI, FalseBB);
1891 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1893 // Put SV in a virtual register to make it available from the new blocks.
1894 ExportFromCurrentBlock(SV);
1897 // Create a CaseBlock record representing a conditional branch to
1898 // the LHS node if the value being switched on SV is less than C.
1899 // Otherwise, branch to LHS.
1900 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1902 if (CR.CaseBB == CurMBB)
1903 visitSwitchCase(CB);
1905 SwitchCases.push_back(CB);
1910 /// handleBitTestsSwitchCase - if current case range has few destination and
1911 /// range span less, than machine word bitwidth, encode case range into series
1912 /// of masks and emit bit tests with these masks.
1913 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1914 CaseRecVector& WorkList,
1916 MachineBasicBlock* Default){
1917 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1919 Case& FrontCase = *CR.Range.first;
1920 Case& BackCase = *(CR.Range.second-1);
1922 // Get the MachineFunction which holds the current MBB. This is used when
1923 // inserting any additional MBBs necessary to represent the switch.
1924 MachineFunction *CurMF = CurMBB->getParent();
1927 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1929 // Single case counts one, case range - two.
1930 numCmps += (I->Low == I->High ? 1 : 2);
1933 // Count unique destinations
1934 SmallSet<MachineBasicBlock*, 4> Dests;
1935 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1936 Dests.insert(I->BB);
1937 if (Dests.size() > 3)
1938 // Don't bother the code below, if there are too much unique destinations
1941 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1942 << "Total number of comparisons: " << numCmps << '\n');
1944 // Compute span of values.
1945 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1946 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1947 APInt cmpRange = maxValue - minValue;
1949 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1950 << "Low bound: " << minValue << '\n'
1951 << "High bound: " << maxValue << '\n');
1953 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1954 (!(Dests.size() == 1 && numCmps >= 3) &&
1955 !(Dests.size() == 2 && numCmps >= 5) &&
1956 !(Dests.size() >= 3 && numCmps >= 6)))
1959 DEBUG(errs() << "Emitting bit tests\n");
1960 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1962 // Optimize the case where all the case values fit in a
1963 // word without having to subtract minValue. In this case,
1964 // we can optimize away the subtraction.
1965 if (minValue.isNonNegative() &&
1966 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1967 cmpRange = maxValue;
1969 lowBound = minValue;
1972 CaseBitsVector CasesBits;
1973 unsigned i, count = 0;
1975 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1976 MachineBasicBlock* Dest = I->BB;
1977 for (i = 0; i < count; ++i)
1978 if (Dest == CasesBits[i].BB)
1982 assert((count < 3) && "Too much destinations to test!");
1983 CasesBits.push_back(CaseBits(0, Dest, 0));
1987 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1988 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1990 uint64_t lo = (lowValue - lowBound).getZExtValue();
1991 uint64_t hi = (highValue - lowBound).getZExtValue();
1993 for (uint64_t j = lo; j <= hi; j++) {
1994 CasesBits[i].Mask |= 1ULL << j;
1995 CasesBits[i].Bits++;
1999 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2003 // Figure out which block is immediately after the current one.
2004 MachineFunction::iterator BBI = CR.CaseBB;
2007 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2009 DEBUG(errs() << "Cases:\n");
2010 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2011 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2012 << ", Bits: " << CasesBits[i].Bits
2013 << ", BB: " << CasesBits[i].BB << '\n');
2015 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2016 CurMF->insert(BBI, CaseBB);
2017 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2021 // Put SV in a virtual register to make it available from the new blocks.
2022 ExportFromCurrentBlock(SV);
2025 BitTestBlock BTB(lowBound, cmpRange, SV,
2026 -1U, (CR.CaseBB == CurMBB),
2027 CR.CaseBB, Default, BTC);
2029 if (CR.CaseBB == CurMBB)
2030 visitBitTestHeader(BTB);
2032 BitTestCases.push_back(BTB);
2038 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2039 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2040 const SwitchInst& SI) {
2043 // Start with "simple" cases
2044 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2045 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2046 Cases.push_back(Case(SI.getSuccessorValue(i),
2047 SI.getSuccessorValue(i),
2050 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2052 // Merge case into clusters
2053 if (Cases.size() >= 2)
2054 // Must recompute end() each iteration because it may be
2055 // invalidated by erase if we hold on to it
2056 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2057 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2058 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2059 MachineBasicBlock* nextBB = J->BB;
2060 MachineBasicBlock* currentBB = I->BB;
2062 // If the two neighboring cases go to the same destination, merge them
2063 // into a single case.
2064 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2072 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2073 if (I->Low != I->High)
2074 // A range counts double, since it requires two compares.
2081 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2082 // Figure out which block is immediately after the current one.
2083 MachineBasicBlock *NextBlock = 0;
2084 MachineFunction::iterator BBI = CurMBB;
2086 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2088 // If there is only the default destination, branch to it if it is not the
2089 // next basic block. Otherwise, just fall through.
2090 if (SI.getNumOperands() == 2) {
2091 // Update machine-CFG edges.
2093 // If this is not a fall-through branch, emit the branch.
2094 CurMBB->addSuccessor(Default);
2095 if (Default != NextBlock)
2096 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2097 MVT::Other, getControlRoot(),
2098 DAG.getBasicBlock(Default)));
2102 // If there are any non-default case statements, create a vector of Cases
2103 // representing each one, and sort the vector so that we can efficiently
2104 // create a binary search tree from them.
2106 size_t numCmps = Clusterify(Cases, SI);
2107 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2108 << ". Total compares: " << numCmps << '\n');
2111 // Get the Value to be switched on and default basic blocks, which will be
2112 // inserted into CaseBlock records, representing basic blocks in the binary
2114 Value *SV = SI.getOperand(0);
2116 // Push the initial CaseRec onto the worklist
2117 CaseRecVector WorkList;
2118 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2120 while (!WorkList.empty()) {
2121 // Grab a record representing a case range to process off the worklist
2122 CaseRec CR = WorkList.back();
2123 WorkList.pop_back();
2125 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2128 // If the range has few cases (two or less) emit a series of specific
2130 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2133 // If the switch has more than 5 blocks, and at least 40% dense, and the
2134 // target supports indirect branches, then emit a jump table rather than
2135 // lowering the switch to a binary tree of conditional branches.
2136 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2139 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2140 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2141 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2146 void SelectionDAGLowering::visitSub(User &I) {
2147 // -0.0 - X --> fneg
2148 const Type *Ty = I.getType();
2149 if (isa<VectorType>(Ty)) {
2150 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2151 const VectorType *DestTy = cast<VectorType>(I.getType());
2152 const Type *ElTy = DestTy->getElementType();
2153 if (ElTy->isFloatingPoint()) {
2154 unsigned VL = DestTy->getNumElements();
2155 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2156 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2158 SDValue Op2 = getValue(I.getOperand(1));
2159 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2160 Op2.getValueType(), Op2));
2166 if (Ty->isFloatingPoint()) {
2167 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2168 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2169 SDValue Op2 = getValue(I.getOperand(1));
2170 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2171 Op2.getValueType(), Op2));
2176 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2179 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2180 SDValue Op1 = getValue(I.getOperand(0));
2181 SDValue Op2 = getValue(I.getOperand(1));
2183 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2184 Op1.getValueType(), Op1, Op2));
2187 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2188 SDValue Op1 = getValue(I.getOperand(0));
2189 SDValue Op2 = getValue(I.getOperand(1));
2190 if (!isa<VectorType>(I.getType()) &&
2191 Op2.getValueType() != TLI.getShiftAmountTy()) {
2192 // If the operand is smaller than the shift count type, promote it.
2193 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2194 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2195 TLI.getShiftAmountTy(), Op2);
2196 // If the operand is larger than the shift count type but the shift
2197 // count type has enough bits to represent any shift value, truncate
2198 // it now. This is a common case and it exposes the truncate to
2199 // optimization early.
2200 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2201 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2202 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2203 TLI.getShiftAmountTy(), Op2);
2204 // Otherwise we'll need to temporarily settle for some other
2205 // convenient type; type legalization will make adjustments as
2207 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2208 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2209 TLI.getPointerTy(), Op2);
2210 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2211 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2212 TLI.getPointerTy(), Op2);
2215 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2216 Op1.getValueType(), Op1, Op2));
2219 void SelectionDAGLowering::visitICmp(User &I) {
2220 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2221 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2222 predicate = IC->getPredicate();
2223 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2224 predicate = ICmpInst::Predicate(IC->getPredicate());
2225 SDValue Op1 = getValue(I.getOperand(0));
2226 SDValue Op2 = getValue(I.getOperand(1));
2227 ISD::CondCode Opcode = getICmpCondCode(predicate);
2228 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2231 void SelectionDAGLowering::visitFCmp(User &I) {
2232 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2233 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2234 predicate = FC->getPredicate();
2235 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2236 predicate = FCmpInst::Predicate(FC->getPredicate());
2237 SDValue Op1 = getValue(I.getOperand(0));
2238 SDValue Op2 = getValue(I.getOperand(1));
2239 ISD::CondCode Condition = getFCmpCondCode(predicate);
2240 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2243 void SelectionDAGLowering::visitVICmp(User &I) {
2244 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2245 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2246 predicate = IC->getPredicate();
2247 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2248 predicate = ICmpInst::Predicate(IC->getPredicate());
2249 SDValue Op1 = getValue(I.getOperand(0));
2250 SDValue Op2 = getValue(I.getOperand(1));
2251 ISD::CondCode Opcode = getICmpCondCode(predicate);
2252 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2256 void SelectionDAGLowering::visitVFCmp(User &I) {
2257 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2258 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2259 predicate = FC->getPredicate();
2260 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2261 predicate = FCmpInst::Predicate(FC->getPredicate());
2262 SDValue Op1 = getValue(I.getOperand(0));
2263 SDValue Op2 = getValue(I.getOperand(1));
2264 ISD::CondCode Condition = getFCmpCondCode(predicate);
2265 MVT DestVT = TLI.getValueType(I.getType());
2267 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2270 void SelectionDAGLowering::visitSelect(User &I) {
2271 SmallVector<MVT, 4> ValueVTs;
2272 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2273 unsigned NumValues = ValueVTs.size();
2274 if (NumValues != 0) {
2275 SmallVector<SDValue, 4> Values(NumValues);
2276 SDValue Cond = getValue(I.getOperand(0));
2277 SDValue TrueVal = getValue(I.getOperand(1));
2278 SDValue FalseVal = getValue(I.getOperand(2));
2280 for (unsigned i = 0; i != NumValues; ++i)
2281 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2282 TrueVal.getValueType(), Cond,
2283 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2284 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2286 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2287 DAG.getVTList(&ValueVTs[0], NumValues),
2288 &Values[0], NumValues));
2293 void SelectionDAGLowering::visitTrunc(User &I) {
2294 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2295 SDValue N = getValue(I.getOperand(0));
2296 MVT DestVT = TLI.getValueType(I.getType());
2297 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2300 void SelectionDAGLowering::visitZExt(User &I) {
2301 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2302 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2303 SDValue N = getValue(I.getOperand(0));
2304 MVT DestVT = TLI.getValueType(I.getType());
2305 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2308 void SelectionDAGLowering::visitSExt(User &I) {
2309 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2310 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2311 SDValue N = getValue(I.getOperand(0));
2312 MVT DestVT = TLI.getValueType(I.getType());
2313 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2316 void SelectionDAGLowering::visitFPTrunc(User &I) {
2317 // FPTrunc is never a no-op cast, no need to check
2318 SDValue N = getValue(I.getOperand(0));
2319 MVT DestVT = TLI.getValueType(I.getType());
2320 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2321 DestVT, N, DAG.getIntPtrConstant(0)));
2324 void SelectionDAGLowering::visitFPExt(User &I){
2325 // FPTrunc is never a no-op cast, no need to check
2326 SDValue N = getValue(I.getOperand(0));
2327 MVT DestVT = TLI.getValueType(I.getType());
2328 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2331 void SelectionDAGLowering::visitFPToUI(User &I) {
2332 // FPToUI is never a no-op cast, no need to check
2333 SDValue N = getValue(I.getOperand(0));
2334 MVT DestVT = TLI.getValueType(I.getType());
2335 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2338 void SelectionDAGLowering::visitFPToSI(User &I) {
2339 // FPToSI is never a no-op cast, no need to check
2340 SDValue N = getValue(I.getOperand(0));
2341 MVT DestVT = TLI.getValueType(I.getType());
2342 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2345 void SelectionDAGLowering::visitUIToFP(User &I) {
2346 // UIToFP is never a no-op cast, no need to check
2347 SDValue N = getValue(I.getOperand(0));
2348 MVT DestVT = TLI.getValueType(I.getType());
2349 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2352 void SelectionDAGLowering::visitSIToFP(User &I){
2353 // SIToFP is never a no-op cast, no need to check
2354 SDValue N = getValue(I.getOperand(0));
2355 MVT DestVT = TLI.getValueType(I.getType());
2356 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2359 void SelectionDAGLowering::visitPtrToInt(User &I) {
2360 // What to do depends on the size of the integer and the size of the pointer.
2361 // We can either truncate, zero extend, or no-op, accordingly.
2362 SDValue N = getValue(I.getOperand(0));
2363 MVT SrcVT = N.getValueType();
2364 MVT DestVT = TLI.getValueType(I.getType());
2366 if (DestVT.bitsLT(SrcVT))
2367 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2369 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2370 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2371 setValue(&I, Result);
2374 void SelectionDAGLowering::visitIntToPtr(User &I) {
2375 // What to do depends on the size of the integer and the size of the pointer.
2376 // We can either truncate, zero extend, or no-op, accordingly.
2377 SDValue N = getValue(I.getOperand(0));
2378 MVT SrcVT = N.getValueType();
2379 MVT DestVT = TLI.getValueType(I.getType());
2380 if (DestVT.bitsLT(SrcVT))
2381 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2383 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2384 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2388 void SelectionDAGLowering::visitBitCast(User &I) {
2389 SDValue N = getValue(I.getOperand(0));
2390 MVT DestVT = TLI.getValueType(I.getType());
2392 // BitCast assures us that source and destination are the same size so this
2393 // is either a BIT_CONVERT or a no-op.
2394 if (DestVT != N.getValueType())
2395 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2396 DestVT, N)); // convert types
2398 setValue(&I, N); // noop cast.
2401 void SelectionDAGLowering::visitInsertElement(User &I) {
2402 SDValue InVec = getValue(I.getOperand(0));
2403 SDValue InVal = getValue(I.getOperand(1));
2404 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2406 getValue(I.getOperand(2)));
2408 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2409 TLI.getValueType(I.getType()),
2410 InVec, InVal, InIdx));
2413 void SelectionDAGLowering::visitExtractElement(User &I) {
2414 SDValue InVec = getValue(I.getOperand(0));
2415 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2417 getValue(I.getOperand(1)));
2418 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2419 TLI.getValueType(I.getType()), InVec, InIdx));
2423 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2424 // from SIndx and increasing to the element length (undefs are allowed).
2425 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2426 unsigned MaskNumElts = Mask.size();
2427 for (unsigned i = 0; i != MaskNumElts; ++i)
2428 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2433 void SelectionDAGLowering::visitShuffleVector(User &I) {
2434 SmallVector<int, 8> Mask;
2435 SDValue Src1 = getValue(I.getOperand(0));
2436 SDValue Src2 = getValue(I.getOperand(1));
2438 // Convert the ConstantVector mask operand into an array of ints, with -1
2439 // representing undef values.
2440 SmallVector<Constant*, 8> MaskElts;
2441 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2442 unsigned MaskNumElts = MaskElts.size();
2443 for (unsigned i = 0; i != MaskNumElts; ++i) {
2444 if (isa<UndefValue>(MaskElts[i]))
2447 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2450 MVT VT = TLI.getValueType(I.getType());
2451 MVT SrcVT = Src1.getValueType();
2452 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2454 if (SrcNumElts == MaskNumElts) {
2455 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2460 // Normalize the shuffle vector since mask and vector length don't match.
2461 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2462 // Mask is longer than the source vectors and is a multiple of the source
2463 // vectors. We can use concatenate vector to make the mask and vectors
2465 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2466 // The shuffle is concatenating two vectors together.
2467 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2472 // Pad both vectors with undefs to make them the same length as the mask.
2473 unsigned NumConcat = MaskNumElts / SrcNumElts;
2474 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2475 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2476 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2478 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2479 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2483 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2484 getCurDebugLoc(), VT,
2485 &MOps1[0], NumConcat);
2486 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2487 getCurDebugLoc(), VT,
2488 &MOps2[0], NumConcat);
2490 // Readjust mask for new input vector length.
2491 SmallVector<int, 8> MappedOps;
2492 for (unsigned i = 0; i != MaskNumElts; ++i) {
2494 if (Idx < (int)SrcNumElts)
2495 MappedOps.push_back(Idx);
2497 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2499 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2504 if (SrcNumElts > MaskNumElts) {
2505 // Analyze the access pattern of the vector to see if we can extract
2506 // two subvectors and do the shuffle. The analysis is done by calculating
2507 // the range of elements the mask access on both vectors.
2508 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2509 int MaxRange[2] = {-1, -1};
2511 for (unsigned i = 0; i != MaskNumElts; ++i) {
2517 if (Idx >= (int)SrcNumElts) {
2521 if (Idx > MaxRange[Input])
2522 MaxRange[Input] = Idx;
2523 if (Idx < MinRange[Input])
2524 MinRange[Input] = Idx;
2527 // Check if the access is smaller than the vector size and can we find
2528 // a reasonable extract index.
2529 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2530 int StartIdx[2]; // StartIdx to extract from
2531 for (int Input=0; Input < 2; ++Input) {
2532 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2533 RangeUse[Input] = 0; // Unused
2534 StartIdx[Input] = 0;
2535 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2536 // Fits within range but we should see if we can find a good
2537 // start index that is a multiple of the mask length.
2538 if (MaxRange[Input] < (int)MaskNumElts) {
2539 RangeUse[Input] = 1; // Extract from beginning of the vector
2540 StartIdx[Input] = 0;
2542 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2543 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2544 StartIdx[Input] + MaskNumElts < SrcNumElts)
2545 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2550 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2551 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2554 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2555 // Extract appropriate subvector and generate a vector shuffle
2556 for (int Input=0; Input < 2; ++Input) {
2557 SDValue& Src = Input == 0 ? Src1 : Src2;
2558 if (RangeUse[Input] == 0) {
2559 Src = DAG.getUNDEF(VT);
2561 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2562 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2565 // Calculate new mask.
2566 SmallVector<int, 8> MappedOps;
2567 for (unsigned i = 0; i != MaskNumElts; ++i) {
2570 MappedOps.push_back(Idx);
2571 else if (Idx < (int)SrcNumElts)
2572 MappedOps.push_back(Idx - StartIdx[0]);
2574 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2576 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2582 // We can't use either concat vectors or extract subvectors so fall back to
2583 // replacing the shuffle with extract and build vector.
2584 // to insert and build vector.
2585 MVT EltVT = VT.getVectorElementType();
2586 MVT PtrVT = TLI.getPointerTy();
2587 SmallVector<SDValue,8> Ops;
2588 for (unsigned i = 0; i != MaskNumElts; ++i) {
2590 Ops.push_back(DAG.getUNDEF(EltVT));
2593 if (Idx < (int)SrcNumElts)
2594 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2595 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2597 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2599 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2602 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2603 VT, &Ops[0], Ops.size()));
2606 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2607 const Value *Op0 = I.getOperand(0);
2608 const Value *Op1 = I.getOperand(1);
2609 const Type *AggTy = I.getType();
2610 const Type *ValTy = Op1->getType();
2611 bool IntoUndef = isa<UndefValue>(Op0);
2612 bool FromUndef = isa<UndefValue>(Op1);
2614 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2615 I.idx_begin(), I.idx_end());
2617 SmallVector<MVT, 4> AggValueVTs;
2618 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2619 SmallVector<MVT, 4> ValValueVTs;
2620 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2622 unsigned NumAggValues = AggValueVTs.size();
2623 unsigned NumValValues = ValValueVTs.size();
2624 SmallVector<SDValue, 4> Values(NumAggValues);
2626 SDValue Agg = getValue(Op0);
2627 SDValue Val = getValue(Op1);
2629 // Copy the beginning value(s) from the original aggregate.
2630 for (; i != LinearIndex; ++i)
2631 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2632 SDValue(Agg.getNode(), Agg.getResNo() + i);
2633 // Copy values from the inserted value(s).
2634 for (; i != LinearIndex + NumValValues; ++i)
2635 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2636 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2637 // Copy remaining value(s) from the original aggregate.
2638 for (; i != NumAggValues; ++i)
2639 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2640 SDValue(Agg.getNode(), Agg.getResNo() + i);
2642 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2643 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2644 &Values[0], NumAggValues));
2647 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2648 const Value *Op0 = I.getOperand(0);
2649 const Type *AggTy = Op0->getType();
2650 const Type *ValTy = I.getType();
2651 bool OutOfUndef = isa<UndefValue>(Op0);
2653 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2654 I.idx_begin(), I.idx_end());
2656 SmallVector<MVT, 4> ValValueVTs;
2657 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2659 unsigned NumValValues = ValValueVTs.size();
2660 SmallVector<SDValue, 4> Values(NumValValues);
2662 SDValue Agg = getValue(Op0);
2663 // Copy out the selected value(s).
2664 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2665 Values[i - LinearIndex] =
2667 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2668 SDValue(Agg.getNode(), Agg.getResNo() + i);
2670 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2671 DAG.getVTList(&ValValueVTs[0], NumValValues),
2672 &Values[0], NumValValues));
2676 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2677 SDValue N = getValue(I.getOperand(0));
2678 const Type *Ty = I.getOperand(0)->getType();
2680 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2683 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2684 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2687 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2688 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2689 DAG.getIntPtrConstant(Offset));
2691 Ty = StTy->getElementType(Field);
2693 Ty = cast<SequentialType>(Ty)->getElementType();
2695 // If this is a constant subscript, handle it quickly.
2696 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2697 if (CI->getZExtValue() == 0) continue;
2699 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2701 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2703 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2705 DAG.getConstant(Offs, MVT::i64));
2707 OffsVal = DAG.getIntPtrConstant(Offs);
2708 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2713 // N = N + Idx * ElementSize;
2714 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2715 SDValue IdxN = getValue(Idx);
2717 // If the index is smaller or larger than intptr_t, truncate or extend
2719 if (IdxN.getValueType().bitsLT(N.getValueType()))
2720 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2721 N.getValueType(), IdxN);
2722 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2723 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2724 N.getValueType(), IdxN);
2726 // If this is a multiply by a power of two, turn it into a shl
2727 // immediately. This is a very common case.
2728 if (ElementSize != 1) {
2729 if (isPowerOf2_64(ElementSize)) {
2730 unsigned Amt = Log2_64(ElementSize);
2731 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2732 N.getValueType(), IdxN,
2733 DAG.getConstant(Amt, TLI.getPointerTy()));
2735 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2736 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2737 N.getValueType(), IdxN, Scale);
2741 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2742 N.getValueType(), N, IdxN);
2748 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2749 // If this is a fixed sized alloca in the entry block of the function,
2750 // allocate it statically on the stack.
2751 if (FuncInfo.StaticAllocaMap.count(&I))
2752 return; // getValue will auto-populate this.
2754 const Type *Ty = I.getAllocatedType();
2755 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2757 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2760 SDValue AllocSize = getValue(I.getArraySize());
2762 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2764 DAG.getConstant(TySize, AllocSize.getValueType()));
2768 MVT IntPtr = TLI.getPointerTy();
2769 if (IntPtr.bitsLT(AllocSize.getValueType()))
2770 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2772 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2773 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2776 // Handle alignment. If the requested alignment is less than or equal to
2777 // the stack alignment, ignore it. If the size is greater than or equal to
2778 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2779 unsigned StackAlign =
2780 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2781 if (Align <= StackAlign)
2784 // Round the size of the allocation up to the stack alignment size
2785 // by add SA-1 to the size.
2786 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2787 AllocSize.getValueType(), AllocSize,
2788 DAG.getIntPtrConstant(StackAlign-1));
2789 // Mask out the low bits for alignment purposes.
2790 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2791 AllocSize.getValueType(), AllocSize,
2792 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2794 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2795 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2796 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2799 DAG.setRoot(DSA.getValue(1));
2801 // Inform the Frame Information that we have just allocated a variable-sized
2803 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2806 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2807 const Value *SV = I.getOperand(0);
2808 SDValue Ptr = getValue(SV);
2810 const Type *Ty = I.getType();
2811 bool isVolatile = I.isVolatile();
2812 unsigned Alignment = I.getAlignment();
2814 SmallVector<MVT, 4> ValueVTs;
2815 SmallVector<uint64_t, 4> Offsets;
2816 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2817 unsigned NumValues = ValueVTs.size();
2822 bool ConstantMemory = false;
2824 // Serialize volatile loads with other side effects.
2826 else if (AA->pointsToConstantMemory(SV)) {
2827 // Do not serialize (non-volatile) loads of constant memory with anything.
2828 Root = DAG.getEntryNode();
2829 ConstantMemory = true;
2831 // Do not serialize non-volatile loads against each other.
2832 Root = DAG.getRoot();
2835 SmallVector<SDValue, 4> Values(NumValues);
2836 SmallVector<SDValue, 4> Chains(NumValues);
2837 MVT PtrVT = Ptr.getValueType();
2838 for (unsigned i = 0; i != NumValues; ++i) {
2839 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2840 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2842 DAG.getConstant(Offsets[i], PtrVT)),
2844 isVolatile, Alignment);
2846 Chains[i] = L.getValue(1);
2849 if (!ConstantMemory) {
2850 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2852 &Chains[0], NumValues);
2856 PendingLoads.push_back(Chain);
2859 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2860 DAG.getVTList(&ValueVTs[0], NumValues),
2861 &Values[0], NumValues));
2865 void SelectionDAGLowering::visitStore(StoreInst &I) {
2866 Value *SrcV = I.getOperand(0);
2867 Value *PtrV = I.getOperand(1);
2869 SmallVector<MVT, 4> ValueVTs;
2870 SmallVector<uint64_t, 4> Offsets;
2871 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2872 unsigned NumValues = ValueVTs.size();
2876 // Get the lowered operands. Note that we do this after
2877 // checking if NumResults is zero, because with zero results
2878 // the operands won't have values in the map.
2879 SDValue Src = getValue(SrcV);
2880 SDValue Ptr = getValue(PtrV);
2882 SDValue Root = getRoot();
2883 SmallVector<SDValue, 4> Chains(NumValues);
2884 MVT PtrVT = Ptr.getValueType();
2885 bool isVolatile = I.isVolatile();
2886 unsigned Alignment = I.getAlignment();
2887 for (unsigned i = 0; i != NumValues; ++i)
2888 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2889 SDValue(Src.getNode(), Src.getResNo() + i),
2890 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2892 DAG.getConstant(Offsets[i], PtrVT)),
2894 isVolatile, Alignment);
2896 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2897 MVT::Other, &Chains[0], NumValues));
2900 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2902 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2903 unsigned Intrinsic) {
2904 bool HasChain = !I.doesNotAccessMemory();
2905 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2907 // Build the operand list.
2908 SmallVector<SDValue, 8> Ops;
2909 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2911 // We don't need to serialize loads against other loads.
2912 Ops.push_back(DAG.getRoot());
2914 Ops.push_back(getRoot());
2918 // Info is set by getTgtMemInstrinsic
2919 TargetLowering::IntrinsicInfo Info;
2920 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2922 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2923 if (!IsTgtIntrinsic)
2924 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2926 // Add all operands of the call to the operand list.
2927 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2928 SDValue Op = getValue(I.getOperand(i));
2929 assert(TLI.isTypeLegal(Op.getValueType()) &&
2930 "Intrinsic uses a non-legal type?");
2934 std::vector<MVT> VTArray;
2935 if (I.getType() != Type::VoidTy) {
2936 MVT VT = TLI.getValueType(I.getType());
2937 if (VT.isVector()) {
2938 const VectorType *DestTy = cast<VectorType>(I.getType());
2939 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2941 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2942 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2945 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2946 VTArray.push_back(VT);
2949 VTArray.push_back(MVT::Other);
2951 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2955 if (IsTgtIntrinsic) {
2956 // This is target intrinsic that touches memory
2957 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2958 VTs, &Ops[0], Ops.size(),
2959 Info.memVT, Info.ptrVal, Info.offset,
2960 Info.align, Info.vol,
2961 Info.readMem, Info.writeMem);
2964 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2965 VTs, &Ops[0], Ops.size());
2966 else if (I.getType() != Type::VoidTy)
2967 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2968 VTs, &Ops[0], Ops.size());
2970 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2971 VTs, &Ops[0], Ops.size());
2974 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2976 PendingLoads.push_back(Chain);
2980 if (I.getType() != Type::VoidTy) {
2981 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2982 MVT VT = TLI.getValueType(PTy);
2983 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2985 setValue(&I, Result);
2989 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2990 static GlobalVariable *ExtractTypeInfo(Value *V) {
2991 V = V->stripPointerCasts();
2992 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2993 assert ((GV || isa<ConstantPointerNull>(V)) &&
2994 "TypeInfo must be a global variable or NULL");
3000 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3001 /// call, and add them to the specified machine basic block.
3002 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3003 MachineBasicBlock *MBB) {
3004 // Inform the MachineModuleInfo of the personality for this landing pad.
3005 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3006 assert(CE->getOpcode() == Instruction::BitCast &&
3007 isa<Function>(CE->getOperand(0)) &&
3008 "Personality should be a function");
3009 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3011 // Gather all the type infos for this landing pad and pass them along to
3012 // MachineModuleInfo.
3013 std::vector<GlobalVariable *> TyInfo;
3014 unsigned N = I.getNumOperands();
3016 for (unsigned i = N - 1; i > 2; --i) {
3017 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3018 unsigned FilterLength = CI->getZExtValue();
3019 unsigned FirstCatch = i + FilterLength + !FilterLength;
3020 assert (FirstCatch <= N && "Invalid filter length");
3022 if (FirstCatch < N) {
3023 TyInfo.reserve(N - FirstCatch);
3024 for (unsigned j = FirstCatch; j < N; ++j)
3025 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3026 MMI->addCatchTypeInfo(MBB, TyInfo);
3030 if (!FilterLength) {
3032 MMI->addCleanup(MBB);
3035 TyInfo.reserve(FilterLength - 1);
3036 for (unsigned j = i + 1; j < FirstCatch; ++j)
3037 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3038 MMI->addFilterTypeInfo(MBB, TyInfo);
3047 TyInfo.reserve(N - 3);
3048 for (unsigned j = 3; j < N; ++j)
3049 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3050 MMI->addCatchTypeInfo(MBB, TyInfo);
3056 /// GetSignificand - Get the significand and build it into a floating-point
3057 /// number with exponent of 1:
3059 /// Op = (Op & 0x007fffff) | 0x3f800000;
3061 /// where Op is the hexidecimal representation of floating point value.
3063 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3064 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3065 DAG.getConstant(0x007fffff, MVT::i32));
3066 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3067 DAG.getConstant(0x3f800000, MVT::i32));
3068 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3071 /// GetExponent - Get the exponent:
3073 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3075 /// where Op is the hexidecimal representation of floating point value.
3077 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3079 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3080 DAG.getConstant(0x7f800000, MVT::i32));
3081 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3082 DAG.getConstant(23, TLI.getPointerTy()));
3083 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3084 DAG.getConstant(127, MVT::i32));
3085 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3088 /// getF32Constant - Get 32-bit floating point constant.
3090 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3091 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3094 /// Inlined utility function to implement binary input atomic intrinsics for
3095 /// visitIntrinsicCall: I is a call instruction
3096 /// Op is the associated NodeType for I
3098 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3099 SDValue Root = getRoot();
3101 DAG.getAtomic(Op, getCurDebugLoc(),
3102 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3104 getValue(I.getOperand(1)),
3105 getValue(I.getOperand(2)),
3108 DAG.setRoot(L.getValue(1));
3112 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3114 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3115 SDValue Op1 = getValue(I.getOperand(1));
3116 SDValue Op2 = getValue(I.getOperand(2));
3118 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3119 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3121 setValue(&I, Result);
3125 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3126 /// limited-precision mode.
3128 SelectionDAGLowering::visitExp(CallInst &I) {
3130 DebugLoc dl = getCurDebugLoc();
3132 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3133 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3134 SDValue Op = getValue(I.getOperand(1));
3136 // Put the exponent in the right bit position for later addition to the
3139 // #define LOG2OFe 1.4426950f
3140 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3141 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3142 getF32Constant(DAG, 0x3fb8aa3b));
3143 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3145 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3146 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3147 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3149 // IntegerPartOfX <<= 23;
3150 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3151 DAG.getConstant(23, TLI.getPointerTy()));
3153 if (LimitFloatPrecision <= 6) {
3154 // For floating-point precision of 6:
3156 // TwoToFractionalPartOfX =
3158 // (0.735607626f + 0.252464424f * x) * x;
3160 // error 0.0144103317, which is 6 bits
3161 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3162 getF32Constant(DAG, 0x3e814304));
3163 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3164 getF32Constant(DAG, 0x3f3c50c8));
3165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3167 getF32Constant(DAG, 0x3f7f5e7e));
3168 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3170 // Add the exponent into the result in integer domain.
3171 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3172 TwoToFracPartOfX, IntegerPartOfX);
3174 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3175 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3176 // For floating-point precision of 12:
3178 // TwoToFractionalPartOfX =
3181 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3183 // 0.000107046256 error, which is 13 to 14 bits
3184 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3185 getF32Constant(DAG, 0x3da235e3));
3186 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3187 getF32Constant(DAG, 0x3e65b8f3));
3188 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3189 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3190 getF32Constant(DAG, 0x3f324b07));
3191 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3192 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3193 getF32Constant(DAG, 0x3f7ff8fd));
3194 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3196 // Add the exponent into the result in integer domain.
3197 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3198 TwoToFracPartOfX, IntegerPartOfX);
3200 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3201 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3202 // For floating-point precision of 18:
3204 // TwoToFractionalPartOfX =
3208 // (0.554906021e-1f +
3209 // (0.961591928e-2f +
3210 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3212 // error 2.47208000*10^(-7), which is better than 18 bits
3213 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3214 getF32Constant(DAG, 0x3924b03e));
3215 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3216 getF32Constant(DAG, 0x3ab24b87));
3217 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3218 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3219 getF32Constant(DAG, 0x3c1d8c17));
3220 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3221 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3222 getF32Constant(DAG, 0x3d634a1d));
3223 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3224 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3225 getF32Constant(DAG, 0x3e75fe14));
3226 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3227 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3228 getF32Constant(DAG, 0x3f317234));
3229 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3230 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3231 getF32Constant(DAG, 0x3f800000));
3232 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3235 // Add the exponent into the result in integer domain.
3236 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3237 TwoToFracPartOfX, IntegerPartOfX);
3239 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3242 // No special expansion.
3243 result = DAG.getNode(ISD::FEXP, dl,
3244 getValue(I.getOperand(1)).getValueType(),
3245 getValue(I.getOperand(1)));
3248 setValue(&I, result);
3251 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3252 /// limited-precision mode.
3254 SelectionDAGLowering::visitLog(CallInst &I) {
3256 DebugLoc dl = getCurDebugLoc();
3258 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3259 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3260 SDValue Op = getValue(I.getOperand(1));
3261 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3263 // Scale the exponent by log(2) [0.69314718f].
3264 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3265 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3266 getF32Constant(DAG, 0x3f317218));
3268 // Get the significand and build it into a floating-point number with
3270 SDValue X = GetSignificand(DAG, Op1, dl);
3272 if (LimitFloatPrecision <= 6) {
3273 // For floating-point precision of 6:
3277 // (1.4034025f - 0.23903021f * x) * x;
3279 // error 0.0034276066, which is better than 8 bits
3280 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3281 getF32Constant(DAG, 0xbe74c456));
3282 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3283 getF32Constant(DAG, 0x3fb3a2b1));
3284 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3285 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3286 getF32Constant(DAG, 0x3f949a29));
3288 result = DAG.getNode(ISD::FADD, dl,
3289 MVT::f32, LogOfExponent, LogOfMantissa);
3290 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3291 // For floating-point precision of 12:
3297 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3299 // error 0.000061011436, which is 14 bits
3300 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3301 getF32Constant(DAG, 0xbd67b6d6));
3302 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3303 getF32Constant(DAG, 0x3ee4f4b8));
3304 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3305 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3306 getF32Constant(DAG, 0x3fbc278b));
3307 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3308 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3309 getF32Constant(DAG, 0x40348e95));
3310 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3311 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3312 getF32Constant(DAG, 0x3fdef31a));
3314 result = DAG.getNode(ISD::FADD, dl,
3315 MVT::f32, LogOfExponent, LogOfMantissa);
3316 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3317 // For floating-point precision of 18:
3325 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3327 // error 0.0000023660568, which is better than 18 bits
3328 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3329 getF32Constant(DAG, 0xbc91e5ac));
3330 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3331 getF32Constant(DAG, 0x3e4350aa));
3332 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3333 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3334 getF32Constant(DAG, 0x3f60d3e3));
3335 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3336 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3337 getF32Constant(DAG, 0x4011cdf0));
3338 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3339 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3340 getF32Constant(DAG, 0x406cfd1c));
3341 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3342 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3343 getF32Constant(DAG, 0x408797cb));
3344 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3345 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3346 getF32Constant(DAG, 0x4006dcab));
3348 result = DAG.getNode(ISD::FADD, dl,
3349 MVT::f32, LogOfExponent, LogOfMantissa);
3352 // No special expansion.
3353 result = DAG.getNode(ISD::FLOG, dl,
3354 getValue(I.getOperand(1)).getValueType(),
3355 getValue(I.getOperand(1)));
3358 setValue(&I, result);
3361 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3362 /// limited-precision mode.
3364 SelectionDAGLowering::visitLog2(CallInst &I) {
3366 DebugLoc dl = getCurDebugLoc();
3368 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3369 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3370 SDValue Op = getValue(I.getOperand(1));
3371 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3373 // Get the exponent.
3374 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3376 // Get the significand and build it into a floating-point number with
3378 SDValue X = GetSignificand(DAG, Op1, dl);
3380 // Different possible minimax approximations of significand in
3381 // floating-point for various degrees of accuracy over [1,2].
3382 if (LimitFloatPrecision <= 6) {
3383 // For floating-point precision of 6:
3385 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3387 // error 0.0049451742, which is more than 7 bits
3388 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3389 getF32Constant(DAG, 0xbeb08fe0));
3390 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3391 getF32Constant(DAG, 0x40019463));
3392 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3393 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3394 getF32Constant(DAG, 0x3fd6633d));
3396 result = DAG.getNode(ISD::FADD, dl,
3397 MVT::f32, LogOfExponent, Log2ofMantissa);
3398 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3399 // For floating-point precision of 12:
3405 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3407 // error 0.0000876136000, which is better than 13 bits
3408 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3409 getF32Constant(DAG, 0xbda7262e));
3410 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3411 getF32Constant(DAG, 0x3f25280b));
3412 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3413 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3414 getF32Constant(DAG, 0x4007b923));
3415 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3416 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3417 getF32Constant(DAG, 0x40823e2f));
3418 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3419 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3420 getF32Constant(DAG, 0x4020d29c));
3422 result = DAG.getNode(ISD::FADD, dl,
3423 MVT::f32, LogOfExponent, Log2ofMantissa);
3424 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3425 // For floating-point precision of 18:
3434 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3436 // error 0.0000018516, which is better than 18 bits
3437 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3438 getF32Constant(DAG, 0xbcd2769e));
3439 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3440 getF32Constant(DAG, 0x3e8ce0b9));
3441 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3442 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3443 getF32Constant(DAG, 0x3fa22ae7));
3444 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3445 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3446 getF32Constant(DAG, 0x40525723));
3447 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3448 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3449 getF32Constant(DAG, 0x40aaf200));
3450 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3451 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3452 getF32Constant(DAG, 0x40c39dad));
3453 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3454 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3455 getF32Constant(DAG, 0x4042902c));
3457 result = DAG.getNode(ISD::FADD, dl,
3458 MVT::f32, LogOfExponent, Log2ofMantissa);
3461 // No special expansion.
3462 result = DAG.getNode(ISD::FLOG2, dl,
3463 getValue(I.getOperand(1)).getValueType(),
3464 getValue(I.getOperand(1)));
3467 setValue(&I, result);
3470 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3471 /// limited-precision mode.
3473 SelectionDAGLowering::visitLog10(CallInst &I) {
3475 DebugLoc dl = getCurDebugLoc();
3477 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3478 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3479 SDValue Op = getValue(I.getOperand(1));
3480 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3482 // Scale the exponent by log10(2) [0.30102999f].
3483 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3484 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3485 getF32Constant(DAG, 0x3e9a209a));
3487 // Get the significand and build it into a floating-point number with
3489 SDValue X = GetSignificand(DAG, Op1, dl);
3491 if (LimitFloatPrecision <= 6) {
3492 // For floating-point precision of 6:
3494 // Log10ofMantissa =
3496 // (0.60948995f - 0.10380950f * x) * x;
3498 // error 0.0014886165, which is 6 bits
3499 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3500 getF32Constant(DAG, 0xbdd49a13));
3501 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3502 getF32Constant(DAG, 0x3f1c0789));
3503 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3504 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3505 getF32Constant(DAG, 0x3f011300));
3507 result = DAG.getNode(ISD::FADD, dl,
3508 MVT::f32, LogOfExponent, Log10ofMantissa);
3509 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3510 // For floating-point precision of 12:
3512 // Log10ofMantissa =
3515 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3517 // error 0.00019228036, which is better than 12 bits
3518 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3519 getF32Constant(DAG, 0x3d431f31));
3520 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3521 getF32Constant(DAG, 0x3ea21fb2));
3522 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3523 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3524 getF32Constant(DAG, 0x3f6ae232));
3525 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3526 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3527 getF32Constant(DAG, 0x3f25f7c3));
3529 result = DAG.getNode(ISD::FADD, dl,
3530 MVT::f32, LogOfExponent, Log10ofMantissa);
3531 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3532 // For floating-point precision of 18:
3534 // Log10ofMantissa =
3539 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3541 // error 0.0000037995730, which is better than 18 bits
3542 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3543 getF32Constant(DAG, 0x3c5d51ce));
3544 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3545 getF32Constant(DAG, 0x3e00685a));
3546 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3547 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3548 getF32Constant(DAG, 0x3efb6798));
3549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3550 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3551 getF32Constant(DAG, 0x3f88d192));
3552 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3553 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3554 getF32Constant(DAG, 0x3fc4316c));
3555 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3556 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3557 getF32Constant(DAG, 0x3f57ce70));
3559 result = DAG.getNode(ISD::FADD, dl,
3560 MVT::f32, LogOfExponent, Log10ofMantissa);
3563 // No special expansion.
3564 result = DAG.getNode(ISD::FLOG10, dl,
3565 getValue(I.getOperand(1)).getValueType(),
3566 getValue(I.getOperand(1)));
3569 setValue(&I, result);
3572 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3573 /// limited-precision mode.
3575 SelectionDAGLowering::visitExp2(CallInst &I) {
3577 DebugLoc dl = getCurDebugLoc();
3579 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3580 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3581 SDValue Op = getValue(I.getOperand(1));
3583 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3585 // FractionalPartOfX = x - (float)IntegerPartOfX;
3586 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3587 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3589 // IntegerPartOfX <<= 23;
3590 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3591 DAG.getConstant(23, TLI.getPointerTy()));
3593 if (LimitFloatPrecision <= 6) {
3594 // For floating-point precision of 6:
3596 // TwoToFractionalPartOfX =
3598 // (0.735607626f + 0.252464424f * x) * x;
3600 // error 0.0144103317, which is 6 bits
3601 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3602 getF32Constant(DAG, 0x3e814304));
3603 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3604 getF32Constant(DAG, 0x3f3c50c8));
3605 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3606 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3607 getF32Constant(DAG, 0x3f7f5e7e));
3608 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3609 SDValue TwoToFractionalPartOfX =
3610 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3612 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3613 MVT::f32, TwoToFractionalPartOfX);
3614 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3615 // For floating-point precision of 12:
3617 // TwoToFractionalPartOfX =
3620 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3622 // error 0.000107046256, which is 13 to 14 bits
3623 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3624 getF32Constant(DAG, 0x3da235e3));
3625 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3626 getF32Constant(DAG, 0x3e65b8f3));
3627 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3628 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3629 getF32Constant(DAG, 0x3f324b07));
3630 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3631 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3632 getF32Constant(DAG, 0x3f7ff8fd));
3633 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3634 SDValue TwoToFractionalPartOfX =
3635 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3637 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3638 MVT::f32, TwoToFractionalPartOfX);
3639 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3640 // For floating-point precision of 18:
3642 // TwoToFractionalPartOfX =
3646 // (0.554906021e-1f +
3647 // (0.961591928e-2f +
3648 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3649 // error 2.47208000*10^(-7), which is better than 18 bits
3650 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3651 getF32Constant(DAG, 0x3924b03e));
3652 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3653 getF32Constant(DAG, 0x3ab24b87));
3654 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3655 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3656 getF32Constant(DAG, 0x3c1d8c17));
3657 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3658 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3659 getF32Constant(DAG, 0x3d634a1d));
3660 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3661 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3662 getF32Constant(DAG, 0x3e75fe14));
3663 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3664 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3665 getF32Constant(DAG, 0x3f317234));
3666 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3667 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3668 getF32Constant(DAG, 0x3f800000));
3669 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3670 SDValue TwoToFractionalPartOfX =
3671 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3673 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3674 MVT::f32, TwoToFractionalPartOfX);
3677 // No special expansion.
3678 result = DAG.getNode(ISD::FEXP2, dl,
3679 getValue(I.getOperand(1)).getValueType(),
3680 getValue(I.getOperand(1)));
3683 setValue(&I, result);
3686 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3687 /// limited-precision mode with x == 10.0f.
3689 SelectionDAGLowering::visitPow(CallInst &I) {
3691 Value *Val = I.getOperand(1);
3692 DebugLoc dl = getCurDebugLoc();
3693 bool IsExp10 = false;
3695 if (getValue(Val).getValueType() == MVT::f32 &&
3696 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3697 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3698 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3699 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3701 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3706 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3707 SDValue Op = getValue(I.getOperand(2));
3709 // Put the exponent in the right bit position for later addition to the
3712 // #define LOG2OF10 3.3219281f
3713 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3714 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3715 getF32Constant(DAG, 0x40549a78));
3716 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3718 // FractionalPartOfX = x - (float)IntegerPartOfX;
3719 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3720 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3722 // IntegerPartOfX <<= 23;
3723 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3724 DAG.getConstant(23, TLI.getPointerTy()));
3726 if (LimitFloatPrecision <= 6) {
3727 // For floating-point precision of 6:
3729 // twoToFractionalPartOfX =
3731 // (0.735607626f + 0.252464424f * x) * x;
3733 // error 0.0144103317, which is 6 bits
3734 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3735 getF32Constant(DAG, 0x3e814304));
3736 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3737 getF32Constant(DAG, 0x3f3c50c8));
3738 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3739 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3740 getF32Constant(DAG, 0x3f7f5e7e));
3741 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3742 SDValue TwoToFractionalPartOfX =
3743 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3745 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3746 MVT::f32, TwoToFractionalPartOfX);
3747 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3748 // For floating-point precision of 12:
3750 // TwoToFractionalPartOfX =
3753 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3755 // error 0.000107046256, which is 13 to 14 bits
3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3757 getF32Constant(DAG, 0x3da235e3));
3758 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3e65b8f3));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x3f324b07));
3763 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3764 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3765 getF32Constant(DAG, 0x3f7ff8fd));
3766 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3767 SDValue TwoToFractionalPartOfX =
3768 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3770 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3771 MVT::f32, TwoToFractionalPartOfX);
3772 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3773 // For floating-point precision of 18:
3775 // TwoToFractionalPartOfX =
3779 // (0.554906021e-1f +
3780 // (0.961591928e-2f +
3781 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3782 // error 2.47208000*10^(-7), which is better than 18 bits
3783 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3784 getF32Constant(DAG, 0x3924b03e));
3785 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3786 getF32Constant(DAG, 0x3ab24b87));
3787 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3788 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3789 getF32Constant(DAG, 0x3c1d8c17));
3790 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3791 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3792 getF32Constant(DAG, 0x3d634a1d));
3793 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3794 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3795 getF32Constant(DAG, 0x3e75fe14));
3796 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3797 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3798 getF32Constant(DAG, 0x3f317234));
3799 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3800 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3801 getF32Constant(DAG, 0x3f800000));
3802 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3803 SDValue TwoToFractionalPartOfX =
3804 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3806 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3807 MVT::f32, TwoToFractionalPartOfX);
3810 // No special expansion.
3811 result = DAG.getNode(ISD::FPOW, dl,
3812 getValue(I.getOperand(1)).getValueType(),
3813 getValue(I.getOperand(1)),
3814 getValue(I.getOperand(2)));
3817 setValue(&I, result);
3820 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3821 /// we want to emit this as a call to a named external function, return the name
3822 /// otherwise lower it and return null.
3824 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3825 DebugLoc dl = getCurDebugLoc();
3826 switch (Intrinsic) {
3828 // By default, turn this into a target intrinsic node.
3829 visitTargetIntrinsic(I, Intrinsic);
3831 case Intrinsic::vastart: visitVAStart(I); return 0;
3832 case Intrinsic::vaend: visitVAEnd(I); return 0;
3833 case Intrinsic::vacopy: visitVACopy(I); return 0;
3834 case Intrinsic::returnaddress:
3835 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3836 getValue(I.getOperand(1))));
3838 case Intrinsic::frameaddress:
3839 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3840 getValue(I.getOperand(1))));
3842 case Intrinsic::setjmp:
3843 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3845 case Intrinsic::longjmp:
3846 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3848 case Intrinsic::memcpy: {
3849 SDValue Op1 = getValue(I.getOperand(1));
3850 SDValue Op2 = getValue(I.getOperand(2));
3851 SDValue Op3 = getValue(I.getOperand(3));
3852 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3853 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3854 I.getOperand(1), 0, I.getOperand(2), 0));
3857 case Intrinsic::memset: {
3858 SDValue Op1 = getValue(I.getOperand(1));
3859 SDValue Op2 = getValue(I.getOperand(2));
3860 SDValue Op3 = getValue(I.getOperand(3));
3861 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3862 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3863 I.getOperand(1), 0));
3866 case Intrinsic::memmove: {
3867 SDValue Op1 = getValue(I.getOperand(1));
3868 SDValue Op2 = getValue(I.getOperand(2));
3869 SDValue Op3 = getValue(I.getOperand(3));
3870 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3872 // If the source and destination are known to not be aliases, we can
3873 // lower memmove as memcpy.
3874 uint64_t Size = -1ULL;
3875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3876 Size = C->getZExtValue();
3877 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3878 AliasAnalysis::NoAlias) {
3879 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3880 I.getOperand(1), 0, I.getOperand(2), 0));
3884 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3885 I.getOperand(1), 0, I.getOperand(2), 0));
3888 case Intrinsic::dbg_stoppoint: {
3889 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3890 if (DIDescriptor::ValidDebugInfo(SPI.getContext(), OptLevel)) {
3891 MachineFunction &MF = DAG.getMachineFunction();
3892 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3893 DebugLoc Loc = DebugLoc::get(MF.getOrCreateDebugLocID(CU.getGV(),
3894 SPI.getLine(), SPI.getColumn()));
3895 setCurDebugLoc(Loc);
3897 if (OptLevel == CodeGenOpt::None)
3898 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3905 case Intrinsic::dbg_region_start: {
3906 DwarfWriter *DW = DAG.getDwarfWriter();
3907 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3909 if (DIDescriptor::ValidDebugInfo(RSI.getContext(), OptLevel) &&
3910 DW && DW->ShouldEmitDwarfDebug()) {
3912 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3913 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3914 getRoot(), LabelID));
3919 case Intrinsic::dbg_region_end: {
3920 DwarfWriter *DW = DAG.getDwarfWriter();
3921 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3923 if (DIDescriptor::ValidDebugInfo(REI.getContext(), OptLevel) &&
3924 DW && DW->ShouldEmitDwarfDebug()) {
3925 MachineFunction &MF = DAG.getMachineFunction();
3926 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3928 Subprogram.getLinkageName(SPName);
3930 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
3931 // This is end of inlined function. Debugging information for
3932 // inlined function is not handled yet (only supported by FastISel).
3933 if (OptLevel == CodeGenOpt::None) {
3934 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3936 // Returned ID is 0 if this is unbalanced "end of inlined
3937 // scope". This could happen if optimizer eats dbg intrinsics
3938 // or "beginning of inlined scope" is not recoginized due to
3939 // missing location info. In such cases, do ignore this region.end.
3940 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3947 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()),
3949 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3950 getRoot(), LabelID));
3955 case Intrinsic::dbg_func_start: {
3956 DwarfWriter *DW = DAG.getDwarfWriter();
3957 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3958 Value *SP = FSI.getSubprogram();
3959 if (!DIDescriptor::ValidDebugInfo(SP, OptLevel))
3962 MachineFunction &MF = DAG.getMachineFunction();
3963 if (OptLevel == CodeGenOpt::None) {
3964 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
3965 // (most?) gdb expects.
3966 DebugLoc PrevLoc = CurDebugLoc;
3967 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3968 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3970 if (!Subprogram.describes(MF.getFunction())) {
3971 // This is a beginning of an inlined function.
3973 // If llvm.dbg.func.start is seen in a new block before any
3974 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3975 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3976 if (PrevLoc.isUnknown())
3979 // Record the source line.
3980 unsigned Line = Subprogram.getLineNumber();
3981 setCurDebugLoc(DebugLoc::get(
3982 MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0)));
3984 if (DW && DW->ShouldEmitDwarfDebug()) {
3985 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3986 unsigned LabelID = DW->RecordInlinedFnStart(Subprogram,
3987 DICompileUnit(PrevLocTpl.CompileUnit),
3990 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3991 getRoot(), LabelID));
3994 // Record the source line.
3995 unsigned Line = Subprogram.getLineNumber();
3996 MF.setDefaultDebugLoc(DebugLoc::get(
3997 MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0)));
3998 if (DW && DW->ShouldEmitDwarfDebug()) {
3999 // llvm.dbg.func_start also defines beginning of function scope.
4000 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
4004 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4007 Subprogram.getLinkageName(SPName);
4009 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
4010 // This is beginning of inlined function. Debugging information for
4011 // inlined function is not handled yet (only supported by FastISel).
4015 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
4016 // what (most?) gdb expects.
4017 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4019 // Record the source line but does not create a label for the normal
4020 // function start. It will be emitted at asm emission time. However,
4021 // create a label if this is a beginning of inlined function.
4022 unsigned Line = Subprogram.getLineNumber();
4023 setCurDebugLoc(DebugLoc::get(
4024 MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0)));
4025 // FIXME - Start new region because llvm.dbg.func_start also defines
4026 // beginning of function scope.
4031 case Intrinsic::dbg_declare: {
4032 if (OptLevel == CodeGenOpt::None) {
4033 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4034 Value *Variable = DI.getVariable();
4035 if (DIDescriptor::ValidDebugInfo(Variable, OptLevel))
4036 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
4037 getValue(DI.getAddress()), getValue(Variable)));
4039 // FIXME: Do something sensible here when we support debug declare.
4043 case Intrinsic::eh_exception: {
4044 if (!CurMBB->isLandingPad()) {
4045 // FIXME: Mark exception register as live in. Hack for PR1508.
4046 unsigned Reg = TLI.getExceptionAddressRegister();
4047 if (Reg) CurMBB->addLiveIn(Reg);
4049 // Insert the EXCEPTIONADDR instruction.
4050 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4052 Ops[0] = DAG.getRoot();
4053 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4055 DAG.setRoot(Op.getValue(1));
4059 case Intrinsic::eh_selector_i32:
4060 case Intrinsic::eh_selector_i64: {
4061 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4062 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4063 MVT::i32 : MVT::i64);
4066 if (CurMBB->isLandingPad())
4067 AddCatchInfo(I, MMI, CurMBB);
4070 FuncInfo.CatchInfoLost.insert(&I);
4072 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4073 unsigned Reg = TLI.getExceptionSelectorRegister();
4074 if (Reg) CurMBB->addLiveIn(Reg);
4077 // Insert the EHSELECTION instruction.
4078 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4080 Ops[0] = getValue(I.getOperand(1));
4082 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4084 DAG.setRoot(Op.getValue(1));
4086 setValue(&I, DAG.getConstant(0, VT));
4092 case Intrinsic::eh_typeid_for_i32:
4093 case Intrinsic::eh_typeid_for_i64: {
4094 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4095 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4096 MVT::i32 : MVT::i64);
4099 // Find the type id for the given typeinfo.
4100 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4102 unsigned TypeID = MMI->getTypeIDFor(GV);
4103 setValue(&I, DAG.getConstant(TypeID, VT));
4105 // Return something different to eh_selector.
4106 setValue(&I, DAG.getConstant(1, VT));
4112 case Intrinsic::eh_return_i32:
4113 case Intrinsic::eh_return_i64:
4114 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4115 MMI->setCallsEHReturn(true);
4116 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4119 getValue(I.getOperand(1)),
4120 getValue(I.getOperand(2))));
4122 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4126 case Intrinsic::eh_unwind_init:
4127 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4128 MMI->setCallsUnwindInit(true);
4133 case Intrinsic::eh_dwarf_cfa: {
4134 MVT VT = getValue(I.getOperand(1)).getValueType();
4136 if (VT.bitsGT(TLI.getPointerTy()))
4137 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4138 TLI.getPointerTy(), getValue(I.getOperand(1)));
4140 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4141 TLI.getPointerTy(), getValue(I.getOperand(1)));
4143 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4145 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4146 TLI.getPointerTy()),
4148 setValue(&I, DAG.getNode(ISD::ADD, dl,
4150 DAG.getNode(ISD::FRAMEADDR, dl,
4153 TLI.getPointerTy())),
4158 case Intrinsic::convertff:
4159 case Intrinsic::convertfsi:
4160 case Intrinsic::convertfui:
4161 case Intrinsic::convertsif:
4162 case Intrinsic::convertuif:
4163 case Intrinsic::convertss:
4164 case Intrinsic::convertsu:
4165 case Intrinsic::convertus:
4166 case Intrinsic::convertuu: {
4167 ISD::CvtCode Code = ISD::CVT_INVALID;
4168 switch (Intrinsic) {
4169 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4170 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4171 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4172 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4173 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4174 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4175 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4176 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4177 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4179 MVT DestVT = TLI.getValueType(I.getType());
4180 Value* Op1 = I.getOperand(1);
4181 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4182 DAG.getValueType(DestVT),
4183 DAG.getValueType(getValue(Op1).getValueType()),
4184 getValue(I.getOperand(2)),
4185 getValue(I.getOperand(3)),
4190 case Intrinsic::sqrt:
4191 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4192 getValue(I.getOperand(1)).getValueType(),
4193 getValue(I.getOperand(1))));
4195 case Intrinsic::powi:
4196 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4197 getValue(I.getOperand(1)).getValueType(),
4198 getValue(I.getOperand(1)),
4199 getValue(I.getOperand(2))));
4201 case Intrinsic::sin:
4202 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4203 getValue(I.getOperand(1)).getValueType(),
4204 getValue(I.getOperand(1))));
4206 case Intrinsic::cos:
4207 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4208 getValue(I.getOperand(1)).getValueType(),
4209 getValue(I.getOperand(1))));
4211 case Intrinsic::log:
4214 case Intrinsic::log2:
4217 case Intrinsic::log10:
4220 case Intrinsic::exp:
4223 case Intrinsic::exp2:
4226 case Intrinsic::pow:
4229 case Intrinsic::pcmarker: {
4230 SDValue Tmp = getValue(I.getOperand(1));
4231 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4234 case Intrinsic::readcyclecounter: {
4235 SDValue Op = getRoot();
4236 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4237 DAG.getVTList(MVT::i64, MVT::Other),
4240 DAG.setRoot(Tmp.getValue(1));
4243 case Intrinsic::part_select: {
4244 // Currently not implemented: just abort
4245 assert(0 && "part_select intrinsic not implemented");
4248 case Intrinsic::part_set: {
4249 // Currently not implemented: just abort
4250 assert(0 && "part_set intrinsic not implemented");
4253 case Intrinsic::bswap:
4254 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4255 getValue(I.getOperand(1)).getValueType(),
4256 getValue(I.getOperand(1))));
4258 case Intrinsic::cttz: {
4259 SDValue Arg = getValue(I.getOperand(1));
4260 MVT Ty = Arg.getValueType();
4261 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4262 setValue(&I, result);
4265 case Intrinsic::ctlz: {
4266 SDValue Arg = getValue(I.getOperand(1));
4267 MVT Ty = Arg.getValueType();
4268 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4269 setValue(&I, result);
4272 case Intrinsic::ctpop: {
4273 SDValue Arg = getValue(I.getOperand(1));
4274 MVT Ty = Arg.getValueType();
4275 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4276 setValue(&I, result);
4279 case Intrinsic::stacksave: {
4280 SDValue Op = getRoot();
4281 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4282 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4284 DAG.setRoot(Tmp.getValue(1));
4287 case Intrinsic::stackrestore: {
4288 SDValue Tmp = getValue(I.getOperand(1));
4289 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4292 case Intrinsic::stackprotector: {
4293 // Emit code into the DAG to store the stack guard onto the stack.
4294 MachineFunction &MF = DAG.getMachineFunction();
4295 MachineFrameInfo *MFI = MF.getFrameInfo();
4296 MVT PtrTy = TLI.getPointerTy();
4298 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4299 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4301 int FI = FuncInfo.StaticAllocaMap[Slot];
4302 MFI->setStackProtectorIndex(FI);
4304 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4306 // Store the stack protector onto the stack.
4307 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4308 PseudoSourceValue::getFixedStack(FI),
4310 setValue(&I, Result);
4311 DAG.setRoot(Result);
4314 case Intrinsic::var_annotation:
4315 // Discard annotate attributes
4318 case Intrinsic::init_trampoline: {
4319 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4323 Ops[1] = getValue(I.getOperand(1));
4324 Ops[2] = getValue(I.getOperand(2));
4325 Ops[3] = getValue(I.getOperand(3));
4326 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4327 Ops[5] = DAG.getSrcValue(F);
4329 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4330 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4334 DAG.setRoot(Tmp.getValue(1));
4338 case Intrinsic::gcroot:
4340 Value *Alloca = I.getOperand(1);
4341 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4343 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4344 GFI->addStackRoot(FI->getIndex(), TypeMap);
4348 case Intrinsic::gcread:
4349 case Intrinsic::gcwrite:
4350 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4353 case Intrinsic::flt_rounds: {
4354 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4358 case Intrinsic::trap: {
4359 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4363 case Intrinsic::uadd_with_overflow:
4364 return implVisitAluOverflow(I, ISD::UADDO);
4365 case Intrinsic::sadd_with_overflow:
4366 return implVisitAluOverflow(I, ISD::SADDO);
4367 case Intrinsic::usub_with_overflow:
4368 return implVisitAluOverflow(I, ISD::USUBO);
4369 case Intrinsic::ssub_with_overflow:
4370 return implVisitAluOverflow(I, ISD::SSUBO);
4371 case Intrinsic::umul_with_overflow:
4372 return implVisitAluOverflow(I, ISD::UMULO);
4373 case Intrinsic::smul_with_overflow:
4374 return implVisitAluOverflow(I, ISD::SMULO);
4376 case Intrinsic::prefetch: {
4379 Ops[1] = getValue(I.getOperand(1));
4380 Ops[2] = getValue(I.getOperand(2));
4381 Ops[3] = getValue(I.getOperand(3));
4382 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4386 case Intrinsic::memory_barrier: {
4389 for (int x = 1; x < 6; ++x)
4390 Ops[x] = getValue(I.getOperand(x));
4392 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4395 case Intrinsic::atomic_cmp_swap: {
4396 SDValue Root = getRoot();
4398 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4399 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4401 getValue(I.getOperand(1)),
4402 getValue(I.getOperand(2)),
4403 getValue(I.getOperand(3)),
4406 DAG.setRoot(L.getValue(1));
4409 case Intrinsic::atomic_load_add:
4410 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4411 case Intrinsic::atomic_load_sub:
4412 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4413 case Intrinsic::atomic_load_or:
4414 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4415 case Intrinsic::atomic_load_xor:
4416 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4417 case Intrinsic::atomic_load_and:
4418 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4419 case Intrinsic::atomic_load_nand:
4420 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4421 case Intrinsic::atomic_load_max:
4422 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4423 case Intrinsic::atomic_load_min:
4424 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4425 case Intrinsic::atomic_load_umin:
4426 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4427 case Intrinsic::atomic_load_umax:
4428 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4429 case Intrinsic::atomic_swap:
4430 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4435 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4437 MachineBasicBlock *LandingPad) {
4438 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4439 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4440 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4441 unsigned BeginLabel = 0, EndLabel = 0;
4443 TargetLowering::ArgListTy Args;
4444 TargetLowering::ArgListEntry Entry;
4445 Args.reserve(CS.arg_size());
4446 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4448 SDValue ArgNode = getValue(*i);
4449 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4451 unsigned attrInd = i - CS.arg_begin() + 1;
4452 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4453 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4454 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4455 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4456 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4457 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4458 Entry.Alignment = CS.getParamAlignment(attrInd);
4459 Args.push_back(Entry);
4462 if (LandingPad && MMI) {
4463 // Insert a label before the invoke call to mark the try range. This can be
4464 // used to detect deletion of the invoke via the MachineModuleInfo.
4465 BeginLabel = MMI->NextLabelID();
4466 // Both PendingLoads and PendingExports must be flushed here;
4467 // this call might not return.
4469 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4470 getControlRoot(), BeginLabel));
4473 std::pair<SDValue,SDValue> Result =
4474 TLI.LowerCallTo(getRoot(), CS.getType(),
4475 CS.paramHasAttr(0, Attribute::SExt),
4476 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4477 CS.paramHasAttr(0, Attribute::InReg),
4478 CS.getCallingConv(),
4479 IsTailCall && PerformTailCallOpt,
4480 Callee, Args, DAG, getCurDebugLoc());
4481 if (CS.getType() != Type::VoidTy)
4482 setValue(CS.getInstruction(), Result.first);
4483 DAG.setRoot(Result.second);
4485 if (LandingPad && MMI) {
4486 // Insert a label at the end of the invoke call to mark the try range. This
4487 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4488 EndLabel = MMI->NextLabelID();
4489 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4490 getRoot(), EndLabel));
4492 // Inform MachineModuleInfo of range.
4493 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4498 void SelectionDAGLowering::visitCall(CallInst &I) {
4499 const char *RenameFn = 0;
4500 if (Function *F = I.getCalledFunction()) {
4501 if (F->isDeclaration()) {
4502 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4504 if (unsigned IID = II->getIntrinsicID(F)) {
4505 RenameFn = visitIntrinsicCall(I, IID);
4510 if (unsigned IID = F->getIntrinsicID()) {
4511 RenameFn = visitIntrinsicCall(I, IID);
4517 // Check for well-known libc/libm calls. If the function is internal, it
4518 // can't be a library call.
4519 unsigned NameLen = F->getNameLen();
4520 if (!F->hasLocalLinkage() && NameLen) {
4521 const char *NameStr = F->getNameStart();
4522 if (NameStr[0] == 'c' &&
4523 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4524 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4525 if (I.getNumOperands() == 3 && // Basic sanity checks.
4526 I.getOperand(1)->getType()->isFloatingPoint() &&
4527 I.getType() == I.getOperand(1)->getType() &&
4528 I.getType() == I.getOperand(2)->getType()) {
4529 SDValue LHS = getValue(I.getOperand(1));
4530 SDValue RHS = getValue(I.getOperand(2));
4531 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4532 LHS.getValueType(), LHS, RHS));
4535 } else if (NameStr[0] == 'f' &&
4536 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4537 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4538 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4539 if (I.getNumOperands() == 2 && // Basic sanity checks.
4540 I.getOperand(1)->getType()->isFloatingPoint() &&
4541 I.getType() == I.getOperand(1)->getType()) {
4542 SDValue Tmp = getValue(I.getOperand(1));
4543 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4544 Tmp.getValueType(), Tmp));
4547 } else if (NameStr[0] == 's' &&
4548 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4549 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4550 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4551 if (I.getNumOperands() == 2 && // Basic sanity checks.
4552 I.getOperand(1)->getType()->isFloatingPoint() &&
4553 I.getType() == I.getOperand(1)->getType()) {
4554 SDValue Tmp = getValue(I.getOperand(1));
4555 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4556 Tmp.getValueType(), Tmp));
4559 } else if (NameStr[0] == 'c' &&
4560 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4561 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4562 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4563 if (I.getNumOperands() == 2 && // Basic sanity checks.
4564 I.getOperand(1)->getType()->isFloatingPoint() &&
4565 I.getType() == I.getOperand(1)->getType()) {
4566 SDValue Tmp = getValue(I.getOperand(1));
4567 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4568 Tmp.getValueType(), Tmp));
4573 } else if (isa<InlineAsm>(I.getOperand(0))) {
4580 Callee = getValue(I.getOperand(0));
4582 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4584 LowerCallTo(&I, Callee, I.isTailCall());
4588 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4589 /// this value and returns the result as a ValueVT value. This uses
4590 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4591 /// If the Flag pointer is NULL, no flag is used.
4592 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4594 SDValue *Flag) const {
4595 // Assemble the legal parts into the final values.
4596 SmallVector<SDValue, 4> Values(ValueVTs.size());
4597 SmallVector<SDValue, 8> Parts;
4598 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4599 // Copy the legal parts from the registers.
4600 MVT ValueVT = ValueVTs[Value];
4601 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4602 MVT RegisterVT = RegVTs[Value];
4604 Parts.resize(NumRegs);
4605 for (unsigned i = 0; i != NumRegs; ++i) {
4608 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4610 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4611 *Flag = P.getValue(2);
4613 Chain = P.getValue(1);
4615 // If the source register was virtual and if we know something about it,
4616 // add an assert node.
4617 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4618 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4619 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4620 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4621 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4622 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4624 unsigned RegSize = RegisterVT.getSizeInBits();
4625 unsigned NumSignBits = LOI.NumSignBits;
4626 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4628 // FIXME: We capture more information than the dag can represent. For
4629 // now, just use the tightest assertzext/assertsext possible.
4631 MVT FromVT(MVT::Other);
4632 if (NumSignBits == RegSize)
4633 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4634 else if (NumZeroBits >= RegSize-1)
4635 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4636 else if (NumSignBits > RegSize-8)
4637 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4638 else if (NumZeroBits >= RegSize-8)
4639 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4640 else if (NumSignBits > RegSize-16)
4641 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4642 else if (NumZeroBits >= RegSize-16)
4643 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4644 else if (NumSignBits > RegSize-32)
4645 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4646 else if (NumZeroBits >= RegSize-32)
4647 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4649 if (FromVT != MVT::Other) {
4650 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4651 RegisterVT, P, DAG.getValueType(FromVT));
4660 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4661 NumRegs, RegisterVT, ValueVT);
4666 return DAG.getNode(ISD::MERGE_VALUES, dl,
4667 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4668 &Values[0], ValueVTs.size());
4671 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4672 /// specified value into the registers specified by this object. This uses
4673 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4674 /// If the Flag pointer is NULL, no flag is used.
4675 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4676 SDValue &Chain, SDValue *Flag) const {
4677 // Get the list of the values's legal parts.
4678 unsigned NumRegs = Regs.size();
4679 SmallVector<SDValue, 8> Parts(NumRegs);
4680 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4681 MVT ValueVT = ValueVTs[Value];
4682 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4683 MVT RegisterVT = RegVTs[Value];
4685 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4686 &Parts[Part], NumParts, RegisterVT);
4690 // Copy the parts into the registers.
4691 SmallVector<SDValue, 8> Chains(NumRegs);
4692 for (unsigned i = 0; i != NumRegs; ++i) {
4695 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4697 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4698 *Flag = Part.getValue(1);
4700 Chains[i] = Part.getValue(0);
4703 if (NumRegs == 1 || Flag)
4704 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4705 // flagged to it. That is the CopyToReg nodes and the user are considered
4706 // a single scheduling unit. If we create a TokenFactor and return it as
4707 // chain, then the TokenFactor is both a predecessor (operand) of the
4708 // user as well as a successor (the TF operands are flagged to the user).
4709 // c1, f1 = CopyToReg
4710 // c2, f2 = CopyToReg
4711 // c3 = TokenFactor c1, c2
4714 Chain = Chains[NumRegs-1];
4716 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4719 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4720 /// operand list. This adds the code marker and includes the number of
4721 /// values added into it.
4722 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4723 bool HasMatching,unsigned MatchingIdx,
4725 std::vector<SDValue> &Ops) const {
4726 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4727 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4728 unsigned Flag = Code | (Regs.size() << 3);
4730 Flag |= 0x80000000 | (MatchingIdx << 16);
4731 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4732 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4733 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4734 MVT RegisterVT = RegVTs[Value];
4735 for (unsigned i = 0; i != NumRegs; ++i) {
4736 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4737 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4742 /// isAllocatableRegister - If the specified register is safe to allocate,
4743 /// i.e. it isn't a stack pointer or some other special register, return the
4744 /// register class for the register. Otherwise, return null.
4745 static const TargetRegisterClass *
4746 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4747 const TargetLowering &TLI,
4748 const TargetRegisterInfo *TRI) {
4749 MVT FoundVT = MVT::Other;
4750 const TargetRegisterClass *FoundRC = 0;
4751 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4752 E = TRI->regclass_end(); RCI != E; ++RCI) {
4753 MVT ThisVT = MVT::Other;
4755 const TargetRegisterClass *RC = *RCI;
4756 // If none of the the value types for this register class are valid, we
4757 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4758 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4760 if (TLI.isTypeLegal(*I)) {
4761 // If we have already found this register in a different register class,
4762 // choose the one with the largest VT specified. For example, on
4763 // PowerPC, we favor f64 register classes over f32.
4764 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4771 if (ThisVT == MVT::Other) continue;
4773 // NOTE: This isn't ideal. In particular, this might allocate the
4774 // frame pointer in functions that need it (due to them not being taken
4775 // out of allocation, because a variable sized allocation hasn't been seen
4776 // yet). This is a slight code pessimization, but should still work.
4777 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4778 E = RC->allocation_order_end(MF); I != E; ++I)
4780 // We found a matching register class. Keep looking at others in case
4781 // we find one with larger registers that this physreg is also in.
4792 /// AsmOperandInfo - This contains information for each constraint that we are
4794 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4795 public TargetLowering::AsmOperandInfo {
4797 /// CallOperand - If this is the result output operand or a clobber
4798 /// this is null, otherwise it is the incoming operand to the CallInst.
4799 /// This gets modified as the asm is processed.
4800 SDValue CallOperand;
4802 /// AssignedRegs - If this is a register or register class operand, this
4803 /// contains the set of register corresponding to the operand.
4804 RegsForValue AssignedRegs;
4806 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4807 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4810 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4811 /// busy in OutputRegs/InputRegs.
4812 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4813 std::set<unsigned> &OutputRegs,
4814 std::set<unsigned> &InputRegs,
4815 const TargetRegisterInfo &TRI) const {
4817 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4818 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4821 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4822 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4826 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4827 /// corresponds to. If there is no Value* for this operand, it returns
4829 MVT getCallOperandValMVT(const TargetLowering &TLI,
4830 const TargetData *TD) const {
4831 if (CallOperandVal == 0) return MVT::Other;
4833 if (isa<BasicBlock>(CallOperandVal))
4834 return TLI.getPointerTy();
4836 const llvm::Type *OpTy = CallOperandVal->getType();
4838 // If this is an indirect operand, the operand is a pointer to the
4841 OpTy = cast<PointerType>(OpTy)->getElementType();
4843 // If OpTy is not a single value, it may be a struct/union that we
4844 // can tile with integers.
4845 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4846 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4855 OpTy = IntegerType::get(BitSize);
4860 return TLI.getValueType(OpTy, true);
4864 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4866 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4867 const TargetRegisterInfo &TRI) {
4868 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4870 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4871 for (; *Aliases; ++Aliases)
4872 Regs.insert(*Aliases);
4875 } // end llvm namespace.
4878 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4879 /// specified operand. We prefer to assign virtual registers, to allow the
4880 /// register allocator handle the assignment process. However, if the asm uses
4881 /// features that we can't model on machineinstrs, we have SDISel do the
4882 /// allocation. This produces generally horrible, but correct, code.
4884 /// OpInfo describes the operand.
4885 /// Input and OutputRegs are the set of already allocated physical registers.
4887 void SelectionDAGLowering::
4888 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4889 std::set<unsigned> &OutputRegs,
4890 std::set<unsigned> &InputRegs) {
4891 // Compute whether this value requires an input register, an output register,
4893 bool isOutReg = false;
4894 bool isInReg = false;
4895 switch (OpInfo.Type) {
4896 case InlineAsm::isOutput:
4899 // If there is an input constraint that matches this, we need to reserve
4900 // the input register so no other inputs allocate to it.
4901 isInReg = OpInfo.hasMatchingInput();
4903 case InlineAsm::isInput:
4907 case InlineAsm::isClobber:
4914 MachineFunction &MF = DAG.getMachineFunction();
4915 SmallVector<unsigned, 4> Regs;
4917 // If this is a constraint for a single physreg, or a constraint for a
4918 // register class, find it.
4919 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4920 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4921 OpInfo.ConstraintVT);
4923 unsigned NumRegs = 1;
4924 if (OpInfo.ConstraintVT != MVT::Other) {
4925 // If this is a FP input in an integer register (or visa versa) insert a bit
4926 // cast of the input value. More generally, handle any case where the input
4927 // value disagrees with the register class we plan to stick this in.
4928 if (OpInfo.Type == InlineAsm::isInput &&
4929 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4930 // Try to convert to the first MVT that the reg class contains. If the
4931 // types are identical size, use a bitcast to convert (e.g. two differing
4933 MVT RegVT = *PhysReg.second->vt_begin();
4934 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4935 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4936 RegVT, OpInfo.CallOperand);
4937 OpInfo.ConstraintVT = RegVT;
4938 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4939 // If the input is a FP value and we want it in FP registers, do a
4940 // bitcast to the corresponding integer type. This turns an f64 value
4941 // into i64, which can be passed with two i32 values on a 32-bit
4943 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4944 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4945 RegVT, OpInfo.CallOperand);
4946 OpInfo.ConstraintVT = RegVT;
4950 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4954 MVT ValueVT = OpInfo.ConstraintVT;
4956 // If this is a constraint for a specific physical register, like {r17},
4958 if (unsigned AssignedReg = PhysReg.first) {
4959 const TargetRegisterClass *RC = PhysReg.second;
4960 if (OpInfo.ConstraintVT == MVT::Other)
4961 ValueVT = *RC->vt_begin();
4963 // Get the actual register value type. This is important, because the user
4964 // may have asked for (e.g.) the AX register in i32 type. We need to
4965 // remember that AX is actually i16 to get the right extension.
4966 RegVT = *RC->vt_begin();
4968 // This is a explicit reference to a physical register.
4969 Regs.push_back(AssignedReg);
4971 // If this is an expanded reference, add the rest of the regs to Regs.
4973 TargetRegisterClass::iterator I = RC->begin();
4974 for (; *I != AssignedReg; ++I)
4975 assert(I != RC->end() && "Didn't find reg!");
4977 // Already added the first reg.
4979 for (; NumRegs; --NumRegs, ++I) {
4980 assert(I != RC->end() && "Ran out of registers to allocate!");
4984 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4985 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4986 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4990 // Otherwise, if this was a reference to an LLVM register class, create vregs
4991 // for this reference.
4992 if (const TargetRegisterClass *RC = PhysReg.second) {
4993 RegVT = *RC->vt_begin();
4994 if (OpInfo.ConstraintVT == MVT::Other)
4997 // Create the appropriate number of virtual registers.
4998 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4999 for (; NumRegs; --NumRegs)
5000 Regs.push_back(RegInfo.createVirtualRegister(RC));
5002 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5006 // This is a reference to a register class that doesn't directly correspond
5007 // to an LLVM register class. Allocate NumRegs consecutive, available,
5008 // registers from the class.
5009 std::vector<unsigned> RegClassRegs
5010 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5011 OpInfo.ConstraintVT);
5013 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5014 unsigned NumAllocated = 0;
5015 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5016 unsigned Reg = RegClassRegs[i];
5017 // See if this register is available.
5018 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5019 (isInReg && InputRegs.count(Reg))) { // Already used.
5020 // Make sure we find consecutive registers.
5025 // Check to see if this register is allocatable (i.e. don't give out the
5027 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5028 if (!RC) { // Couldn't allocate this register.
5029 // Reset NumAllocated to make sure we return consecutive registers.
5034 // Okay, this register is good, we can use it.
5037 // If we allocated enough consecutive registers, succeed.
5038 if (NumAllocated == NumRegs) {
5039 unsigned RegStart = (i-NumAllocated)+1;
5040 unsigned RegEnd = i+1;
5041 // Mark all of the allocated registers used.
5042 for (unsigned i = RegStart; i != RegEnd; ++i)
5043 Regs.push_back(RegClassRegs[i]);
5045 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5046 OpInfo.ConstraintVT);
5047 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5052 // Otherwise, we couldn't allocate enough registers for this.
5055 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5056 /// processed uses a memory 'm' constraint.
5058 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5059 const TargetLowering &TLI) {
5060 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5061 InlineAsm::ConstraintInfo &CI = CInfos[i];
5062 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5063 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5064 if (CType == TargetLowering::C_Memory)
5068 // Indirect operand accesses access memory.
5076 /// visitInlineAsm - Handle a call to an InlineAsm object.
5078 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5079 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5081 /// ConstraintOperands - Information about all of the constraints.
5082 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5084 std::set<unsigned> OutputRegs, InputRegs;
5086 // Do a prepass over the constraints, canonicalizing them, and building up the
5087 // ConstraintOperands list.
5088 std::vector<InlineAsm::ConstraintInfo>
5089 ConstraintInfos = IA->ParseConstraints();
5091 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5093 SDValue Chain, Flag;
5095 // We won't need to flush pending loads if this asm doesn't touch
5096 // memory and is nonvolatile.
5097 if (hasMemory || IA->hasSideEffects())
5100 Chain = DAG.getRoot();
5102 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5103 unsigned ResNo = 0; // ResNo - The result number of the next output.
5104 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5105 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5106 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5108 MVT OpVT = MVT::Other;
5110 // Compute the value type for each operand.
5111 switch (OpInfo.Type) {
5112 case InlineAsm::isOutput:
5113 // Indirect outputs just consume an argument.
5114 if (OpInfo.isIndirect) {
5115 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5119 // The return value of the call is this value. As such, there is no
5120 // corresponding argument.
5121 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5122 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5123 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5125 assert(ResNo == 0 && "Asm only has one result!");
5126 OpVT = TLI.getValueType(CS.getType());
5130 case InlineAsm::isInput:
5131 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5133 case InlineAsm::isClobber:
5138 // If this is an input or an indirect output, process the call argument.
5139 // BasicBlocks are labels, currently appearing only in asm's.
5140 if (OpInfo.CallOperandVal) {
5141 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5142 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5144 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5147 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5150 OpInfo.ConstraintVT = OpVT;
5153 // Second pass over the constraints: compute which constraint option to use
5154 // and assign registers to constraints that want a specific physreg.
5155 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5156 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5158 // If this is an output operand with a matching input operand, look up the
5159 // matching input. If their types mismatch, e.g. one is an integer, the
5160 // other is floating point, or their sizes are different, flag it as an
5162 if (OpInfo.hasMatchingInput()) {
5163 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5164 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5165 if ((OpInfo.ConstraintVT.isInteger() !=
5166 Input.ConstraintVT.isInteger()) ||
5167 (OpInfo.ConstraintVT.getSizeInBits() !=
5168 Input.ConstraintVT.getSizeInBits())) {
5169 cerr << "llvm: error: Unsupported asm: input constraint with a "
5170 << "matching output constraint of incompatible type!\n";
5173 Input.ConstraintVT = OpInfo.ConstraintVT;
5177 // Compute the constraint code and ConstraintType to use.
5178 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5180 // If this is a memory input, and if the operand is not indirect, do what we
5181 // need to to provide an address for the memory input.
5182 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5183 !OpInfo.isIndirect) {
5184 assert(OpInfo.Type == InlineAsm::isInput &&
5185 "Can only indirectify direct input operands!");
5187 // Memory operands really want the address of the value. If we don't have
5188 // an indirect input, put it in the constpool if we can, otherwise spill
5189 // it to a stack slot.
5191 // If the operand is a float, integer, or vector constant, spill to a
5192 // constant pool entry to get its address.
5193 Value *OpVal = OpInfo.CallOperandVal;
5194 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5195 isa<ConstantVector>(OpVal)) {
5196 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5197 TLI.getPointerTy());
5199 // Otherwise, create a stack slot and emit a store to it before the
5201 const Type *Ty = OpVal->getType();
5202 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5203 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5204 MachineFunction &MF = DAG.getMachineFunction();
5205 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5206 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5207 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5208 OpInfo.CallOperand, StackSlot, NULL, 0);
5209 OpInfo.CallOperand = StackSlot;
5212 // There is no longer a Value* corresponding to this operand.
5213 OpInfo.CallOperandVal = 0;
5214 // It is now an indirect operand.
5215 OpInfo.isIndirect = true;
5218 // If this constraint is for a specific register, allocate it before
5220 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5221 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5223 ConstraintInfos.clear();
5226 // Second pass - Loop over all of the operands, assigning virtual or physregs
5227 // to register class operands.
5228 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5229 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5231 // C_Register operands have already been allocated, Other/Memory don't need
5233 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5234 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5237 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5238 std::vector<SDValue> AsmNodeOperands;
5239 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5240 AsmNodeOperands.push_back(
5241 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5244 // Loop over all of the inputs, copying the operand values into the
5245 // appropriate registers and processing the output regs.
5246 RegsForValue RetValRegs;
5248 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5249 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5251 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5252 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5254 switch (OpInfo.Type) {
5255 case InlineAsm::isOutput: {
5256 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5257 OpInfo.ConstraintType != TargetLowering::C_Register) {
5258 // Memory output, or 'other' output (e.g. 'X' constraint).
5259 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5261 // Add information to the INLINEASM node to know about this output.
5262 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5263 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5264 TLI.getPointerTy()));
5265 AsmNodeOperands.push_back(OpInfo.CallOperand);
5269 // Otherwise, this is a register or register class output.
5271 // Copy the output from the appropriate register. Find a register that
5273 if (OpInfo.AssignedRegs.Regs.empty()) {
5274 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5275 << OpInfo.ConstraintCode << "'!\n";
5279 // If this is an indirect operand, store through the pointer after the
5281 if (OpInfo.isIndirect) {
5282 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5283 OpInfo.CallOperandVal));
5285 // This is the result value of the call.
5286 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5287 // Concatenate this output onto the outputs list.
5288 RetValRegs.append(OpInfo.AssignedRegs);
5291 // Add information to the INLINEASM node to know that this register is
5293 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5294 6 /* EARLYCLOBBER REGDEF */ :
5298 DAG, AsmNodeOperands);
5301 case InlineAsm::isInput: {
5302 SDValue InOperandVal = OpInfo.CallOperand;
5304 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5305 // If this is required to match an output register we have already set,
5306 // just use its register.
5307 unsigned OperandNo = OpInfo.getMatchedOperand();
5309 // Scan until we find the definition we already emitted of this operand.
5310 // When we find it, create a RegsForValue operand.
5311 unsigned CurOp = 2; // The first operand.
5312 for (; OperandNo; --OperandNo) {
5313 // Advance to the next operand.
5315 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5316 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5317 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5318 (OpFlag & 7) == 4 /*MEM*/) &&
5319 "Skipped past definitions?");
5320 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5324 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5325 if ((OpFlag & 7) == 2 /*REGDEF*/
5326 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5327 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5328 RegsForValue MatchedRegs;
5329 MatchedRegs.TLI = &TLI;
5330 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5331 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5332 MatchedRegs.RegVTs.push_back(RegVT);
5333 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5334 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5337 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5339 // Use the produced MatchedRegs object to
5340 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5342 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5343 true, OpInfo.getMatchedOperand(),
5344 DAG, AsmNodeOperands);
5347 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5348 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5349 "Unexpected number of operands");
5350 // Add information to the INLINEASM node to know about this input.
5351 // See InlineAsm.h isUseOperandTiedToDef.
5352 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5353 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5354 TLI.getPointerTy()));
5355 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5360 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5361 assert(!OpInfo.isIndirect &&
5362 "Don't know how to handle indirect other inputs yet!");
5364 std::vector<SDValue> Ops;
5365 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5366 hasMemory, Ops, DAG);
5368 cerr << "llvm: error: Invalid operand for inline asm constraint '"
5369 << OpInfo.ConstraintCode << "'!\n";
5373 // Add information to the INLINEASM node to know about this input.
5374 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5375 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5376 TLI.getPointerTy()));
5377 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5379 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5380 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5381 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5382 "Memory operands expect pointer values");
5384 // Add information to the INLINEASM node to know about this input.
5385 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5386 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5387 TLI.getPointerTy()));
5388 AsmNodeOperands.push_back(InOperandVal);
5392 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5393 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5394 "Unknown constraint type!");
5395 assert(!OpInfo.isIndirect &&
5396 "Don't know how to handle indirect register inputs yet!");
5398 // Copy the input into the appropriate registers.
5399 if (OpInfo.AssignedRegs.Regs.empty()) {
5400 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5401 << OpInfo.ConstraintCode << "'!\n";
5405 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5408 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5409 DAG, AsmNodeOperands);
5412 case InlineAsm::isClobber: {
5413 // Add the clobbered value to the operand list, so that the register
5414 // allocator is aware that the physreg got clobbered.
5415 if (!OpInfo.AssignedRegs.Regs.empty())
5416 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5417 false, 0, DAG,AsmNodeOperands);
5423 // Finish up input operands.
5424 AsmNodeOperands[0] = Chain;
5425 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5427 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5428 DAG.getVTList(MVT::Other, MVT::Flag),
5429 &AsmNodeOperands[0], AsmNodeOperands.size());
5430 Flag = Chain.getValue(1);
5432 // If this asm returns a register value, copy the result from that register
5433 // and set it as the value of the call.
5434 if (!RetValRegs.Regs.empty()) {
5435 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5438 // FIXME: Why don't we do this for inline asms with MRVs?
5439 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5440 MVT ResultType = TLI.getValueType(CS.getType());
5442 // If any of the results of the inline asm is a vector, it may have the
5443 // wrong width/num elts. This can happen for register classes that can
5444 // contain multiple different value types. The preg or vreg allocated may
5445 // not have the same VT as was expected. Convert it to the right type
5446 // with bit_convert.
5447 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5448 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5451 } else if (ResultType != Val.getValueType() &&
5452 ResultType.isInteger() && Val.getValueType().isInteger()) {
5453 // If a result value was tied to an input value, the computed result may
5454 // have a wider width than the expected result. Extract the relevant
5456 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5459 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5462 setValue(CS.getInstruction(), Val);
5463 // Don't need to use this as a chain in this case.
5464 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5468 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5470 // Process indirect outputs, first output all of the flagged copies out of
5472 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5473 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5474 Value *Ptr = IndirectStoresToEmit[i].second;
5475 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5477 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5481 // Emit the non-flagged stores from the physregs.
5482 SmallVector<SDValue, 8> OutChains;
5483 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5484 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5485 StoresToEmit[i].first,
5486 getValue(StoresToEmit[i].second),
5487 StoresToEmit[i].second, 0));
5488 if (!OutChains.empty())
5489 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5490 &OutChains[0], OutChains.size());
5495 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5496 SDValue Src = getValue(I.getOperand(0));
5498 // Scale up by the type size in the original i32 type width. Various
5499 // mid-level optimizers may make assumptions about demanded bits etc from the
5500 // i32-ness of the optimizer: we do not want to promote to i64 and then
5501 // multiply on 64-bit targets.
5502 // FIXME: Malloc inst should go away: PR715.
5503 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5504 if (ElementSize != 1)
5505 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5506 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5508 MVT IntPtr = TLI.getPointerTy();
5510 if (IntPtr.bitsLT(Src.getValueType()))
5511 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5512 else if (IntPtr.bitsGT(Src.getValueType()))
5513 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5515 TargetLowering::ArgListTy Args;
5516 TargetLowering::ArgListEntry Entry;
5518 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5519 Args.push_back(Entry);
5521 std::pair<SDValue,SDValue> Result =
5522 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5523 CallingConv::C, PerformTailCallOpt,
5524 DAG.getExternalSymbol("malloc", IntPtr),
5525 Args, DAG, getCurDebugLoc());
5526 setValue(&I, Result.first); // Pointers always fit in registers
5527 DAG.setRoot(Result.second);
5530 void SelectionDAGLowering::visitFree(FreeInst &I) {
5531 TargetLowering::ArgListTy Args;
5532 TargetLowering::ArgListEntry Entry;
5533 Entry.Node = getValue(I.getOperand(0));
5534 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5535 Args.push_back(Entry);
5536 MVT IntPtr = TLI.getPointerTy();
5537 std::pair<SDValue,SDValue> Result =
5538 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5539 CallingConv::C, PerformTailCallOpt,
5540 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5542 DAG.setRoot(Result.second);
5545 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5546 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5547 MVT::Other, getRoot(),
5548 getValue(I.getOperand(1)),
5549 DAG.getSrcValue(I.getOperand(1))));
5552 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5553 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5554 getRoot(), getValue(I.getOperand(0)),
5555 DAG.getSrcValue(I.getOperand(0)));
5557 DAG.setRoot(V.getValue(1));
5560 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5561 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5562 MVT::Other, getRoot(),
5563 getValue(I.getOperand(1)),
5564 DAG.getSrcValue(I.getOperand(1))));
5567 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5568 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5569 MVT::Other, getRoot(),
5570 getValue(I.getOperand(1)),
5571 getValue(I.getOperand(2)),
5572 DAG.getSrcValue(I.getOperand(1)),
5573 DAG.getSrcValue(I.getOperand(2))));
5576 /// TargetLowering::LowerArguments - This is the default LowerArguments
5577 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5578 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5579 /// integrated into SDISel.
5580 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5581 SmallVectorImpl<SDValue> &ArgValues,
5583 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5584 SmallVector<SDValue, 3+16> Ops;
5585 Ops.push_back(DAG.getRoot());
5586 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5587 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5589 // Add one result value for each formal argument.
5590 SmallVector<MVT, 16> RetVals;
5592 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5594 SmallVector<MVT, 4> ValueVTs;
5595 ComputeValueVTs(*this, I->getType(), ValueVTs);
5596 for (unsigned Value = 0, NumValues = ValueVTs.size();
5597 Value != NumValues; ++Value) {
5598 MVT VT = ValueVTs[Value];
5599 const Type *ArgTy = VT.getTypeForMVT();
5600 ISD::ArgFlagsTy Flags;
5601 unsigned OriginalAlignment =
5602 getTargetData()->getABITypeAlignment(ArgTy);
5604 if (F.paramHasAttr(j, Attribute::ZExt))
5606 if (F.paramHasAttr(j, Attribute::SExt))
5608 if (F.paramHasAttr(j, Attribute::InReg))
5610 if (F.paramHasAttr(j, Attribute::StructRet))
5612 if (F.paramHasAttr(j, Attribute::ByVal)) {
5614 const PointerType *Ty = cast<PointerType>(I->getType());
5615 const Type *ElementTy = Ty->getElementType();
5616 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5617 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5618 // For ByVal, alignment should be passed from FE. BE will guess if
5619 // this info is not there but there are cases it cannot get right.
5620 if (F.getParamAlignment(j))
5621 FrameAlign = F.getParamAlignment(j);
5622 Flags.setByValAlign(FrameAlign);
5623 Flags.setByValSize(FrameSize);
5625 if (F.paramHasAttr(j, Attribute::Nest))
5627 Flags.setOrigAlign(OriginalAlignment);
5629 MVT RegisterVT = getRegisterType(VT);
5630 unsigned NumRegs = getNumRegisters(VT);
5631 for (unsigned i = 0; i != NumRegs; ++i) {
5632 RetVals.push_back(RegisterVT);
5633 ISD::ArgFlagsTy MyFlags = Flags;
5634 if (NumRegs > 1 && i == 0)
5636 // if it isn't first piece, alignment must be 1
5638 MyFlags.setOrigAlign(1);
5639 Ops.push_back(DAG.getArgFlags(MyFlags));
5644 RetVals.push_back(MVT::Other);
5647 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5648 DAG.getVTList(&RetVals[0], RetVals.size()),
5649 &Ops[0], Ops.size()).getNode();
5651 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5652 // allows exposing the loads that may be part of the argument access to the
5653 // first DAGCombiner pass.
5654 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5656 // The number of results should match up, except that the lowered one may have
5657 // an extra flag result.
5658 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5659 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5660 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5661 && "Lowering produced unexpected number of results!");
5663 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5664 if (Result != TmpRes.getNode() && Result->use_empty()) {
5665 HandleSDNode Dummy(DAG.getRoot());
5666 DAG.RemoveDeadNode(Result);
5669 Result = TmpRes.getNode();
5671 unsigned NumArgRegs = Result->getNumValues() - 1;
5672 DAG.setRoot(SDValue(Result, NumArgRegs));
5674 // Set up the return result vector.
5677 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5679 SmallVector<MVT, 4> ValueVTs;
5680 ComputeValueVTs(*this, I->getType(), ValueVTs);
5681 for (unsigned Value = 0, NumValues = ValueVTs.size();
5682 Value != NumValues; ++Value) {
5683 MVT VT = ValueVTs[Value];
5684 MVT PartVT = getRegisterType(VT);
5686 unsigned NumParts = getNumRegisters(VT);
5687 SmallVector<SDValue, 4> Parts(NumParts);
5688 for (unsigned j = 0; j != NumParts; ++j)
5689 Parts[j] = SDValue(Result, i++);
5691 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5692 if (F.paramHasAttr(Idx, Attribute::SExt))
5693 AssertOp = ISD::AssertSext;
5694 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5695 AssertOp = ISD::AssertZext;
5697 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5698 PartVT, VT, AssertOp));
5701 assert(i == NumArgRegs && "Argument register count mismatch!");
5705 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5706 /// implementation, which just inserts an ISD::CALL node, which is later custom
5707 /// lowered by the target to something concrete. FIXME: When all targets are
5708 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5709 std::pair<SDValue, SDValue>
5710 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5711 bool RetSExt, bool RetZExt, bool isVarArg,
5713 unsigned CallingConv, bool isTailCall,
5715 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5716 assert((!isTailCall || PerformTailCallOpt) &&
5717 "isTailCall set when tail-call optimizations are disabled!");
5719 SmallVector<SDValue, 32> Ops;
5720 Ops.push_back(Chain); // Op#0 - Chain
5721 Ops.push_back(Callee);
5723 // Handle all of the outgoing arguments.
5724 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5725 SmallVector<MVT, 4> ValueVTs;
5726 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5727 for (unsigned Value = 0, NumValues = ValueVTs.size();
5728 Value != NumValues; ++Value) {
5729 MVT VT = ValueVTs[Value];
5730 const Type *ArgTy = VT.getTypeForMVT();
5731 SDValue Op = SDValue(Args[i].Node.getNode(),
5732 Args[i].Node.getResNo() + Value);
5733 ISD::ArgFlagsTy Flags;
5734 unsigned OriginalAlignment =
5735 getTargetData()->getABITypeAlignment(ArgTy);
5741 if (Args[i].isInReg)
5745 if (Args[i].isByVal) {
5747 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5748 const Type *ElementTy = Ty->getElementType();
5749 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5750 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5751 // For ByVal, alignment should come from FE. BE will guess if this
5752 // info is not there but there are cases it cannot get right.
5753 if (Args[i].Alignment)
5754 FrameAlign = Args[i].Alignment;
5755 Flags.setByValAlign(FrameAlign);
5756 Flags.setByValSize(FrameSize);
5760 Flags.setOrigAlign(OriginalAlignment);
5762 MVT PartVT = getRegisterType(VT);
5763 unsigned NumParts = getNumRegisters(VT);
5764 SmallVector<SDValue, 4> Parts(NumParts);
5765 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5768 ExtendKind = ISD::SIGN_EXTEND;
5769 else if (Args[i].isZExt)
5770 ExtendKind = ISD::ZERO_EXTEND;
5772 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5774 for (unsigned i = 0; i != NumParts; ++i) {
5775 // if it isn't first piece, alignment must be 1
5776 ISD::ArgFlagsTy MyFlags = Flags;
5777 if (NumParts > 1 && i == 0)
5780 MyFlags.setOrigAlign(1);
5782 Ops.push_back(Parts[i]);
5783 Ops.push_back(DAG.getArgFlags(MyFlags));
5788 // Figure out the result value types. We start by making a list of
5789 // the potentially illegal return value types.
5790 SmallVector<MVT, 4> LoweredRetTys;
5791 SmallVector<MVT, 4> RetTys;
5792 ComputeValueVTs(*this, RetTy, RetTys);
5794 // Then we translate that to a list of legal types.
5795 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5797 MVT RegisterVT = getRegisterType(VT);
5798 unsigned NumRegs = getNumRegisters(VT);
5799 for (unsigned i = 0; i != NumRegs; ++i)
5800 LoweredRetTys.push_back(RegisterVT);
5803 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5805 // Create the CALL node.
5806 SDValue Res = DAG.getCall(CallingConv, dl,
5807 isVarArg, isTailCall, isInreg,
5808 DAG.getVTList(&LoweredRetTys[0],
5809 LoweredRetTys.size()),
5812 Chain = Res.getValue(LoweredRetTys.size() - 1);
5814 // Gather up the call result into a single value.
5815 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5816 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5819 AssertOp = ISD::AssertSext;
5821 AssertOp = ISD::AssertZext;
5823 SmallVector<SDValue, 4> ReturnValues;
5825 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5827 MVT RegisterVT = getRegisterType(VT);
5828 unsigned NumRegs = getNumRegisters(VT);
5829 unsigned RegNoEnd = NumRegs + RegNo;
5830 SmallVector<SDValue, 4> Results;
5831 for (; RegNo != RegNoEnd; ++RegNo)
5832 Results.push_back(Res.getValue(RegNo));
5833 SDValue ReturnValue =
5834 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5836 ReturnValues.push_back(ReturnValue);
5838 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5839 DAG.getVTList(&RetTys[0], RetTys.size()),
5840 &ReturnValues[0], ReturnValues.size());
5843 return std::make_pair(Res, Chain);
5846 void TargetLowering::LowerOperationWrapper(SDNode *N,
5847 SmallVectorImpl<SDValue> &Results,
5848 SelectionDAG &DAG) {
5849 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5851 Results.push_back(Res);
5854 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5855 assert(0 && "LowerOperation not implemented for this target!");
5861 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5862 SDValue Op = getValue(V);
5863 assert((Op.getOpcode() != ISD::CopyFromReg ||
5864 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5865 "Copy from a reg to the same reg!");
5866 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5868 RegsForValue RFV(TLI, Reg, V->getType());
5869 SDValue Chain = DAG.getEntryNode();
5870 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5871 PendingExports.push_back(Chain);
5874 #include "llvm/CodeGen/SelectionDAGISel.h"
5876 void SelectionDAGISel::
5877 LowerArguments(BasicBlock *LLVMBB) {
5878 // If this is the entry block, emit arguments.
5879 Function &F = *LLVMBB->getParent();
5880 SDValue OldRoot = SDL->DAG.getRoot();
5881 SmallVector<SDValue, 16> Args;
5882 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5885 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5887 SmallVector<MVT, 4> ValueVTs;
5888 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5889 unsigned NumValues = ValueVTs.size();
5890 if (!AI->use_empty()) {
5891 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5892 SDL->getCurDebugLoc()));
5893 // If this argument is live outside of the entry block, insert a copy from
5894 // whereever we got it to the vreg that other BB's will reference it as.
5895 SDL->CopyToExportRegsIfNeeded(AI);
5900 // Finally, if the target has anything special to do, allow it to do so.
5901 // FIXME: this should insert code into the DAG!
5902 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5905 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5906 /// ensure constants are generated when needed. Remember the virtual registers
5907 /// that need to be added to the Machine PHI nodes as input. We cannot just
5908 /// directly add them, because expansion might result in multiple MBB's for one
5909 /// BB. As such, the start of the BB might correspond to a different MBB than
5913 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5914 TerminatorInst *TI = LLVMBB->getTerminator();
5916 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5918 // Check successor nodes' PHI nodes that expect a constant to be available
5920 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5921 BasicBlock *SuccBB = TI->getSuccessor(succ);
5922 if (!isa<PHINode>(SuccBB->begin())) continue;
5923 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5925 // If this terminator has multiple identical successors (common for
5926 // switches), only handle each succ once.
5927 if (!SuccsHandled.insert(SuccMBB)) continue;
5929 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5932 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5933 // nodes and Machine PHI nodes, but the incoming operands have not been
5935 for (BasicBlock::iterator I = SuccBB->begin();
5936 (PN = dyn_cast<PHINode>(I)); ++I) {
5937 // Ignore dead phi's.
5938 if (PN->use_empty()) continue;
5941 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5943 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5944 unsigned &RegOut = SDL->ConstantsOut[C];
5946 RegOut = FuncInfo->CreateRegForValue(C);
5947 SDL->CopyValueToVirtualRegister(C, RegOut);
5951 Reg = FuncInfo->ValueMap[PHIOp];
5953 assert(isa<AllocaInst>(PHIOp) &&
5954 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5955 "Didn't codegen value into a register!??");
5956 Reg = FuncInfo->CreateRegForValue(PHIOp);
5957 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5961 // Remember that this register needs to added to the machine PHI node as
5962 // the input for this MBB.
5963 SmallVector<MVT, 4> ValueVTs;
5964 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5965 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5966 MVT VT = ValueVTs[vti];
5967 unsigned NumRegisters = TLI.getNumRegisters(VT);
5968 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5969 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5970 Reg += NumRegisters;
5974 SDL->ConstantsOut.clear();
5977 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5978 /// supports legal types, and it emits MachineInstrs directly instead of
5979 /// creating SelectionDAG nodes.
5982 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5984 TerminatorInst *TI = LLVMBB->getTerminator();
5986 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5987 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5989 // Check successor nodes' PHI nodes that expect a constant to be available
5991 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5992 BasicBlock *SuccBB = TI->getSuccessor(succ);
5993 if (!isa<PHINode>(SuccBB->begin())) continue;
5994 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5996 // If this terminator has multiple identical successors (common for
5997 // switches), only handle each succ once.
5998 if (!SuccsHandled.insert(SuccMBB)) continue;
6000 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6003 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6004 // nodes and Machine PHI nodes, but the incoming operands have not been
6006 for (BasicBlock::iterator I = SuccBB->begin();
6007 (PN = dyn_cast<PHINode>(I)); ++I) {
6008 // Ignore dead phi's.
6009 if (PN->use_empty()) continue;
6011 // Only handle legal types. Two interesting things to note here. First,
6012 // by bailing out early, we may leave behind some dead instructions,
6013 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6014 // own moves. Second, this check is necessary becuase FastISel doesn't
6015 // use CreateRegForValue to create registers, so it always creates
6016 // exactly one register for each non-void instruction.
6017 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6018 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6021 VT = TLI.getTypeToTransformTo(VT);
6023 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6028 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6030 unsigned Reg = F->getRegForValue(PHIOp);
6032 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6035 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));