1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Interpret void as zero return values.
139 if (Ty == Type::VoidTy)
141 // Base case: we can get an MVT for this LLVM IR type.
142 ValueVTs.push_back(TLI.getValueType(Ty));
144 Offsets->push_back(StartingOffset);
148 /// RegsForValue - This struct represents the registers (physical or virtual)
149 /// that a particular set of values is assigned, and the type information about
150 /// the value. The most common situation is to represent one value at a time,
151 /// but struct or array values are handled element-wise as multiple values.
152 /// The splitting of aggregates is performed recursively, so that we never
153 /// have aggregate-typed registers. The values at this point do not necessarily
154 /// have legal types, so each value may require one or more registers of some
157 struct VISIBILITY_HIDDEN RegsForValue {
158 /// TLI - The TargetLowering object.
160 const TargetLowering *TLI;
162 /// ValueVTs - The value types of the values, which may not be legal, and
163 /// may need be promoted or synthesized from one or more registers.
165 SmallVector<MVT, 4> ValueVTs;
167 /// RegVTs - The value types of the registers. This is the same size as
168 /// ValueVTs and it records, for each value, what the type of the assigned
169 /// register or registers are. (Individual values are never synthesized
170 /// from more than one type of register.)
172 /// With virtual registers, the contents of RegVTs is redundant with TLI's
173 /// getRegisterType member function, however when with physical registers
174 /// it is necessary to have a separate record of the types.
176 SmallVector<MVT, 4> RegVTs;
178 /// Regs - This list holds the registers assigned to the values.
179 /// Each legal or promoted value requires one register, and each
180 /// expanded value requires multiple registers.
182 SmallVector<unsigned, 4> Regs;
184 RegsForValue() : TLI(0) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 MVT regvt, MVT valuevt)
189 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
190 RegsForValue(const TargetLowering &tli,
191 const SmallVector<unsigned, 4> ®s,
192 const SmallVector<MVT, 4> ®vts,
193 const SmallVector<MVT, 4> &valuevts)
194 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
195 RegsForValue(const TargetLowering &tli,
196 unsigned Reg, const Type *Ty) : TLI(&tli) {
197 ComputeValueVTs(tli, Ty, ValueVTs);
199 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
200 MVT ValueVT = ValueVTs[Value];
201 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
202 MVT RegisterVT = TLI->getRegisterType(ValueVT);
203 for (unsigned i = 0; i != NumRegs; ++i)
204 Regs.push_back(Reg + i);
205 RegVTs.push_back(RegisterVT);
210 /// append - Add the specified values to this one.
211 void append(const RegsForValue &RHS) {
213 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
214 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
215 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
219 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
220 /// this value and returns the result as a ValueVTs value. This uses
221 /// Chain/Flag as the input and updates them for the output Chain/Flag.
222 /// If the Flag pointer is NULL, no flag is used.
223 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
224 SDValue &Chain, SDValue *Flag) const;
226 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
227 /// specified value into the registers specified by this object. This uses
228 /// Chain/Flag as the input and updates them for the output Chain/Flag.
229 /// If the Flag pointer is NULL, no flag is used.
230 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
231 SDValue &Chain, SDValue *Flag) const;
233 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
234 /// operand list. This adds the code marker, matching input operand index
235 /// (if applicable), and includes the number of values added into it.
236 void AddInlineAsmOperands(unsigned Code,
237 bool HasMatching, unsigned MatchingIdx,
238 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
242 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
243 /// PHI nodes or outside of the basic block that defines it, or used by a
244 /// switch or atomic instruction, which may expand to multiple basic blocks.
245 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
246 if (isa<PHINode>(I)) return true;
247 BasicBlock *BB = I->getParent();
248 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
249 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
254 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
255 /// entry block, return true. This includes arguments used by switches, since
256 /// the switch may expand into multiple basic blocks.
257 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
258 // With FastISel active, we may be splitting blocks, so force creation
259 // of virtual registers for all non-dead arguments.
260 // Don't force virtual registers for byval arguments though, because
261 // fast-isel can't handle those in all cases.
262 if (EnableFastISel && !A->hasByValAttr())
263 return A->use_empty();
265 BasicBlock *Entry = A->getParent()->begin();
266 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
267 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
268 return false; // Use not in entry block.
272 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
276 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 bool EnableFastISel) {
281 RegInfo = &MF->getRegInfo();
283 // Create a vreg for each argument register that is not dead and is used
284 // outside of the entry block for the function.
285 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
288 InitializeRegForValue(AI);
290 // Initialize the mapping of values to registers. This is only set up for
291 // instruction values that are used outside of the block that defines
293 Function::iterator BB = Fn->begin(), EB = Fn->end();
294 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
295 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
296 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
297 const Type *Ty = AI->getAllocatedType();
298 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
300 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
303 TySize *= CUI->getZExtValue(); // Get total allocated size.
304 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
305 StaticAllocaMap[AI] =
306 MF->getFrameInfo()->CreateStackObject(TySize, Align);
309 for (; BB != EB; ++BB)
310 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
311 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
312 if (!isa<AllocaInst>(I) ||
313 !StaticAllocaMap.count(cast<AllocaInst>(I)))
314 InitializeRegForValue(I);
316 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
317 // also creates the initial PHI MachineInstrs, though none of the input
318 // operands are populated.
319 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
320 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
324 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
328 for (BasicBlock::iterator
329 I = BB->begin(), E = BB->end(); I != E; ++I) {
330 if (CallInst *CI = dyn_cast<CallInst>(I)) {
331 if (Function *F = CI->getCalledFunction()) {
332 switch (F->getIntrinsicID()) {
334 case Intrinsic::dbg_stoppoint: {
335 DwarfWriter *DW = DAG.getDwarfWriter();
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
338 if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
339 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
341 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
343 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
346 DL = DebugLoc::get(idx);
351 case Intrinsic::dbg_func_start: {
352 DwarfWriter *DW = DAG.getDwarfWriter();
354 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
355 Value *SP = FSI->getSubprogram();
357 if (DW->ValidDebugInfo(SP, false)) {
358 DISubprogram Subprogram(cast<GlobalVariable>(SP));
359 DICompileUnit CU(Subprogram.getCompileUnit());
361 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
363 unsigned Line = Subprogram.getLineNumber();
364 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
374 PN = dyn_cast<PHINode>(I);
375 if (!PN || PN->use_empty()) continue;
377 unsigned PHIReg = ValueMap[PN];
378 assert(PHIReg && "PHI node does not have an assigned virtual register!");
380 SmallVector<MVT, 4> ValueVTs;
381 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
382 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
383 MVT VT = ValueVTs[vti];
384 unsigned NumRegisters = TLI.getNumRegisters(VT);
385 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
386 for (unsigned i = 0; i != NumRegisters; ++i)
387 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
388 PHIReg += NumRegisters;
394 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
395 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
398 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
399 /// the correctly promoted or expanded types. Assign these registers
400 /// consecutive vreg numbers and return the first assigned number.
402 /// In the case that the given value has struct or array type, this function
403 /// will assign registers for each member or element.
405 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
406 SmallVector<MVT, 4> ValueVTs;
407 ComputeValueVTs(TLI, V->getType(), ValueVTs);
409 unsigned FirstReg = 0;
410 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
411 MVT ValueVT = ValueVTs[Value];
412 MVT RegisterVT = TLI.getRegisterType(ValueVT);
414 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
415 for (unsigned i = 0; i != NumRegs; ++i) {
416 unsigned R = MakeReg(RegisterVT);
417 if (!FirstReg) FirstReg = R;
423 /// getCopyFromParts - Create a value that contains the specified legal parts
424 /// combined into the value they represent. If the parts combine to a type
425 /// larger then ValueVT then AssertOp can be used to specify whether the extra
426 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
427 /// (ISD::AssertSext).
428 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
429 const SDValue *Parts,
430 unsigned NumParts, MVT PartVT, MVT ValueVT,
431 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
432 assert(NumParts > 0 && "No parts to assemble!");
433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
434 SDValue Val = Parts[0];
437 // Assemble the value from multiple parts.
438 if (!ValueVT.isVector()) {
439 unsigned PartBits = PartVT.getSizeInBits();
440 unsigned ValueBits = ValueVT.getSizeInBits();
442 // Assemble the power of 2 part.
443 unsigned RoundParts = NumParts & (NumParts - 1) ?
444 1 << Log2_32(NumParts) : NumParts;
445 unsigned RoundBits = PartBits * RoundParts;
446 MVT RoundVT = RoundBits == ValueBits ?
447 ValueVT : MVT::getIntegerVT(RoundBits);
450 MVT HalfVT = ValueVT.isInteger() ?
451 MVT::getIntegerVT(RoundBits/2) :
452 MVT::getFloatingPointVT(RoundBits/2);
454 if (RoundParts > 2) {
455 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
456 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
459 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
460 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
462 if (TLI.isBigEndian())
464 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
466 if (RoundParts < NumParts) {
467 // Assemble the trailing non-power-of-2 part.
468 unsigned OddParts = NumParts - RoundParts;
469 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
470 Hi = getCopyFromParts(DAG, dl,
471 Parts+RoundParts, OddParts, PartVT, OddVT);
473 // Combine the round and odd parts.
475 if (TLI.isBigEndian())
477 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
478 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
479 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
480 DAG.getConstant(Lo.getValueType().getSizeInBits(),
481 TLI.getPointerTy()));
482 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
483 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
486 // Handle a multi-element vector.
487 MVT IntermediateVT, RegisterVT;
488 unsigned NumIntermediates;
490 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
492 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
493 NumParts = NumRegs; // Silence a compiler warning.
494 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
495 assert(RegisterVT == Parts[0].getValueType() &&
496 "Part type doesn't match part!");
498 // Assemble the parts into intermediate operands.
499 SmallVector<SDValue, 8> Ops(NumIntermediates);
500 if (NumIntermediates == NumParts) {
501 // If the register was not expanded, truncate or copy the value,
503 for (unsigned i = 0; i != NumParts; ++i)
504 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
505 PartVT, IntermediateVT);
506 } else if (NumParts > 0) {
507 // If the intermediate type was expanded, build the intermediate operands
509 assert(NumParts % NumIntermediates == 0 &&
510 "Must expand into a divisible number of parts!");
511 unsigned Factor = NumParts / NumIntermediates;
512 for (unsigned i = 0; i != NumIntermediates; ++i)
513 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
514 PartVT, IntermediateVT);
517 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
519 Val = DAG.getNode(IntermediateVT.isVector() ?
520 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
521 ValueVT, &Ops[0], NumIntermediates);
525 // There is now one part, held in Val. Correct it to match ValueVT.
526 PartVT = Val.getValueType();
528 if (PartVT == ValueVT)
531 if (PartVT.isVector()) {
532 assert(ValueVT.isVector() && "Unknown vector conversion!");
533 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
536 if (ValueVT.isVector()) {
537 assert(ValueVT.getVectorElementType() == PartVT &&
538 ValueVT.getVectorNumElements() == 1 &&
539 "Only trivial scalar-to-vector conversions should get here!");
540 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
543 if (PartVT.isInteger() &&
544 ValueVT.isInteger()) {
545 if (ValueVT.bitsLT(PartVT)) {
546 // For a truncate, see if we have any information to
547 // indicate whether the truncated bits will always be
548 // zero or sign-extension.
549 if (AssertOp != ISD::DELETED_NODE)
550 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
551 DAG.getValueType(ValueVT));
552 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
554 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
558 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
559 if (ValueVT.bitsLT(Val.getValueType()))
560 // FP_ROUND's are always exact here.
561 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
562 DAG.getIntPtrConstant(1));
563 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
566 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
567 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
569 assert(0 && "Unknown mismatch!");
573 /// getCopyToParts - Create a series of nodes that contain the specified value
574 /// split into legal parts. If the parts contain more bits than Val, then, for
575 /// integers, ExtendKind can be used to specify how to generate the extra bits.
576 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
577 SDValue *Parts, unsigned NumParts, MVT PartVT,
578 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
580 MVT PtrVT = TLI.getPointerTy();
581 MVT ValueVT = Val.getValueType();
582 unsigned PartBits = PartVT.getSizeInBits();
583 unsigned OrigNumParts = NumParts;
584 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
589 if (!ValueVT.isVector()) {
590 if (PartVT == ValueVT) {
591 assert(NumParts == 1 && "No-op copy with multiple parts!");
596 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
597 // If the parts cover more bits than the value has, promote the value.
598 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
599 assert(NumParts == 1 && "Do not know what to promote to!");
600 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
601 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
602 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
603 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
605 assert(0 && "Unknown mismatch!");
607 } else if (PartBits == ValueVT.getSizeInBits()) {
608 // Different types of the same size.
609 assert(NumParts == 1 && PartVT != ValueVT);
610 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
611 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
612 // If the parts cover less bits than value has, truncate the value.
613 if (PartVT.isInteger() && ValueVT.isInteger()) {
614 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
615 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
617 assert(0 && "Unknown mismatch!");
621 // The value may have changed - recompute ValueVT.
622 ValueVT = Val.getValueType();
623 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
624 "Failed to tile the value with PartVT!");
627 assert(PartVT == ValueVT && "Type conversion failed!");
632 // Expand the value into multiple parts.
633 if (NumParts & (NumParts - 1)) {
634 // The number of parts is not a power of 2. Split off and copy the tail.
635 assert(PartVT.isInteger() && ValueVT.isInteger() &&
636 "Do not know what to expand to!");
637 unsigned RoundParts = 1 << Log2_32(NumParts);
638 unsigned RoundBits = RoundParts * PartBits;
639 unsigned OddParts = NumParts - RoundParts;
640 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
641 DAG.getConstant(RoundBits,
642 TLI.getPointerTy()));
643 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
644 if (TLI.isBigEndian())
645 // The odd parts were reversed by getCopyToParts - unreverse them.
646 std::reverse(Parts + RoundParts, Parts + NumParts);
647 NumParts = RoundParts;
648 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
649 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
652 // The number of parts is a power of 2. Repeatedly bisect the value using
654 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
655 MVT::getIntegerVT(ValueVT.getSizeInBits()),
657 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
658 for (unsigned i = 0; i < NumParts; i += StepSize) {
659 unsigned ThisBits = StepSize * PartBits / 2;
660 MVT ThisVT = MVT::getIntegerVT (ThisBits);
661 SDValue &Part0 = Parts[i];
662 SDValue &Part1 = Parts[i+StepSize/2];
664 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
666 DAG.getConstant(1, PtrVT));
667 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
669 DAG.getConstant(0, PtrVT));
671 if (ThisBits == PartBits && ThisVT != PartVT) {
672 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
680 if (TLI.isBigEndian())
681 std::reverse(Parts, Parts + OrigNumParts);
688 if (PartVT != ValueVT) {
689 if (PartVT.isVector()) {
690 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
692 assert(ValueVT.getVectorElementType() == PartVT &&
693 ValueVT.getVectorNumElements() == 1 &&
694 "Only trivial vector-to-scalar conversions should get here!");
695 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
697 DAG.getConstant(0, PtrVT));
705 // Handle a multi-element vector.
706 MVT IntermediateVT, RegisterVT;
707 unsigned NumIntermediates;
708 unsigned NumRegs = TLI
709 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
711 unsigned NumElements = ValueVT.getVectorNumElements();
713 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
714 NumParts = NumRegs; // Silence a compiler warning.
715 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
717 // Split the vector into intermediate operands.
718 SmallVector<SDValue, 8> Ops(NumIntermediates);
719 for (unsigned i = 0; i != NumIntermediates; ++i)
720 if (IntermediateVT.isVector())
721 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
723 DAG.getConstant(i * (NumElements / NumIntermediates),
726 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
728 DAG.getConstant(i, PtrVT));
730 // Split the intermediate operands into legal parts.
731 if (NumParts == NumIntermediates) {
732 // If the register was not expanded, promote or copy the value,
734 for (unsigned i = 0; i != NumParts; ++i)
735 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
736 } else if (NumParts > 0) {
737 // If the intermediate type was expanded, split each the value into
739 assert(NumParts % NumIntermediates == 0 &&
740 "Must expand into a divisible number of parts!");
741 unsigned Factor = NumParts / NumIntermediates;
742 for (unsigned i = 0; i != NumIntermediates; ++i)
743 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
748 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
751 TD = DAG.getTarget().getTargetData();
754 /// clear - Clear out the curret SelectionDAG and the associated
755 /// state and prepare this SelectionDAGLowering object to be used
756 /// for a new block. This doesn't clear out information about
757 /// additional blocks that are needed to complete switch lowering
758 /// or PHI node updating; that information is cleared out as it is
760 void SelectionDAGLowering::clear() {
762 PendingLoads.clear();
763 PendingExports.clear();
765 CurDebugLoc = DebugLoc::getUnknownLoc();
768 /// getRoot - Return the current virtual root of the Selection DAG,
769 /// flushing any PendingLoad items. This must be done before emitting
770 /// a store or any other node that may need to be ordered after any
771 /// prior load instructions.
773 SDValue SelectionDAGLowering::getRoot() {
774 if (PendingLoads.empty())
775 return DAG.getRoot();
777 if (PendingLoads.size() == 1) {
778 SDValue Root = PendingLoads[0];
780 PendingLoads.clear();
784 // Otherwise, we have to make a token factor node.
785 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
786 &PendingLoads[0], PendingLoads.size());
787 PendingLoads.clear();
792 /// getControlRoot - Similar to getRoot, but instead of flushing all the
793 /// PendingLoad items, flush all the PendingExports items. It is necessary
794 /// to do this before emitting a terminator instruction.
796 SDValue SelectionDAGLowering::getControlRoot() {
797 SDValue Root = DAG.getRoot();
799 if (PendingExports.empty())
802 // Turn all of the CopyToReg chains into one factored node.
803 if (Root.getOpcode() != ISD::EntryToken) {
804 unsigned i = 0, e = PendingExports.size();
805 for (; i != e; ++i) {
806 assert(PendingExports[i].getNode()->getNumOperands() > 1);
807 if (PendingExports[i].getNode()->getOperand(0) == Root)
808 break; // Don't add the root if we already indirectly depend on it.
812 PendingExports.push_back(Root);
815 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
817 PendingExports.size());
818 PendingExports.clear();
823 void SelectionDAGLowering::visit(Instruction &I) {
824 visit(I.getOpcode(), I);
827 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
828 // Note: this doesn't use InstVisitor, because it has to work with
829 // ConstantExpr's in addition to instructions.
831 default: assert(0 && "Unknown instruction type encountered!");
833 // Build the switch statement using the Instruction.def file.
834 #define HANDLE_INST(NUM, OPCODE, CLASS) \
835 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
836 #include "llvm/Instruction.def"
840 void SelectionDAGLowering::visitAdd(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FADD);
844 visitBinary(I, ISD::ADD);
847 void SelectionDAGLowering::visitMul(User &I) {
848 if (I.getType()->isFPOrFPVector())
849 visitBinary(I, ISD::FMUL);
851 visitBinary(I, ISD::MUL);
854 SDValue SelectionDAGLowering::getValue(const Value *V) {
855 SDValue &N = NodeMap[V];
856 if (N.getNode()) return N;
858 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
859 MVT VT = TLI.getValueType(V->getType(), true);
861 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
862 return N = DAG.getConstant(*CI, VT);
864 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
865 return N = DAG.getGlobalAddress(GV, VT);
867 if (isa<ConstantPointerNull>(C))
868 return N = DAG.getConstant(0, TLI.getPointerTy());
870 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
871 return N = DAG.getConstantFP(*CFP, VT);
873 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
874 !V->getType()->isAggregateType())
875 return N = DAG.getUNDEF(VT);
877 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
878 visit(CE->getOpcode(), *CE);
879 SDValue N1 = NodeMap[V];
880 assert(N1.getNode() && "visit didn't populate the ValueMap!");
884 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
885 SmallVector<SDValue, 4> Constants;
886 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
888 SDNode *Val = getValue(*OI).getNode();
889 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
890 Constants.push_back(SDValue(Val, i));
892 return DAG.getMergeValues(&Constants[0], Constants.size(),
896 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
897 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
898 "Unknown struct or array constant!");
900 SmallVector<MVT, 4> ValueVTs;
901 ComputeValueVTs(TLI, C->getType(), ValueVTs);
902 unsigned NumElts = ValueVTs.size();
904 return SDValue(); // empty struct
905 SmallVector<SDValue, 4> Constants(NumElts);
906 for (unsigned i = 0; i != NumElts; ++i) {
907 MVT EltVT = ValueVTs[i];
908 if (isa<UndefValue>(C))
909 Constants[i] = DAG.getUNDEF(EltVT);
910 else if (EltVT.isFloatingPoint())
911 Constants[i] = DAG.getConstantFP(0, EltVT);
913 Constants[i] = DAG.getConstant(0, EltVT);
915 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
918 const VectorType *VecTy = cast<VectorType>(V->getType());
919 unsigned NumElements = VecTy->getNumElements();
921 // Now that we know the number and type of the elements, get that number of
922 // elements into the Ops array based on what kind of constant it is.
923 SmallVector<SDValue, 16> Ops;
924 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
925 for (unsigned i = 0; i != NumElements; ++i)
926 Ops.push_back(getValue(CP->getOperand(i)));
928 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
929 "Unknown vector constant!");
930 MVT EltVT = TLI.getValueType(VecTy->getElementType());
933 if (isa<UndefValue>(C))
934 Op = DAG.getUNDEF(EltVT);
935 else if (EltVT.isFloatingPoint())
936 Op = DAG.getConstantFP(0, EltVT);
938 Op = DAG.getConstant(0, EltVT);
939 Ops.assign(NumElements, Op);
942 // Create a BUILD_VECTOR node.
943 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
944 VT, &Ops[0], Ops.size());
947 // If this is a static alloca, generate it as the frameindex instead of
949 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
950 DenseMap<const AllocaInst*, int>::iterator SI =
951 FuncInfo.StaticAllocaMap.find(AI);
952 if (SI != FuncInfo.StaticAllocaMap.end())
953 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
956 unsigned InReg = FuncInfo.ValueMap[V];
957 assert(InReg && "Value not in map!");
959 RegsForValue RFV(TLI, InReg, V->getType());
960 SDValue Chain = DAG.getEntryNode();
961 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
965 void SelectionDAGLowering::visitRet(ReturnInst &I) {
966 if (I.getNumOperands() == 0) {
967 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
968 MVT::Other, getControlRoot()));
972 SmallVector<SDValue, 8> NewValues;
973 NewValues.push_back(getControlRoot());
974 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
975 SmallVector<MVT, 4> ValueVTs;
976 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
977 unsigned NumValues = ValueVTs.size();
978 if (NumValues == 0) continue;
980 SDValue RetOp = getValue(I.getOperand(i));
981 for (unsigned j = 0, f = NumValues; j != f; ++j) {
982 MVT VT = ValueVTs[j];
984 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
986 const Function *F = I.getParent()->getParent();
987 if (F->paramHasAttr(0, Attribute::SExt))
988 ExtendKind = ISD::SIGN_EXTEND;
989 else if (F->paramHasAttr(0, Attribute::ZExt))
990 ExtendKind = ISD::ZERO_EXTEND;
992 // FIXME: C calling convention requires the return type to be promoted to
993 // at least 32-bit. But this is not necessary for non-C calling
994 // conventions. The frontend should mark functions whose return values
995 // require promoting with signext or zeroext attributes.
996 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
997 MVT MinVT = TLI.getRegisterType(MVT::i32);
998 if (VT.bitsLT(MinVT))
1002 unsigned NumParts = TLI.getNumRegisters(VT);
1003 MVT PartVT = TLI.getRegisterType(VT);
1004 SmallVector<SDValue, 4> Parts(NumParts);
1005 getCopyToParts(DAG, getCurDebugLoc(),
1006 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1007 &Parts[0], NumParts, PartVT, ExtendKind);
1009 // 'inreg' on function refers to return value
1010 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1011 if (F->paramHasAttr(0, Attribute::InReg))
1013 for (unsigned i = 0; i < NumParts; ++i) {
1014 NewValues.push_back(Parts[i]);
1015 NewValues.push_back(DAG.getArgFlags(Flags));
1019 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1020 &NewValues[0], NewValues.size()));
1023 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1024 /// the current basic block, add it to ValueMap now so that we'll get a
1026 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1027 // No need to export constants.
1028 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1030 // Already exported?
1031 if (FuncInfo.isExportedInst(V)) return;
1033 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1034 CopyValueToVirtualRegister(V, Reg);
1037 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1038 const BasicBlock *FromBB) {
1039 // The operands of the setcc have to be in this block. We don't know
1040 // how to export them from some other block.
1041 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1042 // Can export from current BB.
1043 if (VI->getParent() == FromBB)
1046 // Is already exported, noop.
1047 return FuncInfo.isExportedInst(V);
1050 // If this is an argument, we can export it if the BB is the entry block or
1051 // if it is already exported.
1052 if (isa<Argument>(V)) {
1053 if (FromBB == &FromBB->getParent()->getEntryBlock())
1056 // Otherwise, can only export this if it is already exported.
1057 return FuncInfo.isExportedInst(V);
1060 // Otherwise, constants can always be exported.
1064 static bool InBlock(const Value *V, const BasicBlock *BB) {
1065 if (const Instruction *I = dyn_cast<Instruction>(V))
1066 return I->getParent() == BB;
1070 /// getFCmpCondCode - Return the ISD condition code corresponding to
1071 /// the given LLVM IR floating-point condition code. This includes
1072 /// consideration of global floating-point math flags.
1074 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1075 ISD::CondCode FPC, FOC;
1077 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1078 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1079 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1080 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1081 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1082 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1083 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1084 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1085 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1086 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1087 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1088 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1089 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1090 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1091 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1092 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1094 assert(0 && "Invalid FCmp predicate opcode!");
1095 FOC = FPC = ISD::SETFALSE;
1098 if (FiniteOnlyFPMath())
1104 /// getICmpCondCode - Return the ISD condition code corresponding to
1105 /// the given LLVM IR integer condition code.
1107 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1109 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1110 case ICmpInst::ICMP_NE: return ISD::SETNE;
1111 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1112 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1113 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1114 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1115 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1116 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1117 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1118 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1120 assert(0 && "Invalid ICmp predicate opcode!");
1125 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1126 /// This function emits a branch and is used at the leaves of an OR or an
1127 /// AND operator tree.
1130 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1131 MachineBasicBlock *TBB,
1132 MachineBasicBlock *FBB,
1133 MachineBasicBlock *CurBB) {
1134 const BasicBlock *BB = CurBB->getBasicBlock();
1136 // If the leaf of the tree is a comparison, merge the condition into
1138 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1139 // The operands of the cmp have to be in this block. We don't know
1140 // how to export them from some other block. If this is the first block
1141 // of the sequence, no exporting is needed.
1142 if (CurBB == CurMBB ||
1143 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1144 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1145 ISD::CondCode Condition;
1146 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1147 Condition = getICmpCondCode(IC->getPredicate());
1148 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1149 Condition = getFCmpCondCode(FC->getPredicate());
1151 Condition = ISD::SETEQ; // silence warning.
1152 assert(0 && "Unknown compare instruction");
1155 CaseBlock CB(Condition, BOp->getOperand(0),
1156 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1157 SwitchCases.push_back(CB);
1162 // Create a CaseBlock record representing this branch.
1163 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1164 NULL, TBB, FBB, CurBB);
1165 SwitchCases.push_back(CB);
1168 /// FindMergedConditions - If Cond is an expression like
1169 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1170 MachineBasicBlock *TBB,
1171 MachineBasicBlock *FBB,
1172 MachineBasicBlock *CurBB,
1174 // If this node is not part of the or/and tree, emit it as a branch.
1175 Instruction *BOp = dyn_cast<Instruction>(Cond);
1176 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1177 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1178 BOp->getParent() != CurBB->getBasicBlock() ||
1179 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1180 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1181 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1185 // Create TmpBB after CurBB.
1186 MachineFunction::iterator BBI = CurBB;
1187 MachineFunction &MF = DAG.getMachineFunction();
1188 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1189 CurBB->getParent()->insert(++BBI, TmpBB);
1191 if (Opc == Instruction::Or) {
1192 // Codegen X | Y as:
1200 // Emit the LHS condition.
1201 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1203 // Emit the RHS condition into TmpBB.
1204 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1206 assert(Opc == Instruction::And && "Unknown merge op!");
1207 // Codegen X & Y as:
1214 // This requires creation of TmpBB after CurBB.
1216 // Emit the LHS condition.
1217 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1219 // Emit the RHS condition into TmpBB.
1220 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1224 /// If the set of cases should be emitted as a series of branches, return true.
1225 /// If we should emit this as a bunch of and/or'd together conditions, return
1228 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1229 if (Cases.size() != 2) return true;
1231 // If this is two comparisons of the same values or'd or and'd together, they
1232 // will get folded into a single comparison, so don't emit two blocks.
1233 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1234 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1235 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1236 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1243 void SelectionDAGLowering::visitBr(BranchInst &I) {
1244 // Update machine-CFG edges.
1245 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1247 // Figure out which block is immediately after the current one.
1248 MachineBasicBlock *NextBlock = 0;
1249 MachineFunction::iterator BBI = CurMBB;
1250 if (++BBI != CurMBB->getParent()->end())
1253 if (I.isUnconditional()) {
1254 // Update machine-CFG edges.
1255 CurMBB->addSuccessor(Succ0MBB);
1257 // If this is not a fall-through branch, emit the branch.
1258 if (Succ0MBB != NextBlock)
1259 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1260 MVT::Other, getControlRoot(),
1261 DAG.getBasicBlock(Succ0MBB)));
1265 // If this condition is one of the special cases we handle, do special stuff
1267 Value *CondVal = I.getCondition();
1268 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1270 // If this is a series of conditions that are or'd or and'd together, emit
1271 // this as a sequence of branches instead of setcc's with and/or operations.
1272 // For example, instead of something like:
1285 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1286 if (BOp->hasOneUse() &&
1287 (BOp->getOpcode() == Instruction::And ||
1288 BOp->getOpcode() == Instruction::Or)) {
1289 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1290 // If the compares in later blocks need to use values not currently
1291 // exported from this block, export them now. This block should always
1292 // be the first entry.
1293 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1295 // Allow some cases to be rejected.
1296 if (ShouldEmitAsBranches(SwitchCases)) {
1297 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1298 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1299 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1302 // Emit the branch for this block.
1303 visitSwitchCase(SwitchCases[0]);
1304 SwitchCases.erase(SwitchCases.begin());
1308 // Okay, we decided not to do this, remove any inserted MBB's and clear
1310 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1311 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1313 SwitchCases.clear();
1317 // Create a CaseBlock record representing this branch.
1318 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1319 NULL, Succ0MBB, Succ1MBB, CurMBB);
1320 // Use visitSwitchCase to actually insert the fast branch sequence for this
1322 visitSwitchCase(CB);
1325 /// visitSwitchCase - Emits the necessary code to represent a single node in
1326 /// the binary search tree resulting from lowering a switch instruction.
1327 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1329 SDValue CondLHS = getValue(CB.CmpLHS);
1330 DebugLoc dl = getCurDebugLoc();
1332 // Build the setcc now.
1333 if (CB.CmpMHS == NULL) {
1334 // Fold "(X == true)" to X and "(X == false)" to !X to
1335 // handle common cases produced by branch lowering.
1336 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1338 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1339 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1340 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1342 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1344 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1346 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1347 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1349 SDValue CmpOp = getValue(CB.CmpMHS);
1350 MVT VT = CmpOp.getValueType();
1352 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1353 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1356 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1357 VT, CmpOp, DAG.getConstant(Low, VT));
1358 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1359 DAG.getConstant(High-Low, VT), ISD::SETULE);
1363 // Update successor info
1364 CurMBB->addSuccessor(CB.TrueBB);
1365 CurMBB->addSuccessor(CB.FalseBB);
1367 // Set NextBlock to be the MBB immediately after the current one, if any.
1368 // This is used to avoid emitting unnecessary branches to the next block.
1369 MachineBasicBlock *NextBlock = 0;
1370 MachineFunction::iterator BBI = CurMBB;
1371 if (++BBI != CurMBB->getParent()->end())
1374 // If the lhs block is the next block, invert the condition so that we can
1375 // fall through to the lhs instead of the rhs block.
1376 if (CB.TrueBB == NextBlock) {
1377 std::swap(CB.TrueBB, CB.FalseBB);
1378 SDValue True = DAG.getConstant(1, Cond.getValueType());
1379 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1381 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1382 MVT::Other, getControlRoot(), Cond,
1383 DAG.getBasicBlock(CB.TrueBB));
1385 // If the branch was constant folded, fix up the CFG.
1386 if (BrCond.getOpcode() == ISD::BR) {
1387 CurMBB->removeSuccessor(CB.FalseBB);
1388 DAG.setRoot(BrCond);
1390 // Otherwise, go ahead and insert the false branch.
1391 if (BrCond == getControlRoot())
1392 CurMBB->removeSuccessor(CB.TrueBB);
1394 if (CB.FalseBB == NextBlock)
1395 DAG.setRoot(BrCond);
1397 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1398 DAG.getBasicBlock(CB.FalseBB)));
1402 /// visitJumpTable - Emit JumpTable node in the current MBB
1403 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1404 // Emit the code for the jump table
1405 assert(JT.Reg != -1U && "Should lower JT Header first!");
1406 MVT PTy = TLI.getPointerTy();
1407 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1409 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1410 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1411 MVT::Other, Index.getValue(1),
1415 /// visitJumpTableHeader - This function emits necessary code to produce index
1416 /// in the JumpTable from switch case.
1417 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1418 JumpTableHeader &JTH) {
1419 // Subtract the lowest switch case value from the value being switched on and
1420 // conditional branch to default mbb if the result is greater than the
1421 // difference between smallest and largest cases.
1422 SDValue SwitchOp = getValue(JTH.SValue);
1423 MVT VT = SwitchOp.getValueType();
1424 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1425 DAG.getConstant(JTH.First, VT));
1427 // The SDNode we just created, which holds the value being switched on minus
1428 // the the smallest case value, needs to be copied to a virtual register so it
1429 // can be used as an index into the jump table in a subsequent basic block.
1430 // This value may be smaller or larger than the target's pointer type, and
1431 // therefore require extension or truncating.
1432 if (VT.bitsGT(TLI.getPointerTy()))
1433 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1434 TLI.getPointerTy(), SUB);
1436 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1437 TLI.getPointerTy(), SUB);
1439 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1440 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1441 JumpTableReg, SwitchOp);
1442 JT.Reg = JumpTableReg;
1444 // Emit the range check for the jump table, and branch to the default block
1445 // for the switch statement if the value being switched on exceeds the largest
1446 // case in the switch.
1447 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1448 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1449 DAG.getConstant(JTH.Last-JTH.First,VT),
1452 // Set NextBlock to be the MBB immediately after the current one, if any.
1453 // This is used to avoid emitting unnecessary branches to the next block.
1454 MachineBasicBlock *NextBlock = 0;
1455 MachineFunction::iterator BBI = CurMBB;
1456 if (++BBI != CurMBB->getParent()->end())
1459 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1460 MVT::Other, CopyTo, CMP,
1461 DAG.getBasicBlock(JT.Default));
1463 if (JT.MBB == NextBlock)
1464 DAG.setRoot(BrCond);
1466 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1467 DAG.getBasicBlock(JT.MBB)));
1470 /// visitBitTestHeader - This function emits necessary code to produce value
1471 /// suitable for "bit tests"
1472 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1473 // Subtract the minimum value
1474 SDValue SwitchOp = getValue(B.SValue);
1475 MVT VT = SwitchOp.getValueType();
1476 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1477 DAG.getConstant(B.First, VT));
1480 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1481 TLI.getSetCCResultType(SUB.getValueType()),
1482 SUB, DAG.getConstant(B.Range, VT),
1486 if (VT.bitsGT(TLI.getPointerTy()))
1487 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1488 TLI.getPointerTy(), SUB);
1490 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1491 TLI.getPointerTy(), SUB);
1493 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1494 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1497 // Set NextBlock to be the MBB immediately after the current one, if any.
1498 // This is used to avoid emitting unnecessary branches to the next block.
1499 MachineBasicBlock *NextBlock = 0;
1500 MachineFunction::iterator BBI = CurMBB;
1501 if (++BBI != CurMBB->getParent()->end())
1504 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1506 CurMBB->addSuccessor(B.Default);
1507 CurMBB->addSuccessor(MBB);
1509 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1510 MVT::Other, CopyTo, RangeCmp,
1511 DAG.getBasicBlock(B.Default));
1513 if (MBB == NextBlock)
1514 DAG.setRoot(BrRange);
1516 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1517 DAG.getBasicBlock(MBB)));
1520 /// visitBitTestCase - this function produces one "bit test"
1521 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1524 // Make desired shift
1525 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1526 TLI.getPointerTy());
1527 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1529 DAG.getConstant(1, TLI.getPointerTy()),
1532 // Emit bit tests and jumps
1533 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1534 TLI.getPointerTy(), SwitchVal,
1535 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1536 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1537 TLI.getSetCCResultType(AndOp.getValueType()),
1538 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1541 CurMBB->addSuccessor(B.TargetBB);
1542 CurMBB->addSuccessor(NextMBB);
1544 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1545 MVT::Other, getControlRoot(),
1546 AndCmp, DAG.getBasicBlock(B.TargetBB));
1548 // Set NextBlock to be the MBB immediately after the current one, if any.
1549 // This is used to avoid emitting unnecessary branches to the next block.
1550 MachineBasicBlock *NextBlock = 0;
1551 MachineFunction::iterator BBI = CurMBB;
1552 if (++BBI != CurMBB->getParent()->end())
1555 if (NextMBB == NextBlock)
1558 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1559 DAG.getBasicBlock(NextMBB)));
1562 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1563 // Retrieve successors.
1564 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1565 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1567 const Value *Callee(I.getCalledValue());
1568 if (isa<InlineAsm>(Callee))
1571 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1573 // If the value of the invoke is used outside of its defining block, make it
1574 // available as a virtual register.
1575 if (!I.use_empty()) {
1576 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1577 if (VMI != FuncInfo.ValueMap.end())
1578 CopyValueToVirtualRegister(&I, VMI->second);
1581 // Update successor info
1582 CurMBB->addSuccessor(Return);
1583 CurMBB->addSuccessor(LandingPad);
1585 // Drop into normal successor.
1586 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1587 MVT::Other, getControlRoot(),
1588 DAG.getBasicBlock(Return)));
1591 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1594 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1595 /// small case ranges).
1596 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1597 CaseRecVector& WorkList,
1599 MachineBasicBlock* Default) {
1600 Case& BackCase = *(CR.Range.second-1);
1602 // Size is the number of Cases represented by this range.
1603 size_t Size = CR.Range.second - CR.Range.first;
1607 // Get the MachineFunction which holds the current MBB. This is used when
1608 // inserting any additional MBBs necessary to represent the switch.
1609 MachineFunction *CurMF = CurMBB->getParent();
1611 // Figure out which block is immediately after the current one.
1612 MachineBasicBlock *NextBlock = 0;
1613 MachineFunction::iterator BBI = CR.CaseBB;
1615 if (++BBI != CurMBB->getParent()->end())
1618 // TODO: If any two of the cases has the same destination, and if one value
1619 // is the same as the other, but has one bit unset that the other has set,
1620 // use bit manipulation to do two compares at once. For example:
1621 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1623 // Rearrange the case blocks so that the last one falls through if possible.
1624 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1625 // The last case block won't fall through into 'NextBlock' if we emit the
1626 // branches in this order. See if rearranging a case value would help.
1627 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1628 if (I->BB == NextBlock) {
1629 std::swap(*I, BackCase);
1635 // Create a CaseBlock record representing a conditional branch to
1636 // the Case's target mbb if the value being switched on SV is equal
1638 MachineBasicBlock *CurBlock = CR.CaseBB;
1639 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1640 MachineBasicBlock *FallThrough;
1642 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1643 CurMF->insert(BBI, FallThrough);
1645 // Put SV in a virtual register to make it available from the new blocks.
1646 ExportFromCurrentBlock(SV);
1648 // If the last case doesn't match, go to the default block.
1649 FallThrough = Default;
1652 Value *RHS, *LHS, *MHS;
1654 if (I->High == I->Low) {
1655 // This is just small small case range :) containing exactly 1 case
1657 LHS = SV; RHS = I->High; MHS = NULL;
1660 LHS = I->Low; MHS = SV; RHS = I->High;
1662 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1664 // If emitting the first comparison, just call visitSwitchCase to emit the
1665 // code into the current block. Otherwise, push the CaseBlock onto the
1666 // vector to be later processed by SDISel, and insert the node's MBB
1667 // before the next MBB.
1668 if (CurBlock == CurMBB)
1669 visitSwitchCase(CB);
1671 SwitchCases.push_back(CB);
1673 CurBlock = FallThrough;
1679 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1680 return !DisableJumpTables &&
1681 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1682 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1685 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1686 APInt LastExt(Last), FirstExt(First);
1687 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1688 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1689 return (LastExt - FirstExt + 1ULL);
1692 /// handleJTSwitchCase - Emit jumptable for current switch case range
1693 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1694 CaseRecVector& WorkList,
1696 MachineBasicBlock* Default) {
1697 Case& FrontCase = *CR.Range.first;
1698 Case& BackCase = *(CR.Range.second-1);
1700 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1701 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1704 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1708 if (!areJTsAllowed(TLI) || TSize <= 3)
1711 APInt Range = ComputeRange(First, Last);
1712 double Density = (double)TSize / Range.roundToDouble();
1716 DEBUG(errs() << "Lowering jump table\n"
1717 << "First entry: " << First << ". Last entry: " << Last << '\n'
1718 << "Range: " << Range
1719 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1721 // Get the MachineFunction which holds the current MBB. This is used when
1722 // inserting any additional MBBs necessary to represent the switch.
1723 MachineFunction *CurMF = CurMBB->getParent();
1725 // Figure out which block is immediately after the current one.
1726 MachineBasicBlock *NextBlock = 0;
1727 MachineFunction::iterator BBI = CR.CaseBB;
1729 if (++BBI != CurMBB->getParent()->end())
1732 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1734 // Create a new basic block to hold the code for loading the address
1735 // of the jump table, and jumping to it. Update successor information;
1736 // we will either branch to the default case for the switch, or the jump
1738 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1739 CurMF->insert(BBI, JumpTableBB);
1740 CR.CaseBB->addSuccessor(Default);
1741 CR.CaseBB->addSuccessor(JumpTableBB);
1743 // Build a vector of destination BBs, corresponding to each target
1744 // of the jump table. If the value of the jump table slot corresponds to
1745 // a case statement, push the case's BB onto the vector, otherwise, push
1747 std::vector<MachineBasicBlock*> DestBBs;
1749 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1750 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1751 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1753 if (Low.sle(TEI) && TEI.sle(High)) {
1754 DestBBs.push_back(I->BB);
1758 DestBBs.push_back(Default);
1762 // Update successor info. Add one edge to each unique successor.
1763 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1764 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1765 E = DestBBs.end(); I != E; ++I) {
1766 if (!SuccsHandled[(*I)->getNumber()]) {
1767 SuccsHandled[(*I)->getNumber()] = true;
1768 JumpTableBB->addSuccessor(*I);
1772 // Create a jump table index for this jump table, or return an existing
1774 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1776 // Set the jump table information so that we can codegen it as a second
1777 // MachineBasicBlock
1778 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1779 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1780 if (CR.CaseBB == CurMBB)
1781 visitJumpTableHeader(JT, JTH);
1783 JTCases.push_back(JumpTableBlock(JTH, JT));
1788 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1790 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1791 CaseRecVector& WorkList,
1793 MachineBasicBlock* Default) {
1794 // Get the MachineFunction which holds the current MBB. This is used when
1795 // inserting any additional MBBs necessary to represent the switch.
1796 MachineFunction *CurMF = CurMBB->getParent();
1798 // Figure out which block is immediately after the current one.
1799 MachineBasicBlock *NextBlock = 0;
1800 MachineFunction::iterator BBI = CR.CaseBB;
1802 if (++BBI != CurMBB->getParent()->end())
1805 Case& FrontCase = *CR.Range.first;
1806 Case& BackCase = *(CR.Range.second-1);
1807 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1809 // Size is the number of Cases represented by this range.
1810 unsigned Size = CR.Range.second - CR.Range.first;
1812 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1813 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1815 CaseItr Pivot = CR.Range.first + Size/2;
1817 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1818 // (heuristically) allow us to emit JumpTable's later.
1820 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1824 size_t LSize = FrontCase.size();
1825 size_t RSize = TSize-LSize;
1826 DEBUG(errs() << "Selecting best pivot: \n"
1827 << "First: " << First << ", Last: " << Last <<'\n'
1828 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1829 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1831 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1832 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1833 APInt Range = ComputeRange(LEnd, RBegin);
1834 assert((Range - 2ULL).isNonNegative() &&
1835 "Invalid case distance");
1836 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1837 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1838 double Metric = Range.logBase2()*(LDensity+RDensity);
1839 // Should always split in some non-trivial place
1840 DEBUG(errs() <<"=>Step\n"
1841 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1842 << "LDensity: " << LDensity
1843 << ", RDensity: " << RDensity << '\n'
1844 << "Metric: " << Metric << '\n');
1845 if (FMetric < Metric) {
1848 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1854 if (areJTsAllowed(TLI)) {
1855 // If our case is dense we *really* should handle it earlier!
1856 assert((FMetric > 0) && "Should handle dense range earlier!");
1858 Pivot = CR.Range.first + Size/2;
1861 CaseRange LHSR(CR.Range.first, Pivot);
1862 CaseRange RHSR(Pivot, CR.Range.second);
1863 Constant *C = Pivot->Low;
1864 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1866 // We know that we branch to the LHS if the Value being switched on is
1867 // less than the Pivot value, C. We use this to optimize our binary
1868 // tree a bit, by recognizing that if SV is greater than or equal to the
1869 // LHS's Case Value, and that Case Value is exactly one less than the
1870 // Pivot's Value, then we can branch directly to the LHS's Target,
1871 // rather than creating a leaf node for it.
1872 if ((LHSR.second - LHSR.first) == 1 &&
1873 LHSR.first->High == CR.GE &&
1874 cast<ConstantInt>(C)->getValue() ==
1875 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1876 TrueBB = LHSR.first->BB;
1878 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1879 CurMF->insert(BBI, TrueBB);
1880 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1882 // Put SV in a virtual register to make it available from the new blocks.
1883 ExportFromCurrentBlock(SV);
1886 // Similar to the optimization above, if the Value being switched on is
1887 // known to be less than the Constant CR.LT, and the current Case Value
1888 // is CR.LT - 1, then we can branch directly to the target block for
1889 // the current Case Value, rather than emitting a RHS leaf node for it.
1890 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1891 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1892 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1893 FalseBB = RHSR.first->BB;
1895 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1896 CurMF->insert(BBI, FalseBB);
1897 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1899 // Put SV in a virtual register to make it available from the new blocks.
1900 ExportFromCurrentBlock(SV);
1903 // Create a CaseBlock record representing a conditional branch to
1904 // the LHS node if the value being switched on SV is less than C.
1905 // Otherwise, branch to LHS.
1906 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1908 if (CR.CaseBB == CurMBB)
1909 visitSwitchCase(CB);
1911 SwitchCases.push_back(CB);
1916 /// handleBitTestsSwitchCase - if current case range has few destination and
1917 /// range span less, than machine word bitwidth, encode case range into series
1918 /// of masks and emit bit tests with these masks.
1919 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1920 CaseRecVector& WorkList,
1922 MachineBasicBlock* Default){
1923 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1925 Case& FrontCase = *CR.Range.first;
1926 Case& BackCase = *(CR.Range.second-1);
1928 // Get the MachineFunction which holds the current MBB. This is used when
1929 // inserting any additional MBBs necessary to represent the switch.
1930 MachineFunction *CurMF = CurMBB->getParent();
1933 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1935 // Single case counts one, case range - two.
1936 numCmps += (I->Low == I->High ? 1 : 2);
1939 // Count unique destinations
1940 SmallSet<MachineBasicBlock*, 4> Dests;
1941 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1942 Dests.insert(I->BB);
1943 if (Dests.size() > 3)
1944 // Don't bother the code below, if there are too much unique destinations
1947 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1948 << "Total number of comparisons: " << numCmps << '\n');
1950 // Compute span of values.
1951 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1952 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1953 APInt cmpRange = maxValue - minValue;
1955 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1956 << "Low bound: " << minValue << '\n'
1957 << "High bound: " << maxValue << '\n');
1959 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1960 (!(Dests.size() == 1 && numCmps >= 3) &&
1961 !(Dests.size() == 2 && numCmps >= 5) &&
1962 !(Dests.size() >= 3 && numCmps >= 6)))
1965 DEBUG(errs() << "Emitting bit tests\n");
1966 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1968 // Optimize the case where all the case values fit in a
1969 // word without having to subtract minValue. In this case,
1970 // we can optimize away the subtraction.
1971 if (minValue.isNonNegative() &&
1972 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1973 cmpRange = maxValue;
1975 lowBound = minValue;
1978 CaseBitsVector CasesBits;
1979 unsigned i, count = 0;
1981 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1982 MachineBasicBlock* Dest = I->BB;
1983 for (i = 0; i < count; ++i)
1984 if (Dest == CasesBits[i].BB)
1988 assert((count < 3) && "Too much destinations to test!");
1989 CasesBits.push_back(CaseBits(0, Dest, 0));
1993 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1994 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1996 uint64_t lo = (lowValue - lowBound).getZExtValue();
1997 uint64_t hi = (highValue - lowBound).getZExtValue();
1999 for (uint64_t j = lo; j <= hi; j++) {
2000 CasesBits[i].Mask |= 1ULL << j;
2001 CasesBits[i].Bits++;
2005 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2009 // Figure out which block is immediately after the current one.
2010 MachineFunction::iterator BBI = CR.CaseBB;
2013 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2015 DEBUG(errs() << "Cases:\n");
2016 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2017 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2018 << ", Bits: " << CasesBits[i].Bits
2019 << ", BB: " << CasesBits[i].BB << '\n');
2021 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2022 CurMF->insert(BBI, CaseBB);
2023 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2027 // Put SV in a virtual register to make it available from the new blocks.
2028 ExportFromCurrentBlock(SV);
2031 BitTestBlock BTB(lowBound, cmpRange, SV,
2032 -1U, (CR.CaseBB == CurMBB),
2033 CR.CaseBB, Default, BTC);
2035 if (CR.CaseBB == CurMBB)
2036 visitBitTestHeader(BTB);
2038 BitTestCases.push_back(BTB);
2044 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2045 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2046 const SwitchInst& SI) {
2049 // Start with "simple" cases
2050 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2051 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2052 Cases.push_back(Case(SI.getSuccessorValue(i),
2053 SI.getSuccessorValue(i),
2056 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2058 // Merge case into clusters
2059 if (Cases.size() >= 2)
2060 // Must recompute end() each iteration because it may be
2061 // invalidated by erase if we hold on to it
2062 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2063 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2064 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2065 MachineBasicBlock* nextBB = J->BB;
2066 MachineBasicBlock* currentBB = I->BB;
2068 // If the two neighboring cases go to the same destination, merge them
2069 // into a single case.
2070 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2078 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2079 if (I->Low != I->High)
2080 // A range counts double, since it requires two compares.
2087 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2088 // Figure out which block is immediately after the current one.
2089 MachineBasicBlock *NextBlock = 0;
2090 MachineFunction::iterator BBI = CurMBB;
2092 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2094 // If there is only the default destination, branch to it if it is not the
2095 // next basic block. Otherwise, just fall through.
2096 if (SI.getNumOperands() == 2) {
2097 // Update machine-CFG edges.
2099 // If this is not a fall-through branch, emit the branch.
2100 CurMBB->addSuccessor(Default);
2101 if (Default != NextBlock)
2102 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2103 MVT::Other, getControlRoot(),
2104 DAG.getBasicBlock(Default)));
2108 // If there are any non-default case statements, create a vector of Cases
2109 // representing each one, and sort the vector so that we can efficiently
2110 // create a binary search tree from them.
2112 size_t numCmps = Clusterify(Cases, SI);
2113 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2114 << ". Total compares: " << numCmps << '\n');
2117 // Get the Value to be switched on and default basic blocks, which will be
2118 // inserted into CaseBlock records, representing basic blocks in the binary
2120 Value *SV = SI.getOperand(0);
2122 // Push the initial CaseRec onto the worklist
2123 CaseRecVector WorkList;
2124 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2126 while (!WorkList.empty()) {
2127 // Grab a record representing a case range to process off the worklist
2128 CaseRec CR = WorkList.back();
2129 WorkList.pop_back();
2131 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2134 // If the range has few cases (two or less) emit a series of specific
2136 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2139 // If the switch has more than 5 blocks, and at least 40% dense, and the
2140 // target supports indirect branches, then emit a jump table rather than
2141 // lowering the switch to a binary tree of conditional branches.
2142 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2145 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2146 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2147 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2152 void SelectionDAGLowering::visitSub(User &I) {
2153 // -0.0 - X --> fneg
2154 const Type *Ty = I.getType();
2155 if (isa<VectorType>(Ty)) {
2156 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2157 const VectorType *DestTy = cast<VectorType>(I.getType());
2158 const Type *ElTy = DestTy->getElementType();
2159 if (ElTy->isFloatingPoint()) {
2160 unsigned VL = DestTy->getNumElements();
2161 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2162 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2164 SDValue Op2 = getValue(I.getOperand(1));
2165 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2166 Op2.getValueType(), Op2));
2172 if (Ty->isFloatingPoint()) {
2173 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2174 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2175 SDValue Op2 = getValue(I.getOperand(1));
2176 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2177 Op2.getValueType(), Op2));
2182 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2185 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2186 SDValue Op1 = getValue(I.getOperand(0));
2187 SDValue Op2 = getValue(I.getOperand(1));
2189 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2190 Op1.getValueType(), Op1, Op2));
2193 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2194 SDValue Op1 = getValue(I.getOperand(0));
2195 SDValue Op2 = getValue(I.getOperand(1));
2196 if (!isa<VectorType>(I.getType()) &&
2197 Op2.getValueType() != TLI.getShiftAmountTy()) {
2198 // If the operand is smaller than the shift count type, promote it.
2199 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2200 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2201 TLI.getShiftAmountTy(), Op2);
2202 // If the operand is larger than the shift count type but the shift
2203 // count type has enough bits to represent any shift value, truncate
2204 // it now. This is a common case and it exposes the truncate to
2205 // optimization early.
2206 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2207 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2208 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2209 TLI.getShiftAmountTy(), Op2);
2210 // Otherwise we'll need to temporarily settle for some other
2211 // convenient type; type legalization will make adjustments as
2213 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2214 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2215 TLI.getPointerTy(), Op2);
2216 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2217 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2218 TLI.getPointerTy(), Op2);
2221 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2222 Op1.getValueType(), Op1, Op2));
2225 void SelectionDAGLowering::visitICmp(User &I) {
2226 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2227 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2228 predicate = IC->getPredicate();
2229 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2230 predicate = ICmpInst::Predicate(IC->getPredicate());
2231 SDValue Op1 = getValue(I.getOperand(0));
2232 SDValue Op2 = getValue(I.getOperand(1));
2233 ISD::CondCode Opcode = getICmpCondCode(predicate);
2234 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2237 void SelectionDAGLowering::visitFCmp(User &I) {
2238 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2239 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2240 predicate = FC->getPredicate();
2241 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2242 predicate = FCmpInst::Predicate(FC->getPredicate());
2243 SDValue Op1 = getValue(I.getOperand(0));
2244 SDValue Op2 = getValue(I.getOperand(1));
2245 ISD::CondCode Condition = getFCmpCondCode(predicate);
2246 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2249 void SelectionDAGLowering::visitVICmp(User &I) {
2250 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2251 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2252 predicate = IC->getPredicate();
2253 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2254 predicate = ICmpInst::Predicate(IC->getPredicate());
2255 SDValue Op1 = getValue(I.getOperand(0));
2256 SDValue Op2 = getValue(I.getOperand(1));
2257 ISD::CondCode Opcode = getICmpCondCode(predicate);
2258 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2262 void SelectionDAGLowering::visitVFCmp(User &I) {
2263 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2264 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2265 predicate = FC->getPredicate();
2266 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2267 predicate = FCmpInst::Predicate(FC->getPredicate());
2268 SDValue Op1 = getValue(I.getOperand(0));
2269 SDValue Op2 = getValue(I.getOperand(1));
2270 ISD::CondCode Condition = getFCmpCondCode(predicate);
2271 MVT DestVT = TLI.getValueType(I.getType());
2273 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2276 void SelectionDAGLowering::visitSelect(User &I) {
2277 SmallVector<MVT, 4> ValueVTs;
2278 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2279 unsigned NumValues = ValueVTs.size();
2280 if (NumValues != 0) {
2281 SmallVector<SDValue, 4> Values(NumValues);
2282 SDValue Cond = getValue(I.getOperand(0));
2283 SDValue TrueVal = getValue(I.getOperand(1));
2284 SDValue FalseVal = getValue(I.getOperand(2));
2286 for (unsigned i = 0; i != NumValues; ++i)
2287 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2288 TrueVal.getValueType(), Cond,
2289 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2290 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2292 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2293 DAG.getVTList(&ValueVTs[0], NumValues),
2294 &Values[0], NumValues));
2299 void SelectionDAGLowering::visitTrunc(User &I) {
2300 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2301 SDValue N = getValue(I.getOperand(0));
2302 MVT DestVT = TLI.getValueType(I.getType());
2303 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2306 void SelectionDAGLowering::visitZExt(User &I) {
2307 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2308 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2309 SDValue N = getValue(I.getOperand(0));
2310 MVT DestVT = TLI.getValueType(I.getType());
2311 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2314 void SelectionDAGLowering::visitSExt(User &I) {
2315 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2316 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2317 SDValue N = getValue(I.getOperand(0));
2318 MVT DestVT = TLI.getValueType(I.getType());
2319 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2322 void SelectionDAGLowering::visitFPTrunc(User &I) {
2323 // FPTrunc is never a no-op cast, no need to check
2324 SDValue N = getValue(I.getOperand(0));
2325 MVT DestVT = TLI.getValueType(I.getType());
2326 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2327 DestVT, N, DAG.getIntPtrConstant(0)));
2330 void SelectionDAGLowering::visitFPExt(User &I){
2331 // FPTrunc is never a no-op cast, no need to check
2332 SDValue N = getValue(I.getOperand(0));
2333 MVT DestVT = TLI.getValueType(I.getType());
2334 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2337 void SelectionDAGLowering::visitFPToUI(User &I) {
2338 // FPToUI is never a no-op cast, no need to check
2339 SDValue N = getValue(I.getOperand(0));
2340 MVT DestVT = TLI.getValueType(I.getType());
2341 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2344 void SelectionDAGLowering::visitFPToSI(User &I) {
2345 // FPToSI is never a no-op cast, no need to check
2346 SDValue N = getValue(I.getOperand(0));
2347 MVT DestVT = TLI.getValueType(I.getType());
2348 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2351 void SelectionDAGLowering::visitUIToFP(User &I) {
2352 // UIToFP is never a no-op cast, no need to check
2353 SDValue N = getValue(I.getOperand(0));
2354 MVT DestVT = TLI.getValueType(I.getType());
2355 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2358 void SelectionDAGLowering::visitSIToFP(User &I){
2359 // SIToFP is never a no-op cast, no need to check
2360 SDValue N = getValue(I.getOperand(0));
2361 MVT DestVT = TLI.getValueType(I.getType());
2362 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2365 void SelectionDAGLowering::visitPtrToInt(User &I) {
2366 // What to do depends on the size of the integer and the size of the pointer.
2367 // We can either truncate, zero extend, or no-op, accordingly.
2368 SDValue N = getValue(I.getOperand(0));
2369 MVT SrcVT = N.getValueType();
2370 MVT DestVT = TLI.getValueType(I.getType());
2372 if (DestVT.bitsLT(SrcVT))
2373 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2375 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2376 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2377 setValue(&I, Result);
2380 void SelectionDAGLowering::visitIntToPtr(User &I) {
2381 // What to do depends on the size of the integer and the size of the pointer.
2382 // We can either truncate, zero extend, or no-op, accordingly.
2383 SDValue N = getValue(I.getOperand(0));
2384 MVT SrcVT = N.getValueType();
2385 MVT DestVT = TLI.getValueType(I.getType());
2386 if (DestVT.bitsLT(SrcVT))
2387 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2389 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2390 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2394 void SelectionDAGLowering::visitBitCast(User &I) {
2395 SDValue N = getValue(I.getOperand(0));
2396 MVT DestVT = TLI.getValueType(I.getType());
2398 // BitCast assures us that source and destination are the same size so this
2399 // is either a BIT_CONVERT or a no-op.
2400 if (DestVT != N.getValueType())
2401 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2402 DestVT, N)); // convert types
2404 setValue(&I, N); // noop cast.
2407 void SelectionDAGLowering::visitInsertElement(User &I) {
2408 SDValue InVec = getValue(I.getOperand(0));
2409 SDValue InVal = getValue(I.getOperand(1));
2410 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2412 getValue(I.getOperand(2)));
2414 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2415 TLI.getValueType(I.getType()),
2416 InVec, InVal, InIdx));
2419 void SelectionDAGLowering::visitExtractElement(User &I) {
2420 SDValue InVec = getValue(I.getOperand(0));
2421 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2423 getValue(I.getOperand(1)));
2424 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2425 TLI.getValueType(I.getType()), InVec, InIdx));
2429 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2430 // from SIndx and increasing to the element length (undefs are allowed).
2431 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2432 unsigned MaskNumElts = Mask.getNumOperands();
2433 for (unsigned i = 0; i != MaskNumElts; ++i) {
2434 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2435 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2436 if (Idx != i + SIndx)
2443 void SelectionDAGLowering::visitShuffleVector(User &I) {
2444 SDValue Src1 = getValue(I.getOperand(0));
2445 SDValue Src2 = getValue(I.getOperand(1));
2446 SDValue Mask = getValue(I.getOperand(2));
2448 MVT VT = TLI.getValueType(I.getType());
2449 MVT SrcVT = Src1.getValueType();
2450 int MaskNumElts = Mask.getNumOperands();
2451 int SrcNumElts = SrcVT.getVectorNumElements();
2453 if (SrcNumElts == MaskNumElts) {
2454 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2455 VT, Src1, Src2, Mask));
2459 // Normalize the shuffle vector since mask and vector length don't match.
2460 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2462 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2463 // Mask is longer than the source vectors and is a multiple of the source
2464 // vectors. We can use concatenate vector to make the mask and vectors
2466 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2467 // The shuffle is concatenating two vectors together.
2468 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2473 // Pad both vectors with undefs to make them the same length as the mask.
2474 unsigned NumConcat = MaskNumElts / SrcNumElts;
2475 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2477 SDValue* MOps1 = new SDValue[NumConcat];
2478 SDValue* MOps2 = new SDValue[NumConcat];
2481 for (unsigned i = 1; i != NumConcat; ++i) {
2482 MOps1[i] = UndefVal;
2483 MOps2[i] = UndefVal;
2485 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2486 VT, MOps1, NumConcat);
2487 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2488 VT, MOps2, NumConcat);
2493 // Readjust mask for new input vector length.
2494 SmallVector<SDValue, 8> MappedOps;
2495 for (int i = 0; i != MaskNumElts; ++i) {
2496 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2497 MappedOps.push_back(Mask.getOperand(i));
2499 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2500 if (Idx < SrcNumElts)
2501 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2503 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2507 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2508 Mask.getValueType(),
2509 &MappedOps[0], MappedOps.size());
2511 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2512 VT, Src1, Src2, Mask));
2516 if (SrcNumElts > MaskNumElts) {
2517 // Resulting vector is shorter than the incoming vector.
2518 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2519 // Shuffle extracts 1st vector.
2524 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2525 // Shuffle extracts 2nd vector.
2530 // Analyze the access pattern of the vector to see if we can extract
2531 // two subvectors and do the shuffle. The analysis is done by calculating
2532 // the range of elements the mask access on both vectors.
2533 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2534 int MaxRange[2] = {-1, -1};
2536 for (int i = 0; i != MaskNumElts; ++i) {
2537 SDValue Arg = Mask.getOperand(i);
2538 if (Arg.getOpcode() != ISD::UNDEF) {
2539 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2540 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2542 if (Idx >= SrcNumElts) {
2546 if (Idx > MaxRange[Input])
2547 MaxRange[Input] = Idx;
2548 if (Idx < MinRange[Input])
2549 MinRange[Input] = Idx;
2553 // Check if the access is smaller than the vector size and can we find
2554 // a reasonable extract index.
2555 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2556 int StartIdx[2]; // StartIdx to extract from
2557 for (int Input=0; Input < 2; ++Input) {
2558 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2559 RangeUse[Input] = 0; // Unused
2560 StartIdx[Input] = 0;
2561 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2562 // Fits within range but we should see if we can find a good
2563 // start index that is a multiple of the mask length.
2564 if (MaxRange[Input] < MaskNumElts) {
2565 RangeUse[Input] = 1; // Extract from beginning of the vector
2566 StartIdx[Input] = 0;
2568 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2569 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2570 StartIdx[Input] + MaskNumElts < SrcNumElts)
2571 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2576 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2577 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2580 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2581 // Extract appropriate subvector and generate a vector shuffle
2582 for (int Input=0; Input < 2; ++Input) {
2583 SDValue& Src = Input == 0 ? Src1 : Src2;
2584 if (RangeUse[Input] == 0) {
2585 Src = DAG.getUNDEF(VT);
2587 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2588 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2591 // Calculate new mask.
2592 SmallVector<SDValue, 8> MappedOps;
2593 for (int i = 0; i != MaskNumElts; ++i) {
2594 SDValue Arg = Mask.getOperand(i);
2595 if (Arg.getOpcode() == ISD::UNDEF) {
2596 MappedOps.push_back(Arg);
2598 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2599 if (Idx < SrcNumElts)
2600 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2602 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2603 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2607 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2608 Mask.getValueType(),
2609 &MappedOps[0], MappedOps.size());
2610 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2611 VT, Src1, Src2, Mask));
2616 // We can't use either concat vectors or extract subvectors so fall back to
2617 // replacing the shuffle with extract and build vector.
2618 // to insert and build vector.
2619 MVT EltVT = VT.getVectorElementType();
2620 MVT PtrVT = TLI.getPointerTy();
2621 SmallVector<SDValue,8> Ops;
2622 for (int i = 0; i != MaskNumElts; ++i) {
2623 SDValue Arg = Mask.getOperand(i);
2624 if (Arg.getOpcode() == ISD::UNDEF) {
2625 Ops.push_back(DAG.getUNDEF(EltVT));
2627 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2628 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2629 if (Idx < SrcNumElts)
2630 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2631 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2633 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2635 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2638 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2639 VT, &Ops[0], Ops.size()));
2642 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2643 const Value *Op0 = I.getOperand(0);
2644 const Value *Op1 = I.getOperand(1);
2645 const Type *AggTy = I.getType();
2646 const Type *ValTy = Op1->getType();
2647 bool IntoUndef = isa<UndefValue>(Op0);
2648 bool FromUndef = isa<UndefValue>(Op1);
2650 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2651 I.idx_begin(), I.idx_end());
2653 SmallVector<MVT, 4> AggValueVTs;
2654 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2655 SmallVector<MVT, 4> ValValueVTs;
2656 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2658 unsigned NumAggValues = AggValueVTs.size();
2659 unsigned NumValValues = ValValueVTs.size();
2660 SmallVector<SDValue, 4> Values(NumAggValues);
2662 SDValue Agg = getValue(Op0);
2663 SDValue Val = getValue(Op1);
2665 // Copy the beginning value(s) from the original aggregate.
2666 for (; i != LinearIndex; ++i)
2667 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2668 SDValue(Agg.getNode(), Agg.getResNo() + i);
2669 // Copy values from the inserted value(s).
2670 for (; i != LinearIndex + NumValValues; ++i)
2671 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2672 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2673 // Copy remaining value(s) from the original aggregate.
2674 for (; i != NumAggValues; ++i)
2675 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2676 SDValue(Agg.getNode(), Agg.getResNo() + i);
2678 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2679 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2680 &Values[0], NumAggValues));
2683 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2684 const Value *Op0 = I.getOperand(0);
2685 const Type *AggTy = Op0->getType();
2686 const Type *ValTy = I.getType();
2687 bool OutOfUndef = isa<UndefValue>(Op0);
2689 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2690 I.idx_begin(), I.idx_end());
2692 SmallVector<MVT, 4> ValValueVTs;
2693 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2695 unsigned NumValValues = ValValueVTs.size();
2696 SmallVector<SDValue, 4> Values(NumValValues);
2698 SDValue Agg = getValue(Op0);
2699 // Copy out the selected value(s).
2700 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2701 Values[i - LinearIndex] =
2703 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2704 SDValue(Agg.getNode(), Agg.getResNo() + i);
2706 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2707 DAG.getVTList(&ValValueVTs[0], NumValValues),
2708 &Values[0], NumValValues));
2712 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2713 SDValue N = getValue(I.getOperand(0));
2714 const Type *Ty = I.getOperand(0)->getType();
2716 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2719 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2720 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2723 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2724 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2725 DAG.getIntPtrConstant(Offset));
2727 Ty = StTy->getElementType(Field);
2729 Ty = cast<SequentialType>(Ty)->getElementType();
2731 // If this is a constant subscript, handle it quickly.
2732 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2733 if (CI->getZExtValue() == 0) continue;
2735 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2737 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2739 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2741 DAG.getConstant(Offs, MVT::i64));
2743 OffsVal = DAG.getIntPtrConstant(Offs);
2744 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2749 // N = N + Idx * ElementSize;
2750 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2751 SDValue IdxN = getValue(Idx);
2753 // If the index is smaller or larger than intptr_t, truncate or extend
2755 if (IdxN.getValueType().bitsLT(N.getValueType()))
2756 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2757 N.getValueType(), IdxN);
2758 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2759 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2760 N.getValueType(), IdxN);
2762 // If this is a multiply by a power of two, turn it into a shl
2763 // immediately. This is a very common case.
2764 if (ElementSize != 1) {
2765 if (isPowerOf2_64(ElementSize)) {
2766 unsigned Amt = Log2_64(ElementSize);
2767 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2768 N.getValueType(), IdxN,
2769 DAG.getConstant(Amt, TLI.getPointerTy()));
2771 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2772 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2773 N.getValueType(), IdxN, Scale);
2777 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2778 N.getValueType(), N, IdxN);
2784 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2785 // If this is a fixed sized alloca in the entry block of the function,
2786 // allocate it statically on the stack.
2787 if (FuncInfo.StaticAllocaMap.count(&I))
2788 return; // getValue will auto-populate this.
2790 const Type *Ty = I.getAllocatedType();
2791 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2793 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2796 SDValue AllocSize = getValue(I.getArraySize());
2798 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2800 DAG.getConstant(TySize, AllocSize.getValueType()));
2804 MVT IntPtr = TLI.getPointerTy();
2805 if (IntPtr.bitsLT(AllocSize.getValueType()))
2806 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2808 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2809 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2812 // Handle alignment. If the requested alignment is less than or equal to
2813 // the stack alignment, ignore it. If the size is greater than or equal to
2814 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2815 unsigned StackAlign =
2816 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2817 if (Align <= StackAlign)
2820 // Round the size of the allocation up to the stack alignment size
2821 // by add SA-1 to the size.
2822 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2823 AllocSize.getValueType(), AllocSize,
2824 DAG.getIntPtrConstant(StackAlign-1));
2825 // Mask out the low bits for alignment purposes.
2826 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2827 AllocSize.getValueType(), AllocSize,
2828 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2830 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2831 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2832 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2835 DAG.setRoot(DSA.getValue(1));
2837 // Inform the Frame Information that we have just allocated a variable-sized
2839 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2842 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2843 const Value *SV = I.getOperand(0);
2844 SDValue Ptr = getValue(SV);
2846 const Type *Ty = I.getType();
2847 bool isVolatile = I.isVolatile();
2848 unsigned Alignment = I.getAlignment();
2850 SmallVector<MVT, 4> ValueVTs;
2851 SmallVector<uint64_t, 4> Offsets;
2852 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2853 unsigned NumValues = ValueVTs.size();
2858 bool ConstantMemory = false;
2860 // Serialize volatile loads with other side effects.
2862 else if (AA->pointsToConstantMemory(SV)) {
2863 // Do not serialize (non-volatile) loads of constant memory with anything.
2864 Root = DAG.getEntryNode();
2865 ConstantMemory = true;
2867 // Do not serialize non-volatile loads against each other.
2868 Root = DAG.getRoot();
2871 SmallVector<SDValue, 4> Values(NumValues);
2872 SmallVector<SDValue, 4> Chains(NumValues);
2873 MVT PtrVT = Ptr.getValueType();
2874 for (unsigned i = 0; i != NumValues; ++i) {
2875 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2876 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2878 DAG.getConstant(Offsets[i], PtrVT)),
2880 isVolatile, Alignment);
2882 Chains[i] = L.getValue(1);
2885 if (!ConstantMemory) {
2886 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2888 &Chains[0], NumValues);
2892 PendingLoads.push_back(Chain);
2895 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2896 DAG.getVTList(&ValueVTs[0], NumValues),
2897 &Values[0], NumValues));
2901 void SelectionDAGLowering::visitStore(StoreInst &I) {
2902 Value *SrcV = I.getOperand(0);
2903 Value *PtrV = I.getOperand(1);
2905 SmallVector<MVT, 4> ValueVTs;
2906 SmallVector<uint64_t, 4> Offsets;
2907 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2908 unsigned NumValues = ValueVTs.size();
2912 // Get the lowered operands. Note that we do this after
2913 // checking if NumResults is zero, because with zero results
2914 // the operands won't have values in the map.
2915 SDValue Src = getValue(SrcV);
2916 SDValue Ptr = getValue(PtrV);
2918 SDValue Root = getRoot();
2919 SmallVector<SDValue, 4> Chains(NumValues);
2920 MVT PtrVT = Ptr.getValueType();
2921 bool isVolatile = I.isVolatile();
2922 unsigned Alignment = I.getAlignment();
2923 for (unsigned i = 0; i != NumValues; ++i)
2924 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2925 SDValue(Src.getNode(), Src.getResNo() + i),
2926 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2928 DAG.getConstant(Offsets[i], PtrVT)),
2930 isVolatile, Alignment);
2932 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2933 MVT::Other, &Chains[0], NumValues));
2936 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2938 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2939 unsigned Intrinsic) {
2940 bool HasChain = !I.doesNotAccessMemory();
2941 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2943 // Build the operand list.
2944 SmallVector<SDValue, 8> Ops;
2945 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2947 // We don't need to serialize loads against other loads.
2948 Ops.push_back(DAG.getRoot());
2950 Ops.push_back(getRoot());
2954 // Info is set by getTgtMemInstrinsic
2955 TargetLowering::IntrinsicInfo Info;
2956 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2958 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2959 if (!IsTgtIntrinsic)
2960 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2962 // Add all operands of the call to the operand list.
2963 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2964 SDValue Op = getValue(I.getOperand(i));
2965 assert(TLI.isTypeLegal(Op.getValueType()) &&
2966 "Intrinsic uses a non-legal type?");
2970 std::vector<MVT> VTArray;
2971 if (I.getType() != Type::VoidTy) {
2972 MVT VT = TLI.getValueType(I.getType());
2973 if (VT.isVector()) {
2974 const VectorType *DestTy = cast<VectorType>(I.getType());
2975 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2977 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2978 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2981 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2982 VTArray.push_back(VT);
2985 VTArray.push_back(MVT::Other);
2987 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2991 if (IsTgtIntrinsic) {
2992 // This is target intrinsic that touches memory
2993 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2994 VTs, &Ops[0], Ops.size(),
2995 Info.memVT, Info.ptrVal, Info.offset,
2996 Info.align, Info.vol,
2997 Info.readMem, Info.writeMem);
3000 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3001 VTs, &Ops[0], Ops.size());
3002 else if (I.getType() != Type::VoidTy)
3003 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3004 VTs, &Ops[0], Ops.size());
3006 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3007 VTs, &Ops[0], Ops.size());
3010 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3012 PendingLoads.push_back(Chain);
3016 if (I.getType() != Type::VoidTy) {
3017 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3018 MVT VT = TLI.getValueType(PTy);
3019 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3021 setValue(&I, Result);
3025 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3026 static GlobalVariable *ExtractTypeInfo(Value *V) {
3027 V = V->stripPointerCasts();
3028 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3029 assert ((GV || isa<ConstantPointerNull>(V)) &&
3030 "TypeInfo must be a global variable or NULL");
3036 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3037 /// call, and add them to the specified machine basic block.
3038 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3039 MachineBasicBlock *MBB) {
3040 // Inform the MachineModuleInfo of the personality for this landing pad.
3041 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3042 assert(CE->getOpcode() == Instruction::BitCast &&
3043 isa<Function>(CE->getOperand(0)) &&
3044 "Personality should be a function");
3045 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3047 // Gather all the type infos for this landing pad and pass them along to
3048 // MachineModuleInfo.
3049 std::vector<GlobalVariable *> TyInfo;
3050 unsigned N = I.getNumOperands();
3052 for (unsigned i = N - 1; i > 2; --i) {
3053 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3054 unsigned FilterLength = CI->getZExtValue();
3055 unsigned FirstCatch = i + FilterLength + !FilterLength;
3056 assert (FirstCatch <= N && "Invalid filter length");
3058 if (FirstCatch < N) {
3059 TyInfo.reserve(N - FirstCatch);
3060 for (unsigned j = FirstCatch; j < N; ++j)
3061 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3062 MMI->addCatchTypeInfo(MBB, TyInfo);
3066 if (!FilterLength) {
3068 MMI->addCleanup(MBB);
3071 TyInfo.reserve(FilterLength - 1);
3072 for (unsigned j = i + 1; j < FirstCatch; ++j)
3073 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3074 MMI->addFilterTypeInfo(MBB, TyInfo);
3083 TyInfo.reserve(N - 3);
3084 for (unsigned j = 3; j < N; ++j)
3085 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3086 MMI->addCatchTypeInfo(MBB, TyInfo);
3092 /// GetSignificand - Get the significand and build it into a floating-point
3093 /// number with exponent of 1:
3095 /// Op = (Op & 0x007fffff) | 0x3f800000;
3097 /// where Op is the hexidecimal representation of floating point value.
3099 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3100 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3101 DAG.getConstant(0x007fffff, MVT::i32));
3102 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3103 DAG.getConstant(0x3f800000, MVT::i32));
3104 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3107 /// GetExponent - Get the exponent:
3109 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3111 /// where Op is the hexidecimal representation of floating point value.
3113 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3115 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3116 DAG.getConstant(0x7f800000, MVT::i32));
3117 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3118 DAG.getConstant(23, TLI.getPointerTy()));
3119 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3120 DAG.getConstant(127, MVT::i32));
3121 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3124 /// getF32Constant - Get 32-bit floating point constant.
3126 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3127 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3130 /// Inlined utility function to implement binary input atomic intrinsics for
3131 /// visitIntrinsicCall: I is a call instruction
3132 /// Op is the associated NodeType for I
3134 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3135 SDValue Root = getRoot();
3137 DAG.getAtomic(Op, getCurDebugLoc(),
3138 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3140 getValue(I.getOperand(1)),
3141 getValue(I.getOperand(2)),
3144 DAG.setRoot(L.getValue(1));
3148 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3150 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3151 SDValue Op1 = getValue(I.getOperand(1));
3152 SDValue Op2 = getValue(I.getOperand(2));
3154 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3155 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3157 setValue(&I, Result);
3161 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3162 /// limited-precision mode.
3164 SelectionDAGLowering::visitExp(CallInst &I) {
3166 DebugLoc dl = getCurDebugLoc();
3168 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3169 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3170 SDValue Op = getValue(I.getOperand(1));
3172 // Put the exponent in the right bit position for later addition to the
3175 // #define LOG2OFe 1.4426950f
3176 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3177 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3178 getF32Constant(DAG, 0x3fb8aa3b));
3179 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3181 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3182 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3183 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3185 // IntegerPartOfX <<= 23;
3186 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3187 DAG.getConstant(23, TLI.getPointerTy()));
3189 if (LimitFloatPrecision <= 6) {
3190 // For floating-point precision of 6:
3192 // TwoToFractionalPartOfX =
3194 // (0.735607626f + 0.252464424f * x) * x;
3196 // error 0.0144103317, which is 6 bits
3197 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3198 getF32Constant(DAG, 0x3e814304));
3199 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3200 getF32Constant(DAG, 0x3f3c50c8));
3201 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3202 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3203 getF32Constant(DAG, 0x3f7f5e7e));
3204 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3206 // Add the exponent into the result in integer domain.
3207 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3208 TwoToFracPartOfX, IntegerPartOfX);
3210 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3211 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3212 // For floating-point precision of 12:
3214 // TwoToFractionalPartOfX =
3217 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3219 // 0.000107046256 error, which is 13 to 14 bits
3220 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3221 getF32Constant(DAG, 0x3da235e3));
3222 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3223 getF32Constant(DAG, 0x3e65b8f3));
3224 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3225 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3226 getF32Constant(DAG, 0x3f324b07));
3227 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3228 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3229 getF32Constant(DAG, 0x3f7ff8fd));
3230 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3232 // Add the exponent into the result in integer domain.
3233 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3234 TwoToFracPartOfX, IntegerPartOfX);
3236 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3237 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3238 // For floating-point precision of 18:
3240 // TwoToFractionalPartOfX =
3244 // (0.554906021e-1f +
3245 // (0.961591928e-2f +
3246 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3248 // error 2.47208000*10^(-7), which is better than 18 bits
3249 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3250 getF32Constant(DAG, 0x3924b03e));
3251 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3252 getF32Constant(DAG, 0x3ab24b87));
3253 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3254 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3255 getF32Constant(DAG, 0x3c1d8c17));
3256 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3257 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3258 getF32Constant(DAG, 0x3d634a1d));
3259 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3260 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3261 getF32Constant(DAG, 0x3e75fe14));
3262 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3263 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3264 getF32Constant(DAG, 0x3f317234));
3265 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3266 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3267 getF32Constant(DAG, 0x3f800000));
3268 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3271 // Add the exponent into the result in integer domain.
3272 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3273 TwoToFracPartOfX, IntegerPartOfX);
3275 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3278 // No special expansion.
3279 result = DAG.getNode(ISD::FEXP, dl,
3280 getValue(I.getOperand(1)).getValueType(),
3281 getValue(I.getOperand(1)));
3284 setValue(&I, result);
3287 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3288 /// limited-precision mode.
3290 SelectionDAGLowering::visitLog(CallInst &I) {
3292 DebugLoc dl = getCurDebugLoc();
3294 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3295 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3296 SDValue Op = getValue(I.getOperand(1));
3297 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3299 // Scale the exponent by log(2) [0.69314718f].
3300 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3301 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3302 getF32Constant(DAG, 0x3f317218));
3304 // Get the significand and build it into a floating-point number with
3306 SDValue X = GetSignificand(DAG, Op1, dl);
3308 if (LimitFloatPrecision <= 6) {
3309 // For floating-point precision of 6:
3313 // (1.4034025f - 0.23903021f * x) * x;
3315 // error 0.0034276066, which is better than 8 bits
3316 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3317 getF32Constant(DAG, 0xbe74c456));
3318 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3319 getF32Constant(DAG, 0x3fb3a2b1));
3320 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3321 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3322 getF32Constant(DAG, 0x3f949a29));
3324 result = DAG.getNode(ISD::FADD, dl,
3325 MVT::f32, LogOfExponent, LogOfMantissa);
3326 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3327 // For floating-point precision of 12:
3333 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3335 // error 0.000061011436, which is 14 bits
3336 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3337 getF32Constant(DAG, 0xbd67b6d6));
3338 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3339 getF32Constant(DAG, 0x3ee4f4b8));
3340 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3341 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3342 getF32Constant(DAG, 0x3fbc278b));
3343 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3344 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3345 getF32Constant(DAG, 0x40348e95));
3346 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3347 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3348 getF32Constant(DAG, 0x3fdef31a));
3350 result = DAG.getNode(ISD::FADD, dl,
3351 MVT::f32, LogOfExponent, LogOfMantissa);
3352 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3353 // For floating-point precision of 18:
3361 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3363 // error 0.0000023660568, which is better than 18 bits
3364 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3365 getF32Constant(DAG, 0xbc91e5ac));
3366 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3367 getF32Constant(DAG, 0x3e4350aa));
3368 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3369 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3370 getF32Constant(DAG, 0x3f60d3e3));
3371 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3372 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3373 getF32Constant(DAG, 0x4011cdf0));
3374 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3375 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3376 getF32Constant(DAG, 0x406cfd1c));
3377 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3378 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3379 getF32Constant(DAG, 0x408797cb));
3380 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3381 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3382 getF32Constant(DAG, 0x4006dcab));
3384 result = DAG.getNode(ISD::FADD, dl,
3385 MVT::f32, LogOfExponent, LogOfMantissa);
3388 // No special expansion.
3389 result = DAG.getNode(ISD::FLOG, dl,
3390 getValue(I.getOperand(1)).getValueType(),
3391 getValue(I.getOperand(1)));
3394 setValue(&I, result);
3397 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3398 /// limited-precision mode.
3400 SelectionDAGLowering::visitLog2(CallInst &I) {
3402 DebugLoc dl = getCurDebugLoc();
3404 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3405 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3406 SDValue Op = getValue(I.getOperand(1));
3407 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3409 // Get the exponent.
3410 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3412 // Get the significand and build it into a floating-point number with
3414 SDValue X = GetSignificand(DAG, Op1, dl);
3416 // Different possible minimax approximations of significand in
3417 // floating-point for various degrees of accuracy over [1,2].
3418 if (LimitFloatPrecision <= 6) {
3419 // For floating-point precision of 6:
3421 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3423 // error 0.0049451742, which is more than 7 bits
3424 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3425 getF32Constant(DAG, 0xbeb08fe0));
3426 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3427 getF32Constant(DAG, 0x40019463));
3428 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3429 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3430 getF32Constant(DAG, 0x3fd6633d));
3432 result = DAG.getNode(ISD::FADD, dl,
3433 MVT::f32, LogOfExponent, Log2ofMantissa);
3434 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3435 // For floating-point precision of 12:
3441 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3443 // error 0.0000876136000, which is better than 13 bits
3444 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3445 getF32Constant(DAG, 0xbda7262e));
3446 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3447 getF32Constant(DAG, 0x3f25280b));
3448 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3449 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3450 getF32Constant(DAG, 0x4007b923));
3451 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3452 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3453 getF32Constant(DAG, 0x40823e2f));
3454 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3455 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3456 getF32Constant(DAG, 0x4020d29c));
3458 result = DAG.getNode(ISD::FADD, dl,
3459 MVT::f32, LogOfExponent, Log2ofMantissa);
3460 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3461 // For floating-point precision of 18:
3470 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3472 // error 0.0000018516, which is better than 18 bits
3473 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3474 getF32Constant(DAG, 0xbcd2769e));
3475 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3476 getF32Constant(DAG, 0x3e8ce0b9));
3477 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3478 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3479 getF32Constant(DAG, 0x3fa22ae7));
3480 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3481 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3482 getF32Constant(DAG, 0x40525723));
3483 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3484 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3485 getF32Constant(DAG, 0x40aaf200));
3486 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3487 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3488 getF32Constant(DAG, 0x40c39dad));
3489 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3490 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3491 getF32Constant(DAG, 0x4042902c));
3493 result = DAG.getNode(ISD::FADD, dl,
3494 MVT::f32, LogOfExponent, Log2ofMantissa);
3497 // No special expansion.
3498 result = DAG.getNode(ISD::FLOG2, dl,
3499 getValue(I.getOperand(1)).getValueType(),
3500 getValue(I.getOperand(1)));
3503 setValue(&I, result);
3506 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3507 /// limited-precision mode.
3509 SelectionDAGLowering::visitLog10(CallInst &I) {
3511 DebugLoc dl = getCurDebugLoc();
3513 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3514 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3515 SDValue Op = getValue(I.getOperand(1));
3516 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3518 // Scale the exponent by log10(2) [0.30102999f].
3519 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3520 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3521 getF32Constant(DAG, 0x3e9a209a));
3523 // Get the significand and build it into a floating-point number with
3525 SDValue X = GetSignificand(DAG, Op1, dl);
3527 if (LimitFloatPrecision <= 6) {
3528 // For floating-point precision of 6:
3530 // Log10ofMantissa =
3532 // (0.60948995f - 0.10380950f * x) * x;
3534 // error 0.0014886165, which is 6 bits
3535 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3536 getF32Constant(DAG, 0xbdd49a13));
3537 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3538 getF32Constant(DAG, 0x3f1c0789));
3539 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3540 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3541 getF32Constant(DAG, 0x3f011300));
3543 result = DAG.getNode(ISD::FADD, dl,
3544 MVT::f32, LogOfExponent, Log10ofMantissa);
3545 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3546 // For floating-point precision of 12:
3548 // Log10ofMantissa =
3551 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3553 // error 0.00019228036, which is better than 12 bits
3554 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3555 getF32Constant(DAG, 0x3d431f31));
3556 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3557 getF32Constant(DAG, 0x3ea21fb2));
3558 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3559 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3560 getF32Constant(DAG, 0x3f6ae232));
3561 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3562 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3563 getF32Constant(DAG, 0x3f25f7c3));
3565 result = DAG.getNode(ISD::FADD, dl,
3566 MVT::f32, LogOfExponent, Log10ofMantissa);
3567 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3568 // For floating-point precision of 18:
3570 // Log10ofMantissa =
3575 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3577 // error 0.0000037995730, which is better than 18 bits
3578 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3579 getF32Constant(DAG, 0x3c5d51ce));
3580 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3581 getF32Constant(DAG, 0x3e00685a));
3582 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3583 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3584 getF32Constant(DAG, 0x3efb6798));
3585 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3586 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3587 getF32Constant(DAG, 0x3f88d192));
3588 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3589 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3590 getF32Constant(DAG, 0x3fc4316c));
3591 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3592 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3593 getF32Constant(DAG, 0x3f57ce70));
3595 result = DAG.getNode(ISD::FADD, dl,
3596 MVT::f32, LogOfExponent, Log10ofMantissa);
3599 // No special expansion.
3600 result = DAG.getNode(ISD::FLOG10, dl,
3601 getValue(I.getOperand(1)).getValueType(),
3602 getValue(I.getOperand(1)));
3605 setValue(&I, result);
3608 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3609 /// limited-precision mode.
3611 SelectionDAGLowering::visitExp2(CallInst &I) {
3613 DebugLoc dl = getCurDebugLoc();
3615 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3616 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3617 SDValue Op = getValue(I.getOperand(1));
3619 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3621 // FractionalPartOfX = x - (float)IntegerPartOfX;
3622 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3623 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3625 // IntegerPartOfX <<= 23;
3626 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3627 DAG.getConstant(23, TLI.getPointerTy()));
3629 if (LimitFloatPrecision <= 6) {
3630 // For floating-point precision of 6:
3632 // TwoToFractionalPartOfX =
3634 // (0.735607626f + 0.252464424f * x) * x;
3636 // error 0.0144103317, which is 6 bits
3637 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3638 getF32Constant(DAG, 0x3e814304));
3639 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3640 getF32Constant(DAG, 0x3f3c50c8));
3641 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3642 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3643 getF32Constant(DAG, 0x3f7f5e7e));
3644 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3645 SDValue TwoToFractionalPartOfX =
3646 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3648 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3649 MVT::f32, TwoToFractionalPartOfX);
3650 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3651 // For floating-point precision of 12:
3653 // TwoToFractionalPartOfX =
3656 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3658 // error 0.000107046256, which is 13 to 14 bits
3659 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3660 getF32Constant(DAG, 0x3da235e3));
3661 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3662 getF32Constant(DAG, 0x3e65b8f3));
3663 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3664 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3665 getF32Constant(DAG, 0x3f324b07));
3666 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3667 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3668 getF32Constant(DAG, 0x3f7ff8fd));
3669 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3670 SDValue TwoToFractionalPartOfX =
3671 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3673 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3674 MVT::f32, TwoToFractionalPartOfX);
3675 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3676 // For floating-point precision of 18:
3678 // TwoToFractionalPartOfX =
3682 // (0.554906021e-1f +
3683 // (0.961591928e-2f +
3684 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3685 // error 2.47208000*10^(-7), which is better than 18 bits
3686 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3687 getF32Constant(DAG, 0x3924b03e));
3688 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3689 getF32Constant(DAG, 0x3ab24b87));
3690 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3691 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3692 getF32Constant(DAG, 0x3c1d8c17));
3693 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3694 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3695 getF32Constant(DAG, 0x3d634a1d));
3696 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3697 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3698 getF32Constant(DAG, 0x3e75fe14));
3699 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3700 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3701 getF32Constant(DAG, 0x3f317234));
3702 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3703 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3704 getF32Constant(DAG, 0x3f800000));
3705 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3706 SDValue TwoToFractionalPartOfX =
3707 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3709 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3710 MVT::f32, TwoToFractionalPartOfX);
3713 // No special expansion.
3714 result = DAG.getNode(ISD::FEXP2, dl,
3715 getValue(I.getOperand(1)).getValueType(),
3716 getValue(I.getOperand(1)));
3719 setValue(&I, result);
3722 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3723 /// limited-precision mode with x == 10.0f.
3725 SelectionDAGLowering::visitPow(CallInst &I) {
3727 Value *Val = I.getOperand(1);
3728 DebugLoc dl = getCurDebugLoc();
3729 bool IsExp10 = false;
3731 if (getValue(Val).getValueType() == MVT::f32 &&
3732 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3733 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3734 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3735 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3737 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3742 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3743 SDValue Op = getValue(I.getOperand(2));
3745 // Put the exponent in the right bit position for later addition to the
3748 // #define LOG2OF10 3.3219281f
3749 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3750 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3751 getF32Constant(DAG, 0x40549a78));
3752 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3754 // FractionalPartOfX = x - (float)IntegerPartOfX;
3755 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3756 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3758 // IntegerPartOfX <<= 23;
3759 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3760 DAG.getConstant(23, TLI.getPointerTy()));
3762 if (LimitFloatPrecision <= 6) {
3763 // For floating-point precision of 6:
3765 // twoToFractionalPartOfX =
3767 // (0.735607626f + 0.252464424f * x) * x;
3769 // error 0.0144103317, which is 6 bits
3770 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3771 getF32Constant(DAG, 0x3e814304));
3772 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3773 getF32Constant(DAG, 0x3f3c50c8));
3774 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3775 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3776 getF32Constant(DAG, 0x3f7f5e7e));
3777 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3778 SDValue TwoToFractionalPartOfX =
3779 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3781 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3782 MVT::f32, TwoToFractionalPartOfX);
3783 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3784 // For floating-point precision of 12:
3786 // TwoToFractionalPartOfX =
3789 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3791 // error 0.000107046256, which is 13 to 14 bits
3792 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3793 getF32Constant(DAG, 0x3da235e3));
3794 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3795 getF32Constant(DAG, 0x3e65b8f3));
3796 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3797 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3798 getF32Constant(DAG, 0x3f324b07));
3799 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3800 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3801 getF32Constant(DAG, 0x3f7ff8fd));
3802 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3803 SDValue TwoToFractionalPartOfX =
3804 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3806 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3807 MVT::f32, TwoToFractionalPartOfX);
3808 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3809 // For floating-point precision of 18:
3811 // TwoToFractionalPartOfX =
3815 // (0.554906021e-1f +
3816 // (0.961591928e-2f +
3817 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3818 // error 2.47208000*10^(-7), which is better than 18 bits
3819 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3820 getF32Constant(DAG, 0x3924b03e));
3821 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3822 getF32Constant(DAG, 0x3ab24b87));
3823 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3824 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3825 getF32Constant(DAG, 0x3c1d8c17));
3826 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3827 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3828 getF32Constant(DAG, 0x3d634a1d));
3829 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3830 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3831 getF32Constant(DAG, 0x3e75fe14));
3832 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3833 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3834 getF32Constant(DAG, 0x3f317234));
3835 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3836 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3837 getF32Constant(DAG, 0x3f800000));
3838 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3839 SDValue TwoToFractionalPartOfX =
3840 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3842 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3843 MVT::f32, TwoToFractionalPartOfX);
3846 // No special expansion.
3847 result = DAG.getNode(ISD::FPOW, dl,
3848 getValue(I.getOperand(1)).getValueType(),
3849 getValue(I.getOperand(1)),
3850 getValue(I.getOperand(2)));
3853 setValue(&I, result);
3856 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3857 /// we want to emit this as a call to a named external function, return the name
3858 /// otherwise lower it and return null.
3860 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3861 DebugLoc dl = getCurDebugLoc();
3862 switch (Intrinsic) {
3864 // By default, turn this into a target intrinsic node.
3865 visitTargetIntrinsic(I, Intrinsic);
3867 case Intrinsic::vastart: visitVAStart(I); return 0;
3868 case Intrinsic::vaend: visitVAEnd(I); return 0;
3869 case Intrinsic::vacopy: visitVACopy(I); return 0;
3870 case Intrinsic::returnaddress:
3871 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3872 getValue(I.getOperand(1))));
3874 case Intrinsic::frameaddress:
3875 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3876 getValue(I.getOperand(1))));
3878 case Intrinsic::setjmp:
3879 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3881 case Intrinsic::longjmp:
3882 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3884 case Intrinsic::memcpy: {
3885 SDValue Op1 = getValue(I.getOperand(1));
3886 SDValue Op2 = getValue(I.getOperand(2));
3887 SDValue Op3 = getValue(I.getOperand(3));
3888 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3889 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3890 I.getOperand(1), 0, I.getOperand(2), 0));
3893 case Intrinsic::memset: {
3894 SDValue Op1 = getValue(I.getOperand(1));
3895 SDValue Op2 = getValue(I.getOperand(2));
3896 SDValue Op3 = getValue(I.getOperand(3));
3897 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3898 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3899 I.getOperand(1), 0));
3902 case Intrinsic::memmove: {
3903 SDValue Op1 = getValue(I.getOperand(1));
3904 SDValue Op2 = getValue(I.getOperand(2));
3905 SDValue Op3 = getValue(I.getOperand(3));
3906 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3908 // If the source and destination are known to not be aliases, we can
3909 // lower memmove as memcpy.
3910 uint64_t Size = -1ULL;
3911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3912 Size = C->getZExtValue();
3913 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3914 AliasAnalysis::NoAlias) {
3915 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3916 I.getOperand(1), 0, I.getOperand(2), 0));
3920 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3921 I.getOperand(1), 0, I.getOperand(2), 0));
3924 case Intrinsic::dbg_stoppoint: {
3925 DwarfWriter *DW = DAG.getDwarfWriter();
3926 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3927 if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
3928 MachineFunction &MF = DAG.getMachineFunction();
3930 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3934 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3935 std::string Dir, FN;
3936 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
3937 CU.getFilename(FN));
3938 unsigned idx = MF.getOrCreateDebugLocID(SrcFile,
3939 SPI.getLine(), SPI.getColumn());
3940 setCurDebugLoc(DebugLoc::get(idx));
3944 case Intrinsic::dbg_region_start: {
3945 DwarfWriter *DW = DAG.getDwarfWriter();
3946 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3947 if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
3949 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3950 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3951 getRoot(), LabelID));
3956 case Intrinsic::dbg_region_end: {
3957 DwarfWriter *DW = DAG.getDwarfWriter();
3958 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3959 if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
3961 MachineFunction &MF = DAG.getMachineFunction();
3962 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3964 Subprogram.getLinkageName(SPName);
3966 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
3967 // This is end of inlined function. Debugging information for
3968 // inlined function is not handled yet (only supported by FastISel).
3970 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3972 // Returned ID is 0 if this is unbalanced "end of inlined
3973 // scope". This could happen if optimizer eats dbg intrinsics
3974 // or "beginning of inlined scope" is not recoginized due to
3975 // missing location info. In such cases, do ignore this region.end.
3976 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3983 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3984 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3985 getRoot(), LabelID));
3990 case Intrinsic::dbg_func_start: {
3991 DwarfWriter *DW = DAG.getDwarfWriter();
3993 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3994 Value *SP = FSI.getSubprogram();
3995 if (SP && DW->ValidDebugInfo(SP, Fast)) {
3996 MachineFunction &MF = DAG.getMachineFunction();
3998 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
3999 // (most?) gdb expects.
4000 DebugLoc PrevLoc = CurDebugLoc;
4001 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4002 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4003 std::string Dir, FN;
4004 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4005 CompileUnit.getFilename(FN));
4007 if (!Subprogram.describes(MF.getFunction())) {
4008 // This is a beginning of an inlined function.
4010 // If llvm.dbg.func.start is seen in a new block before any
4011 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
4012 // FIXME : Why DebugLoc is reset at the beginning of each block ?
4013 if (PrevLoc.isUnknown())
4016 // Record the source line.
4017 unsigned Line = Subprogram.getLineNumber();
4018 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
4019 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4021 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
4022 getRoot(), LabelID));
4023 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
4024 DW->RecordInlinedFnStart(&FSI, Subprogram, LabelID,
4029 // Record the source line.
4030 unsigned Line = Subprogram.getLineNumber();
4031 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4032 DW->RecordSourceLine(Line, 0, SrcFile);
4033 // llvm.dbg.func_start also defines beginning of function scope.
4034 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
4037 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4040 Subprogram.getLinkageName(SPName);
4042 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
4043 // This is beginning of inlined function. Debugging information for
4044 // inlined function is not handled yet (only supported by FastISel).
4048 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
4049 // what (most?) gdb expects.
4050 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4051 std::string Dir, FN;
4052 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4053 CompileUnit.getFilename(FN));
4055 // Record the source line but does not create a label for the normal
4056 // function start. It will be emitted at asm emission time. However,
4057 // create a label if this is a beginning of inlined function.
4058 unsigned Line = Subprogram.getLineNumber();
4059 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4060 // FIXME - Start new region because llvm.dbg.func_start also defines
4061 // beginning of function scope.
4067 case Intrinsic::dbg_declare: {
4069 DwarfWriter *DW = DAG.getDwarfWriter();
4070 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4071 Value *Variable = DI.getVariable();
4072 if (DW && DW->ValidDebugInfo(Variable, Fast))
4073 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
4074 getValue(DI.getAddress()), getValue(Variable)));
4076 // FIXME: Do something sensible here when we support debug declare.
4080 case Intrinsic::eh_exception: {
4081 if (!CurMBB->isLandingPad()) {
4082 // FIXME: Mark exception register as live in. Hack for PR1508.
4083 unsigned Reg = TLI.getExceptionAddressRegister();
4084 if (Reg) CurMBB->addLiveIn(Reg);
4086 // Insert the EXCEPTIONADDR instruction.
4087 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4089 Ops[0] = DAG.getRoot();
4090 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4092 DAG.setRoot(Op.getValue(1));
4096 case Intrinsic::eh_selector_i32:
4097 case Intrinsic::eh_selector_i64: {
4098 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4099 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4100 MVT::i32 : MVT::i64);
4103 if (CurMBB->isLandingPad())
4104 AddCatchInfo(I, MMI, CurMBB);
4107 FuncInfo.CatchInfoLost.insert(&I);
4109 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4110 unsigned Reg = TLI.getExceptionSelectorRegister();
4111 if (Reg) CurMBB->addLiveIn(Reg);
4114 // Insert the EHSELECTION instruction.
4115 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4117 Ops[0] = getValue(I.getOperand(1));
4119 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4121 DAG.setRoot(Op.getValue(1));
4123 setValue(&I, DAG.getConstant(0, VT));
4129 case Intrinsic::eh_typeid_for_i32:
4130 case Intrinsic::eh_typeid_for_i64: {
4131 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4132 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4133 MVT::i32 : MVT::i64);
4136 // Find the type id for the given typeinfo.
4137 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4139 unsigned TypeID = MMI->getTypeIDFor(GV);
4140 setValue(&I, DAG.getConstant(TypeID, VT));
4142 // Return something different to eh_selector.
4143 setValue(&I, DAG.getConstant(1, VT));
4149 case Intrinsic::eh_return_i32:
4150 case Intrinsic::eh_return_i64:
4151 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4152 MMI->setCallsEHReturn(true);
4153 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4156 getValue(I.getOperand(1)),
4157 getValue(I.getOperand(2))));
4159 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4163 case Intrinsic::eh_unwind_init:
4164 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4165 MMI->setCallsUnwindInit(true);
4170 case Intrinsic::eh_dwarf_cfa: {
4171 MVT VT = getValue(I.getOperand(1)).getValueType();
4173 if (VT.bitsGT(TLI.getPointerTy()))
4174 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4175 TLI.getPointerTy(), getValue(I.getOperand(1)));
4177 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4178 TLI.getPointerTy(), getValue(I.getOperand(1)));
4180 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4182 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4183 TLI.getPointerTy()),
4185 setValue(&I, DAG.getNode(ISD::ADD, dl,
4187 DAG.getNode(ISD::FRAMEADDR, dl,
4190 TLI.getPointerTy())),
4195 case Intrinsic::convertff:
4196 case Intrinsic::convertfsi:
4197 case Intrinsic::convertfui:
4198 case Intrinsic::convertsif:
4199 case Intrinsic::convertuif:
4200 case Intrinsic::convertss:
4201 case Intrinsic::convertsu:
4202 case Intrinsic::convertus:
4203 case Intrinsic::convertuu: {
4204 ISD::CvtCode Code = ISD::CVT_INVALID;
4205 switch (Intrinsic) {
4206 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4207 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4208 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4209 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4210 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4211 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4212 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4213 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4214 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4216 MVT DestVT = TLI.getValueType(I.getType());
4217 Value* Op1 = I.getOperand(1);
4218 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4219 DAG.getValueType(DestVT),
4220 DAG.getValueType(getValue(Op1).getValueType()),
4221 getValue(I.getOperand(2)),
4222 getValue(I.getOperand(3)),
4227 case Intrinsic::sqrt:
4228 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4229 getValue(I.getOperand(1)).getValueType(),
4230 getValue(I.getOperand(1))));
4232 case Intrinsic::powi:
4233 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4234 getValue(I.getOperand(1)).getValueType(),
4235 getValue(I.getOperand(1)),
4236 getValue(I.getOperand(2))));
4238 case Intrinsic::sin:
4239 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4240 getValue(I.getOperand(1)).getValueType(),
4241 getValue(I.getOperand(1))));
4243 case Intrinsic::cos:
4244 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4245 getValue(I.getOperand(1)).getValueType(),
4246 getValue(I.getOperand(1))));
4248 case Intrinsic::log:
4251 case Intrinsic::log2:
4254 case Intrinsic::log10:
4257 case Intrinsic::exp:
4260 case Intrinsic::exp2:
4263 case Intrinsic::pow:
4266 case Intrinsic::pcmarker: {
4267 SDValue Tmp = getValue(I.getOperand(1));
4268 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4271 case Intrinsic::readcyclecounter: {
4272 SDValue Op = getRoot();
4273 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4274 DAG.getVTList(MVT::i64, MVT::Other),
4277 DAG.setRoot(Tmp.getValue(1));
4280 case Intrinsic::part_select: {
4281 // Currently not implemented: just abort
4282 assert(0 && "part_select intrinsic not implemented");
4285 case Intrinsic::part_set: {
4286 // Currently not implemented: just abort
4287 assert(0 && "part_set intrinsic not implemented");
4290 case Intrinsic::bswap:
4291 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4292 getValue(I.getOperand(1)).getValueType(),
4293 getValue(I.getOperand(1))));
4295 case Intrinsic::cttz: {
4296 SDValue Arg = getValue(I.getOperand(1));
4297 MVT Ty = Arg.getValueType();
4298 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4299 setValue(&I, result);
4302 case Intrinsic::ctlz: {
4303 SDValue Arg = getValue(I.getOperand(1));
4304 MVT Ty = Arg.getValueType();
4305 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4306 setValue(&I, result);
4309 case Intrinsic::ctpop: {
4310 SDValue Arg = getValue(I.getOperand(1));
4311 MVT Ty = Arg.getValueType();
4312 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4313 setValue(&I, result);
4316 case Intrinsic::stacksave: {
4317 SDValue Op = getRoot();
4318 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4319 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4321 DAG.setRoot(Tmp.getValue(1));
4324 case Intrinsic::stackrestore: {
4325 SDValue Tmp = getValue(I.getOperand(1));
4326 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4329 case Intrinsic::stackprotector: {
4330 // Emit code into the DAG to store the stack guard onto the stack.
4331 MachineFunction &MF = DAG.getMachineFunction();
4332 MachineFrameInfo *MFI = MF.getFrameInfo();
4333 MVT PtrTy = TLI.getPointerTy();
4335 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4336 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4338 int FI = FuncInfo.StaticAllocaMap[Slot];
4339 MFI->setStackProtectorIndex(FI);
4341 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4343 // Store the stack protector onto the stack.
4344 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4345 PseudoSourceValue::getFixedStack(FI),
4347 setValue(&I, Result);
4348 DAG.setRoot(Result);
4351 case Intrinsic::var_annotation:
4352 // Discard annotate attributes
4355 case Intrinsic::init_trampoline: {
4356 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4360 Ops[1] = getValue(I.getOperand(1));
4361 Ops[2] = getValue(I.getOperand(2));
4362 Ops[3] = getValue(I.getOperand(3));
4363 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4364 Ops[5] = DAG.getSrcValue(F);
4366 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4367 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4371 DAG.setRoot(Tmp.getValue(1));
4375 case Intrinsic::gcroot:
4377 Value *Alloca = I.getOperand(1);
4378 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4380 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4381 GFI->addStackRoot(FI->getIndex(), TypeMap);
4385 case Intrinsic::gcread:
4386 case Intrinsic::gcwrite:
4387 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4390 case Intrinsic::flt_rounds: {
4391 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4395 case Intrinsic::trap: {
4396 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4400 case Intrinsic::uadd_with_overflow:
4401 return implVisitAluOverflow(I, ISD::UADDO);
4402 case Intrinsic::sadd_with_overflow:
4403 return implVisitAluOverflow(I, ISD::SADDO);
4404 case Intrinsic::usub_with_overflow:
4405 return implVisitAluOverflow(I, ISD::USUBO);
4406 case Intrinsic::ssub_with_overflow:
4407 return implVisitAluOverflow(I, ISD::SSUBO);
4408 case Intrinsic::umul_with_overflow:
4409 return implVisitAluOverflow(I, ISD::UMULO);
4410 case Intrinsic::smul_with_overflow:
4411 return implVisitAluOverflow(I, ISD::SMULO);
4413 case Intrinsic::prefetch: {
4416 Ops[1] = getValue(I.getOperand(1));
4417 Ops[2] = getValue(I.getOperand(2));
4418 Ops[3] = getValue(I.getOperand(3));
4419 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4423 case Intrinsic::memory_barrier: {
4426 for (int x = 1; x < 6; ++x)
4427 Ops[x] = getValue(I.getOperand(x));
4429 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4432 case Intrinsic::atomic_cmp_swap: {
4433 SDValue Root = getRoot();
4435 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4436 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4438 getValue(I.getOperand(1)),
4439 getValue(I.getOperand(2)),
4440 getValue(I.getOperand(3)),
4443 DAG.setRoot(L.getValue(1));
4446 case Intrinsic::atomic_load_add:
4447 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4448 case Intrinsic::atomic_load_sub:
4449 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4450 case Intrinsic::atomic_load_or:
4451 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4452 case Intrinsic::atomic_load_xor:
4453 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4454 case Intrinsic::atomic_load_and:
4455 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4456 case Intrinsic::atomic_load_nand:
4457 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4458 case Intrinsic::atomic_load_max:
4459 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4460 case Intrinsic::atomic_load_min:
4461 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4462 case Intrinsic::atomic_load_umin:
4463 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4464 case Intrinsic::atomic_load_umax:
4465 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4466 case Intrinsic::atomic_swap:
4467 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4472 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4474 MachineBasicBlock *LandingPad) {
4475 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4476 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4477 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4478 unsigned BeginLabel = 0, EndLabel = 0;
4480 TargetLowering::ArgListTy Args;
4481 TargetLowering::ArgListEntry Entry;
4482 Args.reserve(CS.arg_size());
4483 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4485 SDValue ArgNode = getValue(*i);
4486 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4488 unsigned attrInd = i - CS.arg_begin() + 1;
4489 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4490 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4491 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4492 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4493 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4494 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4495 Entry.Alignment = CS.getParamAlignment(attrInd);
4496 Args.push_back(Entry);
4499 if (LandingPad && MMI) {
4500 // Insert a label before the invoke call to mark the try range. This can be
4501 // used to detect deletion of the invoke via the MachineModuleInfo.
4502 BeginLabel = MMI->NextLabelID();
4503 // Both PendingLoads and PendingExports must be flushed here;
4504 // this call might not return.
4506 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4507 getControlRoot(), BeginLabel));
4510 std::pair<SDValue,SDValue> Result =
4511 TLI.LowerCallTo(getRoot(), CS.getType(),
4512 CS.paramHasAttr(0, Attribute::SExt),
4513 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4514 CS.paramHasAttr(0, Attribute::InReg),
4515 CS.getCallingConv(),
4516 IsTailCall && PerformTailCallOpt,
4517 Callee, Args, DAG, getCurDebugLoc());
4518 if (CS.getType() != Type::VoidTy)
4519 setValue(CS.getInstruction(), Result.first);
4520 DAG.setRoot(Result.second);
4522 if (LandingPad && MMI) {
4523 // Insert a label at the end of the invoke call to mark the try range. This
4524 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4525 EndLabel = MMI->NextLabelID();
4526 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4527 getRoot(), EndLabel));
4529 // Inform MachineModuleInfo of range.
4530 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4535 void SelectionDAGLowering::visitCall(CallInst &I) {
4536 const char *RenameFn = 0;
4537 if (Function *F = I.getCalledFunction()) {
4538 if (F->isDeclaration()) {
4539 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4541 if (unsigned IID = II->getIntrinsicID(F)) {
4542 RenameFn = visitIntrinsicCall(I, IID);
4547 if (unsigned IID = F->getIntrinsicID()) {
4548 RenameFn = visitIntrinsicCall(I, IID);
4554 // Check for well-known libc/libm calls. If the function is internal, it
4555 // can't be a library call.
4556 unsigned NameLen = F->getNameLen();
4557 if (!F->hasLocalLinkage() && NameLen) {
4558 const char *NameStr = F->getNameStart();
4559 if (NameStr[0] == 'c' &&
4560 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4561 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4562 if (I.getNumOperands() == 3 && // Basic sanity checks.
4563 I.getOperand(1)->getType()->isFloatingPoint() &&
4564 I.getType() == I.getOperand(1)->getType() &&
4565 I.getType() == I.getOperand(2)->getType()) {
4566 SDValue LHS = getValue(I.getOperand(1));
4567 SDValue RHS = getValue(I.getOperand(2));
4568 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4569 LHS.getValueType(), LHS, RHS));
4572 } else if (NameStr[0] == 'f' &&
4573 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4574 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4575 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4576 if (I.getNumOperands() == 2 && // Basic sanity checks.
4577 I.getOperand(1)->getType()->isFloatingPoint() &&
4578 I.getType() == I.getOperand(1)->getType()) {
4579 SDValue Tmp = getValue(I.getOperand(1));
4580 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4581 Tmp.getValueType(), Tmp));
4584 } else if (NameStr[0] == 's' &&
4585 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4586 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4587 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4588 if (I.getNumOperands() == 2 && // Basic sanity checks.
4589 I.getOperand(1)->getType()->isFloatingPoint() &&
4590 I.getType() == I.getOperand(1)->getType()) {
4591 SDValue Tmp = getValue(I.getOperand(1));
4592 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4593 Tmp.getValueType(), Tmp));
4596 } else if (NameStr[0] == 'c' &&
4597 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4598 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4599 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4600 if (I.getNumOperands() == 2 && // Basic sanity checks.
4601 I.getOperand(1)->getType()->isFloatingPoint() &&
4602 I.getType() == I.getOperand(1)->getType()) {
4603 SDValue Tmp = getValue(I.getOperand(1));
4604 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4605 Tmp.getValueType(), Tmp));
4610 } else if (isa<InlineAsm>(I.getOperand(0))) {
4617 Callee = getValue(I.getOperand(0));
4619 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4621 LowerCallTo(&I, Callee, I.isTailCall());
4625 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4626 /// this value and returns the result as a ValueVT value. This uses
4627 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4628 /// If the Flag pointer is NULL, no flag is used.
4629 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4631 SDValue *Flag) const {
4632 // Assemble the legal parts into the final values.
4633 SmallVector<SDValue, 4> Values(ValueVTs.size());
4634 SmallVector<SDValue, 8> Parts;
4635 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4636 // Copy the legal parts from the registers.
4637 MVT ValueVT = ValueVTs[Value];
4638 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4639 MVT RegisterVT = RegVTs[Value];
4641 Parts.resize(NumRegs);
4642 for (unsigned i = 0; i != NumRegs; ++i) {
4645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4647 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4648 *Flag = P.getValue(2);
4650 Chain = P.getValue(1);
4652 // If the source register was virtual and if we know something about it,
4653 // add an assert node.
4654 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4655 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4656 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4657 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4658 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4659 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4661 unsigned RegSize = RegisterVT.getSizeInBits();
4662 unsigned NumSignBits = LOI.NumSignBits;
4663 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4665 // FIXME: We capture more information than the dag can represent. For
4666 // now, just use the tightest assertzext/assertsext possible.
4668 MVT FromVT(MVT::Other);
4669 if (NumSignBits == RegSize)
4670 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4671 else if (NumZeroBits >= RegSize-1)
4672 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4673 else if (NumSignBits > RegSize-8)
4674 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4675 else if (NumZeroBits >= RegSize-8)
4676 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4677 else if (NumSignBits > RegSize-16)
4678 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4679 else if (NumZeroBits >= RegSize-16)
4680 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4681 else if (NumSignBits > RegSize-32)
4682 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4683 else if (NumZeroBits >= RegSize-32)
4684 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4686 if (FromVT != MVT::Other) {
4687 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4688 RegisterVT, P, DAG.getValueType(FromVT));
4697 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4698 NumRegs, RegisterVT, ValueVT);
4703 return DAG.getNode(ISD::MERGE_VALUES, dl,
4704 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4705 &Values[0], ValueVTs.size());
4708 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4709 /// specified value into the registers specified by this object. This uses
4710 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4711 /// If the Flag pointer is NULL, no flag is used.
4712 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4713 SDValue &Chain, SDValue *Flag) const {
4714 // Get the list of the values's legal parts.
4715 unsigned NumRegs = Regs.size();
4716 SmallVector<SDValue, 8> Parts(NumRegs);
4717 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4718 MVT ValueVT = ValueVTs[Value];
4719 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4720 MVT RegisterVT = RegVTs[Value];
4722 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4723 &Parts[Part], NumParts, RegisterVT);
4727 // Copy the parts into the registers.
4728 SmallVector<SDValue, 8> Chains(NumRegs);
4729 for (unsigned i = 0; i != NumRegs; ++i) {
4732 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4734 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4735 *Flag = Part.getValue(1);
4737 Chains[i] = Part.getValue(0);
4740 if (NumRegs == 1 || Flag)
4741 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4742 // flagged to it. That is the CopyToReg nodes and the user are considered
4743 // a single scheduling unit. If we create a TokenFactor and return it as
4744 // chain, then the TokenFactor is both a predecessor (operand) of the
4745 // user as well as a successor (the TF operands are flagged to the user).
4746 // c1, f1 = CopyToReg
4747 // c2, f2 = CopyToReg
4748 // c3 = TokenFactor c1, c2
4751 Chain = Chains[NumRegs-1];
4753 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4756 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4757 /// operand list. This adds the code marker and includes the number of
4758 /// values added into it.
4759 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4760 bool HasMatching,unsigned MatchingIdx,
4762 std::vector<SDValue> &Ops) const {
4763 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4764 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4765 unsigned Flag = Code | (Regs.size() << 3);
4767 Flag |= 0x80000000 | (MatchingIdx << 16);
4768 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4769 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4770 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4771 MVT RegisterVT = RegVTs[Value];
4772 for (unsigned i = 0; i != NumRegs; ++i) {
4773 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4774 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4779 /// isAllocatableRegister - If the specified register is safe to allocate,
4780 /// i.e. it isn't a stack pointer or some other special register, return the
4781 /// register class for the register. Otherwise, return null.
4782 static const TargetRegisterClass *
4783 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4784 const TargetLowering &TLI,
4785 const TargetRegisterInfo *TRI) {
4786 MVT FoundVT = MVT::Other;
4787 const TargetRegisterClass *FoundRC = 0;
4788 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4789 E = TRI->regclass_end(); RCI != E; ++RCI) {
4790 MVT ThisVT = MVT::Other;
4792 const TargetRegisterClass *RC = *RCI;
4793 // If none of the the value types for this register class are valid, we
4794 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4795 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4797 if (TLI.isTypeLegal(*I)) {
4798 // If we have already found this register in a different register class,
4799 // choose the one with the largest VT specified. For example, on
4800 // PowerPC, we favor f64 register classes over f32.
4801 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4808 if (ThisVT == MVT::Other) continue;
4810 // NOTE: This isn't ideal. In particular, this might allocate the
4811 // frame pointer in functions that need it (due to them not being taken
4812 // out of allocation, because a variable sized allocation hasn't been seen
4813 // yet). This is a slight code pessimization, but should still work.
4814 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4815 E = RC->allocation_order_end(MF); I != E; ++I)
4817 // We found a matching register class. Keep looking at others in case
4818 // we find one with larger registers that this physreg is also in.
4829 /// AsmOperandInfo - This contains information for each constraint that we are
4831 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4832 public TargetLowering::AsmOperandInfo {
4834 /// CallOperand - If this is the result output operand or a clobber
4835 /// this is null, otherwise it is the incoming operand to the CallInst.
4836 /// This gets modified as the asm is processed.
4837 SDValue CallOperand;
4839 /// AssignedRegs - If this is a register or register class operand, this
4840 /// contains the set of register corresponding to the operand.
4841 RegsForValue AssignedRegs;
4843 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4844 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4847 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4848 /// busy in OutputRegs/InputRegs.
4849 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4850 std::set<unsigned> &OutputRegs,
4851 std::set<unsigned> &InputRegs,
4852 const TargetRegisterInfo &TRI) const {
4854 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4855 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4858 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4859 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4863 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4864 /// corresponds to. If there is no Value* for this operand, it returns
4866 MVT getCallOperandValMVT(const TargetLowering &TLI,
4867 const TargetData *TD) const {
4868 if (CallOperandVal == 0) return MVT::Other;
4870 if (isa<BasicBlock>(CallOperandVal))
4871 return TLI.getPointerTy();
4873 const llvm::Type *OpTy = CallOperandVal->getType();
4875 // If this is an indirect operand, the operand is a pointer to the
4878 OpTy = cast<PointerType>(OpTy)->getElementType();
4880 // If OpTy is not a single value, it may be a struct/union that we
4881 // can tile with integers.
4882 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4883 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4892 OpTy = IntegerType::get(BitSize);
4897 return TLI.getValueType(OpTy, true);
4901 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4903 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4904 const TargetRegisterInfo &TRI) {
4905 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4907 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4908 for (; *Aliases; ++Aliases)
4909 Regs.insert(*Aliases);
4912 } // end llvm namespace.
4915 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4916 /// specified operand. We prefer to assign virtual registers, to allow the
4917 /// register allocator handle the assignment process. However, if the asm uses
4918 /// features that we can't model on machineinstrs, we have SDISel do the
4919 /// allocation. This produces generally horrible, but correct, code.
4921 /// OpInfo describes the operand.
4922 /// Input and OutputRegs are the set of already allocated physical registers.
4924 void SelectionDAGLowering::
4925 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4926 std::set<unsigned> &OutputRegs,
4927 std::set<unsigned> &InputRegs) {
4928 // Compute whether this value requires an input register, an output register,
4930 bool isOutReg = false;
4931 bool isInReg = false;
4932 switch (OpInfo.Type) {
4933 case InlineAsm::isOutput:
4936 // If there is an input constraint that matches this, we need to reserve
4937 // the input register so no other inputs allocate to it.
4938 isInReg = OpInfo.hasMatchingInput();
4940 case InlineAsm::isInput:
4944 case InlineAsm::isClobber:
4951 MachineFunction &MF = DAG.getMachineFunction();
4952 SmallVector<unsigned, 4> Regs;
4954 // If this is a constraint for a single physreg, or a constraint for a
4955 // register class, find it.
4956 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4957 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4958 OpInfo.ConstraintVT);
4960 unsigned NumRegs = 1;
4961 if (OpInfo.ConstraintVT != MVT::Other) {
4962 // If this is a FP input in an integer register (or visa versa) insert a bit
4963 // cast of the input value. More generally, handle any case where the input
4964 // value disagrees with the register class we plan to stick this in.
4965 if (OpInfo.Type == InlineAsm::isInput &&
4966 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4967 // Try to convert to the first MVT that the reg class contains. If the
4968 // types are identical size, use a bitcast to convert (e.g. two differing
4970 MVT RegVT = *PhysReg.second->vt_begin();
4971 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4972 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4973 RegVT, OpInfo.CallOperand);
4974 OpInfo.ConstraintVT = RegVT;
4975 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4976 // If the input is a FP value and we want it in FP registers, do a
4977 // bitcast to the corresponding integer type. This turns an f64 value
4978 // into i64, which can be passed with two i32 values on a 32-bit
4980 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4981 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4982 RegVT, OpInfo.CallOperand);
4983 OpInfo.ConstraintVT = RegVT;
4987 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4991 MVT ValueVT = OpInfo.ConstraintVT;
4993 // If this is a constraint for a specific physical register, like {r17},
4995 if (unsigned AssignedReg = PhysReg.first) {
4996 const TargetRegisterClass *RC = PhysReg.second;
4997 if (OpInfo.ConstraintVT == MVT::Other)
4998 ValueVT = *RC->vt_begin();
5000 // Get the actual register value type. This is important, because the user
5001 // may have asked for (e.g.) the AX register in i32 type. We need to
5002 // remember that AX is actually i16 to get the right extension.
5003 RegVT = *RC->vt_begin();
5005 // This is a explicit reference to a physical register.
5006 Regs.push_back(AssignedReg);
5008 // If this is an expanded reference, add the rest of the regs to Regs.
5010 TargetRegisterClass::iterator I = RC->begin();
5011 for (; *I != AssignedReg; ++I)
5012 assert(I != RC->end() && "Didn't find reg!");
5014 // Already added the first reg.
5016 for (; NumRegs; --NumRegs, ++I) {
5017 assert(I != RC->end() && "Ran out of registers to allocate!");
5021 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5022 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5023 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5027 // Otherwise, if this was a reference to an LLVM register class, create vregs
5028 // for this reference.
5029 if (const TargetRegisterClass *RC = PhysReg.second) {
5030 RegVT = *RC->vt_begin();
5031 if (OpInfo.ConstraintVT == MVT::Other)
5034 // Create the appropriate number of virtual registers.
5035 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5036 for (; NumRegs; --NumRegs)
5037 Regs.push_back(RegInfo.createVirtualRegister(RC));
5039 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5043 // This is a reference to a register class that doesn't directly correspond
5044 // to an LLVM register class. Allocate NumRegs consecutive, available,
5045 // registers from the class.
5046 std::vector<unsigned> RegClassRegs
5047 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5048 OpInfo.ConstraintVT);
5050 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5051 unsigned NumAllocated = 0;
5052 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5053 unsigned Reg = RegClassRegs[i];
5054 // See if this register is available.
5055 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5056 (isInReg && InputRegs.count(Reg))) { // Already used.
5057 // Make sure we find consecutive registers.
5062 // Check to see if this register is allocatable (i.e. don't give out the
5064 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5065 if (!RC) { // Couldn't allocate this register.
5066 // Reset NumAllocated to make sure we return consecutive registers.
5071 // Okay, this register is good, we can use it.
5074 // If we allocated enough consecutive registers, succeed.
5075 if (NumAllocated == NumRegs) {
5076 unsigned RegStart = (i-NumAllocated)+1;
5077 unsigned RegEnd = i+1;
5078 // Mark all of the allocated registers used.
5079 for (unsigned i = RegStart; i != RegEnd; ++i)
5080 Regs.push_back(RegClassRegs[i]);
5082 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5083 OpInfo.ConstraintVT);
5084 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5089 // Otherwise, we couldn't allocate enough registers for this.
5092 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5093 /// processed uses a memory 'm' constraint.
5095 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5096 const TargetLowering &TLI) {
5097 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5098 InlineAsm::ConstraintInfo &CI = CInfos[i];
5099 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5100 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5101 if (CType == TargetLowering::C_Memory)
5109 /// visitInlineAsm - Handle a call to an InlineAsm object.
5111 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5112 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5114 /// ConstraintOperands - Information about all of the constraints.
5115 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5117 // We won't need to flush pending loads if this asm doesn't touch
5118 // memory and is nonvolatile.
5119 SDValue Chain = IA->hasSideEffects() ? getRoot() : DAG.getRoot();
5122 std::set<unsigned> OutputRegs, InputRegs;
5124 // Do a prepass over the constraints, canonicalizing them, and building up the
5125 // ConstraintOperands list.
5126 std::vector<InlineAsm::ConstraintInfo>
5127 ConstraintInfos = IA->ParseConstraints();
5129 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5130 // Flush pending loads if this touches memory (includes clobbering it).
5131 // It's possible this is overly conservative.
5135 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5136 unsigned ResNo = 0; // ResNo - The result number of the next output.
5137 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5138 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5139 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5141 MVT OpVT = MVT::Other;
5143 // Compute the value type for each operand.
5144 switch (OpInfo.Type) {
5145 case InlineAsm::isOutput:
5146 // Indirect outputs just consume an argument.
5147 if (OpInfo.isIndirect) {
5148 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5152 // The return value of the call is this value. As such, there is no
5153 // corresponding argument.
5154 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5155 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5156 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5158 assert(ResNo == 0 && "Asm only has one result!");
5159 OpVT = TLI.getValueType(CS.getType());
5163 case InlineAsm::isInput:
5164 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5166 case InlineAsm::isClobber:
5171 // If this is an input or an indirect output, process the call argument.
5172 // BasicBlocks are labels, currently appearing only in asm's.
5173 if (OpInfo.CallOperandVal) {
5174 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5175 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5177 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5180 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5183 OpInfo.ConstraintVT = OpVT;
5186 // Second pass over the constraints: compute which constraint option to use
5187 // and assign registers to constraints that want a specific physreg.
5188 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5189 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5191 // If this is an output operand with a matching input operand, look up the
5192 // matching input. If their types mismatch, e.g. one is an integer, the
5193 // other is floating point, or their sizes are different, flag it as an
5195 if (OpInfo.hasMatchingInput()) {
5196 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5197 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5198 if ((OpInfo.ConstraintVT.isInteger() !=
5199 Input.ConstraintVT.isInteger()) ||
5200 (OpInfo.ConstraintVT.getSizeInBits() !=
5201 Input.ConstraintVT.getSizeInBits())) {
5202 cerr << "llvm: error: Unsupported asm: input constraint with a "
5203 << "matching output constraint of incompatible type!\n";
5206 Input.ConstraintVT = OpInfo.ConstraintVT;
5210 // Compute the constraint code and ConstraintType to use.
5211 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5213 // If this is a memory input, and if the operand is not indirect, do what we
5214 // need to to provide an address for the memory input.
5215 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5216 !OpInfo.isIndirect) {
5217 assert(OpInfo.Type == InlineAsm::isInput &&
5218 "Can only indirectify direct input operands!");
5220 // Memory operands really want the address of the value. If we don't have
5221 // an indirect input, put it in the constpool if we can, otherwise spill
5222 // it to a stack slot.
5224 // If the operand is a float, integer, or vector constant, spill to a
5225 // constant pool entry to get its address.
5226 Value *OpVal = OpInfo.CallOperandVal;
5227 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5228 isa<ConstantVector>(OpVal)) {
5229 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5230 TLI.getPointerTy());
5232 // Otherwise, create a stack slot and emit a store to it before the
5234 const Type *Ty = OpVal->getType();
5235 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5236 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5237 MachineFunction &MF = DAG.getMachineFunction();
5238 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5239 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5240 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5241 OpInfo.CallOperand, StackSlot, NULL, 0);
5242 OpInfo.CallOperand = StackSlot;
5245 // There is no longer a Value* corresponding to this operand.
5246 OpInfo.CallOperandVal = 0;
5247 // It is now an indirect operand.
5248 OpInfo.isIndirect = true;
5251 // If this constraint is for a specific register, allocate it before
5253 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5254 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5256 ConstraintInfos.clear();
5259 // Second pass - Loop over all of the operands, assigning virtual or physregs
5260 // to register class operands.
5261 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5262 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5264 // C_Register operands have already been allocated, Other/Memory don't need
5266 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5267 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5270 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5271 std::vector<SDValue> AsmNodeOperands;
5272 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5273 AsmNodeOperands.push_back(
5274 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5277 // Loop over all of the inputs, copying the operand values into the
5278 // appropriate registers and processing the output regs.
5279 RegsForValue RetValRegs;
5281 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5282 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5284 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5285 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5287 switch (OpInfo.Type) {
5288 case InlineAsm::isOutput: {
5289 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5290 OpInfo.ConstraintType != TargetLowering::C_Register) {
5291 // Memory output, or 'other' output (e.g. 'X' constraint).
5292 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5294 // Add information to the INLINEASM node to know about this output.
5295 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5296 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5297 TLI.getPointerTy()));
5298 AsmNodeOperands.push_back(OpInfo.CallOperand);
5302 // Otherwise, this is a register or register class output.
5304 // Copy the output from the appropriate register. Find a register that
5306 if (OpInfo.AssignedRegs.Regs.empty()) {
5307 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5308 << OpInfo.ConstraintCode << "'!\n";
5312 // If this is an indirect operand, store through the pointer after the
5314 if (OpInfo.isIndirect) {
5315 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5316 OpInfo.CallOperandVal));
5318 // This is the result value of the call.
5319 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5320 // Concatenate this output onto the outputs list.
5321 RetValRegs.append(OpInfo.AssignedRegs);
5324 // Add information to the INLINEASM node to know that this register is
5326 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5327 6 /* EARLYCLOBBER REGDEF */ :
5331 DAG, AsmNodeOperands);
5334 case InlineAsm::isInput: {
5335 SDValue InOperandVal = OpInfo.CallOperand;
5337 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5338 // If this is required to match an output register we have already set,
5339 // just use its register.
5340 unsigned OperandNo = OpInfo.getMatchedOperand();
5342 // Scan until we find the definition we already emitted of this operand.
5343 // When we find it, create a RegsForValue operand.
5344 unsigned CurOp = 2; // The first operand.
5345 for (; OperandNo; --OperandNo) {
5346 // Advance to the next operand.
5348 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5349 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5350 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5351 (OpFlag & 7) == 4 /*MEM*/) &&
5352 "Skipped past definitions?");
5353 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5357 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5358 if ((OpFlag & 7) == 2 /*REGDEF*/
5359 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5360 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5361 RegsForValue MatchedRegs;
5362 MatchedRegs.TLI = &TLI;
5363 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5364 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5365 MatchedRegs.RegVTs.push_back(RegVT);
5366 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5367 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5370 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5372 // Use the produced MatchedRegs object to
5373 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5375 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5376 true, OpInfo.getMatchedOperand(),
5377 DAG, AsmNodeOperands);
5380 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5381 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5382 "Unexpected number of operands");
5383 // Add information to the INLINEASM node to know about this input.
5384 // See InlineAsm.h isUseOperandTiedToDef.
5385 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5386 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5387 TLI.getPointerTy()));
5388 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5393 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5394 assert(!OpInfo.isIndirect &&
5395 "Don't know how to handle indirect other inputs yet!");
5397 std::vector<SDValue> Ops;
5398 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5399 hasMemory, Ops, DAG);
5401 cerr << "llvm: error: Invalid operand for inline asm constraint '"
5402 << OpInfo.ConstraintCode << "'!\n";
5406 // Add information to the INLINEASM node to know about this input.
5407 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5408 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5409 TLI.getPointerTy()));
5410 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5412 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5413 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5414 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5415 "Memory operands expect pointer values");
5417 // Add information to the INLINEASM node to know about this input.
5418 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5419 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5420 TLI.getPointerTy()));
5421 AsmNodeOperands.push_back(InOperandVal);
5425 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5426 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5427 "Unknown constraint type!");
5428 assert(!OpInfo.isIndirect &&
5429 "Don't know how to handle indirect register inputs yet!");
5431 // Copy the input into the appropriate registers.
5432 if (OpInfo.AssignedRegs.Regs.empty()) {
5433 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5434 << OpInfo.ConstraintCode << "'!\n";
5438 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5441 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5442 DAG, AsmNodeOperands);
5445 case InlineAsm::isClobber: {
5446 // Add the clobbered value to the operand list, so that the register
5447 // allocator is aware that the physreg got clobbered.
5448 if (!OpInfo.AssignedRegs.Regs.empty())
5449 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5450 false, 0, DAG,AsmNodeOperands);
5456 // Finish up input operands.
5457 AsmNodeOperands[0] = Chain;
5458 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5460 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5461 DAG.getVTList(MVT::Other, MVT::Flag),
5462 &AsmNodeOperands[0], AsmNodeOperands.size());
5463 Flag = Chain.getValue(1);
5465 // If this asm returns a register value, copy the result from that register
5466 // and set it as the value of the call.
5467 if (!RetValRegs.Regs.empty()) {
5468 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5471 // FIXME: Why don't we do this for inline asms with MRVs?
5472 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5473 MVT ResultType = TLI.getValueType(CS.getType());
5475 // If any of the results of the inline asm is a vector, it may have the
5476 // wrong width/num elts. This can happen for register classes that can
5477 // contain multiple different value types. The preg or vreg allocated may
5478 // not have the same VT as was expected. Convert it to the right type
5479 // with bit_convert.
5480 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5481 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5484 } else if (ResultType != Val.getValueType() &&
5485 ResultType.isInteger() && Val.getValueType().isInteger()) {
5486 // If a result value was tied to an input value, the computed result may
5487 // have a wider width than the expected result. Extract the relevant
5489 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5492 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5495 setValue(CS.getInstruction(), Val);
5496 // Don't need to use this as a chain in this case.
5497 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5501 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5503 // Process indirect outputs, first output all of the flagged copies out of
5505 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5506 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5507 Value *Ptr = IndirectStoresToEmit[i].second;
5508 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5510 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5513 // Emit the non-flagged stores from the physregs.
5514 SmallVector<SDValue, 8> OutChains;
5515 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5516 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5517 StoresToEmit[i].first,
5518 getValue(StoresToEmit[i].second),
5519 StoresToEmit[i].second, 0));
5520 if (!OutChains.empty())
5521 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5522 &OutChains[0], OutChains.size());
5527 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5528 SDValue Src = getValue(I.getOperand(0));
5530 // Scale up by the type size in the original i32 type width. Various
5531 // mid-level optimizers may make assumptions about demanded bits etc from the
5532 // i32-ness of the optimizer: we do not want to promote to i64 and then
5533 // multiply on 64-bit targets.
5534 // FIXME: Malloc inst should go away: PR715.
5535 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5536 if (ElementSize != 1)
5537 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5538 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5540 MVT IntPtr = TLI.getPointerTy();
5542 if (IntPtr.bitsLT(Src.getValueType()))
5543 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5544 else if (IntPtr.bitsGT(Src.getValueType()))
5545 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5547 TargetLowering::ArgListTy Args;
5548 TargetLowering::ArgListEntry Entry;
5550 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5551 Args.push_back(Entry);
5553 std::pair<SDValue,SDValue> Result =
5554 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5555 CallingConv::C, PerformTailCallOpt,
5556 DAG.getExternalSymbol("malloc", IntPtr),
5557 Args, DAG, getCurDebugLoc());
5558 setValue(&I, Result.first); // Pointers always fit in registers
5559 DAG.setRoot(Result.second);
5562 void SelectionDAGLowering::visitFree(FreeInst &I) {
5563 TargetLowering::ArgListTy Args;
5564 TargetLowering::ArgListEntry Entry;
5565 Entry.Node = getValue(I.getOperand(0));
5566 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5567 Args.push_back(Entry);
5568 MVT IntPtr = TLI.getPointerTy();
5569 std::pair<SDValue,SDValue> Result =
5570 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5571 CallingConv::C, PerformTailCallOpt,
5572 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5574 DAG.setRoot(Result.second);
5577 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5578 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5579 MVT::Other, getRoot(),
5580 getValue(I.getOperand(1)),
5581 DAG.getSrcValue(I.getOperand(1))));
5584 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5585 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5586 getRoot(), getValue(I.getOperand(0)),
5587 DAG.getSrcValue(I.getOperand(0)));
5589 DAG.setRoot(V.getValue(1));
5592 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5593 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5594 MVT::Other, getRoot(),
5595 getValue(I.getOperand(1)),
5596 DAG.getSrcValue(I.getOperand(1))));
5599 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5600 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5601 MVT::Other, getRoot(),
5602 getValue(I.getOperand(1)),
5603 getValue(I.getOperand(2)),
5604 DAG.getSrcValue(I.getOperand(1)),
5605 DAG.getSrcValue(I.getOperand(2))));
5608 /// TargetLowering::LowerArguments - This is the default LowerArguments
5609 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5610 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5611 /// integrated into SDISel.
5612 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5613 SmallVectorImpl<SDValue> &ArgValues,
5615 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5616 SmallVector<SDValue, 3+16> Ops;
5617 Ops.push_back(DAG.getRoot());
5618 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5619 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5621 // Add one result value for each formal argument.
5622 SmallVector<MVT, 16> RetVals;
5624 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5626 SmallVector<MVT, 4> ValueVTs;
5627 ComputeValueVTs(*this, I->getType(), ValueVTs);
5628 for (unsigned Value = 0, NumValues = ValueVTs.size();
5629 Value != NumValues; ++Value) {
5630 MVT VT = ValueVTs[Value];
5631 const Type *ArgTy = VT.getTypeForMVT();
5632 ISD::ArgFlagsTy Flags;
5633 unsigned OriginalAlignment =
5634 getTargetData()->getABITypeAlignment(ArgTy);
5636 if (F.paramHasAttr(j, Attribute::ZExt))
5638 if (F.paramHasAttr(j, Attribute::SExt))
5640 if (F.paramHasAttr(j, Attribute::InReg))
5642 if (F.paramHasAttr(j, Attribute::StructRet))
5644 if (F.paramHasAttr(j, Attribute::ByVal)) {
5646 const PointerType *Ty = cast<PointerType>(I->getType());
5647 const Type *ElementTy = Ty->getElementType();
5648 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5649 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5650 // For ByVal, alignment should be passed from FE. BE will guess if
5651 // this info is not there but there are cases it cannot get right.
5652 if (F.getParamAlignment(j))
5653 FrameAlign = F.getParamAlignment(j);
5654 Flags.setByValAlign(FrameAlign);
5655 Flags.setByValSize(FrameSize);
5657 if (F.paramHasAttr(j, Attribute::Nest))
5659 Flags.setOrigAlign(OriginalAlignment);
5661 MVT RegisterVT = getRegisterType(VT);
5662 unsigned NumRegs = getNumRegisters(VT);
5663 for (unsigned i = 0; i != NumRegs; ++i) {
5664 RetVals.push_back(RegisterVT);
5665 ISD::ArgFlagsTy MyFlags = Flags;
5666 if (NumRegs > 1 && i == 0)
5668 // if it isn't first piece, alignment must be 1
5670 MyFlags.setOrigAlign(1);
5671 Ops.push_back(DAG.getArgFlags(MyFlags));
5676 RetVals.push_back(MVT::Other);
5679 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5680 DAG.getVTList(&RetVals[0], RetVals.size()),
5681 &Ops[0], Ops.size()).getNode();
5683 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5684 // allows exposing the loads that may be part of the argument access to the
5685 // first DAGCombiner pass.
5686 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5688 // The number of results should match up, except that the lowered one may have
5689 // an extra flag result.
5690 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5691 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5692 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5693 && "Lowering produced unexpected number of results!");
5695 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5696 if (Result != TmpRes.getNode() && Result->use_empty()) {
5697 HandleSDNode Dummy(DAG.getRoot());
5698 DAG.RemoveDeadNode(Result);
5701 Result = TmpRes.getNode();
5703 unsigned NumArgRegs = Result->getNumValues() - 1;
5704 DAG.setRoot(SDValue(Result, NumArgRegs));
5706 // Set up the return result vector.
5709 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5711 SmallVector<MVT, 4> ValueVTs;
5712 ComputeValueVTs(*this, I->getType(), ValueVTs);
5713 for (unsigned Value = 0, NumValues = ValueVTs.size();
5714 Value != NumValues; ++Value) {
5715 MVT VT = ValueVTs[Value];
5716 MVT PartVT = getRegisterType(VT);
5718 unsigned NumParts = getNumRegisters(VT);
5719 SmallVector<SDValue, 4> Parts(NumParts);
5720 for (unsigned j = 0; j != NumParts; ++j)
5721 Parts[j] = SDValue(Result, i++);
5723 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5724 if (F.paramHasAttr(Idx, Attribute::SExt))
5725 AssertOp = ISD::AssertSext;
5726 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5727 AssertOp = ISD::AssertZext;
5729 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5730 PartVT, VT, AssertOp));
5733 assert(i == NumArgRegs && "Argument register count mismatch!");
5737 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5738 /// implementation, which just inserts an ISD::CALL node, which is later custom
5739 /// lowered by the target to something concrete. FIXME: When all targets are
5740 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5741 std::pair<SDValue, SDValue>
5742 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5743 bool RetSExt, bool RetZExt, bool isVarArg,
5745 unsigned CallingConv, bool isTailCall,
5747 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5748 assert((!isTailCall || PerformTailCallOpt) &&
5749 "isTailCall set when tail-call optimizations are disabled!");
5751 SmallVector<SDValue, 32> Ops;
5752 Ops.push_back(Chain); // Op#0 - Chain
5753 Ops.push_back(Callee);
5755 // Handle all of the outgoing arguments.
5756 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5757 SmallVector<MVT, 4> ValueVTs;
5758 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5759 for (unsigned Value = 0, NumValues = ValueVTs.size();
5760 Value != NumValues; ++Value) {
5761 MVT VT = ValueVTs[Value];
5762 const Type *ArgTy = VT.getTypeForMVT();
5763 SDValue Op = SDValue(Args[i].Node.getNode(),
5764 Args[i].Node.getResNo() + Value);
5765 ISD::ArgFlagsTy Flags;
5766 unsigned OriginalAlignment =
5767 getTargetData()->getABITypeAlignment(ArgTy);
5773 if (Args[i].isInReg)
5777 if (Args[i].isByVal) {
5779 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5780 const Type *ElementTy = Ty->getElementType();
5781 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5782 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5783 // For ByVal, alignment should come from FE. BE will guess if this
5784 // info is not there but there are cases it cannot get right.
5785 if (Args[i].Alignment)
5786 FrameAlign = Args[i].Alignment;
5787 Flags.setByValAlign(FrameAlign);
5788 Flags.setByValSize(FrameSize);
5792 Flags.setOrigAlign(OriginalAlignment);
5794 MVT PartVT = getRegisterType(VT);
5795 unsigned NumParts = getNumRegisters(VT);
5796 SmallVector<SDValue, 4> Parts(NumParts);
5797 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5800 ExtendKind = ISD::SIGN_EXTEND;
5801 else if (Args[i].isZExt)
5802 ExtendKind = ISD::ZERO_EXTEND;
5804 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5806 for (unsigned i = 0; i != NumParts; ++i) {
5807 // if it isn't first piece, alignment must be 1
5808 ISD::ArgFlagsTy MyFlags = Flags;
5809 if (NumParts > 1 && i == 0)
5812 MyFlags.setOrigAlign(1);
5814 Ops.push_back(Parts[i]);
5815 Ops.push_back(DAG.getArgFlags(MyFlags));
5820 // Figure out the result value types. We start by making a list of
5821 // the potentially illegal return value types.
5822 SmallVector<MVT, 4> LoweredRetTys;
5823 SmallVector<MVT, 4> RetTys;
5824 ComputeValueVTs(*this, RetTy, RetTys);
5826 // Then we translate that to a list of legal types.
5827 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5829 MVT RegisterVT = getRegisterType(VT);
5830 unsigned NumRegs = getNumRegisters(VT);
5831 for (unsigned i = 0; i != NumRegs; ++i)
5832 LoweredRetTys.push_back(RegisterVT);
5835 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5837 // Create the CALL node.
5838 SDValue Res = DAG.getCall(CallingConv, dl,
5839 isVarArg, isTailCall, isInreg,
5840 DAG.getVTList(&LoweredRetTys[0],
5841 LoweredRetTys.size()),
5844 Chain = Res.getValue(LoweredRetTys.size() - 1);
5846 // Gather up the call result into a single value.
5847 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5848 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5851 AssertOp = ISD::AssertSext;
5853 AssertOp = ISD::AssertZext;
5855 SmallVector<SDValue, 4> ReturnValues;
5857 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5859 MVT RegisterVT = getRegisterType(VT);
5860 unsigned NumRegs = getNumRegisters(VT);
5861 unsigned RegNoEnd = NumRegs + RegNo;
5862 SmallVector<SDValue, 4> Results;
5863 for (; RegNo != RegNoEnd; ++RegNo)
5864 Results.push_back(Res.getValue(RegNo));
5865 SDValue ReturnValue =
5866 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5868 ReturnValues.push_back(ReturnValue);
5870 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5871 DAG.getVTList(&RetTys[0], RetTys.size()),
5872 &ReturnValues[0], ReturnValues.size());
5875 return std::make_pair(Res, Chain);
5878 void TargetLowering::LowerOperationWrapper(SDNode *N,
5879 SmallVectorImpl<SDValue> &Results,
5880 SelectionDAG &DAG) {
5881 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5883 Results.push_back(Res);
5886 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5887 assert(0 && "LowerOperation not implemented for this target!");
5893 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5894 SDValue Op = getValue(V);
5895 assert((Op.getOpcode() != ISD::CopyFromReg ||
5896 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5897 "Copy from a reg to the same reg!");
5898 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5900 RegsForValue RFV(TLI, Reg, V->getType());
5901 SDValue Chain = DAG.getEntryNode();
5902 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5903 PendingExports.push_back(Chain);
5906 #include "llvm/CodeGen/SelectionDAGISel.h"
5908 void SelectionDAGISel::
5909 LowerArguments(BasicBlock *LLVMBB) {
5910 // If this is the entry block, emit arguments.
5911 Function &F = *LLVMBB->getParent();
5912 SDValue OldRoot = SDL->DAG.getRoot();
5913 SmallVector<SDValue, 16> Args;
5914 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5917 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5919 SmallVector<MVT, 4> ValueVTs;
5920 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5921 unsigned NumValues = ValueVTs.size();
5922 if (!AI->use_empty()) {
5923 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5924 SDL->getCurDebugLoc()));
5925 // If this argument is live outside of the entry block, insert a copy from
5926 // whereever we got it to the vreg that other BB's will reference it as.
5927 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5928 if (VMI != FuncInfo->ValueMap.end()) {
5929 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5935 // Finally, if the target has anything special to do, allow it to do so.
5936 // FIXME: this should insert code into the DAG!
5937 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5940 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5941 /// ensure constants are generated when needed. Remember the virtual registers
5942 /// that need to be added to the Machine PHI nodes as input. We cannot just
5943 /// directly add them, because expansion might result in multiple MBB's for one
5944 /// BB. As such, the start of the BB might correspond to a different MBB than
5948 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5949 TerminatorInst *TI = LLVMBB->getTerminator();
5951 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5953 // Check successor nodes' PHI nodes that expect a constant to be available
5955 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5956 BasicBlock *SuccBB = TI->getSuccessor(succ);
5957 if (!isa<PHINode>(SuccBB->begin())) continue;
5958 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5960 // If this terminator has multiple identical successors (common for
5961 // switches), only handle each succ once.
5962 if (!SuccsHandled.insert(SuccMBB)) continue;
5964 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5967 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5968 // nodes and Machine PHI nodes, but the incoming operands have not been
5970 for (BasicBlock::iterator I = SuccBB->begin();
5971 (PN = dyn_cast<PHINode>(I)); ++I) {
5972 // Ignore dead phi's.
5973 if (PN->use_empty()) continue;
5976 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5978 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5979 unsigned &RegOut = SDL->ConstantsOut[C];
5981 RegOut = FuncInfo->CreateRegForValue(C);
5982 SDL->CopyValueToVirtualRegister(C, RegOut);
5986 Reg = FuncInfo->ValueMap[PHIOp];
5988 assert(isa<AllocaInst>(PHIOp) &&
5989 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5990 "Didn't codegen value into a register!??");
5991 Reg = FuncInfo->CreateRegForValue(PHIOp);
5992 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5996 // Remember that this register needs to added to the machine PHI node as
5997 // the input for this MBB.
5998 SmallVector<MVT, 4> ValueVTs;
5999 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6000 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6001 MVT VT = ValueVTs[vti];
6002 unsigned NumRegisters = TLI.getNumRegisters(VT);
6003 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6004 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6005 Reg += NumRegisters;
6009 SDL->ConstantsOut.clear();
6012 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6013 /// supports legal types, and it emits MachineInstrs directly instead of
6014 /// creating SelectionDAG nodes.
6017 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6019 TerminatorInst *TI = LLVMBB->getTerminator();
6021 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6022 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6024 // Check successor nodes' PHI nodes that expect a constant to be available
6026 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6027 BasicBlock *SuccBB = TI->getSuccessor(succ);
6028 if (!isa<PHINode>(SuccBB->begin())) continue;
6029 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6031 // If this terminator has multiple identical successors (common for
6032 // switches), only handle each succ once.
6033 if (!SuccsHandled.insert(SuccMBB)) continue;
6035 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6038 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6039 // nodes and Machine PHI nodes, but the incoming operands have not been
6041 for (BasicBlock::iterator I = SuccBB->begin();
6042 (PN = dyn_cast<PHINode>(I)); ++I) {
6043 // Ignore dead phi's.
6044 if (PN->use_empty()) continue;
6046 // Only handle legal types. Two interesting things to note here. First,
6047 // by bailing out early, we may leave behind some dead instructions,
6048 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6049 // own moves. Second, this check is necessary becuase FastISel doesn't
6050 // use CreateRegForValue to create registers, so it always creates
6051 // exactly one register for each non-void instruction.
6052 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6053 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6056 VT = TLI.getTypeToTransformTo(VT);
6058 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6063 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6065 unsigned Reg = F->getRegForValue(PHIOp);
6067 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6070 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));