1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 /// LimitFloatPrecision - Generate low-precision inline sequences for
58 /// some float libcalls (6, 8 or 12 bits).
59 static unsigned LimitFloatPrecision;
61 static cl::opt<unsigned, true>
62 LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
68 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
69 /// of insertvalue or extractvalue indices that identify a member, return
70 /// the linearized index of the start of the member.
72 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
84 EE = STy->element_end();
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 // We haven't found the type we're looking for, so keep searching.
106 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107 /// MVTs that represent all the individual underlying
108 /// non-aggregate types that comprise it.
110 /// If Offsets is non-null, it points to a vector to be filled in
111 /// with the in-memory offsets of each of the individual values.
113 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
122 EE = STy->element_end();
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
137 // Base case: we can get an MVT for this LLVM IR type.
138 ValueVTs.push_back(TLI.getValueType(Ty));
140 Offsets->push_back(StartingOffset);
144 /// RegsForValue - This struct represents the registers (physical or virtual)
145 /// that a particular set of values is assigned, and the type information about
146 /// the value. The most common situation is to represent one value at a time,
147 /// but struct or array values are handled element-wise as multiple values.
148 /// The splitting of aggregates is performed recursively, so that we never
149 /// have aggregate-typed registers. The values at this point do not necessarily
150 /// have legal types, so each value may require one or more registers of some
153 struct VISIBILITY_HIDDEN RegsForValue {
154 /// TLI - The TargetLowering object.
156 const TargetLowering *TLI;
158 /// ValueVTs - The value types of the values, which may not be legal, and
159 /// may need be promoted or synthesized from one or more registers.
161 SmallVector<MVT, 4> ValueVTs;
163 /// RegVTs - The value types of the registers. This is the same size as
164 /// ValueVTs and it records, for each value, what the type of the assigned
165 /// register or registers are. (Individual values are never synthesized
166 /// from more than one type of register.)
168 /// With virtual registers, the contents of RegVTs is redundant with TLI's
169 /// getRegisterType member function, however when with physical registers
170 /// it is necessary to have a separate record of the types.
172 SmallVector<MVT, 4> RegVTs;
174 /// Regs - This list holds the registers assigned to the values.
175 /// Each legal or promoted value requires one register, and each
176 /// expanded value requires multiple registers.
178 SmallVector<unsigned, 4> Regs;
180 RegsForValue() : TLI(0) {}
182 RegsForValue(const TargetLowering &tli,
183 const SmallVector<unsigned, 4> ®s,
184 MVT regvt, MVT valuevt)
185 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 const SmallVector<MVT, 4> ®vts,
189 const SmallVector<MVT, 4> &valuevts)
190 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 unsigned Reg, const Type *Ty) : TLI(&tli) {
193 ComputeValueVTs(tli, Ty, ValueVTs);
195 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
196 MVT ValueVT = ValueVTs[Value];
197 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
198 MVT RegisterVT = TLI->getRegisterType(ValueVT);
199 for (unsigned i = 0; i != NumRegs; ++i)
200 Regs.push_back(Reg + i);
201 RegVTs.push_back(RegisterVT);
206 /// append - Add the specified values to this one.
207 void append(const RegsForValue &RHS) {
209 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
210 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
211 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
215 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
216 /// this value and returns the result as a ValueVTs value. This uses
217 /// Chain/Flag as the input and updates them for the output Chain/Flag.
218 /// If the Flag pointer is NULL, no flag is used.
219 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
220 SDValue &Chain, SDValue *Flag) const;
222 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
223 /// specified value into the registers specified by this object. This uses
224 /// Chain/Flag as the input and updates them for the output Chain/Flag.
225 /// If the Flag pointer is NULL, no flag is used.
226 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
227 SDValue &Chain, SDValue *Flag) const;
229 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
230 /// operand list. This adds the code marker and includes the number of
231 /// values added into it.
232 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
233 std::vector<SDValue> &Ops) const;
237 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
238 /// PHI nodes or outside of the basic block that defines it, or used by a
239 /// switch or atomic instruction, which may expand to multiple basic blocks.
240 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
241 if (isa<PHINode>(I)) return true;
242 BasicBlock *BB = I->getParent();
243 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
244 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
245 // FIXME: Remove switchinst special case.
246 isa<SwitchInst>(*UI))
251 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252 /// entry block, return true. This includes arguments used by switches, since
253 /// the switch may expand into multiple basic blocks.
254 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
260 return A->use_empty();
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
269 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
273 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
275 bool EnableFastISel) {
278 RegInfo = &MF->getRegInfo();
280 // Create a vreg for each argument register that is not dead and is used
281 // outside of the entry block for the function.
282 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
284 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
285 InitializeRegForValue(AI);
287 // Initialize the mapping of values to registers. This is only set up for
288 // instruction values that are used outside of the block that defines
290 Function::iterator BB = Fn->begin(), EB = Fn->end();
291 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
292 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
293 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
294 const Type *Ty = AI->getAllocatedType();
295 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
297 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
300 TySize *= CUI->getZExtValue(); // Get total allocated size.
301 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
302 StaticAllocaMap[AI] =
303 MF->getFrameInfo()->CreateStackObject(TySize, Align);
306 for (; BB != EB; ++BB)
307 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
308 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
309 if (!isa<AllocaInst>(I) ||
310 !StaticAllocaMap.count(cast<AllocaInst>(I)))
311 InitializeRegForValue(I);
313 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
314 // also creates the initial PHI MachineInstrs, though none of the input
315 // operands are populated.
316 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
317 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
321 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
325 for (BasicBlock::iterator
326 I = BB->begin(), E = BB->end(); I != E; ++I) {
327 if (CallInst *CI = dyn_cast<CallInst>(I)) {
328 if (Function *F = CI->getCalledFunction()) {
329 switch (F->getIntrinsicID()) {
331 case Intrinsic::dbg_stoppoint: {
332 DwarfWriter *DW = DAG.getDwarfWriter();
333 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
335 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
336 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
337 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
339 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
342 DL = DebugLoc::get(idx);
347 case Intrinsic::dbg_func_start: {
348 DwarfWriter *DW = DAG.getDwarfWriter();
350 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
351 Value *SP = FSI->getSubprogram();
353 if (DW->ValidDebugInfo(SP)) {
354 DISubprogram Subprogram(cast<GlobalVariable>(SP));
355 DICompileUnit CU(Subprogram.getCompileUnit());
356 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
358 unsigned Line = Subprogram.getLineNumber();
359 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
369 PN = dyn_cast<PHINode>(I);
370 if (!PN || PN->use_empty()) continue;
372 unsigned PHIReg = ValueMap[PN];
373 assert(PHIReg && "PHI node does not have an assigned virtual register!");
375 SmallVector<MVT, 4> ValueVTs;
376 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
377 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
378 MVT VT = ValueVTs[vti];
379 unsigned NumRegisters = TLI.getNumRegisters(VT);
380 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
381 for (unsigned i = 0; i != NumRegisters; ++i)
382 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
383 PHIReg += NumRegisters;
389 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
390 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
393 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
394 /// the correctly promoted or expanded types. Assign these registers
395 /// consecutive vreg numbers and return the first assigned number.
397 /// In the case that the given value has struct or array type, this function
398 /// will assign registers for each member or element.
400 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
401 SmallVector<MVT, 4> ValueVTs;
402 ComputeValueVTs(TLI, V->getType(), ValueVTs);
404 unsigned FirstReg = 0;
405 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
406 MVT ValueVT = ValueVTs[Value];
407 MVT RegisterVT = TLI.getRegisterType(ValueVT);
409 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
410 for (unsigned i = 0; i != NumRegs; ++i) {
411 unsigned R = MakeReg(RegisterVT);
412 if (!FirstReg) FirstReg = R;
418 /// getCopyFromParts - Create a value that contains the specified legal parts
419 /// combined into the value they represent. If the parts combine to a type
420 /// larger then ValueVT then AssertOp can be used to specify whether the extra
421 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
422 /// (ISD::AssertSext).
423 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
424 const SDValue *Parts,
425 unsigned NumParts, MVT PartVT, MVT ValueVT,
426 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
427 assert(NumParts > 0 && "No parts to assemble!");
428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
429 SDValue Val = Parts[0];
432 // Assemble the value from multiple parts.
433 if (!ValueVT.isVector()) {
434 unsigned PartBits = PartVT.getSizeInBits();
435 unsigned ValueBits = ValueVT.getSizeInBits();
437 // Assemble the power of 2 part.
438 unsigned RoundParts = NumParts & (NumParts - 1) ?
439 1 << Log2_32(NumParts) : NumParts;
440 unsigned RoundBits = PartBits * RoundParts;
441 MVT RoundVT = RoundBits == ValueBits ?
442 ValueVT : MVT::getIntegerVT(RoundBits);
445 MVT HalfVT = ValueVT.isInteger() ?
446 MVT::getIntegerVT(RoundBits/2) :
447 MVT::getFloatingPointVT(RoundBits/2);
449 if (RoundParts > 2) {
450 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
451 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
454 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
455 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
457 if (TLI.isBigEndian())
459 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
461 if (RoundParts < NumParts) {
462 // Assemble the trailing non-power-of-2 part.
463 unsigned OddParts = NumParts - RoundParts;
464 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
465 Hi = getCopyFromParts(DAG, dl,
466 Parts+RoundParts, OddParts, PartVT, OddVT);
468 // Combine the round and odd parts.
470 if (TLI.isBigEndian())
472 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
473 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
474 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
475 DAG.getConstant(Lo.getValueType().getSizeInBits(),
476 TLI.getPointerTy()));
477 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
478 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
481 // Handle a multi-element vector.
482 MVT IntermediateVT, RegisterVT;
483 unsigned NumIntermediates;
485 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
487 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
488 NumParts = NumRegs; // Silence a compiler warning.
489 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
490 assert(RegisterVT == Parts[0].getValueType() &&
491 "Part type doesn't match part!");
493 // Assemble the parts into intermediate operands.
494 SmallVector<SDValue, 8> Ops(NumIntermediates);
495 if (NumIntermediates == NumParts) {
496 // If the register was not expanded, truncate or copy the value,
498 for (unsigned i = 0; i != NumParts; ++i)
499 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
500 PartVT, IntermediateVT);
501 } else if (NumParts > 0) {
502 // If the intermediate type was expanded, build the intermediate operands
504 assert(NumParts % NumIntermediates == 0 &&
505 "Must expand into a divisible number of parts!");
506 unsigned Factor = NumParts / NumIntermediates;
507 for (unsigned i = 0; i != NumIntermediates; ++i)
508 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
509 PartVT, IntermediateVT);
512 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
514 Val = DAG.getNode(IntermediateVT.isVector() ?
515 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
516 ValueVT, &Ops[0], NumIntermediates);
520 // There is now one part, held in Val. Correct it to match ValueVT.
521 PartVT = Val.getValueType();
523 if (PartVT == ValueVT)
526 if (PartVT.isVector()) {
527 assert(ValueVT.isVector() && "Unknown vector conversion!");
528 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
531 if (ValueVT.isVector()) {
532 assert(ValueVT.getVectorElementType() == PartVT &&
533 ValueVT.getVectorNumElements() == 1 &&
534 "Only trivial scalar-to-vector conversions should get here!");
535 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
538 if (PartVT.isInteger() &&
539 ValueVT.isInteger()) {
540 if (ValueVT.bitsLT(PartVT)) {
541 // For a truncate, see if we have any information to
542 // indicate whether the truncated bits will always be
543 // zero or sign-extension.
544 if (AssertOp != ISD::DELETED_NODE)
545 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
546 DAG.getValueType(ValueVT));
547 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
549 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
553 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
554 if (ValueVT.bitsLT(Val.getValueType()))
555 // FP_ROUND's are always exact here.
556 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
557 DAG.getIntPtrConstant(1));
558 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
561 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
562 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
564 assert(0 && "Unknown mismatch!");
568 /// getCopyToParts - Create a series of nodes that contain the specified value
569 /// split into legal parts. If the parts contain more bits than Val, then, for
570 /// integers, ExtendKind can be used to specify how to generate the extra bits.
571 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
572 SDValue *Parts, unsigned NumParts, MVT PartVT,
573 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
575 MVT PtrVT = TLI.getPointerTy();
576 MVT ValueVT = Val.getValueType();
577 unsigned PartBits = PartVT.getSizeInBits();
578 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
583 if (!ValueVT.isVector()) {
584 if (PartVT == ValueVT) {
585 assert(NumParts == 1 && "No-op copy with multiple parts!");
590 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
591 // If the parts cover more bits than the value has, promote the value.
592 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
593 assert(NumParts == 1 && "Do not know what to promote to!");
594 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
595 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
596 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
597 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
599 assert(0 && "Unknown mismatch!");
601 } else if (PartBits == ValueVT.getSizeInBits()) {
602 // Different types of the same size.
603 assert(NumParts == 1 && PartVT != ValueVT);
604 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
605 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
606 // If the parts cover less bits than value has, truncate the value.
607 if (PartVT.isInteger() && ValueVT.isInteger()) {
608 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
609 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
611 assert(0 && "Unknown mismatch!");
615 // The value may have changed - recompute ValueVT.
616 ValueVT = Val.getValueType();
617 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
618 "Failed to tile the value with PartVT!");
621 assert(PartVT == ValueVT && "Type conversion failed!");
626 // Expand the value into multiple parts.
627 if (NumParts & (NumParts - 1)) {
628 // The number of parts is not a power of 2. Split off and copy the tail.
629 assert(PartVT.isInteger() && ValueVT.isInteger() &&
630 "Do not know what to expand to!");
631 unsigned RoundParts = 1 << Log2_32(NumParts);
632 unsigned RoundBits = RoundParts * PartBits;
633 unsigned OddParts = NumParts - RoundParts;
634 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
635 DAG.getConstant(RoundBits,
636 TLI.getPointerTy()));
637 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
638 if (TLI.isBigEndian())
639 // The odd parts were reversed by getCopyToParts - unreverse them.
640 std::reverse(Parts + RoundParts, Parts + NumParts);
641 NumParts = RoundParts;
642 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
643 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
646 // The number of parts is a power of 2. Repeatedly bisect the value using
648 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
649 MVT::getIntegerVT(ValueVT.getSizeInBits()),
651 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
652 for (unsigned i = 0; i < NumParts; i += StepSize) {
653 unsigned ThisBits = StepSize * PartBits / 2;
654 MVT ThisVT = MVT::getIntegerVT (ThisBits);
655 SDValue &Part0 = Parts[i];
656 SDValue &Part1 = Parts[i+StepSize/2];
658 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(1, PtrVT));
661 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
663 DAG.getConstant(0, PtrVT));
665 if (ThisBits == PartBits && ThisVT != PartVT) {
666 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
668 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 if (TLI.isBigEndian())
675 std::reverse(Parts, Parts + NumParts);
682 if (PartVT != ValueVT) {
683 if (PartVT.isVector()) {
684 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
686 assert(ValueVT.getVectorElementType() == PartVT &&
687 ValueVT.getVectorNumElements() == 1 &&
688 "Only trivial vector-to-scalar conversions should get here!");
689 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
691 DAG.getConstant(0, PtrVT));
699 // Handle a multi-element vector.
700 MVT IntermediateVT, RegisterVT;
701 unsigned NumIntermediates;
702 unsigned NumRegs = TLI
703 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
705 unsigned NumElements = ValueVT.getVectorNumElements();
707 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
708 NumParts = NumRegs; // Silence a compiler warning.
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
711 // Split the vector into intermediate operands.
712 SmallVector<SDValue, 8> Ops(NumIntermediates);
713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 if (IntermediateVT.isVector())
715 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
717 DAG.getConstant(i * (NumElements / NumIntermediates),
720 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
722 DAG.getConstant(i, PtrVT));
724 // Split the intermediate operands into legal parts.
725 if (NumParts == NumIntermediates) {
726 // If the register was not expanded, promote or copy the value,
728 for (unsigned i = 0; i != NumParts; ++i)
729 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
730 } else if (NumParts > 0) {
731 // If the intermediate type was expanded, split each the value into
733 assert(NumParts % NumIntermediates == 0 &&
734 "Must expand into a divisible number of parts!");
735 unsigned Factor = NumParts / NumIntermediates;
736 for (unsigned i = 0; i != NumIntermediates; ++i)
737 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
742 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
745 TD = DAG.getTarget().getTargetData();
748 /// clear - Clear out the curret SelectionDAG and the associated
749 /// state and prepare this SelectionDAGLowering object to be used
750 /// for a new block. This doesn't clear out information about
751 /// additional blocks that are needed to complete switch lowering
752 /// or PHI node updating; that information is cleared out as it is
754 void SelectionDAGLowering::clear() {
756 PendingLoads.clear();
757 PendingExports.clear();
761 /// getRoot - Return the current virtual root of the Selection DAG,
762 /// flushing any PendingLoad items. This must be done before emitting
763 /// a store or any other node that may need to be ordered after any
764 /// prior load instructions.
766 SDValue SelectionDAGLowering::getRoot() {
767 if (PendingLoads.empty())
768 return DAG.getRoot();
770 if (PendingLoads.size() == 1) {
771 SDValue Root = PendingLoads[0];
773 PendingLoads.clear();
777 // Otherwise, we have to make a token factor node.
778 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
779 &PendingLoads[0], PendingLoads.size());
780 PendingLoads.clear();
785 /// getControlRoot - Similar to getRoot, but instead of flushing all the
786 /// PendingLoad items, flush all the PendingExports items. It is necessary
787 /// to do this before emitting a terminator instruction.
789 SDValue SelectionDAGLowering::getControlRoot() {
790 SDValue Root = DAG.getRoot();
792 if (PendingExports.empty())
795 // Turn all of the CopyToReg chains into one factored node.
796 if (Root.getOpcode() != ISD::EntryToken) {
797 unsigned i = 0, e = PendingExports.size();
798 for (; i != e; ++i) {
799 assert(PendingExports[i].getNode()->getNumOperands() > 1);
800 if (PendingExports[i].getNode()->getOperand(0) == Root)
801 break; // Don't add the root if we already indirectly depend on it.
805 PendingExports.push_back(Root);
808 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
810 PendingExports.size());
811 PendingExports.clear();
816 void SelectionDAGLowering::visit(Instruction &I) {
817 visit(I.getOpcode(), I);
820 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
821 // Note: this doesn't use InstVisitor, because it has to work with
822 // ConstantExpr's in addition to instructions.
824 default: assert(0 && "Unknown instruction type encountered!");
826 // Build the switch statement using the Instruction.def file.
827 #define HANDLE_INST(NUM, OPCODE, CLASS) \
828 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
829 #include "llvm/Instruction.def"
833 void SelectionDAGLowering::visitAdd(User &I) {
834 if (I.getType()->isFPOrFPVector())
835 visitBinary(I, ISD::FADD);
837 visitBinary(I, ISD::ADD);
840 void SelectionDAGLowering::visitMul(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FMUL);
844 visitBinary(I, ISD::MUL);
847 SDValue SelectionDAGLowering::getValue(const Value *V) {
848 SDValue &N = NodeMap[V];
849 if (N.getNode()) return N;
851 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
852 MVT VT = TLI.getValueType(V->getType(), true);
854 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
855 return N = DAG.getConstant(*CI, VT);
857 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
858 return N = DAG.getGlobalAddress(GV, VT);
860 if (isa<ConstantPointerNull>(C))
861 return N = DAG.getConstant(0, TLI.getPointerTy());
863 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
864 return N = DAG.getConstantFP(*CFP, VT);
866 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
867 !V->getType()->isAggregateType())
868 return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
870 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
871 visit(CE->getOpcode(), *CE);
872 SDValue N1 = NodeMap[V];
873 assert(N1.getNode() && "visit didn't populate the ValueMap!");
877 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
878 SmallVector<SDValue, 4> Constants;
879 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
881 SDNode *Val = getValue(*OI).getNode();
882 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
883 Constants.push_back(SDValue(Val, i));
885 return DAG.getMergeValues(&Constants[0], Constants.size());
888 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
889 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
890 "Unknown struct or array constant!");
892 SmallVector<MVT, 4> ValueVTs;
893 ComputeValueVTs(TLI, C->getType(), ValueVTs);
894 unsigned NumElts = ValueVTs.size();
896 return SDValue(); // empty struct
897 SmallVector<SDValue, 4> Constants(NumElts);
898 for (unsigned i = 0; i != NumElts; ++i) {
899 MVT EltVT = ValueVTs[i];
900 if (isa<UndefValue>(C))
901 Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
902 else if (EltVT.isFloatingPoint())
903 Constants[i] = DAG.getConstantFP(0, EltVT);
905 Constants[i] = DAG.getConstant(0, EltVT);
907 return DAG.getMergeValues(&Constants[0], NumElts);
910 const VectorType *VecTy = cast<VectorType>(V->getType());
911 unsigned NumElements = VecTy->getNumElements();
913 // Now that we know the number and type of the elements, get that number of
914 // elements into the Ops array based on what kind of constant it is.
915 SmallVector<SDValue, 16> Ops;
916 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
917 for (unsigned i = 0; i != NumElements; ++i)
918 Ops.push_back(getValue(CP->getOperand(i)));
920 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
921 "Unknown vector constant!");
922 MVT EltVT = TLI.getValueType(VecTy->getElementType());
925 if (isa<UndefValue>(C))
926 Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
927 else if (EltVT.isFloatingPoint())
928 Op = DAG.getConstantFP(0, EltVT);
930 Op = DAG.getConstant(0, EltVT);
931 Ops.assign(NumElements, Op);
934 // Create a BUILD_VECTOR node.
935 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
936 VT, &Ops[0], Ops.size());
939 // If this is a static alloca, generate it as the frameindex instead of
941 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
942 DenseMap<const AllocaInst*, int>::iterator SI =
943 FuncInfo.StaticAllocaMap.find(AI);
944 if (SI != FuncInfo.StaticAllocaMap.end())
945 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
948 unsigned InReg = FuncInfo.ValueMap[V];
949 assert(InReg && "Value not in map!");
951 RegsForValue RFV(TLI, InReg, V->getType());
952 SDValue Chain = DAG.getEntryNode();
953 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
957 void SelectionDAGLowering::visitRet(ReturnInst &I) {
958 if (I.getNumOperands() == 0) {
959 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
960 MVT::Other, getControlRoot()));
964 SmallVector<SDValue, 8> NewValues;
965 NewValues.push_back(getControlRoot());
966 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
967 SmallVector<MVT, 4> ValueVTs;
968 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
969 unsigned NumValues = ValueVTs.size();
970 if (NumValues == 0) continue;
972 SDValue RetOp = getValue(I.getOperand(i));
973 for (unsigned j = 0, f = NumValues; j != f; ++j) {
974 MVT VT = ValueVTs[j];
976 // FIXME: C calling convention requires the return type to be promoted to
977 // at least 32-bit. But this is not necessary for non-C calling
979 if (VT.isInteger()) {
980 MVT MinVT = TLI.getRegisterType(MVT::i32);
981 if (VT.bitsLT(MinVT))
985 unsigned NumParts = TLI.getNumRegisters(VT);
986 MVT PartVT = TLI.getRegisterType(VT);
987 SmallVector<SDValue, 4> Parts(NumParts);
988 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
990 const Function *F = I.getParent()->getParent();
991 if (F->paramHasAttr(0, Attribute::SExt))
992 ExtendKind = ISD::SIGN_EXTEND;
993 else if (F->paramHasAttr(0, Attribute::ZExt))
994 ExtendKind = ISD::ZERO_EXTEND;
996 getCopyToParts(DAG, getCurDebugLoc(),
997 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
998 &Parts[0], NumParts, PartVT, ExtendKind);
1000 // 'inreg' on function refers to return value
1001 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1002 if (F->paramHasAttr(0, Attribute::InReg))
1004 for (unsigned i = 0; i < NumParts; ++i) {
1005 NewValues.push_back(Parts[i]);
1006 NewValues.push_back(DAG.getArgFlags(Flags));
1010 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1011 &NewValues[0], NewValues.size()));
1014 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1015 /// the current basic block, add it to ValueMap now so that we'll get a
1017 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1018 // No need to export constants.
1019 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1021 // Already exported?
1022 if (FuncInfo.isExportedInst(V)) return;
1024 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1025 CopyValueToVirtualRegister(V, Reg);
1028 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1029 const BasicBlock *FromBB) {
1030 // The operands of the setcc have to be in this block. We don't know
1031 // how to export them from some other block.
1032 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1033 // Can export from current BB.
1034 if (VI->getParent() == FromBB)
1037 // Is already exported, noop.
1038 return FuncInfo.isExportedInst(V);
1041 // If this is an argument, we can export it if the BB is the entry block or
1042 // if it is already exported.
1043 if (isa<Argument>(V)) {
1044 if (FromBB == &FromBB->getParent()->getEntryBlock())
1047 // Otherwise, can only export this if it is already exported.
1048 return FuncInfo.isExportedInst(V);
1051 // Otherwise, constants can always be exported.
1055 static bool InBlock(const Value *V, const BasicBlock *BB) {
1056 if (const Instruction *I = dyn_cast<Instruction>(V))
1057 return I->getParent() == BB;
1061 /// getFCmpCondCode - Return the ISD condition code corresponding to
1062 /// the given LLVM IR floating-point condition code. This includes
1063 /// consideration of global floating-point math flags.
1065 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1066 ISD::CondCode FPC, FOC;
1068 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1069 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1070 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1071 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1072 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1073 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1074 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1075 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1076 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1077 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1078 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1079 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1080 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1081 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1082 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1083 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1085 assert(0 && "Invalid FCmp predicate opcode!");
1086 FOC = FPC = ISD::SETFALSE;
1089 if (FiniteOnlyFPMath())
1095 /// getICmpCondCode - Return the ISD condition code corresponding to
1096 /// the given LLVM IR integer condition code.
1098 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1100 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1101 case ICmpInst::ICMP_NE: return ISD::SETNE;
1102 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1103 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1104 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1105 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1106 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1107 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1108 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1109 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1111 assert(0 && "Invalid ICmp predicate opcode!");
1116 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1117 /// This function emits a branch and is used at the leaves of an OR or an
1118 /// AND operator tree.
1121 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1122 MachineBasicBlock *TBB,
1123 MachineBasicBlock *FBB,
1124 MachineBasicBlock *CurBB) {
1125 const BasicBlock *BB = CurBB->getBasicBlock();
1127 // If the leaf of the tree is a comparison, merge the condition into
1129 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1130 // The operands of the cmp have to be in this block. We don't know
1131 // how to export them from some other block. If this is the first block
1132 // of the sequence, no exporting is needed.
1133 if (CurBB == CurMBB ||
1134 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1135 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1136 ISD::CondCode Condition;
1137 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1138 Condition = getICmpCondCode(IC->getPredicate());
1139 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1140 Condition = getFCmpCondCode(FC->getPredicate());
1142 Condition = ISD::SETEQ; // silence warning.
1143 assert(0 && "Unknown compare instruction");
1146 CaseBlock CB(Condition, BOp->getOperand(0),
1147 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1148 SwitchCases.push_back(CB);
1153 // Create a CaseBlock record representing this branch.
1154 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1155 NULL, TBB, FBB, CurBB);
1156 SwitchCases.push_back(CB);
1159 /// FindMergedConditions - If Cond is an expression like
1160 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1161 MachineBasicBlock *TBB,
1162 MachineBasicBlock *FBB,
1163 MachineBasicBlock *CurBB,
1165 // If this node is not part of the or/and tree, emit it as a branch.
1166 Instruction *BOp = dyn_cast<Instruction>(Cond);
1167 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1168 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1169 BOp->getParent() != CurBB->getBasicBlock() ||
1170 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1171 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1172 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1176 // Create TmpBB after CurBB.
1177 MachineFunction::iterator BBI = CurBB;
1178 MachineFunction &MF = DAG.getMachineFunction();
1179 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1180 CurBB->getParent()->insert(++BBI, TmpBB);
1182 if (Opc == Instruction::Or) {
1183 // Codegen X | Y as:
1191 // Emit the LHS condition.
1192 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1194 // Emit the RHS condition into TmpBB.
1195 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1197 assert(Opc == Instruction::And && "Unknown merge op!");
1198 // Codegen X & Y as:
1205 // This requires creation of TmpBB after CurBB.
1207 // Emit the LHS condition.
1208 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1210 // Emit the RHS condition into TmpBB.
1211 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1215 /// If the set of cases should be emitted as a series of branches, return true.
1216 /// If we should emit this as a bunch of and/or'd together conditions, return
1219 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1220 if (Cases.size() != 2) return true;
1222 // If this is two comparisons of the same values or'd or and'd together, they
1223 // will get folded into a single comparison, so don't emit two blocks.
1224 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1225 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1226 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1227 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1234 void SelectionDAGLowering::visitBr(BranchInst &I) {
1235 // Update machine-CFG edges.
1236 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1238 // Figure out which block is immediately after the current one.
1239 MachineBasicBlock *NextBlock = 0;
1240 MachineFunction::iterator BBI = CurMBB;
1241 if (++BBI != CurMBB->getParent()->end())
1244 if (I.isUnconditional()) {
1245 // Update machine-CFG edges.
1246 CurMBB->addSuccessor(Succ0MBB);
1248 // If this is not a fall-through branch, emit the branch.
1249 if (Succ0MBB != NextBlock)
1250 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1251 MVT::Other, getControlRoot(),
1252 DAG.getBasicBlock(Succ0MBB)));
1256 // If this condition is one of the special cases we handle, do special stuff
1258 Value *CondVal = I.getCondition();
1259 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1261 // If this is a series of conditions that are or'd or and'd together, emit
1262 // this as a sequence of branches instead of setcc's with and/or operations.
1263 // For example, instead of something like:
1276 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1277 if (BOp->hasOneUse() &&
1278 (BOp->getOpcode() == Instruction::And ||
1279 BOp->getOpcode() == Instruction::Or)) {
1280 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1281 // If the compares in later blocks need to use values not currently
1282 // exported from this block, export them now. This block should always
1283 // be the first entry.
1284 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1286 // Allow some cases to be rejected.
1287 if (ShouldEmitAsBranches(SwitchCases)) {
1288 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1289 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1290 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1293 // Emit the branch for this block.
1294 visitSwitchCase(SwitchCases[0]);
1295 SwitchCases.erase(SwitchCases.begin());
1299 // Okay, we decided not to do this, remove any inserted MBB's and clear
1301 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1302 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1304 SwitchCases.clear();
1308 // Create a CaseBlock record representing this branch.
1309 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1310 NULL, Succ0MBB, Succ1MBB, CurMBB);
1311 // Use visitSwitchCase to actually insert the fast branch sequence for this
1313 visitSwitchCase(CB);
1316 /// visitSwitchCase - Emits the necessary code to represent a single node in
1317 /// the binary search tree resulting from lowering a switch instruction.
1318 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1320 SDValue CondLHS = getValue(CB.CmpLHS);
1322 // Build the setcc now.
1323 if (CB.CmpMHS == NULL) {
1324 // Fold "(X == true)" to X and "(X == false)" to !X to
1325 // handle common cases produced by branch lowering.
1326 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1328 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1329 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1330 Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
1331 CondLHS.getValueType(), CondLHS, True);
1333 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1335 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1337 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1338 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1340 SDValue CmpOp = getValue(CB.CmpMHS);
1341 MVT VT = CmpOp.getValueType();
1343 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1344 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1346 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(),
1347 VT, CmpOp, DAG.getConstant(Low, VT));
1348 Cond = DAG.getSetCC(MVT::i1, SUB,
1349 DAG.getConstant(High-Low, VT), ISD::SETULE);
1353 // Update successor info
1354 CurMBB->addSuccessor(CB.TrueBB);
1355 CurMBB->addSuccessor(CB.FalseBB);
1357 // Set NextBlock to be the MBB immediately after the current one, if any.
1358 // This is used to avoid emitting unnecessary branches to the next block.
1359 MachineBasicBlock *NextBlock = 0;
1360 MachineFunction::iterator BBI = CurMBB;
1361 if (++BBI != CurMBB->getParent()->end())
1364 // If the lhs block is the next block, invert the condition so that we can
1365 // fall through to the lhs instead of the rhs block.
1366 if (CB.TrueBB == NextBlock) {
1367 std::swap(CB.TrueBB, CB.FalseBB);
1368 SDValue True = DAG.getConstant(1, Cond.getValueType());
1369 Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
1370 Cond.getValueType(), Cond, True);
1372 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1373 MVT::Other, getControlRoot(), Cond,
1374 DAG.getBasicBlock(CB.TrueBB));
1376 // If the branch was constant folded, fix up the CFG.
1377 if (BrCond.getOpcode() == ISD::BR) {
1378 CurMBB->removeSuccessor(CB.FalseBB);
1379 DAG.setRoot(BrCond);
1381 // Otherwise, go ahead and insert the false branch.
1382 if (BrCond == getControlRoot())
1383 CurMBB->removeSuccessor(CB.TrueBB);
1385 if (CB.FalseBB == NextBlock)
1386 DAG.setRoot(BrCond);
1388 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1389 DAG.getBasicBlock(CB.FalseBB)));
1393 /// visitJumpTable - Emit JumpTable node in the current MBB
1394 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1395 // Emit the code for the jump table
1396 assert(JT.Reg != -1U && "Should lower JT Header first!");
1397 MVT PTy = TLI.getPointerTy();
1398 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1399 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1400 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1401 MVT::Other, Index.getValue(1),
1405 /// visitJumpTableHeader - This function emits necessary code to produce index
1406 /// in the JumpTable from switch case.
1407 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1408 JumpTableHeader &JTH) {
1409 // Subtract the lowest switch case value from the value being switched on and
1410 // conditional branch to default mbb if the result is greater than the
1411 // difference between smallest and largest cases.
1412 SDValue SwitchOp = getValue(JTH.SValue);
1413 MVT VT = SwitchOp.getValueType();
1414 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1415 DAG.getConstant(JTH.First, VT));
1417 // The SDNode we just created, which holds the value being switched on minus
1418 // the the smallest case value, needs to be copied to a virtual register so it
1419 // can be used as an index into the jump table in a subsequent basic block.
1420 // This value may be smaller or larger than the target's pointer type, and
1421 // therefore require extension or truncating.
1422 if (VT.bitsGT(TLI.getPointerTy()))
1423 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1424 TLI.getPointerTy(), SUB);
1426 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1427 TLI.getPointerTy(), SUB);
1429 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1430 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1431 JT.Reg = JumpTableReg;
1433 // Emit the range check for the jump table, and branch to the default block
1434 // for the switch statement if the value being switched on exceeds the largest
1435 // case in the switch.
1436 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
1437 DAG.getConstant(JTH.Last-JTH.First,VT),
1440 // Set NextBlock to be the MBB immediately after the current one, if any.
1441 // This is used to avoid emitting unnecessary branches to the next block.
1442 MachineBasicBlock *NextBlock = 0;
1443 MachineFunction::iterator BBI = CurMBB;
1444 if (++BBI != CurMBB->getParent()->end())
1447 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1448 MVT::Other, CopyTo, CMP,
1449 DAG.getBasicBlock(JT.Default));
1451 if (JT.MBB == NextBlock)
1452 DAG.setRoot(BrCond);
1454 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1455 DAG.getBasicBlock(JT.MBB)));
1458 /// visitBitTestHeader - This function emits necessary code to produce value
1459 /// suitable for "bit tests"
1460 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1461 // Subtract the minimum value
1462 SDValue SwitchOp = getValue(B.SValue);
1463 MVT VT = SwitchOp.getValueType();
1464 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1465 DAG.getConstant(B.First, VT));
1468 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
1469 DAG.getConstant(B.Range, VT),
1473 if (VT.bitsGT(TLI.getPointerTy()))
1474 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1475 TLI.getPointerTy(), SUB);
1477 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1478 TLI.getPointerTy(), SUB);
1480 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1481 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp);
1483 // Set NextBlock to be the MBB immediately after the current one, if any.
1484 // This is used to avoid emitting unnecessary branches to the next block.
1485 MachineBasicBlock *NextBlock = 0;
1486 MachineFunction::iterator BBI = CurMBB;
1487 if (++BBI != CurMBB->getParent()->end())
1490 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1492 CurMBB->addSuccessor(B.Default);
1493 CurMBB->addSuccessor(MBB);
1495 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1496 MVT::Other, CopyTo, RangeCmp,
1497 DAG.getBasicBlock(B.Default));
1499 if (MBB == NextBlock)
1500 DAG.setRoot(BrRange);
1502 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1503 DAG.getBasicBlock(MBB)));
1506 /// visitBitTestCase - this function produces one "bit test"
1507 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1510 // Make desired shift
1511 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg,
1512 TLI.getPointerTy());
1513 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1515 DAG.getConstant(1, TLI.getPointerTy()),
1518 // Emit bit tests and jumps
1519 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1520 TLI.getPointerTy(), SwitchVal,
1521 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1522 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
1523 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1526 CurMBB->addSuccessor(B.TargetBB);
1527 CurMBB->addSuccessor(NextMBB);
1529 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1530 MVT::Other, getControlRoot(),
1531 AndCmp, DAG.getBasicBlock(B.TargetBB));
1533 // Set NextBlock to be the MBB immediately after the current one, if any.
1534 // This is used to avoid emitting unnecessary branches to the next block.
1535 MachineBasicBlock *NextBlock = 0;
1536 MachineFunction::iterator BBI = CurMBB;
1537 if (++BBI != CurMBB->getParent()->end())
1540 if (NextMBB == NextBlock)
1543 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1544 DAG.getBasicBlock(NextMBB)));
1547 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1548 // Retrieve successors.
1549 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1550 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1552 const Value *Callee(I.getCalledValue());
1553 if (isa<InlineAsm>(Callee))
1556 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1558 // If the value of the invoke is used outside of its defining block, make it
1559 // available as a virtual register.
1560 if (!I.use_empty()) {
1561 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1562 if (VMI != FuncInfo.ValueMap.end())
1563 CopyValueToVirtualRegister(&I, VMI->second);
1566 // Update successor info
1567 CurMBB->addSuccessor(Return);
1568 CurMBB->addSuccessor(LandingPad);
1570 // Drop into normal successor.
1571 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1572 MVT::Other, getControlRoot(),
1573 DAG.getBasicBlock(Return)));
1576 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1579 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1580 /// small case ranges).
1581 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1582 CaseRecVector& WorkList,
1584 MachineBasicBlock* Default) {
1585 Case& BackCase = *(CR.Range.second-1);
1587 // Size is the number of Cases represented by this range.
1588 size_t Size = CR.Range.second - CR.Range.first;
1592 // Get the MachineFunction which holds the current MBB. This is used when
1593 // inserting any additional MBBs necessary to represent the switch.
1594 MachineFunction *CurMF = CurMBB->getParent();
1596 // Figure out which block is immediately after the current one.
1597 MachineBasicBlock *NextBlock = 0;
1598 MachineFunction::iterator BBI = CR.CaseBB;
1600 if (++BBI != CurMBB->getParent()->end())
1603 // TODO: If any two of the cases has the same destination, and if one value
1604 // is the same as the other, but has one bit unset that the other has set,
1605 // use bit manipulation to do two compares at once. For example:
1606 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1608 // Rearrange the case blocks so that the last one falls through if possible.
1609 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1610 // The last case block won't fall through into 'NextBlock' if we emit the
1611 // branches in this order. See if rearranging a case value would help.
1612 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1613 if (I->BB == NextBlock) {
1614 std::swap(*I, BackCase);
1620 // Create a CaseBlock record representing a conditional branch to
1621 // the Case's target mbb if the value being switched on SV is equal
1623 MachineBasicBlock *CurBlock = CR.CaseBB;
1624 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1625 MachineBasicBlock *FallThrough;
1627 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1628 CurMF->insert(BBI, FallThrough);
1630 // If the last case doesn't match, go to the default block.
1631 FallThrough = Default;
1634 Value *RHS, *LHS, *MHS;
1636 if (I->High == I->Low) {
1637 // This is just small small case range :) containing exactly 1 case
1639 LHS = SV; RHS = I->High; MHS = NULL;
1642 LHS = I->Low; MHS = SV; RHS = I->High;
1644 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1646 // If emitting the first comparison, just call visitSwitchCase to emit the
1647 // code into the current block. Otherwise, push the CaseBlock onto the
1648 // vector to be later processed by SDISel, and insert the node's MBB
1649 // before the next MBB.
1650 if (CurBlock == CurMBB)
1651 visitSwitchCase(CB);
1653 SwitchCases.push_back(CB);
1655 CurBlock = FallThrough;
1661 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1662 return !DisableJumpTables &&
1663 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1664 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1667 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1668 APInt LastExt(Last), FirstExt(First);
1669 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1670 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1671 return (LastExt - FirstExt + 1ULL);
1674 /// handleJTSwitchCase - Emit jumptable for current switch case range
1675 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1676 CaseRecVector& WorkList,
1678 MachineBasicBlock* Default) {
1679 Case& FrontCase = *CR.Range.first;
1680 Case& BackCase = *(CR.Range.second-1);
1682 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1683 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1686 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1690 if (!areJTsAllowed(TLI) || TSize <= 3)
1693 APInt Range = ComputeRange(First, Last);
1694 double Density = (double)TSize / Range.roundToDouble();
1698 DEBUG(errs() << "Lowering jump table\n"
1699 << "First entry: " << First << ". Last entry: " << Last << '\n'
1700 << "Range: " << Range
1701 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1703 // Get the MachineFunction which holds the current MBB. This is used when
1704 // inserting any additional MBBs necessary to represent the switch.
1705 MachineFunction *CurMF = CurMBB->getParent();
1707 // Figure out which block is immediately after the current one.
1708 MachineBasicBlock *NextBlock = 0;
1709 MachineFunction::iterator BBI = CR.CaseBB;
1711 if (++BBI != CurMBB->getParent()->end())
1714 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1716 // Create a new basic block to hold the code for loading the address
1717 // of the jump table, and jumping to it. Update successor information;
1718 // we will either branch to the default case for the switch, or the jump
1720 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1721 CurMF->insert(BBI, JumpTableBB);
1722 CR.CaseBB->addSuccessor(Default);
1723 CR.CaseBB->addSuccessor(JumpTableBB);
1725 // Build a vector of destination BBs, corresponding to each target
1726 // of the jump table. If the value of the jump table slot corresponds to
1727 // a case statement, push the case's BB onto the vector, otherwise, push
1729 std::vector<MachineBasicBlock*> DestBBs;
1731 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1732 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1733 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1735 if (Low.sle(TEI) && TEI.sle(High)) {
1736 DestBBs.push_back(I->BB);
1740 DestBBs.push_back(Default);
1744 // Update successor info. Add one edge to each unique successor.
1745 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1746 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1747 E = DestBBs.end(); I != E; ++I) {
1748 if (!SuccsHandled[(*I)->getNumber()]) {
1749 SuccsHandled[(*I)->getNumber()] = true;
1750 JumpTableBB->addSuccessor(*I);
1754 // Create a jump table index for this jump table, or return an existing
1756 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1758 // Set the jump table information so that we can codegen it as a second
1759 // MachineBasicBlock
1760 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1761 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1762 if (CR.CaseBB == CurMBB)
1763 visitJumpTableHeader(JT, JTH);
1765 JTCases.push_back(JumpTableBlock(JTH, JT));
1770 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1772 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1773 CaseRecVector& WorkList,
1775 MachineBasicBlock* Default) {
1776 // Get the MachineFunction which holds the current MBB. This is used when
1777 // inserting any additional MBBs necessary to represent the switch.
1778 MachineFunction *CurMF = CurMBB->getParent();
1780 // Figure out which block is immediately after the current one.
1781 MachineBasicBlock *NextBlock = 0;
1782 MachineFunction::iterator BBI = CR.CaseBB;
1784 if (++BBI != CurMBB->getParent()->end())
1787 Case& FrontCase = *CR.Range.first;
1788 Case& BackCase = *(CR.Range.second-1);
1789 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1791 // Size is the number of Cases represented by this range.
1792 unsigned Size = CR.Range.second - CR.Range.first;
1794 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1795 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1797 CaseItr Pivot = CR.Range.first + Size/2;
1799 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1800 // (heuristically) allow us to emit JumpTable's later.
1802 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1806 size_t LSize = FrontCase.size();
1807 size_t RSize = TSize-LSize;
1808 DEBUG(errs() << "Selecting best pivot: \n"
1809 << "First: " << First << ", Last: " << Last <<'\n'
1810 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1811 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1813 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1814 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1815 APInt Range = ComputeRange(LEnd, RBegin);
1816 assert((Range - 2ULL).isNonNegative() &&
1817 "Invalid case distance");
1818 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1819 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1820 double Metric = Range.logBase2()*(LDensity+RDensity);
1821 // Should always split in some non-trivial place
1822 DEBUG(errs() <<"=>Step\n"
1823 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1824 << "LDensity: " << LDensity
1825 << ", RDensity: " << RDensity << '\n'
1826 << "Metric: " << Metric << '\n');
1827 if (FMetric < Metric) {
1830 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1836 if (areJTsAllowed(TLI)) {
1837 // If our case is dense we *really* should handle it earlier!
1838 assert((FMetric > 0) && "Should handle dense range earlier!");
1840 Pivot = CR.Range.first + Size/2;
1843 CaseRange LHSR(CR.Range.first, Pivot);
1844 CaseRange RHSR(Pivot, CR.Range.second);
1845 Constant *C = Pivot->Low;
1846 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1848 // We know that we branch to the LHS if the Value being switched on is
1849 // less than the Pivot value, C. We use this to optimize our binary
1850 // tree a bit, by recognizing that if SV is greater than or equal to the
1851 // LHS's Case Value, and that Case Value is exactly one less than the
1852 // Pivot's Value, then we can branch directly to the LHS's Target,
1853 // rather than creating a leaf node for it.
1854 if ((LHSR.second - LHSR.first) == 1 &&
1855 LHSR.first->High == CR.GE &&
1856 cast<ConstantInt>(C)->getValue() ==
1857 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1858 TrueBB = LHSR.first->BB;
1860 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1861 CurMF->insert(BBI, TrueBB);
1862 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1865 // Similar to the optimization above, if the Value being switched on is
1866 // known to be less than the Constant CR.LT, and the current Case Value
1867 // is CR.LT - 1, then we can branch directly to the target block for
1868 // the current Case Value, rather than emitting a RHS leaf node for it.
1869 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1870 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1871 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1872 FalseBB = RHSR.first->BB;
1874 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1875 CurMF->insert(BBI, FalseBB);
1876 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1879 // Create a CaseBlock record representing a conditional branch to
1880 // the LHS node if the value being switched on SV is less than C.
1881 // Otherwise, branch to LHS.
1882 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1884 if (CR.CaseBB == CurMBB)
1885 visitSwitchCase(CB);
1887 SwitchCases.push_back(CB);
1892 /// handleBitTestsSwitchCase - if current case range has few destination and
1893 /// range span less, than machine word bitwidth, encode case range into series
1894 /// of masks and emit bit tests with these masks.
1895 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1896 CaseRecVector& WorkList,
1898 MachineBasicBlock* Default){
1899 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1901 Case& FrontCase = *CR.Range.first;
1902 Case& BackCase = *(CR.Range.second-1);
1904 // Get the MachineFunction which holds the current MBB. This is used when
1905 // inserting any additional MBBs necessary to represent the switch.
1906 MachineFunction *CurMF = CurMBB->getParent();
1909 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1911 // Single case counts one, case range - two.
1912 numCmps += (I->Low == I->High ? 1 : 2);
1915 // Count unique destinations
1916 SmallSet<MachineBasicBlock*, 4> Dests;
1917 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1918 Dests.insert(I->BB);
1919 if (Dests.size() > 3)
1920 // Don't bother the code below, if there are too much unique destinations
1923 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1924 << "Total number of comparisons: " << numCmps << '\n');
1926 // Compute span of values.
1927 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1928 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1929 APInt cmpRange = maxValue - minValue;
1931 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1932 << "Low bound: " << minValue << '\n'
1933 << "High bound: " << maxValue << '\n');
1935 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1936 (!(Dests.size() == 1 && numCmps >= 3) &&
1937 !(Dests.size() == 2 && numCmps >= 5) &&
1938 !(Dests.size() >= 3 && numCmps >= 6)))
1941 DEBUG(errs() << "Emitting bit tests\n");
1942 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1944 // Optimize the case where all the case values fit in a
1945 // word without having to subtract minValue. In this case,
1946 // we can optimize away the subtraction.
1947 if (minValue.isNonNegative() &&
1948 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1949 cmpRange = maxValue;
1951 lowBound = minValue;
1954 CaseBitsVector CasesBits;
1955 unsigned i, count = 0;
1957 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1958 MachineBasicBlock* Dest = I->BB;
1959 for (i = 0; i < count; ++i)
1960 if (Dest == CasesBits[i].BB)
1964 assert((count < 3) && "Too much destinations to test!");
1965 CasesBits.push_back(CaseBits(0, Dest, 0));
1969 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1970 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1972 uint64_t lo = (lowValue - lowBound).getZExtValue();
1973 uint64_t hi = (highValue - lowBound).getZExtValue();
1975 for (uint64_t j = lo; j <= hi; j++) {
1976 CasesBits[i].Mask |= 1ULL << j;
1977 CasesBits[i].Bits++;
1981 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1985 // Figure out which block is immediately after the current one.
1986 MachineFunction::iterator BBI = CR.CaseBB;
1989 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1991 DEBUG(errs() << "Cases:\n");
1992 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1993 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
1994 << ", Bits: " << CasesBits[i].Bits
1995 << ", BB: " << CasesBits[i].BB << '\n');
1997 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1998 CurMF->insert(BBI, CaseBB);
1999 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2004 BitTestBlock BTB(lowBound, cmpRange, SV,
2005 -1U, (CR.CaseBB == CurMBB),
2006 CR.CaseBB, Default, BTC);
2008 if (CR.CaseBB == CurMBB)
2009 visitBitTestHeader(BTB);
2011 BitTestCases.push_back(BTB);
2017 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2018 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2019 const SwitchInst& SI) {
2022 // Start with "simple" cases
2023 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2024 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2025 Cases.push_back(Case(SI.getSuccessorValue(i),
2026 SI.getSuccessorValue(i),
2029 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2031 // Merge case into clusters
2032 if (Cases.size() >= 2)
2033 // Must recompute end() each iteration because it may be
2034 // invalidated by erase if we hold on to it
2035 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2036 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2037 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2038 MachineBasicBlock* nextBB = J->BB;
2039 MachineBasicBlock* currentBB = I->BB;
2041 // If the two neighboring cases go to the same destination, merge them
2042 // into a single case.
2043 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2051 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2052 if (I->Low != I->High)
2053 // A range counts double, since it requires two compares.
2060 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2061 // Figure out which block is immediately after the current one.
2062 MachineBasicBlock *NextBlock = 0;
2063 MachineFunction::iterator BBI = CurMBB;
2065 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2067 // If there is only the default destination, branch to it if it is not the
2068 // next basic block. Otherwise, just fall through.
2069 if (SI.getNumOperands() == 2) {
2070 // Update machine-CFG edges.
2072 // If this is not a fall-through branch, emit the branch.
2073 CurMBB->addSuccessor(Default);
2074 if (Default != NextBlock)
2075 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2076 MVT::Other, getControlRoot(),
2077 DAG.getBasicBlock(Default)));
2081 // If there are any non-default case statements, create a vector of Cases
2082 // representing each one, and sort the vector so that we can efficiently
2083 // create a binary search tree from them.
2085 size_t numCmps = Clusterify(Cases, SI);
2086 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2087 << ". Total compares: " << numCmps << '\n');
2090 // Get the Value to be switched on and default basic blocks, which will be
2091 // inserted into CaseBlock records, representing basic blocks in the binary
2093 Value *SV = SI.getOperand(0);
2095 // Push the initial CaseRec onto the worklist
2096 CaseRecVector WorkList;
2097 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2099 while (!WorkList.empty()) {
2100 // Grab a record representing a case range to process off the worklist
2101 CaseRec CR = WorkList.back();
2102 WorkList.pop_back();
2104 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2107 // If the range has few cases (two or less) emit a series of specific
2109 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2112 // If the switch has more than 5 blocks, and at least 40% dense, and the
2113 // target supports indirect branches, then emit a jump table rather than
2114 // lowering the switch to a binary tree of conditional branches.
2115 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2118 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2119 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2120 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2125 void SelectionDAGLowering::visitSub(User &I) {
2126 // -0.0 - X --> fneg
2127 const Type *Ty = I.getType();
2128 if (isa<VectorType>(Ty)) {
2129 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2130 const VectorType *DestTy = cast<VectorType>(I.getType());
2131 const Type *ElTy = DestTy->getElementType();
2132 if (ElTy->isFloatingPoint()) {
2133 unsigned VL = DestTy->getNumElements();
2134 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2135 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2137 SDValue Op2 = getValue(I.getOperand(1));
2138 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2139 Op2.getValueType(), Op2));
2145 if (Ty->isFloatingPoint()) {
2146 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2147 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2148 SDValue Op2 = getValue(I.getOperand(1));
2149 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2150 Op2.getValueType(), Op2));
2155 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2158 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2159 SDValue Op1 = getValue(I.getOperand(0));
2160 SDValue Op2 = getValue(I.getOperand(1));
2162 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2163 Op1.getValueType(), Op1, Op2));
2166 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2167 SDValue Op1 = getValue(I.getOperand(0));
2168 SDValue Op2 = getValue(I.getOperand(1));
2169 if (!isa<VectorType>(I.getType())) {
2170 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2171 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2172 TLI.getPointerTy(), Op2);
2173 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2174 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2175 TLI.getPointerTy(), Op2);
2178 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2179 Op1.getValueType(), Op1, Op2));
2182 void SelectionDAGLowering::visitICmp(User &I) {
2183 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2184 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2185 predicate = IC->getPredicate();
2186 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2187 predicate = ICmpInst::Predicate(IC->getPredicate());
2188 SDValue Op1 = getValue(I.getOperand(0));
2189 SDValue Op2 = getValue(I.getOperand(1));
2190 ISD::CondCode Opcode = getICmpCondCode(predicate);
2191 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2194 void SelectionDAGLowering::visitFCmp(User &I) {
2195 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2196 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2197 predicate = FC->getPredicate();
2198 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2199 predicate = FCmpInst::Predicate(FC->getPredicate());
2200 SDValue Op1 = getValue(I.getOperand(0));
2201 SDValue Op2 = getValue(I.getOperand(1));
2202 ISD::CondCode Condition = getFCmpCondCode(predicate);
2203 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2206 void SelectionDAGLowering::visitVICmp(User &I) {
2207 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2208 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2209 predicate = IC->getPredicate();
2210 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2211 predicate = ICmpInst::Predicate(IC->getPredicate());
2212 SDValue Op1 = getValue(I.getOperand(0));
2213 SDValue Op2 = getValue(I.getOperand(1));
2214 ISD::CondCode Opcode = getICmpCondCode(predicate);
2215 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2218 void SelectionDAGLowering::visitVFCmp(User &I) {
2219 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2220 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2221 predicate = FC->getPredicate();
2222 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2223 predicate = FCmpInst::Predicate(FC->getPredicate());
2224 SDValue Op1 = getValue(I.getOperand(0));
2225 SDValue Op2 = getValue(I.getOperand(1));
2226 ISD::CondCode Condition = getFCmpCondCode(predicate);
2227 MVT DestVT = TLI.getValueType(I.getType());
2229 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2232 void SelectionDAGLowering::visitSelect(User &I) {
2233 SmallVector<MVT, 4> ValueVTs;
2234 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2235 unsigned NumValues = ValueVTs.size();
2236 if (NumValues != 0) {
2237 SmallVector<SDValue, 4> Values(NumValues);
2238 SDValue Cond = getValue(I.getOperand(0));
2239 SDValue TrueVal = getValue(I.getOperand(1));
2240 SDValue FalseVal = getValue(I.getOperand(2));
2242 for (unsigned i = 0; i != NumValues; ++i)
2243 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2244 TrueVal.getValueType(), Cond,
2245 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2246 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2248 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2249 DAG.getVTList(&ValueVTs[0], NumValues),
2250 &Values[0], NumValues));
2255 void SelectionDAGLowering::visitTrunc(User &I) {
2256 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2257 SDValue N = getValue(I.getOperand(0));
2258 MVT DestVT = TLI.getValueType(I.getType());
2259 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2262 void SelectionDAGLowering::visitZExt(User &I) {
2263 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2264 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2265 SDValue N = getValue(I.getOperand(0));
2266 MVT DestVT = TLI.getValueType(I.getType());
2267 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2270 void SelectionDAGLowering::visitSExt(User &I) {
2271 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2272 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2273 SDValue N = getValue(I.getOperand(0));
2274 MVT DestVT = TLI.getValueType(I.getType());
2275 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2278 void SelectionDAGLowering::visitFPTrunc(User &I) {
2279 // FPTrunc is never a no-op cast, no need to check
2280 SDValue N = getValue(I.getOperand(0));
2281 MVT DestVT = TLI.getValueType(I.getType());
2282 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2283 DestVT, N, DAG.getIntPtrConstant(0)));
2286 void SelectionDAGLowering::visitFPExt(User &I){
2287 // FPTrunc is never a no-op cast, no need to check
2288 SDValue N = getValue(I.getOperand(0));
2289 MVT DestVT = TLI.getValueType(I.getType());
2290 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2293 void SelectionDAGLowering::visitFPToUI(User &I) {
2294 // FPToUI is never a no-op cast, no need to check
2295 SDValue N = getValue(I.getOperand(0));
2296 MVT DestVT = TLI.getValueType(I.getType());
2297 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2300 void SelectionDAGLowering::visitFPToSI(User &I) {
2301 // FPToSI is never a no-op cast, no need to check
2302 SDValue N = getValue(I.getOperand(0));
2303 MVT DestVT = TLI.getValueType(I.getType());
2304 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2307 void SelectionDAGLowering::visitUIToFP(User &I) {
2308 // UIToFP is never a no-op cast, no need to check
2309 SDValue N = getValue(I.getOperand(0));
2310 MVT DestVT = TLI.getValueType(I.getType());
2311 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2314 void SelectionDAGLowering::visitSIToFP(User &I){
2315 // SIToFP is never a no-op cast, no need to check
2316 SDValue N = getValue(I.getOperand(0));
2317 MVT DestVT = TLI.getValueType(I.getType());
2318 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2321 void SelectionDAGLowering::visitPtrToInt(User &I) {
2322 // What to do depends on the size of the integer and the size of the pointer.
2323 // We can either truncate, zero extend, or no-op, accordingly.
2324 SDValue N = getValue(I.getOperand(0));
2325 MVT SrcVT = N.getValueType();
2326 MVT DestVT = TLI.getValueType(I.getType());
2328 if (DestVT.bitsLT(SrcVT))
2329 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2331 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2332 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2333 setValue(&I, Result);
2336 void SelectionDAGLowering::visitIntToPtr(User &I) {
2337 // What to do depends on the size of the integer and the size of the pointer.
2338 // We can either truncate, zero extend, or no-op, accordingly.
2339 SDValue N = getValue(I.getOperand(0));
2340 MVT SrcVT = N.getValueType();
2341 MVT DestVT = TLI.getValueType(I.getType());
2342 if (DestVT.bitsLT(SrcVT))
2343 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2345 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2346 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2350 void SelectionDAGLowering::visitBitCast(User &I) {
2351 SDValue N = getValue(I.getOperand(0));
2352 MVT DestVT = TLI.getValueType(I.getType());
2354 // BitCast assures us that source and destination are the same size so this
2355 // is either a BIT_CONVERT or a no-op.
2356 if (DestVT != N.getValueType())
2357 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2358 DestVT, N)); // convert types
2360 setValue(&I, N); // noop cast.
2363 void SelectionDAGLowering::visitInsertElement(User &I) {
2364 SDValue InVec = getValue(I.getOperand(0));
2365 SDValue InVal = getValue(I.getOperand(1));
2366 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2368 getValue(I.getOperand(2)));
2370 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2371 TLI.getValueType(I.getType()),
2372 InVec, InVal, InIdx));
2375 void SelectionDAGLowering::visitExtractElement(User &I) {
2376 SDValue InVec = getValue(I.getOperand(0));
2377 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2379 getValue(I.getOperand(1)));
2380 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2381 TLI.getValueType(I.getType()), InVec, InIdx));
2385 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2386 // from SIndx and increasing to the element length (undefs are allowed).
2387 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2388 unsigned MaskNumElts = Mask.getNumOperands();
2389 for (unsigned i = 0; i != MaskNumElts; ++i) {
2390 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2391 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2392 if (Idx != i + SIndx)
2399 void SelectionDAGLowering::visitShuffleVector(User &I) {
2400 SDValue Src1 = getValue(I.getOperand(0));
2401 SDValue Src2 = getValue(I.getOperand(1));
2402 SDValue Mask = getValue(I.getOperand(2));
2404 MVT VT = TLI.getValueType(I.getType());
2405 MVT SrcVT = Src1.getValueType();
2406 int MaskNumElts = Mask.getNumOperands();
2407 int SrcNumElts = SrcVT.getVectorNumElements();
2409 if (SrcNumElts == MaskNumElts) {
2410 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2411 VT, Src1, Src2, Mask));
2415 // Normalize the shuffle vector since mask and vector length don't match.
2416 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2418 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2419 // Mask is longer than the source vectors and is a multiple of the source
2420 // vectors. We can use concatenate vector to make the mask and vectors
2422 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2423 // The shuffle is concatenating two vectors together.
2424 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2429 // Pad both vectors with undefs to make them the same length as the mask.
2430 unsigned NumConcat = MaskNumElts / SrcNumElts;
2431 SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
2433 SDValue* MOps1 = new SDValue[NumConcat];
2434 SDValue* MOps2 = new SDValue[NumConcat];
2437 for (unsigned i = 1; i != NumConcat; ++i) {
2438 MOps1[i] = UndefVal;
2439 MOps2[i] = UndefVal;
2441 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2442 VT, MOps1, NumConcat);
2443 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2444 VT, MOps2, NumConcat);
2449 // Readjust mask for new input vector length.
2450 SmallVector<SDValue, 8> MappedOps;
2451 for (int i = 0; i != MaskNumElts; ++i) {
2452 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2453 MappedOps.push_back(Mask.getOperand(i));
2455 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2456 if (Idx < SrcNumElts)
2457 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2459 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2463 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2464 Mask.getValueType(),
2465 &MappedOps[0], MappedOps.size());
2467 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2468 VT, Src1, Src2, Mask));
2472 if (SrcNumElts > MaskNumElts) {
2473 // Resulting vector is shorter than the incoming vector.
2474 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2475 // Shuffle extracts 1st vector.
2480 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2481 // Shuffle extracts 2nd vector.
2486 // Analyze the access pattern of the vector to see if we can extract
2487 // two subvectors and do the shuffle. The analysis is done by calculating
2488 // the range of elements the mask access on both vectors.
2489 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2490 int MaxRange[2] = {-1, -1};
2492 for (int i = 0; i != MaskNumElts; ++i) {
2493 SDValue Arg = Mask.getOperand(i);
2494 if (Arg.getOpcode() != ISD::UNDEF) {
2495 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2496 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2498 if (Idx >= SrcNumElts) {
2502 if (Idx > MaxRange[Input])
2503 MaxRange[Input] = Idx;
2504 if (Idx < MinRange[Input])
2505 MinRange[Input] = Idx;
2509 // Check if the access is smaller than the vector size and can we find
2510 // a reasonable extract index.
2511 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2512 int StartIdx[2]; // StartIdx to extract from
2513 for (int Input=0; Input < 2; ++Input) {
2514 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2515 RangeUse[Input] = 0; // Unused
2516 StartIdx[Input] = 0;
2517 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2518 // Fits within range but we should see if we can find a good
2519 // start index that is a multiple of the mask length.
2520 if (MaxRange[Input] < MaskNumElts) {
2521 RangeUse[Input] = 1; // Extract from beginning of the vector
2522 StartIdx[Input] = 0;
2524 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2525 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2526 StartIdx[Input] + MaskNumElts < SrcNumElts)
2527 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2532 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2533 setValue(&I, DAG.getNode(ISD::UNDEF,
2534 getCurDebugLoc(), VT)); // Vectors are not used.
2537 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2538 // Extract appropriate subvector and generate a vector shuffle
2539 for (int Input=0; Input < 2; ++Input) {
2540 SDValue& Src = Input == 0 ? Src1 : Src2;
2541 if (RangeUse[Input] == 0) {
2542 Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
2544 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2545 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2548 // Calculate new mask.
2549 SmallVector<SDValue, 8> MappedOps;
2550 for (int i = 0; i != MaskNumElts; ++i) {
2551 SDValue Arg = Mask.getOperand(i);
2552 if (Arg.getOpcode() == ISD::UNDEF) {
2553 MappedOps.push_back(Arg);
2555 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2556 if (Idx < SrcNumElts)
2557 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2559 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2560 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2564 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2565 Mask.getValueType(),
2566 &MappedOps[0], MappedOps.size());
2567 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2568 VT, Src1, Src2, Mask));
2573 // We can't use either concat vectors or extract subvectors so fall back to
2574 // replacing the shuffle with extract and build vector.
2575 // to insert and build vector.
2576 MVT EltVT = VT.getVectorElementType();
2577 MVT PtrVT = TLI.getPointerTy();
2578 SmallVector<SDValue,8> Ops;
2579 for (int i = 0; i != MaskNumElts; ++i) {
2580 SDValue Arg = Mask.getOperand(i);
2581 if (Arg.getOpcode() == ISD::UNDEF) {
2582 Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
2584 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2585 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2586 if (Idx < SrcNumElts)
2587 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2588 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2590 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2592 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2595 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2596 VT, &Ops[0], Ops.size()));
2599 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2600 const Value *Op0 = I.getOperand(0);
2601 const Value *Op1 = I.getOperand(1);
2602 const Type *AggTy = I.getType();
2603 const Type *ValTy = Op1->getType();
2604 bool IntoUndef = isa<UndefValue>(Op0);
2605 bool FromUndef = isa<UndefValue>(Op1);
2607 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2608 I.idx_begin(), I.idx_end());
2610 SmallVector<MVT, 4> AggValueVTs;
2611 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2612 SmallVector<MVT, 4> ValValueVTs;
2613 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2615 unsigned NumAggValues = AggValueVTs.size();
2616 unsigned NumValValues = ValValueVTs.size();
2617 SmallVector<SDValue, 4> Values(NumAggValues);
2619 SDValue Agg = getValue(Op0);
2620 SDValue Val = getValue(Op1);
2622 // Copy the beginning value(s) from the original aggregate.
2623 for (; i != LinearIndex; ++i)
2624 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2626 SDValue(Agg.getNode(), Agg.getResNo() + i);
2627 // Copy values from the inserted value(s).
2628 for (; i != LinearIndex + NumValValues; ++i)
2629 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2631 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2632 // Copy remaining value(s) from the original aggregate.
2633 for (; i != NumAggValues; ++i)
2634 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2636 SDValue(Agg.getNode(), Agg.getResNo() + i);
2638 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2639 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2640 &Values[0], NumAggValues));
2643 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2644 const Value *Op0 = I.getOperand(0);
2645 const Type *AggTy = Op0->getType();
2646 const Type *ValTy = I.getType();
2647 bool OutOfUndef = isa<UndefValue>(Op0);
2649 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2650 I.idx_begin(), I.idx_end());
2652 SmallVector<MVT, 4> ValValueVTs;
2653 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2655 unsigned NumValValues = ValValueVTs.size();
2656 SmallVector<SDValue, 4> Values(NumValValues);
2658 SDValue Agg = getValue(Op0);
2659 // Copy out the selected value(s).
2660 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2661 Values[i - LinearIndex] =
2663 DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
2664 Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2665 SDValue(Agg.getNode(), Agg.getResNo() + i);
2667 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2668 DAG.getVTList(&ValValueVTs[0], NumValValues),
2669 &Values[0], NumValValues));
2673 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2674 SDValue N = getValue(I.getOperand(0));
2675 const Type *Ty = I.getOperand(0)->getType();
2677 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2680 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2681 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2684 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2685 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2686 DAG.getIntPtrConstant(Offset));
2688 Ty = StTy->getElementType(Field);
2690 Ty = cast<SequentialType>(Ty)->getElementType();
2692 // If this is a constant subscript, handle it quickly.
2693 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2694 if (CI->getZExtValue() == 0) continue;
2696 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2697 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2698 DAG.getIntPtrConstant(Offs));
2702 // N = N + Idx * ElementSize;
2703 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2704 SDValue IdxN = getValue(Idx);
2706 // If the index is smaller or larger than intptr_t, truncate or extend
2708 if (IdxN.getValueType().bitsLT(N.getValueType()))
2709 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2710 N.getValueType(), IdxN);
2711 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2712 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2713 N.getValueType(), IdxN);
2715 // If this is a multiply by a power of two, turn it into a shl
2716 // immediately. This is a very common case.
2717 if (ElementSize != 1) {
2718 if (isPowerOf2_64(ElementSize)) {
2719 unsigned Amt = Log2_64(ElementSize);
2720 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2721 N.getValueType(), IdxN,
2722 DAG.getConstant(Amt, TLI.getPointerTy()));
2724 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2725 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2726 N.getValueType(), IdxN, Scale);
2730 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2731 N.getValueType(), N, IdxN);
2737 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2738 // If this is a fixed sized alloca in the entry block of the function,
2739 // allocate it statically on the stack.
2740 if (FuncInfo.StaticAllocaMap.count(&I))
2741 return; // getValue will auto-populate this.
2743 const Type *Ty = I.getAllocatedType();
2744 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2746 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2749 SDValue AllocSize = getValue(I.getArraySize());
2750 MVT IntPtr = TLI.getPointerTy();
2751 if (IntPtr.bitsLT(AllocSize.getValueType()))
2752 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2754 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2755 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2758 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
2759 DAG.getIntPtrConstant(TySize));
2761 // Handle alignment. If the requested alignment is less than or equal to
2762 // the stack alignment, ignore it. If the size is greater than or equal to
2763 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2764 unsigned StackAlign =
2765 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2766 if (Align <= StackAlign)
2769 // Round the size of the allocation up to the stack alignment size
2770 // by add SA-1 to the size.
2771 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2772 AllocSize.getValueType(), AllocSize,
2773 DAG.getIntPtrConstant(StackAlign-1));
2774 // Mask out the low bits for alignment purposes.
2775 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2776 AllocSize.getValueType(), AllocSize,
2777 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2779 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2780 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2782 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2785 DAG.setRoot(DSA.getValue(1));
2787 // Inform the Frame Information that we have just allocated a variable-sized
2789 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2792 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2793 const Value *SV = I.getOperand(0);
2794 SDValue Ptr = getValue(SV);
2796 const Type *Ty = I.getType();
2797 bool isVolatile = I.isVolatile();
2798 unsigned Alignment = I.getAlignment();
2800 SmallVector<MVT, 4> ValueVTs;
2801 SmallVector<uint64_t, 4> Offsets;
2802 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2803 unsigned NumValues = ValueVTs.size();
2808 bool ConstantMemory = false;
2810 // Serialize volatile loads with other side effects.
2812 else if (AA->pointsToConstantMemory(SV)) {
2813 // Do not serialize (non-volatile) loads of constant memory with anything.
2814 Root = DAG.getEntryNode();
2815 ConstantMemory = true;
2817 // Do not serialize non-volatile loads against each other.
2818 Root = DAG.getRoot();
2821 SmallVector<SDValue, 4> Values(NumValues);
2822 SmallVector<SDValue, 4> Chains(NumValues);
2823 MVT PtrVT = Ptr.getValueType();
2824 for (unsigned i = 0; i != NumValues; ++i) {
2825 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2826 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2828 DAG.getConstant(Offsets[i], PtrVT)),
2830 isVolatile, Alignment);
2832 Chains[i] = L.getValue(1);
2835 if (!ConstantMemory) {
2836 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2838 &Chains[0], NumValues);
2842 PendingLoads.push_back(Chain);
2845 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2846 DAG.getVTList(&ValueVTs[0], NumValues),
2847 &Values[0], NumValues));
2851 void SelectionDAGLowering::visitStore(StoreInst &I) {
2852 Value *SrcV = I.getOperand(0);
2853 Value *PtrV = I.getOperand(1);
2855 SmallVector<MVT, 4> ValueVTs;
2856 SmallVector<uint64_t, 4> Offsets;
2857 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2858 unsigned NumValues = ValueVTs.size();
2862 // Get the lowered operands. Note that we do this after
2863 // checking if NumResults is zero, because with zero results
2864 // the operands won't have values in the map.
2865 SDValue Src = getValue(SrcV);
2866 SDValue Ptr = getValue(PtrV);
2868 SDValue Root = getRoot();
2869 SmallVector<SDValue, 4> Chains(NumValues);
2870 MVT PtrVT = Ptr.getValueType();
2871 bool isVolatile = I.isVolatile();
2872 unsigned Alignment = I.getAlignment();
2873 for (unsigned i = 0; i != NumValues; ++i)
2874 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2875 SDValue(Src.getNode(), Src.getResNo() + i),
2876 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2878 DAG.getConstant(Offsets[i], PtrVT)),
2880 isVolatile, Alignment);
2882 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2883 MVT::Other, &Chains[0], NumValues));
2886 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2888 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2889 unsigned Intrinsic) {
2890 bool HasChain = !I.doesNotAccessMemory();
2891 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2893 // Build the operand list.
2894 SmallVector<SDValue, 8> Ops;
2895 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2897 // We don't need to serialize loads against other loads.
2898 Ops.push_back(DAG.getRoot());
2900 Ops.push_back(getRoot());
2904 // Info is set by getTgtMemInstrinsic
2905 TargetLowering::IntrinsicInfo Info;
2906 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2908 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2909 if (!IsTgtIntrinsic)
2910 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2912 // Add all operands of the call to the operand list.
2913 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2914 SDValue Op = getValue(I.getOperand(i));
2915 assert(TLI.isTypeLegal(Op.getValueType()) &&
2916 "Intrinsic uses a non-legal type?");
2920 std::vector<MVT> VTs;
2921 if (I.getType() != Type::VoidTy) {
2922 MVT VT = TLI.getValueType(I.getType());
2923 if (VT.isVector()) {
2924 const VectorType *DestTy = cast<VectorType>(I.getType());
2925 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2927 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2928 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2931 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2935 VTs.push_back(MVT::Other);
2937 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2941 if (IsTgtIntrinsic) {
2942 // This is target intrinsic that touches memory
2943 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2945 &Ops[0], Ops.size(),
2946 Info.memVT, Info.ptrVal, Info.offset,
2947 Info.align, Info.vol,
2948 Info.readMem, Info.writeMem);
2951 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2953 &Ops[0], Ops.size());
2954 else if (I.getType() != Type::VoidTy)
2955 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2957 &Ops[0], Ops.size());
2959 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2961 &Ops[0], Ops.size());
2964 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2966 PendingLoads.push_back(Chain);
2970 if (I.getType() != Type::VoidTy) {
2971 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2972 MVT VT = TLI.getValueType(PTy);
2973 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2975 setValue(&I, Result);
2979 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2980 static GlobalVariable *ExtractTypeInfo(Value *V) {
2981 V = V->stripPointerCasts();
2982 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2983 assert ((GV || isa<ConstantPointerNull>(V)) &&
2984 "TypeInfo must be a global variable or NULL");
2990 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2991 /// call, and add them to the specified machine basic block.
2992 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2993 MachineBasicBlock *MBB) {
2994 // Inform the MachineModuleInfo of the personality for this landing pad.
2995 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2996 assert(CE->getOpcode() == Instruction::BitCast &&
2997 isa<Function>(CE->getOperand(0)) &&
2998 "Personality should be a function");
2999 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3001 // Gather all the type infos for this landing pad and pass them along to
3002 // MachineModuleInfo.
3003 std::vector<GlobalVariable *> TyInfo;
3004 unsigned N = I.getNumOperands();
3006 for (unsigned i = N - 1; i > 2; --i) {
3007 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3008 unsigned FilterLength = CI->getZExtValue();
3009 unsigned FirstCatch = i + FilterLength + !FilterLength;
3010 assert (FirstCatch <= N && "Invalid filter length");
3012 if (FirstCatch < N) {
3013 TyInfo.reserve(N - FirstCatch);
3014 for (unsigned j = FirstCatch; j < N; ++j)
3015 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3016 MMI->addCatchTypeInfo(MBB, TyInfo);
3020 if (!FilterLength) {
3022 MMI->addCleanup(MBB);
3025 TyInfo.reserve(FilterLength - 1);
3026 for (unsigned j = i + 1; j < FirstCatch; ++j)
3027 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3028 MMI->addFilterTypeInfo(MBB, TyInfo);
3037 TyInfo.reserve(N - 3);
3038 for (unsigned j = 3; j < N; ++j)
3039 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3040 MMI->addCatchTypeInfo(MBB, TyInfo);
3046 /// GetSignificand - Get the significand and build it into a floating-point
3047 /// number with exponent of 1:
3049 /// Op = (Op & 0x007fffff) | 0x3f800000;
3051 /// where Op is the hexidecimal representation of floating point value.
3053 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3054 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3055 DAG.getConstant(0x007fffff, MVT::i32));
3056 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3057 DAG.getConstant(0x3f800000, MVT::i32));
3058 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3061 /// GetExponent - Get the exponent:
3063 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3065 /// where Op is the hexidecimal representation of floating point value.
3067 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3069 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3070 DAG.getConstant(0x7f800000, MVT::i32));
3071 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3072 DAG.getConstant(23, TLI.getPointerTy()));
3073 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3074 DAG.getConstant(127, MVT::i32));
3075 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3078 /// getF32Constant - Get 32-bit floating point constant.
3080 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3081 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3084 /// Inlined utility function to implement binary input atomic intrinsics for
3085 /// visitIntrinsicCall: I is a call instruction
3086 /// Op is the associated NodeType for I
3088 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3089 SDValue Root = getRoot();
3091 DAG.getAtomic(Op, getCurDebugLoc(),
3092 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3094 getValue(I.getOperand(1)),
3095 getValue(I.getOperand(2)),
3098 DAG.setRoot(L.getValue(1));
3102 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3104 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3105 SDValue Op1 = getValue(I.getOperand(1));
3106 SDValue Op2 = getValue(I.getOperand(2));
3108 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3109 SDValue Ops[] = { Op1, Op2 };
3111 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
3112 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
3114 setValue(&I, Result);
3118 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3119 /// limited-precision mode.
3121 SelectionDAGLowering::visitExp(CallInst &I) {
3123 DebugLoc dl = getCurDebugLoc();
3125 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3126 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3127 SDValue Op = getValue(I.getOperand(1));
3129 // Put the exponent in the right bit position for later addition to the
3132 // #define LOG2OFe 1.4426950f
3133 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3134 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3135 getF32Constant(DAG, 0x3fb8aa3b));
3136 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3138 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3139 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3140 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3142 // IntegerPartOfX <<= 23;
3143 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3144 DAG.getConstant(23, TLI.getPointerTy()));
3146 if (LimitFloatPrecision <= 6) {
3147 // For floating-point precision of 6:
3149 // TwoToFractionalPartOfX =
3151 // (0.735607626f + 0.252464424f * x) * x;
3153 // error 0.0144103317, which is 6 bits
3154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3155 getF32Constant(DAG, 0x3e814304));
3156 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3157 getF32Constant(DAG, 0x3f3c50c8));
3158 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3159 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3160 getF32Constant(DAG, 0x3f7f5e7e));
3161 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3163 // Add the exponent into the result in integer domain.
3164 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3165 TwoToFracPartOfX, IntegerPartOfX);
3167 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3168 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3169 // For floating-point precision of 12:
3171 // TwoToFractionalPartOfX =
3174 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3176 // 0.000107046256 error, which is 13 to 14 bits
3177 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3178 getF32Constant(DAG, 0x3da235e3));
3179 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3180 getF32Constant(DAG, 0x3e65b8f3));
3181 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3182 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3183 getF32Constant(DAG, 0x3f324b07));
3184 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3185 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3186 getF32Constant(DAG, 0x3f7ff8fd));
3187 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3189 // Add the exponent into the result in integer domain.
3190 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3191 TwoToFracPartOfX, IntegerPartOfX);
3193 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3194 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3195 // For floating-point precision of 18:
3197 // TwoToFractionalPartOfX =
3201 // (0.554906021e-1f +
3202 // (0.961591928e-2f +
3203 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3205 // error 2.47208000*10^(-7), which is better than 18 bits
3206 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3207 getF32Constant(DAG, 0x3924b03e));
3208 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3209 getF32Constant(DAG, 0x3ab24b87));
3210 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3211 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3212 getF32Constant(DAG, 0x3c1d8c17));
3213 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3214 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3215 getF32Constant(DAG, 0x3d634a1d));
3216 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3217 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3218 getF32Constant(DAG, 0x3e75fe14));
3219 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3220 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3221 getF32Constant(DAG, 0x3f317234));
3222 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3223 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3224 getF32Constant(DAG, 0x3f800000));
3225 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3228 // Add the exponent into the result in integer domain.
3229 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3230 TwoToFracPartOfX, IntegerPartOfX);
3232 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3235 // No special expansion.
3236 result = DAG.getNode(ISD::FEXP, dl,
3237 getValue(I.getOperand(1)).getValueType(),
3238 getValue(I.getOperand(1)));
3241 setValue(&I, result);
3244 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3245 /// limited-precision mode.
3247 SelectionDAGLowering::visitLog(CallInst &I) {
3249 DebugLoc dl = getCurDebugLoc();
3251 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3252 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3253 SDValue Op = getValue(I.getOperand(1));
3254 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3256 // Scale the exponent by log(2) [0.69314718f].
3257 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3258 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3259 getF32Constant(DAG, 0x3f317218));
3261 // Get the significand and build it into a floating-point number with
3263 SDValue X = GetSignificand(DAG, Op1, dl);
3265 if (LimitFloatPrecision <= 6) {
3266 // For floating-point precision of 6:
3270 // (1.4034025f - 0.23903021f * x) * x;
3272 // error 0.0034276066, which is better than 8 bits
3273 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3274 getF32Constant(DAG, 0xbe74c456));
3275 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3276 getF32Constant(DAG, 0x3fb3a2b1));
3277 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3278 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3279 getF32Constant(DAG, 0x3f949a29));
3281 result = DAG.getNode(ISD::FADD, dl,
3282 MVT::f32, LogOfExponent, LogOfMantissa);
3283 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3284 // For floating-point precision of 12:
3290 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3292 // error 0.000061011436, which is 14 bits
3293 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3294 getF32Constant(DAG, 0xbd67b6d6));
3295 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3296 getF32Constant(DAG, 0x3ee4f4b8));
3297 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3298 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3299 getF32Constant(DAG, 0x3fbc278b));
3300 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3301 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3302 getF32Constant(DAG, 0x40348e95));
3303 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3304 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3305 getF32Constant(DAG, 0x3fdef31a));
3307 result = DAG.getNode(ISD::FADD, dl,
3308 MVT::f32, LogOfExponent, LogOfMantissa);
3309 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3310 // For floating-point precision of 18:
3318 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3320 // error 0.0000023660568, which is better than 18 bits
3321 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3322 getF32Constant(DAG, 0xbc91e5ac));
3323 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3324 getF32Constant(DAG, 0x3e4350aa));
3325 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3326 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3327 getF32Constant(DAG, 0x3f60d3e3));
3328 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3329 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3330 getF32Constant(DAG, 0x4011cdf0));
3331 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3332 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3333 getF32Constant(DAG, 0x406cfd1c));
3334 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3335 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3336 getF32Constant(DAG, 0x408797cb));
3337 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3338 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3339 getF32Constant(DAG, 0x4006dcab));
3341 result = DAG.getNode(ISD::FADD, dl,
3342 MVT::f32, LogOfExponent, LogOfMantissa);
3345 // No special expansion.
3346 result = DAG.getNode(ISD::FLOG, dl,
3347 getValue(I.getOperand(1)).getValueType(),
3348 getValue(I.getOperand(1)));
3351 setValue(&I, result);
3354 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3355 /// limited-precision mode.
3357 SelectionDAGLowering::visitLog2(CallInst &I) {
3359 DebugLoc dl = getCurDebugLoc();
3361 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3362 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3363 SDValue Op = getValue(I.getOperand(1));
3364 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3366 // Get the exponent.
3367 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3369 // Get the significand and build it into a floating-point number with
3371 SDValue X = GetSignificand(DAG, Op1, dl);
3373 // Different possible minimax approximations of significand in
3374 // floating-point for various degrees of accuracy over [1,2].
3375 if (LimitFloatPrecision <= 6) {
3376 // For floating-point precision of 6:
3378 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3380 // error 0.0049451742, which is more than 7 bits
3381 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3382 getF32Constant(DAG, 0xbeb08fe0));
3383 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3384 getF32Constant(DAG, 0x40019463));
3385 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3386 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3387 getF32Constant(DAG, 0x3fd6633d));
3389 result = DAG.getNode(ISD::FADD, dl,
3390 MVT::f32, LogOfExponent, Log2ofMantissa);
3391 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3392 // For floating-point precision of 12:
3398 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3400 // error 0.0000876136000, which is better than 13 bits
3401 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3402 getF32Constant(DAG, 0xbda7262e));
3403 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3404 getF32Constant(DAG, 0x3f25280b));
3405 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3406 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3407 getF32Constant(DAG, 0x4007b923));
3408 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3409 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3410 getF32Constant(DAG, 0x40823e2f));
3411 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3412 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3413 getF32Constant(DAG, 0x4020d29c));
3415 result = DAG.getNode(ISD::FADD, dl,
3416 MVT::f32, LogOfExponent, Log2ofMantissa);
3417 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3418 // For floating-point precision of 18:
3427 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3429 // error 0.0000018516, which is better than 18 bits
3430 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3431 getF32Constant(DAG, 0xbcd2769e));
3432 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3433 getF32Constant(DAG, 0x3e8ce0b9));
3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3435 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3436 getF32Constant(DAG, 0x3fa22ae7));
3437 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3438 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3439 getF32Constant(DAG, 0x40525723));
3440 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3441 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3442 getF32Constant(DAG, 0x40aaf200));
3443 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3444 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3445 getF32Constant(DAG, 0x40c39dad));
3446 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3447 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3448 getF32Constant(DAG, 0x4042902c));
3450 result = DAG.getNode(ISD::FADD, dl,
3451 MVT::f32, LogOfExponent, Log2ofMantissa);
3454 // No special expansion.
3455 result = DAG.getNode(ISD::FLOG2, dl,
3456 getValue(I.getOperand(1)).getValueType(),
3457 getValue(I.getOperand(1)));
3460 setValue(&I, result);
3463 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3464 /// limited-precision mode.
3466 SelectionDAGLowering::visitLog10(CallInst &I) {
3468 DebugLoc dl = getCurDebugLoc();
3470 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3471 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3472 SDValue Op = getValue(I.getOperand(1));
3473 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3475 // Scale the exponent by log10(2) [0.30102999f].
3476 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3477 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3478 getF32Constant(DAG, 0x3e9a209a));
3480 // Get the significand and build it into a floating-point number with
3482 SDValue X = GetSignificand(DAG, Op1, dl);
3484 if (LimitFloatPrecision <= 6) {
3485 // For floating-point precision of 6:
3487 // Log10ofMantissa =
3489 // (0.60948995f - 0.10380950f * x) * x;
3491 // error 0.0014886165, which is 6 bits
3492 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3493 getF32Constant(DAG, 0xbdd49a13));
3494 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3495 getF32Constant(DAG, 0x3f1c0789));
3496 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3497 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3498 getF32Constant(DAG, 0x3f011300));
3500 result = DAG.getNode(ISD::FADD, dl,
3501 MVT::f32, LogOfExponent, Log10ofMantissa);
3502 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3503 // For floating-point precision of 12:
3505 // Log10ofMantissa =
3508 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3510 // error 0.00019228036, which is better than 12 bits
3511 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3512 getF32Constant(DAG, 0x3d431f31));
3513 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3514 getF32Constant(DAG, 0x3ea21fb2));
3515 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3516 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3517 getF32Constant(DAG, 0x3f6ae232));
3518 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3519 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3520 getF32Constant(DAG, 0x3f25f7c3));
3522 result = DAG.getNode(ISD::FADD, dl,
3523 MVT::f32, LogOfExponent, Log10ofMantissa);
3524 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3525 // For floating-point precision of 18:
3527 // Log10ofMantissa =
3532 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3534 // error 0.0000037995730, which is better than 18 bits
3535 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3536 getF32Constant(DAG, 0x3c5d51ce));
3537 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3538 getF32Constant(DAG, 0x3e00685a));
3539 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3540 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3541 getF32Constant(DAG, 0x3efb6798));
3542 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3543 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3544 getF32Constant(DAG, 0x3f88d192));
3545 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3546 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3547 getF32Constant(DAG, 0x3fc4316c));
3548 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3549 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3550 getF32Constant(DAG, 0x3f57ce70));
3552 result = DAG.getNode(ISD::FADD, dl,
3553 MVT::f32, LogOfExponent, Log10ofMantissa);
3556 // No special expansion.
3557 result = DAG.getNode(ISD::FLOG10, dl,
3558 getValue(I.getOperand(1)).getValueType(),
3559 getValue(I.getOperand(1)));
3562 setValue(&I, result);
3565 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3566 /// limited-precision mode.
3568 SelectionDAGLowering::visitExp2(CallInst &I) {
3570 DebugLoc dl = getCurDebugLoc();
3572 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3573 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3574 SDValue Op = getValue(I.getOperand(1));
3576 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3578 // FractionalPartOfX = x - (float)IntegerPartOfX;
3579 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3580 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3582 // IntegerPartOfX <<= 23;
3583 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3584 DAG.getConstant(23, TLI.getPointerTy()));
3586 if (LimitFloatPrecision <= 6) {
3587 // For floating-point precision of 6:
3589 // TwoToFractionalPartOfX =
3591 // (0.735607626f + 0.252464424f * x) * x;
3593 // error 0.0144103317, which is 6 bits
3594 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3595 getF32Constant(DAG, 0x3e814304));
3596 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3597 getF32Constant(DAG, 0x3f3c50c8));
3598 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3599 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3600 getF32Constant(DAG, 0x3f7f5e7e));
3601 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3602 SDValue TwoToFractionalPartOfX =
3603 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3605 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3606 MVT::f32, TwoToFractionalPartOfX);
3607 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3608 // For floating-point precision of 12:
3610 // TwoToFractionalPartOfX =
3613 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3615 // error 0.000107046256, which is 13 to 14 bits
3616 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3617 getF32Constant(DAG, 0x3da235e3));
3618 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3619 getF32Constant(DAG, 0x3e65b8f3));
3620 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3621 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3622 getF32Constant(DAG, 0x3f324b07));
3623 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3624 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3625 getF32Constant(DAG, 0x3f7ff8fd));
3626 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3627 SDValue TwoToFractionalPartOfX =
3628 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3630 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3631 MVT::f32, TwoToFractionalPartOfX);
3632 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3633 // For floating-point precision of 18:
3635 // TwoToFractionalPartOfX =
3639 // (0.554906021e-1f +
3640 // (0.961591928e-2f +
3641 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3642 // error 2.47208000*10^(-7), which is better than 18 bits
3643 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3644 getF32Constant(DAG, 0x3924b03e));
3645 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3646 getF32Constant(DAG, 0x3ab24b87));
3647 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3648 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3649 getF32Constant(DAG, 0x3c1d8c17));
3650 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3651 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3652 getF32Constant(DAG, 0x3d634a1d));
3653 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3654 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3655 getF32Constant(DAG, 0x3e75fe14));
3656 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3657 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3658 getF32Constant(DAG, 0x3f317234));
3659 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3660 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3661 getF32Constant(DAG, 0x3f800000));
3662 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3663 SDValue TwoToFractionalPartOfX =
3664 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3666 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3667 MVT::f32, TwoToFractionalPartOfX);
3670 // No special expansion.
3671 result = DAG.getNode(ISD::FEXP2, dl,
3672 getValue(I.getOperand(1)).getValueType(),
3673 getValue(I.getOperand(1)));
3676 setValue(&I, result);
3679 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3680 /// limited-precision mode with x == 10.0f.
3682 SelectionDAGLowering::visitPow(CallInst &I) {
3684 Value *Val = I.getOperand(1);
3685 DebugLoc dl = getCurDebugLoc();
3686 bool IsExp10 = false;
3688 if (getValue(Val).getValueType() == MVT::f32 &&
3689 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3690 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3691 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3692 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3694 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3699 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3700 SDValue Op = getValue(I.getOperand(2));
3702 // Put the exponent in the right bit position for later addition to the
3705 // #define LOG2OF10 3.3219281f
3706 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3707 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3708 getF32Constant(DAG, 0x40549a78));
3709 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3711 // FractionalPartOfX = x - (float)IntegerPartOfX;
3712 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3713 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3715 // IntegerPartOfX <<= 23;
3716 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3717 DAG.getConstant(23, TLI.getPointerTy()));
3719 if (LimitFloatPrecision <= 6) {
3720 // For floating-point precision of 6:
3722 // twoToFractionalPartOfX =
3724 // (0.735607626f + 0.252464424f * x) * x;
3726 // error 0.0144103317, which is 6 bits
3727 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3728 getF32Constant(DAG, 0x3e814304));
3729 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3730 getF32Constant(DAG, 0x3f3c50c8));
3731 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3732 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3733 getF32Constant(DAG, 0x3f7f5e7e));
3734 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3735 SDValue TwoToFractionalPartOfX =
3736 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3738 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3739 MVT::f32, TwoToFractionalPartOfX);
3740 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3741 // For floating-point precision of 12:
3743 // TwoToFractionalPartOfX =
3746 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3748 // error 0.000107046256, which is 13 to 14 bits
3749 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3750 getF32Constant(DAG, 0x3da235e3));
3751 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3752 getF32Constant(DAG, 0x3e65b8f3));
3753 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3754 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3755 getF32Constant(DAG, 0x3f324b07));
3756 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3757 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3758 getF32Constant(DAG, 0x3f7ff8fd));
3759 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3760 SDValue TwoToFractionalPartOfX =
3761 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3763 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3764 MVT::f32, TwoToFractionalPartOfX);
3765 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3766 // For floating-point precision of 18:
3768 // TwoToFractionalPartOfX =
3772 // (0.554906021e-1f +
3773 // (0.961591928e-2f +
3774 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3775 // error 2.47208000*10^(-7), which is better than 18 bits
3776 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3777 getF32Constant(DAG, 0x3924b03e));
3778 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3779 getF32Constant(DAG, 0x3ab24b87));
3780 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3781 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3782 getF32Constant(DAG, 0x3c1d8c17));
3783 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3784 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3785 getF32Constant(DAG, 0x3d634a1d));
3786 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3787 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3788 getF32Constant(DAG, 0x3e75fe14));
3789 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3790 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3791 getF32Constant(DAG, 0x3f317234));
3792 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3793 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3794 getF32Constant(DAG, 0x3f800000));
3795 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3796 SDValue TwoToFractionalPartOfX =
3797 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3799 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3800 MVT::f32, TwoToFractionalPartOfX);
3803 // No special expansion.
3804 result = DAG.getNode(ISD::FPOW, dl,
3805 getValue(I.getOperand(1)).getValueType(),
3806 getValue(I.getOperand(1)),
3807 getValue(I.getOperand(2)));
3810 setValue(&I, result);
3813 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3814 /// we want to emit this as a call to a named external function, return the name
3815 /// otherwise lower it and return null.
3817 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3818 DebugLoc dl = getCurDebugLoc();
3819 switch (Intrinsic) {
3821 // By default, turn this into a target intrinsic node.
3822 visitTargetIntrinsic(I, Intrinsic);
3824 case Intrinsic::vastart: visitVAStart(I); return 0;
3825 case Intrinsic::vaend: visitVAEnd(I); return 0;
3826 case Intrinsic::vacopy: visitVACopy(I); return 0;
3827 case Intrinsic::returnaddress:
3828 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3829 getValue(I.getOperand(1))));
3831 case Intrinsic::frameaddress:
3832 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3833 getValue(I.getOperand(1))));
3835 case Intrinsic::setjmp:
3836 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3838 case Intrinsic::longjmp:
3839 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3841 case Intrinsic::memcpy: {
3842 SDValue Op1 = getValue(I.getOperand(1));
3843 SDValue Op2 = getValue(I.getOperand(2));
3844 SDValue Op3 = getValue(I.getOperand(3));
3845 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3846 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3847 I.getOperand(1), 0, I.getOperand(2), 0));
3850 case Intrinsic::memset: {
3851 SDValue Op1 = getValue(I.getOperand(1));
3852 SDValue Op2 = getValue(I.getOperand(2));
3853 SDValue Op3 = getValue(I.getOperand(3));
3854 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3855 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3856 I.getOperand(1), 0));
3859 case Intrinsic::memmove: {
3860 SDValue Op1 = getValue(I.getOperand(1));
3861 SDValue Op2 = getValue(I.getOperand(2));
3862 SDValue Op3 = getValue(I.getOperand(3));
3863 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3865 // If the source and destination are known to not be aliases, we can
3866 // lower memmove as memcpy.
3867 uint64_t Size = -1ULL;
3868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3869 Size = C->getZExtValue();
3870 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3871 AliasAnalysis::NoAlias) {
3872 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3873 I.getOperand(1), 0, I.getOperand(2), 0));
3877 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3878 I.getOperand(1), 0, I.getOperand(2), 0));
3881 case Intrinsic::dbg_stoppoint: {
3882 DwarfWriter *DW = DAG.getDwarfWriter();
3883 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3884 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
3885 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3889 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3890 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3891 unsigned idx = DAG.getMachineFunction().
3892 getOrCreateDebugLocID(SrcFile,
3895 setCurDebugLoc(DebugLoc::get(idx));
3899 case Intrinsic::dbg_region_start: {
3900 DwarfWriter *DW = DAG.getDwarfWriter();
3901 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3902 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
3904 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3905 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3910 case Intrinsic::dbg_region_end: {
3911 DwarfWriter *DW = DAG.getDwarfWriter();
3912 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3913 if (DW && DW->ValidDebugInfo(REI.getContext())) {
3915 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3916 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3921 case Intrinsic::dbg_func_start: {
3922 DwarfWriter *DW = DAG.getDwarfWriter();
3924 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3925 Value *SP = FSI.getSubprogram();
3926 if (SP && DW->ValidDebugInfo(SP)) {
3927 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3928 // what (most?) gdb expects.
3929 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3930 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3931 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3932 CompileUnit.getFilename());
3934 // Record the source line but does not create a label for the normal
3935 // function start. It will be emitted at asm emission time. However,
3936 // create a label if this is a beginning of inlined function.
3937 unsigned Line = Subprogram.getLineNumber();
3938 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3940 if (DW->getRecordSourceLineCount() != 1)
3941 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3943 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
3944 getOrCreateDebugLocID(SrcFile, Line, 0)));
3949 case Intrinsic::dbg_declare: {
3950 DwarfWriter *DW = DAG.getDwarfWriter();
3951 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3952 Value *Variable = DI.getVariable();
3953 if (DW && DW->ValidDebugInfo(Variable))
3954 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3955 getValue(DI.getAddress()), getValue(Variable)));
3959 case Intrinsic::eh_exception: {
3960 if (!CurMBB->isLandingPad()) {
3961 // FIXME: Mark exception register as live in. Hack for PR1508.
3962 unsigned Reg = TLI.getExceptionAddressRegister();
3963 if (Reg) CurMBB->addLiveIn(Reg);
3965 // Insert the EXCEPTIONADDR instruction.
3966 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3968 Ops[0] = DAG.getRoot();
3969 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3971 DAG.setRoot(Op.getValue(1));
3975 case Intrinsic::eh_selector_i32:
3976 case Intrinsic::eh_selector_i64: {
3977 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3978 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3979 MVT::i32 : MVT::i64);
3982 if (CurMBB->isLandingPad())
3983 AddCatchInfo(I, MMI, CurMBB);
3986 FuncInfo.CatchInfoLost.insert(&I);
3988 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3989 unsigned Reg = TLI.getExceptionSelectorRegister();
3990 if (Reg) CurMBB->addLiveIn(Reg);
3993 // Insert the EHSELECTION instruction.
3994 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3996 Ops[0] = getValue(I.getOperand(1));
3998 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4000 DAG.setRoot(Op.getValue(1));
4002 setValue(&I, DAG.getConstant(0, VT));
4008 case Intrinsic::eh_typeid_for_i32:
4009 case Intrinsic::eh_typeid_for_i64: {
4010 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4011 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4012 MVT::i32 : MVT::i64);
4015 // Find the type id for the given typeinfo.
4016 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4018 unsigned TypeID = MMI->getTypeIDFor(GV);
4019 setValue(&I, DAG.getConstant(TypeID, VT));
4021 // Return something different to eh_selector.
4022 setValue(&I, DAG.getConstant(1, VT));
4028 case Intrinsic::eh_return_i32:
4029 case Intrinsic::eh_return_i64:
4030 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4031 MMI->setCallsEHReturn(true);
4032 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4035 getValue(I.getOperand(1)),
4036 getValue(I.getOperand(2))));
4038 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4042 case Intrinsic::eh_unwind_init:
4043 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4044 MMI->setCallsUnwindInit(true);
4049 case Intrinsic::eh_dwarf_cfa: {
4050 MVT VT = getValue(I.getOperand(1)).getValueType();
4052 if (VT.bitsGT(TLI.getPointerTy()))
4053 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4054 TLI.getPointerTy(), getValue(I.getOperand(1)));
4056 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4057 TLI.getPointerTy(), getValue(I.getOperand(1)));
4059 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4061 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4062 TLI.getPointerTy()),
4064 setValue(&I, DAG.getNode(ISD::ADD, dl,
4066 DAG.getNode(ISD::FRAMEADDR, dl,
4069 TLI.getPointerTy())),
4074 case Intrinsic::convertff:
4075 case Intrinsic::convertfsi:
4076 case Intrinsic::convertfui:
4077 case Intrinsic::convertsif:
4078 case Intrinsic::convertuif:
4079 case Intrinsic::convertss:
4080 case Intrinsic::convertsu:
4081 case Intrinsic::convertus:
4082 case Intrinsic::convertuu: {
4083 ISD::CvtCode Code = ISD::CVT_INVALID;
4084 switch (Intrinsic) {
4085 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4086 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4087 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4088 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4089 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4090 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4091 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4092 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4093 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4095 MVT DestVT = TLI.getValueType(I.getType());
4096 Value* Op1 = I.getOperand(1);
4097 setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1),
4098 DAG.getValueType(DestVT),
4099 DAG.getValueType(getValue(Op1).getValueType()),
4100 getValue(I.getOperand(2)),
4101 getValue(I.getOperand(3)),
4106 case Intrinsic::sqrt:
4107 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4108 getValue(I.getOperand(1)).getValueType(),
4109 getValue(I.getOperand(1))));
4111 case Intrinsic::powi:
4112 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4113 getValue(I.getOperand(1)).getValueType(),
4114 getValue(I.getOperand(1)),
4115 getValue(I.getOperand(2))));
4117 case Intrinsic::sin:
4118 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4119 getValue(I.getOperand(1)).getValueType(),
4120 getValue(I.getOperand(1))));
4122 case Intrinsic::cos:
4123 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4124 getValue(I.getOperand(1)).getValueType(),
4125 getValue(I.getOperand(1))));
4127 case Intrinsic::log:
4130 case Intrinsic::log2:
4133 case Intrinsic::log10:
4136 case Intrinsic::exp:
4139 case Intrinsic::exp2:
4142 case Intrinsic::pow:
4145 case Intrinsic::pcmarker: {
4146 SDValue Tmp = getValue(I.getOperand(1));
4147 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4150 case Intrinsic::readcyclecounter: {
4151 SDValue Op = getRoot();
4152 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4153 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4156 DAG.setRoot(Tmp.getValue(1));
4159 case Intrinsic::part_select: {
4160 // Currently not implemented: just abort
4161 assert(0 && "part_select intrinsic not implemented");
4164 case Intrinsic::part_set: {
4165 // Currently not implemented: just abort
4166 assert(0 && "part_set intrinsic not implemented");
4169 case Intrinsic::bswap:
4170 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4171 getValue(I.getOperand(1)).getValueType(),
4172 getValue(I.getOperand(1))));
4174 case Intrinsic::cttz: {
4175 SDValue Arg = getValue(I.getOperand(1));
4176 MVT Ty = Arg.getValueType();
4177 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4178 setValue(&I, result);
4181 case Intrinsic::ctlz: {
4182 SDValue Arg = getValue(I.getOperand(1));
4183 MVT Ty = Arg.getValueType();
4184 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4185 setValue(&I, result);
4188 case Intrinsic::ctpop: {
4189 SDValue Arg = getValue(I.getOperand(1));
4190 MVT Ty = Arg.getValueType();
4191 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4192 setValue(&I, result);
4195 case Intrinsic::stacksave: {
4196 SDValue Op = getRoot();
4197 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4198 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4200 DAG.setRoot(Tmp.getValue(1));
4203 case Intrinsic::stackrestore: {
4204 SDValue Tmp = getValue(I.getOperand(1));
4205 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4208 case Intrinsic::stackprotector: {
4209 // Emit code into the DAG to store the stack guard onto the stack.
4210 MachineFunction &MF = DAG.getMachineFunction();
4211 MachineFrameInfo *MFI = MF.getFrameInfo();
4212 MVT PtrTy = TLI.getPointerTy();
4214 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4215 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4217 int FI = FuncInfo.StaticAllocaMap[Slot];
4218 MFI->setStackProtectorIndex(FI);
4220 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4222 // Store the stack protector onto the stack.
4223 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4224 PseudoSourceValue::getFixedStack(FI),
4226 setValue(&I, Result);
4227 DAG.setRoot(Result);
4230 case Intrinsic::var_annotation:
4231 // Discard annotate attributes
4234 case Intrinsic::init_trampoline: {
4235 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4239 Ops[1] = getValue(I.getOperand(1));
4240 Ops[2] = getValue(I.getOperand(2));
4241 Ops[3] = getValue(I.getOperand(3));
4242 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4243 Ops[5] = DAG.getSrcValue(F);
4245 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4246 DAG.getNodeValueTypes(TLI.getPointerTy(),
4251 DAG.setRoot(Tmp.getValue(1));
4255 case Intrinsic::gcroot:
4257 Value *Alloca = I.getOperand(1);
4258 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4260 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4261 GFI->addStackRoot(FI->getIndex(), TypeMap);
4265 case Intrinsic::gcread:
4266 case Intrinsic::gcwrite:
4267 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4270 case Intrinsic::flt_rounds: {
4271 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4275 case Intrinsic::trap: {
4276 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4280 case Intrinsic::uadd_with_overflow:
4281 return implVisitAluOverflow(I, ISD::UADDO);
4282 case Intrinsic::sadd_with_overflow:
4283 return implVisitAluOverflow(I, ISD::SADDO);
4284 case Intrinsic::usub_with_overflow:
4285 return implVisitAluOverflow(I, ISD::USUBO);
4286 case Intrinsic::ssub_with_overflow:
4287 return implVisitAluOverflow(I, ISD::SSUBO);
4288 case Intrinsic::umul_with_overflow:
4289 return implVisitAluOverflow(I, ISD::UMULO);
4290 case Intrinsic::smul_with_overflow:
4291 return implVisitAluOverflow(I, ISD::SMULO);
4293 case Intrinsic::prefetch: {
4296 Ops[1] = getValue(I.getOperand(1));
4297 Ops[2] = getValue(I.getOperand(2));
4298 Ops[3] = getValue(I.getOperand(3));
4299 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4303 case Intrinsic::memory_barrier: {
4306 for (int x = 1; x < 6; ++x)
4307 Ops[x] = getValue(I.getOperand(x));
4309 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4312 case Intrinsic::atomic_cmp_swap: {
4313 SDValue Root = getRoot();
4315 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4316 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4318 getValue(I.getOperand(1)),
4319 getValue(I.getOperand(2)),
4320 getValue(I.getOperand(3)),
4323 DAG.setRoot(L.getValue(1));
4326 case Intrinsic::atomic_load_add:
4327 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4328 case Intrinsic::atomic_load_sub:
4329 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4330 case Intrinsic::atomic_load_or:
4331 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4332 case Intrinsic::atomic_load_xor:
4333 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4334 case Intrinsic::atomic_load_and:
4335 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4336 case Intrinsic::atomic_load_nand:
4337 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4338 case Intrinsic::atomic_load_max:
4339 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4340 case Intrinsic::atomic_load_min:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4342 case Intrinsic::atomic_load_umin:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4344 case Intrinsic::atomic_load_umax:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4346 case Intrinsic::atomic_swap:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4352 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4354 MachineBasicBlock *LandingPad) {
4355 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4356 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4357 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4358 unsigned BeginLabel = 0, EndLabel = 0;
4360 TargetLowering::ArgListTy Args;
4361 TargetLowering::ArgListEntry Entry;
4362 Args.reserve(CS.arg_size());
4363 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4365 SDValue ArgNode = getValue(*i);
4366 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4368 unsigned attrInd = i - CS.arg_begin() + 1;
4369 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4370 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4371 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4372 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4373 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4374 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4375 Entry.Alignment = CS.getParamAlignment(attrInd);
4376 Args.push_back(Entry);
4379 if (LandingPad && MMI) {
4380 // Insert a label before the invoke call to mark the try range. This can be
4381 // used to detect deletion of the invoke via the MachineModuleInfo.
4382 BeginLabel = MMI->NextLabelID();
4383 // Both PendingLoads and PendingExports must be flushed here;
4384 // this call might not return.
4386 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
4389 std::pair<SDValue,SDValue> Result =
4390 TLI.LowerCallTo(getRoot(), CS.getType(),
4391 CS.paramHasAttr(0, Attribute::SExt),
4392 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4393 CS.paramHasAttr(0, Attribute::InReg),
4394 CS.getCallingConv(),
4395 IsTailCall && PerformTailCallOpt,
4396 Callee, Args, DAG, getCurDebugLoc());
4397 if (CS.getType() != Type::VoidTy)
4398 setValue(CS.getInstruction(), Result.first);
4399 DAG.setRoot(Result.second);
4401 if (LandingPad && MMI) {
4402 // Insert a label at the end of the invoke call to mark the try range. This
4403 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4404 EndLabel = MMI->NextLabelID();
4405 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
4407 // Inform MachineModuleInfo of range.
4408 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4413 void SelectionDAGLowering::visitCall(CallInst &I) {
4414 const char *RenameFn = 0;
4415 if (Function *F = I.getCalledFunction()) {
4416 if (F->isDeclaration()) {
4417 if (unsigned IID = F->getIntrinsicID()) {
4418 RenameFn = visitIntrinsicCall(I, IID);
4424 // Check for well-known libc/libm calls. If the function is internal, it
4425 // can't be a library call.
4426 unsigned NameLen = F->getNameLen();
4427 if (!F->hasLocalLinkage() && NameLen) {
4428 const char *NameStr = F->getNameStart();
4429 if (NameStr[0] == 'c' &&
4430 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4431 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4432 if (I.getNumOperands() == 3 && // Basic sanity checks.
4433 I.getOperand(1)->getType()->isFloatingPoint() &&
4434 I.getType() == I.getOperand(1)->getType() &&
4435 I.getType() == I.getOperand(2)->getType()) {
4436 SDValue LHS = getValue(I.getOperand(1));
4437 SDValue RHS = getValue(I.getOperand(2));
4438 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4439 LHS.getValueType(), LHS, RHS));
4442 } else if (NameStr[0] == 'f' &&
4443 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4444 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4445 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4446 if (I.getNumOperands() == 2 && // Basic sanity checks.
4447 I.getOperand(1)->getType()->isFloatingPoint() &&
4448 I.getType() == I.getOperand(1)->getType()) {
4449 SDValue Tmp = getValue(I.getOperand(1));
4450 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4451 Tmp.getValueType(), Tmp));
4454 } else if (NameStr[0] == 's' &&
4455 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4456 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4457 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4458 if (I.getNumOperands() == 2 && // Basic sanity checks.
4459 I.getOperand(1)->getType()->isFloatingPoint() &&
4460 I.getType() == I.getOperand(1)->getType()) {
4461 SDValue Tmp = getValue(I.getOperand(1));
4462 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4463 Tmp.getValueType(), Tmp));
4466 } else if (NameStr[0] == 'c' &&
4467 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4468 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4469 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4470 if (I.getNumOperands() == 2 && // Basic sanity checks.
4471 I.getOperand(1)->getType()->isFloatingPoint() &&
4472 I.getType() == I.getOperand(1)->getType()) {
4473 SDValue Tmp = getValue(I.getOperand(1));
4474 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4475 Tmp.getValueType(), Tmp));
4480 } else if (isa<InlineAsm>(I.getOperand(0))) {
4487 Callee = getValue(I.getOperand(0));
4489 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4491 LowerCallTo(&I, Callee, I.isTailCall());
4495 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4496 /// this value and returns the result as a ValueVT value. This uses
4497 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4498 /// If the Flag pointer is NULL, no flag is used.
4499 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4501 SDValue *Flag) const {
4502 // Assemble the legal parts into the final values.
4503 SmallVector<SDValue, 4> Values(ValueVTs.size());
4504 SmallVector<SDValue, 8> Parts;
4505 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4506 // Copy the legal parts from the registers.
4507 MVT ValueVT = ValueVTs[Value];
4508 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4509 MVT RegisterVT = RegVTs[Value];
4511 Parts.resize(NumRegs);
4512 for (unsigned i = 0; i != NumRegs; ++i) {
4515 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4517 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4518 *Flag = P.getValue(2);
4520 Chain = P.getValue(1);
4522 // If the source register was virtual and if we know something about it,
4523 // add an assert node.
4524 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4525 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4526 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4527 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4528 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4529 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4531 unsigned RegSize = RegisterVT.getSizeInBits();
4532 unsigned NumSignBits = LOI.NumSignBits;
4533 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4535 // FIXME: We capture more information than the dag can represent. For
4536 // now, just use the tightest assertzext/assertsext possible.
4538 MVT FromVT(MVT::Other);
4539 if (NumSignBits == RegSize)
4540 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4541 else if (NumZeroBits >= RegSize-1)
4542 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4543 else if (NumSignBits > RegSize-8)
4544 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4545 else if (NumZeroBits >= RegSize-9)
4546 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4547 else if (NumSignBits > RegSize-16)
4548 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4549 else if (NumZeroBits >= RegSize-17)
4550 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4551 else if (NumSignBits > RegSize-32)
4552 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4553 else if (NumZeroBits >= RegSize-33)
4554 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4556 if (FromVT != MVT::Other) {
4557 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4558 RegisterVT, P, DAG.getValueType(FromVT));
4567 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4568 NumRegs, RegisterVT, ValueVT);
4573 return DAG.getNode(ISD::MERGE_VALUES, dl,
4574 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4575 &Values[0], ValueVTs.size());
4578 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4579 /// specified value into the registers specified by this object. This uses
4580 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4581 /// If the Flag pointer is NULL, no flag is used.
4582 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4583 SDValue &Chain, SDValue *Flag) const {
4584 // Get the list of the values's legal parts.
4585 unsigned NumRegs = Regs.size();
4586 SmallVector<SDValue, 8> Parts(NumRegs);
4587 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4588 MVT ValueVT = ValueVTs[Value];
4589 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4590 MVT RegisterVT = RegVTs[Value];
4592 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4593 &Parts[Part], NumParts, RegisterVT);
4597 // Copy the parts into the registers.
4598 SmallVector<SDValue, 8> Chains(NumRegs);
4599 for (unsigned i = 0; i != NumRegs; ++i) {
4602 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4604 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4605 *Flag = Part.getValue(1);
4607 Chains[i] = Part.getValue(0);
4610 if (NumRegs == 1 || Flag)
4611 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4612 // flagged to it. That is the CopyToReg nodes and the user are considered
4613 // a single scheduling unit. If we create a TokenFactor and return it as
4614 // chain, then the TokenFactor is both a predecessor (operand) of the
4615 // user as well as a successor (the TF operands are flagged to the user).
4616 // c1, f1 = CopyToReg
4617 // c2, f2 = CopyToReg
4618 // c3 = TokenFactor c1, c2
4621 Chain = Chains[NumRegs-1];
4623 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4626 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4627 /// operand list. This adds the code marker and includes the number of
4628 /// values added into it.
4629 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4630 std::vector<SDValue> &Ops) const {
4631 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4632 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4633 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4634 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4635 MVT RegisterVT = RegVTs[Value];
4636 for (unsigned i = 0; i != NumRegs; ++i) {
4637 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4638 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4643 /// isAllocatableRegister - If the specified register is safe to allocate,
4644 /// i.e. it isn't a stack pointer or some other special register, return the
4645 /// register class for the register. Otherwise, return null.
4646 static const TargetRegisterClass *
4647 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4648 const TargetLowering &TLI,
4649 const TargetRegisterInfo *TRI) {
4650 MVT FoundVT = MVT::Other;
4651 const TargetRegisterClass *FoundRC = 0;
4652 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4653 E = TRI->regclass_end(); RCI != E; ++RCI) {
4654 MVT ThisVT = MVT::Other;
4656 const TargetRegisterClass *RC = *RCI;
4657 // If none of the the value types for this register class are valid, we
4658 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4659 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4661 if (TLI.isTypeLegal(*I)) {
4662 // If we have already found this register in a different register class,
4663 // choose the one with the largest VT specified. For example, on
4664 // PowerPC, we favor f64 register classes over f32.
4665 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4672 if (ThisVT == MVT::Other) continue;
4674 // NOTE: This isn't ideal. In particular, this might allocate the
4675 // frame pointer in functions that need it (due to them not being taken
4676 // out of allocation, because a variable sized allocation hasn't been seen
4677 // yet). This is a slight code pessimization, but should still work.
4678 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4679 E = RC->allocation_order_end(MF); I != E; ++I)
4681 // We found a matching register class. Keep looking at others in case
4682 // we find one with larger registers that this physreg is also in.
4693 /// AsmOperandInfo - This contains information for each constraint that we are
4695 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4696 public TargetLowering::AsmOperandInfo {
4697 /// CallOperand - If this is the result output operand or a clobber
4698 /// this is null, otherwise it is the incoming operand to the CallInst.
4699 /// This gets modified as the asm is processed.
4700 SDValue CallOperand;
4702 /// AssignedRegs - If this is a register or register class operand, this
4703 /// contains the set of register corresponding to the operand.
4704 RegsForValue AssignedRegs;
4706 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4707 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4710 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4711 /// busy in OutputRegs/InputRegs.
4712 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4713 std::set<unsigned> &OutputRegs,
4714 std::set<unsigned> &InputRegs,
4715 const TargetRegisterInfo &TRI) const {
4717 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4718 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4721 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4722 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4726 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4727 /// corresponds to. If there is no Value* for this operand, it returns
4729 MVT getCallOperandValMVT(const TargetLowering &TLI,
4730 const TargetData *TD) const {
4731 if (CallOperandVal == 0) return MVT::Other;
4733 if (isa<BasicBlock>(CallOperandVal))
4734 return TLI.getPointerTy();
4736 const llvm::Type *OpTy = CallOperandVal->getType();
4738 // If this is an indirect operand, the operand is a pointer to the
4741 OpTy = cast<PointerType>(OpTy)->getElementType();
4743 // If OpTy is not a single value, it may be a struct/union that we
4744 // can tile with integers.
4745 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4746 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4755 OpTy = IntegerType::get(BitSize);
4760 return TLI.getValueType(OpTy, true);
4764 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4766 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4767 const TargetRegisterInfo &TRI) {
4768 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4770 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4771 for (; *Aliases; ++Aliases)
4772 Regs.insert(*Aliases);
4775 } // end llvm namespace.
4778 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4779 /// specified operand. We prefer to assign virtual registers, to allow the
4780 /// register allocator handle the assignment process. However, if the asm uses
4781 /// features that we can't model on machineinstrs, we have SDISel do the
4782 /// allocation. This produces generally horrible, but correct, code.
4784 /// OpInfo describes the operand.
4785 /// Input and OutputRegs are the set of already allocated physical registers.
4787 void SelectionDAGLowering::
4788 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4789 std::set<unsigned> &OutputRegs,
4790 std::set<unsigned> &InputRegs) {
4791 // Compute whether this value requires an input register, an output register,
4793 bool isOutReg = false;
4794 bool isInReg = false;
4795 switch (OpInfo.Type) {
4796 case InlineAsm::isOutput:
4799 // If there is an input constraint that matches this, we need to reserve
4800 // the input register so no other inputs allocate to it.
4801 isInReg = OpInfo.hasMatchingInput();
4803 case InlineAsm::isInput:
4807 case InlineAsm::isClobber:
4814 MachineFunction &MF = DAG.getMachineFunction();
4815 SmallVector<unsigned, 4> Regs;
4817 // If this is a constraint for a single physreg, or a constraint for a
4818 // register class, find it.
4819 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4820 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4821 OpInfo.ConstraintVT);
4823 unsigned NumRegs = 1;
4824 if (OpInfo.ConstraintVT != MVT::Other) {
4825 // If this is a FP input in an integer register (or visa versa) insert a bit
4826 // cast of the input value. More generally, handle any case where the input
4827 // value disagrees with the register class we plan to stick this in.
4828 if (OpInfo.Type == InlineAsm::isInput &&
4829 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4830 // Try to convert to the first MVT that the reg class contains. If the
4831 // types are identical size, use a bitcast to convert (e.g. two differing
4833 MVT RegVT = *PhysReg.second->vt_begin();
4834 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4835 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4836 RegVT, OpInfo.CallOperand);
4837 OpInfo.ConstraintVT = RegVT;
4838 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4839 // If the input is a FP value and we want it in FP registers, do a
4840 // bitcast to the corresponding integer type. This turns an f64 value
4841 // into i64, which can be passed with two i32 values on a 32-bit
4843 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4844 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4845 RegVT, OpInfo.CallOperand);
4846 OpInfo.ConstraintVT = RegVT;
4850 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4854 MVT ValueVT = OpInfo.ConstraintVT;
4856 // If this is a constraint for a specific physical register, like {r17},
4858 if (PhysReg.first) {
4859 if (OpInfo.ConstraintVT == MVT::Other)
4860 ValueVT = *PhysReg.second->vt_begin();
4862 // Get the actual register value type. This is important, because the user
4863 // may have asked for (e.g.) the AX register in i32 type. We need to
4864 // remember that AX is actually i16 to get the right extension.
4865 RegVT = *PhysReg.second->vt_begin();
4867 // This is a explicit reference to a physical register.
4868 Regs.push_back(PhysReg.first);
4870 // If this is an expanded reference, add the rest of the regs to Regs.
4872 TargetRegisterClass::iterator I = PhysReg.second->begin();
4873 for (; *I != PhysReg.first; ++I)
4874 assert(I != PhysReg.second->end() && "Didn't find reg!");
4876 // Already added the first reg.
4878 for (; NumRegs; --NumRegs, ++I) {
4879 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4883 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4884 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4885 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4889 // Otherwise, if this was a reference to an LLVM register class, create vregs
4890 // for this reference.
4891 std::vector<unsigned> RegClassRegs;
4892 const TargetRegisterClass *RC = PhysReg.second;
4894 // If this is a tied register, our regalloc doesn't know how to maintain
4895 // the constraint, so we have to pick a register to pin the input/output to.
4896 // If it isn't a matched constraint, go ahead and create vreg and let the
4897 // regalloc do its thing.
4898 if (!OpInfo.hasMatchingInput()) {
4899 RegVT = *PhysReg.second->vt_begin();
4900 if (OpInfo.ConstraintVT == MVT::Other)
4903 // Create the appropriate number of virtual registers.
4904 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4905 for (; NumRegs; --NumRegs)
4906 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4908 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4912 // Otherwise, we can't allocate it. Let the code below figure out how to
4913 // maintain these constraints.
4914 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4917 // This is a reference to a register class that doesn't directly correspond
4918 // to an LLVM register class. Allocate NumRegs consecutive, available,
4919 // registers from the class.
4920 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4921 OpInfo.ConstraintVT);
4924 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4925 unsigned NumAllocated = 0;
4926 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4927 unsigned Reg = RegClassRegs[i];
4928 // See if this register is available.
4929 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4930 (isInReg && InputRegs.count(Reg))) { // Already used.
4931 // Make sure we find consecutive registers.
4936 // Check to see if this register is allocatable (i.e. don't give out the
4939 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4940 if (!RC) { // Couldn't allocate this register.
4941 // Reset NumAllocated to make sure we return consecutive registers.
4947 // Okay, this register is good, we can use it.
4950 // If we allocated enough consecutive registers, succeed.
4951 if (NumAllocated == NumRegs) {
4952 unsigned RegStart = (i-NumAllocated)+1;
4953 unsigned RegEnd = i+1;
4954 // Mark all of the allocated registers used.
4955 for (unsigned i = RegStart; i != RegEnd; ++i)
4956 Regs.push_back(RegClassRegs[i]);
4958 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4959 OpInfo.ConstraintVT);
4960 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4965 // Otherwise, we couldn't allocate enough registers for this.
4968 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4969 /// processed uses a memory 'm' constraint.
4971 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4972 const TargetLowering &TLI) {
4973 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4974 InlineAsm::ConstraintInfo &CI = CInfos[i];
4975 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4976 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4977 if (CType == TargetLowering::C_Memory)
4985 /// visitInlineAsm - Handle a call to an InlineAsm object.
4987 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4988 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4990 /// ConstraintOperands - Information about all of the constraints.
4991 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4993 SDValue Chain = getRoot();
4996 std::set<unsigned> OutputRegs, InputRegs;
4998 // Do a prepass over the constraints, canonicalizing them, and building up the
4999 // ConstraintOperands list.
5000 std::vector<InlineAsm::ConstraintInfo>
5001 ConstraintInfos = IA->ParseConstraints();
5003 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5005 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5006 unsigned ResNo = 0; // ResNo - The result number of the next output.
5007 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5008 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5009 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5011 MVT OpVT = MVT::Other;
5013 // Compute the value type for each operand.
5014 switch (OpInfo.Type) {
5015 case InlineAsm::isOutput:
5016 // Indirect outputs just consume an argument.
5017 if (OpInfo.isIndirect) {
5018 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5022 // The return value of the call is this value. As such, there is no
5023 // corresponding argument.
5024 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5025 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5026 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5028 assert(ResNo == 0 && "Asm only has one result!");
5029 OpVT = TLI.getValueType(CS.getType());
5033 case InlineAsm::isInput:
5034 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5036 case InlineAsm::isClobber:
5041 // If this is an input or an indirect output, process the call argument.
5042 // BasicBlocks are labels, currently appearing only in asm's.
5043 if (OpInfo.CallOperandVal) {
5044 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5045 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5047 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5050 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5053 OpInfo.ConstraintVT = OpVT;
5056 // Second pass over the constraints: compute which constraint option to use
5057 // and assign registers to constraints that want a specific physreg.
5058 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5059 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5061 // If this is an output operand with a matching input operand, look up the
5062 // matching input. If their types mismatch, e.g. one is an integer, the
5063 // other is floating point, or their sizes are different, flag it as an
5065 if (OpInfo.hasMatchingInput()) {
5066 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5067 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5068 if ((OpInfo.ConstraintVT.isInteger() !=
5069 Input.ConstraintVT.isInteger()) ||
5070 (OpInfo.ConstraintVT.getSizeInBits() !=
5071 Input.ConstraintVT.getSizeInBits())) {
5072 cerr << "Unsupported asm: input constraint with a matching output "
5073 << "constraint of incompatible type!\n";
5076 Input.ConstraintVT = OpInfo.ConstraintVT;
5080 // Compute the constraint code and ConstraintType to use.
5081 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5083 // If this is a memory input, and if the operand is not indirect, do what we
5084 // need to to provide an address for the memory input.
5085 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5086 !OpInfo.isIndirect) {
5087 assert(OpInfo.Type == InlineAsm::isInput &&
5088 "Can only indirectify direct input operands!");
5090 // Memory operands really want the address of the value. If we don't have
5091 // an indirect input, put it in the constpool if we can, otherwise spill
5092 // it to a stack slot.
5094 // If the operand is a float, integer, or vector constant, spill to a
5095 // constant pool entry to get its address.
5096 Value *OpVal = OpInfo.CallOperandVal;
5097 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5098 isa<ConstantVector>(OpVal)) {
5099 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5100 TLI.getPointerTy());
5102 // Otherwise, create a stack slot and emit a store to it before the
5104 const Type *Ty = OpVal->getType();
5105 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5106 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5107 MachineFunction &MF = DAG.getMachineFunction();
5108 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5109 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5110 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5111 OpInfo.CallOperand, StackSlot, NULL, 0);
5112 OpInfo.CallOperand = StackSlot;
5115 // There is no longer a Value* corresponding to this operand.
5116 OpInfo.CallOperandVal = 0;
5117 // It is now an indirect operand.
5118 OpInfo.isIndirect = true;
5121 // If this constraint is for a specific register, allocate it before
5123 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5124 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5126 ConstraintInfos.clear();
5129 // Second pass - Loop over all of the operands, assigning virtual or physregs
5130 // to register class operands.
5131 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5132 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5134 // C_Register operands have already been allocated, Other/Memory don't need
5136 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5137 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5140 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5141 std::vector<SDValue> AsmNodeOperands;
5142 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5143 AsmNodeOperands.push_back(
5144 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5147 // Loop over all of the inputs, copying the operand values into the
5148 // appropriate registers and processing the output regs.
5149 RegsForValue RetValRegs;
5151 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5152 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5154 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5155 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5157 switch (OpInfo.Type) {
5158 case InlineAsm::isOutput: {
5159 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5160 OpInfo.ConstraintType != TargetLowering::C_Register) {
5161 // Memory output, or 'other' output (e.g. 'X' constraint).
5162 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5164 // Add information to the INLINEASM node to know about this output.
5165 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5166 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5167 TLI.getPointerTy()));
5168 AsmNodeOperands.push_back(OpInfo.CallOperand);
5172 // Otherwise, this is a register or register class output.
5174 // Copy the output from the appropriate register. Find a register that
5176 if (OpInfo.AssignedRegs.Regs.empty()) {
5177 cerr << "Couldn't allocate output reg for constraint '"
5178 << OpInfo.ConstraintCode << "'!\n";
5182 // If this is an indirect operand, store through the pointer after the
5184 if (OpInfo.isIndirect) {
5185 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5186 OpInfo.CallOperandVal));
5188 // This is the result value of the call.
5189 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5190 // Concatenate this output onto the outputs list.
5191 RetValRegs.append(OpInfo.AssignedRegs);
5194 // Add information to the INLINEASM node to know that this register is
5196 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5197 6 /* EARLYCLOBBER REGDEF */ :
5199 DAG, AsmNodeOperands);
5202 case InlineAsm::isInput: {
5203 SDValue InOperandVal = OpInfo.CallOperand;
5205 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5206 // If this is required to match an output register we have already set,
5207 // just use its register.
5208 unsigned OperandNo = OpInfo.getMatchedOperand();
5210 // Scan until we find the definition we already emitted of this operand.
5211 // When we find it, create a RegsForValue operand.
5212 unsigned CurOp = 2; // The first operand.
5213 for (; OperandNo; --OperandNo) {
5214 // Advance to the next operand.
5216 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5217 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
5218 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5219 (NumOps & 7) == 4 /*MEM*/) &&
5220 "Skipped past definitions?");
5221 CurOp += (NumOps>>3)+1;
5225 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5226 if ((NumOps & 7) == 2 /*REGDEF*/
5227 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5228 // Add NumOps>>3 registers to MatchedRegs.
5229 RegsForValue MatchedRegs;
5230 MatchedRegs.TLI = &TLI;
5231 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5232 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5233 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5235 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5236 MatchedRegs.Regs.push_back(Reg);
5239 // Use the produced MatchedRegs object to
5240 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5242 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
5245 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5246 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5247 // Add information to the INLINEASM node to know about this input.
5248 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
5249 TLI.getPointerTy()));
5250 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5255 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5256 assert(!OpInfo.isIndirect &&
5257 "Don't know how to handle indirect other inputs yet!");
5259 std::vector<SDValue> Ops;
5260 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5261 hasMemory, Ops, DAG);
5263 cerr << "Invalid operand for inline asm constraint '"
5264 << OpInfo.ConstraintCode << "'!\n";
5268 // Add information to the INLINEASM node to know about this input.
5269 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5270 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5271 TLI.getPointerTy()));
5272 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5274 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5275 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5276 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5277 "Memory operands expect pointer values");
5279 // Add information to the INLINEASM node to know about this input.
5280 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5281 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5282 TLI.getPointerTy()));
5283 AsmNodeOperands.push_back(InOperandVal);
5287 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5288 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5289 "Unknown constraint type!");
5290 assert(!OpInfo.isIndirect &&
5291 "Don't know how to handle indirect register inputs yet!");
5293 // Copy the input into the appropriate registers.
5294 if (OpInfo.AssignedRegs.Regs.empty()) {
5295 cerr << "Couldn't allocate output reg for constraint '"
5296 << OpInfo.ConstraintCode << "'!\n";
5300 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5303 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5304 DAG, AsmNodeOperands);
5307 case InlineAsm::isClobber: {
5308 // Add the clobbered value to the operand list, so that the register
5309 // allocator is aware that the physreg got clobbered.
5310 if (!OpInfo.AssignedRegs.Regs.empty())
5311 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5312 DAG, AsmNodeOperands);
5318 // Finish up input operands.
5319 AsmNodeOperands[0] = Chain;
5320 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5322 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5323 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5324 &AsmNodeOperands[0], AsmNodeOperands.size());
5325 Flag = Chain.getValue(1);
5327 // If this asm returns a register value, copy the result from that register
5328 // and set it as the value of the call.
5329 if (!RetValRegs.Regs.empty()) {
5330 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5333 // FIXME: Why don't we do this for inline asms with MRVs?
5334 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5335 MVT ResultType = TLI.getValueType(CS.getType());
5337 // If any of the results of the inline asm is a vector, it may have the
5338 // wrong width/num elts. This can happen for register classes that can
5339 // contain multiple different value types. The preg or vreg allocated may
5340 // not have the same VT as was expected. Convert it to the right type
5341 // with bit_convert.
5342 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5343 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5346 } else if (ResultType != Val.getValueType() &&
5347 ResultType.isInteger() && Val.getValueType().isInteger()) {
5348 // If a result value was tied to an input value, the computed result may
5349 // have a wider width than the expected result. Extract the relevant
5351 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5354 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5357 setValue(CS.getInstruction(), Val);
5360 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5362 // Process indirect outputs, first output all of the flagged copies out of
5364 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5365 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5366 Value *Ptr = IndirectStoresToEmit[i].second;
5367 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5369 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5372 // Emit the non-flagged stores from the physregs.
5373 SmallVector<SDValue, 8> OutChains;
5374 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5375 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5376 StoresToEmit[i].first,
5377 getValue(StoresToEmit[i].second),
5378 StoresToEmit[i].second, 0));
5379 if (!OutChains.empty())
5380 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5381 &OutChains[0], OutChains.size());
5386 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5387 SDValue Src = getValue(I.getOperand(0));
5389 MVT IntPtr = TLI.getPointerTy();
5391 if (IntPtr.bitsLT(Src.getValueType()))
5392 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5393 else if (IntPtr.bitsGT(Src.getValueType()))
5394 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5396 // Scale the source by the type size.
5397 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5398 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5399 Src, DAG.getIntPtrConstant(ElementSize));
5401 TargetLowering::ArgListTy Args;
5402 TargetLowering::ArgListEntry Entry;
5404 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5405 Args.push_back(Entry);
5407 std::pair<SDValue,SDValue> Result =
5408 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5409 CallingConv::C, PerformTailCallOpt,
5410 DAG.getExternalSymbol("malloc", IntPtr),
5411 Args, DAG, getCurDebugLoc());
5412 setValue(&I, Result.first); // Pointers always fit in registers
5413 DAG.setRoot(Result.second);
5416 void SelectionDAGLowering::visitFree(FreeInst &I) {
5417 TargetLowering::ArgListTy Args;
5418 TargetLowering::ArgListEntry Entry;
5419 Entry.Node = getValue(I.getOperand(0));
5420 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5421 Args.push_back(Entry);
5422 MVT IntPtr = TLI.getPointerTy();
5423 std::pair<SDValue,SDValue> Result =
5424 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5425 CallingConv::C, PerformTailCallOpt,
5426 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5428 DAG.setRoot(Result.second);
5431 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5432 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5433 MVT::Other, getRoot(),
5434 getValue(I.getOperand(1)),
5435 DAG.getSrcValue(I.getOperand(1))));
5438 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5439 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
5440 getValue(I.getOperand(0)),
5441 DAG.getSrcValue(I.getOperand(0)));
5443 DAG.setRoot(V.getValue(1));
5446 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5447 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5448 MVT::Other, getRoot(),
5449 getValue(I.getOperand(1)),
5450 DAG.getSrcValue(I.getOperand(1))));
5453 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5454 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5455 MVT::Other, getRoot(),
5456 getValue(I.getOperand(1)),
5457 getValue(I.getOperand(2)),
5458 DAG.getSrcValue(I.getOperand(1)),
5459 DAG.getSrcValue(I.getOperand(2))));
5462 /// TargetLowering::LowerArguments - This is the default LowerArguments
5463 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5464 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5465 /// integrated into SDISel.
5466 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5467 SmallVectorImpl<SDValue> &ArgValues,
5469 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5470 SmallVector<SDValue, 3+16> Ops;
5471 Ops.push_back(DAG.getRoot());
5472 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5473 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5475 // Add one result value for each formal argument.
5476 SmallVector<MVT, 16> RetVals;
5478 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5480 SmallVector<MVT, 4> ValueVTs;
5481 ComputeValueVTs(*this, I->getType(), ValueVTs);
5482 for (unsigned Value = 0, NumValues = ValueVTs.size();
5483 Value != NumValues; ++Value) {
5484 MVT VT = ValueVTs[Value];
5485 const Type *ArgTy = VT.getTypeForMVT();
5486 ISD::ArgFlagsTy Flags;
5487 unsigned OriginalAlignment =
5488 getTargetData()->getABITypeAlignment(ArgTy);
5490 if (F.paramHasAttr(j, Attribute::ZExt))
5492 if (F.paramHasAttr(j, Attribute::SExt))
5494 if (F.paramHasAttr(j, Attribute::InReg))
5496 if (F.paramHasAttr(j, Attribute::StructRet))
5498 if (F.paramHasAttr(j, Attribute::ByVal)) {
5500 const PointerType *Ty = cast<PointerType>(I->getType());
5501 const Type *ElementTy = Ty->getElementType();
5502 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5503 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5504 // For ByVal, alignment should be passed from FE. BE will guess if
5505 // this info is not there but there are cases it cannot get right.
5506 if (F.getParamAlignment(j))
5507 FrameAlign = F.getParamAlignment(j);
5508 Flags.setByValAlign(FrameAlign);
5509 Flags.setByValSize(FrameSize);
5511 if (F.paramHasAttr(j, Attribute::Nest))
5513 Flags.setOrigAlign(OriginalAlignment);
5515 MVT RegisterVT = getRegisterType(VT);
5516 unsigned NumRegs = getNumRegisters(VT);
5517 for (unsigned i = 0; i != NumRegs; ++i) {
5518 RetVals.push_back(RegisterVT);
5519 ISD::ArgFlagsTy MyFlags = Flags;
5520 if (NumRegs > 1 && i == 0)
5522 // if it isn't first piece, alignment must be 1
5524 MyFlags.setOrigAlign(1);
5525 Ops.push_back(DAG.getArgFlags(MyFlags));
5530 RetVals.push_back(MVT::Other);
5533 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5534 DAG.getVTList(&RetVals[0], RetVals.size()),
5535 &Ops[0], Ops.size()).getNode();
5537 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5538 // allows exposing the loads that may be part of the argument access to the
5539 // first DAGCombiner pass.
5540 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5542 // The number of results should match up, except that the lowered one may have
5543 // an extra flag result.
5544 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5545 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5546 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5547 && "Lowering produced unexpected number of results!");
5549 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5550 if (Result != TmpRes.getNode() && Result->use_empty()) {
5551 HandleSDNode Dummy(DAG.getRoot());
5552 DAG.RemoveDeadNode(Result);
5555 Result = TmpRes.getNode();
5557 unsigned NumArgRegs = Result->getNumValues() - 1;
5558 DAG.setRoot(SDValue(Result, NumArgRegs));
5560 // Set up the return result vector.
5563 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5565 SmallVector<MVT, 4> ValueVTs;
5566 ComputeValueVTs(*this, I->getType(), ValueVTs);
5567 for (unsigned Value = 0, NumValues = ValueVTs.size();
5568 Value != NumValues; ++Value) {
5569 MVT VT = ValueVTs[Value];
5570 MVT PartVT = getRegisterType(VT);
5572 unsigned NumParts = getNumRegisters(VT);
5573 SmallVector<SDValue, 4> Parts(NumParts);
5574 for (unsigned j = 0; j != NumParts; ++j)
5575 Parts[j] = SDValue(Result, i++);
5577 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5578 if (F.paramHasAttr(Idx, Attribute::SExt))
5579 AssertOp = ISD::AssertSext;
5580 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5581 AssertOp = ISD::AssertZext;
5583 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5584 PartVT, VT, AssertOp));
5587 assert(i == NumArgRegs && "Argument register count mismatch!");
5591 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5592 /// implementation, which just inserts an ISD::CALL node, which is later custom
5593 /// lowered by the target to something concrete. FIXME: When all targets are
5594 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5595 std::pair<SDValue, SDValue>
5596 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5597 bool RetSExt, bool RetZExt, bool isVarArg,
5599 unsigned CallingConv, bool isTailCall,
5601 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5602 assert((!isTailCall || PerformTailCallOpt) &&
5603 "isTailCall set when tail-call optimizations are disabled!");
5605 SmallVector<SDValue, 32> Ops;
5606 Ops.push_back(Chain); // Op#0 - Chain
5607 Ops.push_back(Callee);
5609 // Handle all of the outgoing arguments.
5610 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5611 SmallVector<MVT, 4> ValueVTs;
5612 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5613 for (unsigned Value = 0, NumValues = ValueVTs.size();
5614 Value != NumValues; ++Value) {
5615 MVT VT = ValueVTs[Value];
5616 const Type *ArgTy = VT.getTypeForMVT();
5617 SDValue Op = SDValue(Args[i].Node.getNode(),
5618 Args[i].Node.getResNo() + Value);
5619 ISD::ArgFlagsTy Flags;
5620 unsigned OriginalAlignment =
5621 getTargetData()->getABITypeAlignment(ArgTy);
5627 if (Args[i].isInReg)
5631 if (Args[i].isByVal) {
5633 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5634 const Type *ElementTy = Ty->getElementType();
5635 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5636 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5637 // For ByVal, alignment should come from FE. BE will guess if this
5638 // info is not there but there are cases it cannot get right.
5639 if (Args[i].Alignment)
5640 FrameAlign = Args[i].Alignment;
5641 Flags.setByValAlign(FrameAlign);
5642 Flags.setByValSize(FrameSize);
5646 Flags.setOrigAlign(OriginalAlignment);
5648 MVT PartVT = getRegisterType(VT);
5649 unsigned NumParts = getNumRegisters(VT);
5650 SmallVector<SDValue, 4> Parts(NumParts);
5651 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5654 ExtendKind = ISD::SIGN_EXTEND;
5655 else if (Args[i].isZExt)
5656 ExtendKind = ISD::ZERO_EXTEND;
5658 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5660 for (unsigned i = 0; i != NumParts; ++i) {
5661 // if it isn't first piece, alignment must be 1
5662 ISD::ArgFlagsTy MyFlags = Flags;
5663 if (NumParts > 1 && i == 0)
5666 MyFlags.setOrigAlign(1);
5668 Ops.push_back(Parts[i]);
5669 Ops.push_back(DAG.getArgFlags(MyFlags));
5674 // Figure out the result value types. We start by making a list of
5675 // the potentially illegal return value types.
5676 SmallVector<MVT, 4> LoweredRetTys;
5677 SmallVector<MVT, 4> RetTys;
5678 ComputeValueVTs(*this, RetTy, RetTys);
5680 // Then we translate that to a list of legal types.
5681 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5683 MVT RegisterVT = getRegisterType(VT);
5684 unsigned NumRegs = getNumRegisters(VT);
5685 for (unsigned i = 0; i != NumRegs; ++i)
5686 LoweredRetTys.push_back(RegisterVT);
5689 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5691 // Create the CALL node.
5692 SDValue Res = DAG.getCall(CallingConv, dl,
5693 isVarArg, isTailCall, isInreg,
5694 DAG.getVTList(&LoweredRetTys[0],
5695 LoweredRetTys.size()),
5698 Chain = Res.getValue(LoweredRetTys.size() - 1);
5700 // Gather up the call result into a single value.
5701 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5702 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5705 AssertOp = ISD::AssertSext;
5707 AssertOp = ISD::AssertZext;
5709 SmallVector<SDValue, 4> ReturnValues;
5711 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5713 MVT RegisterVT = getRegisterType(VT);
5714 unsigned NumRegs = getNumRegisters(VT);
5715 unsigned RegNoEnd = NumRegs + RegNo;
5716 SmallVector<SDValue, 4> Results;
5717 for (; RegNo != RegNoEnd; ++RegNo)
5718 Results.push_back(Res.getValue(RegNo));
5719 SDValue ReturnValue =
5720 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5722 ReturnValues.push_back(ReturnValue);
5724 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5725 DAG.getVTList(&RetTys[0], RetTys.size()),
5726 &ReturnValues[0], ReturnValues.size());
5729 return std::make_pair(Res, Chain);
5732 void TargetLowering::LowerOperationWrapper(SDNode *N,
5733 SmallVectorImpl<SDValue> &Results,
5734 SelectionDAG &DAG) {
5735 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5737 Results.push_back(Res);
5740 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5741 assert(0 && "LowerOperation not implemented for this target!");
5747 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5748 SDValue Op = getValue(V);
5749 assert((Op.getOpcode() != ISD::CopyFromReg ||
5750 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5751 "Copy from a reg to the same reg!");
5752 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5754 RegsForValue RFV(TLI, Reg, V->getType());
5755 SDValue Chain = DAG.getEntryNode();
5756 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5757 PendingExports.push_back(Chain);
5760 #include "llvm/CodeGen/SelectionDAGISel.h"
5762 void SelectionDAGISel::
5763 LowerArguments(BasicBlock *LLVMBB) {
5764 // If this is the entry block, emit arguments.
5765 Function &F = *LLVMBB->getParent();
5766 SDValue OldRoot = SDL->DAG.getRoot();
5767 SmallVector<SDValue, 16> Args;
5768 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5771 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5773 SmallVector<MVT, 4> ValueVTs;
5774 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5775 unsigned NumValues = ValueVTs.size();
5776 if (!AI->use_empty()) {
5777 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5778 // If this argument is live outside of the entry block, insert a copy from
5779 // whereever we got it to the vreg that other BB's will reference it as.
5780 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5781 if (VMI != FuncInfo->ValueMap.end()) {
5782 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5788 // Finally, if the target has anything special to do, allow it to do so.
5789 // FIXME: this should insert code into the DAG!
5790 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5793 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5794 /// ensure constants are generated when needed. Remember the virtual registers
5795 /// that need to be added to the Machine PHI nodes as input. We cannot just
5796 /// directly add them, because expansion might result in multiple MBB's for one
5797 /// BB. As such, the start of the BB might correspond to a different MBB than
5801 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5802 TerminatorInst *TI = LLVMBB->getTerminator();
5804 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5806 // Check successor nodes' PHI nodes that expect a constant to be available
5808 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5809 BasicBlock *SuccBB = TI->getSuccessor(succ);
5810 if (!isa<PHINode>(SuccBB->begin())) continue;
5811 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5813 // If this terminator has multiple identical successors (common for
5814 // switches), only handle each succ once.
5815 if (!SuccsHandled.insert(SuccMBB)) continue;
5817 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5820 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5821 // nodes and Machine PHI nodes, but the incoming operands have not been
5823 for (BasicBlock::iterator I = SuccBB->begin();
5824 (PN = dyn_cast<PHINode>(I)); ++I) {
5825 // Ignore dead phi's.
5826 if (PN->use_empty()) continue;
5829 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5831 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5832 unsigned &RegOut = SDL->ConstantsOut[C];
5834 RegOut = FuncInfo->CreateRegForValue(C);
5835 SDL->CopyValueToVirtualRegister(C, RegOut);
5839 Reg = FuncInfo->ValueMap[PHIOp];
5841 assert(isa<AllocaInst>(PHIOp) &&
5842 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5843 "Didn't codegen value into a register!??");
5844 Reg = FuncInfo->CreateRegForValue(PHIOp);
5845 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5849 // Remember that this register needs to added to the machine PHI node as
5850 // the input for this MBB.
5851 SmallVector<MVT, 4> ValueVTs;
5852 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5853 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5854 MVT VT = ValueVTs[vti];
5855 unsigned NumRegisters = TLI.getNumRegisters(VT);
5856 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5857 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5858 Reg += NumRegisters;
5862 SDL->ConstantsOut.clear();
5865 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5866 /// supports legal types, and it emits MachineInstrs directly instead of
5867 /// creating SelectionDAG nodes.
5870 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5872 TerminatorInst *TI = LLVMBB->getTerminator();
5874 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5875 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5877 // Check successor nodes' PHI nodes that expect a constant to be available
5879 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5880 BasicBlock *SuccBB = TI->getSuccessor(succ);
5881 if (!isa<PHINode>(SuccBB->begin())) continue;
5882 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5884 // If this terminator has multiple identical successors (common for
5885 // switches), only handle each succ once.
5886 if (!SuccsHandled.insert(SuccMBB)) continue;
5888 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5891 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5892 // nodes and Machine PHI nodes, but the incoming operands have not been
5894 for (BasicBlock::iterator I = SuccBB->begin();
5895 (PN = dyn_cast<PHINode>(I)); ++I) {
5896 // Ignore dead phi's.
5897 if (PN->use_empty()) continue;
5899 // Only handle legal types. Two interesting things to note here. First,
5900 // by bailing out early, we may leave behind some dead instructions,
5901 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5902 // own moves. Second, this check is necessary becuase FastISel doesn't
5903 // use CreateRegForValue to create registers, so it always creates
5904 // exactly one register for each non-void instruction.
5905 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5906 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5909 VT = TLI.getTypeToTransformTo(VT);
5911 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5916 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5918 unsigned Reg = F->getRegForValue(PHIOp);
5920 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5923 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));