1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Interpret void as zero return values.
139 if (Ty == Type::VoidTy)
141 // Base case: we can get an MVT for this LLVM IR type.
142 ValueVTs.push_back(TLI.getValueType(Ty));
144 Offsets->push_back(StartingOffset);
148 /// RegsForValue - This struct represents the registers (physical or virtual)
149 /// that a particular set of values is assigned, and the type information about
150 /// the value. The most common situation is to represent one value at a time,
151 /// but struct or array values are handled element-wise as multiple values.
152 /// The splitting of aggregates is performed recursively, so that we never
153 /// have aggregate-typed registers. The values at this point do not necessarily
154 /// have legal types, so each value may require one or more registers of some
157 struct VISIBILITY_HIDDEN RegsForValue {
158 /// TLI - The TargetLowering object.
160 const TargetLowering *TLI;
162 /// ValueVTs - The value types of the values, which may not be legal, and
163 /// may need be promoted or synthesized from one or more registers.
165 SmallVector<MVT, 4> ValueVTs;
167 /// RegVTs - The value types of the registers. This is the same size as
168 /// ValueVTs and it records, for each value, what the type of the assigned
169 /// register or registers are. (Individual values are never synthesized
170 /// from more than one type of register.)
172 /// With virtual registers, the contents of RegVTs is redundant with TLI's
173 /// getRegisterType member function, however when with physical registers
174 /// it is necessary to have a separate record of the types.
176 SmallVector<MVT, 4> RegVTs;
178 /// Regs - This list holds the registers assigned to the values.
179 /// Each legal or promoted value requires one register, and each
180 /// expanded value requires multiple registers.
182 SmallVector<unsigned, 4> Regs;
184 RegsForValue() : TLI(0) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 MVT regvt, MVT valuevt)
189 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
190 RegsForValue(const TargetLowering &tli,
191 const SmallVector<unsigned, 4> ®s,
192 const SmallVector<MVT, 4> ®vts,
193 const SmallVector<MVT, 4> &valuevts)
194 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
195 RegsForValue(const TargetLowering &tli,
196 unsigned Reg, const Type *Ty) : TLI(&tli) {
197 ComputeValueVTs(tli, Ty, ValueVTs);
199 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
200 MVT ValueVT = ValueVTs[Value];
201 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
202 MVT RegisterVT = TLI->getRegisterType(ValueVT);
203 for (unsigned i = 0; i != NumRegs; ++i)
204 Regs.push_back(Reg + i);
205 RegVTs.push_back(RegisterVT);
210 /// append - Add the specified values to this one.
211 void append(const RegsForValue &RHS) {
213 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
214 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
215 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
219 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
220 /// this value and returns the result as a ValueVTs value. This uses
221 /// Chain/Flag as the input and updates them for the output Chain/Flag.
222 /// If the Flag pointer is NULL, no flag is used.
223 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
224 SDValue &Chain, SDValue *Flag) const;
226 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
227 /// specified value into the registers specified by this object. This uses
228 /// Chain/Flag as the input and updates them for the output Chain/Flag.
229 /// If the Flag pointer is NULL, no flag is used.
230 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
231 SDValue &Chain, SDValue *Flag) const;
233 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
234 /// operand list. This adds the code marker, matching input operand index
235 /// (if applicable), and includes the number of values added into it.
236 void AddInlineAsmOperands(unsigned Code,
237 bool HasMatching, unsigned MatchingIdx,
238 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
242 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
243 /// PHI nodes or outside of the basic block that defines it, or used by a
244 /// switch or atomic instruction, which may expand to multiple basic blocks.
245 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
246 if (isa<PHINode>(I)) return true;
247 BasicBlock *BB = I->getParent();
248 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
249 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
254 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
255 /// entry block, return true. This includes arguments used by switches, since
256 /// the switch may expand into multiple basic blocks.
257 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
258 // With FastISel active, we may be splitting blocks, so force creation
259 // of virtual registers for all non-dead arguments.
260 // Don't force virtual registers for byval arguments though, because
261 // fast-isel can't handle those in all cases.
262 if (EnableFastISel && !A->hasByValAttr())
263 return A->use_empty();
265 BasicBlock *Entry = A->getParent()->begin();
266 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
267 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
268 return false; // Use not in entry block.
272 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
276 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 bool EnableFastISel) {
281 RegInfo = &MF->getRegInfo();
283 // Create a vreg for each argument register that is not dead and is used
284 // outside of the entry block for the function.
285 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
288 InitializeRegForValue(AI);
290 // Initialize the mapping of values to registers. This is only set up for
291 // instruction values that are used outside of the block that defines
293 Function::iterator BB = Fn->begin(), EB = Fn->end();
294 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
295 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
296 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
297 const Type *Ty = AI->getAllocatedType();
298 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
300 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
303 TySize *= CUI->getZExtValue(); // Get total allocated size.
304 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
305 StaticAllocaMap[AI] =
306 MF->getFrameInfo()->CreateStackObject(TySize, Align);
309 for (; BB != EB; ++BB)
310 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
311 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
312 if (!isa<AllocaInst>(I) ||
313 !StaticAllocaMap.count(cast<AllocaInst>(I)))
314 InitializeRegForValue(I);
316 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
317 // also creates the initial PHI MachineInstrs, though none of the input
318 // operands are populated.
319 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
320 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
324 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
328 for (BasicBlock::iterator
329 I = BB->begin(), E = BB->end(); I != E; ++I) {
330 if (CallInst *CI = dyn_cast<CallInst>(I)) {
331 if (Function *F = CI->getCalledFunction()) {
332 switch (F->getIntrinsicID()) {
334 case Intrinsic::dbg_stoppoint: {
335 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
336 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
337 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
340 case Intrinsic::dbg_func_start: {
341 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
342 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
343 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
350 PN = dyn_cast<PHINode>(I);
351 if (!PN || PN->use_empty()) continue;
353 unsigned PHIReg = ValueMap[PN];
354 assert(PHIReg && "PHI node does not have an assigned virtual register!");
356 SmallVector<MVT, 4> ValueVTs;
357 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
358 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
359 MVT VT = ValueVTs[vti];
360 unsigned NumRegisters = TLI.getNumRegisters(VT);
361 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
362 for (unsigned i = 0; i != NumRegisters; ++i)
363 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
364 PHIReg += NumRegisters;
370 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
371 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
374 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
375 /// the correctly promoted or expanded types. Assign these registers
376 /// consecutive vreg numbers and return the first assigned number.
378 /// In the case that the given value has struct or array type, this function
379 /// will assign registers for each member or element.
381 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
382 SmallVector<MVT, 4> ValueVTs;
383 ComputeValueVTs(TLI, V->getType(), ValueVTs);
385 unsigned FirstReg = 0;
386 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
387 MVT ValueVT = ValueVTs[Value];
388 MVT RegisterVT = TLI.getRegisterType(ValueVT);
390 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
391 for (unsigned i = 0; i != NumRegs; ++i) {
392 unsigned R = MakeReg(RegisterVT);
393 if (!FirstReg) FirstReg = R;
399 /// getCopyFromParts - Create a value that contains the specified legal parts
400 /// combined into the value they represent. If the parts combine to a type
401 /// larger then ValueVT then AssertOp can be used to specify whether the extra
402 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
403 /// (ISD::AssertSext).
404 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
405 const SDValue *Parts,
406 unsigned NumParts, MVT PartVT, MVT ValueVT,
407 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
408 assert(NumParts > 0 && "No parts to assemble!");
409 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
410 SDValue Val = Parts[0];
413 // Assemble the value from multiple parts.
414 if (!ValueVT.isVector() && ValueVT.isInteger()) {
415 unsigned PartBits = PartVT.getSizeInBits();
416 unsigned ValueBits = ValueVT.getSizeInBits();
418 // Assemble the power of 2 part.
419 unsigned RoundParts = NumParts & (NumParts - 1) ?
420 1 << Log2_32(NumParts) : NumParts;
421 unsigned RoundBits = PartBits * RoundParts;
422 MVT RoundVT = RoundBits == ValueBits ?
423 ValueVT : MVT::getIntegerVT(RoundBits);
426 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
428 if (RoundParts > 2) {
429 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
430 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
433 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
434 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
436 if (TLI.isBigEndian())
438 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
440 if (RoundParts < NumParts) {
441 // Assemble the trailing non-power-of-2 part.
442 unsigned OddParts = NumParts - RoundParts;
443 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
444 Hi = getCopyFromParts(DAG, dl,
445 Parts+RoundParts, OddParts, PartVT, OddVT);
447 // Combine the round and odd parts.
449 if (TLI.isBigEndian())
451 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
452 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
453 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
454 DAG.getConstant(Lo.getValueType().getSizeInBits(),
455 TLI.getPointerTy()));
456 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
457 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
459 } else if (ValueVT.isVector()) {
460 // Handle a multi-element vector.
461 MVT IntermediateVT, RegisterVT;
462 unsigned NumIntermediates;
464 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
466 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
467 NumParts = NumRegs; // Silence a compiler warning.
468 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
469 assert(RegisterVT == Parts[0].getValueType() &&
470 "Part type doesn't match part!");
472 // Assemble the parts into intermediate operands.
473 SmallVector<SDValue, 8> Ops(NumIntermediates);
474 if (NumIntermediates == NumParts) {
475 // If the register was not expanded, truncate or copy the value,
477 for (unsigned i = 0; i != NumParts; ++i)
478 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
479 PartVT, IntermediateVT);
480 } else if (NumParts > 0) {
481 // If the intermediate type was expanded, build the intermediate operands
483 assert(NumParts % NumIntermediates == 0 &&
484 "Must expand into a divisible number of parts!");
485 unsigned Factor = NumParts / NumIntermediates;
486 for (unsigned i = 0; i != NumIntermediates; ++i)
487 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
488 PartVT, IntermediateVT);
491 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
493 Val = DAG.getNode(IntermediateVT.isVector() ?
494 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
495 ValueVT, &Ops[0], NumIntermediates);
496 } else if (PartVT.isFloatingPoint()) {
497 // FP split into multiple FP parts (for ppcf128)
498 assert(ValueVT == MVT(MVT::ppcf128) && PartVT == MVT(MVT::f64) &&
501 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[0]);
502 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[1]);
503 if (TLI.isBigEndian())
505 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
507 // FP split into integer parts (soft fp)
508 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
509 !PartVT.isVector() && "Unexpected split");
510 MVT IntVT = MVT::getIntegerVT(ValueVT.getSizeInBits());
511 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
515 // There is now one part, held in Val. Correct it to match ValueVT.
516 PartVT = Val.getValueType();
518 if (PartVT == ValueVT)
521 if (PartVT.isVector()) {
522 assert(ValueVT.isVector() && "Unknown vector conversion!");
523 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
526 if (ValueVT.isVector()) {
527 assert(ValueVT.getVectorElementType() == PartVT &&
528 ValueVT.getVectorNumElements() == 1 &&
529 "Only trivial scalar-to-vector conversions should get here!");
530 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
533 if (PartVT.isInteger() &&
534 ValueVT.isInteger()) {
535 if (ValueVT.bitsLT(PartVT)) {
536 // For a truncate, see if we have any information to
537 // indicate whether the truncated bits will always be
538 // zero or sign-extension.
539 if (AssertOp != ISD::DELETED_NODE)
540 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
541 DAG.getValueType(ValueVT));
542 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
544 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
548 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
549 if (ValueVT.bitsLT(Val.getValueType()))
550 // FP_ROUND's are always exact here.
551 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
552 DAG.getIntPtrConstant(1));
553 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
556 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
557 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
559 llvm_unreachable("Unknown mismatch!");
563 /// getCopyToParts - Create a series of nodes that contain the specified value
564 /// split into legal parts. If the parts contain more bits than Val, then, for
565 /// integers, ExtendKind can be used to specify how to generate the extra bits.
566 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
567 SDValue *Parts, unsigned NumParts, MVT PartVT,
568 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
569 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
570 MVT PtrVT = TLI.getPointerTy();
571 MVT ValueVT = Val.getValueType();
572 unsigned PartBits = PartVT.getSizeInBits();
573 unsigned OrigNumParts = NumParts;
574 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
579 if (!ValueVT.isVector()) {
580 if (PartVT == ValueVT) {
581 assert(NumParts == 1 && "No-op copy with multiple parts!");
586 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
587 // If the parts cover more bits than the value has, promote the value.
588 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
589 assert(NumParts == 1 && "Do not know what to promote to!");
590 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
591 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
592 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
593 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
595 llvm_unreachable("Unknown mismatch!");
597 } else if (PartBits == ValueVT.getSizeInBits()) {
598 // Different types of the same size.
599 assert(NumParts == 1 && PartVT != ValueVT);
600 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
601 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
602 // If the parts cover less bits than value has, truncate the value.
603 if (PartVT.isInteger() && ValueVT.isInteger()) {
604 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
605 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
607 llvm_unreachable("Unknown mismatch!");
611 // The value may have changed - recompute ValueVT.
612 ValueVT = Val.getValueType();
613 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
614 "Failed to tile the value with PartVT!");
617 assert(PartVT == ValueVT && "Type conversion failed!");
622 // Expand the value into multiple parts.
623 if (NumParts & (NumParts - 1)) {
624 // The number of parts is not a power of 2. Split off and copy the tail.
625 assert(PartVT.isInteger() && ValueVT.isInteger() &&
626 "Do not know what to expand to!");
627 unsigned RoundParts = 1 << Log2_32(NumParts);
628 unsigned RoundBits = RoundParts * PartBits;
629 unsigned OddParts = NumParts - RoundParts;
630 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
631 DAG.getConstant(RoundBits,
632 TLI.getPointerTy()));
633 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
634 if (TLI.isBigEndian())
635 // The odd parts were reversed by getCopyToParts - unreverse them.
636 std::reverse(Parts + RoundParts, Parts + NumParts);
637 NumParts = RoundParts;
638 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
639 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
642 // The number of parts is a power of 2. Repeatedly bisect the value using
644 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
645 MVT::getIntegerVT(ValueVT.getSizeInBits()),
647 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
648 for (unsigned i = 0; i < NumParts; i += StepSize) {
649 unsigned ThisBits = StepSize * PartBits / 2;
650 MVT ThisVT = MVT::getIntegerVT (ThisBits);
651 SDValue &Part0 = Parts[i];
652 SDValue &Part1 = Parts[i+StepSize/2];
654 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
656 DAG.getConstant(1, PtrVT));
657 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
659 DAG.getConstant(0, PtrVT));
661 if (ThisBits == PartBits && ThisVT != PartVT) {
662 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
664 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
670 if (TLI.isBigEndian())
671 std::reverse(Parts, Parts + OrigNumParts);
678 if (PartVT != ValueVT) {
679 if (PartVT.isVector()) {
680 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
682 assert(ValueVT.getVectorElementType() == PartVT &&
683 ValueVT.getVectorNumElements() == 1 &&
684 "Only trivial vector-to-scalar conversions should get here!");
685 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
687 DAG.getConstant(0, PtrVT));
695 // Handle a multi-element vector.
696 MVT IntermediateVT, RegisterVT;
697 unsigned NumIntermediates;
698 unsigned NumRegs = TLI
699 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
701 unsigned NumElements = ValueVT.getVectorNumElements();
703 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
704 NumParts = NumRegs; // Silence a compiler warning.
705 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
707 // Split the vector into intermediate operands.
708 SmallVector<SDValue, 8> Ops(NumIntermediates);
709 for (unsigned i = 0; i != NumIntermediates; ++i)
710 if (IntermediateVT.isVector())
711 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
713 DAG.getConstant(i * (NumElements / NumIntermediates),
716 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
718 DAG.getConstant(i, PtrVT));
720 // Split the intermediate operands into legal parts.
721 if (NumParts == NumIntermediates) {
722 // If the register was not expanded, promote or copy the value,
724 for (unsigned i = 0; i != NumParts; ++i)
725 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
726 } else if (NumParts > 0) {
727 // If the intermediate type was expanded, split each the value into
729 assert(NumParts % NumIntermediates == 0 &&
730 "Must expand into a divisible number of parts!");
731 unsigned Factor = NumParts / NumIntermediates;
732 for (unsigned i = 0; i != NumIntermediates; ++i)
733 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
738 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
741 TD = DAG.getTarget().getTargetData();
744 /// clear - Clear out the curret SelectionDAG and the associated
745 /// state and prepare this SelectionDAGLowering object to be used
746 /// for a new block. This doesn't clear out information about
747 /// additional blocks that are needed to complete switch lowering
748 /// or PHI node updating; that information is cleared out as it is
750 void SelectionDAGLowering::clear() {
752 PendingLoads.clear();
753 PendingExports.clear();
755 CurDebugLoc = DebugLoc::getUnknownLoc();
758 /// getRoot - Return the current virtual root of the Selection DAG,
759 /// flushing any PendingLoad items. This must be done before emitting
760 /// a store or any other node that may need to be ordered after any
761 /// prior load instructions.
763 SDValue SelectionDAGLowering::getRoot() {
764 if (PendingLoads.empty())
765 return DAG.getRoot();
767 if (PendingLoads.size() == 1) {
768 SDValue Root = PendingLoads[0];
770 PendingLoads.clear();
774 // Otherwise, we have to make a token factor node.
775 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
776 &PendingLoads[0], PendingLoads.size());
777 PendingLoads.clear();
782 /// getControlRoot - Similar to getRoot, but instead of flushing all the
783 /// PendingLoad items, flush all the PendingExports items. It is necessary
784 /// to do this before emitting a terminator instruction.
786 SDValue SelectionDAGLowering::getControlRoot() {
787 SDValue Root = DAG.getRoot();
789 if (PendingExports.empty())
792 // Turn all of the CopyToReg chains into one factored node.
793 if (Root.getOpcode() != ISD::EntryToken) {
794 unsigned i = 0, e = PendingExports.size();
795 for (; i != e; ++i) {
796 assert(PendingExports[i].getNode()->getNumOperands() > 1);
797 if (PendingExports[i].getNode()->getOperand(0) == Root)
798 break; // Don't add the root if we already indirectly depend on it.
802 PendingExports.push_back(Root);
805 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
807 PendingExports.size());
808 PendingExports.clear();
813 void SelectionDAGLowering::visit(Instruction &I) {
814 visit(I.getOpcode(), I);
817 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
818 // Note: this doesn't use InstVisitor, because it has to work with
819 // ConstantExpr's in addition to instructions.
821 default: llvm_unreachable("Unknown instruction type encountered!");
822 // Build the switch statement using the Instruction.def file.
823 #define HANDLE_INST(NUM, OPCODE, CLASS) \
824 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
825 #include "llvm/Instruction.def"
829 SDValue SelectionDAGLowering::getValue(const Value *V) {
830 SDValue &N = NodeMap[V];
831 if (N.getNode()) return N;
833 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
834 MVT VT = TLI.getValueType(V->getType(), true);
836 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
837 return N = DAG.getConstant(*CI, VT);
839 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
840 return N = DAG.getGlobalAddress(GV, VT);
842 if (isa<ConstantPointerNull>(C))
843 return N = DAG.getConstant(0, TLI.getPointerTy());
845 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
846 return N = DAG.getConstantFP(*CFP, VT);
848 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
849 return N = DAG.getUNDEF(VT);
851 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
852 visit(CE->getOpcode(), *CE);
853 SDValue N1 = NodeMap[V];
854 assert(N1.getNode() && "visit didn't populate the ValueMap!");
858 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
859 SmallVector<SDValue, 4> Constants;
860 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
862 SDNode *Val = getValue(*OI).getNode();
863 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
864 Constants.push_back(SDValue(Val, i));
866 return DAG.getMergeValues(&Constants[0], Constants.size(),
870 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
871 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
872 "Unknown struct or array constant!");
874 SmallVector<MVT, 4> ValueVTs;
875 ComputeValueVTs(TLI, C->getType(), ValueVTs);
876 unsigned NumElts = ValueVTs.size();
878 return SDValue(); // empty struct
879 SmallVector<SDValue, 4> Constants(NumElts);
880 for (unsigned i = 0; i != NumElts; ++i) {
881 MVT EltVT = ValueVTs[i];
882 if (isa<UndefValue>(C))
883 Constants[i] = DAG.getUNDEF(EltVT);
884 else if (EltVT.isFloatingPoint())
885 Constants[i] = DAG.getConstantFP(0, EltVT);
887 Constants[i] = DAG.getConstant(0, EltVT);
889 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
892 const VectorType *VecTy = cast<VectorType>(V->getType());
893 unsigned NumElements = VecTy->getNumElements();
895 // Now that we know the number and type of the elements, get that number of
896 // elements into the Ops array based on what kind of constant it is.
897 SmallVector<SDValue, 16> Ops;
898 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
899 for (unsigned i = 0; i != NumElements; ++i)
900 Ops.push_back(getValue(CP->getOperand(i)));
902 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
903 MVT EltVT = TLI.getValueType(VecTy->getElementType());
906 if (EltVT.isFloatingPoint())
907 Op = DAG.getConstantFP(0, EltVT);
909 Op = DAG.getConstant(0, EltVT);
910 Ops.assign(NumElements, Op);
913 // Create a BUILD_VECTOR node.
914 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
915 VT, &Ops[0], Ops.size());
918 // If this is a static alloca, generate it as the frameindex instead of
920 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
921 DenseMap<const AllocaInst*, int>::iterator SI =
922 FuncInfo.StaticAllocaMap.find(AI);
923 if (SI != FuncInfo.StaticAllocaMap.end())
924 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
927 unsigned InReg = FuncInfo.ValueMap[V];
928 assert(InReg && "Value not in map!");
930 RegsForValue RFV(TLI, InReg, V->getType());
931 SDValue Chain = DAG.getEntryNode();
932 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
936 void SelectionDAGLowering::visitRet(ReturnInst &I) {
937 if (I.getNumOperands() == 0) {
938 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
939 MVT::Other, getControlRoot()));
943 SmallVector<SDValue, 8> NewValues;
944 NewValues.push_back(getControlRoot());
945 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
946 SmallVector<MVT, 4> ValueVTs;
947 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
948 unsigned NumValues = ValueVTs.size();
949 if (NumValues == 0) continue;
951 SDValue RetOp = getValue(I.getOperand(i));
952 for (unsigned j = 0, f = NumValues; j != f; ++j) {
953 MVT VT = ValueVTs[j];
955 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
957 const Function *F = I.getParent()->getParent();
958 if (F->paramHasAttr(0, Attribute::SExt))
959 ExtendKind = ISD::SIGN_EXTEND;
960 else if (F->paramHasAttr(0, Attribute::ZExt))
961 ExtendKind = ISD::ZERO_EXTEND;
963 // FIXME: C calling convention requires the return type to be promoted to
964 // at least 32-bit. But this is not necessary for non-C calling
965 // conventions. The frontend should mark functions whose return values
966 // require promoting with signext or zeroext attributes.
967 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
968 MVT MinVT = TLI.getRegisterType(MVT::i32);
969 if (VT.bitsLT(MinVT))
973 unsigned NumParts = TLI.getNumRegisters(VT);
974 MVT PartVT = TLI.getRegisterType(VT);
975 SmallVector<SDValue, 4> Parts(NumParts);
976 getCopyToParts(DAG, getCurDebugLoc(),
977 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
978 &Parts[0], NumParts, PartVT, ExtendKind);
980 // 'inreg' on function refers to return value
981 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
982 if (F->paramHasAttr(0, Attribute::InReg))
985 // Propagate extension type if any
986 if (F->paramHasAttr(0, Attribute::SExt))
988 else if (F->paramHasAttr(0, Attribute::ZExt))
991 for (unsigned i = 0; i < NumParts; ++i) {
992 NewValues.push_back(Parts[i]);
993 NewValues.push_back(DAG.getArgFlags(Flags));
997 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
998 &NewValues[0], NewValues.size()));
1001 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1002 /// created for it, emit nodes to copy the value into the virtual
1004 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1005 if (!V->use_empty()) {
1006 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1007 if (VMI != FuncInfo.ValueMap.end())
1008 CopyValueToVirtualRegister(V, VMI->second);
1012 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1013 /// the current basic block, add it to ValueMap now so that we'll get a
1015 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1016 // No need to export constants.
1017 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1019 // Already exported?
1020 if (FuncInfo.isExportedInst(V)) return;
1022 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1023 CopyValueToVirtualRegister(V, Reg);
1026 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1027 const BasicBlock *FromBB) {
1028 // The operands of the setcc have to be in this block. We don't know
1029 // how to export them from some other block.
1030 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1031 // Can export from current BB.
1032 if (VI->getParent() == FromBB)
1035 // Is already exported, noop.
1036 return FuncInfo.isExportedInst(V);
1039 // If this is an argument, we can export it if the BB is the entry block or
1040 // if it is already exported.
1041 if (isa<Argument>(V)) {
1042 if (FromBB == &FromBB->getParent()->getEntryBlock())
1045 // Otherwise, can only export this if it is already exported.
1046 return FuncInfo.isExportedInst(V);
1049 // Otherwise, constants can always be exported.
1053 static bool InBlock(const Value *V, const BasicBlock *BB) {
1054 if (const Instruction *I = dyn_cast<Instruction>(V))
1055 return I->getParent() == BB;
1059 /// getFCmpCondCode - Return the ISD condition code corresponding to
1060 /// the given LLVM IR floating-point condition code. This includes
1061 /// consideration of global floating-point math flags.
1063 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1064 ISD::CondCode FPC, FOC;
1066 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1067 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1068 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1069 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1070 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1071 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1072 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1073 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1074 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1075 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1076 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1077 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1078 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1079 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1080 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1081 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1083 llvm_unreachable("Invalid FCmp predicate opcode!");
1084 FOC = FPC = ISD::SETFALSE;
1087 if (FiniteOnlyFPMath())
1093 /// getICmpCondCode - Return the ISD condition code corresponding to
1094 /// the given LLVM IR integer condition code.
1096 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1098 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1099 case ICmpInst::ICMP_NE: return ISD::SETNE;
1100 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1101 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1102 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1103 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1104 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1105 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1106 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1107 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1109 llvm_unreachable("Invalid ICmp predicate opcode!");
1114 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1115 /// This function emits a branch and is used at the leaves of an OR or an
1116 /// AND operator tree.
1119 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1120 MachineBasicBlock *TBB,
1121 MachineBasicBlock *FBB,
1122 MachineBasicBlock *CurBB) {
1123 const BasicBlock *BB = CurBB->getBasicBlock();
1125 // If the leaf of the tree is a comparison, merge the condition into
1127 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1128 // The operands of the cmp have to be in this block. We don't know
1129 // how to export them from some other block. If this is the first block
1130 // of the sequence, no exporting is needed.
1131 if (CurBB == CurMBB ||
1132 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1133 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1134 ISD::CondCode Condition;
1135 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1136 Condition = getICmpCondCode(IC->getPredicate());
1137 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1138 Condition = getFCmpCondCode(FC->getPredicate());
1140 Condition = ISD::SETEQ; // silence warning.
1141 llvm_unreachable("Unknown compare instruction");
1144 CaseBlock CB(Condition, BOp->getOperand(0),
1145 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1146 SwitchCases.push_back(CB);
1151 // Create a CaseBlock record representing this branch.
1152 CaseBlock CB(ISD::SETEQ, Cond, DAG.getContext()->getTrue(),
1153 NULL, TBB, FBB, CurBB);
1154 SwitchCases.push_back(CB);
1157 /// FindMergedConditions - If Cond is an expression like
1158 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1159 MachineBasicBlock *TBB,
1160 MachineBasicBlock *FBB,
1161 MachineBasicBlock *CurBB,
1163 // If this node is not part of the or/and tree, emit it as a branch.
1164 Instruction *BOp = dyn_cast<Instruction>(Cond);
1165 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1166 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1167 BOp->getParent() != CurBB->getBasicBlock() ||
1168 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1169 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1170 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1174 // Create TmpBB after CurBB.
1175 MachineFunction::iterator BBI = CurBB;
1176 MachineFunction &MF = DAG.getMachineFunction();
1177 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1178 CurBB->getParent()->insert(++BBI, TmpBB);
1180 if (Opc == Instruction::Or) {
1181 // Codegen X | Y as:
1189 // Emit the LHS condition.
1190 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1192 // Emit the RHS condition into TmpBB.
1193 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1195 assert(Opc == Instruction::And && "Unknown merge op!");
1196 // Codegen X & Y as:
1203 // This requires creation of TmpBB after CurBB.
1205 // Emit the LHS condition.
1206 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1208 // Emit the RHS condition into TmpBB.
1209 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1213 /// If the set of cases should be emitted as a series of branches, return true.
1214 /// If we should emit this as a bunch of and/or'd together conditions, return
1217 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1218 if (Cases.size() != 2) return true;
1220 // If this is two comparisons of the same values or'd or and'd together, they
1221 // will get folded into a single comparison, so don't emit two blocks.
1222 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1223 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1224 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1225 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1232 void SelectionDAGLowering::visitBr(BranchInst &I) {
1233 // Update machine-CFG edges.
1234 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1236 // Figure out which block is immediately after the current one.
1237 MachineBasicBlock *NextBlock = 0;
1238 MachineFunction::iterator BBI = CurMBB;
1239 if (++BBI != CurMBB->getParent()->end())
1242 if (I.isUnconditional()) {
1243 // Update machine-CFG edges.
1244 CurMBB->addSuccessor(Succ0MBB);
1246 // If this is not a fall-through branch, emit the branch.
1247 if (Succ0MBB != NextBlock)
1248 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1249 MVT::Other, getControlRoot(),
1250 DAG.getBasicBlock(Succ0MBB)));
1254 // If this condition is one of the special cases we handle, do special stuff
1256 Value *CondVal = I.getCondition();
1257 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1259 // If this is a series of conditions that are or'd or and'd together, emit
1260 // this as a sequence of branches instead of setcc's with and/or operations.
1261 // For example, instead of something like:
1274 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1275 if (BOp->hasOneUse() &&
1276 (BOp->getOpcode() == Instruction::And ||
1277 BOp->getOpcode() == Instruction::Or)) {
1278 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1279 // If the compares in later blocks need to use values not currently
1280 // exported from this block, export them now. This block should always
1281 // be the first entry.
1282 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1284 // Allow some cases to be rejected.
1285 if (ShouldEmitAsBranches(SwitchCases)) {
1286 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1287 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1288 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1291 // Emit the branch for this block.
1292 visitSwitchCase(SwitchCases[0]);
1293 SwitchCases.erase(SwitchCases.begin());
1297 // Okay, we decided not to do this, remove any inserted MBB's and clear
1299 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1300 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1302 SwitchCases.clear();
1306 // Create a CaseBlock record representing this branch.
1307 CaseBlock CB(ISD::SETEQ, CondVal, DAG.getContext()->getTrue(),
1308 NULL, Succ0MBB, Succ1MBB, CurMBB);
1309 // Use visitSwitchCase to actually insert the fast branch sequence for this
1311 visitSwitchCase(CB);
1314 /// visitSwitchCase - Emits the necessary code to represent a single node in
1315 /// the binary search tree resulting from lowering a switch instruction.
1316 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1318 SDValue CondLHS = getValue(CB.CmpLHS);
1319 DebugLoc dl = getCurDebugLoc();
1321 // Build the setcc now.
1322 if (CB.CmpMHS == NULL) {
1323 // Fold "(X == true)" to X and "(X == false)" to !X to
1324 // handle common cases produced by branch lowering.
1325 if (CB.CmpRHS == DAG.getContext()->getTrue() &&
1326 CB.CC == ISD::SETEQ)
1328 else if (CB.CmpRHS == DAG.getContext()->getFalse() &&
1329 CB.CC == ISD::SETEQ) {
1330 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1331 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1333 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1335 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1337 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1338 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1340 SDValue CmpOp = getValue(CB.CmpMHS);
1341 MVT VT = CmpOp.getValueType();
1343 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1344 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1347 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1348 VT, CmpOp, DAG.getConstant(Low, VT));
1349 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1350 DAG.getConstant(High-Low, VT), ISD::SETULE);
1354 // Update successor info
1355 CurMBB->addSuccessor(CB.TrueBB);
1356 CurMBB->addSuccessor(CB.FalseBB);
1358 // Set NextBlock to be the MBB immediately after the current one, if any.
1359 // This is used to avoid emitting unnecessary branches to the next block.
1360 MachineBasicBlock *NextBlock = 0;
1361 MachineFunction::iterator BBI = CurMBB;
1362 if (++BBI != CurMBB->getParent()->end())
1365 // If the lhs block is the next block, invert the condition so that we can
1366 // fall through to the lhs instead of the rhs block.
1367 if (CB.TrueBB == NextBlock) {
1368 std::swap(CB.TrueBB, CB.FalseBB);
1369 SDValue True = DAG.getConstant(1, Cond.getValueType());
1370 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1372 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1373 MVT::Other, getControlRoot(), Cond,
1374 DAG.getBasicBlock(CB.TrueBB));
1376 // If the branch was constant folded, fix up the CFG.
1377 if (BrCond.getOpcode() == ISD::BR) {
1378 CurMBB->removeSuccessor(CB.FalseBB);
1379 DAG.setRoot(BrCond);
1381 // Otherwise, go ahead and insert the false branch.
1382 if (BrCond == getControlRoot())
1383 CurMBB->removeSuccessor(CB.TrueBB);
1385 if (CB.FalseBB == NextBlock)
1386 DAG.setRoot(BrCond);
1388 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1389 DAG.getBasicBlock(CB.FalseBB)));
1393 /// visitJumpTable - Emit JumpTable node in the current MBB
1394 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1395 // Emit the code for the jump table
1396 assert(JT.Reg != -1U && "Should lower JT Header first!");
1397 MVT PTy = TLI.getPointerTy();
1398 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1400 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1401 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1402 MVT::Other, Index.getValue(1),
1406 /// visitJumpTableHeader - This function emits necessary code to produce index
1407 /// in the JumpTable from switch case.
1408 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1409 JumpTableHeader &JTH) {
1410 // Subtract the lowest switch case value from the value being switched on and
1411 // conditional branch to default mbb if the result is greater than the
1412 // difference between smallest and largest cases.
1413 SDValue SwitchOp = getValue(JTH.SValue);
1414 MVT VT = SwitchOp.getValueType();
1415 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1416 DAG.getConstant(JTH.First, VT));
1418 // The SDNode we just created, which holds the value being switched on minus
1419 // the the smallest case value, needs to be copied to a virtual register so it
1420 // can be used as an index into the jump table in a subsequent basic block.
1421 // This value may be smaller or larger than the target's pointer type, and
1422 // therefore require extension or truncating.
1423 if (VT.bitsGT(TLI.getPointerTy()))
1424 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1425 TLI.getPointerTy(), SUB);
1427 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1428 TLI.getPointerTy(), SUB);
1430 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1431 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1432 JumpTableReg, SwitchOp);
1433 JT.Reg = JumpTableReg;
1435 // Emit the range check for the jump table, and branch to the default block
1436 // for the switch statement if the value being switched on exceeds the largest
1437 // case in the switch.
1438 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1439 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1440 DAG.getConstant(JTH.Last-JTH.First,VT),
1443 // Set NextBlock to be the MBB immediately after the current one, if any.
1444 // This is used to avoid emitting unnecessary branches to the next block.
1445 MachineBasicBlock *NextBlock = 0;
1446 MachineFunction::iterator BBI = CurMBB;
1447 if (++BBI != CurMBB->getParent()->end())
1450 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1451 MVT::Other, CopyTo, CMP,
1452 DAG.getBasicBlock(JT.Default));
1454 if (JT.MBB == NextBlock)
1455 DAG.setRoot(BrCond);
1457 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1458 DAG.getBasicBlock(JT.MBB)));
1461 /// visitBitTestHeader - This function emits necessary code to produce value
1462 /// suitable for "bit tests"
1463 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1464 // Subtract the minimum value
1465 SDValue SwitchOp = getValue(B.SValue);
1466 MVT VT = SwitchOp.getValueType();
1467 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1468 DAG.getConstant(B.First, VT));
1471 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1472 TLI.getSetCCResultType(SUB.getValueType()),
1473 SUB, DAG.getConstant(B.Range, VT),
1477 if (VT.bitsGT(TLI.getPointerTy()))
1478 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1479 TLI.getPointerTy(), SUB);
1481 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1482 TLI.getPointerTy(), SUB);
1484 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1485 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = CurMBB;
1492 if (++BBI != CurMBB->getParent()->end())
1495 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1497 CurMBB->addSuccessor(B.Default);
1498 CurMBB->addSuccessor(MBB);
1500 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1501 MVT::Other, CopyTo, RangeCmp,
1502 DAG.getBasicBlock(B.Default));
1504 if (MBB == NextBlock)
1505 DAG.setRoot(BrRange);
1507 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1508 DAG.getBasicBlock(MBB)));
1511 /// visitBitTestCase - this function produces one "bit test"
1512 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1515 // Make desired shift
1516 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1517 TLI.getPointerTy());
1518 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1520 DAG.getConstant(1, TLI.getPointerTy()),
1523 // Emit bit tests and jumps
1524 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1525 TLI.getPointerTy(), SwitchVal,
1526 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1527 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1528 TLI.getSetCCResultType(AndOp.getValueType()),
1529 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1532 CurMBB->addSuccessor(B.TargetBB);
1533 CurMBB->addSuccessor(NextMBB);
1535 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1536 MVT::Other, getControlRoot(),
1537 AndCmp, DAG.getBasicBlock(B.TargetBB));
1539 // Set NextBlock to be the MBB immediately after the current one, if any.
1540 // This is used to avoid emitting unnecessary branches to the next block.
1541 MachineBasicBlock *NextBlock = 0;
1542 MachineFunction::iterator BBI = CurMBB;
1543 if (++BBI != CurMBB->getParent()->end())
1546 if (NextMBB == NextBlock)
1549 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1550 DAG.getBasicBlock(NextMBB)));
1553 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1554 // Retrieve successors.
1555 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1556 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1558 const Value *Callee(I.getCalledValue());
1559 if (isa<InlineAsm>(Callee))
1562 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1564 // If the value of the invoke is used outside of its defining block, make it
1565 // available as a virtual register.
1566 CopyToExportRegsIfNeeded(&I);
1568 // Update successor info
1569 CurMBB->addSuccessor(Return);
1570 CurMBB->addSuccessor(LandingPad);
1572 // Drop into normal successor.
1573 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1574 MVT::Other, getControlRoot(),
1575 DAG.getBasicBlock(Return)));
1578 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1581 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1582 /// small case ranges).
1583 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1584 CaseRecVector& WorkList,
1586 MachineBasicBlock* Default) {
1587 Case& BackCase = *(CR.Range.second-1);
1589 // Size is the number of Cases represented by this range.
1590 size_t Size = CR.Range.second - CR.Range.first;
1594 // Get the MachineFunction which holds the current MBB. This is used when
1595 // inserting any additional MBBs necessary to represent the switch.
1596 MachineFunction *CurMF = CurMBB->getParent();
1598 // Figure out which block is immediately after the current one.
1599 MachineBasicBlock *NextBlock = 0;
1600 MachineFunction::iterator BBI = CR.CaseBB;
1602 if (++BBI != CurMBB->getParent()->end())
1605 // TODO: If any two of the cases has the same destination, and if one value
1606 // is the same as the other, but has one bit unset that the other has set,
1607 // use bit manipulation to do two compares at once. For example:
1608 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1610 // Rearrange the case blocks so that the last one falls through if possible.
1611 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1612 // The last case block won't fall through into 'NextBlock' if we emit the
1613 // branches in this order. See if rearranging a case value would help.
1614 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1615 if (I->BB == NextBlock) {
1616 std::swap(*I, BackCase);
1622 // Create a CaseBlock record representing a conditional branch to
1623 // the Case's target mbb if the value being switched on SV is equal
1625 MachineBasicBlock *CurBlock = CR.CaseBB;
1626 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1627 MachineBasicBlock *FallThrough;
1629 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1630 CurMF->insert(BBI, FallThrough);
1632 // Put SV in a virtual register to make it available from the new blocks.
1633 ExportFromCurrentBlock(SV);
1635 // If the last case doesn't match, go to the default block.
1636 FallThrough = Default;
1639 Value *RHS, *LHS, *MHS;
1641 if (I->High == I->Low) {
1642 // This is just small small case range :) containing exactly 1 case
1644 LHS = SV; RHS = I->High; MHS = NULL;
1647 LHS = I->Low; MHS = SV; RHS = I->High;
1649 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1651 // If emitting the first comparison, just call visitSwitchCase to emit the
1652 // code into the current block. Otherwise, push the CaseBlock onto the
1653 // vector to be later processed by SDISel, and insert the node's MBB
1654 // before the next MBB.
1655 if (CurBlock == CurMBB)
1656 visitSwitchCase(CB);
1658 SwitchCases.push_back(CB);
1660 CurBlock = FallThrough;
1666 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1667 return !DisableJumpTables &&
1668 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1669 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1672 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1673 APInt LastExt(Last), FirstExt(First);
1674 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1675 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1676 return (LastExt - FirstExt + 1ULL);
1679 /// handleJTSwitchCase - Emit jumptable for current switch case range
1680 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1681 CaseRecVector& WorkList,
1683 MachineBasicBlock* Default) {
1684 Case& FrontCase = *CR.Range.first;
1685 Case& BackCase = *(CR.Range.second-1);
1687 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1688 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1691 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1695 if (!areJTsAllowed(TLI) || TSize <= 3)
1698 APInt Range = ComputeRange(First, Last);
1699 double Density = (double)TSize / Range.roundToDouble();
1703 DEBUG(errs() << "Lowering jump table\n"
1704 << "First entry: " << First << ". Last entry: " << Last << '\n'
1705 << "Range: " << Range
1706 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1708 // Get the MachineFunction which holds the current MBB. This is used when
1709 // inserting any additional MBBs necessary to represent the switch.
1710 MachineFunction *CurMF = CurMBB->getParent();
1712 // Figure out which block is immediately after the current one.
1713 MachineBasicBlock *NextBlock = 0;
1714 MachineFunction::iterator BBI = CR.CaseBB;
1716 if (++BBI != CurMBB->getParent()->end())
1719 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1721 // Create a new basic block to hold the code for loading the address
1722 // of the jump table, and jumping to it. Update successor information;
1723 // we will either branch to the default case for the switch, or the jump
1725 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1726 CurMF->insert(BBI, JumpTableBB);
1727 CR.CaseBB->addSuccessor(Default);
1728 CR.CaseBB->addSuccessor(JumpTableBB);
1730 // Build a vector of destination BBs, corresponding to each target
1731 // of the jump table. If the value of the jump table slot corresponds to
1732 // a case statement, push the case's BB onto the vector, otherwise, push
1734 std::vector<MachineBasicBlock*> DestBBs;
1736 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1737 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1738 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1740 if (Low.sle(TEI) && TEI.sle(High)) {
1741 DestBBs.push_back(I->BB);
1745 DestBBs.push_back(Default);
1749 // Update successor info. Add one edge to each unique successor.
1750 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1751 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1752 E = DestBBs.end(); I != E; ++I) {
1753 if (!SuccsHandled[(*I)->getNumber()]) {
1754 SuccsHandled[(*I)->getNumber()] = true;
1755 JumpTableBB->addSuccessor(*I);
1759 // Create a jump table index for this jump table, or return an existing
1761 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1763 // Set the jump table information so that we can codegen it as a second
1764 // MachineBasicBlock
1765 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1766 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1767 if (CR.CaseBB == CurMBB)
1768 visitJumpTableHeader(JT, JTH);
1770 JTCases.push_back(JumpTableBlock(JTH, JT));
1775 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1777 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1778 CaseRecVector& WorkList,
1780 MachineBasicBlock* Default) {
1781 // Get the MachineFunction which holds the current MBB. This is used when
1782 // inserting any additional MBBs necessary to represent the switch.
1783 MachineFunction *CurMF = CurMBB->getParent();
1785 // Figure out which block is immediately after the current one.
1786 MachineBasicBlock *NextBlock = 0;
1787 MachineFunction::iterator BBI = CR.CaseBB;
1789 if (++BBI != CurMBB->getParent()->end())
1792 Case& FrontCase = *CR.Range.first;
1793 Case& BackCase = *(CR.Range.second-1);
1794 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1796 // Size is the number of Cases represented by this range.
1797 unsigned Size = CR.Range.second - CR.Range.first;
1799 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1800 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1802 CaseItr Pivot = CR.Range.first + Size/2;
1804 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1805 // (heuristically) allow us to emit JumpTable's later.
1807 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1811 size_t LSize = FrontCase.size();
1812 size_t RSize = TSize-LSize;
1813 DEBUG(errs() << "Selecting best pivot: \n"
1814 << "First: " << First << ", Last: " << Last <<'\n'
1815 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1816 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1818 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1819 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1820 APInt Range = ComputeRange(LEnd, RBegin);
1821 assert((Range - 2ULL).isNonNegative() &&
1822 "Invalid case distance");
1823 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1824 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1825 double Metric = Range.logBase2()*(LDensity+RDensity);
1826 // Should always split in some non-trivial place
1827 DEBUG(errs() <<"=>Step\n"
1828 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1829 << "LDensity: " << LDensity
1830 << ", RDensity: " << RDensity << '\n'
1831 << "Metric: " << Metric << '\n');
1832 if (FMetric < Metric) {
1835 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1841 if (areJTsAllowed(TLI)) {
1842 // If our case is dense we *really* should handle it earlier!
1843 assert((FMetric > 0) && "Should handle dense range earlier!");
1845 Pivot = CR.Range.first + Size/2;
1848 CaseRange LHSR(CR.Range.first, Pivot);
1849 CaseRange RHSR(Pivot, CR.Range.second);
1850 Constant *C = Pivot->Low;
1851 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1853 // We know that we branch to the LHS if the Value being switched on is
1854 // less than the Pivot value, C. We use this to optimize our binary
1855 // tree a bit, by recognizing that if SV is greater than or equal to the
1856 // LHS's Case Value, and that Case Value is exactly one less than the
1857 // Pivot's Value, then we can branch directly to the LHS's Target,
1858 // rather than creating a leaf node for it.
1859 if ((LHSR.second - LHSR.first) == 1 &&
1860 LHSR.first->High == CR.GE &&
1861 cast<ConstantInt>(C)->getValue() ==
1862 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1863 TrueBB = LHSR.first->BB;
1865 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1866 CurMF->insert(BBI, TrueBB);
1867 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1869 // Put SV in a virtual register to make it available from the new blocks.
1870 ExportFromCurrentBlock(SV);
1873 // Similar to the optimization above, if the Value being switched on is
1874 // known to be less than the Constant CR.LT, and the current Case Value
1875 // is CR.LT - 1, then we can branch directly to the target block for
1876 // the current Case Value, rather than emitting a RHS leaf node for it.
1877 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1878 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1879 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1880 FalseBB = RHSR.first->BB;
1882 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1883 CurMF->insert(BBI, FalseBB);
1884 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1886 // Put SV in a virtual register to make it available from the new blocks.
1887 ExportFromCurrentBlock(SV);
1890 // Create a CaseBlock record representing a conditional branch to
1891 // the LHS node if the value being switched on SV is less than C.
1892 // Otherwise, branch to LHS.
1893 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1895 if (CR.CaseBB == CurMBB)
1896 visitSwitchCase(CB);
1898 SwitchCases.push_back(CB);
1903 /// handleBitTestsSwitchCase - if current case range has few destination and
1904 /// range span less, than machine word bitwidth, encode case range into series
1905 /// of masks and emit bit tests with these masks.
1906 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1907 CaseRecVector& WorkList,
1909 MachineBasicBlock* Default){
1910 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1912 Case& FrontCase = *CR.Range.first;
1913 Case& BackCase = *(CR.Range.second-1);
1915 // Get the MachineFunction which holds the current MBB. This is used when
1916 // inserting any additional MBBs necessary to represent the switch.
1917 MachineFunction *CurMF = CurMBB->getParent();
1919 // If target does not have legal shift left, do not emit bit tests at all.
1920 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1924 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1926 // Single case counts one, case range - two.
1927 numCmps += (I->Low == I->High ? 1 : 2);
1930 // Count unique destinations
1931 SmallSet<MachineBasicBlock*, 4> Dests;
1932 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1933 Dests.insert(I->BB);
1934 if (Dests.size() > 3)
1935 // Don't bother the code below, if there are too much unique destinations
1938 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1939 << "Total number of comparisons: " << numCmps << '\n');
1941 // Compute span of values.
1942 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1943 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1944 APInt cmpRange = maxValue - minValue;
1946 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1947 << "Low bound: " << minValue << '\n'
1948 << "High bound: " << maxValue << '\n');
1950 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1951 (!(Dests.size() == 1 && numCmps >= 3) &&
1952 !(Dests.size() == 2 && numCmps >= 5) &&
1953 !(Dests.size() >= 3 && numCmps >= 6)))
1956 DEBUG(errs() << "Emitting bit tests\n");
1957 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1959 // Optimize the case where all the case values fit in a
1960 // word without having to subtract minValue. In this case,
1961 // we can optimize away the subtraction.
1962 if (minValue.isNonNegative() &&
1963 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1964 cmpRange = maxValue;
1966 lowBound = minValue;
1969 CaseBitsVector CasesBits;
1970 unsigned i, count = 0;
1972 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1973 MachineBasicBlock* Dest = I->BB;
1974 for (i = 0; i < count; ++i)
1975 if (Dest == CasesBits[i].BB)
1979 assert((count < 3) && "Too much destinations to test!");
1980 CasesBits.push_back(CaseBits(0, Dest, 0));
1984 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1985 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1987 uint64_t lo = (lowValue - lowBound).getZExtValue();
1988 uint64_t hi = (highValue - lowBound).getZExtValue();
1990 for (uint64_t j = lo; j <= hi; j++) {
1991 CasesBits[i].Mask |= 1ULL << j;
1992 CasesBits[i].Bits++;
1996 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2000 // Figure out which block is immediately after the current one.
2001 MachineFunction::iterator BBI = CR.CaseBB;
2004 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2006 DEBUG(errs() << "Cases:\n");
2007 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2008 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2009 << ", Bits: " << CasesBits[i].Bits
2010 << ", BB: " << CasesBits[i].BB << '\n');
2012 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2013 CurMF->insert(BBI, CaseBB);
2014 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2018 // Put SV in a virtual register to make it available from the new blocks.
2019 ExportFromCurrentBlock(SV);
2022 BitTestBlock BTB(lowBound, cmpRange, SV,
2023 -1U, (CR.CaseBB == CurMBB),
2024 CR.CaseBB, Default, BTC);
2026 if (CR.CaseBB == CurMBB)
2027 visitBitTestHeader(BTB);
2029 BitTestCases.push_back(BTB);
2035 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2036 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2037 const SwitchInst& SI) {
2040 // Start with "simple" cases
2041 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2042 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2043 Cases.push_back(Case(SI.getSuccessorValue(i),
2044 SI.getSuccessorValue(i),
2047 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2049 // Merge case into clusters
2050 if (Cases.size() >= 2)
2051 // Must recompute end() each iteration because it may be
2052 // invalidated by erase if we hold on to it
2053 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2054 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2055 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2056 MachineBasicBlock* nextBB = J->BB;
2057 MachineBasicBlock* currentBB = I->BB;
2059 // If the two neighboring cases go to the same destination, merge them
2060 // into a single case.
2061 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2069 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2070 if (I->Low != I->High)
2071 // A range counts double, since it requires two compares.
2078 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2079 // Figure out which block is immediately after the current one.
2080 MachineBasicBlock *NextBlock = 0;
2081 MachineFunction::iterator BBI = CurMBB;
2083 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2085 // If there is only the default destination, branch to it if it is not the
2086 // next basic block. Otherwise, just fall through.
2087 if (SI.getNumOperands() == 2) {
2088 // Update machine-CFG edges.
2090 // If this is not a fall-through branch, emit the branch.
2091 CurMBB->addSuccessor(Default);
2092 if (Default != NextBlock)
2093 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2094 MVT::Other, getControlRoot(),
2095 DAG.getBasicBlock(Default)));
2099 // If there are any non-default case statements, create a vector of Cases
2100 // representing each one, and sort the vector so that we can efficiently
2101 // create a binary search tree from them.
2103 size_t numCmps = Clusterify(Cases, SI);
2104 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2105 << ". Total compares: " << numCmps << '\n');
2108 // Get the Value to be switched on and default basic blocks, which will be
2109 // inserted into CaseBlock records, representing basic blocks in the binary
2111 Value *SV = SI.getOperand(0);
2113 // Push the initial CaseRec onto the worklist
2114 CaseRecVector WorkList;
2115 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2117 while (!WorkList.empty()) {
2118 // Grab a record representing a case range to process off the worklist
2119 CaseRec CR = WorkList.back();
2120 WorkList.pop_back();
2122 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2125 // If the range has few cases (two or less) emit a series of specific
2127 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2130 // If the switch has more than 5 blocks, and at least 40% dense, and the
2131 // target supports indirect branches, then emit a jump table rather than
2132 // lowering the switch to a binary tree of conditional branches.
2133 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2136 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2137 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2138 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2143 void SelectionDAGLowering::visitFSub(User &I) {
2144 // -0.0 - X --> fneg
2145 const Type *Ty = I.getType();
2146 if (isa<VectorType>(Ty)) {
2147 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2148 const VectorType *DestTy = cast<VectorType>(I.getType());
2149 const Type *ElTy = DestTy->getElementType();
2150 unsigned VL = DestTy->getNumElements();
2151 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2152 Constant *CNZ = DAG.getContext()->getConstantVector(&NZ[0], NZ.size());
2154 SDValue Op2 = getValue(I.getOperand(1));
2155 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2156 Op2.getValueType(), Op2));
2161 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2162 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2163 SDValue Op2 = getValue(I.getOperand(1));
2164 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2165 Op2.getValueType(), Op2));
2169 visitBinary(I, ISD::FSUB);
2172 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2173 SDValue Op1 = getValue(I.getOperand(0));
2174 SDValue Op2 = getValue(I.getOperand(1));
2176 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2177 Op1.getValueType(), Op1, Op2));
2180 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2181 SDValue Op1 = getValue(I.getOperand(0));
2182 SDValue Op2 = getValue(I.getOperand(1));
2183 if (!isa<VectorType>(I.getType()) &&
2184 Op2.getValueType() != TLI.getShiftAmountTy()) {
2185 // If the operand is smaller than the shift count type, promote it.
2186 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2187 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2188 TLI.getShiftAmountTy(), Op2);
2189 // If the operand is larger than the shift count type but the shift
2190 // count type has enough bits to represent any shift value, truncate
2191 // it now. This is a common case and it exposes the truncate to
2192 // optimization early.
2193 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2194 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2195 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2196 TLI.getShiftAmountTy(), Op2);
2197 // Otherwise we'll need to temporarily settle for some other
2198 // convenient type; type legalization will make adjustments as
2200 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2201 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2202 TLI.getPointerTy(), Op2);
2203 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2204 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2205 TLI.getPointerTy(), Op2);
2208 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2209 Op1.getValueType(), Op1, Op2));
2212 void SelectionDAGLowering::visitICmp(User &I) {
2213 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2214 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2215 predicate = IC->getPredicate();
2216 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2217 predicate = ICmpInst::Predicate(IC->getPredicate());
2218 SDValue Op1 = getValue(I.getOperand(0));
2219 SDValue Op2 = getValue(I.getOperand(1));
2220 ISD::CondCode Opcode = getICmpCondCode(predicate);
2222 MVT DestVT = TLI.getValueType(I.getType());
2223 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2226 void SelectionDAGLowering::visitFCmp(User &I) {
2227 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2228 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2229 predicate = FC->getPredicate();
2230 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2231 predicate = FCmpInst::Predicate(FC->getPredicate());
2232 SDValue Op1 = getValue(I.getOperand(0));
2233 SDValue Op2 = getValue(I.getOperand(1));
2234 ISD::CondCode Condition = getFCmpCondCode(predicate);
2235 MVT DestVT = TLI.getValueType(I.getType());
2236 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2239 void SelectionDAGLowering::visitSelect(User &I) {
2240 SmallVector<MVT, 4> ValueVTs;
2241 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2242 unsigned NumValues = ValueVTs.size();
2243 if (NumValues != 0) {
2244 SmallVector<SDValue, 4> Values(NumValues);
2245 SDValue Cond = getValue(I.getOperand(0));
2246 SDValue TrueVal = getValue(I.getOperand(1));
2247 SDValue FalseVal = getValue(I.getOperand(2));
2249 for (unsigned i = 0; i != NumValues; ++i)
2250 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2251 TrueVal.getValueType(), Cond,
2252 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2253 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2255 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2256 DAG.getVTList(&ValueVTs[0], NumValues),
2257 &Values[0], NumValues));
2262 void SelectionDAGLowering::visitTrunc(User &I) {
2263 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2264 SDValue N = getValue(I.getOperand(0));
2265 MVT DestVT = TLI.getValueType(I.getType());
2266 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2269 void SelectionDAGLowering::visitZExt(User &I) {
2270 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2271 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2272 SDValue N = getValue(I.getOperand(0));
2273 MVT DestVT = TLI.getValueType(I.getType());
2274 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2277 void SelectionDAGLowering::visitSExt(User &I) {
2278 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2279 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2280 SDValue N = getValue(I.getOperand(0));
2281 MVT DestVT = TLI.getValueType(I.getType());
2282 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2285 void SelectionDAGLowering::visitFPTrunc(User &I) {
2286 // FPTrunc is never a no-op cast, no need to check
2287 SDValue N = getValue(I.getOperand(0));
2288 MVT DestVT = TLI.getValueType(I.getType());
2289 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2290 DestVT, N, DAG.getIntPtrConstant(0)));
2293 void SelectionDAGLowering::visitFPExt(User &I){
2294 // FPTrunc is never a no-op cast, no need to check
2295 SDValue N = getValue(I.getOperand(0));
2296 MVT DestVT = TLI.getValueType(I.getType());
2297 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2300 void SelectionDAGLowering::visitFPToUI(User &I) {
2301 // FPToUI is never a no-op cast, no need to check
2302 SDValue N = getValue(I.getOperand(0));
2303 MVT DestVT = TLI.getValueType(I.getType());
2304 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2307 void SelectionDAGLowering::visitFPToSI(User &I) {
2308 // FPToSI is never a no-op cast, no need to check
2309 SDValue N = getValue(I.getOperand(0));
2310 MVT DestVT = TLI.getValueType(I.getType());
2311 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2314 void SelectionDAGLowering::visitUIToFP(User &I) {
2315 // UIToFP is never a no-op cast, no need to check
2316 SDValue N = getValue(I.getOperand(0));
2317 MVT DestVT = TLI.getValueType(I.getType());
2318 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2321 void SelectionDAGLowering::visitSIToFP(User &I){
2322 // SIToFP is never a no-op cast, no need to check
2323 SDValue N = getValue(I.getOperand(0));
2324 MVT DestVT = TLI.getValueType(I.getType());
2325 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2328 void SelectionDAGLowering::visitPtrToInt(User &I) {
2329 // What to do depends on the size of the integer and the size of the pointer.
2330 // We can either truncate, zero extend, or no-op, accordingly.
2331 SDValue N = getValue(I.getOperand(0));
2332 MVT SrcVT = N.getValueType();
2333 MVT DestVT = TLI.getValueType(I.getType());
2335 if (DestVT.bitsLT(SrcVT))
2336 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2338 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2339 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2340 setValue(&I, Result);
2343 void SelectionDAGLowering::visitIntToPtr(User &I) {
2344 // What to do depends on the size of the integer and the size of the pointer.
2345 // We can either truncate, zero extend, or no-op, accordingly.
2346 SDValue N = getValue(I.getOperand(0));
2347 MVT SrcVT = N.getValueType();
2348 MVT DestVT = TLI.getValueType(I.getType());
2349 if (DestVT.bitsLT(SrcVT))
2350 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2352 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2353 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2357 void SelectionDAGLowering::visitBitCast(User &I) {
2358 SDValue N = getValue(I.getOperand(0));
2359 MVT DestVT = TLI.getValueType(I.getType());
2361 // BitCast assures us that source and destination are the same size so this
2362 // is either a BIT_CONVERT or a no-op.
2363 if (DestVT != N.getValueType())
2364 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2365 DestVT, N)); // convert types
2367 setValue(&I, N); // noop cast.
2370 void SelectionDAGLowering::visitInsertElement(User &I) {
2371 SDValue InVec = getValue(I.getOperand(0));
2372 SDValue InVal = getValue(I.getOperand(1));
2373 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2375 getValue(I.getOperand(2)));
2377 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2378 TLI.getValueType(I.getType()),
2379 InVec, InVal, InIdx));
2382 void SelectionDAGLowering::visitExtractElement(User &I) {
2383 SDValue InVec = getValue(I.getOperand(0));
2384 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2386 getValue(I.getOperand(1)));
2387 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2388 TLI.getValueType(I.getType()), InVec, InIdx));
2392 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2393 // from SIndx and increasing to the element length (undefs are allowed).
2394 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2395 unsigned MaskNumElts = Mask.size();
2396 for (unsigned i = 0; i != MaskNumElts; ++i)
2397 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2402 void SelectionDAGLowering::visitShuffleVector(User &I) {
2403 SmallVector<int, 8> Mask;
2404 SDValue Src1 = getValue(I.getOperand(0));
2405 SDValue Src2 = getValue(I.getOperand(1));
2407 // Convert the ConstantVector mask operand into an array of ints, with -1
2408 // representing undef values.
2409 SmallVector<Constant*, 8> MaskElts;
2410 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2412 unsigned MaskNumElts = MaskElts.size();
2413 for (unsigned i = 0; i != MaskNumElts; ++i) {
2414 if (isa<UndefValue>(MaskElts[i]))
2417 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2420 MVT VT = TLI.getValueType(I.getType());
2421 MVT SrcVT = Src1.getValueType();
2422 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2424 if (SrcNumElts == MaskNumElts) {
2425 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2430 // Normalize the shuffle vector since mask and vector length don't match.
2431 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2432 // Mask is longer than the source vectors and is a multiple of the source
2433 // vectors. We can use concatenate vector to make the mask and vectors
2435 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2436 // The shuffle is concatenating two vectors together.
2437 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2442 // Pad both vectors with undefs to make them the same length as the mask.
2443 unsigned NumConcat = MaskNumElts / SrcNumElts;
2444 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2445 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2446 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2448 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2449 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2453 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2454 getCurDebugLoc(), VT,
2455 &MOps1[0], NumConcat);
2456 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2457 getCurDebugLoc(), VT,
2458 &MOps2[0], NumConcat);
2460 // Readjust mask for new input vector length.
2461 SmallVector<int, 8> MappedOps;
2462 for (unsigned i = 0; i != MaskNumElts; ++i) {
2464 if (Idx < (int)SrcNumElts)
2465 MappedOps.push_back(Idx);
2467 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2469 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2474 if (SrcNumElts > MaskNumElts) {
2475 // Analyze the access pattern of the vector to see if we can extract
2476 // two subvectors and do the shuffle. The analysis is done by calculating
2477 // the range of elements the mask access on both vectors.
2478 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2479 int MaxRange[2] = {-1, -1};
2481 for (unsigned i = 0; i != MaskNumElts; ++i) {
2487 if (Idx >= (int)SrcNumElts) {
2491 if (Idx > MaxRange[Input])
2492 MaxRange[Input] = Idx;
2493 if (Idx < MinRange[Input])
2494 MinRange[Input] = Idx;
2497 // Check if the access is smaller than the vector size and can we find
2498 // a reasonable extract index.
2499 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2500 int StartIdx[2]; // StartIdx to extract from
2501 for (int Input=0; Input < 2; ++Input) {
2502 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2503 RangeUse[Input] = 0; // Unused
2504 StartIdx[Input] = 0;
2505 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2506 // Fits within range but we should see if we can find a good
2507 // start index that is a multiple of the mask length.
2508 if (MaxRange[Input] < (int)MaskNumElts) {
2509 RangeUse[Input] = 1; // Extract from beginning of the vector
2510 StartIdx[Input] = 0;
2512 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2513 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2514 StartIdx[Input] + MaskNumElts < SrcNumElts)
2515 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2520 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2521 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2524 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2525 // Extract appropriate subvector and generate a vector shuffle
2526 for (int Input=0; Input < 2; ++Input) {
2527 SDValue& Src = Input == 0 ? Src1 : Src2;
2528 if (RangeUse[Input] == 0) {
2529 Src = DAG.getUNDEF(VT);
2531 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2532 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2535 // Calculate new mask.
2536 SmallVector<int, 8> MappedOps;
2537 for (unsigned i = 0; i != MaskNumElts; ++i) {
2540 MappedOps.push_back(Idx);
2541 else if (Idx < (int)SrcNumElts)
2542 MappedOps.push_back(Idx - StartIdx[0]);
2544 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2546 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2552 // We can't use either concat vectors or extract subvectors so fall back to
2553 // replacing the shuffle with extract and build vector.
2554 // to insert and build vector.
2555 MVT EltVT = VT.getVectorElementType();
2556 MVT PtrVT = TLI.getPointerTy();
2557 SmallVector<SDValue,8> Ops;
2558 for (unsigned i = 0; i != MaskNumElts; ++i) {
2560 Ops.push_back(DAG.getUNDEF(EltVT));
2563 if (Idx < (int)SrcNumElts)
2564 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2565 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2567 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2569 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2572 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2573 VT, &Ops[0], Ops.size()));
2576 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2577 const Value *Op0 = I.getOperand(0);
2578 const Value *Op1 = I.getOperand(1);
2579 const Type *AggTy = I.getType();
2580 const Type *ValTy = Op1->getType();
2581 bool IntoUndef = isa<UndefValue>(Op0);
2582 bool FromUndef = isa<UndefValue>(Op1);
2584 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2585 I.idx_begin(), I.idx_end());
2587 SmallVector<MVT, 4> AggValueVTs;
2588 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2589 SmallVector<MVT, 4> ValValueVTs;
2590 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2592 unsigned NumAggValues = AggValueVTs.size();
2593 unsigned NumValValues = ValValueVTs.size();
2594 SmallVector<SDValue, 4> Values(NumAggValues);
2596 SDValue Agg = getValue(Op0);
2597 SDValue Val = getValue(Op1);
2599 // Copy the beginning value(s) from the original aggregate.
2600 for (; i != LinearIndex; ++i)
2601 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2602 SDValue(Agg.getNode(), Agg.getResNo() + i);
2603 // Copy values from the inserted value(s).
2604 for (; i != LinearIndex + NumValValues; ++i)
2605 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2606 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2607 // Copy remaining value(s) from the original aggregate.
2608 for (; i != NumAggValues; ++i)
2609 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2610 SDValue(Agg.getNode(), Agg.getResNo() + i);
2612 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2613 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2614 &Values[0], NumAggValues));
2617 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2618 const Value *Op0 = I.getOperand(0);
2619 const Type *AggTy = Op0->getType();
2620 const Type *ValTy = I.getType();
2621 bool OutOfUndef = isa<UndefValue>(Op0);
2623 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2624 I.idx_begin(), I.idx_end());
2626 SmallVector<MVT, 4> ValValueVTs;
2627 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2629 unsigned NumValValues = ValValueVTs.size();
2630 SmallVector<SDValue, 4> Values(NumValValues);
2632 SDValue Agg = getValue(Op0);
2633 // Copy out the selected value(s).
2634 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2635 Values[i - LinearIndex] =
2637 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2638 SDValue(Agg.getNode(), Agg.getResNo() + i);
2640 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2641 DAG.getVTList(&ValValueVTs[0], NumValValues),
2642 &Values[0], NumValValues));
2646 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2647 SDValue N = getValue(I.getOperand(0));
2648 const Type *Ty = I.getOperand(0)->getType();
2650 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2653 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2654 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2657 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2658 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2659 DAG.getIntPtrConstant(Offset));
2661 Ty = StTy->getElementType(Field);
2663 Ty = cast<SequentialType>(Ty)->getElementType();
2665 // If this is a constant subscript, handle it quickly.
2666 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2667 if (CI->getZExtValue() == 0) continue;
2669 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2671 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2673 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2675 DAG.getConstant(Offs, MVT::i64));
2677 OffsVal = DAG.getIntPtrConstant(Offs);
2678 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2683 // N = N + Idx * ElementSize;
2684 uint64_t ElementSize = TD->getTypeAllocSize(Ty);
2685 SDValue IdxN = getValue(Idx);
2687 // If the index is smaller or larger than intptr_t, truncate or extend
2689 if (IdxN.getValueType().bitsLT(N.getValueType()))
2690 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2691 N.getValueType(), IdxN);
2692 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2693 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2694 N.getValueType(), IdxN);
2696 // If this is a multiply by a power of two, turn it into a shl
2697 // immediately. This is a very common case.
2698 if (ElementSize != 1) {
2699 if (isPowerOf2_64(ElementSize)) {
2700 unsigned Amt = Log2_64(ElementSize);
2701 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2702 N.getValueType(), IdxN,
2703 DAG.getConstant(Amt, TLI.getPointerTy()));
2705 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2706 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2707 N.getValueType(), IdxN, Scale);
2711 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2712 N.getValueType(), N, IdxN);
2718 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2719 // If this is a fixed sized alloca in the entry block of the function,
2720 // allocate it statically on the stack.
2721 if (FuncInfo.StaticAllocaMap.count(&I))
2722 return; // getValue will auto-populate this.
2724 const Type *Ty = I.getAllocatedType();
2725 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2727 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2730 SDValue AllocSize = getValue(I.getArraySize());
2732 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2734 DAG.getConstant(TySize, AllocSize.getValueType()));
2738 MVT IntPtr = TLI.getPointerTy();
2739 if (IntPtr.bitsLT(AllocSize.getValueType()))
2740 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2742 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2743 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2746 // Handle alignment. If the requested alignment is less than or equal to
2747 // the stack alignment, ignore it. If the size is greater than or equal to
2748 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2749 unsigned StackAlign =
2750 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2751 if (Align <= StackAlign)
2754 // Round the size of the allocation up to the stack alignment size
2755 // by add SA-1 to the size.
2756 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2757 AllocSize.getValueType(), AllocSize,
2758 DAG.getIntPtrConstant(StackAlign-1));
2759 // Mask out the low bits for alignment purposes.
2760 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2761 AllocSize.getValueType(), AllocSize,
2762 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2764 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2765 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2766 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2769 DAG.setRoot(DSA.getValue(1));
2771 // Inform the Frame Information that we have just allocated a variable-sized
2773 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2776 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2777 const Value *SV = I.getOperand(0);
2778 SDValue Ptr = getValue(SV);
2780 const Type *Ty = I.getType();
2781 bool isVolatile = I.isVolatile();
2782 unsigned Alignment = I.getAlignment();
2784 SmallVector<MVT, 4> ValueVTs;
2785 SmallVector<uint64_t, 4> Offsets;
2786 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2787 unsigned NumValues = ValueVTs.size();
2792 bool ConstantMemory = false;
2794 // Serialize volatile loads with other side effects.
2796 else if (AA->pointsToConstantMemory(SV)) {
2797 // Do not serialize (non-volatile) loads of constant memory with anything.
2798 Root = DAG.getEntryNode();
2799 ConstantMemory = true;
2801 // Do not serialize non-volatile loads against each other.
2802 Root = DAG.getRoot();
2805 SmallVector<SDValue, 4> Values(NumValues);
2806 SmallVector<SDValue, 4> Chains(NumValues);
2807 MVT PtrVT = Ptr.getValueType();
2808 for (unsigned i = 0; i != NumValues; ++i) {
2809 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2810 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2812 DAG.getConstant(Offsets[i], PtrVT)),
2814 isVolatile, Alignment);
2816 Chains[i] = L.getValue(1);
2819 if (!ConstantMemory) {
2820 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2822 &Chains[0], NumValues);
2826 PendingLoads.push_back(Chain);
2829 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2830 DAG.getVTList(&ValueVTs[0], NumValues),
2831 &Values[0], NumValues));
2835 void SelectionDAGLowering::visitStore(StoreInst &I) {
2836 Value *SrcV = I.getOperand(0);
2837 Value *PtrV = I.getOperand(1);
2839 SmallVector<MVT, 4> ValueVTs;
2840 SmallVector<uint64_t, 4> Offsets;
2841 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2842 unsigned NumValues = ValueVTs.size();
2846 // Get the lowered operands. Note that we do this after
2847 // checking if NumResults is zero, because with zero results
2848 // the operands won't have values in the map.
2849 SDValue Src = getValue(SrcV);
2850 SDValue Ptr = getValue(PtrV);
2852 SDValue Root = getRoot();
2853 SmallVector<SDValue, 4> Chains(NumValues);
2854 MVT PtrVT = Ptr.getValueType();
2855 bool isVolatile = I.isVolatile();
2856 unsigned Alignment = I.getAlignment();
2857 for (unsigned i = 0; i != NumValues; ++i)
2858 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2859 SDValue(Src.getNode(), Src.getResNo() + i),
2860 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2862 DAG.getConstant(Offsets[i], PtrVT)),
2864 isVolatile, Alignment);
2866 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2867 MVT::Other, &Chains[0], NumValues));
2870 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2872 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2873 unsigned Intrinsic) {
2874 bool HasChain = !I.doesNotAccessMemory();
2875 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2877 // Build the operand list.
2878 SmallVector<SDValue, 8> Ops;
2879 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2881 // We don't need to serialize loads against other loads.
2882 Ops.push_back(DAG.getRoot());
2884 Ops.push_back(getRoot());
2888 // Info is set by getTgtMemInstrinsic
2889 TargetLowering::IntrinsicInfo Info;
2890 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2892 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2893 if (!IsTgtIntrinsic)
2894 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2896 // Add all operands of the call to the operand list.
2897 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2898 SDValue Op = getValue(I.getOperand(i));
2899 assert(TLI.isTypeLegal(Op.getValueType()) &&
2900 "Intrinsic uses a non-legal type?");
2904 std::vector<MVT> VTArray;
2905 if (I.getType() != Type::VoidTy) {
2906 MVT VT = TLI.getValueType(I.getType());
2907 if (VT.isVector()) {
2908 const VectorType *DestTy = cast<VectorType>(I.getType());
2909 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2911 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2912 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2915 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2916 VTArray.push_back(VT);
2919 VTArray.push_back(MVT::Other);
2921 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2925 if (IsTgtIntrinsic) {
2926 // This is target intrinsic that touches memory
2927 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2928 VTs, &Ops[0], Ops.size(),
2929 Info.memVT, Info.ptrVal, Info.offset,
2930 Info.align, Info.vol,
2931 Info.readMem, Info.writeMem);
2934 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2935 VTs, &Ops[0], Ops.size());
2936 else if (I.getType() != Type::VoidTy)
2937 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2938 VTs, &Ops[0], Ops.size());
2940 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2941 VTs, &Ops[0], Ops.size());
2944 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2946 PendingLoads.push_back(Chain);
2950 if (I.getType() != Type::VoidTy) {
2951 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2952 MVT VT = TLI.getValueType(PTy);
2953 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2955 setValue(&I, Result);
2959 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2960 static GlobalVariable *ExtractTypeInfo(Value *V) {
2961 V = V->stripPointerCasts();
2962 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2963 assert ((GV || isa<ConstantPointerNull>(V)) &&
2964 "TypeInfo must be a global variable or NULL");
2970 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2971 /// call, and add them to the specified machine basic block.
2972 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2973 MachineBasicBlock *MBB) {
2974 // Inform the MachineModuleInfo of the personality for this landing pad.
2975 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2976 assert(CE->getOpcode() == Instruction::BitCast &&
2977 isa<Function>(CE->getOperand(0)) &&
2978 "Personality should be a function");
2979 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2981 // Gather all the type infos for this landing pad and pass them along to
2982 // MachineModuleInfo.
2983 std::vector<GlobalVariable *> TyInfo;
2984 unsigned N = I.getNumOperands();
2986 for (unsigned i = N - 1; i > 2; --i) {
2987 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2988 unsigned FilterLength = CI->getZExtValue();
2989 unsigned FirstCatch = i + FilterLength + !FilterLength;
2990 assert (FirstCatch <= N && "Invalid filter length");
2992 if (FirstCatch < N) {
2993 TyInfo.reserve(N - FirstCatch);
2994 for (unsigned j = FirstCatch; j < N; ++j)
2995 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2996 MMI->addCatchTypeInfo(MBB, TyInfo);
3000 if (!FilterLength) {
3002 MMI->addCleanup(MBB);
3005 TyInfo.reserve(FilterLength - 1);
3006 for (unsigned j = i + 1; j < FirstCatch; ++j)
3007 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3008 MMI->addFilterTypeInfo(MBB, TyInfo);
3017 TyInfo.reserve(N - 3);
3018 for (unsigned j = 3; j < N; ++j)
3019 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3020 MMI->addCatchTypeInfo(MBB, TyInfo);
3026 /// GetSignificand - Get the significand and build it into a floating-point
3027 /// number with exponent of 1:
3029 /// Op = (Op & 0x007fffff) | 0x3f800000;
3031 /// where Op is the hexidecimal representation of floating point value.
3033 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3034 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3035 DAG.getConstant(0x007fffff, MVT::i32));
3036 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3037 DAG.getConstant(0x3f800000, MVT::i32));
3038 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3041 /// GetExponent - Get the exponent:
3043 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3045 /// where Op is the hexidecimal representation of floating point value.
3047 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3049 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3050 DAG.getConstant(0x7f800000, MVT::i32));
3051 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3052 DAG.getConstant(23, TLI.getPointerTy()));
3053 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3054 DAG.getConstant(127, MVT::i32));
3055 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3058 /// getF32Constant - Get 32-bit floating point constant.
3060 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3061 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3064 /// Inlined utility function to implement binary input atomic intrinsics for
3065 /// visitIntrinsicCall: I is a call instruction
3066 /// Op is the associated NodeType for I
3068 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3069 SDValue Root = getRoot();
3071 DAG.getAtomic(Op, getCurDebugLoc(),
3072 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3074 getValue(I.getOperand(1)),
3075 getValue(I.getOperand(2)),
3078 DAG.setRoot(L.getValue(1));
3082 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3084 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3085 SDValue Op1 = getValue(I.getOperand(1));
3086 SDValue Op2 = getValue(I.getOperand(2));
3088 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3089 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3091 setValue(&I, Result);
3095 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3096 /// limited-precision mode.
3098 SelectionDAGLowering::visitExp(CallInst &I) {
3100 DebugLoc dl = getCurDebugLoc();
3102 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3103 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3104 SDValue Op = getValue(I.getOperand(1));
3106 // Put the exponent in the right bit position for later addition to the
3109 // #define LOG2OFe 1.4426950f
3110 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3111 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3112 getF32Constant(DAG, 0x3fb8aa3b));
3113 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3115 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3116 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3117 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3119 // IntegerPartOfX <<= 23;
3120 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3121 DAG.getConstant(23, TLI.getPointerTy()));
3123 if (LimitFloatPrecision <= 6) {
3124 // For floating-point precision of 6:
3126 // TwoToFractionalPartOfX =
3128 // (0.735607626f + 0.252464424f * x) * x;
3130 // error 0.0144103317, which is 6 bits
3131 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3132 getF32Constant(DAG, 0x3e814304));
3133 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3134 getF32Constant(DAG, 0x3f3c50c8));
3135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3136 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3137 getF32Constant(DAG, 0x3f7f5e7e));
3138 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3140 // Add the exponent into the result in integer domain.
3141 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3142 TwoToFracPartOfX, IntegerPartOfX);
3144 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3145 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3146 // For floating-point precision of 12:
3148 // TwoToFractionalPartOfX =
3151 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3153 // 0.000107046256 error, which is 13 to 14 bits
3154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3155 getF32Constant(DAG, 0x3da235e3));
3156 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3157 getF32Constant(DAG, 0x3e65b8f3));
3158 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3159 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3160 getF32Constant(DAG, 0x3f324b07));
3161 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3162 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3163 getF32Constant(DAG, 0x3f7ff8fd));
3164 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3166 // Add the exponent into the result in integer domain.
3167 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3168 TwoToFracPartOfX, IntegerPartOfX);
3170 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3171 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3172 // For floating-point precision of 18:
3174 // TwoToFractionalPartOfX =
3178 // (0.554906021e-1f +
3179 // (0.961591928e-2f +
3180 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3182 // error 2.47208000*10^(-7), which is better than 18 bits
3183 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3184 getF32Constant(DAG, 0x3924b03e));
3185 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3186 getF32Constant(DAG, 0x3ab24b87));
3187 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3188 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3189 getF32Constant(DAG, 0x3c1d8c17));
3190 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3191 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3192 getF32Constant(DAG, 0x3d634a1d));
3193 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3194 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3195 getF32Constant(DAG, 0x3e75fe14));
3196 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3197 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3198 getF32Constant(DAG, 0x3f317234));
3199 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3200 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3201 getF32Constant(DAG, 0x3f800000));
3202 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3205 // Add the exponent into the result in integer domain.
3206 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3207 TwoToFracPartOfX, IntegerPartOfX);
3209 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3212 // No special expansion.
3213 result = DAG.getNode(ISD::FEXP, dl,
3214 getValue(I.getOperand(1)).getValueType(),
3215 getValue(I.getOperand(1)));
3218 setValue(&I, result);
3221 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3222 /// limited-precision mode.
3224 SelectionDAGLowering::visitLog(CallInst &I) {
3226 DebugLoc dl = getCurDebugLoc();
3228 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3229 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3230 SDValue Op = getValue(I.getOperand(1));
3231 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3233 // Scale the exponent by log(2) [0.69314718f].
3234 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3235 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3236 getF32Constant(DAG, 0x3f317218));
3238 // Get the significand and build it into a floating-point number with
3240 SDValue X = GetSignificand(DAG, Op1, dl);
3242 if (LimitFloatPrecision <= 6) {
3243 // For floating-point precision of 6:
3247 // (1.4034025f - 0.23903021f * x) * x;
3249 // error 0.0034276066, which is better than 8 bits
3250 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3251 getF32Constant(DAG, 0xbe74c456));
3252 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3253 getF32Constant(DAG, 0x3fb3a2b1));
3254 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3255 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3256 getF32Constant(DAG, 0x3f949a29));
3258 result = DAG.getNode(ISD::FADD, dl,
3259 MVT::f32, LogOfExponent, LogOfMantissa);
3260 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3261 // For floating-point precision of 12:
3267 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3269 // error 0.000061011436, which is 14 bits
3270 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3271 getF32Constant(DAG, 0xbd67b6d6));
3272 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3273 getF32Constant(DAG, 0x3ee4f4b8));
3274 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3275 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3276 getF32Constant(DAG, 0x3fbc278b));
3277 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3278 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3279 getF32Constant(DAG, 0x40348e95));
3280 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3281 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3282 getF32Constant(DAG, 0x3fdef31a));
3284 result = DAG.getNode(ISD::FADD, dl,
3285 MVT::f32, LogOfExponent, LogOfMantissa);
3286 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3287 // For floating-point precision of 18:
3295 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3297 // error 0.0000023660568, which is better than 18 bits
3298 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3299 getF32Constant(DAG, 0xbc91e5ac));
3300 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3301 getF32Constant(DAG, 0x3e4350aa));
3302 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3303 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3304 getF32Constant(DAG, 0x3f60d3e3));
3305 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3306 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3307 getF32Constant(DAG, 0x4011cdf0));
3308 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3309 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3310 getF32Constant(DAG, 0x406cfd1c));
3311 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3312 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3313 getF32Constant(DAG, 0x408797cb));
3314 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3315 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3316 getF32Constant(DAG, 0x4006dcab));
3318 result = DAG.getNode(ISD::FADD, dl,
3319 MVT::f32, LogOfExponent, LogOfMantissa);
3322 // No special expansion.
3323 result = DAG.getNode(ISD::FLOG, dl,
3324 getValue(I.getOperand(1)).getValueType(),
3325 getValue(I.getOperand(1)));
3328 setValue(&I, result);
3331 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3332 /// limited-precision mode.
3334 SelectionDAGLowering::visitLog2(CallInst &I) {
3336 DebugLoc dl = getCurDebugLoc();
3338 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3339 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3340 SDValue Op = getValue(I.getOperand(1));
3341 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3343 // Get the exponent.
3344 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3346 // Get the significand and build it into a floating-point number with
3348 SDValue X = GetSignificand(DAG, Op1, dl);
3350 // Different possible minimax approximations of significand in
3351 // floating-point for various degrees of accuracy over [1,2].
3352 if (LimitFloatPrecision <= 6) {
3353 // For floating-point precision of 6:
3355 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3357 // error 0.0049451742, which is more than 7 bits
3358 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3359 getF32Constant(DAG, 0xbeb08fe0));
3360 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3361 getF32Constant(DAG, 0x40019463));
3362 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3363 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3364 getF32Constant(DAG, 0x3fd6633d));
3366 result = DAG.getNode(ISD::FADD, dl,
3367 MVT::f32, LogOfExponent, Log2ofMantissa);
3368 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3369 // For floating-point precision of 12:
3375 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3377 // error 0.0000876136000, which is better than 13 bits
3378 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3379 getF32Constant(DAG, 0xbda7262e));
3380 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3381 getF32Constant(DAG, 0x3f25280b));
3382 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3383 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3384 getF32Constant(DAG, 0x4007b923));
3385 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3386 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3387 getF32Constant(DAG, 0x40823e2f));
3388 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3389 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3390 getF32Constant(DAG, 0x4020d29c));
3392 result = DAG.getNode(ISD::FADD, dl,
3393 MVT::f32, LogOfExponent, Log2ofMantissa);
3394 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3395 // For floating-point precision of 18:
3404 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3406 // error 0.0000018516, which is better than 18 bits
3407 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3408 getF32Constant(DAG, 0xbcd2769e));
3409 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3410 getF32Constant(DAG, 0x3e8ce0b9));
3411 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3412 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3413 getF32Constant(DAG, 0x3fa22ae7));
3414 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3415 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3416 getF32Constant(DAG, 0x40525723));
3417 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3418 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3419 getF32Constant(DAG, 0x40aaf200));
3420 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3421 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3422 getF32Constant(DAG, 0x40c39dad));
3423 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3424 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3425 getF32Constant(DAG, 0x4042902c));
3427 result = DAG.getNode(ISD::FADD, dl,
3428 MVT::f32, LogOfExponent, Log2ofMantissa);
3431 // No special expansion.
3432 result = DAG.getNode(ISD::FLOG2, dl,
3433 getValue(I.getOperand(1)).getValueType(),
3434 getValue(I.getOperand(1)));
3437 setValue(&I, result);
3440 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3441 /// limited-precision mode.
3443 SelectionDAGLowering::visitLog10(CallInst &I) {
3445 DebugLoc dl = getCurDebugLoc();
3447 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3448 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3449 SDValue Op = getValue(I.getOperand(1));
3450 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3452 // Scale the exponent by log10(2) [0.30102999f].
3453 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3454 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3455 getF32Constant(DAG, 0x3e9a209a));
3457 // Get the significand and build it into a floating-point number with
3459 SDValue X = GetSignificand(DAG, Op1, dl);
3461 if (LimitFloatPrecision <= 6) {
3462 // For floating-point precision of 6:
3464 // Log10ofMantissa =
3466 // (0.60948995f - 0.10380950f * x) * x;
3468 // error 0.0014886165, which is 6 bits
3469 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3470 getF32Constant(DAG, 0xbdd49a13));
3471 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3472 getF32Constant(DAG, 0x3f1c0789));
3473 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3474 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3475 getF32Constant(DAG, 0x3f011300));
3477 result = DAG.getNode(ISD::FADD, dl,
3478 MVT::f32, LogOfExponent, Log10ofMantissa);
3479 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3480 // For floating-point precision of 12:
3482 // Log10ofMantissa =
3485 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3487 // error 0.00019228036, which is better than 12 bits
3488 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3489 getF32Constant(DAG, 0x3d431f31));
3490 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3491 getF32Constant(DAG, 0x3ea21fb2));
3492 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3493 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3494 getF32Constant(DAG, 0x3f6ae232));
3495 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3496 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3497 getF32Constant(DAG, 0x3f25f7c3));
3499 result = DAG.getNode(ISD::FADD, dl,
3500 MVT::f32, LogOfExponent, Log10ofMantissa);
3501 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3502 // For floating-point precision of 18:
3504 // Log10ofMantissa =
3509 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3511 // error 0.0000037995730, which is better than 18 bits
3512 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3513 getF32Constant(DAG, 0x3c5d51ce));
3514 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3515 getF32Constant(DAG, 0x3e00685a));
3516 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3517 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3518 getF32Constant(DAG, 0x3efb6798));
3519 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3520 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3521 getF32Constant(DAG, 0x3f88d192));
3522 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3523 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3524 getF32Constant(DAG, 0x3fc4316c));
3525 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3526 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3527 getF32Constant(DAG, 0x3f57ce70));
3529 result = DAG.getNode(ISD::FADD, dl,
3530 MVT::f32, LogOfExponent, Log10ofMantissa);
3533 // No special expansion.
3534 result = DAG.getNode(ISD::FLOG10, dl,
3535 getValue(I.getOperand(1)).getValueType(),
3536 getValue(I.getOperand(1)));
3539 setValue(&I, result);
3542 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3543 /// limited-precision mode.
3545 SelectionDAGLowering::visitExp2(CallInst &I) {
3547 DebugLoc dl = getCurDebugLoc();
3549 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3550 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3551 SDValue Op = getValue(I.getOperand(1));
3553 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3555 // FractionalPartOfX = x - (float)IntegerPartOfX;
3556 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3557 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3559 // IntegerPartOfX <<= 23;
3560 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3561 DAG.getConstant(23, TLI.getPointerTy()));
3563 if (LimitFloatPrecision <= 6) {
3564 // For floating-point precision of 6:
3566 // TwoToFractionalPartOfX =
3568 // (0.735607626f + 0.252464424f * x) * x;
3570 // error 0.0144103317, which is 6 bits
3571 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3572 getF32Constant(DAG, 0x3e814304));
3573 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3574 getF32Constant(DAG, 0x3f3c50c8));
3575 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3576 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3577 getF32Constant(DAG, 0x3f7f5e7e));
3578 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3579 SDValue TwoToFractionalPartOfX =
3580 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3582 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3583 MVT::f32, TwoToFractionalPartOfX);
3584 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3585 // For floating-point precision of 12:
3587 // TwoToFractionalPartOfX =
3590 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3592 // error 0.000107046256, which is 13 to 14 bits
3593 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3594 getF32Constant(DAG, 0x3da235e3));
3595 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3596 getF32Constant(DAG, 0x3e65b8f3));
3597 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3598 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3599 getF32Constant(DAG, 0x3f324b07));
3600 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3601 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3602 getF32Constant(DAG, 0x3f7ff8fd));
3603 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3604 SDValue TwoToFractionalPartOfX =
3605 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3607 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3608 MVT::f32, TwoToFractionalPartOfX);
3609 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3610 // For floating-point precision of 18:
3612 // TwoToFractionalPartOfX =
3616 // (0.554906021e-1f +
3617 // (0.961591928e-2f +
3618 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3619 // error 2.47208000*10^(-7), which is better than 18 bits
3620 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3621 getF32Constant(DAG, 0x3924b03e));
3622 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3623 getF32Constant(DAG, 0x3ab24b87));
3624 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3625 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3626 getF32Constant(DAG, 0x3c1d8c17));
3627 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3628 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3629 getF32Constant(DAG, 0x3d634a1d));
3630 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3631 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3632 getF32Constant(DAG, 0x3e75fe14));
3633 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3634 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3635 getF32Constant(DAG, 0x3f317234));
3636 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3637 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3638 getF32Constant(DAG, 0x3f800000));
3639 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3640 SDValue TwoToFractionalPartOfX =
3641 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3643 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3644 MVT::f32, TwoToFractionalPartOfX);
3647 // No special expansion.
3648 result = DAG.getNode(ISD::FEXP2, dl,
3649 getValue(I.getOperand(1)).getValueType(),
3650 getValue(I.getOperand(1)));
3653 setValue(&I, result);
3656 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3657 /// limited-precision mode with x == 10.0f.
3659 SelectionDAGLowering::visitPow(CallInst &I) {
3661 Value *Val = I.getOperand(1);
3662 DebugLoc dl = getCurDebugLoc();
3663 bool IsExp10 = false;
3665 if (getValue(Val).getValueType() == MVT::f32 &&
3666 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3667 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3668 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3669 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3671 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3676 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3677 SDValue Op = getValue(I.getOperand(2));
3679 // Put the exponent in the right bit position for later addition to the
3682 // #define LOG2OF10 3.3219281f
3683 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3684 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3685 getF32Constant(DAG, 0x40549a78));
3686 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3688 // FractionalPartOfX = x - (float)IntegerPartOfX;
3689 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3690 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3692 // IntegerPartOfX <<= 23;
3693 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3694 DAG.getConstant(23, TLI.getPointerTy()));
3696 if (LimitFloatPrecision <= 6) {
3697 // For floating-point precision of 6:
3699 // twoToFractionalPartOfX =
3701 // (0.735607626f + 0.252464424f * x) * x;
3703 // error 0.0144103317, which is 6 bits
3704 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3705 getF32Constant(DAG, 0x3e814304));
3706 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3707 getF32Constant(DAG, 0x3f3c50c8));
3708 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3709 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3710 getF32Constant(DAG, 0x3f7f5e7e));
3711 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3712 SDValue TwoToFractionalPartOfX =
3713 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3715 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3716 MVT::f32, TwoToFractionalPartOfX);
3717 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3718 // For floating-point precision of 12:
3720 // TwoToFractionalPartOfX =
3723 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3725 // error 0.000107046256, which is 13 to 14 bits
3726 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3727 getF32Constant(DAG, 0x3da235e3));
3728 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3729 getF32Constant(DAG, 0x3e65b8f3));
3730 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3731 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3732 getF32Constant(DAG, 0x3f324b07));
3733 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3734 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3735 getF32Constant(DAG, 0x3f7ff8fd));
3736 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3737 SDValue TwoToFractionalPartOfX =
3738 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3740 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3741 MVT::f32, TwoToFractionalPartOfX);
3742 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3743 // For floating-point precision of 18:
3745 // TwoToFractionalPartOfX =
3749 // (0.554906021e-1f +
3750 // (0.961591928e-2f +
3751 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3752 // error 2.47208000*10^(-7), which is better than 18 bits
3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3754 getF32Constant(DAG, 0x3924b03e));
3755 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3756 getF32Constant(DAG, 0x3ab24b87));
3757 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3758 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3759 getF32Constant(DAG, 0x3c1d8c17));
3760 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3761 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3762 getF32Constant(DAG, 0x3d634a1d));
3763 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3764 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3765 getF32Constant(DAG, 0x3e75fe14));
3766 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3767 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3768 getF32Constant(DAG, 0x3f317234));
3769 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3770 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3771 getF32Constant(DAG, 0x3f800000));
3772 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3773 SDValue TwoToFractionalPartOfX =
3774 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3776 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3777 MVT::f32, TwoToFractionalPartOfX);
3780 // No special expansion.
3781 result = DAG.getNode(ISD::FPOW, dl,
3782 getValue(I.getOperand(1)).getValueType(),
3783 getValue(I.getOperand(1)),
3784 getValue(I.getOperand(2)));
3787 setValue(&I, result);
3790 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3791 /// we want to emit this as a call to a named external function, return the name
3792 /// otherwise lower it and return null.
3794 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3795 DebugLoc dl = getCurDebugLoc();
3796 switch (Intrinsic) {
3798 // By default, turn this into a target intrinsic node.
3799 visitTargetIntrinsic(I, Intrinsic);
3801 case Intrinsic::vastart: visitVAStart(I); return 0;
3802 case Intrinsic::vaend: visitVAEnd(I); return 0;
3803 case Intrinsic::vacopy: visitVACopy(I); return 0;
3804 case Intrinsic::returnaddress:
3805 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3806 getValue(I.getOperand(1))));
3808 case Intrinsic::frameaddress:
3809 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3810 getValue(I.getOperand(1))));
3812 case Intrinsic::setjmp:
3813 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3815 case Intrinsic::longjmp:
3816 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3818 case Intrinsic::memcpy: {
3819 SDValue Op1 = getValue(I.getOperand(1));
3820 SDValue Op2 = getValue(I.getOperand(2));
3821 SDValue Op3 = getValue(I.getOperand(3));
3822 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3823 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3824 I.getOperand(1), 0, I.getOperand(2), 0));
3827 case Intrinsic::memset: {
3828 SDValue Op1 = getValue(I.getOperand(1));
3829 SDValue Op2 = getValue(I.getOperand(2));
3830 SDValue Op3 = getValue(I.getOperand(3));
3831 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3832 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3833 I.getOperand(1), 0));
3836 case Intrinsic::memmove: {
3837 SDValue Op1 = getValue(I.getOperand(1));
3838 SDValue Op2 = getValue(I.getOperand(2));
3839 SDValue Op3 = getValue(I.getOperand(3));
3840 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3842 // If the source and destination are known to not be aliases, we can
3843 // lower memmove as memcpy.
3844 uint64_t Size = -1ULL;
3845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3846 Size = C->getZExtValue();
3847 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3848 AliasAnalysis::NoAlias) {
3849 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3850 I.getOperand(1), 0, I.getOperand(2), 0));
3854 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3855 I.getOperand(1), 0, I.getOperand(2), 0));
3858 case Intrinsic::dbg_stoppoint: {
3859 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3860 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3861 MachineFunction &MF = DAG.getMachineFunction();
3862 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3863 setCurDebugLoc(Loc);
3865 if (OptLevel == CodeGenOpt::None)
3866 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3873 case Intrinsic::dbg_region_start: {
3874 DwarfWriter *DW = DAG.getDwarfWriter();
3875 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3876 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3877 && DW->ShouldEmitDwarfDebug()) {
3879 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3880 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3881 getRoot(), LabelID));
3885 case Intrinsic::dbg_region_end: {
3886 DwarfWriter *DW = DAG.getDwarfWriter();
3887 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3889 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3890 || !DW->ShouldEmitDwarfDebug())
3893 MachineFunction &MF = DAG.getMachineFunction();
3894 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3896 if (isInlinedFnEnd(REI, MF.getFunction())) {
3897 // This is end of inlined function. Debugging information for inlined
3898 // function is not handled yet (only supported by FastISel).
3899 if (OptLevel == CodeGenOpt::None) {
3900 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3902 // Returned ID is 0 if this is unbalanced "end of inlined
3903 // scope". This could happen if optimizer eats dbg intrinsics or
3904 // "beginning of inlined scope" is not recoginized due to missing
3905 // location info. In such cases, do ignore this region.end.
3906 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3913 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3914 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3915 getRoot(), LabelID));
3918 case Intrinsic::dbg_func_start: {
3919 DwarfWriter *DW = DAG.getDwarfWriter();
3920 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3921 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3924 MachineFunction &MF = DAG.getMachineFunction();
3925 // This is a beginning of an inlined function.
3926 if (isInlinedFnStart(FSI, MF.getFunction())) {
3927 if (OptLevel != CodeGenOpt::None)
3928 // FIXME: Debugging informaation for inlined function is only
3929 // supported at CodeGenOpt::Node.
3932 DebugLoc PrevLoc = CurDebugLoc;
3933 // If llvm.dbg.func.start is seen in a new block before any
3934 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3935 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3936 if (PrevLoc.isUnknown())
3939 // Record the source line.
3940 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3942 if (!DW || !DW->ShouldEmitDwarfDebug())
3944 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3945 DISubprogram SP(cast<GlobalVariable>(FSI.getSubprogram()));
3946 DICompileUnit CU(PrevLocTpl.CompileUnit);
3947 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3950 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3951 getRoot(), LabelID));
3955 // This is a beginning of a new function.
3956 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3958 if (!DW || !DW->ShouldEmitDwarfDebug())
3960 // llvm.dbg.func_start also defines beginning of function scope.
3961 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
3964 case Intrinsic::dbg_declare: {
3965 if (OptLevel != CodeGenOpt::None)
3966 // FIXME: Variable debug info is not supported here.
3969 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3970 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3973 Value *Variable = DI.getVariable();
3974 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3975 getValue(DI.getAddress()), getValue(Variable)));
3978 case Intrinsic::eh_exception: {
3979 // Insert the EXCEPTIONADDR instruction.
3980 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3981 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3983 Ops[0] = DAG.getRoot();
3984 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3986 DAG.setRoot(Op.getValue(1));
3990 case Intrinsic::eh_selector_i32:
3991 case Intrinsic::eh_selector_i64: {
3992 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3993 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3994 MVT::i32 : MVT::i64);
3997 if (CurMBB->isLandingPad())
3998 AddCatchInfo(I, MMI, CurMBB);
4001 FuncInfo.CatchInfoLost.insert(&I);
4003 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4004 unsigned Reg = TLI.getExceptionSelectorRegister();
4005 if (Reg) CurMBB->addLiveIn(Reg);
4008 // Insert the EHSELECTION instruction.
4009 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4011 Ops[0] = getValue(I.getOperand(1));
4013 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4015 DAG.setRoot(Op.getValue(1));
4017 setValue(&I, DAG.getConstant(0, VT));
4023 case Intrinsic::eh_typeid_for_i32:
4024 case Intrinsic::eh_typeid_for_i64: {
4025 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4026 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4027 MVT::i32 : MVT::i64);
4030 // Find the type id for the given typeinfo.
4031 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4033 unsigned TypeID = MMI->getTypeIDFor(GV);
4034 setValue(&I, DAG.getConstant(TypeID, VT));
4036 // Return something different to eh_selector.
4037 setValue(&I, DAG.getConstant(1, VT));
4043 case Intrinsic::eh_return_i32:
4044 case Intrinsic::eh_return_i64:
4045 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4046 MMI->setCallsEHReturn(true);
4047 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4050 getValue(I.getOperand(1)),
4051 getValue(I.getOperand(2))));
4053 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4057 case Intrinsic::eh_unwind_init:
4058 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4059 MMI->setCallsUnwindInit(true);
4064 case Intrinsic::eh_dwarf_cfa: {
4065 MVT VT = getValue(I.getOperand(1)).getValueType();
4067 if (VT.bitsGT(TLI.getPointerTy()))
4068 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4069 TLI.getPointerTy(), getValue(I.getOperand(1)));
4071 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4072 TLI.getPointerTy(), getValue(I.getOperand(1)));
4074 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4076 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4077 TLI.getPointerTy()),
4079 setValue(&I, DAG.getNode(ISD::ADD, dl,
4081 DAG.getNode(ISD::FRAMEADDR, dl,
4084 TLI.getPointerTy())),
4089 case Intrinsic::convertff:
4090 case Intrinsic::convertfsi:
4091 case Intrinsic::convertfui:
4092 case Intrinsic::convertsif:
4093 case Intrinsic::convertuif:
4094 case Intrinsic::convertss:
4095 case Intrinsic::convertsu:
4096 case Intrinsic::convertus:
4097 case Intrinsic::convertuu: {
4098 ISD::CvtCode Code = ISD::CVT_INVALID;
4099 switch (Intrinsic) {
4100 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4101 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4102 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4103 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4104 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4105 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4106 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4107 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4108 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4110 MVT DestVT = TLI.getValueType(I.getType());
4111 Value* Op1 = I.getOperand(1);
4112 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4113 DAG.getValueType(DestVT),
4114 DAG.getValueType(getValue(Op1).getValueType()),
4115 getValue(I.getOperand(2)),
4116 getValue(I.getOperand(3)),
4121 case Intrinsic::sqrt:
4122 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4123 getValue(I.getOperand(1)).getValueType(),
4124 getValue(I.getOperand(1))));
4126 case Intrinsic::powi:
4127 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4128 getValue(I.getOperand(1)).getValueType(),
4129 getValue(I.getOperand(1)),
4130 getValue(I.getOperand(2))));
4132 case Intrinsic::sin:
4133 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4134 getValue(I.getOperand(1)).getValueType(),
4135 getValue(I.getOperand(1))));
4137 case Intrinsic::cos:
4138 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4139 getValue(I.getOperand(1)).getValueType(),
4140 getValue(I.getOperand(1))));
4142 case Intrinsic::log:
4145 case Intrinsic::log2:
4148 case Intrinsic::log10:
4151 case Intrinsic::exp:
4154 case Intrinsic::exp2:
4157 case Intrinsic::pow:
4160 case Intrinsic::pcmarker: {
4161 SDValue Tmp = getValue(I.getOperand(1));
4162 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4165 case Intrinsic::readcyclecounter: {
4166 SDValue Op = getRoot();
4167 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4168 DAG.getVTList(MVT::i64, MVT::Other),
4171 DAG.setRoot(Tmp.getValue(1));
4174 case Intrinsic::bswap:
4175 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4176 getValue(I.getOperand(1)).getValueType(),
4177 getValue(I.getOperand(1))));
4179 case Intrinsic::cttz: {
4180 SDValue Arg = getValue(I.getOperand(1));
4181 MVT Ty = Arg.getValueType();
4182 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4183 setValue(&I, result);
4186 case Intrinsic::ctlz: {
4187 SDValue Arg = getValue(I.getOperand(1));
4188 MVT Ty = Arg.getValueType();
4189 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4190 setValue(&I, result);
4193 case Intrinsic::ctpop: {
4194 SDValue Arg = getValue(I.getOperand(1));
4195 MVT Ty = Arg.getValueType();
4196 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4197 setValue(&I, result);
4200 case Intrinsic::stacksave: {
4201 SDValue Op = getRoot();
4202 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4203 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4205 DAG.setRoot(Tmp.getValue(1));
4208 case Intrinsic::stackrestore: {
4209 SDValue Tmp = getValue(I.getOperand(1));
4210 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4213 case Intrinsic::stackprotector: {
4214 // Emit code into the DAG to store the stack guard onto the stack.
4215 MachineFunction &MF = DAG.getMachineFunction();
4216 MachineFrameInfo *MFI = MF.getFrameInfo();
4217 MVT PtrTy = TLI.getPointerTy();
4219 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4220 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4222 int FI = FuncInfo.StaticAllocaMap[Slot];
4223 MFI->setStackProtectorIndex(FI);
4225 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4227 // Store the stack protector onto the stack.
4228 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4229 PseudoSourceValue::getFixedStack(FI),
4231 setValue(&I, Result);
4232 DAG.setRoot(Result);
4235 case Intrinsic::var_annotation:
4236 // Discard annotate attributes
4239 case Intrinsic::init_trampoline: {
4240 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4244 Ops[1] = getValue(I.getOperand(1));
4245 Ops[2] = getValue(I.getOperand(2));
4246 Ops[3] = getValue(I.getOperand(3));
4247 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4248 Ops[5] = DAG.getSrcValue(F);
4250 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4251 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4255 DAG.setRoot(Tmp.getValue(1));
4259 case Intrinsic::gcroot:
4261 Value *Alloca = I.getOperand(1);
4262 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4264 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4265 GFI->addStackRoot(FI->getIndex(), TypeMap);
4269 case Intrinsic::gcread:
4270 case Intrinsic::gcwrite:
4271 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4274 case Intrinsic::flt_rounds: {
4275 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4279 case Intrinsic::trap: {
4280 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4284 case Intrinsic::uadd_with_overflow:
4285 return implVisitAluOverflow(I, ISD::UADDO);
4286 case Intrinsic::sadd_with_overflow:
4287 return implVisitAluOverflow(I, ISD::SADDO);
4288 case Intrinsic::usub_with_overflow:
4289 return implVisitAluOverflow(I, ISD::USUBO);
4290 case Intrinsic::ssub_with_overflow:
4291 return implVisitAluOverflow(I, ISD::SSUBO);
4292 case Intrinsic::umul_with_overflow:
4293 return implVisitAluOverflow(I, ISD::UMULO);
4294 case Intrinsic::smul_with_overflow:
4295 return implVisitAluOverflow(I, ISD::SMULO);
4297 case Intrinsic::prefetch: {
4300 Ops[1] = getValue(I.getOperand(1));
4301 Ops[2] = getValue(I.getOperand(2));
4302 Ops[3] = getValue(I.getOperand(3));
4303 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4307 case Intrinsic::memory_barrier: {
4310 for (int x = 1; x < 6; ++x)
4311 Ops[x] = getValue(I.getOperand(x));
4313 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4316 case Intrinsic::atomic_cmp_swap: {
4317 SDValue Root = getRoot();
4319 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4320 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4322 getValue(I.getOperand(1)),
4323 getValue(I.getOperand(2)),
4324 getValue(I.getOperand(3)),
4327 DAG.setRoot(L.getValue(1));
4330 case Intrinsic::atomic_load_add:
4331 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4332 case Intrinsic::atomic_load_sub:
4333 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4334 case Intrinsic::atomic_load_or:
4335 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4336 case Intrinsic::atomic_load_xor:
4337 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4338 case Intrinsic::atomic_load_and:
4339 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4340 case Intrinsic::atomic_load_nand:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4342 case Intrinsic::atomic_load_max:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4344 case Intrinsic::atomic_load_min:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4346 case Intrinsic::atomic_load_umin:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4348 case Intrinsic::atomic_load_umax:
4349 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4350 case Intrinsic::atomic_swap:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4356 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4358 MachineBasicBlock *LandingPad) {
4359 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4360 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4361 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4362 unsigned BeginLabel = 0, EndLabel = 0;
4364 TargetLowering::ArgListTy Args;
4365 TargetLowering::ArgListEntry Entry;
4366 Args.reserve(CS.arg_size());
4367 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4369 SDValue ArgNode = getValue(*i);
4370 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4372 unsigned attrInd = i - CS.arg_begin() + 1;
4373 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4374 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4375 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4376 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4377 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4378 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4379 Entry.Alignment = CS.getParamAlignment(attrInd);
4380 Args.push_back(Entry);
4383 if (LandingPad && MMI) {
4384 // Insert a label before the invoke call to mark the try range. This can be
4385 // used to detect deletion of the invoke via the MachineModuleInfo.
4386 BeginLabel = MMI->NextLabelID();
4387 // Both PendingLoads and PendingExports must be flushed here;
4388 // this call might not return.
4390 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4391 getControlRoot(), BeginLabel));
4394 std::pair<SDValue,SDValue> Result =
4395 TLI.LowerCallTo(getRoot(), CS.getType(),
4396 CS.paramHasAttr(0, Attribute::SExt),
4397 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4398 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4399 CS.getCallingConv(),
4400 IsTailCall && PerformTailCallOpt,
4401 Callee, Args, DAG, getCurDebugLoc());
4402 if (CS.getType() != Type::VoidTy)
4403 setValue(CS.getInstruction(), Result.first);
4404 DAG.setRoot(Result.second);
4406 if (LandingPad && MMI) {
4407 // Insert a label at the end of the invoke call to mark the try range. This
4408 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4409 EndLabel = MMI->NextLabelID();
4410 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4411 getRoot(), EndLabel));
4413 // Inform MachineModuleInfo of range.
4414 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4419 void SelectionDAGLowering::visitCall(CallInst &I) {
4420 const char *RenameFn = 0;
4421 if (Function *F = I.getCalledFunction()) {
4422 if (F->isDeclaration()) {
4423 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4425 if (unsigned IID = II->getIntrinsicID(F)) {
4426 RenameFn = visitIntrinsicCall(I, IID);
4431 if (unsigned IID = F->getIntrinsicID()) {
4432 RenameFn = visitIntrinsicCall(I, IID);
4438 // Check for well-known libc/libm calls. If the function is internal, it
4439 // can't be a library call.
4440 if (!F->hasLocalLinkage() && F->hasName()) {
4441 StringRef Name = F->getName();
4442 if (Name == "copysign" || Name == "copysignf") {
4443 if (I.getNumOperands() == 3 && // Basic sanity checks.
4444 I.getOperand(1)->getType()->isFloatingPoint() &&
4445 I.getType() == I.getOperand(1)->getType() &&
4446 I.getType() == I.getOperand(2)->getType()) {
4447 SDValue LHS = getValue(I.getOperand(1));
4448 SDValue RHS = getValue(I.getOperand(2));
4449 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4450 LHS.getValueType(), LHS, RHS));
4453 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4454 if (I.getNumOperands() == 2 && // Basic sanity checks.
4455 I.getOperand(1)->getType()->isFloatingPoint() &&
4456 I.getType() == I.getOperand(1)->getType()) {
4457 SDValue Tmp = getValue(I.getOperand(1));
4458 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4459 Tmp.getValueType(), Tmp));
4462 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4463 if (I.getNumOperands() == 2 && // Basic sanity checks.
4464 I.getOperand(1)->getType()->isFloatingPoint() &&
4465 I.getType() == I.getOperand(1)->getType()) {
4466 SDValue Tmp = getValue(I.getOperand(1));
4467 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4468 Tmp.getValueType(), Tmp));
4471 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4472 if (I.getNumOperands() == 2 && // Basic sanity checks.
4473 I.getOperand(1)->getType()->isFloatingPoint() &&
4474 I.getType() == I.getOperand(1)->getType()) {
4475 SDValue Tmp = getValue(I.getOperand(1));
4476 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4477 Tmp.getValueType(), Tmp));
4482 } else if (isa<InlineAsm>(I.getOperand(0))) {
4489 Callee = getValue(I.getOperand(0));
4491 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4493 LowerCallTo(&I, Callee, I.isTailCall());
4497 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4498 /// this value and returns the result as a ValueVT value. This uses
4499 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4500 /// If the Flag pointer is NULL, no flag is used.
4501 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4503 SDValue *Flag) const {
4504 // Assemble the legal parts into the final values.
4505 SmallVector<SDValue, 4> Values(ValueVTs.size());
4506 SmallVector<SDValue, 8> Parts;
4507 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4508 // Copy the legal parts from the registers.
4509 MVT ValueVT = ValueVTs[Value];
4510 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4511 MVT RegisterVT = RegVTs[Value];
4513 Parts.resize(NumRegs);
4514 for (unsigned i = 0; i != NumRegs; ++i) {
4517 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4519 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4520 *Flag = P.getValue(2);
4522 Chain = P.getValue(1);
4524 // If the source register was virtual and if we know something about it,
4525 // add an assert node.
4526 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4527 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4528 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4529 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4530 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4531 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4533 unsigned RegSize = RegisterVT.getSizeInBits();
4534 unsigned NumSignBits = LOI.NumSignBits;
4535 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4537 // FIXME: We capture more information than the dag can represent. For
4538 // now, just use the tightest assertzext/assertsext possible.
4540 MVT FromVT(MVT::Other);
4541 if (NumSignBits == RegSize)
4542 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4543 else if (NumZeroBits >= RegSize-1)
4544 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4545 else if (NumSignBits > RegSize-8)
4546 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4547 else if (NumZeroBits >= RegSize-8)
4548 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4549 else if (NumSignBits > RegSize-16)
4550 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4551 else if (NumZeroBits >= RegSize-16)
4552 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4553 else if (NumSignBits > RegSize-32)
4554 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4555 else if (NumZeroBits >= RegSize-32)
4556 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4558 if (FromVT != MVT::Other) {
4559 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4560 RegisterVT, P, DAG.getValueType(FromVT));
4569 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4570 NumRegs, RegisterVT, ValueVT);
4575 return DAG.getNode(ISD::MERGE_VALUES, dl,
4576 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4577 &Values[0], ValueVTs.size());
4580 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4581 /// specified value into the registers specified by this object. This uses
4582 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4583 /// If the Flag pointer is NULL, no flag is used.
4584 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4585 SDValue &Chain, SDValue *Flag) const {
4586 // Get the list of the values's legal parts.
4587 unsigned NumRegs = Regs.size();
4588 SmallVector<SDValue, 8> Parts(NumRegs);
4589 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4590 MVT ValueVT = ValueVTs[Value];
4591 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4592 MVT RegisterVT = RegVTs[Value];
4594 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4595 &Parts[Part], NumParts, RegisterVT);
4599 // Copy the parts into the registers.
4600 SmallVector<SDValue, 8> Chains(NumRegs);
4601 for (unsigned i = 0; i != NumRegs; ++i) {
4604 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4606 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4607 *Flag = Part.getValue(1);
4609 Chains[i] = Part.getValue(0);
4612 if (NumRegs == 1 || Flag)
4613 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4614 // flagged to it. That is the CopyToReg nodes and the user are considered
4615 // a single scheduling unit. If we create a TokenFactor and return it as
4616 // chain, then the TokenFactor is both a predecessor (operand) of the
4617 // user as well as a successor (the TF operands are flagged to the user).
4618 // c1, f1 = CopyToReg
4619 // c2, f2 = CopyToReg
4620 // c3 = TokenFactor c1, c2
4623 Chain = Chains[NumRegs-1];
4625 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4628 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4629 /// operand list. This adds the code marker and includes the number of
4630 /// values added into it.
4631 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4632 bool HasMatching,unsigned MatchingIdx,
4634 std::vector<SDValue> &Ops) const {
4635 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4636 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4637 unsigned Flag = Code | (Regs.size() << 3);
4639 Flag |= 0x80000000 | (MatchingIdx << 16);
4640 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4641 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4642 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4643 MVT RegisterVT = RegVTs[Value];
4644 for (unsigned i = 0; i != NumRegs; ++i) {
4645 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4646 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4651 /// isAllocatableRegister - If the specified register is safe to allocate,
4652 /// i.e. it isn't a stack pointer or some other special register, return the
4653 /// register class for the register. Otherwise, return null.
4654 static const TargetRegisterClass *
4655 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4656 const TargetLowering &TLI,
4657 const TargetRegisterInfo *TRI) {
4658 MVT FoundVT = MVT::Other;
4659 const TargetRegisterClass *FoundRC = 0;
4660 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4661 E = TRI->regclass_end(); RCI != E; ++RCI) {
4662 MVT ThisVT = MVT::Other;
4664 const TargetRegisterClass *RC = *RCI;
4665 // If none of the the value types for this register class are valid, we
4666 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4667 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4669 if (TLI.isTypeLegal(*I)) {
4670 // If we have already found this register in a different register class,
4671 // choose the one with the largest VT specified. For example, on
4672 // PowerPC, we favor f64 register classes over f32.
4673 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4680 if (ThisVT == MVT::Other) continue;
4682 // NOTE: This isn't ideal. In particular, this might allocate the
4683 // frame pointer in functions that need it (due to them not being taken
4684 // out of allocation, because a variable sized allocation hasn't been seen
4685 // yet). This is a slight code pessimization, but should still work.
4686 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4687 E = RC->allocation_order_end(MF); I != E; ++I)
4689 // We found a matching register class. Keep looking at others in case
4690 // we find one with larger registers that this physreg is also in.
4701 /// AsmOperandInfo - This contains information for each constraint that we are
4703 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4704 public TargetLowering::AsmOperandInfo {
4706 /// CallOperand - If this is the result output operand or a clobber
4707 /// this is null, otherwise it is the incoming operand to the CallInst.
4708 /// This gets modified as the asm is processed.
4709 SDValue CallOperand;
4711 /// AssignedRegs - If this is a register or register class operand, this
4712 /// contains the set of register corresponding to the operand.
4713 RegsForValue AssignedRegs;
4715 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4716 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4719 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4720 /// busy in OutputRegs/InputRegs.
4721 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4722 std::set<unsigned> &OutputRegs,
4723 std::set<unsigned> &InputRegs,
4724 const TargetRegisterInfo &TRI) const {
4726 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4727 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4730 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4731 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4735 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4736 /// corresponds to. If there is no Value* for this operand, it returns
4738 MVT getCallOperandValMVT(const TargetLowering &TLI,
4739 const TargetData *TD) const {
4740 if (CallOperandVal == 0) return MVT::Other;
4742 if (isa<BasicBlock>(CallOperandVal))
4743 return TLI.getPointerTy();
4745 const llvm::Type *OpTy = CallOperandVal->getType();
4747 // If this is an indirect operand, the operand is a pointer to the
4750 OpTy = cast<PointerType>(OpTy)->getElementType();
4752 // If OpTy is not a single value, it may be a struct/union that we
4753 // can tile with integers.
4754 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4755 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4764 OpTy = IntegerType::get(BitSize);
4769 return TLI.getValueType(OpTy, true);
4773 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4775 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4776 const TargetRegisterInfo &TRI) {
4777 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4779 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4780 for (; *Aliases; ++Aliases)
4781 Regs.insert(*Aliases);
4784 } // end llvm namespace.
4787 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4788 /// specified operand. We prefer to assign virtual registers, to allow the
4789 /// register allocator handle the assignment process. However, if the asm uses
4790 /// features that we can't model on machineinstrs, we have SDISel do the
4791 /// allocation. This produces generally horrible, but correct, code.
4793 /// OpInfo describes the operand.
4794 /// Input and OutputRegs are the set of already allocated physical registers.
4796 void SelectionDAGLowering::
4797 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4798 std::set<unsigned> &OutputRegs,
4799 std::set<unsigned> &InputRegs) {
4800 // Compute whether this value requires an input register, an output register,
4802 bool isOutReg = false;
4803 bool isInReg = false;
4804 switch (OpInfo.Type) {
4805 case InlineAsm::isOutput:
4808 // If there is an input constraint that matches this, we need to reserve
4809 // the input register so no other inputs allocate to it.
4810 isInReg = OpInfo.hasMatchingInput();
4812 case InlineAsm::isInput:
4816 case InlineAsm::isClobber:
4823 MachineFunction &MF = DAG.getMachineFunction();
4824 SmallVector<unsigned, 4> Regs;
4826 // If this is a constraint for a single physreg, or a constraint for a
4827 // register class, find it.
4828 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4829 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4830 OpInfo.ConstraintVT);
4832 unsigned NumRegs = 1;
4833 if (OpInfo.ConstraintVT != MVT::Other) {
4834 // If this is a FP input in an integer register (or visa versa) insert a bit
4835 // cast of the input value. More generally, handle any case where the input
4836 // value disagrees with the register class we plan to stick this in.
4837 if (OpInfo.Type == InlineAsm::isInput &&
4838 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4839 // Try to convert to the first MVT that the reg class contains. If the
4840 // types are identical size, use a bitcast to convert (e.g. two differing
4842 MVT RegVT = *PhysReg.second->vt_begin();
4843 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4844 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4845 RegVT, OpInfo.CallOperand);
4846 OpInfo.ConstraintVT = RegVT;
4847 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4848 // If the input is a FP value and we want it in FP registers, do a
4849 // bitcast to the corresponding integer type. This turns an f64 value
4850 // into i64, which can be passed with two i32 values on a 32-bit
4852 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4853 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4854 RegVT, OpInfo.CallOperand);
4855 OpInfo.ConstraintVT = RegVT;
4859 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4863 MVT ValueVT = OpInfo.ConstraintVT;
4865 // If this is a constraint for a specific physical register, like {r17},
4867 if (unsigned AssignedReg = PhysReg.first) {
4868 const TargetRegisterClass *RC = PhysReg.second;
4869 if (OpInfo.ConstraintVT == MVT::Other)
4870 ValueVT = *RC->vt_begin();
4872 // Get the actual register value type. This is important, because the user
4873 // may have asked for (e.g.) the AX register in i32 type. We need to
4874 // remember that AX is actually i16 to get the right extension.
4875 RegVT = *RC->vt_begin();
4877 // This is a explicit reference to a physical register.
4878 Regs.push_back(AssignedReg);
4880 // If this is an expanded reference, add the rest of the regs to Regs.
4882 TargetRegisterClass::iterator I = RC->begin();
4883 for (; *I != AssignedReg; ++I)
4884 assert(I != RC->end() && "Didn't find reg!");
4886 // Already added the first reg.
4888 for (; NumRegs; --NumRegs, ++I) {
4889 assert(I != RC->end() && "Ran out of registers to allocate!");
4893 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4894 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4895 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4899 // Otherwise, if this was a reference to an LLVM register class, create vregs
4900 // for this reference.
4901 if (const TargetRegisterClass *RC = PhysReg.second) {
4902 RegVT = *RC->vt_begin();
4903 if (OpInfo.ConstraintVT == MVT::Other)
4906 // Create the appropriate number of virtual registers.
4907 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4908 for (; NumRegs; --NumRegs)
4909 Regs.push_back(RegInfo.createVirtualRegister(RC));
4911 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4915 // This is a reference to a register class that doesn't directly correspond
4916 // to an LLVM register class. Allocate NumRegs consecutive, available,
4917 // registers from the class.
4918 std::vector<unsigned> RegClassRegs
4919 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4920 OpInfo.ConstraintVT);
4922 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4923 unsigned NumAllocated = 0;
4924 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4925 unsigned Reg = RegClassRegs[i];
4926 // See if this register is available.
4927 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4928 (isInReg && InputRegs.count(Reg))) { // Already used.
4929 // Make sure we find consecutive registers.
4934 // Check to see if this register is allocatable (i.e. don't give out the
4936 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4937 if (!RC) { // Couldn't allocate this register.
4938 // Reset NumAllocated to make sure we return consecutive registers.
4943 // Okay, this register is good, we can use it.
4946 // If we allocated enough consecutive registers, succeed.
4947 if (NumAllocated == NumRegs) {
4948 unsigned RegStart = (i-NumAllocated)+1;
4949 unsigned RegEnd = i+1;
4950 // Mark all of the allocated registers used.
4951 for (unsigned i = RegStart; i != RegEnd; ++i)
4952 Regs.push_back(RegClassRegs[i]);
4954 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4955 OpInfo.ConstraintVT);
4956 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4961 // Otherwise, we couldn't allocate enough registers for this.
4964 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4965 /// processed uses a memory 'm' constraint.
4967 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4968 const TargetLowering &TLI) {
4969 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4970 InlineAsm::ConstraintInfo &CI = CInfos[i];
4971 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4972 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4973 if (CType == TargetLowering::C_Memory)
4977 // Indirect operand accesses access memory.
4985 /// visitInlineAsm - Handle a call to an InlineAsm object.
4987 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4988 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4990 /// ConstraintOperands - Information about all of the constraints.
4991 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4993 std::set<unsigned> OutputRegs, InputRegs;
4995 // Do a prepass over the constraints, canonicalizing them, and building up the
4996 // ConstraintOperands list.
4997 std::vector<InlineAsm::ConstraintInfo>
4998 ConstraintInfos = IA->ParseConstraints();
5000 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5002 SDValue Chain, Flag;
5004 // We won't need to flush pending loads if this asm doesn't touch
5005 // memory and is nonvolatile.
5006 if (hasMemory || IA->hasSideEffects())
5009 Chain = DAG.getRoot();
5011 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5012 unsigned ResNo = 0; // ResNo - The result number of the next output.
5013 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5014 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5015 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5017 MVT OpVT = MVT::Other;
5019 // Compute the value type for each operand.
5020 switch (OpInfo.Type) {
5021 case InlineAsm::isOutput:
5022 // Indirect outputs just consume an argument.
5023 if (OpInfo.isIndirect) {
5024 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5028 // The return value of the call is this value. As such, there is no
5029 // corresponding argument.
5030 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5031 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5032 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5034 assert(ResNo == 0 && "Asm only has one result!");
5035 OpVT = TLI.getValueType(CS.getType());
5039 case InlineAsm::isInput:
5040 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5042 case InlineAsm::isClobber:
5047 // If this is an input or an indirect output, process the call argument.
5048 // BasicBlocks are labels, currently appearing only in asm's.
5049 if (OpInfo.CallOperandVal) {
5050 // Strip bitcasts, if any. This mostly comes up for functions.
5051 ConstantExpr* CE = NULL;
5052 while ((CE = dyn_cast<ConstantExpr>(OpInfo.CallOperandVal)) &&
5053 CE->getOpcode()==Instruction::BitCast)
5054 OpInfo.CallOperandVal = CE->getOperand(0);
5055 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5056 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5058 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5061 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5064 OpInfo.ConstraintVT = OpVT;
5067 // Second pass over the constraints: compute which constraint option to use
5068 // and assign registers to constraints that want a specific physreg.
5069 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5070 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5072 // If this is an output operand with a matching input operand, look up the
5073 // matching input. If their types mismatch, e.g. one is an integer, the
5074 // other is floating point, or their sizes are different, flag it as an
5076 if (OpInfo.hasMatchingInput()) {
5077 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5078 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5079 if ((OpInfo.ConstraintVT.isInteger() !=
5080 Input.ConstraintVT.isInteger()) ||
5081 (OpInfo.ConstraintVT.getSizeInBits() !=
5082 Input.ConstraintVT.getSizeInBits())) {
5083 llvm_report_error("llvm: error: Unsupported asm: input constraint"
5084 " with a matching output constraint of incompatible"
5087 Input.ConstraintVT = OpInfo.ConstraintVT;
5091 // Compute the constraint code and ConstraintType to use.
5092 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5094 // If this is a memory input, and if the operand is not indirect, do what we
5095 // need to to provide an address for the memory input.
5096 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5097 !OpInfo.isIndirect) {
5098 assert(OpInfo.Type == InlineAsm::isInput &&
5099 "Can only indirectify direct input operands!");
5101 // Memory operands really want the address of the value. If we don't have
5102 // an indirect input, put it in the constpool if we can, otherwise spill
5103 // it to a stack slot.
5105 // If the operand is a float, integer, or vector constant, spill to a
5106 // constant pool entry to get its address.
5107 Value *OpVal = OpInfo.CallOperandVal;
5108 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5109 isa<ConstantVector>(OpVal)) {
5110 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5111 TLI.getPointerTy());
5113 // Otherwise, create a stack slot and emit a store to it before the
5115 const Type *Ty = OpVal->getType();
5116 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5117 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5118 MachineFunction &MF = DAG.getMachineFunction();
5119 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5120 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5121 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5122 OpInfo.CallOperand, StackSlot, NULL, 0);
5123 OpInfo.CallOperand = StackSlot;
5126 // There is no longer a Value* corresponding to this operand.
5127 OpInfo.CallOperandVal = 0;
5128 // It is now an indirect operand.
5129 OpInfo.isIndirect = true;
5132 // If this constraint is for a specific register, allocate it before
5134 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5135 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5137 ConstraintInfos.clear();
5140 // Second pass - Loop over all of the operands, assigning virtual or physregs
5141 // to register class operands.
5142 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5143 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5145 // C_Register operands have already been allocated, Other/Memory don't need
5147 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5148 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5151 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5152 std::vector<SDValue> AsmNodeOperands;
5153 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5154 AsmNodeOperands.push_back(
5155 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5158 // Loop over all of the inputs, copying the operand values into the
5159 // appropriate registers and processing the output regs.
5160 RegsForValue RetValRegs;
5162 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5163 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5165 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5166 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5168 switch (OpInfo.Type) {
5169 case InlineAsm::isOutput: {
5170 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5171 OpInfo.ConstraintType != TargetLowering::C_Register) {
5172 // Memory output, or 'other' output (e.g. 'X' constraint).
5173 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5175 // Add information to the INLINEASM node to know about this output.
5176 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5177 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5178 TLI.getPointerTy()));
5179 AsmNodeOperands.push_back(OpInfo.CallOperand);
5183 // Otherwise, this is a register or register class output.
5185 // Copy the output from the appropriate register. Find a register that
5187 if (OpInfo.AssignedRegs.Regs.empty()) {
5188 llvm_report_error("llvm: error: Couldn't allocate output reg for"
5189 " constraint '" + OpInfo.ConstraintCode + "'!");
5192 // If this is an indirect operand, store through the pointer after the
5194 if (OpInfo.isIndirect) {
5195 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5196 OpInfo.CallOperandVal));
5198 // This is the result value of the call.
5199 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5200 // Concatenate this output onto the outputs list.
5201 RetValRegs.append(OpInfo.AssignedRegs);
5204 // Add information to the INLINEASM node to know that this register is
5206 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5207 6 /* EARLYCLOBBER REGDEF */ :
5211 DAG, AsmNodeOperands);
5214 case InlineAsm::isInput: {
5215 SDValue InOperandVal = OpInfo.CallOperand;
5217 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5218 // If this is required to match an output register we have already set,
5219 // just use its register.
5220 unsigned OperandNo = OpInfo.getMatchedOperand();
5222 // Scan until we find the definition we already emitted of this operand.
5223 // When we find it, create a RegsForValue operand.
5224 unsigned CurOp = 2; // The first operand.
5225 for (; OperandNo; --OperandNo) {
5226 // Advance to the next operand.
5228 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5229 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5230 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5231 (OpFlag & 7) == 4 /*MEM*/) &&
5232 "Skipped past definitions?");
5233 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5237 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5238 if ((OpFlag & 7) == 2 /*REGDEF*/
5239 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5240 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5241 if (OpInfo.isIndirect) {
5242 llvm_report_error("llvm: error: "
5243 "Don't know how to handle tied indirect "
5244 "register inputs yet!");
5246 RegsForValue MatchedRegs;
5247 MatchedRegs.TLI = &TLI;
5248 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5249 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5250 MatchedRegs.RegVTs.push_back(RegVT);
5251 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5252 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5255 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5257 // Use the produced MatchedRegs object to
5258 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5260 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5261 true, OpInfo.getMatchedOperand(),
5262 DAG, AsmNodeOperands);
5265 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5266 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5267 "Unexpected number of operands");
5268 // Add information to the INLINEASM node to know about this input.
5269 // See InlineAsm.h isUseOperandTiedToDef.
5270 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5271 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5272 TLI.getPointerTy()));
5273 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5278 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5279 assert(!OpInfo.isIndirect &&
5280 "Don't know how to handle indirect other inputs yet!");
5282 std::vector<SDValue> Ops;
5283 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5284 hasMemory, Ops, DAG);
5286 llvm_report_error("llvm: error: Invalid operand for inline asm"
5287 " constraint '" + OpInfo.ConstraintCode + "'!");
5290 // Add information to the INLINEASM node to know about this input.
5291 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5292 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5293 TLI.getPointerTy()));
5294 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5296 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5297 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5298 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5299 "Memory operands expect pointer values");
5301 // Add information to the INLINEASM node to know about this input.
5302 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5303 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5304 TLI.getPointerTy()));
5305 AsmNodeOperands.push_back(InOperandVal);
5309 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5310 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5311 "Unknown constraint type!");
5312 assert(!OpInfo.isIndirect &&
5313 "Don't know how to handle indirect register inputs yet!");
5315 // Copy the input into the appropriate registers.
5316 if (OpInfo.AssignedRegs.Regs.empty()) {
5317 llvm_report_error("llvm: error: Couldn't allocate input reg for"
5318 " constraint '"+ OpInfo.ConstraintCode +"'!");
5321 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5324 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5325 DAG, AsmNodeOperands);
5328 case InlineAsm::isClobber: {
5329 // Add the clobbered value to the operand list, so that the register
5330 // allocator is aware that the physreg got clobbered.
5331 if (!OpInfo.AssignedRegs.Regs.empty())
5332 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5333 false, 0, DAG,AsmNodeOperands);
5339 // Finish up input operands.
5340 AsmNodeOperands[0] = Chain;
5341 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5343 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5344 DAG.getVTList(MVT::Other, MVT::Flag),
5345 &AsmNodeOperands[0], AsmNodeOperands.size());
5346 Flag = Chain.getValue(1);
5348 // If this asm returns a register value, copy the result from that register
5349 // and set it as the value of the call.
5350 if (!RetValRegs.Regs.empty()) {
5351 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5354 // FIXME: Why don't we do this for inline asms with MRVs?
5355 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5356 MVT ResultType = TLI.getValueType(CS.getType());
5358 // If any of the results of the inline asm is a vector, it may have the
5359 // wrong width/num elts. This can happen for register classes that can
5360 // contain multiple different value types. The preg or vreg allocated may
5361 // not have the same VT as was expected. Convert it to the right type
5362 // with bit_convert.
5363 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5364 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5367 } else if (ResultType != Val.getValueType() &&
5368 ResultType.isInteger() && Val.getValueType().isInteger()) {
5369 // If a result value was tied to an input value, the computed result may
5370 // have a wider width than the expected result. Extract the relevant
5372 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5375 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5378 setValue(CS.getInstruction(), Val);
5379 // Don't need to use this as a chain in this case.
5380 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5384 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5386 // Process indirect outputs, first output all of the flagged copies out of
5388 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5389 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5390 Value *Ptr = IndirectStoresToEmit[i].second;
5391 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5393 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5397 // Emit the non-flagged stores from the physregs.
5398 SmallVector<SDValue, 8> OutChains;
5399 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5400 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5401 StoresToEmit[i].first,
5402 getValue(StoresToEmit[i].second),
5403 StoresToEmit[i].second, 0));
5404 if (!OutChains.empty())
5405 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5406 &OutChains[0], OutChains.size());
5411 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5412 SDValue Src = getValue(I.getOperand(0));
5414 // Scale up by the type size in the original i32 type width. Various
5415 // mid-level optimizers may make assumptions about demanded bits etc from the
5416 // i32-ness of the optimizer: we do not want to promote to i64 and then
5417 // multiply on 64-bit targets.
5418 // FIXME: Malloc inst should go away: PR715.
5419 uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
5420 if (ElementSize != 1) {
5421 // Src is always 32-bits, make sure the constant fits.
5422 assert(Src.getValueType() == MVT::i32);
5423 ElementSize = (uint32_t)ElementSize;
5424 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5425 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5428 MVT IntPtr = TLI.getPointerTy();
5430 if (IntPtr.bitsLT(Src.getValueType()))
5431 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5432 else if (IntPtr.bitsGT(Src.getValueType()))
5433 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5435 TargetLowering::ArgListTy Args;
5436 TargetLowering::ArgListEntry Entry;
5438 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5439 Args.push_back(Entry);
5441 std::pair<SDValue,SDValue> Result =
5442 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5443 0, CallingConv::C, PerformTailCallOpt,
5444 DAG.getExternalSymbol("malloc", IntPtr),
5445 Args, DAG, getCurDebugLoc());
5446 setValue(&I, Result.first); // Pointers always fit in registers
5447 DAG.setRoot(Result.second);
5450 void SelectionDAGLowering::visitFree(FreeInst &I) {
5451 TargetLowering::ArgListTy Args;
5452 TargetLowering::ArgListEntry Entry;
5453 Entry.Node = getValue(I.getOperand(0));
5454 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5455 Args.push_back(Entry);
5456 MVT IntPtr = TLI.getPointerTy();
5457 std::pair<SDValue,SDValue> Result =
5458 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5459 0, CallingConv::C, PerformTailCallOpt,
5460 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5462 DAG.setRoot(Result.second);
5465 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5466 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5467 MVT::Other, getRoot(),
5468 getValue(I.getOperand(1)),
5469 DAG.getSrcValue(I.getOperand(1))));
5472 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5473 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5474 getRoot(), getValue(I.getOperand(0)),
5475 DAG.getSrcValue(I.getOperand(0)));
5477 DAG.setRoot(V.getValue(1));
5480 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5481 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5482 MVT::Other, getRoot(),
5483 getValue(I.getOperand(1)),
5484 DAG.getSrcValue(I.getOperand(1))));
5487 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5488 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5489 MVT::Other, getRoot(),
5490 getValue(I.getOperand(1)),
5491 getValue(I.getOperand(2)),
5492 DAG.getSrcValue(I.getOperand(1)),
5493 DAG.getSrcValue(I.getOperand(2))));
5496 /// TargetLowering::LowerArguments - This is the default LowerArguments
5497 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5498 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5499 /// integrated into SDISel.
5500 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5501 SmallVectorImpl<SDValue> &ArgValues,
5503 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5504 SmallVector<SDValue, 3+16> Ops;
5505 Ops.push_back(DAG.getRoot());
5506 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5507 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5509 // Add one result value for each formal argument.
5510 SmallVector<MVT, 16> RetVals;
5512 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5514 SmallVector<MVT, 4> ValueVTs;
5515 ComputeValueVTs(*this, I->getType(), ValueVTs);
5516 for (unsigned Value = 0, NumValues = ValueVTs.size();
5517 Value != NumValues; ++Value) {
5518 MVT VT = ValueVTs[Value];
5519 const Type *ArgTy = VT.getTypeForMVT(*DAG.getContext());
5520 ISD::ArgFlagsTy Flags;
5521 unsigned OriginalAlignment =
5522 getTargetData()->getABITypeAlignment(ArgTy);
5524 if (F.paramHasAttr(j, Attribute::ZExt))
5526 if (F.paramHasAttr(j, Attribute::SExt))
5528 if (F.paramHasAttr(j, Attribute::InReg))
5530 if (F.paramHasAttr(j, Attribute::StructRet))
5532 if (F.paramHasAttr(j, Attribute::ByVal)) {
5534 const PointerType *Ty = cast<PointerType>(I->getType());
5535 const Type *ElementTy = Ty->getElementType();
5536 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5537 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5538 // For ByVal, alignment should be passed from FE. BE will guess if
5539 // this info is not there but there are cases it cannot get right.
5540 if (F.getParamAlignment(j))
5541 FrameAlign = F.getParamAlignment(j);
5542 Flags.setByValAlign(FrameAlign);
5543 Flags.setByValSize(FrameSize);
5545 if (F.paramHasAttr(j, Attribute::Nest))
5547 Flags.setOrigAlign(OriginalAlignment);
5549 MVT RegisterVT = getRegisterType(VT);
5550 unsigned NumRegs = getNumRegisters(VT);
5551 for (unsigned i = 0; i != NumRegs; ++i) {
5552 RetVals.push_back(RegisterVT);
5553 ISD::ArgFlagsTy MyFlags = Flags;
5554 if (NumRegs > 1 && i == 0)
5556 // if it isn't first piece, alignment must be 1
5558 MyFlags.setOrigAlign(1);
5559 Ops.push_back(DAG.getArgFlags(MyFlags));
5564 RetVals.push_back(MVT::Other);
5567 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5568 DAG.getVTList(&RetVals[0], RetVals.size()),
5569 &Ops[0], Ops.size()).getNode();
5571 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5572 // allows exposing the loads that may be part of the argument access to the
5573 // first DAGCombiner pass.
5574 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5576 // The number of results should match up, except that the lowered one may have
5577 // an extra flag result.
5578 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5579 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5580 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5581 && "Lowering produced unexpected number of results!");
5583 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5584 if (Result != TmpRes.getNode() && Result->use_empty()) {
5585 HandleSDNode Dummy(DAG.getRoot());
5586 DAG.RemoveDeadNode(Result);
5589 Result = TmpRes.getNode();
5591 unsigned NumArgRegs = Result->getNumValues() - 1;
5592 DAG.setRoot(SDValue(Result, NumArgRegs));
5594 // Set up the return result vector.
5597 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5599 SmallVector<MVT, 4> ValueVTs;
5600 ComputeValueVTs(*this, I->getType(), ValueVTs);
5601 for (unsigned Value = 0, NumValues = ValueVTs.size();
5602 Value != NumValues; ++Value) {
5603 MVT VT = ValueVTs[Value];
5604 MVT PartVT = getRegisterType(VT);
5606 unsigned NumParts = getNumRegisters(VT);
5607 SmallVector<SDValue, 4> Parts(NumParts);
5608 for (unsigned j = 0; j != NumParts; ++j)
5609 Parts[j] = SDValue(Result, i++);
5611 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5612 if (F.paramHasAttr(Idx, Attribute::SExt))
5613 AssertOp = ISD::AssertSext;
5614 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5615 AssertOp = ISD::AssertZext;
5617 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5618 PartVT, VT, AssertOp));
5621 assert(i == NumArgRegs && "Argument register count mismatch!");
5625 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5626 /// implementation, which just inserts an ISD::CALL node, which is later custom
5627 /// lowered by the target to something concrete. FIXME: When all targets are
5628 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5629 std::pair<SDValue, SDValue>
5630 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5631 bool RetSExt, bool RetZExt, bool isVarArg,
5632 bool isInreg, unsigned NumFixedArgs,
5633 unsigned CallingConv, bool isTailCall,
5635 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5636 assert((!isTailCall || PerformTailCallOpt) &&
5637 "isTailCall set when tail-call optimizations are disabled!");
5639 SmallVector<SDValue, 32> Ops;
5640 Ops.push_back(Chain); // Op#0 - Chain
5641 Ops.push_back(Callee);
5643 // Handle all of the outgoing arguments.
5644 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5645 SmallVector<MVT, 4> ValueVTs;
5646 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5647 for (unsigned Value = 0, NumValues = ValueVTs.size();
5648 Value != NumValues; ++Value) {
5649 MVT VT = ValueVTs[Value];
5650 const Type *ArgTy = VT.getTypeForMVT(*DAG.getContext());
5651 SDValue Op = SDValue(Args[i].Node.getNode(),
5652 Args[i].Node.getResNo() + Value);
5653 ISD::ArgFlagsTy Flags;
5654 unsigned OriginalAlignment =
5655 getTargetData()->getABITypeAlignment(ArgTy);
5661 if (Args[i].isInReg)
5665 if (Args[i].isByVal) {
5667 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5668 const Type *ElementTy = Ty->getElementType();
5669 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5670 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5671 // For ByVal, alignment should come from FE. BE will guess if this
5672 // info is not there but there are cases it cannot get right.
5673 if (Args[i].Alignment)
5674 FrameAlign = Args[i].Alignment;
5675 Flags.setByValAlign(FrameAlign);
5676 Flags.setByValSize(FrameSize);
5680 Flags.setOrigAlign(OriginalAlignment);
5682 MVT PartVT = getRegisterType(VT);
5683 unsigned NumParts = getNumRegisters(VT);
5684 SmallVector<SDValue, 4> Parts(NumParts);
5685 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5688 ExtendKind = ISD::SIGN_EXTEND;
5689 else if (Args[i].isZExt)
5690 ExtendKind = ISD::ZERO_EXTEND;
5692 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5694 for (unsigned i = 0; i != NumParts; ++i) {
5695 // if it isn't first piece, alignment must be 1
5696 ISD::ArgFlagsTy MyFlags = Flags;
5697 if (NumParts > 1 && i == 0)
5700 MyFlags.setOrigAlign(1);
5702 Ops.push_back(Parts[i]);
5703 Ops.push_back(DAG.getArgFlags(MyFlags));
5708 // Figure out the result value types. We start by making a list of
5709 // the potentially illegal return value types.
5710 SmallVector<MVT, 4> LoweredRetTys;
5711 SmallVector<MVT, 4> RetTys;
5712 ComputeValueVTs(*this, RetTy, RetTys);
5714 // Then we translate that to a list of legal types.
5715 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5717 MVT RegisterVT = getRegisterType(VT);
5718 unsigned NumRegs = getNumRegisters(VT);
5719 for (unsigned i = 0; i != NumRegs; ++i)
5720 LoweredRetTys.push_back(RegisterVT);
5723 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5725 // Create the CALL node.
5726 SDValue Res = DAG.getCall(CallingConv, dl,
5727 isVarArg, isTailCall, isInreg,
5728 DAG.getVTList(&LoweredRetTys[0],
5729 LoweredRetTys.size()),
5730 &Ops[0], Ops.size(), NumFixedArgs
5732 Chain = Res.getValue(LoweredRetTys.size() - 1);
5734 // Gather up the call result into a single value.
5735 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5736 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5739 AssertOp = ISD::AssertSext;
5741 AssertOp = ISD::AssertZext;
5743 SmallVector<SDValue, 4> ReturnValues;
5745 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5747 MVT RegisterVT = getRegisterType(VT);
5748 unsigned NumRegs = getNumRegisters(VT);
5749 unsigned RegNoEnd = NumRegs + RegNo;
5750 SmallVector<SDValue, 4> Results;
5751 for (; RegNo != RegNoEnd; ++RegNo)
5752 Results.push_back(Res.getValue(RegNo));
5753 SDValue ReturnValue =
5754 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5756 ReturnValues.push_back(ReturnValue);
5758 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5759 DAG.getVTList(&RetTys[0], RetTys.size()),
5760 &ReturnValues[0], ReturnValues.size());
5763 return std::make_pair(Res, Chain);
5766 void TargetLowering::LowerOperationWrapper(SDNode *N,
5767 SmallVectorImpl<SDValue> &Results,
5768 SelectionDAG &DAG) {
5769 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5771 Results.push_back(Res);
5774 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5775 llvm_unreachable("LowerOperation not implemented for this target!");
5780 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5781 SDValue Op = getValue(V);
5782 assert((Op.getOpcode() != ISD::CopyFromReg ||
5783 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5784 "Copy from a reg to the same reg!");
5785 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5787 RegsForValue RFV(TLI, Reg, V->getType());
5788 SDValue Chain = DAG.getEntryNode();
5789 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5790 PendingExports.push_back(Chain);
5793 #include "llvm/CodeGen/SelectionDAGISel.h"
5795 void SelectionDAGISel::
5796 LowerArguments(BasicBlock *LLVMBB) {
5797 // If this is the entry block, emit arguments.
5798 Function &F = *LLVMBB->getParent();
5799 SDValue OldRoot = SDL->DAG.getRoot();
5800 SmallVector<SDValue, 16> Args;
5801 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5804 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5806 SmallVector<MVT, 4> ValueVTs;
5807 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5808 unsigned NumValues = ValueVTs.size();
5809 if (!AI->use_empty()) {
5810 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5811 SDL->getCurDebugLoc()));
5812 // If this argument is live outside of the entry block, insert a copy from
5813 // whereever we got it to the vreg that other BB's will reference it as.
5814 SDL->CopyToExportRegsIfNeeded(AI);
5819 // Finally, if the target has anything special to do, allow it to do so.
5820 // FIXME: this should insert code into the DAG!
5821 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5824 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5825 /// ensure constants are generated when needed. Remember the virtual registers
5826 /// that need to be added to the Machine PHI nodes as input. We cannot just
5827 /// directly add them, because expansion might result in multiple MBB's for one
5828 /// BB. As such, the start of the BB might correspond to a different MBB than
5832 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5833 TerminatorInst *TI = LLVMBB->getTerminator();
5835 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5837 // Check successor nodes' PHI nodes that expect a constant to be available
5839 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5840 BasicBlock *SuccBB = TI->getSuccessor(succ);
5841 if (!isa<PHINode>(SuccBB->begin())) continue;
5842 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5844 // If this terminator has multiple identical successors (common for
5845 // switches), only handle each succ once.
5846 if (!SuccsHandled.insert(SuccMBB)) continue;
5848 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5851 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5852 // nodes and Machine PHI nodes, but the incoming operands have not been
5854 for (BasicBlock::iterator I = SuccBB->begin();
5855 (PN = dyn_cast<PHINode>(I)); ++I) {
5856 // Ignore dead phi's.
5857 if (PN->use_empty()) continue;
5860 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5862 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5863 unsigned &RegOut = SDL->ConstantsOut[C];
5865 RegOut = FuncInfo->CreateRegForValue(C);
5866 SDL->CopyValueToVirtualRegister(C, RegOut);
5870 Reg = FuncInfo->ValueMap[PHIOp];
5872 assert(isa<AllocaInst>(PHIOp) &&
5873 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5874 "Didn't codegen value into a register!??");
5875 Reg = FuncInfo->CreateRegForValue(PHIOp);
5876 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5880 // Remember that this register needs to added to the machine PHI node as
5881 // the input for this MBB.
5882 SmallVector<MVT, 4> ValueVTs;
5883 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5884 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5885 MVT VT = ValueVTs[vti];
5886 unsigned NumRegisters = TLI.getNumRegisters(VT);
5887 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5888 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5889 Reg += NumRegisters;
5893 SDL->ConstantsOut.clear();
5896 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5897 /// supports legal types, and it emits MachineInstrs directly instead of
5898 /// creating SelectionDAG nodes.
5901 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5903 TerminatorInst *TI = LLVMBB->getTerminator();
5905 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5906 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5908 // Check successor nodes' PHI nodes that expect a constant to be available
5910 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5911 BasicBlock *SuccBB = TI->getSuccessor(succ);
5912 if (!isa<PHINode>(SuccBB->begin())) continue;
5913 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5915 // If this terminator has multiple identical successors (common for
5916 // switches), only handle each succ once.
5917 if (!SuccsHandled.insert(SuccMBB)) continue;
5919 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5922 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5923 // nodes and Machine PHI nodes, but the incoming operands have not been
5925 for (BasicBlock::iterator I = SuccBB->begin();
5926 (PN = dyn_cast<PHINode>(I)); ++I) {
5927 // Ignore dead phi's.
5928 if (PN->use_empty()) continue;
5930 // Only handle legal types. Two interesting things to note here. First,
5931 // by bailing out early, we may leave behind some dead instructions,
5932 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5933 // own moves. Second, this check is necessary becuase FastISel doesn't
5934 // use CreateRegForValue to create registers, so it always creates
5935 // exactly one register for each non-void instruction.
5936 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5937 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5940 VT = TLI.getTypeToTransformTo(VT);
5942 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5947 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5949 unsigned Reg = F->getRegForValue(PHIOp);
5951 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5954 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));