1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Base case: we can get an MVT for this LLVM IR type.
139 ValueVTs.push_back(TLI.getValueType(Ty));
141 Offsets->push_back(StartingOffset);
145 /// RegsForValue - This struct represents the registers (physical or virtual)
146 /// that a particular set of values is assigned, and the type information about
147 /// the value. The most common situation is to represent one value at a time,
148 /// but struct or array values are handled element-wise as multiple values.
149 /// The splitting of aggregates is performed recursively, so that we never
150 /// have aggregate-typed registers. The values at this point do not necessarily
151 /// have legal types, so each value may require one or more registers of some
154 struct VISIBILITY_HIDDEN RegsForValue {
155 /// TLI - The TargetLowering object.
157 const TargetLowering *TLI;
159 /// ValueVTs - The value types of the values, which may not be legal, and
160 /// may need be promoted or synthesized from one or more registers.
162 SmallVector<MVT, 4> ValueVTs;
164 /// RegVTs - The value types of the registers. This is the same size as
165 /// ValueVTs and it records, for each value, what the type of the assigned
166 /// register or registers are. (Individual values are never synthesized
167 /// from more than one type of register.)
169 /// With virtual registers, the contents of RegVTs is redundant with TLI's
170 /// getRegisterType member function, however when with physical registers
171 /// it is necessary to have a separate record of the types.
173 SmallVector<MVT, 4> RegVTs;
175 /// Regs - This list holds the registers assigned to the values.
176 /// Each legal or promoted value requires one register, and each
177 /// expanded value requires multiple registers.
179 SmallVector<unsigned, 4> Regs;
181 RegsForValue() : TLI(0) {}
183 RegsForValue(const TargetLowering &tli,
184 const SmallVector<unsigned, 4> ®s,
185 MVT regvt, MVT valuevt)
186 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> ®s,
189 const SmallVector<MVT, 4> ®vts,
190 const SmallVector<MVT, 4> &valuevts)
191 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
192 RegsForValue(const TargetLowering &tli,
193 unsigned Reg, const Type *Ty) : TLI(&tli) {
194 ComputeValueVTs(tli, Ty, ValueVTs);
196 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
197 MVT ValueVT = ValueVTs[Value];
198 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
199 MVT RegisterVT = TLI->getRegisterType(ValueVT);
200 for (unsigned i = 0; i != NumRegs; ++i)
201 Regs.push_back(Reg + i);
202 RegVTs.push_back(RegisterVT);
207 /// append - Add the specified values to this one.
208 void append(const RegsForValue &RHS) {
210 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
211 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
212 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
216 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
217 /// this value and returns the result as a ValueVTs value. This uses
218 /// Chain/Flag as the input and updates them for the output Chain/Flag.
219 /// If the Flag pointer is NULL, no flag is used.
220 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
221 SDValue &Chain, SDValue *Flag) const;
223 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
224 /// specified value into the registers specified by this object. This uses
225 /// Chain/Flag as the input and updates them for the output Chain/Flag.
226 /// If the Flag pointer is NULL, no flag is used.
227 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
228 SDValue &Chain, SDValue *Flag) const;
230 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
231 /// operand list. This adds the code marker, matching input operand index
232 /// (if applicable), and includes the number of values added into it.
233 void AddInlineAsmOperands(unsigned Code,
234 bool HasMatching, unsigned MatchingIdx,
235 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
239 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
240 /// PHI nodes or outside of the basic block that defines it, or used by a
241 /// switch or atomic instruction, which may expand to multiple basic blocks.
242 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
243 if (isa<PHINode>(I)) return true;
244 BasicBlock *BB = I->getParent();
245 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
246 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
251 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252 /// entry block, return true. This includes arguments used by switches, since
253 /// the switch may expand into multiple basic blocks.
254 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
260 return A->use_empty();
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
269 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
273 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
275 bool EnableFastISel) {
278 RegInfo = &MF->getRegInfo();
280 // Create a vreg for each argument register that is not dead and is used
281 // outside of the entry block for the function.
282 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
284 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
285 InitializeRegForValue(AI);
287 // Initialize the mapping of values to registers. This is only set up for
288 // instruction values that are used outside of the block that defines
290 Function::iterator BB = Fn->begin(), EB = Fn->end();
291 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
292 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
293 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
294 const Type *Ty = AI->getAllocatedType();
295 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
297 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
300 TySize *= CUI->getZExtValue(); // Get total allocated size.
301 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
302 StaticAllocaMap[AI] =
303 MF->getFrameInfo()->CreateStackObject(TySize, Align);
306 for (; BB != EB; ++BB)
307 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
308 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
309 if (!isa<AllocaInst>(I) ||
310 !StaticAllocaMap.count(cast<AllocaInst>(I)))
311 InitializeRegForValue(I);
313 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
314 // also creates the initial PHI MachineInstrs, though none of the input
315 // operands are populated.
316 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
317 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
321 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
325 for (BasicBlock::iterator
326 I = BB->begin(), E = BB->end(); I != E; ++I) {
327 if (CallInst *CI = dyn_cast<CallInst>(I)) {
328 if (Function *F = CI->getCalledFunction()) {
329 switch (F->getIntrinsicID()) {
331 case Intrinsic::dbg_stoppoint: {
332 DwarfWriter *DW = DAG.getDwarfWriter();
333 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
335 if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
336 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
338 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
340 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
343 DL = DebugLoc::get(idx);
348 case Intrinsic::dbg_func_start: {
349 DwarfWriter *DW = DAG.getDwarfWriter();
351 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
352 Value *SP = FSI->getSubprogram();
354 if (DW->ValidDebugInfo(SP, false)) {
355 DISubprogram Subprogram(cast<GlobalVariable>(SP));
356 DICompileUnit CU(Subprogram.getCompileUnit());
358 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
360 unsigned Line = Subprogram.getLineNumber();
361 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
371 PN = dyn_cast<PHINode>(I);
372 if (!PN || PN->use_empty()) continue;
374 unsigned PHIReg = ValueMap[PN];
375 assert(PHIReg && "PHI node does not have an assigned virtual register!");
377 SmallVector<MVT, 4> ValueVTs;
378 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
379 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
380 MVT VT = ValueVTs[vti];
381 unsigned NumRegisters = TLI.getNumRegisters(VT);
382 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
383 for (unsigned i = 0; i != NumRegisters; ++i)
384 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
385 PHIReg += NumRegisters;
391 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
392 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
395 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
396 /// the correctly promoted or expanded types. Assign these registers
397 /// consecutive vreg numbers and return the first assigned number.
399 /// In the case that the given value has struct or array type, this function
400 /// will assign registers for each member or element.
402 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
403 SmallVector<MVT, 4> ValueVTs;
404 ComputeValueVTs(TLI, V->getType(), ValueVTs);
406 unsigned FirstReg = 0;
407 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
408 MVT ValueVT = ValueVTs[Value];
409 MVT RegisterVT = TLI.getRegisterType(ValueVT);
411 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
412 for (unsigned i = 0; i != NumRegs; ++i) {
413 unsigned R = MakeReg(RegisterVT);
414 if (!FirstReg) FirstReg = R;
420 /// getCopyFromParts - Create a value that contains the specified legal parts
421 /// combined into the value they represent. If the parts combine to a type
422 /// larger then ValueVT then AssertOp can be used to specify whether the extra
423 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
424 /// (ISD::AssertSext).
425 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
426 const SDValue *Parts,
427 unsigned NumParts, MVT PartVT, MVT ValueVT,
428 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
429 assert(NumParts > 0 && "No parts to assemble!");
430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
431 SDValue Val = Parts[0];
434 // Assemble the value from multiple parts.
435 if (!ValueVT.isVector()) {
436 unsigned PartBits = PartVT.getSizeInBits();
437 unsigned ValueBits = ValueVT.getSizeInBits();
439 // Assemble the power of 2 part.
440 unsigned RoundParts = NumParts & (NumParts - 1) ?
441 1 << Log2_32(NumParts) : NumParts;
442 unsigned RoundBits = PartBits * RoundParts;
443 MVT RoundVT = RoundBits == ValueBits ?
444 ValueVT : MVT::getIntegerVT(RoundBits);
447 MVT HalfVT = ValueVT.isInteger() ?
448 MVT::getIntegerVT(RoundBits/2) :
449 MVT::getFloatingPointVT(RoundBits/2);
451 if (RoundParts > 2) {
452 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
453 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
456 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
457 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
459 if (TLI.isBigEndian())
461 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
463 if (RoundParts < NumParts) {
464 // Assemble the trailing non-power-of-2 part.
465 unsigned OddParts = NumParts - RoundParts;
466 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
467 Hi = getCopyFromParts(DAG, dl,
468 Parts+RoundParts, OddParts, PartVT, OddVT);
470 // Combine the round and odd parts.
472 if (TLI.isBigEndian())
474 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
475 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
476 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
477 DAG.getConstant(Lo.getValueType().getSizeInBits(),
478 TLI.getPointerTy()));
479 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
480 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
483 // Handle a multi-element vector.
484 MVT IntermediateVT, RegisterVT;
485 unsigned NumIntermediates;
487 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
489 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
490 NumParts = NumRegs; // Silence a compiler warning.
491 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
492 assert(RegisterVT == Parts[0].getValueType() &&
493 "Part type doesn't match part!");
495 // Assemble the parts into intermediate operands.
496 SmallVector<SDValue, 8> Ops(NumIntermediates);
497 if (NumIntermediates == NumParts) {
498 // If the register was not expanded, truncate or copy the value,
500 for (unsigned i = 0; i != NumParts; ++i)
501 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
502 PartVT, IntermediateVT);
503 } else if (NumParts > 0) {
504 // If the intermediate type was expanded, build the intermediate operands
506 assert(NumParts % NumIntermediates == 0 &&
507 "Must expand into a divisible number of parts!");
508 unsigned Factor = NumParts / NumIntermediates;
509 for (unsigned i = 0; i != NumIntermediates; ++i)
510 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
511 PartVT, IntermediateVT);
514 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
516 Val = DAG.getNode(IntermediateVT.isVector() ?
517 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
518 ValueVT, &Ops[0], NumIntermediates);
522 // There is now one part, held in Val. Correct it to match ValueVT.
523 PartVT = Val.getValueType();
525 if (PartVT == ValueVT)
528 if (PartVT.isVector()) {
529 assert(ValueVT.isVector() && "Unknown vector conversion!");
530 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
533 if (ValueVT.isVector()) {
534 assert(ValueVT.getVectorElementType() == PartVT &&
535 ValueVT.getVectorNumElements() == 1 &&
536 "Only trivial scalar-to-vector conversions should get here!");
537 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
540 if (PartVT.isInteger() &&
541 ValueVT.isInteger()) {
542 if (ValueVT.bitsLT(PartVT)) {
543 // For a truncate, see if we have any information to
544 // indicate whether the truncated bits will always be
545 // zero or sign-extension.
546 if (AssertOp != ISD::DELETED_NODE)
547 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
548 DAG.getValueType(ValueVT));
549 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
551 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
555 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
556 if (ValueVT.bitsLT(Val.getValueType()))
557 // FP_ROUND's are always exact here.
558 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
559 DAG.getIntPtrConstant(1));
560 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
563 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
564 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
566 assert(0 && "Unknown mismatch!");
570 /// getCopyToParts - Create a series of nodes that contain the specified value
571 /// split into legal parts. If the parts contain more bits than Val, then, for
572 /// integers, ExtendKind can be used to specify how to generate the extra bits.
573 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
574 SDValue *Parts, unsigned NumParts, MVT PartVT,
575 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
576 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
577 MVT PtrVT = TLI.getPointerTy();
578 MVT ValueVT = Val.getValueType();
579 unsigned PartBits = PartVT.getSizeInBits();
580 unsigned OrigNumParts = NumParts;
581 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
586 if (!ValueVT.isVector()) {
587 if (PartVT == ValueVT) {
588 assert(NumParts == 1 && "No-op copy with multiple parts!");
593 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
594 // If the parts cover more bits than the value has, promote the value.
595 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
596 assert(NumParts == 1 && "Do not know what to promote to!");
597 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
598 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
599 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
600 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
602 assert(0 && "Unknown mismatch!");
604 } else if (PartBits == ValueVT.getSizeInBits()) {
605 // Different types of the same size.
606 assert(NumParts == 1 && PartVT != ValueVT);
607 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
608 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
609 // If the parts cover less bits than value has, truncate the value.
610 if (PartVT.isInteger() && ValueVT.isInteger()) {
611 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
612 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
614 assert(0 && "Unknown mismatch!");
618 // The value may have changed - recompute ValueVT.
619 ValueVT = Val.getValueType();
620 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
621 "Failed to tile the value with PartVT!");
624 assert(PartVT == ValueVT && "Type conversion failed!");
629 // Expand the value into multiple parts.
630 if (NumParts & (NumParts - 1)) {
631 // The number of parts is not a power of 2. Split off and copy the tail.
632 assert(PartVT.isInteger() && ValueVT.isInteger() &&
633 "Do not know what to expand to!");
634 unsigned RoundParts = 1 << Log2_32(NumParts);
635 unsigned RoundBits = RoundParts * PartBits;
636 unsigned OddParts = NumParts - RoundParts;
637 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
638 DAG.getConstant(RoundBits,
639 TLI.getPointerTy()));
640 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
641 if (TLI.isBigEndian())
642 // The odd parts were reversed by getCopyToParts - unreverse them.
643 std::reverse(Parts + RoundParts, Parts + NumParts);
644 NumParts = RoundParts;
645 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
646 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
649 // The number of parts is a power of 2. Repeatedly bisect the value using
651 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
652 MVT::getIntegerVT(ValueVT.getSizeInBits()),
654 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
655 for (unsigned i = 0; i < NumParts; i += StepSize) {
656 unsigned ThisBits = StepSize * PartBits / 2;
657 MVT ThisVT = MVT::getIntegerVT (ThisBits);
658 SDValue &Part0 = Parts[i];
659 SDValue &Part1 = Parts[i+StepSize/2];
661 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
663 DAG.getConstant(1, PtrVT));
664 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
666 DAG.getConstant(0, PtrVT));
668 if (ThisBits == PartBits && ThisVT != PartVT) {
669 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
671 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
677 if (TLI.isBigEndian())
678 std::reverse(Parts, Parts + OrigNumParts);
685 if (PartVT != ValueVT) {
686 if (PartVT.isVector()) {
687 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
689 assert(ValueVT.getVectorElementType() == PartVT &&
690 ValueVT.getVectorNumElements() == 1 &&
691 "Only trivial vector-to-scalar conversions should get here!");
692 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
694 DAG.getConstant(0, PtrVT));
702 // Handle a multi-element vector.
703 MVT IntermediateVT, RegisterVT;
704 unsigned NumIntermediates;
705 unsigned NumRegs = TLI
706 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
708 unsigned NumElements = ValueVT.getVectorNumElements();
710 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
711 NumParts = NumRegs; // Silence a compiler warning.
712 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
714 // Split the vector into intermediate operands.
715 SmallVector<SDValue, 8> Ops(NumIntermediates);
716 for (unsigned i = 0; i != NumIntermediates; ++i)
717 if (IntermediateVT.isVector())
718 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
720 DAG.getConstant(i * (NumElements / NumIntermediates),
723 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
725 DAG.getConstant(i, PtrVT));
727 // Split the intermediate operands into legal parts.
728 if (NumParts == NumIntermediates) {
729 // If the register was not expanded, promote or copy the value,
731 for (unsigned i = 0; i != NumParts; ++i)
732 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
733 } else if (NumParts > 0) {
734 // If the intermediate type was expanded, split each the value into
736 assert(NumParts % NumIntermediates == 0 &&
737 "Must expand into a divisible number of parts!");
738 unsigned Factor = NumParts / NumIntermediates;
739 for (unsigned i = 0; i != NumIntermediates; ++i)
740 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
745 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
748 TD = DAG.getTarget().getTargetData();
751 /// clear - Clear out the curret SelectionDAG and the associated
752 /// state and prepare this SelectionDAGLowering object to be used
753 /// for a new block. This doesn't clear out information about
754 /// additional blocks that are needed to complete switch lowering
755 /// or PHI node updating; that information is cleared out as it is
757 void SelectionDAGLowering::clear() {
759 PendingLoads.clear();
760 PendingExports.clear();
762 CurDebugLoc = DebugLoc::getUnknownLoc();
765 /// getRoot - Return the current virtual root of the Selection DAG,
766 /// flushing any PendingLoad items. This must be done before emitting
767 /// a store or any other node that may need to be ordered after any
768 /// prior load instructions.
770 SDValue SelectionDAGLowering::getRoot() {
771 if (PendingLoads.empty())
772 return DAG.getRoot();
774 if (PendingLoads.size() == 1) {
775 SDValue Root = PendingLoads[0];
777 PendingLoads.clear();
781 // Otherwise, we have to make a token factor node.
782 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
783 &PendingLoads[0], PendingLoads.size());
784 PendingLoads.clear();
789 /// getControlRoot - Similar to getRoot, but instead of flushing all the
790 /// PendingLoad items, flush all the PendingExports items. It is necessary
791 /// to do this before emitting a terminator instruction.
793 SDValue SelectionDAGLowering::getControlRoot() {
794 SDValue Root = DAG.getRoot();
796 if (PendingExports.empty())
799 // Turn all of the CopyToReg chains into one factored node.
800 if (Root.getOpcode() != ISD::EntryToken) {
801 unsigned i = 0, e = PendingExports.size();
802 for (; i != e; ++i) {
803 assert(PendingExports[i].getNode()->getNumOperands() > 1);
804 if (PendingExports[i].getNode()->getOperand(0) == Root)
805 break; // Don't add the root if we already indirectly depend on it.
809 PendingExports.push_back(Root);
812 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
814 PendingExports.size());
815 PendingExports.clear();
820 void SelectionDAGLowering::visit(Instruction &I) {
821 visit(I.getOpcode(), I);
824 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
825 // Note: this doesn't use InstVisitor, because it has to work with
826 // ConstantExpr's in addition to instructions.
828 default: assert(0 && "Unknown instruction type encountered!");
830 // Build the switch statement using the Instruction.def file.
831 #define HANDLE_INST(NUM, OPCODE, CLASS) \
832 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
833 #include "llvm/Instruction.def"
837 void SelectionDAGLowering::visitAdd(User &I) {
838 if (I.getType()->isFPOrFPVector())
839 visitBinary(I, ISD::FADD);
841 visitBinary(I, ISD::ADD);
844 void SelectionDAGLowering::visitMul(User &I) {
845 if (I.getType()->isFPOrFPVector())
846 visitBinary(I, ISD::FMUL);
848 visitBinary(I, ISD::MUL);
851 SDValue SelectionDAGLowering::getValue(const Value *V) {
852 SDValue &N = NodeMap[V];
853 if (N.getNode()) return N;
855 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
856 MVT VT = TLI.getValueType(V->getType(), true);
858 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
859 return N = DAG.getConstant(*CI, VT);
861 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
862 return N = DAG.getGlobalAddress(GV, VT);
864 if (isa<ConstantPointerNull>(C))
865 return N = DAG.getConstant(0, TLI.getPointerTy());
867 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
868 return N = DAG.getConstantFP(*CFP, VT);
870 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
871 !V->getType()->isAggregateType())
872 return N = DAG.getUNDEF(VT);
874 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
875 visit(CE->getOpcode(), *CE);
876 SDValue N1 = NodeMap[V];
877 assert(N1.getNode() && "visit didn't populate the ValueMap!");
881 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
882 SmallVector<SDValue, 4> Constants;
883 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
885 SDNode *Val = getValue(*OI).getNode();
886 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
887 Constants.push_back(SDValue(Val, i));
889 return DAG.getMergeValues(&Constants[0], Constants.size(),
893 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
894 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
895 "Unknown struct or array constant!");
897 SmallVector<MVT, 4> ValueVTs;
898 ComputeValueVTs(TLI, C->getType(), ValueVTs);
899 unsigned NumElts = ValueVTs.size();
901 return SDValue(); // empty struct
902 SmallVector<SDValue, 4> Constants(NumElts);
903 for (unsigned i = 0; i != NumElts; ++i) {
904 MVT EltVT = ValueVTs[i];
905 if (isa<UndefValue>(C))
906 Constants[i] = DAG.getUNDEF(EltVT);
907 else if (EltVT.isFloatingPoint())
908 Constants[i] = DAG.getConstantFP(0, EltVT);
910 Constants[i] = DAG.getConstant(0, EltVT);
912 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
915 const VectorType *VecTy = cast<VectorType>(V->getType());
916 unsigned NumElements = VecTy->getNumElements();
918 // Now that we know the number and type of the elements, get that number of
919 // elements into the Ops array based on what kind of constant it is.
920 SmallVector<SDValue, 16> Ops;
921 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
922 for (unsigned i = 0; i != NumElements; ++i)
923 Ops.push_back(getValue(CP->getOperand(i)));
925 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
926 "Unknown vector constant!");
927 MVT EltVT = TLI.getValueType(VecTy->getElementType());
930 if (isa<UndefValue>(C))
931 Op = DAG.getUNDEF(EltVT);
932 else if (EltVT.isFloatingPoint())
933 Op = DAG.getConstantFP(0, EltVT);
935 Op = DAG.getConstant(0, EltVT);
936 Ops.assign(NumElements, Op);
939 // Create a BUILD_VECTOR node.
940 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
941 VT, &Ops[0], Ops.size());
944 // If this is a static alloca, generate it as the frameindex instead of
946 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
947 DenseMap<const AllocaInst*, int>::iterator SI =
948 FuncInfo.StaticAllocaMap.find(AI);
949 if (SI != FuncInfo.StaticAllocaMap.end())
950 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
953 unsigned InReg = FuncInfo.ValueMap[V];
954 assert(InReg && "Value not in map!");
956 RegsForValue RFV(TLI, InReg, V->getType());
957 SDValue Chain = DAG.getEntryNode();
958 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
962 void SelectionDAGLowering::visitRet(ReturnInst &I) {
963 if (I.getNumOperands() == 0) {
964 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
965 MVT::Other, getControlRoot()));
969 SmallVector<SDValue, 8> NewValues;
970 NewValues.push_back(getControlRoot());
971 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
972 SmallVector<MVT, 4> ValueVTs;
973 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
974 unsigned NumValues = ValueVTs.size();
975 if (NumValues == 0) continue;
977 SDValue RetOp = getValue(I.getOperand(i));
978 for (unsigned j = 0, f = NumValues; j != f; ++j) {
979 MVT VT = ValueVTs[j];
981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
983 const Function *F = I.getParent()->getParent();
984 if (F->paramHasAttr(0, Attribute::SExt))
985 ExtendKind = ISD::SIGN_EXTEND;
986 else if (F->paramHasAttr(0, Attribute::ZExt))
987 ExtendKind = ISD::ZERO_EXTEND;
989 // FIXME: C calling convention requires the return type to be promoted to
990 // at least 32-bit. But this is not necessary for non-C calling
991 // conventions. The frontend should mark functions whose return values
992 // require promoting with signext or zeroext attributes.
993 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
994 MVT MinVT = TLI.getRegisterType(MVT::i32);
995 if (VT.bitsLT(MinVT))
999 unsigned NumParts = TLI.getNumRegisters(VT);
1000 MVT PartVT = TLI.getRegisterType(VT);
1001 SmallVector<SDValue, 4> Parts(NumParts);
1002 getCopyToParts(DAG, getCurDebugLoc(),
1003 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1004 &Parts[0], NumParts, PartVT, ExtendKind);
1006 // 'inreg' on function refers to return value
1007 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1008 if (F->paramHasAttr(0, Attribute::InReg))
1010 for (unsigned i = 0; i < NumParts; ++i) {
1011 NewValues.push_back(Parts[i]);
1012 NewValues.push_back(DAG.getArgFlags(Flags));
1016 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1017 &NewValues[0], NewValues.size()));
1020 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1021 /// the current basic block, add it to ValueMap now so that we'll get a
1023 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1024 // No need to export constants.
1025 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1027 // Already exported?
1028 if (FuncInfo.isExportedInst(V)) return;
1030 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1031 CopyValueToVirtualRegister(V, Reg);
1034 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1035 const BasicBlock *FromBB) {
1036 // The operands of the setcc have to be in this block. We don't know
1037 // how to export them from some other block.
1038 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1039 // Can export from current BB.
1040 if (VI->getParent() == FromBB)
1043 // Is already exported, noop.
1044 return FuncInfo.isExportedInst(V);
1047 // If this is an argument, we can export it if the BB is the entry block or
1048 // if it is already exported.
1049 if (isa<Argument>(V)) {
1050 if (FromBB == &FromBB->getParent()->getEntryBlock())
1053 // Otherwise, can only export this if it is already exported.
1054 return FuncInfo.isExportedInst(V);
1057 // Otherwise, constants can always be exported.
1061 static bool InBlock(const Value *V, const BasicBlock *BB) {
1062 if (const Instruction *I = dyn_cast<Instruction>(V))
1063 return I->getParent() == BB;
1067 /// getFCmpCondCode - Return the ISD condition code corresponding to
1068 /// the given LLVM IR floating-point condition code. This includes
1069 /// consideration of global floating-point math flags.
1071 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1072 ISD::CondCode FPC, FOC;
1074 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1075 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1076 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1077 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1078 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1079 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1080 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1081 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1082 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1083 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1084 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1085 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1086 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1087 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1088 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1089 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1091 assert(0 && "Invalid FCmp predicate opcode!");
1092 FOC = FPC = ISD::SETFALSE;
1095 if (FiniteOnlyFPMath())
1101 /// getICmpCondCode - Return the ISD condition code corresponding to
1102 /// the given LLVM IR integer condition code.
1104 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1106 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1107 case ICmpInst::ICMP_NE: return ISD::SETNE;
1108 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1109 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1110 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1111 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1112 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1113 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1114 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1115 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1117 assert(0 && "Invalid ICmp predicate opcode!");
1122 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1123 /// This function emits a branch and is used at the leaves of an OR or an
1124 /// AND operator tree.
1127 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1128 MachineBasicBlock *TBB,
1129 MachineBasicBlock *FBB,
1130 MachineBasicBlock *CurBB) {
1131 const BasicBlock *BB = CurBB->getBasicBlock();
1133 // If the leaf of the tree is a comparison, merge the condition into
1135 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1136 // The operands of the cmp have to be in this block. We don't know
1137 // how to export them from some other block. If this is the first block
1138 // of the sequence, no exporting is needed.
1139 if (CurBB == CurMBB ||
1140 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1141 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1142 ISD::CondCode Condition;
1143 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1144 Condition = getICmpCondCode(IC->getPredicate());
1145 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1146 Condition = getFCmpCondCode(FC->getPredicate());
1148 Condition = ISD::SETEQ; // silence warning.
1149 assert(0 && "Unknown compare instruction");
1152 CaseBlock CB(Condition, BOp->getOperand(0),
1153 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1154 SwitchCases.push_back(CB);
1159 // Create a CaseBlock record representing this branch.
1160 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1161 NULL, TBB, FBB, CurBB);
1162 SwitchCases.push_back(CB);
1165 /// FindMergedConditions - If Cond is an expression like
1166 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1167 MachineBasicBlock *TBB,
1168 MachineBasicBlock *FBB,
1169 MachineBasicBlock *CurBB,
1171 // If this node is not part of the or/and tree, emit it as a branch.
1172 Instruction *BOp = dyn_cast<Instruction>(Cond);
1173 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1174 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1175 BOp->getParent() != CurBB->getBasicBlock() ||
1176 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1177 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1178 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1182 // Create TmpBB after CurBB.
1183 MachineFunction::iterator BBI = CurBB;
1184 MachineFunction &MF = DAG.getMachineFunction();
1185 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1186 CurBB->getParent()->insert(++BBI, TmpBB);
1188 if (Opc == Instruction::Or) {
1189 // Codegen X | Y as:
1197 // Emit the LHS condition.
1198 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1200 // Emit the RHS condition into TmpBB.
1201 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1203 assert(Opc == Instruction::And && "Unknown merge op!");
1204 // Codegen X & Y as:
1211 // This requires creation of TmpBB after CurBB.
1213 // Emit the LHS condition.
1214 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1216 // Emit the RHS condition into TmpBB.
1217 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1221 /// If the set of cases should be emitted as a series of branches, return true.
1222 /// If we should emit this as a bunch of and/or'd together conditions, return
1225 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1226 if (Cases.size() != 2) return true;
1228 // If this is two comparisons of the same values or'd or and'd together, they
1229 // will get folded into a single comparison, so don't emit two blocks.
1230 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1231 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1232 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1233 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1240 void SelectionDAGLowering::visitBr(BranchInst &I) {
1241 // Update machine-CFG edges.
1242 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1244 // Figure out which block is immediately after the current one.
1245 MachineBasicBlock *NextBlock = 0;
1246 MachineFunction::iterator BBI = CurMBB;
1247 if (++BBI != CurMBB->getParent()->end())
1250 if (I.isUnconditional()) {
1251 // Update machine-CFG edges.
1252 CurMBB->addSuccessor(Succ0MBB);
1254 // If this is not a fall-through branch, emit the branch.
1255 if (Succ0MBB != NextBlock)
1256 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1257 MVT::Other, getControlRoot(),
1258 DAG.getBasicBlock(Succ0MBB)));
1262 // If this condition is one of the special cases we handle, do special stuff
1264 Value *CondVal = I.getCondition();
1265 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1267 // If this is a series of conditions that are or'd or and'd together, emit
1268 // this as a sequence of branches instead of setcc's with and/or operations.
1269 // For example, instead of something like:
1282 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1283 if (BOp->hasOneUse() &&
1284 (BOp->getOpcode() == Instruction::And ||
1285 BOp->getOpcode() == Instruction::Or)) {
1286 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1287 // If the compares in later blocks need to use values not currently
1288 // exported from this block, export them now. This block should always
1289 // be the first entry.
1290 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1292 // Allow some cases to be rejected.
1293 if (ShouldEmitAsBranches(SwitchCases)) {
1294 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1295 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1296 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1299 // Emit the branch for this block.
1300 visitSwitchCase(SwitchCases[0]);
1301 SwitchCases.erase(SwitchCases.begin());
1305 // Okay, we decided not to do this, remove any inserted MBB's and clear
1307 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1308 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1310 SwitchCases.clear();
1314 // Create a CaseBlock record representing this branch.
1315 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1316 NULL, Succ0MBB, Succ1MBB, CurMBB);
1317 // Use visitSwitchCase to actually insert the fast branch sequence for this
1319 visitSwitchCase(CB);
1322 /// visitSwitchCase - Emits the necessary code to represent a single node in
1323 /// the binary search tree resulting from lowering a switch instruction.
1324 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1326 SDValue CondLHS = getValue(CB.CmpLHS);
1327 DebugLoc dl = getCurDebugLoc();
1329 // Build the setcc now.
1330 if (CB.CmpMHS == NULL) {
1331 // Fold "(X == true)" to X and "(X == false)" to !X to
1332 // handle common cases produced by branch lowering.
1333 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1335 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1336 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1337 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1339 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1341 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1343 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1344 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1346 SDValue CmpOp = getValue(CB.CmpMHS);
1347 MVT VT = CmpOp.getValueType();
1349 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1350 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1353 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1354 VT, CmpOp, DAG.getConstant(Low, VT));
1355 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1356 DAG.getConstant(High-Low, VT), ISD::SETULE);
1360 // Update successor info
1361 CurMBB->addSuccessor(CB.TrueBB);
1362 CurMBB->addSuccessor(CB.FalseBB);
1364 // Set NextBlock to be the MBB immediately after the current one, if any.
1365 // This is used to avoid emitting unnecessary branches to the next block.
1366 MachineBasicBlock *NextBlock = 0;
1367 MachineFunction::iterator BBI = CurMBB;
1368 if (++BBI != CurMBB->getParent()->end())
1371 // If the lhs block is the next block, invert the condition so that we can
1372 // fall through to the lhs instead of the rhs block.
1373 if (CB.TrueBB == NextBlock) {
1374 std::swap(CB.TrueBB, CB.FalseBB);
1375 SDValue True = DAG.getConstant(1, Cond.getValueType());
1376 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1378 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1379 MVT::Other, getControlRoot(), Cond,
1380 DAG.getBasicBlock(CB.TrueBB));
1382 // If the branch was constant folded, fix up the CFG.
1383 if (BrCond.getOpcode() == ISD::BR) {
1384 CurMBB->removeSuccessor(CB.FalseBB);
1385 DAG.setRoot(BrCond);
1387 // Otherwise, go ahead and insert the false branch.
1388 if (BrCond == getControlRoot())
1389 CurMBB->removeSuccessor(CB.TrueBB);
1391 if (CB.FalseBB == NextBlock)
1392 DAG.setRoot(BrCond);
1394 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1395 DAG.getBasicBlock(CB.FalseBB)));
1399 /// visitJumpTable - Emit JumpTable node in the current MBB
1400 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1401 // Emit the code for the jump table
1402 assert(JT.Reg != -1U && "Should lower JT Header first!");
1403 MVT PTy = TLI.getPointerTy();
1404 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1406 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1407 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1408 MVT::Other, Index.getValue(1),
1412 /// visitJumpTableHeader - This function emits necessary code to produce index
1413 /// in the JumpTable from switch case.
1414 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1415 JumpTableHeader &JTH) {
1416 // Subtract the lowest switch case value from the value being switched on and
1417 // conditional branch to default mbb if the result is greater than the
1418 // difference between smallest and largest cases.
1419 SDValue SwitchOp = getValue(JTH.SValue);
1420 MVT VT = SwitchOp.getValueType();
1421 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1422 DAG.getConstant(JTH.First, VT));
1424 // The SDNode we just created, which holds the value being switched on minus
1425 // the the smallest case value, needs to be copied to a virtual register so it
1426 // can be used as an index into the jump table in a subsequent basic block.
1427 // This value may be smaller or larger than the target's pointer type, and
1428 // therefore require extension or truncating.
1429 if (VT.bitsGT(TLI.getPointerTy()))
1430 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1431 TLI.getPointerTy(), SUB);
1433 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1434 TLI.getPointerTy(), SUB);
1436 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1437 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1438 JumpTableReg, SwitchOp);
1439 JT.Reg = JumpTableReg;
1441 // Emit the range check for the jump table, and branch to the default block
1442 // for the switch statement if the value being switched on exceeds the largest
1443 // case in the switch.
1444 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1445 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1446 DAG.getConstant(JTH.Last-JTH.First,VT),
1449 // Set NextBlock to be the MBB immediately after the current one, if any.
1450 // This is used to avoid emitting unnecessary branches to the next block.
1451 MachineBasicBlock *NextBlock = 0;
1452 MachineFunction::iterator BBI = CurMBB;
1453 if (++BBI != CurMBB->getParent()->end())
1456 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1457 MVT::Other, CopyTo, CMP,
1458 DAG.getBasicBlock(JT.Default));
1460 if (JT.MBB == NextBlock)
1461 DAG.setRoot(BrCond);
1463 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1464 DAG.getBasicBlock(JT.MBB)));
1467 /// visitBitTestHeader - This function emits necessary code to produce value
1468 /// suitable for "bit tests"
1469 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1470 // Subtract the minimum value
1471 SDValue SwitchOp = getValue(B.SValue);
1472 MVT VT = SwitchOp.getValueType();
1473 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1474 DAG.getConstant(B.First, VT));
1477 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1478 TLI.getSetCCResultType(SUB.getValueType()),
1479 SUB, DAG.getConstant(B.Range, VT),
1483 if (VT.bitsGT(TLI.getPointerTy()))
1484 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1485 TLI.getPointerTy(), SUB);
1487 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1488 TLI.getPointerTy(), SUB);
1490 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1491 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1494 // Set NextBlock to be the MBB immediately after the current one, if any.
1495 // This is used to avoid emitting unnecessary branches to the next block.
1496 MachineBasicBlock *NextBlock = 0;
1497 MachineFunction::iterator BBI = CurMBB;
1498 if (++BBI != CurMBB->getParent()->end())
1501 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1503 CurMBB->addSuccessor(B.Default);
1504 CurMBB->addSuccessor(MBB);
1506 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1507 MVT::Other, CopyTo, RangeCmp,
1508 DAG.getBasicBlock(B.Default));
1510 if (MBB == NextBlock)
1511 DAG.setRoot(BrRange);
1513 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1514 DAG.getBasicBlock(MBB)));
1517 /// visitBitTestCase - this function produces one "bit test"
1518 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1521 // Make desired shift
1522 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1523 TLI.getPointerTy());
1524 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1526 DAG.getConstant(1, TLI.getPointerTy()),
1529 // Emit bit tests and jumps
1530 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1531 TLI.getPointerTy(), SwitchVal,
1532 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1533 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1534 TLI.getSetCCResultType(AndOp.getValueType()),
1535 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1538 CurMBB->addSuccessor(B.TargetBB);
1539 CurMBB->addSuccessor(NextMBB);
1541 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1542 MVT::Other, getControlRoot(),
1543 AndCmp, DAG.getBasicBlock(B.TargetBB));
1545 // Set NextBlock to be the MBB immediately after the current one, if any.
1546 // This is used to avoid emitting unnecessary branches to the next block.
1547 MachineBasicBlock *NextBlock = 0;
1548 MachineFunction::iterator BBI = CurMBB;
1549 if (++BBI != CurMBB->getParent()->end())
1552 if (NextMBB == NextBlock)
1555 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1556 DAG.getBasicBlock(NextMBB)));
1559 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1560 // Retrieve successors.
1561 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1562 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1564 const Value *Callee(I.getCalledValue());
1565 if (isa<InlineAsm>(Callee))
1568 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1570 // If the value of the invoke is used outside of its defining block, make it
1571 // available as a virtual register.
1572 if (!I.use_empty()) {
1573 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1574 if (VMI != FuncInfo.ValueMap.end())
1575 CopyValueToVirtualRegister(&I, VMI->second);
1578 // Update successor info
1579 CurMBB->addSuccessor(Return);
1580 CurMBB->addSuccessor(LandingPad);
1582 // Drop into normal successor.
1583 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1584 MVT::Other, getControlRoot(),
1585 DAG.getBasicBlock(Return)));
1588 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1591 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1592 /// small case ranges).
1593 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1594 CaseRecVector& WorkList,
1596 MachineBasicBlock* Default) {
1597 Case& BackCase = *(CR.Range.second-1);
1599 // Size is the number of Cases represented by this range.
1600 size_t Size = CR.Range.second - CR.Range.first;
1604 // Get the MachineFunction which holds the current MBB. This is used when
1605 // inserting any additional MBBs necessary to represent the switch.
1606 MachineFunction *CurMF = CurMBB->getParent();
1608 // Figure out which block is immediately after the current one.
1609 MachineBasicBlock *NextBlock = 0;
1610 MachineFunction::iterator BBI = CR.CaseBB;
1612 if (++BBI != CurMBB->getParent()->end())
1615 // TODO: If any two of the cases has the same destination, and if one value
1616 // is the same as the other, but has one bit unset that the other has set,
1617 // use bit manipulation to do two compares at once. For example:
1618 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1620 // Rearrange the case blocks so that the last one falls through if possible.
1621 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1622 // The last case block won't fall through into 'NextBlock' if we emit the
1623 // branches in this order. See if rearranging a case value would help.
1624 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1625 if (I->BB == NextBlock) {
1626 std::swap(*I, BackCase);
1632 // Create a CaseBlock record representing a conditional branch to
1633 // the Case's target mbb if the value being switched on SV is equal
1635 MachineBasicBlock *CurBlock = CR.CaseBB;
1636 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1637 MachineBasicBlock *FallThrough;
1639 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1640 CurMF->insert(BBI, FallThrough);
1642 // Put SV in a virtual register to make it available from the new blocks.
1643 ExportFromCurrentBlock(SV);
1645 // If the last case doesn't match, go to the default block.
1646 FallThrough = Default;
1649 Value *RHS, *LHS, *MHS;
1651 if (I->High == I->Low) {
1652 // This is just small small case range :) containing exactly 1 case
1654 LHS = SV; RHS = I->High; MHS = NULL;
1657 LHS = I->Low; MHS = SV; RHS = I->High;
1659 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1661 // If emitting the first comparison, just call visitSwitchCase to emit the
1662 // code into the current block. Otherwise, push the CaseBlock onto the
1663 // vector to be later processed by SDISel, and insert the node's MBB
1664 // before the next MBB.
1665 if (CurBlock == CurMBB)
1666 visitSwitchCase(CB);
1668 SwitchCases.push_back(CB);
1670 CurBlock = FallThrough;
1676 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1677 return !DisableJumpTables &&
1678 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1679 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1682 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1683 APInt LastExt(Last), FirstExt(First);
1684 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1685 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1686 return (LastExt - FirstExt + 1ULL);
1689 /// handleJTSwitchCase - Emit jumptable for current switch case range
1690 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1691 CaseRecVector& WorkList,
1693 MachineBasicBlock* Default) {
1694 Case& FrontCase = *CR.Range.first;
1695 Case& BackCase = *(CR.Range.second-1);
1697 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1698 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1701 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1705 if (!areJTsAllowed(TLI) || TSize <= 3)
1708 APInt Range = ComputeRange(First, Last);
1709 double Density = (double)TSize / Range.roundToDouble();
1713 DEBUG(errs() << "Lowering jump table\n"
1714 << "First entry: " << First << ". Last entry: " << Last << '\n'
1715 << "Range: " << Range
1716 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1718 // Get the MachineFunction which holds the current MBB. This is used when
1719 // inserting any additional MBBs necessary to represent the switch.
1720 MachineFunction *CurMF = CurMBB->getParent();
1722 // Figure out which block is immediately after the current one.
1723 MachineBasicBlock *NextBlock = 0;
1724 MachineFunction::iterator BBI = CR.CaseBB;
1726 if (++BBI != CurMBB->getParent()->end())
1729 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1731 // Create a new basic block to hold the code for loading the address
1732 // of the jump table, and jumping to it. Update successor information;
1733 // we will either branch to the default case for the switch, or the jump
1735 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1736 CurMF->insert(BBI, JumpTableBB);
1737 CR.CaseBB->addSuccessor(Default);
1738 CR.CaseBB->addSuccessor(JumpTableBB);
1740 // Build a vector of destination BBs, corresponding to each target
1741 // of the jump table. If the value of the jump table slot corresponds to
1742 // a case statement, push the case's BB onto the vector, otherwise, push
1744 std::vector<MachineBasicBlock*> DestBBs;
1746 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1747 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1748 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1750 if (Low.sle(TEI) && TEI.sle(High)) {
1751 DestBBs.push_back(I->BB);
1755 DestBBs.push_back(Default);
1759 // Update successor info. Add one edge to each unique successor.
1760 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1761 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1762 E = DestBBs.end(); I != E; ++I) {
1763 if (!SuccsHandled[(*I)->getNumber()]) {
1764 SuccsHandled[(*I)->getNumber()] = true;
1765 JumpTableBB->addSuccessor(*I);
1769 // Create a jump table index for this jump table, or return an existing
1771 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1773 // Set the jump table information so that we can codegen it as a second
1774 // MachineBasicBlock
1775 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1776 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1777 if (CR.CaseBB == CurMBB)
1778 visitJumpTableHeader(JT, JTH);
1780 JTCases.push_back(JumpTableBlock(JTH, JT));
1785 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1787 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1788 CaseRecVector& WorkList,
1790 MachineBasicBlock* Default) {
1791 // Get the MachineFunction which holds the current MBB. This is used when
1792 // inserting any additional MBBs necessary to represent the switch.
1793 MachineFunction *CurMF = CurMBB->getParent();
1795 // Figure out which block is immediately after the current one.
1796 MachineBasicBlock *NextBlock = 0;
1797 MachineFunction::iterator BBI = CR.CaseBB;
1799 if (++BBI != CurMBB->getParent()->end())
1802 Case& FrontCase = *CR.Range.first;
1803 Case& BackCase = *(CR.Range.second-1);
1804 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1806 // Size is the number of Cases represented by this range.
1807 unsigned Size = CR.Range.second - CR.Range.first;
1809 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1810 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1812 CaseItr Pivot = CR.Range.first + Size/2;
1814 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1815 // (heuristically) allow us to emit JumpTable's later.
1817 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1821 size_t LSize = FrontCase.size();
1822 size_t RSize = TSize-LSize;
1823 DEBUG(errs() << "Selecting best pivot: \n"
1824 << "First: " << First << ", Last: " << Last <<'\n'
1825 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1826 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1828 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1829 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1830 APInt Range = ComputeRange(LEnd, RBegin);
1831 assert((Range - 2ULL).isNonNegative() &&
1832 "Invalid case distance");
1833 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1834 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1835 double Metric = Range.logBase2()*(LDensity+RDensity);
1836 // Should always split in some non-trivial place
1837 DEBUG(errs() <<"=>Step\n"
1838 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1839 << "LDensity: " << LDensity
1840 << ", RDensity: " << RDensity << '\n'
1841 << "Metric: " << Metric << '\n');
1842 if (FMetric < Metric) {
1845 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1851 if (areJTsAllowed(TLI)) {
1852 // If our case is dense we *really* should handle it earlier!
1853 assert((FMetric > 0) && "Should handle dense range earlier!");
1855 Pivot = CR.Range.first + Size/2;
1858 CaseRange LHSR(CR.Range.first, Pivot);
1859 CaseRange RHSR(Pivot, CR.Range.second);
1860 Constant *C = Pivot->Low;
1861 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1863 // We know that we branch to the LHS if the Value being switched on is
1864 // less than the Pivot value, C. We use this to optimize our binary
1865 // tree a bit, by recognizing that if SV is greater than or equal to the
1866 // LHS's Case Value, and that Case Value is exactly one less than the
1867 // Pivot's Value, then we can branch directly to the LHS's Target,
1868 // rather than creating a leaf node for it.
1869 if ((LHSR.second - LHSR.first) == 1 &&
1870 LHSR.first->High == CR.GE &&
1871 cast<ConstantInt>(C)->getValue() ==
1872 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1873 TrueBB = LHSR.first->BB;
1875 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1876 CurMF->insert(BBI, TrueBB);
1877 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1879 // Put SV in a virtual register to make it available from the new blocks.
1880 ExportFromCurrentBlock(SV);
1883 // Similar to the optimization above, if the Value being switched on is
1884 // known to be less than the Constant CR.LT, and the current Case Value
1885 // is CR.LT - 1, then we can branch directly to the target block for
1886 // the current Case Value, rather than emitting a RHS leaf node for it.
1887 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1888 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1889 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1890 FalseBB = RHSR.first->BB;
1892 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1893 CurMF->insert(BBI, FalseBB);
1894 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1896 // Put SV in a virtual register to make it available from the new blocks.
1897 ExportFromCurrentBlock(SV);
1900 // Create a CaseBlock record representing a conditional branch to
1901 // the LHS node if the value being switched on SV is less than C.
1902 // Otherwise, branch to LHS.
1903 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1905 if (CR.CaseBB == CurMBB)
1906 visitSwitchCase(CB);
1908 SwitchCases.push_back(CB);
1913 /// handleBitTestsSwitchCase - if current case range has few destination and
1914 /// range span less, than machine word bitwidth, encode case range into series
1915 /// of masks and emit bit tests with these masks.
1916 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1917 CaseRecVector& WorkList,
1919 MachineBasicBlock* Default){
1920 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1922 Case& FrontCase = *CR.Range.first;
1923 Case& BackCase = *(CR.Range.second-1);
1925 // Get the MachineFunction which holds the current MBB. This is used when
1926 // inserting any additional MBBs necessary to represent the switch.
1927 MachineFunction *CurMF = CurMBB->getParent();
1930 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1932 // Single case counts one, case range - two.
1933 numCmps += (I->Low == I->High ? 1 : 2);
1936 // Count unique destinations
1937 SmallSet<MachineBasicBlock*, 4> Dests;
1938 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1939 Dests.insert(I->BB);
1940 if (Dests.size() > 3)
1941 // Don't bother the code below, if there are too much unique destinations
1944 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1945 << "Total number of comparisons: " << numCmps << '\n');
1947 // Compute span of values.
1948 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1949 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1950 APInt cmpRange = maxValue - minValue;
1952 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1953 << "Low bound: " << minValue << '\n'
1954 << "High bound: " << maxValue << '\n');
1956 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1957 (!(Dests.size() == 1 && numCmps >= 3) &&
1958 !(Dests.size() == 2 && numCmps >= 5) &&
1959 !(Dests.size() >= 3 && numCmps >= 6)))
1962 DEBUG(errs() << "Emitting bit tests\n");
1963 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1965 // Optimize the case where all the case values fit in a
1966 // word without having to subtract minValue. In this case,
1967 // we can optimize away the subtraction.
1968 if (minValue.isNonNegative() &&
1969 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1970 cmpRange = maxValue;
1972 lowBound = minValue;
1975 CaseBitsVector CasesBits;
1976 unsigned i, count = 0;
1978 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1979 MachineBasicBlock* Dest = I->BB;
1980 for (i = 0; i < count; ++i)
1981 if (Dest == CasesBits[i].BB)
1985 assert((count < 3) && "Too much destinations to test!");
1986 CasesBits.push_back(CaseBits(0, Dest, 0));
1990 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1991 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1993 uint64_t lo = (lowValue - lowBound).getZExtValue();
1994 uint64_t hi = (highValue - lowBound).getZExtValue();
1996 for (uint64_t j = lo; j <= hi; j++) {
1997 CasesBits[i].Mask |= 1ULL << j;
1998 CasesBits[i].Bits++;
2002 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2006 // Figure out which block is immediately after the current one.
2007 MachineFunction::iterator BBI = CR.CaseBB;
2010 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2012 DEBUG(errs() << "Cases:\n");
2013 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2014 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2015 << ", Bits: " << CasesBits[i].Bits
2016 << ", BB: " << CasesBits[i].BB << '\n');
2018 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2019 CurMF->insert(BBI, CaseBB);
2020 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2024 // Put SV in a virtual register to make it available from the new blocks.
2025 ExportFromCurrentBlock(SV);
2028 BitTestBlock BTB(lowBound, cmpRange, SV,
2029 -1U, (CR.CaseBB == CurMBB),
2030 CR.CaseBB, Default, BTC);
2032 if (CR.CaseBB == CurMBB)
2033 visitBitTestHeader(BTB);
2035 BitTestCases.push_back(BTB);
2041 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2042 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2043 const SwitchInst& SI) {
2046 // Start with "simple" cases
2047 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2048 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2049 Cases.push_back(Case(SI.getSuccessorValue(i),
2050 SI.getSuccessorValue(i),
2053 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2055 // Merge case into clusters
2056 if (Cases.size() >= 2)
2057 // Must recompute end() each iteration because it may be
2058 // invalidated by erase if we hold on to it
2059 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2060 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2061 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2062 MachineBasicBlock* nextBB = J->BB;
2063 MachineBasicBlock* currentBB = I->BB;
2065 // If the two neighboring cases go to the same destination, merge them
2066 // into a single case.
2067 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2075 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2076 if (I->Low != I->High)
2077 // A range counts double, since it requires two compares.
2084 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2085 // Figure out which block is immediately after the current one.
2086 MachineBasicBlock *NextBlock = 0;
2087 MachineFunction::iterator BBI = CurMBB;
2089 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2091 // If there is only the default destination, branch to it if it is not the
2092 // next basic block. Otherwise, just fall through.
2093 if (SI.getNumOperands() == 2) {
2094 // Update machine-CFG edges.
2096 // If this is not a fall-through branch, emit the branch.
2097 CurMBB->addSuccessor(Default);
2098 if (Default != NextBlock)
2099 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2100 MVT::Other, getControlRoot(),
2101 DAG.getBasicBlock(Default)));
2105 // If there are any non-default case statements, create a vector of Cases
2106 // representing each one, and sort the vector so that we can efficiently
2107 // create a binary search tree from them.
2109 size_t numCmps = Clusterify(Cases, SI);
2110 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2111 << ". Total compares: " << numCmps << '\n');
2114 // Get the Value to be switched on and default basic blocks, which will be
2115 // inserted into CaseBlock records, representing basic blocks in the binary
2117 Value *SV = SI.getOperand(0);
2119 // Push the initial CaseRec onto the worklist
2120 CaseRecVector WorkList;
2121 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2123 while (!WorkList.empty()) {
2124 // Grab a record representing a case range to process off the worklist
2125 CaseRec CR = WorkList.back();
2126 WorkList.pop_back();
2128 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2131 // If the range has few cases (two or less) emit a series of specific
2133 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2136 // If the switch has more than 5 blocks, and at least 40% dense, and the
2137 // target supports indirect branches, then emit a jump table rather than
2138 // lowering the switch to a binary tree of conditional branches.
2139 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2142 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2143 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2144 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2149 void SelectionDAGLowering::visitSub(User &I) {
2150 // -0.0 - X --> fneg
2151 const Type *Ty = I.getType();
2152 if (isa<VectorType>(Ty)) {
2153 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2154 const VectorType *DestTy = cast<VectorType>(I.getType());
2155 const Type *ElTy = DestTy->getElementType();
2156 if (ElTy->isFloatingPoint()) {
2157 unsigned VL = DestTy->getNumElements();
2158 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2159 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2161 SDValue Op2 = getValue(I.getOperand(1));
2162 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2163 Op2.getValueType(), Op2));
2169 if (Ty->isFloatingPoint()) {
2170 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2171 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2172 SDValue Op2 = getValue(I.getOperand(1));
2173 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2174 Op2.getValueType(), Op2));
2179 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2182 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2183 SDValue Op1 = getValue(I.getOperand(0));
2184 SDValue Op2 = getValue(I.getOperand(1));
2186 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2187 Op1.getValueType(), Op1, Op2));
2190 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2191 SDValue Op1 = getValue(I.getOperand(0));
2192 SDValue Op2 = getValue(I.getOperand(1));
2193 if (!isa<VectorType>(I.getType()) &&
2194 Op2.getValueType() != TLI.getShiftAmountTy()) {
2195 // If the operand is smaller than the shift count type, promote it.
2196 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2197 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2198 TLI.getShiftAmountTy(), Op2);
2199 // If the operand is larger than the shift count type but the shift
2200 // count type has enough bits to represent any shift value, truncate
2201 // it now. This is a common case and it exposes the truncate to
2202 // optimization early.
2203 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2204 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2205 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2206 TLI.getShiftAmountTy(), Op2);
2207 // Otherwise we'll need to temporarily settle for some other
2208 // convenient type; type legalization will make adjustments as
2210 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2211 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2212 TLI.getPointerTy(), Op2);
2213 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2214 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2215 TLI.getPointerTy(), Op2);
2218 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2219 Op1.getValueType(), Op1, Op2));
2222 void SelectionDAGLowering::visitICmp(User &I) {
2223 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2224 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2225 predicate = IC->getPredicate();
2226 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2227 predicate = ICmpInst::Predicate(IC->getPredicate());
2228 SDValue Op1 = getValue(I.getOperand(0));
2229 SDValue Op2 = getValue(I.getOperand(1));
2230 ISD::CondCode Opcode = getICmpCondCode(predicate);
2231 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2234 void SelectionDAGLowering::visitFCmp(User &I) {
2235 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2236 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2237 predicate = FC->getPredicate();
2238 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2239 predicate = FCmpInst::Predicate(FC->getPredicate());
2240 SDValue Op1 = getValue(I.getOperand(0));
2241 SDValue Op2 = getValue(I.getOperand(1));
2242 ISD::CondCode Condition = getFCmpCondCode(predicate);
2243 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2246 void SelectionDAGLowering::visitVICmp(User &I) {
2247 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2248 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2249 predicate = IC->getPredicate();
2250 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2251 predicate = ICmpInst::Predicate(IC->getPredicate());
2252 SDValue Op1 = getValue(I.getOperand(0));
2253 SDValue Op2 = getValue(I.getOperand(1));
2254 ISD::CondCode Opcode = getICmpCondCode(predicate);
2255 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2259 void SelectionDAGLowering::visitVFCmp(User &I) {
2260 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2261 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2262 predicate = FC->getPredicate();
2263 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2264 predicate = FCmpInst::Predicate(FC->getPredicate());
2265 SDValue Op1 = getValue(I.getOperand(0));
2266 SDValue Op2 = getValue(I.getOperand(1));
2267 ISD::CondCode Condition = getFCmpCondCode(predicate);
2268 MVT DestVT = TLI.getValueType(I.getType());
2270 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2273 void SelectionDAGLowering::visitSelect(User &I) {
2274 SmallVector<MVT, 4> ValueVTs;
2275 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2276 unsigned NumValues = ValueVTs.size();
2277 if (NumValues != 0) {
2278 SmallVector<SDValue, 4> Values(NumValues);
2279 SDValue Cond = getValue(I.getOperand(0));
2280 SDValue TrueVal = getValue(I.getOperand(1));
2281 SDValue FalseVal = getValue(I.getOperand(2));
2283 for (unsigned i = 0; i != NumValues; ++i)
2284 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2285 TrueVal.getValueType(), Cond,
2286 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2287 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2289 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2290 DAG.getVTList(&ValueVTs[0], NumValues),
2291 &Values[0], NumValues));
2296 void SelectionDAGLowering::visitTrunc(User &I) {
2297 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2298 SDValue N = getValue(I.getOperand(0));
2299 MVT DestVT = TLI.getValueType(I.getType());
2300 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2303 void SelectionDAGLowering::visitZExt(User &I) {
2304 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2305 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2306 SDValue N = getValue(I.getOperand(0));
2307 MVT DestVT = TLI.getValueType(I.getType());
2308 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2311 void SelectionDAGLowering::visitSExt(User &I) {
2312 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2313 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2314 SDValue N = getValue(I.getOperand(0));
2315 MVT DestVT = TLI.getValueType(I.getType());
2316 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2319 void SelectionDAGLowering::visitFPTrunc(User &I) {
2320 // FPTrunc is never a no-op cast, no need to check
2321 SDValue N = getValue(I.getOperand(0));
2322 MVT DestVT = TLI.getValueType(I.getType());
2323 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2324 DestVT, N, DAG.getIntPtrConstant(0)));
2327 void SelectionDAGLowering::visitFPExt(User &I){
2328 // FPTrunc is never a no-op cast, no need to check
2329 SDValue N = getValue(I.getOperand(0));
2330 MVT DestVT = TLI.getValueType(I.getType());
2331 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2334 void SelectionDAGLowering::visitFPToUI(User &I) {
2335 // FPToUI is never a no-op cast, no need to check
2336 SDValue N = getValue(I.getOperand(0));
2337 MVT DestVT = TLI.getValueType(I.getType());
2338 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2341 void SelectionDAGLowering::visitFPToSI(User &I) {
2342 // FPToSI is never a no-op cast, no need to check
2343 SDValue N = getValue(I.getOperand(0));
2344 MVT DestVT = TLI.getValueType(I.getType());
2345 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2348 void SelectionDAGLowering::visitUIToFP(User &I) {
2349 // UIToFP is never a no-op cast, no need to check
2350 SDValue N = getValue(I.getOperand(0));
2351 MVT DestVT = TLI.getValueType(I.getType());
2352 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2355 void SelectionDAGLowering::visitSIToFP(User &I){
2356 // SIToFP is never a no-op cast, no need to check
2357 SDValue N = getValue(I.getOperand(0));
2358 MVT DestVT = TLI.getValueType(I.getType());
2359 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2362 void SelectionDAGLowering::visitPtrToInt(User &I) {
2363 // What to do depends on the size of the integer and the size of the pointer.
2364 // We can either truncate, zero extend, or no-op, accordingly.
2365 SDValue N = getValue(I.getOperand(0));
2366 MVT SrcVT = N.getValueType();
2367 MVT DestVT = TLI.getValueType(I.getType());
2369 if (DestVT.bitsLT(SrcVT))
2370 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2372 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2373 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2374 setValue(&I, Result);
2377 void SelectionDAGLowering::visitIntToPtr(User &I) {
2378 // What to do depends on the size of the integer and the size of the pointer.
2379 // We can either truncate, zero extend, or no-op, accordingly.
2380 SDValue N = getValue(I.getOperand(0));
2381 MVT SrcVT = N.getValueType();
2382 MVT DestVT = TLI.getValueType(I.getType());
2383 if (DestVT.bitsLT(SrcVT))
2384 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2386 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2387 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2391 void SelectionDAGLowering::visitBitCast(User &I) {
2392 SDValue N = getValue(I.getOperand(0));
2393 MVT DestVT = TLI.getValueType(I.getType());
2395 // BitCast assures us that source and destination are the same size so this
2396 // is either a BIT_CONVERT or a no-op.
2397 if (DestVT != N.getValueType())
2398 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2399 DestVT, N)); // convert types
2401 setValue(&I, N); // noop cast.
2404 void SelectionDAGLowering::visitInsertElement(User &I) {
2405 SDValue InVec = getValue(I.getOperand(0));
2406 SDValue InVal = getValue(I.getOperand(1));
2407 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2409 getValue(I.getOperand(2)));
2411 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2412 TLI.getValueType(I.getType()),
2413 InVec, InVal, InIdx));
2416 void SelectionDAGLowering::visitExtractElement(User &I) {
2417 SDValue InVec = getValue(I.getOperand(0));
2418 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2420 getValue(I.getOperand(1)));
2421 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2422 TLI.getValueType(I.getType()), InVec, InIdx));
2426 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2427 // from SIndx and increasing to the element length (undefs are allowed).
2428 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2429 unsigned MaskNumElts = Mask.getNumOperands();
2430 for (unsigned i = 0; i != MaskNumElts; ++i) {
2431 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2432 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2433 if (Idx != i + SIndx)
2440 void SelectionDAGLowering::visitShuffleVector(User &I) {
2441 SDValue Src1 = getValue(I.getOperand(0));
2442 SDValue Src2 = getValue(I.getOperand(1));
2443 SDValue Mask = getValue(I.getOperand(2));
2445 MVT VT = TLI.getValueType(I.getType());
2446 MVT SrcVT = Src1.getValueType();
2447 int MaskNumElts = Mask.getNumOperands();
2448 int SrcNumElts = SrcVT.getVectorNumElements();
2450 if (SrcNumElts == MaskNumElts) {
2451 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2452 VT, Src1, Src2, Mask));
2456 // Normalize the shuffle vector since mask and vector length don't match.
2457 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2459 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2460 // Mask is longer than the source vectors and is a multiple of the source
2461 // vectors. We can use concatenate vector to make the mask and vectors
2463 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2464 // The shuffle is concatenating two vectors together.
2465 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2470 // Pad both vectors with undefs to make them the same length as the mask.
2471 unsigned NumConcat = MaskNumElts / SrcNumElts;
2472 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2474 SDValue* MOps1 = new SDValue[NumConcat];
2475 SDValue* MOps2 = new SDValue[NumConcat];
2478 for (unsigned i = 1; i != NumConcat; ++i) {
2479 MOps1[i] = UndefVal;
2480 MOps2[i] = UndefVal;
2482 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2483 VT, MOps1, NumConcat);
2484 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2485 VT, MOps2, NumConcat);
2490 // Readjust mask for new input vector length.
2491 SmallVector<SDValue, 8> MappedOps;
2492 for (int i = 0; i != MaskNumElts; ++i) {
2493 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2494 MappedOps.push_back(Mask.getOperand(i));
2496 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2497 if (Idx < SrcNumElts)
2498 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2500 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2504 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2505 Mask.getValueType(),
2506 &MappedOps[0], MappedOps.size());
2508 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2509 VT, Src1, Src2, Mask));
2513 if (SrcNumElts > MaskNumElts) {
2514 // Resulting vector is shorter than the incoming vector.
2515 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2516 // Shuffle extracts 1st vector.
2521 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2522 // Shuffle extracts 2nd vector.
2527 // Analyze the access pattern of the vector to see if we can extract
2528 // two subvectors and do the shuffle. The analysis is done by calculating
2529 // the range of elements the mask access on both vectors.
2530 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2531 int MaxRange[2] = {-1, -1};
2533 for (int i = 0; i != MaskNumElts; ++i) {
2534 SDValue Arg = Mask.getOperand(i);
2535 if (Arg.getOpcode() != ISD::UNDEF) {
2536 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2537 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2539 if (Idx >= SrcNumElts) {
2543 if (Idx > MaxRange[Input])
2544 MaxRange[Input] = Idx;
2545 if (Idx < MinRange[Input])
2546 MinRange[Input] = Idx;
2550 // Check if the access is smaller than the vector size and can we find
2551 // a reasonable extract index.
2552 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2553 int StartIdx[2]; // StartIdx to extract from
2554 for (int Input=0; Input < 2; ++Input) {
2555 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2556 RangeUse[Input] = 0; // Unused
2557 StartIdx[Input] = 0;
2558 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2559 // Fits within range but we should see if we can find a good
2560 // start index that is a multiple of the mask length.
2561 if (MaxRange[Input] < MaskNumElts) {
2562 RangeUse[Input] = 1; // Extract from beginning of the vector
2563 StartIdx[Input] = 0;
2565 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2566 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2567 StartIdx[Input] + MaskNumElts < SrcNumElts)
2568 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2573 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2574 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2577 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2578 // Extract appropriate subvector and generate a vector shuffle
2579 for (int Input=0; Input < 2; ++Input) {
2580 SDValue& Src = Input == 0 ? Src1 : Src2;
2581 if (RangeUse[Input] == 0) {
2582 Src = DAG.getUNDEF(VT);
2584 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2585 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2588 // Calculate new mask.
2589 SmallVector<SDValue, 8> MappedOps;
2590 for (int i = 0; i != MaskNumElts; ++i) {
2591 SDValue Arg = Mask.getOperand(i);
2592 if (Arg.getOpcode() == ISD::UNDEF) {
2593 MappedOps.push_back(Arg);
2595 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2596 if (Idx < SrcNumElts)
2597 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2599 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2600 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2604 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2605 Mask.getValueType(),
2606 &MappedOps[0], MappedOps.size());
2607 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2608 VT, Src1, Src2, Mask));
2613 // We can't use either concat vectors or extract subvectors so fall back to
2614 // replacing the shuffle with extract and build vector.
2615 // to insert and build vector.
2616 MVT EltVT = VT.getVectorElementType();
2617 MVT PtrVT = TLI.getPointerTy();
2618 SmallVector<SDValue,8> Ops;
2619 for (int i = 0; i != MaskNumElts; ++i) {
2620 SDValue Arg = Mask.getOperand(i);
2621 if (Arg.getOpcode() == ISD::UNDEF) {
2622 Ops.push_back(DAG.getUNDEF(EltVT));
2624 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2625 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2626 if (Idx < SrcNumElts)
2627 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2628 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2630 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2632 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2635 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2636 VT, &Ops[0], Ops.size()));
2639 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2640 const Value *Op0 = I.getOperand(0);
2641 const Value *Op1 = I.getOperand(1);
2642 const Type *AggTy = I.getType();
2643 const Type *ValTy = Op1->getType();
2644 bool IntoUndef = isa<UndefValue>(Op0);
2645 bool FromUndef = isa<UndefValue>(Op1);
2647 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2648 I.idx_begin(), I.idx_end());
2650 SmallVector<MVT, 4> AggValueVTs;
2651 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2652 SmallVector<MVT, 4> ValValueVTs;
2653 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2655 unsigned NumAggValues = AggValueVTs.size();
2656 unsigned NumValValues = ValValueVTs.size();
2657 SmallVector<SDValue, 4> Values(NumAggValues);
2659 SDValue Agg = getValue(Op0);
2660 SDValue Val = getValue(Op1);
2662 // Copy the beginning value(s) from the original aggregate.
2663 for (; i != LinearIndex; ++i)
2664 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2665 SDValue(Agg.getNode(), Agg.getResNo() + i);
2666 // Copy values from the inserted value(s).
2667 for (; i != LinearIndex + NumValValues; ++i)
2668 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2669 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2670 // Copy remaining value(s) from the original aggregate.
2671 for (; i != NumAggValues; ++i)
2672 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2673 SDValue(Agg.getNode(), Agg.getResNo() + i);
2675 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2676 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2677 &Values[0], NumAggValues));
2680 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2681 const Value *Op0 = I.getOperand(0);
2682 const Type *AggTy = Op0->getType();
2683 const Type *ValTy = I.getType();
2684 bool OutOfUndef = isa<UndefValue>(Op0);
2686 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2687 I.idx_begin(), I.idx_end());
2689 SmallVector<MVT, 4> ValValueVTs;
2690 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2692 unsigned NumValValues = ValValueVTs.size();
2693 SmallVector<SDValue, 4> Values(NumValValues);
2695 SDValue Agg = getValue(Op0);
2696 // Copy out the selected value(s).
2697 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2698 Values[i - LinearIndex] =
2700 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2701 SDValue(Agg.getNode(), Agg.getResNo() + i);
2703 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2704 DAG.getVTList(&ValValueVTs[0], NumValValues),
2705 &Values[0], NumValValues));
2709 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2710 SDValue N = getValue(I.getOperand(0));
2711 const Type *Ty = I.getOperand(0)->getType();
2713 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2716 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2717 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2720 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2721 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2722 DAG.getIntPtrConstant(Offset));
2724 Ty = StTy->getElementType(Field);
2726 Ty = cast<SequentialType>(Ty)->getElementType();
2728 // If this is a constant subscript, handle it quickly.
2729 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2730 if (CI->getZExtValue() == 0) continue;
2732 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2734 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2736 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2738 DAG.getConstant(Offs, MVT::i64));
2740 OffsVal = DAG.getIntPtrConstant(Offs);
2741 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2746 // N = N + Idx * ElementSize;
2747 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2748 SDValue IdxN = getValue(Idx);
2750 // If the index is smaller or larger than intptr_t, truncate or extend
2752 if (IdxN.getValueType().bitsLT(N.getValueType()))
2753 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2754 N.getValueType(), IdxN);
2755 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2756 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2757 N.getValueType(), IdxN);
2759 // If this is a multiply by a power of two, turn it into a shl
2760 // immediately. This is a very common case.
2761 if (ElementSize != 1) {
2762 if (isPowerOf2_64(ElementSize)) {
2763 unsigned Amt = Log2_64(ElementSize);
2764 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2765 N.getValueType(), IdxN,
2766 DAG.getConstant(Amt, TLI.getPointerTy()));
2768 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2769 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2770 N.getValueType(), IdxN, Scale);
2774 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2775 N.getValueType(), N, IdxN);
2781 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2782 // If this is a fixed sized alloca in the entry block of the function,
2783 // allocate it statically on the stack.
2784 if (FuncInfo.StaticAllocaMap.count(&I))
2785 return; // getValue will auto-populate this.
2787 const Type *Ty = I.getAllocatedType();
2788 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2790 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2793 SDValue AllocSize = getValue(I.getArraySize());
2795 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2797 DAG.getConstant(TySize, AllocSize.getValueType()));
2801 MVT IntPtr = TLI.getPointerTy();
2802 if (IntPtr.bitsLT(AllocSize.getValueType()))
2803 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2805 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2806 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2809 // Handle alignment. If the requested alignment is less than or equal to
2810 // the stack alignment, ignore it. If the size is greater than or equal to
2811 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2812 unsigned StackAlign =
2813 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2814 if (Align <= StackAlign)
2817 // Round the size of the allocation up to the stack alignment size
2818 // by add SA-1 to the size.
2819 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2820 AllocSize.getValueType(), AllocSize,
2821 DAG.getIntPtrConstant(StackAlign-1));
2822 // Mask out the low bits for alignment purposes.
2823 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2824 AllocSize.getValueType(), AllocSize,
2825 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2827 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2828 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2829 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2832 DAG.setRoot(DSA.getValue(1));
2834 // Inform the Frame Information that we have just allocated a variable-sized
2836 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2839 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2840 const Value *SV = I.getOperand(0);
2841 SDValue Ptr = getValue(SV);
2843 const Type *Ty = I.getType();
2844 bool isVolatile = I.isVolatile();
2845 unsigned Alignment = I.getAlignment();
2847 SmallVector<MVT, 4> ValueVTs;
2848 SmallVector<uint64_t, 4> Offsets;
2849 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2850 unsigned NumValues = ValueVTs.size();
2855 bool ConstantMemory = false;
2857 // Serialize volatile loads with other side effects.
2859 else if (AA->pointsToConstantMemory(SV)) {
2860 // Do not serialize (non-volatile) loads of constant memory with anything.
2861 Root = DAG.getEntryNode();
2862 ConstantMemory = true;
2864 // Do not serialize non-volatile loads against each other.
2865 Root = DAG.getRoot();
2868 SmallVector<SDValue, 4> Values(NumValues);
2869 SmallVector<SDValue, 4> Chains(NumValues);
2870 MVT PtrVT = Ptr.getValueType();
2871 for (unsigned i = 0; i != NumValues; ++i) {
2872 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2873 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2875 DAG.getConstant(Offsets[i], PtrVT)),
2877 isVolatile, Alignment);
2879 Chains[i] = L.getValue(1);
2882 if (!ConstantMemory) {
2883 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2885 &Chains[0], NumValues);
2889 PendingLoads.push_back(Chain);
2892 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2893 DAG.getVTList(&ValueVTs[0], NumValues),
2894 &Values[0], NumValues));
2898 void SelectionDAGLowering::visitStore(StoreInst &I) {
2899 Value *SrcV = I.getOperand(0);
2900 Value *PtrV = I.getOperand(1);
2902 SmallVector<MVT, 4> ValueVTs;
2903 SmallVector<uint64_t, 4> Offsets;
2904 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2905 unsigned NumValues = ValueVTs.size();
2909 // Get the lowered operands. Note that we do this after
2910 // checking if NumResults is zero, because with zero results
2911 // the operands won't have values in the map.
2912 SDValue Src = getValue(SrcV);
2913 SDValue Ptr = getValue(PtrV);
2915 SDValue Root = getRoot();
2916 SmallVector<SDValue, 4> Chains(NumValues);
2917 MVT PtrVT = Ptr.getValueType();
2918 bool isVolatile = I.isVolatile();
2919 unsigned Alignment = I.getAlignment();
2920 for (unsigned i = 0; i != NumValues; ++i)
2921 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2922 SDValue(Src.getNode(), Src.getResNo() + i),
2923 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2925 DAG.getConstant(Offsets[i], PtrVT)),
2927 isVolatile, Alignment);
2929 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2930 MVT::Other, &Chains[0], NumValues));
2933 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2935 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2936 unsigned Intrinsic) {
2937 bool HasChain = !I.doesNotAccessMemory();
2938 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2940 // Build the operand list.
2941 SmallVector<SDValue, 8> Ops;
2942 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2944 // We don't need to serialize loads against other loads.
2945 Ops.push_back(DAG.getRoot());
2947 Ops.push_back(getRoot());
2951 // Info is set by getTgtMemInstrinsic
2952 TargetLowering::IntrinsicInfo Info;
2953 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2955 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2956 if (!IsTgtIntrinsic)
2957 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2959 // Add all operands of the call to the operand list.
2960 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2961 SDValue Op = getValue(I.getOperand(i));
2962 assert(TLI.isTypeLegal(Op.getValueType()) &&
2963 "Intrinsic uses a non-legal type?");
2967 std::vector<MVT> VTArray;
2968 if (I.getType() != Type::VoidTy) {
2969 MVT VT = TLI.getValueType(I.getType());
2970 if (VT.isVector()) {
2971 const VectorType *DestTy = cast<VectorType>(I.getType());
2972 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2974 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2975 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2978 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2979 VTArray.push_back(VT);
2982 VTArray.push_back(MVT::Other);
2984 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2988 if (IsTgtIntrinsic) {
2989 // This is target intrinsic that touches memory
2990 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2991 VTs, &Ops[0], Ops.size(),
2992 Info.memVT, Info.ptrVal, Info.offset,
2993 Info.align, Info.vol,
2994 Info.readMem, Info.writeMem);
2997 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2998 VTs, &Ops[0], Ops.size());
2999 else if (I.getType() != Type::VoidTy)
3000 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3001 VTs, &Ops[0], Ops.size());
3003 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3004 VTs, &Ops[0], Ops.size());
3007 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3009 PendingLoads.push_back(Chain);
3013 if (I.getType() != Type::VoidTy) {
3014 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3015 MVT VT = TLI.getValueType(PTy);
3016 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3018 setValue(&I, Result);
3022 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3023 static GlobalVariable *ExtractTypeInfo(Value *V) {
3024 V = V->stripPointerCasts();
3025 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3026 assert ((GV || isa<ConstantPointerNull>(V)) &&
3027 "TypeInfo must be a global variable or NULL");
3033 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3034 /// call, and add them to the specified machine basic block.
3035 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3036 MachineBasicBlock *MBB) {
3037 // Inform the MachineModuleInfo of the personality for this landing pad.
3038 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3039 assert(CE->getOpcode() == Instruction::BitCast &&
3040 isa<Function>(CE->getOperand(0)) &&
3041 "Personality should be a function");
3042 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3044 // Gather all the type infos for this landing pad and pass them along to
3045 // MachineModuleInfo.
3046 std::vector<GlobalVariable *> TyInfo;
3047 unsigned N = I.getNumOperands();
3049 for (unsigned i = N - 1; i > 2; --i) {
3050 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3051 unsigned FilterLength = CI->getZExtValue();
3052 unsigned FirstCatch = i + FilterLength + !FilterLength;
3053 assert (FirstCatch <= N && "Invalid filter length");
3055 if (FirstCatch < N) {
3056 TyInfo.reserve(N - FirstCatch);
3057 for (unsigned j = FirstCatch; j < N; ++j)
3058 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3059 MMI->addCatchTypeInfo(MBB, TyInfo);
3063 if (!FilterLength) {
3065 MMI->addCleanup(MBB);
3068 TyInfo.reserve(FilterLength - 1);
3069 for (unsigned j = i + 1; j < FirstCatch; ++j)
3070 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3071 MMI->addFilterTypeInfo(MBB, TyInfo);
3080 TyInfo.reserve(N - 3);
3081 for (unsigned j = 3; j < N; ++j)
3082 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3083 MMI->addCatchTypeInfo(MBB, TyInfo);
3089 /// GetSignificand - Get the significand and build it into a floating-point
3090 /// number with exponent of 1:
3092 /// Op = (Op & 0x007fffff) | 0x3f800000;
3094 /// where Op is the hexidecimal representation of floating point value.
3096 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3097 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3098 DAG.getConstant(0x007fffff, MVT::i32));
3099 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3100 DAG.getConstant(0x3f800000, MVT::i32));
3101 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3104 /// GetExponent - Get the exponent:
3106 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3108 /// where Op is the hexidecimal representation of floating point value.
3110 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3112 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3113 DAG.getConstant(0x7f800000, MVT::i32));
3114 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3115 DAG.getConstant(23, TLI.getPointerTy()));
3116 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3117 DAG.getConstant(127, MVT::i32));
3118 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3121 /// getF32Constant - Get 32-bit floating point constant.
3123 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3124 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3127 /// Inlined utility function to implement binary input atomic intrinsics for
3128 /// visitIntrinsicCall: I is a call instruction
3129 /// Op is the associated NodeType for I
3131 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3132 SDValue Root = getRoot();
3134 DAG.getAtomic(Op, getCurDebugLoc(),
3135 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3137 getValue(I.getOperand(1)),
3138 getValue(I.getOperand(2)),
3141 DAG.setRoot(L.getValue(1));
3145 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3147 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3148 SDValue Op1 = getValue(I.getOperand(1));
3149 SDValue Op2 = getValue(I.getOperand(2));
3151 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3152 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3154 setValue(&I, Result);
3158 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3159 /// limited-precision mode.
3161 SelectionDAGLowering::visitExp(CallInst &I) {
3163 DebugLoc dl = getCurDebugLoc();
3165 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3166 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3167 SDValue Op = getValue(I.getOperand(1));
3169 // Put the exponent in the right bit position for later addition to the
3172 // #define LOG2OFe 1.4426950f
3173 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3174 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3175 getF32Constant(DAG, 0x3fb8aa3b));
3176 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3178 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3179 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3180 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3182 // IntegerPartOfX <<= 23;
3183 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3184 DAG.getConstant(23, TLI.getPointerTy()));
3186 if (LimitFloatPrecision <= 6) {
3187 // For floating-point precision of 6:
3189 // TwoToFractionalPartOfX =
3191 // (0.735607626f + 0.252464424f * x) * x;
3193 // error 0.0144103317, which is 6 bits
3194 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3195 getF32Constant(DAG, 0x3e814304));
3196 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3197 getF32Constant(DAG, 0x3f3c50c8));
3198 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3199 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3200 getF32Constant(DAG, 0x3f7f5e7e));
3201 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3203 // Add the exponent into the result in integer domain.
3204 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3205 TwoToFracPartOfX, IntegerPartOfX);
3207 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3208 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3209 // For floating-point precision of 12:
3211 // TwoToFractionalPartOfX =
3214 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3216 // 0.000107046256 error, which is 13 to 14 bits
3217 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3218 getF32Constant(DAG, 0x3da235e3));
3219 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3220 getF32Constant(DAG, 0x3e65b8f3));
3221 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3222 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3223 getF32Constant(DAG, 0x3f324b07));
3224 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3225 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3226 getF32Constant(DAG, 0x3f7ff8fd));
3227 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3229 // Add the exponent into the result in integer domain.
3230 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3231 TwoToFracPartOfX, IntegerPartOfX);
3233 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3234 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3235 // For floating-point precision of 18:
3237 // TwoToFractionalPartOfX =
3241 // (0.554906021e-1f +
3242 // (0.961591928e-2f +
3243 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3245 // error 2.47208000*10^(-7), which is better than 18 bits
3246 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3247 getF32Constant(DAG, 0x3924b03e));
3248 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3249 getF32Constant(DAG, 0x3ab24b87));
3250 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3251 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3252 getF32Constant(DAG, 0x3c1d8c17));
3253 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3254 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3255 getF32Constant(DAG, 0x3d634a1d));
3256 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3257 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3258 getF32Constant(DAG, 0x3e75fe14));
3259 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3260 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3261 getF32Constant(DAG, 0x3f317234));
3262 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3263 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3264 getF32Constant(DAG, 0x3f800000));
3265 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3268 // Add the exponent into the result in integer domain.
3269 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3270 TwoToFracPartOfX, IntegerPartOfX);
3272 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3275 // No special expansion.
3276 result = DAG.getNode(ISD::FEXP, dl,
3277 getValue(I.getOperand(1)).getValueType(),
3278 getValue(I.getOperand(1)));
3281 setValue(&I, result);
3284 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3285 /// limited-precision mode.
3287 SelectionDAGLowering::visitLog(CallInst &I) {
3289 DebugLoc dl = getCurDebugLoc();
3291 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3292 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3293 SDValue Op = getValue(I.getOperand(1));
3294 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3296 // Scale the exponent by log(2) [0.69314718f].
3297 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3298 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3299 getF32Constant(DAG, 0x3f317218));
3301 // Get the significand and build it into a floating-point number with
3303 SDValue X = GetSignificand(DAG, Op1, dl);
3305 if (LimitFloatPrecision <= 6) {
3306 // For floating-point precision of 6:
3310 // (1.4034025f - 0.23903021f * x) * x;
3312 // error 0.0034276066, which is better than 8 bits
3313 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3314 getF32Constant(DAG, 0xbe74c456));
3315 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3316 getF32Constant(DAG, 0x3fb3a2b1));
3317 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3318 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3319 getF32Constant(DAG, 0x3f949a29));
3321 result = DAG.getNode(ISD::FADD, dl,
3322 MVT::f32, LogOfExponent, LogOfMantissa);
3323 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3324 // For floating-point precision of 12:
3330 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3332 // error 0.000061011436, which is 14 bits
3333 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3334 getF32Constant(DAG, 0xbd67b6d6));
3335 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3336 getF32Constant(DAG, 0x3ee4f4b8));
3337 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3338 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3339 getF32Constant(DAG, 0x3fbc278b));
3340 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3341 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3342 getF32Constant(DAG, 0x40348e95));
3343 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3344 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3345 getF32Constant(DAG, 0x3fdef31a));
3347 result = DAG.getNode(ISD::FADD, dl,
3348 MVT::f32, LogOfExponent, LogOfMantissa);
3349 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3350 // For floating-point precision of 18:
3358 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3360 // error 0.0000023660568, which is better than 18 bits
3361 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3362 getF32Constant(DAG, 0xbc91e5ac));
3363 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3364 getF32Constant(DAG, 0x3e4350aa));
3365 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3366 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3367 getF32Constant(DAG, 0x3f60d3e3));
3368 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3369 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3370 getF32Constant(DAG, 0x4011cdf0));
3371 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3372 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3373 getF32Constant(DAG, 0x406cfd1c));
3374 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3375 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3376 getF32Constant(DAG, 0x408797cb));
3377 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3378 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3379 getF32Constant(DAG, 0x4006dcab));
3381 result = DAG.getNode(ISD::FADD, dl,
3382 MVT::f32, LogOfExponent, LogOfMantissa);
3385 // No special expansion.
3386 result = DAG.getNode(ISD::FLOG, dl,
3387 getValue(I.getOperand(1)).getValueType(),
3388 getValue(I.getOperand(1)));
3391 setValue(&I, result);
3394 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3395 /// limited-precision mode.
3397 SelectionDAGLowering::visitLog2(CallInst &I) {
3399 DebugLoc dl = getCurDebugLoc();
3401 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3402 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3403 SDValue Op = getValue(I.getOperand(1));
3404 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3406 // Get the exponent.
3407 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3409 // Get the significand and build it into a floating-point number with
3411 SDValue X = GetSignificand(DAG, Op1, dl);
3413 // Different possible minimax approximations of significand in
3414 // floating-point for various degrees of accuracy over [1,2].
3415 if (LimitFloatPrecision <= 6) {
3416 // For floating-point precision of 6:
3418 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3420 // error 0.0049451742, which is more than 7 bits
3421 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3422 getF32Constant(DAG, 0xbeb08fe0));
3423 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3424 getF32Constant(DAG, 0x40019463));
3425 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3426 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3427 getF32Constant(DAG, 0x3fd6633d));
3429 result = DAG.getNode(ISD::FADD, dl,
3430 MVT::f32, LogOfExponent, Log2ofMantissa);
3431 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3432 // For floating-point precision of 12:
3438 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3440 // error 0.0000876136000, which is better than 13 bits
3441 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3442 getF32Constant(DAG, 0xbda7262e));
3443 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3444 getF32Constant(DAG, 0x3f25280b));
3445 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3446 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3447 getF32Constant(DAG, 0x4007b923));
3448 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3449 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3450 getF32Constant(DAG, 0x40823e2f));
3451 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3452 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3453 getF32Constant(DAG, 0x4020d29c));
3455 result = DAG.getNode(ISD::FADD, dl,
3456 MVT::f32, LogOfExponent, Log2ofMantissa);
3457 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3458 // For floating-point precision of 18:
3467 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3469 // error 0.0000018516, which is better than 18 bits
3470 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3471 getF32Constant(DAG, 0xbcd2769e));
3472 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3473 getF32Constant(DAG, 0x3e8ce0b9));
3474 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3475 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3476 getF32Constant(DAG, 0x3fa22ae7));
3477 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3478 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3479 getF32Constant(DAG, 0x40525723));
3480 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3481 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3482 getF32Constant(DAG, 0x40aaf200));
3483 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3484 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3485 getF32Constant(DAG, 0x40c39dad));
3486 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3487 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3488 getF32Constant(DAG, 0x4042902c));
3490 result = DAG.getNode(ISD::FADD, dl,
3491 MVT::f32, LogOfExponent, Log2ofMantissa);
3494 // No special expansion.
3495 result = DAG.getNode(ISD::FLOG2, dl,
3496 getValue(I.getOperand(1)).getValueType(),
3497 getValue(I.getOperand(1)));
3500 setValue(&I, result);
3503 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3504 /// limited-precision mode.
3506 SelectionDAGLowering::visitLog10(CallInst &I) {
3508 DebugLoc dl = getCurDebugLoc();
3510 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3511 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3512 SDValue Op = getValue(I.getOperand(1));
3513 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3515 // Scale the exponent by log10(2) [0.30102999f].
3516 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3517 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3518 getF32Constant(DAG, 0x3e9a209a));
3520 // Get the significand and build it into a floating-point number with
3522 SDValue X = GetSignificand(DAG, Op1, dl);
3524 if (LimitFloatPrecision <= 6) {
3525 // For floating-point precision of 6:
3527 // Log10ofMantissa =
3529 // (0.60948995f - 0.10380950f * x) * x;
3531 // error 0.0014886165, which is 6 bits
3532 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3533 getF32Constant(DAG, 0xbdd49a13));
3534 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3535 getF32Constant(DAG, 0x3f1c0789));
3536 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3537 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3538 getF32Constant(DAG, 0x3f011300));
3540 result = DAG.getNode(ISD::FADD, dl,
3541 MVT::f32, LogOfExponent, Log10ofMantissa);
3542 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3543 // For floating-point precision of 12:
3545 // Log10ofMantissa =
3548 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3550 // error 0.00019228036, which is better than 12 bits
3551 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3552 getF32Constant(DAG, 0x3d431f31));
3553 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3554 getF32Constant(DAG, 0x3ea21fb2));
3555 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3556 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3557 getF32Constant(DAG, 0x3f6ae232));
3558 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3559 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3560 getF32Constant(DAG, 0x3f25f7c3));
3562 result = DAG.getNode(ISD::FADD, dl,
3563 MVT::f32, LogOfExponent, Log10ofMantissa);
3564 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3565 // For floating-point precision of 18:
3567 // Log10ofMantissa =
3572 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3574 // error 0.0000037995730, which is better than 18 bits
3575 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3576 getF32Constant(DAG, 0x3c5d51ce));
3577 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3578 getF32Constant(DAG, 0x3e00685a));
3579 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3580 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3581 getF32Constant(DAG, 0x3efb6798));
3582 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3583 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3584 getF32Constant(DAG, 0x3f88d192));
3585 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3586 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3587 getF32Constant(DAG, 0x3fc4316c));
3588 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3589 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3590 getF32Constant(DAG, 0x3f57ce70));
3592 result = DAG.getNode(ISD::FADD, dl,
3593 MVT::f32, LogOfExponent, Log10ofMantissa);
3596 // No special expansion.
3597 result = DAG.getNode(ISD::FLOG10, dl,
3598 getValue(I.getOperand(1)).getValueType(),
3599 getValue(I.getOperand(1)));
3602 setValue(&I, result);
3605 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3606 /// limited-precision mode.
3608 SelectionDAGLowering::visitExp2(CallInst &I) {
3610 DebugLoc dl = getCurDebugLoc();
3612 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3613 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3614 SDValue Op = getValue(I.getOperand(1));
3616 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3618 // FractionalPartOfX = x - (float)IntegerPartOfX;
3619 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3620 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3622 // IntegerPartOfX <<= 23;
3623 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3624 DAG.getConstant(23, TLI.getPointerTy()));
3626 if (LimitFloatPrecision <= 6) {
3627 // For floating-point precision of 6:
3629 // TwoToFractionalPartOfX =
3631 // (0.735607626f + 0.252464424f * x) * x;
3633 // error 0.0144103317, which is 6 bits
3634 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3635 getF32Constant(DAG, 0x3e814304));
3636 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3637 getF32Constant(DAG, 0x3f3c50c8));
3638 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3639 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3640 getF32Constant(DAG, 0x3f7f5e7e));
3641 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3642 SDValue TwoToFractionalPartOfX =
3643 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3645 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3646 MVT::f32, TwoToFractionalPartOfX);
3647 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3648 // For floating-point precision of 12:
3650 // TwoToFractionalPartOfX =
3653 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3655 // error 0.000107046256, which is 13 to 14 bits
3656 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3657 getF32Constant(DAG, 0x3da235e3));
3658 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3659 getF32Constant(DAG, 0x3e65b8f3));
3660 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3661 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3662 getF32Constant(DAG, 0x3f324b07));
3663 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3664 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3665 getF32Constant(DAG, 0x3f7ff8fd));
3666 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3667 SDValue TwoToFractionalPartOfX =
3668 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3670 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3671 MVT::f32, TwoToFractionalPartOfX);
3672 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3673 // For floating-point precision of 18:
3675 // TwoToFractionalPartOfX =
3679 // (0.554906021e-1f +
3680 // (0.961591928e-2f +
3681 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3682 // error 2.47208000*10^(-7), which is better than 18 bits
3683 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3684 getF32Constant(DAG, 0x3924b03e));
3685 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3686 getF32Constant(DAG, 0x3ab24b87));
3687 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3688 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3689 getF32Constant(DAG, 0x3c1d8c17));
3690 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3691 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3692 getF32Constant(DAG, 0x3d634a1d));
3693 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3694 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3695 getF32Constant(DAG, 0x3e75fe14));
3696 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3697 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3698 getF32Constant(DAG, 0x3f317234));
3699 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3700 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3701 getF32Constant(DAG, 0x3f800000));
3702 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3703 SDValue TwoToFractionalPartOfX =
3704 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3706 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3707 MVT::f32, TwoToFractionalPartOfX);
3710 // No special expansion.
3711 result = DAG.getNode(ISD::FEXP2, dl,
3712 getValue(I.getOperand(1)).getValueType(),
3713 getValue(I.getOperand(1)));
3716 setValue(&I, result);
3719 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3720 /// limited-precision mode with x == 10.0f.
3722 SelectionDAGLowering::visitPow(CallInst &I) {
3724 Value *Val = I.getOperand(1);
3725 DebugLoc dl = getCurDebugLoc();
3726 bool IsExp10 = false;
3728 if (getValue(Val).getValueType() == MVT::f32 &&
3729 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3730 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3731 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3732 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3734 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3739 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3740 SDValue Op = getValue(I.getOperand(2));
3742 // Put the exponent in the right bit position for later addition to the
3745 // #define LOG2OF10 3.3219281f
3746 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3747 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3748 getF32Constant(DAG, 0x40549a78));
3749 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3751 // FractionalPartOfX = x - (float)IntegerPartOfX;
3752 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3753 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3755 // IntegerPartOfX <<= 23;
3756 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3757 DAG.getConstant(23, TLI.getPointerTy()));
3759 if (LimitFloatPrecision <= 6) {
3760 // For floating-point precision of 6:
3762 // twoToFractionalPartOfX =
3764 // (0.735607626f + 0.252464424f * x) * x;
3766 // error 0.0144103317, which is 6 bits
3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3768 getF32Constant(DAG, 0x3e814304));
3769 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3770 getF32Constant(DAG, 0x3f3c50c8));
3771 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3772 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3773 getF32Constant(DAG, 0x3f7f5e7e));
3774 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3775 SDValue TwoToFractionalPartOfX =
3776 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3778 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3779 MVT::f32, TwoToFractionalPartOfX);
3780 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3781 // For floating-point precision of 12:
3783 // TwoToFractionalPartOfX =
3786 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3788 // error 0.000107046256, which is 13 to 14 bits
3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3790 getF32Constant(DAG, 0x3da235e3));
3791 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3792 getF32Constant(DAG, 0x3e65b8f3));
3793 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3794 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3795 getF32Constant(DAG, 0x3f324b07));
3796 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3797 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3798 getF32Constant(DAG, 0x3f7ff8fd));
3799 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3800 SDValue TwoToFractionalPartOfX =
3801 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3803 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3804 MVT::f32, TwoToFractionalPartOfX);
3805 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3806 // For floating-point precision of 18:
3808 // TwoToFractionalPartOfX =
3812 // (0.554906021e-1f +
3813 // (0.961591928e-2f +
3814 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3815 // error 2.47208000*10^(-7), which is better than 18 bits
3816 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3817 getF32Constant(DAG, 0x3924b03e));
3818 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3819 getF32Constant(DAG, 0x3ab24b87));
3820 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3821 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3822 getF32Constant(DAG, 0x3c1d8c17));
3823 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3824 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3825 getF32Constant(DAG, 0x3d634a1d));
3826 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3827 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3828 getF32Constant(DAG, 0x3e75fe14));
3829 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3830 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3831 getF32Constant(DAG, 0x3f317234));
3832 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3833 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3834 getF32Constant(DAG, 0x3f800000));
3835 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3836 SDValue TwoToFractionalPartOfX =
3837 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3839 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3840 MVT::f32, TwoToFractionalPartOfX);
3843 // No special expansion.
3844 result = DAG.getNode(ISD::FPOW, dl,
3845 getValue(I.getOperand(1)).getValueType(),
3846 getValue(I.getOperand(1)),
3847 getValue(I.getOperand(2)));
3850 setValue(&I, result);
3853 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3854 /// we want to emit this as a call to a named external function, return the name
3855 /// otherwise lower it and return null.
3857 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3858 DebugLoc dl = getCurDebugLoc();
3859 switch (Intrinsic) {
3861 // By default, turn this into a target intrinsic node.
3862 visitTargetIntrinsic(I, Intrinsic);
3864 case Intrinsic::vastart: visitVAStart(I); return 0;
3865 case Intrinsic::vaend: visitVAEnd(I); return 0;
3866 case Intrinsic::vacopy: visitVACopy(I); return 0;
3867 case Intrinsic::returnaddress:
3868 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3869 getValue(I.getOperand(1))));
3871 case Intrinsic::frameaddress:
3872 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3873 getValue(I.getOperand(1))));
3875 case Intrinsic::setjmp:
3876 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3878 case Intrinsic::longjmp:
3879 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3881 case Intrinsic::memcpy: {
3882 SDValue Op1 = getValue(I.getOperand(1));
3883 SDValue Op2 = getValue(I.getOperand(2));
3884 SDValue Op3 = getValue(I.getOperand(3));
3885 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3886 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3887 I.getOperand(1), 0, I.getOperand(2), 0));
3890 case Intrinsic::memset: {
3891 SDValue Op1 = getValue(I.getOperand(1));
3892 SDValue Op2 = getValue(I.getOperand(2));
3893 SDValue Op3 = getValue(I.getOperand(3));
3894 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3895 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3896 I.getOperand(1), 0));
3899 case Intrinsic::memmove: {
3900 SDValue Op1 = getValue(I.getOperand(1));
3901 SDValue Op2 = getValue(I.getOperand(2));
3902 SDValue Op3 = getValue(I.getOperand(3));
3903 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3905 // If the source and destination are known to not be aliases, we can
3906 // lower memmove as memcpy.
3907 uint64_t Size = -1ULL;
3908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3909 Size = C->getZExtValue();
3910 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3911 AliasAnalysis::NoAlias) {
3912 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3913 I.getOperand(1), 0, I.getOperand(2), 0));
3917 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3918 I.getOperand(1), 0, I.getOperand(2), 0));
3921 case Intrinsic::dbg_stoppoint: {
3922 DwarfWriter *DW = DAG.getDwarfWriter();
3923 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3924 if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
3925 MachineFunction &MF = DAG.getMachineFunction();
3927 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3931 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3932 std::string Dir, FN;
3933 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
3934 CU.getFilename(FN));
3935 unsigned idx = MF.getOrCreateDebugLocID(SrcFile,
3936 SPI.getLine(), SPI.getColumn());
3937 setCurDebugLoc(DebugLoc::get(idx));
3941 case Intrinsic::dbg_region_start: {
3942 DwarfWriter *DW = DAG.getDwarfWriter();
3943 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3944 if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
3946 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3947 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3948 getRoot(), LabelID));
3953 case Intrinsic::dbg_region_end: {
3954 DwarfWriter *DW = DAG.getDwarfWriter();
3955 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3956 if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
3958 MachineFunction &MF = DAG.getMachineFunction();
3959 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3961 Subprogram.getLinkageName(SPName);
3963 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
3964 // This is end of inlined function. Debugging information for
3965 // inlined function is not handled yet (only supported by FastISel).
3967 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3969 // Returned ID is 0 if this is unbalanced "end of inlined
3970 // scope". This could happen if optimizer eats dbg intrinsics
3971 // or "beginning of inlined scope" is not recoginized due to
3972 // missing location info. In such cases, do ignore this region.end.
3973 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3980 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3981 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3982 getRoot(), LabelID));
3987 case Intrinsic::dbg_func_start: {
3988 DwarfWriter *DW = DAG.getDwarfWriter();
3990 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3991 Value *SP = FSI.getSubprogram();
3992 if (SP && DW->ValidDebugInfo(SP, Fast)) {
3993 MachineFunction &MF = DAG.getMachineFunction();
3995 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
3996 // (most?) gdb expects.
3997 DebugLoc PrevLoc = CurDebugLoc;
3998 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3999 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4000 std::string Dir, FN;
4001 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4002 CompileUnit.getFilename(FN));
4004 if (!Subprogram.describes(MF.getFunction())) {
4005 // This is a beginning of an inlined function.
4007 // If llvm.dbg.func.start is seen in a new block before any
4008 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
4009 // FIXME : Why DebugLoc is reset at the beginning of each block ?
4010 if (PrevLoc.isUnknown())
4013 // Record the source line.
4014 unsigned Line = Subprogram.getLineNumber();
4015 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
4016 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4018 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
4019 getRoot(), LabelID));
4020 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
4021 DW->RecordInlinedFnStart(&FSI, Subprogram, LabelID,
4026 // Record the source line.
4027 unsigned Line = Subprogram.getLineNumber();
4028 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4029 DW->RecordSourceLine(Line, 0, SrcFile);
4030 // llvm.dbg.func_start also defines beginning of function scope.
4031 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
4034 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4037 Subprogram.getLinkageName(SPName);
4039 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
4040 // This is beginning of inlined function. Debugging information for
4041 // inlined function is not handled yet (only supported by FastISel).
4045 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
4046 // what (most?) gdb expects.
4047 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4048 std::string Dir, FN;
4049 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4050 CompileUnit.getFilename(FN));
4052 // Record the source line but does not create a label for the normal
4053 // function start. It will be emitted at asm emission time. However,
4054 // create a label if this is a beginning of inlined function.
4055 unsigned Line = Subprogram.getLineNumber();
4056 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4057 // FIXME - Start new region because llvm.dbg.func_start also defines
4058 // beginning of function scope.
4064 case Intrinsic::dbg_declare: {
4066 DwarfWriter *DW = DAG.getDwarfWriter();
4067 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4068 Value *Variable = DI.getVariable();
4069 if (DW && DW->ValidDebugInfo(Variable, Fast))
4070 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
4071 getValue(DI.getAddress()), getValue(Variable)));
4073 // FIXME: Do something sensible here when we support debug declare.
4077 case Intrinsic::eh_exception: {
4078 if (!CurMBB->isLandingPad()) {
4079 // FIXME: Mark exception register as live in. Hack for PR1508.
4080 unsigned Reg = TLI.getExceptionAddressRegister();
4081 if (Reg) CurMBB->addLiveIn(Reg);
4083 // Insert the EXCEPTIONADDR instruction.
4084 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4086 Ops[0] = DAG.getRoot();
4087 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4089 DAG.setRoot(Op.getValue(1));
4093 case Intrinsic::eh_selector_i32:
4094 case Intrinsic::eh_selector_i64: {
4095 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4096 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4097 MVT::i32 : MVT::i64);
4100 if (CurMBB->isLandingPad())
4101 AddCatchInfo(I, MMI, CurMBB);
4104 FuncInfo.CatchInfoLost.insert(&I);
4106 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4107 unsigned Reg = TLI.getExceptionSelectorRegister();
4108 if (Reg) CurMBB->addLiveIn(Reg);
4111 // Insert the EHSELECTION instruction.
4112 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4114 Ops[0] = getValue(I.getOperand(1));
4116 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4118 DAG.setRoot(Op.getValue(1));
4120 setValue(&I, DAG.getConstant(0, VT));
4126 case Intrinsic::eh_typeid_for_i32:
4127 case Intrinsic::eh_typeid_for_i64: {
4128 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4129 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4130 MVT::i32 : MVT::i64);
4133 // Find the type id for the given typeinfo.
4134 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4136 unsigned TypeID = MMI->getTypeIDFor(GV);
4137 setValue(&I, DAG.getConstant(TypeID, VT));
4139 // Return something different to eh_selector.
4140 setValue(&I, DAG.getConstant(1, VT));
4146 case Intrinsic::eh_return_i32:
4147 case Intrinsic::eh_return_i64:
4148 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4149 MMI->setCallsEHReturn(true);
4150 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4153 getValue(I.getOperand(1)),
4154 getValue(I.getOperand(2))));
4156 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4160 case Intrinsic::eh_unwind_init:
4161 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4162 MMI->setCallsUnwindInit(true);
4167 case Intrinsic::eh_dwarf_cfa: {
4168 MVT VT = getValue(I.getOperand(1)).getValueType();
4170 if (VT.bitsGT(TLI.getPointerTy()))
4171 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4172 TLI.getPointerTy(), getValue(I.getOperand(1)));
4174 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4175 TLI.getPointerTy(), getValue(I.getOperand(1)));
4177 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4179 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4180 TLI.getPointerTy()),
4182 setValue(&I, DAG.getNode(ISD::ADD, dl,
4184 DAG.getNode(ISD::FRAMEADDR, dl,
4187 TLI.getPointerTy())),
4192 case Intrinsic::convertff:
4193 case Intrinsic::convertfsi:
4194 case Intrinsic::convertfui:
4195 case Intrinsic::convertsif:
4196 case Intrinsic::convertuif:
4197 case Intrinsic::convertss:
4198 case Intrinsic::convertsu:
4199 case Intrinsic::convertus:
4200 case Intrinsic::convertuu: {
4201 ISD::CvtCode Code = ISD::CVT_INVALID;
4202 switch (Intrinsic) {
4203 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4204 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4205 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4206 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4207 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4208 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4209 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4210 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4211 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4213 MVT DestVT = TLI.getValueType(I.getType());
4214 Value* Op1 = I.getOperand(1);
4215 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4216 DAG.getValueType(DestVT),
4217 DAG.getValueType(getValue(Op1).getValueType()),
4218 getValue(I.getOperand(2)),
4219 getValue(I.getOperand(3)),
4224 case Intrinsic::sqrt:
4225 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4226 getValue(I.getOperand(1)).getValueType(),
4227 getValue(I.getOperand(1))));
4229 case Intrinsic::powi:
4230 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4231 getValue(I.getOperand(1)).getValueType(),
4232 getValue(I.getOperand(1)),
4233 getValue(I.getOperand(2))));
4235 case Intrinsic::sin:
4236 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4237 getValue(I.getOperand(1)).getValueType(),
4238 getValue(I.getOperand(1))));
4240 case Intrinsic::cos:
4241 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4242 getValue(I.getOperand(1)).getValueType(),
4243 getValue(I.getOperand(1))));
4245 case Intrinsic::log:
4248 case Intrinsic::log2:
4251 case Intrinsic::log10:
4254 case Intrinsic::exp:
4257 case Intrinsic::exp2:
4260 case Intrinsic::pow:
4263 case Intrinsic::pcmarker: {
4264 SDValue Tmp = getValue(I.getOperand(1));
4265 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4268 case Intrinsic::readcyclecounter: {
4269 SDValue Op = getRoot();
4270 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4271 DAG.getVTList(MVT::i64, MVT::Other),
4274 DAG.setRoot(Tmp.getValue(1));
4277 case Intrinsic::part_select: {
4278 // Currently not implemented: just abort
4279 assert(0 && "part_select intrinsic not implemented");
4282 case Intrinsic::part_set: {
4283 // Currently not implemented: just abort
4284 assert(0 && "part_set intrinsic not implemented");
4287 case Intrinsic::bswap:
4288 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4289 getValue(I.getOperand(1)).getValueType(),
4290 getValue(I.getOperand(1))));
4292 case Intrinsic::cttz: {
4293 SDValue Arg = getValue(I.getOperand(1));
4294 MVT Ty = Arg.getValueType();
4295 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4296 setValue(&I, result);
4299 case Intrinsic::ctlz: {
4300 SDValue Arg = getValue(I.getOperand(1));
4301 MVT Ty = Arg.getValueType();
4302 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4303 setValue(&I, result);
4306 case Intrinsic::ctpop: {
4307 SDValue Arg = getValue(I.getOperand(1));
4308 MVT Ty = Arg.getValueType();
4309 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4310 setValue(&I, result);
4313 case Intrinsic::stacksave: {
4314 SDValue Op = getRoot();
4315 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4316 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4318 DAG.setRoot(Tmp.getValue(1));
4321 case Intrinsic::stackrestore: {
4322 SDValue Tmp = getValue(I.getOperand(1));
4323 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4326 case Intrinsic::stackprotector: {
4327 // Emit code into the DAG to store the stack guard onto the stack.
4328 MachineFunction &MF = DAG.getMachineFunction();
4329 MachineFrameInfo *MFI = MF.getFrameInfo();
4330 MVT PtrTy = TLI.getPointerTy();
4332 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4333 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4335 int FI = FuncInfo.StaticAllocaMap[Slot];
4336 MFI->setStackProtectorIndex(FI);
4338 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4340 // Store the stack protector onto the stack.
4341 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4342 PseudoSourceValue::getFixedStack(FI),
4344 setValue(&I, Result);
4345 DAG.setRoot(Result);
4348 case Intrinsic::var_annotation:
4349 // Discard annotate attributes
4352 case Intrinsic::init_trampoline: {
4353 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4357 Ops[1] = getValue(I.getOperand(1));
4358 Ops[2] = getValue(I.getOperand(2));
4359 Ops[3] = getValue(I.getOperand(3));
4360 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4361 Ops[5] = DAG.getSrcValue(F);
4363 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4364 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4368 DAG.setRoot(Tmp.getValue(1));
4372 case Intrinsic::gcroot:
4374 Value *Alloca = I.getOperand(1);
4375 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4377 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4378 GFI->addStackRoot(FI->getIndex(), TypeMap);
4382 case Intrinsic::gcread:
4383 case Intrinsic::gcwrite:
4384 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4387 case Intrinsic::flt_rounds: {
4388 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4392 case Intrinsic::trap: {
4393 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4397 case Intrinsic::uadd_with_overflow:
4398 return implVisitAluOverflow(I, ISD::UADDO);
4399 case Intrinsic::sadd_with_overflow:
4400 return implVisitAluOverflow(I, ISD::SADDO);
4401 case Intrinsic::usub_with_overflow:
4402 return implVisitAluOverflow(I, ISD::USUBO);
4403 case Intrinsic::ssub_with_overflow:
4404 return implVisitAluOverflow(I, ISD::SSUBO);
4405 case Intrinsic::umul_with_overflow:
4406 return implVisitAluOverflow(I, ISD::UMULO);
4407 case Intrinsic::smul_with_overflow:
4408 return implVisitAluOverflow(I, ISD::SMULO);
4410 case Intrinsic::prefetch: {
4413 Ops[1] = getValue(I.getOperand(1));
4414 Ops[2] = getValue(I.getOperand(2));
4415 Ops[3] = getValue(I.getOperand(3));
4416 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4420 case Intrinsic::memory_barrier: {
4423 for (int x = 1; x < 6; ++x)
4424 Ops[x] = getValue(I.getOperand(x));
4426 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4429 case Intrinsic::atomic_cmp_swap: {
4430 SDValue Root = getRoot();
4432 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4433 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4435 getValue(I.getOperand(1)),
4436 getValue(I.getOperand(2)),
4437 getValue(I.getOperand(3)),
4440 DAG.setRoot(L.getValue(1));
4443 case Intrinsic::atomic_load_add:
4444 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4445 case Intrinsic::atomic_load_sub:
4446 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4447 case Intrinsic::atomic_load_or:
4448 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4449 case Intrinsic::atomic_load_xor:
4450 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4451 case Intrinsic::atomic_load_and:
4452 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4453 case Intrinsic::atomic_load_nand:
4454 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4455 case Intrinsic::atomic_load_max:
4456 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4457 case Intrinsic::atomic_load_min:
4458 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4459 case Intrinsic::atomic_load_umin:
4460 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4461 case Intrinsic::atomic_load_umax:
4462 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4463 case Intrinsic::atomic_swap:
4464 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4469 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4471 MachineBasicBlock *LandingPad) {
4472 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4473 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4474 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4475 unsigned BeginLabel = 0, EndLabel = 0;
4477 TargetLowering::ArgListTy Args;
4478 TargetLowering::ArgListEntry Entry;
4479 Args.reserve(CS.arg_size());
4480 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4482 SDValue ArgNode = getValue(*i);
4483 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4485 unsigned attrInd = i - CS.arg_begin() + 1;
4486 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4487 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4488 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4489 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4490 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4491 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4492 Entry.Alignment = CS.getParamAlignment(attrInd);
4493 Args.push_back(Entry);
4496 if (LandingPad && MMI) {
4497 // Insert a label before the invoke call to mark the try range. This can be
4498 // used to detect deletion of the invoke via the MachineModuleInfo.
4499 BeginLabel = MMI->NextLabelID();
4500 // Both PendingLoads and PendingExports must be flushed here;
4501 // this call might not return.
4503 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4504 getControlRoot(), BeginLabel));
4507 std::pair<SDValue,SDValue> Result =
4508 TLI.LowerCallTo(getRoot(), CS.getType(),
4509 CS.paramHasAttr(0, Attribute::SExt),
4510 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4511 CS.paramHasAttr(0, Attribute::InReg),
4512 CS.getCallingConv(),
4513 IsTailCall && PerformTailCallOpt,
4514 Callee, Args, DAG, getCurDebugLoc());
4515 if (CS.getType() != Type::VoidTy)
4516 setValue(CS.getInstruction(), Result.first);
4517 DAG.setRoot(Result.second);
4519 if (LandingPad && MMI) {
4520 // Insert a label at the end of the invoke call to mark the try range. This
4521 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4522 EndLabel = MMI->NextLabelID();
4523 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4524 getRoot(), EndLabel));
4526 // Inform MachineModuleInfo of range.
4527 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4532 void SelectionDAGLowering::visitCall(CallInst &I) {
4533 const char *RenameFn = 0;
4534 if (Function *F = I.getCalledFunction()) {
4535 if (F->isDeclaration()) {
4536 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4538 if (unsigned IID = II->getIntrinsicID(F)) {
4539 RenameFn = visitIntrinsicCall(I, IID);
4544 if (unsigned IID = F->getIntrinsicID()) {
4545 RenameFn = visitIntrinsicCall(I, IID);
4551 // Check for well-known libc/libm calls. If the function is internal, it
4552 // can't be a library call.
4553 unsigned NameLen = F->getNameLen();
4554 if (!F->hasLocalLinkage() && NameLen) {
4555 const char *NameStr = F->getNameStart();
4556 if (NameStr[0] == 'c' &&
4557 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4558 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4559 if (I.getNumOperands() == 3 && // Basic sanity checks.
4560 I.getOperand(1)->getType()->isFloatingPoint() &&
4561 I.getType() == I.getOperand(1)->getType() &&
4562 I.getType() == I.getOperand(2)->getType()) {
4563 SDValue LHS = getValue(I.getOperand(1));
4564 SDValue RHS = getValue(I.getOperand(2));
4565 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4566 LHS.getValueType(), LHS, RHS));
4569 } else if (NameStr[0] == 'f' &&
4570 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4571 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4572 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4573 if (I.getNumOperands() == 2 && // Basic sanity checks.
4574 I.getOperand(1)->getType()->isFloatingPoint() &&
4575 I.getType() == I.getOperand(1)->getType()) {
4576 SDValue Tmp = getValue(I.getOperand(1));
4577 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4578 Tmp.getValueType(), Tmp));
4581 } else if (NameStr[0] == 's' &&
4582 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4583 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4584 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4585 if (I.getNumOperands() == 2 && // Basic sanity checks.
4586 I.getOperand(1)->getType()->isFloatingPoint() &&
4587 I.getType() == I.getOperand(1)->getType()) {
4588 SDValue Tmp = getValue(I.getOperand(1));
4589 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4590 Tmp.getValueType(), Tmp));
4593 } else if (NameStr[0] == 'c' &&
4594 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4595 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4596 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4597 if (I.getNumOperands() == 2 && // Basic sanity checks.
4598 I.getOperand(1)->getType()->isFloatingPoint() &&
4599 I.getType() == I.getOperand(1)->getType()) {
4600 SDValue Tmp = getValue(I.getOperand(1));
4601 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4602 Tmp.getValueType(), Tmp));
4607 } else if (isa<InlineAsm>(I.getOperand(0))) {
4614 Callee = getValue(I.getOperand(0));
4616 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4618 LowerCallTo(&I, Callee, I.isTailCall());
4622 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4623 /// this value and returns the result as a ValueVT value. This uses
4624 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4625 /// If the Flag pointer is NULL, no flag is used.
4626 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4628 SDValue *Flag) const {
4629 // Assemble the legal parts into the final values.
4630 SmallVector<SDValue, 4> Values(ValueVTs.size());
4631 SmallVector<SDValue, 8> Parts;
4632 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4633 // Copy the legal parts from the registers.
4634 MVT ValueVT = ValueVTs[Value];
4635 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4636 MVT RegisterVT = RegVTs[Value];
4638 Parts.resize(NumRegs);
4639 for (unsigned i = 0; i != NumRegs; ++i) {
4642 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4644 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4645 *Flag = P.getValue(2);
4647 Chain = P.getValue(1);
4649 // If the source register was virtual and if we know something about it,
4650 // add an assert node.
4651 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4652 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4653 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4654 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4655 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4656 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4658 unsigned RegSize = RegisterVT.getSizeInBits();
4659 unsigned NumSignBits = LOI.NumSignBits;
4660 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4662 // FIXME: We capture more information than the dag can represent. For
4663 // now, just use the tightest assertzext/assertsext possible.
4665 MVT FromVT(MVT::Other);
4666 if (NumSignBits == RegSize)
4667 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4668 else if (NumZeroBits >= RegSize-1)
4669 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4670 else if (NumSignBits > RegSize-8)
4671 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4672 else if (NumZeroBits >= RegSize-8)
4673 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4674 else if (NumSignBits > RegSize-16)
4675 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4676 else if (NumZeroBits >= RegSize-16)
4677 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4678 else if (NumSignBits > RegSize-32)
4679 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4680 else if (NumZeroBits >= RegSize-32)
4681 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4683 if (FromVT != MVT::Other) {
4684 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4685 RegisterVT, P, DAG.getValueType(FromVT));
4694 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4695 NumRegs, RegisterVT, ValueVT);
4700 return DAG.getNode(ISD::MERGE_VALUES, dl,
4701 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4702 &Values[0], ValueVTs.size());
4705 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4706 /// specified value into the registers specified by this object. This uses
4707 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4708 /// If the Flag pointer is NULL, no flag is used.
4709 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4710 SDValue &Chain, SDValue *Flag) const {
4711 // Get the list of the values's legal parts.
4712 unsigned NumRegs = Regs.size();
4713 SmallVector<SDValue, 8> Parts(NumRegs);
4714 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4715 MVT ValueVT = ValueVTs[Value];
4716 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4717 MVT RegisterVT = RegVTs[Value];
4719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4720 &Parts[Part], NumParts, RegisterVT);
4724 // Copy the parts into the registers.
4725 SmallVector<SDValue, 8> Chains(NumRegs);
4726 for (unsigned i = 0; i != NumRegs; ++i) {
4729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4732 *Flag = Part.getValue(1);
4734 Chains[i] = Part.getValue(0);
4737 if (NumRegs == 1 || Flag)
4738 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4739 // flagged to it. That is the CopyToReg nodes and the user are considered
4740 // a single scheduling unit. If we create a TokenFactor and return it as
4741 // chain, then the TokenFactor is both a predecessor (operand) of the
4742 // user as well as a successor (the TF operands are flagged to the user).
4743 // c1, f1 = CopyToReg
4744 // c2, f2 = CopyToReg
4745 // c3 = TokenFactor c1, c2
4748 Chain = Chains[NumRegs-1];
4750 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4753 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4754 /// operand list. This adds the code marker and includes the number of
4755 /// values added into it.
4756 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4757 bool HasMatching,unsigned MatchingIdx,
4759 std::vector<SDValue> &Ops) const {
4760 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4761 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4762 unsigned Flag = Code | (Regs.size() << 3);
4764 Flag |= 0x80000000 | (MatchingIdx << 16);
4765 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4766 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4767 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4768 MVT RegisterVT = RegVTs[Value];
4769 for (unsigned i = 0; i != NumRegs; ++i) {
4770 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4771 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4776 /// isAllocatableRegister - If the specified register is safe to allocate,
4777 /// i.e. it isn't a stack pointer or some other special register, return the
4778 /// register class for the register. Otherwise, return null.
4779 static const TargetRegisterClass *
4780 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4781 const TargetLowering &TLI,
4782 const TargetRegisterInfo *TRI) {
4783 MVT FoundVT = MVT::Other;
4784 const TargetRegisterClass *FoundRC = 0;
4785 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4786 E = TRI->regclass_end(); RCI != E; ++RCI) {
4787 MVT ThisVT = MVT::Other;
4789 const TargetRegisterClass *RC = *RCI;
4790 // If none of the the value types for this register class are valid, we
4791 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4792 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4794 if (TLI.isTypeLegal(*I)) {
4795 // If we have already found this register in a different register class,
4796 // choose the one with the largest VT specified. For example, on
4797 // PowerPC, we favor f64 register classes over f32.
4798 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4805 if (ThisVT == MVT::Other) continue;
4807 // NOTE: This isn't ideal. In particular, this might allocate the
4808 // frame pointer in functions that need it (due to them not being taken
4809 // out of allocation, because a variable sized allocation hasn't been seen
4810 // yet). This is a slight code pessimization, but should still work.
4811 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4812 E = RC->allocation_order_end(MF); I != E; ++I)
4814 // We found a matching register class. Keep looking at others in case
4815 // we find one with larger registers that this physreg is also in.
4826 /// AsmOperandInfo - This contains information for each constraint that we are
4828 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4829 public TargetLowering::AsmOperandInfo {
4831 /// CallOperand - If this is the result output operand or a clobber
4832 /// this is null, otherwise it is the incoming operand to the CallInst.
4833 /// This gets modified as the asm is processed.
4834 SDValue CallOperand;
4836 /// AssignedRegs - If this is a register or register class operand, this
4837 /// contains the set of register corresponding to the operand.
4838 RegsForValue AssignedRegs;
4840 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4841 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4844 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4845 /// busy in OutputRegs/InputRegs.
4846 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4847 std::set<unsigned> &OutputRegs,
4848 std::set<unsigned> &InputRegs,
4849 const TargetRegisterInfo &TRI) const {
4851 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4852 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4855 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4856 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4860 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4861 /// corresponds to. If there is no Value* for this operand, it returns
4863 MVT getCallOperandValMVT(const TargetLowering &TLI,
4864 const TargetData *TD) const {
4865 if (CallOperandVal == 0) return MVT::Other;
4867 if (isa<BasicBlock>(CallOperandVal))
4868 return TLI.getPointerTy();
4870 const llvm::Type *OpTy = CallOperandVal->getType();
4872 // If this is an indirect operand, the operand is a pointer to the
4875 OpTy = cast<PointerType>(OpTy)->getElementType();
4877 // If OpTy is not a single value, it may be a struct/union that we
4878 // can tile with integers.
4879 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4880 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4889 OpTy = IntegerType::get(BitSize);
4894 return TLI.getValueType(OpTy, true);
4898 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4900 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4901 const TargetRegisterInfo &TRI) {
4902 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4904 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4905 for (; *Aliases; ++Aliases)
4906 Regs.insert(*Aliases);
4909 } // end llvm namespace.
4912 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4913 /// specified operand. We prefer to assign virtual registers, to allow the
4914 /// register allocator handle the assignment process. However, if the asm uses
4915 /// features that we can't model on machineinstrs, we have SDISel do the
4916 /// allocation. This produces generally horrible, but correct, code.
4918 /// OpInfo describes the operand.
4919 /// Input and OutputRegs are the set of already allocated physical registers.
4921 void SelectionDAGLowering::
4922 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4923 std::set<unsigned> &OutputRegs,
4924 std::set<unsigned> &InputRegs) {
4925 // Compute whether this value requires an input register, an output register,
4927 bool isOutReg = false;
4928 bool isInReg = false;
4929 switch (OpInfo.Type) {
4930 case InlineAsm::isOutput:
4933 // If there is an input constraint that matches this, we need to reserve
4934 // the input register so no other inputs allocate to it.
4935 isInReg = OpInfo.hasMatchingInput();
4937 case InlineAsm::isInput:
4941 case InlineAsm::isClobber:
4948 MachineFunction &MF = DAG.getMachineFunction();
4949 SmallVector<unsigned, 4> Regs;
4951 // If this is a constraint for a single physreg, or a constraint for a
4952 // register class, find it.
4953 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4954 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4955 OpInfo.ConstraintVT);
4957 unsigned NumRegs = 1;
4958 if (OpInfo.ConstraintVT != MVT::Other) {
4959 // If this is a FP input in an integer register (or visa versa) insert a bit
4960 // cast of the input value. More generally, handle any case where the input
4961 // value disagrees with the register class we plan to stick this in.
4962 if (OpInfo.Type == InlineAsm::isInput &&
4963 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4964 // Try to convert to the first MVT that the reg class contains. If the
4965 // types are identical size, use a bitcast to convert (e.g. two differing
4967 MVT RegVT = *PhysReg.second->vt_begin();
4968 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4969 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4970 RegVT, OpInfo.CallOperand);
4971 OpInfo.ConstraintVT = RegVT;
4972 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4973 // If the input is a FP value and we want it in FP registers, do a
4974 // bitcast to the corresponding integer type. This turns an f64 value
4975 // into i64, which can be passed with two i32 values on a 32-bit
4977 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4978 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4979 RegVT, OpInfo.CallOperand);
4980 OpInfo.ConstraintVT = RegVT;
4984 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4988 MVT ValueVT = OpInfo.ConstraintVT;
4990 // If this is a constraint for a specific physical register, like {r17},
4992 if (unsigned AssignedReg = PhysReg.first) {
4993 const TargetRegisterClass *RC = PhysReg.second;
4994 if (OpInfo.ConstraintVT == MVT::Other)
4995 ValueVT = *RC->vt_begin();
4997 // Get the actual register value type. This is important, because the user
4998 // may have asked for (e.g.) the AX register in i32 type. We need to
4999 // remember that AX is actually i16 to get the right extension.
5000 RegVT = *RC->vt_begin();
5002 // This is a explicit reference to a physical register.
5003 Regs.push_back(AssignedReg);
5005 // If this is an expanded reference, add the rest of the regs to Regs.
5007 TargetRegisterClass::iterator I = RC->begin();
5008 for (; *I != AssignedReg; ++I)
5009 assert(I != RC->end() && "Didn't find reg!");
5011 // Already added the first reg.
5013 for (; NumRegs; --NumRegs, ++I) {
5014 assert(I != RC->end() && "Ran out of registers to allocate!");
5018 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5019 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5020 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5024 // Otherwise, if this was a reference to an LLVM register class, create vregs
5025 // for this reference.
5026 if (const TargetRegisterClass *RC = PhysReg.second) {
5027 RegVT = *RC->vt_begin();
5028 if (OpInfo.ConstraintVT == MVT::Other)
5031 // Create the appropriate number of virtual registers.
5032 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5033 for (; NumRegs; --NumRegs)
5034 Regs.push_back(RegInfo.createVirtualRegister(RC));
5036 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5040 // This is a reference to a register class that doesn't directly correspond
5041 // to an LLVM register class. Allocate NumRegs consecutive, available,
5042 // registers from the class.
5043 std::vector<unsigned> RegClassRegs
5044 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5045 OpInfo.ConstraintVT);
5047 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5048 unsigned NumAllocated = 0;
5049 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5050 unsigned Reg = RegClassRegs[i];
5051 // See if this register is available.
5052 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5053 (isInReg && InputRegs.count(Reg))) { // Already used.
5054 // Make sure we find consecutive registers.
5059 // Check to see if this register is allocatable (i.e. don't give out the
5061 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5062 if (!RC) { // Couldn't allocate this register.
5063 // Reset NumAllocated to make sure we return consecutive registers.
5068 // Okay, this register is good, we can use it.
5071 // If we allocated enough consecutive registers, succeed.
5072 if (NumAllocated == NumRegs) {
5073 unsigned RegStart = (i-NumAllocated)+1;
5074 unsigned RegEnd = i+1;
5075 // Mark all of the allocated registers used.
5076 for (unsigned i = RegStart; i != RegEnd; ++i)
5077 Regs.push_back(RegClassRegs[i]);
5079 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5080 OpInfo.ConstraintVT);
5081 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5086 // Otherwise, we couldn't allocate enough registers for this.
5089 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5090 /// processed uses a memory 'm' constraint.
5092 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5093 const TargetLowering &TLI) {
5094 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5095 InlineAsm::ConstraintInfo &CI = CInfos[i];
5096 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5097 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5098 if (CType == TargetLowering::C_Memory)
5106 /// visitInlineAsm - Handle a call to an InlineAsm object.
5108 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5109 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5111 /// ConstraintOperands - Information about all of the constraints.
5112 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5114 // We won't need to flush pending loads if this asm doesn't touch
5115 // memory and is nonvolatile.
5116 SDValue Chain = IA->hasSideEffects() ? getRoot() : DAG.getRoot();
5119 std::set<unsigned> OutputRegs, InputRegs;
5121 // Do a prepass over the constraints, canonicalizing them, and building up the
5122 // ConstraintOperands list.
5123 std::vector<InlineAsm::ConstraintInfo>
5124 ConstraintInfos = IA->ParseConstraints();
5126 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5127 // Flush pending loads if this touches memory (includes clobbering it).
5128 // It's possible this is overly conservative.
5132 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5133 unsigned ResNo = 0; // ResNo - The result number of the next output.
5134 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5135 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5136 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5138 MVT OpVT = MVT::Other;
5140 // Compute the value type for each operand.
5141 switch (OpInfo.Type) {
5142 case InlineAsm::isOutput:
5143 // Indirect outputs just consume an argument.
5144 if (OpInfo.isIndirect) {
5145 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5149 // The return value of the call is this value. As such, there is no
5150 // corresponding argument.
5151 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5152 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5153 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5155 assert(ResNo == 0 && "Asm only has one result!");
5156 OpVT = TLI.getValueType(CS.getType());
5160 case InlineAsm::isInput:
5161 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5163 case InlineAsm::isClobber:
5168 // If this is an input or an indirect output, process the call argument.
5169 // BasicBlocks are labels, currently appearing only in asm's.
5170 if (OpInfo.CallOperandVal) {
5171 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5172 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5174 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5177 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5180 OpInfo.ConstraintVT = OpVT;
5183 // Second pass over the constraints: compute which constraint option to use
5184 // and assign registers to constraints that want a specific physreg.
5185 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5186 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5188 // If this is an output operand with a matching input operand, look up the
5189 // matching input. If their types mismatch, e.g. one is an integer, the
5190 // other is floating point, or their sizes are different, flag it as an
5192 if (OpInfo.hasMatchingInput()) {
5193 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5194 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5195 if ((OpInfo.ConstraintVT.isInteger() !=
5196 Input.ConstraintVT.isInteger()) ||
5197 (OpInfo.ConstraintVT.getSizeInBits() !=
5198 Input.ConstraintVT.getSizeInBits())) {
5199 cerr << "llvm: error: Unsupported asm: input constraint with a "
5200 << "matching output constraint of incompatible type!\n";
5203 Input.ConstraintVT = OpInfo.ConstraintVT;
5207 // Compute the constraint code and ConstraintType to use.
5208 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5210 // If this is a memory input, and if the operand is not indirect, do what we
5211 // need to to provide an address for the memory input.
5212 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5213 !OpInfo.isIndirect) {
5214 assert(OpInfo.Type == InlineAsm::isInput &&
5215 "Can only indirectify direct input operands!");
5217 // Memory operands really want the address of the value. If we don't have
5218 // an indirect input, put it in the constpool if we can, otherwise spill
5219 // it to a stack slot.
5221 // If the operand is a float, integer, or vector constant, spill to a
5222 // constant pool entry to get its address.
5223 Value *OpVal = OpInfo.CallOperandVal;
5224 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5225 isa<ConstantVector>(OpVal)) {
5226 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5227 TLI.getPointerTy());
5229 // Otherwise, create a stack slot and emit a store to it before the
5231 const Type *Ty = OpVal->getType();
5232 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5233 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5234 MachineFunction &MF = DAG.getMachineFunction();
5235 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5236 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5237 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5238 OpInfo.CallOperand, StackSlot, NULL, 0);
5239 OpInfo.CallOperand = StackSlot;
5242 // There is no longer a Value* corresponding to this operand.
5243 OpInfo.CallOperandVal = 0;
5244 // It is now an indirect operand.
5245 OpInfo.isIndirect = true;
5248 // If this constraint is for a specific register, allocate it before
5250 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5251 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5253 ConstraintInfos.clear();
5256 // Second pass - Loop over all of the operands, assigning virtual or physregs
5257 // to register class operands.
5258 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5259 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5261 // C_Register operands have already been allocated, Other/Memory don't need
5263 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5264 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5267 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5268 std::vector<SDValue> AsmNodeOperands;
5269 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5270 AsmNodeOperands.push_back(
5271 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5274 // Loop over all of the inputs, copying the operand values into the
5275 // appropriate registers and processing the output regs.
5276 RegsForValue RetValRegs;
5278 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5279 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5281 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5282 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5284 switch (OpInfo.Type) {
5285 case InlineAsm::isOutput: {
5286 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5287 OpInfo.ConstraintType != TargetLowering::C_Register) {
5288 // Memory output, or 'other' output (e.g. 'X' constraint).
5289 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5291 // Add information to the INLINEASM node to know about this output.
5292 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5293 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5294 TLI.getPointerTy()));
5295 AsmNodeOperands.push_back(OpInfo.CallOperand);
5299 // Otherwise, this is a register or register class output.
5301 // Copy the output from the appropriate register. Find a register that
5303 if (OpInfo.AssignedRegs.Regs.empty()) {
5304 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5305 << OpInfo.ConstraintCode << "'!\n";
5309 // If this is an indirect operand, store through the pointer after the
5311 if (OpInfo.isIndirect) {
5312 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5313 OpInfo.CallOperandVal));
5315 // This is the result value of the call.
5316 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5317 // Concatenate this output onto the outputs list.
5318 RetValRegs.append(OpInfo.AssignedRegs);
5321 // Add information to the INLINEASM node to know that this register is
5323 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5324 6 /* EARLYCLOBBER REGDEF */ :
5328 DAG, AsmNodeOperands);
5331 case InlineAsm::isInput: {
5332 SDValue InOperandVal = OpInfo.CallOperand;
5334 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5335 // If this is required to match an output register we have already set,
5336 // just use its register.
5337 unsigned OperandNo = OpInfo.getMatchedOperand();
5339 // Scan until we find the definition we already emitted of this operand.
5340 // When we find it, create a RegsForValue operand.
5341 unsigned CurOp = 2; // The first operand.
5342 for (; OperandNo; --OperandNo) {
5343 // Advance to the next operand.
5345 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5346 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5347 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5348 (OpFlag & 7) == 4 /*MEM*/) &&
5349 "Skipped past definitions?");
5350 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5354 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5355 if ((OpFlag & 7) == 2 /*REGDEF*/
5356 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5357 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5358 RegsForValue MatchedRegs;
5359 MatchedRegs.TLI = &TLI;
5360 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5361 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5362 MatchedRegs.RegVTs.push_back(RegVT);
5363 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5364 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5367 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5369 // Use the produced MatchedRegs object to
5370 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5372 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5373 true, OpInfo.getMatchedOperand(),
5374 DAG, AsmNodeOperands);
5377 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5378 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5379 "Unexpected number of operands");
5380 // Add information to the INLINEASM node to know about this input.
5381 // See InlineAsm.h isUseOperandTiedToDef.
5382 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5383 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5384 TLI.getPointerTy()));
5385 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5390 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5391 assert(!OpInfo.isIndirect &&
5392 "Don't know how to handle indirect other inputs yet!");
5394 std::vector<SDValue> Ops;
5395 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5396 hasMemory, Ops, DAG);
5398 cerr << "llvm: error: Invalid operand for inline asm constraint '"
5399 << OpInfo.ConstraintCode << "'!\n";
5403 // Add information to the INLINEASM node to know about this input.
5404 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5405 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5406 TLI.getPointerTy()));
5407 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5409 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5410 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5411 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5412 "Memory operands expect pointer values");
5414 // Add information to the INLINEASM node to know about this input.
5415 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5416 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5417 TLI.getPointerTy()));
5418 AsmNodeOperands.push_back(InOperandVal);
5422 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5423 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5424 "Unknown constraint type!");
5425 assert(!OpInfo.isIndirect &&
5426 "Don't know how to handle indirect register inputs yet!");
5428 // Copy the input into the appropriate registers.
5429 if (OpInfo.AssignedRegs.Regs.empty()) {
5430 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5431 << OpInfo.ConstraintCode << "'!\n";
5435 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5438 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5439 DAG, AsmNodeOperands);
5442 case InlineAsm::isClobber: {
5443 // Add the clobbered value to the operand list, so that the register
5444 // allocator is aware that the physreg got clobbered.
5445 if (!OpInfo.AssignedRegs.Regs.empty())
5446 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5447 false, 0, DAG,AsmNodeOperands);
5453 // Finish up input operands.
5454 AsmNodeOperands[0] = Chain;
5455 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5457 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5458 DAG.getVTList(MVT::Other, MVT::Flag),
5459 &AsmNodeOperands[0], AsmNodeOperands.size());
5460 Flag = Chain.getValue(1);
5462 // If this asm returns a register value, copy the result from that register
5463 // and set it as the value of the call.
5464 if (!RetValRegs.Regs.empty()) {
5465 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5468 // FIXME: Why don't we do this for inline asms with MRVs?
5469 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5470 MVT ResultType = TLI.getValueType(CS.getType());
5472 // If any of the results of the inline asm is a vector, it may have the
5473 // wrong width/num elts. This can happen for register classes that can
5474 // contain multiple different value types. The preg or vreg allocated may
5475 // not have the same VT as was expected. Convert it to the right type
5476 // with bit_convert.
5477 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5478 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5481 } else if (ResultType != Val.getValueType() &&
5482 ResultType.isInteger() && Val.getValueType().isInteger()) {
5483 // If a result value was tied to an input value, the computed result may
5484 // have a wider width than the expected result. Extract the relevant
5486 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5489 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5492 setValue(CS.getInstruction(), Val);
5493 // Don't need to use this as a chain in this case.
5494 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5498 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5500 // Process indirect outputs, first output all of the flagged copies out of
5502 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5503 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5504 Value *Ptr = IndirectStoresToEmit[i].second;
5505 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5507 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5510 // Emit the non-flagged stores from the physregs.
5511 SmallVector<SDValue, 8> OutChains;
5512 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5513 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5514 StoresToEmit[i].first,
5515 getValue(StoresToEmit[i].second),
5516 StoresToEmit[i].second, 0));
5517 if (!OutChains.empty())
5518 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5519 &OutChains[0], OutChains.size());
5524 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5525 SDValue Src = getValue(I.getOperand(0));
5527 // Scale up by the type size in the original i32 type width. Various
5528 // mid-level optimizers may make assumptions about demanded bits etc from the
5529 // i32-ness of the optimizer: we do not want to promote to i64 and then
5530 // multiply on 64-bit targets.
5531 // FIXME: Malloc inst should go away: PR715.
5532 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5533 if (ElementSize != 1)
5534 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5535 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5537 MVT IntPtr = TLI.getPointerTy();
5539 if (IntPtr.bitsLT(Src.getValueType()))
5540 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5541 else if (IntPtr.bitsGT(Src.getValueType()))
5542 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5544 TargetLowering::ArgListTy Args;
5545 TargetLowering::ArgListEntry Entry;
5547 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5548 Args.push_back(Entry);
5550 std::pair<SDValue,SDValue> Result =
5551 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5552 CallingConv::C, PerformTailCallOpt,
5553 DAG.getExternalSymbol("malloc", IntPtr),
5554 Args, DAG, getCurDebugLoc());
5555 setValue(&I, Result.first); // Pointers always fit in registers
5556 DAG.setRoot(Result.second);
5559 void SelectionDAGLowering::visitFree(FreeInst &I) {
5560 TargetLowering::ArgListTy Args;
5561 TargetLowering::ArgListEntry Entry;
5562 Entry.Node = getValue(I.getOperand(0));
5563 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5564 Args.push_back(Entry);
5565 MVT IntPtr = TLI.getPointerTy();
5566 std::pair<SDValue,SDValue> Result =
5567 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5568 CallingConv::C, PerformTailCallOpt,
5569 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5571 DAG.setRoot(Result.second);
5574 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5575 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5576 MVT::Other, getRoot(),
5577 getValue(I.getOperand(1)),
5578 DAG.getSrcValue(I.getOperand(1))));
5581 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5582 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5583 getRoot(), getValue(I.getOperand(0)),
5584 DAG.getSrcValue(I.getOperand(0)));
5586 DAG.setRoot(V.getValue(1));
5589 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5590 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5591 MVT::Other, getRoot(),
5592 getValue(I.getOperand(1)),
5593 DAG.getSrcValue(I.getOperand(1))));
5596 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5597 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5598 MVT::Other, getRoot(),
5599 getValue(I.getOperand(1)),
5600 getValue(I.getOperand(2)),
5601 DAG.getSrcValue(I.getOperand(1)),
5602 DAG.getSrcValue(I.getOperand(2))));
5605 /// TargetLowering::LowerArguments - This is the default LowerArguments
5606 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5607 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5608 /// integrated into SDISel.
5609 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5610 SmallVectorImpl<SDValue> &ArgValues,
5612 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5613 SmallVector<SDValue, 3+16> Ops;
5614 Ops.push_back(DAG.getRoot());
5615 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5616 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5618 // Add one result value for each formal argument.
5619 SmallVector<MVT, 16> RetVals;
5621 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5623 SmallVector<MVT, 4> ValueVTs;
5624 ComputeValueVTs(*this, I->getType(), ValueVTs);
5625 for (unsigned Value = 0, NumValues = ValueVTs.size();
5626 Value != NumValues; ++Value) {
5627 MVT VT = ValueVTs[Value];
5628 const Type *ArgTy = VT.getTypeForMVT();
5629 ISD::ArgFlagsTy Flags;
5630 unsigned OriginalAlignment =
5631 getTargetData()->getABITypeAlignment(ArgTy);
5633 if (F.paramHasAttr(j, Attribute::ZExt))
5635 if (F.paramHasAttr(j, Attribute::SExt))
5637 if (F.paramHasAttr(j, Attribute::InReg))
5639 if (F.paramHasAttr(j, Attribute::StructRet))
5641 if (F.paramHasAttr(j, Attribute::ByVal)) {
5643 const PointerType *Ty = cast<PointerType>(I->getType());
5644 const Type *ElementTy = Ty->getElementType();
5645 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5646 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5647 // For ByVal, alignment should be passed from FE. BE will guess if
5648 // this info is not there but there are cases it cannot get right.
5649 if (F.getParamAlignment(j))
5650 FrameAlign = F.getParamAlignment(j);
5651 Flags.setByValAlign(FrameAlign);
5652 Flags.setByValSize(FrameSize);
5654 if (F.paramHasAttr(j, Attribute::Nest))
5656 Flags.setOrigAlign(OriginalAlignment);
5658 MVT RegisterVT = getRegisterType(VT);
5659 unsigned NumRegs = getNumRegisters(VT);
5660 for (unsigned i = 0; i != NumRegs; ++i) {
5661 RetVals.push_back(RegisterVT);
5662 ISD::ArgFlagsTy MyFlags = Flags;
5663 if (NumRegs > 1 && i == 0)
5665 // if it isn't first piece, alignment must be 1
5667 MyFlags.setOrigAlign(1);
5668 Ops.push_back(DAG.getArgFlags(MyFlags));
5673 RetVals.push_back(MVT::Other);
5676 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5677 DAG.getVTList(&RetVals[0], RetVals.size()),
5678 &Ops[0], Ops.size()).getNode();
5680 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5681 // allows exposing the loads that may be part of the argument access to the
5682 // first DAGCombiner pass.
5683 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5685 // The number of results should match up, except that the lowered one may have
5686 // an extra flag result.
5687 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5688 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5689 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5690 && "Lowering produced unexpected number of results!");
5692 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5693 if (Result != TmpRes.getNode() && Result->use_empty()) {
5694 HandleSDNode Dummy(DAG.getRoot());
5695 DAG.RemoveDeadNode(Result);
5698 Result = TmpRes.getNode();
5700 unsigned NumArgRegs = Result->getNumValues() - 1;
5701 DAG.setRoot(SDValue(Result, NumArgRegs));
5703 // Set up the return result vector.
5706 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5708 SmallVector<MVT, 4> ValueVTs;
5709 ComputeValueVTs(*this, I->getType(), ValueVTs);
5710 for (unsigned Value = 0, NumValues = ValueVTs.size();
5711 Value != NumValues; ++Value) {
5712 MVT VT = ValueVTs[Value];
5713 MVT PartVT = getRegisterType(VT);
5715 unsigned NumParts = getNumRegisters(VT);
5716 SmallVector<SDValue, 4> Parts(NumParts);
5717 for (unsigned j = 0; j != NumParts; ++j)
5718 Parts[j] = SDValue(Result, i++);
5720 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5721 if (F.paramHasAttr(Idx, Attribute::SExt))
5722 AssertOp = ISD::AssertSext;
5723 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5724 AssertOp = ISD::AssertZext;
5726 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5727 PartVT, VT, AssertOp));
5730 assert(i == NumArgRegs && "Argument register count mismatch!");
5734 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5735 /// implementation, which just inserts an ISD::CALL node, which is later custom
5736 /// lowered by the target to something concrete. FIXME: When all targets are
5737 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5738 std::pair<SDValue, SDValue>
5739 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5740 bool RetSExt, bool RetZExt, bool isVarArg,
5742 unsigned CallingConv, bool isTailCall,
5744 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5745 assert((!isTailCall || PerformTailCallOpt) &&
5746 "isTailCall set when tail-call optimizations are disabled!");
5748 SmallVector<SDValue, 32> Ops;
5749 Ops.push_back(Chain); // Op#0 - Chain
5750 Ops.push_back(Callee);
5752 // Handle all of the outgoing arguments.
5753 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5754 SmallVector<MVT, 4> ValueVTs;
5755 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5756 for (unsigned Value = 0, NumValues = ValueVTs.size();
5757 Value != NumValues; ++Value) {
5758 MVT VT = ValueVTs[Value];
5759 const Type *ArgTy = VT.getTypeForMVT();
5760 SDValue Op = SDValue(Args[i].Node.getNode(),
5761 Args[i].Node.getResNo() + Value);
5762 ISD::ArgFlagsTy Flags;
5763 unsigned OriginalAlignment =
5764 getTargetData()->getABITypeAlignment(ArgTy);
5770 if (Args[i].isInReg)
5774 if (Args[i].isByVal) {
5776 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5777 const Type *ElementTy = Ty->getElementType();
5778 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5779 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5780 // For ByVal, alignment should come from FE. BE will guess if this
5781 // info is not there but there are cases it cannot get right.
5782 if (Args[i].Alignment)
5783 FrameAlign = Args[i].Alignment;
5784 Flags.setByValAlign(FrameAlign);
5785 Flags.setByValSize(FrameSize);
5789 Flags.setOrigAlign(OriginalAlignment);
5791 MVT PartVT = getRegisterType(VT);
5792 unsigned NumParts = getNumRegisters(VT);
5793 SmallVector<SDValue, 4> Parts(NumParts);
5794 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5797 ExtendKind = ISD::SIGN_EXTEND;
5798 else if (Args[i].isZExt)
5799 ExtendKind = ISD::ZERO_EXTEND;
5801 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5803 for (unsigned i = 0; i != NumParts; ++i) {
5804 // if it isn't first piece, alignment must be 1
5805 ISD::ArgFlagsTy MyFlags = Flags;
5806 if (NumParts > 1 && i == 0)
5809 MyFlags.setOrigAlign(1);
5811 Ops.push_back(Parts[i]);
5812 Ops.push_back(DAG.getArgFlags(MyFlags));
5817 // Figure out the result value types. We start by making a list of
5818 // the potentially illegal return value types.
5819 SmallVector<MVT, 4> LoweredRetTys;
5820 SmallVector<MVT, 4> RetTys;
5821 ComputeValueVTs(*this, RetTy, RetTys);
5823 // Then we translate that to a list of legal types.
5824 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5826 MVT RegisterVT = getRegisterType(VT);
5827 unsigned NumRegs = getNumRegisters(VT);
5828 for (unsigned i = 0; i != NumRegs; ++i)
5829 LoweredRetTys.push_back(RegisterVT);
5832 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5834 // Create the CALL node.
5835 SDValue Res = DAG.getCall(CallingConv, dl,
5836 isVarArg, isTailCall, isInreg,
5837 DAG.getVTList(&LoweredRetTys[0],
5838 LoweredRetTys.size()),
5841 Chain = Res.getValue(LoweredRetTys.size() - 1);
5843 // Gather up the call result into a single value.
5844 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5845 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5848 AssertOp = ISD::AssertSext;
5850 AssertOp = ISD::AssertZext;
5852 SmallVector<SDValue, 4> ReturnValues;
5854 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5856 MVT RegisterVT = getRegisterType(VT);
5857 unsigned NumRegs = getNumRegisters(VT);
5858 unsigned RegNoEnd = NumRegs + RegNo;
5859 SmallVector<SDValue, 4> Results;
5860 for (; RegNo != RegNoEnd; ++RegNo)
5861 Results.push_back(Res.getValue(RegNo));
5862 SDValue ReturnValue =
5863 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5865 ReturnValues.push_back(ReturnValue);
5867 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5868 DAG.getVTList(&RetTys[0], RetTys.size()),
5869 &ReturnValues[0], ReturnValues.size());
5872 return std::make_pair(Res, Chain);
5875 void TargetLowering::LowerOperationWrapper(SDNode *N,
5876 SmallVectorImpl<SDValue> &Results,
5877 SelectionDAG &DAG) {
5878 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5880 Results.push_back(Res);
5883 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5884 assert(0 && "LowerOperation not implemented for this target!");
5890 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5891 SDValue Op = getValue(V);
5892 assert((Op.getOpcode() != ISD::CopyFromReg ||
5893 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5894 "Copy from a reg to the same reg!");
5895 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5897 RegsForValue RFV(TLI, Reg, V->getType());
5898 SDValue Chain = DAG.getEntryNode();
5899 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5900 PendingExports.push_back(Chain);
5903 #include "llvm/CodeGen/SelectionDAGISel.h"
5905 void SelectionDAGISel::
5906 LowerArguments(BasicBlock *LLVMBB) {
5907 // If this is the entry block, emit arguments.
5908 Function &F = *LLVMBB->getParent();
5909 SDValue OldRoot = SDL->DAG.getRoot();
5910 SmallVector<SDValue, 16> Args;
5911 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5914 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5916 SmallVector<MVT, 4> ValueVTs;
5917 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5918 unsigned NumValues = ValueVTs.size();
5919 if (!AI->use_empty()) {
5920 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5921 SDL->getCurDebugLoc()));
5922 // If this argument is live outside of the entry block, insert a copy from
5923 // whereever we got it to the vreg that other BB's will reference it as.
5924 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5925 if (VMI != FuncInfo->ValueMap.end()) {
5926 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5932 // Finally, if the target has anything special to do, allow it to do so.
5933 // FIXME: this should insert code into the DAG!
5934 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5937 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5938 /// ensure constants are generated when needed. Remember the virtual registers
5939 /// that need to be added to the Machine PHI nodes as input. We cannot just
5940 /// directly add them, because expansion might result in multiple MBB's for one
5941 /// BB. As such, the start of the BB might correspond to a different MBB than
5945 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5946 TerminatorInst *TI = LLVMBB->getTerminator();
5948 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5950 // Check successor nodes' PHI nodes that expect a constant to be available
5952 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5953 BasicBlock *SuccBB = TI->getSuccessor(succ);
5954 if (!isa<PHINode>(SuccBB->begin())) continue;
5955 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5957 // If this terminator has multiple identical successors (common for
5958 // switches), only handle each succ once.
5959 if (!SuccsHandled.insert(SuccMBB)) continue;
5961 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5964 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5965 // nodes and Machine PHI nodes, but the incoming operands have not been
5967 for (BasicBlock::iterator I = SuccBB->begin();
5968 (PN = dyn_cast<PHINode>(I)); ++I) {
5969 // Ignore dead phi's.
5970 if (PN->use_empty()) continue;
5973 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5975 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5976 unsigned &RegOut = SDL->ConstantsOut[C];
5978 RegOut = FuncInfo->CreateRegForValue(C);
5979 SDL->CopyValueToVirtualRegister(C, RegOut);
5983 Reg = FuncInfo->ValueMap[PHIOp];
5985 assert(isa<AllocaInst>(PHIOp) &&
5986 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5987 "Didn't codegen value into a register!??");
5988 Reg = FuncInfo->CreateRegForValue(PHIOp);
5989 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5993 // Remember that this register needs to added to the machine PHI node as
5994 // the input for this MBB.
5995 SmallVector<MVT, 4> ValueVTs;
5996 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5997 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5998 MVT VT = ValueVTs[vti];
5999 unsigned NumRegisters = TLI.getNumRegisters(VT);
6000 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6001 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6002 Reg += NumRegisters;
6006 SDL->ConstantsOut.clear();
6009 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6010 /// supports legal types, and it emits MachineInstrs directly instead of
6011 /// creating SelectionDAG nodes.
6014 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6016 TerminatorInst *TI = LLVMBB->getTerminator();
6018 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6019 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6021 // Check successor nodes' PHI nodes that expect a constant to be available
6023 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6024 BasicBlock *SuccBB = TI->getSuccessor(succ);
6025 if (!isa<PHINode>(SuccBB->begin())) continue;
6026 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6028 // If this terminator has multiple identical successors (common for
6029 // switches), only handle each succ once.
6030 if (!SuccsHandled.insert(SuccMBB)) continue;
6032 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6035 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6036 // nodes and Machine PHI nodes, but the incoming operands have not been
6038 for (BasicBlock::iterator I = SuccBB->begin();
6039 (PN = dyn_cast<PHINode>(I)); ++I) {
6040 // Ignore dead phi's.
6041 if (PN->use_empty()) continue;
6043 // Only handle legal types. Two interesting things to note here. First,
6044 // by bailing out early, we may leave behind some dead instructions,
6045 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6046 // own moves. Second, this check is necessary becuase FastISel doesn't
6047 // use CreateRegForValue to create registers, so it always creates
6048 // exactly one register for each non-void instruction.
6049 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6050 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6053 VT = TLI.getTypeToTransformTo(VT);
6055 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6060 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6062 unsigned Reg = F->getRegForValue(PHIOp);
6064 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6067 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));