1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 /// LimitFloatPrecision - Generate low-precision inline sequences for
58 /// some float libcalls (6, 8 or 12 bits).
59 static unsigned LimitFloatPrecision;
61 static cl::opt<unsigned, true>
62 LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
68 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
69 /// of insertvalue or extractvalue indices that identify a member, return
70 /// the linearized index of the start of the member.
72 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
84 EE = STy->element_end();
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 // We haven't found the type we're looking for, so keep searching.
106 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107 /// MVTs that represent all the individual underlying
108 /// non-aggregate types that comprise it.
110 /// If Offsets is non-null, it points to a vector to be filled in
111 /// with the in-memory offsets of each of the individual values.
113 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
122 EE = STy->element_end();
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
137 // Interpret void as zero return values.
138 if (Ty == Type::VoidTy)
140 // Base case: we can get an MVT for this LLVM IR type.
141 ValueVTs.push_back(TLI.getValueType(Ty));
143 Offsets->push_back(StartingOffset);
147 /// RegsForValue - This struct represents the registers (physical or virtual)
148 /// that a particular set of values is assigned, and the type information about
149 /// the value. The most common situation is to represent one value at a time,
150 /// but struct or array values are handled element-wise as multiple values.
151 /// The splitting of aggregates is performed recursively, so that we never
152 /// have aggregate-typed registers. The values at this point do not necessarily
153 /// have legal types, so each value may require one or more registers of some
156 struct VISIBILITY_HIDDEN RegsForValue {
157 /// TLI - The TargetLowering object.
159 const TargetLowering *TLI;
161 /// ValueVTs - The value types of the values, which may not be legal, and
162 /// may need be promoted or synthesized from one or more registers.
164 SmallVector<MVT, 4> ValueVTs;
166 /// RegVTs - The value types of the registers. This is the same size as
167 /// ValueVTs and it records, for each value, what the type of the assigned
168 /// register or registers are. (Individual values are never synthesized
169 /// from more than one type of register.)
171 /// With virtual registers, the contents of RegVTs is redundant with TLI's
172 /// getRegisterType member function, however when with physical registers
173 /// it is necessary to have a separate record of the types.
175 SmallVector<MVT, 4> RegVTs;
177 /// Regs - This list holds the registers assigned to the values.
178 /// Each legal or promoted value requires one register, and each
179 /// expanded value requires multiple registers.
181 SmallVector<unsigned, 4> Regs;
183 RegsForValue() : TLI(0) {}
185 RegsForValue(const TargetLowering &tli,
186 const SmallVector<unsigned, 4> ®s,
187 MVT regvt, MVT valuevt)
188 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
189 RegsForValue(const TargetLowering &tli,
190 const SmallVector<unsigned, 4> ®s,
191 const SmallVector<MVT, 4> ®vts,
192 const SmallVector<MVT, 4> &valuevts)
193 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
194 RegsForValue(const TargetLowering &tli,
195 unsigned Reg, const Type *Ty) : TLI(&tli) {
196 ComputeValueVTs(tli, Ty, ValueVTs);
198 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
199 MVT ValueVT = ValueVTs[Value];
200 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
201 MVT RegisterVT = TLI->getRegisterType(ValueVT);
202 for (unsigned i = 0; i != NumRegs; ++i)
203 Regs.push_back(Reg + i);
204 RegVTs.push_back(RegisterVT);
209 /// append - Add the specified values to this one.
210 void append(const RegsForValue &RHS) {
212 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
213 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
214 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
218 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
219 /// this value and returns the result as a ValueVTs value. This uses
220 /// Chain/Flag as the input and updates them for the output Chain/Flag.
221 /// If the Flag pointer is NULL, no flag is used.
222 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
223 SDValue &Chain, SDValue *Flag) const;
225 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
226 /// specified value into the registers specified by this object. This uses
227 /// Chain/Flag as the input and updates them for the output Chain/Flag.
228 /// If the Flag pointer is NULL, no flag is used.
229 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
230 SDValue &Chain, SDValue *Flag) const;
232 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
233 /// operand list. This adds the code marker, matching input operand index
234 /// (if applicable), and includes the number of values added into it.
235 void AddInlineAsmOperands(unsigned Code,
236 bool HasMatching, unsigned MatchingIdx,
237 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
241 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
242 /// PHI nodes or outside of the basic block that defines it, or used by a
243 /// switch or atomic instruction, which may expand to multiple basic blocks.
244 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
245 if (isa<PHINode>(I)) return true;
246 BasicBlock *BB = I->getParent();
247 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
248 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
253 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
254 /// entry block, return true. This includes arguments used by switches, since
255 /// the switch may expand into multiple basic blocks.
256 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
257 // With FastISel active, we may be splitting blocks, so force creation
258 // of virtual registers for all non-dead arguments.
259 // Don't force virtual registers for byval arguments though, because
260 // fast-isel can't handle those in all cases.
261 if (EnableFastISel && !A->hasByValAttr())
262 return A->use_empty();
264 BasicBlock *Entry = A->getParent()->begin();
265 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
266 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
267 return false; // Use not in entry block.
271 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
275 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
277 bool EnableFastISel) {
280 RegInfo = &MF->getRegInfo();
282 // Create a vreg for each argument register that is not dead and is used
283 // outside of the entry block for the function.
284 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
286 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
287 InitializeRegForValue(AI);
289 // Initialize the mapping of values to registers. This is only set up for
290 // instruction values that are used outside of the block that defines
292 Function::iterator BB = Fn->begin(), EB = Fn->end();
293 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
294 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
295 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
296 const Type *Ty = AI->getAllocatedType();
297 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
299 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
302 TySize *= CUI->getZExtValue(); // Get total allocated size.
303 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
304 StaticAllocaMap[AI] =
305 MF->getFrameInfo()->CreateStackObject(TySize, Align);
308 for (; BB != EB; ++BB)
309 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
310 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
311 if (!isa<AllocaInst>(I) ||
312 !StaticAllocaMap.count(cast<AllocaInst>(I)))
313 InitializeRegForValue(I);
315 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
316 // also creates the initial PHI MachineInstrs, though none of the input
317 // operands are populated.
318 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
319 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
323 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
327 for (BasicBlock::iterator
328 I = BB->begin(), E = BB->end(); I != E; ++I) {
329 if (CallInst *CI = dyn_cast<CallInst>(I)) {
330 if (Function *F = CI->getCalledFunction()) {
331 switch (F->getIntrinsicID()) {
333 case Intrinsic::dbg_stoppoint: {
334 DwarfWriter *DW = DAG.getDwarfWriter();
335 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
337 if (DW && DW->ValidDebugInfo(SPI->getContext(),
338 CodeGenOpt::Default)) {
339 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
341 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
343 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
346 DL = DebugLoc::get(idx);
351 case Intrinsic::dbg_func_start: {
352 DwarfWriter *DW = DAG.getDwarfWriter();
354 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
355 Value *SP = FSI->getSubprogram();
357 if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
358 DISubprogram Subprogram(cast<GlobalVariable>(SP));
359 DICompileUnit CU(Subprogram.getCompileUnit());
361 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
363 unsigned Line = Subprogram.getLineNumber();
364 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
374 PN = dyn_cast<PHINode>(I);
375 if (!PN || PN->use_empty()) continue;
377 unsigned PHIReg = ValueMap[PN];
378 assert(PHIReg && "PHI node does not have an assigned virtual register!");
380 SmallVector<MVT, 4> ValueVTs;
381 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
382 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
383 MVT VT = ValueVTs[vti];
384 unsigned NumRegisters = TLI.getNumRegisters(VT);
385 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
386 for (unsigned i = 0; i != NumRegisters; ++i)
387 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
388 PHIReg += NumRegisters;
394 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
395 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
398 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
399 /// the correctly promoted or expanded types. Assign these registers
400 /// consecutive vreg numbers and return the first assigned number.
402 /// In the case that the given value has struct or array type, this function
403 /// will assign registers for each member or element.
405 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
406 SmallVector<MVT, 4> ValueVTs;
407 ComputeValueVTs(TLI, V->getType(), ValueVTs);
409 unsigned FirstReg = 0;
410 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
411 MVT ValueVT = ValueVTs[Value];
412 MVT RegisterVT = TLI.getRegisterType(ValueVT);
414 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
415 for (unsigned i = 0; i != NumRegs; ++i) {
416 unsigned R = MakeReg(RegisterVT);
417 if (!FirstReg) FirstReg = R;
423 /// getCopyFromParts - Create a value that contains the specified legal parts
424 /// combined into the value they represent. If the parts combine to a type
425 /// larger then ValueVT then AssertOp can be used to specify whether the extra
426 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
427 /// (ISD::AssertSext).
428 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
429 const SDValue *Parts,
430 unsigned NumParts, MVT PartVT, MVT ValueVT,
431 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
432 assert(NumParts > 0 && "No parts to assemble!");
433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
434 SDValue Val = Parts[0];
437 // Assemble the value from multiple parts.
438 if (!ValueVT.isVector()) {
439 unsigned PartBits = PartVT.getSizeInBits();
440 unsigned ValueBits = ValueVT.getSizeInBits();
442 // Assemble the power of 2 part.
443 unsigned RoundParts = NumParts & (NumParts - 1) ?
444 1 << Log2_32(NumParts) : NumParts;
445 unsigned RoundBits = PartBits * RoundParts;
446 MVT RoundVT = RoundBits == ValueBits ?
447 ValueVT : MVT::getIntegerVT(RoundBits);
450 MVT HalfVT = ValueVT.isInteger() ?
451 MVT::getIntegerVT(RoundBits/2) :
452 MVT::getFloatingPointVT(RoundBits/2);
454 if (RoundParts > 2) {
455 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
456 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
459 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
460 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
462 if (TLI.isBigEndian())
464 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
466 if (RoundParts < NumParts) {
467 // Assemble the trailing non-power-of-2 part.
468 unsigned OddParts = NumParts - RoundParts;
469 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
470 Hi = getCopyFromParts(DAG, dl,
471 Parts+RoundParts, OddParts, PartVT, OddVT);
473 // Combine the round and odd parts.
475 if (TLI.isBigEndian())
477 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
478 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
479 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
480 DAG.getConstant(Lo.getValueType().getSizeInBits(),
481 TLI.getPointerTy()));
482 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
483 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
486 // Handle a multi-element vector.
487 MVT IntermediateVT, RegisterVT;
488 unsigned NumIntermediates;
490 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
492 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
493 NumParts = NumRegs; // Silence a compiler warning.
494 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
495 assert(RegisterVT == Parts[0].getValueType() &&
496 "Part type doesn't match part!");
498 // Assemble the parts into intermediate operands.
499 SmallVector<SDValue, 8> Ops(NumIntermediates);
500 if (NumIntermediates == NumParts) {
501 // If the register was not expanded, truncate or copy the value,
503 for (unsigned i = 0; i != NumParts; ++i)
504 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
505 PartVT, IntermediateVT);
506 } else if (NumParts > 0) {
507 // If the intermediate type was expanded, build the intermediate operands
509 assert(NumParts % NumIntermediates == 0 &&
510 "Must expand into a divisible number of parts!");
511 unsigned Factor = NumParts / NumIntermediates;
512 for (unsigned i = 0; i != NumIntermediates; ++i)
513 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
514 PartVT, IntermediateVT);
517 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
519 Val = DAG.getNode(IntermediateVT.isVector() ?
520 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
521 ValueVT, &Ops[0], NumIntermediates);
525 // There is now one part, held in Val. Correct it to match ValueVT.
526 PartVT = Val.getValueType();
528 if (PartVT == ValueVT)
531 if (PartVT.isVector()) {
532 assert(ValueVT.isVector() && "Unknown vector conversion!");
533 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
536 if (ValueVT.isVector()) {
537 assert(ValueVT.getVectorElementType() == PartVT &&
538 ValueVT.getVectorNumElements() == 1 &&
539 "Only trivial scalar-to-vector conversions should get here!");
540 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
543 if (PartVT.isInteger() &&
544 ValueVT.isInteger()) {
545 if (ValueVT.bitsLT(PartVT)) {
546 // For a truncate, see if we have any information to
547 // indicate whether the truncated bits will always be
548 // zero or sign-extension.
549 if (AssertOp != ISD::DELETED_NODE)
550 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
551 DAG.getValueType(ValueVT));
552 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
554 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
558 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
559 if (ValueVT.bitsLT(Val.getValueType()))
560 // FP_ROUND's are always exact here.
561 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
562 DAG.getIntPtrConstant(1));
563 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
566 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
567 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
569 assert(0 && "Unknown mismatch!");
573 /// getCopyToParts - Create a series of nodes that contain the specified value
574 /// split into legal parts. If the parts contain more bits than Val, then, for
575 /// integers, ExtendKind can be used to specify how to generate the extra bits.
576 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
577 SDValue *Parts, unsigned NumParts, MVT PartVT,
578 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
580 MVT PtrVT = TLI.getPointerTy();
581 MVT ValueVT = Val.getValueType();
582 unsigned PartBits = PartVT.getSizeInBits();
583 unsigned OrigNumParts = NumParts;
584 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
589 if (!ValueVT.isVector()) {
590 if (PartVT == ValueVT) {
591 assert(NumParts == 1 && "No-op copy with multiple parts!");
596 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
597 // If the parts cover more bits than the value has, promote the value.
598 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
599 assert(NumParts == 1 && "Do not know what to promote to!");
600 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
601 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
602 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
603 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
605 assert(0 && "Unknown mismatch!");
607 } else if (PartBits == ValueVT.getSizeInBits()) {
608 // Different types of the same size.
609 assert(NumParts == 1 && PartVT != ValueVT);
610 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
611 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
612 // If the parts cover less bits than value has, truncate the value.
613 if (PartVT.isInteger() && ValueVT.isInteger()) {
614 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
615 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
617 assert(0 && "Unknown mismatch!");
621 // The value may have changed - recompute ValueVT.
622 ValueVT = Val.getValueType();
623 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
624 "Failed to tile the value with PartVT!");
627 assert(PartVT == ValueVT && "Type conversion failed!");
632 // Expand the value into multiple parts.
633 if (NumParts & (NumParts - 1)) {
634 // The number of parts is not a power of 2. Split off and copy the tail.
635 assert(PartVT.isInteger() && ValueVT.isInteger() &&
636 "Do not know what to expand to!");
637 unsigned RoundParts = 1 << Log2_32(NumParts);
638 unsigned RoundBits = RoundParts * PartBits;
639 unsigned OddParts = NumParts - RoundParts;
640 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
641 DAG.getConstant(RoundBits,
642 TLI.getPointerTy()));
643 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
644 if (TLI.isBigEndian())
645 // The odd parts were reversed by getCopyToParts - unreverse them.
646 std::reverse(Parts + RoundParts, Parts + NumParts);
647 NumParts = RoundParts;
648 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
649 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
652 // The number of parts is a power of 2. Repeatedly bisect the value using
654 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
655 MVT::getIntegerVT(ValueVT.getSizeInBits()),
657 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
658 for (unsigned i = 0; i < NumParts; i += StepSize) {
659 unsigned ThisBits = StepSize * PartBits / 2;
660 MVT ThisVT = MVT::getIntegerVT (ThisBits);
661 SDValue &Part0 = Parts[i];
662 SDValue &Part1 = Parts[i+StepSize/2];
664 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
666 DAG.getConstant(1, PtrVT));
667 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
669 DAG.getConstant(0, PtrVT));
671 if (ThisBits == PartBits && ThisVT != PartVT) {
672 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
680 if (TLI.isBigEndian())
681 std::reverse(Parts, Parts + OrigNumParts);
688 if (PartVT != ValueVT) {
689 if (PartVT.isVector()) {
690 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
692 assert(ValueVT.getVectorElementType() == PartVT &&
693 ValueVT.getVectorNumElements() == 1 &&
694 "Only trivial vector-to-scalar conversions should get here!");
695 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
697 DAG.getConstant(0, PtrVT));
705 // Handle a multi-element vector.
706 MVT IntermediateVT, RegisterVT;
707 unsigned NumIntermediates;
708 unsigned NumRegs = TLI
709 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
711 unsigned NumElements = ValueVT.getVectorNumElements();
713 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
714 NumParts = NumRegs; // Silence a compiler warning.
715 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
717 // Split the vector into intermediate operands.
718 SmallVector<SDValue, 8> Ops(NumIntermediates);
719 for (unsigned i = 0; i != NumIntermediates; ++i)
720 if (IntermediateVT.isVector())
721 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
723 DAG.getConstant(i * (NumElements / NumIntermediates),
726 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
728 DAG.getConstant(i, PtrVT));
730 // Split the intermediate operands into legal parts.
731 if (NumParts == NumIntermediates) {
732 // If the register was not expanded, promote or copy the value,
734 for (unsigned i = 0; i != NumParts; ++i)
735 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
736 } else if (NumParts > 0) {
737 // If the intermediate type was expanded, split each the value into
739 assert(NumParts % NumIntermediates == 0 &&
740 "Must expand into a divisible number of parts!");
741 unsigned Factor = NumParts / NumIntermediates;
742 for (unsigned i = 0; i != NumIntermediates; ++i)
743 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
748 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
751 TD = DAG.getTarget().getTargetData();
754 /// clear - Clear out the curret SelectionDAG and the associated
755 /// state and prepare this SelectionDAGLowering object to be used
756 /// for a new block. This doesn't clear out information about
757 /// additional blocks that are needed to complete switch lowering
758 /// or PHI node updating; that information is cleared out as it is
760 void SelectionDAGLowering::clear() {
762 PendingLoads.clear();
763 PendingExports.clear();
765 CurDebugLoc = DebugLoc::getUnknownLoc();
768 /// getRoot - Return the current virtual root of the Selection DAG,
769 /// flushing any PendingLoad items. This must be done before emitting
770 /// a store or any other node that may need to be ordered after any
771 /// prior load instructions.
773 SDValue SelectionDAGLowering::getRoot() {
774 if (PendingLoads.empty())
775 return DAG.getRoot();
777 if (PendingLoads.size() == 1) {
778 SDValue Root = PendingLoads[0];
780 PendingLoads.clear();
784 // Otherwise, we have to make a token factor node.
785 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
786 &PendingLoads[0], PendingLoads.size());
787 PendingLoads.clear();
792 /// getControlRoot - Similar to getRoot, but instead of flushing all the
793 /// PendingLoad items, flush all the PendingExports items. It is necessary
794 /// to do this before emitting a terminator instruction.
796 SDValue SelectionDAGLowering::getControlRoot() {
797 SDValue Root = DAG.getRoot();
799 if (PendingExports.empty())
802 // Turn all of the CopyToReg chains into one factored node.
803 if (Root.getOpcode() != ISD::EntryToken) {
804 unsigned i = 0, e = PendingExports.size();
805 for (; i != e; ++i) {
806 assert(PendingExports[i].getNode()->getNumOperands() > 1);
807 if (PendingExports[i].getNode()->getOperand(0) == Root)
808 break; // Don't add the root if we already indirectly depend on it.
812 PendingExports.push_back(Root);
815 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
817 PendingExports.size());
818 PendingExports.clear();
823 void SelectionDAGLowering::visit(Instruction &I) {
824 visit(I.getOpcode(), I);
827 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
828 // Note: this doesn't use InstVisitor, because it has to work with
829 // ConstantExpr's in addition to instructions.
831 default: assert(0 && "Unknown instruction type encountered!");
833 // Build the switch statement using the Instruction.def file.
834 #define HANDLE_INST(NUM, OPCODE, CLASS) \
835 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
836 #include "llvm/Instruction.def"
840 void SelectionDAGLowering::visitAdd(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FADD);
844 visitBinary(I, ISD::ADD);
847 void SelectionDAGLowering::visitMul(User &I) {
848 if (I.getType()->isFPOrFPVector())
849 visitBinary(I, ISD::FMUL);
851 visitBinary(I, ISD::MUL);
854 SDValue SelectionDAGLowering::getValue(const Value *V) {
855 SDValue &N = NodeMap[V];
856 if (N.getNode()) return N;
858 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
859 MVT VT = TLI.getValueType(V->getType(), true);
861 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
862 return N = DAG.getConstant(*CI, VT);
864 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
865 return N = DAG.getGlobalAddress(GV, VT);
867 if (isa<ConstantPointerNull>(C))
868 return N = DAG.getConstant(0, TLI.getPointerTy());
870 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
871 return N = DAG.getConstantFP(*CFP, VT);
873 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
874 return N = DAG.getUNDEF(VT);
876 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
877 visit(CE->getOpcode(), *CE);
878 SDValue N1 = NodeMap[V];
879 assert(N1.getNode() && "visit didn't populate the ValueMap!");
883 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
884 SmallVector<SDValue, 4> Constants;
885 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
887 SDNode *Val = getValue(*OI).getNode();
888 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
889 Constants.push_back(SDValue(Val, i));
891 return DAG.getMergeValues(&Constants[0], Constants.size(),
895 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
896 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
897 "Unknown struct or array constant!");
899 SmallVector<MVT, 4> ValueVTs;
900 ComputeValueVTs(TLI, C->getType(), ValueVTs);
901 unsigned NumElts = ValueVTs.size();
903 return SDValue(); // empty struct
904 SmallVector<SDValue, 4> Constants(NumElts);
905 for (unsigned i = 0; i != NumElts; ++i) {
906 MVT EltVT = ValueVTs[i];
907 if (isa<UndefValue>(C))
908 Constants[i] = DAG.getUNDEF(EltVT);
909 else if (EltVT.isFloatingPoint())
910 Constants[i] = DAG.getConstantFP(0, EltVT);
912 Constants[i] = DAG.getConstant(0, EltVT);
914 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
917 const VectorType *VecTy = cast<VectorType>(V->getType());
918 unsigned NumElements = VecTy->getNumElements();
920 // Now that we know the number and type of the elements, get that number of
921 // elements into the Ops array based on what kind of constant it is.
922 SmallVector<SDValue, 16> Ops;
923 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
924 for (unsigned i = 0; i != NumElements; ++i)
925 Ops.push_back(getValue(CP->getOperand(i)));
927 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
928 MVT EltVT = TLI.getValueType(VecTy->getElementType());
931 if (EltVT.isFloatingPoint())
932 Op = DAG.getConstantFP(0, EltVT);
934 Op = DAG.getConstant(0, EltVT);
935 Ops.assign(NumElements, Op);
938 // Create a BUILD_VECTOR node.
939 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
940 VT, &Ops[0], Ops.size());
943 // If this is a static alloca, generate it as the frameindex instead of
945 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
946 DenseMap<const AllocaInst*, int>::iterator SI =
947 FuncInfo.StaticAllocaMap.find(AI);
948 if (SI != FuncInfo.StaticAllocaMap.end())
949 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
952 unsigned InReg = FuncInfo.ValueMap[V];
953 assert(InReg && "Value not in map!");
955 RegsForValue RFV(TLI, InReg, V->getType());
956 SDValue Chain = DAG.getEntryNode();
957 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
961 void SelectionDAGLowering::visitRet(ReturnInst &I) {
962 if (I.getNumOperands() == 0) {
963 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
964 MVT::Other, getControlRoot()));
968 SmallVector<SDValue, 8> NewValues;
969 NewValues.push_back(getControlRoot());
970 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
971 SmallVector<MVT, 4> ValueVTs;
972 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
973 unsigned NumValues = ValueVTs.size();
974 if (NumValues == 0) continue;
976 SDValue RetOp = getValue(I.getOperand(i));
977 for (unsigned j = 0, f = NumValues; j != f; ++j) {
978 MVT VT = ValueVTs[j];
980 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
982 const Function *F = I.getParent()->getParent();
983 if (F->paramHasAttr(0, Attribute::SExt))
984 ExtendKind = ISD::SIGN_EXTEND;
985 else if (F->paramHasAttr(0, Attribute::ZExt))
986 ExtendKind = ISD::ZERO_EXTEND;
988 // FIXME: C calling convention requires the return type to be promoted to
989 // at least 32-bit. But this is not necessary for non-C calling
990 // conventions. The frontend should mark functions whose return values
991 // require promoting with signext or zeroext attributes.
992 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
993 MVT MinVT = TLI.getRegisterType(MVT::i32);
994 if (VT.bitsLT(MinVT))
998 unsigned NumParts = TLI.getNumRegisters(VT);
999 MVT PartVT = TLI.getRegisterType(VT);
1000 SmallVector<SDValue, 4> Parts(NumParts);
1001 getCopyToParts(DAG, getCurDebugLoc(),
1002 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1003 &Parts[0], NumParts, PartVT, ExtendKind);
1005 // 'inreg' on function refers to return value
1006 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1007 if (F->paramHasAttr(0, Attribute::InReg))
1009 for (unsigned i = 0; i < NumParts; ++i) {
1010 NewValues.push_back(Parts[i]);
1011 NewValues.push_back(DAG.getArgFlags(Flags));
1015 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1016 &NewValues[0], NewValues.size()));
1019 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1020 /// created for it, emit nodes to copy the value into the virtual
1022 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1023 if (!V->use_empty()) {
1024 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1025 if (VMI != FuncInfo.ValueMap.end())
1026 CopyValueToVirtualRegister(V, VMI->second);
1030 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1031 /// the current basic block, add it to ValueMap now so that we'll get a
1033 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1034 // No need to export constants.
1035 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1037 // Already exported?
1038 if (FuncInfo.isExportedInst(V)) return;
1040 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1041 CopyValueToVirtualRegister(V, Reg);
1044 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1045 const BasicBlock *FromBB) {
1046 // The operands of the setcc have to be in this block. We don't know
1047 // how to export them from some other block.
1048 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1049 // Can export from current BB.
1050 if (VI->getParent() == FromBB)
1053 // Is already exported, noop.
1054 return FuncInfo.isExportedInst(V);
1057 // If this is an argument, we can export it if the BB is the entry block or
1058 // if it is already exported.
1059 if (isa<Argument>(V)) {
1060 if (FromBB == &FromBB->getParent()->getEntryBlock())
1063 // Otherwise, can only export this if it is already exported.
1064 return FuncInfo.isExportedInst(V);
1067 // Otherwise, constants can always be exported.
1071 static bool InBlock(const Value *V, const BasicBlock *BB) {
1072 if (const Instruction *I = dyn_cast<Instruction>(V))
1073 return I->getParent() == BB;
1077 /// getFCmpCondCode - Return the ISD condition code corresponding to
1078 /// the given LLVM IR floating-point condition code. This includes
1079 /// consideration of global floating-point math flags.
1081 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1082 ISD::CondCode FPC, FOC;
1084 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1085 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1086 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1087 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1088 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1089 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1090 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1091 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1092 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1093 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1094 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1095 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1096 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1097 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1098 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1099 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1101 assert(0 && "Invalid FCmp predicate opcode!");
1102 FOC = FPC = ISD::SETFALSE;
1105 if (FiniteOnlyFPMath())
1111 /// getICmpCondCode - Return the ISD condition code corresponding to
1112 /// the given LLVM IR integer condition code.
1114 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1116 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1117 case ICmpInst::ICMP_NE: return ISD::SETNE;
1118 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1119 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1120 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1121 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1122 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1123 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1124 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1125 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1127 assert(0 && "Invalid ICmp predicate opcode!");
1132 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1133 /// This function emits a branch and is used at the leaves of an OR or an
1134 /// AND operator tree.
1137 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1138 MachineBasicBlock *TBB,
1139 MachineBasicBlock *FBB,
1140 MachineBasicBlock *CurBB) {
1141 const BasicBlock *BB = CurBB->getBasicBlock();
1143 // If the leaf of the tree is a comparison, merge the condition into
1145 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1146 // The operands of the cmp have to be in this block. We don't know
1147 // how to export them from some other block. If this is the first block
1148 // of the sequence, no exporting is needed.
1149 if (CurBB == CurMBB ||
1150 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1151 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1152 ISD::CondCode Condition;
1153 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1154 Condition = getICmpCondCode(IC->getPredicate());
1155 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1156 Condition = getFCmpCondCode(FC->getPredicate());
1158 Condition = ISD::SETEQ; // silence warning.
1159 assert(0 && "Unknown compare instruction");
1162 CaseBlock CB(Condition, BOp->getOperand(0),
1163 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1164 SwitchCases.push_back(CB);
1169 // Create a CaseBlock record representing this branch.
1170 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1171 NULL, TBB, FBB, CurBB);
1172 SwitchCases.push_back(CB);
1175 /// FindMergedConditions - If Cond is an expression like
1176 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1177 MachineBasicBlock *TBB,
1178 MachineBasicBlock *FBB,
1179 MachineBasicBlock *CurBB,
1181 // If this node is not part of the or/and tree, emit it as a branch.
1182 Instruction *BOp = dyn_cast<Instruction>(Cond);
1183 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1184 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1185 BOp->getParent() != CurBB->getBasicBlock() ||
1186 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1187 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1188 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1192 // Create TmpBB after CurBB.
1193 MachineFunction::iterator BBI = CurBB;
1194 MachineFunction &MF = DAG.getMachineFunction();
1195 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1196 CurBB->getParent()->insert(++BBI, TmpBB);
1198 if (Opc == Instruction::Or) {
1199 // Codegen X | Y as:
1207 // Emit the LHS condition.
1208 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1210 // Emit the RHS condition into TmpBB.
1211 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1213 assert(Opc == Instruction::And && "Unknown merge op!");
1214 // Codegen X & Y as:
1221 // This requires creation of TmpBB after CurBB.
1223 // Emit the LHS condition.
1224 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1226 // Emit the RHS condition into TmpBB.
1227 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1231 /// If the set of cases should be emitted as a series of branches, return true.
1232 /// If we should emit this as a bunch of and/or'd together conditions, return
1235 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1236 if (Cases.size() != 2) return true;
1238 // If this is two comparisons of the same values or'd or and'd together, they
1239 // will get folded into a single comparison, so don't emit two blocks.
1240 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1241 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1242 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1243 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1250 void SelectionDAGLowering::visitBr(BranchInst &I) {
1251 // Update machine-CFG edges.
1252 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1254 // Figure out which block is immediately after the current one.
1255 MachineBasicBlock *NextBlock = 0;
1256 MachineFunction::iterator BBI = CurMBB;
1257 if (++BBI != CurMBB->getParent()->end())
1260 if (I.isUnconditional()) {
1261 // Update machine-CFG edges.
1262 CurMBB->addSuccessor(Succ0MBB);
1264 // If this is not a fall-through branch, emit the branch.
1265 if (Succ0MBB != NextBlock)
1266 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1267 MVT::Other, getControlRoot(),
1268 DAG.getBasicBlock(Succ0MBB)));
1272 // If this condition is one of the special cases we handle, do special stuff
1274 Value *CondVal = I.getCondition();
1275 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1277 // If this is a series of conditions that are or'd or and'd together, emit
1278 // this as a sequence of branches instead of setcc's with and/or operations.
1279 // For example, instead of something like:
1292 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1293 if (BOp->hasOneUse() &&
1294 (BOp->getOpcode() == Instruction::And ||
1295 BOp->getOpcode() == Instruction::Or)) {
1296 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1297 // If the compares in later blocks need to use values not currently
1298 // exported from this block, export them now. This block should always
1299 // be the first entry.
1300 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1302 // Allow some cases to be rejected.
1303 if (ShouldEmitAsBranches(SwitchCases)) {
1304 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1305 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1306 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1309 // Emit the branch for this block.
1310 visitSwitchCase(SwitchCases[0]);
1311 SwitchCases.erase(SwitchCases.begin());
1315 // Okay, we decided not to do this, remove any inserted MBB's and clear
1317 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1318 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1320 SwitchCases.clear();
1324 // Create a CaseBlock record representing this branch.
1325 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1326 NULL, Succ0MBB, Succ1MBB, CurMBB);
1327 // Use visitSwitchCase to actually insert the fast branch sequence for this
1329 visitSwitchCase(CB);
1332 /// visitSwitchCase - Emits the necessary code to represent a single node in
1333 /// the binary search tree resulting from lowering a switch instruction.
1334 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1336 SDValue CondLHS = getValue(CB.CmpLHS);
1337 DebugLoc dl = getCurDebugLoc();
1339 // Build the setcc now.
1340 if (CB.CmpMHS == NULL) {
1341 // Fold "(X == true)" to X and "(X == false)" to !X to
1342 // handle common cases produced by branch lowering.
1343 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1345 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1346 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1347 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1349 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1351 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1353 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1354 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1356 SDValue CmpOp = getValue(CB.CmpMHS);
1357 MVT VT = CmpOp.getValueType();
1359 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1360 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1363 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1364 VT, CmpOp, DAG.getConstant(Low, VT));
1365 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1366 DAG.getConstant(High-Low, VT), ISD::SETULE);
1370 // Update successor info
1371 CurMBB->addSuccessor(CB.TrueBB);
1372 CurMBB->addSuccessor(CB.FalseBB);
1374 // Set NextBlock to be the MBB immediately after the current one, if any.
1375 // This is used to avoid emitting unnecessary branches to the next block.
1376 MachineBasicBlock *NextBlock = 0;
1377 MachineFunction::iterator BBI = CurMBB;
1378 if (++BBI != CurMBB->getParent()->end())
1381 // If the lhs block is the next block, invert the condition so that we can
1382 // fall through to the lhs instead of the rhs block.
1383 if (CB.TrueBB == NextBlock) {
1384 std::swap(CB.TrueBB, CB.FalseBB);
1385 SDValue True = DAG.getConstant(1, Cond.getValueType());
1386 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1388 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1389 MVT::Other, getControlRoot(), Cond,
1390 DAG.getBasicBlock(CB.TrueBB));
1392 // If the branch was constant folded, fix up the CFG.
1393 if (BrCond.getOpcode() == ISD::BR) {
1394 CurMBB->removeSuccessor(CB.FalseBB);
1395 DAG.setRoot(BrCond);
1397 // Otherwise, go ahead and insert the false branch.
1398 if (BrCond == getControlRoot())
1399 CurMBB->removeSuccessor(CB.TrueBB);
1401 if (CB.FalseBB == NextBlock)
1402 DAG.setRoot(BrCond);
1404 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1405 DAG.getBasicBlock(CB.FalseBB)));
1409 /// visitJumpTable - Emit JumpTable node in the current MBB
1410 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1411 // Emit the code for the jump table
1412 assert(JT.Reg != -1U && "Should lower JT Header first!");
1413 MVT PTy = TLI.getPointerTy();
1414 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1416 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1417 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1418 MVT::Other, Index.getValue(1),
1422 /// visitJumpTableHeader - This function emits necessary code to produce index
1423 /// in the JumpTable from switch case.
1424 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1425 JumpTableHeader &JTH) {
1426 // Subtract the lowest switch case value from the value being switched on and
1427 // conditional branch to default mbb if the result is greater than the
1428 // difference between smallest and largest cases.
1429 SDValue SwitchOp = getValue(JTH.SValue);
1430 MVT VT = SwitchOp.getValueType();
1431 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1432 DAG.getConstant(JTH.First, VT));
1434 // The SDNode we just created, which holds the value being switched on minus
1435 // the the smallest case value, needs to be copied to a virtual register so it
1436 // can be used as an index into the jump table in a subsequent basic block.
1437 // This value may be smaller or larger than the target's pointer type, and
1438 // therefore require extension or truncating.
1439 if (VT.bitsGT(TLI.getPointerTy()))
1440 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1441 TLI.getPointerTy(), SUB);
1443 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1444 TLI.getPointerTy(), SUB);
1446 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1447 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1448 JumpTableReg, SwitchOp);
1449 JT.Reg = JumpTableReg;
1451 // Emit the range check for the jump table, and branch to the default block
1452 // for the switch statement if the value being switched on exceeds the largest
1453 // case in the switch.
1454 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1455 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1456 DAG.getConstant(JTH.Last-JTH.First,VT),
1459 // Set NextBlock to be the MBB immediately after the current one, if any.
1460 // This is used to avoid emitting unnecessary branches to the next block.
1461 MachineBasicBlock *NextBlock = 0;
1462 MachineFunction::iterator BBI = CurMBB;
1463 if (++BBI != CurMBB->getParent()->end())
1466 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1467 MVT::Other, CopyTo, CMP,
1468 DAG.getBasicBlock(JT.Default));
1470 if (JT.MBB == NextBlock)
1471 DAG.setRoot(BrCond);
1473 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1474 DAG.getBasicBlock(JT.MBB)));
1477 /// visitBitTestHeader - This function emits necessary code to produce value
1478 /// suitable for "bit tests"
1479 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1480 // Subtract the minimum value
1481 SDValue SwitchOp = getValue(B.SValue);
1482 MVT VT = SwitchOp.getValueType();
1483 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1484 DAG.getConstant(B.First, VT));
1487 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1488 TLI.getSetCCResultType(SUB.getValueType()),
1489 SUB, DAG.getConstant(B.Range, VT),
1493 if (VT.bitsGT(TLI.getPointerTy()))
1494 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1495 TLI.getPointerTy(), SUB);
1497 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1498 TLI.getPointerTy(), SUB);
1500 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1501 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1504 // Set NextBlock to be the MBB immediately after the current one, if any.
1505 // This is used to avoid emitting unnecessary branches to the next block.
1506 MachineBasicBlock *NextBlock = 0;
1507 MachineFunction::iterator BBI = CurMBB;
1508 if (++BBI != CurMBB->getParent()->end())
1511 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1513 CurMBB->addSuccessor(B.Default);
1514 CurMBB->addSuccessor(MBB);
1516 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1517 MVT::Other, CopyTo, RangeCmp,
1518 DAG.getBasicBlock(B.Default));
1520 if (MBB == NextBlock)
1521 DAG.setRoot(BrRange);
1523 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1524 DAG.getBasicBlock(MBB)));
1527 /// visitBitTestCase - this function produces one "bit test"
1528 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1531 // Make desired shift
1532 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1533 TLI.getPointerTy());
1534 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1536 DAG.getConstant(1, TLI.getPointerTy()),
1539 // Emit bit tests and jumps
1540 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1541 TLI.getPointerTy(), SwitchVal,
1542 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1543 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1544 TLI.getSetCCResultType(AndOp.getValueType()),
1545 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1548 CurMBB->addSuccessor(B.TargetBB);
1549 CurMBB->addSuccessor(NextMBB);
1551 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1552 MVT::Other, getControlRoot(),
1553 AndCmp, DAG.getBasicBlock(B.TargetBB));
1555 // Set NextBlock to be the MBB immediately after the current one, if any.
1556 // This is used to avoid emitting unnecessary branches to the next block.
1557 MachineBasicBlock *NextBlock = 0;
1558 MachineFunction::iterator BBI = CurMBB;
1559 if (++BBI != CurMBB->getParent()->end())
1562 if (NextMBB == NextBlock)
1565 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1566 DAG.getBasicBlock(NextMBB)));
1569 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1570 // Retrieve successors.
1571 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1572 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1574 const Value *Callee(I.getCalledValue());
1575 if (isa<InlineAsm>(Callee))
1578 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1580 // If the value of the invoke is used outside of its defining block, make it
1581 // available as a virtual register.
1582 CopyToExportRegsIfNeeded(&I);
1584 // Update successor info
1585 CurMBB->addSuccessor(Return);
1586 CurMBB->addSuccessor(LandingPad);
1588 // Drop into normal successor.
1589 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1590 MVT::Other, getControlRoot(),
1591 DAG.getBasicBlock(Return)));
1594 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1597 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1598 /// small case ranges).
1599 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1600 CaseRecVector& WorkList,
1602 MachineBasicBlock* Default) {
1603 Case& BackCase = *(CR.Range.second-1);
1605 // Size is the number of Cases represented by this range.
1606 size_t Size = CR.Range.second - CR.Range.first;
1610 // Get the MachineFunction which holds the current MBB. This is used when
1611 // inserting any additional MBBs necessary to represent the switch.
1612 MachineFunction *CurMF = CurMBB->getParent();
1614 // Figure out which block is immediately after the current one.
1615 MachineBasicBlock *NextBlock = 0;
1616 MachineFunction::iterator BBI = CR.CaseBB;
1618 if (++BBI != CurMBB->getParent()->end())
1621 // TODO: If any two of the cases has the same destination, and if one value
1622 // is the same as the other, but has one bit unset that the other has set,
1623 // use bit manipulation to do two compares at once. For example:
1624 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1626 // Rearrange the case blocks so that the last one falls through if possible.
1627 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1628 // The last case block won't fall through into 'NextBlock' if we emit the
1629 // branches in this order. See if rearranging a case value would help.
1630 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1631 if (I->BB == NextBlock) {
1632 std::swap(*I, BackCase);
1638 // Create a CaseBlock record representing a conditional branch to
1639 // the Case's target mbb if the value being switched on SV is equal
1641 MachineBasicBlock *CurBlock = CR.CaseBB;
1642 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1643 MachineBasicBlock *FallThrough;
1645 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1646 CurMF->insert(BBI, FallThrough);
1648 // Put SV in a virtual register to make it available from the new blocks.
1649 ExportFromCurrentBlock(SV);
1651 // If the last case doesn't match, go to the default block.
1652 FallThrough = Default;
1655 Value *RHS, *LHS, *MHS;
1657 if (I->High == I->Low) {
1658 // This is just small small case range :) containing exactly 1 case
1660 LHS = SV; RHS = I->High; MHS = NULL;
1663 LHS = I->Low; MHS = SV; RHS = I->High;
1665 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1667 // If emitting the first comparison, just call visitSwitchCase to emit the
1668 // code into the current block. Otherwise, push the CaseBlock onto the
1669 // vector to be later processed by SDISel, and insert the node's MBB
1670 // before the next MBB.
1671 if (CurBlock == CurMBB)
1672 visitSwitchCase(CB);
1674 SwitchCases.push_back(CB);
1676 CurBlock = FallThrough;
1682 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1683 return !DisableJumpTables &&
1684 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1685 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1688 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1689 APInt LastExt(Last), FirstExt(First);
1690 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1691 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1692 return (LastExt - FirstExt + 1ULL);
1695 /// handleJTSwitchCase - Emit jumptable for current switch case range
1696 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1697 CaseRecVector& WorkList,
1699 MachineBasicBlock* Default) {
1700 Case& FrontCase = *CR.Range.first;
1701 Case& BackCase = *(CR.Range.second-1);
1703 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1704 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1707 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1711 if (!areJTsAllowed(TLI) || TSize <= 3)
1714 APInt Range = ComputeRange(First, Last);
1715 double Density = (double)TSize / Range.roundToDouble();
1719 DEBUG(errs() << "Lowering jump table\n"
1720 << "First entry: " << First << ". Last entry: " << Last << '\n'
1721 << "Range: " << Range
1722 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1724 // Get the MachineFunction which holds the current MBB. This is used when
1725 // inserting any additional MBBs necessary to represent the switch.
1726 MachineFunction *CurMF = CurMBB->getParent();
1728 // Figure out which block is immediately after the current one.
1729 MachineBasicBlock *NextBlock = 0;
1730 MachineFunction::iterator BBI = CR.CaseBB;
1732 if (++BBI != CurMBB->getParent()->end())
1735 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1737 // Create a new basic block to hold the code for loading the address
1738 // of the jump table, and jumping to it. Update successor information;
1739 // we will either branch to the default case for the switch, or the jump
1741 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1742 CurMF->insert(BBI, JumpTableBB);
1743 CR.CaseBB->addSuccessor(Default);
1744 CR.CaseBB->addSuccessor(JumpTableBB);
1746 // Build a vector of destination BBs, corresponding to each target
1747 // of the jump table. If the value of the jump table slot corresponds to
1748 // a case statement, push the case's BB onto the vector, otherwise, push
1750 std::vector<MachineBasicBlock*> DestBBs;
1752 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1753 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1754 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1756 if (Low.sle(TEI) && TEI.sle(High)) {
1757 DestBBs.push_back(I->BB);
1761 DestBBs.push_back(Default);
1765 // Update successor info. Add one edge to each unique successor.
1766 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1767 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1768 E = DestBBs.end(); I != E; ++I) {
1769 if (!SuccsHandled[(*I)->getNumber()]) {
1770 SuccsHandled[(*I)->getNumber()] = true;
1771 JumpTableBB->addSuccessor(*I);
1775 // Create a jump table index for this jump table, or return an existing
1777 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1779 // Set the jump table information so that we can codegen it as a second
1780 // MachineBasicBlock
1781 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1782 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1783 if (CR.CaseBB == CurMBB)
1784 visitJumpTableHeader(JT, JTH);
1786 JTCases.push_back(JumpTableBlock(JTH, JT));
1791 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1793 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1794 CaseRecVector& WorkList,
1796 MachineBasicBlock* Default) {
1797 // Get the MachineFunction which holds the current MBB. This is used when
1798 // inserting any additional MBBs necessary to represent the switch.
1799 MachineFunction *CurMF = CurMBB->getParent();
1801 // Figure out which block is immediately after the current one.
1802 MachineBasicBlock *NextBlock = 0;
1803 MachineFunction::iterator BBI = CR.CaseBB;
1805 if (++BBI != CurMBB->getParent()->end())
1808 Case& FrontCase = *CR.Range.first;
1809 Case& BackCase = *(CR.Range.second-1);
1810 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1812 // Size is the number of Cases represented by this range.
1813 unsigned Size = CR.Range.second - CR.Range.first;
1815 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1816 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1818 CaseItr Pivot = CR.Range.first + Size/2;
1820 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1821 // (heuristically) allow us to emit JumpTable's later.
1823 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1827 size_t LSize = FrontCase.size();
1828 size_t RSize = TSize-LSize;
1829 DEBUG(errs() << "Selecting best pivot: \n"
1830 << "First: " << First << ", Last: " << Last <<'\n'
1831 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1832 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1834 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1835 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1836 APInt Range = ComputeRange(LEnd, RBegin);
1837 assert((Range - 2ULL).isNonNegative() &&
1838 "Invalid case distance");
1839 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1840 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1841 double Metric = Range.logBase2()*(LDensity+RDensity);
1842 // Should always split in some non-trivial place
1843 DEBUG(errs() <<"=>Step\n"
1844 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1845 << "LDensity: " << LDensity
1846 << ", RDensity: " << RDensity << '\n'
1847 << "Metric: " << Metric << '\n');
1848 if (FMetric < Metric) {
1851 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1857 if (areJTsAllowed(TLI)) {
1858 // If our case is dense we *really* should handle it earlier!
1859 assert((FMetric > 0) && "Should handle dense range earlier!");
1861 Pivot = CR.Range.first + Size/2;
1864 CaseRange LHSR(CR.Range.first, Pivot);
1865 CaseRange RHSR(Pivot, CR.Range.second);
1866 Constant *C = Pivot->Low;
1867 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1869 // We know that we branch to the LHS if the Value being switched on is
1870 // less than the Pivot value, C. We use this to optimize our binary
1871 // tree a bit, by recognizing that if SV is greater than or equal to the
1872 // LHS's Case Value, and that Case Value is exactly one less than the
1873 // Pivot's Value, then we can branch directly to the LHS's Target,
1874 // rather than creating a leaf node for it.
1875 if ((LHSR.second - LHSR.first) == 1 &&
1876 LHSR.first->High == CR.GE &&
1877 cast<ConstantInt>(C)->getValue() ==
1878 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1879 TrueBB = LHSR.first->BB;
1881 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1882 CurMF->insert(BBI, TrueBB);
1883 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1885 // Put SV in a virtual register to make it available from the new blocks.
1886 ExportFromCurrentBlock(SV);
1889 // Similar to the optimization above, if the Value being switched on is
1890 // known to be less than the Constant CR.LT, and the current Case Value
1891 // is CR.LT - 1, then we can branch directly to the target block for
1892 // the current Case Value, rather than emitting a RHS leaf node for it.
1893 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1894 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1895 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1896 FalseBB = RHSR.first->BB;
1898 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1899 CurMF->insert(BBI, FalseBB);
1900 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1902 // Put SV in a virtual register to make it available from the new blocks.
1903 ExportFromCurrentBlock(SV);
1906 // Create a CaseBlock record representing a conditional branch to
1907 // the LHS node if the value being switched on SV is less than C.
1908 // Otherwise, branch to LHS.
1909 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1911 if (CR.CaseBB == CurMBB)
1912 visitSwitchCase(CB);
1914 SwitchCases.push_back(CB);
1919 /// handleBitTestsSwitchCase - if current case range has few destination and
1920 /// range span less, than machine word bitwidth, encode case range into series
1921 /// of masks and emit bit tests with these masks.
1922 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1923 CaseRecVector& WorkList,
1925 MachineBasicBlock* Default){
1926 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1928 Case& FrontCase = *CR.Range.first;
1929 Case& BackCase = *(CR.Range.second-1);
1931 // Get the MachineFunction which holds the current MBB. This is used when
1932 // inserting any additional MBBs necessary to represent the switch.
1933 MachineFunction *CurMF = CurMBB->getParent();
1936 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1938 // Single case counts one, case range - two.
1939 numCmps += (I->Low == I->High ? 1 : 2);
1942 // Count unique destinations
1943 SmallSet<MachineBasicBlock*, 4> Dests;
1944 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1945 Dests.insert(I->BB);
1946 if (Dests.size() > 3)
1947 // Don't bother the code below, if there are too much unique destinations
1950 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1951 << "Total number of comparisons: " << numCmps << '\n');
1953 // Compute span of values.
1954 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1955 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1956 APInt cmpRange = maxValue - minValue;
1958 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1959 << "Low bound: " << minValue << '\n'
1960 << "High bound: " << maxValue << '\n');
1962 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1963 (!(Dests.size() == 1 && numCmps >= 3) &&
1964 !(Dests.size() == 2 && numCmps >= 5) &&
1965 !(Dests.size() >= 3 && numCmps >= 6)))
1968 DEBUG(errs() << "Emitting bit tests\n");
1969 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1971 // Optimize the case where all the case values fit in a
1972 // word without having to subtract minValue. In this case,
1973 // we can optimize away the subtraction.
1974 if (minValue.isNonNegative() &&
1975 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1976 cmpRange = maxValue;
1978 lowBound = minValue;
1981 CaseBitsVector CasesBits;
1982 unsigned i, count = 0;
1984 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1985 MachineBasicBlock* Dest = I->BB;
1986 for (i = 0; i < count; ++i)
1987 if (Dest == CasesBits[i].BB)
1991 assert((count < 3) && "Too much destinations to test!");
1992 CasesBits.push_back(CaseBits(0, Dest, 0));
1996 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1997 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1999 uint64_t lo = (lowValue - lowBound).getZExtValue();
2000 uint64_t hi = (highValue - lowBound).getZExtValue();
2002 for (uint64_t j = lo; j <= hi; j++) {
2003 CasesBits[i].Mask |= 1ULL << j;
2004 CasesBits[i].Bits++;
2008 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2012 // Figure out which block is immediately after the current one.
2013 MachineFunction::iterator BBI = CR.CaseBB;
2016 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2018 DEBUG(errs() << "Cases:\n");
2019 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2020 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2021 << ", Bits: " << CasesBits[i].Bits
2022 << ", BB: " << CasesBits[i].BB << '\n');
2024 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2025 CurMF->insert(BBI, CaseBB);
2026 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2030 // Put SV in a virtual register to make it available from the new blocks.
2031 ExportFromCurrentBlock(SV);
2034 BitTestBlock BTB(lowBound, cmpRange, SV,
2035 -1U, (CR.CaseBB == CurMBB),
2036 CR.CaseBB, Default, BTC);
2038 if (CR.CaseBB == CurMBB)
2039 visitBitTestHeader(BTB);
2041 BitTestCases.push_back(BTB);
2047 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2048 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2049 const SwitchInst& SI) {
2052 // Start with "simple" cases
2053 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2054 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2055 Cases.push_back(Case(SI.getSuccessorValue(i),
2056 SI.getSuccessorValue(i),
2059 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2061 // Merge case into clusters
2062 if (Cases.size() >= 2)
2063 // Must recompute end() each iteration because it may be
2064 // invalidated by erase if we hold on to it
2065 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2066 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2067 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2068 MachineBasicBlock* nextBB = J->BB;
2069 MachineBasicBlock* currentBB = I->BB;
2071 // If the two neighboring cases go to the same destination, merge them
2072 // into a single case.
2073 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2081 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2082 if (I->Low != I->High)
2083 // A range counts double, since it requires two compares.
2090 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2091 // Figure out which block is immediately after the current one.
2092 MachineBasicBlock *NextBlock = 0;
2093 MachineFunction::iterator BBI = CurMBB;
2095 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2097 // If there is only the default destination, branch to it if it is not the
2098 // next basic block. Otherwise, just fall through.
2099 if (SI.getNumOperands() == 2) {
2100 // Update machine-CFG edges.
2102 // If this is not a fall-through branch, emit the branch.
2103 CurMBB->addSuccessor(Default);
2104 if (Default != NextBlock)
2105 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2106 MVT::Other, getControlRoot(),
2107 DAG.getBasicBlock(Default)));
2111 // If there are any non-default case statements, create a vector of Cases
2112 // representing each one, and sort the vector so that we can efficiently
2113 // create a binary search tree from them.
2115 size_t numCmps = Clusterify(Cases, SI);
2116 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2117 << ". Total compares: " << numCmps << '\n');
2120 // Get the Value to be switched on and default basic blocks, which will be
2121 // inserted into CaseBlock records, representing basic blocks in the binary
2123 Value *SV = SI.getOperand(0);
2125 // Push the initial CaseRec onto the worklist
2126 CaseRecVector WorkList;
2127 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2129 while (!WorkList.empty()) {
2130 // Grab a record representing a case range to process off the worklist
2131 CaseRec CR = WorkList.back();
2132 WorkList.pop_back();
2134 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2137 // If the range has few cases (two or less) emit a series of specific
2139 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2142 // If the switch has more than 5 blocks, and at least 40% dense, and the
2143 // target supports indirect branches, then emit a jump table rather than
2144 // lowering the switch to a binary tree of conditional branches.
2145 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2148 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2149 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2150 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2155 void SelectionDAGLowering::visitSub(User &I) {
2156 // -0.0 - X --> fneg
2157 const Type *Ty = I.getType();
2158 if (isa<VectorType>(Ty)) {
2159 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2160 const VectorType *DestTy = cast<VectorType>(I.getType());
2161 const Type *ElTy = DestTy->getElementType();
2162 if (ElTy->isFloatingPoint()) {
2163 unsigned VL = DestTy->getNumElements();
2164 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2165 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2167 SDValue Op2 = getValue(I.getOperand(1));
2168 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2169 Op2.getValueType(), Op2));
2175 if (Ty->isFloatingPoint()) {
2176 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2177 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2178 SDValue Op2 = getValue(I.getOperand(1));
2179 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2180 Op2.getValueType(), Op2));
2185 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2188 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2189 SDValue Op1 = getValue(I.getOperand(0));
2190 SDValue Op2 = getValue(I.getOperand(1));
2192 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2193 Op1.getValueType(), Op1, Op2));
2196 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2197 SDValue Op1 = getValue(I.getOperand(0));
2198 SDValue Op2 = getValue(I.getOperand(1));
2199 if (!isa<VectorType>(I.getType()) &&
2200 Op2.getValueType() != TLI.getShiftAmountTy()) {
2201 // If the operand is smaller than the shift count type, promote it.
2202 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2203 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2204 TLI.getShiftAmountTy(), Op2);
2205 // If the operand is larger than the shift count type but the shift
2206 // count type has enough bits to represent any shift value, truncate
2207 // it now. This is a common case and it exposes the truncate to
2208 // optimization early.
2209 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2210 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2211 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2212 TLI.getShiftAmountTy(), Op2);
2213 // Otherwise we'll need to temporarily settle for some other
2214 // convenient type; type legalization will make adjustments as
2216 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2217 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2218 TLI.getPointerTy(), Op2);
2219 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2220 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2221 TLI.getPointerTy(), Op2);
2224 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2225 Op1.getValueType(), Op1, Op2));
2228 void SelectionDAGLowering::visitICmp(User &I) {
2229 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2230 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2231 predicate = IC->getPredicate();
2232 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2233 predicate = ICmpInst::Predicate(IC->getPredicate());
2234 SDValue Op1 = getValue(I.getOperand(0));
2235 SDValue Op2 = getValue(I.getOperand(1));
2236 ISD::CondCode Opcode = getICmpCondCode(predicate);
2237 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2240 void SelectionDAGLowering::visitFCmp(User &I) {
2241 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2242 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2243 predicate = FC->getPredicate();
2244 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2245 predicate = FCmpInst::Predicate(FC->getPredicate());
2246 SDValue Op1 = getValue(I.getOperand(0));
2247 SDValue Op2 = getValue(I.getOperand(1));
2248 ISD::CondCode Condition = getFCmpCondCode(predicate);
2249 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2252 void SelectionDAGLowering::visitVICmp(User &I) {
2253 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2254 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2255 predicate = IC->getPredicate();
2256 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2257 predicate = ICmpInst::Predicate(IC->getPredicate());
2258 SDValue Op1 = getValue(I.getOperand(0));
2259 SDValue Op2 = getValue(I.getOperand(1));
2260 ISD::CondCode Opcode = getICmpCondCode(predicate);
2261 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2265 void SelectionDAGLowering::visitVFCmp(User &I) {
2266 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2267 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2268 predicate = FC->getPredicate();
2269 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2270 predicate = FCmpInst::Predicate(FC->getPredicate());
2271 SDValue Op1 = getValue(I.getOperand(0));
2272 SDValue Op2 = getValue(I.getOperand(1));
2273 ISD::CondCode Condition = getFCmpCondCode(predicate);
2274 MVT DestVT = TLI.getValueType(I.getType());
2276 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2279 void SelectionDAGLowering::visitSelect(User &I) {
2280 SmallVector<MVT, 4> ValueVTs;
2281 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2282 unsigned NumValues = ValueVTs.size();
2283 if (NumValues != 0) {
2284 SmallVector<SDValue, 4> Values(NumValues);
2285 SDValue Cond = getValue(I.getOperand(0));
2286 SDValue TrueVal = getValue(I.getOperand(1));
2287 SDValue FalseVal = getValue(I.getOperand(2));
2289 for (unsigned i = 0; i != NumValues; ++i)
2290 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2291 TrueVal.getValueType(), Cond,
2292 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2293 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2295 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2296 DAG.getVTList(&ValueVTs[0], NumValues),
2297 &Values[0], NumValues));
2302 void SelectionDAGLowering::visitTrunc(User &I) {
2303 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2304 SDValue N = getValue(I.getOperand(0));
2305 MVT DestVT = TLI.getValueType(I.getType());
2306 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2309 void SelectionDAGLowering::visitZExt(User &I) {
2310 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2311 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2312 SDValue N = getValue(I.getOperand(0));
2313 MVT DestVT = TLI.getValueType(I.getType());
2314 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2317 void SelectionDAGLowering::visitSExt(User &I) {
2318 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2319 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2320 SDValue N = getValue(I.getOperand(0));
2321 MVT DestVT = TLI.getValueType(I.getType());
2322 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2325 void SelectionDAGLowering::visitFPTrunc(User &I) {
2326 // FPTrunc is never a no-op cast, no need to check
2327 SDValue N = getValue(I.getOperand(0));
2328 MVT DestVT = TLI.getValueType(I.getType());
2329 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2330 DestVT, N, DAG.getIntPtrConstant(0)));
2333 void SelectionDAGLowering::visitFPExt(User &I){
2334 // FPTrunc is never a no-op cast, no need to check
2335 SDValue N = getValue(I.getOperand(0));
2336 MVT DestVT = TLI.getValueType(I.getType());
2337 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2340 void SelectionDAGLowering::visitFPToUI(User &I) {
2341 // FPToUI is never a no-op cast, no need to check
2342 SDValue N = getValue(I.getOperand(0));
2343 MVT DestVT = TLI.getValueType(I.getType());
2344 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2347 void SelectionDAGLowering::visitFPToSI(User &I) {
2348 // FPToSI is never a no-op cast, no need to check
2349 SDValue N = getValue(I.getOperand(0));
2350 MVT DestVT = TLI.getValueType(I.getType());
2351 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2354 void SelectionDAGLowering::visitUIToFP(User &I) {
2355 // UIToFP is never a no-op cast, no need to check
2356 SDValue N = getValue(I.getOperand(0));
2357 MVT DestVT = TLI.getValueType(I.getType());
2358 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2361 void SelectionDAGLowering::visitSIToFP(User &I){
2362 // SIToFP is never a no-op cast, no need to check
2363 SDValue N = getValue(I.getOperand(0));
2364 MVT DestVT = TLI.getValueType(I.getType());
2365 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2368 void SelectionDAGLowering::visitPtrToInt(User &I) {
2369 // What to do depends on the size of the integer and the size of the pointer.
2370 // We can either truncate, zero extend, or no-op, accordingly.
2371 SDValue N = getValue(I.getOperand(0));
2372 MVT SrcVT = N.getValueType();
2373 MVT DestVT = TLI.getValueType(I.getType());
2375 if (DestVT.bitsLT(SrcVT))
2376 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2378 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2379 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2380 setValue(&I, Result);
2383 void SelectionDAGLowering::visitIntToPtr(User &I) {
2384 // What to do depends on the size of the integer and the size of the pointer.
2385 // We can either truncate, zero extend, or no-op, accordingly.
2386 SDValue N = getValue(I.getOperand(0));
2387 MVT SrcVT = N.getValueType();
2388 MVT DestVT = TLI.getValueType(I.getType());
2389 if (DestVT.bitsLT(SrcVT))
2390 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2392 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2393 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2397 void SelectionDAGLowering::visitBitCast(User &I) {
2398 SDValue N = getValue(I.getOperand(0));
2399 MVT DestVT = TLI.getValueType(I.getType());
2401 // BitCast assures us that source and destination are the same size so this
2402 // is either a BIT_CONVERT or a no-op.
2403 if (DestVT != N.getValueType())
2404 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2405 DestVT, N)); // convert types
2407 setValue(&I, N); // noop cast.
2410 void SelectionDAGLowering::visitInsertElement(User &I) {
2411 SDValue InVec = getValue(I.getOperand(0));
2412 SDValue InVal = getValue(I.getOperand(1));
2413 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2415 getValue(I.getOperand(2)));
2417 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2418 TLI.getValueType(I.getType()),
2419 InVec, InVal, InIdx));
2422 void SelectionDAGLowering::visitExtractElement(User &I) {
2423 SDValue InVec = getValue(I.getOperand(0));
2424 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2426 getValue(I.getOperand(1)));
2427 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2428 TLI.getValueType(I.getType()), InVec, InIdx));
2432 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2433 // from SIndx and increasing to the element length (undefs are allowed).
2434 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2435 unsigned MaskNumElts = Mask.size();
2436 for (unsigned i = 0; i != MaskNumElts; ++i)
2437 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2442 void SelectionDAGLowering::visitShuffleVector(User &I) {
2443 SmallVector<int, 8> Mask;
2444 SDValue Src1 = getValue(I.getOperand(0));
2445 SDValue Src2 = getValue(I.getOperand(1));
2447 // Convert the ConstantVector mask operand into an array of ints, with -1
2448 // representing undef values.
2449 SmallVector<Constant*, 8> MaskElts;
2450 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2451 unsigned MaskNumElts = MaskElts.size();
2452 for (unsigned i = 0; i != MaskNumElts; ++i) {
2453 if (isa<UndefValue>(MaskElts[i]))
2456 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2459 MVT VT = TLI.getValueType(I.getType());
2460 MVT SrcVT = Src1.getValueType();
2461 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2463 if (SrcNumElts == MaskNumElts) {
2464 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2469 // Normalize the shuffle vector since mask and vector length don't match.
2470 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2471 // Mask is longer than the source vectors and is a multiple of the source
2472 // vectors. We can use concatenate vector to make the mask and vectors
2474 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2475 // The shuffle is concatenating two vectors together.
2476 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2481 // Pad both vectors with undefs to make them the same length as the mask.
2482 unsigned NumConcat = MaskNumElts / SrcNumElts;
2483 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2484 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2485 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2487 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2488 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2492 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2493 getCurDebugLoc(), VT,
2494 &MOps1[0], NumConcat);
2495 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2496 getCurDebugLoc(), VT,
2497 &MOps2[0], NumConcat);
2499 // Readjust mask for new input vector length.
2500 SmallVector<int, 8> MappedOps;
2501 for (unsigned i = 0; i != MaskNumElts; ++i) {
2503 if (Idx < (int)SrcNumElts)
2504 MappedOps.push_back(Idx);
2506 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2508 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2513 if (SrcNumElts > MaskNumElts) {
2514 // Analyze the access pattern of the vector to see if we can extract
2515 // two subvectors and do the shuffle. The analysis is done by calculating
2516 // the range of elements the mask access on both vectors.
2517 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2518 int MaxRange[2] = {-1, -1};
2520 for (unsigned i = 0; i != MaskNumElts; ++i) {
2526 if (Idx >= (int)SrcNumElts) {
2530 if (Idx > MaxRange[Input])
2531 MaxRange[Input] = Idx;
2532 if (Idx < MinRange[Input])
2533 MinRange[Input] = Idx;
2536 // Check if the access is smaller than the vector size and can we find
2537 // a reasonable extract index.
2538 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2539 int StartIdx[2]; // StartIdx to extract from
2540 for (int Input=0; Input < 2; ++Input) {
2541 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2542 RangeUse[Input] = 0; // Unused
2543 StartIdx[Input] = 0;
2544 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2545 // Fits within range but we should see if we can find a good
2546 // start index that is a multiple of the mask length.
2547 if (MaxRange[Input] < (int)MaskNumElts) {
2548 RangeUse[Input] = 1; // Extract from beginning of the vector
2549 StartIdx[Input] = 0;
2551 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2552 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2553 StartIdx[Input] + MaskNumElts < SrcNumElts)
2554 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2559 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2560 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2563 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2564 // Extract appropriate subvector and generate a vector shuffle
2565 for (int Input=0; Input < 2; ++Input) {
2566 SDValue& Src = Input == 0 ? Src1 : Src2;
2567 if (RangeUse[Input] == 0) {
2568 Src = DAG.getUNDEF(VT);
2570 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2571 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2574 // Calculate new mask.
2575 SmallVector<int, 8> MappedOps;
2576 for (unsigned i = 0; i != MaskNumElts; ++i) {
2579 MappedOps.push_back(Idx);
2580 else if (Idx < (int)SrcNumElts)
2581 MappedOps.push_back(Idx - StartIdx[0]);
2583 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2585 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2591 // We can't use either concat vectors or extract subvectors so fall back to
2592 // replacing the shuffle with extract and build vector.
2593 // to insert and build vector.
2594 MVT EltVT = VT.getVectorElementType();
2595 MVT PtrVT = TLI.getPointerTy();
2596 SmallVector<SDValue,8> Ops;
2597 for (unsigned i = 0; i != MaskNumElts; ++i) {
2599 Ops.push_back(DAG.getUNDEF(EltVT));
2602 if (Idx < (int)SrcNumElts)
2603 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2604 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2606 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2608 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2611 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2612 VT, &Ops[0], Ops.size()));
2615 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2616 const Value *Op0 = I.getOperand(0);
2617 const Value *Op1 = I.getOperand(1);
2618 const Type *AggTy = I.getType();
2619 const Type *ValTy = Op1->getType();
2620 bool IntoUndef = isa<UndefValue>(Op0);
2621 bool FromUndef = isa<UndefValue>(Op1);
2623 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2624 I.idx_begin(), I.idx_end());
2626 SmallVector<MVT, 4> AggValueVTs;
2627 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2628 SmallVector<MVT, 4> ValValueVTs;
2629 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2631 unsigned NumAggValues = AggValueVTs.size();
2632 unsigned NumValValues = ValValueVTs.size();
2633 SmallVector<SDValue, 4> Values(NumAggValues);
2635 SDValue Agg = getValue(Op0);
2636 SDValue Val = getValue(Op1);
2638 // Copy the beginning value(s) from the original aggregate.
2639 for (; i != LinearIndex; ++i)
2640 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2641 SDValue(Agg.getNode(), Agg.getResNo() + i);
2642 // Copy values from the inserted value(s).
2643 for (; i != LinearIndex + NumValValues; ++i)
2644 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2645 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2646 // Copy remaining value(s) from the original aggregate.
2647 for (; i != NumAggValues; ++i)
2648 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2649 SDValue(Agg.getNode(), Agg.getResNo() + i);
2651 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2652 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2653 &Values[0], NumAggValues));
2656 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2657 const Value *Op0 = I.getOperand(0);
2658 const Type *AggTy = Op0->getType();
2659 const Type *ValTy = I.getType();
2660 bool OutOfUndef = isa<UndefValue>(Op0);
2662 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2663 I.idx_begin(), I.idx_end());
2665 SmallVector<MVT, 4> ValValueVTs;
2666 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2668 unsigned NumValValues = ValValueVTs.size();
2669 SmallVector<SDValue, 4> Values(NumValValues);
2671 SDValue Agg = getValue(Op0);
2672 // Copy out the selected value(s).
2673 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2674 Values[i - LinearIndex] =
2676 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2677 SDValue(Agg.getNode(), Agg.getResNo() + i);
2679 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2680 DAG.getVTList(&ValValueVTs[0], NumValValues),
2681 &Values[0], NumValValues));
2685 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2686 SDValue N = getValue(I.getOperand(0));
2687 const Type *Ty = I.getOperand(0)->getType();
2689 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2692 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2693 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2696 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2697 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2698 DAG.getIntPtrConstant(Offset));
2700 Ty = StTy->getElementType(Field);
2702 Ty = cast<SequentialType>(Ty)->getElementType();
2704 // If this is a constant subscript, handle it quickly.
2705 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2706 if (CI->getZExtValue() == 0) continue;
2708 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2710 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2712 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2714 DAG.getConstant(Offs, MVT::i64));
2716 OffsVal = DAG.getIntPtrConstant(Offs);
2717 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2722 // N = N + Idx * ElementSize;
2723 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2724 SDValue IdxN = getValue(Idx);
2726 // If the index is smaller or larger than intptr_t, truncate or extend
2728 if (IdxN.getValueType().bitsLT(N.getValueType()))
2729 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2730 N.getValueType(), IdxN);
2731 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2732 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2733 N.getValueType(), IdxN);
2735 // If this is a multiply by a power of two, turn it into a shl
2736 // immediately. This is a very common case.
2737 if (ElementSize != 1) {
2738 if (isPowerOf2_64(ElementSize)) {
2739 unsigned Amt = Log2_64(ElementSize);
2740 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2741 N.getValueType(), IdxN,
2742 DAG.getConstant(Amt, TLI.getPointerTy()));
2744 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2745 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2746 N.getValueType(), IdxN, Scale);
2750 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2751 N.getValueType(), N, IdxN);
2757 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2758 // If this is a fixed sized alloca in the entry block of the function,
2759 // allocate it statically on the stack.
2760 if (FuncInfo.StaticAllocaMap.count(&I))
2761 return; // getValue will auto-populate this.
2763 const Type *Ty = I.getAllocatedType();
2764 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2766 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2769 SDValue AllocSize = getValue(I.getArraySize());
2771 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2773 DAG.getConstant(TySize, AllocSize.getValueType()));
2777 MVT IntPtr = TLI.getPointerTy();
2778 if (IntPtr.bitsLT(AllocSize.getValueType()))
2779 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2781 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2782 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2785 // Handle alignment. If the requested alignment is less than or equal to
2786 // the stack alignment, ignore it. If the size is greater than or equal to
2787 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2788 unsigned StackAlign =
2789 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2790 if (Align <= StackAlign)
2793 // Round the size of the allocation up to the stack alignment size
2794 // by add SA-1 to the size.
2795 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2796 AllocSize.getValueType(), AllocSize,
2797 DAG.getIntPtrConstant(StackAlign-1));
2798 // Mask out the low bits for alignment purposes.
2799 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2800 AllocSize.getValueType(), AllocSize,
2801 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2803 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2804 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2805 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2808 DAG.setRoot(DSA.getValue(1));
2810 // Inform the Frame Information that we have just allocated a variable-sized
2812 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2815 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2816 const Value *SV = I.getOperand(0);
2817 SDValue Ptr = getValue(SV);
2819 const Type *Ty = I.getType();
2820 bool isVolatile = I.isVolatile();
2821 unsigned Alignment = I.getAlignment();
2823 SmallVector<MVT, 4> ValueVTs;
2824 SmallVector<uint64_t, 4> Offsets;
2825 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2826 unsigned NumValues = ValueVTs.size();
2831 bool ConstantMemory = false;
2833 // Serialize volatile loads with other side effects.
2835 else if (AA->pointsToConstantMemory(SV)) {
2836 // Do not serialize (non-volatile) loads of constant memory with anything.
2837 Root = DAG.getEntryNode();
2838 ConstantMemory = true;
2840 // Do not serialize non-volatile loads against each other.
2841 Root = DAG.getRoot();
2844 SmallVector<SDValue, 4> Values(NumValues);
2845 SmallVector<SDValue, 4> Chains(NumValues);
2846 MVT PtrVT = Ptr.getValueType();
2847 for (unsigned i = 0; i != NumValues; ++i) {
2848 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2849 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2851 DAG.getConstant(Offsets[i], PtrVT)),
2853 isVolatile, Alignment);
2855 Chains[i] = L.getValue(1);
2858 if (!ConstantMemory) {
2859 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2861 &Chains[0], NumValues);
2865 PendingLoads.push_back(Chain);
2868 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2869 DAG.getVTList(&ValueVTs[0], NumValues),
2870 &Values[0], NumValues));
2874 void SelectionDAGLowering::visitStore(StoreInst &I) {
2875 Value *SrcV = I.getOperand(0);
2876 Value *PtrV = I.getOperand(1);
2878 SmallVector<MVT, 4> ValueVTs;
2879 SmallVector<uint64_t, 4> Offsets;
2880 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2881 unsigned NumValues = ValueVTs.size();
2885 // Get the lowered operands. Note that we do this after
2886 // checking if NumResults is zero, because with zero results
2887 // the operands won't have values in the map.
2888 SDValue Src = getValue(SrcV);
2889 SDValue Ptr = getValue(PtrV);
2891 SDValue Root = getRoot();
2892 SmallVector<SDValue, 4> Chains(NumValues);
2893 MVT PtrVT = Ptr.getValueType();
2894 bool isVolatile = I.isVolatile();
2895 unsigned Alignment = I.getAlignment();
2896 for (unsigned i = 0; i != NumValues; ++i)
2897 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2898 SDValue(Src.getNode(), Src.getResNo() + i),
2899 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2901 DAG.getConstant(Offsets[i], PtrVT)),
2903 isVolatile, Alignment);
2905 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2906 MVT::Other, &Chains[0], NumValues));
2909 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2911 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2912 unsigned Intrinsic) {
2913 bool HasChain = !I.doesNotAccessMemory();
2914 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2916 // Build the operand list.
2917 SmallVector<SDValue, 8> Ops;
2918 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2920 // We don't need to serialize loads against other loads.
2921 Ops.push_back(DAG.getRoot());
2923 Ops.push_back(getRoot());
2927 // Info is set by getTgtMemInstrinsic
2928 TargetLowering::IntrinsicInfo Info;
2929 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2931 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2932 if (!IsTgtIntrinsic)
2933 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2935 // Add all operands of the call to the operand list.
2936 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2937 SDValue Op = getValue(I.getOperand(i));
2938 assert(TLI.isTypeLegal(Op.getValueType()) &&
2939 "Intrinsic uses a non-legal type?");
2943 std::vector<MVT> VTArray;
2944 if (I.getType() != Type::VoidTy) {
2945 MVT VT = TLI.getValueType(I.getType());
2946 if (VT.isVector()) {
2947 const VectorType *DestTy = cast<VectorType>(I.getType());
2948 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2950 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2951 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2954 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2955 VTArray.push_back(VT);
2958 VTArray.push_back(MVT::Other);
2960 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2964 if (IsTgtIntrinsic) {
2965 // This is target intrinsic that touches memory
2966 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2967 VTs, &Ops[0], Ops.size(),
2968 Info.memVT, Info.ptrVal, Info.offset,
2969 Info.align, Info.vol,
2970 Info.readMem, Info.writeMem);
2973 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2974 VTs, &Ops[0], Ops.size());
2975 else if (I.getType() != Type::VoidTy)
2976 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2977 VTs, &Ops[0], Ops.size());
2979 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2980 VTs, &Ops[0], Ops.size());
2983 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2985 PendingLoads.push_back(Chain);
2989 if (I.getType() != Type::VoidTy) {
2990 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2991 MVT VT = TLI.getValueType(PTy);
2992 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2994 setValue(&I, Result);
2998 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2999 static GlobalVariable *ExtractTypeInfo(Value *V) {
3000 V = V->stripPointerCasts();
3001 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3002 assert ((GV || isa<ConstantPointerNull>(V)) &&
3003 "TypeInfo must be a global variable or NULL");
3009 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3010 /// call, and add them to the specified machine basic block.
3011 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3012 MachineBasicBlock *MBB) {
3013 // Inform the MachineModuleInfo of the personality for this landing pad.
3014 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3015 assert(CE->getOpcode() == Instruction::BitCast &&
3016 isa<Function>(CE->getOperand(0)) &&
3017 "Personality should be a function");
3018 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3020 // Gather all the type infos for this landing pad and pass them along to
3021 // MachineModuleInfo.
3022 std::vector<GlobalVariable *> TyInfo;
3023 unsigned N = I.getNumOperands();
3025 for (unsigned i = N - 1; i > 2; --i) {
3026 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3027 unsigned FilterLength = CI->getZExtValue();
3028 unsigned FirstCatch = i + FilterLength + !FilterLength;
3029 assert (FirstCatch <= N && "Invalid filter length");
3031 if (FirstCatch < N) {
3032 TyInfo.reserve(N - FirstCatch);
3033 for (unsigned j = FirstCatch; j < N; ++j)
3034 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3035 MMI->addCatchTypeInfo(MBB, TyInfo);
3039 if (!FilterLength) {
3041 MMI->addCleanup(MBB);
3044 TyInfo.reserve(FilterLength - 1);
3045 for (unsigned j = i + 1; j < FirstCatch; ++j)
3046 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3047 MMI->addFilterTypeInfo(MBB, TyInfo);
3056 TyInfo.reserve(N - 3);
3057 for (unsigned j = 3; j < N; ++j)
3058 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3059 MMI->addCatchTypeInfo(MBB, TyInfo);
3065 /// GetSignificand - Get the significand and build it into a floating-point
3066 /// number with exponent of 1:
3068 /// Op = (Op & 0x007fffff) | 0x3f800000;
3070 /// where Op is the hexidecimal representation of floating point value.
3072 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3073 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3074 DAG.getConstant(0x007fffff, MVT::i32));
3075 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3076 DAG.getConstant(0x3f800000, MVT::i32));
3077 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3080 /// GetExponent - Get the exponent:
3082 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3084 /// where Op is the hexidecimal representation of floating point value.
3086 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3088 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3089 DAG.getConstant(0x7f800000, MVT::i32));
3090 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3091 DAG.getConstant(23, TLI.getPointerTy()));
3092 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3093 DAG.getConstant(127, MVT::i32));
3094 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3097 /// getF32Constant - Get 32-bit floating point constant.
3099 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3100 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3103 /// Inlined utility function to implement binary input atomic intrinsics for
3104 /// visitIntrinsicCall: I is a call instruction
3105 /// Op is the associated NodeType for I
3107 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3108 SDValue Root = getRoot();
3110 DAG.getAtomic(Op, getCurDebugLoc(),
3111 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3113 getValue(I.getOperand(1)),
3114 getValue(I.getOperand(2)),
3117 DAG.setRoot(L.getValue(1));
3121 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3123 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3124 SDValue Op1 = getValue(I.getOperand(1));
3125 SDValue Op2 = getValue(I.getOperand(2));
3127 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3128 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3130 setValue(&I, Result);
3134 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3135 /// limited-precision mode.
3137 SelectionDAGLowering::visitExp(CallInst &I) {
3139 DebugLoc dl = getCurDebugLoc();
3141 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3142 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3143 SDValue Op = getValue(I.getOperand(1));
3145 // Put the exponent in the right bit position for later addition to the
3148 // #define LOG2OFe 1.4426950f
3149 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3150 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3151 getF32Constant(DAG, 0x3fb8aa3b));
3152 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3154 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3155 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3156 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3158 // IntegerPartOfX <<= 23;
3159 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3160 DAG.getConstant(23, TLI.getPointerTy()));
3162 if (LimitFloatPrecision <= 6) {
3163 // For floating-point precision of 6:
3165 // TwoToFractionalPartOfX =
3167 // (0.735607626f + 0.252464424f * x) * x;
3169 // error 0.0144103317, which is 6 bits
3170 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3171 getF32Constant(DAG, 0x3e814304));
3172 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3173 getF32Constant(DAG, 0x3f3c50c8));
3174 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3175 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3176 getF32Constant(DAG, 0x3f7f5e7e));
3177 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3179 // Add the exponent into the result in integer domain.
3180 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3181 TwoToFracPartOfX, IntegerPartOfX);
3183 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3184 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3185 // For floating-point precision of 12:
3187 // TwoToFractionalPartOfX =
3190 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3192 // 0.000107046256 error, which is 13 to 14 bits
3193 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3194 getF32Constant(DAG, 0x3da235e3));
3195 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3196 getF32Constant(DAG, 0x3e65b8f3));
3197 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3198 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3199 getF32Constant(DAG, 0x3f324b07));
3200 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3201 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3202 getF32Constant(DAG, 0x3f7ff8fd));
3203 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3205 // Add the exponent into the result in integer domain.
3206 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3207 TwoToFracPartOfX, IntegerPartOfX);
3209 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3210 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3211 // For floating-point precision of 18:
3213 // TwoToFractionalPartOfX =
3217 // (0.554906021e-1f +
3218 // (0.961591928e-2f +
3219 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3221 // error 2.47208000*10^(-7), which is better than 18 bits
3222 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3223 getF32Constant(DAG, 0x3924b03e));
3224 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3225 getF32Constant(DAG, 0x3ab24b87));
3226 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3227 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3228 getF32Constant(DAG, 0x3c1d8c17));
3229 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3230 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3231 getF32Constant(DAG, 0x3d634a1d));
3232 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3233 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3234 getF32Constant(DAG, 0x3e75fe14));
3235 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3236 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3237 getF32Constant(DAG, 0x3f317234));
3238 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3239 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3240 getF32Constant(DAG, 0x3f800000));
3241 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3244 // Add the exponent into the result in integer domain.
3245 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3246 TwoToFracPartOfX, IntegerPartOfX);
3248 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3251 // No special expansion.
3252 result = DAG.getNode(ISD::FEXP, dl,
3253 getValue(I.getOperand(1)).getValueType(),
3254 getValue(I.getOperand(1)));
3257 setValue(&I, result);
3260 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3261 /// limited-precision mode.
3263 SelectionDAGLowering::visitLog(CallInst &I) {
3265 DebugLoc dl = getCurDebugLoc();
3267 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3268 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3269 SDValue Op = getValue(I.getOperand(1));
3270 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3272 // Scale the exponent by log(2) [0.69314718f].
3273 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3274 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3275 getF32Constant(DAG, 0x3f317218));
3277 // Get the significand and build it into a floating-point number with
3279 SDValue X = GetSignificand(DAG, Op1, dl);
3281 if (LimitFloatPrecision <= 6) {
3282 // For floating-point precision of 6:
3286 // (1.4034025f - 0.23903021f * x) * x;
3288 // error 0.0034276066, which is better than 8 bits
3289 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3290 getF32Constant(DAG, 0xbe74c456));
3291 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3292 getF32Constant(DAG, 0x3fb3a2b1));
3293 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3294 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3295 getF32Constant(DAG, 0x3f949a29));
3297 result = DAG.getNode(ISD::FADD, dl,
3298 MVT::f32, LogOfExponent, LogOfMantissa);
3299 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3300 // For floating-point precision of 12:
3306 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3308 // error 0.000061011436, which is 14 bits
3309 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3310 getF32Constant(DAG, 0xbd67b6d6));
3311 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3312 getF32Constant(DAG, 0x3ee4f4b8));
3313 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3314 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3315 getF32Constant(DAG, 0x3fbc278b));
3316 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3317 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3318 getF32Constant(DAG, 0x40348e95));
3319 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3320 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3321 getF32Constant(DAG, 0x3fdef31a));
3323 result = DAG.getNode(ISD::FADD, dl,
3324 MVT::f32, LogOfExponent, LogOfMantissa);
3325 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3326 // For floating-point precision of 18:
3334 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3336 // error 0.0000023660568, which is better than 18 bits
3337 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3338 getF32Constant(DAG, 0xbc91e5ac));
3339 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3340 getF32Constant(DAG, 0x3e4350aa));
3341 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3342 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3343 getF32Constant(DAG, 0x3f60d3e3));
3344 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3345 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3346 getF32Constant(DAG, 0x4011cdf0));
3347 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3348 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3349 getF32Constant(DAG, 0x406cfd1c));
3350 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3351 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3352 getF32Constant(DAG, 0x408797cb));
3353 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3354 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3355 getF32Constant(DAG, 0x4006dcab));
3357 result = DAG.getNode(ISD::FADD, dl,
3358 MVT::f32, LogOfExponent, LogOfMantissa);
3361 // No special expansion.
3362 result = DAG.getNode(ISD::FLOG, dl,
3363 getValue(I.getOperand(1)).getValueType(),
3364 getValue(I.getOperand(1)));
3367 setValue(&I, result);
3370 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3371 /// limited-precision mode.
3373 SelectionDAGLowering::visitLog2(CallInst &I) {
3375 DebugLoc dl = getCurDebugLoc();
3377 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3378 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3379 SDValue Op = getValue(I.getOperand(1));
3380 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3382 // Get the exponent.
3383 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3385 // Get the significand and build it into a floating-point number with
3387 SDValue X = GetSignificand(DAG, Op1, dl);
3389 // Different possible minimax approximations of significand in
3390 // floating-point for various degrees of accuracy over [1,2].
3391 if (LimitFloatPrecision <= 6) {
3392 // For floating-point precision of 6:
3394 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3396 // error 0.0049451742, which is more than 7 bits
3397 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3398 getF32Constant(DAG, 0xbeb08fe0));
3399 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3400 getF32Constant(DAG, 0x40019463));
3401 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3402 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3403 getF32Constant(DAG, 0x3fd6633d));
3405 result = DAG.getNode(ISD::FADD, dl,
3406 MVT::f32, LogOfExponent, Log2ofMantissa);
3407 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3408 // For floating-point precision of 12:
3414 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3416 // error 0.0000876136000, which is better than 13 bits
3417 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3418 getF32Constant(DAG, 0xbda7262e));
3419 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3420 getF32Constant(DAG, 0x3f25280b));
3421 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3422 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3423 getF32Constant(DAG, 0x4007b923));
3424 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3425 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3426 getF32Constant(DAG, 0x40823e2f));
3427 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3428 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3429 getF32Constant(DAG, 0x4020d29c));
3431 result = DAG.getNode(ISD::FADD, dl,
3432 MVT::f32, LogOfExponent, Log2ofMantissa);
3433 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3434 // For floating-point precision of 18:
3443 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3445 // error 0.0000018516, which is better than 18 bits
3446 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3447 getF32Constant(DAG, 0xbcd2769e));
3448 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3449 getF32Constant(DAG, 0x3e8ce0b9));
3450 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3451 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3452 getF32Constant(DAG, 0x3fa22ae7));
3453 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3454 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3455 getF32Constant(DAG, 0x40525723));
3456 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3457 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3458 getF32Constant(DAG, 0x40aaf200));
3459 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3460 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3461 getF32Constant(DAG, 0x40c39dad));
3462 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3463 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3464 getF32Constant(DAG, 0x4042902c));
3466 result = DAG.getNode(ISD::FADD, dl,
3467 MVT::f32, LogOfExponent, Log2ofMantissa);
3470 // No special expansion.
3471 result = DAG.getNode(ISD::FLOG2, dl,
3472 getValue(I.getOperand(1)).getValueType(),
3473 getValue(I.getOperand(1)));
3476 setValue(&I, result);
3479 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3480 /// limited-precision mode.
3482 SelectionDAGLowering::visitLog10(CallInst &I) {
3484 DebugLoc dl = getCurDebugLoc();
3486 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3487 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3488 SDValue Op = getValue(I.getOperand(1));
3489 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3491 // Scale the exponent by log10(2) [0.30102999f].
3492 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3493 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3494 getF32Constant(DAG, 0x3e9a209a));
3496 // Get the significand and build it into a floating-point number with
3498 SDValue X = GetSignificand(DAG, Op1, dl);
3500 if (LimitFloatPrecision <= 6) {
3501 // For floating-point precision of 6:
3503 // Log10ofMantissa =
3505 // (0.60948995f - 0.10380950f * x) * x;
3507 // error 0.0014886165, which is 6 bits
3508 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3509 getF32Constant(DAG, 0xbdd49a13));
3510 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3511 getF32Constant(DAG, 0x3f1c0789));
3512 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3513 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3514 getF32Constant(DAG, 0x3f011300));
3516 result = DAG.getNode(ISD::FADD, dl,
3517 MVT::f32, LogOfExponent, Log10ofMantissa);
3518 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3519 // For floating-point precision of 12:
3521 // Log10ofMantissa =
3524 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3526 // error 0.00019228036, which is better than 12 bits
3527 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3528 getF32Constant(DAG, 0x3d431f31));
3529 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3530 getF32Constant(DAG, 0x3ea21fb2));
3531 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3532 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3533 getF32Constant(DAG, 0x3f6ae232));
3534 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3535 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3536 getF32Constant(DAG, 0x3f25f7c3));
3538 result = DAG.getNode(ISD::FADD, dl,
3539 MVT::f32, LogOfExponent, Log10ofMantissa);
3540 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3541 // For floating-point precision of 18:
3543 // Log10ofMantissa =
3548 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3550 // error 0.0000037995730, which is better than 18 bits
3551 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3552 getF32Constant(DAG, 0x3c5d51ce));
3553 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3554 getF32Constant(DAG, 0x3e00685a));
3555 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3556 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3557 getF32Constant(DAG, 0x3efb6798));
3558 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3559 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3560 getF32Constant(DAG, 0x3f88d192));
3561 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3562 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3563 getF32Constant(DAG, 0x3fc4316c));
3564 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3565 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3566 getF32Constant(DAG, 0x3f57ce70));
3568 result = DAG.getNode(ISD::FADD, dl,
3569 MVT::f32, LogOfExponent, Log10ofMantissa);
3572 // No special expansion.
3573 result = DAG.getNode(ISD::FLOG10, dl,
3574 getValue(I.getOperand(1)).getValueType(),
3575 getValue(I.getOperand(1)));
3578 setValue(&I, result);
3581 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3582 /// limited-precision mode.
3584 SelectionDAGLowering::visitExp2(CallInst &I) {
3586 DebugLoc dl = getCurDebugLoc();
3588 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3589 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3590 SDValue Op = getValue(I.getOperand(1));
3592 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3594 // FractionalPartOfX = x - (float)IntegerPartOfX;
3595 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3596 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3598 // IntegerPartOfX <<= 23;
3599 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3600 DAG.getConstant(23, TLI.getPointerTy()));
3602 if (LimitFloatPrecision <= 6) {
3603 // For floating-point precision of 6:
3605 // TwoToFractionalPartOfX =
3607 // (0.735607626f + 0.252464424f * x) * x;
3609 // error 0.0144103317, which is 6 bits
3610 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3611 getF32Constant(DAG, 0x3e814304));
3612 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3613 getF32Constant(DAG, 0x3f3c50c8));
3614 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3615 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3616 getF32Constant(DAG, 0x3f7f5e7e));
3617 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3618 SDValue TwoToFractionalPartOfX =
3619 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3621 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3622 MVT::f32, TwoToFractionalPartOfX);
3623 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3624 // For floating-point precision of 12:
3626 // TwoToFractionalPartOfX =
3629 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3631 // error 0.000107046256, which is 13 to 14 bits
3632 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3633 getF32Constant(DAG, 0x3da235e3));
3634 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3635 getF32Constant(DAG, 0x3e65b8f3));
3636 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3637 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3638 getF32Constant(DAG, 0x3f324b07));
3639 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3640 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3641 getF32Constant(DAG, 0x3f7ff8fd));
3642 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3643 SDValue TwoToFractionalPartOfX =
3644 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3646 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3647 MVT::f32, TwoToFractionalPartOfX);
3648 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3649 // For floating-point precision of 18:
3651 // TwoToFractionalPartOfX =
3655 // (0.554906021e-1f +
3656 // (0.961591928e-2f +
3657 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3658 // error 2.47208000*10^(-7), which is better than 18 bits
3659 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3660 getF32Constant(DAG, 0x3924b03e));
3661 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3662 getF32Constant(DAG, 0x3ab24b87));
3663 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3664 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3665 getF32Constant(DAG, 0x3c1d8c17));
3666 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3667 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3668 getF32Constant(DAG, 0x3d634a1d));
3669 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3670 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3671 getF32Constant(DAG, 0x3e75fe14));
3672 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3673 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3674 getF32Constant(DAG, 0x3f317234));
3675 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3676 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3677 getF32Constant(DAG, 0x3f800000));
3678 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3679 SDValue TwoToFractionalPartOfX =
3680 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3682 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3683 MVT::f32, TwoToFractionalPartOfX);
3686 // No special expansion.
3687 result = DAG.getNode(ISD::FEXP2, dl,
3688 getValue(I.getOperand(1)).getValueType(),
3689 getValue(I.getOperand(1)));
3692 setValue(&I, result);
3695 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3696 /// limited-precision mode with x == 10.0f.
3698 SelectionDAGLowering::visitPow(CallInst &I) {
3700 Value *Val = I.getOperand(1);
3701 DebugLoc dl = getCurDebugLoc();
3702 bool IsExp10 = false;
3704 if (getValue(Val).getValueType() == MVT::f32 &&
3705 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3706 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3707 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3708 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3710 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3715 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3716 SDValue Op = getValue(I.getOperand(2));
3718 // Put the exponent in the right bit position for later addition to the
3721 // #define LOG2OF10 3.3219281f
3722 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3723 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3724 getF32Constant(DAG, 0x40549a78));
3725 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3727 // FractionalPartOfX = x - (float)IntegerPartOfX;
3728 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3729 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3731 // IntegerPartOfX <<= 23;
3732 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3733 DAG.getConstant(23, TLI.getPointerTy()));
3735 if (LimitFloatPrecision <= 6) {
3736 // For floating-point precision of 6:
3738 // twoToFractionalPartOfX =
3740 // (0.735607626f + 0.252464424f * x) * x;
3742 // error 0.0144103317, which is 6 bits
3743 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3744 getF32Constant(DAG, 0x3e814304));
3745 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3746 getF32Constant(DAG, 0x3f3c50c8));
3747 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3748 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3749 getF32Constant(DAG, 0x3f7f5e7e));
3750 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3751 SDValue TwoToFractionalPartOfX =
3752 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3754 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3755 MVT::f32, TwoToFractionalPartOfX);
3756 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3757 // For floating-point precision of 12:
3759 // TwoToFractionalPartOfX =
3762 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3764 // error 0.000107046256, which is 13 to 14 bits
3765 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3766 getF32Constant(DAG, 0x3da235e3));
3767 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3768 getF32Constant(DAG, 0x3e65b8f3));
3769 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3770 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3771 getF32Constant(DAG, 0x3f324b07));
3772 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3773 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3774 getF32Constant(DAG, 0x3f7ff8fd));
3775 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3776 SDValue TwoToFractionalPartOfX =
3777 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3779 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3780 MVT::f32, TwoToFractionalPartOfX);
3781 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3782 // For floating-point precision of 18:
3784 // TwoToFractionalPartOfX =
3788 // (0.554906021e-1f +
3789 // (0.961591928e-2f +
3790 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3791 // error 2.47208000*10^(-7), which is better than 18 bits
3792 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3793 getF32Constant(DAG, 0x3924b03e));
3794 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3795 getF32Constant(DAG, 0x3ab24b87));
3796 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3797 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3798 getF32Constant(DAG, 0x3c1d8c17));
3799 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3800 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3801 getF32Constant(DAG, 0x3d634a1d));
3802 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3803 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3804 getF32Constant(DAG, 0x3e75fe14));
3805 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3806 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3807 getF32Constant(DAG, 0x3f317234));
3808 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3809 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3810 getF32Constant(DAG, 0x3f800000));
3811 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3812 SDValue TwoToFractionalPartOfX =
3813 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3815 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3816 MVT::f32, TwoToFractionalPartOfX);
3819 // No special expansion.
3820 result = DAG.getNode(ISD::FPOW, dl,
3821 getValue(I.getOperand(1)).getValueType(),
3822 getValue(I.getOperand(1)),
3823 getValue(I.getOperand(2)));
3826 setValue(&I, result);
3829 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3830 /// we want to emit this as a call to a named external function, return the name
3831 /// otherwise lower it and return null.
3833 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3834 DebugLoc dl = getCurDebugLoc();
3835 switch (Intrinsic) {
3837 // By default, turn this into a target intrinsic node.
3838 visitTargetIntrinsic(I, Intrinsic);
3840 case Intrinsic::vastart: visitVAStart(I); return 0;
3841 case Intrinsic::vaend: visitVAEnd(I); return 0;
3842 case Intrinsic::vacopy: visitVACopy(I); return 0;
3843 case Intrinsic::returnaddress:
3844 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3845 getValue(I.getOperand(1))));
3847 case Intrinsic::frameaddress:
3848 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3849 getValue(I.getOperand(1))));
3851 case Intrinsic::setjmp:
3852 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3854 case Intrinsic::longjmp:
3855 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3857 case Intrinsic::memcpy: {
3858 SDValue Op1 = getValue(I.getOperand(1));
3859 SDValue Op2 = getValue(I.getOperand(2));
3860 SDValue Op3 = getValue(I.getOperand(3));
3861 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3862 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3863 I.getOperand(1), 0, I.getOperand(2), 0));
3866 case Intrinsic::memset: {
3867 SDValue Op1 = getValue(I.getOperand(1));
3868 SDValue Op2 = getValue(I.getOperand(2));
3869 SDValue Op3 = getValue(I.getOperand(3));
3870 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3871 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3872 I.getOperand(1), 0));
3875 case Intrinsic::memmove: {
3876 SDValue Op1 = getValue(I.getOperand(1));
3877 SDValue Op2 = getValue(I.getOperand(2));
3878 SDValue Op3 = getValue(I.getOperand(3));
3879 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3881 // If the source and destination are known to not be aliases, we can
3882 // lower memmove as memcpy.
3883 uint64_t Size = -1ULL;
3884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3885 Size = C->getZExtValue();
3886 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3887 AliasAnalysis::NoAlias) {
3888 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3889 I.getOperand(1), 0, I.getOperand(2), 0));
3893 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3894 I.getOperand(1), 0, I.getOperand(2), 0));
3897 case Intrinsic::dbg_stoppoint: {
3898 DwarfWriter *DW = DAG.getDwarfWriter();
3899 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3900 if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
3901 MachineFunction &MF = DAG.getMachineFunction();
3902 if (OptLevel == CodeGenOpt::None)
3903 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3907 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3908 std::string Dir, FN;
3909 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
3910 CU.getFilename(FN));
3911 unsigned idx = MF.getOrCreateDebugLocID(SrcFile,
3912 SPI.getLine(), SPI.getColumn());
3913 setCurDebugLoc(DebugLoc::get(idx));
3917 case Intrinsic::dbg_region_start: {
3918 DwarfWriter *DW = DAG.getDwarfWriter();
3919 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3921 if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
3923 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3924 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3925 getRoot(), LabelID));
3930 case Intrinsic::dbg_region_end: {
3931 DwarfWriter *DW = DAG.getDwarfWriter();
3932 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3934 if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
3935 MachineFunction &MF = DAG.getMachineFunction();
3936 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3938 Subprogram.getLinkageName(SPName);
3940 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
3941 // This is end of inlined function. Debugging information for
3942 // inlined function is not handled yet (only supported by FastISel).
3943 if (OptLevel == CodeGenOpt::None) {
3944 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3946 // Returned ID is 0 if this is unbalanced "end of inlined
3947 // scope". This could happen if optimizer eats dbg intrinsics
3948 // or "beginning of inlined scope" is not recoginized due to
3949 // missing location info. In such cases, do ignore this region.end.
3950 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3957 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3958 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3959 getRoot(), LabelID));
3964 case Intrinsic::dbg_func_start: {
3965 DwarfWriter *DW = DAG.getDwarfWriter();
3967 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3968 Value *SP = FSI.getSubprogram();
3969 if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
3970 MachineFunction &MF = DAG.getMachineFunction();
3971 if (OptLevel == CodeGenOpt::None) {
3972 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
3973 // (most?) gdb expects.
3974 DebugLoc PrevLoc = CurDebugLoc;
3975 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3976 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3977 std::string Dir, FN;
3978 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
3979 CompileUnit.getFilename(FN));
3981 if (!Subprogram.describes(MF.getFunction())) {
3982 // This is a beginning of an inlined function.
3984 // If llvm.dbg.func.start is seen in a new block before any
3985 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3986 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3987 if (PrevLoc.isUnknown())
3990 // Record the source line.
3991 unsigned Line = Subprogram.getLineNumber();
3992 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3993 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
3995 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3996 getRoot(), LabelID));
3997 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3998 DW->RecordInlinedFnStart(&FSI, Subprogram, LabelID,
4003 // Record the source line.
4004 unsigned Line = Subprogram.getLineNumber();
4005 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4006 DW->RecordSourceLine(Line, 0, SrcFile);
4007 // llvm.dbg.func_start also defines beginning of function scope.
4008 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
4011 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4014 Subprogram.getLinkageName(SPName);
4016 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
4017 // This is beginning of inlined function. Debugging information for
4018 // inlined function is not handled yet (only supported by FastISel).
4022 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
4023 // what (most?) gdb expects.
4024 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4025 std::string Dir, FN;
4026 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4027 CompileUnit.getFilename(FN));
4029 // Record the source line but does not create a label for the normal
4030 // function start. It will be emitted at asm emission time. However,
4031 // create a label if this is a beginning of inlined function.
4032 unsigned Line = Subprogram.getLineNumber();
4033 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4034 // FIXME - Start new region because llvm.dbg.func_start also defines
4035 // beginning of function scope.
4041 case Intrinsic::dbg_declare: {
4042 if (OptLevel == CodeGenOpt::None) {
4043 DwarfWriter *DW = DAG.getDwarfWriter();
4044 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4045 Value *Variable = DI.getVariable();
4046 if (DW && DW->ValidDebugInfo(Variable, OptLevel))
4047 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
4048 getValue(DI.getAddress()), getValue(Variable)));
4050 // FIXME: Do something sensible here when we support debug declare.
4054 case Intrinsic::eh_exception: {
4055 if (!CurMBB->isLandingPad()) {
4056 // FIXME: Mark exception register as live in. Hack for PR1508.
4057 unsigned Reg = TLI.getExceptionAddressRegister();
4058 if (Reg) CurMBB->addLiveIn(Reg);
4060 // Insert the EXCEPTIONADDR instruction.
4061 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4063 Ops[0] = DAG.getRoot();
4064 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4066 DAG.setRoot(Op.getValue(1));
4070 case Intrinsic::eh_selector_i32:
4071 case Intrinsic::eh_selector_i64: {
4072 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4073 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4074 MVT::i32 : MVT::i64);
4077 if (CurMBB->isLandingPad())
4078 AddCatchInfo(I, MMI, CurMBB);
4081 FuncInfo.CatchInfoLost.insert(&I);
4083 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4084 unsigned Reg = TLI.getExceptionSelectorRegister();
4085 if (Reg) CurMBB->addLiveIn(Reg);
4088 // Insert the EHSELECTION instruction.
4089 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4091 Ops[0] = getValue(I.getOperand(1));
4093 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4095 DAG.setRoot(Op.getValue(1));
4097 setValue(&I, DAG.getConstant(0, VT));
4103 case Intrinsic::eh_typeid_for_i32:
4104 case Intrinsic::eh_typeid_for_i64: {
4105 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4106 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4107 MVT::i32 : MVT::i64);
4110 // Find the type id for the given typeinfo.
4111 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4113 unsigned TypeID = MMI->getTypeIDFor(GV);
4114 setValue(&I, DAG.getConstant(TypeID, VT));
4116 // Return something different to eh_selector.
4117 setValue(&I, DAG.getConstant(1, VT));
4123 case Intrinsic::eh_return_i32:
4124 case Intrinsic::eh_return_i64:
4125 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4126 MMI->setCallsEHReturn(true);
4127 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4130 getValue(I.getOperand(1)),
4131 getValue(I.getOperand(2))));
4133 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4137 case Intrinsic::eh_unwind_init:
4138 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4139 MMI->setCallsUnwindInit(true);
4144 case Intrinsic::eh_dwarf_cfa: {
4145 MVT VT = getValue(I.getOperand(1)).getValueType();
4147 if (VT.bitsGT(TLI.getPointerTy()))
4148 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4149 TLI.getPointerTy(), getValue(I.getOperand(1)));
4151 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4152 TLI.getPointerTy(), getValue(I.getOperand(1)));
4154 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4156 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4157 TLI.getPointerTy()),
4159 setValue(&I, DAG.getNode(ISD::ADD, dl,
4161 DAG.getNode(ISD::FRAMEADDR, dl,
4164 TLI.getPointerTy())),
4169 case Intrinsic::convertff:
4170 case Intrinsic::convertfsi:
4171 case Intrinsic::convertfui:
4172 case Intrinsic::convertsif:
4173 case Intrinsic::convertuif:
4174 case Intrinsic::convertss:
4175 case Intrinsic::convertsu:
4176 case Intrinsic::convertus:
4177 case Intrinsic::convertuu: {
4178 ISD::CvtCode Code = ISD::CVT_INVALID;
4179 switch (Intrinsic) {
4180 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4181 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4182 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4183 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4184 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4185 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4186 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4187 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4188 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4190 MVT DestVT = TLI.getValueType(I.getType());
4191 Value* Op1 = I.getOperand(1);
4192 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4193 DAG.getValueType(DestVT),
4194 DAG.getValueType(getValue(Op1).getValueType()),
4195 getValue(I.getOperand(2)),
4196 getValue(I.getOperand(3)),
4201 case Intrinsic::sqrt:
4202 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4203 getValue(I.getOperand(1)).getValueType(),
4204 getValue(I.getOperand(1))));
4206 case Intrinsic::powi:
4207 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4208 getValue(I.getOperand(1)).getValueType(),
4209 getValue(I.getOperand(1)),
4210 getValue(I.getOperand(2))));
4212 case Intrinsic::sin:
4213 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4214 getValue(I.getOperand(1)).getValueType(),
4215 getValue(I.getOperand(1))));
4217 case Intrinsic::cos:
4218 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4219 getValue(I.getOperand(1)).getValueType(),
4220 getValue(I.getOperand(1))));
4222 case Intrinsic::log:
4225 case Intrinsic::log2:
4228 case Intrinsic::log10:
4231 case Intrinsic::exp:
4234 case Intrinsic::exp2:
4237 case Intrinsic::pow:
4240 case Intrinsic::pcmarker: {
4241 SDValue Tmp = getValue(I.getOperand(1));
4242 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4245 case Intrinsic::readcyclecounter: {
4246 SDValue Op = getRoot();
4247 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4248 DAG.getVTList(MVT::i64, MVT::Other),
4251 DAG.setRoot(Tmp.getValue(1));
4254 case Intrinsic::part_select: {
4255 // Currently not implemented: just abort
4256 assert(0 && "part_select intrinsic not implemented");
4259 case Intrinsic::part_set: {
4260 // Currently not implemented: just abort
4261 assert(0 && "part_set intrinsic not implemented");
4264 case Intrinsic::bswap:
4265 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4266 getValue(I.getOperand(1)).getValueType(),
4267 getValue(I.getOperand(1))));
4269 case Intrinsic::cttz: {
4270 SDValue Arg = getValue(I.getOperand(1));
4271 MVT Ty = Arg.getValueType();
4272 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4273 setValue(&I, result);
4276 case Intrinsic::ctlz: {
4277 SDValue Arg = getValue(I.getOperand(1));
4278 MVT Ty = Arg.getValueType();
4279 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4280 setValue(&I, result);
4283 case Intrinsic::ctpop: {
4284 SDValue Arg = getValue(I.getOperand(1));
4285 MVT Ty = Arg.getValueType();
4286 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4287 setValue(&I, result);
4290 case Intrinsic::stacksave: {
4291 SDValue Op = getRoot();
4292 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4293 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4295 DAG.setRoot(Tmp.getValue(1));
4298 case Intrinsic::stackrestore: {
4299 SDValue Tmp = getValue(I.getOperand(1));
4300 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4303 case Intrinsic::stackprotector: {
4304 // Emit code into the DAG to store the stack guard onto the stack.
4305 MachineFunction &MF = DAG.getMachineFunction();
4306 MachineFrameInfo *MFI = MF.getFrameInfo();
4307 MVT PtrTy = TLI.getPointerTy();
4309 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4310 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4312 int FI = FuncInfo.StaticAllocaMap[Slot];
4313 MFI->setStackProtectorIndex(FI);
4315 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4317 // Store the stack protector onto the stack.
4318 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4319 PseudoSourceValue::getFixedStack(FI),
4321 setValue(&I, Result);
4322 DAG.setRoot(Result);
4325 case Intrinsic::var_annotation:
4326 // Discard annotate attributes
4329 case Intrinsic::init_trampoline: {
4330 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4334 Ops[1] = getValue(I.getOperand(1));
4335 Ops[2] = getValue(I.getOperand(2));
4336 Ops[3] = getValue(I.getOperand(3));
4337 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4338 Ops[5] = DAG.getSrcValue(F);
4340 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4341 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4345 DAG.setRoot(Tmp.getValue(1));
4349 case Intrinsic::gcroot:
4351 Value *Alloca = I.getOperand(1);
4352 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4354 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4355 GFI->addStackRoot(FI->getIndex(), TypeMap);
4359 case Intrinsic::gcread:
4360 case Intrinsic::gcwrite:
4361 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4364 case Intrinsic::flt_rounds: {
4365 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4369 case Intrinsic::trap: {
4370 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4374 case Intrinsic::uadd_with_overflow:
4375 return implVisitAluOverflow(I, ISD::UADDO);
4376 case Intrinsic::sadd_with_overflow:
4377 return implVisitAluOverflow(I, ISD::SADDO);
4378 case Intrinsic::usub_with_overflow:
4379 return implVisitAluOverflow(I, ISD::USUBO);
4380 case Intrinsic::ssub_with_overflow:
4381 return implVisitAluOverflow(I, ISD::SSUBO);
4382 case Intrinsic::umul_with_overflow:
4383 return implVisitAluOverflow(I, ISD::UMULO);
4384 case Intrinsic::smul_with_overflow:
4385 return implVisitAluOverflow(I, ISD::SMULO);
4387 case Intrinsic::prefetch: {
4390 Ops[1] = getValue(I.getOperand(1));
4391 Ops[2] = getValue(I.getOperand(2));
4392 Ops[3] = getValue(I.getOperand(3));
4393 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4397 case Intrinsic::memory_barrier: {
4400 for (int x = 1; x < 6; ++x)
4401 Ops[x] = getValue(I.getOperand(x));
4403 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4406 case Intrinsic::atomic_cmp_swap: {
4407 SDValue Root = getRoot();
4409 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4410 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4412 getValue(I.getOperand(1)),
4413 getValue(I.getOperand(2)),
4414 getValue(I.getOperand(3)),
4417 DAG.setRoot(L.getValue(1));
4420 case Intrinsic::atomic_load_add:
4421 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4422 case Intrinsic::atomic_load_sub:
4423 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4424 case Intrinsic::atomic_load_or:
4425 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4426 case Intrinsic::atomic_load_xor:
4427 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4428 case Intrinsic::atomic_load_and:
4429 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4430 case Intrinsic::atomic_load_nand:
4431 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4432 case Intrinsic::atomic_load_max:
4433 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4434 case Intrinsic::atomic_load_min:
4435 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4436 case Intrinsic::atomic_load_umin:
4437 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4438 case Intrinsic::atomic_load_umax:
4439 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4440 case Intrinsic::atomic_swap:
4441 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4446 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4448 MachineBasicBlock *LandingPad) {
4449 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4450 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4451 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4452 unsigned BeginLabel = 0, EndLabel = 0;
4454 TargetLowering::ArgListTy Args;
4455 TargetLowering::ArgListEntry Entry;
4456 Args.reserve(CS.arg_size());
4457 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4459 SDValue ArgNode = getValue(*i);
4460 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4462 unsigned attrInd = i - CS.arg_begin() + 1;
4463 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4464 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4465 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4466 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4467 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4468 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4469 Entry.Alignment = CS.getParamAlignment(attrInd);
4470 Args.push_back(Entry);
4473 if (LandingPad && MMI) {
4474 // Insert a label before the invoke call to mark the try range. This can be
4475 // used to detect deletion of the invoke via the MachineModuleInfo.
4476 BeginLabel = MMI->NextLabelID();
4477 // Both PendingLoads and PendingExports must be flushed here;
4478 // this call might not return.
4480 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4481 getControlRoot(), BeginLabel));
4484 std::pair<SDValue,SDValue> Result =
4485 TLI.LowerCallTo(getRoot(), CS.getType(),
4486 CS.paramHasAttr(0, Attribute::SExt),
4487 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4488 CS.paramHasAttr(0, Attribute::InReg),
4489 CS.getCallingConv(),
4490 IsTailCall && PerformTailCallOpt,
4491 Callee, Args, DAG, getCurDebugLoc());
4492 if (CS.getType() != Type::VoidTy)
4493 setValue(CS.getInstruction(), Result.first);
4494 DAG.setRoot(Result.second);
4496 if (LandingPad && MMI) {
4497 // Insert a label at the end of the invoke call to mark the try range. This
4498 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4499 EndLabel = MMI->NextLabelID();
4500 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4501 getRoot(), EndLabel));
4503 // Inform MachineModuleInfo of range.
4504 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4509 void SelectionDAGLowering::visitCall(CallInst &I) {
4510 const char *RenameFn = 0;
4511 if (Function *F = I.getCalledFunction()) {
4512 if (F->isDeclaration()) {
4513 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4515 if (unsigned IID = II->getIntrinsicID(F)) {
4516 RenameFn = visitIntrinsicCall(I, IID);
4521 if (unsigned IID = F->getIntrinsicID()) {
4522 RenameFn = visitIntrinsicCall(I, IID);
4528 // Check for well-known libc/libm calls. If the function is internal, it
4529 // can't be a library call.
4530 unsigned NameLen = F->getNameLen();
4531 if (!F->hasLocalLinkage() && NameLen) {
4532 const char *NameStr = F->getNameStart();
4533 if (NameStr[0] == 'c' &&
4534 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4535 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4536 if (I.getNumOperands() == 3 && // Basic sanity checks.
4537 I.getOperand(1)->getType()->isFloatingPoint() &&
4538 I.getType() == I.getOperand(1)->getType() &&
4539 I.getType() == I.getOperand(2)->getType()) {
4540 SDValue LHS = getValue(I.getOperand(1));
4541 SDValue RHS = getValue(I.getOperand(2));
4542 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4543 LHS.getValueType(), LHS, RHS));
4546 } else if (NameStr[0] == 'f' &&
4547 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4548 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4549 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4550 if (I.getNumOperands() == 2 && // Basic sanity checks.
4551 I.getOperand(1)->getType()->isFloatingPoint() &&
4552 I.getType() == I.getOperand(1)->getType()) {
4553 SDValue Tmp = getValue(I.getOperand(1));
4554 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4555 Tmp.getValueType(), Tmp));
4558 } else if (NameStr[0] == 's' &&
4559 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4560 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4561 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4562 if (I.getNumOperands() == 2 && // Basic sanity checks.
4563 I.getOperand(1)->getType()->isFloatingPoint() &&
4564 I.getType() == I.getOperand(1)->getType()) {
4565 SDValue Tmp = getValue(I.getOperand(1));
4566 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4567 Tmp.getValueType(), Tmp));
4570 } else if (NameStr[0] == 'c' &&
4571 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4572 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4573 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4574 if (I.getNumOperands() == 2 && // Basic sanity checks.
4575 I.getOperand(1)->getType()->isFloatingPoint() &&
4576 I.getType() == I.getOperand(1)->getType()) {
4577 SDValue Tmp = getValue(I.getOperand(1));
4578 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4579 Tmp.getValueType(), Tmp));
4584 } else if (isa<InlineAsm>(I.getOperand(0))) {
4591 Callee = getValue(I.getOperand(0));
4593 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4595 LowerCallTo(&I, Callee, I.isTailCall());
4599 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4600 /// this value and returns the result as a ValueVT value. This uses
4601 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4602 /// If the Flag pointer is NULL, no flag is used.
4603 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4605 SDValue *Flag) const {
4606 // Assemble the legal parts into the final values.
4607 SmallVector<SDValue, 4> Values(ValueVTs.size());
4608 SmallVector<SDValue, 8> Parts;
4609 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4610 // Copy the legal parts from the registers.
4611 MVT ValueVT = ValueVTs[Value];
4612 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4613 MVT RegisterVT = RegVTs[Value];
4615 Parts.resize(NumRegs);
4616 for (unsigned i = 0; i != NumRegs; ++i) {
4619 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4621 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4622 *Flag = P.getValue(2);
4624 Chain = P.getValue(1);
4626 // If the source register was virtual and if we know something about it,
4627 // add an assert node.
4628 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4629 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4630 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4631 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4632 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4633 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4635 unsigned RegSize = RegisterVT.getSizeInBits();
4636 unsigned NumSignBits = LOI.NumSignBits;
4637 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4639 // FIXME: We capture more information than the dag can represent. For
4640 // now, just use the tightest assertzext/assertsext possible.
4642 MVT FromVT(MVT::Other);
4643 if (NumSignBits == RegSize)
4644 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4645 else if (NumZeroBits >= RegSize-1)
4646 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4647 else if (NumSignBits > RegSize-8)
4648 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4649 else if (NumZeroBits >= RegSize-8)
4650 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4651 else if (NumSignBits > RegSize-16)
4652 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4653 else if (NumZeroBits >= RegSize-16)
4654 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4655 else if (NumSignBits > RegSize-32)
4656 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4657 else if (NumZeroBits >= RegSize-32)
4658 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4660 if (FromVT != MVT::Other) {
4661 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4662 RegisterVT, P, DAG.getValueType(FromVT));
4671 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4672 NumRegs, RegisterVT, ValueVT);
4677 return DAG.getNode(ISD::MERGE_VALUES, dl,
4678 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4679 &Values[0], ValueVTs.size());
4682 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4683 /// specified value into the registers specified by this object. This uses
4684 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4685 /// If the Flag pointer is NULL, no flag is used.
4686 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4687 SDValue &Chain, SDValue *Flag) const {
4688 // Get the list of the values's legal parts.
4689 unsigned NumRegs = Regs.size();
4690 SmallVector<SDValue, 8> Parts(NumRegs);
4691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4692 MVT ValueVT = ValueVTs[Value];
4693 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4694 MVT RegisterVT = RegVTs[Value];
4696 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4697 &Parts[Part], NumParts, RegisterVT);
4701 // Copy the parts into the registers.
4702 SmallVector<SDValue, 8> Chains(NumRegs);
4703 for (unsigned i = 0; i != NumRegs; ++i) {
4706 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4708 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4709 *Flag = Part.getValue(1);
4711 Chains[i] = Part.getValue(0);
4714 if (NumRegs == 1 || Flag)
4715 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4716 // flagged to it. That is the CopyToReg nodes and the user are considered
4717 // a single scheduling unit. If we create a TokenFactor and return it as
4718 // chain, then the TokenFactor is both a predecessor (operand) of the
4719 // user as well as a successor (the TF operands are flagged to the user).
4720 // c1, f1 = CopyToReg
4721 // c2, f2 = CopyToReg
4722 // c3 = TokenFactor c1, c2
4725 Chain = Chains[NumRegs-1];
4727 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4730 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4731 /// operand list. This adds the code marker and includes the number of
4732 /// values added into it.
4733 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4734 bool HasMatching,unsigned MatchingIdx,
4736 std::vector<SDValue> &Ops) const {
4737 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4738 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4739 unsigned Flag = Code | (Regs.size() << 3);
4741 Flag |= 0x80000000 | (MatchingIdx << 16);
4742 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4743 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4744 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4745 MVT RegisterVT = RegVTs[Value];
4746 for (unsigned i = 0; i != NumRegs; ++i) {
4747 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4748 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4753 /// isAllocatableRegister - If the specified register is safe to allocate,
4754 /// i.e. it isn't a stack pointer or some other special register, return the
4755 /// register class for the register. Otherwise, return null.
4756 static const TargetRegisterClass *
4757 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4758 const TargetLowering &TLI,
4759 const TargetRegisterInfo *TRI) {
4760 MVT FoundVT = MVT::Other;
4761 const TargetRegisterClass *FoundRC = 0;
4762 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4763 E = TRI->regclass_end(); RCI != E; ++RCI) {
4764 MVT ThisVT = MVT::Other;
4766 const TargetRegisterClass *RC = *RCI;
4767 // If none of the the value types for this register class are valid, we
4768 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4769 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4771 if (TLI.isTypeLegal(*I)) {
4772 // If we have already found this register in a different register class,
4773 // choose the one with the largest VT specified. For example, on
4774 // PowerPC, we favor f64 register classes over f32.
4775 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4782 if (ThisVT == MVT::Other) continue;
4784 // NOTE: This isn't ideal. In particular, this might allocate the
4785 // frame pointer in functions that need it (due to them not being taken
4786 // out of allocation, because a variable sized allocation hasn't been seen
4787 // yet). This is a slight code pessimization, but should still work.
4788 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4789 E = RC->allocation_order_end(MF); I != E; ++I)
4791 // We found a matching register class. Keep looking at others in case
4792 // we find one with larger registers that this physreg is also in.
4803 /// AsmOperandInfo - This contains information for each constraint that we are
4805 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4806 public TargetLowering::AsmOperandInfo {
4808 /// CallOperand - If this is the result output operand or a clobber
4809 /// this is null, otherwise it is the incoming operand to the CallInst.
4810 /// This gets modified as the asm is processed.
4811 SDValue CallOperand;
4813 /// AssignedRegs - If this is a register or register class operand, this
4814 /// contains the set of register corresponding to the operand.
4815 RegsForValue AssignedRegs;
4817 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4818 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4821 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4822 /// busy in OutputRegs/InputRegs.
4823 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4824 std::set<unsigned> &OutputRegs,
4825 std::set<unsigned> &InputRegs,
4826 const TargetRegisterInfo &TRI) const {
4828 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4829 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4832 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4833 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4837 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4838 /// corresponds to. If there is no Value* for this operand, it returns
4840 MVT getCallOperandValMVT(const TargetLowering &TLI,
4841 const TargetData *TD) const {
4842 if (CallOperandVal == 0) return MVT::Other;
4844 if (isa<BasicBlock>(CallOperandVal))
4845 return TLI.getPointerTy();
4847 const llvm::Type *OpTy = CallOperandVal->getType();
4849 // If this is an indirect operand, the operand is a pointer to the
4852 OpTy = cast<PointerType>(OpTy)->getElementType();
4854 // If OpTy is not a single value, it may be a struct/union that we
4855 // can tile with integers.
4856 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4857 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4866 OpTy = IntegerType::get(BitSize);
4871 return TLI.getValueType(OpTy, true);
4875 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4877 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4878 const TargetRegisterInfo &TRI) {
4879 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4881 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4882 for (; *Aliases; ++Aliases)
4883 Regs.insert(*Aliases);
4886 } // end llvm namespace.
4889 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4890 /// specified operand. We prefer to assign virtual registers, to allow the
4891 /// register allocator handle the assignment process. However, if the asm uses
4892 /// features that we can't model on machineinstrs, we have SDISel do the
4893 /// allocation. This produces generally horrible, but correct, code.
4895 /// OpInfo describes the operand.
4896 /// Input and OutputRegs are the set of already allocated physical registers.
4898 void SelectionDAGLowering::
4899 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4900 std::set<unsigned> &OutputRegs,
4901 std::set<unsigned> &InputRegs) {
4902 // Compute whether this value requires an input register, an output register,
4904 bool isOutReg = false;
4905 bool isInReg = false;
4906 switch (OpInfo.Type) {
4907 case InlineAsm::isOutput:
4910 // If there is an input constraint that matches this, we need to reserve
4911 // the input register so no other inputs allocate to it.
4912 isInReg = OpInfo.hasMatchingInput();
4914 case InlineAsm::isInput:
4918 case InlineAsm::isClobber:
4925 MachineFunction &MF = DAG.getMachineFunction();
4926 SmallVector<unsigned, 4> Regs;
4928 // If this is a constraint for a single physreg, or a constraint for a
4929 // register class, find it.
4930 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4931 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4932 OpInfo.ConstraintVT);
4934 unsigned NumRegs = 1;
4935 if (OpInfo.ConstraintVT != MVT::Other) {
4936 // If this is a FP input in an integer register (or visa versa) insert a bit
4937 // cast of the input value. More generally, handle any case where the input
4938 // value disagrees with the register class we plan to stick this in.
4939 if (OpInfo.Type == InlineAsm::isInput &&
4940 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4941 // Try to convert to the first MVT that the reg class contains. If the
4942 // types are identical size, use a bitcast to convert (e.g. two differing
4944 MVT RegVT = *PhysReg.second->vt_begin();
4945 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4946 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4947 RegVT, OpInfo.CallOperand);
4948 OpInfo.ConstraintVT = RegVT;
4949 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4950 // If the input is a FP value and we want it in FP registers, do a
4951 // bitcast to the corresponding integer type. This turns an f64 value
4952 // into i64, which can be passed with two i32 values on a 32-bit
4954 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4955 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4956 RegVT, OpInfo.CallOperand);
4957 OpInfo.ConstraintVT = RegVT;
4961 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4965 MVT ValueVT = OpInfo.ConstraintVT;
4967 // If this is a constraint for a specific physical register, like {r17},
4969 if (unsigned AssignedReg = PhysReg.first) {
4970 const TargetRegisterClass *RC = PhysReg.second;
4971 if (OpInfo.ConstraintVT == MVT::Other)
4972 ValueVT = *RC->vt_begin();
4974 // Get the actual register value type. This is important, because the user
4975 // may have asked for (e.g.) the AX register in i32 type. We need to
4976 // remember that AX is actually i16 to get the right extension.
4977 RegVT = *RC->vt_begin();
4979 // This is a explicit reference to a physical register.
4980 Regs.push_back(AssignedReg);
4982 // If this is an expanded reference, add the rest of the regs to Regs.
4984 TargetRegisterClass::iterator I = RC->begin();
4985 for (; *I != AssignedReg; ++I)
4986 assert(I != RC->end() && "Didn't find reg!");
4988 // Already added the first reg.
4990 for (; NumRegs; --NumRegs, ++I) {
4991 assert(I != RC->end() && "Ran out of registers to allocate!");
4995 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4996 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4997 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5001 // Otherwise, if this was a reference to an LLVM register class, create vregs
5002 // for this reference.
5003 if (const TargetRegisterClass *RC = PhysReg.second) {
5004 RegVT = *RC->vt_begin();
5005 if (OpInfo.ConstraintVT == MVT::Other)
5008 // Create the appropriate number of virtual registers.
5009 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5010 for (; NumRegs; --NumRegs)
5011 Regs.push_back(RegInfo.createVirtualRegister(RC));
5013 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5017 // This is a reference to a register class that doesn't directly correspond
5018 // to an LLVM register class. Allocate NumRegs consecutive, available,
5019 // registers from the class.
5020 std::vector<unsigned> RegClassRegs
5021 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5022 OpInfo.ConstraintVT);
5024 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5025 unsigned NumAllocated = 0;
5026 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5027 unsigned Reg = RegClassRegs[i];
5028 // See if this register is available.
5029 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5030 (isInReg && InputRegs.count(Reg))) { // Already used.
5031 // Make sure we find consecutive registers.
5036 // Check to see if this register is allocatable (i.e. don't give out the
5038 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5039 if (!RC) { // Couldn't allocate this register.
5040 // Reset NumAllocated to make sure we return consecutive registers.
5045 // Okay, this register is good, we can use it.
5048 // If we allocated enough consecutive registers, succeed.
5049 if (NumAllocated == NumRegs) {
5050 unsigned RegStart = (i-NumAllocated)+1;
5051 unsigned RegEnd = i+1;
5052 // Mark all of the allocated registers used.
5053 for (unsigned i = RegStart; i != RegEnd; ++i)
5054 Regs.push_back(RegClassRegs[i]);
5056 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5057 OpInfo.ConstraintVT);
5058 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5063 // Otherwise, we couldn't allocate enough registers for this.
5066 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5067 /// processed uses a memory 'm' constraint.
5069 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5070 const TargetLowering &TLI) {
5071 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5072 InlineAsm::ConstraintInfo &CI = CInfos[i];
5073 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5074 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5075 if (CType == TargetLowering::C_Memory)
5083 /// visitInlineAsm - Handle a call to an InlineAsm object.
5085 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5086 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5088 /// ConstraintOperands - Information about all of the constraints.
5089 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5091 // We won't need to flush pending loads if this asm doesn't touch
5092 // memory and is nonvolatile.
5093 SDValue Chain = IA->hasSideEffects() ? getRoot() : DAG.getRoot();
5096 std::set<unsigned> OutputRegs, InputRegs;
5098 // Do a prepass over the constraints, canonicalizing them, and building up the
5099 // ConstraintOperands list.
5100 std::vector<InlineAsm::ConstraintInfo>
5101 ConstraintInfos = IA->ParseConstraints();
5103 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5104 // Flush pending loads if this touches memory (includes clobbering it).
5105 // It's possible this is overly conservative.
5109 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5110 unsigned ResNo = 0; // ResNo - The result number of the next output.
5111 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5112 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5113 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5115 MVT OpVT = MVT::Other;
5117 // Compute the value type for each operand.
5118 switch (OpInfo.Type) {
5119 case InlineAsm::isOutput:
5120 // Indirect outputs just consume an argument.
5121 if (OpInfo.isIndirect) {
5122 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5126 // The return value of the call is this value. As such, there is no
5127 // corresponding argument.
5128 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5129 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5130 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5132 assert(ResNo == 0 && "Asm only has one result!");
5133 OpVT = TLI.getValueType(CS.getType());
5137 case InlineAsm::isInput:
5138 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5140 case InlineAsm::isClobber:
5145 // If this is an input or an indirect output, process the call argument.
5146 // BasicBlocks are labels, currently appearing only in asm's.
5147 if (OpInfo.CallOperandVal) {
5148 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5149 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5151 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5154 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5157 OpInfo.ConstraintVT = OpVT;
5160 // Second pass over the constraints: compute which constraint option to use
5161 // and assign registers to constraints that want a specific physreg.
5162 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5163 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5165 // If this is an output operand with a matching input operand, look up the
5166 // matching input. If their types mismatch, e.g. one is an integer, the
5167 // other is floating point, or their sizes are different, flag it as an
5169 if (OpInfo.hasMatchingInput()) {
5170 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5171 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5172 if ((OpInfo.ConstraintVT.isInteger() !=
5173 Input.ConstraintVT.isInteger()) ||
5174 (OpInfo.ConstraintVT.getSizeInBits() !=
5175 Input.ConstraintVT.getSizeInBits())) {
5176 cerr << "llvm: error: Unsupported asm: input constraint with a "
5177 << "matching output constraint of incompatible type!\n";
5180 Input.ConstraintVT = OpInfo.ConstraintVT;
5184 // Compute the constraint code and ConstraintType to use.
5185 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5187 // If this is a memory input, and if the operand is not indirect, do what we
5188 // need to to provide an address for the memory input.
5189 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5190 !OpInfo.isIndirect) {
5191 assert(OpInfo.Type == InlineAsm::isInput &&
5192 "Can only indirectify direct input operands!");
5194 // Memory operands really want the address of the value. If we don't have
5195 // an indirect input, put it in the constpool if we can, otherwise spill
5196 // it to a stack slot.
5198 // If the operand is a float, integer, or vector constant, spill to a
5199 // constant pool entry to get its address.
5200 Value *OpVal = OpInfo.CallOperandVal;
5201 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5202 isa<ConstantVector>(OpVal)) {
5203 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5204 TLI.getPointerTy());
5206 // Otherwise, create a stack slot and emit a store to it before the
5208 const Type *Ty = OpVal->getType();
5209 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5210 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5211 MachineFunction &MF = DAG.getMachineFunction();
5212 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5213 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5214 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5215 OpInfo.CallOperand, StackSlot, NULL, 0);
5216 OpInfo.CallOperand = StackSlot;
5219 // There is no longer a Value* corresponding to this operand.
5220 OpInfo.CallOperandVal = 0;
5221 // It is now an indirect operand.
5222 OpInfo.isIndirect = true;
5225 // If this constraint is for a specific register, allocate it before
5227 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5228 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5230 ConstraintInfos.clear();
5233 // Second pass - Loop over all of the operands, assigning virtual or physregs
5234 // to register class operands.
5235 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5236 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5238 // C_Register operands have already been allocated, Other/Memory don't need
5240 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5241 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5244 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5245 std::vector<SDValue> AsmNodeOperands;
5246 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5247 AsmNodeOperands.push_back(
5248 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5251 // Loop over all of the inputs, copying the operand values into the
5252 // appropriate registers and processing the output regs.
5253 RegsForValue RetValRegs;
5255 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5256 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5258 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5259 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5261 switch (OpInfo.Type) {
5262 case InlineAsm::isOutput: {
5263 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5264 OpInfo.ConstraintType != TargetLowering::C_Register) {
5265 // Memory output, or 'other' output (e.g. 'X' constraint).
5266 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5268 // Add information to the INLINEASM node to know about this output.
5269 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5270 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5271 TLI.getPointerTy()));
5272 AsmNodeOperands.push_back(OpInfo.CallOperand);
5276 // Otherwise, this is a register or register class output.
5278 // Copy the output from the appropriate register. Find a register that
5280 if (OpInfo.AssignedRegs.Regs.empty()) {
5281 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5282 << OpInfo.ConstraintCode << "'!\n";
5286 // If this is an indirect operand, store through the pointer after the
5288 if (OpInfo.isIndirect) {
5289 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5290 OpInfo.CallOperandVal));
5292 // This is the result value of the call.
5293 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5294 // Concatenate this output onto the outputs list.
5295 RetValRegs.append(OpInfo.AssignedRegs);
5298 // Add information to the INLINEASM node to know that this register is
5300 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5301 6 /* EARLYCLOBBER REGDEF */ :
5305 DAG, AsmNodeOperands);
5308 case InlineAsm::isInput: {
5309 SDValue InOperandVal = OpInfo.CallOperand;
5311 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5312 // If this is required to match an output register we have already set,
5313 // just use its register.
5314 unsigned OperandNo = OpInfo.getMatchedOperand();
5316 // Scan until we find the definition we already emitted of this operand.
5317 // When we find it, create a RegsForValue operand.
5318 unsigned CurOp = 2; // The first operand.
5319 for (; OperandNo; --OperandNo) {
5320 // Advance to the next operand.
5322 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5323 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5324 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5325 (OpFlag & 7) == 4 /*MEM*/) &&
5326 "Skipped past definitions?");
5327 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5331 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5332 if ((OpFlag & 7) == 2 /*REGDEF*/
5333 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5334 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5335 RegsForValue MatchedRegs;
5336 MatchedRegs.TLI = &TLI;
5337 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5338 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5339 MatchedRegs.RegVTs.push_back(RegVT);
5340 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5341 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5344 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5346 // Use the produced MatchedRegs object to
5347 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5349 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5350 true, OpInfo.getMatchedOperand(),
5351 DAG, AsmNodeOperands);
5354 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5355 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5356 "Unexpected number of operands");
5357 // Add information to the INLINEASM node to know about this input.
5358 // See InlineAsm.h isUseOperandTiedToDef.
5359 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5360 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5361 TLI.getPointerTy()));
5362 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5367 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5368 assert(!OpInfo.isIndirect &&
5369 "Don't know how to handle indirect other inputs yet!");
5371 std::vector<SDValue> Ops;
5372 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5373 hasMemory, Ops, DAG);
5375 cerr << "llvm: error: Invalid operand for inline asm constraint '"
5376 << OpInfo.ConstraintCode << "'!\n";
5380 // Add information to the INLINEASM node to know about this input.
5381 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5382 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5383 TLI.getPointerTy()));
5384 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5386 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5387 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5388 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5389 "Memory operands expect pointer values");
5391 // Add information to the INLINEASM node to know about this input.
5392 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5393 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5394 TLI.getPointerTy()));
5395 AsmNodeOperands.push_back(InOperandVal);
5399 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5400 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5401 "Unknown constraint type!");
5402 assert(!OpInfo.isIndirect &&
5403 "Don't know how to handle indirect register inputs yet!");
5405 // Copy the input into the appropriate registers.
5406 if (OpInfo.AssignedRegs.Regs.empty()) {
5407 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5408 << OpInfo.ConstraintCode << "'!\n";
5412 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5415 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5416 DAG, AsmNodeOperands);
5419 case InlineAsm::isClobber: {
5420 // Add the clobbered value to the operand list, so that the register
5421 // allocator is aware that the physreg got clobbered.
5422 if (!OpInfo.AssignedRegs.Regs.empty())
5423 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5424 false, 0, DAG,AsmNodeOperands);
5430 // Finish up input operands.
5431 AsmNodeOperands[0] = Chain;
5432 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5434 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5435 DAG.getVTList(MVT::Other, MVT::Flag),
5436 &AsmNodeOperands[0], AsmNodeOperands.size());
5437 Flag = Chain.getValue(1);
5439 // If this asm returns a register value, copy the result from that register
5440 // and set it as the value of the call.
5441 if (!RetValRegs.Regs.empty()) {
5442 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5445 // FIXME: Why don't we do this for inline asms with MRVs?
5446 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5447 MVT ResultType = TLI.getValueType(CS.getType());
5449 // If any of the results of the inline asm is a vector, it may have the
5450 // wrong width/num elts. This can happen for register classes that can
5451 // contain multiple different value types. The preg or vreg allocated may
5452 // not have the same VT as was expected. Convert it to the right type
5453 // with bit_convert.
5454 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5455 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5458 } else if (ResultType != Val.getValueType() &&
5459 ResultType.isInteger() && Val.getValueType().isInteger()) {
5460 // If a result value was tied to an input value, the computed result may
5461 // have a wider width than the expected result. Extract the relevant
5463 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5466 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5469 setValue(CS.getInstruction(), Val);
5470 // Don't need to use this as a chain in this case.
5471 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5475 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5477 // Process indirect outputs, first output all of the flagged copies out of
5479 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5480 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5481 Value *Ptr = IndirectStoresToEmit[i].second;
5482 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5484 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5487 // Emit the non-flagged stores from the physregs.
5488 SmallVector<SDValue, 8> OutChains;
5489 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5490 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5491 StoresToEmit[i].first,
5492 getValue(StoresToEmit[i].second),
5493 StoresToEmit[i].second, 0));
5494 if (!OutChains.empty())
5495 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5496 &OutChains[0], OutChains.size());
5501 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5502 SDValue Src = getValue(I.getOperand(0));
5504 // Scale up by the type size in the original i32 type width. Various
5505 // mid-level optimizers may make assumptions about demanded bits etc from the
5506 // i32-ness of the optimizer: we do not want to promote to i64 and then
5507 // multiply on 64-bit targets.
5508 // FIXME: Malloc inst should go away: PR715.
5509 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5510 if (ElementSize != 1)
5511 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5512 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5514 MVT IntPtr = TLI.getPointerTy();
5516 if (IntPtr.bitsLT(Src.getValueType()))
5517 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5518 else if (IntPtr.bitsGT(Src.getValueType()))
5519 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5521 TargetLowering::ArgListTy Args;
5522 TargetLowering::ArgListEntry Entry;
5524 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5525 Args.push_back(Entry);
5527 std::pair<SDValue,SDValue> Result =
5528 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5529 CallingConv::C, PerformTailCallOpt,
5530 DAG.getExternalSymbol("malloc", IntPtr),
5531 Args, DAG, getCurDebugLoc());
5532 setValue(&I, Result.first); // Pointers always fit in registers
5533 DAG.setRoot(Result.second);
5536 void SelectionDAGLowering::visitFree(FreeInst &I) {
5537 TargetLowering::ArgListTy Args;
5538 TargetLowering::ArgListEntry Entry;
5539 Entry.Node = getValue(I.getOperand(0));
5540 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5541 Args.push_back(Entry);
5542 MVT IntPtr = TLI.getPointerTy();
5543 std::pair<SDValue,SDValue> Result =
5544 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5545 CallingConv::C, PerformTailCallOpt,
5546 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5548 DAG.setRoot(Result.second);
5551 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5552 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5553 MVT::Other, getRoot(),
5554 getValue(I.getOperand(1)),
5555 DAG.getSrcValue(I.getOperand(1))));
5558 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5559 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5560 getRoot(), getValue(I.getOperand(0)),
5561 DAG.getSrcValue(I.getOperand(0)));
5563 DAG.setRoot(V.getValue(1));
5566 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5567 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5568 MVT::Other, getRoot(),
5569 getValue(I.getOperand(1)),
5570 DAG.getSrcValue(I.getOperand(1))));
5573 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5574 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5575 MVT::Other, getRoot(),
5576 getValue(I.getOperand(1)),
5577 getValue(I.getOperand(2)),
5578 DAG.getSrcValue(I.getOperand(1)),
5579 DAG.getSrcValue(I.getOperand(2))));
5582 /// TargetLowering::LowerArguments - This is the default LowerArguments
5583 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5584 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5585 /// integrated into SDISel.
5586 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5587 SmallVectorImpl<SDValue> &ArgValues,
5589 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5590 SmallVector<SDValue, 3+16> Ops;
5591 Ops.push_back(DAG.getRoot());
5592 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5593 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5595 // Add one result value for each formal argument.
5596 SmallVector<MVT, 16> RetVals;
5598 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5600 SmallVector<MVT, 4> ValueVTs;
5601 ComputeValueVTs(*this, I->getType(), ValueVTs);
5602 for (unsigned Value = 0, NumValues = ValueVTs.size();
5603 Value != NumValues; ++Value) {
5604 MVT VT = ValueVTs[Value];
5605 const Type *ArgTy = VT.getTypeForMVT();
5606 ISD::ArgFlagsTy Flags;
5607 unsigned OriginalAlignment =
5608 getTargetData()->getABITypeAlignment(ArgTy);
5610 if (F.paramHasAttr(j, Attribute::ZExt))
5612 if (F.paramHasAttr(j, Attribute::SExt))
5614 if (F.paramHasAttr(j, Attribute::InReg))
5616 if (F.paramHasAttr(j, Attribute::StructRet))
5618 if (F.paramHasAttr(j, Attribute::ByVal)) {
5620 const PointerType *Ty = cast<PointerType>(I->getType());
5621 const Type *ElementTy = Ty->getElementType();
5622 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5623 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5624 // For ByVal, alignment should be passed from FE. BE will guess if
5625 // this info is not there but there are cases it cannot get right.
5626 if (F.getParamAlignment(j))
5627 FrameAlign = F.getParamAlignment(j);
5628 Flags.setByValAlign(FrameAlign);
5629 Flags.setByValSize(FrameSize);
5631 if (F.paramHasAttr(j, Attribute::Nest))
5633 Flags.setOrigAlign(OriginalAlignment);
5635 MVT RegisterVT = getRegisterType(VT);
5636 unsigned NumRegs = getNumRegisters(VT);
5637 for (unsigned i = 0; i != NumRegs; ++i) {
5638 RetVals.push_back(RegisterVT);
5639 ISD::ArgFlagsTy MyFlags = Flags;
5640 if (NumRegs > 1 && i == 0)
5642 // if it isn't first piece, alignment must be 1
5644 MyFlags.setOrigAlign(1);
5645 Ops.push_back(DAG.getArgFlags(MyFlags));
5650 RetVals.push_back(MVT::Other);
5653 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5654 DAG.getVTList(&RetVals[0], RetVals.size()),
5655 &Ops[0], Ops.size()).getNode();
5657 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5658 // allows exposing the loads that may be part of the argument access to the
5659 // first DAGCombiner pass.
5660 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5662 // The number of results should match up, except that the lowered one may have
5663 // an extra flag result.
5664 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5665 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5666 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5667 && "Lowering produced unexpected number of results!");
5669 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5670 if (Result != TmpRes.getNode() && Result->use_empty()) {
5671 HandleSDNode Dummy(DAG.getRoot());
5672 DAG.RemoveDeadNode(Result);
5675 Result = TmpRes.getNode();
5677 unsigned NumArgRegs = Result->getNumValues() - 1;
5678 DAG.setRoot(SDValue(Result, NumArgRegs));
5680 // Set up the return result vector.
5683 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5685 SmallVector<MVT, 4> ValueVTs;
5686 ComputeValueVTs(*this, I->getType(), ValueVTs);
5687 for (unsigned Value = 0, NumValues = ValueVTs.size();
5688 Value != NumValues; ++Value) {
5689 MVT VT = ValueVTs[Value];
5690 MVT PartVT = getRegisterType(VT);
5692 unsigned NumParts = getNumRegisters(VT);
5693 SmallVector<SDValue, 4> Parts(NumParts);
5694 for (unsigned j = 0; j != NumParts; ++j)
5695 Parts[j] = SDValue(Result, i++);
5697 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5698 if (F.paramHasAttr(Idx, Attribute::SExt))
5699 AssertOp = ISD::AssertSext;
5700 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5701 AssertOp = ISD::AssertZext;
5703 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5704 PartVT, VT, AssertOp));
5707 assert(i == NumArgRegs && "Argument register count mismatch!");
5711 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5712 /// implementation, which just inserts an ISD::CALL node, which is later custom
5713 /// lowered by the target to something concrete. FIXME: When all targets are
5714 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5715 std::pair<SDValue, SDValue>
5716 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5717 bool RetSExt, bool RetZExt, bool isVarArg,
5719 unsigned CallingConv, bool isTailCall,
5721 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5722 assert((!isTailCall || PerformTailCallOpt) &&
5723 "isTailCall set when tail-call optimizations are disabled!");
5725 SmallVector<SDValue, 32> Ops;
5726 Ops.push_back(Chain); // Op#0 - Chain
5727 Ops.push_back(Callee);
5729 // Handle all of the outgoing arguments.
5730 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5731 SmallVector<MVT, 4> ValueVTs;
5732 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5733 for (unsigned Value = 0, NumValues = ValueVTs.size();
5734 Value != NumValues; ++Value) {
5735 MVT VT = ValueVTs[Value];
5736 const Type *ArgTy = VT.getTypeForMVT();
5737 SDValue Op = SDValue(Args[i].Node.getNode(),
5738 Args[i].Node.getResNo() + Value);
5739 ISD::ArgFlagsTy Flags;
5740 unsigned OriginalAlignment =
5741 getTargetData()->getABITypeAlignment(ArgTy);
5747 if (Args[i].isInReg)
5751 if (Args[i].isByVal) {
5753 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5754 const Type *ElementTy = Ty->getElementType();
5755 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5756 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5757 // For ByVal, alignment should come from FE. BE will guess if this
5758 // info is not there but there are cases it cannot get right.
5759 if (Args[i].Alignment)
5760 FrameAlign = Args[i].Alignment;
5761 Flags.setByValAlign(FrameAlign);
5762 Flags.setByValSize(FrameSize);
5766 Flags.setOrigAlign(OriginalAlignment);
5768 MVT PartVT = getRegisterType(VT);
5769 unsigned NumParts = getNumRegisters(VT);
5770 SmallVector<SDValue, 4> Parts(NumParts);
5771 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5774 ExtendKind = ISD::SIGN_EXTEND;
5775 else if (Args[i].isZExt)
5776 ExtendKind = ISD::ZERO_EXTEND;
5778 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5780 for (unsigned i = 0; i != NumParts; ++i) {
5781 // if it isn't first piece, alignment must be 1
5782 ISD::ArgFlagsTy MyFlags = Flags;
5783 if (NumParts > 1 && i == 0)
5786 MyFlags.setOrigAlign(1);
5788 Ops.push_back(Parts[i]);
5789 Ops.push_back(DAG.getArgFlags(MyFlags));
5794 // Figure out the result value types. We start by making a list of
5795 // the potentially illegal return value types.
5796 SmallVector<MVT, 4> LoweredRetTys;
5797 SmallVector<MVT, 4> RetTys;
5798 ComputeValueVTs(*this, RetTy, RetTys);
5800 // Then we translate that to a list of legal types.
5801 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5803 MVT RegisterVT = getRegisterType(VT);
5804 unsigned NumRegs = getNumRegisters(VT);
5805 for (unsigned i = 0; i != NumRegs; ++i)
5806 LoweredRetTys.push_back(RegisterVT);
5809 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5811 // Create the CALL node.
5812 SDValue Res = DAG.getCall(CallingConv, dl,
5813 isVarArg, isTailCall, isInreg,
5814 DAG.getVTList(&LoweredRetTys[0],
5815 LoweredRetTys.size()),
5818 Chain = Res.getValue(LoweredRetTys.size() - 1);
5820 // Gather up the call result into a single value.
5821 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5822 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5825 AssertOp = ISD::AssertSext;
5827 AssertOp = ISD::AssertZext;
5829 SmallVector<SDValue, 4> ReturnValues;
5831 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5833 MVT RegisterVT = getRegisterType(VT);
5834 unsigned NumRegs = getNumRegisters(VT);
5835 unsigned RegNoEnd = NumRegs + RegNo;
5836 SmallVector<SDValue, 4> Results;
5837 for (; RegNo != RegNoEnd; ++RegNo)
5838 Results.push_back(Res.getValue(RegNo));
5839 SDValue ReturnValue =
5840 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5842 ReturnValues.push_back(ReturnValue);
5844 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5845 DAG.getVTList(&RetTys[0], RetTys.size()),
5846 &ReturnValues[0], ReturnValues.size());
5849 return std::make_pair(Res, Chain);
5852 void TargetLowering::LowerOperationWrapper(SDNode *N,
5853 SmallVectorImpl<SDValue> &Results,
5854 SelectionDAG &DAG) {
5855 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5857 Results.push_back(Res);
5860 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5861 assert(0 && "LowerOperation not implemented for this target!");
5867 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5868 SDValue Op = getValue(V);
5869 assert((Op.getOpcode() != ISD::CopyFromReg ||
5870 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5871 "Copy from a reg to the same reg!");
5872 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5874 RegsForValue RFV(TLI, Reg, V->getType());
5875 SDValue Chain = DAG.getEntryNode();
5876 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5877 PendingExports.push_back(Chain);
5880 #include "llvm/CodeGen/SelectionDAGISel.h"
5882 void SelectionDAGISel::
5883 LowerArguments(BasicBlock *LLVMBB) {
5884 // If this is the entry block, emit arguments.
5885 Function &F = *LLVMBB->getParent();
5886 SDValue OldRoot = SDL->DAG.getRoot();
5887 SmallVector<SDValue, 16> Args;
5888 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5891 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5893 SmallVector<MVT, 4> ValueVTs;
5894 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5895 unsigned NumValues = ValueVTs.size();
5896 if (!AI->use_empty()) {
5897 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5898 SDL->getCurDebugLoc()));
5899 // If this argument is live outside of the entry block, insert a copy from
5900 // whereever we got it to the vreg that other BB's will reference it as.
5901 SDL->CopyToExportRegsIfNeeded(AI);
5906 // Finally, if the target has anything special to do, allow it to do so.
5907 // FIXME: this should insert code into the DAG!
5908 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5911 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5912 /// ensure constants are generated when needed. Remember the virtual registers
5913 /// that need to be added to the Machine PHI nodes as input. We cannot just
5914 /// directly add them, because expansion might result in multiple MBB's for one
5915 /// BB. As such, the start of the BB might correspond to a different MBB than
5919 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5920 TerminatorInst *TI = LLVMBB->getTerminator();
5922 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5924 // Check successor nodes' PHI nodes that expect a constant to be available
5926 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5927 BasicBlock *SuccBB = TI->getSuccessor(succ);
5928 if (!isa<PHINode>(SuccBB->begin())) continue;
5929 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5931 // If this terminator has multiple identical successors (common for
5932 // switches), only handle each succ once.
5933 if (!SuccsHandled.insert(SuccMBB)) continue;
5935 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5938 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5939 // nodes and Machine PHI nodes, but the incoming operands have not been
5941 for (BasicBlock::iterator I = SuccBB->begin();
5942 (PN = dyn_cast<PHINode>(I)); ++I) {
5943 // Ignore dead phi's.
5944 if (PN->use_empty()) continue;
5947 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5949 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5950 unsigned &RegOut = SDL->ConstantsOut[C];
5952 RegOut = FuncInfo->CreateRegForValue(C);
5953 SDL->CopyValueToVirtualRegister(C, RegOut);
5957 Reg = FuncInfo->ValueMap[PHIOp];
5959 assert(isa<AllocaInst>(PHIOp) &&
5960 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5961 "Didn't codegen value into a register!??");
5962 Reg = FuncInfo->CreateRegForValue(PHIOp);
5963 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5967 // Remember that this register needs to added to the machine PHI node as
5968 // the input for this MBB.
5969 SmallVector<MVT, 4> ValueVTs;
5970 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5971 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5972 MVT VT = ValueVTs[vti];
5973 unsigned NumRegisters = TLI.getNumRegisters(VT);
5974 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5975 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5976 Reg += NumRegisters;
5980 SDL->ConstantsOut.clear();
5983 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5984 /// supports legal types, and it emits MachineInstrs directly instead of
5985 /// creating SelectionDAG nodes.
5988 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5990 TerminatorInst *TI = LLVMBB->getTerminator();
5992 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5993 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5995 // Check successor nodes' PHI nodes that expect a constant to be available
5997 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5998 BasicBlock *SuccBB = TI->getSuccessor(succ);
5999 if (!isa<PHINode>(SuccBB->begin())) continue;
6000 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6002 // If this terminator has multiple identical successors (common for
6003 // switches), only handle each succ once.
6004 if (!SuccsHandled.insert(SuccMBB)) continue;
6006 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6009 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6010 // nodes and Machine PHI nodes, but the incoming operands have not been
6012 for (BasicBlock::iterator I = SuccBB->begin();
6013 (PN = dyn_cast<PHINode>(I)); ++I) {
6014 // Ignore dead phi's.
6015 if (PN->use_empty()) continue;
6017 // Only handle legal types. Two interesting things to note here. First,
6018 // by bailing out early, we may leave behind some dead instructions,
6019 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6020 // own moves. Second, this check is necessary becuase FastISel doesn't
6021 // use CreateRegForValue to create registers, so it always creates
6022 // exactly one register for each non-void instruction.
6023 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6024 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6027 VT = TLI.getTypeToTransformTo(VT);
6029 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6034 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6036 unsigned Reg = F->getRegForValue(PHIOp);
6038 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6041 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));