1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Base case: we can get an MVT for this LLVM IR type.
139 ValueVTs.push_back(TLI.getValueType(Ty));
141 Offsets->push_back(StartingOffset);
145 /// RegsForValue - This struct represents the registers (physical or virtual)
146 /// that a particular set of values is assigned, and the type information about
147 /// the value. The most common situation is to represent one value at a time,
148 /// but struct or array values are handled element-wise as multiple values.
149 /// The splitting of aggregates is performed recursively, so that we never
150 /// have aggregate-typed registers. The values at this point do not necessarily
151 /// have legal types, so each value may require one or more registers of some
154 struct VISIBILITY_HIDDEN RegsForValue {
155 /// TLI - The TargetLowering object.
157 const TargetLowering *TLI;
159 /// ValueVTs - The value types of the values, which may not be legal, and
160 /// may need be promoted or synthesized from one or more registers.
162 SmallVector<MVT, 4> ValueVTs;
164 /// RegVTs - The value types of the registers. This is the same size as
165 /// ValueVTs and it records, for each value, what the type of the assigned
166 /// register or registers are. (Individual values are never synthesized
167 /// from more than one type of register.)
169 /// With virtual registers, the contents of RegVTs is redundant with TLI's
170 /// getRegisterType member function, however when with physical registers
171 /// it is necessary to have a separate record of the types.
173 SmallVector<MVT, 4> RegVTs;
175 /// Regs - This list holds the registers assigned to the values.
176 /// Each legal or promoted value requires one register, and each
177 /// expanded value requires multiple registers.
179 SmallVector<unsigned, 4> Regs;
181 RegsForValue() : TLI(0) {}
183 RegsForValue(const TargetLowering &tli,
184 const SmallVector<unsigned, 4> ®s,
185 MVT regvt, MVT valuevt)
186 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> ®s,
189 const SmallVector<MVT, 4> ®vts,
190 const SmallVector<MVT, 4> &valuevts)
191 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
192 RegsForValue(const TargetLowering &tli,
193 unsigned Reg, const Type *Ty) : TLI(&tli) {
194 ComputeValueVTs(tli, Ty, ValueVTs);
196 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
197 MVT ValueVT = ValueVTs[Value];
198 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
199 MVT RegisterVT = TLI->getRegisterType(ValueVT);
200 for (unsigned i = 0; i != NumRegs; ++i)
201 Regs.push_back(Reg + i);
202 RegVTs.push_back(RegisterVT);
207 /// append - Add the specified values to this one.
208 void append(const RegsForValue &RHS) {
210 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
211 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
212 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
216 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
217 /// this value and returns the result as a ValueVTs value. This uses
218 /// Chain/Flag as the input and updates them for the output Chain/Flag.
219 /// If the Flag pointer is NULL, no flag is used.
220 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
221 SDValue &Chain, SDValue *Flag) const;
223 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
224 /// specified value into the registers specified by this object. This uses
225 /// Chain/Flag as the input and updates them for the output Chain/Flag.
226 /// If the Flag pointer is NULL, no flag is used.
227 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
228 SDValue &Chain, SDValue *Flag) const;
230 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
231 /// operand list. This adds the code marker and includes the number of
232 /// values added into it.
233 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
234 std::vector<SDValue> &Ops) const;
238 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
239 /// PHI nodes or outside of the basic block that defines it, or used by a
240 /// switch or atomic instruction, which may expand to multiple basic blocks.
241 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
242 if (isa<PHINode>(I)) return true;
243 BasicBlock *BB = I->getParent();
244 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
245 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
246 // FIXME: Remove switchinst special case.
247 isa<SwitchInst>(*UI))
252 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
253 /// entry block, return true. This includes arguments used by switches, since
254 /// the switch may expand into multiple basic blocks.
255 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
256 // With FastISel active, we may be splitting blocks, so force creation
257 // of virtual registers for all non-dead arguments.
258 // Don't force virtual registers for byval arguments though, because
259 // fast-isel can't handle those in all cases.
260 if (EnableFastISel && !A->hasByValAttr())
261 return A->use_empty();
263 BasicBlock *Entry = A->getParent()->begin();
264 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
265 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
266 return false; // Use not in entry block.
270 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
274 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
276 bool EnableFastISel) {
279 RegInfo = &MF->getRegInfo();
281 // Create a vreg for each argument register that is not dead and is used
282 // outside of the entry block for the function.
283 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
285 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
286 InitializeRegForValue(AI);
288 // Initialize the mapping of values to registers. This is only set up for
289 // instruction values that are used outside of the block that defines
291 Function::iterator BB = Fn->begin(), EB = Fn->end();
292 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
293 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
294 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
295 const Type *Ty = AI->getAllocatedType();
296 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
298 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
301 TySize *= CUI->getZExtValue(); // Get total allocated size.
302 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
303 StaticAllocaMap[AI] =
304 MF->getFrameInfo()->CreateStackObject(TySize, Align);
307 for (; BB != EB; ++BB)
308 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
309 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
310 if (!isa<AllocaInst>(I) ||
311 !StaticAllocaMap.count(cast<AllocaInst>(I)))
312 InitializeRegForValue(I);
314 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
315 // also creates the initial PHI MachineInstrs, though none of the input
316 // operands are populated.
317 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
318 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
322 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
326 for (BasicBlock::iterator
327 I = BB->begin(), E = BB->end(); I != E; ++I) {
328 if (CallInst *CI = dyn_cast<CallInst>(I)) {
329 if (Function *F = CI->getCalledFunction()) {
330 switch (F->getIntrinsicID()) {
332 case Intrinsic::dbg_stoppoint: {
333 DwarfWriter *DW = DAG.getDwarfWriter();
334 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
336 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
337 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
338 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(),
340 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
343 DL = DebugLoc::get(idx);
348 case Intrinsic::dbg_func_start: {
349 DwarfWriter *DW = DAG.getDwarfWriter();
351 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
352 Value *SP = FSI->getSubprogram();
354 if (DW->ValidDebugInfo(SP)) {
355 DISubprogram Subprogram(cast<GlobalVariable>(SP));
356 DICompileUnit CU(Subprogram.getCompileUnit());
357 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(),
359 unsigned Line = Subprogram.getLineNumber();
360 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
370 PN = dyn_cast<PHINode>(I);
371 if (!PN || PN->use_empty()) continue;
373 unsigned PHIReg = ValueMap[PN];
374 assert(PHIReg && "PHI node does not have an assigned virtual register!");
376 SmallVector<MVT, 4> ValueVTs;
377 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
378 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
379 MVT VT = ValueVTs[vti];
380 unsigned NumRegisters = TLI.getNumRegisters(VT);
381 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
382 for (unsigned i = 0; i != NumRegisters; ++i)
383 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
384 PHIReg += NumRegisters;
390 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
391 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
394 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
395 /// the correctly promoted or expanded types. Assign these registers
396 /// consecutive vreg numbers and return the first assigned number.
398 /// In the case that the given value has struct or array type, this function
399 /// will assign registers for each member or element.
401 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
402 SmallVector<MVT, 4> ValueVTs;
403 ComputeValueVTs(TLI, V->getType(), ValueVTs);
405 unsigned FirstReg = 0;
406 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
407 MVT ValueVT = ValueVTs[Value];
408 MVT RegisterVT = TLI.getRegisterType(ValueVT);
410 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
411 for (unsigned i = 0; i != NumRegs; ++i) {
412 unsigned R = MakeReg(RegisterVT);
413 if (!FirstReg) FirstReg = R;
419 /// getCopyFromParts - Create a value that contains the specified legal parts
420 /// combined into the value they represent. If the parts combine to a type
421 /// larger then ValueVT then AssertOp can be used to specify whether the extra
422 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
423 /// (ISD::AssertSext).
424 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
425 const SDValue *Parts,
426 unsigned NumParts, MVT PartVT, MVT ValueVT,
427 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
428 assert(NumParts > 0 && "No parts to assemble!");
429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
430 SDValue Val = Parts[0];
433 // Assemble the value from multiple parts.
434 if (!ValueVT.isVector()) {
435 unsigned PartBits = PartVT.getSizeInBits();
436 unsigned ValueBits = ValueVT.getSizeInBits();
438 // Assemble the power of 2 part.
439 unsigned RoundParts = NumParts & (NumParts - 1) ?
440 1 << Log2_32(NumParts) : NumParts;
441 unsigned RoundBits = PartBits * RoundParts;
442 MVT RoundVT = RoundBits == ValueBits ?
443 ValueVT : MVT::getIntegerVT(RoundBits);
446 MVT HalfVT = ValueVT.isInteger() ?
447 MVT::getIntegerVT(RoundBits/2) :
448 MVT::getFloatingPointVT(RoundBits/2);
450 if (RoundParts > 2) {
451 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
452 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
455 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
456 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
458 if (TLI.isBigEndian())
460 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
462 if (RoundParts < NumParts) {
463 // Assemble the trailing non-power-of-2 part.
464 unsigned OddParts = NumParts - RoundParts;
465 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
466 Hi = getCopyFromParts(DAG, dl,
467 Parts+RoundParts, OddParts, PartVT, OddVT);
469 // Combine the round and odd parts.
471 if (TLI.isBigEndian())
473 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
474 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
475 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
476 DAG.getConstant(Lo.getValueType().getSizeInBits(),
477 TLI.getPointerTy()));
478 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
479 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
482 // Handle a multi-element vector.
483 MVT IntermediateVT, RegisterVT;
484 unsigned NumIntermediates;
486 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
488 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
489 NumParts = NumRegs; // Silence a compiler warning.
490 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
491 assert(RegisterVT == Parts[0].getValueType() &&
492 "Part type doesn't match part!");
494 // Assemble the parts into intermediate operands.
495 SmallVector<SDValue, 8> Ops(NumIntermediates);
496 if (NumIntermediates == NumParts) {
497 // If the register was not expanded, truncate or copy the value,
499 for (unsigned i = 0; i != NumParts; ++i)
500 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
501 PartVT, IntermediateVT);
502 } else if (NumParts > 0) {
503 // If the intermediate type was expanded, build the intermediate operands
505 assert(NumParts % NumIntermediates == 0 &&
506 "Must expand into a divisible number of parts!");
507 unsigned Factor = NumParts / NumIntermediates;
508 for (unsigned i = 0; i != NumIntermediates; ++i)
509 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
510 PartVT, IntermediateVT);
513 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
515 Val = DAG.getNode(IntermediateVT.isVector() ?
516 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
517 ValueVT, &Ops[0], NumIntermediates);
521 // There is now one part, held in Val. Correct it to match ValueVT.
522 PartVT = Val.getValueType();
524 if (PartVT == ValueVT)
527 if (PartVT.isVector()) {
528 assert(ValueVT.isVector() && "Unknown vector conversion!");
529 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
532 if (ValueVT.isVector()) {
533 assert(ValueVT.getVectorElementType() == PartVT &&
534 ValueVT.getVectorNumElements() == 1 &&
535 "Only trivial scalar-to-vector conversions should get here!");
536 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
539 if (PartVT.isInteger() &&
540 ValueVT.isInteger()) {
541 if (ValueVT.bitsLT(PartVT)) {
542 // For a truncate, see if we have any information to
543 // indicate whether the truncated bits will always be
544 // zero or sign-extension.
545 if (AssertOp != ISD::DELETED_NODE)
546 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
547 DAG.getValueType(ValueVT));
548 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
550 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
554 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
555 if (ValueVT.bitsLT(Val.getValueType()))
556 // FP_ROUND's are always exact here.
557 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
558 DAG.getIntPtrConstant(1));
559 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
562 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
563 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
565 assert(0 && "Unknown mismatch!");
569 /// getCopyToParts - Create a series of nodes that contain the specified value
570 /// split into legal parts. If the parts contain more bits than Val, then, for
571 /// integers, ExtendKind can be used to specify how to generate the extra bits.
572 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
573 SDValue *Parts, unsigned NumParts, MVT PartVT,
574 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
575 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
576 MVT PtrVT = TLI.getPointerTy();
577 MVT ValueVT = Val.getValueType();
578 unsigned PartBits = PartVT.getSizeInBits();
579 unsigned OrigNumParts = NumParts;
580 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
585 if (!ValueVT.isVector()) {
586 if (PartVT == ValueVT) {
587 assert(NumParts == 1 && "No-op copy with multiple parts!");
592 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
593 // If the parts cover more bits than the value has, promote the value.
594 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
595 assert(NumParts == 1 && "Do not know what to promote to!");
596 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
597 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
598 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
599 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
601 assert(0 && "Unknown mismatch!");
603 } else if (PartBits == ValueVT.getSizeInBits()) {
604 // Different types of the same size.
605 assert(NumParts == 1 && PartVT != ValueVT);
606 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
607 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
608 // If the parts cover less bits than value has, truncate the value.
609 if (PartVT.isInteger() && ValueVT.isInteger()) {
610 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
611 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
613 assert(0 && "Unknown mismatch!");
617 // The value may have changed - recompute ValueVT.
618 ValueVT = Val.getValueType();
619 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
620 "Failed to tile the value with PartVT!");
623 assert(PartVT == ValueVT && "Type conversion failed!");
628 // Expand the value into multiple parts.
629 if (NumParts & (NumParts - 1)) {
630 // The number of parts is not a power of 2. Split off and copy the tail.
631 assert(PartVT.isInteger() && ValueVT.isInteger() &&
632 "Do not know what to expand to!");
633 unsigned RoundParts = 1 << Log2_32(NumParts);
634 unsigned RoundBits = RoundParts * PartBits;
635 unsigned OddParts = NumParts - RoundParts;
636 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
637 DAG.getConstant(RoundBits,
638 TLI.getPointerTy()));
639 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
640 if (TLI.isBigEndian())
641 // The odd parts were reversed by getCopyToParts - unreverse them.
642 std::reverse(Parts + RoundParts, Parts + NumParts);
643 NumParts = RoundParts;
644 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
645 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
648 // The number of parts is a power of 2. Repeatedly bisect the value using
650 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
651 MVT::getIntegerVT(ValueVT.getSizeInBits()),
653 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
654 for (unsigned i = 0; i < NumParts; i += StepSize) {
655 unsigned ThisBits = StepSize * PartBits / 2;
656 MVT ThisVT = MVT::getIntegerVT (ThisBits);
657 SDValue &Part0 = Parts[i];
658 SDValue &Part1 = Parts[i+StepSize/2];
660 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
662 DAG.getConstant(1, PtrVT));
663 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
665 DAG.getConstant(0, PtrVT));
667 if (ThisBits == PartBits && ThisVT != PartVT) {
668 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
670 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
676 if (TLI.isBigEndian())
677 std::reverse(Parts, Parts + OrigNumParts);
684 if (PartVT != ValueVT) {
685 if (PartVT.isVector()) {
686 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
688 assert(ValueVT.getVectorElementType() == PartVT &&
689 ValueVT.getVectorNumElements() == 1 &&
690 "Only trivial vector-to-scalar conversions should get here!");
691 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
693 DAG.getConstant(0, PtrVT));
701 // Handle a multi-element vector.
702 MVT IntermediateVT, RegisterVT;
703 unsigned NumIntermediates;
704 unsigned NumRegs = TLI
705 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
707 unsigned NumElements = ValueVT.getVectorNumElements();
709 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
710 NumParts = NumRegs; // Silence a compiler warning.
711 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
713 // Split the vector into intermediate operands.
714 SmallVector<SDValue, 8> Ops(NumIntermediates);
715 for (unsigned i = 0; i != NumIntermediates; ++i)
716 if (IntermediateVT.isVector())
717 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
719 DAG.getConstant(i * (NumElements / NumIntermediates),
722 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
724 DAG.getConstant(i, PtrVT));
726 // Split the intermediate operands into legal parts.
727 if (NumParts == NumIntermediates) {
728 // If the register was not expanded, promote or copy the value,
730 for (unsigned i = 0; i != NumParts; ++i)
731 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
732 } else if (NumParts > 0) {
733 // If the intermediate type was expanded, split each the value into
735 assert(NumParts % NumIntermediates == 0 &&
736 "Must expand into a divisible number of parts!");
737 unsigned Factor = NumParts / NumIntermediates;
738 for (unsigned i = 0; i != NumIntermediates; ++i)
739 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
744 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
747 TD = DAG.getTarget().getTargetData();
750 /// clear - Clear out the curret SelectionDAG and the associated
751 /// state and prepare this SelectionDAGLowering object to be used
752 /// for a new block. This doesn't clear out information about
753 /// additional blocks that are needed to complete switch lowering
754 /// or PHI node updating; that information is cleared out as it is
756 void SelectionDAGLowering::clear() {
758 PendingLoads.clear();
759 PendingExports.clear();
761 CurDebugLoc = DebugLoc::getUnknownLoc();
764 /// getRoot - Return the current virtual root of the Selection DAG,
765 /// flushing any PendingLoad items. This must be done before emitting
766 /// a store or any other node that may need to be ordered after any
767 /// prior load instructions.
769 SDValue SelectionDAGLowering::getRoot() {
770 if (PendingLoads.empty())
771 return DAG.getRoot();
773 if (PendingLoads.size() == 1) {
774 SDValue Root = PendingLoads[0];
776 PendingLoads.clear();
780 // Otherwise, we have to make a token factor node.
781 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
782 &PendingLoads[0], PendingLoads.size());
783 PendingLoads.clear();
788 /// getControlRoot - Similar to getRoot, but instead of flushing all the
789 /// PendingLoad items, flush all the PendingExports items. It is necessary
790 /// to do this before emitting a terminator instruction.
792 SDValue SelectionDAGLowering::getControlRoot() {
793 SDValue Root = DAG.getRoot();
795 if (PendingExports.empty())
798 // Turn all of the CopyToReg chains into one factored node.
799 if (Root.getOpcode() != ISD::EntryToken) {
800 unsigned i = 0, e = PendingExports.size();
801 for (; i != e; ++i) {
802 assert(PendingExports[i].getNode()->getNumOperands() > 1);
803 if (PendingExports[i].getNode()->getOperand(0) == Root)
804 break; // Don't add the root if we already indirectly depend on it.
808 PendingExports.push_back(Root);
811 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
813 PendingExports.size());
814 PendingExports.clear();
819 void SelectionDAGLowering::visit(Instruction &I) {
820 visit(I.getOpcode(), I);
823 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
824 // Note: this doesn't use InstVisitor, because it has to work with
825 // ConstantExpr's in addition to instructions.
827 default: assert(0 && "Unknown instruction type encountered!");
829 // Build the switch statement using the Instruction.def file.
830 #define HANDLE_INST(NUM, OPCODE, CLASS) \
831 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
832 #include "llvm/Instruction.def"
836 void SelectionDAGLowering::visitAdd(User &I) {
837 if (I.getType()->isFPOrFPVector())
838 visitBinary(I, ISD::FADD);
840 visitBinary(I, ISD::ADD);
843 void SelectionDAGLowering::visitMul(User &I) {
844 if (I.getType()->isFPOrFPVector())
845 visitBinary(I, ISD::FMUL);
847 visitBinary(I, ISD::MUL);
850 SDValue SelectionDAGLowering::getValue(const Value *V) {
851 SDValue &N = NodeMap[V];
852 if (N.getNode()) return N;
854 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
855 MVT VT = TLI.getValueType(V->getType(), true);
857 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
858 return N = DAG.getConstant(*CI, VT);
860 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
861 return N = DAG.getGlobalAddress(GV, VT);
863 if (isa<ConstantPointerNull>(C))
864 return N = DAG.getConstant(0, TLI.getPointerTy());
866 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
867 return N = DAG.getConstantFP(*CFP, VT);
869 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
870 !V->getType()->isAggregateType())
871 return N = DAG.getUNDEF(VT);
873 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
874 visit(CE->getOpcode(), *CE);
875 SDValue N1 = NodeMap[V];
876 assert(N1.getNode() && "visit didn't populate the ValueMap!");
880 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
881 SmallVector<SDValue, 4> Constants;
882 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
884 SDNode *Val = getValue(*OI).getNode();
885 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
886 Constants.push_back(SDValue(Val, i));
888 return DAG.getMergeValues(&Constants[0], Constants.size(),
892 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
893 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
894 "Unknown struct or array constant!");
896 SmallVector<MVT, 4> ValueVTs;
897 ComputeValueVTs(TLI, C->getType(), ValueVTs);
898 unsigned NumElts = ValueVTs.size();
900 return SDValue(); // empty struct
901 SmallVector<SDValue, 4> Constants(NumElts);
902 for (unsigned i = 0; i != NumElts; ++i) {
903 MVT EltVT = ValueVTs[i];
904 if (isa<UndefValue>(C))
905 Constants[i] = DAG.getUNDEF(EltVT);
906 else if (EltVT.isFloatingPoint())
907 Constants[i] = DAG.getConstantFP(0, EltVT);
909 Constants[i] = DAG.getConstant(0, EltVT);
911 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
914 const VectorType *VecTy = cast<VectorType>(V->getType());
915 unsigned NumElements = VecTy->getNumElements();
917 // Now that we know the number and type of the elements, get that number of
918 // elements into the Ops array based on what kind of constant it is.
919 SmallVector<SDValue, 16> Ops;
920 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
921 for (unsigned i = 0; i != NumElements; ++i)
922 Ops.push_back(getValue(CP->getOperand(i)));
924 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
925 "Unknown vector constant!");
926 MVT EltVT = TLI.getValueType(VecTy->getElementType());
929 if (isa<UndefValue>(C))
930 Op = DAG.getUNDEF(EltVT);
931 else if (EltVT.isFloatingPoint())
932 Op = DAG.getConstantFP(0, EltVT);
934 Op = DAG.getConstant(0, EltVT);
935 Ops.assign(NumElements, Op);
938 // Create a BUILD_VECTOR node.
939 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
940 VT, &Ops[0], Ops.size());
943 // If this is a static alloca, generate it as the frameindex instead of
945 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
946 DenseMap<const AllocaInst*, int>::iterator SI =
947 FuncInfo.StaticAllocaMap.find(AI);
948 if (SI != FuncInfo.StaticAllocaMap.end())
949 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
952 unsigned InReg = FuncInfo.ValueMap[V];
953 assert(InReg && "Value not in map!");
955 RegsForValue RFV(TLI, InReg, V->getType());
956 SDValue Chain = DAG.getEntryNode();
957 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
961 void SelectionDAGLowering::visitRet(ReturnInst &I) {
962 if (I.getNumOperands() == 0) {
963 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
964 MVT::Other, getControlRoot()));
968 SmallVector<SDValue, 8> NewValues;
969 NewValues.push_back(getControlRoot());
970 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
971 SmallVector<MVT, 4> ValueVTs;
972 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
973 unsigned NumValues = ValueVTs.size();
974 if (NumValues == 0) continue;
976 SDValue RetOp = getValue(I.getOperand(i));
977 for (unsigned j = 0, f = NumValues; j != f; ++j) {
978 MVT VT = ValueVTs[j];
980 // FIXME: C calling convention requires the return type to be promoted to
981 // at least 32-bit. But this is not necessary for non-C calling
983 if (VT.isInteger()) {
984 MVT MinVT = TLI.getRegisterType(MVT::i32);
985 if (VT.bitsLT(MinVT))
989 unsigned NumParts = TLI.getNumRegisters(VT);
990 MVT PartVT = TLI.getRegisterType(VT);
991 SmallVector<SDValue, 4> Parts(NumParts);
992 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
994 const Function *F = I.getParent()->getParent();
995 if (F->paramHasAttr(0, Attribute::SExt))
996 ExtendKind = ISD::SIGN_EXTEND;
997 else if (F->paramHasAttr(0, Attribute::ZExt))
998 ExtendKind = ISD::ZERO_EXTEND;
1000 getCopyToParts(DAG, getCurDebugLoc(),
1001 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1002 &Parts[0], NumParts, PartVT, ExtendKind);
1004 // 'inreg' on function refers to return value
1005 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1006 if (F->paramHasAttr(0, Attribute::InReg))
1008 for (unsigned i = 0; i < NumParts; ++i) {
1009 NewValues.push_back(Parts[i]);
1010 NewValues.push_back(DAG.getArgFlags(Flags));
1014 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1015 &NewValues[0], NewValues.size()));
1018 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1019 /// the current basic block, add it to ValueMap now so that we'll get a
1021 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1022 // No need to export constants.
1023 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1025 // Already exported?
1026 if (FuncInfo.isExportedInst(V)) return;
1028 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1029 CopyValueToVirtualRegister(V, Reg);
1032 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1033 const BasicBlock *FromBB) {
1034 // The operands of the setcc have to be in this block. We don't know
1035 // how to export them from some other block.
1036 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1037 // Can export from current BB.
1038 if (VI->getParent() == FromBB)
1041 // Is already exported, noop.
1042 return FuncInfo.isExportedInst(V);
1045 // If this is an argument, we can export it if the BB is the entry block or
1046 // if it is already exported.
1047 if (isa<Argument>(V)) {
1048 if (FromBB == &FromBB->getParent()->getEntryBlock())
1051 // Otherwise, can only export this if it is already exported.
1052 return FuncInfo.isExportedInst(V);
1055 // Otherwise, constants can always be exported.
1059 static bool InBlock(const Value *V, const BasicBlock *BB) {
1060 if (const Instruction *I = dyn_cast<Instruction>(V))
1061 return I->getParent() == BB;
1065 /// getFCmpCondCode - Return the ISD condition code corresponding to
1066 /// the given LLVM IR floating-point condition code. This includes
1067 /// consideration of global floating-point math flags.
1069 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1070 ISD::CondCode FPC, FOC;
1072 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1073 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1074 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1075 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1076 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1077 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1078 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1079 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1080 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1081 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1082 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1083 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1084 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1085 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1086 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1087 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1089 assert(0 && "Invalid FCmp predicate opcode!");
1090 FOC = FPC = ISD::SETFALSE;
1093 if (FiniteOnlyFPMath())
1099 /// getICmpCondCode - Return the ISD condition code corresponding to
1100 /// the given LLVM IR integer condition code.
1102 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1104 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1105 case ICmpInst::ICMP_NE: return ISD::SETNE;
1106 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1107 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1108 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1109 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1110 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1111 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1112 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1113 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1115 assert(0 && "Invalid ICmp predicate opcode!");
1120 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1121 /// This function emits a branch and is used at the leaves of an OR or an
1122 /// AND operator tree.
1125 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1126 MachineBasicBlock *TBB,
1127 MachineBasicBlock *FBB,
1128 MachineBasicBlock *CurBB) {
1129 const BasicBlock *BB = CurBB->getBasicBlock();
1131 // If the leaf of the tree is a comparison, merge the condition into
1133 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1134 // The operands of the cmp have to be in this block. We don't know
1135 // how to export them from some other block. If this is the first block
1136 // of the sequence, no exporting is needed.
1137 if (CurBB == CurMBB ||
1138 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1139 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1140 ISD::CondCode Condition;
1141 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1142 Condition = getICmpCondCode(IC->getPredicate());
1143 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1144 Condition = getFCmpCondCode(FC->getPredicate());
1146 Condition = ISD::SETEQ; // silence warning.
1147 assert(0 && "Unknown compare instruction");
1150 CaseBlock CB(Condition, BOp->getOperand(0),
1151 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1152 SwitchCases.push_back(CB);
1157 // Create a CaseBlock record representing this branch.
1158 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1159 NULL, TBB, FBB, CurBB);
1160 SwitchCases.push_back(CB);
1163 /// FindMergedConditions - If Cond is an expression like
1164 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1165 MachineBasicBlock *TBB,
1166 MachineBasicBlock *FBB,
1167 MachineBasicBlock *CurBB,
1169 // If this node is not part of the or/and tree, emit it as a branch.
1170 Instruction *BOp = dyn_cast<Instruction>(Cond);
1171 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1172 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1173 BOp->getParent() != CurBB->getBasicBlock() ||
1174 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1175 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1176 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1180 // Create TmpBB after CurBB.
1181 MachineFunction::iterator BBI = CurBB;
1182 MachineFunction &MF = DAG.getMachineFunction();
1183 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1184 CurBB->getParent()->insert(++BBI, TmpBB);
1186 if (Opc == Instruction::Or) {
1187 // Codegen X | Y as:
1195 // Emit the LHS condition.
1196 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1198 // Emit the RHS condition into TmpBB.
1199 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1201 assert(Opc == Instruction::And && "Unknown merge op!");
1202 // Codegen X & Y as:
1209 // This requires creation of TmpBB after CurBB.
1211 // Emit the LHS condition.
1212 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1214 // Emit the RHS condition into TmpBB.
1215 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1219 /// If the set of cases should be emitted as a series of branches, return true.
1220 /// If we should emit this as a bunch of and/or'd together conditions, return
1223 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1224 if (Cases.size() != 2) return true;
1226 // If this is two comparisons of the same values or'd or and'd together, they
1227 // will get folded into a single comparison, so don't emit two blocks.
1228 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1229 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1230 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1231 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1238 void SelectionDAGLowering::visitBr(BranchInst &I) {
1239 // Update machine-CFG edges.
1240 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1242 // Figure out which block is immediately after the current one.
1243 MachineBasicBlock *NextBlock = 0;
1244 MachineFunction::iterator BBI = CurMBB;
1245 if (++BBI != CurMBB->getParent()->end())
1248 if (I.isUnconditional()) {
1249 // Update machine-CFG edges.
1250 CurMBB->addSuccessor(Succ0MBB);
1252 // If this is not a fall-through branch, emit the branch.
1253 if (Succ0MBB != NextBlock)
1254 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1255 MVT::Other, getControlRoot(),
1256 DAG.getBasicBlock(Succ0MBB)));
1260 // If this condition is one of the special cases we handle, do special stuff
1262 Value *CondVal = I.getCondition();
1263 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1265 // If this is a series of conditions that are or'd or and'd together, emit
1266 // this as a sequence of branches instead of setcc's with and/or operations.
1267 // For example, instead of something like:
1280 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1281 if (BOp->hasOneUse() &&
1282 (BOp->getOpcode() == Instruction::And ||
1283 BOp->getOpcode() == Instruction::Or)) {
1284 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1285 // If the compares in later blocks need to use values not currently
1286 // exported from this block, export them now. This block should always
1287 // be the first entry.
1288 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1290 // Allow some cases to be rejected.
1291 if (ShouldEmitAsBranches(SwitchCases)) {
1292 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1293 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1294 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1297 // Emit the branch for this block.
1298 visitSwitchCase(SwitchCases[0]);
1299 SwitchCases.erase(SwitchCases.begin());
1303 // Okay, we decided not to do this, remove any inserted MBB's and clear
1305 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1306 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1308 SwitchCases.clear();
1312 // Create a CaseBlock record representing this branch.
1313 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1314 NULL, Succ0MBB, Succ1MBB, CurMBB);
1315 // Use visitSwitchCase to actually insert the fast branch sequence for this
1317 visitSwitchCase(CB);
1320 /// visitSwitchCase - Emits the necessary code to represent a single node in
1321 /// the binary search tree resulting from lowering a switch instruction.
1322 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1324 SDValue CondLHS = getValue(CB.CmpLHS);
1325 DebugLoc dl = getCurDebugLoc();
1327 // Build the setcc now.
1328 if (CB.CmpMHS == NULL) {
1329 // Fold "(X == true)" to X and "(X == false)" to !X to
1330 // handle common cases produced by branch lowering.
1331 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1333 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1334 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1335 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1337 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1339 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1341 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1342 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1344 SDValue CmpOp = getValue(CB.CmpMHS);
1345 MVT VT = CmpOp.getValueType();
1347 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1348 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1351 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1352 VT, CmpOp, DAG.getConstant(Low, VT));
1353 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1354 DAG.getConstant(High-Low, VT), ISD::SETULE);
1358 // Update successor info
1359 CurMBB->addSuccessor(CB.TrueBB);
1360 CurMBB->addSuccessor(CB.FalseBB);
1362 // Set NextBlock to be the MBB immediately after the current one, if any.
1363 // This is used to avoid emitting unnecessary branches to the next block.
1364 MachineBasicBlock *NextBlock = 0;
1365 MachineFunction::iterator BBI = CurMBB;
1366 if (++BBI != CurMBB->getParent()->end())
1369 // If the lhs block is the next block, invert the condition so that we can
1370 // fall through to the lhs instead of the rhs block.
1371 if (CB.TrueBB == NextBlock) {
1372 std::swap(CB.TrueBB, CB.FalseBB);
1373 SDValue True = DAG.getConstant(1, Cond.getValueType());
1374 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1376 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1377 MVT::Other, getControlRoot(), Cond,
1378 DAG.getBasicBlock(CB.TrueBB));
1380 // If the branch was constant folded, fix up the CFG.
1381 if (BrCond.getOpcode() == ISD::BR) {
1382 CurMBB->removeSuccessor(CB.FalseBB);
1383 DAG.setRoot(BrCond);
1385 // Otherwise, go ahead and insert the false branch.
1386 if (BrCond == getControlRoot())
1387 CurMBB->removeSuccessor(CB.TrueBB);
1389 if (CB.FalseBB == NextBlock)
1390 DAG.setRoot(BrCond);
1392 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1393 DAG.getBasicBlock(CB.FalseBB)));
1397 /// visitJumpTable - Emit JumpTable node in the current MBB
1398 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1399 // Emit the code for the jump table
1400 assert(JT.Reg != -1U && "Should lower JT Header first!");
1401 MVT PTy = TLI.getPointerTy();
1402 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1404 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1405 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1406 MVT::Other, Index.getValue(1),
1410 /// visitJumpTableHeader - This function emits necessary code to produce index
1411 /// in the JumpTable from switch case.
1412 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1413 JumpTableHeader &JTH) {
1414 // Subtract the lowest switch case value from the value being switched on and
1415 // conditional branch to default mbb if the result is greater than the
1416 // difference between smallest and largest cases.
1417 SDValue SwitchOp = getValue(JTH.SValue);
1418 MVT VT = SwitchOp.getValueType();
1419 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1420 DAG.getConstant(JTH.First, VT));
1422 // The SDNode we just created, which holds the value being switched on minus
1423 // the the smallest case value, needs to be copied to a virtual register so it
1424 // can be used as an index into the jump table in a subsequent basic block.
1425 // This value may be smaller or larger than the target's pointer type, and
1426 // therefore require extension or truncating.
1427 if (VT.bitsGT(TLI.getPointerTy()))
1428 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1429 TLI.getPointerTy(), SUB);
1431 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1432 TLI.getPointerTy(), SUB);
1434 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1435 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1436 JumpTableReg, SwitchOp);
1437 JT.Reg = JumpTableReg;
1439 // Emit the range check for the jump table, and branch to the default block
1440 // for the switch statement if the value being switched on exceeds the largest
1441 // case in the switch.
1442 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1443 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1444 DAG.getConstant(JTH.Last-JTH.First,VT),
1447 // Set NextBlock to be the MBB immediately after the current one, if any.
1448 // This is used to avoid emitting unnecessary branches to the next block.
1449 MachineBasicBlock *NextBlock = 0;
1450 MachineFunction::iterator BBI = CurMBB;
1451 if (++BBI != CurMBB->getParent()->end())
1454 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1455 MVT::Other, CopyTo, CMP,
1456 DAG.getBasicBlock(JT.Default));
1458 if (JT.MBB == NextBlock)
1459 DAG.setRoot(BrCond);
1461 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1462 DAG.getBasicBlock(JT.MBB)));
1465 /// visitBitTestHeader - This function emits necessary code to produce value
1466 /// suitable for "bit tests"
1467 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1468 // Subtract the minimum value
1469 SDValue SwitchOp = getValue(B.SValue);
1470 MVT VT = SwitchOp.getValueType();
1471 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1472 DAG.getConstant(B.First, VT));
1475 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1476 TLI.getSetCCResultType(SUB.getValueType()),
1477 SUB, DAG.getConstant(B.Range, VT),
1481 if (VT.bitsGT(TLI.getPointerTy()))
1482 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1483 TLI.getPointerTy(), SUB);
1485 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1486 TLI.getPointerTy(), SUB);
1488 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1489 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1492 // Set NextBlock to be the MBB immediately after the current one, if any.
1493 // This is used to avoid emitting unnecessary branches to the next block.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CurMBB;
1496 if (++BBI != CurMBB->getParent()->end())
1499 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1501 CurMBB->addSuccessor(B.Default);
1502 CurMBB->addSuccessor(MBB);
1504 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1505 MVT::Other, CopyTo, RangeCmp,
1506 DAG.getBasicBlock(B.Default));
1508 if (MBB == NextBlock)
1509 DAG.setRoot(BrRange);
1511 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1512 DAG.getBasicBlock(MBB)));
1515 /// visitBitTestCase - this function produces one "bit test"
1516 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1519 // Make desired shift
1520 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1521 TLI.getPointerTy());
1522 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1524 DAG.getConstant(1, TLI.getPointerTy()),
1527 // Emit bit tests and jumps
1528 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1529 TLI.getPointerTy(), SwitchVal,
1530 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1531 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1532 TLI.getSetCCResultType(AndOp.getValueType()),
1533 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1536 CurMBB->addSuccessor(B.TargetBB);
1537 CurMBB->addSuccessor(NextMBB);
1539 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1540 MVT::Other, getControlRoot(),
1541 AndCmp, DAG.getBasicBlock(B.TargetBB));
1543 // Set NextBlock to be the MBB immediately after the current one, if any.
1544 // This is used to avoid emitting unnecessary branches to the next block.
1545 MachineBasicBlock *NextBlock = 0;
1546 MachineFunction::iterator BBI = CurMBB;
1547 if (++BBI != CurMBB->getParent()->end())
1550 if (NextMBB == NextBlock)
1553 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1554 DAG.getBasicBlock(NextMBB)));
1557 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1558 // Retrieve successors.
1559 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1560 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1562 const Value *Callee(I.getCalledValue());
1563 if (isa<InlineAsm>(Callee))
1566 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1568 // If the value of the invoke is used outside of its defining block, make it
1569 // available as a virtual register.
1570 if (!I.use_empty()) {
1571 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1572 if (VMI != FuncInfo.ValueMap.end())
1573 CopyValueToVirtualRegister(&I, VMI->second);
1576 // Update successor info
1577 CurMBB->addSuccessor(Return);
1578 CurMBB->addSuccessor(LandingPad);
1580 // Drop into normal successor.
1581 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1582 MVT::Other, getControlRoot(),
1583 DAG.getBasicBlock(Return)));
1586 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1589 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1590 /// small case ranges).
1591 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1592 CaseRecVector& WorkList,
1594 MachineBasicBlock* Default) {
1595 Case& BackCase = *(CR.Range.second-1);
1597 // Size is the number of Cases represented by this range.
1598 size_t Size = CR.Range.second - CR.Range.first;
1602 // Get the MachineFunction which holds the current MBB. This is used when
1603 // inserting any additional MBBs necessary to represent the switch.
1604 MachineFunction *CurMF = CurMBB->getParent();
1606 // Figure out which block is immediately after the current one.
1607 MachineBasicBlock *NextBlock = 0;
1608 MachineFunction::iterator BBI = CR.CaseBB;
1610 if (++BBI != CurMBB->getParent()->end())
1613 // TODO: If any two of the cases has the same destination, and if one value
1614 // is the same as the other, but has one bit unset that the other has set,
1615 // use bit manipulation to do two compares at once. For example:
1616 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1618 // Rearrange the case blocks so that the last one falls through if possible.
1619 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1620 // The last case block won't fall through into 'NextBlock' if we emit the
1621 // branches in this order. See if rearranging a case value would help.
1622 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1623 if (I->BB == NextBlock) {
1624 std::swap(*I, BackCase);
1630 // Create a CaseBlock record representing a conditional branch to
1631 // the Case's target mbb if the value being switched on SV is equal
1633 MachineBasicBlock *CurBlock = CR.CaseBB;
1634 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1635 MachineBasicBlock *FallThrough;
1637 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1638 CurMF->insert(BBI, FallThrough);
1640 // If the last case doesn't match, go to the default block.
1641 FallThrough = Default;
1644 Value *RHS, *LHS, *MHS;
1646 if (I->High == I->Low) {
1647 // This is just small small case range :) containing exactly 1 case
1649 LHS = SV; RHS = I->High; MHS = NULL;
1652 LHS = I->Low; MHS = SV; RHS = I->High;
1654 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1656 // If emitting the first comparison, just call visitSwitchCase to emit the
1657 // code into the current block. Otherwise, push the CaseBlock onto the
1658 // vector to be later processed by SDISel, and insert the node's MBB
1659 // before the next MBB.
1660 if (CurBlock == CurMBB)
1661 visitSwitchCase(CB);
1663 SwitchCases.push_back(CB);
1665 CurBlock = FallThrough;
1671 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1672 return !DisableJumpTables &&
1673 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1674 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1677 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1678 APInt LastExt(Last), FirstExt(First);
1679 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1680 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1681 return (LastExt - FirstExt + 1ULL);
1684 /// handleJTSwitchCase - Emit jumptable for current switch case range
1685 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1686 CaseRecVector& WorkList,
1688 MachineBasicBlock* Default) {
1689 Case& FrontCase = *CR.Range.first;
1690 Case& BackCase = *(CR.Range.second-1);
1692 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1693 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1696 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1700 if (!areJTsAllowed(TLI) || TSize <= 3)
1703 APInt Range = ComputeRange(First, Last);
1704 double Density = (double)TSize / Range.roundToDouble();
1708 DEBUG(errs() << "Lowering jump table\n"
1709 << "First entry: " << First << ". Last entry: " << Last << '\n'
1710 << "Range: " << Range
1711 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1713 // Get the MachineFunction which holds the current MBB. This is used when
1714 // inserting any additional MBBs necessary to represent the switch.
1715 MachineFunction *CurMF = CurMBB->getParent();
1717 // Figure out which block is immediately after the current one.
1718 MachineBasicBlock *NextBlock = 0;
1719 MachineFunction::iterator BBI = CR.CaseBB;
1721 if (++BBI != CurMBB->getParent()->end())
1724 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1726 // Create a new basic block to hold the code for loading the address
1727 // of the jump table, and jumping to it. Update successor information;
1728 // we will either branch to the default case for the switch, or the jump
1730 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1731 CurMF->insert(BBI, JumpTableBB);
1732 CR.CaseBB->addSuccessor(Default);
1733 CR.CaseBB->addSuccessor(JumpTableBB);
1735 // Build a vector of destination BBs, corresponding to each target
1736 // of the jump table. If the value of the jump table slot corresponds to
1737 // a case statement, push the case's BB onto the vector, otherwise, push
1739 std::vector<MachineBasicBlock*> DestBBs;
1741 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1742 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1743 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1745 if (Low.sle(TEI) && TEI.sle(High)) {
1746 DestBBs.push_back(I->BB);
1750 DestBBs.push_back(Default);
1754 // Update successor info. Add one edge to each unique successor.
1755 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1756 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1757 E = DestBBs.end(); I != E; ++I) {
1758 if (!SuccsHandled[(*I)->getNumber()]) {
1759 SuccsHandled[(*I)->getNumber()] = true;
1760 JumpTableBB->addSuccessor(*I);
1764 // Create a jump table index for this jump table, or return an existing
1766 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1768 // Set the jump table information so that we can codegen it as a second
1769 // MachineBasicBlock
1770 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1771 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1772 if (CR.CaseBB == CurMBB)
1773 visitJumpTableHeader(JT, JTH);
1775 JTCases.push_back(JumpTableBlock(JTH, JT));
1780 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1782 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1783 CaseRecVector& WorkList,
1785 MachineBasicBlock* Default) {
1786 // Get the MachineFunction which holds the current MBB. This is used when
1787 // inserting any additional MBBs necessary to represent the switch.
1788 MachineFunction *CurMF = CurMBB->getParent();
1790 // Figure out which block is immediately after the current one.
1791 MachineBasicBlock *NextBlock = 0;
1792 MachineFunction::iterator BBI = CR.CaseBB;
1794 if (++BBI != CurMBB->getParent()->end())
1797 Case& FrontCase = *CR.Range.first;
1798 Case& BackCase = *(CR.Range.second-1);
1799 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1801 // Size is the number of Cases represented by this range.
1802 unsigned Size = CR.Range.second - CR.Range.first;
1804 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1805 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1807 CaseItr Pivot = CR.Range.first + Size/2;
1809 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1810 // (heuristically) allow us to emit JumpTable's later.
1812 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1816 size_t LSize = FrontCase.size();
1817 size_t RSize = TSize-LSize;
1818 DEBUG(errs() << "Selecting best pivot: \n"
1819 << "First: " << First << ", Last: " << Last <<'\n'
1820 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1821 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1823 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1824 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1825 APInt Range = ComputeRange(LEnd, RBegin);
1826 assert((Range - 2ULL).isNonNegative() &&
1827 "Invalid case distance");
1828 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1829 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1830 double Metric = Range.logBase2()*(LDensity+RDensity);
1831 // Should always split in some non-trivial place
1832 DEBUG(errs() <<"=>Step\n"
1833 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1834 << "LDensity: " << LDensity
1835 << ", RDensity: " << RDensity << '\n'
1836 << "Metric: " << Metric << '\n');
1837 if (FMetric < Metric) {
1840 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1846 if (areJTsAllowed(TLI)) {
1847 // If our case is dense we *really* should handle it earlier!
1848 assert((FMetric > 0) && "Should handle dense range earlier!");
1850 Pivot = CR.Range.first + Size/2;
1853 CaseRange LHSR(CR.Range.first, Pivot);
1854 CaseRange RHSR(Pivot, CR.Range.second);
1855 Constant *C = Pivot->Low;
1856 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1858 // We know that we branch to the LHS if the Value being switched on is
1859 // less than the Pivot value, C. We use this to optimize our binary
1860 // tree a bit, by recognizing that if SV is greater than or equal to the
1861 // LHS's Case Value, and that Case Value is exactly one less than the
1862 // Pivot's Value, then we can branch directly to the LHS's Target,
1863 // rather than creating a leaf node for it.
1864 if ((LHSR.second - LHSR.first) == 1 &&
1865 LHSR.first->High == CR.GE &&
1866 cast<ConstantInt>(C)->getValue() ==
1867 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1868 TrueBB = LHSR.first->BB;
1870 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1871 CurMF->insert(BBI, TrueBB);
1872 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1875 // Similar to the optimization above, if the Value being switched on is
1876 // known to be less than the Constant CR.LT, and the current Case Value
1877 // is CR.LT - 1, then we can branch directly to the target block for
1878 // the current Case Value, rather than emitting a RHS leaf node for it.
1879 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1880 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1881 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1882 FalseBB = RHSR.first->BB;
1884 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1885 CurMF->insert(BBI, FalseBB);
1886 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1889 // Create a CaseBlock record representing a conditional branch to
1890 // the LHS node if the value being switched on SV is less than C.
1891 // Otherwise, branch to LHS.
1892 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1894 if (CR.CaseBB == CurMBB)
1895 visitSwitchCase(CB);
1897 SwitchCases.push_back(CB);
1902 /// handleBitTestsSwitchCase - if current case range has few destination and
1903 /// range span less, than machine word bitwidth, encode case range into series
1904 /// of masks and emit bit tests with these masks.
1905 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1906 CaseRecVector& WorkList,
1908 MachineBasicBlock* Default){
1909 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1911 Case& FrontCase = *CR.Range.first;
1912 Case& BackCase = *(CR.Range.second-1);
1914 // Get the MachineFunction which holds the current MBB. This is used when
1915 // inserting any additional MBBs necessary to represent the switch.
1916 MachineFunction *CurMF = CurMBB->getParent();
1919 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1921 // Single case counts one, case range - two.
1922 numCmps += (I->Low == I->High ? 1 : 2);
1925 // Count unique destinations
1926 SmallSet<MachineBasicBlock*, 4> Dests;
1927 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1928 Dests.insert(I->BB);
1929 if (Dests.size() > 3)
1930 // Don't bother the code below, if there are too much unique destinations
1933 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1934 << "Total number of comparisons: " << numCmps << '\n');
1936 // Compute span of values.
1937 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1938 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1939 APInt cmpRange = maxValue - minValue;
1941 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1942 << "Low bound: " << minValue << '\n'
1943 << "High bound: " << maxValue << '\n');
1945 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1946 (!(Dests.size() == 1 && numCmps >= 3) &&
1947 !(Dests.size() == 2 && numCmps >= 5) &&
1948 !(Dests.size() >= 3 && numCmps >= 6)))
1951 DEBUG(errs() << "Emitting bit tests\n");
1952 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1954 // Optimize the case where all the case values fit in a
1955 // word without having to subtract minValue. In this case,
1956 // we can optimize away the subtraction.
1957 if (minValue.isNonNegative() &&
1958 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1959 cmpRange = maxValue;
1961 lowBound = minValue;
1964 CaseBitsVector CasesBits;
1965 unsigned i, count = 0;
1967 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1968 MachineBasicBlock* Dest = I->BB;
1969 for (i = 0; i < count; ++i)
1970 if (Dest == CasesBits[i].BB)
1974 assert((count < 3) && "Too much destinations to test!");
1975 CasesBits.push_back(CaseBits(0, Dest, 0));
1979 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1980 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1982 uint64_t lo = (lowValue - lowBound).getZExtValue();
1983 uint64_t hi = (highValue - lowBound).getZExtValue();
1985 for (uint64_t j = lo; j <= hi; j++) {
1986 CasesBits[i].Mask |= 1ULL << j;
1987 CasesBits[i].Bits++;
1991 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1995 // Figure out which block is immediately after the current one.
1996 MachineFunction::iterator BBI = CR.CaseBB;
1999 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2001 DEBUG(errs() << "Cases:\n");
2002 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2003 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2004 << ", Bits: " << CasesBits[i].Bits
2005 << ", BB: " << CasesBits[i].BB << '\n');
2007 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2008 CurMF->insert(BBI, CaseBB);
2009 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2014 BitTestBlock BTB(lowBound, cmpRange, SV,
2015 -1U, (CR.CaseBB == CurMBB),
2016 CR.CaseBB, Default, BTC);
2018 if (CR.CaseBB == CurMBB)
2019 visitBitTestHeader(BTB);
2021 BitTestCases.push_back(BTB);
2027 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2028 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2029 const SwitchInst& SI) {
2032 // Start with "simple" cases
2033 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2034 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2035 Cases.push_back(Case(SI.getSuccessorValue(i),
2036 SI.getSuccessorValue(i),
2039 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2041 // Merge case into clusters
2042 if (Cases.size() >= 2)
2043 // Must recompute end() each iteration because it may be
2044 // invalidated by erase if we hold on to it
2045 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2046 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2047 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2048 MachineBasicBlock* nextBB = J->BB;
2049 MachineBasicBlock* currentBB = I->BB;
2051 // If the two neighboring cases go to the same destination, merge them
2052 // into a single case.
2053 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2061 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2062 if (I->Low != I->High)
2063 // A range counts double, since it requires two compares.
2070 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2071 // Figure out which block is immediately after the current one.
2072 MachineBasicBlock *NextBlock = 0;
2073 MachineFunction::iterator BBI = CurMBB;
2075 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2077 // If there is only the default destination, branch to it if it is not the
2078 // next basic block. Otherwise, just fall through.
2079 if (SI.getNumOperands() == 2) {
2080 // Update machine-CFG edges.
2082 // If this is not a fall-through branch, emit the branch.
2083 CurMBB->addSuccessor(Default);
2084 if (Default != NextBlock)
2085 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2086 MVT::Other, getControlRoot(),
2087 DAG.getBasicBlock(Default)));
2091 // If there are any non-default case statements, create a vector of Cases
2092 // representing each one, and sort the vector so that we can efficiently
2093 // create a binary search tree from them.
2095 size_t numCmps = Clusterify(Cases, SI);
2096 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2097 << ". Total compares: " << numCmps << '\n');
2100 // Get the Value to be switched on and default basic blocks, which will be
2101 // inserted into CaseBlock records, representing basic blocks in the binary
2103 Value *SV = SI.getOperand(0);
2105 // Push the initial CaseRec onto the worklist
2106 CaseRecVector WorkList;
2107 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2109 while (!WorkList.empty()) {
2110 // Grab a record representing a case range to process off the worklist
2111 CaseRec CR = WorkList.back();
2112 WorkList.pop_back();
2114 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2117 // If the range has few cases (two or less) emit a series of specific
2119 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2122 // If the switch has more than 5 blocks, and at least 40% dense, and the
2123 // target supports indirect branches, then emit a jump table rather than
2124 // lowering the switch to a binary tree of conditional branches.
2125 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2128 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2129 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2130 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2135 void SelectionDAGLowering::visitSub(User &I) {
2136 // -0.0 - X --> fneg
2137 const Type *Ty = I.getType();
2138 if (isa<VectorType>(Ty)) {
2139 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2140 const VectorType *DestTy = cast<VectorType>(I.getType());
2141 const Type *ElTy = DestTy->getElementType();
2142 if (ElTy->isFloatingPoint()) {
2143 unsigned VL = DestTy->getNumElements();
2144 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2145 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2147 SDValue Op2 = getValue(I.getOperand(1));
2148 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2149 Op2.getValueType(), Op2));
2155 if (Ty->isFloatingPoint()) {
2156 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2157 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2158 SDValue Op2 = getValue(I.getOperand(1));
2159 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2160 Op2.getValueType(), Op2));
2165 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2168 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2169 SDValue Op1 = getValue(I.getOperand(0));
2170 SDValue Op2 = getValue(I.getOperand(1));
2172 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2173 Op1.getValueType(), Op1, Op2));
2176 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2177 SDValue Op1 = getValue(I.getOperand(0));
2178 SDValue Op2 = getValue(I.getOperand(1));
2179 if (!isa<VectorType>(I.getType())) {
2180 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2181 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2182 TLI.getPointerTy(), Op2);
2183 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2184 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2185 TLI.getPointerTy(), Op2);
2188 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2189 Op1.getValueType(), Op1, Op2));
2192 void SelectionDAGLowering::visitICmp(User &I) {
2193 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2194 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2195 predicate = IC->getPredicate();
2196 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2197 predicate = ICmpInst::Predicate(IC->getPredicate());
2198 SDValue Op1 = getValue(I.getOperand(0));
2199 SDValue Op2 = getValue(I.getOperand(1));
2200 ISD::CondCode Opcode = getICmpCondCode(predicate);
2201 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2204 void SelectionDAGLowering::visitFCmp(User &I) {
2205 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2206 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2207 predicate = FC->getPredicate();
2208 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2209 predicate = FCmpInst::Predicate(FC->getPredicate());
2210 SDValue Op1 = getValue(I.getOperand(0));
2211 SDValue Op2 = getValue(I.getOperand(1));
2212 ISD::CondCode Condition = getFCmpCondCode(predicate);
2213 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2216 void SelectionDAGLowering::visitVICmp(User &I) {
2217 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2218 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2219 predicate = IC->getPredicate();
2220 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2221 predicate = ICmpInst::Predicate(IC->getPredicate());
2222 SDValue Op1 = getValue(I.getOperand(0));
2223 SDValue Op2 = getValue(I.getOperand(1));
2224 ISD::CondCode Opcode = getICmpCondCode(predicate);
2225 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2229 void SelectionDAGLowering::visitVFCmp(User &I) {
2230 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2231 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2232 predicate = FC->getPredicate();
2233 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2234 predicate = FCmpInst::Predicate(FC->getPredicate());
2235 SDValue Op1 = getValue(I.getOperand(0));
2236 SDValue Op2 = getValue(I.getOperand(1));
2237 ISD::CondCode Condition = getFCmpCondCode(predicate);
2238 MVT DestVT = TLI.getValueType(I.getType());
2240 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2243 void SelectionDAGLowering::visitSelect(User &I) {
2244 SmallVector<MVT, 4> ValueVTs;
2245 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2246 unsigned NumValues = ValueVTs.size();
2247 if (NumValues != 0) {
2248 SmallVector<SDValue, 4> Values(NumValues);
2249 SDValue Cond = getValue(I.getOperand(0));
2250 SDValue TrueVal = getValue(I.getOperand(1));
2251 SDValue FalseVal = getValue(I.getOperand(2));
2253 for (unsigned i = 0; i != NumValues; ++i)
2254 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2255 TrueVal.getValueType(), Cond,
2256 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2257 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2259 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2260 DAG.getVTList(&ValueVTs[0], NumValues),
2261 &Values[0], NumValues));
2266 void SelectionDAGLowering::visitTrunc(User &I) {
2267 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2268 SDValue N = getValue(I.getOperand(0));
2269 MVT DestVT = TLI.getValueType(I.getType());
2270 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2273 void SelectionDAGLowering::visitZExt(User &I) {
2274 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2275 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2276 SDValue N = getValue(I.getOperand(0));
2277 MVT DestVT = TLI.getValueType(I.getType());
2278 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2281 void SelectionDAGLowering::visitSExt(User &I) {
2282 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2283 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2284 SDValue N = getValue(I.getOperand(0));
2285 MVT DestVT = TLI.getValueType(I.getType());
2286 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2289 void SelectionDAGLowering::visitFPTrunc(User &I) {
2290 // FPTrunc is never a no-op cast, no need to check
2291 SDValue N = getValue(I.getOperand(0));
2292 MVT DestVT = TLI.getValueType(I.getType());
2293 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2294 DestVT, N, DAG.getIntPtrConstant(0)));
2297 void SelectionDAGLowering::visitFPExt(User &I){
2298 // FPTrunc is never a no-op cast, no need to check
2299 SDValue N = getValue(I.getOperand(0));
2300 MVT DestVT = TLI.getValueType(I.getType());
2301 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2304 void SelectionDAGLowering::visitFPToUI(User &I) {
2305 // FPToUI is never a no-op cast, no need to check
2306 SDValue N = getValue(I.getOperand(0));
2307 MVT DestVT = TLI.getValueType(I.getType());
2308 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2311 void SelectionDAGLowering::visitFPToSI(User &I) {
2312 // FPToSI is never a no-op cast, no need to check
2313 SDValue N = getValue(I.getOperand(0));
2314 MVT DestVT = TLI.getValueType(I.getType());
2315 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2318 void SelectionDAGLowering::visitUIToFP(User &I) {
2319 // UIToFP is never a no-op cast, no need to check
2320 SDValue N = getValue(I.getOperand(0));
2321 MVT DestVT = TLI.getValueType(I.getType());
2322 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2325 void SelectionDAGLowering::visitSIToFP(User &I){
2326 // SIToFP is never a no-op cast, no need to check
2327 SDValue N = getValue(I.getOperand(0));
2328 MVT DestVT = TLI.getValueType(I.getType());
2329 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2332 void SelectionDAGLowering::visitPtrToInt(User &I) {
2333 // What to do depends on the size of the integer and the size of the pointer.
2334 // We can either truncate, zero extend, or no-op, accordingly.
2335 SDValue N = getValue(I.getOperand(0));
2336 MVT SrcVT = N.getValueType();
2337 MVT DestVT = TLI.getValueType(I.getType());
2339 if (DestVT.bitsLT(SrcVT))
2340 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2342 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2343 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2344 setValue(&I, Result);
2347 void SelectionDAGLowering::visitIntToPtr(User &I) {
2348 // What to do depends on the size of the integer and the size of the pointer.
2349 // We can either truncate, zero extend, or no-op, accordingly.
2350 SDValue N = getValue(I.getOperand(0));
2351 MVT SrcVT = N.getValueType();
2352 MVT DestVT = TLI.getValueType(I.getType());
2353 if (DestVT.bitsLT(SrcVT))
2354 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2356 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2357 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2361 void SelectionDAGLowering::visitBitCast(User &I) {
2362 SDValue N = getValue(I.getOperand(0));
2363 MVT DestVT = TLI.getValueType(I.getType());
2365 // BitCast assures us that source and destination are the same size so this
2366 // is either a BIT_CONVERT or a no-op.
2367 if (DestVT != N.getValueType())
2368 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2369 DestVT, N)); // convert types
2371 setValue(&I, N); // noop cast.
2374 void SelectionDAGLowering::visitInsertElement(User &I) {
2375 SDValue InVec = getValue(I.getOperand(0));
2376 SDValue InVal = getValue(I.getOperand(1));
2377 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2379 getValue(I.getOperand(2)));
2381 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2382 TLI.getValueType(I.getType()),
2383 InVec, InVal, InIdx));
2386 void SelectionDAGLowering::visitExtractElement(User &I) {
2387 SDValue InVec = getValue(I.getOperand(0));
2388 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2390 getValue(I.getOperand(1)));
2391 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2392 TLI.getValueType(I.getType()), InVec, InIdx));
2396 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2397 // from SIndx and increasing to the element length (undefs are allowed).
2398 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2399 unsigned MaskNumElts = Mask.getNumOperands();
2400 for (unsigned i = 0; i != MaskNumElts; ++i) {
2401 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2402 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2403 if (Idx != i + SIndx)
2410 void SelectionDAGLowering::visitShuffleVector(User &I) {
2411 SDValue Src1 = getValue(I.getOperand(0));
2412 SDValue Src2 = getValue(I.getOperand(1));
2413 SDValue Mask = getValue(I.getOperand(2));
2415 MVT VT = TLI.getValueType(I.getType());
2416 MVT SrcVT = Src1.getValueType();
2417 int MaskNumElts = Mask.getNumOperands();
2418 int SrcNumElts = SrcVT.getVectorNumElements();
2420 if (SrcNumElts == MaskNumElts) {
2421 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2422 VT, Src1, Src2, Mask));
2426 // Normalize the shuffle vector since mask and vector length don't match.
2427 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2429 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2430 // Mask is longer than the source vectors and is a multiple of the source
2431 // vectors. We can use concatenate vector to make the mask and vectors
2433 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2434 // The shuffle is concatenating two vectors together.
2435 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2440 // Pad both vectors with undefs to make them the same length as the mask.
2441 unsigned NumConcat = MaskNumElts / SrcNumElts;
2442 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2444 SDValue* MOps1 = new SDValue[NumConcat];
2445 SDValue* MOps2 = new SDValue[NumConcat];
2448 for (unsigned i = 1; i != NumConcat; ++i) {
2449 MOps1[i] = UndefVal;
2450 MOps2[i] = UndefVal;
2452 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2453 VT, MOps1, NumConcat);
2454 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2455 VT, MOps2, NumConcat);
2460 // Readjust mask for new input vector length.
2461 SmallVector<SDValue, 8> MappedOps;
2462 for (int i = 0; i != MaskNumElts; ++i) {
2463 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2464 MappedOps.push_back(Mask.getOperand(i));
2466 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2467 if (Idx < SrcNumElts)
2468 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2470 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2474 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2475 Mask.getValueType(),
2476 &MappedOps[0], MappedOps.size());
2478 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2479 VT, Src1, Src2, Mask));
2483 if (SrcNumElts > MaskNumElts) {
2484 // Resulting vector is shorter than the incoming vector.
2485 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2486 // Shuffle extracts 1st vector.
2491 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2492 // Shuffle extracts 2nd vector.
2497 // Analyze the access pattern of the vector to see if we can extract
2498 // two subvectors and do the shuffle. The analysis is done by calculating
2499 // the range of elements the mask access on both vectors.
2500 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2501 int MaxRange[2] = {-1, -1};
2503 for (int i = 0; i != MaskNumElts; ++i) {
2504 SDValue Arg = Mask.getOperand(i);
2505 if (Arg.getOpcode() != ISD::UNDEF) {
2506 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2507 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2509 if (Idx >= SrcNumElts) {
2513 if (Idx > MaxRange[Input])
2514 MaxRange[Input] = Idx;
2515 if (Idx < MinRange[Input])
2516 MinRange[Input] = Idx;
2520 // Check if the access is smaller than the vector size and can we find
2521 // a reasonable extract index.
2522 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2523 int StartIdx[2]; // StartIdx to extract from
2524 for (int Input=0; Input < 2; ++Input) {
2525 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2526 RangeUse[Input] = 0; // Unused
2527 StartIdx[Input] = 0;
2528 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2529 // Fits within range but we should see if we can find a good
2530 // start index that is a multiple of the mask length.
2531 if (MaxRange[Input] < MaskNumElts) {
2532 RangeUse[Input] = 1; // Extract from beginning of the vector
2533 StartIdx[Input] = 0;
2535 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2536 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2537 StartIdx[Input] + MaskNumElts < SrcNumElts)
2538 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2543 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2544 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2547 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2548 // Extract appropriate subvector and generate a vector shuffle
2549 for (int Input=0; Input < 2; ++Input) {
2550 SDValue& Src = Input == 0 ? Src1 : Src2;
2551 if (RangeUse[Input] == 0) {
2552 Src = DAG.getUNDEF(VT);
2554 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2555 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2558 // Calculate new mask.
2559 SmallVector<SDValue, 8> MappedOps;
2560 for (int i = 0; i != MaskNumElts; ++i) {
2561 SDValue Arg = Mask.getOperand(i);
2562 if (Arg.getOpcode() == ISD::UNDEF) {
2563 MappedOps.push_back(Arg);
2565 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2566 if (Idx < SrcNumElts)
2567 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2569 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2570 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2574 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2575 Mask.getValueType(),
2576 &MappedOps[0], MappedOps.size());
2577 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2578 VT, Src1, Src2, Mask));
2583 // We can't use either concat vectors or extract subvectors so fall back to
2584 // replacing the shuffle with extract and build vector.
2585 // to insert and build vector.
2586 MVT EltVT = VT.getVectorElementType();
2587 MVT PtrVT = TLI.getPointerTy();
2588 SmallVector<SDValue,8> Ops;
2589 for (int i = 0; i != MaskNumElts; ++i) {
2590 SDValue Arg = Mask.getOperand(i);
2591 if (Arg.getOpcode() == ISD::UNDEF) {
2592 Ops.push_back(DAG.getUNDEF(EltVT));
2594 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2595 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2596 if (Idx < SrcNumElts)
2597 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2598 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2600 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2602 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2605 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2606 VT, &Ops[0], Ops.size()));
2609 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2610 const Value *Op0 = I.getOperand(0);
2611 const Value *Op1 = I.getOperand(1);
2612 const Type *AggTy = I.getType();
2613 const Type *ValTy = Op1->getType();
2614 bool IntoUndef = isa<UndefValue>(Op0);
2615 bool FromUndef = isa<UndefValue>(Op1);
2617 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2618 I.idx_begin(), I.idx_end());
2620 SmallVector<MVT, 4> AggValueVTs;
2621 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2622 SmallVector<MVT, 4> ValValueVTs;
2623 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2625 unsigned NumAggValues = AggValueVTs.size();
2626 unsigned NumValValues = ValValueVTs.size();
2627 SmallVector<SDValue, 4> Values(NumAggValues);
2629 SDValue Agg = getValue(Op0);
2630 SDValue Val = getValue(Op1);
2632 // Copy the beginning value(s) from the original aggregate.
2633 for (; i != LinearIndex; ++i)
2634 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2635 SDValue(Agg.getNode(), Agg.getResNo() + i);
2636 // Copy values from the inserted value(s).
2637 for (; i != LinearIndex + NumValValues; ++i)
2638 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2639 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2640 // Copy remaining value(s) from the original aggregate.
2641 for (; i != NumAggValues; ++i)
2642 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2643 SDValue(Agg.getNode(), Agg.getResNo() + i);
2645 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2646 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2647 &Values[0], NumAggValues));
2650 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2651 const Value *Op0 = I.getOperand(0);
2652 const Type *AggTy = Op0->getType();
2653 const Type *ValTy = I.getType();
2654 bool OutOfUndef = isa<UndefValue>(Op0);
2656 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2657 I.idx_begin(), I.idx_end());
2659 SmallVector<MVT, 4> ValValueVTs;
2660 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2662 unsigned NumValValues = ValValueVTs.size();
2663 SmallVector<SDValue, 4> Values(NumValValues);
2665 SDValue Agg = getValue(Op0);
2666 // Copy out the selected value(s).
2667 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2668 Values[i - LinearIndex] =
2670 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2671 SDValue(Agg.getNode(), Agg.getResNo() + i);
2673 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2674 DAG.getVTList(&ValValueVTs[0], NumValValues),
2675 &Values[0], NumValValues));
2679 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2680 SDValue N = getValue(I.getOperand(0));
2681 const Type *Ty = I.getOperand(0)->getType();
2683 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2686 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2687 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2690 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2691 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2692 DAG.getIntPtrConstant(Offset));
2694 Ty = StTy->getElementType(Field);
2696 Ty = cast<SequentialType>(Ty)->getElementType();
2698 // If this is a constant subscript, handle it quickly.
2699 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2700 if (CI->getZExtValue() == 0) continue;
2702 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2704 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2706 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2708 DAG.getConstant(Offs, MVT::i64));
2710 OffsVal = DAG.getIntPtrConstant(Offs);
2711 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2716 // N = N + Idx * ElementSize;
2717 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2718 SDValue IdxN = getValue(Idx);
2720 // If the index is smaller or larger than intptr_t, truncate or extend
2722 if (IdxN.getValueType().bitsLT(N.getValueType()))
2723 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2724 N.getValueType(), IdxN);
2725 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2726 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2727 N.getValueType(), IdxN);
2729 // If this is a multiply by a power of two, turn it into a shl
2730 // immediately. This is a very common case.
2731 if (ElementSize != 1) {
2732 if (isPowerOf2_64(ElementSize)) {
2733 unsigned Amt = Log2_64(ElementSize);
2734 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2735 N.getValueType(), IdxN,
2736 DAG.getConstant(Amt, TLI.getPointerTy()));
2738 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2739 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2740 N.getValueType(), IdxN, Scale);
2744 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2745 N.getValueType(), N, IdxN);
2751 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2752 // If this is a fixed sized alloca in the entry block of the function,
2753 // allocate it statically on the stack.
2754 if (FuncInfo.StaticAllocaMap.count(&I))
2755 return; // getValue will auto-populate this.
2757 const Type *Ty = I.getAllocatedType();
2758 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2760 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2763 SDValue AllocSize = getValue(I.getArraySize());
2764 MVT IntPtr = TLI.getPointerTy();
2765 if (IntPtr.bitsLT(AllocSize.getValueType()))
2766 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2768 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2769 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2772 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
2773 DAG.getIntPtrConstant(TySize));
2775 // Handle alignment. If the requested alignment is less than or equal to
2776 // the stack alignment, ignore it. If the size is greater than or equal to
2777 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2778 unsigned StackAlign =
2779 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2780 if (Align <= StackAlign)
2783 // Round the size of the allocation up to the stack alignment size
2784 // by add SA-1 to the size.
2785 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2786 AllocSize.getValueType(), AllocSize,
2787 DAG.getIntPtrConstant(StackAlign-1));
2788 // Mask out the low bits for alignment purposes.
2789 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2790 AllocSize.getValueType(), AllocSize,
2791 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2793 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2794 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2796 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2799 DAG.setRoot(DSA.getValue(1));
2801 // Inform the Frame Information that we have just allocated a variable-sized
2803 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2806 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2807 const Value *SV = I.getOperand(0);
2808 SDValue Ptr = getValue(SV);
2810 const Type *Ty = I.getType();
2811 bool isVolatile = I.isVolatile();
2812 unsigned Alignment = I.getAlignment();
2814 SmallVector<MVT, 4> ValueVTs;
2815 SmallVector<uint64_t, 4> Offsets;
2816 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2817 unsigned NumValues = ValueVTs.size();
2822 bool ConstantMemory = false;
2824 // Serialize volatile loads with other side effects.
2826 else if (AA->pointsToConstantMemory(SV)) {
2827 // Do not serialize (non-volatile) loads of constant memory with anything.
2828 Root = DAG.getEntryNode();
2829 ConstantMemory = true;
2831 // Do not serialize non-volatile loads against each other.
2832 Root = DAG.getRoot();
2835 SmallVector<SDValue, 4> Values(NumValues);
2836 SmallVector<SDValue, 4> Chains(NumValues);
2837 MVT PtrVT = Ptr.getValueType();
2838 for (unsigned i = 0; i != NumValues; ++i) {
2839 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2840 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2842 DAG.getConstant(Offsets[i], PtrVT)),
2844 isVolatile, Alignment);
2846 Chains[i] = L.getValue(1);
2849 if (!ConstantMemory) {
2850 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2852 &Chains[0], NumValues);
2856 PendingLoads.push_back(Chain);
2859 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2860 DAG.getVTList(&ValueVTs[0], NumValues),
2861 &Values[0], NumValues));
2865 void SelectionDAGLowering::visitStore(StoreInst &I) {
2866 Value *SrcV = I.getOperand(0);
2867 Value *PtrV = I.getOperand(1);
2869 SmallVector<MVT, 4> ValueVTs;
2870 SmallVector<uint64_t, 4> Offsets;
2871 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2872 unsigned NumValues = ValueVTs.size();
2876 // Get the lowered operands. Note that we do this after
2877 // checking if NumResults is zero, because with zero results
2878 // the operands won't have values in the map.
2879 SDValue Src = getValue(SrcV);
2880 SDValue Ptr = getValue(PtrV);
2882 SDValue Root = getRoot();
2883 SmallVector<SDValue, 4> Chains(NumValues);
2884 MVT PtrVT = Ptr.getValueType();
2885 bool isVolatile = I.isVolatile();
2886 unsigned Alignment = I.getAlignment();
2887 for (unsigned i = 0; i != NumValues; ++i)
2888 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2889 SDValue(Src.getNode(), Src.getResNo() + i),
2890 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2892 DAG.getConstant(Offsets[i], PtrVT)),
2894 isVolatile, Alignment);
2896 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2897 MVT::Other, &Chains[0], NumValues));
2900 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2902 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2903 unsigned Intrinsic) {
2904 bool HasChain = !I.doesNotAccessMemory();
2905 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2907 // Build the operand list.
2908 SmallVector<SDValue, 8> Ops;
2909 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2911 // We don't need to serialize loads against other loads.
2912 Ops.push_back(DAG.getRoot());
2914 Ops.push_back(getRoot());
2918 // Info is set by getTgtMemInstrinsic
2919 TargetLowering::IntrinsicInfo Info;
2920 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2922 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2923 if (!IsTgtIntrinsic)
2924 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2926 // Add all operands of the call to the operand list.
2927 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2928 SDValue Op = getValue(I.getOperand(i));
2929 assert(TLI.isTypeLegal(Op.getValueType()) &&
2930 "Intrinsic uses a non-legal type?");
2934 std::vector<MVT> VTs;
2935 if (I.getType() != Type::VoidTy) {
2936 MVT VT = TLI.getValueType(I.getType());
2937 if (VT.isVector()) {
2938 const VectorType *DestTy = cast<VectorType>(I.getType());
2939 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2941 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2942 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2945 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2949 VTs.push_back(MVT::Other);
2951 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2955 if (IsTgtIntrinsic) {
2956 // This is target intrinsic that touches memory
2957 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2959 &Ops[0], Ops.size(),
2960 Info.memVT, Info.ptrVal, Info.offset,
2961 Info.align, Info.vol,
2962 Info.readMem, Info.writeMem);
2965 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2967 &Ops[0], Ops.size());
2968 else if (I.getType() != Type::VoidTy)
2969 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2971 &Ops[0], Ops.size());
2973 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2975 &Ops[0], Ops.size());
2978 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2980 PendingLoads.push_back(Chain);
2984 if (I.getType() != Type::VoidTy) {
2985 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2986 MVT VT = TLI.getValueType(PTy);
2987 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2989 setValue(&I, Result);
2993 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2994 static GlobalVariable *ExtractTypeInfo(Value *V) {
2995 V = V->stripPointerCasts();
2996 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2997 assert ((GV || isa<ConstantPointerNull>(V)) &&
2998 "TypeInfo must be a global variable or NULL");
3004 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3005 /// call, and add them to the specified machine basic block.
3006 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3007 MachineBasicBlock *MBB) {
3008 // Inform the MachineModuleInfo of the personality for this landing pad.
3009 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3010 assert(CE->getOpcode() == Instruction::BitCast &&
3011 isa<Function>(CE->getOperand(0)) &&
3012 "Personality should be a function");
3013 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3015 // Gather all the type infos for this landing pad and pass them along to
3016 // MachineModuleInfo.
3017 std::vector<GlobalVariable *> TyInfo;
3018 unsigned N = I.getNumOperands();
3020 for (unsigned i = N - 1; i > 2; --i) {
3021 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3022 unsigned FilterLength = CI->getZExtValue();
3023 unsigned FirstCatch = i + FilterLength + !FilterLength;
3024 assert (FirstCatch <= N && "Invalid filter length");
3026 if (FirstCatch < N) {
3027 TyInfo.reserve(N - FirstCatch);
3028 for (unsigned j = FirstCatch; j < N; ++j)
3029 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3030 MMI->addCatchTypeInfo(MBB, TyInfo);
3034 if (!FilterLength) {
3036 MMI->addCleanup(MBB);
3039 TyInfo.reserve(FilterLength - 1);
3040 for (unsigned j = i + 1; j < FirstCatch; ++j)
3041 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3042 MMI->addFilterTypeInfo(MBB, TyInfo);
3051 TyInfo.reserve(N - 3);
3052 for (unsigned j = 3; j < N; ++j)
3053 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3054 MMI->addCatchTypeInfo(MBB, TyInfo);
3060 /// GetSignificand - Get the significand and build it into a floating-point
3061 /// number with exponent of 1:
3063 /// Op = (Op & 0x007fffff) | 0x3f800000;
3065 /// where Op is the hexidecimal representation of floating point value.
3067 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3068 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3069 DAG.getConstant(0x007fffff, MVT::i32));
3070 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3071 DAG.getConstant(0x3f800000, MVT::i32));
3072 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3075 /// GetExponent - Get the exponent:
3077 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3079 /// where Op is the hexidecimal representation of floating point value.
3081 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3083 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3084 DAG.getConstant(0x7f800000, MVT::i32));
3085 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3086 DAG.getConstant(23, TLI.getPointerTy()));
3087 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3088 DAG.getConstant(127, MVT::i32));
3089 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3092 /// getF32Constant - Get 32-bit floating point constant.
3094 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3095 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3098 /// Inlined utility function to implement binary input atomic intrinsics for
3099 /// visitIntrinsicCall: I is a call instruction
3100 /// Op is the associated NodeType for I
3102 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3103 SDValue Root = getRoot();
3105 DAG.getAtomic(Op, getCurDebugLoc(),
3106 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3108 getValue(I.getOperand(1)),
3109 getValue(I.getOperand(2)),
3112 DAG.setRoot(L.getValue(1));
3116 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3118 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3119 SDValue Op1 = getValue(I.getOperand(1));
3120 SDValue Op2 = getValue(I.getOperand(2));
3122 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3123 SDValue Ops[] = { Op1, Op2 };
3125 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
3126 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
3128 setValue(&I, Result);
3132 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3133 /// limited-precision mode.
3135 SelectionDAGLowering::visitExp(CallInst &I) {
3137 DebugLoc dl = getCurDebugLoc();
3139 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3140 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3141 SDValue Op = getValue(I.getOperand(1));
3143 // Put the exponent in the right bit position for later addition to the
3146 // #define LOG2OFe 1.4426950f
3147 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3148 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3149 getF32Constant(DAG, 0x3fb8aa3b));
3150 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3152 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3153 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3154 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3156 // IntegerPartOfX <<= 23;
3157 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3158 DAG.getConstant(23, TLI.getPointerTy()));
3160 if (LimitFloatPrecision <= 6) {
3161 // For floating-point precision of 6:
3163 // TwoToFractionalPartOfX =
3165 // (0.735607626f + 0.252464424f * x) * x;
3167 // error 0.0144103317, which is 6 bits
3168 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3169 getF32Constant(DAG, 0x3e814304));
3170 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3171 getF32Constant(DAG, 0x3f3c50c8));
3172 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3173 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3174 getF32Constant(DAG, 0x3f7f5e7e));
3175 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3177 // Add the exponent into the result in integer domain.
3178 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3179 TwoToFracPartOfX, IntegerPartOfX);
3181 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3182 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3183 // For floating-point precision of 12:
3185 // TwoToFractionalPartOfX =
3188 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3190 // 0.000107046256 error, which is 13 to 14 bits
3191 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3192 getF32Constant(DAG, 0x3da235e3));
3193 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3194 getF32Constant(DAG, 0x3e65b8f3));
3195 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3196 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3197 getF32Constant(DAG, 0x3f324b07));
3198 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3199 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3200 getF32Constant(DAG, 0x3f7ff8fd));
3201 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3203 // Add the exponent into the result in integer domain.
3204 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3205 TwoToFracPartOfX, IntegerPartOfX);
3207 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3208 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3209 // For floating-point precision of 18:
3211 // TwoToFractionalPartOfX =
3215 // (0.554906021e-1f +
3216 // (0.961591928e-2f +
3217 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3219 // error 2.47208000*10^(-7), which is better than 18 bits
3220 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3221 getF32Constant(DAG, 0x3924b03e));
3222 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3223 getF32Constant(DAG, 0x3ab24b87));
3224 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3225 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3226 getF32Constant(DAG, 0x3c1d8c17));
3227 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3228 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3229 getF32Constant(DAG, 0x3d634a1d));
3230 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3231 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3232 getF32Constant(DAG, 0x3e75fe14));
3233 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3234 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3235 getF32Constant(DAG, 0x3f317234));
3236 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3237 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3238 getF32Constant(DAG, 0x3f800000));
3239 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3242 // Add the exponent into the result in integer domain.
3243 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3244 TwoToFracPartOfX, IntegerPartOfX);
3246 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3249 // No special expansion.
3250 result = DAG.getNode(ISD::FEXP, dl,
3251 getValue(I.getOperand(1)).getValueType(),
3252 getValue(I.getOperand(1)));
3255 setValue(&I, result);
3258 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3259 /// limited-precision mode.
3261 SelectionDAGLowering::visitLog(CallInst &I) {
3263 DebugLoc dl = getCurDebugLoc();
3265 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3266 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3267 SDValue Op = getValue(I.getOperand(1));
3268 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3270 // Scale the exponent by log(2) [0.69314718f].
3271 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3272 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3273 getF32Constant(DAG, 0x3f317218));
3275 // Get the significand and build it into a floating-point number with
3277 SDValue X = GetSignificand(DAG, Op1, dl);
3279 if (LimitFloatPrecision <= 6) {
3280 // For floating-point precision of 6:
3284 // (1.4034025f - 0.23903021f * x) * x;
3286 // error 0.0034276066, which is better than 8 bits
3287 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3288 getF32Constant(DAG, 0xbe74c456));
3289 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3290 getF32Constant(DAG, 0x3fb3a2b1));
3291 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3292 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3293 getF32Constant(DAG, 0x3f949a29));
3295 result = DAG.getNode(ISD::FADD, dl,
3296 MVT::f32, LogOfExponent, LogOfMantissa);
3297 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3298 // For floating-point precision of 12:
3304 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3306 // error 0.000061011436, which is 14 bits
3307 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3308 getF32Constant(DAG, 0xbd67b6d6));
3309 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3310 getF32Constant(DAG, 0x3ee4f4b8));
3311 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3312 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3313 getF32Constant(DAG, 0x3fbc278b));
3314 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3315 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3316 getF32Constant(DAG, 0x40348e95));
3317 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3318 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3319 getF32Constant(DAG, 0x3fdef31a));
3321 result = DAG.getNode(ISD::FADD, dl,
3322 MVT::f32, LogOfExponent, LogOfMantissa);
3323 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3324 // For floating-point precision of 18:
3332 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3334 // error 0.0000023660568, which is better than 18 bits
3335 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3336 getF32Constant(DAG, 0xbc91e5ac));
3337 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3338 getF32Constant(DAG, 0x3e4350aa));
3339 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3340 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3341 getF32Constant(DAG, 0x3f60d3e3));
3342 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3343 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3344 getF32Constant(DAG, 0x4011cdf0));
3345 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3346 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3347 getF32Constant(DAG, 0x406cfd1c));
3348 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3349 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3350 getF32Constant(DAG, 0x408797cb));
3351 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3352 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3353 getF32Constant(DAG, 0x4006dcab));
3355 result = DAG.getNode(ISD::FADD, dl,
3356 MVT::f32, LogOfExponent, LogOfMantissa);
3359 // No special expansion.
3360 result = DAG.getNode(ISD::FLOG, dl,
3361 getValue(I.getOperand(1)).getValueType(),
3362 getValue(I.getOperand(1)));
3365 setValue(&I, result);
3368 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3369 /// limited-precision mode.
3371 SelectionDAGLowering::visitLog2(CallInst &I) {
3373 DebugLoc dl = getCurDebugLoc();
3375 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3376 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3377 SDValue Op = getValue(I.getOperand(1));
3378 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3380 // Get the exponent.
3381 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3383 // Get the significand and build it into a floating-point number with
3385 SDValue X = GetSignificand(DAG, Op1, dl);
3387 // Different possible minimax approximations of significand in
3388 // floating-point for various degrees of accuracy over [1,2].
3389 if (LimitFloatPrecision <= 6) {
3390 // For floating-point precision of 6:
3392 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3394 // error 0.0049451742, which is more than 7 bits
3395 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3396 getF32Constant(DAG, 0xbeb08fe0));
3397 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3398 getF32Constant(DAG, 0x40019463));
3399 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3400 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3401 getF32Constant(DAG, 0x3fd6633d));
3403 result = DAG.getNode(ISD::FADD, dl,
3404 MVT::f32, LogOfExponent, Log2ofMantissa);
3405 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3406 // For floating-point precision of 12:
3412 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3414 // error 0.0000876136000, which is better than 13 bits
3415 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3416 getF32Constant(DAG, 0xbda7262e));
3417 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3418 getF32Constant(DAG, 0x3f25280b));
3419 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3420 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3421 getF32Constant(DAG, 0x4007b923));
3422 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3423 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3424 getF32Constant(DAG, 0x40823e2f));
3425 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3426 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3427 getF32Constant(DAG, 0x4020d29c));
3429 result = DAG.getNode(ISD::FADD, dl,
3430 MVT::f32, LogOfExponent, Log2ofMantissa);
3431 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3432 // For floating-point precision of 18:
3441 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3443 // error 0.0000018516, which is better than 18 bits
3444 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3445 getF32Constant(DAG, 0xbcd2769e));
3446 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3447 getF32Constant(DAG, 0x3e8ce0b9));
3448 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3449 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3450 getF32Constant(DAG, 0x3fa22ae7));
3451 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3452 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3453 getF32Constant(DAG, 0x40525723));
3454 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3455 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3456 getF32Constant(DAG, 0x40aaf200));
3457 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3458 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3459 getF32Constant(DAG, 0x40c39dad));
3460 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3461 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3462 getF32Constant(DAG, 0x4042902c));
3464 result = DAG.getNode(ISD::FADD, dl,
3465 MVT::f32, LogOfExponent, Log2ofMantissa);
3468 // No special expansion.
3469 result = DAG.getNode(ISD::FLOG2, dl,
3470 getValue(I.getOperand(1)).getValueType(),
3471 getValue(I.getOperand(1)));
3474 setValue(&I, result);
3477 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3478 /// limited-precision mode.
3480 SelectionDAGLowering::visitLog10(CallInst &I) {
3482 DebugLoc dl = getCurDebugLoc();
3484 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3485 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3486 SDValue Op = getValue(I.getOperand(1));
3487 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3489 // Scale the exponent by log10(2) [0.30102999f].
3490 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3491 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3492 getF32Constant(DAG, 0x3e9a209a));
3494 // Get the significand and build it into a floating-point number with
3496 SDValue X = GetSignificand(DAG, Op1, dl);
3498 if (LimitFloatPrecision <= 6) {
3499 // For floating-point precision of 6:
3501 // Log10ofMantissa =
3503 // (0.60948995f - 0.10380950f * x) * x;
3505 // error 0.0014886165, which is 6 bits
3506 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3507 getF32Constant(DAG, 0xbdd49a13));
3508 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3509 getF32Constant(DAG, 0x3f1c0789));
3510 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3511 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3512 getF32Constant(DAG, 0x3f011300));
3514 result = DAG.getNode(ISD::FADD, dl,
3515 MVT::f32, LogOfExponent, Log10ofMantissa);
3516 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3517 // For floating-point precision of 12:
3519 // Log10ofMantissa =
3522 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3524 // error 0.00019228036, which is better than 12 bits
3525 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3526 getF32Constant(DAG, 0x3d431f31));
3527 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3528 getF32Constant(DAG, 0x3ea21fb2));
3529 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3530 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3531 getF32Constant(DAG, 0x3f6ae232));
3532 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3533 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3534 getF32Constant(DAG, 0x3f25f7c3));
3536 result = DAG.getNode(ISD::FADD, dl,
3537 MVT::f32, LogOfExponent, Log10ofMantissa);
3538 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3539 // For floating-point precision of 18:
3541 // Log10ofMantissa =
3546 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3548 // error 0.0000037995730, which is better than 18 bits
3549 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3550 getF32Constant(DAG, 0x3c5d51ce));
3551 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3552 getF32Constant(DAG, 0x3e00685a));
3553 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3554 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3555 getF32Constant(DAG, 0x3efb6798));
3556 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3557 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3558 getF32Constant(DAG, 0x3f88d192));
3559 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3560 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3561 getF32Constant(DAG, 0x3fc4316c));
3562 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3563 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3564 getF32Constant(DAG, 0x3f57ce70));
3566 result = DAG.getNode(ISD::FADD, dl,
3567 MVT::f32, LogOfExponent, Log10ofMantissa);
3570 // No special expansion.
3571 result = DAG.getNode(ISD::FLOG10, dl,
3572 getValue(I.getOperand(1)).getValueType(),
3573 getValue(I.getOperand(1)));
3576 setValue(&I, result);
3579 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3580 /// limited-precision mode.
3582 SelectionDAGLowering::visitExp2(CallInst &I) {
3584 DebugLoc dl = getCurDebugLoc();
3586 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3587 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3588 SDValue Op = getValue(I.getOperand(1));
3590 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3592 // FractionalPartOfX = x - (float)IntegerPartOfX;
3593 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3594 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3596 // IntegerPartOfX <<= 23;
3597 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3598 DAG.getConstant(23, TLI.getPointerTy()));
3600 if (LimitFloatPrecision <= 6) {
3601 // For floating-point precision of 6:
3603 // TwoToFractionalPartOfX =
3605 // (0.735607626f + 0.252464424f * x) * x;
3607 // error 0.0144103317, which is 6 bits
3608 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3609 getF32Constant(DAG, 0x3e814304));
3610 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3611 getF32Constant(DAG, 0x3f3c50c8));
3612 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3613 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3614 getF32Constant(DAG, 0x3f7f5e7e));
3615 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3616 SDValue TwoToFractionalPartOfX =
3617 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3619 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3620 MVT::f32, TwoToFractionalPartOfX);
3621 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3622 // For floating-point precision of 12:
3624 // TwoToFractionalPartOfX =
3627 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3629 // error 0.000107046256, which is 13 to 14 bits
3630 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3631 getF32Constant(DAG, 0x3da235e3));
3632 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3633 getF32Constant(DAG, 0x3e65b8f3));
3634 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3635 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3636 getF32Constant(DAG, 0x3f324b07));
3637 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3638 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3639 getF32Constant(DAG, 0x3f7ff8fd));
3640 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3641 SDValue TwoToFractionalPartOfX =
3642 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3644 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3645 MVT::f32, TwoToFractionalPartOfX);
3646 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3647 // For floating-point precision of 18:
3649 // TwoToFractionalPartOfX =
3653 // (0.554906021e-1f +
3654 // (0.961591928e-2f +
3655 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3656 // error 2.47208000*10^(-7), which is better than 18 bits
3657 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3658 getF32Constant(DAG, 0x3924b03e));
3659 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3660 getF32Constant(DAG, 0x3ab24b87));
3661 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3662 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3663 getF32Constant(DAG, 0x3c1d8c17));
3664 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3665 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3666 getF32Constant(DAG, 0x3d634a1d));
3667 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3668 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3669 getF32Constant(DAG, 0x3e75fe14));
3670 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3671 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3672 getF32Constant(DAG, 0x3f317234));
3673 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3674 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3675 getF32Constant(DAG, 0x3f800000));
3676 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3677 SDValue TwoToFractionalPartOfX =
3678 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3680 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3681 MVT::f32, TwoToFractionalPartOfX);
3684 // No special expansion.
3685 result = DAG.getNode(ISD::FEXP2, dl,
3686 getValue(I.getOperand(1)).getValueType(),
3687 getValue(I.getOperand(1)));
3690 setValue(&I, result);
3693 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3694 /// limited-precision mode with x == 10.0f.
3696 SelectionDAGLowering::visitPow(CallInst &I) {
3698 Value *Val = I.getOperand(1);
3699 DebugLoc dl = getCurDebugLoc();
3700 bool IsExp10 = false;
3702 if (getValue(Val).getValueType() == MVT::f32 &&
3703 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3704 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3705 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3706 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3708 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3713 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3714 SDValue Op = getValue(I.getOperand(2));
3716 // Put the exponent in the right bit position for later addition to the
3719 // #define LOG2OF10 3.3219281f
3720 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3721 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3722 getF32Constant(DAG, 0x40549a78));
3723 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3725 // FractionalPartOfX = x - (float)IntegerPartOfX;
3726 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3727 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3729 // IntegerPartOfX <<= 23;
3730 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3731 DAG.getConstant(23, TLI.getPointerTy()));
3733 if (LimitFloatPrecision <= 6) {
3734 // For floating-point precision of 6:
3736 // twoToFractionalPartOfX =
3738 // (0.735607626f + 0.252464424f * x) * x;
3740 // error 0.0144103317, which is 6 bits
3741 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3742 getF32Constant(DAG, 0x3e814304));
3743 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3744 getF32Constant(DAG, 0x3f3c50c8));
3745 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3746 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3747 getF32Constant(DAG, 0x3f7f5e7e));
3748 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3749 SDValue TwoToFractionalPartOfX =
3750 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3752 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3753 MVT::f32, TwoToFractionalPartOfX);
3754 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3755 // For floating-point precision of 12:
3757 // TwoToFractionalPartOfX =
3760 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3762 // error 0.000107046256, which is 13 to 14 bits
3763 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3764 getF32Constant(DAG, 0x3da235e3));
3765 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3766 getF32Constant(DAG, 0x3e65b8f3));
3767 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3768 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3769 getF32Constant(DAG, 0x3f324b07));
3770 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3771 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3772 getF32Constant(DAG, 0x3f7ff8fd));
3773 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3774 SDValue TwoToFractionalPartOfX =
3775 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3777 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3778 MVT::f32, TwoToFractionalPartOfX);
3779 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3780 // For floating-point precision of 18:
3782 // TwoToFractionalPartOfX =
3786 // (0.554906021e-1f +
3787 // (0.961591928e-2f +
3788 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3789 // error 2.47208000*10^(-7), which is better than 18 bits
3790 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3791 getF32Constant(DAG, 0x3924b03e));
3792 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3793 getF32Constant(DAG, 0x3ab24b87));
3794 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3795 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3796 getF32Constant(DAG, 0x3c1d8c17));
3797 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3798 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3799 getF32Constant(DAG, 0x3d634a1d));
3800 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3801 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3802 getF32Constant(DAG, 0x3e75fe14));
3803 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3804 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3805 getF32Constant(DAG, 0x3f317234));
3806 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3807 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3808 getF32Constant(DAG, 0x3f800000));
3809 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3810 SDValue TwoToFractionalPartOfX =
3811 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3813 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3814 MVT::f32, TwoToFractionalPartOfX);
3817 // No special expansion.
3818 result = DAG.getNode(ISD::FPOW, dl,
3819 getValue(I.getOperand(1)).getValueType(),
3820 getValue(I.getOperand(1)),
3821 getValue(I.getOperand(2)));
3824 setValue(&I, result);
3827 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3828 /// we want to emit this as a call to a named external function, return the name
3829 /// otherwise lower it and return null.
3831 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3832 DebugLoc dl = getCurDebugLoc();
3833 switch (Intrinsic) {
3835 // By default, turn this into a target intrinsic node.
3836 visitTargetIntrinsic(I, Intrinsic);
3838 case Intrinsic::vastart: visitVAStart(I); return 0;
3839 case Intrinsic::vaend: visitVAEnd(I); return 0;
3840 case Intrinsic::vacopy: visitVACopy(I); return 0;
3841 case Intrinsic::returnaddress:
3842 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3843 getValue(I.getOperand(1))));
3845 case Intrinsic::frameaddress:
3846 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3847 getValue(I.getOperand(1))));
3849 case Intrinsic::setjmp:
3850 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3852 case Intrinsic::longjmp:
3853 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3855 case Intrinsic::memcpy: {
3856 SDValue Op1 = getValue(I.getOperand(1));
3857 SDValue Op2 = getValue(I.getOperand(2));
3858 SDValue Op3 = getValue(I.getOperand(3));
3859 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3860 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3861 I.getOperand(1), 0, I.getOperand(2), 0));
3864 case Intrinsic::memset: {
3865 SDValue Op1 = getValue(I.getOperand(1));
3866 SDValue Op2 = getValue(I.getOperand(2));
3867 SDValue Op3 = getValue(I.getOperand(3));
3868 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3869 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3870 I.getOperand(1), 0));
3873 case Intrinsic::memmove: {
3874 SDValue Op1 = getValue(I.getOperand(1));
3875 SDValue Op2 = getValue(I.getOperand(2));
3876 SDValue Op3 = getValue(I.getOperand(3));
3877 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3879 // If the source and destination are known to not be aliases, we can
3880 // lower memmove as memcpy.
3881 uint64_t Size = -1ULL;
3882 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3883 Size = C->getZExtValue();
3884 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3885 AliasAnalysis::NoAlias) {
3886 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3887 I.getOperand(1), 0, I.getOperand(2), 0));
3891 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3892 I.getOperand(1), 0, I.getOperand(2), 0));
3895 case Intrinsic::dbg_stoppoint: {
3896 DwarfWriter *DW = DAG.getDwarfWriter();
3897 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3898 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
3899 MachineFunction &MF = DAG.getMachineFunction();
3900 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3904 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3905 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(),
3907 unsigned idx = MF.getOrCreateDebugLocID(SrcFile,
3908 SPI.getLine(), SPI.getColumn());
3909 setCurDebugLoc(DebugLoc::get(idx));
3913 case Intrinsic::dbg_region_start: {
3914 DwarfWriter *DW = DAG.getDwarfWriter();
3915 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3916 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
3918 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3920 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3921 getRoot(), LabelID));
3926 case Intrinsic::dbg_region_end: {
3927 DwarfWriter *DW = DAG.getDwarfWriter();
3928 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3929 if (DW && DW->ValidDebugInfo(REI.getContext())) {
3931 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3933 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3934 getRoot(), LabelID));
3939 case Intrinsic::dbg_func_start: {
3940 DwarfWriter *DW = DAG.getDwarfWriter();
3942 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3943 Value *SP = FSI.getSubprogram();
3944 if (SP && DW->ValidDebugInfo(SP)) {
3945 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3946 // what (most?) gdb expects.
3947 MachineFunction &MF = DAG.getMachineFunction();
3948 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3949 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3950 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(),
3951 CompileUnit.getFilename());
3953 // Record the source line but does not create a label for the normal
3954 // function start. It will be emitted at asm emission time. However,
3955 // create a label if this is a beginning of inlined function.
3956 unsigned Line = Subprogram.getLineNumber();
3959 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3960 if (DW->getRecordSourceLineCount() != 1)
3961 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3962 getRoot(), LabelID));
3965 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
3970 case Intrinsic::dbg_declare: {
3972 DwarfWriter *DW = DAG.getDwarfWriter();
3973 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3974 Value *Variable = DI.getVariable();
3975 if (DW && DW->ValidDebugInfo(Variable))
3976 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3977 getValue(DI.getAddress()), getValue(Variable)));
3979 // FIXME: Do something sensible here when we support debug declare.
3983 case Intrinsic::eh_exception: {
3984 if (!CurMBB->isLandingPad()) {
3985 // FIXME: Mark exception register as live in. Hack for PR1508.
3986 unsigned Reg = TLI.getExceptionAddressRegister();
3987 if (Reg) CurMBB->addLiveIn(Reg);
3989 // Insert the EXCEPTIONADDR instruction.
3990 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3992 Ops[0] = DAG.getRoot();
3993 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3995 DAG.setRoot(Op.getValue(1));
3999 case Intrinsic::eh_selector_i32:
4000 case Intrinsic::eh_selector_i64: {
4001 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4002 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4003 MVT::i32 : MVT::i64);
4006 if (CurMBB->isLandingPad())
4007 AddCatchInfo(I, MMI, CurMBB);
4010 FuncInfo.CatchInfoLost.insert(&I);
4012 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4013 unsigned Reg = TLI.getExceptionSelectorRegister();
4014 if (Reg) CurMBB->addLiveIn(Reg);
4017 // Insert the EHSELECTION instruction.
4018 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4020 Ops[0] = getValue(I.getOperand(1));
4022 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4024 DAG.setRoot(Op.getValue(1));
4026 setValue(&I, DAG.getConstant(0, VT));
4032 case Intrinsic::eh_typeid_for_i32:
4033 case Intrinsic::eh_typeid_for_i64: {
4034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4035 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4036 MVT::i32 : MVT::i64);
4039 // Find the type id for the given typeinfo.
4040 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4042 unsigned TypeID = MMI->getTypeIDFor(GV);
4043 setValue(&I, DAG.getConstant(TypeID, VT));
4045 // Return something different to eh_selector.
4046 setValue(&I, DAG.getConstant(1, VT));
4052 case Intrinsic::eh_return_i32:
4053 case Intrinsic::eh_return_i64:
4054 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4055 MMI->setCallsEHReturn(true);
4056 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4059 getValue(I.getOperand(1)),
4060 getValue(I.getOperand(2))));
4062 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4066 case Intrinsic::eh_unwind_init:
4067 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4068 MMI->setCallsUnwindInit(true);
4073 case Intrinsic::eh_dwarf_cfa: {
4074 MVT VT = getValue(I.getOperand(1)).getValueType();
4076 if (VT.bitsGT(TLI.getPointerTy()))
4077 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4078 TLI.getPointerTy(), getValue(I.getOperand(1)));
4080 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4081 TLI.getPointerTy(), getValue(I.getOperand(1)));
4083 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4085 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4086 TLI.getPointerTy()),
4088 setValue(&I, DAG.getNode(ISD::ADD, dl,
4090 DAG.getNode(ISD::FRAMEADDR, dl,
4093 TLI.getPointerTy())),
4098 case Intrinsic::convertff:
4099 case Intrinsic::convertfsi:
4100 case Intrinsic::convertfui:
4101 case Intrinsic::convertsif:
4102 case Intrinsic::convertuif:
4103 case Intrinsic::convertss:
4104 case Intrinsic::convertsu:
4105 case Intrinsic::convertus:
4106 case Intrinsic::convertuu: {
4107 ISD::CvtCode Code = ISD::CVT_INVALID;
4108 switch (Intrinsic) {
4109 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4110 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4111 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4112 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4113 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4114 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4115 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4116 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4117 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4119 MVT DestVT = TLI.getValueType(I.getType());
4120 Value* Op1 = I.getOperand(1);
4121 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4122 DAG.getValueType(DestVT),
4123 DAG.getValueType(getValue(Op1).getValueType()),
4124 getValue(I.getOperand(2)),
4125 getValue(I.getOperand(3)),
4130 case Intrinsic::sqrt:
4131 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4132 getValue(I.getOperand(1)).getValueType(),
4133 getValue(I.getOperand(1))));
4135 case Intrinsic::powi:
4136 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4137 getValue(I.getOperand(1)).getValueType(),
4138 getValue(I.getOperand(1)),
4139 getValue(I.getOperand(2))));
4141 case Intrinsic::sin:
4142 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4143 getValue(I.getOperand(1)).getValueType(),
4144 getValue(I.getOperand(1))));
4146 case Intrinsic::cos:
4147 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4148 getValue(I.getOperand(1)).getValueType(),
4149 getValue(I.getOperand(1))));
4151 case Intrinsic::log:
4154 case Intrinsic::log2:
4157 case Intrinsic::log10:
4160 case Intrinsic::exp:
4163 case Intrinsic::exp2:
4166 case Intrinsic::pow:
4169 case Intrinsic::pcmarker: {
4170 SDValue Tmp = getValue(I.getOperand(1));
4171 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4174 case Intrinsic::readcyclecounter: {
4175 SDValue Op = getRoot();
4176 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4177 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4180 DAG.setRoot(Tmp.getValue(1));
4183 case Intrinsic::part_select: {
4184 // Currently not implemented: just abort
4185 assert(0 && "part_select intrinsic not implemented");
4188 case Intrinsic::part_set: {
4189 // Currently not implemented: just abort
4190 assert(0 && "part_set intrinsic not implemented");
4193 case Intrinsic::bswap:
4194 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4195 getValue(I.getOperand(1)).getValueType(),
4196 getValue(I.getOperand(1))));
4198 case Intrinsic::cttz: {
4199 SDValue Arg = getValue(I.getOperand(1));
4200 MVT Ty = Arg.getValueType();
4201 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4202 setValue(&I, result);
4205 case Intrinsic::ctlz: {
4206 SDValue Arg = getValue(I.getOperand(1));
4207 MVT Ty = Arg.getValueType();
4208 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4209 setValue(&I, result);
4212 case Intrinsic::ctpop: {
4213 SDValue Arg = getValue(I.getOperand(1));
4214 MVT Ty = Arg.getValueType();
4215 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4216 setValue(&I, result);
4219 case Intrinsic::stacksave: {
4220 SDValue Op = getRoot();
4221 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4222 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4224 DAG.setRoot(Tmp.getValue(1));
4227 case Intrinsic::stackrestore: {
4228 SDValue Tmp = getValue(I.getOperand(1));
4229 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4232 case Intrinsic::stackprotector: {
4233 // Emit code into the DAG to store the stack guard onto the stack.
4234 MachineFunction &MF = DAG.getMachineFunction();
4235 MachineFrameInfo *MFI = MF.getFrameInfo();
4236 MVT PtrTy = TLI.getPointerTy();
4238 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4239 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4241 int FI = FuncInfo.StaticAllocaMap[Slot];
4242 MFI->setStackProtectorIndex(FI);
4244 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4246 // Store the stack protector onto the stack.
4247 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4248 PseudoSourceValue::getFixedStack(FI),
4250 setValue(&I, Result);
4251 DAG.setRoot(Result);
4254 case Intrinsic::var_annotation:
4255 // Discard annotate attributes
4258 case Intrinsic::init_trampoline: {
4259 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4263 Ops[1] = getValue(I.getOperand(1));
4264 Ops[2] = getValue(I.getOperand(2));
4265 Ops[3] = getValue(I.getOperand(3));
4266 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4267 Ops[5] = DAG.getSrcValue(F);
4269 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4270 DAG.getNodeValueTypes(TLI.getPointerTy(),
4275 DAG.setRoot(Tmp.getValue(1));
4279 case Intrinsic::gcroot:
4281 Value *Alloca = I.getOperand(1);
4282 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4284 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4285 GFI->addStackRoot(FI->getIndex(), TypeMap);
4289 case Intrinsic::gcread:
4290 case Intrinsic::gcwrite:
4291 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4294 case Intrinsic::flt_rounds: {
4295 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4299 case Intrinsic::trap: {
4300 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4304 case Intrinsic::uadd_with_overflow:
4305 return implVisitAluOverflow(I, ISD::UADDO);
4306 case Intrinsic::sadd_with_overflow:
4307 return implVisitAluOverflow(I, ISD::SADDO);
4308 case Intrinsic::usub_with_overflow:
4309 return implVisitAluOverflow(I, ISD::USUBO);
4310 case Intrinsic::ssub_with_overflow:
4311 return implVisitAluOverflow(I, ISD::SSUBO);
4312 case Intrinsic::umul_with_overflow:
4313 return implVisitAluOverflow(I, ISD::UMULO);
4314 case Intrinsic::smul_with_overflow:
4315 return implVisitAluOverflow(I, ISD::SMULO);
4317 case Intrinsic::prefetch: {
4320 Ops[1] = getValue(I.getOperand(1));
4321 Ops[2] = getValue(I.getOperand(2));
4322 Ops[3] = getValue(I.getOperand(3));
4323 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4327 case Intrinsic::memory_barrier: {
4330 for (int x = 1; x < 6; ++x)
4331 Ops[x] = getValue(I.getOperand(x));
4333 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4336 case Intrinsic::atomic_cmp_swap: {
4337 SDValue Root = getRoot();
4339 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4340 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4342 getValue(I.getOperand(1)),
4343 getValue(I.getOperand(2)),
4344 getValue(I.getOperand(3)),
4347 DAG.setRoot(L.getValue(1));
4350 case Intrinsic::atomic_load_add:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4352 case Intrinsic::atomic_load_sub:
4353 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4354 case Intrinsic::atomic_load_or:
4355 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4356 case Intrinsic::atomic_load_xor:
4357 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4358 case Intrinsic::atomic_load_and:
4359 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4360 case Intrinsic::atomic_load_nand:
4361 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4362 case Intrinsic::atomic_load_max:
4363 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4364 case Intrinsic::atomic_load_min:
4365 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4366 case Intrinsic::atomic_load_umin:
4367 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4368 case Intrinsic::atomic_load_umax:
4369 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4370 case Intrinsic::atomic_swap:
4371 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4376 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4378 MachineBasicBlock *LandingPad) {
4379 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4380 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4381 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4382 unsigned BeginLabel = 0, EndLabel = 0;
4384 TargetLowering::ArgListTy Args;
4385 TargetLowering::ArgListEntry Entry;
4386 Args.reserve(CS.arg_size());
4387 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4389 SDValue ArgNode = getValue(*i);
4390 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4392 unsigned attrInd = i - CS.arg_begin() + 1;
4393 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4394 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4395 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4396 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4397 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4398 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4399 Entry.Alignment = CS.getParamAlignment(attrInd);
4400 Args.push_back(Entry);
4403 if (LandingPad && MMI) {
4404 // Insert a label before the invoke call to mark the try range. This can be
4405 // used to detect deletion of the invoke via the MachineModuleInfo.
4406 BeginLabel = MMI->NextLabelID();
4407 // Both PendingLoads and PendingExports must be flushed here;
4408 // this call might not return.
4410 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4411 getControlRoot(), BeginLabel));
4414 std::pair<SDValue,SDValue> Result =
4415 TLI.LowerCallTo(getRoot(), CS.getType(),
4416 CS.paramHasAttr(0, Attribute::SExt),
4417 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4418 CS.paramHasAttr(0, Attribute::InReg),
4419 CS.getCallingConv(),
4420 IsTailCall && PerformTailCallOpt,
4421 Callee, Args, DAG, getCurDebugLoc());
4422 if (CS.getType() != Type::VoidTy)
4423 setValue(CS.getInstruction(), Result.first);
4424 DAG.setRoot(Result.second);
4426 if (LandingPad && MMI) {
4427 // Insert a label at the end of the invoke call to mark the try range. This
4428 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4429 EndLabel = MMI->NextLabelID();
4430 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4431 getRoot(), EndLabel));
4433 // Inform MachineModuleInfo of range.
4434 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4439 void SelectionDAGLowering::visitCall(CallInst &I) {
4440 const char *RenameFn = 0;
4441 if (Function *F = I.getCalledFunction()) {
4442 if (F->isDeclaration()) {
4443 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4445 if (unsigned IID = II->getIntrinsicID(F)) {
4446 RenameFn = visitIntrinsicCall(I, IID);
4451 if (unsigned IID = F->getIntrinsicID()) {
4452 RenameFn = visitIntrinsicCall(I, IID);
4458 // Check for well-known libc/libm calls. If the function is internal, it
4459 // can't be a library call.
4460 unsigned NameLen = F->getNameLen();
4461 if (!F->hasLocalLinkage() && NameLen) {
4462 const char *NameStr = F->getNameStart();
4463 if (NameStr[0] == 'c' &&
4464 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4465 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4466 if (I.getNumOperands() == 3 && // Basic sanity checks.
4467 I.getOperand(1)->getType()->isFloatingPoint() &&
4468 I.getType() == I.getOperand(1)->getType() &&
4469 I.getType() == I.getOperand(2)->getType()) {
4470 SDValue LHS = getValue(I.getOperand(1));
4471 SDValue RHS = getValue(I.getOperand(2));
4472 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4473 LHS.getValueType(), LHS, RHS));
4476 } else if (NameStr[0] == 'f' &&
4477 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4478 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4479 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4480 if (I.getNumOperands() == 2 && // Basic sanity checks.
4481 I.getOperand(1)->getType()->isFloatingPoint() &&
4482 I.getType() == I.getOperand(1)->getType()) {
4483 SDValue Tmp = getValue(I.getOperand(1));
4484 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4485 Tmp.getValueType(), Tmp));
4488 } else if (NameStr[0] == 's' &&
4489 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4490 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4491 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4492 if (I.getNumOperands() == 2 && // Basic sanity checks.
4493 I.getOperand(1)->getType()->isFloatingPoint() &&
4494 I.getType() == I.getOperand(1)->getType()) {
4495 SDValue Tmp = getValue(I.getOperand(1));
4496 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4497 Tmp.getValueType(), Tmp));
4500 } else if (NameStr[0] == 'c' &&
4501 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4502 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4503 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4504 if (I.getNumOperands() == 2 && // Basic sanity checks.
4505 I.getOperand(1)->getType()->isFloatingPoint() &&
4506 I.getType() == I.getOperand(1)->getType()) {
4507 SDValue Tmp = getValue(I.getOperand(1));
4508 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4509 Tmp.getValueType(), Tmp));
4514 } else if (isa<InlineAsm>(I.getOperand(0))) {
4521 Callee = getValue(I.getOperand(0));
4523 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4525 LowerCallTo(&I, Callee, I.isTailCall());
4529 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4530 /// this value and returns the result as a ValueVT value. This uses
4531 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4532 /// If the Flag pointer is NULL, no flag is used.
4533 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4535 SDValue *Flag) const {
4536 // Assemble the legal parts into the final values.
4537 SmallVector<SDValue, 4> Values(ValueVTs.size());
4538 SmallVector<SDValue, 8> Parts;
4539 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4540 // Copy the legal parts from the registers.
4541 MVT ValueVT = ValueVTs[Value];
4542 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4543 MVT RegisterVT = RegVTs[Value];
4545 Parts.resize(NumRegs);
4546 for (unsigned i = 0; i != NumRegs; ++i) {
4549 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4551 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4552 *Flag = P.getValue(2);
4554 Chain = P.getValue(1);
4556 // If the source register was virtual and if we know something about it,
4557 // add an assert node.
4558 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4559 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4560 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4561 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4562 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4563 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4565 unsigned RegSize = RegisterVT.getSizeInBits();
4566 unsigned NumSignBits = LOI.NumSignBits;
4567 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4569 // FIXME: We capture more information than the dag can represent. For
4570 // now, just use the tightest assertzext/assertsext possible.
4572 MVT FromVT(MVT::Other);
4573 if (NumSignBits == RegSize)
4574 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4575 else if (NumZeroBits >= RegSize-1)
4576 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4577 else if (NumSignBits > RegSize-8)
4578 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4579 else if (NumZeroBits >= RegSize-9)
4580 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4581 else if (NumSignBits > RegSize-16)
4582 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4583 else if (NumZeroBits >= RegSize-17)
4584 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4585 else if (NumSignBits > RegSize-32)
4586 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4587 else if (NumZeroBits >= RegSize-33)
4588 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4590 if (FromVT != MVT::Other) {
4591 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4592 RegisterVT, P, DAG.getValueType(FromVT));
4601 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4602 NumRegs, RegisterVT, ValueVT);
4607 return DAG.getNode(ISD::MERGE_VALUES, dl,
4608 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4609 &Values[0], ValueVTs.size());
4612 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4613 /// specified value into the registers specified by this object. This uses
4614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4615 /// If the Flag pointer is NULL, no flag is used.
4616 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4617 SDValue &Chain, SDValue *Flag) const {
4618 // Get the list of the values's legal parts.
4619 unsigned NumRegs = Regs.size();
4620 SmallVector<SDValue, 8> Parts(NumRegs);
4621 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4622 MVT ValueVT = ValueVTs[Value];
4623 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4624 MVT RegisterVT = RegVTs[Value];
4626 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4627 &Parts[Part], NumParts, RegisterVT);
4631 // Copy the parts into the registers.
4632 SmallVector<SDValue, 8> Chains(NumRegs);
4633 for (unsigned i = 0; i != NumRegs; ++i) {
4636 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4638 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4639 *Flag = Part.getValue(1);
4641 Chains[i] = Part.getValue(0);
4644 if (NumRegs == 1 || Flag)
4645 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4646 // flagged to it. That is the CopyToReg nodes and the user are considered
4647 // a single scheduling unit. If we create a TokenFactor and return it as
4648 // chain, then the TokenFactor is both a predecessor (operand) of the
4649 // user as well as a successor (the TF operands are flagged to the user).
4650 // c1, f1 = CopyToReg
4651 // c2, f2 = CopyToReg
4652 // c3 = TokenFactor c1, c2
4655 Chain = Chains[NumRegs-1];
4657 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4660 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4661 /// operand list. This adds the code marker and includes the number of
4662 /// values added into it.
4663 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4664 std::vector<SDValue> &Ops) const {
4665 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4666 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4667 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4668 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4669 MVT RegisterVT = RegVTs[Value];
4670 for (unsigned i = 0; i != NumRegs; ++i) {
4671 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4672 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4677 /// isAllocatableRegister - If the specified register is safe to allocate,
4678 /// i.e. it isn't a stack pointer or some other special register, return the
4679 /// register class for the register. Otherwise, return null.
4680 static const TargetRegisterClass *
4681 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4682 const TargetLowering &TLI,
4683 const TargetRegisterInfo *TRI) {
4684 MVT FoundVT = MVT::Other;
4685 const TargetRegisterClass *FoundRC = 0;
4686 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4687 E = TRI->regclass_end(); RCI != E; ++RCI) {
4688 MVT ThisVT = MVT::Other;
4690 const TargetRegisterClass *RC = *RCI;
4691 // If none of the the value types for this register class are valid, we
4692 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4693 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4695 if (TLI.isTypeLegal(*I)) {
4696 // If we have already found this register in a different register class,
4697 // choose the one with the largest VT specified. For example, on
4698 // PowerPC, we favor f64 register classes over f32.
4699 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4706 if (ThisVT == MVT::Other) continue;
4708 // NOTE: This isn't ideal. In particular, this might allocate the
4709 // frame pointer in functions that need it (due to them not being taken
4710 // out of allocation, because a variable sized allocation hasn't been seen
4711 // yet). This is a slight code pessimization, but should still work.
4712 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4713 E = RC->allocation_order_end(MF); I != E; ++I)
4715 // We found a matching register class. Keep looking at others in case
4716 // we find one with larger registers that this physreg is also in.
4727 /// AsmOperandInfo - This contains information for each constraint that we are
4729 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4730 public TargetLowering::AsmOperandInfo {
4732 /// CallOperand - If this is the result output operand or a clobber
4733 /// this is null, otherwise it is the incoming operand to the CallInst.
4734 /// This gets modified as the asm is processed.
4735 SDValue CallOperand;
4737 /// AssignedRegs - If this is a register or register class operand, this
4738 /// contains the set of register corresponding to the operand.
4739 RegsForValue AssignedRegs;
4741 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4742 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4745 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4746 /// busy in OutputRegs/InputRegs.
4747 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4748 std::set<unsigned> &OutputRegs,
4749 std::set<unsigned> &InputRegs,
4750 const TargetRegisterInfo &TRI) const {
4752 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4753 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4756 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4757 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4761 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4762 /// corresponds to. If there is no Value* for this operand, it returns
4764 MVT getCallOperandValMVT(const TargetLowering &TLI,
4765 const TargetData *TD) const {
4766 if (CallOperandVal == 0) return MVT::Other;
4768 if (isa<BasicBlock>(CallOperandVal))
4769 return TLI.getPointerTy();
4771 const llvm::Type *OpTy = CallOperandVal->getType();
4773 // If this is an indirect operand, the operand is a pointer to the
4776 OpTy = cast<PointerType>(OpTy)->getElementType();
4778 // If OpTy is not a single value, it may be a struct/union that we
4779 // can tile with integers.
4780 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4781 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4790 OpTy = IntegerType::get(BitSize);
4795 return TLI.getValueType(OpTy, true);
4799 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4801 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4802 const TargetRegisterInfo &TRI) {
4803 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4805 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4806 for (; *Aliases; ++Aliases)
4807 Regs.insert(*Aliases);
4810 } // end llvm namespace.
4813 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4814 /// specified operand. We prefer to assign virtual registers, to allow the
4815 /// register allocator handle the assignment process. However, if the asm uses
4816 /// features that we can't model on machineinstrs, we have SDISel do the
4817 /// allocation. This produces generally horrible, but correct, code.
4819 /// OpInfo describes the operand.
4820 /// Input and OutputRegs are the set of already allocated physical registers.
4822 void SelectionDAGLowering::
4823 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4824 std::set<unsigned> &OutputRegs,
4825 std::set<unsigned> &InputRegs) {
4826 // Compute whether this value requires an input register, an output register,
4828 bool isOutReg = false;
4829 bool isInReg = false;
4830 switch (OpInfo.Type) {
4831 case InlineAsm::isOutput:
4834 // If there is an input constraint that matches this, we need to reserve
4835 // the input register so no other inputs allocate to it.
4836 isInReg = OpInfo.hasMatchingInput();
4838 case InlineAsm::isInput:
4842 case InlineAsm::isClobber:
4849 MachineFunction &MF = DAG.getMachineFunction();
4850 SmallVector<unsigned, 4> Regs;
4852 // If this is a constraint for a single physreg, or a constraint for a
4853 // register class, find it.
4854 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4855 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4856 OpInfo.ConstraintVT);
4858 unsigned NumRegs = 1;
4859 if (OpInfo.ConstraintVT != MVT::Other) {
4860 // If this is a FP input in an integer register (or visa versa) insert a bit
4861 // cast of the input value. More generally, handle any case where the input
4862 // value disagrees with the register class we plan to stick this in.
4863 if (OpInfo.Type == InlineAsm::isInput &&
4864 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4865 // Try to convert to the first MVT that the reg class contains. If the
4866 // types are identical size, use a bitcast to convert (e.g. two differing
4868 MVT RegVT = *PhysReg.second->vt_begin();
4869 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4870 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4871 RegVT, OpInfo.CallOperand);
4872 OpInfo.ConstraintVT = RegVT;
4873 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4874 // If the input is a FP value and we want it in FP registers, do a
4875 // bitcast to the corresponding integer type. This turns an f64 value
4876 // into i64, which can be passed with two i32 values on a 32-bit
4878 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4879 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4880 RegVT, OpInfo.CallOperand);
4881 OpInfo.ConstraintVT = RegVT;
4885 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4889 MVT ValueVT = OpInfo.ConstraintVT;
4891 // If this is a constraint for a specific physical register, like {r17},
4893 if (PhysReg.first) {
4894 if (OpInfo.ConstraintVT == MVT::Other)
4895 ValueVT = *PhysReg.second->vt_begin();
4897 // Get the actual register value type. This is important, because the user
4898 // may have asked for (e.g.) the AX register in i32 type. We need to
4899 // remember that AX is actually i16 to get the right extension.
4900 RegVT = *PhysReg.second->vt_begin();
4902 // This is a explicit reference to a physical register.
4903 Regs.push_back(PhysReg.first);
4905 // If this is an expanded reference, add the rest of the regs to Regs.
4907 TargetRegisterClass::iterator I = PhysReg.second->begin();
4908 for (; *I != PhysReg.first; ++I)
4909 assert(I != PhysReg.second->end() && "Didn't find reg!");
4911 // Already added the first reg.
4913 for (; NumRegs; --NumRegs, ++I) {
4914 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4918 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4919 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4920 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4924 // Otherwise, if this was a reference to an LLVM register class, create vregs
4925 // for this reference.
4926 std::vector<unsigned> RegClassRegs;
4927 const TargetRegisterClass *RC = PhysReg.second;
4929 // If this is a tied register, our regalloc doesn't know how to maintain
4930 // the constraint, so we have to pick a register to pin the input/output to.
4931 // If it isn't a matched constraint, go ahead and create vreg and let the
4932 // regalloc do its thing.
4933 if (!OpInfo.hasMatchingInput()) {
4934 RegVT = *PhysReg.second->vt_begin();
4935 if (OpInfo.ConstraintVT == MVT::Other)
4938 // Create the appropriate number of virtual registers.
4939 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4940 for (; NumRegs; --NumRegs)
4941 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4943 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4947 // Otherwise, we can't allocate it. Let the code below figure out how to
4948 // maintain these constraints.
4949 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4952 // This is a reference to a register class that doesn't directly correspond
4953 // to an LLVM register class. Allocate NumRegs consecutive, available,
4954 // registers from the class.
4955 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4956 OpInfo.ConstraintVT);
4959 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4960 unsigned NumAllocated = 0;
4961 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4962 unsigned Reg = RegClassRegs[i];
4963 // See if this register is available.
4964 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4965 (isInReg && InputRegs.count(Reg))) { // Already used.
4966 // Make sure we find consecutive registers.
4971 // Check to see if this register is allocatable (i.e. don't give out the
4974 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4975 if (!RC) { // Couldn't allocate this register.
4976 // Reset NumAllocated to make sure we return consecutive registers.
4982 // Okay, this register is good, we can use it.
4985 // If we allocated enough consecutive registers, succeed.
4986 if (NumAllocated == NumRegs) {
4987 unsigned RegStart = (i-NumAllocated)+1;
4988 unsigned RegEnd = i+1;
4989 // Mark all of the allocated registers used.
4990 for (unsigned i = RegStart; i != RegEnd; ++i)
4991 Regs.push_back(RegClassRegs[i]);
4993 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4994 OpInfo.ConstraintVT);
4995 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5000 // Otherwise, we couldn't allocate enough registers for this.
5003 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5004 /// processed uses a memory 'm' constraint.
5006 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5007 const TargetLowering &TLI) {
5008 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5009 InlineAsm::ConstraintInfo &CI = CInfos[i];
5010 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5011 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5012 if (CType == TargetLowering::C_Memory)
5020 /// visitInlineAsm - Handle a call to an InlineAsm object.
5022 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5023 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5025 /// ConstraintOperands - Information about all of the constraints.
5026 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5028 SDValue Chain = getRoot();
5031 std::set<unsigned> OutputRegs, InputRegs;
5033 // Do a prepass over the constraints, canonicalizing them, and building up the
5034 // ConstraintOperands list.
5035 std::vector<InlineAsm::ConstraintInfo>
5036 ConstraintInfos = IA->ParseConstraints();
5038 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5040 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5041 unsigned ResNo = 0; // ResNo - The result number of the next output.
5042 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5043 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5044 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5046 MVT OpVT = MVT::Other;
5048 // Compute the value type for each operand.
5049 switch (OpInfo.Type) {
5050 case InlineAsm::isOutput:
5051 // Indirect outputs just consume an argument.
5052 if (OpInfo.isIndirect) {
5053 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5057 // The return value of the call is this value. As such, there is no
5058 // corresponding argument.
5059 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5060 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5061 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5063 assert(ResNo == 0 && "Asm only has one result!");
5064 OpVT = TLI.getValueType(CS.getType());
5068 case InlineAsm::isInput:
5069 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5071 case InlineAsm::isClobber:
5076 // If this is an input or an indirect output, process the call argument.
5077 // BasicBlocks are labels, currently appearing only in asm's.
5078 if (OpInfo.CallOperandVal) {
5079 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5080 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5082 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5085 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5088 OpInfo.ConstraintVT = OpVT;
5091 // Second pass over the constraints: compute which constraint option to use
5092 // and assign registers to constraints that want a specific physreg.
5093 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5094 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5096 // If this is an output operand with a matching input operand, look up the
5097 // matching input. If their types mismatch, e.g. one is an integer, the
5098 // other is floating point, or their sizes are different, flag it as an
5100 if (OpInfo.hasMatchingInput()) {
5101 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5102 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5103 if ((OpInfo.ConstraintVT.isInteger() !=
5104 Input.ConstraintVT.isInteger()) ||
5105 (OpInfo.ConstraintVT.getSizeInBits() !=
5106 Input.ConstraintVT.getSizeInBits())) {
5107 cerr << "Unsupported asm: input constraint with a matching output "
5108 << "constraint of incompatible type!\n";
5111 Input.ConstraintVT = OpInfo.ConstraintVT;
5115 // Compute the constraint code and ConstraintType to use.
5116 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5118 // If this is a memory input, and if the operand is not indirect, do what we
5119 // need to to provide an address for the memory input.
5120 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5121 !OpInfo.isIndirect) {
5122 assert(OpInfo.Type == InlineAsm::isInput &&
5123 "Can only indirectify direct input operands!");
5125 // Memory operands really want the address of the value. If we don't have
5126 // an indirect input, put it in the constpool if we can, otherwise spill
5127 // it to a stack slot.
5129 // If the operand is a float, integer, or vector constant, spill to a
5130 // constant pool entry to get its address.
5131 Value *OpVal = OpInfo.CallOperandVal;
5132 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5133 isa<ConstantVector>(OpVal)) {
5134 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5135 TLI.getPointerTy());
5137 // Otherwise, create a stack slot and emit a store to it before the
5139 const Type *Ty = OpVal->getType();
5140 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5141 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5142 MachineFunction &MF = DAG.getMachineFunction();
5143 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5144 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5145 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5146 OpInfo.CallOperand, StackSlot, NULL, 0);
5147 OpInfo.CallOperand = StackSlot;
5150 // There is no longer a Value* corresponding to this operand.
5151 OpInfo.CallOperandVal = 0;
5152 // It is now an indirect operand.
5153 OpInfo.isIndirect = true;
5156 // If this constraint is for a specific register, allocate it before
5158 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5159 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5161 ConstraintInfos.clear();
5164 // Second pass - Loop over all of the operands, assigning virtual or physregs
5165 // to register class operands.
5166 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5167 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5169 // C_Register operands have already been allocated, Other/Memory don't need
5171 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5172 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5175 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5176 std::vector<SDValue> AsmNodeOperands;
5177 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5178 AsmNodeOperands.push_back(
5179 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5182 // Loop over all of the inputs, copying the operand values into the
5183 // appropriate registers and processing the output regs.
5184 RegsForValue RetValRegs;
5186 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5187 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5189 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5190 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5192 switch (OpInfo.Type) {
5193 case InlineAsm::isOutput: {
5194 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5195 OpInfo.ConstraintType != TargetLowering::C_Register) {
5196 // Memory output, or 'other' output (e.g. 'X' constraint).
5197 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5199 // Add information to the INLINEASM node to know about this output.
5200 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5201 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5202 TLI.getPointerTy()));
5203 AsmNodeOperands.push_back(OpInfo.CallOperand);
5207 // Otherwise, this is a register or register class output.
5209 // Copy the output from the appropriate register. Find a register that
5211 if (OpInfo.AssignedRegs.Regs.empty()) {
5212 cerr << "Couldn't allocate output reg for constraint '"
5213 << OpInfo.ConstraintCode << "'!\n";
5217 // If this is an indirect operand, store through the pointer after the
5219 if (OpInfo.isIndirect) {
5220 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5221 OpInfo.CallOperandVal));
5223 // This is the result value of the call.
5224 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5225 // Concatenate this output onto the outputs list.
5226 RetValRegs.append(OpInfo.AssignedRegs);
5229 // Add information to the INLINEASM node to know that this register is
5231 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5232 6 /* EARLYCLOBBER REGDEF */ :
5234 DAG, AsmNodeOperands);
5237 case InlineAsm::isInput: {
5238 SDValue InOperandVal = OpInfo.CallOperand;
5240 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5241 // If this is required to match an output register we have already set,
5242 // just use its register.
5243 unsigned OperandNo = OpInfo.getMatchedOperand();
5245 // Scan until we find the definition we already emitted of this operand.
5246 // When we find it, create a RegsForValue operand.
5247 unsigned CurOp = 2; // The first operand.
5248 for (; OperandNo; --OperandNo) {
5249 // Advance to the next operand.
5251 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5252 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
5253 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5254 (NumOps & 7) == 4 /*MEM*/) &&
5255 "Skipped past definitions?");
5256 CurOp += (NumOps>>3)+1;
5260 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5261 if ((NumOps & 7) == 2 /*REGDEF*/
5262 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5263 // Add NumOps>>3 registers to MatchedRegs.
5264 RegsForValue MatchedRegs;
5265 MatchedRegs.TLI = &TLI;
5266 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5267 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5268 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5270 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5271 MatchedRegs.Regs.push_back(Reg);
5274 // Use the produced MatchedRegs object to
5275 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5277 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
5280 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
5281 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
5282 // Add information to the INLINEASM node to know about this input.
5283 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
5284 TLI.getPointerTy()));
5285 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5290 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5291 assert(!OpInfo.isIndirect &&
5292 "Don't know how to handle indirect other inputs yet!");
5294 std::vector<SDValue> Ops;
5295 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5296 hasMemory, Ops, DAG);
5298 cerr << "Invalid operand for inline asm constraint '"
5299 << OpInfo.ConstraintCode << "'!\n";
5303 // Add information to the INLINEASM node to know about this input.
5304 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5305 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5306 TLI.getPointerTy()));
5307 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5309 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5310 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5311 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5312 "Memory operands expect pointer values");
5314 // Add information to the INLINEASM node to know about this input.
5315 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5316 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5317 TLI.getPointerTy()));
5318 AsmNodeOperands.push_back(InOperandVal);
5322 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5323 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5324 "Unknown constraint type!");
5325 assert(!OpInfo.isIndirect &&
5326 "Don't know how to handle indirect register inputs yet!");
5328 // Copy the input into the appropriate registers.
5329 if (OpInfo.AssignedRegs.Regs.empty()) {
5330 cerr << "Couldn't allocate output reg for constraint '"
5331 << OpInfo.ConstraintCode << "'!\n";
5335 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5338 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5339 DAG, AsmNodeOperands);
5342 case InlineAsm::isClobber: {
5343 // Add the clobbered value to the operand list, so that the register
5344 // allocator is aware that the physreg got clobbered.
5345 if (!OpInfo.AssignedRegs.Regs.empty())
5346 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5347 DAG, AsmNodeOperands);
5353 // Finish up input operands.
5354 AsmNodeOperands[0] = Chain;
5355 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5357 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5358 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5359 &AsmNodeOperands[0], AsmNodeOperands.size());
5360 Flag = Chain.getValue(1);
5362 // If this asm returns a register value, copy the result from that register
5363 // and set it as the value of the call.
5364 if (!RetValRegs.Regs.empty()) {
5365 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5368 // FIXME: Why don't we do this for inline asms with MRVs?
5369 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5370 MVT ResultType = TLI.getValueType(CS.getType());
5372 // If any of the results of the inline asm is a vector, it may have the
5373 // wrong width/num elts. This can happen for register classes that can
5374 // contain multiple different value types. The preg or vreg allocated may
5375 // not have the same VT as was expected. Convert it to the right type
5376 // with bit_convert.
5377 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5378 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5381 } else if (ResultType != Val.getValueType() &&
5382 ResultType.isInteger() && Val.getValueType().isInteger()) {
5383 // If a result value was tied to an input value, the computed result may
5384 // have a wider width than the expected result. Extract the relevant
5386 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5389 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5392 setValue(CS.getInstruction(), Val);
5395 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5397 // Process indirect outputs, first output all of the flagged copies out of
5399 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5400 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5401 Value *Ptr = IndirectStoresToEmit[i].second;
5402 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5404 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5407 // Emit the non-flagged stores from the physregs.
5408 SmallVector<SDValue, 8> OutChains;
5409 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5410 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5411 StoresToEmit[i].first,
5412 getValue(StoresToEmit[i].second),
5413 StoresToEmit[i].second, 0));
5414 if (!OutChains.empty())
5415 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5416 &OutChains[0], OutChains.size());
5421 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5422 SDValue Src = getValue(I.getOperand(0));
5424 MVT IntPtr = TLI.getPointerTy();
5426 if (IntPtr.bitsLT(Src.getValueType()))
5427 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5428 else if (IntPtr.bitsGT(Src.getValueType()))
5429 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5431 // Scale the source by the type size.
5432 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5433 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5434 Src, DAG.getIntPtrConstant(ElementSize));
5436 TargetLowering::ArgListTy Args;
5437 TargetLowering::ArgListEntry Entry;
5439 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5440 Args.push_back(Entry);
5442 std::pair<SDValue,SDValue> Result =
5443 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5444 CallingConv::C, PerformTailCallOpt,
5445 DAG.getExternalSymbol("malloc", IntPtr),
5446 Args, DAG, getCurDebugLoc());
5447 setValue(&I, Result.first); // Pointers always fit in registers
5448 DAG.setRoot(Result.second);
5451 void SelectionDAGLowering::visitFree(FreeInst &I) {
5452 TargetLowering::ArgListTy Args;
5453 TargetLowering::ArgListEntry Entry;
5454 Entry.Node = getValue(I.getOperand(0));
5455 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5456 Args.push_back(Entry);
5457 MVT IntPtr = TLI.getPointerTy();
5458 std::pair<SDValue,SDValue> Result =
5459 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5460 CallingConv::C, PerformTailCallOpt,
5461 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5463 DAG.setRoot(Result.second);
5466 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5467 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5468 MVT::Other, getRoot(),
5469 getValue(I.getOperand(1)),
5470 DAG.getSrcValue(I.getOperand(1))));
5473 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5474 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5475 getRoot(), getValue(I.getOperand(0)),
5476 DAG.getSrcValue(I.getOperand(0)));
5478 DAG.setRoot(V.getValue(1));
5481 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5482 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5483 MVT::Other, getRoot(),
5484 getValue(I.getOperand(1)),
5485 DAG.getSrcValue(I.getOperand(1))));
5488 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5489 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5490 MVT::Other, getRoot(),
5491 getValue(I.getOperand(1)),
5492 getValue(I.getOperand(2)),
5493 DAG.getSrcValue(I.getOperand(1)),
5494 DAG.getSrcValue(I.getOperand(2))));
5497 /// TargetLowering::LowerArguments - This is the default LowerArguments
5498 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5499 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5500 /// integrated into SDISel.
5501 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5502 SmallVectorImpl<SDValue> &ArgValues,
5504 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5505 SmallVector<SDValue, 3+16> Ops;
5506 Ops.push_back(DAG.getRoot());
5507 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5508 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5510 // Add one result value for each formal argument.
5511 SmallVector<MVT, 16> RetVals;
5513 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5515 SmallVector<MVT, 4> ValueVTs;
5516 ComputeValueVTs(*this, I->getType(), ValueVTs);
5517 for (unsigned Value = 0, NumValues = ValueVTs.size();
5518 Value != NumValues; ++Value) {
5519 MVT VT = ValueVTs[Value];
5520 const Type *ArgTy = VT.getTypeForMVT();
5521 ISD::ArgFlagsTy Flags;
5522 unsigned OriginalAlignment =
5523 getTargetData()->getABITypeAlignment(ArgTy);
5525 if (F.paramHasAttr(j, Attribute::ZExt))
5527 if (F.paramHasAttr(j, Attribute::SExt))
5529 if (F.paramHasAttr(j, Attribute::InReg))
5531 if (F.paramHasAttr(j, Attribute::StructRet))
5533 if (F.paramHasAttr(j, Attribute::ByVal)) {
5535 const PointerType *Ty = cast<PointerType>(I->getType());
5536 const Type *ElementTy = Ty->getElementType();
5537 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5538 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5539 // For ByVal, alignment should be passed from FE. BE will guess if
5540 // this info is not there but there are cases it cannot get right.
5541 if (F.getParamAlignment(j))
5542 FrameAlign = F.getParamAlignment(j);
5543 Flags.setByValAlign(FrameAlign);
5544 Flags.setByValSize(FrameSize);
5546 if (F.paramHasAttr(j, Attribute::Nest))
5548 Flags.setOrigAlign(OriginalAlignment);
5550 MVT RegisterVT = getRegisterType(VT);
5551 unsigned NumRegs = getNumRegisters(VT);
5552 for (unsigned i = 0; i != NumRegs; ++i) {
5553 RetVals.push_back(RegisterVT);
5554 ISD::ArgFlagsTy MyFlags = Flags;
5555 if (NumRegs > 1 && i == 0)
5557 // if it isn't first piece, alignment must be 1
5559 MyFlags.setOrigAlign(1);
5560 Ops.push_back(DAG.getArgFlags(MyFlags));
5565 RetVals.push_back(MVT::Other);
5568 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5569 DAG.getVTList(&RetVals[0], RetVals.size()),
5570 &Ops[0], Ops.size()).getNode();
5572 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5573 // allows exposing the loads that may be part of the argument access to the
5574 // first DAGCombiner pass.
5575 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5577 // The number of results should match up, except that the lowered one may have
5578 // an extra flag result.
5579 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5580 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5581 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5582 && "Lowering produced unexpected number of results!");
5584 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5585 if (Result != TmpRes.getNode() && Result->use_empty()) {
5586 HandleSDNode Dummy(DAG.getRoot());
5587 DAG.RemoveDeadNode(Result);
5590 Result = TmpRes.getNode();
5592 unsigned NumArgRegs = Result->getNumValues() - 1;
5593 DAG.setRoot(SDValue(Result, NumArgRegs));
5595 // Set up the return result vector.
5598 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5600 SmallVector<MVT, 4> ValueVTs;
5601 ComputeValueVTs(*this, I->getType(), ValueVTs);
5602 for (unsigned Value = 0, NumValues = ValueVTs.size();
5603 Value != NumValues; ++Value) {
5604 MVT VT = ValueVTs[Value];
5605 MVT PartVT = getRegisterType(VT);
5607 unsigned NumParts = getNumRegisters(VT);
5608 SmallVector<SDValue, 4> Parts(NumParts);
5609 for (unsigned j = 0; j != NumParts; ++j)
5610 Parts[j] = SDValue(Result, i++);
5612 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5613 if (F.paramHasAttr(Idx, Attribute::SExt))
5614 AssertOp = ISD::AssertSext;
5615 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5616 AssertOp = ISD::AssertZext;
5618 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5619 PartVT, VT, AssertOp));
5622 assert(i == NumArgRegs && "Argument register count mismatch!");
5626 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5627 /// implementation, which just inserts an ISD::CALL node, which is later custom
5628 /// lowered by the target to something concrete. FIXME: When all targets are
5629 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5630 std::pair<SDValue, SDValue>
5631 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5632 bool RetSExt, bool RetZExt, bool isVarArg,
5634 unsigned CallingConv, bool isTailCall,
5636 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5637 assert((!isTailCall || PerformTailCallOpt) &&
5638 "isTailCall set when tail-call optimizations are disabled!");
5640 SmallVector<SDValue, 32> Ops;
5641 Ops.push_back(Chain); // Op#0 - Chain
5642 Ops.push_back(Callee);
5644 // Handle all of the outgoing arguments.
5645 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5646 SmallVector<MVT, 4> ValueVTs;
5647 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5648 for (unsigned Value = 0, NumValues = ValueVTs.size();
5649 Value != NumValues; ++Value) {
5650 MVT VT = ValueVTs[Value];
5651 const Type *ArgTy = VT.getTypeForMVT();
5652 SDValue Op = SDValue(Args[i].Node.getNode(),
5653 Args[i].Node.getResNo() + Value);
5654 ISD::ArgFlagsTy Flags;
5655 unsigned OriginalAlignment =
5656 getTargetData()->getABITypeAlignment(ArgTy);
5662 if (Args[i].isInReg)
5666 if (Args[i].isByVal) {
5668 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5669 const Type *ElementTy = Ty->getElementType();
5670 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5671 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5672 // For ByVal, alignment should come from FE. BE will guess if this
5673 // info is not there but there are cases it cannot get right.
5674 if (Args[i].Alignment)
5675 FrameAlign = Args[i].Alignment;
5676 Flags.setByValAlign(FrameAlign);
5677 Flags.setByValSize(FrameSize);
5681 Flags.setOrigAlign(OriginalAlignment);
5683 MVT PartVT = getRegisterType(VT);
5684 unsigned NumParts = getNumRegisters(VT);
5685 SmallVector<SDValue, 4> Parts(NumParts);
5686 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5689 ExtendKind = ISD::SIGN_EXTEND;
5690 else if (Args[i].isZExt)
5691 ExtendKind = ISD::ZERO_EXTEND;
5693 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5695 for (unsigned i = 0; i != NumParts; ++i) {
5696 // if it isn't first piece, alignment must be 1
5697 ISD::ArgFlagsTy MyFlags = Flags;
5698 if (NumParts > 1 && i == 0)
5701 MyFlags.setOrigAlign(1);
5703 Ops.push_back(Parts[i]);
5704 Ops.push_back(DAG.getArgFlags(MyFlags));
5709 // Figure out the result value types. We start by making a list of
5710 // the potentially illegal return value types.
5711 SmallVector<MVT, 4> LoweredRetTys;
5712 SmallVector<MVT, 4> RetTys;
5713 ComputeValueVTs(*this, RetTy, RetTys);
5715 // Then we translate that to a list of legal types.
5716 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5718 MVT RegisterVT = getRegisterType(VT);
5719 unsigned NumRegs = getNumRegisters(VT);
5720 for (unsigned i = 0; i != NumRegs; ++i)
5721 LoweredRetTys.push_back(RegisterVT);
5724 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5726 // Create the CALL node.
5727 SDValue Res = DAG.getCall(CallingConv, dl,
5728 isVarArg, isTailCall, isInreg,
5729 DAG.getVTList(&LoweredRetTys[0],
5730 LoweredRetTys.size()),
5733 Chain = Res.getValue(LoweredRetTys.size() - 1);
5735 // Gather up the call result into a single value.
5736 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5737 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5740 AssertOp = ISD::AssertSext;
5742 AssertOp = ISD::AssertZext;
5744 SmallVector<SDValue, 4> ReturnValues;
5746 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5748 MVT RegisterVT = getRegisterType(VT);
5749 unsigned NumRegs = getNumRegisters(VT);
5750 unsigned RegNoEnd = NumRegs + RegNo;
5751 SmallVector<SDValue, 4> Results;
5752 for (; RegNo != RegNoEnd; ++RegNo)
5753 Results.push_back(Res.getValue(RegNo));
5754 SDValue ReturnValue =
5755 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5757 ReturnValues.push_back(ReturnValue);
5759 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5760 DAG.getVTList(&RetTys[0], RetTys.size()),
5761 &ReturnValues[0], ReturnValues.size());
5764 return std::make_pair(Res, Chain);
5767 void TargetLowering::LowerOperationWrapper(SDNode *N,
5768 SmallVectorImpl<SDValue> &Results,
5769 SelectionDAG &DAG) {
5770 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5772 Results.push_back(Res);
5775 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5776 assert(0 && "LowerOperation not implemented for this target!");
5782 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5783 SDValue Op = getValue(V);
5784 assert((Op.getOpcode() != ISD::CopyFromReg ||
5785 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5786 "Copy from a reg to the same reg!");
5787 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5789 RegsForValue RFV(TLI, Reg, V->getType());
5790 SDValue Chain = DAG.getEntryNode();
5791 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5792 PendingExports.push_back(Chain);
5795 #include "llvm/CodeGen/SelectionDAGISel.h"
5797 void SelectionDAGISel::
5798 LowerArguments(BasicBlock *LLVMBB) {
5799 // If this is the entry block, emit arguments.
5800 Function &F = *LLVMBB->getParent();
5801 SDValue OldRoot = SDL->DAG.getRoot();
5802 SmallVector<SDValue, 16> Args;
5803 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5806 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5808 SmallVector<MVT, 4> ValueVTs;
5809 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5810 unsigned NumValues = ValueVTs.size();
5811 if (!AI->use_empty()) {
5812 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5813 SDL->getCurDebugLoc()));
5814 // If this argument is live outside of the entry block, insert a copy from
5815 // whereever we got it to the vreg that other BB's will reference it as.
5816 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5817 if (VMI != FuncInfo->ValueMap.end()) {
5818 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5824 // Finally, if the target has anything special to do, allow it to do so.
5825 // FIXME: this should insert code into the DAG!
5826 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5829 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5830 /// ensure constants are generated when needed. Remember the virtual registers
5831 /// that need to be added to the Machine PHI nodes as input. We cannot just
5832 /// directly add them, because expansion might result in multiple MBB's for one
5833 /// BB. As such, the start of the BB might correspond to a different MBB than
5837 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5838 TerminatorInst *TI = LLVMBB->getTerminator();
5840 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5842 // Check successor nodes' PHI nodes that expect a constant to be available
5844 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5845 BasicBlock *SuccBB = TI->getSuccessor(succ);
5846 if (!isa<PHINode>(SuccBB->begin())) continue;
5847 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5849 // If this terminator has multiple identical successors (common for
5850 // switches), only handle each succ once.
5851 if (!SuccsHandled.insert(SuccMBB)) continue;
5853 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5856 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5857 // nodes and Machine PHI nodes, but the incoming operands have not been
5859 for (BasicBlock::iterator I = SuccBB->begin();
5860 (PN = dyn_cast<PHINode>(I)); ++I) {
5861 // Ignore dead phi's.
5862 if (PN->use_empty()) continue;
5865 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5867 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5868 unsigned &RegOut = SDL->ConstantsOut[C];
5870 RegOut = FuncInfo->CreateRegForValue(C);
5871 SDL->CopyValueToVirtualRegister(C, RegOut);
5875 Reg = FuncInfo->ValueMap[PHIOp];
5877 assert(isa<AllocaInst>(PHIOp) &&
5878 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5879 "Didn't codegen value into a register!??");
5880 Reg = FuncInfo->CreateRegForValue(PHIOp);
5881 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5885 // Remember that this register needs to added to the machine PHI node as
5886 // the input for this MBB.
5887 SmallVector<MVT, 4> ValueVTs;
5888 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5889 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5890 MVT VT = ValueVTs[vti];
5891 unsigned NumRegisters = TLI.getNumRegisters(VT);
5892 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5893 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5894 Reg += NumRegisters;
5898 SDL->ConstantsOut.clear();
5901 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5902 /// supports legal types, and it emits MachineInstrs directly instead of
5903 /// creating SelectionDAG nodes.
5906 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5908 TerminatorInst *TI = LLVMBB->getTerminator();
5910 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5911 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5913 // Check successor nodes' PHI nodes that expect a constant to be available
5915 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5916 BasicBlock *SuccBB = TI->getSuccessor(succ);
5917 if (!isa<PHINode>(SuccBB->begin())) continue;
5918 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5920 // If this terminator has multiple identical successors (common for
5921 // switches), only handle each succ once.
5922 if (!SuccsHandled.insert(SuccMBB)) continue;
5924 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5927 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5928 // nodes and Machine PHI nodes, but the incoming operands have not been
5930 for (BasicBlock::iterator I = SuccBB->begin();
5931 (PN = dyn_cast<PHINode>(I)); ++I) {
5932 // Ignore dead phi's.
5933 if (PN->use_empty()) continue;
5935 // Only handle legal types. Two interesting things to note here. First,
5936 // by bailing out early, we may leave behind some dead instructions,
5937 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5938 // own moves. Second, this check is necessary becuase FastISel doesn't
5939 // use CreateRegForValue to create registers, so it always creates
5940 // exactly one register for each non-void instruction.
5941 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5942 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5945 VT = TLI.getTypeToTransformTo(VT);
5947 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5952 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5954 unsigned Reg = F->getRegForValue(PHIOp);
5956 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5959 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));