1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Interpret void as zero return values.
139 if (Ty == Type::VoidTy)
141 // Base case: we can get an MVT for this LLVM IR type.
142 ValueVTs.push_back(TLI.getValueType(Ty));
144 Offsets->push_back(StartingOffset);
148 /// RegsForValue - This struct represents the registers (physical or virtual)
149 /// that a particular set of values is assigned, and the type information about
150 /// the value. The most common situation is to represent one value at a time,
151 /// but struct or array values are handled element-wise as multiple values.
152 /// The splitting of aggregates is performed recursively, so that we never
153 /// have aggregate-typed registers. The values at this point do not necessarily
154 /// have legal types, so each value may require one or more registers of some
157 struct VISIBILITY_HIDDEN RegsForValue {
158 /// TLI - The TargetLowering object.
160 const TargetLowering *TLI;
162 /// ValueVTs - The value types of the values, which may not be legal, and
163 /// may need be promoted or synthesized from one or more registers.
165 SmallVector<MVT, 4> ValueVTs;
167 /// RegVTs - The value types of the registers. This is the same size as
168 /// ValueVTs and it records, for each value, what the type of the assigned
169 /// register or registers are. (Individual values are never synthesized
170 /// from more than one type of register.)
172 /// With virtual registers, the contents of RegVTs is redundant with TLI's
173 /// getRegisterType member function, however when with physical registers
174 /// it is necessary to have a separate record of the types.
176 SmallVector<MVT, 4> RegVTs;
178 /// Regs - This list holds the registers assigned to the values.
179 /// Each legal or promoted value requires one register, and each
180 /// expanded value requires multiple registers.
182 SmallVector<unsigned, 4> Regs;
184 RegsForValue() : TLI(0) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 MVT regvt, MVT valuevt)
189 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
190 RegsForValue(const TargetLowering &tli,
191 const SmallVector<unsigned, 4> ®s,
192 const SmallVector<MVT, 4> ®vts,
193 const SmallVector<MVT, 4> &valuevts)
194 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
195 RegsForValue(const TargetLowering &tli,
196 unsigned Reg, const Type *Ty) : TLI(&tli) {
197 ComputeValueVTs(tli, Ty, ValueVTs);
199 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
200 MVT ValueVT = ValueVTs[Value];
201 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
202 MVT RegisterVT = TLI->getRegisterType(ValueVT);
203 for (unsigned i = 0; i != NumRegs; ++i)
204 Regs.push_back(Reg + i);
205 RegVTs.push_back(RegisterVT);
210 /// append - Add the specified values to this one.
211 void append(const RegsForValue &RHS) {
213 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
214 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
215 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
219 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
220 /// this value and returns the result as a ValueVTs value. This uses
221 /// Chain/Flag as the input and updates them for the output Chain/Flag.
222 /// If the Flag pointer is NULL, no flag is used.
223 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
224 SDValue &Chain, SDValue *Flag) const;
226 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
227 /// specified value into the registers specified by this object. This uses
228 /// Chain/Flag as the input and updates them for the output Chain/Flag.
229 /// If the Flag pointer is NULL, no flag is used.
230 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
231 SDValue &Chain, SDValue *Flag) const;
233 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
234 /// operand list. This adds the code marker, matching input operand index
235 /// (if applicable), and includes the number of values added into it.
236 void AddInlineAsmOperands(unsigned Code,
237 bool HasMatching, unsigned MatchingIdx,
238 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
242 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
243 /// PHI nodes or outside of the basic block that defines it, or used by a
244 /// switch or atomic instruction, which may expand to multiple basic blocks.
245 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
246 if (isa<PHINode>(I)) return true;
247 BasicBlock *BB = I->getParent();
248 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
249 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
254 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
255 /// entry block, return true. This includes arguments used by switches, since
256 /// the switch may expand into multiple basic blocks.
257 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
258 // With FastISel active, we may be splitting blocks, so force creation
259 // of virtual registers for all non-dead arguments.
260 // Don't force virtual registers for byval arguments though, because
261 // fast-isel can't handle those in all cases.
262 if (EnableFastISel && !A->hasByValAttr())
263 return A->use_empty();
265 BasicBlock *Entry = A->getParent()->begin();
266 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
267 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
268 return false; // Use not in entry block.
272 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
276 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 bool EnableFastISel) {
281 RegInfo = &MF->getRegInfo();
283 // Create a vreg for each argument register that is not dead and is used
284 // outside of the entry block for the function.
285 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
288 InitializeRegForValue(AI);
290 // Initialize the mapping of values to registers. This is only set up for
291 // instruction values that are used outside of the block that defines
293 Function::iterator BB = Fn->begin(), EB = Fn->end();
294 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
295 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
296 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
297 const Type *Ty = AI->getAllocatedType();
298 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
300 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
303 TySize *= CUI->getZExtValue(); // Get total allocated size.
304 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
305 StaticAllocaMap[AI] =
306 MF->getFrameInfo()->CreateStackObject(TySize, Align);
309 for (; BB != EB; ++BB)
310 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
311 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
312 if (!isa<AllocaInst>(I) ||
313 !StaticAllocaMap.count(cast<AllocaInst>(I)))
314 InitializeRegForValue(I);
316 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
317 // also creates the initial PHI MachineInstrs, though none of the input
318 // operands are populated.
319 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
320 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
324 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
328 for (BasicBlock::iterator
329 I = BB->begin(), E = BB->end(); I != E; ++I) {
330 if (CallInst *CI = dyn_cast<CallInst>(I)) {
331 if (Function *F = CI->getCalledFunction()) {
332 switch (F->getIntrinsicID()) {
334 case Intrinsic::dbg_stoppoint: {
335 DwarfWriter *DW = DAG.getDwarfWriter();
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
338 if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
339 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
341 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
343 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
346 DL = DebugLoc::get(idx);
351 case Intrinsic::dbg_func_start: {
352 DwarfWriter *DW = DAG.getDwarfWriter();
354 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
355 Value *SP = FSI->getSubprogram();
357 if (DW->ValidDebugInfo(SP, false)) {
358 DISubprogram Subprogram(cast<GlobalVariable>(SP));
359 DICompileUnit CU(Subprogram.getCompileUnit());
361 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
363 unsigned Line = Subprogram.getLineNumber();
364 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
374 PN = dyn_cast<PHINode>(I);
375 if (!PN || PN->use_empty()) continue;
377 unsigned PHIReg = ValueMap[PN];
378 assert(PHIReg && "PHI node does not have an assigned virtual register!");
380 SmallVector<MVT, 4> ValueVTs;
381 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
382 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
383 MVT VT = ValueVTs[vti];
384 unsigned NumRegisters = TLI.getNumRegisters(VT);
385 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
386 for (unsigned i = 0; i != NumRegisters; ++i)
387 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
388 PHIReg += NumRegisters;
394 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
395 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
398 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
399 /// the correctly promoted or expanded types. Assign these registers
400 /// consecutive vreg numbers and return the first assigned number.
402 /// In the case that the given value has struct or array type, this function
403 /// will assign registers for each member or element.
405 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
406 SmallVector<MVT, 4> ValueVTs;
407 ComputeValueVTs(TLI, V->getType(), ValueVTs);
409 unsigned FirstReg = 0;
410 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
411 MVT ValueVT = ValueVTs[Value];
412 MVT RegisterVT = TLI.getRegisterType(ValueVT);
414 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
415 for (unsigned i = 0; i != NumRegs; ++i) {
416 unsigned R = MakeReg(RegisterVT);
417 if (!FirstReg) FirstReg = R;
423 /// getCopyFromParts - Create a value that contains the specified legal parts
424 /// combined into the value they represent. If the parts combine to a type
425 /// larger then ValueVT then AssertOp can be used to specify whether the extra
426 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
427 /// (ISD::AssertSext).
428 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
429 const SDValue *Parts,
430 unsigned NumParts, MVT PartVT, MVT ValueVT,
431 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
432 assert(NumParts > 0 && "No parts to assemble!");
433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
434 SDValue Val = Parts[0];
437 // Assemble the value from multiple parts.
438 if (!ValueVT.isVector()) {
439 unsigned PartBits = PartVT.getSizeInBits();
440 unsigned ValueBits = ValueVT.getSizeInBits();
442 // Assemble the power of 2 part.
443 unsigned RoundParts = NumParts & (NumParts - 1) ?
444 1 << Log2_32(NumParts) : NumParts;
445 unsigned RoundBits = PartBits * RoundParts;
446 MVT RoundVT = RoundBits == ValueBits ?
447 ValueVT : MVT::getIntegerVT(RoundBits);
450 MVT HalfVT = ValueVT.isInteger() ?
451 MVT::getIntegerVT(RoundBits/2) :
452 MVT::getFloatingPointVT(RoundBits/2);
454 if (RoundParts > 2) {
455 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
456 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
459 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
460 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
462 if (TLI.isBigEndian())
464 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
466 if (RoundParts < NumParts) {
467 // Assemble the trailing non-power-of-2 part.
468 unsigned OddParts = NumParts - RoundParts;
469 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
470 Hi = getCopyFromParts(DAG, dl,
471 Parts+RoundParts, OddParts, PartVT, OddVT);
473 // Combine the round and odd parts.
475 if (TLI.isBigEndian())
477 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
478 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
479 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
480 DAG.getConstant(Lo.getValueType().getSizeInBits(),
481 TLI.getPointerTy()));
482 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
483 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
486 // Handle a multi-element vector.
487 MVT IntermediateVT, RegisterVT;
488 unsigned NumIntermediates;
490 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
492 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
493 NumParts = NumRegs; // Silence a compiler warning.
494 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
495 assert(RegisterVT == Parts[0].getValueType() &&
496 "Part type doesn't match part!");
498 // Assemble the parts into intermediate operands.
499 SmallVector<SDValue, 8> Ops(NumIntermediates);
500 if (NumIntermediates == NumParts) {
501 // If the register was not expanded, truncate or copy the value,
503 for (unsigned i = 0; i != NumParts; ++i)
504 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
505 PartVT, IntermediateVT);
506 } else if (NumParts > 0) {
507 // If the intermediate type was expanded, build the intermediate operands
509 assert(NumParts % NumIntermediates == 0 &&
510 "Must expand into a divisible number of parts!");
511 unsigned Factor = NumParts / NumIntermediates;
512 for (unsigned i = 0; i != NumIntermediates; ++i)
513 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
514 PartVT, IntermediateVT);
517 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
519 Val = DAG.getNode(IntermediateVT.isVector() ?
520 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
521 ValueVT, &Ops[0], NumIntermediates);
525 // There is now one part, held in Val. Correct it to match ValueVT.
526 PartVT = Val.getValueType();
528 if (PartVT == ValueVT)
531 if (PartVT.isVector()) {
532 assert(ValueVT.isVector() && "Unknown vector conversion!");
533 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
536 if (ValueVT.isVector()) {
537 assert(ValueVT.getVectorElementType() == PartVT &&
538 ValueVT.getVectorNumElements() == 1 &&
539 "Only trivial scalar-to-vector conversions should get here!");
540 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
543 if (PartVT.isInteger() &&
544 ValueVT.isInteger()) {
545 if (ValueVT.bitsLT(PartVT)) {
546 // For a truncate, see if we have any information to
547 // indicate whether the truncated bits will always be
548 // zero or sign-extension.
549 if (AssertOp != ISD::DELETED_NODE)
550 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
551 DAG.getValueType(ValueVT));
552 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
554 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
558 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
559 if (ValueVT.bitsLT(Val.getValueType()))
560 // FP_ROUND's are always exact here.
561 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
562 DAG.getIntPtrConstant(1));
563 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
566 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
567 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
569 assert(0 && "Unknown mismatch!");
573 /// getCopyToParts - Create a series of nodes that contain the specified value
574 /// split into legal parts. If the parts contain more bits than Val, then, for
575 /// integers, ExtendKind can be used to specify how to generate the extra bits.
576 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
577 SDValue *Parts, unsigned NumParts, MVT PartVT,
578 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
580 MVT PtrVT = TLI.getPointerTy();
581 MVT ValueVT = Val.getValueType();
582 unsigned PartBits = PartVT.getSizeInBits();
583 unsigned OrigNumParts = NumParts;
584 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
589 if (!ValueVT.isVector()) {
590 if (PartVT == ValueVT) {
591 assert(NumParts == 1 && "No-op copy with multiple parts!");
596 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
597 // If the parts cover more bits than the value has, promote the value.
598 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
599 assert(NumParts == 1 && "Do not know what to promote to!");
600 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
601 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
602 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
603 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
605 assert(0 && "Unknown mismatch!");
607 } else if (PartBits == ValueVT.getSizeInBits()) {
608 // Different types of the same size.
609 assert(NumParts == 1 && PartVT != ValueVT);
610 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
611 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
612 // If the parts cover less bits than value has, truncate the value.
613 if (PartVT.isInteger() && ValueVT.isInteger()) {
614 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
615 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
617 assert(0 && "Unknown mismatch!");
621 // The value may have changed - recompute ValueVT.
622 ValueVT = Val.getValueType();
623 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
624 "Failed to tile the value with PartVT!");
627 assert(PartVT == ValueVT && "Type conversion failed!");
632 // Expand the value into multiple parts.
633 if (NumParts & (NumParts - 1)) {
634 // The number of parts is not a power of 2. Split off and copy the tail.
635 assert(PartVT.isInteger() && ValueVT.isInteger() &&
636 "Do not know what to expand to!");
637 unsigned RoundParts = 1 << Log2_32(NumParts);
638 unsigned RoundBits = RoundParts * PartBits;
639 unsigned OddParts = NumParts - RoundParts;
640 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
641 DAG.getConstant(RoundBits,
642 TLI.getPointerTy()));
643 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
644 if (TLI.isBigEndian())
645 // The odd parts were reversed by getCopyToParts - unreverse them.
646 std::reverse(Parts + RoundParts, Parts + NumParts);
647 NumParts = RoundParts;
648 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
649 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
652 // The number of parts is a power of 2. Repeatedly bisect the value using
654 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
655 MVT::getIntegerVT(ValueVT.getSizeInBits()),
657 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
658 for (unsigned i = 0; i < NumParts; i += StepSize) {
659 unsigned ThisBits = StepSize * PartBits / 2;
660 MVT ThisVT = MVT::getIntegerVT (ThisBits);
661 SDValue &Part0 = Parts[i];
662 SDValue &Part1 = Parts[i+StepSize/2];
664 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
666 DAG.getConstant(1, PtrVT));
667 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
669 DAG.getConstant(0, PtrVT));
671 if (ThisBits == PartBits && ThisVT != PartVT) {
672 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
680 if (TLI.isBigEndian())
681 std::reverse(Parts, Parts + OrigNumParts);
688 if (PartVT != ValueVT) {
689 if (PartVT.isVector()) {
690 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
692 assert(ValueVT.getVectorElementType() == PartVT &&
693 ValueVT.getVectorNumElements() == 1 &&
694 "Only trivial vector-to-scalar conversions should get here!");
695 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
697 DAG.getConstant(0, PtrVT));
705 // Handle a multi-element vector.
706 MVT IntermediateVT, RegisterVT;
707 unsigned NumIntermediates;
708 unsigned NumRegs = TLI
709 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
711 unsigned NumElements = ValueVT.getVectorNumElements();
713 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
714 NumParts = NumRegs; // Silence a compiler warning.
715 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
717 // Split the vector into intermediate operands.
718 SmallVector<SDValue, 8> Ops(NumIntermediates);
719 for (unsigned i = 0; i != NumIntermediates; ++i)
720 if (IntermediateVT.isVector())
721 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
723 DAG.getConstant(i * (NumElements / NumIntermediates),
726 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
728 DAG.getConstant(i, PtrVT));
730 // Split the intermediate operands into legal parts.
731 if (NumParts == NumIntermediates) {
732 // If the register was not expanded, promote or copy the value,
734 for (unsigned i = 0; i != NumParts; ++i)
735 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
736 } else if (NumParts > 0) {
737 // If the intermediate type was expanded, split each the value into
739 assert(NumParts % NumIntermediates == 0 &&
740 "Must expand into a divisible number of parts!");
741 unsigned Factor = NumParts / NumIntermediates;
742 for (unsigned i = 0; i != NumIntermediates; ++i)
743 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
748 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
751 TD = DAG.getTarget().getTargetData();
754 /// clear - Clear out the curret SelectionDAG and the associated
755 /// state and prepare this SelectionDAGLowering object to be used
756 /// for a new block. This doesn't clear out information about
757 /// additional blocks that are needed to complete switch lowering
758 /// or PHI node updating; that information is cleared out as it is
760 void SelectionDAGLowering::clear() {
762 PendingLoads.clear();
763 PendingExports.clear();
765 CurDebugLoc = DebugLoc::getUnknownLoc();
768 /// getRoot - Return the current virtual root of the Selection DAG,
769 /// flushing any PendingLoad items. This must be done before emitting
770 /// a store or any other node that may need to be ordered after any
771 /// prior load instructions.
773 SDValue SelectionDAGLowering::getRoot() {
774 if (PendingLoads.empty())
775 return DAG.getRoot();
777 if (PendingLoads.size() == 1) {
778 SDValue Root = PendingLoads[0];
780 PendingLoads.clear();
784 // Otherwise, we have to make a token factor node.
785 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
786 &PendingLoads[0], PendingLoads.size());
787 PendingLoads.clear();
792 /// getControlRoot - Similar to getRoot, but instead of flushing all the
793 /// PendingLoad items, flush all the PendingExports items. It is necessary
794 /// to do this before emitting a terminator instruction.
796 SDValue SelectionDAGLowering::getControlRoot() {
797 SDValue Root = DAG.getRoot();
799 if (PendingExports.empty())
802 // Turn all of the CopyToReg chains into one factored node.
803 if (Root.getOpcode() != ISD::EntryToken) {
804 unsigned i = 0, e = PendingExports.size();
805 for (; i != e; ++i) {
806 assert(PendingExports[i].getNode()->getNumOperands() > 1);
807 if (PendingExports[i].getNode()->getOperand(0) == Root)
808 break; // Don't add the root if we already indirectly depend on it.
812 PendingExports.push_back(Root);
815 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
817 PendingExports.size());
818 PendingExports.clear();
823 void SelectionDAGLowering::visit(Instruction &I) {
824 visit(I.getOpcode(), I);
827 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
828 // Note: this doesn't use InstVisitor, because it has to work with
829 // ConstantExpr's in addition to instructions.
831 default: assert(0 && "Unknown instruction type encountered!");
833 // Build the switch statement using the Instruction.def file.
834 #define HANDLE_INST(NUM, OPCODE, CLASS) \
835 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
836 #include "llvm/Instruction.def"
840 void SelectionDAGLowering::visitAdd(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FADD);
844 visitBinary(I, ISD::ADD);
847 void SelectionDAGLowering::visitMul(User &I) {
848 if (I.getType()->isFPOrFPVector())
849 visitBinary(I, ISD::FMUL);
851 visitBinary(I, ISD::MUL);
854 SDValue SelectionDAGLowering::getValue(const Value *V) {
855 SDValue &N = NodeMap[V];
856 if (N.getNode()) return N;
858 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
859 MVT VT = TLI.getValueType(V->getType(), true);
861 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
862 return N = DAG.getConstant(*CI, VT);
864 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
865 return N = DAG.getGlobalAddress(GV, VT);
867 if (isa<ConstantPointerNull>(C))
868 return N = DAG.getConstant(0, TLI.getPointerTy());
870 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
871 return N = DAG.getConstantFP(*CFP, VT);
873 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
874 !V->getType()->isAggregateType())
875 return N = DAG.getUNDEF(VT);
877 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
878 visit(CE->getOpcode(), *CE);
879 SDValue N1 = NodeMap[V];
880 assert(N1.getNode() && "visit didn't populate the ValueMap!");
884 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
885 SmallVector<SDValue, 4> Constants;
886 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
888 SDNode *Val = getValue(*OI).getNode();
889 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
890 Constants.push_back(SDValue(Val, i));
892 return DAG.getMergeValues(&Constants[0], Constants.size(),
896 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
897 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
898 "Unknown struct or array constant!");
900 SmallVector<MVT, 4> ValueVTs;
901 ComputeValueVTs(TLI, C->getType(), ValueVTs);
902 unsigned NumElts = ValueVTs.size();
904 return SDValue(); // empty struct
905 SmallVector<SDValue, 4> Constants(NumElts);
906 for (unsigned i = 0; i != NumElts; ++i) {
907 MVT EltVT = ValueVTs[i];
908 if (isa<UndefValue>(C))
909 Constants[i] = DAG.getUNDEF(EltVT);
910 else if (EltVT.isFloatingPoint())
911 Constants[i] = DAG.getConstantFP(0, EltVT);
913 Constants[i] = DAG.getConstant(0, EltVT);
915 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
918 const VectorType *VecTy = cast<VectorType>(V->getType());
919 unsigned NumElements = VecTy->getNumElements();
921 // Now that we know the number and type of the elements, get that number of
922 // elements into the Ops array based on what kind of constant it is.
923 SmallVector<SDValue, 16> Ops;
924 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
925 for (unsigned i = 0; i != NumElements; ++i)
926 Ops.push_back(getValue(CP->getOperand(i)));
928 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
929 "Unknown vector constant!");
930 MVT EltVT = TLI.getValueType(VecTy->getElementType());
933 if (isa<UndefValue>(C))
934 Op = DAG.getUNDEF(EltVT);
935 else if (EltVT.isFloatingPoint())
936 Op = DAG.getConstantFP(0, EltVT);
938 Op = DAG.getConstant(0, EltVT);
939 Ops.assign(NumElements, Op);
942 // Create a BUILD_VECTOR node.
943 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
944 VT, &Ops[0], Ops.size());
947 // If this is a static alloca, generate it as the frameindex instead of
949 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
950 DenseMap<const AllocaInst*, int>::iterator SI =
951 FuncInfo.StaticAllocaMap.find(AI);
952 if (SI != FuncInfo.StaticAllocaMap.end())
953 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
956 unsigned InReg = FuncInfo.ValueMap[V];
957 assert(InReg && "Value not in map!");
959 RegsForValue RFV(TLI, InReg, V->getType());
960 SDValue Chain = DAG.getEntryNode();
961 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
965 void SelectionDAGLowering::visitRet(ReturnInst &I) {
966 if (I.getNumOperands() == 0) {
967 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
968 MVT::Other, getControlRoot()));
972 SmallVector<SDValue, 8> NewValues;
973 NewValues.push_back(getControlRoot());
974 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
975 SmallVector<MVT, 4> ValueVTs;
976 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
977 unsigned NumValues = ValueVTs.size();
978 if (NumValues == 0) continue;
980 SDValue RetOp = getValue(I.getOperand(i));
981 for (unsigned j = 0, f = NumValues; j != f; ++j) {
982 MVT VT = ValueVTs[j];
984 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
986 const Function *F = I.getParent()->getParent();
987 if (F->paramHasAttr(0, Attribute::SExt))
988 ExtendKind = ISD::SIGN_EXTEND;
989 else if (F->paramHasAttr(0, Attribute::ZExt))
990 ExtendKind = ISD::ZERO_EXTEND;
992 // FIXME: C calling convention requires the return type to be promoted to
993 // at least 32-bit. But this is not necessary for non-C calling
994 // conventions. The frontend should mark functions whose return values
995 // require promoting with signext or zeroext attributes.
996 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
997 MVT MinVT = TLI.getRegisterType(MVT::i32);
998 if (VT.bitsLT(MinVT))
1002 unsigned NumParts = TLI.getNumRegisters(VT);
1003 MVT PartVT = TLI.getRegisterType(VT);
1004 SmallVector<SDValue, 4> Parts(NumParts);
1005 getCopyToParts(DAG, getCurDebugLoc(),
1006 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1007 &Parts[0], NumParts, PartVT, ExtendKind);
1009 // 'inreg' on function refers to return value
1010 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1011 if (F->paramHasAttr(0, Attribute::InReg))
1013 for (unsigned i = 0; i < NumParts; ++i) {
1014 NewValues.push_back(Parts[i]);
1015 NewValues.push_back(DAG.getArgFlags(Flags));
1019 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1020 &NewValues[0], NewValues.size()));
1023 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1024 /// created for it, emit nodes to copy the value into the virtual
1026 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1027 if (!V->use_empty()) {
1028 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1029 if (VMI != FuncInfo.ValueMap.end())
1030 CopyValueToVirtualRegister(V, VMI->second);
1034 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1035 /// the current basic block, add it to ValueMap now so that we'll get a
1037 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1038 // No need to export constants.
1039 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1041 // Already exported?
1042 if (FuncInfo.isExportedInst(V)) return;
1044 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1045 CopyValueToVirtualRegister(V, Reg);
1048 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1049 const BasicBlock *FromBB) {
1050 // The operands of the setcc have to be in this block. We don't know
1051 // how to export them from some other block.
1052 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1053 // Can export from current BB.
1054 if (VI->getParent() == FromBB)
1057 // Is already exported, noop.
1058 return FuncInfo.isExportedInst(V);
1061 // If this is an argument, we can export it if the BB is the entry block or
1062 // if it is already exported.
1063 if (isa<Argument>(V)) {
1064 if (FromBB == &FromBB->getParent()->getEntryBlock())
1067 // Otherwise, can only export this if it is already exported.
1068 return FuncInfo.isExportedInst(V);
1071 // Otherwise, constants can always be exported.
1075 static bool InBlock(const Value *V, const BasicBlock *BB) {
1076 if (const Instruction *I = dyn_cast<Instruction>(V))
1077 return I->getParent() == BB;
1081 /// getFCmpCondCode - Return the ISD condition code corresponding to
1082 /// the given LLVM IR floating-point condition code. This includes
1083 /// consideration of global floating-point math flags.
1085 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1086 ISD::CondCode FPC, FOC;
1088 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1089 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1090 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1091 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1092 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1093 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1094 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1095 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1096 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1097 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1098 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1099 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1100 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1101 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1102 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1103 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1105 assert(0 && "Invalid FCmp predicate opcode!");
1106 FOC = FPC = ISD::SETFALSE;
1109 if (FiniteOnlyFPMath())
1115 /// getICmpCondCode - Return the ISD condition code corresponding to
1116 /// the given LLVM IR integer condition code.
1118 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1120 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1121 case ICmpInst::ICMP_NE: return ISD::SETNE;
1122 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1123 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1124 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1125 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1126 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1127 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1128 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1129 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1131 assert(0 && "Invalid ICmp predicate opcode!");
1136 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1137 /// This function emits a branch and is used at the leaves of an OR or an
1138 /// AND operator tree.
1141 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1142 MachineBasicBlock *TBB,
1143 MachineBasicBlock *FBB,
1144 MachineBasicBlock *CurBB) {
1145 const BasicBlock *BB = CurBB->getBasicBlock();
1147 // If the leaf of the tree is a comparison, merge the condition into
1149 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1150 // The operands of the cmp have to be in this block. We don't know
1151 // how to export them from some other block. If this is the first block
1152 // of the sequence, no exporting is needed.
1153 if (CurBB == CurMBB ||
1154 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1155 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1156 ISD::CondCode Condition;
1157 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1158 Condition = getICmpCondCode(IC->getPredicate());
1159 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1160 Condition = getFCmpCondCode(FC->getPredicate());
1162 Condition = ISD::SETEQ; // silence warning.
1163 assert(0 && "Unknown compare instruction");
1166 CaseBlock CB(Condition, BOp->getOperand(0),
1167 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1168 SwitchCases.push_back(CB);
1173 // Create a CaseBlock record representing this branch.
1174 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1175 NULL, TBB, FBB, CurBB);
1176 SwitchCases.push_back(CB);
1179 /// FindMergedConditions - If Cond is an expression like
1180 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1181 MachineBasicBlock *TBB,
1182 MachineBasicBlock *FBB,
1183 MachineBasicBlock *CurBB,
1185 // If this node is not part of the or/and tree, emit it as a branch.
1186 Instruction *BOp = dyn_cast<Instruction>(Cond);
1187 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1188 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1189 BOp->getParent() != CurBB->getBasicBlock() ||
1190 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1191 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1192 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1196 // Create TmpBB after CurBB.
1197 MachineFunction::iterator BBI = CurBB;
1198 MachineFunction &MF = DAG.getMachineFunction();
1199 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1200 CurBB->getParent()->insert(++BBI, TmpBB);
1202 if (Opc == Instruction::Or) {
1203 // Codegen X | Y as:
1211 // Emit the LHS condition.
1212 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1214 // Emit the RHS condition into TmpBB.
1215 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1217 assert(Opc == Instruction::And && "Unknown merge op!");
1218 // Codegen X & Y as:
1225 // This requires creation of TmpBB after CurBB.
1227 // Emit the LHS condition.
1228 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1230 // Emit the RHS condition into TmpBB.
1231 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1235 /// If the set of cases should be emitted as a series of branches, return true.
1236 /// If we should emit this as a bunch of and/or'd together conditions, return
1239 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1240 if (Cases.size() != 2) return true;
1242 // If this is two comparisons of the same values or'd or and'd together, they
1243 // will get folded into a single comparison, so don't emit two blocks.
1244 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1245 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1246 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1247 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1254 void SelectionDAGLowering::visitBr(BranchInst &I) {
1255 // Update machine-CFG edges.
1256 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1258 // Figure out which block is immediately after the current one.
1259 MachineBasicBlock *NextBlock = 0;
1260 MachineFunction::iterator BBI = CurMBB;
1261 if (++BBI != CurMBB->getParent()->end())
1264 if (I.isUnconditional()) {
1265 // Update machine-CFG edges.
1266 CurMBB->addSuccessor(Succ0MBB);
1268 // If this is not a fall-through branch, emit the branch.
1269 if (Succ0MBB != NextBlock)
1270 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1271 MVT::Other, getControlRoot(),
1272 DAG.getBasicBlock(Succ0MBB)));
1276 // If this condition is one of the special cases we handle, do special stuff
1278 Value *CondVal = I.getCondition();
1279 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1281 // If this is a series of conditions that are or'd or and'd together, emit
1282 // this as a sequence of branches instead of setcc's with and/or operations.
1283 // For example, instead of something like:
1296 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1297 if (BOp->hasOneUse() &&
1298 (BOp->getOpcode() == Instruction::And ||
1299 BOp->getOpcode() == Instruction::Or)) {
1300 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1301 // If the compares in later blocks need to use values not currently
1302 // exported from this block, export them now. This block should always
1303 // be the first entry.
1304 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1306 // Allow some cases to be rejected.
1307 if (ShouldEmitAsBranches(SwitchCases)) {
1308 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1309 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1310 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1313 // Emit the branch for this block.
1314 visitSwitchCase(SwitchCases[0]);
1315 SwitchCases.erase(SwitchCases.begin());
1319 // Okay, we decided not to do this, remove any inserted MBB's and clear
1321 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1322 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1324 SwitchCases.clear();
1328 // Create a CaseBlock record representing this branch.
1329 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1330 NULL, Succ0MBB, Succ1MBB, CurMBB);
1331 // Use visitSwitchCase to actually insert the fast branch sequence for this
1333 visitSwitchCase(CB);
1336 /// visitSwitchCase - Emits the necessary code to represent a single node in
1337 /// the binary search tree resulting from lowering a switch instruction.
1338 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1340 SDValue CondLHS = getValue(CB.CmpLHS);
1341 DebugLoc dl = getCurDebugLoc();
1343 // Build the setcc now.
1344 if (CB.CmpMHS == NULL) {
1345 // Fold "(X == true)" to X and "(X == false)" to !X to
1346 // handle common cases produced by branch lowering.
1347 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1349 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1350 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1351 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1353 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1355 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1357 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1358 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1360 SDValue CmpOp = getValue(CB.CmpMHS);
1361 MVT VT = CmpOp.getValueType();
1363 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1364 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1367 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1368 VT, CmpOp, DAG.getConstant(Low, VT));
1369 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1370 DAG.getConstant(High-Low, VT), ISD::SETULE);
1374 // Update successor info
1375 CurMBB->addSuccessor(CB.TrueBB);
1376 CurMBB->addSuccessor(CB.FalseBB);
1378 // Set NextBlock to be the MBB immediately after the current one, if any.
1379 // This is used to avoid emitting unnecessary branches to the next block.
1380 MachineBasicBlock *NextBlock = 0;
1381 MachineFunction::iterator BBI = CurMBB;
1382 if (++BBI != CurMBB->getParent()->end())
1385 // If the lhs block is the next block, invert the condition so that we can
1386 // fall through to the lhs instead of the rhs block.
1387 if (CB.TrueBB == NextBlock) {
1388 std::swap(CB.TrueBB, CB.FalseBB);
1389 SDValue True = DAG.getConstant(1, Cond.getValueType());
1390 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1392 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1393 MVT::Other, getControlRoot(), Cond,
1394 DAG.getBasicBlock(CB.TrueBB));
1396 // If the branch was constant folded, fix up the CFG.
1397 if (BrCond.getOpcode() == ISD::BR) {
1398 CurMBB->removeSuccessor(CB.FalseBB);
1399 DAG.setRoot(BrCond);
1401 // Otherwise, go ahead and insert the false branch.
1402 if (BrCond == getControlRoot())
1403 CurMBB->removeSuccessor(CB.TrueBB);
1405 if (CB.FalseBB == NextBlock)
1406 DAG.setRoot(BrCond);
1408 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1409 DAG.getBasicBlock(CB.FalseBB)));
1413 /// visitJumpTable - Emit JumpTable node in the current MBB
1414 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1415 // Emit the code for the jump table
1416 assert(JT.Reg != -1U && "Should lower JT Header first!");
1417 MVT PTy = TLI.getPointerTy();
1418 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1420 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1421 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1422 MVT::Other, Index.getValue(1),
1426 /// visitJumpTableHeader - This function emits necessary code to produce index
1427 /// in the JumpTable from switch case.
1428 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1429 JumpTableHeader &JTH) {
1430 // Subtract the lowest switch case value from the value being switched on and
1431 // conditional branch to default mbb if the result is greater than the
1432 // difference between smallest and largest cases.
1433 SDValue SwitchOp = getValue(JTH.SValue);
1434 MVT VT = SwitchOp.getValueType();
1435 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1436 DAG.getConstant(JTH.First, VT));
1438 // The SDNode we just created, which holds the value being switched on minus
1439 // the the smallest case value, needs to be copied to a virtual register so it
1440 // can be used as an index into the jump table in a subsequent basic block.
1441 // This value may be smaller or larger than the target's pointer type, and
1442 // therefore require extension or truncating.
1443 if (VT.bitsGT(TLI.getPointerTy()))
1444 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1445 TLI.getPointerTy(), SUB);
1447 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1448 TLI.getPointerTy(), SUB);
1450 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1451 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1452 JumpTableReg, SwitchOp);
1453 JT.Reg = JumpTableReg;
1455 // Emit the range check for the jump table, and branch to the default block
1456 // for the switch statement if the value being switched on exceeds the largest
1457 // case in the switch.
1458 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1459 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1460 DAG.getConstant(JTH.Last-JTH.First,VT),
1463 // Set NextBlock to be the MBB immediately after the current one, if any.
1464 // This is used to avoid emitting unnecessary branches to the next block.
1465 MachineBasicBlock *NextBlock = 0;
1466 MachineFunction::iterator BBI = CurMBB;
1467 if (++BBI != CurMBB->getParent()->end())
1470 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1471 MVT::Other, CopyTo, CMP,
1472 DAG.getBasicBlock(JT.Default));
1474 if (JT.MBB == NextBlock)
1475 DAG.setRoot(BrCond);
1477 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1478 DAG.getBasicBlock(JT.MBB)));
1481 /// visitBitTestHeader - This function emits necessary code to produce value
1482 /// suitable for "bit tests"
1483 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1484 // Subtract the minimum value
1485 SDValue SwitchOp = getValue(B.SValue);
1486 MVT VT = SwitchOp.getValueType();
1487 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1488 DAG.getConstant(B.First, VT));
1491 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1492 TLI.getSetCCResultType(SUB.getValueType()),
1493 SUB, DAG.getConstant(B.Range, VT),
1497 if (VT.bitsGT(TLI.getPointerTy()))
1498 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1499 TLI.getPointerTy(), SUB);
1501 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1502 TLI.getPointerTy(), SUB);
1504 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1505 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1508 // Set NextBlock to be the MBB immediately after the current one, if any.
1509 // This is used to avoid emitting unnecessary branches to the next block.
1510 MachineBasicBlock *NextBlock = 0;
1511 MachineFunction::iterator BBI = CurMBB;
1512 if (++BBI != CurMBB->getParent()->end())
1515 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1517 CurMBB->addSuccessor(B.Default);
1518 CurMBB->addSuccessor(MBB);
1520 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1521 MVT::Other, CopyTo, RangeCmp,
1522 DAG.getBasicBlock(B.Default));
1524 if (MBB == NextBlock)
1525 DAG.setRoot(BrRange);
1527 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1528 DAG.getBasicBlock(MBB)));
1531 /// visitBitTestCase - this function produces one "bit test"
1532 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1535 // Make desired shift
1536 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1537 TLI.getPointerTy());
1538 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1540 DAG.getConstant(1, TLI.getPointerTy()),
1543 // Emit bit tests and jumps
1544 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1545 TLI.getPointerTy(), SwitchVal,
1546 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1547 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1548 TLI.getSetCCResultType(AndOp.getValueType()),
1549 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1552 CurMBB->addSuccessor(B.TargetBB);
1553 CurMBB->addSuccessor(NextMBB);
1555 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1556 MVT::Other, getControlRoot(),
1557 AndCmp, DAG.getBasicBlock(B.TargetBB));
1559 // Set NextBlock to be the MBB immediately after the current one, if any.
1560 // This is used to avoid emitting unnecessary branches to the next block.
1561 MachineBasicBlock *NextBlock = 0;
1562 MachineFunction::iterator BBI = CurMBB;
1563 if (++BBI != CurMBB->getParent()->end())
1566 if (NextMBB == NextBlock)
1569 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1570 DAG.getBasicBlock(NextMBB)));
1573 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1574 // Retrieve successors.
1575 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1576 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1578 const Value *Callee(I.getCalledValue());
1579 if (isa<InlineAsm>(Callee))
1582 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1584 // If the value of the invoke is used outside of its defining block, make it
1585 // available as a virtual register.
1586 CopyToExportRegsIfNeeded(&I);
1588 // Update successor info
1589 CurMBB->addSuccessor(Return);
1590 CurMBB->addSuccessor(LandingPad);
1592 // Drop into normal successor.
1593 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1594 MVT::Other, getControlRoot(),
1595 DAG.getBasicBlock(Return)));
1598 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1601 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1602 /// small case ranges).
1603 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1604 CaseRecVector& WorkList,
1606 MachineBasicBlock* Default) {
1607 Case& BackCase = *(CR.Range.second-1);
1609 // Size is the number of Cases represented by this range.
1610 size_t Size = CR.Range.second - CR.Range.first;
1614 // Get the MachineFunction which holds the current MBB. This is used when
1615 // inserting any additional MBBs necessary to represent the switch.
1616 MachineFunction *CurMF = CurMBB->getParent();
1618 // Figure out which block is immediately after the current one.
1619 MachineBasicBlock *NextBlock = 0;
1620 MachineFunction::iterator BBI = CR.CaseBB;
1622 if (++BBI != CurMBB->getParent()->end())
1625 // TODO: If any two of the cases has the same destination, and if one value
1626 // is the same as the other, but has one bit unset that the other has set,
1627 // use bit manipulation to do two compares at once. For example:
1628 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1630 // Rearrange the case blocks so that the last one falls through if possible.
1631 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1632 // The last case block won't fall through into 'NextBlock' if we emit the
1633 // branches in this order. See if rearranging a case value would help.
1634 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1635 if (I->BB == NextBlock) {
1636 std::swap(*I, BackCase);
1642 // Create a CaseBlock record representing a conditional branch to
1643 // the Case's target mbb if the value being switched on SV is equal
1645 MachineBasicBlock *CurBlock = CR.CaseBB;
1646 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1647 MachineBasicBlock *FallThrough;
1649 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1650 CurMF->insert(BBI, FallThrough);
1652 // Put SV in a virtual register to make it available from the new blocks.
1653 ExportFromCurrentBlock(SV);
1655 // If the last case doesn't match, go to the default block.
1656 FallThrough = Default;
1659 Value *RHS, *LHS, *MHS;
1661 if (I->High == I->Low) {
1662 // This is just small small case range :) containing exactly 1 case
1664 LHS = SV; RHS = I->High; MHS = NULL;
1667 LHS = I->Low; MHS = SV; RHS = I->High;
1669 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1671 // If emitting the first comparison, just call visitSwitchCase to emit the
1672 // code into the current block. Otherwise, push the CaseBlock onto the
1673 // vector to be later processed by SDISel, and insert the node's MBB
1674 // before the next MBB.
1675 if (CurBlock == CurMBB)
1676 visitSwitchCase(CB);
1678 SwitchCases.push_back(CB);
1680 CurBlock = FallThrough;
1686 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1687 return !DisableJumpTables &&
1688 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1689 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1692 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1693 APInt LastExt(Last), FirstExt(First);
1694 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1695 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1696 return (LastExt - FirstExt + 1ULL);
1699 /// handleJTSwitchCase - Emit jumptable for current switch case range
1700 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1701 CaseRecVector& WorkList,
1703 MachineBasicBlock* Default) {
1704 Case& FrontCase = *CR.Range.first;
1705 Case& BackCase = *(CR.Range.second-1);
1707 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1708 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1711 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1715 if (!areJTsAllowed(TLI) || TSize <= 3)
1718 APInt Range = ComputeRange(First, Last);
1719 double Density = (double)TSize / Range.roundToDouble();
1723 DEBUG(errs() << "Lowering jump table\n"
1724 << "First entry: " << First << ". Last entry: " << Last << '\n'
1725 << "Range: " << Range
1726 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1728 // Get the MachineFunction which holds the current MBB. This is used when
1729 // inserting any additional MBBs necessary to represent the switch.
1730 MachineFunction *CurMF = CurMBB->getParent();
1732 // Figure out which block is immediately after the current one.
1733 MachineBasicBlock *NextBlock = 0;
1734 MachineFunction::iterator BBI = CR.CaseBB;
1736 if (++BBI != CurMBB->getParent()->end())
1739 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1741 // Create a new basic block to hold the code for loading the address
1742 // of the jump table, and jumping to it. Update successor information;
1743 // we will either branch to the default case for the switch, or the jump
1745 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1746 CurMF->insert(BBI, JumpTableBB);
1747 CR.CaseBB->addSuccessor(Default);
1748 CR.CaseBB->addSuccessor(JumpTableBB);
1750 // Build a vector of destination BBs, corresponding to each target
1751 // of the jump table. If the value of the jump table slot corresponds to
1752 // a case statement, push the case's BB onto the vector, otherwise, push
1754 std::vector<MachineBasicBlock*> DestBBs;
1756 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1757 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1758 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1760 if (Low.sle(TEI) && TEI.sle(High)) {
1761 DestBBs.push_back(I->BB);
1765 DestBBs.push_back(Default);
1769 // Update successor info. Add one edge to each unique successor.
1770 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1771 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1772 E = DestBBs.end(); I != E; ++I) {
1773 if (!SuccsHandled[(*I)->getNumber()]) {
1774 SuccsHandled[(*I)->getNumber()] = true;
1775 JumpTableBB->addSuccessor(*I);
1779 // Create a jump table index for this jump table, or return an existing
1781 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1783 // Set the jump table information so that we can codegen it as a second
1784 // MachineBasicBlock
1785 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1786 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1787 if (CR.CaseBB == CurMBB)
1788 visitJumpTableHeader(JT, JTH);
1790 JTCases.push_back(JumpTableBlock(JTH, JT));
1795 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1797 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1798 CaseRecVector& WorkList,
1800 MachineBasicBlock* Default) {
1801 // Get the MachineFunction which holds the current MBB. This is used when
1802 // inserting any additional MBBs necessary to represent the switch.
1803 MachineFunction *CurMF = CurMBB->getParent();
1805 // Figure out which block is immediately after the current one.
1806 MachineBasicBlock *NextBlock = 0;
1807 MachineFunction::iterator BBI = CR.CaseBB;
1809 if (++BBI != CurMBB->getParent()->end())
1812 Case& FrontCase = *CR.Range.first;
1813 Case& BackCase = *(CR.Range.second-1);
1814 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1816 // Size is the number of Cases represented by this range.
1817 unsigned Size = CR.Range.second - CR.Range.first;
1819 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1820 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1822 CaseItr Pivot = CR.Range.first + Size/2;
1824 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1825 // (heuristically) allow us to emit JumpTable's later.
1827 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1831 size_t LSize = FrontCase.size();
1832 size_t RSize = TSize-LSize;
1833 DEBUG(errs() << "Selecting best pivot: \n"
1834 << "First: " << First << ", Last: " << Last <<'\n'
1835 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1836 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1838 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1839 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1840 APInt Range = ComputeRange(LEnd, RBegin);
1841 assert((Range - 2ULL).isNonNegative() &&
1842 "Invalid case distance");
1843 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1844 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1845 double Metric = Range.logBase2()*(LDensity+RDensity);
1846 // Should always split in some non-trivial place
1847 DEBUG(errs() <<"=>Step\n"
1848 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1849 << "LDensity: " << LDensity
1850 << ", RDensity: " << RDensity << '\n'
1851 << "Metric: " << Metric << '\n');
1852 if (FMetric < Metric) {
1855 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1861 if (areJTsAllowed(TLI)) {
1862 // If our case is dense we *really* should handle it earlier!
1863 assert((FMetric > 0) && "Should handle dense range earlier!");
1865 Pivot = CR.Range.first + Size/2;
1868 CaseRange LHSR(CR.Range.first, Pivot);
1869 CaseRange RHSR(Pivot, CR.Range.second);
1870 Constant *C = Pivot->Low;
1871 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1873 // We know that we branch to the LHS if the Value being switched on is
1874 // less than the Pivot value, C. We use this to optimize our binary
1875 // tree a bit, by recognizing that if SV is greater than or equal to the
1876 // LHS's Case Value, and that Case Value is exactly one less than the
1877 // Pivot's Value, then we can branch directly to the LHS's Target,
1878 // rather than creating a leaf node for it.
1879 if ((LHSR.second - LHSR.first) == 1 &&
1880 LHSR.first->High == CR.GE &&
1881 cast<ConstantInt>(C)->getValue() ==
1882 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1883 TrueBB = LHSR.first->BB;
1885 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1886 CurMF->insert(BBI, TrueBB);
1887 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1889 // Put SV in a virtual register to make it available from the new blocks.
1890 ExportFromCurrentBlock(SV);
1893 // Similar to the optimization above, if the Value being switched on is
1894 // known to be less than the Constant CR.LT, and the current Case Value
1895 // is CR.LT - 1, then we can branch directly to the target block for
1896 // the current Case Value, rather than emitting a RHS leaf node for it.
1897 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1898 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1899 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1900 FalseBB = RHSR.first->BB;
1902 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1903 CurMF->insert(BBI, FalseBB);
1904 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1906 // Put SV in a virtual register to make it available from the new blocks.
1907 ExportFromCurrentBlock(SV);
1910 // Create a CaseBlock record representing a conditional branch to
1911 // the LHS node if the value being switched on SV is less than C.
1912 // Otherwise, branch to LHS.
1913 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1915 if (CR.CaseBB == CurMBB)
1916 visitSwitchCase(CB);
1918 SwitchCases.push_back(CB);
1923 /// handleBitTestsSwitchCase - if current case range has few destination and
1924 /// range span less, than machine word bitwidth, encode case range into series
1925 /// of masks and emit bit tests with these masks.
1926 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1927 CaseRecVector& WorkList,
1929 MachineBasicBlock* Default){
1930 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1932 Case& FrontCase = *CR.Range.first;
1933 Case& BackCase = *(CR.Range.second-1);
1935 // Get the MachineFunction which holds the current MBB. This is used when
1936 // inserting any additional MBBs necessary to represent the switch.
1937 MachineFunction *CurMF = CurMBB->getParent();
1940 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1942 // Single case counts one, case range - two.
1943 numCmps += (I->Low == I->High ? 1 : 2);
1946 // Count unique destinations
1947 SmallSet<MachineBasicBlock*, 4> Dests;
1948 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1949 Dests.insert(I->BB);
1950 if (Dests.size() > 3)
1951 // Don't bother the code below, if there are too much unique destinations
1954 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1955 << "Total number of comparisons: " << numCmps << '\n');
1957 // Compute span of values.
1958 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1959 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1960 APInt cmpRange = maxValue - minValue;
1962 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1963 << "Low bound: " << minValue << '\n'
1964 << "High bound: " << maxValue << '\n');
1966 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1967 (!(Dests.size() == 1 && numCmps >= 3) &&
1968 !(Dests.size() == 2 && numCmps >= 5) &&
1969 !(Dests.size() >= 3 && numCmps >= 6)))
1972 DEBUG(errs() << "Emitting bit tests\n");
1973 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1975 // Optimize the case where all the case values fit in a
1976 // word without having to subtract minValue. In this case,
1977 // we can optimize away the subtraction.
1978 if (minValue.isNonNegative() &&
1979 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1980 cmpRange = maxValue;
1982 lowBound = minValue;
1985 CaseBitsVector CasesBits;
1986 unsigned i, count = 0;
1988 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1989 MachineBasicBlock* Dest = I->BB;
1990 for (i = 0; i < count; ++i)
1991 if (Dest == CasesBits[i].BB)
1995 assert((count < 3) && "Too much destinations to test!");
1996 CasesBits.push_back(CaseBits(0, Dest, 0));
2000 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2001 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2003 uint64_t lo = (lowValue - lowBound).getZExtValue();
2004 uint64_t hi = (highValue - lowBound).getZExtValue();
2006 for (uint64_t j = lo; j <= hi; j++) {
2007 CasesBits[i].Mask |= 1ULL << j;
2008 CasesBits[i].Bits++;
2012 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2016 // Figure out which block is immediately after the current one.
2017 MachineFunction::iterator BBI = CR.CaseBB;
2020 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2022 DEBUG(errs() << "Cases:\n");
2023 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2024 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2025 << ", Bits: " << CasesBits[i].Bits
2026 << ", BB: " << CasesBits[i].BB << '\n');
2028 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2029 CurMF->insert(BBI, CaseBB);
2030 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2034 // Put SV in a virtual register to make it available from the new blocks.
2035 ExportFromCurrentBlock(SV);
2038 BitTestBlock BTB(lowBound, cmpRange, SV,
2039 -1U, (CR.CaseBB == CurMBB),
2040 CR.CaseBB, Default, BTC);
2042 if (CR.CaseBB == CurMBB)
2043 visitBitTestHeader(BTB);
2045 BitTestCases.push_back(BTB);
2051 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2052 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2053 const SwitchInst& SI) {
2056 // Start with "simple" cases
2057 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2058 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2059 Cases.push_back(Case(SI.getSuccessorValue(i),
2060 SI.getSuccessorValue(i),
2063 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2065 // Merge case into clusters
2066 if (Cases.size() >= 2)
2067 // Must recompute end() each iteration because it may be
2068 // invalidated by erase if we hold on to it
2069 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2070 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2071 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2072 MachineBasicBlock* nextBB = J->BB;
2073 MachineBasicBlock* currentBB = I->BB;
2075 // If the two neighboring cases go to the same destination, merge them
2076 // into a single case.
2077 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2085 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2086 if (I->Low != I->High)
2087 // A range counts double, since it requires two compares.
2094 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2095 // Figure out which block is immediately after the current one.
2096 MachineBasicBlock *NextBlock = 0;
2097 MachineFunction::iterator BBI = CurMBB;
2099 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2101 // If there is only the default destination, branch to it if it is not the
2102 // next basic block. Otherwise, just fall through.
2103 if (SI.getNumOperands() == 2) {
2104 // Update machine-CFG edges.
2106 // If this is not a fall-through branch, emit the branch.
2107 CurMBB->addSuccessor(Default);
2108 if (Default != NextBlock)
2109 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2110 MVT::Other, getControlRoot(),
2111 DAG.getBasicBlock(Default)));
2115 // If there are any non-default case statements, create a vector of Cases
2116 // representing each one, and sort the vector so that we can efficiently
2117 // create a binary search tree from them.
2119 size_t numCmps = Clusterify(Cases, SI);
2120 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2121 << ". Total compares: " << numCmps << '\n');
2124 // Get the Value to be switched on and default basic blocks, which will be
2125 // inserted into CaseBlock records, representing basic blocks in the binary
2127 Value *SV = SI.getOperand(0);
2129 // Push the initial CaseRec onto the worklist
2130 CaseRecVector WorkList;
2131 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2133 while (!WorkList.empty()) {
2134 // Grab a record representing a case range to process off the worklist
2135 CaseRec CR = WorkList.back();
2136 WorkList.pop_back();
2138 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2141 // If the range has few cases (two or less) emit a series of specific
2143 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2146 // If the switch has more than 5 blocks, and at least 40% dense, and the
2147 // target supports indirect branches, then emit a jump table rather than
2148 // lowering the switch to a binary tree of conditional branches.
2149 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2152 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2153 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2154 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2159 void SelectionDAGLowering::visitSub(User &I) {
2160 // -0.0 - X --> fneg
2161 const Type *Ty = I.getType();
2162 if (isa<VectorType>(Ty)) {
2163 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2164 const VectorType *DestTy = cast<VectorType>(I.getType());
2165 const Type *ElTy = DestTy->getElementType();
2166 if (ElTy->isFloatingPoint()) {
2167 unsigned VL = DestTy->getNumElements();
2168 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2169 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2171 SDValue Op2 = getValue(I.getOperand(1));
2172 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2173 Op2.getValueType(), Op2));
2179 if (Ty->isFloatingPoint()) {
2180 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2181 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2182 SDValue Op2 = getValue(I.getOperand(1));
2183 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2184 Op2.getValueType(), Op2));
2189 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2192 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2193 SDValue Op1 = getValue(I.getOperand(0));
2194 SDValue Op2 = getValue(I.getOperand(1));
2196 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2197 Op1.getValueType(), Op1, Op2));
2200 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2201 SDValue Op1 = getValue(I.getOperand(0));
2202 SDValue Op2 = getValue(I.getOperand(1));
2203 if (!isa<VectorType>(I.getType()) &&
2204 Op2.getValueType() != TLI.getShiftAmountTy()) {
2205 // If the operand is smaller than the shift count type, promote it.
2206 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2207 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2208 TLI.getShiftAmountTy(), Op2);
2209 // If the operand is larger than the shift count type but the shift
2210 // count type has enough bits to represent any shift value, truncate
2211 // it now. This is a common case and it exposes the truncate to
2212 // optimization early.
2213 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2214 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2215 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2216 TLI.getShiftAmountTy(), Op2);
2217 // Otherwise we'll need to temporarily settle for some other
2218 // convenient type; type legalization will make adjustments as
2220 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2221 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2222 TLI.getPointerTy(), Op2);
2223 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2224 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2225 TLI.getPointerTy(), Op2);
2228 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2229 Op1.getValueType(), Op1, Op2));
2232 void SelectionDAGLowering::visitICmp(User &I) {
2233 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2234 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2235 predicate = IC->getPredicate();
2236 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2237 predicate = ICmpInst::Predicate(IC->getPredicate());
2238 SDValue Op1 = getValue(I.getOperand(0));
2239 SDValue Op2 = getValue(I.getOperand(1));
2240 ISD::CondCode Opcode = getICmpCondCode(predicate);
2241 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2244 void SelectionDAGLowering::visitFCmp(User &I) {
2245 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2246 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2247 predicate = FC->getPredicate();
2248 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2249 predicate = FCmpInst::Predicate(FC->getPredicate());
2250 SDValue Op1 = getValue(I.getOperand(0));
2251 SDValue Op2 = getValue(I.getOperand(1));
2252 ISD::CondCode Condition = getFCmpCondCode(predicate);
2253 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2256 void SelectionDAGLowering::visitVICmp(User &I) {
2257 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2258 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2259 predicate = IC->getPredicate();
2260 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2261 predicate = ICmpInst::Predicate(IC->getPredicate());
2262 SDValue Op1 = getValue(I.getOperand(0));
2263 SDValue Op2 = getValue(I.getOperand(1));
2264 ISD::CondCode Opcode = getICmpCondCode(predicate);
2265 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2269 void SelectionDAGLowering::visitVFCmp(User &I) {
2270 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2271 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2272 predicate = FC->getPredicate();
2273 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2274 predicate = FCmpInst::Predicate(FC->getPredicate());
2275 SDValue Op1 = getValue(I.getOperand(0));
2276 SDValue Op2 = getValue(I.getOperand(1));
2277 ISD::CondCode Condition = getFCmpCondCode(predicate);
2278 MVT DestVT = TLI.getValueType(I.getType());
2280 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2283 void SelectionDAGLowering::visitSelect(User &I) {
2284 SmallVector<MVT, 4> ValueVTs;
2285 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2286 unsigned NumValues = ValueVTs.size();
2287 if (NumValues != 0) {
2288 SmallVector<SDValue, 4> Values(NumValues);
2289 SDValue Cond = getValue(I.getOperand(0));
2290 SDValue TrueVal = getValue(I.getOperand(1));
2291 SDValue FalseVal = getValue(I.getOperand(2));
2293 for (unsigned i = 0; i != NumValues; ++i)
2294 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2295 TrueVal.getValueType(), Cond,
2296 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2297 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2299 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2300 DAG.getVTList(&ValueVTs[0], NumValues),
2301 &Values[0], NumValues));
2306 void SelectionDAGLowering::visitTrunc(User &I) {
2307 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2308 SDValue N = getValue(I.getOperand(0));
2309 MVT DestVT = TLI.getValueType(I.getType());
2310 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2313 void SelectionDAGLowering::visitZExt(User &I) {
2314 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2315 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2316 SDValue N = getValue(I.getOperand(0));
2317 MVT DestVT = TLI.getValueType(I.getType());
2318 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2321 void SelectionDAGLowering::visitSExt(User &I) {
2322 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2323 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2324 SDValue N = getValue(I.getOperand(0));
2325 MVT DestVT = TLI.getValueType(I.getType());
2326 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2329 void SelectionDAGLowering::visitFPTrunc(User &I) {
2330 // FPTrunc is never a no-op cast, no need to check
2331 SDValue N = getValue(I.getOperand(0));
2332 MVT DestVT = TLI.getValueType(I.getType());
2333 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2334 DestVT, N, DAG.getIntPtrConstant(0)));
2337 void SelectionDAGLowering::visitFPExt(User &I){
2338 // FPTrunc is never a no-op cast, no need to check
2339 SDValue N = getValue(I.getOperand(0));
2340 MVT DestVT = TLI.getValueType(I.getType());
2341 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2344 void SelectionDAGLowering::visitFPToUI(User &I) {
2345 // FPToUI is never a no-op cast, no need to check
2346 SDValue N = getValue(I.getOperand(0));
2347 MVT DestVT = TLI.getValueType(I.getType());
2348 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2351 void SelectionDAGLowering::visitFPToSI(User &I) {
2352 // FPToSI is never a no-op cast, no need to check
2353 SDValue N = getValue(I.getOperand(0));
2354 MVT DestVT = TLI.getValueType(I.getType());
2355 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2358 void SelectionDAGLowering::visitUIToFP(User &I) {
2359 // UIToFP is never a no-op cast, no need to check
2360 SDValue N = getValue(I.getOperand(0));
2361 MVT DestVT = TLI.getValueType(I.getType());
2362 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2365 void SelectionDAGLowering::visitSIToFP(User &I){
2366 // SIToFP is never a no-op cast, no need to check
2367 SDValue N = getValue(I.getOperand(0));
2368 MVT DestVT = TLI.getValueType(I.getType());
2369 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2372 void SelectionDAGLowering::visitPtrToInt(User &I) {
2373 // What to do depends on the size of the integer and the size of the pointer.
2374 // We can either truncate, zero extend, or no-op, accordingly.
2375 SDValue N = getValue(I.getOperand(0));
2376 MVT SrcVT = N.getValueType();
2377 MVT DestVT = TLI.getValueType(I.getType());
2379 if (DestVT.bitsLT(SrcVT))
2380 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2382 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2383 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2384 setValue(&I, Result);
2387 void SelectionDAGLowering::visitIntToPtr(User &I) {
2388 // What to do depends on the size of the integer and the size of the pointer.
2389 // We can either truncate, zero extend, or no-op, accordingly.
2390 SDValue N = getValue(I.getOperand(0));
2391 MVT SrcVT = N.getValueType();
2392 MVT DestVT = TLI.getValueType(I.getType());
2393 if (DestVT.bitsLT(SrcVT))
2394 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2396 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2397 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2401 void SelectionDAGLowering::visitBitCast(User &I) {
2402 SDValue N = getValue(I.getOperand(0));
2403 MVT DestVT = TLI.getValueType(I.getType());
2405 // BitCast assures us that source and destination are the same size so this
2406 // is either a BIT_CONVERT or a no-op.
2407 if (DestVT != N.getValueType())
2408 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2409 DestVT, N)); // convert types
2411 setValue(&I, N); // noop cast.
2414 void SelectionDAGLowering::visitInsertElement(User &I) {
2415 SDValue InVec = getValue(I.getOperand(0));
2416 SDValue InVal = getValue(I.getOperand(1));
2417 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2419 getValue(I.getOperand(2)));
2421 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2422 TLI.getValueType(I.getType()),
2423 InVec, InVal, InIdx));
2426 void SelectionDAGLowering::visitExtractElement(User &I) {
2427 SDValue InVec = getValue(I.getOperand(0));
2428 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2430 getValue(I.getOperand(1)));
2431 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2432 TLI.getValueType(I.getType()), InVec, InIdx));
2436 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2437 // from SIndx and increasing to the element length (undefs are allowed).
2438 static bool SequentialMask(SDValue Mask, unsigned SIndx) {
2439 unsigned MaskNumElts = Mask.getNumOperands();
2440 for (unsigned i = 0; i != MaskNumElts; ++i) {
2441 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2442 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2443 if (Idx != i + SIndx)
2450 void SelectionDAGLowering::visitShuffleVector(User &I) {
2451 SDValue Src1 = getValue(I.getOperand(0));
2452 SDValue Src2 = getValue(I.getOperand(1));
2453 SDValue Mask = getValue(I.getOperand(2));
2455 MVT VT = TLI.getValueType(I.getType());
2456 MVT SrcVT = Src1.getValueType();
2457 int MaskNumElts = Mask.getNumOperands();
2458 int SrcNumElts = SrcVT.getVectorNumElements();
2460 if (SrcNumElts == MaskNumElts) {
2461 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2462 VT, Src1, Src2, Mask));
2466 // Normalize the shuffle vector since mask and vector length don't match.
2467 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2469 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2470 // Mask is longer than the source vectors and is a multiple of the source
2471 // vectors. We can use concatenate vector to make the mask and vectors
2473 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2474 // The shuffle is concatenating two vectors together.
2475 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2480 // Pad both vectors with undefs to make them the same length as the mask.
2481 unsigned NumConcat = MaskNumElts / SrcNumElts;
2482 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2484 SDValue* MOps1 = new SDValue[NumConcat];
2485 SDValue* MOps2 = new SDValue[NumConcat];
2488 for (unsigned i = 1; i != NumConcat; ++i) {
2489 MOps1[i] = UndefVal;
2490 MOps2[i] = UndefVal;
2492 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2493 VT, MOps1, NumConcat);
2494 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2495 VT, MOps2, NumConcat);
2500 // Readjust mask for new input vector length.
2501 SmallVector<SDValue, 8> MappedOps;
2502 for (int i = 0; i != MaskNumElts; ++i) {
2503 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2504 MappedOps.push_back(Mask.getOperand(i));
2506 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2507 if (Idx < SrcNumElts)
2508 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2510 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2514 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2515 Mask.getValueType(),
2516 &MappedOps[0], MappedOps.size());
2518 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2519 VT, Src1, Src2, Mask));
2523 if (SrcNumElts > MaskNumElts) {
2524 // Resulting vector is shorter than the incoming vector.
2525 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2526 // Shuffle extracts 1st vector.
2531 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2532 // Shuffle extracts 2nd vector.
2537 // Analyze the access pattern of the vector to see if we can extract
2538 // two subvectors and do the shuffle. The analysis is done by calculating
2539 // the range of elements the mask access on both vectors.
2540 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2541 int MaxRange[2] = {-1, -1};
2543 for (int i = 0; i != MaskNumElts; ++i) {
2544 SDValue Arg = Mask.getOperand(i);
2545 if (Arg.getOpcode() != ISD::UNDEF) {
2546 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2547 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2549 if (Idx >= SrcNumElts) {
2553 if (Idx > MaxRange[Input])
2554 MaxRange[Input] = Idx;
2555 if (Idx < MinRange[Input])
2556 MinRange[Input] = Idx;
2560 // Check if the access is smaller than the vector size and can we find
2561 // a reasonable extract index.
2562 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2563 int StartIdx[2]; // StartIdx to extract from
2564 for (int Input=0; Input < 2; ++Input) {
2565 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2566 RangeUse[Input] = 0; // Unused
2567 StartIdx[Input] = 0;
2568 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2569 // Fits within range but we should see if we can find a good
2570 // start index that is a multiple of the mask length.
2571 if (MaxRange[Input] < MaskNumElts) {
2572 RangeUse[Input] = 1; // Extract from beginning of the vector
2573 StartIdx[Input] = 0;
2575 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2576 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2577 StartIdx[Input] + MaskNumElts < SrcNumElts)
2578 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2583 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2584 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2587 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2588 // Extract appropriate subvector and generate a vector shuffle
2589 for (int Input=0; Input < 2; ++Input) {
2590 SDValue& Src = Input == 0 ? Src1 : Src2;
2591 if (RangeUse[Input] == 0) {
2592 Src = DAG.getUNDEF(VT);
2594 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2595 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2598 // Calculate new mask.
2599 SmallVector<SDValue, 8> MappedOps;
2600 for (int i = 0; i != MaskNumElts; ++i) {
2601 SDValue Arg = Mask.getOperand(i);
2602 if (Arg.getOpcode() == ISD::UNDEF) {
2603 MappedOps.push_back(Arg);
2605 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2606 if (Idx < SrcNumElts)
2607 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2609 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2610 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2614 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2615 Mask.getValueType(),
2616 &MappedOps[0], MappedOps.size());
2617 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
2618 VT, Src1, Src2, Mask));
2623 // We can't use either concat vectors or extract subvectors so fall back to
2624 // replacing the shuffle with extract and build vector.
2625 // to insert and build vector.
2626 MVT EltVT = VT.getVectorElementType();
2627 MVT PtrVT = TLI.getPointerTy();
2628 SmallVector<SDValue,8> Ops;
2629 for (int i = 0; i != MaskNumElts; ++i) {
2630 SDValue Arg = Mask.getOperand(i);
2631 if (Arg.getOpcode() == ISD::UNDEF) {
2632 Ops.push_back(DAG.getUNDEF(EltVT));
2634 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2635 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2636 if (Idx < SrcNumElts)
2637 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2638 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2640 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2642 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2645 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2646 VT, &Ops[0], Ops.size()));
2649 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2650 const Value *Op0 = I.getOperand(0);
2651 const Value *Op1 = I.getOperand(1);
2652 const Type *AggTy = I.getType();
2653 const Type *ValTy = Op1->getType();
2654 bool IntoUndef = isa<UndefValue>(Op0);
2655 bool FromUndef = isa<UndefValue>(Op1);
2657 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2658 I.idx_begin(), I.idx_end());
2660 SmallVector<MVT, 4> AggValueVTs;
2661 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2662 SmallVector<MVT, 4> ValValueVTs;
2663 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2665 unsigned NumAggValues = AggValueVTs.size();
2666 unsigned NumValValues = ValValueVTs.size();
2667 SmallVector<SDValue, 4> Values(NumAggValues);
2669 SDValue Agg = getValue(Op0);
2670 SDValue Val = getValue(Op1);
2672 // Copy the beginning value(s) from the original aggregate.
2673 for (; i != LinearIndex; ++i)
2674 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2675 SDValue(Agg.getNode(), Agg.getResNo() + i);
2676 // Copy values from the inserted value(s).
2677 for (; i != LinearIndex + NumValValues; ++i)
2678 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2679 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2680 // Copy remaining value(s) from the original aggregate.
2681 for (; i != NumAggValues; ++i)
2682 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2683 SDValue(Agg.getNode(), Agg.getResNo() + i);
2685 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2686 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2687 &Values[0], NumAggValues));
2690 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2691 const Value *Op0 = I.getOperand(0);
2692 const Type *AggTy = Op0->getType();
2693 const Type *ValTy = I.getType();
2694 bool OutOfUndef = isa<UndefValue>(Op0);
2696 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2697 I.idx_begin(), I.idx_end());
2699 SmallVector<MVT, 4> ValValueVTs;
2700 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2702 unsigned NumValValues = ValValueVTs.size();
2703 SmallVector<SDValue, 4> Values(NumValValues);
2705 SDValue Agg = getValue(Op0);
2706 // Copy out the selected value(s).
2707 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2708 Values[i - LinearIndex] =
2710 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2711 SDValue(Agg.getNode(), Agg.getResNo() + i);
2713 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2714 DAG.getVTList(&ValValueVTs[0], NumValValues),
2715 &Values[0], NumValValues));
2719 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2720 SDValue N = getValue(I.getOperand(0));
2721 const Type *Ty = I.getOperand(0)->getType();
2723 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2726 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2727 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2730 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2731 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2732 DAG.getIntPtrConstant(Offset));
2734 Ty = StTy->getElementType(Field);
2736 Ty = cast<SequentialType>(Ty)->getElementType();
2738 // If this is a constant subscript, handle it quickly.
2739 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2740 if (CI->getZExtValue() == 0) continue;
2742 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2744 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2746 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2748 DAG.getConstant(Offs, MVT::i64));
2750 OffsVal = DAG.getIntPtrConstant(Offs);
2751 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2756 // N = N + Idx * ElementSize;
2757 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2758 SDValue IdxN = getValue(Idx);
2760 // If the index is smaller or larger than intptr_t, truncate or extend
2762 if (IdxN.getValueType().bitsLT(N.getValueType()))
2763 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2764 N.getValueType(), IdxN);
2765 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2766 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2767 N.getValueType(), IdxN);
2769 // If this is a multiply by a power of two, turn it into a shl
2770 // immediately. This is a very common case.
2771 if (ElementSize != 1) {
2772 if (isPowerOf2_64(ElementSize)) {
2773 unsigned Amt = Log2_64(ElementSize);
2774 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2775 N.getValueType(), IdxN,
2776 DAG.getConstant(Amt, TLI.getPointerTy()));
2778 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2779 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2780 N.getValueType(), IdxN, Scale);
2784 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2785 N.getValueType(), N, IdxN);
2791 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2792 // If this is a fixed sized alloca in the entry block of the function,
2793 // allocate it statically on the stack.
2794 if (FuncInfo.StaticAllocaMap.count(&I))
2795 return; // getValue will auto-populate this.
2797 const Type *Ty = I.getAllocatedType();
2798 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2800 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2803 SDValue AllocSize = getValue(I.getArraySize());
2805 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2807 DAG.getConstant(TySize, AllocSize.getValueType()));
2811 MVT IntPtr = TLI.getPointerTy();
2812 if (IntPtr.bitsLT(AllocSize.getValueType()))
2813 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2815 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2816 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2819 // Handle alignment. If the requested alignment is less than or equal to
2820 // the stack alignment, ignore it. If the size is greater than or equal to
2821 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2822 unsigned StackAlign =
2823 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2824 if (Align <= StackAlign)
2827 // Round the size of the allocation up to the stack alignment size
2828 // by add SA-1 to the size.
2829 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2830 AllocSize.getValueType(), AllocSize,
2831 DAG.getIntPtrConstant(StackAlign-1));
2832 // Mask out the low bits for alignment purposes.
2833 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2834 AllocSize.getValueType(), AllocSize,
2835 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2837 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2838 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2839 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2842 DAG.setRoot(DSA.getValue(1));
2844 // Inform the Frame Information that we have just allocated a variable-sized
2846 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2849 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2850 const Value *SV = I.getOperand(0);
2851 SDValue Ptr = getValue(SV);
2853 const Type *Ty = I.getType();
2854 bool isVolatile = I.isVolatile();
2855 unsigned Alignment = I.getAlignment();
2857 SmallVector<MVT, 4> ValueVTs;
2858 SmallVector<uint64_t, 4> Offsets;
2859 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2860 unsigned NumValues = ValueVTs.size();
2865 bool ConstantMemory = false;
2867 // Serialize volatile loads with other side effects.
2869 else if (AA->pointsToConstantMemory(SV)) {
2870 // Do not serialize (non-volatile) loads of constant memory with anything.
2871 Root = DAG.getEntryNode();
2872 ConstantMemory = true;
2874 // Do not serialize non-volatile loads against each other.
2875 Root = DAG.getRoot();
2878 SmallVector<SDValue, 4> Values(NumValues);
2879 SmallVector<SDValue, 4> Chains(NumValues);
2880 MVT PtrVT = Ptr.getValueType();
2881 for (unsigned i = 0; i != NumValues; ++i) {
2882 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2883 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2885 DAG.getConstant(Offsets[i], PtrVT)),
2887 isVolatile, Alignment);
2889 Chains[i] = L.getValue(1);
2892 if (!ConstantMemory) {
2893 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2895 &Chains[0], NumValues);
2899 PendingLoads.push_back(Chain);
2902 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2903 DAG.getVTList(&ValueVTs[0], NumValues),
2904 &Values[0], NumValues));
2908 void SelectionDAGLowering::visitStore(StoreInst &I) {
2909 Value *SrcV = I.getOperand(0);
2910 Value *PtrV = I.getOperand(1);
2912 SmallVector<MVT, 4> ValueVTs;
2913 SmallVector<uint64_t, 4> Offsets;
2914 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2915 unsigned NumValues = ValueVTs.size();
2919 // Get the lowered operands. Note that we do this after
2920 // checking if NumResults is zero, because with zero results
2921 // the operands won't have values in the map.
2922 SDValue Src = getValue(SrcV);
2923 SDValue Ptr = getValue(PtrV);
2925 SDValue Root = getRoot();
2926 SmallVector<SDValue, 4> Chains(NumValues);
2927 MVT PtrVT = Ptr.getValueType();
2928 bool isVolatile = I.isVolatile();
2929 unsigned Alignment = I.getAlignment();
2930 for (unsigned i = 0; i != NumValues; ++i)
2931 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2932 SDValue(Src.getNode(), Src.getResNo() + i),
2933 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2935 DAG.getConstant(Offsets[i], PtrVT)),
2937 isVolatile, Alignment);
2939 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2940 MVT::Other, &Chains[0], NumValues));
2943 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2945 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2946 unsigned Intrinsic) {
2947 bool HasChain = !I.doesNotAccessMemory();
2948 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2950 // Build the operand list.
2951 SmallVector<SDValue, 8> Ops;
2952 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2954 // We don't need to serialize loads against other loads.
2955 Ops.push_back(DAG.getRoot());
2957 Ops.push_back(getRoot());
2961 // Info is set by getTgtMemInstrinsic
2962 TargetLowering::IntrinsicInfo Info;
2963 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2965 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2966 if (!IsTgtIntrinsic)
2967 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2969 // Add all operands of the call to the operand list.
2970 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2971 SDValue Op = getValue(I.getOperand(i));
2972 assert(TLI.isTypeLegal(Op.getValueType()) &&
2973 "Intrinsic uses a non-legal type?");
2977 std::vector<MVT> VTArray;
2978 if (I.getType() != Type::VoidTy) {
2979 MVT VT = TLI.getValueType(I.getType());
2980 if (VT.isVector()) {
2981 const VectorType *DestTy = cast<VectorType>(I.getType());
2982 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2984 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2985 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2988 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2989 VTArray.push_back(VT);
2992 VTArray.push_back(MVT::Other);
2994 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2998 if (IsTgtIntrinsic) {
2999 // This is target intrinsic that touches memory
3000 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3001 VTs, &Ops[0], Ops.size(),
3002 Info.memVT, Info.ptrVal, Info.offset,
3003 Info.align, Info.vol,
3004 Info.readMem, Info.writeMem);
3007 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3008 VTs, &Ops[0], Ops.size());
3009 else if (I.getType() != Type::VoidTy)
3010 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3011 VTs, &Ops[0], Ops.size());
3013 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3014 VTs, &Ops[0], Ops.size());
3017 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3019 PendingLoads.push_back(Chain);
3023 if (I.getType() != Type::VoidTy) {
3024 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3025 MVT VT = TLI.getValueType(PTy);
3026 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3028 setValue(&I, Result);
3032 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3033 static GlobalVariable *ExtractTypeInfo(Value *V) {
3034 V = V->stripPointerCasts();
3035 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3036 assert ((GV || isa<ConstantPointerNull>(V)) &&
3037 "TypeInfo must be a global variable or NULL");
3043 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3044 /// call, and add them to the specified machine basic block.
3045 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3046 MachineBasicBlock *MBB) {
3047 // Inform the MachineModuleInfo of the personality for this landing pad.
3048 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3049 assert(CE->getOpcode() == Instruction::BitCast &&
3050 isa<Function>(CE->getOperand(0)) &&
3051 "Personality should be a function");
3052 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3054 // Gather all the type infos for this landing pad and pass them along to
3055 // MachineModuleInfo.
3056 std::vector<GlobalVariable *> TyInfo;
3057 unsigned N = I.getNumOperands();
3059 for (unsigned i = N - 1; i > 2; --i) {
3060 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3061 unsigned FilterLength = CI->getZExtValue();
3062 unsigned FirstCatch = i + FilterLength + !FilterLength;
3063 assert (FirstCatch <= N && "Invalid filter length");
3065 if (FirstCatch < N) {
3066 TyInfo.reserve(N - FirstCatch);
3067 for (unsigned j = FirstCatch; j < N; ++j)
3068 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3069 MMI->addCatchTypeInfo(MBB, TyInfo);
3073 if (!FilterLength) {
3075 MMI->addCleanup(MBB);
3078 TyInfo.reserve(FilterLength - 1);
3079 for (unsigned j = i + 1; j < FirstCatch; ++j)
3080 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3081 MMI->addFilterTypeInfo(MBB, TyInfo);
3090 TyInfo.reserve(N - 3);
3091 for (unsigned j = 3; j < N; ++j)
3092 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3093 MMI->addCatchTypeInfo(MBB, TyInfo);
3099 /// GetSignificand - Get the significand and build it into a floating-point
3100 /// number with exponent of 1:
3102 /// Op = (Op & 0x007fffff) | 0x3f800000;
3104 /// where Op is the hexidecimal representation of floating point value.
3106 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3107 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3108 DAG.getConstant(0x007fffff, MVT::i32));
3109 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3110 DAG.getConstant(0x3f800000, MVT::i32));
3111 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3114 /// GetExponent - Get the exponent:
3116 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3118 /// where Op is the hexidecimal representation of floating point value.
3120 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3122 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3123 DAG.getConstant(0x7f800000, MVT::i32));
3124 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3125 DAG.getConstant(23, TLI.getPointerTy()));
3126 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3127 DAG.getConstant(127, MVT::i32));
3128 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3131 /// getF32Constant - Get 32-bit floating point constant.
3133 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3134 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3137 /// Inlined utility function to implement binary input atomic intrinsics for
3138 /// visitIntrinsicCall: I is a call instruction
3139 /// Op is the associated NodeType for I
3141 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3142 SDValue Root = getRoot();
3144 DAG.getAtomic(Op, getCurDebugLoc(),
3145 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3147 getValue(I.getOperand(1)),
3148 getValue(I.getOperand(2)),
3151 DAG.setRoot(L.getValue(1));
3155 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3157 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3158 SDValue Op1 = getValue(I.getOperand(1));
3159 SDValue Op2 = getValue(I.getOperand(2));
3161 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3162 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3164 setValue(&I, Result);
3168 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3169 /// limited-precision mode.
3171 SelectionDAGLowering::visitExp(CallInst &I) {
3173 DebugLoc dl = getCurDebugLoc();
3175 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3176 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3177 SDValue Op = getValue(I.getOperand(1));
3179 // Put the exponent in the right bit position for later addition to the
3182 // #define LOG2OFe 1.4426950f
3183 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3184 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3185 getF32Constant(DAG, 0x3fb8aa3b));
3186 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3188 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3189 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3190 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3192 // IntegerPartOfX <<= 23;
3193 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3194 DAG.getConstant(23, TLI.getPointerTy()));
3196 if (LimitFloatPrecision <= 6) {
3197 // For floating-point precision of 6:
3199 // TwoToFractionalPartOfX =
3201 // (0.735607626f + 0.252464424f * x) * x;
3203 // error 0.0144103317, which is 6 bits
3204 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3205 getF32Constant(DAG, 0x3e814304));
3206 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3207 getF32Constant(DAG, 0x3f3c50c8));
3208 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3209 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3210 getF32Constant(DAG, 0x3f7f5e7e));
3211 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3213 // Add the exponent into the result in integer domain.
3214 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3215 TwoToFracPartOfX, IntegerPartOfX);
3217 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3218 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3219 // For floating-point precision of 12:
3221 // TwoToFractionalPartOfX =
3224 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3226 // 0.000107046256 error, which is 13 to 14 bits
3227 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3228 getF32Constant(DAG, 0x3da235e3));
3229 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3230 getF32Constant(DAG, 0x3e65b8f3));
3231 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3232 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3233 getF32Constant(DAG, 0x3f324b07));
3234 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3235 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3236 getF32Constant(DAG, 0x3f7ff8fd));
3237 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3239 // Add the exponent into the result in integer domain.
3240 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3241 TwoToFracPartOfX, IntegerPartOfX);
3243 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3244 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3245 // For floating-point precision of 18:
3247 // TwoToFractionalPartOfX =
3251 // (0.554906021e-1f +
3252 // (0.961591928e-2f +
3253 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3255 // error 2.47208000*10^(-7), which is better than 18 bits
3256 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3257 getF32Constant(DAG, 0x3924b03e));
3258 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3259 getF32Constant(DAG, 0x3ab24b87));
3260 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3261 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3262 getF32Constant(DAG, 0x3c1d8c17));
3263 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3264 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3265 getF32Constant(DAG, 0x3d634a1d));
3266 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3267 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3268 getF32Constant(DAG, 0x3e75fe14));
3269 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3270 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3271 getF32Constant(DAG, 0x3f317234));
3272 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3273 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3274 getF32Constant(DAG, 0x3f800000));
3275 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3278 // Add the exponent into the result in integer domain.
3279 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3280 TwoToFracPartOfX, IntegerPartOfX);
3282 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3285 // No special expansion.
3286 result = DAG.getNode(ISD::FEXP, dl,
3287 getValue(I.getOperand(1)).getValueType(),
3288 getValue(I.getOperand(1)));
3291 setValue(&I, result);
3294 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3295 /// limited-precision mode.
3297 SelectionDAGLowering::visitLog(CallInst &I) {
3299 DebugLoc dl = getCurDebugLoc();
3301 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3302 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3303 SDValue Op = getValue(I.getOperand(1));
3304 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3306 // Scale the exponent by log(2) [0.69314718f].
3307 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3308 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3309 getF32Constant(DAG, 0x3f317218));
3311 // Get the significand and build it into a floating-point number with
3313 SDValue X = GetSignificand(DAG, Op1, dl);
3315 if (LimitFloatPrecision <= 6) {
3316 // For floating-point precision of 6:
3320 // (1.4034025f - 0.23903021f * x) * x;
3322 // error 0.0034276066, which is better than 8 bits
3323 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3324 getF32Constant(DAG, 0xbe74c456));
3325 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3326 getF32Constant(DAG, 0x3fb3a2b1));
3327 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3328 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3329 getF32Constant(DAG, 0x3f949a29));
3331 result = DAG.getNode(ISD::FADD, dl,
3332 MVT::f32, LogOfExponent, LogOfMantissa);
3333 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3334 // For floating-point precision of 12:
3340 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3342 // error 0.000061011436, which is 14 bits
3343 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3344 getF32Constant(DAG, 0xbd67b6d6));
3345 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3346 getF32Constant(DAG, 0x3ee4f4b8));
3347 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3348 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3349 getF32Constant(DAG, 0x3fbc278b));
3350 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3351 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3352 getF32Constant(DAG, 0x40348e95));
3353 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3354 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3355 getF32Constant(DAG, 0x3fdef31a));
3357 result = DAG.getNode(ISD::FADD, dl,
3358 MVT::f32, LogOfExponent, LogOfMantissa);
3359 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3360 // For floating-point precision of 18:
3368 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3370 // error 0.0000023660568, which is better than 18 bits
3371 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3372 getF32Constant(DAG, 0xbc91e5ac));
3373 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3374 getF32Constant(DAG, 0x3e4350aa));
3375 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3376 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3377 getF32Constant(DAG, 0x3f60d3e3));
3378 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3379 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3380 getF32Constant(DAG, 0x4011cdf0));
3381 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3382 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3383 getF32Constant(DAG, 0x406cfd1c));
3384 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3385 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3386 getF32Constant(DAG, 0x408797cb));
3387 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3388 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3389 getF32Constant(DAG, 0x4006dcab));
3391 result = DAG.getNode(ISD::FADD, dl,
3392 MVT::f32, LogOfExponent, LogOfMantissa);
3395 // No special expansion.
3396 result = DAG.getNode(ISD::FLOG, dl,
3397 getValue(I.getOperand(1)).getValueType(),
3398 getValue(I.getOperand(1)));
3401 setValue(&I, result);
3404 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3405 /// limited-precision mode.
3407 SelectionDAGLowering::visitLog2(CallInst &I) {
3409 DebugLoc dl = getCurDebugLoc();
3411 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3412 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3413 SDValue Op = getValue(I.getOperand(1));
3414 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3416 // Get the exponent.
3417 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3419 // Get the significand and build it into a floating-point number with
3421 SDValue X = GetSignificand(DAG, Op1, dl);
3423 // Different possible minimax approximations of significand in
3424 // floating-point for various degrees of accuracy over [1,2].
3425 if (LimitFloatPrecision <= 6) {
3426 // For floating-point precision of 6:
3428 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3430 // error 0.0049451742, which is more than 7 bits
3431 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3432 getF32Constant(DAG, 0xbeb08fe0));
3433 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3434 getF32Constant(DAG, 0x40019463));
3435 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3436 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3437 getF32Constant(DAG, 0x3fd6633d));
3439 result = DAG.getNode(ISD::FADD, dl,
3440 MVT::f32, LogOfExponent, Log2ofMantissa);
3441 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3442 // For floating-point precision of 12:
3448 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3450 // error 0.0000876136000, which is better than 13 bits
3451 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3452 getF32Constant(DAG, 0xbda7262e));
3453 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3454 getF32Constant(DAG, 0x3f25280b));
3455 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3456 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3457 getF32Constant(DAG, 0x4007b923));
3458 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3459 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3460 getF32Constant(DAG, 0x40823e2f));
3461 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3462 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3463 getF32Constant(DAG, 0x4020d29c));
3465 result = DAG.getNode(ISD::FADD, dl,
3466 MVT::f32, LogOfExponent, Log2ofMantissa);
3467 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3468 // For floating-point precision of 18:
3477 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3479 // error 0.0000018516, which is better than 18 bits
3480 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3481 getF32Constant(DAG, 0xbcd2769e));
3482 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3483 getF32Constant(DAG, 0x3e8ce0b9));
3484 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3485 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3486 getF32Constant(DAG, 0x3fa22ae7));
3487 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3488 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3489 getF32Constant(DAG, 0x40525723));
3490 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3491 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3492 getF32Constant(DAG, 0x40aaf200));
3493 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3494 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3495 getF32Constant(DAG, 0x40c39dad));
3496 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3497 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3498 getF32Constant(DAG, 0x4042902c));
3500 result = DAG.getNode(ISD::FADD, dl,
3501 MVT::f32, LogOfExponent, Log2ofMantissa);
3504 // No special expansion.
3505 result = DAG.getNode(ISD::FLOG2, dl,
3506 getValue(I.getOperand(1)).getValueType(),
3507 getValue(I.getOperand(1)));
3510 setValue(&I, result);
3513 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3514 /// limited-precision mode.
3516 SelectionDAGLowering::visitLog10(CallInst &I) {
3518 DebugLoc dl = getCurDebugLoc();
3520 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3521 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3522 SDValue Op = getValue(I.getOperand(1));
3523 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3525 // Scale the exponent by log10(2) [0.30102999f].
3526 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3527 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3528 getF32Constant(DAG, 0x3e9a209a));
3530 // Get the significand and build it into a floating-point number with
3532 SDValue X = GetSignificand(DAG, Op1, dl);
3534 if (LimitFloatPrecision <= 6) {
3535 // For floating-point precision of 6:
3537 // Log10ofMantissa =
3539 // (0.60948995f - 0.10380950f * x) * x;
3541 // error 0.0014886165, which is 6 bits
3542 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3543 getF32Constant(DAG, 0xbdd49a13));
3544 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3545 getF32Constant(DAG, 0x3f1c0789));
3546 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3547 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3548 getF32Constant(DAG, 0x3f011300));
3550 result = DAG.getNode(ISD::FADD, dl,
3551 MVT::f32, LogOfExponent, Log10ofMantissa);
3552 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3553 // For floating-point precision of 12:
3555 // Log10ofMantissa =
3558 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3560 // error 0.00019228036, which is better than 12 bits
3561 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3562 getF32Constant(DAG, 0x3d431f31));
3563 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3564 getF32Constant(DAG, 0x3ea21fb2));
3565 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3566 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3567 getF32Constant(DAG, 0x3f6ae232));
3568 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3569 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3570 getF32Constant(DAG, 0x3f25f7c3));
3572 result = DAG.getNode(ISD::FADD, dl,
3573 MVT::f32, LogOfExponent, Log10ofMantissa);
3574 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3575 // For floating-point precision of 18:
3577 // Log10ofMantissa =
3582 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3584 // error 0.0000037995730, which is better than 18 bits
3585 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3586 getF32Constant(DAG, 0x3c5d51ce));
3587 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3588 getF32Constant(DAG, 0x3e00685a));
3589 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3590 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3591 getF32Constant(DAG, 0x3efb6798));
3592 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3593 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3594 getF32Constant(DAG, 0x3f88d192));
3595 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3596 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3597 getF32Constant(DAG, 0x3fc4316c));
3598 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3599 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3600 getF32Constant(DAG, 0x3f57ce70));
3602 result = DAG.getNode(ISD::FADD, dl,
3603 MVT::f32, LogOfExponent, Log10ofMantissa);
3606 // No special expansion.
3607 result = DAG.getNode(ISD::FLOG10, dl,
3608 getValue(I.getOperand(1)).getValueType(),
3609 getValue(I.getOperand(1)));
3612 setValue(&I, result);
3615 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3616 /// limited-precision mode.
3618 SelectionDAGLowering::visitExp2(CallInst &I) {
3620 DebugLoc dl = getCurDebugLoc();
3622 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3623 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3624 SDValue Op = getValue(I.getOperand(1));
3626 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3628 // FractionalPartOfX = x - (float)IntegerPartOfX;
3629 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3630 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3632 // IntegerPartOfX <<= 23;
3633 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3634 DAG.getConstant(23, TLI.getPointerTy()));
3636 if (LimitFloatPrecision <= 6) {
3637 // For floating-point precision of 6:
3639 // TwoToFractionalPartOfX =
3641 // (0.735607626f + 0.252464424f * x) * x;
3643 // error 0.0144103317, which is 6 bits
3644 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3645 getF32Constant(DAG, 0x3e814304));
3646 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3647 getF32Constant(DAG, 0x3f3c50c8));
3648 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3649 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3650 getF32Constant(DAG, 0x3f7f5e7e));
3651 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3652 SDValue TwoToFractionalPartOfX =
3653 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3655 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3656 MVT::f32, TwoToFractionalPartOfX);
3657 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3658 // For floating-point precision of 12:
3660 // TwoToFractionalPartOfX =
3663 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3665 // error 0.000107046256, which is 13 to 14 bits
3666 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3667 getF32Constant(DAG, 0x3da235e3));
3668 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3669 getF32Constant(DAG, 0x3e65b8f3));
3670 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3671 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3672 getF32Constant(DAG, 0x3f324b07));
3673 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3674 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3675 getF32Constant(DAG, 0x3f7ff8fd));
3676 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3677 SDValue TwoToFractionalPartOfX =
3678 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3680 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3681 MVT::f32, TwoToFractionalPartOfX);
3682 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3683 // For floating-point precision of 18:
3685 // TwoToFractionalPartOfX =
3689 // (0.554906021e-1f +
3690 // (0.961591928e-2f +
3691 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3692 // error 2.47208000*10^(-7), which is better than 18 bits
3693 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3694 getF32Constant(DAG, 0x3924b03e));
3695 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3696 getF32Constant(DAG, 0x3ab24b87));
3697 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3698 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3699 getF32Constant(DAG, 0x3c1d8c17));
3700 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3701 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3702 getF32Constant(DAG, 0x3d634a1d));
3703 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3704 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3705 getF32Constant(DAG, 0x3e75fe14));
3706 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3707 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3708 getF32Constant(DAG, 0x3f317234));
3709 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3710 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3711 getF32Constant(DAG, 0x3f800000));
3712 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3713 SDValue TwoToFractionalPartOfX =
3714 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3716 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3717 MVT::f32, TwoToFractionalPartOfX);
3720 // No special expansion.
3721 result = DAG.getNode(ISD::FEXP2, dl,
3722 getValue(I.getOperand(1)).getValueType(),
3723 getValue(I.getOperand(1)));
3726 setValue(&I, result);
3729 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3730 /// limited-precision mode with x == 10.0f.
3732 SelectionDAGLowering::visitPow(CallInst &I) {
3734 Value *Val = I.getOperand(1);
3735 DebugLoc dl = getCurDebugLoc();
3736 bool IsExp10 = false;
3738 if (getValue(Val).getValueType() == MVT::f32 &&
3739 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3740 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3741 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3742 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3744 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3749 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3750 SDValue Op = getValue(I.getOperand(2));
3752 // Put the exponent in the right bit position for later addition to the
3755 // #define LOG2OF10 3.3219281f
3756 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3757 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3758 getF32Constant(DAG, 0x40549a78));
3759 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3761 // FractionalPartOfX = x - (float)IntegerPartOfX;
3762 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3763 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3765 // IntegerPartOfX <<= 23;
3766 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3767 DAG.getConstant(23, TLI.getPointerTy()));
3769 if (LimitFloatPrecision <= 6) {
3770 // For floating-point precision of 6:
3772 // twoToFractionalPartOfX =
3774 // (0.735607626f + 0.252464424f * x) * x;
3776 // error 0.0144103317, which is 6 bits
3777 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3778 getF32Constant(DAG, 0x3e814304));
3779 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3780 getF32Constant(DAG, 0x3f3c50c8));
3781 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3782 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3783 getF32Constant(DAG, 0x3f7f5e7e));
3784 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3785 SDValue TwoToFractionalPartOfX =
3786 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3788 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3789 MVT::f32, TwoToFractionalPartOfX);
3790 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3791 // For floating-point precision of 12:
3793 // TwoToFractionalPartOfX =
3796 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3798 // error 0.000107046256, which is 13 to 14 bits
3799 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3800 getF32Constant(DAG, 0x3da235e3));
3801 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3802 getF32Constant(DAG, 0x3e65b8f3));
3803 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3804 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3805 getF32Constant(DAG, 0x3f324b07));
3806 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3807 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3808 getF32Constant(DAG, 0x3f7ff8fd));
3809 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3810 SDValue TwoToFractionalPartOfX =
3811 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3813 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3814 MVT::f32, TwoToFractionalPartOfX);
3815 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3816 // For floating-point precision of 18:
3818 // TwoToFractionalPartOfX =
3822 // (0.554906021e-1f +
3823 // (0.961591928e-2f +
3824 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3825 // error 2.47208000*10^(-7), which is better than 18 bits
3826 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3827 getF32Constant(DAG, 0x3924b03e));
3828 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3829 getF32Constant(DAG, 0x3ab24b87));
3830 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3831 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3832 getF32Constant(DAG, 0x3c1d8c17));
3833 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3834 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3835 getF32Constant(DAG, 0x3d634a1d));
3836 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3837 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3838 getF32Constant(DAG, 0x3e75fe14));
3839 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3840 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3841 getF32Constant(DAG, 0x3f317234));
3842 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3843 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3844 getF32Constant(DAG, 0x3f800000));
3845 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3846 SDValue TwoToFractionalPartOfX =
3847 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3849 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3850 MVT::f32, TwoToFractionalPartOfX);
3853 // No special expansion.
3854 result = DAG.getNode(ISD::FPOW, dl,
3855 getValue(I.getOperand(1)).getValueType(),
3856 getValue(I.getOperand(1)),
3857 getValue(I.getOperand(2)));
3860 setValue(&I, result);
3863 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3864 /// we want to emit this as a call to a named external function, return the name
3865 /// otherwise lower it and return null.
3867 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3868 DebugLoc dl = getCurDebugLoc();
3869 switch (Intrinsic) {
3871 // By default, turn this into a target intrinsic node.
3872 visitTargetIntrinsic(I, Intrinsic);
3874 case Intrinsic::vastart: visitVAStart(I); return 0;
3875 case Intrinsic::vaend: visitVAEnd(I); return 0;
3876 case Intrinsic::vacopy: visitVACopy(I); return 0;
3877 case Intrinsic::returnaddress:
3878 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3879 getValue(I.getOperand(1))));
3881 case Intrinsic::frameaddress:
3882 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3883 getValue(I.getOperand(1))));
3885 case Intrinsic::setjmp:
3886 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3888 case Intrinsic::longjmp:
3889 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3891 case Intrinsic::memcpy: {
3892 SDValue Op1 = getValue(I.getOperand(1));
3893 SDValue Op2 = getValue(I.getOperand(2));
3894 SDValue Op3 = getValue(I.getOperand(3));
3895 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3896 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3897 I.getOperand(1), 0, I.getOperand(2), 0));
3900 case Intrinsic::memset: {
3901 SDValue Op1 = getValue(I.getOperand(1));
3902 SDValue Op2 = getValue(I.getOperand(2));
3903 SDValue Op3 = getValue(I.getOperand(3));
3904 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3905 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3906 I.getOperand(1), 0));
3909 case Intrinsic::memmove: {
3910 SDValue Op1 = getValue(I.getOperand(1));
3911 SDValue Op2 = getValue(I.getOperand(2));
3912 SDValue Op3 = getValue(I.getOperand(3));
3913 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3915 // If the source and destination are known to not be aliases, we can
3916 // lower memmove as memcpy.
3917 uint64_t Size = -1ULL;
3918 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3919 Size = C->getZExtValue();
3920 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3921 AliasAnalysis::NoAlias) {
3922 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3923 I.getOperand(1), 0, I.getOperand(2), 0));
3927 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3928 I.getOperand(1), 0, I.getOperand(2), 0));
3931 case Intrinsic::dbg_stoppoint: {
3932 DwarfWriter *DW = DAG.getDwarfWriter();
3933 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3934 if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
3935 MachineFunction &MF = DAG.getMachineFunction();
3937 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3941 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3942 std::string Dir, FN;
3943 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
3944 CU.getFilename(FN));
3945 unsigned idx = MF.getOrCreateDebugLocID(SrcFile,
3946 SPI.getLine(), SPI.getColumn());
3947 setCurDebugLoc(DebugLoc::get(idx));
3951 case Intrinsic::dbg_region_start: {
3952 DwarfWriter *DW = DAG.getDwarfWriter();
3953 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3954 if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
3956 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3957 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3958 getRoot(), LabelID));
3963 case Intrinsic::dbg_region_end: {
3964 DwarfWriter *DW = DAG.getDwarfWriter();
3965 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3966 if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
3968 MachineFunction &MF = DAG.getMachineFunction();
3969 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3971 Subprogram.getLinkageName(SPName);
3973 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
3974 // This is end of inlined function. Debugging information for
3975 // inlined function is not handled yet (only supported by FastISel).
3977 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3979 // Returned ID is 0 if this is unbalanced "end of inlined
3980 // scope". This could happen if optimizer eats dbg intrinsics
3981 // or "beginning of inlined scope" is not recoginized due to
3982 // missing location info. In such cases, do ignore this region.end.
3983 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3990 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3991 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3992 getRoot(), LabelID));
3997 case Intrinsic::dbg_func_start: {
3998 DwarfWriter *DW = DAG.getDwarfWriter();
4000 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
4001 Value *SP = FSI.getSubprogram();
4002 if (SP && DW->ValidDebugInfo(SP, Fast)) {
4003 MachineFunction &MF = DAG.getMachineFunction();
4005 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
4006 // (most?) gdb expects.
4007 DebugLoc PrevLoc = CurDebugLoc;
4008 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4009 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4010 std::string Dir, FN;
4011 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4012 CompileUnit.getFilename(FN));
4014 if (!Subprogram.describes(MF.getFunction())) {
4015 // This is a beginning of an inlined function.
4017 // If llvm.dbg.func.start is seen in a new block before any
4018 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
4019 // FIXME : Why DebugLoc is reset at the beginning of each block ?
4020 if (PrevLoc.isUnknown())
4023 // Record the source line.
4024 unsigned Line = Subprogram.getLineNumber();
4025 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
4026 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4028 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
4029 getRoot(), LabelID));
4030 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
4031 DW->RecordInlinedFnStart(&FSI, Subprogram, LabelID,
4036 // Record the source line.
4037 unsigned Line = Subprogram.getLineNumber();
4038 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4039 DW->RecordSourceLine(Line, 0, SrcFile);
4040 // llvm.dbg.func_start also defines beginning of function scope.
4041 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
4044 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4047 Subprogram.getLinkageName(SPName);
4049 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
4050 // This is beginning of inlined function. Debugging information for
4051 // inlined function is not handled yet (only supported by FastISel).
4055 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
4056 // what (most?) gdb expects.
4057 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4058 std::string Dir, FN;
4059 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4060 CompileUnit.getFilename(FN));
4062 // Record the source line but does not create a label for the normal
4063 // function start. It will be emitted at asm emission time. However,
4064 // create a label if this is a beginning of inlined function.
4065 unsigned Line = Subprogram.getLineNumber();
4066 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4067 // FIXME - Start new region because llvm.dbg.func_start also defines
4068 // beginning of function scope.
4074 case Intrinsic::dbg_declare: {
4076 DwarfWriter *DW = DAG.getDwarfWriter();
4077 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4078 Value *Variable = DI.getVariable();
4079 if (DW && DW->ValidDebugInfo(Variable, Fast))
4080 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
4081 getValue(DI.getAddress()), getValue(Variable)));
4083 // FIXME: Do something sensible here when we support debug declare.
4087 case Intrinsic::eh_exception: {
4088 if (!CurMBB->isLandingPad()) {
4089 // FIXME: Mark exception register as live in. Hack for PR1508.
4090 unsigned Reg = TLI.getExceptionAddressRegister();
4091 if (Reg) CurMBB->addLiveIn(Reg);
4093 // Insert the EXCEPTIONADDR instruction.
4094 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4096 Ops[0] = DAG.getRoot();
4097 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4099 DAG.setRoot(Op.getValue(1));
4103 case Intrinsic::eh_selector_i32:
4104 case Intrinsic::eh_selector_i64: {
4105 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4106 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4107 MVT::i32 : MVT::i64);
4110 if (CurMBB->isLandingPad())
4111 AddCatchInfo(I, MMI, CurMBB);
4114 FuncInfo.CatchInfoLost.insert(&I);
4116 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4117 unsigned Reg = TLI.getExceptionSelectorRegister();
4118 if (Reg) CurMBB->addLiveIn(Reg);
4121 // Insert the EHSELECTION instruction.
4122 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4124 Ops[0] = getValue(I.getOperand(1));
4126 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4128 DAG.setRoot(Op.getValue(1));
4130 setValue(&I, DAG.getConstant(0, VT));
4136 case Intrinsic::eh_typeid_for_i32:
4137 case Intrinsic::eh_typeid_for_i64: {
4138 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4139 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4140 MVT::i32 : MVT::i64);
4143 // Find the type id for the given typeinfo.
4144 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4146 unsigned TypeID = MMI->getTypeIDFor(GV);
4147 setValue(&I, DAG.getConstant(TypeID, VT));
4149 // Return something different to eh_selector.
4150 setValue(&I, DAG.getConstant(1, VT));
4156 case Intrinsic::eh_return_i32:
4157 case Intrinsic::eh_return_i64:
4158 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4159 MMI->setCallsEHReturn(true);
4160 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4163 getValue(I.getOperand(1)),
4164 getValue(I.getOperand(2))));
4166 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4170 case Intrinsic::eh_unwind_init:
4171 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4172 MMI->setCallsUnwindInit(true);
4177 case Intrinsic::eh_dwarf_cfa: {
4178 MVT VT = getValue(I.getOperand(1)).getValueType();
4180 if (VT.bitsGT(TLI.getPointerTy()))
4181 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4182 TLI.getPointerTy(), getValue(I.getOperand(1)));
4184 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4185 TLI.getPointerTy(), getValue(I.getOperand(1)));
4187 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4189 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4190 TLI.getPointerTy()),
4192 setValue(&I, DAG.getNode(ISD::ADD, dl,
4194 DAG.getNode(ISD::FRAMEADDR, dl,
4197 TLI.getPointerTy())),
4202 case Intrinsic::convertff:
4203 case Intrinsic::convertfsi:
4204 case Intrinsic::convertfui:
4205 case Intrinsic::convertsif:
4206 case Intrinsic::convertuif:
4207 case Intrinsic::convertss:
4208 case Intrinsic::convertsu:
4209 case Intrinsic::convertus:
4210 case Intrinsic::convertuu: {
4211 ISD::CvtCode Code = ISD::CVT_INVALID;
4212 switch (Intrinsic) {
4213 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4214 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4215 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4216 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4217 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4218 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4219 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4220 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4221 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4223 MVT DestVT = TLI.getValueType(I.getType());
4224 Value* Op1 = I.getOperand(1);
4225 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4226 DAG.getValueType(DestVT),
4227 DAG.getValueType(getValue(Op1).getValueType()),
4228 getValue(I.getOperand(2)),
4229 getValue(I.getOperand(3)),
4234 case Intrinsic::sqrt:
4235 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4236 getValue(I.getOperand(1)).getValueType(),
4237 getValue(I.getOperand(1))));
4239 case Intrinsic::powi:
4240 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4241 getValue(I.getOperand(1)).getValueType(),
4242 getValue(I.getOperand(1)),
4243 getValue(I.getOperand(2))));
4245 case Intrinsic::sin:
4246 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4247 getValue(I.getOperand(1)).getValueType(),
4248 getValue(I.getOperand(1))));
4250 case Intrinsic::cos:
4251 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4252 getValue(I.getOperand(1)).getValueType(),
4253 getValue(I.getOperand(1))));
4255 case Intrinsic::log:
4258 case Intrinsic::log2:
4261 case Intrinsic::log10:
4264 case Intrinsic::exp:
4267 case Intrinsic::exp2:
4270 case Intrinsic::pow:
4273 case Intrinsic::pcmarker: {
4274 SDValue Tmp = getValue(I.getOperand(1));
4275 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4278 case Intrinsic::readcyclecounter: {
4279 SDValue Op = getRoot();
4280 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4281 DAG.getVTList(MVT::i64, MVT::Other),
4284 DAG.setRoot(Tmp.getValue(1));
4287 case Intrinsic::part_select: {
4288 // Currently not implemented: just abort
4289 assert(0 && "part_select intrinsic not implemented");
4292 case Intrinsic::part_set: {
4293 // Currently not implemented: just abort
4294 assert(0 && "part_set intrinsic not implemented");
4297 case Intrinsic::bswap:
4298 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4299 getValue(I.getOperand(1)).getValueType(),
4300 getValue(I.getOperand(1))));
4302 case Intrinsic::cttz: {
4303 SDValue Arg = getValue(I.getOperand(1));
4304 MVT Ty = Arg.getValueType();
4305 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4306 setValue(&I, result);
4309 case Intrinsic::ctlz: {
4310 SDValue Arg = getValue(I.getOperand(1));
4311 MVT Ty = Arg.getValueType();
4312 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4313 setValue(&I, result);
4316 case Intrinsic::ctpop: {
4317 SDValue Arg = getValue(I.getOperand(1));
4318 MVT Ty = Arg.getValueType();
4319 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4320 setValue(&I, result);
4323 case Intrinsic::stacksave: {
4324 SDValue Op = getRoot();
4325 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4326 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4328 DAG.setRoot(Tmp.getValue(1));
4331 case Intrinsic::stackrestore: {
4332 SDValue Tmp = getValue(I.getOperand(1));
4333 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4336 case Intrinsic::stackprotector: {
4337 // Emit code into the DAG to store the stack guard onto the stack.
4338 MachineFunction &MF = DAG.getMachineFunction();
4339 MachineFrameInfo *MFI = MF.getFrameInfo();
4340 MVT PtrTy = TLI.getPointerTy();
4342 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4343 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4345 int FI = FuncInfo.StaticAllocaMap[Slot];
4346 MFI->setStackProtectorIndex(FI);
4348 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4350 // Store the stack protector onto the stack.
4351 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4352 PseudoSourceValue::getFixedStack(FI),
4354 setValue(&I, Result);
4355 DAG.setRoot(Result);
4358 case Intrinsic::var_annotation:
4359 // Discard annotate attributes
4362 case Intrinsic::init_trampoline: {
4363 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4367 Ops[1] = getValue(I.getOperand(1));
4368 Ops[2] = getValue(I.getOperand(2));
4369 Ops[3] = getValue(I.getOperand(3));
4370 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4371 Ops[5] = DAG.getSrcValue(F);
4373 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4374 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4378 DAG.setRoot(Tmp.getValue(1));
4382 case Intrinsic::gcroot:
4384 Value *Alloca = I.getOperand(1);
4385 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4387 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4388 GFI->addStackRoot(FI->getIndex(), TypeMap);
4392 case Intrinsic::gcread:
4393 case Intrinsic::gcwrite:
4394 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4397 case Intrinsic::flt_rounds: {
4398 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4402 case Intrinsic::trap: {
4403 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4407 case Intrinsic::uadd_with_overflow:
4408 return implVisitAluOverflow(I, ISD::UADDO);
4409 case Intrinsic::sadd_with_overflow:
4410 return implVisitAluOverflow(I, ISD::SADDO);
4411 case Intrinsic::usub_with_overflow:
4412 return implVisitAluOverflow(I, ISD::USUBO);
4413 case Intrinsic::ssub_with_overflow:
4414 return implVisitAluOverflow(I, ISD::SSUBO);
4415 case Intrinsic::umul_with_overflow:
4416 return implVisitAluOverflow(I, ISD::UMULO);
4417 case Intrinsic::smul_with_overflow:
4418 return implVisitAluOverflow(I, ISD::SMULO);
4420 case Intrinsic::prefetch: {
4423 Ops[1] = getValue(I.getOperand(1));
4424 Ops[2] = getValue(I.getOperand(2));
4425 Ops[3] = getValue(I.getOperand(3));
4426 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4430 case Intrinsic::memory_barrier: {
4433 for (int x = 1; x < 6; ++x)
4434 Ops[x] = getValue(I.getOperand(x));
4436 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4439 case Intrinsic::atomic_cmp_swap: {
4440 SDValue Root = getRoot();
4442 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4443 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4445 getValue(I.getOperand(1)),
4446 getValue(I.getOperand(2)),
4447 getValue(I.getOperand(3)),
4450 DAG.setRoot(L.getValue(1));
4453 case Intrinsic::atomic_load_add:
4454 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4455 case Intrinsic::atomic_load_sub:
4456 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4457 case Intrinsic::atomic_load_or:
4458 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4459 case Intrinsic::atomic_load_xor:
4460 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4461 case Intrinsic::atomic_load_and:
4462 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4463 case Intrinsic::atomic_load_nand:
4464 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4465 case Intrinsic::atomic_load_max:
4466 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4467 case Intrinsic::atomic_load_min:
4468 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4469 case Intrinsic::atomic_load_umin:
4470 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4471 case Intrinsic::atomic_load_umax:
4472 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4473 case Intrinsic::atomic_swap:
4474 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4479 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4481 MachineBasicBlock *LandingPad) {
4482 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4483 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4484 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4485 unsigned BeginLabel = 0, EndLabel = 0;
4487 TargetLowering::ArgListTy Args;
4488 TargetLowering::ArgListEntry Entry;
4489 Args.reserve(CS.arg_size());
4490 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4492 SDValue ArgNode = getValue(*i);
4493 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4495 unsigned attrInd = i - CS.arg_begin() + 1;
4496 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4497 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4498 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4499 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4500 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4501 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4502 Entry.Alignment = CS.getParamAlignment(attrInd);
4503 Args.push_back(Entry);
4506 if (LandingPad && MMI) {
4507 // Insert a label before the invoke call to mark the try range. This can be
4508 // used to detect deletion of the invoke via the MachineModuleInfo.
4509 BeginLabel = MMI->NextLabelID();
4510 // Both PendingLoads and PendingExports must be flushed here;
4511 // this call might not return.
4513 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4514 getControlRoot(), BeginLabel));
4517 std::pair<SDValue,SDValue> Result =
4518 TLI.LowerCallTo(getRoot(), CS.getType(),
4519 CS.paramHasAttr(0, Attribute::SExt),
4520 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4521 CS.paramHasAttr(0, Attribute::InReg),
4522 CS.getCallingConv(),
4523 IsTailCall && PerformTailCallOpt,
4524 Callee, Args, DAG, getCurDebugLoc());
4525 if (CS.getType() != Type::VoidTy)
4526 setValue(CS.getInstruction(), Result.first);
4527 DAG.setRoot(Result.second);
4529 if (LandingPad && MMI) {
4530 // Insert a label at the end of the invoke call to mark the try range. This
4531 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4532 EndLabel = MMI->NextLabelID();
4533 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4534 getRoot(), EndLabel));
4536 // Inform MachineModuleInfo of range.
4537 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4542 void SelectionDAGLowering::visitCall(CallInst &I) {
4543 const char *RenameFn = 0;
4544 if (Function *F = I.getCalledFunction()) {
4545 if (F->isDeclaration()) {
4546 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4548 if (unsigned IID = II->getIntrinsicID(F)) {
4549 RenameFn = visitIntrinsicCall(I, IID);
4554 if (unsigned IID = F->getIntrinsicID()) {
4555 RenameFn = visitIntrinsicCall(I, IID);
4561 // Check for well-known libc/libm calls. If the function is internal, it
4562 // can't be a library call.
4563 unsigned NameLen = F->getNameLen();
4564 if (!F->hasLocalLinkage() && NameLen) {
4565 const char *NameStr = F->getNameStart();
4566 if (NameStr[0] == 'c' &&
4567 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4568 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4569 if (I.getNumOperands() == 3 && // Basic sanity checks.
4570 I.getOperand(1)->getType()->isFloatingPoint() &&
4571 I.getType() == I.getOperand(1)->getType() &&
4572 I.getType() == I.getOperand(2)->getType()) {
4573 SDValue LHS = getValue(I.getOperand(1));
4574 SDValue RHS = getValue(I.getOperand(2));
4575 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4576 LHS.getValueType(), LHS, RHS));
4579 } else if (NameStr[0] == 'f' &&
4580 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4581 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4582 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4583 if (I.getNumOperands() == 2 && // Basic sanity checks.
4584 I.getOperand(1)->getType()->isFloatingPoint() &&
4585 I.getType() == I.getOperand(1)->getType()) {
4586 SDValue Tmp = getValue(I.getOperand(1));
4587 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4588 Tmp.getValueType(), Tmp));
4591 } else if (NameStr[0] == 's' &&
4592 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4593 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4594 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4595 if (I.getNumOperands() == 2 && // Basic sanity checks.
4596 I.getOperand(1)->getType()->isFloatingPoint() &&
4597 I.getType() == I.getOperand(1)->getType()) {
4598 SDValue Tmp = getValue(I.getOperand(1));
4599 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4600 Tmp.getValueType(), Tmp));
4603 } else if (NameStr[0] == 'c' &&
4604 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4605 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4606 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4607 if (I.getNumOperands() == 2 && // Basic sanity checks.
4608 I.getOperand(1)->getType()->isFloatingPoint() &&
4609 I.getType() == I.getOperand(1)->getType()) {
4610 SDValue Tmp = getValue(I.getOperand(1));
4611 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4612 Tmp.getValueType(), Tmp));
4617 } else if (isa<InlineAsm>(I.getOperand(0))) {
4624 Callee = getValue(I.getOperand(0));
4626 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4628 LowerCallTo(&I, Callee, I.isTailCall());
4632 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4633 /// this value and returns the result as a ValueVT value. This uses
4634 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4635 /// If the Flag pointer is NULL, no flag is used.
4636 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4638 SDValue *Flag) const {
4639 // Assemble the legal parts into the final values.
4640 SmallVector<SDValue, 4> Values(ValueVTs.size());
4641 SmallVector<SDValue, 8> Parts;
4642 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4643 // Copy the legal parts from the registers.
4644 MVT ValueVT = ValueVTs[Value];
4645 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4646 MVT RegisterVT = RegVTs[Value];
4648 Parts.resize(NumRegs);
4649 for (unsigned i = 0; i != NumRegs; ++i) {
4652 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4654 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4655 *Flag = P.getValue(2);
4657 Chain = P.getValue(1);
4659 // If the source register was virtual and if we know something about it,
4660 // add an assert node.
4661 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4662 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4663 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4664 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4665 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4666 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4668 unsigned RegSize = RegisterVT.getSizeInBits();
4669 unsigned NumSignBits = LOI.NumSignBits;
4670 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4672 // FIXME: We capture more information than the dag can represent. For
4673 // now, just use the tightest assertzext/assertsext possible.
4675 MVT FromVT(MVT::Other);
4676 if (NumSignBits == RegSize)
4677 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4678 else if (NumZeroBits >= RegSize-1)
4679 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4680 else if (NumSignBits > RegSize-8)
4681 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4682 else if (NumZeroBits >= RegSize-8)
4683 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4684 else if (NumSignBits > RegSize-16)
4685 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4686 else if (NumZeroBits >= RegSize-16)
4687 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4688 else if (NumSignBits > RegSize-32)
4689 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4690 else if (NumZeroBits >= RegSize-32)
4691 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4693 if (FromVT != MVT::Other) {
4694 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4695 RegisterVT, P, DAG.getValueType(FromVT));
4704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4705 NumRegs, RegisterVT, ValueVT);
4710 return DAG.getNode(ISD::MERGE_VALUES, dl,
4711 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4712 &Values[0], ValueVTs.size());
4715 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4716 /// specified value into the registers specified by this object. This uses
4717 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4718 /// If the Flag pointer is NULL, no flag is used.
4719 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4720 SDValue &Chain, SDValue *Flag) const {
4721 // Get the list of the values's legal parts.
4722 unsigned NumRegs = Regs.size();
4723 SmallVector<SDValue, 8> Parts(NumRegs);
4724 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4725 MVT ValueVT = ValueVTs[Value];
4726 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4727 MVT RegisterVT = RegVTs[Value];
4729 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4730 &Parts[Part], NumParts, RegisterVT);
4734 // Copy the parts into the registers.
4735 SmallVector<SDValue, 8> Chains(NumRegs);
4736 for (unsigned i = 0; i != NumRegs; ++i) {
4739 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4741 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4742 *Flag = Part.getValue(1);
4744 Chains[i] = Part.getValue(0);
4747 if (NumRegs == 1 || Flag)
4748 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4749 // flagged to it. That is the CopyToReg nodes and the user are considered
4750 // a single scheduling unit. If we create a TokenFactor and return it as
4751 // chain, then the TokenFactor is both a predecessor (operand) of the
4752 // user as well as a successor (the TF operands are flagged to the user).
4753 // c1, f1 = CopyToReg
4754 // c2, f2 = CopyToReg
4755 // c3 = TokenFactor c1, c2
4758 Chain = Chains[NumRegs-1];
4760 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4763 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4764 /// operand list. This adds the code marker and includes the number of
4765 /// values added into it.
4766 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4767 bool HasMatching,unsigned MatchingIdx,
4769 std::vector<SDValue> &Ops) const {
4770 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4771 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4772 unsigned Flag = Code | (Regs.size() << 3);
4774 Flag |= 0x80000000 | (MatchingIdx << 16);
4775 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4776 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4777 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4778 MVT RegisterVT = RegVTs[Value];
4779 for (unsigned i = 0; i != NumRegs; ++i) {
4780 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4781 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4786 /// isAllocatableRegister - If the specified register is safe to allocate,
4787 /// i.e. it isn't a stack pointer or some other special register, return the
4788 /// register class for the register. Otherwise, return null.
4789 static const TargetRegisterClass *
4790 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4791 const TargetLowering &TLI,
4792 const TargetRegisterInfo *TRI) {
4793 MVT FoundVT = MVT::Other;
4794 const TargetRegisterClass *FoundRC = 0;
4795 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4796 E = TRI->regclass_end(); RCI != E; ++RCI) {
4797 MVT ThisVT = MVT::Other;
4799 const TargetRegisterClass *RC = *RCI;
4800 // If none of the the value types for this register class are valid, we
4801 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4802 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4804 if (TLI.isTypeLegal(*I)) {
4805 // If we have already found this register in a different register class,
4806 // choose the one with the largest VT specified. For example, on
4807 // PowerPC, we favor f64 register classes over f32.
4808 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4815 if (ThisVT == MVT::Other) continue;
4817 // NOTE: This isn't ideal. In particular, this might allocate the
4818 // frame pointer in functions that need it (due to them not being taken
4819 // out of allocation, because a variable sized allocation hasn't been seen
4820 // yet). This is a slight code pessimization, but should still work.
4821 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4822 E = RC->allocation_order_end(MF); I != E; ++I)
4824 // We found a matching register class. Keep looking at others in case
4825 // we find one with larger registers that this physreg is also in.
4836 /// AsmOperandInfo - This contains information for each constraint that we are
4838 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4839 public TargetLowering::AsmOperandInfo {
4841 /// CallOperand - If this is the result output operand or a clobber
4842 /// this is null, otherwise it is the incoming operand to the CallInst.
4843 /// This gets modified as the asm is processed.
4844 SDValue CallOperand;
4846 /// AssignedRegs - If this is a register or register class operand, this
4847 /// contains the set of register corresponding to the operand.
4848 RegsForValue AssignedRegs;
4850 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4851 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4854 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4855 /// busy in OutputRegs/InputRegs.
4856 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4857 std::set<unsigned> &OutputRegs,
4858 std::set<unsigned> &InputRegs,
4859 const TargetRegisterInfo &TRI) const {
4861 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4862 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4865 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4866 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4870 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4871 /// corresponds to. If there is no Value* for this operand, it returns
4873 MVT getCallOperandValMVT(const TargetLowering &TLI,
4874 const TargetData *TD) const {
4875 if (CallOperandVal == 0) return MVT::Other;
4877 if (isa<BasicBlock>(CallOperandVal))
4878 return TLI.getPointerTy();
4880 const llvm::Type *OpTy = CallOperandVal->getType();
4882 // If this is an indirect operand, the operand is a pointer to the
4885 OpTy = cast<PointerType>(OpTy)->getElementType();
4887 // If OpTy is not a single value, it may be a struct/union that we
4888 // can tile with integers.
4889 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4890 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4899 OpTy = IntegerType::get(BitSize);
4904 return TLI.getValueType(OpTy, true);
4908 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4910 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4911 const TargetRegisterInfo &TRI) {
4912 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4914 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4915 for (; *Aliases; ++Aliases)
4916 Regs.insert(*Aliases);
4919 } // end llvm namespace.
4922 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4923 /// specified operand. We prefer to assign virtual registers, to allow the
4924 /// register allocator handle the assignment process. However, if the asm uses
4925 /// features that we can't model on machineinstrs, we have SDISel do the
4926 /// allocation. This produces generally horrible, but correct, code.
4928 /// OpInfo describes the operand.
4929 /// Input and OutputRegs are the set of already allocated physical registers.
4931 void SelectionDAGLowering::
4932 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4933 std::set<unsigned> &OutputRegs,
4934 std::set<unsigned> &InputRegs) {
4935 // Compute whether this value requires an input register, an output register,
4937 bool isOutReg = false;
4938 bool isInReg = false;
4939 switch (OpInfo.Type) {
4940 case InlineAsm::isOutput:
4943 // If there is an input constraint that matches this, we need to reserve
4944 // the input register so no other inputs allocate to it.
4945 isInReg = OpInfo.hasMatchingInput();
4947 case InlineAsm::isInput:
4951 case InlineAsm::isClobber:
4958 MachineFunction &MF = DAG.getMachineFunction();
4959 SmallVector<unsigned, 4> Regs;
4961 // If this is a constraint for a single physreg, or a constraint for a
4962 // register class, find it.
4963 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4964 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4965 OpInfo.ConstraintVT);
4967 unsigned NumRegs = 1;
4968 if (OpInfo.ConstraintVT != MVT::Other) {
4969 // If this is a FP input in an integer register (or visa versa) insert a bit
4970 // cast of the input value. More generally, handle any case where the input
4971 // value disagrees with the register class we plan to stick this in.
4972 if (OpInfo.Type == InlineAsm::isInput &&
4973 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4974 // Try to convert to the first MVT that the reg class contains. If the
4975 // types are identical size, use a bitcast to convert (e.g. two differing
4977 MVT RegVT = *PhysReg.second->vt_begin();
4978 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4979 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4980 RegVT, OpInfo.CallOperand);
4981 OpInfo.ConstraintVT = RegVT;
4982 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4983 // If the input is a FP value and we want it in FP registers, do a
4984 // bitcast to the corresponding integer type. This turns an f64 value
4985 // into i64, which can be passed with two i32 values on a 32-bit
4987 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4988 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4989 RegVT, OpInfo.CallOperand);
4990 OpInfo.ConstraintVT = RegVT;
4994 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4998 MVT ValueVT = OpInfo.ConstraintVT;
5000 // If this is a constraint for a specific physical register, like {r17},
5002 if (unsigned AssignedReg = PhysReg.first) {
5003 const TargetRegisterClass *RC = PhysReg.second;
5004 if (OpInfo.ConstraintVT == MVT::Other)
5005 ValueVT = *RC->vt_begin();
5007 // Get the actual register value type. This is important, because the user
5008 // may have asked for (e.g.) the AX register in i32 type. We need to
5009 // remember that AX is actually i16 to get the right extension.
5010 RegVT = *RC->vt_begin();
5012 // This is a explicit reference to a physical register.
5013 Regs.push_back(AssignedReg);
5015 // If this is an expanded reference, add the rest of the regs to Regs.
5017 TargetRegisterClass::iterator I = RC->begin();
5018 for (; *I != AssignedReg; ++I)
5019 assert(I != RC->end() && "Didn't find reg!");
5021 // Already added the first reg.
5023 for (; NumRegs; --NumRegs, ++I) {
5024 assert(I != RC->end() && "Ran out of registers to allocate!");
5028 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5029 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5030 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5034 // Otherwise, if this was a reference to an LLVM register class, create vregs
5035 // for this reference.
5036 if (const TargetRegisterClass *RC = PhysReg.second) {
5037 RegVT = *RC->vt_begin();
5038 if (OpInfo.ConstraintVT == MVT::Other)
5041 // Create the appropriate number of virtual registers.
5042 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5043 for (; NumRegs; --NumRegs)
5044 Regs.push_back(RegInfo.createVirtualRegister(RC));
5046 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5050 // This is a reference to a register class that doesn't directly correspond
5051 // to an LLVM register class. Allocate NumRegs consecutive, available,
5052 // registers from the class.
5053 std::vector<unsigned> RegClassRegs
5054 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5055 OpInfo.ConstraintVT);
5057 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5058 unsigned NumAllocated = 0;
5059 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5060 unsigned Reg = RegClassRegs[i];
5061 // See if this register is available.
5062 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5063 (isInReg && InputRegs.count(Reg))) { // Already used.
5064 // Make sure we find consecutive registers.
5069 // Check to see if this register is allocatable (i.e. don't give out the
5071 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5072 if (!RC) { // Couldn't allocate this register.
5073 // Reset NumAllocated to make sure we return consecutive registers.
5078 // Okay, this register is good, we can use it.
5081 // If we allocated enough consecutive registers, succeed.
5082 if (NumAllocated == NumRegs) {
5083 unsigned RegStart = (i-NumAllocated)+1;
5084 unsigned RegEnd = i+1;
5085 // Mark all of the allocated registers used.
5086 for (unsigned i = RegStart; i != RegEnd; ++i)
5087 Regs.push_back(RegClassRegs[i]);
5089 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5090 OpInfo.ConstraintVT);
5091 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5096 // Otherwise, we couldn't allocate enough registers for this.
5099 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5100 /// processed uses a memory 'm' constraint.
5102 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5103 const TargetLowering &TLI) {
5104 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5105 InlineAsm::ConstraintInfo &CI = CInfos[i];
5106 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5107 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5108 if (CType == TargetLowering::C_Memory)
5116 /// visitInlineAsm - Handle a call to an InlineAsm object.
5118 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5119 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5121 /// ConstraintOperands - Information about all of the constraints.
5122 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5124 // We won't need to flush pending loads if this asm doesn't touch
5125 // memory and is nonvolatile.
5126 SDValue Chain = IA->hasSideEffects() ? getRoot() : DAG.getRoot();
5129 std::set<unsigned> OutputRegs, InputRegs;
5131 // Do a prepass over the constraints, canonicalizing them, and building up the
5132 // ConstraintOperands list.
5133 std::vector<InlineAsm::ConstraintInfo>
5134 ConstraintInfos = IA->ParseConstraints();
5136 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5137 // Flush pending loads if this touches memory (includes clobbering it).
5138 // It's possible this is overly conservative.
5142 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5143 unsigned ResNo = 0; // ResNo - The result number of the next output.
5144 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5145 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5146 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5148 MVT OpVT = MVT::Other;
5150 // Compute the value type for each operand.
5151 switch (OpInfo.Type) {
5152 case InlineAsm::isOutput:
5153 // Indirect outputs just consume an argument.
5154 if (OpInfo.isIndirect) {
5155 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5159 // The return value of the call is this value. As such, there is no
5160 // corresponding argument.
5161 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5162 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5163 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5165 assert(ResNo == 0 && "Asm only has one result!");
5166 OpVT = TLI.getValueType(CS.getType());
5170 case InlineAsm::isInput:
5171 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5173 case InlineAsm::isClobber:
5178 // If this is an input or an indirect output, process the call argument.
5179 // BasicBlocks are labels, currently appearing only in asm's.
5180 if (OpInfo.CallOperandVal) {
5181 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5182 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5184 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5187 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5190 OpInfo.ConstraintVT = OpVT;
5193 // Second pass over the constraints: compute which constraint option to use
5194 // and assign registers to constraints that want a specific physreg.
5195 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5196 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5198 // If this is an output operand with a matching input operand, look up the
5199 // matching input. If their types mismatch, e.g. one is an integer, the
5200 // other is floating point, or their sizes are different, flag it as an
5202 if (OpInfo.hasMatchingInput()) {
5203 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5204 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5205 if ((OpInfo.ConstraintVT.isInteger() !=
5206 Input.ConstraintVT.isInteger()) ||
5207 (OpInfo.ConstraintVT.getSizeInBits() !=
5208 Input.ConstraintVT.getSizeInBits())) {
5209 cerr << "llvm: error: Unsupported asm: input constraint with a "
5210 << "matching output constraint of incompatible type!\n";
5213 Input.ConstraintVT = OpInfo.ConstraintVT;
5217 // Compute the constraint code and ConstraintType to use.
5218 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5220 // If this is a memory input, and if the operand is not indirect, do what we
5221 // need to to provide an address for the memory input.
5222 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5223 !OpInfo.isIndirect) {
5224 assert(OpInfo.Type == InlineAsm::isInput &&
5225 "Can only indirectify direct input operands!");
5227 // Memory operands really want the address of the value. If we don't have
5228 // an indirect input, put it in the constpool if we can, otherwise spill
5229 // it to a stack slot.
5231 // If the operand is a float, integer, or vector constant, spill to a
5232 // constant pool entry to get its address.
5233 Value *OpVal = OpInfo.CallOperandVal;
5234 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5235 isa<ConstantVector>(OpVal)) {
5236 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5237 TLI.getPointerTy());
5239 // Otherwise, create a stack slot and emit a store to it before the
5241 const Type *Ty = OpVal->getType();
5242 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5243 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5244 MachineFunction &MF = DAG.getMachineFunction();
5245 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5246 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5247 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5248 OpInfo.CallOperand, StackSlot, NULL, 0);
5249 OpInfo.CallOperand = StackSlot;
5252 // There is no longer a Value* corresponding to this operand.
5253 OpInfo.CallOperandVal = 0;
5254 // It is now an indirect operand.
5255 OpInfo.isIndirect = true;
5258 // If this constraint is for a specific register, allocate it before
5260 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5261 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5263 ConstraintInfos.clear();
5266 // Second pass - Loop over all of the operands, assigning virtual or physregs
5267 // to register class operands.
5268 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5269 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5271 // C_Register operands have already been allocated, Other/Memory don't need
5273 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5274 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5277 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5278 std::vector<SDValue> AsmNodeOperands;
5279 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5280 AsmNodeOperands.push_back(
5281 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5284 // Loop over all of the inputs, copying the operand values into the
5285 // appropriate registers and processing the output regs.
5286 RegsForValue RetValRegs;
5288 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5289 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5291 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5292 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5294 switch (OpInfo.Type) {
5295 case InlineAsm::isOutput: {
5296 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5297 OpInfo.ConstraintType != TargetLowering::C_Register) {
5298 // Memory output, or 'other' output (e.g. 'X' constraint).
5299 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5301 // Add information to the INLINEASM node to know about this output.
5302 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5303 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5304 TLI.getPointerTy()));
5305 AsmNodeOperands.push_back(OpInfo.CallOperand);
5309 // Otherwise, this is a register or register class output.
5311 // Copy the output from the appropriate register. Find a register that
5313 if (OpInfo.AssignedRegs.Regs.empty()) {
5314 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5315 << OpInfo.ConstraintCode << "'!\n";
5319 // If this is an indirect operand, store through the pointer after the
5321 if (OpInfo.isIndirect) {
5322 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5323 OpInfo.CallOperandVal));
5325 // This is the result value of the call.
5326 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5327 // Concatenate this output onto the outputs list.
5328 RetValRegs.append(OpInfo.AssignedRegs);
5331 // Add information to the INLINEASM node to know that this register is
5333 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5334 6 /* EARLYCLOBBER REGDEF */ :
5338 DAG, AsmNodeOperands);
5341 case InlineAsm::isInput: {
5342 SDValue InOperandVal = OpInfo.CallOperand;
5344 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5345 // If this is required to match an output register we have already set,
5346 // just use its register.
5347 unsigned OperandNo = OpInfo.getMatchedOperand();
5349 // Scan until we find the definition we already emitted of this operand.
5350 // When we find it, create a RegsForValue operand.
5351 unsigned CurOp = 2; // The first operand.
5352 for (; OperandNo; --OperandNo) {
5353 // Advance to the next operand.
5355 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5356 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5357 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5358 (OpFlag & 7) == 4 /*MEM*/) &&
5359 "Skipped past definitions?");
5360 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5364 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5365 if ((OpFlag & 7) == 2 /*REGDEF*/
5366 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5367 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5368 RegsForValue MatchedRegs;
5369 MatchedRegs.TLI = &TLI;
5370 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5371 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5372 MatchedRegs.RegVTs.push_back(RegVT);
5373 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5374 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5377 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5379 // Use the produced MatchedRegs object to
5380 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5382 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5383 true, OpInfo.getMatchedOperand(),
5384 DAG, AsmNodeOperands);
5387 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5388 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5389 "Unexpected number of operands");
5390 // Add information to the INLINEASM node to know about this input.
5391 // See InlineAsm.h isUseOperandTiedToDef.
5392 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5393 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5394 TLI.getPointerTy()));
5395 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5400 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5401 assert(!OpInfo.isIndirect &&
5402 "Don't know how to handle indirect other inputs yet!");
5404 std::vector<SDValue> Ops;
5405 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5406 hasMemory, Ops, DAG);
5408 cerr << "llvm: error: Invalid operand for inline asm constraint '"
5409 << OpInfo.ConstraintCode << "'!\n";
5413 // Add information to the INLINEASM node to know about this input.
5414 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5415 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5416 TLI.getPointerTy()));
5417 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5419 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5420 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5421 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5422 "Memory operands expect pointer values");
5424 // Add information to the INLINEASM node to know about this input.
5425 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5426 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5427 TLI.getPointerTy()));
5428 AsmNodeOperands.push_back(InOperandVal);
5432 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5433 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5434 "Unknown constraint type!");
5435 assert(!OpInfo.isIndirect &&
5436 "Don't know how to handle indirect register inputs yet!");
5438 // Copy the input into the appropriate registers.
5439 if (OpInfo.AssignedRegs.Regs.empty()) {
5440 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5441 << OpInfo.ConstraintCode << "'!\n";
5445 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5448 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5449 DAG, AsmNodeOperands);
5452 case InlineAsm::isClobber: {
5453 // Add the clobbered value to the operand list, so that the register
5454 // allocator is aware that the physreg got clobbered.
5455 if (!OpInfo.AssignedRegs.Regs.empty())
5456 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5457 false, 0, DAG,AsmNodeOperands);
5463 // Finish up input operands.
5464 AsmNodeOperands[0] = Chain;
5465 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5467 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5468 DAG.getVTList(MVT::Other, MVT::Flag),
5469 &AsmNodeOperands[0], AsmNodeOperands.size());
5470 Flag = Chain.getValue(1);
5472 // If this asm returns a register value, copy the result from that register
5473 // and set it as the value of the call.
5474 if (!RetValRegs.Regs.empty()) {
5475 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5478 // FIXME: Why don't we do this for inline asms with MRVs?
5479 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5480 MVT ResultType = TLI.getValueType(CS.getType());
5482 // If any of the results of the inline asm is a vector, it may have the
5483 // wrong width/num elts. This can happen for register classes that can
5484 // contain multiple different value types. The preg or vreg allocated may
5485 // not have the same VT as was expected. Convert it to the right type
5486 // with bit_convert.
5487 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5488 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5491 } else if (ResultType != Val.getValueType() &&
5492 ResultType.isInteger() && Val.getValueType().isInteger()) {
5493 // If a result value was tied to an input value, the computed result may
5494 // have a wider width than the expected result. Extract the relevant
5496 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5499 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5502 setValue(CS.getInstruction(), Val);
5503 // Don't need to use this as a chain in this case.
5504 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5508 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5510 // Process indirect outputs, first output all of the flagged copies out of
5512 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5513 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5514 Value *Ptr = IndirectStoresToEmit[i].second;
5515 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5517 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5520 // Emit the non-flagged stores from the physregs.
5521 SmallVector<SDValue, 8> OutChains;
5522 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5523 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5524 StoresToEmit[i].first,
5525 getValue(StoresToEmit[i].second),
5526 StoresToEmit[i].second, 0));
5527 if (!OutChains.empty())
5528 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5529 &OutChains[0], OutChains.size());
5534 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5535 SDValue Src = getValue(I.getOperand(0));
5537 // Scale up by the type size in the original i32 type width. Various
5538 // mid-level optimizers may make assumptions about demanded bits etc from the
5539 // i32-ness of the optimizer: we do not want to promote to i64 and then
5540 // multiply on 64-bit targets.
5541 // FIXME: Malloc inst should go away: PR715.
5542 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5543 if (ElementSize != 1)
5544 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5545 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5547 MVT IntPtr = TLI.getPointerTy();
5549 if (IntPtr.bitsLT(Src.getValueType()))
5550 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5551 else if (IntPtr.bitsGT(Src.getValueType()))
5552 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5554 TargetLowering::ArgListTy Args;
5555 TargetLowering::ArgListEntry Entry;
5557 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5558 Args.push_back(Entry);
5560 std::pair<SDValue,SDValue> Result =
5561 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5562 CallingConv::C, PerformTailCallOpt,
5563 DAG.getExternalSymbol("malloc", IntPtr),
5564 Args, DAG, getCurDebugLoc());
5565 setValue(&I, Result.first); // Pointers always fit in registers
5566 DAG.setRoot(Result.second);
5569 void SelectionDAGLowering::visitFree(FreeInst &I) {
5570 TargetLowering::ArgListTy Args;
5571 TargetLowering::ArgListEntry Entry;
5572 Entry.Node = getValue(I.getOperand(0));
5573 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5574 Args.push_back(Entry);
5575 MVT IntPtr = TLI.getPointerTy();
5576 std::pair<SDValue,SDValue> Result =
5577 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5578 CallingConv::C, PerformTailCallOpt,
5579 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5581 DAG.setRoot(Result.second);
5584 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5585 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5586 MVT::Other, getRoot(),
5587 getValue(I.getOperand(1)),
5588 DAG.getSrcValue(I.getOperand(1))));
5591 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5592 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5593 getRoot(), getValue(I.getOperand(0)),
5594 DAG.getSrcValue(I.getOperand(0)));
5596 DAG.setRoot(V.getValue(1));
5599 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5600 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5601 MVT::Other, getRoot(),
5602 getValue(I.getOperand(1)),
5603 DAG.getSrcValue(I.getOperand(1))));
5606 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5607 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5608 MVT::Other, getRoot(),
5609 getValue(I.getOperand(1)),
5610 getValue(I.getOperand(2)),
5611 DAG.getSrcValue(I.getOperand(1)),
5612 DAG.getSrcValue(I.getOperand(2))));
5615 /// TargetLowering::LowerArguments - This is the default LowerArguments
5616 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5617 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5618 /// integrated into SDISel.
5619 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5620 SmallVectorImpl<SDValue> &ArgValues,
5622 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5623 SmallVector<SDValue, 3+16> Ops;
5624 Ops.push_back(DAG.getRoot());
5625 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5626 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5628 // Add one result value for each formal argument.
5629 SmallVector<MVT, 16> RetVals;
5631 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5633 SmallVector<MVT, 4> ValueVTs;
5634 ComputeValueVTs(*this, I->getType(), ValueVTs);
5635 for (unsigned Value = 0, NumValues = ValueVTs.size();
5636 Value != NumValues; ++Value) {
5637 MVT VT = ValueVTs[Value];
5638 const Type *ArgTy = VT.getTypeForMVT();
5639 ISD::ArgFlagsTy Flags;
5640 unsigned OriginalAlignment =
5641 getTargetData()->getABITypeAlignment(ArgTy);
5643 if (F.paramHasAttr(j, Attribute::ZExt))
5645 if (F.paramHasAttr(j, Attribute::SExt))
5647 if (F.paramHasAttr(j, Attribute::InReg))
5649 if (F.paramHasAttr(j, Attribute::StructRet))
5651 if (F.paramHasAttr(j, Attribute::ByVal)) {
5653 const PointerType *Ty = cast<PointerType>(I->getType());
5654 const Type *ElementTy = Ty->getElementType();
5655 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5656 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5657 // For ByVal, alignment should be passed from FE. BE will guess if
5658 // this info is not there but there are cases it cannot get right.
5659 if (F.getParamAlignment(j))
5660 FrameAlign = F.getParamAlignment(j);
5661 Flags.setByValAlign(FrameAlign);
5662 Flags.setByValSize(FrameSize);
5664 if (F.paramHasAttr(j, Attribute::Nest))
5666 Flags.setOrigAlign(OriginalAlignment);
5668 MVT RegisterVT = getRegisterType(VT);
5669 unsigned NumRegs = getNumRegisters(VT);
5670 for (unsigned i = 0; i != NumRegs; ++i) {
5671 RetVals.push_back(RegisterVT);
5672 ISD::ArgFlagsTy MyFlags = Flags;
5673 if (NumRegs > 1 && i == 0)
5675 // if it isn't first piece, alignment must be 1
5677 MyFlags.setOrigAlign(1);
5678 Ops.push_back(DAG.getArgFlags(MyFlags));
5683 RetVals.push_back(MVT::Other);
5686 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5687 DAG.getVTList(&RetVals[0], RetVals.size()),
5688 &Ops[0], Ops.size()).getNode();
5690 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5691 // allows exposing the loads that may be part of the argument access to the
5692 // first DAGCombiner pass.
5693 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5695 // The number of results should match up, except that the lowered one may have
5696 // an extra flag result.
5697 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5698 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5699 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5700 && "Lowering produced unexpected number of results!");
5702 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5703 if (Result != TmpRes.getNode() && Result->use_empty()) {
5704 HandleSDNode Dummy(DAG.getRoot());
5705 DAG.RemoveDeadNode(Result);
5708 Result = TmpRes.getNode();
5710 unsigned NumArgRegs = Result->getNumValues() - 1;
5711 DAG.setRoot(SDValue(Result, NumArgRegs));
5713 // Set up the return result vector.
5716 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5718 SmallVector<MVT, 4> ValueVTs;
5719 ComputeValueVTs(*this, I->getType(), ValueVTs);
5720 for (unsigned Value = 0, NumValues = ValueVTs.size();
5721 Value != NumValues; ++Value) {
5722 MVT VT = ValueVTs[Value];
5723 MVT PartVT = getRegisterType(VT);
5725 unsigned NumParts = getNumRegisters(VT);
5726 SmallVector<SDValue, 4> Parts(NumParts);
5727 for (unsigned j = 0; j != NumParts; ++j)
5728 Parts[j] = SDValue(Result, i++);
5730 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5731 if (F.paramHasAttr(Idx, Attribute::SExt))
5732 AssertOp = ISD::AssertSext;
5733 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5734 AssertOp = ISD::AssertZext;
5736 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5737 PartVT, VT, AssertOp));
5740 assert(i == NumArgRegs && "Argument register count mismatch!");
5744 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5745 /// implementation, which just inserts an ISD::CALL node, which is later custom
5746 /// lowered by the target to something concrete. FIXME: When all targets are
5747 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5748 std::pair<SDValue, SDValue>
5749 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5750 bool RetSExt, bool RetZExt, bool isVarArg,
5752 unsigned CallingConv, bool isTailCall,
5754 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5755 assert((!isTailCall || PerformTailCallOpt) &&
5756 "isTailCall set when tail-call optimizations are disabled!");
5758 SmallVector<SDValue, 32> Ops;
5759 Ops.push_back(Chain); // Op#0 - Chain
5760 Ops.push_back(Callee);
5762 // Handle all of the outgoing arguments.
5763 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5764 SmallVector<MVT, 4> ValueVTs;
5765 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5766 for (unsigned Value = 0, NumValues = ValueVTs.size();
5767 Value != NumValues; ++Value) {
5768 MVT VT = ValueVTs[Value];
5769 const Type *ArgTy = VT.getTypeForMVT();
5770 SDValue Op = SDValue(Args[i].Node.getNode(),
5771 Args[i].Node.getResNo() + Value);
5772 ISD::ArgFlagsTy Flags;
5773 unsigned OriginalAlignment =
5774 getTargetData()->getABITypeAlignment(ArgTy);
5780 if (Args[i].isInReg)
5784 if (Args[i].isByVal) {
5786 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5787 const Type *ElementTy = Ty->getElementType();
5788 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5789 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5790 // For ByVal, alignment should come from FE. BE will guess if this
5791 // info is not there but there are cases it cannot get right.
5792 if (Args[i].Alignment)
5793 FrameAlign = Args[i].Alignment;
5794 Flags.setByValAlign(FrameAlign);
5795 Flags.setByValSize(FrameSize);
5799 Flags.setOrigAlign(OriginalAlignment);
5801 MVT PartVT = getRegisterType(VT);
5802 unsigned NumParts = getNumRegisters(VT);
5803 SmallVector<SDValue, 4> Parts(NumParts);
5804 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5807 ExtendKind = ISD::SIGN_EXTEND;
5808 else if (Args[i].isZExt)
5809 ExtendKind = ISD::ZERO_EXTEND;
5811 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5813 for (unsigned i = 0; i != NumParts; ++i) {
5814 // if it isn't first piece, alignment must be 1
5815 ISD::ArgFlagsTy MyFlags = Flags;
5816 if (NumParts > 1 && i == 0)
5819 MyFlags.setOrigAlign(1);
5821 Ops.push_back(Parts[i]);
5822 Ops.push_back(DAG.getArgFlags(MyFlags));
5827 // Figure out the result value types. We start by making a list of
5828 // the potentially illegal return value types.
5829 SmallVector<MVT, 4> LoweredRetTys;
5830 SmallVector<MVT, 4> RetTys;
5831 ComputeValueVTs(*this, RetTy, RetTys);
5833 // Then we translate that to a list of legal types.
5834 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5836 MVT RegisterVT = getRegisterType(VT);
5837 unsigned NumRegs = getNumRegisters(VT);
5838 for (unsigned i = 0; i != NumRegs; ++i)
5839 LoweredRetTys.push_back(RegisterVT);
5842 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5844 // Create the CALL node.
5845 SDValue Res = DAG.getCall(CallingConv, dl,
5846 isVarArg, isTailCall, isInreg,
5847 DAG.getVTList(&LoweredRetTys[0],
5848 LoweredRetTys.size()),
5851 Chain = Res.getValue(LoweredRetTys.size() - 1);
5853 // Gather up the call result into a single value.
5854 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5855 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5858 AssertOp = ISD::AssertSext;
5860 AssertOp = ISD::AssertZext;
5862 SmallVector<SDValue, 4> ReturnValues;
5864 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5866 MVT RegisterVT = getRegisterType(VT);
5867 unsigned NumRegs = getNumRegisters(VT);
5868 unsigned RegNoEnd = NumRegs + RegNo;
5869 SmallVector<SDValue, 4> Results;
5870 for (; RegNo != RegNoEnd; ++RegNo)
5871 Results.push_back(Res.getValue(RegNo));
5872 SDValue ReturnValue =
5873 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5875 ReturnValues.push_back(ReturnValue);
5877 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5878 DAG.getVTList(&RetTys[0], RetTys.size()),
5879 &ReturnValues[0], ReturnValues.size());
5882 return std::make_pair(Res, Chain);
5885 void TargetLowering::LowerOperationWrapper(SDNode *N,
5886 SmallVectorImpl<SDValue> &Results,
5887 SelectionDAG &DAG) {
5888 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5890 Results.push_back(Res);
5893 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5894 assert(0 && "LowerOperation not implemented for this target!");
5900 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5901 SDValue Op = getValue(V);
5902 assert((Op.getOpcode() != ISD::CopyFromReg ||
5903 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5904 "Copy from a reg to the same reg!");
5905 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5907 RegsForValue RFV(TLI, Reg, V->getType());
5908 SDValue Chain = DAG.getEntryNode();
5909 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5910 PendingExports.push_back(Chain);
5913 #include "llvm/CodeGen/SelectionDAGISel.h"
5915 void SelectionDAGISel::
5916 LowerArguments(BasicBlock *LLVMBB) {
5917 // If this is the entry block, emit arguments.
5918 Function &F = *LLVMBB->getParent();
5919 SDValue OldRoot = SDL->DAG.getRoot();
5920 SmallVector<SDValue, 16> Args;
5921 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5924 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5926 SmallVector<MVT, 4> ValueVTs;
5927 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5928 unsigned NumValues = ValueVTs.size();
5929 if (!AI->use_empty()) {
5930 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5931 SDL->getCurDebugLoc()));
5932 // If this argument is live outside of the entry block, insert a copy from
5933 // whereever we got it to the vreg that other BB's will reference it as.
5934 SDL->CopyToExportRegsIfNeeded(AI);
5939 // Finally, if the target has anything special to do, allow it to do so.
5940 // FIXME: this should insert code into the DAG!
5941 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5944 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5945 /// ensure constants are generated when needed. Remember the virtual registers
5946 /// that need to be added to the Machine PHI nodes as input. We cannot just
5947 /// directly add them, because expansion might result in multiple MBB's for one
5948 /// BB. As such, the start of the BB might correspond to a different MBB than
5952 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5953 TerminatorInst *TI = LLVMBB->getTerminator();
5955 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5957 // Check successor nodes' PHI nodes that expect a constant to be available
5959 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5960 BasicBlock *SuccBB = TI->getSuccessor(succ);
5961 if (!isa<PHINode>(SuccBB->begin())) continue;
5962 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5964 // If this terminator has multiple identical successors (common for
5965 // switches), only handle each succ once.
5966 if (!SuccsHandled.insert(SuccMBB)) continue;
5968 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5971 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5972 // nodes and Machine PHI nodes, but the incoming operands have not been
5974 for (BasicBlock::iterator I = SuccBB->begin();
5975 (PN = dyn_cast<PHINode>(I)); ++I) {
5976 // Ignore dead phi's.
5977 if (PN->use_empty()) continue;
5980 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5982 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5983 unsigned &RegOut = SDL->ConstantsOut[C];
5985 RegOut = FuncInfo->CreateRegForValue(C);
5986 SDL->CopyValueToVirtualRegister(C, RegOut);
5990 Reg = FuncInfo->ValueMap[PHIOp];
5992 assert(isa<AllocaInst>(PHIOp) &&
5993 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5994 "Didn't codegen value into a register!??");
5995 Reg = FuncInfo->CreateRegForValue(PHIOp);
5996 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
6000 // Remember that this register needs to added to the machine PHI node as
6001 // the input for this MBB.
6002 SmallVector<MVT, 4> ValueVTs;
6003 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6004 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6005 MVT VT = ValueVTs[vti];
6006 unsigned NumRegisters = TLI.getNumRegisters(VT);
6007 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6008 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6009 Reg += NumRegisters;
6013 SDL->ConstantsOut.clear();
6016 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6017 /// supports legal types, and it emits MachineInstrs directly instead of
6018 /// creating SelectionDAG nodes.
6021 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6023 TerminatorInst *TI = LLVMBB->getTerminator();
6025 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6026 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6028 // Check successor nodes' PHI nodes that expect a constant to be available
6030 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6031 BasicBlock *SuccBB = TI->getSuccessor(succ);
6032 if (!isa<PHINode>(SuccBB->begin())) continue;
6033 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6035 // If this terminator has multiple identical successors (common for
6036 // switches), only handle each succ once.
6037 if (!SuccsHandled.insert(SuccMBB)) continue;
6039 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6042 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6043 // nodes and Machine PHI nodes, but the incoming operands have not been
6045 for (BasicBlock::iterator I = SuccBB->begin();
6046 (PN = dyn_cast<PHINode>(I)); ++I) {
6047 // Ignore dead phi's.
6048 if (PN->use_empty()) continue;
6050 // Only handle legal types. Two interesting things to note here. First,
6051 // by bailing out early, we may leave behind some dead instructions,
6052 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6053 // own moves. Second, this check is necessary becuase FastISel doesn't
6054 // use CreateRegForValue to create registers, so it always creates
6055 // exactly one register for each non-void instruction.
6056 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6057 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6060 VT = TLI.getTypeToTransformTo(VT);
6062 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6067 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6069 unsigned Reg = F->getRegForValue(PHIOp);
6071 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6074 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));