1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
51 /// LimitFloatPrecision - Generate low-precision inline sequences for
52 /// some float libcalls (6, 8 or 12 bits).
53 static unsigned LimitFloatPrecision;
55 static cl::opt<unsigned, true>
56 LimitFPPrecision("limit-float-precision",
57 cl::desc("Generate low-precision inline sequences "
58 "for some float libcalls"),
59 cl::location(LimitFloatPrecision),
62 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
63 /// insertvalue or extractvalue indices that identify a member, return
64 /// the linearized index of the start of the member.
66 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
67 const unsigned *Indices,
68 const unsigned *IndicesEnd,
69 unsigned CurIndex = 0) {
70 // Base case: We're done.
71 if (Indices && Indices == IndicesEnd)
74 // Given a struct type, recursively traverse the elements.
75 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
76 for (StructType::element_iterator EB = STy->element_begin(),
78 EE = STy->element_end();
80 if (Indices && *Indices == unsigned(EI - EB))
81 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
82 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
85 // Given an array type, recursively traverse the elements.
86 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
87 const Type *EltTy = ATy->getElementType();
88 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
89 if (Indices && *Indices == i)
90 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
91 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
94 // We haven't found the type we're looking for, so keep searching.
98 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
99 /// MVTs that represent all the individual underlying
100 /// non-aggregate types that comprise it.
102 /// If Offsets is non-null, it points to a vector to be filled in
103 /// with the in-memory offsets of each of the individual values.
105 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
106 SmallVectorImpl<MVT> &ValueVTs,
107 SmallVectorImpl<uint64_t> *Offsets = 0,
108 uint64_t StartingOffset = 0) {
109 // Given a struct type, recursively traverse the elements.
110 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
111 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
112 for (StructType::element_iterator EB = STy->element_begin(),
114 EE = STy->element_end();
116 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
117 StartingOffset + SL->getElementOffset(EI - EB));
120 // Given an array type, recursively traverse the elements.
121 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
122 const Type *EltTy = ATy->getElementType();
123 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
124 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
125 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
126 StartingOffset + i * EltSize);
129 // Base case: we can get an MVT for this LLVM IR type.
130 ValueVTs.push_back(TLI.getValueType(Ty));
132 Offsets->push_back(StartingOffset);
136 /// RegsForValue - This struct represents the registers (physical or virtual)
137 /// that a particular set of values is assigned, and the type information about
138 /// the value. The most common situation is to represent one value at a time,
139 /// but struct or array values are handled element-wise as multiple values.
140 /// The splitting of aggregates is performed recursively, so that we never
141 /// have aggregate-typed registers. The values at this point do not necessarily
142 /// have legal types, so each value may require one or more registers of some
145 struct VISIBILITY_HIDDEN RegsForValue {
146 /// TLI - The TargetLowering object.
148 const TargetLowering *TLI;
150 /// ValueVTs - The value types of the values, which may not be legal, and
151 /// may need be promoted or synthesized from one or more registers.
153 SmallVector<MVT, 4> ValueVTs;
155 /// RegVTs - The value types of the registers. This is the same size as
156 /// ValueVTs and it records, for each value, what the type of the assigned
157 /// register or registers are. (Individual values are never synthesized
158 /// from more than one type of register.)
160 /// With virtual registers, the contents of RegVTs is redundant with TLI's
161 /// getRegisterType member function, however when with physical registers
162 /// it is necessary to have a separate record of the types.
164 SmallVector<MVT, 4> RegVTs;
166 /// Regs - This list holds the registers assigned to the values.
167 /// Each legal or promoted value requires one register, and each
168 /// expanded value requires multiple registers.
170 SmallVector<unsigned, 4> Regs;
172 RegsForValue() : TLI(0) {}
174 RegsForValue(const TargetLowering &tli,
175 const SmallVector<unsigned, 4> ®s,
176 MVT regvt, MVT valuevt)
177 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
178 RegsForValue(const TargetLowering &tli,
179 const SmallVector<unsigned, 4> ®s,
180 const SmallVector<MVT, 4> ®vts,
181 const SmallVector<MVT, 4> &valuevts)
182 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
183 RegsForValue(const TargetLowering &tli,
184 unsigned Reg, const Type *Ty) : TLI(&tli) {
185 ComputeValueVTs(tli, Ty, ValueVTs);
187 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
188 MVT ValueVT = ValueVTs[Value];
189 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
190 MVT RegisterVT = TLI->getRegisterType(ValueVT);
191 for (unsigned i = 0; i != NumRegs; ++i)
192 Regs.push_back(Reg + i);
193 RegVTs.push_back(RegisterVT);
198 /// append - Add the specified values to this one.
199 void append(const RegsForValue &RHS) {
201 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
202 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
203 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
207 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
208 /// this value and returns the result as a ValueVTs value. This uses
209 /// Chain/Flag as the input and updates them for the output Chain/Flag.
210 /// If the Flag pointer is NULL, no flag is used.
211 SDValue getCopyFromRegs(SelectionDAG &DAG,
212 SDValue &Chain, SDValue *Flag) const;
214 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
215 /// specified value into the registers specified by this object. This uses
216 /// Chain/Flag as the input and updates them for the output Chain/Flag.
217 /// If the Flag pointer is NULL, no flag is used.
218 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
219 SDValue &Chain, SDValue *Flag) const;
221 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
222 /// operand list. This adds the code marker and includes the number of
223 /// values added into it.
224 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
225 std::vector<SDValue> &Ops) const;
229 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
230 /// PHI nodes or outside of the basic block that defines it, or used by a
231 /// switch or atomic instruction, which may expand to multiple basic blocks.
232 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
233 if (isa<PHINode>(I)) return true;
234 BasicBlock *BB = I->getParent();
235 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
236 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
237 // FIXME: Remove switchinst special case.
238 isa<SwitchInst>(*UI))
243 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
244 /// entry block, return true. This includes arguments used by switches, since
245 /// the switch may expand into multiple basic blocks.
246 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
247 // With FastISel active, we may be splitting blocks, so force creation
248 // of virtual registers for all non-dead arguments.
249 // Don't force virtual registers for byval arguments though, because
250 // fast-isel can't handle those in all cases.
251 if (EnableFastISel && !A->hasByValAttr())
252 return A->use_empty();
254 BasicBlock *Entry = A->getParent()->begin();
255 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
256 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
257 return false; // Use not in entry block.
261 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
265 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
266 bool EnableFastISel) {
269 RegInfo = &MF->getRegInfo();
271 // Create a vreg for each argument register that is not dead and is used
272 // outside of the entry block for the function.
273 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
275 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
276 InitializeRegForValue(AI);
278 // Initialize the mapping of values to registers. This is only set up for
279 // instruction values that are used outside of the block that defines
281 Function::iterator BB = Fn->begin(), EB = Fn->end();
282 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
283 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
284 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
285 const Type *Ty = AI->getAllocatedType();
286 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
288 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
291 TySize *= CUI->getZExtValue(); // Get total allocated size.
292 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
293 StaticAllocaMap[AI] =
294 MF->getFrameInfo()->CreateStackObject(TySize, Align);
297 for (; BB != EB; ++BB)
298 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
299 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
300 if (!isa<AllocaInst>(I) ||
301 !StaticAllocaMap.count(cast<AllocaInst>(I)))
302 InitializeRegForValue(I);
304 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
305 // also creates the initial PHI MachineInstrs, though none of the input
306 // operands are populated.
307 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
308 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
312 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
315 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
316 if (PN->use_empty()) continue;
318 unsigned PHIReg = ValueMap[PN];
319 assert(PHIReg && "PHI node does not have an assigned virtual register!");
321 SmallVector<MVT, 4> ValueVTs;
322 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
323 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
324 MVT VT = ValueVTs[vti];
325 unsigned NumRegisters = TLI.getNumRegisters(VT);
326 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
327 for (unsigned i = 0; i != NumRegisters; ++i)
328 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
329 PHIReg += NumRegisters;
335 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
336 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
339 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
340 /// the correctly promoted or expanded types. Assign these registers
341 /// consecutive vreg numbers and return the first assigned number.
343 /// In the case that the given value has struct or array type, this function
344 /// will assign registers for each member or element.
346 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
347 SmallVector<MVT, 4> ValueVTs;
348 ComputeValueVTs(TLI, V->getType(), ValueVTs);
350 unsigned FirstReg = 0;
351 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
352 MVT ValueVT = ValueVTs[Value];
353 MVT RegisterVT = TLI.getRegisterType(ValueVT);
355 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
356 for (unsigned i = 0; i != NumRegs; ++i) {
357 unsigned R = MakeReg(RegisterVT);
358 if (!FirstReg) FirstReg = R;
364 /// getCopyFromParts - Create a value that contains the specified legal parts
365 /// combined into the value they represent. If the parts combine to a type
366 /// larger then ValueVT then AssertOp can be used to specify whether the extra
367 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
368 /// (ISD::AssertSext).
369 static SDValue getCopyFromParts(SelectionDAG &DAG,
370 const SDValue *Parts,
374 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
375 assert(NumParts > 0 && "No parts to assemble!");
376 TargetLowering &TLI = DAG.getTargetLoweringInfo();
377 SDValue Val = Parts[0];
380 // Assemble the value from multiple parts.
381 if (!ValueVT.isVector()) {
382 unsigned PartBits = PartVT.getSizeInBits();
383 unsigned ValueBits = ValueVT.getSizeInBits();
385 // Assemble the power of 2 part.
386 unsigned RoundParts = NumParts & (NumParts - 1) ?
387 1 << Log2_32(NumParts) : NumParts;
388 unsigned RoundBits = PartBits * RoundParts;
389 MVT RoundVT = RoundBits == ValueBits ?
390 ValueVT : MVT::getIntegerVT(RoundBits);
393 if (RoundParts > 2) {
394 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
395 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
396 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
402 if (TLI.isBigEndian())
404 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
406 if (RoundParts < NumParts) {
407 // Assemble the trailing non-power-of-2 part.
408 unsigned OddParts = NumParts - RoundParts;
409 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
410 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
412 // Combine the round and odd parts.
414 if (TLI.isBigEndian())
416 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
417 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
418 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
419 DAG.getConstant(Lo.getValueType().getSizeInBits(),
420 TLI.getShiftAmountTy()));
421 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
422 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
425 // Handle a multi-element vector.
426 MVT IntermediateVT, RegisterVT;
427 unsigned NumIntermediates;
429 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
431 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
432 NumParts = NumRegs; // Silence a compiler warning.
433 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
434 assert(RegisterVT == Parts[0].getValueType() &&
435 "Part type doesn't match part!");
437 // Assemble the parts into intermediate operands.
438 SmallVector<SDValue, 8> Ops(NumIntermediates);
439 if (NumIntermediates == NumParts) {
440 // If the register was not expanded, truncate or copy the value,
442 for (unsigned i = 0; i != NumParts; ++i)
443 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
444 PartVT, IntermediateVT);
445 } else if (NumParts > 0) {
446 // If the intermediate type was expanded, build the intermediate operands
448 assert(NumParts % NumIntermediates == 0 &&
449 "Must expand into a divisible number of parts!");
450 unsigned Factor = NumParts / NumIntermediates;
451 for (unsigned i = 0; i != NumIntermediates; ++i)
452 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
453 PartVT, IntermediateVT);
456 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
458 Val = DAG.getNode(IntermediateVT.isVector() ?
459 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
460 ValueVT, &Ops[0], NumIntermediates);
464 // There is now one part, held in Val. Correct it to match ValueVT.
465 PartVT = Val.getValueType();
467 if (PartVT == ValueVT)
470 if (PartVT.isVector()) {
471 assert(ValueVT.isVector() && "Unknown vector conversion!");
472 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
475 if (ValueVT.isVector()) {
476 assert(ValueVT.getVectorElementType() == PartVT &&
477 ValueVT.getVectorNumElements() == 1 &&
478 "Only trivial scalar-to-vector conversions should get here!");
479 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
482 if (PartVT.isInteger() &&
483 ValueVT.isInteger()) {
484 if (ValueVT.bitsLT(PartVT)) {
485 // For a truncate, see if we have any information to
486 // indicate whether the truncated bits will always be
487 // zero or sign-extension.
488 if (AssertOp != ISD::DELETED_NODE)
489 Val = DAG.getNode(AssertOp, PartVT, Val,
490 DAG.getValueType(ValueVT));
491 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
493 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
497 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
498 if (ValueVT.bitsLT(Val.getValueType()))
499 // FP_ROUND's are always exact here.
500 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
501 DAG.getIntPtrConstant(1));
502 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
505 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
506 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
508 assert(0 && "Unknown mismatch!");
512 /// getCopyToParts - Create a series of nodes that contain the specified value
513 /// split into legal parts. If the parts contain more bits than Val, then, for
514 /// integers, ExtendKind can be used to specify how to generate the extra bits.
515 static void getCopyToParts(SelectionDAG &DAG,
520 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
521 TargetLowering &TLI = DAG.getTargetLoweringInfo();
522 MVT PtrVT = TLI.getPointerTy();
523 MVT ValueVT = Val.getValueType();
524 unsigned PartBits = PartVT.getSizeInBits();
525 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
530 if (!ValueVT.isVector()) {
531 if (PartVT == ValueVT) {
532 assert(NumParts == 1 && "No-op copy with multiple parts!");
537 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
538 // If the parts cover more bits than the value has, promote the value.
539 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
540 assert(NumParts == 1 && "Do not know what to promote to!");
541 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
542 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
543 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
544 Val = DAG.getNode(ExtendKind, ValueVT, Val);
546 assert(0 && "Unknown mismatch!");
548 } else if (PartBits == ValueVT.getSizeInBits()) {
549 // Different types of the same size.
550 assert(NumParts == 1 && PartVT != ValueVT);
551 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
552 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
553 // If the parts cover less bits than value has, truncate the value.
554 if (PartVT.isInteger() && ValueVT.isInteger()) {
555 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
556 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
558 assert(0 && "Unknown mismatch!");
562 // The value may have changed - recompute ValueVT.
563 ValueVT = Val.getValueType();
564 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
565 "Failed to tile the value with PartVT!");
568 assert(PartVT == ValueVT && "Type conversion failed!");
573 // Expand the value into multiple parts.
574 if (NumParts & (NumParts - 1)) {
575 // The number of parts is not a power of 2. Split off and copy the tail.
576 assert(PartVT.isInteger() && ValueVT.isInteger() &&
577 "Do not know what to expand to!");
578 unsigned RoundParts = 1 << Log2_32(NumParts);
579 unsigned RoundBits = RoundParts * PartBits;
580 unsigned OddParts = NumParts - RoundParts;
581 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
582 DAG.getConstant(RoundBits,
583 TLI.getShiftAmountTy()));
584 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
585 if (TLI.isBigEndian())
586 // The odd parts were reversed by getCopyToParts - unreverse them.
587 std::reverse(Parts + RoundParts, Parts + NumParts);
588 NumParts = RoundParts;
589 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
590 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
593 // The number of parts is a power of 2. Repeatedly bisect the value using
595 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
596 MVT::getIntegerVT(ValueVT.getSizeInBits()),
598 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
599 for (unsigned i = 0; i < NumParts; i += StepSize) {
600 unsigned ThisBits = StepSize * PartBits / 2;
601 MVT ThisVT = MVT::getIntegerVT (ThisBits);
602 SDValue &Part0 = Parts[i];
603 SDValue &Part1 = Parts[i+StepSize/2];
605 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
606 DAG.getConstant(1, PtrVT));
607 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
608 DAG.getConstant(0, PtrVT));
610 if (ThisBits == PartBits && ThisVT != PartVT) {
611 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
612 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
617 if (TLI.isBigEndian())
618 std::reverse(Parts, Parts + NumParts);
625 if (PartVT != ValueVT) {
626 if (PartVT.isVector()) {
627 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
629 assert(ValueVT.getVectorElementType() == PartVT &&
630 ValueVT.getVectorNumElements() == 1 &&
631 "Only trivial vector-to-scalar conversions should get here!");
632 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
633 DAG.getConstant(0, PtrVT));
641 // Handle a multi-element vector.
642 MVT IntermediateVT, RegisterVT;
643 unsigned NumIntermediates;
645 DAG.getTargetLoweringInfo()
646 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
648 unsigned NumElements = ValueVT.getVectorNumElements();
650 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
651 NumParts = NumRegs; // Silence a compiler warning.
652 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
654 // Split the vector into intermediate operands.
655 SmallVector<SDValue, 8> Ops(NumIntermediates);
656 for (unsigned i = 0; i != NumIntermediates; ++i)
657 if (IntermediateVT.isVector())
658 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
660 DAG.getConstant(i * (NumElements / NumIntermediates),
663 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
665 DAG.getConstant(i, PtrVT));
667 // Split the intermediate operands into legal parts.
668 if (NumParts == NumIntermediates) {
669 // If the register was not expanded, promote or copy the value,
671 for (unsigned i = 0; i != NumParts; ++i)
672 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
673 } else if (NumParts > 0) {
674 // If the intermediate type was expanded, split each the value into
676 assert(NumParts % NumIntermediates == 0 &&
677 "Must expand into a divisible number of parts!");
678 unsigned Factor = NumParts / NumIntermediates;
679 for (unsigned i = 0; i != NumIntermediates; ++i)
680 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
685 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
688 TD = DAG.getTarget().getTargetData();
691 /// clear - Clear out the curret SelectionDAG and the associated
692 /// state and prepare this SelectionDAGLowering object to be used
693 /// for a new block. This doesn't clear out information about
694 /// additional blocks that are needed to complete switch lowering
695 /// or PHI node updating; that information is cleared out as it is
697 void SelectionDAGLowering::clear() {
699 PendingLoads.clear();
700 PendingExports.clear();
704 /// getRoot - Return the current virtual root of the Selection DAG,
705 /// flushing any PendingLoad items. This must be done before emitting
706 /// a store or any other node that may need to be ordered after any
707 /// prior load instructions.
709 SDValue SelectionDAGLowering::getRoot() {
710 if (PendingLoads.empty())
711 return DAG.getRoot();
713 if (PendingLoads.size() == 1) {
714 SDValue Root = PendingLoads[0];
716 PendingLoads.clear();
720 // Otherwise, we have to make a token factor node.
721 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
722 &PendingLoads[0], PendingLoads.size());
723 PendingLoads.clear();
728 /// getControlRoot - Similar to getRoot, but instead of flushing all the
729 /// PendingLoad items, flush all the PendingExports items. It is necessary
730 /// to do this before emitting a terminator instruction.
732 SDValue SelectionDAGLowering::getControlRoot() {
733 SDValue Root = DAG.getRoot();
735 if (PendingExports.empty())
738 // Turn all of the CopyToReg chains into one factored node.
739 if (Root.getOpcode() != ISD::EntryToken) {
740 unsigned i = 0, e = PendingExports.size();
741 for (; i != e; ++i) {
742 assert(PendingExports[i].getNode()->getNumOperands() > 1);
743 if (PendingExports[i].getNode()->getOperand(0) == Root)
744 break; // Don't add the root if we already indirectly depend on it.
748 PendingExports.push_back(Root);
751 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
753 PendingExports.size());
754 PendingExports.clear();
759 void SelectionDAGLowering::visit(Instruction &I) {
760 visit(I.getOpcode(), I);
763 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
764 // Note: this doesn't use InstVisitor, because it has to work with
765 // ConstantExpr's in addition to instructions.
767 default: assert(0 && "Unknown instruction type encountered!");
769 // Build the switch statement using the Instruction.def file.
770 #define HANDLE_INST(NUM, OPCODE, CLASS) \
771 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
772 #include "llvm/Instruction.def"
776 void SelectionDAGLowering::visitAdd(User &I) {
777 if (I.getType()->isFPOrFPVector())
778 visitBinary(I, ISD::FADD);
780 visitBinary(I, ISD::ADD);
783 void SelectionDAGLowering::visitMul(User &I) {
784 if (I.getType()->isFPOrFPVector())
785 visitBinary(I, ISD::FMUL);
787 visitBinary(I, ISD::MUL);
790 SDValue SelectionDAGLowering::getValue(const Value *V) {
791 SDValue &N = NodeMap[V];
792 if (N.getNode()) return N;
794 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
795 MVT VT = TLI.getValueType(V->getType(), true);
797 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
798 return N = DAG.getConstant(*CI, VT);
800 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
801 return N = DAG.getGlobalAddress(GV, VT);
803 if (isa<ConstantPointerNull>(C))
804 return N = DAG.getConstant(0, TLI.getPointerTy());
806 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
807 return N = DAG.getConstantFP(*CFP, VT);
809 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
810 !V->getType()->isAggregateType())
811 return N = DAG.getNode(ISD::UNDEF, VT);
813 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
814 visit(CE->getOpcode(), *CE);
815 SDValue N1 = NodeMap[V];
816 assert(N1.getNode() && "visit didn't populate the ValueMap!");
820 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
821 SmallVector<SDValue, 4> Constants;
822 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
824 SDNode *Val = getValue(*OI).getNode();
825 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
826 Constants.push_back(SDValue(Val, i));
828 return DAG.getMergeValues(&Constants[0], Constants.size());
831 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
832 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
833 "Unknown struct or array constant!");
835 SmallVector<MVT, 4> ValueVTs;
836 ComputeValueVTs(TLI, C->getType(), ValueVTs);
837 unsigned NumElts = ValueVTs.size();
839 return SDValue(); // empty struct
840 SmallVector<SDValue, 4> Constants(NumElts);
841 for (unsigned i = 0; i != NumElts; ++i) {
842 MVT EltVT = ValueVTs[i];
843 if (isa<UndefValue>(C))
844 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
845 else if (EltVT.isFloatingPoint())
846 Constants[i] = DAG.getConstantFP(0, EltVT);
848 Constants[i] = DAG.getConstant(0, EltVT);
850 return DAG.getMergeValues(&Constants[0], NumElts);
853 const VectorType *VecTy = cast<VectorType>(V->getType());
854 unsigned NumElements = VecTy->getNumElements();
856 // Now that we know the number and type of the elements, get that number of
857 // elements into the Ops array based on what kind of constant it is.
858 SmallVector<SDValue, 16> Ops;
859 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
860 for (unsigned i = 0; i != NumElements; ++i)
861 Ops.push_back(getValue(CP->getOperand(i)));
863 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
864 "Unknown vector constant!");
865 MVT EltVT = TLI.getValueType(VecTy->getElementType());
868 if (isa<UndefValue>(C))
869 Op = DAG.getNode(ISD::UNDEF, EltVT);
870 else if (EltVT.isFloatingPoint())
871 Op = DAG.getConstantFP(0, EltVT);
873 Op = DAG.getConstant(0, EltVT);
874 Ops.assign(NumElements, Op);
877 // Create a BUILD_VECTOR node.
878 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
881 // If this is a static alloca, generate it as the frameindex instead of
883 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
884 DenseMap<const AllocaInst*, int>::iterator SI =
885 FuncInfo.StaticAllocaMap.find(AI);
886 if (SI != FuncInfo.StaticAllocaMap.end())
887 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
890 unsigned InReg = FuncInfo.ValueMap[V];
891 assert(InReg && "Value not in map!");
893 RegsForValue RFV(TLI, InReg, V->getType());
894 SDValue Chain = DAG.getEntryNode();
895 return RFV.getCopyFromRegs(DAG, Chain, NULL);
899 void SelectionDAGLowering::visitRet(ReturnInst &I) {
900 if (I.getNumOperands() == 0) {
901 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
905 SmallVector<SDValue, 8> NewValues;
906 NewValues.push_back(getControlRoot());
907 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
908 SDValue RetOp = getValue(I.getOperand(i));
910 SmallVector<MVT, 4> ValueVTs;
911 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
912 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
913 MVT VT = ValueVTs[j];
915 // FIXME: C calling convention requires the return type to be promoted to
916 // at least 32-bit. But this is not necessary for non-C calling
918 if (VT.isInteger()) {
919 MVT MinVT = TLI.getRegisterType(MVT::i32);
920 if (VT.bitsLT(MinVT))
924 unsigned NumParts = TLI.getNumRegisters(VT);
925 MVT PartVT = TLI.getRegisterType(VT);
926 SmallVector<SDValue, 4> Parts(NumParts);
927 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
929 const Function *F = I.getParent()->getParent();
930 if (F->paramHasAttr(0, Attribute::SExt))
931 ExtendKind = ISD::SIGN_EXTEND;
932 else if (F->paramHasAttr(0, Attribute::ZExt))
933 ExtendKind = ISD::ZERO_EXTEND;
935 getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j),
936 &Parts[0], NumParts, PartVT, ExtendKind);
938 // 'inreg' on function refers to return value
939 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
940 if (F->paramHasAttr(0, Attribute::InReg))
942 for (unsigned i = 0; i < NumParts; ++i) {
943 NewValues.push_back(Parts[i]);
944 NewValues.push_back(DAG.getArgFlags(Flags));
948 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
949 &NewValues[0], NewValues.size()));
952 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
953 /// the current basic block, add it to ValueMap now so that we'll get a
955 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
956 // No need to export constants.
957 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
960 if (FuncInfo.isExportedInst(V)) return;
962 unsigned Reg = FuncInfo.InitializeRegForValue(V);
963 CopyValueToVirtualRegister(V, Reg);
966 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
967 const BasicBlock *FromBB) {
968 // The operands of the setcc have to be in this block. We don't know
969 // how to export them from some other block.
970 if (Instruction *VI = dyn_cast<Instruction>(V)) {
971 // Can export from current BB.
972 if (VI->getParent() == FromBB)
975 // Is already exported, noop.
976 return FuncInfo.isExportedInst(V);
979 // If this is an argument, we can export it if the BB is the entry block or
980 // if it is already exported.
981 if (isa<Argument>(V)) {
982 if (FromBB == &FromBB->getParent()->getEntryBlock())
985 // Otherwise, can only export this if it is already exported.
986 return FuncInfo.isExportedInst(V);
989 // Otherwise, constants can always be exported.
993 static bool InBlock(const Value *V, const BasicBlock *BB) {
994 if (const Instruction *I = dyn_cast<Instruction>(V))
995 return I->getParent() == BB;
999 /// getFCmpCondCode - Return the ISD condition code corresponding to
1000 /// the given LLVM IR floating-point condition code. This includes
1001 /// consideration of global floating-point math flags.
1003 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1004 ISD::CondCode FPC, FOC;
1006 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1007 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1008 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1009 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1010 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1011 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1012 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1013 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1014 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1015 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1016 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1017 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1018 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1019 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1020 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1021 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1023 assert(0 && "Invalid FCmp predicate opcode!");
1024 FOC = FPC = ISD::SETFALSE;
1027 if (FiniteOnlyFPMath())
1033 /// getICmpCondCode - Return the ISD condition code corresponding to
1034 /// the given LLVM IR integer condition code.
1036 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1038 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1039 case ICmpInst::ICMP_NE: return ISD::SETNE;
1040 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1041 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1042 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1043 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1044 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1045 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1046 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1047 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1049 assert(0 && "Invalid ICmp predicate opcode!");
1054 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1055 /// This function emits a branch and is used at the leaves of an OR or an
1056 /// AND operator tree.
1059 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1060 MachineBasicBlock *TBB,
1061 MachineBasicBlock *FBB,
1062 MachineBasicBlock *CurBB) {
1063 const BasicBlock *BB = CurBB->getBasicBlock();
1065 // If the leaf of the tree is a comparison, merge the condition into
1067 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1068 // The operands of the cmp have to be in this block. We don't know
1069 // how to export them from some other block. If this is the first block
1070 // of the sequence, no exporting is needed.
1071 if (CurBB == CurMBB ||
1072 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1073 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1074 ISD::CondCode Condition;
1075 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1076 Condition = getICmpCondCode(IC->getPredicate());
1077 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1078 Condition = getFCmpCondCode(FC->getPredicate());
1080 Condition = ISD::SETEQ; // silence warning.
1081 assert(0 && "Unknown compare instruction");
1084 CaseBlock CB(Condition, BOp->getOperand(0),
1085 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1086 SwitchCases.push_back(CB);
1091 // Create a CaseBlock record representing this branch.
1092 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1093 NULL, TBB, FBB, CurBB);
1094 SwitchCases.push_back(CB);
1097 /// FindMergedConditions - If Cond is an expression like
1098 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1099 MachineBasicBlock *TBB,
1100 MachineBasicBlock *FBB,
1101 MachineBasicBlock *CurBB,
1103 // If this node is not part of the or/and tree, emit it as a branch.
1104 Instruction *BOp = dyn_cast<Instruction>(Cond);
1105 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1106 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1107 BOp->getParent() != CurBB->getBasicBlock() ||
1108 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1109 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1110 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1114 // Create TmpBB after CurBB.
1115 MachineFunction::iterator BBI = CurBB;
1116 MachineFunction &MF = DAG.getMachineFunction();
1117 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1118 CurBB->getParent()->insert(++BBI, TmpBB);
1120 if (Opc == Instruction::Or) {
1121 // Codegen X | Y as:
1129 // Emit the LHS condition.
1130 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1132 // Emit the RHS condition into TmpBB.
1133 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1135 assert(Opc == Instruction::And && "Unknown merge op!");
1136 // Codegen X & Y as:
1143 // This requires creation of TmpBB after CurBB.
1145 // Emit the LHS condition.
1146 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1148 // Emit the RHS condition into TmpBB.
1149 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1153 /// If the set of cases should be emitted as a series of branches, return true.
1154 /// If we should emit this as a bunch of and/or'd together conditions, return
1157 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1158 if (Cases.size() != 2) return true;
1160 // If this is two comparisons of the same values or'd or and'd together, they
1161 // will get folded into a single comparison, so don't emit two blocks.
1162 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1163 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1164 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1165 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1172 void SelectionDAGLowering::visitBr(BranchInst &I) {
1173 // Update machine-CFG edges.
1174 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1176 // Figure out which block is immediately after the current one.
1177 MachineBasicBlock *NextBlock = 0;
1178 MachineFunction::iterator BBI = CurMBB;
1179 if (++BBI != CurMBB->getParent()->end())
1182 if (I.isUnconditional()) {
1183 // Update machine-CFG edges.
1184 CurMBB->addSuccessor(Succ0MBB);
1186 // If this is not a fall-through branch, emit the branch.
1187 if (Succ0MBB != NextBlock)
1188 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1189 DAG.getBasicBlock(Succ0MBB)));
1193 // If this condition is one of the special cases we handle, do special stuff
1195 Value *CondVal = I.getCondition();
1196 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1198 // If this is a series of conditions that are or'd or and'd together, emit
1199 // this as a sequence of branches instead of setcc's with and/or operations.
1200 // For example, instead of something like:
1213 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1214 if (BOp->hasOneUse() &&
1215 (BOp->getOpcode() == Instruction::And ||
1216 BOp->getOpcode() == Instruction::Or)) {
1217 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1218 // If the compares in later blocks need to use values not currently
1219 // exported from this block, export them now. This block should always
1220 // be the first entry.
1221 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1223 // Allow some cases to be rejected.
1224 if (ShouldEmitAsBranches(SwitchCases)) {
1225 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1226 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1227 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1230 // Emit the branch for this block.
1231 visitSwitchCase(SwitchCases[0]);
1232 SwitchCases.erase(SwitchCases.begin());
1236 // Okay, we decided not to do this, remove any inserted MBB's and clear
1238 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1239 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1241 SwitchCases.clear();
1245 // Create a CaseBlock record representing this branch.
1246 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1247 NULL, Succ0MBB, Succ1MBB, CurMBB);
1248 // Use visitSwitchCase to actually insert the fast branch sequence for this
1250 visitSwitchCase(CB);
1253 /// visitSwitchCase - Emits the necessary code to represent a single node in
1254 /// the binary search tree resulting from lowering a switch instruction.
1255 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1257 SDValue CondLHS = getValue(CB.CmpLHS);
1259 // Build the setcc now.
1260 if (CB.CmpMHS == NULL) {
1261 // Fold "(X == true)" to X and "(X == false)" to !X to
1262 // handle common cases produced by branch lowering.
1263 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1265 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1266 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1267 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1269 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1271 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1273 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1274 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1276 SDValue CmpOp = getValue(CB.CmpMHS);
1277 MVT VT = CmpOp.getValueType();
1279 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1280 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1282 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1283 Cond = DAG.getSetCC(MVT::i1, SUB,
1284 DAG.getConstant(High-Low, VT), ISD::SETULE);
1288 // Update successor info
1289 CurMBB->addSuccessor(CB.TrueBB);
1290 CurMBB->addSuccessor(CB.FalseBB);
1292 // Set NextBlock to be the MBB immediately after the current one, if any.
1293 // This is used to avoid emitting unnecessary branches to the next block.
1294 MachineBasicBlock *NextBlock = 0;
1295 MachineFunction::iterator BBI = CurMBB;
1296 if (++BBI != CurMBB->getParent()->end())
1299 // If the lhs block is the next block, invert the condition so that we can
1300 // fall through to the lhs instead of the rhs block.
1301 if (CB.TrueBB == NextBlock) {
1302 std::swap(CB.TrueBB, CB.FalseBB);
1303 SDValue True = DAG.getConstant(1, Cond.getValueType());
1304 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1306 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1307 DAG.getBasicBlock(CB.TrueBB));
1309 // If the branch was constant folded, fix up the CFG.
1310 if (BrCond.getOpcode() == ISD::BR) {
1311 CurMBB->removeSuccessor(CB.FalseBB);
1312 DAG.setRoot(BrCond);
1314 // Otherwise, go ahead and insert the false branch.
1315 if (BrCond == getControlRoot())
1316 CurMBB->removeSuccessor(CB.TrueBB);
1318 if (CB.FalseBB == NextBlock)
1319 DAG.setRoot(BrCond);
1321 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1322 DAG.getBasicBlock(CB.FalseBB)));
1326 /// visitJumpTable - Emit JumpTable node in the current MBB
1327 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1328 // Emit the code for the jump table
1329 assert(JT.Reg != -1U && "Should lower JT Header first!");
1330 MVT PTy = TLI.getPointerTy();
1331 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1332 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1333 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1338 /// visitJumpTableHeader - This function emits necessary code to produce index
1339 /// in the JumpTable from switch case.
1340 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1341 JumpTableHeader &JTH) {
1342 // Subtract the lowest switch case value from the value being switched on
1343 // and conditional branch to default mbb if the result is greater than the
1344 // difference between smallest and largest cases.
1345 SDValue SwitchOp = getValue(JTH.SValue);
1346 MVT VT = SwitchOp.getValueType();
1347 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1348 DAG.getConstant(JTH.First, VT));
1350 // The SDNode we just created, which holds the value being switched on
1351 // minus the the smallest case value, needs to be copied to a virtual
1352 // register so it can be used as an index into the jump table in a
1353 // subsequent basic block. This value may be smaller or larger than the
1354 // target's pointer type, and therefore require extension or truncating.
1355 if (VT.bitsGT(TLI.getPointerTy()))
1356 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1358 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1360 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1361 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1362 JT.Reg = JumpTableReg;
1364 // Emit the range check for the jump table, and branch to the default
1365 // block for the switch statement if the value being switched on exceeds
1366 // the largest case in the switch.
1367 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1368 DAG.getConstant(JTH.Last-JTH.First,VT),
1371 // Set NextBlock to be the MBB immediately after the current one, if any.
1372 // This is used to avoid emitting unnecessary branches to the next block.
1373 MachineBasicBlock *NextBlock = 0;
1374 MachineFunction::iterator BBI = CurMBB;
1375 if (++BBI != CurMBB->getParent()->end())
1378 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1379 DAG.getBasicBlock(JT.Default));
1381 if (JT.MBB == NextBlock)
1382 DAG.setRoot(BrCond);
1384 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1385 DAG.getBasicBlock(JT.MBB)));
1390 /// visitBitTestHeader - This function emits necessary code to produce value
1391 /// suitable for "bit tests"
1392 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1393 // Subtract the minimum value
1394 SDValue SwitchOp = getValue(B.SValue);
1395 MVT VT = SwitchOp.getValueType();
1396 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1397 DAG.getConstant(B.First, VT));
1400 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1401 DAG.getConstant(B.Range, VT),
1405 if (VT.bitsGT(TLI.getShiftAmountTy()))
1406 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1408 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1410 // Make desired shift
1411 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1412 DAG.getConstant(1, TLI.getPointerTy()),
1415 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1416 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1419 // Set NextBlock to be the MBB immediately after the current one, if any.
1420 // This is used to avoid emitting unnecessary branches to the next block.
1421 MachineBasicBlock *NextBlock = 0;
1422 MachineFunction::iterator BBI = CurMBB;
1423 if (++BBI != CurMBB->getParent()->end())
1426 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1428 CurMBB->addSuccessor(B.Default);
1429 CurMBB->addSuccessor(MBB);
1431 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1432 DAG.getBasicBlock(B.Default));
1434 if (MBB == NextBlock)
1435 DAG.setRoot(BrRange);
1437 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1438 DAG.getBasicBlock(MBB)));
1443 /// visitBitTestCase - this function produces one "bit test"
1444 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1447 // Emit bit tests and jumps
1448 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1449 TLI.getPointerTy());
1451 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1452 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1453 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1454 DAG.getConstant(0, TLI.getPointerTy()),
1457 CurMBB->addSuccessor(B.TargetBB);
1458 CurMBB->addSuccessor(NextMBB);
1460 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1461 AndCmp, DAG.getBasicBlock(B.TargetBB));
1463 // Set NextBlock to be the MBB immediately after the current one, if any.
1464 // This is used to avoid emitting unnecessary branches to the next block.
1465 MachineBasicBlock *NextBlock = 0;
1466 MachineFunction::iterator BBI = CurMBB;
1467 if (++BBI != CurMBB->getParent()->end())
1470 if (NextMBB == NextBlock)
1473 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1474 DAG.getBasicBlock(NextMBB)));
1479 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1480 // Retrieve successors.
1481 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1482 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1484 if (isa<InlineAsm>(I.getCalledValue()))
1487 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1489 // If the value of the invoke is used outside of its defining block, make it
1490 // available as a virtual register.
1491 if (!I.use_empty()) {
1492 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1493 if (VMI != FuncInfo.ValueMap.end())
1494 CopyValueToVirtualRegister(&I, VMI->second);
1497 // Update successor info
1498 CurMBB->addSuccessor(Return);
1499 CurMBB->addSuccessor(LandingPad);
1501 // Drop into normal successor.
1502 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1503 DAG.getBasicBlock(Return)));
1506 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1509 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1510 /// small case ranges).
1511 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1512 CaseRecVector& WorkList,
1514 MachineBasicBlock* Default) {
1515 Case& BackCase = *(CR.Range.second-1);
1517 // Size is the number of Cases represented by this range.
1518 unsigned Size = CR.Range.second - CR.Range.first;
1522 // Get the MachineFunction which holds the current MBB. This is used when
1523 // inserting any additional MBBs necessary to represent the switch.
1524 MachineFunction *CurMF = CurMBB->getParent();
1526 // Figure out which block is immediately after the current one.
1527 MachineBasicBlock *NextBlock = 0;
1528 MachineFunction::iterator BBI = CR.CaseBB;
1530 if (++BBI != CurMBB->getParent()->end())
1533 // TODO: If any two of the cases has the same destination, and if one value
1534 // is the same as the other, but has one bit unset that the other has set,
1535 // use bit manipulation to do two compares at once. For example:
1536 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1538 // Rearrange the case blocks so that the last one falls through if possible.
1539 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1540 // The last case block won't fall through into 'NextBlock' if we emit the
1541 // branches in this order. See if rearranging a case value would help.
1542 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1543 if (I->BB == NextBlock) {
1544 std::swap(*I, BackCase);
1550 // Create a CaseBlock record representing a conditional branch to
1551 // the Case's target mbb if the value being switched on SV is equal
1553 MachineBasicBlock *CurBlock = CR.CaseBB;
1554 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1555 MachineBasicBlock *FallThrough;
1557 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1558 CurMF->insert(BBI, FallThrough);
1560 // If the last case doesn't match, go to the default block.
1561 FallThrough = Default;
1564 Value *RHS, *LHS, *MHS;
1566 if (I->High == I->Low) {
1567 // This is just small small case range :) containing exactly 1 case
1569 LHS = SV; RHS = I->High; MHS = NULL;
1572 LHS = I->Low; MHS = SV; RHS = I->High;
1574 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1576 // If emitting the first comparison, just call visitSwitchCase to emit the
1577 // code into the current block. Otherwise, push the CaseBlock onto the
1578 // vector to be later processed by SDISel, and insert the node's MBB
1579 // before the next MBB.
1580 if (CurBlock == CurMBB)
1581 visitSwitchCase(CB);
1583 SwitchCases.push_back(CB);
1585 CurBlock = FallThrough;
1591 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1592 return !DisableJumpTables &&
1593 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1594 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1597 /// handleJTSwitchCase - Emit jumptable for current switch case range
1598 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1599 CaseRecVector& WorkList,
1601 MachineBasicBlock* Default) {
1602 Case& FrontCase = *CR.Range.first;
1603 Case& BackCase = *(CR.Range.second-1);
1605 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1606 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1609 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1613 if (!areJTsAllowed(TLI) || TSize <= 3)
1616 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1620 DOUT << "Lowering jump table\n"
1621 << "First entry: " << First << ". Last entry: " << Last << "\n"
1622 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1624 // Get the MachineFunction which holds the current MBB. This is used when
1625 // inserting any additional MBBs necessary to represent the switch.
1626 MachineFunction *CurMF = CurMBB->getParent();
1628 // Figure out which block is immediately after the current one.
1629 MachineBasicBlock *NextBlock = 0;
1630 MachineFunction::iterator BBI = CR.CaseBB;
1632 if (++BBI != CurMBB->getParent()->end())
1635 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1637 // Create a new basic block to hold the code for loading the address
1638 // of the jump table, and jumping to it. Update successor information;
1639 // we will either branch to the default case for the switch, or the jump
1641 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1642 CurMF->insert(BBI, JumpTableBB);
1643 CR.CaseBB->addSuccessor(Default);
1644 CR.CaseBB->addSuccessor(JumpTableBB);
1646 // Build a vector of destination BBs, corresponding to each target
1647 // of the jump table. If the value of the jump table slot corresponds to
1648 // a case statement, push the case's BB onto the vector, otherwise, push
1650 std::vector<MachineBasicBlock*> DestBBs;
1651 int64_t TEI = First;
1652 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1653 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1654 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1656 if ((Low <= TEI) && (TEI <= High)) {
1657 DestBBs.push_back(I->BB);
1661 DestBBs.push_back(Default);
1665 // Update successor info. Add one edge to each unique successor.
1666 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1667 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1668 E = DestBBs.end(); I != E; ++I) {
1669 if (!SuccsHandled[(*I)->getNumber()]) {
1670 SuccsHandled[(*I)->getNumber()] = true;
1671 JumpTableBB->addSuccessor(*I);
1675 // Create a jump table index for this jump table, or return an existing
1677 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1679 // Set the jump table information so that we can codegen it as a second
1680 // MachineBasicBlock
1681 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1682 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1683 if (CR.CaseBB == CurMBB)
1684 visitJumpTableHeader(JT, JTH);
1686 JTCases.push_back(JumpTableBlock(JTH, JT));
1691 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1693 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1694 CaseRecVector& WorkList,
1696 MachineBasicBlock* Default) {
1697 // Get the MachineFunction which holds the current MBB. This is used when
1698 // inserting any additional MBBs necessary to represent the switch.
1699 MachineFunction *CurMF = CurMBB->getParent();
1701 // Figure out which block is immediately after the current one.
1702 MachineBasicBlock *NextBlock = 0;
1703 MachineFunction::iterator BBI = CR.CaseBB;
1705 if (++BBI != CurMBB->getParent()->end())
1708 Case& FrontCase = *CR.Range.first;
1709 Case& BackCase = *(CR.Range.second-1);
1710 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1712 // Size is the number of Cases represented by this range.
1713 unsigned Size = CR.Range.second - CR.Range.first;
1715 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1716 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1718 CaseItr Pivot = CR.Range.first + Size/2;
1720 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1721 // (heuristically) allow us to emit JumpTable's later.
1723 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1727 uint64_t LSize = FrontCase.size();
1728 uint64_t RSize = TSize-LSize;
1729 DOUT << "Selecting best pivot: \n"
1730 << "First: " << First << ", Last: " << Last <<"\n"
1731 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1732 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1734 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1735 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1736 assert((RBegin-LEnd>=1) && "Invalid case distance");
1737 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1738 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1739 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1740 // Should always split in some non-trivial place
1742 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1743 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1744 << "Metric: " << Metric << "\n";
1745 if (FMetric < Metric) {
1748 DOUT << "Current metric set to: " << FMetric << "\n";
1754 if (areJTsAllowed(TLI)) {
1755 // If our case is dense we *really* should handle it earlier!
1756 assert((FMetric > 0) && "Should handle dense range earlier!");
1758 Pivot = CR.Range.first + Size/2;
1761 CaseRange LHSR(CR.Range.first, Pivot);
1762 CaseRange RHSR(Pivot, CR.Range.second);
1763 Constant *C = Pivot->Low;
1764 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1766 // We know that we branch to the LHS if the Value being switched on is
1767 // less than the Pivot value, C. We use this to optimize our binary
1768 // tree a bit, by recognizing that if SV is greater than or equal to the
1769 // LHS's Case Value, and that Case Value is exactly one less than the
1770 // Pivot's Value, then we can branch directly to the LHS's Target,
1771 // rather than creating a leaf node for it.
1772 if ((LHSR.second - LHSR.first) == 1 &&
1773 LHSR.first->High == CR.GE &&
1774 cast<ConstantInt>(C)->getSExtValue() ==
1775 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1776 TrueBB = LHSR.first->BB;
1778 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1779 CurMF->insert(BBI, TrueBB);
1780 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1783 // Similar to the optimization above, if the Value being switched on is
1784 // known to be less than the Constant CR.LT, and the current Case Value
1785 // is CR.LT - 1, then we can branch directly to the target block for
1786 // the current Case Value, rather than emitting a RHS leaf node for it.
1787 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1788 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1789 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1790 FalseBB = RHSR.first->BB;
1792 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1793 CurMF->insert(BBI, FalseBB);
1794 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1797 // Create a CaseBlock record representing a conditional branch to
1798 // the LHS node if the value being switched on SV is less than C.
1799 // Otherwise, branch to LHS.
1800 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1802 if (CR.CaseBB == CurMBB)
1803 visitSwitchCase(CB);
1805 SwitchCases.push_back(CB);
1810 /// handleBitTestsSwitchCase - if current case range has few destination and
1811 /// range span less, than machine word bitwidth, encode case range into series
1812 /// of masks and emit bit tests with these masks.
1813 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1814 CaseRecVector& WorkList,
1816 MachineBasicBlock* Default){
1817 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1819 Case& FrontCase = *CR.Range.first;
1820 Case& BackCase = *(CR.Range.second-1);
1822 // Get the MachineFunction which holds the current MBB. This is used when
1823 // inserting any additional MBBs necessary to represent the switch.
1824 MachineFunction *CurMF = CurMBB->getParent();
1826 unsigned numCmps = 0;
1827 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1829 // Single case counts one, case range - two.
1830 if (I->Low == I->High)
1836 // Count unique destinations
1837 SmallSet<MachineBasicBlock*, 4> Dests;
1838 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1839 Dests.insert(I->BB);
1840 if (Dests.size() > 3)
1841 // Don't bother the code below, if there are too much unique destinations
1844 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1845 << "Total number of comparisons: " << numCmps << "\n";
1847 // Compute span of values.
1848 Constant* minValue = FrontCase.Low;
1849 Constant* maxValue = BackCase.High;
1850 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1851 cast<ConstantInt>(minValue)->getSExtValue();
1852 DOUT << "Compare range: " << range << "\n"
1853 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1854 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1856 if (range>=IntPtrBits ||
1857 (!(Dests.size() == 1 && numCmps >= 3) &&
1858 !(Dests.size() == 2 && numCmps >= 5) &&
1859 !(Dests.size() >= 3 && numCmps >= 6)))
1862 DOUT << "Emitting bit tests\n";
1863 int64_t lowBound = 0;
1865 // Optimize the case where all the case values fit in a
1866 // word without having to subtract minValue. In this case,
1867 // we can optimize away the subtraction.
1868 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1869 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1870 range = cast<ConstantInt>(maxValue)->getSExtValue();
1872 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1875 CaseBitsVector CasesBits;
1876 unsigned i, count = 0;
1878 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1879 MachineBasicBlock* Dest = I->BB;
1880 for (i = 0; i < count; ++i)
1881 if (Dest == CasesBits[i].BB)
1885 assert((count < 3) && "Too much destinations to test!");
1886 CasesBits.push_back(CaseBits(0, Dest, 0));
1890 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1891 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1893 for (uint64_t j = lo; j <= hi; j++) {
1894 CasesBits[i].Mask |= 1ULL << j;
1895 CasesBits[i].Bits++;
1899 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1903 // Figure out which block is immediately after the current one.
1904 MachineFunction::iterator BBI = CR.CaseBB;
1907 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1910 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1911 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1912 << ", BB: " << CasesBits[i].BB << "\n";
1914 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1915 CurMF->insert(BBI, CaseBB);
1916 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1921 BitTestBlock BTB(lowBound, range, SV,
1922 -1U, (CR.CaseBB == CurMBB),
1923 CR.CaseBB, Default, BTC);
1925 if (CR.CaseBB == CurMBB)
1926 visitBitTestHeader(BTB);
1928 BitTestCases.push_back(BTB);
1934 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1935 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1936 const SwitchInst& SI) {
1937 unsigned numCmps = 0;
1939 // Start with "simple" cases
1940 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1941 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1942 Cases.push_back(Case(SI.getSuccessorValue(i),
1943 SI.getSuccessorValue(i),
1946 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1948 // Merge case into clusters
1949 if (Cases.size()>=2)
1950 // Must recompute end() each iteration because it may be
1951 // invalidated by erase if we hold on to it
1952 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1953 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1954 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1955 MachineBasicBlock* nextBB = J->BB;
1956 MachineBasicBlock* currentBB = I->BB;
1958 // If the two neighboring cases go to the same destination, merge them
1959 // into a single case.
1960 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1968 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1969 if (I->Low != I->High)
1970 // A range counts double, since it requires two compares.
1977 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1978 // Figure out which block is immediately after the current one.
1979 MachineBasicBlock *NextBlock = 0;
1980 MachineFunction::iterator BBI = CurMBB;
1982 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1984 // If there is only the default destination, branch to it if it is not the
1985 // next basic block. Otherwise, just fall through.
1986 if (SI.getNumOperands() == 2) {
1987 // Update machine-CFG edges.
1989 // If this is not a fall-through branch, emit the branch.
1990 CurMBB->addSuccessor(Default);
1991 if (Default != NextBlock)
1992 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1993 DAG.getBasicBlock(Default)));
1998 // If there are any non-default case statements, create a vector of Cases
1999 // representing each one, and sort the vector so that we can efficiently
2000 // create a binary search tree from them.
2002 unsigned numCmps = Clusterify(Cases, SI);
2003 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2004 << ". Total compares: " << numCmps << "\n";
2006 // Get the Value to be switched on and default basic blocks, which will be
2007 // inserted into CaseBlock records, representing basic blocks in the binary
2009 Value *SV = SI.getOperand(0);
2011 // Push the initial CaseRec onto the worklist
2012 CaseRecVector WorkList;
2013 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2015 while (!WorkList.empty()) {
2016 // Grab a record representing a case range to process off the worklist
2017 CaseRec CR = WorkList.back();
2018 WorkList.pop_back();
2020 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2023 // If the range has few cases (two or less) emit a series of specific
2025 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2028 // If the switch has more than 5 blocks, and at least 40% dense, and the
2029 // target supports indirect branches, then emit a jump table rather than
2030 // lowering the switch to a binary tree of conditional branches.
2031 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2034 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2035 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2036 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2041 void SelectionDAGLowering::visitSub(User &I) {
2042 // -0.0 - X --> fneg
2043 const Type *Ty = I.getType();
2044 if (isa<VectorType>(Ty)) {
2045 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2046 const VectorType *DestTy = cast<VectorType>(I.getType());
2047 const Type *ElTy = DestTy->getElementType();
2048 if (ElTy->isFloatingPoint()) {
2049 unsigned VL = DestTy->getNumElements();
2050 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2051 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2053 SDValue Op2 = getValue(I.getOperand(1));
2054 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2060 if (Ty->isFloatingPoint()) {
2061 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2062 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2063 SDValue Op2 = getValue(I.getOperand(1));
2064 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2069 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2072 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2073 SDValue Op1 = getValue(I.getOperand(0));
2074 SDValue Op2 = getValue(I.getOperand(1));
2076 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2079 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2080 SDValue Op1 = getValue(I.getOperand(0));
2081 SDValue Op2 = getValue(I.getOperand(1));
2082 if (!isa<VectorType>(I.getType())) {
2083 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2084 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2085 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2086 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2089 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2092 void SelectionDAGLowering::visitICmp(User &I) {
2093 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2094 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2095 predicate = IC->getPredicate();
2096 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2097 predicate = ICmpInst::Predicate(IC->getPredicate());
2098 SDValue Op1 = getValue(I.getOperand(0));
2099 SDValue Op2 = getValue(I.getOperand(1));
2100 ISD::CondCode Opcode = getICmpCondCode(predicate);
2101 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2104 void SelectionDAGLowering::visitFCmp(User &I) {
2105 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2106 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2107 predicate = FC->getPredicate();
2108 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2109 predicate = FCmpInst::Predicate(FC->getPredicate());
2110 SDValue Op1 = getValue(I.getOperand(0));
2111 SDValue Op2 = getValue(I.getOperand(1));
2112 ISD::CondCode Condition = getFCmpCondCode(predicate);
2113 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2116 void SelectionDAGLowering::visitVICmp(User &I) {
2117 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2118 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2119 predicate = IC->getPredicate();
2120 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2121 predicate = ICmpInst::Predicate(IC->getPredicate());
2122 SDValue Op1 = getValue(I.getOperand(0));
2123 SDValue Op2 = getValue(I.getOperand(1));
2124 ISD::CondCode Opcode = getICmpCondCode(predicate);
2125 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2128 void SelectionDAGLowering::visitVFCmp(User &I) {
2129 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2130 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2131 predicate = FC->getPredicate();
2132 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2133 predicate = FCmpInst::Predicate(FC->getPredicate());
2134 SDValue Op1 = getValue(I.getOperand(0));
2135 SDValue Op2 = getValue(I.getOperand(1));
2136 ISD::CondCode Condition = getFCmpCondCode(predicate);
2137 MVT DestVT = TLI.getValueType(I.getType());
2139 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2142 void SelectionDAGLowering::visitSelect(User &I) {
2143 SDValue Cond = getValue(I.getOperand(0));
2144 SDValue TrueVal = getValue(I.getOperand(1));
2145 SDValue FalseVal = getValue(I.getOperand(2));
2146 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2147 TrueVal, FalseVal));
2151 void SelectionDAGLowering::visitTrunc(User &I) {
2152 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2153 SDValue N = getValue(I.getOperand(0));
2154 MVT DestVT = TLI.getValueType(I.getType());
2155 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2158 void SelectionDAGLowering::visitZExt(User &I) {
2159 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2160 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2161 SDValue N = getValue(I.getOperand(0));
2162 MVT DestVT = TLI.getValueType(I.getType());
2163 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2166 void SelectionDAGLowering::visitSExt(User &I) {
2167 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2168 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2169 SDValue N = getValue(I.getOperand(0));
2170 MVT DestVT = TLI.getValueType(I.getType());
2171 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2174 void SelectionDAGLowering::visitFPTrunc(User &I) {
2175 // FPTrunc is never a no-op cast, no need to check
2176 SDValue N = getValue(I.getOperand(0));
2177 MVT DestVT = TLI.getValueType(I.getType());
2178 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2181 void SelectionDAGLowering::visitFPExt(User &I){
2182 // FPTrunc is never a no-op cast, no need to check
2183 SDValue N = getValue(I.getOperand(0));
2184 MVT DestVT = TLI.getValueType(I.getType());
2185 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2188 void SelectionDAGLowering::visitFPToUI(User &I) {
2189 // FPToUI is never a no-op cast, no need to check
2190 SDValue N = getValue(I.getOperand(0));
2191 MVT DestVT = TLI.getValueType(I.getType());
2192 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2195 void SelectionDAGLowering::visitFPToSI(User &I) {
2196 // FPToSI is never a no-op cast, no need to check
2197 SDValue N = getValue(I.getOperand(0));
2198 MVT DestVT = TLI.getValueType(I.getType());
2199 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2202 void SelectionDAGLowering::visitUIToFP(User &I) {
2203 // UIToFP is never a no-op cast, no need to check
2204 SDValue N = getValue(I.getOperand(0));
2205 MVT DestVT = TLI.getValueType(I.getType());
2206 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2209 void SelectionDAGLowering::visitSIToFP(User &I){
2210 // UIToFP is never a no-op cast, no need to check
2211 SDValue N = getValue(I.getOperand(0));
2212 MVT DestVT = TLI.getValueType(I.getType());
2213 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2216 void SelectionDAGLowering::visitPtrToInt(User &I) {
2217 // What to do depends on the size of the integer and the size of the pointer.
2218 // We can either truncate, zero extend, or no-op, accordingly.
2219 SDValue N = getValue(I.getOperand(0));
2220 MVT SrcVT = N.getValueType();
2221 MVT DestVT = TLI.getValueType(I.getType());
2223 if (DestVT.bitsLT(SrcVT))
2224 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2226 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2227 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2228 setValue(&I, Result);
2231 void SelectionDAGLowering::visitIntToPtr(User &I) {
2232 // What to do depends on the size of the integer and the size of the pointer.
2233 // We can either truncate, zero extend, or no-op, accordingly.
2234 SDValue N = getValue(I.getOperand(0));
2235 MVT SrcVT = N.getValueType();
2236 MVT DestVT = TLI.getValueType(I.getType());
2237 if (DestVT.bitsLT(SrcVT))
2238 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2240 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2241 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2244 void SelectionDAGLowering::visitBitCast(User &I) {
2245 SDValue N = getValue(I.getOperand(0));
2246 MVT DestVT = TLI.getValueType(I.getType());
2248 // BitCast assures us that source and destination are the same size so this
2249 // is either a BIT_CONVERT or a no-op.
2250 if (DestVT != N.getValueType())
2251 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2253 setValue(&I, N); // noop cast.
2256 void SelectionDAGLowering::visitInsertElement(User &I) {
2257 SDValue InVec = getValue(I.getOperand(0));
2258 SDValue InVal = getValue(I.getOperand(1));
2259 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2260 getValue(I.getOperand(2)));
2262 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2263 TLI.getValueType(I.getType()),
2264 InVec, InVal, InIdx));
2267 void SelectionDAGLowering::visitExtractElement(User &I) {
2268 SDValue InVec = getValue(I.getOperand(0));
2269 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2270 getValue(I.getOperand(1)));
2271 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2272 TLI.getValueType(I.getType()), InVec, InIdx));
2275 void SelectionDAGLowering::visitShuffleVector(User &I) {
2276 SDValue V1 = getValue(I.getOperand(0));
2277 SDValue V2 = getValue(I.getOperand(1));
2278 SDValue Mask = getValue(I.getOperand(2));
2280 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2281 TLI.getValueType(I.getType()),
2285 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2286 const Value *Op0 = I.getOperand(0);
2287 const Value *Op1 = I.getOperand(1);
2288 const Type *AggTy = I.getType();
2289 const Type *ValTy = Op1->getType();
2290 bool IntoUndef = isa<UndefValue>(Op0);
2291 bool FromUndef = isa<UndefValue>(Op1);
2293 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2294 I.idx_begin(), I.idx_end());
2296 SmallVector<MVT, 4> AggValueVTs;
2297 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2298 SmallVector<MVT, 4> ValValueVTs;
2299 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2301 unsigned NumAggValues = AggValueVTs.size();
2302 unsigned NumValValues = ValValueVTs.size();
2303 SmallVector<SDValue, 4> Values(NumAggValues);
2305 SDValue Agg = getValue(Op0);
2306 SDValue Val = getValue(Op1);
2308 // Copy the beginning value(s) from the original aggregate.
2309 for (; i != LinearIndex; ++i)
2310 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2311 SDValue(Agg.getNode(), Agg.getResNo() + i);
2312 // Copy values from the inserted value(s).
2313 for (; i != LinearIndex + NumValValues; ++i)
2314 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2315 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2316 // Copy remaining value(s) from the original aggregate.
2317 for (; i != NumAggValues; ++i)
2318 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2319 SDValue(Agg.getNode(), Agg.getResNo() + i);
2321 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2322 &Values[0], NumAggValues));
2325 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2326 const Value *Op0 = I.getOperand(0);
2327 const Type *AggTy = Op0->getType();
2328 const Type *ValTy = I.getType();
2329 bool OutOfUndef = isa<UndefValue>(Op0);
2331 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2332 I.idx_begin(), I.idx_end());
2334 SmallVector<MVT, 4> ValValueVTs;
2335 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2337 unsigned NumValValues = ValValueVTs.size();
2338 SmallVector<SDValue, 4> Values(NumValValues);
2340 SDValue Agg = getValue(Op0);
2341 // Copy out the selected value(s).
2342 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2343 Values[i - LinearIndex] =
2344 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2345 SDValue(Agg.getNode(), Agg.getResNo() + i);
2347 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2348 &Values[0], NumValValues));
2352 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2353 SDValue N = getValue(I.getOperand(0));
2354 const Type *Ty = I.getOperand(0)->getType();
2356 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2359 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2360 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2363 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2364 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2365 DAG.getIntPtrConstant(Offset));
2367 Ty = StTy->getElementType(Field);
2369 Ty = cast<SequentialType>(Ty)->getElementType();
2371 // If this is a constant subscript, handle it quickly.
2372 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2373 if (CI->getZExtValue() == 0) continue;
2375 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2376 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2377 DAG.getIntPtrConstant(Offs));
2381 // N = N + Idx * ElementSize;
2382 uint64_t ElementSize = TD->getABITypeSize(Ty);
2383 SDValue IdxN = getValue(Idx);
2385 // If the index is smaller or larger than intptr_t, truncate or extend
2387 if (IdxN.getValueType().bitsLT(N.getValueType()))
2388 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2389 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2390 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2392 // If this is a multiply by a power of two, turn it into a shl
2393 // immediately. This is a very common case.
2394 if (ElementSize != 1) {
2395 if (isPowerOf2_64(ElementSize)) {
2396 unsigned Amt = Log2_64(ElementSize);
2397 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2398 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2400 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2401 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2405 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2411 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2412 // If this is a fixed sized alloca in the entry block of the function,
2413 // allocate it statically on the stack.
2414 if (FuncInfo.StaticAllocaMap.count(&I))
2415 return; // getValue will auto-populate this.
2417 const Type *Ty = I.getAllocatedType();
2418 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2420 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2423 SDValue AllocSize = getValue(I.getArraySize());
2424 MVT IntPtr = TLI.getPointerTy();
2425 if (IntPtr.bitsLT(AllocSize.getValueType()))
2426 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2427 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2428 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2430 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2431 DAG.getIntPtrConstant(TySize));
2433 // Handle alignment. If the requested alignment is less than or equal to
2434 // the stack alignment, ignore it. If the size is greater than or equal to
2435 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2436 unsigned StackAlign =
2437 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2438 if (Align <= StackAlign)
2441 // Round the size of the allocation up to the stack alignment size
2442 // by add SA-1 to the size.
2443 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2444 DAG.getIntPtrConstant(StackAlign-1));
2445 // Mask out the low bits for alignment purposes.
2446 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2447 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2449 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2450 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2452 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2454 DAG.setRoot(DSA.getValue(1));
2456 // Inform the Frame Information that we have just allocated a variable-sized
2458 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2461 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2462 const Value *SV = I.getOperand(0);
2463 SDValue Ptr = getValue(SV);
2465 const Type *Ty = I.getType();
2466 bool isVolatile = I.isVolatile();
2467 unsigned Alignment = I.getAlignment();
2469 SmallVector<MVT, 4> ValueVTs;
2470 SmallVector<uint64_t, 4> Offsets;
2471 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2472 unsigned NumValues = ValueVTs.size();
2477 bool ConstantMemory = false;
2479 // Serialize volatile loads with other side effects.
2481 else if (AA->pointsToConstantMemory(SV)) {
2482 // Do not serialize (non-volatile) loads of constant memory with anything.
2483 Root = DAG.getEntryNode();
2484 ConstantMemory = true;
2486 // Do not serialize non-volatile loads against each other.
2487 Root = DAG.getRoot();
2490 SmallVector<SDValue, 4> Values(NumValues);
2491 SmallVector<SDValue, 4> Chains(NumValues);
2492 MVT PtrVT = Ptr.getValueType();
2493 for (unsigned i = 0; i != NumValues; ++i) {
2494 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2495 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2496 DAG.getConstant(Offsets[i], PtrVT)),
2498 isVolatile, Alignment);
2500 Chains[i] = L.getValue(1);
2503 if (!ConstantMemory) {
2504 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2505 &Chains[0], NumValues);
2509 PendingLoads.push_back(Chain);
2512 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2513 &Values[0], NumValues));
2517 void SelectionDAGLowering::visitStore(StoreInst &I) {
2518 Value *SrcV = I.getOperand(0);
2519 Value *PtrV = I.getOperand(1);
2521 SmallVector<MVT, 4> ValueVTs;
2522 SmallVector<uint64_t, 4> Offsets;
2523 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2524 unsigned NumValues = ValueVTs.size();
2528 // Get the lowered operands. Note that we do this after
2529 // checking if NumResults is zero, because with zero results
2530 // the operands won't have values in the map.
2531 SDValue Src = getValue(SrcV);
2532 SDValue Ptr = getValue(PtrV);
2534 SDValue Root = getRoot();
2535 SmallVector<SDValue, 4> Chains(NumValues);
2536 MVT PtrVT = Ptr.getValueType();
2537 bool isVolatile = I.isVolatile();
2538 unsigned Alignment = I.getAlignment();
2539 for (unsigned i = 0; i != NumValues; ++i)
2540 Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(), Src.getResNo() + i),
2541 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2542 DAG.getConstant(Offsets[i], PtrVT)),
2544 isVolatile, Alignment);
2546 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2549 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2551 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2552 unsigned Intrinsic) {
2553 bool HasChain = !I.doesNotAccessMemory();
2554 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2556 // Build the operand list.
2557 SmallVector<SDValue, 8> Ops;
2558 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2560 // We don't need to serialize loads against other loads.
2561 Ops.push_back(DAG.getRoot());
2563 Ops.push_back(getRoot());
2567 // Add the intrinsic ID as an integer operand.
2568 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2570 // Add all operands of the call to the operand list.
2571 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2572 SDValue Op = getValue(I.getOperand(i));
2573 assert(TLI.isTypeLegal(Op.getValueType()) &&
2574 "Intrinsic uses a non-legal type?");
2578 std::vector<MVT> VTs;
2579 if (I.getType() != Type::VoidTy) {
2580 MVT VT = TLI.getValueType(I.getType());
2581 if (VT.isVector()) {
2582 const VectorType *DestTy = cast<VectorType>(I.getType());
2583 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2585 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2586 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2589 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2593 VTs.push_back(MVT::Other);
2595 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2600 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2601 &Ops[0], Ops.size());
2602 else if (I.getType() != Type::VoidTy)
2603 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2604 &Ops[0], Ops.size());
2606 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2607 &Ops[0], Ops.size());
2610 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2612 PendingLoads.push_back(Chain);
2616 if (I.getType() != Type::VoidTy) {
2617 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2618 MVT VT = TLI.getValueType(PTy);
2619 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2621 setValue(&I, Result);
2625 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2626 static GlobalVariable *ExtractTypeInfo(Value *V) {
2627 V = V->stripPointerCasts();
2628 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2629 assert ((GV || isa<ConstantPointerNull>(V)) &&
2630 "TypeInfo must be a global variable or NULL");
2636 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2637 /// call, and add them to the specified machine basic block.
2638 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2639 MachineBasicBlock *MBB) {
2640 // Inform the MachineModuleInfo of the personality for this landing pad.
2641 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2642 assert(CE->getOpcode() == Instruction::BitCast &&
2643 isa<Function>(CE->getOperand(0)) &&
2644 "Personality should be a function");
2645 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2647 // Gather all the type infos for this landing pad and pass them along to
2648 // MachineModuleInfo.
2649 std::vector<GlobalVariable *> TyInfo;
2650 unsigned N = I.getNumOperands();
2652 for (unsigned i = N - 1; i > 2; --i) {
2653 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2654 unsigned FilterLength = CI->getZExtValue();
2655 unsigned FirstCatch = i + FilterLength + !FilterLength;
2656 assert (FirstCatch <= N && "Invalid filter length");
2658 if (FirstCatch < N) {
2659 TyInfo.reserve(N - FirstCatch);
2660 for (unsigned j = FirstCatch; j < N; ++j)
2661 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2662 MMI->addCatchTypeInfo(MBB, TyInfo);
2666 if (!FilterLength) {
2668 MMI->addCleanup(MBB);
2671 TyInfo.reserve(FilterLength - 1);
2672 for (unsigned j = i + 1; j < FirstCatch; ++j)
2673 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2674 MMI->addFilterTypeInfo(MBB, TyInfo);
2683 TyInfo.reserve(N - 3);
2684 for (unsigned j = 3; j < N; ++j)
2685 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2686 MMI->addCatchTypeInfo(MBB, TyInfo);
2692 /// GetSignificand - Get the significand and build it into a floating-point
2693 /// number with exponent of 1:
2695 /// Op = (Op & 0x007fffff) | 0x3f800000;
2697 /// where Op is the hexidecimal representation of floating point value.
2699 GetSignificand(SelectionDAG &DAG, SDValue Op) {
2700 SDValue t1 = DAG.getNode(ISD::AND, MVT::i32, Op,
2701 DAG.getConstant(0x007fffff, MVT::i32));
2702 SDValue t2 = DAG.getNode(ISD::OR, MVT::i32, t1,
2703 DAG.getConstant(0x3f800000, MVT::i32));
2704 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t2);
2707 /// GetExponent - Get the exponent:
2709 /// (float)((Op1 >> 23) - 127);
2711 /// where Op is the hexidecimal representation of floating point value.
2713 GetExponent(SelectionDAG &DAG, SDValue Op) {
2714 SDValue t1 = DAG.getNode(ISD::SRL, MVT::i32, Op,
2715 DAG.getConstant(23, MVT::i32));
2716 SDValue t2 = DAG.getNode(ISD::SUB, MVT::i32, t1,
2717 DAG.getConstant(127, MVT::i32));
2718 return DAG.getNode(ISD::UINT_TO_FP, MVT::f32, t2);
2721 /// getF32Constant - Get 32-bit floating point constant.
2723 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2724 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2727 /// Inlined utility function to implement binary input atomic intrinsics for
2728 /// visitIntrinsicCall: I is a call instruction
2729 /// Op is the associated NodeType for I
2731 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2732 SDValue Root = getRoot();
2733 SDValue L = DAG.getAtomic(Op, Root,
2734 getValue(I.getOperand(1)),
2735 getValue(I.getOperand(2)),
2738 DAG.setRoot(L.getValue(1));
2742 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2743 /// limited-precision mode.
2745 SelectionDAGLowering::visitExp(CallInst &I) {
2748 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2749 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2750 SDValue Op = getValue(I.getOperand(1));
2752 // Put the exponent in the right bit position for later addition to the
2755 // #define LOG2OFe 1.4426950f
2756 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2757 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
2758 getF32Constant(DAG, 0x3fb8aa3b));
2759 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
2761 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2762 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
2763 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
2765 // IntegerPartOfX <<= 23;
2766 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
2767 DAG.getConstant(23, MVT::i32));
2769 if (LimitFloatPrecision <= 6) {
2770 // For floating-point precision of 6:
2772 // TwoToFractionalPartOfX =
2774 // (0.735607626f + 0.252464424f * x) * x;
2776 // error 0.0144103317, which is 6 bits
2777 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2778 getF32Constant(DAG, 0x3e814304));
2779 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2780 getF32Constant(DAG, 0x3f3c50c8));
2781 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2782 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2783 getF32Constant(DAG, 0x3f7f5e7e));
2784 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
2786 // Add the exponent into the result in integer domain.
2787 SDValue t6 = DAG.getNode(ISD::ADD, MVT::i32,
2788 TwoToFracPartOfX, IntegerPartOfX);
2790 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t6);
2791 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2792 // For floating-point precision of 12:
2794 // TwoToFractionalPartOfX =
2797 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2799 // 0.000107046256 error, which is 13 to 14 bits
2800 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2801 getF32Constant(DAG, 0x3da235e3));
2802 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2803 getF32Constant(DAG, 0x3e65b8f3));
2804 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2805 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2806 getF32Constant(DAG, 0x3f324b07));
2807 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2808 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
2809 getF32Constant(DAG, 0x3f7ff8fd));
2810 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
2812 // Add the exponent into the result in integer domain.
2813 SDValue t8 = DAG.getNode(ISD::ADD, MVT::i32,
2814 TwoToFracPartOfX, IntegerPartOfX);
2816 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t8);
2817 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2818 // For floating-point precision of 18:
2820 // TwoToFractionalPartOfX =
2824 // (0.554906021e-1f +
2825 // (0.961591928e-2f +
2826 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
2828 // error 2.47208000*10^(-7), which is better than 18 bits
2829 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2830 getF32Constant(DAG, 0x3924b03e));
2831 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
2832 getF32Constant(DAG, 0x3ab24b87));
2833 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2834 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2835 getF32Constant(DAG, 0x3c1d8c17));
2836 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2837 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
2838 getF32Constant(DAG, 0x3d634a1d));
2839 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
2840 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
2841 getF32Constant(DAG, 0x3e75fe14));
2842 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
2843 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
2844 getF32Constant(DAG, 0x3f317234));
2845 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
2846 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
2847 getF32Constant(DAG, 0x3f800000));
2848 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
2850 // Add the exponent into the result in integer domain.
2851 SDValue t14 = DAG.getNode(ISD::ADD, MVT::i32,
2852 TwoToFracPartOfX, IntegerPartOfX);
2854 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t14);
2857 // No special expansion.
2858 result = DAG.getNode(ISD::FEXP,
2859 getValue(I.getOperand(1)).getValueType(),
2860 getValue(I.getOperand(1)));
2863 setValue(&I, result);
2866 /// visitLog - Lower a log intrinsic. Handles the special sequences for
2867 /// limited-precision mode.
2869 SelectionDAGLowering::visitLog(CallInst &I) {
2872 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2873 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2874 SDValue Op = getValue(I.getOperand(1));
2875 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
2877 // Scale the exponent by log(2) [0.69314718f].
2878 SDValue Exp = GetExponent(DAG, Op1);
2879 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
2880 getF32Constant(DAG, 0x3f317218));
2882 // Get the significand and build it into a floating-point number with
2884 SDValue X = GetSignificand(DAG, Op1);
2886 if (LimitFloatPrecision <= 6) {
2887 // For floating-point precision of 6:
2891 // (1.4034025f - 0.23903021f * x) * x;
2893 // error 0.0034276066, which is better than 8 bits
2894 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2895 getF32Constant(DAG, 0xbe74c456));
2896 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2897 getF32Constant(DAG, 0x3fb3a2b1));
2898 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2899 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2900 getF32Constant(DAG, 0x3f949a29));
2902 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2903 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2904 // For floating-point precision of 12:
2910 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
2912 // error 0.000061011436, which is 14 bits
2913 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2914 getF32Constant(DAG, 0xbd67b6d6));
2915 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2916 getF32Constant(DAG, 0x3ee4f4b8));
2917 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2918 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2919 getF32Constant(DAG, 0x3fbc278b));
2920 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2921 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2922 getF32Constant(DAG, 0x40348e95));
2923 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2924 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
2925 getF32Constant(DAG, 0x3fdef31a));
2927 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2928 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2929 // For floating-point precision of 18:
2937 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
2939 // error 0.0000023660568, which is better than 18 bits
2940 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2941 getF32Constant(DAG, 0xbc91e5ac));
2942 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
2943 getF32Constant(DAG, 0x3e4350aa));
2944 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
2945 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
2946 getF32Constant(DAG, 0x3f60d3e3));
2947 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
2948 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
2949 getF32Constant(DAG, 0x4011cdf0));
2950 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
2951 SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
2952 getF32Constant(DAG, 0x406cfd1c));
2953 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
2954 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
2955 getF32Constant(DAG, 0x408797cb));
2956 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
2957 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
2958 getF32Constant(DAG, 0x4006dcab));
2960 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
2963 // No special expansion.
2964 result = DAG.getNode(ISD::FLOG,
2965 getValue(I.getOperand(1)).getValueType(),
2966 getValue(I.getOperand(1)));
2969 setValue(&I, result);
2972 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
2973 /// limited-precision mode.
2975 SelectionDAGLowering::visitLog2(CallInst &I) {
2978 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2979 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2980 SDValue Op = getValue(I.getOperand(1));
2981 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
2983 // Get the exponent.
2984 SDValue LogOfExponent = GetExponent(DAG, Op1);
2986 // Get the significand and build it into a floating-point number with
2988 SDValue X = GetSignificand(DAG, Op1);
2990 // Different possible minimax approximations of significand in
2991 // floating-point for various degrees of accuracy over [1,2].
2992 if (LimitFloatPrecision <= 6) {
2993 // For floating-point precision of 6:
2995 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
2997 // error 0.0049451742, which is more than 7 bits
2998 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
2999 getF32Constant(DAG, 0xbeb08fe0));
3000 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3001 getF32Constant(DAG, 0x40019463));
3002 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3003 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3004 getF32Constant(DAG, 0x3fd6633d));
3006 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3007 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3008 // For floating-point precision of 12:
3014 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3016 // error 0.0000876136000, which is better than 13 bits
3017 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3018 getF32Constant(DAG, 0xbda7262e));
3019 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3020 getF32Constant(DAG, 0x3f25280b));
3021 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3022 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3023 getF32Constant(DAG, 0x4007b923));
3024 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3025 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3026 getF32Constant(DAG, 0x40823e2f));
3027 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3028 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3029 getF32Constant(DAG, 0x4020d29c));
3031 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3032 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3033 // For floating-point precision of 18:
3042 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3044 // error 0.0000018516, which is better than 18 bits
3045 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3046 getF32Constant(DAG, 0xbcd2769e));
3047 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3048 getF32Constant(DAG, 0x3e8ce0b9));
3049 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3050 SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3051 getF32Constant(DAG, 0x3fa22ae7));
3052 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3053 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3054 getF32Constant(DAG, 0x40525723));
3055 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3056 SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
3057 getF32Constant(DAG, 0x40aaf200));
3058 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3059 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3060 getF32Constant(DAG, 0x40c39dad));
3061 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3062 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
3063 getF32Constant(DAG, 0x4042902c));
3065 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
3068 // No special expansion.
3069 result = DAG.getNode(ISD::FLOG2,
3070 getValue(I.getOperand(1)).getValueType(),
3071 getValue(I.getOperand(1)));
3074 setValue(&I, result);
3077 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3078 /// limited-precision mode.
3080 SelectionDAGLowering::visitLog10(CallInst &I) {
3082 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3083 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3084 SDValue Op = getValue(I.getOperand(1));
3085 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
3087 // Scale the exponent by log10(2) [0.30102999f].
3088 SDValue Exp = GetExponent(DAG, Op1);
3089 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
3090 getF32Constant(DAG, 0x3e9a209a));
3092 // Get the significand and build it into a floating-point number with
3094 SDValue X = GetSignificand(DAG, Op1);
3096 if (LimitFloatPrecision <= 6) {
3097 // For floating-point precision of 6:
3099 // Log10ofMantissa =
3101 // (0.60948995f - 0.10380950f * x) * x;
3103 // error 0.0014886165, which is 6 bits
3104 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3105 getF32Constant(DAG, 0xbdd49a13));
3106 SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
3107 getF32Constant(DAG, 0x3f1c0789));
3108 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3109 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
3110 getF32Constant(DAG, 0x3f011300));
3112 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3113 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3114 // For floating-point precision of 12:
3116 // Log10ofMantissa =
3119 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3121 // error 0.00019228036, which is better than 12 bits
3122 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3123 getF32Constant(DAG, 0x3d431f31));
3124 SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
3125 getF32Constant(DAG, 0x3ea21fb2));
3126 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3127 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3128 getF32Constant(DAG, 0x3f6ae232));
3129 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3130 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t4,
3131 getF32Constant(DAG, 0x3f25f7c3));
3133 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3134 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3135 // For floating-point precision of 18:
3137 // Log10ofMantissa =
3142 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3144 // error 0.0000037995730, which is better than 18 bits
3145 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3146 getF32Constant(DAG, 0x3c5d51ce));
3147 SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
3148 getF32Constant(DAG, 0x3e00685a));
3149 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
3150 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3151 getF32Constant(DAG, 0x3efb6798));
3152 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3153 SDValue t5 = DAG.getNode(ISD::FSUB, MVT::f32, t4,
3154 getF32Constant(DAG, 0x3f88d192));
3155 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3156 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3157 getF32Constant(DAG, 0x3fc4316c));
3158 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3159 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t8,
3160 getF32Constant(DAG, 0x3f57ce70));
3162 result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
3165 // No special expansion.
3166 result = DAG.getNode(ISD::FLOG10,
3167 getValue(I.getOperand(1)).getValueType(),
3168 getValue(I.getOperand(1)));
3171 setValue(&I, result);
3174 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3175 /// limited-precision mode.
3177 SelectionDAGLowering::visitExp2(CallInst &I) {
3180 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3181 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3182 SDValue Op = getValue(I.getOperand(1));
3184 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Op);
3186 // FractionalPartOfX = x - (float)IntegerPartOfX;
3187 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
3188 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, Op, t1);
3190 // IntegerPartOfX <<= 23;
3191 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
3192 DAG.getConstant(23, MVT::i32));
3194 if (LimitFloatPrecision <= 6) {
3195 // For floating-point precision of 6:
3197 // TwoToFractionalPartOfX =
3199 // (0.735607626f + 0.252464424f * x) * x;
3201 // error 0.0144103317, which is 6 bits
3202 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3203 getF32Constant(DAG, 0x3e814304));
3204 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3205 getF32Constant(DAG, 0x3f3c50c8));
3206 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3207 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3208 getF32Constant(DAG, 0x3f7f5e7e));
3209 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
3210 SDValue TwoToFractionalPartOfX =
3211 DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
3213 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3214 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3215 // For floating-point precision of 12:
3217 // TwoToFractionalPartOfX =
3220 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3222 // error 0.000107046256, which is 13 to 14 bits
3223 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3224 getF32Constant(DAG, 0x3da235e3));
3225 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3226 getF32Constant(DAG, 0x3e65b8f3));
3227 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3228 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3229 getF32Constant(DAG, 0x3f324b07));
3230 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3231 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3232 getF32Constant(DAG, 0x3f7ff8fd));
3233 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
3234 SDValue TwoToFractionalPartOfX =
3235 DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
3237 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3238 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3239 // For floating-point precision of 18:
3241 // TwoToFractionalPartOfX =
3245 // (0.554906021e-1f +
3246 // (0.961591928e-2f +
3247 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3248 // error 2.47208000*10^(-7), which is better than 18 bits
3249 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3250 getF32Constant(DAG, 0x3924b03e));
3251 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3252 getF32Constant(DAG, 0x3ab24b87));
3253 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3254 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3255 getF32Constant(DAG, 0x3c1d8c17));
3256 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3257 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3258 getF32Constant(DAG, 0x3d634a1d));
3259 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3260 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3261 getF32Constant(DAG, 0x3e75fe14));
3262 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3263 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
3264 getF32Constant(DAG, 0x3f317234));
3265 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
3266 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
3267 getF32Constant(DAG, 0x3f800000));
3268 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
3269 SDValue TwoToFractionalPartOfX =
3270 DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
3272 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3275 // No special expansion.
3276 result = DAG.getNode(ISD::FEXP2,
3277 getValue(I.getOperand(1)).getValueType(),
3278 getValue(I.getOperand(1)));
3281 setValue(&I, result);
3284 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3285 /// limited-precision mode with x == 10.0f.
3287 SelectionDAGLowering::visitPow(CallInst &I) {
3289 Value *Val = I.getOperand(1);
3290 bool IsExp10 = false;
3292 if (getValue(Val).getValueType() == MVT::f32 &&
3293 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3294 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3295 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3296 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3298 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3303 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3304 SDValue Op = getValue(I.getOperand(2));
3306 // Put the exponent in the right bit position for later addition to the
3309 // #define LOG2OF10 3.3219281f
3310 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3311 SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
3312 getF32Constant(DAG, 0x40549a78));
3313 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
3315 // FractionalPartOfX = x - (float)IntegerPartOfX;
3316 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
3317 SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
3319 // IntegerPartOfX <<= 23;
3320 IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
3321 DAG.getConstant(23, MVT::i32));
3323 if (LimitFloatPrecision <= 6) {
3324 // For floating-point precision of 6:
3326 // twoToFractionalPartOfX =
3328 // (0.735607626f + 0.252464424f * x) * x;
3330 // error 0.0144103317, which is 6 bits
3331 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3332 getF32Constant(DAG, 0x3e814304));
3333 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3334 getF32Constant(DAG, 0x3f3c50c8));
3335 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3336 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3337 getF32Constant(DAG, 0x3f7f5e7e));
3338 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
3339 SDValue TwoToFractionalPartOfX =
3340 DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
3342 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3343 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3344 // For floating-point precision of 12:
3346 // TwoToFractionalPartOfX =
3349 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3351 // error 0.000107046256, which is 13 to 14 bits
3352 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3353 getF32Constant(DAG, 0x3da235e3));
3354 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3355 getF32Constant(DAG, 0x3e65b8f3));
3356 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3357 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3358 getF32Constant(DAG, 0x3f324b07));
3359 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3360 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3361 getF32Constant(DAG, 0x3f7ff8fd));
3362 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
3363 SDValue TwoToFractionalPartOfX =
3364 DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
3366 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3367 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3368 // For floating-point precision of 18:
3370 // TwoToFractionalPartOfX =
3374 // (0.554906021e-1f +
3375 // (0.961591928e-2f +
3376 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3377 // error 2.47208000*10^(-7), which is better than 18 bits
3378 SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
3379 getF32Constant(DAG, 0x3924b03e));
3380 SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
3381 getF32Constant(DAG, 0x3ab24b87));
3382 SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
3383 SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
3384 getF32Constant(DAG, 0x3c1d8c17));
3385 SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
3386 SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
3387 getF32Constant(DAG, 0x3d634a1d));
3388 SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
3389 SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
3390 getF32Constant(DAG, 0x3e75fe14));
3391 SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
3392 SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
3393 getF32Constant(DAG, 0x3f317234));
3394 SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
3395 SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
3396 getF32Constant(DAG, 0x3f800000));
3397 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
3398 SDValue TwoToFractionalPartOfX =
3399 DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
3401 result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
3404 // No special expansion.
3405 result = DAG.getNode(ISD::FPOW,
3406 getValue(I.getOperand(1)).getValueType(),
3407 getValue(I.getOperand(1)),
3408 getValue(I.getOperand(2)));
3411 setValue(&I, result);
3414 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3415 /// we want to emit this as a call to a named external function, return the name
3416 /// otherwise lower it and return null.
3418 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3419 switch (Intrinsic) {
3421 // By default, turn this into a target intrinsic node.
3422 visitTargetIntrinsic(I, Intrinsic);
3424 case Intrinsic::vastart: visitVAStart(I); return 0;
3425 case Intrinsic::vaend: visitVAEnd(I); return 0;
3426 case Intrinsic::vacopy: visitVACopy(I); return 0;
3427 case Intrinsic::returnaddress:
3428 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3429 getValue(I.getOperand(1))));
3431 case Intrinsic::frameaddress:
3432 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3433 getValue(I.getOperand(1))));
3435 case Intrinsic::setjmp:
3436 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3438 case Intrinsic::longjmp:
3439 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3441 case Intrinsic::memcpy_i32:
3442 case Intrinsic::memcpy_i64: {
3443 SDValue Op1 = getValue(I.getOperand(1));
3444 SDValue Op2 = getValue(I.getOperand(2));
3445 SDValue Op3 = getValue(I.getOperand(3));
3446 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3447 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3448 I.getOperand(1), 0, I.getOperand(2), 0));
3451 case Intrinsic::memset_i32:
3452 case Intrinsic::memset_i64: {
3453 SDValue Op1 = getValue(I.getOperand(1));
3454 SDValue Op2 = getValue(I.getOperand(2));
3455 SDValue Op3 = getValue(I.getOperand(3));
3456 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3457 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3458 I.getOperand(1), 0));
3461 case Intrinsic::memmove_i32:
3462 case Intrinsic::memmove_i64: {
3463 SDValue Op1 = getValue(I.getOperand(1));
3464 SDValue Op2 = getValue(I.getOperand(2));
3465 SDValue Op3 = getValue(I.getOperand(3));
3466 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3468 // If the source and destination are known to not be aliases, we can
3469 // lower memmove as memcpy.
3470 uint64_t Size = -1ULL;
3471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3472 Size = C->getZExtValue();
3473 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3474 AliasAnalysis::NoAlias) {
3475 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3476 I.getOperand(1), 0, I.getOperand(2), 0));
3480 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3481 I.getOperand(1), 0, I.getOperand(2), 0));
3484 case Intrinsic::dbg_stoppoint: {
3485 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3486 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3487 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3488 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3489 assert(DD && "Not a debug information descriptor");
3490 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3493 cast<CompileUnitDesc>(DD)));
3498 case Intrinsic::dbg_region_start: {
3499 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3500 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3501 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3502 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3503 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3508 case Intrinsic::dbg_region_end: {
3509 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3510 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3511 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3512 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3513 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3518 case Intrinsic::dbg_func_start: {
3519 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3521 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3522 Value *SP = FSI.getSubprogram();
3523 if (SP && MMI->Verify(SP)) {
3524 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3525 // what (most?) gdb expects.
3526 DebugInfoDesc *DD = MMI->getDescFor(SP);
3527 assert(DD && "Not a debug information descriptor");
3528 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3529 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3530 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3531 // Record the source line but does create a label. It will be emitted
3532 // at asm emission time.
3533 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3538 case Intrinsic::dbg_declare: {
3539 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3540 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3541 Value *Variable = DI.getVariable();
3542 if (MMI && Variable && MMI->Verify(Variable))
3543 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3544 getValue(DI.getAddress()), getValue(Variable)));
3548 case Intrinsic::eh_exception: {
3549 if (!CurMBB->isLandingPad()) {
3550 // FIXME: Mark exception register as live in. Hack for PR1508.
3551 unsigned Reg = TLI.getExceptionAddressRegister();
3552 if (Reg) CurMBB->addLiveIn(Reg);
3554 // Insert the EXCEPTIONADDR instruction.
3555 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3557 Ops[0] = DAG.getRoot();
3558 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3560 DAG.setRoot(Op.getValue(1));
3564 case Intrinsic::eh_selector_i32:
3565 case Intrinsic::eh_selector_i64: {
3566 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3567 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3568 MVT::i32 : MVT::i64);
3571 if (CurMBB->isLandingPad())
3572 AddCatchInfo(I, MMI, CurMBB);
3575 FuncInfo.CatchInfoLost.insert(&I);
3577 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3578 unsigned Reg = TLI.getExceptionSelectorRegister();
3579 if (Reg) CurMBB->addLiveIn(Reg);
3582 // Insert the EHSELECTION instruction.
3583 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3585 Ops[0] = getValue(I.getOperand(1));
3587 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3589 DAG.setRoot(Op.getValue(1));
3591 setValue(&I, DAG.getConstant(0, VT));
3597 case Intrinsic::eh_typeid_for_i32:
3598 case Intrinsic::eh_typeid_for_i64: {
3599 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3600 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3601 MVT::i32 : MVT::i64);
3604 // Find the type id for the given typeinfo.
3605 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3607 unsigned TypeID = MMI->getTypeIDFor(GV);
3608 setValue(&I, DAG.getConstant(TypeID, VT));
3610 // Return something different to eh_selector.
3611 setValue(&I, DAG.getConstant(1, VT));
3617 case Intrinsic::eh_return_i32:
3618 case Intrinsic::eh_return_i64:
3619 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3620 MMI->setCallsEHReturn(true);
3621 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3624 getValue(I.getOperand(1)),
3625 getValue(I.getOperand(2))));
3627 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3631 case Intrinsic::eh_unwind_init:
3632 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3633 MMI->setCallsUnwindInit(true);
3638 case Intrinsic::eh_dwarf_cfa: {
3639 MVT VT = getValue(I.getOperand(1)).getValueType();
3641 if (VT.bitsGT(TLI.getPointerTy()))
3642 CfaArg = DAG.getNode(ISD::TRUNCATE,
3643 TLI.getPointerTy(), getValue(I.getOperand(1)));
3645 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3646 TLI.getPointerTy(), getValue(I.getOperand(1)));
3648 SDValue Offset = DAG.getNode(ISD::ADD,
3650 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3651 TLI.getPointerTy()),
3653 setValue(&I, DAG.getNode(ISD::ADD,
3655 DAG.getNode(ISD::FRAMEADDR,
3658 TLI.getPointerTy())),
3663 case Intrinsic::sqrt:
3664 setValue(&I, DAG.getNode(ISD::FSQRT,
3665 getValue(I.getOperand(1)).getValueType(),
3666 getValue(I.getOperand(1))));
3668 case Intrinsic::powi:
3669 setValue(&I, DAG.getNode(ISD::FPOWI,
3670 getValue(I.getOperand(1)).getValueType(),
3671 getValue(I.getOperand(1)),
3672 getValue(I.getOperand(2))));
3674 case Intrinsic::sin:
3675 setValue(&I, DAG.getNode(ISD::FSIN,
3676 getValue(I.getOperand(1)).getValueType(),
3677 getValue(I.getOperand(1))));
3679 case Intrinsic::cos:
3680 setValue(&I, DAG.getNode(ISD::FCOS,
3681 getValue(I.getOperand(1)).getValueType(),
3682 getValue(I.getOperand(1))));
3684 case Intrinsic::log:
3687 case Intrinsic::log2:
3690 case Intrinsic::log10:
3693 case Intrinsic::exp:
3696 case Intrinsic::exp2:
3699 case Intrinsic::pow:
3702 case Intrinsic::pcmarker: {
3703 SDValue Tmp = getValue(I.getOperand(1));
3704 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3707 case Intrinsic::readcyclecounter: {
3708 SDValue Op = getRoot();
3709 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3710 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3713 DAG.setRoot(Tmp.getValue(1));
3716 case Intrinsic::part_select: {
3717 // Currently not implemented: just abort
3718 assert(0 && "part_select intrinsic not implemented");
3721 case Intrinsic::part_set: {
3722 // Currently not implemented: just abort
3723 assert(0 && "part_set intrinsic not implemented");
3726 case Intrinsic::bswap:
3727 setValue(&I, DAG.getNode(ISD::BSWAP,
3728 getValue(I.getOperand(1)).getValueType(),
3729 getValue(I.getOperand(1))));
3731 case Intrinsic::cttz: {
3732 SDValue Arg = getValue(I.getOperand(1));
3733 MVT Ty = Arg.getValueType();
3734 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3735 setValue(&I, result);
3738 case Intrinsic::ctlz: {
3739 SDValue Arg = getValue(I.getOperand(1));
3740 MVT Ty = Arg.getValueType();
3741 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3742 setValue(&I, result);
3745 case Intrinsic::ctpop: {
3746 SDValue Arg = getValue(I.getOperand(1));
3747 MVT Ty = Arg.getValueType();
3748 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3749 setValue(&I, result);
3752 case Intrinsic::stacksave: {
3753 SDValue Op = getRoot();
3754 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3755 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3757 DAG.setRoot(Tmp.getValue(1));
3760 case Intrinsic::stackrestore: {
3761 SDValue Tmp = getValue(I.getOperand(1));
3762 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3765 case Intrinsic::var_annotation:
3766 // Discard annotate attributes
3769 case Intrinsic::init_trampoline: {
3770 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3774 Ops[1] = getValue(I.getOperand(1));
3775 Ops[2] = getValue(I.getOperand(2));
3776 Ops[3] = getValue(I.getOperand(3));
3777 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3778 Ops[5] = DAG.getSrcValue(F);
3780 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3781 DAG.getNodeValueTypes(TLI.getPointerTy(),
3786 DAG.setRoot(Tmp.getValue(1));
3790 case Intrinsic::gcroot:
3792 Value *Alloca = I.getOperand(1);
3793 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3795 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
3796 GFI->addStackRoot(FI->getIndex(), TypeMap);
3800 case Intrinsic::gcread:
3801 case Intrinsic::gcwrite:
3802 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
3805 case Intrinsic::flt_rounds: {
3806 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3810 case Intrinsic::trap: {
3811 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3814 case Intrinsic::prefetch: {
3817 Ops[1] = getValue(I.getOperand(1));
3818 Ops[2] = getValue(I.getOperand(2));
3819 Ops[3] = getValue(I.getOperand(3));
3820 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3824 case Intrinsic::memory_barrier: {
3827 for (int x = 1; x < 6; ++x)
3828 Ops[x] = getValue(I.getOperand(x));
3830 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3833 case Intrinsic::atomic_cmp_swap: {
3834 SDValue Root = getRoot();
3836 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3838 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_8, Root,
3839 getValue(I.getOperand(1)),
3840 getValue(I.getOperand(2)),
3841 getValue(I.getOperand(3)),
3845 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_16, Root,
3846 getValue(I.getOperand(1)),
3847 getValue(I.getOperand(2)),
3848 getValue(I.getOperand(3)),
3852 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_32, Root,
3853 getValue(I.getOperand(1)),
3854 getValue(I.getOperand(2)),
3855 getValue(I.getOperand(3)),
3859 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_64, Root,
3860 getValue(I.getOperand(1)),
3861 getValue(I.getOperand(2)),
3862 getValue(I.getOperand(3)),
3866 assert(0 && "Invalid atomic type");
3870 DAG.setRoot(L.getValue(1));
3873 case Intrinsic::atomic_load_add:
3874 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3876 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_8);
3878 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_16);
3880 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_32);
3882 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_64);
3884 assert(0 && "Invalid atomic type");
3887 case Intrinsic::atomic_load_sub:
3888 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3890 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_8);
3892 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_16);
3894 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_32);
3896 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_64);
3898 assert(0 && "Invalid atomic type");
3901 case Intrinsic::atomic_load_or:
3902 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3904 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_8);
3906 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_16);
3908 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_32);
3910 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_64);
3912 assert(0 && "Invalid atomic type");
3915 case Intrinsic::atomic_load_xor:
3916 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3918 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_8);
3920 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_16);
3922 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_32);
3924 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_64);
3926 assert(0 && "Invalid atomic type");
3929 case Intrinsic::atomic_load_and:
3930 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3932 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_8);
3934 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_16);
3936 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_32);
3938 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_64);
3940 assert(0 && "Invalid atomic type");
3943 case Intrinsic::atomic_load_nand:
3944 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3946 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_8);
3948 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_16);
3950 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_32);
3952 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_64);
3954 assert(0 && "Invalid atomic type");
3957 case Intrinsic::atomic_load_max:
3958 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3960 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_8);
3962 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_16);
3964 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_32);
3966 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_64);
3968 assert(0 && "Invalid atomic type");
3971 case Intrinsic::atomic_load_min:
3972 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3974 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_8);
3976 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_16);
3978 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_32);
3980 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_64);
3982 assert(0 && "Invalid atomic type");
3985 case Intrinsic::atomic_load_umin:
3986 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3988 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_8);
3990 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_16);
3992 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_32);
3994 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_64);
3996 assert(0 && "Invalid atomic type");
3999 case Intrinsic::atomic_load_umax:
4000 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4002 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_8);
4004 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_16);
4006 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_32);
4008 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_64);
4010 assert(0 && "Invalid atomic type");
4013 case Intrinsic::atomic_swap:
4014 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
4016 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_8);
4018 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_16);
4020 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_32);
4022 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_64);
4024 assert(0 && "Invalid atomic type");
4031 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4033 MachineBasicBlock *LandingPad) {
4034 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4035 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4036 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4037 unsigned BeginLabel = 0, EndLabel = 0;
4039 TargetLowering::ArgListTy Args;
4040 TargetLowering::ArgListEntry Entry;
4041 Args.reserve(CS.arg_size());
4042 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4044 SDValue ArgNode = getValue(*i);
4045 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4047 unsigned attrInd = i - CS.arg_begin() + 1;
4048 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4049 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4050 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4051 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4052 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4053 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4054 Entry.Alignment = CS.getParamAlignment(attrInd);
4055 Args.push_back(Entry);
4058 if (LandingPad && MMI) {
4059 // Insert a label before the invoke call to mark the try range. This can be
4060 // used to detect deletion of the invoke via the MachineModuleInfo.
4061 BeginLabel = MMI->NextLabelID();
4062 // Both PendingLoads and PendingExports must be flushed here;
4063 // this call might not return.
4065 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
4068 std::pair<SDValue,SDValue> Result =
4069 TLI.LowerCallTo(getRoot(), CS.getType(),
4070 CS.paramHasAttr(0, Attribute::SExt),
4071 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4072 CS.paramHasAttr(0, Attribute::InReg),
4073 CS.getCallingConv(),
4074 IsTailCall && PerformTailCallOpt,
4076 if (CS.getType() != Type::VoidTy)
4077 setValue(CS.getInstruction(), Result.first);
4078 DAG.setRoot(Result.second);
4080 if (LandingPad && MMI) {
4081 // Insert a label at the end of the invoke call to mark the try range. This
4082 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4083 EndLabel = MMI->NextLabelID();
4084 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
4086 // Inform MachineModuleInfo of range.
4087 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4092 void SelectionDAGLowering::visitCall(CallInst &I) {
4093 const char *RenameFn = 0;
4094 if (Function *F = I.getCalledFunction()) {
4095 if (F->isDeclaration()) {
4096 if (unsigned IID = F->getIntrinsicID()) {
4097 RenameFn = visitIntrinsicCall(I, IID);
4103 // Check for well-known libc/libm calls. If the function is internal, it
4104 // can't be a library call.
4105 unsigned NameLen = F->getNameLen();
4106 if (!F->hasInternalLinkage() && NameLen) {
4107 const char *NameStr = F->getNameStart();
4108 if (NameStr[0] == 'c' &&
4109 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4110 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4111 if (I.getNumOperands() == 3 && // Basic sanity checks.
4112 I.getOperand(1)->getType()->isFloatingPoint() &&
4113 I.getType() == I.getOperand(1)->getType() &&
4114 I.getType() == I.getOperand(2)->getType()) {
4115 SDValue LHS = getValue(I.getOperand(1));
4116 SDValue RHS = getValue(I.getOperand(2));
4117 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
4121 } else if (NameStr[0] == 'f' &&
4122 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4123 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4124 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4125 if (I.getNumOperands() == 2 && // Basic sanity checks.
4126 I.getOperand(1)->getType()->isFloatingPoint() &&
4127 I.getType() == I.getOperand(1)->getType()) {
4128 SDValue Tmp = getValue(I.getOperand(1));
4129 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
4132 } else if (NameStr[0] == 's' &&
4133 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4134 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4135 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4136 if (I.getNumOperands() == 2 && // Basic sanity checks.
4137 I.getOperand(1)->getType()->isFloatingPoint() &&
4138 I.getType() == I.getOperand(1)->getType()) {
4139 SDValue Tmp = getValue(I.getOperand(1));
4140 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
4143 } else if (NameStr[0] == 'c' &&
4144 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4145 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4146 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4147 if (I.getNumOperands() == 2 && // Basic sanity checks.
4148 I.getOperand(1)->getType()->isFloatingPoint() &&
4149 I.getType() == I.getOperand(1)->getType()) {
4150 SDValue Tmp = getValue(I.getOperand(1));
4151 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
4156 } else if (isa<InlineAsm>(I.getOperand(0))) {
4163 Callee = getValue(I.getOperand(0));
4165 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4167 LowerCallTo(&I, Callee, I.isTailCall());
4171 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4172 /// this value and returns the result as a ValueVT value. This uses
4173 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4174 /// If the Flag pointer is NULL, no flag is used.
4175 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
4177 SDValue *Flag) const {
4178 // Assemble the legal parts into the final values.
4179 SmallVector<SDValue, 4> Values(ValueVTs.size());
4180 SmallVector<SDValue, 8> Parts;
4181 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4182 // Copy the legal parts from the registers.
4183 MVT ValueVT = ValueVTs[Value];
4184 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4185 MVT RegisterVT = RegVTs[Value];
4187 Parts.resize(NumRegs);
4188 for (unsigned i = 0; i != NumRegs; ++i) {
4191 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4193 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4194 *Flag = P.getValue(2);
4196 Chain = P.getValue(1);
4198 // If the source register was virtual and if we know something about it,
4199 // add an assert node.
4200 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4201 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4202 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4203 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4204 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4205 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4207 unsigned RegSize = RegisterVT.getSizeInBits();
4208 unsigned NumSignBits = LOI.NumSignBits;
4209 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4211 // FIXME: We capture more information than the dag can represent. For
4212 // now, just use the tightest assertzext/assertsext possible.
4214 MVT FromVT(MVT::Other);
4215 if (NumSignBits == RegSize)
4216 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4217 else if (NumZeroBits >= RegSize-1)
4218 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4219 else if (NumSignBits > RegSize-8)
4220 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4221 else if (NumZeroBits >= RegSize-9)
4222 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4223 else if (NumSignBits > RegSize-16)
4224 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4225 else if (NumZeroBits >= RegSize-17)
4226 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4227 else if (NumSignBits > RegSize-32)
4228 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4229 else if (NumZeroBits >= RegSize-33)
4230 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4232 if (FromVT != MVT::Other) {
4233 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
4234 RegisterVT, P, DAG.getValueType(FromVT));
4243 Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT,
4249 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4250 &Values[0], ValueVTs.size());
4253 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4254 /// specified value into the registers specified by this object. This uses
4255 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4256 /// If the Flag pointer is NULL, no flag is used.
4257 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
4258 SDValue &Chain, SDValue *Flag) const {
4259 // Get the list of the values's legal parts.
4260 unsigned NumRegs = Regs.size();
4261 SmallVector<SDValue, 8> Parts(NumRegs);
4262 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4263 MVT ValueVT = ValueVTs[Value];
4264 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4265 MVT RegisterVT = RegVTs[Value];
4267 getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
4268 &Parts[Part], NumParts, RegisterVT);
4272 // Copy the parts into the registers.
4273 SmallVector<SDValue, 8> Chains(NumRegs);
4274 for (unsigned i = 0; i != NumRegs; ++i) {
4277 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4279 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4280 *Flag = Part.getValue(1);
4282 Chains[i] = Part.getValue(0);
4285 if (NumRegs == 1 || Flag)
4286 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4287 // flagged to it. That is the CopyToReg nodes and the user are considered
4288 // a single scheduling unit. If we create a TokenFactor and return it as
4289 // chain, then the TokenFactor is both a predecessor (operand) of the
4290 // user as well as a successor (the TF operands are flagged to the user).
4291 // c1, f1 = CopyToReg
4292 // c2, f2 = CopyToReg
4293 // c3 = TokenFactor c1, c2
4296 Chain = Chains[NumRegs-1];
4298 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4301 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4302 /// operand list. This adds the code marker and includes the number of
4303 /// values added into it.
4304 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4305 std::vector<SDValue> &Ops) const {
4306 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4307 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4308 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4309 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4310 MVT RegisterVT = RegVTs[Value];
4311 for (unsigned i = 0; i != NumRegs; ++i) {
4312 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4313 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4318 /// isAllocatableRegister - If the specified register is safe to allocate,
4319 /// i.e. it isn't a stack pointer or some other special register, return the
4320 /// register class for the register. Otherwise, return null.
4321 static const TargetRegisterClass *
4322 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4323 const TargetLowering &TLI,
4324 const TargetRegisterInfo *TRI) {
4325 MVT FoundVT = MVT::Other;
4326 const TargetRegisterClass *FoundRC = 0;
4327 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4328 E = TRI->regclass_end(); RCI != E; ++RCI) {
4329 MVT ThisVT = MVT::Other;
4331 const TargetRegisterClass *RC = *RCI;
4332 // If none of the the value types for this register class are valid, we
4333 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4334 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4336 if (TLI.isTypeLegal(*I)) {
4337 // If we have already found this register in a different register class,
4338 // choose the one with the largest VT specified. For example, on
4339 // PowerPC, we favor f64 register classes over f32.
4340 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4347 if (ThisVT == MVT::Other) continue;
4349 // NOTE: This isn't ideal. In particular, this might allocate the
4350 // frame pointer in functions that need it (due to them not being taken
4351 // out of allocation, because a variable sized allocation hasn't been seen
4352 // yet). This is a slight code pessimization, but should still work.
4353 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4354 E = RC->allocation_order_end(MF); I != E; ++I)
4356 // We found a matching register class. Keep looking at others in case
4357 // we find one with larger registers that this physreg is also in.
4368 /// AsmOperandInfo - This contains information for each constraint that we are
4370 struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4371 public TargetLowering::AsmOperandInfo {
4372 /// CallOperand - If this is the result output operand or a clobber
4373 /// this is null, otherwise it is the incoming operand to the CallInst.
4374 /// This gets modified as the asm is processed.
4375 SDValue CallOperand;
4377 /// AssignedRegs - If this is a register or register class operand, this
4378 /// contains the set of register corresponding to the operand.
4379 RegsForValue AssignedRegs;
4381 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4382 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4385 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4386 /// busy in OutputRegs/InputRegs.
4387 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4388 std::set<unsigned> &OutputRegs,
4389 std::set<unsigned> &InputRegs,
4390 const TargetRegisterInfo &TRI) const {
4392 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4393 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4396 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4397 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4401 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4402 /// corresponds to. If there is no Value* for this operand, it returns
4404 MVT getCallOperandValMVT(const TargetLowering &TLI,
4405 const TargetData *TD) const {
4406 if (CallOperandVal == 0) return MVT::Other;
4408 if (isa<BasicBlock>(CallOperandVal))
4409 return TLI.getPointerTy();
4411 const llvm::Type *OpTy = CallOperandVal->getType();
4413 // If this is an indirect operand, the operand is a pointer to the
4416 OpTy = cast<PointerType>(OpTy)->getElementType();
4418 // If OpTy is not a single value, it may be a struct/union that we
4419 // can tile with integers.
4420 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4421 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4430 OpTy = IntegerType::get(BitSize);
4435 return TLI.getValueType(OpTy, true);
4439 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4441 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4442 const TargetRegisterInfo &TRI) {
4443 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4445 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4446 for (; *Aliases; ++Aliases)
4447 Regs.insert(*Aliases);
4450 } // end llvm namespace.
4453 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4454 /// specified operand. We prefer to assign virtual registers, to allow the
4455 /// register allocator handle the assignment process. However, if the asm uses
4456 /// features that we can't model on machineinstrs, we have SDISel do the
4457 /// allocation. This produces generally horrible, but correct, code.
4459 /// OpInfo describes the operand.
4460 /// Input and OutputRegs are the set of already allocated physical registers.
4462 void SelectionDAGLowering::
4463 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4464 std::set<unsigned> &OutputRegs,
4465 std::set<unsigned> &InputRegs) {
4466 // Compute whether this value requires an input register, an output register,
4468 bool isOutReg = false;
4469 bool isInReg = false;
4470 switch (OpInfo.Type) {
4471 case InlineAsm::isOutput:
4474 // If there is an input constraint that matches this, we need to reserve
4475 // the input register so no other inputs allocate to it.
4476 isInReg = OpInfo.hasMatchingInput();
4478 case InlineAsm::isInput:
4482 case InlineAsm::isClobber:
4489 MachineFunction &MF = DAG.getMachineFunction();
4490 SmallVector<unsigned, 4> Regs;
4492 // If this is a constraint for a single physreg, or a constraint for a
4493 // register class, find it.
4494 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4495 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4496 OpInfo.ConstraintVT);
4498 unsigned NumRegs = 1;
4499 if (OpInfo.ConstraintVT != MVT::Other)
4500 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4502 MVT ValueVT = OpInfo.ConstraintVT;
4505 // If this is a constraint for a specific physical register, like {r17},
4507 if (PhysReg.first) {
4508 if (OpInfo.ConstraintVT == MVT::Other)
4509 ValueVT = *PhysReg.second->vt_begin();
4511 // Get the actual register value type. This is important, because the user
4512 // may have asked for (e.g.) the AX register in i32 type. We need to
4513 // remember that AX is actually i16 to get the right extension.
4514 RegVT = *PhysReg.second->vt_begin();
4516 // This is a explicit reference to a physical register.
4517 Regs.push_back(PhysReg.first);
4519 // If this is an expanded reference, add the rest of the regs to Regs.
4521 TargetRegisterClass::iterator I = PhysReg.second->begin();
4522 for (; *I != PhysReg.first; ++I)
4523 assert(I != PhysReg.second->end() && "Didn't find reg!");
4525 // Already added the first reg.
4527 for (; NumRegs; --NumRegs, ++I) {
4528 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4532 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4533 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4534 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4538 // Otherwise, if this was a reference to an LLVM register class, create vregs
4539 // for this reference.
4540 std::vector<unsigned> RegClassRegs;
4541 const TargetRegisterClass *RC = PhysReg.second;
4543 // If this is a tied register, our regalloc doesn't know how to maintain
4544 // the constraint, so we have to pick a register to pin the input/output to.
4545 // If it isn't a matched constraint, go ahead and create vreg and let the
4546 // regalloc do its thing.
4547 if (!OpInfo.hasMatchingInput()) {
4548 RegVT = *PhysReg.second->vt_begin();
4549 if (OpInfo.ConstraintVT == MVT::Other)
4552 // Create the appropriate number of virtual registers.
4553 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4554 for (; NumRegs; --NumRegs)
4555 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4557 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4561 // Otherwise, we can't allocate it. Let the code below figure out how to
4562 // maintain these constraints.
4563 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4566 // This is a reference to a register class that doesn't directly correspond
4567 // to an LLVM register class. Allocate NumRegs consecutive, available,
4568 // registers from the class.
4569 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4570 OpInfo.ConstraintVT);
4573 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4574 unsigned NumAllocated = 0;
4575 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4576 unsigned Reg = RegClassRegs[i];
4577 // See if this register is available.
4578 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4579 (isInReg && InputRegs.count(Reg))) { // Already used.
4580 // Make sure we find consecutive registers.
4585 // Check to see if this register is allocatable (i.e. don't give out the
4588 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4589 if (!RC) { // Couldn't allocate this register.
4590 // Reset NumAllocated to make sure we return consecutive registers.
4596 // Okay, this register is good, we can use it.
4599 // If we allocated enough consecutive registers, succeed.
4600 if (NumAllocated == NumRegs) {
4601 unsigned RegStart = (i-NumAllocated)+1;
4602 unsigned RegEnd = i+1;
4603 // Mark all of the allocated registers used.
4604 for (unsigned i = RegStart; i != RegEnd; ++i)
4605 Regs.push_back(RegClassRegs[i]);
4607 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4608 OpInfo.ConstraintVT);
4609 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4614 // Otherwise, we couldn't allocate enough registers for this.
4617 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4618 /// processed uses a memory 'm' constraint.
4620 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4621 TargetLowering &TLI) {
4622 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4623 InlineAsm::ConstraintInfo &CI = CInfos[i];
4624 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4625 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4626 if (CType == TargetLowering::C_Memory)
4634 /// visitInlineAsm - Handle a call to an InlineAsm object.
4636 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4637 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4639 /// ConstraintOperands - Information about all of the constraints.
4640 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4642 SDValue Chain = getRoot();
4645 std::set<unsigned> OutputRegs, InputRegs;
4647 // Do a prepass over the constraints, canonicalizing them, and building up the
4648 // ConstraintOperands list.
4649 std::vector<InlineAsm::ConstraintInfo>
4650 ConstraintInfos = IA->ParseConstraints();
4652 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
4654 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4655 unsigned ResNo = 0; // ResNo - The result number of the next output.
4656 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4657 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4658 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4660 MVT OpVT = MVT::Other;
4662 // Compute the value type for each operand.
4663 switch (OpInfo.Type) {
4664 case InlineAsm::isOutput:
4665 // Indirect outputs just consume an argument.
4666 if (OpInfo.isIndirect) {
4667 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4671 // The return value of the call is this value. As such, there is no
4672 // corresponding argument.
4673 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4674 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4675 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4677 assert(ResNo == 0 && "Asm only has one result!");
4678 OpVT = TLI.getValueType(CS.getType());
4682 case InlineAsm::isInput:
4683 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4685 case InlineAsm::isClobber:
4690 // If this is an input or an indirect output, process the call argument.
4691 // BasicBlocks are labels, currently appearing only in asm's.
4692 if (OpInfo.CallOperandVal) {
4693 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
4694 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4696 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4699 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
4702 OpInfo.ConstraintVT = OpVT;
4705 // Second pass over the constraints: compute which constraint option to use
4706 // and assign registers to constraints that want a specific physreg.
4707 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4708 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4710 // If this is an output operand with a matching input operand, look up the
4711 // matching input. It might have a different type (e.g. the output might be
4712 // i32 and the input i64) and we need to pick the larger width to ensure we
4713 // reserve the right number of registers.
4714 if (OpInfo.hasMatchingInput()) {
4715 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
4716 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
4717 assert(OpInfo.ConstraintVT.isInteger() &&
4718 Input.ConstraintVT.isInteger() &&
4719 "Asm constraints must be the same or different sized integers");
4720 if (OpInfo.ConstraintVT.getSizeInBits() <
4721 Input.ConstraintVT.getSizeInBits())
4722 OpInfo.ConstraintVT = Input.ConstraintVT;
4724 Input.ConstraintVT = OpInfo.ConstraintVT;
4728 // Compute the constraint code and ConstraintType to use.
4729 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
4731 // If this is a memory input, and if the operand is not indirect, do what we
4732 // need to to provide an address for the memory input.
4733 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4734 !OpInfo.isIndirect) {
4735 assert(OpInfo.Type == InlineAsm::isInput &&
4736 "Can only indirectify direct input operands!");
4738 // Memory operands really want the address of the value. If we don't have
4739 // an indirect input, put it in the constpool if we can, otherwise spill
4740 // it to a stack slot.
4742 // If the operand is a float, integer, or vector constant, spill to a
4743 // constant pool entry to get its address.
4744 Value *OpVal = OpInfo.CallOperandVal;
4745 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4746 isa<ConstantVector>(OpVal)) {
4747 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4748 TLI.getPointerTy());
4750 // Otherwise, create a stack slot and emit a store to it before the
4752 const Type *Ty = OpVal->getType();
4753 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4754 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4755 MachineFunction &MF = DAG.getMachineFunction();
4756 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4757 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4758 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4759 OpInfo.CallOperand = StackSlot;
4762 // There is no longer a Value* corresponding to this operand.
4763 OpInfo.CallOperandVal = 0;
4764 // It is now an indirect operand.
4765 OpInfo.isIndirect = true;
4768 // If this constraint is for a specific register, allocate it before
4770 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4771 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4773 ConstraintInfos.clear();
4776 // Second pass - Loop over all of the operands, assigning virtual or physregs
4777 // to register class operands.
4778 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4779 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4781 // C_Register operands have already been allocated, Other/Memory don't need
4783 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4784 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
4787 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4788 std::vector<SDValue> AsmNodeOperands;
4789 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4790 AsmNodeOperands.push_back(
4791 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4794 // Loop over all of the inputs, copying the operand values into the
4795 // appropriate registers and processing the output regs.
4796 RegsForValue RetValRegs;
4798 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4799 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4801 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4802 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4804 switch (OpInfo.Type) {
4805 case InlineAsm::isOutput: {
4806 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4807 OpInfo.ConstraintType != TargetLowering::C_Register) {
4808 // Memory output, or 'other' output (e.g. 'X' constraint).
4809 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4811 // Add information to the INLINEASM node to know about this output.
4812 unsigned ResOpType = 4/*MEM*/ | (1<<3);
4813 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4814 TLI.getPointerTy()));
4815 AsmNodeOperands.push_back(OpInfo.CallOperand);
4819 // Otherwise, this is a register or register class output.
4821 // Copy the output from the appropriate register. Find a register that
4823 if (OpInfo.AssignedRegs.Regs.empty()) {
4824 cerr << "Couldn't allocate output reg for constraint '"
4825 << OpInfo.ConstraintCode << "'!\n";
4829 // If this is an indirect operand, store through the pointer after the
4831 if (OpInfo.isIndirect) {
4832 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4833 OpInfo.CallOperandVal));
4835 // This is the result value of the call.
4836 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4837 // Concatenate this output onto the outputs list.
4838 RetValRegs.append(OpInfo.AssignedRegs);
4841 // Add information to the INLINEASM node to know that this register is
4843 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
4844 6 /* EARLYCLOBBER REGDEF */ :
4846 DAG, AsmNodeOperands);
4849 case InlineAsm::isInput: {
4850 SDValue InOperandVal = OpInfo.CallOperand;
4852 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
4853 // If this is required to match an output register we have already set,
4854 // just use its register.
4855 unsigned OperandNo = OpInfo.getMatchedOperand();
4857 // Scan until we find the definition we already emitted of this operand.
4858 // When we find it, create a RegsForValue operand.
4859 unsigned CurOp = 2; // The first operand.
4860 for (; OperandNo; --OperandNo) {
4861 // Advance to the next operand.
4863 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
4864 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4865 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
4866 (NumOps & 7) == 4 /*MEM*/) &&
4867 "Skipped past definitions?");
4868 CurOp += (NumOps>>3)+1;
4872 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
4873 if ((NumOps & 7) == 2 /*REGDEF*/
4874 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
4875 // Add NumOps>>3 registers to MatchedRegs.
4876 RegsForValue MatchedRegs;
4877 MatchedRegs.TLI = &TLI;
4878 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4879 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4880 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4882 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4883 MatchedRegs.Regs.push_back(Reg);
4886 // Use the produced MatchedRegs object to
4887 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4888 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4891 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
4892 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4893 // Add information to the INLINEASM node to know about this input.
4894 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
4895 TLI.getPointerTy()));
4896 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4901 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4902 assert(!OpInfo.isIndirect &&
4903 "Don't know how to handle indirect other inputs yet!");
4905 std::vector<SDValue> Ops;
4906 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4907 hasMemory, Ops, DAG);
4909 cerr << "Invalid operand for inline asm constraint '"
4910 << OpInfo.ConstraintCode << "'!\n";
4914 // Add information to the INLINEASM node to know about this input.
4915 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4916 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4917 TLI.getPointerTy()));
4918 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4920 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4921 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4922 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4923 "Memory operands expect pointer values");
4925 // Add information to the INLINEASM node to know about this input.
4926 unsigned ResOpType = 4/*MEM*/ | (1<<3);
4927 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4928 TLI.getPointerTy()));
4929 AsmNodeOperands.push_back(InOperandVal);
4933 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4934 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4935 "Unknown constraint type!");
4936 assert(!OpInfo.isIndirect &&
4937 "Don't know how to handle indirect register inputs yet!");
4939 // Copy the input into the appropriate registers.
4940 if (OpInfo.AssignedRegs.Regs.empty()) {
4941 cerr << "Couldn't allocate output reg for constraint '"
4942 << OpInfo.ConstraintCode << "'!\n";
4946 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4948 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
4949 DAG, AsmNodeOperands);
4952 case InlineAsm::isClobber: {
4953 // Add the clobbered value to the operand list, so that the register
4954 // allocator is aware that the physreg got clobbered.
4955 if (!OpInfo.AssignedRegs.Regs.empty())
4956 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
4957 DAG, AsmNodeOperands);
4963 // Finish up input operands.
4964 AsmNodeOperands[0] = Chain;
4965 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
4967 Chain = DAG.getNode(ISD::INLINEASM,
4968 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4969 &AsmNodeOperands[0], AsmNodeOperands.size());
4970 Flag = Chain.getValue(1);
4972 // If this asm returns a register value, copy the result from that register
4973 // and set it as the value of the call.
4974 if (!RetValRegs.Regs.empty()) {
4975 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4976 MVT ResultType = TLI.getValueType(CS.getType());
4978 // If any of the results of the inline asm is a vector, it may have the
4979 // wrong width/num elts. This can happen for register classes that can
4980 // contain multiple different value types. The preg or vreg allocated may
4981 // not have the same VT as was expected. Convert it to the right type
4982 // with bit_convert.
4983 // FIXME: Is this sufficient for inline asms with MRVs?
4984 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
4985 Val = DAG.getNode(ISD::BIT_CONVERT, ResultType, Val);
4987 } else if (ResultType != Val.getValueType() &&
4988 ResultType.isInteger() && Val.getValueType().isInteger()) {
4989 // If a result value was tied to an input value, the computed result may
4990 // have a wider width than the expected result. Extract the relevant
4992 Val = DAG.getNode(ISD::TRUNCATE, ResultType, Val);
4995 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
4996 setValue(CS.getInstruction(), Val);
4999 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5001 // Process indirect outputs, first output all of the flagged copies out of
5003 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5004 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5005 Value *Ptr = IndirectStoresToEmit[i].second;
5006 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
5007 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5010 // Emit the non-flagged stores from the physregs.
5011 SmallVector<SDValue, 8> OutChains;
5012 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5013 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
5014 getValue(StoresToEmit[i].second),
5015 StoresToEmit[i].second, 0));
5016 if (!OutChains.empty())
5017 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5018 &OutChains[0], OutChains.size());
5023 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5024 SDValue Src = getValue(I.getOperand(0));
5026 MVT IntPtr = TLI.getPointerTy();
5028 if (IntPtr.bitsLT(Src.getValueType()))
5029 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
5030 else if (IntPtr.bitsGT(Src.getValueType()))
5031 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
5033 // Scale the source by the type size.
5034 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
5035 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
5036 Src, DAG.getIntPtrConstant(ElementSize));
5038 TargetLowering::ArgListTy Args;
5039 TargetLowering::ArgListEntry Entry;
5041 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5042 Args.push_back(Entry);
5044 std::pair<SDValue,SDValue> Result =
5045 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5046 CallingConv::C, PerformTailCallOpt,
5047 DAG.getExternalSymbol("malloc", IntPtr),
5049 setValue(&I, Result.first); // Pointers always fit in registers
5050 DAG.setRoot(Result.second);
5053 void SelectionDAGLowering::visitFree(FreeInst &I) {
5054 TargetLowering::ArgListTy Args;
5055 TargetLowering::ArgListEntry Entry;
5056 Entry.Node = getValue(I.getOperand(0));
5057 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5058 Args.push_back(Entry);
5059 MVT IntPtr = TLI.getPointerTy();
5060 std::pair<SDValue,SDValue> Result =
5061 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5062 CallingConv::C, PerformTailCallOpt,
5063 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
5064 DAG.setRoot(Result.second);
5067 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5068 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
5069 getValue(I.getOperand(1)),
5070 DAG.getSrcValue(I.getOperand(1))));
5073 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5074 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
5075 getValue(I.getOperand(0)),
5076 DAG.getSrcValue(I.getOperand(0)));
5078 DAG.setRoot(V.getValue(1));
5081 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5082 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
5083 getValue(I.getOperand(1)),
5084 DAG.getSrcValue(I.getOperand(1))));
5087 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5088 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
5089 getValue(I.getOperand(1)),
5090 getValue(I.getOperand(2)),
5091 DAG.getSrcValue(I.getOperand(1)),
5092 DAG.getSrcValue(I.getOperand(2))));
5095 /// TargetLowering::LowerArguments - This is the default LowerArguments
5096 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5097 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5098 /// integrated into SDISel.
5099 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5100 SmallVectorImpl<SDValue> &ArgValues) {
5101 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5102 SmallVector<SDValue, 3+16> Ops;
5103 Ops.push_back(DAG.getRoot());
5104 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5105 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5107 // Add one result value for each formal argument.
5108 SmallVector<MVT, 16> RetVals;
5110 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5112 SmallVector<MVT, 4> ValueVTs;
5113 ComputeValueVTs(*this, I->getType(), ValueVTs);
5114 for (unsigned Value = 0, NumValues = ValueVTs.size();
5115 Value != NumValues; ++Value) {
5116 MVT VT = ValueVTs[Value];
5117 const Type *ArgTy = VT.getTypeForMVT();
5118 ISD::ArgFlagsTy Flags;
5119 unsigned OriginalAlignment =
5120 getTargetData()->getABITypeAlignment(ArgTy);
5122 if (F.paramHasAttr(j, Attribute::ZExt))
5124 if (F.paramHasAttr(j, Attribute::SExt))
5126 if (F.paramHasAttr(j, Attribute::InReg))
5128 if (F.paramHasAttr(j, Attribute::StructRet))
5130 if (F.paramHasAttr(j, Attribute::ByVal)) {
5132 const PointerType *Ty = cast<PointerType>(I->getType());
5133 const Type *ElementTy = Ty->getElementType();
5134 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5135 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5136 // For ByVal, alignment should be passed from FE. BE will guess if
5137 // this info is not there but there are cases it cannot get right.
5138 if (F.getParamAlignment(j))
5139 FrameAlign = F.getParamAlignment(j);
5140 Flags.setByValAlign(FrameAlign);
5141 Flags.setByValSize(FrameSize);
5143 if (F.paramHasAttr(j, Attribute::Nest))
5145 Flags.setOrigAlign(OriginalAlignment);
5147 MVT RegisterVT = getRegisterType(VT);
5148 unsigned NumRegs = getNumRegisters(VT);
5149 for (unsigned i = 0; i != NumRegs; ++i) {
5150 RetVals.push_back(RegisterVT);
5151 ISD::ArgFlagsTy MyFlags = Flags;
5152 if (NumRegs > 1 && i == 0)
5154 // if it isn't first piece, alignment must be 1
5156 MyFlags.setOrigAlign(1);
5157 Ops.push_back(DAG.getArgFlags(MyFlags));
5162 RetVals.push_back(MVT::Other);
5165 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
5166 DAG.getVTList(&RetVals[0], RetVals.size()),
5167 &Ops[0], Ops.size()).getNode();
5169 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5170 // allows exposing the loads that may be part of the argument access to the
5171 // first DAGCombiner pass.
5172 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5174 // The number of results should match up, except that the lowered one may have
5175 // an extra flag result.
5176 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5177 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5178 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5179 && "Lowering produced unexpected number of results!");
5181 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5182 if (Result != TmpRes.getNode() && Result->use_empty()) {
5183 HandleSDNode Dummy(DAG.getRoot());
5184 DAG.RemoveDeadNode(Result);
5187 Result = TmpRes.getNode();
5189 unsigned NumArgRegs = Result->getNumValues() - 1;
5190 DAG.setRoot(SDValue(Result, NumArgRegs));
5192 // Set up the return result vector.
5195 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5197 SmallVector<MVT, 4> ValueVTs;
5198 ComputeValueVTs(*this, I->getType(), ValueVTs);
5199 for (unsigned Value = 0, NumValues = ValueVTs.size();
5200 Value != NumValues; ++Value) {
5201 MVT VT = ValueVTs[Value];
5202 MVT PartVT = getRegisterType(VT);
5204 unsigned NumParts = getNumRegisters(VT);
5205 SmallVector<SDValue, 4> Parts(NumParts);
5206 for (unsigned j = 0; j != NumParts; ++j)
5207 Parts[j] = SDValue(Result, i++);
5209 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5210 if (F.paramHasAttr(Idx, Attribute::SExt))
5211 AssertOp = ISD::AssertSext;
5212 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5213 AssertOp = ISD::AssertZext;
5215 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
5219 assert(i == NumArgRegs && "Argument register count mismatch!");
5223 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5224 /// implementation, which just inserts an ISD::CALL node, which is later custom
5225 /// lowered by the target to something concrete. FIXME: When all targets are
5226 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5227 std::pair<SDValue, SDValue>
5228 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5229 bool RetSExt, bool RetZExt, bool isVarArg,
5231 unsigned CallingConv, bool isTailCall,
5233 ArgListTy &Args, SelectionDAG &DAG) {
5234 assert((!isTailCall || PerformTailCallOpt) &&
5235 "isTailCall set when tail-call optimizations are disabled!");
5237 SmallVector<SDValue, 32> Ops;
5238 Ops.push_back(Chain); // Op#0 - Chain
5239 Ops.push_back(Callee);
5241 // Handle all of the outgoing arguments.
5242 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5243 SmallVector<MVT, 4> ValueVTs;
5244 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5245 for (unsigned Value = 0, NumValues = ValueVTs.size();
5246 Value != NumValues; ++Value) {
5247 MVT VT = ValueVTs[Value];
5248 const Type *ArgTy = VT.getTypeForMVT();
5249 SDValue Op = SDValue(Args[i].Node.getNode(),
5250 Args[i].Node.getResNo() + Value);
5251 ISD::ArgFlagsTy Flags;
5252 unsigned OriginalAlignment =
5253 getTargetData()->getABITypeAlignment(ArgTy);
5259 if (Args[i].isInReg)
5263 if (Args[i].isByVal) {
5265 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5266 const Type *ElementTy = Ty->getElementType();
5267 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5268 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5269 // For ByVal, alignment should come from FE. BE will guess if this
5270 // info is not there but there are cases it cannot get right.
5271 if (Args[i].Alignment)
5272 FrameAlign = Args[i].Alignment;
5273 Flags.setByValAlign(FrameAlign);
5274 Flags.setByValSize(FrameSize);
5278 Flags.setOrigAlign(OriginalAlignment);
5280 MVT PartVT = getRegisterType(VT);
5281 unsigned NumParts = getNumRegisters(VT);
5282 SmallVector<SDValue, 4> Parts(NumParts);
5283 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5286 ExtendKind = ISD::SIGN_EXTEND;
5287 else if (Args[i].isZExt)
5288 ExtendKind = ISD::ZERO_EXTEND;
5290 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5292 for (unsigned i = 0; i != NumParts; ++i) {
5293 // if it isn't first piece, alignment must be 1
5294 ISD::ArgFlagsTy MyFlags = Flags;
5295 if (NumParts > 1 && i == 0)
5298 MyFlags.setOrigAlign(1);
5300 Ops.push_back(Parts[i]);
5301 Ops.push_back(DAG.getArgFlags(MyFlags));
5306 // Figure out the result value types. We start by making a list of
5307 // the potentially illegal return value types.
5308 SmallVector<MVT, 4> LoweredRetTys;
5309 SmallVector<MVT, 4> RetTys;
5310 ComputeValueVTs(*this, RetTy, RetTys);
5312 // Then we translate that to a list of legal types.
5313 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5315 MVT RegisterVT = getRegisterType(VT);
5316 unsigned NumRegs = getNumRegisters(VT);
5317 for (unsigned i = 0; i != NumRegs; ++i)
5318 LoweredRetTys.push_back(RegisterVT);
5321 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5323 // Create the CALL node.
5324 SDValue Res = DAG.getCall(CallingConv, isVarArg, isTailCall, isInreg,
5325 DAG.getVTList(&LoweredRetTys[0],
5326 LoweredRetTys.size()),
5329 Chain = Res.getValue(LoweredRetTys.size() - 1);
5331 // Gather up the call result into a single value.
5332 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5333 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5336 AssertOp = ISD::AssertSext;
5338 AssertOp = ISD::AssertZext;
5340 SmallVector<SDValue, 4> ReturnValues;
5342 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5344 MVT RegisterVT = getRegisterType(VT);
5345 unsigned NumRegs = getNumRegisters(VT);
5346 unsigned RegNoEnd = NumRegs + RegNo;
5347 SmallVector<SDValue, 4> Results;
5348 for (; RegNo != RegNoEnd; ++RegNo)
5349 Results.push_back(Res.getValue(RegNo));
5350 SDValue ReturnValue =
5351 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
5353 ReturnValues.push_back(ReturnValue);
5355 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
5356 &ReturnValues[0], ReturnValues.size());
5359 return std::make_pair(Res, Chain);
5362 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5363 assert(0 && "LowerOperation not implemented for this target!");
5369 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5370 SDValue Op = getValue(V);
5371 assert((Op.getOpcode() != ISD::CopyFromReg ||
5372 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5373 "Copy from a reg to the same reg!");
5374 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5376 RegsForValue RFV(TLI, Reg, V->getType());
5377 SDValue Chain = DAG.getEntryNode();
5378 RFV.getCopyToRegs(Op, DAG, Chain, 0);
5379 PendingExports.push_back(Chain);
5382 #include "llvm/CodeGen/SelectionDAGISel.h"
5384 void SelectionDAGISel::
5385 LowerArguments(BasicBlock *LLVMBB) {
5386 // If this is the entry block, emit arguments.
5387 Function &F = *LLVMBB->getParent();
5388 SDValue OldRoot = SDL->DAG.getRoot();
5389 SmallVector<SDValue, 16> Args;
5390 TLI.LowerArguments(F, SDL->DAG, Args);
5393 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5395 SmallVector<MVT, 4> ValueVTs;
5396 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5397 unsigned NumValues = ValueVTs.size();
5398 if (!AI->use_empty()) {
5399 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5400 // If this argument is live outside of the entry block, insert a copy from
5401 // whereever we got it to the vreg that other BB's will reference it as.
5402 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5403 if (VMI != FuncInfo->ValueMap.end()) {
5404 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5410 // Finally, if the target has anything special to do, allow it to do so.
5411 // FIXME: this should insert code into the DAG!
5412 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5415 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5416 /// ensure constants are generated when needed. Remember the virtual registers
5417 /// that need to be added to the Machine PHI nodes as input. We cannot just
5418 /// directly add them, because expansion might result in multiple MBB's for one
5419 /// BB. As such, the start of the BB might correspond to a different MBB than
5423 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5424 TerminatorInst *TI = LLVMBB->getTerminator();
5426 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5428 // Check successor nodes' PHI nodes that expect a constant to be available
5430 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5431 BasicBlock *SuccBB = TI->getSuccessor(succ);
5432 if (!isa<PHINode>(SuccBB->begin())) continue;
5433 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5435 // If this terminator has multiple identical successors (common for
5436 // switches), only handle each succ once.
5437 if (!SuccsHandled.insert(SuccMBB)) continue;
5439 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5442 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5443 // nodes and Machine PHI nodes, but the incoming operands have not been
5445 for (BasicBlock::iterator I = SuccBB->begin();
5446 (PN = dyn_cast<PHINode>(I)); ++I) {
5447 // Ignore dead phi's.
5448 if (PN->use_empty()) continue;
5451 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5453 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5454 unsigned &RegOut = SDL->ConstantsOut[C];
5456 RegOut = FuncInfo->CreateRegForValue(C);
5457 SDL->CopyValueToVirtualRegister(C, RegOut);
5461 Reg = FuncInfo->ValueMap[PHIOp];
5463 assert(isa<AllocaInst>(PHIOp) &&
5464 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5465 "Didn't codegen value into a register!??");
5466 Reg = FuncInfo->CreateRegForValue(PHIOp);
5467 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5471 // Remember that this register needs to added to the machine PHI node as
5472 // the input for this MBB.
5473 SmallVector<MVT, 4> ValueVTs;
5474 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5475 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5476 MVT VT = ValueVTs[vti];
5477 unsigned NumRegisters = TLI.getNumRegisters(VT);
5478 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5479 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5480 Reg += NumRegisters;
5484 SDL->ConstantsOut.clear();
5487 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5488 /// supports legal types, and it emits MachineInstrs directly instead of
5489 /// creating SelectionDAG nodes.
5492 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5494 TerminatorInst *TI = LLVMBB->getTerminator();
5496 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5497 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5499 // Check successor nodes' PHI nodes that expect a constant to be available
5501 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5502 BasicBlock *SuccBB = TI->getSuccessor(succ);
5503 if (!isa<PHINode>(SuccBB->begin())) continue;
5504 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5506 // If this terminator has multiple identical successors (common for
5507 // switches), only handle each succ once.
5508 if (!SuccsHandled.insert(SuccMBB)) continue;
5510 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5513 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5514 // nodes and Machine PHI nodes, but the incoming operands have not been
5516 for (BasicBlock::iterator I = SuccBB->begin();
5517 (PN = dyn_cast<PHINode>(I)); ++I) {
5518 // Ignore dead phi's.
5519 if (PN->use_empty()) continue;
5521 // Only handle legal types. Two interesting things to note here. First,
5522 // by bailing out early, we may leave behind some dead instructions,
5523 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5524 // own moves. Second, this check is necessary becuase FastISel doesn't
5525 // use CreateRegForValue to create registers, so it always creates
5526 // exactly one register for each non-void instruction.
5527 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5528 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5531 VT = TLI.getTypeToTransformTo(VT);
5533 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5538 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5540 unsigned Reg = F->getRegForValue(PHIOp);
5542 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5545 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));