1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/IntegersSubsetMapping.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetIntrinsicInfo.h"
58 #include "llvm/Target/TargetLibraryInfo.h"
59 #include "llvm/Target/TargetLowering.h"
60 #include "llvm/Target/TargetOptions.h"
64 /// LimitFloatPrecision - Generate low-precision inline sequences for
65 /// some float libcalls (6, 8 or 12 bits).
66 static unsigned LimitFloatPrecision;
68 static cl::opt<unsigned, true>
69 LimitFPPrecision("limit-float-precision",
70 cl::desc("Generate low-precision inline sequences "
71 "for some float libcalls"),
72 cl::location(LimitFloatPrecision),
75 // Limit the width of DAG chains. This is important in general to prevent
76 // prevent DAG-based analysis from blowing up. For example, alias analysis and
77 // load clustering may not complete in reasonable time. It is difficult to
78 // recognize and avoid this situation within each individual analysis, and
79 // future analyses are likely to have the same behavior. Limiting DAG width is
80 // the safe approach, and will be especially important with global DAGs.
82 // MaxParallelChains default is arbitrarily high to avoid affecting
83 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
84 // sequence over this should have been converted to llvm.memcpy by the
85 // frontend. It easy to induce this behavior with .ll code such as:
86 // %buffer = alloca [4096 x i8]
87 // %data = load [4096 x i8]* %argPtr
88 // store [4096 x i8] %data, [4096 x i8]* %buffer
89 static const unsigned MaxParallelChains = 64;
91 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
92 const SDValue *Parts, unsigned NumParts,
93 MVT PartVT, EVT ValueVT, const Value *V);
95 /// getCopyFromParts - Create a value that contains the specified legal parts
96 /// combined into the value they represent. If the parts combine to a type
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
100 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
101 const SDValue *Parts,
102 unsigned NumParts, MVT PartVT, EVT ValueVT,
104 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
105 if (ValueVT.isVector())
106 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
109 assert(NumParts > 0 && "No parts to assemble!");
110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
111 SDValue Val = Parts[0];
114 // Assemble the value from multiple parts.
115 if (ValueVT.isInteger()) {
116 unsigned PartBits = PartVT.getSizeInBits();
117 unsigned ValueBits = ValueVT.getSizeInBits();
119 // Assemble the power of 2 part.
120 unsigned RoundParts = NumParts & (NumParts - 1) ?
121 1 << Log2_32(NumParts) : NumParts;
122 unsigned RoundBits = PartBits * RoundParts;
123 EVT RoundVT = RoundBits == ValueBits ?
124 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
127 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
129 if (RoundParts > 2) {
130 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
132 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
133 RoundParts / 2, PartVT, HalfVT, V);
135 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
136 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
139 if (TLI.isBigEndian())
142 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
144 if (RoundParts < NumParts) {
145 // Assemble the trailing non-power-of-2 part.
146 unsigned OddParts = NumParts - RoundParts;
147 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
148 Hi = getCopyFromParts(DAG, DL,
149 Parts + RoundParts, OddParts, PartVT, OddVT, V);
151 // Combine the round and odd parts.
153 if (TLI.isBigEndian())
155 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
156 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
157 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
158 DAG.getConstant(Lo.getValueType().getSizeInBits(),
159 TLI.getPointerTy()));
160 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
161 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
163 } else if (PartVT.isFloatingPoint()) {
164 // FP split into multiple FP parts (for ppcf128)
165 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
168 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
169 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
170 if (TLI.isBigEndian())
172 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
174 // FP split into integer parts (soft fp)
175 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
176 !PartVT.isVector() && "Unexpected split");
177 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
178 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
182 // There is now one part, held in Val. Correct it to match ValueVT.
183 EVT PartEVT = Val.getValueType();
185 if (PartEVT == ValueVT)
188 if (PartEVT.isInteger() && ValueVT.isInteger()) {
189 if (ValueVT.bitsLT(PartEVT)) {
190 // For a truncate, see if we have any information to
191 // indicate whether the truncated bits will always be
192 // zero or sign-extension.
193 if (AssertOp != ISD::DELETED_NODE)
194 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
195 DAG.getValueType(ValueVT));
196 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
198 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
201 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
202 // FP_ROUND's are always exact here.
203 if (ValueVT.bitsLT(Val.getValueType()))
204 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
205 DAG.getTargetConstant(1, TLI.getPointerTy()));
207 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
210 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
211 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
213 llvm_unreachable("Unknown mismatch!");
216 /// getCopyFromPartsVector - Create a value that contains the specified legal
217 /// parts combined into the value they represent. If the parts combine to a
218 /// type larger then ValueVT then AssertOp can be used to specify whether the
219 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
220 /// ValueVT (ISD::AssertSext).
221 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
222 const SDValue *Parts, unsigned NumParts,
223 MVT PartVT, EVT ValueVT, const Value *V) {
224 assert(ValueVT.isVector() && "Not a vector value");
225 assert(NumParts > 0 && "No parts to assemble!");
226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
227 SDValue Val = Parts[0];
229 // Handle a multi-element vector.
233 unsigned NumIntermediates;
235 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
236 NumIntermediates, RegisterVT);
237 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
238 NumParts = NumRegs; // Silence a compiler warning.
239 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
240 assert(RegisterVT == Parts[0].getSimpleValueType() &&
241 "Part type doesn't match part!");
243 // Assemble the parts into intermediate operands.
244 SmallVector<SDValue, 8> Ops(NumIntermediates);
245 if (NumIntermediates == NumParts) {
246 // If the register was not expanded, truncate or copy the value,
248 for (unsigned i = 0; i != NumParts; ++i)
249 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
250 PartVT, IntermediateVT, V);
251 } else if (NumParts > 0) {
252 // If the intermediate type was expanded, build the intermediate
253 // operands from the parts.
254 assert(NumParts % NumIntermediates == 0 &&
255 "Must expand into a divisible number of parts!");
256 unsigned Factor = NumParts / NumIntermediates;
257 for (unsigned i = 0; i != NumIntermediates; ++i)
258 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
259 PartVT, IntermediateVT, V);
262 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
263 // intermediate operands.
264 Val = DAG.getNode(IntermediateVT.isVector() ?
265 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
266 ValueVT, &Ops[0], NumIntermediates);
269 // There is now one part, held in Val. Correct it to match ValueVT.
270 EVT PartEVT = Val.getValueType();
272 if (PartEVT == ValueVT)
275 if (PartEVT.isVector()) {
276 // If the element type of the source/dest vectors are the same, but the
277 // parts vector has more elements than the value vector, then we have a
278 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
280 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
281 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
282 "Cannot narrow, it would be a lossy transformation");
283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
284 DAG.getIntPtrConstant(0));
287 // Vector/Vector bitcast.
288 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
289 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
291 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
292 "Cannot handle this kind of promotion");
293 // Promoted vector extract
294 bool Smaller = ValueVT.bitsLE(PartEVT);
295 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
300 // Trivial bitcast if the types are the same size and the destination
301 // vector type is legal.
302 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
303 TLI.isTypeLegal(ValueVT))
304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
306 // Handle cases such as i8 -> <1 x i1>
307 if (ValueVT.getVectorNumElements() != 1) {
308 LLVMContext &Ctx = *DAG.getContext();
309 Twine ErrMsg("non-trivial scalar-to-vector conversion");
310 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
311 if (const CallInst *CI = dyn_cast<CallInst>(I))
312 if (isa<InlineAsm>(CI->getCalledValue()))
313 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
314 Ctx.emitError(I, ErrMsg);
316 Ctx.emitError(ErrMsg);
318 return DAG.getUNDEF(ValueVT);
321 if (ValueVT.getVectorNumElements() == 1 &&
322 ValueVT.getVectorElementType() != PartEVT) {
323 bool Smaller = ValueVT.bitsLE(PartEVT);
324 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
325 DL, ValueVT.getScalarType(), Val);
328 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
331 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
332 SDValue Val, SDValue *Parts, unsigned NumParts,
333 MVT PartVT, const Value *V);
335 /// getCopyToParts - Create a series of nodes that contain the specified value
336 /// split into legal parts. If the parts contain more bits than Val, then, for
337 /// integers, ExtendKind can be used to specify how to generate the extra bits.
338 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
339 SDValue Val, SDValue *Parts, unsigned NumParts,
340 MVT PartVT, const Value *V,
341 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
342 EVT ValueVT = Val.getValueType();
344 // Handle the vector case separately.
345 if (ValueVT.isVector())
346 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
349 unsigned PartBits = PartVT.getSizeInBits();
350 unsigned OrigNumParts = NumParts;
351 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
356 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
357 EVT PartEVT = PartVT;
358 if (PartEVT == ValueVT) {
359 assert(NumParts == 1 && "No-op copy with multiple parts!");
364 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
365 // If the parts cover more bits than the value has, promote the value.
366 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
367 assert(NumParts == 1 && "Do not know what to promote to!");
368 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
371 ValueVT.isInteger() &&
372 "Unknown mismatch!");
373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
374 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
375 if (PartVT == MVT::x86mmx)
376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
378 } else if (PartBits == ValueVT.getSizeInBits()) {
379 // Different types of the same size.
380 assert(NumParts == 1 && PartEVT != ValueVT);
381 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
382 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
383 // If the parts cover less bits than value has, truncate the value.
384 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
385 ValueVT.isInteger() &&
386 "Unknown mismatch!");
387 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
388 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
389 if (PartVT == MVT::x86mmx)
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 // The value may have changed - recompute ValueVT.
394 ValueVT = Val.getValueType();
395 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
396 "Failed to tile the value with PartVT!");
399 if (PartEVT != ValueVT) {
400 LLVMContext &Ctx = *DAG.getContext();
401 Twine ErrMsg("scalar-to-vector conversion failed");
402 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
403 if (const CallInst *CI = dyn_cast<CallInst>(I))
404 if (isa<InlineAsm>(CI->getCalledValue()))
405 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
406 Ctx.emitError(I, ErrMsg);
408 Ctx.emitError(ErrMsg);
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getIntPtrConstant(i)));
495 for (unsigned i = ValueVT.getVectorNumElements(),
496 e = PartVT.getVectorNumElements(); i != e; ++i)
497 Ops.push_back(DAG.getUNDEF(ElementVT));
499 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
501 // FIXME: Use CONCAT for 2x -> 4x.
503 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
504 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
505 } else if (PartVT.isVector() &&
506 PartEVT.getVectorElementType().bitsGE(
507 ValueVT.getVectorElementType()) &&
508 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
510 // Promoted vector extract
511 bool Smaller = PartEVT.bitsLE(ValueVT);
512 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
515 // Vector -> scalar conversion.
516 assert(ValueVT.getVectorNumElements() == 1 &&
517 "Only trivial vector-to-scalar conversions should get here!");
518 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
519 PartVT, Val, DAG.getIntPtrConstant(0));
521 bool Smaller = ValueVT.bitsLE(PartVT);
522 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
530 // Handle a multi-element vector.
533 unsigned NumIntermediates;
534 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
536 NumIntermediates, RegisterVT);
537 unsigned NumElements = ValueVT.getVectorNumElements();
539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540 NumParts = NumRegs; // Silence a compiler warning.
541 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
543 // Split the vector into intermediate operands.
544 SmallVector<SDValue, 8> Ops(NumIntermediates);
545 for (unsigned i = 0; i != NumIntermediates; ++i) {
546 if (IntermediateVT.isVector())
547 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
549 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
551 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
552 IntermediateVT, Val, DAG.getIntPtrConstant(i));
555 // Split the intermediate operands into legal parts.
556 if (NumParts == NumIntermediates) {
557 // If the register was not expanded, promote or copy the value,
559 for (unsigned i = 0; i != NumParts; ++i)
560 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
561 } else if (NumParts > 0) {
562 // If the intermediate type was expanded, split each the value into
564 assert(NumParts % NumIntermediates == 0 &&
565 "Must expand into a divisible number of parts!");
566 unsigned Factor = NumParts / NumIntermediates;
567 for (unsigned i = 0; i != NumIntermediates; ++i)
568 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
573 /// RegsForValue - This struct represents the registers (physical or virtual)
574 /// that a particular set of values is assigned, and the type information
575 /// about the value. The most common situation is to represent one value at a
576 /// time, but struct or array values are handled element-wise as multiple
577 /// values. The splitting of aggregates is performed recursively, so that we
578 /// never have aggregate-typed registers. The values at this point do not
579 /// necessarily have legal types, so each value may require one or more
580 /// registers of some legal type.
582 struct RegsForValue {
583 /// ValueVTs - The value types of the values, which may not be legal, and
584 /// may need be promoted or synthesized from one or more registers.
586 SmallVector<EVT, 4> ValueVTs;
588 /// RegVTs - The value types of the registers. This is the same size as
589 /// ValueVTs and it records, for each value, what the type of the assigned
590 /// register or registers are. (Individual values are never synthesized
591 /// from more than one type of register.)
593 /// With virtual registers, the contents of RegVTs is redundant with TLI's
594 /// getRegisterType member function, however when with physical registers
595 /// it is necessary to have a separate record of the types.
597 SmallVector<MVT, 4> RegVTs;
599 /// Regs - This list holds the registers assigned to the values.
600 /// Each legal or promoted value requires one register, and each
601 /// expanded value requires multiple registers.
603 SmallVector<unsigned, 4> Regs;
607 RegsForValue(const SmallVector<unsigned, 4> ®s,
608 MVT regvt, EVT valuevt)
609 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
611 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
612 unsigned Reg, Type *Ty) {
613 ComputeValueVTs(tli, Ty, ValueVTs);
615 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
616 EVT ValueVT = ValueVTs[Value];
617 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
618 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
619 for (unsigned i = 0; i != NumRegs; ++i)
620 Regs.push_back(Reg + i);
621 RegVTs.push_back(RegisterVT);
626 /// areValueTypesLegal - Return true if types of all the values are legal.
627 bool areValueTypesLegal(const TargetLowering &TLI) {
628 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
629 MVT RegisterVT = RegVTs[Value];
630 if (!TLI.isTypeLegal(RegisterVT))
636 /// append - Add the specified values to this one.
637 void append(const RegsForValue &RHS) {
638 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
639 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
640 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
644 /// this value and returns the result as a ValueVTs value. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
649 SDValue &Chain, SDValue *Flag,
650 const Value *V = 0) const;
652 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
653 /// specified value into the registers specified by this object. This uses
654 /// Chain/Flag as the input and updates them for the output Chain/Flag.
655 /// If the Flag pointer is NULL, no flag is used.
656 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
657 SDValue &Chain, SDValue *Flag, const Value *V) const;
659 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
660 /// operand list. This adds the code marker, matching input operand index
661 /// (if applicable), and includes the number of values added into it.
662 void AddInlineAsmOperands(unsigned Kind,
663 bool HasMatching, unsigned MatchingIdx,
665 std::vector<SDValue> &Ops) const;
669 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
670 /// this value and returns the result as a ValueVT value. This uses
671 /// Chain/Flag as the input and updates them for the output Chain/Flag.
672 /// If the Flag pointer is NULL, no flag is used.
673 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
674 FunctionLoweringInfo &FuncInfo,
676 SDValue &Chain, SDValue *Flag,
677 const Value *V) const {
678 // A Value with type {} or [0 x %t] needs no registers.
679 if (ValueVTs.empty())
682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
684 // Assemble the legal parts into the final values.
685 SmallVector<SDValue, 4> Values(ValueVTs.size());
686 SmallVector<SDValue, 8> Parts;
687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
688 // Copy the legal parts from the registers.
689 EVT ValueVT = ValueVTs[Value];
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
691 MVT RegisterVT = RegVTs[Value];
693 Parts.resize(NumRegs);
694 for (unsigned i = 0; i != NumRegs; ++i) {
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
700 *Flag = P.getValue(2);
703 Chain = P.getValue(1);
706 // If the source register was virtual and if we know something about it,
707 // add an assert node.
708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
709 !RegisterVT.isInteger() || RegisterVT.isVector())
712 const FunctionLoweringInfo::LiveOutInfo *LOI =
713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
717 unsigned RegSize = RegisterVT.getSizeInBits();
718 unsigned NumSignBits = LOI->NumSignBits;
719 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
721 if (NumZeroBits == RegSize) {
722 // The current value is a zero.
723 // Explicitly express that as it would be easier for
724 // optimizations to kick in.
725 Parts[i] = DAG.getConstant(0, RegisterVT);
729 // FIXME: We capture more information than the dag can represent. For
730 // now, just use the tightest assertzext/assertsext possible.
732 EVT FromVT(MVT::Other);
733 if (NumSignBits == RegSize)
734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
735 else if (NumZeroBits >= RegSize-1)
736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
737 else if (NumSignBits > RegSize-8)
738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
739 else if (NumZeroBits >= RegSize-8)
740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
741 else if (NumSignBits > RegSize-16)
742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
743 else if (NumZeroBits >= RegSize-16)
744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
745 else if (NumSignBits > RegSize-32)
746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
747 else if (NumZeroBits >= RegSize-32)
748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
752 // Add an assertion node.
753 assert(FromVT != MVT::Other);
754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
755 RegisterVT, P, DAG.getValueType(FromVT));
758 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
759 NumRegs, RegisterVT, ValueVT, V);
764 return DAG.getNode(ISD::MERGE_VALUES, dl,
765 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
766 &Values[0], ValueVTs.size());
769 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
770 /// specified value into the registers specified by this object. This uses
771 /// Chain/Flag as the input and updates them for the output Chain/Flag.
772 /// If the Flag pointer is NULL, no flag is used.
773 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
774 SDValue &Chain, SDValue *Flag,
775 const Value *V) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 // Get the list of the values's legal parts.
779 unsigned NumRegs = Regs.size();
780 SmallVector<SDValue, 8> Parts(NumRegs);
781 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
782 EVT ValueVT = ValueVTs[Value];
783 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
784 MVT RegisterVT = RegVTs[Value];
785 ISD::NodeType ExtendKind =
786 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
789 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
793 // Copy the parts into the registers.
794 SmallVector<SDValue, 8> Chains(NumRegs);
795 for (unsigned i = 0; i != NumRegs; ++i) {
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
800 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
801 *Flag = Part.getValue(1);
804 Chains[i] = Part.getValue(0);
807 if (NumRegs == 1 || Flag)
808 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
809 // flagged to it. That is the CopyToReg nodes and the user are considered
810 // a single scheduling unit. If we create a TokenFactor and return it as
811 // chain, then the TokenFactor is both a predecessor (operand) of the
812 // user as well as a successor (the TF operands are flagged to the user).
813 // c1, f1 = CopyToReg
814 // c2, f2 = CopyToReg
815 // c3 = TokenFactor c1, c2
818 Chain = Chains[NumRegs-1];
820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
823 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
824 /// operand list. This adds the code marker and includes the number of
825 /// values added into it.
826 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
827 unsigned MatchingIdx,
829 std::vector<SDValue> &Ops) const {
830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
832 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
834 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
835 else if (!Regs.empty() &&
836 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
837 // Put the register class of the virtual registers in the flag word. That
838 // way, later passes can recompute register class constraints for inline
839 // assembly as well as normal instructions.
840 // Don't do this for tied operands that can use the regclass information
842 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
843 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
844 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
847 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
860 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
861 const TargetLibraryInfo *li) {
865 TD = DAG.getTarget().getDataLayout();
866 Context = DAG.getContext();
867 LPadToCallSiteMap.clear();
870 /// clear - Clear out the current SelectionDAG and the associated
871 /// state and prepare this SelectionDAGBuilder object to be used
872 /// for a new block. This doesn't clear out information about
873 /// additional blocks that are needed to complete switch lowering
874 /// or PHI node updating; that information is cleared out as it is
876 void SelectionDAGBuilder::clear() {
878 UnusedArgNodeMap.clear();
879 PendingLoads.clear();
880 PendingExports.clear();
885 /// clearDanglingDebugInfo - Clear the dangling debug information
886 /// map. This function is separated from the clear so that debug
887 /// information that is dangling in a basic block can be properly
888 /// resolved in a different basic block. This allows the
889 /// SelectionDAG to resolve dangling debug information attached
891 void SelectionDAGBuilder::clearDanglingDebugInfo() {
892 DanglingDebugInfoMap.clear();
895 /// getRoot - Return the current virtual root of the Selection DAG,
896 /// flushing any PendingLoad items. This must be done before emitting
897 /// a store or any other node that may need to be ordered after any
898 /// prior load instructions.
900 SDValue SelectionDAGBuilder::getRoot() {
901 if (PendingLoads.empty())
902 return DAG.getRoot();
904 if (PendingLoads.size() == 1) {
905 SDValue Root = PendingLoads[0];
907 PendingLoads.clear();
911 // Otherwise, we have to make a token factor node.
912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
913 &PendingLoads[0], PendingLoads.size());
914 PendingLoads.clear();
919 /// getControlRoot - Similar to getRoot, but instead of flushing all the
920 /// PendingLoad items, flush all the PendingExports items. It is necessary
921 /// to do this before emitting a terminator instruction.
923 SDValue SelectionDAGBuilder::getControlRoot() {
924 SDValue Root = DAG.getRoot();
926 if (PendingExports.empty())
929 // Turn all of the CopyToReg chains into one factored node.
930 if (Root.getOpcode() != ISD::EntryToken) {
931 unsigned i = 0, e = PendingExports.size();
932 for (; i != e; ++i) {
933 assert(PendingExports[i].getNode()->getNumOperands() > 1);
934 if (PendingExports[i].getNode()->getOperand(0) == Root)
935 break; // Don't add the root if we already indirectly depend on it.
939 PendingExports.push_back(Root);
942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 PendingExports.size());
945 PendingExports.clear();
950 void SelectionDAGBuilder::visit(const Instruction &I) {
951 // Set up outgoing PHI node register values before emitting the terminator.
952 if (isa<TerminatorInst>(&I))
953 HandlePHINodesInSuccessorBlocks(I.getParent());
959 visit(I.getOpcode(), I);
961 if (!isa<TerminatorInst>(&I) && !HasTailCall)
962 CopyToExportRegsIfNeeded(&I);
967 void SelectionDAGBuilder::visitPHI(const PHINode &) {
968 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
971 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
972 // Note: this doesn't use InstVisitor, because it has to work with
973 // ConstantExpr's in addition to instructions.
975 default: llvm_unreachable("Unknown instruction type encountered!");
976 // Build the switch statement using the Instruction.def file.
977 #define HANDLE_INST(NUM, OPCODE, CLASS) \
978 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
979 #include "llvm/IR/Instruction.def"
983 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
984 // generate the debug data structures now that we've seen its definition.
985 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
987 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
989 const DbgValueInst *DI = DDI.getDI();
990 DebugLoc dl = DDI.getdl();
991 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
992 MDNode *Variable = DI->getVariable();
993 uint64_t Offset = DI->getOffset();
996 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
997 SDV = DAG.getDbgValue(Variable, Val.getNode(),
998 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
999 DAG.AddDbgValue(SDV, Val.getNode(), false);
1002 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1003 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1007 /// getValue - Return an SDValue for the given Value.
1008 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1009 // If we already have an SDValue for this value, use it. It's important
1010 // to do this first, so that we don't create a CopyFromReg if we already
1011 // have a regular SDValue.
1012 SDValue &N = NodeMap[V];
1013 if (N.getNode()) return N;
1015 // If there's a virtual register allocated and initialized for this
1017 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1018 if (It != FuncInfo.ValueMap.end()) {
1019 unsigned InReg = It->second;
1020 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1021 InReg, V->getType());
1022 SDValue Chain = DAG.getEntryNode();
1023 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1024 resolveDanglingDebugInfo(V, N);
1028 // Otherwise create a new SDValue and remember it.
1029 SDValue Val = getValueImpl(V);
1031 resolveDanglingDebugInfo(V, Val);
1035 /// getNonRegisterValue - Return an SDValue for the given Value, but
1036 /// don't look in FuncInfo.ValueMap for a virtual register.
1037 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1038 // If we already have an SDValue for this value, use it.
1039 SDValue &N = NodeMap[V];
1040 if (N.getNode()) return N;
1042 // Otherwise create a new SDValue and remember it.
1043 SDValue Val = getValueImpl(V);
1045 resolveDanglingDebugInfo(V, Val);
1049 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1050 /// Create an SDValue for the given value.
1051 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1052 const TargetLowering *TLI = TM.getTargetLowering();
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI->getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1063 if (isa<ConstantPointerNull>(C))
1064 return DAG.getConstant(0, TLI->getPointerTy());
1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1067 return DAG.getConstantFP(*CFP, VT);
1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1070 return DAG.getUNDEF(VT);
1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1073 visit(CE->getOpcode(), *CE);
1074 SDValue N1 = NodeMap[V];
1075 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1080 SmallVector<SDValue, 4> Constants;
1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1083 SDNode *Val = getValue(*OI).getNode();
1084 // If the operand is an empty aggregate, there are no values.
1086 // Add each leaf value from the operand to the Constants list
1087 // to form a flattened list of all the values.
1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1089 Constants.push_back(SDValue(Val, i));
1092 return DAG.getMergeValues(&Constants[0], Constants.size(),
1096 if (const ConstantDataSequential *CDS =
1097 dyn_cast<ConstantDataSequential>(C)) {
1098 SmallVector<SDValue, 4> Ops;
1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Ops.push_back(SDValue(Val, i));
1107 if (isa<ArrayType>(CDS->getType()))
1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1110 VT, &Ops[0], Ops.size());
1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1115 "Unknown struct or array constant!");
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1119 unsigned NumElts = ValueVTs.size();
1121 return SDValue(); // empty struct
1122 SmallVector<SDValue, 4> Constants(NumElts);
1123 for (unsigned i = 0; i != NumElts; ++i) {
1124 EVT EltVT = ValueVTs[i];
1125 if (isa<UndefValue>(C))
1126 Constants[i] = DAG.getUNDEF(EltVT);
1127 else if (EltVT.isFloatingPoint())
1128 Constants[i] = DAG.getConstantFP(0, EltVT);
1130 Constants[i] = DAG.getConstant(0, EltVT);
1133 return DAG.getMergeValues(&Constants[0], NumElts,
1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1138 return DAG.getBlockAddress(BA, VT);
1140 VectorType *VecTy = cast<VectorType>(V->getType());
1141 unsigned NumElements = VecTy->getNumElements();
1143 // Now that we know the number and type of the elements, get that number of
1144 // elements into the Ops array based on what kind of constant it is.
1145 SmallVector<SDValue, 16> Ops;
1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1147 for (unsigned i = 0; i != NumElements; ++i)
1148 Ops.push_back(getValue(CV->getOperand(i)));
1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1151 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1154 if (EltVT.isFloatingPoint())
1155 Op = DAG.getConstantFP(0, EltVT);
1157 Op = DAG.getConstant(0, EltVT);
1158 Ops.assign(NumElements, Op);
1161 // Create a BUILD_VECTOR node.
1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1163 VT, &Ops[0], Ops.size());
1166 // If this is a static alloca, generate it as the frameindex instead of
1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1169 DenseMap<const AllocaInst*, int>::iterator SI =
1170 FuncInfo.StaticAllocaMap.find(AI);
1171 if (SI != FuncInfo.StaticAllocaMap.end())
1172 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1175 // If this is an instruction which fast-isel has deferred, select it now.
1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1178 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1179 SDValue Chain = DAG.getEntryNode();
1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1183 llvm_unreachable("Can't get register for value!");
1186 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1187 const TargetLowering *TLI = TM.getTargetLowering();
1188 SDValue Chain = getControlRoot();
1189 SmallVector<ISD::OutputArg, 8> Outs;
1190 SmallVector<SDValue, 8> OutVals;
1192 if (!FuncInfo.CanLowerReturn) {
1193 unsigned DemoteReg = FuncInfo.DemoteRegister;
1194 const Function *F = I.getParent()->getParent();
1196 // Emit a store of the return value through the virtual register.
1197 // Leave Outs empty so that LowerReturn won't try to load return
1198 // registers the usual way.
1199 SmallVector<EVT, 1> PtrValueVTs;
1200 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1203 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1204 SDValue RetOp = getValue(I.getOperand(0));
1206 SmallVector<EVT, 4> ValueVTs;
1207 SmallVector<uint64_t, 4> Offsets;
1208 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1209 unsigned NumValues = ValueVTs.size();
1211 SmallVector<SDValue, 4> Chains(NumValues);
1212 for (unsigned i = 0; i != NumValues; ++i) {
1213 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1214 RetPtr.getValueType(), RetPtr,
1215 DAG.getIntPtrConstant(Offsets[i]));
1217 DAG.getStore(Chain, getCurSDLoc(),
1218 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1219 // FIXME: better loc info would be nice.
1220 Add, MachinePointerInfo(), false, false, 0);
1223 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1224 MVT::Other, &Chains[0], NumValues);
1225 } else if (I.getNumOperands() != 0) {
1226 SmallVector<EVT, 4> ValueVTs;
1227 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1228 unsigned NumValues = ValueVTs.size();
1230 SDValue RetOp = getValue(I.getOperand(0));
1231 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1232 EVT VT = ValueVTs[j];
1234 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1236 const Function *F = I.getParent()->getParent();
1237 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1239 ExtendKind = ISD::SIGN_EXTEND;
1240 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1242 ExtendKind = ISD::ZERO_EXTEND;
1244 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1245 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1247 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1248 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1249 SmallVector<SDValue, 4> Parts(NumParts);
1250 getCopyToParts(DAG, getCurSDLoc(),
1251 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1252 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1254 // 'inreg' on function refers to return value
1255 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1256 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 // Propagate extension type if any
1261 if (ExtendKind == ISD::SIGN_EXTEND)
1263 else if (ExtendKind == ISD::ZERO_EXTEND)
1266 for (unsigned i = 0; i < NumParts; ++i) {
1267 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1268 /*isfixed=*/true, 0, 0));
1269 OutVals.push_back(Parts[i]);
1275 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1276 CallingConv::ID CallConv =
1277 DAG.getMachineFunction().getFunction()->getCallingConv();
1278 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1279 Outs, OutVals, getCurSDLoc(),
1282 // Verify that the target's LowerReturn behaved as expected.
1283 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1284 "LowerReturn didn't return a valid chain!");
1286 // Update the DAG with the new chain value resulting from return lowering.
1290 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1291 /// created for it, emit nodes to copy the value into the virtual
1293 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1295 if (V->getType()->isEmptyTy())
1298 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1299 if (VMI != FuncInfo.ValueMap.end()) {
1300 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1301 CopyValueToVirtualRegister(V, VMI->second);
1305 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1306 /// the current basic block, add it to ValueMap now so that we'll get a
1308 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1309 // No need to export constants.
1310 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1312 // Already exported?
1313 if (FuncInfo.isExportedInst(V)) return;
1315 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1316 CopyValueToVirtualRegister(V, Reg);
1319 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1320 const BasicBlock *FromBB) {
1321 // The operands of the setcc have to be in this block. We don't know
1322 // how to export them from some other block.
1323 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1324 // Can export from current BB.
1325 if (VI->getParent() == FromBB)
1328 // Is already exported, noop.
1329 return FuncInfo.isExportedInst(V);
1332 // If this is an argument, we can export it if the BB is the entry block or
1333 // if it is already exported.
1334 if (isa<Argument>(V)) {
1335 if (FromBB == &FromBB->getParent()->getEntryBlock())
1338 // Otherwise, can only export this if it is already exported.
1339 return FuncInfo.isExportedInst(V);
1342 // Otherwise, constants can always be exported.
1346 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1347 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1348 const MachineBasicBlock *Dst) const {
1349 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1352 const BasicBlock *SrcBB = Src->getBasicBlock();
1353 const BasicBlock *DstBB = Dst->getBasicBlock();
1354 return BPI->getEdgeWeight(SrcBB, DstBB);
1357 void SelectionDAGBuilder::
1358 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1359 uint32_t Weight /* = 0 */) {
1361 Weight = getEdgeWeight(Src, Dst);
1362 Src->addSuccessor(Dst, Weight);
1366 static bool InBlock(const Value *V, const BasicBlock *BB) {
1367 if (const Instruction *I = dyn_cast<Instruction>(V))
1368 return I->getParent() == BB;
1372 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1373 /// This function emits a branch and is used at the leaves of an OR or an
1374 /// AND operator tree.
1377 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1378 MachineBasicBlock *TBB,
1379 MachineBasicBlock *FBB,
1380 MachineBasicBlock *CurBB,
1381 MachineBasicBlock *SwitchBB) {
1382 const BasicBlock *BB = CurBB->getBasicBlock();
1384 // If the leaf of the tree is a comparison, merge the condition into
1386 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1387 // The operands of the cmp have to be in this block. We don't know
1388 // how to export them from some other block. If this is the first block
1389 // of the sequence, no exporting is needed.
1390 if (CurBB == SwitchBB ||
1391 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1392 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1393 ISD::CondCode Condition;
1394 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1395 Condition = getICmpCondCode(IC->getPredicate());
1396 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1397 Condition = getFCmpCondCode(FC->getPredicate());
1398 if (TM.Options.NoNaNsFPMath)
1399 Condition = getFCmpCodeWithoutNaN(Condition);
1401 Condition = ISD::SETEQ; // silence warning.
1402 llvm_unreachable("Unknown compare instruction");
1405 CaseBlock CB(Condition, BOp->getOperand(0),
1406 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1407 SwitchCases.push_back(CB);
1412 // Create a CaseBlock record representing this branch.
1413 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1414 NULL, TBB, FBB, CurBB);
1415 SwitchCases.push_back(CB);
1418 /// FindMergedConditions - If Cond is an expression like
1419 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1420 MachineBasicBlock *TBB,
1421 MachineBasicBlock *FBB,
1422 MachineBasicBlock *CurBB,
1423 MachineBasicBlock *SwitchBB,
1425 // If this node is not part of the or/and tree, emit it as a branch.
1426 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1427 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1428 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1429 BOp->getParent() != CurBB->getBasicBlock() ||
1430 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1431 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1432 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1436 // Create TmpBB after CurBB.
1437 MachineFunction::iterator BBI = CurBB;
1438 MachineFunction &MF = DAG.getMachineFunction();
1439 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1440 CurBB->getParent()->insert(++BBI, TmpBB);
1442 if (Opc == Instruction::Or) {
1443 // Codegen X | Y as:
1451 // Emit the LHS condition.
1452 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1454 // Emit the RHS condition into TmpBB.
1455 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1457 assert(Opc == Instruction::And && "Unknown merge op!");
1458 // Codegen X & Y as:
1465 // This requires creation of TmpBB after CurBB.
1467 // Emit the LHS condition.
1468 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1470 // Emit the RHS condition into TmpBB.
1471 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1475 /// If the set of cases should be emitted as a series of branches, return true.
1476 /// If we should emit this as a bunch of and/or'd together conditions, return
1479 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1480 if (Cases.size() != 2) return true;
1482 // If this is two comparisons of the same values or'd or and'd together, they
1483 // will get folded into a single comparison, so don't emit two blocks.
1484 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1485 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1486 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1487 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1491 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1492 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1493 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1494 Cases[0].CC == Cases[1].CC &&
1495 isa<Constant>(Cases[0].CmpRHS) &&
1496 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1497 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1499 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1506 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1507 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1509 // Update machine-CFG edges.
1510 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1512 // Figure out which block is immediately after the current one.
1513 MachineBasicBlock *NextBlock = 0;
1514 MachineFunction::iterator BBI = BrMBB;
1515 if (++BBI != FuncInfo.MF->end())
1518 if (I.isUnconditional()) {
1519 // Update machine-CFG edges.
1520 BrMBB->addSuccessor(Succ0MBB);
1522 // If this is not a fall-through branch, emit the branch.
1523 if (Succ0MBB != NextBlock)
1524 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1525 MVT::Other, getControlRoot(),
1526 DAG.getBasicBlock(Succ0MBB)));
1531 // If this condition is one of the special cases we handle, do special stuff
1533 const Value *CondVal = I.getCondition();
1534 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1536 // If this is a series of conditions that are or'd or and'd together, emit
1537 // this as a sequence of branches instead of setcc's with and/or operations.
1538 // As long as jumps are not expensive, this should improve performance.
1539 // For example, instead of something like:
1552 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1553 if (!TM.getTargetLowering()->isJumpExpensive() &&
1555 (BOp->getOpcode() == Instruction::And ||
1556 BOp->getOpcode() == Instruction::Or)) {
1557 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1559 // If the compares in later blocks need to use values not currently
1560 // exported from this block, export them now. This block should always
1561 // be the first entry.
1562 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1564 // Allow some cases to be rejected.
1565 if (ShouldEmitAsBranches(SwitchCases)) {
1566 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1567 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1568 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1571 // Emit the branch for this block.
1572 visitSwitchCase(SwitchCases[0], BrMBB);
1573 SwitchCases.erase(SwitchCases.begin());
1577 // Okay, we decided not to do this, remove any inserted MBB's and clear
1579 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1580 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1582 SwitchCases.clear();
1586 // Create a CaseBlock record representing this branch.
1587 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1588 NULL, Succ0MBB, Succ1MBB, BrMBB);
1590 // Use visitSwitchCase to actually insert the fast branch sequence for this
1592 visitSwitchCase(CB, BrMBB);
1595 /// visitSwitchCase - Emits the necessary code to represent a single node in
1596 /// the binary search tree resulting from lowering a switch instruction.
1597 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1598 MachineBasicBlock *SwitchBB) {
1600 SDValue CondLHS = getValue(CB.CmpLHS);
1601 SDLoc dl = getCurSDLoc();
1603 // Build the setcc now.
1604 if (CB.CmpMHS == NULL) {
1605 // Fold "(X == true)" to X and "(X == false)" to !X to
1606 // handle common cases produced by branch lowering.
1607 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1608 CB.CC == ISD::SETEQ)
1610 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1611 CB.CC == ISD::SETEQ) {
1612 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1613 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1615 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1617 assert(CB.CC == ISD::SETCC_INVALID &&
1618 "Condition is undefined for to-the-range belonging check.");
1620 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1621 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1623 SDValue CmpOp = getValue(CB.CmpMHS);
1624 EVT VT = CmpOp.getValueType();
1626 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1627 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1630 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1631 VT, CmpOp, DAG.getConstant(Low, VT));
1632 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1633 DAG.getConstant(High-Low, VT), ISD::SETULE);
1637 // Update successor info
1638 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1639 // TrueBB and FalseBB are always different unless the incoming IR is
1640 // degenerate. This only happens when running llc on weird IR.
1641 if (CB.TrueBB != CB.FalseBB)
1642 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1644 // Set NextBlock to be the MBB immediately after the current one, if any.
1645 // This is used to avoid emitting unnecessary branches to the next block.
1646 MachineBasicBlock *NextBlock = 0;
1647 MachineFunction::iterator BBI = SwitchBB;
1648 if (++BBI != FuncInfo.MF->end())
1651 // If the lhs block is the next block, invert the condition so that we can
1652 // fall through to the lhs instead of the rhs block.
1653 if (CB.TrueBB == NextBlock) {
1654 std::swap(CB.TrueBB, CB.FalseBB);
1655 SDValue True = DAG.getConstant(1, Cond.getValueType());
1656 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1659 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1660 MVT::Other, getControlRoot(), Cond,
1661 DAG.getBasicBlock(CB.TrueBB));
1663 // Insert the false branch. Do this even if it's a fall through branch,
1664 // this makes it easier to do DAG optimizations which require inverting
1665 // the branch condition.
1666 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1667 DAG.getBasicBlock(CB.FalseBB));
1669 DAG.setRoot(BrCond);
1672 /// visitJumpTable - Emit JumpTable node in the current MBB
1673 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1674 // Emit the code for the jump table
1675 assert(JT.Reg != -1U && "Should lower JT Header first!");
1676 EVT PTy = TM.getTargetLowering()->getPointerTy();
1677 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1679 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1680 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1681 MVT::Other, Index.getValue(1),
1683 DAG.setRoot(BrJumpTable);
1686 /// visitJumpTableHeader - This function emits necessary code to produce index
1687 /// in the JumpTable from switch case.
1688 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1689 JumpTableHeader &JTH,
1690 MachineBasicBlock *SwitchBB) {
1691 // Subtract the lowest switch case value from the value being switched on and
1692 // conditional branch to default mbb if the result is greater than the
1693 // difference between smallest and largest cases.
1694 SDValue SwitchOp = getValue(JTH.SValue);
1695 EVT VT = SwitchOp.getValueType();
1696 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1697 DAG.getConstant(JTH.First, VT));
1699 // The SDNode we just created, which holds the value being switched on minus
1700 // the smallest case value, needs to be copied to a virtual register so it
1701 // can be used as an index into the jump table in a subsequent basic block.
1702 // This value may be smaller or larger than the target's pointer type, and
1703 // therefore require extension or truncating.
1704 const TargetLowering *TLI = TM.getTargetLowering();
1705 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1707 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1708 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1709 JumpTableReg, SwitchOp);
1710 JT.Reg = JumpTableReg;
1712 // Emit the range check for the jump table, and branch to the default block
1713 // for the switch statement if the value being switched on exceeds the largest
1714 // case in the switch.
1715 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1716 TLI->getSetCCResultType(*DAG.getContext(),
1717 Sub.getValueType()),
1719 DAG.getConstant(JTH.Last - JTH.First,VT),
1722 // Set NextBlock to be the MBB immediately after the current one, if any.
1723 // This is used to avoid emitting unnecessary branches to the next block.
1724 MachineBasicBlock *NextBlock = 0;
1725 MachineFunction::iterator BBI = SwitchBB;
1727 if (++BBI != FuncInfo.MF->end())
1730 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1731 MVT::Other, CopyTo, CMP,
1732 DAG.getBasicBlock(JT.Default));
1734 if (JT.MBB != NextBlock)
1735 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1736 DAG.getBasicBlock(JT.MBB));
1738 DAG.setRoot(BrCond);
1741 /// visitBitTestHeader - This function emits necessary code to produce value
1742 /// suitable for "bit tests"
1743 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1744 MachineBasicBlock *SwitchBB) {
1745 // Subtract the minimum value
1746 SDValue SwitchOp = getValue(B.SValue);
1747 EVT VT = SwitchOp.getValueType();
1748 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1749 DAG.getConstant(B.First, VT));
1752 const TargetLowering *TLI = TM.getTargetLowering();
1753 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1754 TLI->getSetCCResultType(*DAG.getContext(),
1755 Sub.getValueType()),
1756 Sub, DAG.getConstant(B.Range, VT),
1759 // Determine the type of the test operands.
1760 bool UsePtrType = false;
1761 if (!TLI->isTypeLegal(VT))
1764 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1765 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1766 // Switch table case range are encoded into series of masks.
1767 // Just use pointer type, it's guaranteed to fit.
1773 VT = TLI->getPointerTy();
1774 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1777 B.RegVT = VT.getSimpleVT();
1778 B.Reg = FuncInfo.CreateReg(B.RegVT);
1779 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1782 // Set NextBlock to be the MBB immediately after the current one, if any.
1783 // This is used to avoid emitting unnecessary branches to the next block.
1784 MachineBasicBlock *NextBlock = 0;
1785 MachineFunction::iterator BBI = SwitchBB;
1786 if (++BBI != FuncInfo.MF->end())
1789 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1791 addSuccessorWithWeight(SwitchBB, B.Default);
1792 addSuccessorWithWeight(SwitchBB, MBB);
1794 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1795 MVT::Other, CopyTo, RangeCmp,
1796 DAG.getBasicBlock(B.Default));
1798 if (MBB != NextBlock)
1799 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1800 DAG.getBasicBlock(MBB));
1802 DAG.setRoot(BrRange);
1805 /// visitBitTestCase - this function produces one "bit test"
1806 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1807 MachineBasicBlock* NextMBB,
1808 uint32_t BranchWeightToNext,
1811 MachineBasicBlock *SwitchBB) {
1813 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1816 unsigned PopCount = CountPopulation_64(B.Mask);
1817 const TargetLowering *TLI = TM.getTargetLowering();
1818 if (PopCount == 1) {
1819 // Testing for a single bit; just compare the shift count with what it
1820 // would need to be to shift a 1 bit in that position.
1821 Cmp = DAG.getSetCC(getCurSDLoc(),
1822 TLI->getSetCCResultType(*DAG.getContext(), VT),
1824 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1826 } else if (PopCount == BB.Range) {
1827 // There is only one zero bit in the range, test for it directly.
1828 Cmp = DAG.getSetCC(getCurSDLoc(),
1829 TLI->getSetCCResultType(*DAG.getContext(), VT),
1831 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1834 // Make desired shift
1835 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1836 DAG.getConstant(1, VT), ShiftOp);
1838 // Emit bit tests and jumps
1839 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1840 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1841 Cmp = DAG.getSetCC(getCurSDLoc(),
1842 TLI->getSetCCResultType(*DAG.getContext(), VT),
1843 AndOp, DAG.getConstant(0, VT),
1847 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1848 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1849 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1850 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1852 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1853 MVT::Other, getControlRoot(),
1854 Cmp, DAG.getBasicBlock(B.TargetBB));
1856 // Set NextBlock to be the MBB immediately after the current one, if any.
1857 // This is used to avoid emitting unnecessary branches to the next block.
1858 MachineBasicBlock *NextBlock = 0;
1859 MachineFunction::iterator BBI = SwitchBB;
1860 if (++BBI != FuncInfo.MF->end())
1863 if (NextMBB != NextBlock)
1864 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1865 DAG.getBasicBlock(NextMBB));
1870 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1871 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1873 // Retrieve successors.
1874 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1875 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1877 const Value *Callee(I.getCalledValue());
1878 const Function *Fn = dyn_cast<Function>(Callee);
1879 if (isa<InlineAsm>(Callee))
1881 else if (Fn && Fn->isIntrinsic()) {
1882 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1883 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1885 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1887 // If the value of the invoke is used outside of its defining block, make it
1888 // available as a virtual register.
1889 CopyToExportRegsIfNeeded(&I);
1891 // Update successor info
1892 addSuccessorWithWeight(InvokeMBB, Return);
1893 addSuccessorWithWeight(InvokeMBB, LandingPad);
1895 // Drop into normal successor.
1896 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1897 MVT::Other, getControlRoot(),
1898 DAG.getBasicBlock(Return)));
1901 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1902 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1905 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1906 assert(FuncInfo.MBB->isLandingPad() &&
1907 "Call to landingpad not in landing pad!");
1909 MachineBasicBlock *MBB = FuncInfo.MBB;
1910 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1911 AddLandingPadInfo(LP, MMI, MBB);
1913 // If there aren't registers to copy the values into (e.g., during SjLj
1914 // exceptions), then don't bother to create these DAG nodes.
1915 const TargetLowering *TLI = TM.getTargetLowering();
1916 if (TLI->getExceptionPointerRegister() == 0 &&
1917 TLI->getExceptionSelectorRegister() == 0)
1920 SmallVector<EVT, 2> ValueVTs;
1921 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
1923 // Insert the EXCEPTIONADDR instruction.
1924 assert(FuncInfo.MBB->isLandingPad() &&
1925 "Call to eh.exception not in landing pad!");
1926 SDVTList VTs = DAG.getVTList(TLI->getPointerTy(), MVT::Other);
1928 Ops[0] = DAG.getRoot();
1929 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurSDLoc(), VTs, Ops, 1);
1930 SDValue Chain = Op1.getValue(1);
1932 // Insert the EHSELECTION instruction.
1933 VTs = DAG.getVTList(TLI->getPointerTy(), MVT::Other);
1936 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurSDLoc(), VTs, Ops, 2);
1937 Chain = Op2.getValue(1);
1938 Op2 = DAG.getSExtOrTrunc(Op2, getCurSDLoc(), MVT::i32);
1942 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
1943 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1946 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1947 setValue(&LP, RetPair.first);
1948 DAG.setRoot(RetPair.second);
1951 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1952 /// small case ranges).
1953 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1954 CaseRecVector& WorkList,
1956 MachineBasicBlock *Default,
1957 MachineBasicBlock *SwitchBB) {
1958 // Size is the number of Cases represented by this range.
1959 size_t Size = CR.Range.second - CR.Range.first;
1963 // Get the MachineFunction which holds the current MBB. This is used when
1964 // inserting any additional MBBs necessary to represent the switch.
1965 MachineFunction *CurMF = FuncInfo.MF;
1967 // Figure out which block is immediately after the current one.
1968 MachineBasicBlock *NextBlock = 0;
1969 MachineFunction::iterator BBI = CR.CaseBB;
1971 if (++BBI != FuncInfo.MF->end())
1974 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1975 // If any two of the cases has the same destination, and if one value
1976 // is the same as the other, but has one bit unset that the other has set,
1977 // use bit manipulation to do two compares at once. For example:
1978 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1979 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1980 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1981 if (Size == 2 && CR.CaseBB == SwitchBB) {
1982 Case &Small = *CR.Range.first;
1983 Case &Big = *(CR.Range.second-1);
1985 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1986 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1987 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1989 // Check that there is only one bit different.
1990 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1991 (SmallValue | BigValue) == BigValue) {
1992 // Isolate the common bit.
1993 APInt CommonBit = BigValue & ~SmallValue;
1994 assert((SmallValue | CommonBit) == BigValue &&
1995 CommonBit.countPopulation() == 1 && "Not a common bit?");
1997 SDValue CondLHS = getValue(SV);
1998 EVT VT = CondLHS.getValueType();
1999 SDLoc DL = getCurSDLoc();
2001 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2002 DAG.getConstant(CommonBit, VT));
2003 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2004 Or, DAG.getConstant(BigValue, VT),
2007 // Update successor info.
2008 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2009 addSuccessorWithWeight(SwitchBB, Small.BB,
2010 Small.ExtraWeight + Big.ExtraWeight);
2011 addSuccessorWithWeight(SwitchBB, Default,
2012 // The default destination is the first successor in IR.
2013 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2015 // Insert the true branch.
2016 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2017 getControlRoot(), Cond,
2018 DAG.getBasicBlock(Small.BB));
2020 // Insert the false branch.
2021 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2022 DAG.getBasicBlock(Default));
2024 DAG.setRoot(BrCond);
2030 // Order cases by weight so the most likely case will be checked first.
2031 uint32_t UnhandledWeights = 0;
2033 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2034 uint32_t IWeight = I->ExtraWeight;
2035 UnhandledWeights += IWeight;
2036 for (CaseItr J = CR.Range.first; J < I; ++J) {
2037 uint32_t JWeight = J->ExtraWeight;
2038 if (IWeight > JWeight)
2043 // Rearrange the case blocks so that the last one falls through if possible.
2044 Case &BackCase = *(CR.Range.second-1);
2046 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2047 // The last case block won't fall through into 'NextBlock' if we emit the
2048 // branches in this order. See if rearranging a case value would help.
2049 // We start at the bottom as it's the case with the least weight.
2050 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2051 if (I->BB == NextBlock) {
2052 std::swap(*I, BackCase);
2058 // Create a CaseBlock record representing a conditional branch to
2059 // the Case's target mbb if the value being switched on SV is equal
2061 MachineBasicBlock *CurBlock = CR.CaseBB;
2062 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2063 MachineBasicBlock *FallThrough;
2065 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2066 CurMF->insert(BBI, FallThrough);
2068 // Put SV in a virtual register to make it available from the new blocks.
2069 ExportFromCurrentBlock(SV);
2071 // If the last case doesn't match, go to the default block.
2072 FallThrough = Default;
2075 const Value *RHS, *LHS, *MHS;
2077 if (I->High == I->Low) {
2078 // This is just small small case range :) containing exactly 1 case
2080 LHS = SV; RHS = I->High; MHS = NULL;
2082 CC = ISD::SETCC_INVALID;
2083 LHS = I->Low; MHS = SV; RHS = I->High;
2086 // The false weight should be sum of all un-handled cases.
2087 UnhandledWeights -= I->ExtraWeight;
2088 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2090 /* trueweight */ I->ExtraWeight,
2091 /* falseweight */ UnhandledWeights);
2093 // If emitting the first comparison, just call visitSwitchCase to emit the
2094 // code into the current block. Otherwise, push the CaseBlock onto the
2095 // vector to be later processed by SDISel, and insert the node's MBB
2096 // before the next MBB.
2097 if (CurBlock == SwitchBB)
2098 visitSwitchCase(CB, SwitchBB);
2100 SwitchCases.push_back(CB);
2102 CurBlock = FallThrough;
2108 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2109 return TLI.supportJumpTables() &&
2110 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2111 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2114 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2115 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2116 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2117 return (LastExt - FirstExt + 1ULL);
2120 /// handleJTSwitchCase - Emit jumptable for current switch case range
2121 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2122 CaseRecVector &WorkList,
2124 MachineBasicBlock *Default,
2125 MachineBasicBlock *SwitchBB) {
2126 Case& FrontCase = *CR.Range.first;
2127 Case& BackCase = *(CR.Range.second-1);
2129 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2130 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2132 APInt TSize(First.getBitWidth(), 0);
2133 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2136 const TargetLowering *TLI = TM.getTargetLowering();
2137 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2140 APInt Range = ComputeRange(First, Last);
2141 // The density is TSize / Range. Require at least 40%.
2142 // It should not be possible for IntTSize to saturate for sane code, but make
2143 // sure we handle Range saturation correctly.
2144 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2145 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2146 if (IntTSize * 10 < IntRange * 4)
2149 DEBUG(dbgs() << "Lowering jump table\n"
2150 << "First entry: " << First << ". Last entry: " << Last << '\n'
2151 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2153 // Get the MachineFunction which holds the current MBB. This is used when
2154 // inserting any additional MBBs necessary to represent the switch.
2155 MachineFunction *CurMF = FuncInfo.MF;
2157 // Figure out which block is immediately after the current one.
2158 MachineFunction::iterator BBI = CR.CaseBB;
2161 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2163 // Create a new basic block to hold the code for loading the address
2164 // of the jump table, and jumping to it. Update successor information;
2165 // we will either branch to the default case for the switch, or the jump
2167 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2168 CurMF->insert(BBI, JumpTableBB);
2170 addSuccessorWithWeight(CR.CaseBB, Default);
2171 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2173 // Build a vector of destination BBs, corresponding to each target
2174 // of the jump table. If the value of the jump table slot corresponds to
2175 // a case statement, push the case's BB onto the vector, otherwise, push
2177 std::vector<MachineBasicBlock*> DestBBs;
2179 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2180 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2181 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2183 if (Low.ule(TEI) && TEI.ule(High)) {
2184 DestBBs.push_back(I->BB);
2188 DestBBs.push_back(Default);
2192 // Calculate weight for each unique destination in CR.
2193 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2195 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2196 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2197 DestWeights.find(I->BB);
2198 if (Itr != DestWeights.end())
2199 Itr->second += I->ExtraWeight;
2201 DestWeights[I->BB] = I->ExtraWeight;
2204 // Update successor info. Add one edge to each unique successor.
2205 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2206 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2207 E = DestBBs.end(); I != E; ++I) {
2208 if (!SuccsHandled[(*I)->getNumber()]) {
2209 SuccsHandled[(*I)->getNumber()] = true;
2210 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2211 DestWeights.find(*I);
2212 addSuccessorWithWeight(JumpTableBB, *I,
2213 Itr != DestWeights.end() ? Itr->second : 0);
2217 // Create a jump table index for this jump table.
2218 unsigned JTEncoding = TLI->getJumpTableEncoding();
2219 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2220 ->createJumpTableIndex(DestBBs);
2222 // Set the jump table information so that we can codegen it as a second
2223 // MachineBasicBlock
2224 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2225 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2226 if (CR.CaseBB == SwitchBB)
2227 visitJumpTableHeader(JT, JTH, SwitchBB);
2229 JTCases.push_back(JumpTableBlock(JTH, JT));
2233 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2235 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2236 CaseRecVector& WorkList,
2238 MachineBasicBlock *Default,
2239 MachineBasicBlock *SwitchBB) {
2240 // Get the MachineFunction which holds the current MBB. This is used when
2241 // inserting any additional MBBs necessary to represent the switch.
2242 MachineFunction *CurMF = FuncInfo.MF;
2244 // Figure out which block is immediately after the current one.
2245 MachineFunction::iterator BBI = CR.CaseBB;
2248 Case& FrontCase = *CR.Range.first;
2249 Case& BackCase = *(CR.Range.second-1);
2250 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2252 // Size is the number of Cases represented by this range.
2253 unsigned Size = CR.Range.second - CR.Range.first;
2255 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2256 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2258 CaseItr Pivot = CR.Range.first + Size/2;
2260 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2261 // (heuristically) allow us to emit JumpTable's later.
2262 APInt TSize(First.getBitWidth(), 0);
2263 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2267 APInt LSize = FrontCase.size();
2268 APInt RSize = TSize-LSize;
2269 DEBUG(dbgs() << "Selecting best pivot: \n"
2270 << "First: " << First << ", Last: " << Last <<'\n'
2271 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2272 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2274 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2275 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2276 APInt Range = ComputeRange(LEnd, RBegin);
2277 assert((Range - 2ULL).isNonNegative() &&
2278 "Invalid case distance");
2279 // Use volatile double here to avoid excess precision issues on some hosts,
2280 // e.g. that use 80-bit X87 registers.
2281 volatile double LDensity =
2282 (double)LSize.roundToDouble() /
2283 (LEnd - First + 1ULL).roundToDouble();
2284 volatile double RDensity =
2285 (double)RSize.roundToDouble() /
2286 (Last - RBegin + 1ULL).roundToDouble();
2287 double Metric = Range.logBase2()*(LDensity+RDensity);
2288 // Should always split in some non-trivial place
2289 DEBUG(dbgs() <<"=>Step\n"
2290 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2291 << "LDensity: " << LDensity
2292 << ", RDensity: " << RDensity << '\n'
2293 << "Metric: " << Metric << '\n');
2294 if (FMetric < Metric) {
2297 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2304 const TargetLowering *TLI = TM.getTargetLowering();
2305 if (areJTsAllowed(*TLI)) {
2306 // If our case is dense we *really* should handle it earlier!
2307 assert((FMetric > 0) && "Should handle dense range earlier!");
2309 Pivot = CR.Range.first + Size/2;
2312 CaseRange LHSR(CR.Range.first, Pivot);
2313 CaseRange RHSR(Pivot, CR.Range.second);
2314 const Constant *C = Pivot->Low;
2315 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2317 // We know that we branch to the LHS if the Value being switched on is
2318 // less than the Pivot value, C. We use this to optimize our binary
2319 // tree a bit, by recognizing that if SV is greater than or equal to the
2320 // LHS's Case Value, and that Case Value is exactly one less than the
2321 // Pivot's Value, then we can branch directly to the LHS's Target,
2322 // rather than creating a leaf node for it.
2323 if ((LHSR.second - LHSR.first) == 1 &&
2324 LHSR.first->High == CR.GE &&
2325 cast<ConstantInt>(C)->getValue() ==
2326 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2327 TrueBB = LHSR.first->BB;
2329 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2330 CurMF->insert(BBI, TrueBB);
2331 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2333 // Put SV in a virtual register to make it available from the new blocks.
2334 ExportFromCurrentBlock(SV);
2337 // Similar to the optimization above, if the Value being switched on is
2338 // known to be less than the Constant CR.LT, and the current Case Value
2339 // is CR.LT - 1, then we can branch directly to the target block for
2340 // the current Case Value, rather than emitting a RHS leaf node for it.
2341 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2342 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2343 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2344 FalseBB = RHSR.first->BB;
2346 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2347 CurMF->insert(BBI, FalseBB);
2348 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2350 // Put SV in a virtual register to make it available from the new blocks.
2351 ExportFromCurrentBlock(SV);
2354 // Create a CaseBlock record representing a conditional branch to
2355 // the LHS node if the value being switched on SV is less than C.
2356 // Otherwise, branch to LHS.
2357 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2359 if (CR.CaseBB == SwitchBB)
2360 visitSwitchCase(CB, SwitchBB);
2362 SwitchCases.push_back(CB);
2367 /// handleBitTestsSwitchCase - if current case range has few destination and
2368 /// range span less, than machine word bitwidth, encode case range into series
2369 /// of masks and emit bit tests with these masks.
2370 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2371 CaseRecVector& WorkList,
2373 MachineBasicBlock* Default,
2374 MachineBasicBlock *SwitchBB){
2375 const TargetLowering *TLI = TM.getTargetLowering();
2376 EVT PTy = TLI->getPointerTy();
2377 unsigned IntPtrBits = PTy.getSizeInBits();
2379 Case& FrontCase = *CR.Range.first;
2380 Case& BackCase = *(CR.Range.second-1);
2382 // Get the MachineFunction which holds the current MBB. This is used when
2383 // inserting any additional MBBs necessary to represent the switch.
2384 MachineFunction *CurMF = FuncInfo.MF;
2386 // If target does not have legal shift left, do not emit bit tests at all.
2387 if (!TLI->isOperationLegal(ISD::SHL, TLI->getPointerTy()))
2391 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2393 // Single case counts one, case range - two.
2394 numCmps += (I->Low == I->High ? 1 : 2);
2397 // Count unique destinations
2398 SmallSet<MachineBasicBlock*, 4> Dests;
2399 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2400 Dests.insert(I->BB);
2401 if (Dests.size() > 3)
2402 // Don't bother the code below, if there are too much unique destinations
2405 DEBUG(dbgs() << "Total number of unique destinations: "
2406 << Dests.size() << '\n'
2407 << "Total number of comparisons: " << numCmps << '\n');
2409 // Compute span of values.
2410 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2411 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2412 APInt cmpRange = maxValue - minValue;
2414 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2415 << "Low bound: " << minValue << '\n'
2416 << "High bound: " << maxValue << '\n');
2418 if (cmpRange.uge(IntPtrBits) ||
2419 (!(Dests.size() == 1 && numCmps >= 3) &&
2420 !(Dests.size() == 2 && numCmps >= 5) &&
2421 !(Dests.size() >= 3 && numCmps >= 6)))
2424 DEBUG(dbgs() << "Emitting bit tests\n");
2425 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2427 // Optimize the case where all the case values fit in a
2428 // word without having to subtract minValue. In this case,
2429 // we can optimize away the subtraction.
2430 if (maxValue.ult(IntPtrBits)) {
2431 cmpRange = maxValue;
2433 lowBound = minValue;
2436 CaseBitsVector CasesBits;
2437 unsigned i, count = 0;
2439 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2440 MachineBasicBlock* Dest = I->BB;
2441 for (i = 0; i < count; ++i)
2442 if (Dest == CasesBits[i].BB)
2446 assert((count < 3) && "Too much destinations to test!");
2447 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2451 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2452 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2454 uint64_t lo = (lowValue - lowBound).getZExtValue();
2455 uint64_t hi = (highValue - lowBound).getZExtValue();
2456 CasesBits[i].ExtraWeight += I->ExtraWeight;
2458 for (uint64_t j = lo; j <= hi; j++) {
2459 CasesBits[i].Mask |= 1ULL << j;
2460 CasesBits[i].Bits++;
2464 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2468 // Figure out which block is immediately after the current one.
2469 MachineFunction::iterator BBI = CR.CaseBB;
2472 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2474 DEBUG(dbgs() << "Cases:\n");
2475 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2476 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2477 << ", Bits: " << CasesBits[i].Bits
2478 << ", BB: " << CasesBits[i].BB << '\n');
2480 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2481 CurMF->insert(BBI, CaseBB);
2482 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2484 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2486 // Put SV in a virtual register to make it available from the new blocks.
2487 ExportFromCurrentBlock(SV);
2490 BitTestBlock BTB(lowBound, cmpRange, SV,
2491 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2492 CR.CaseBB, Default, BTC);
2494 if (CR.CaseBB == SwitchBB)
2495 visitBitTestHeader(BTB, SwitchBB);
2497 BitTestCases.push_back(BTB);
2502 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2503 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2504 const SwitchInst& SI) {
2506 /// Use a shorter form of declaration, and also
2507 /// show the we want to use CRSBuilder as Clusterifier.
2508 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2510 Clusterifier TheClusterifier;
2512 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2513 // Start with "simple" cases
2514 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2516 const BasicBlock *SuccBB = i.getCaseSuccessor();
2517 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2519 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2520 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2523 TheClusterifier.optimize();
2526 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2527 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2528 Clusterifier::Cluster &C = *i;
2529 // Update edge weight for the cluster.
2530 unsigned W = C.first.Weight;
2532 // FIXME: Currently work with ConstantInt based numbers.
2533 // Changing it to APInt based is a pretty heavy for this commit.
2534 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2535 C.first.getHigh().toConstantInt(), C.second, W));
2537 if (C.first.getLow() != C.first.getHigh())
2538 // A range counts double, since it requires two compares.
2545 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2546 MachineBasicBlock *Last) {
2548 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2549 if (JTCases[i].first.HeaderBB == First)
2550 JTCases[i].first.HeaderBB = Last;
2552 // Update BitTestCases.
2553 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2554 if (BitTestCases[i].Parent == First)
2555 BitTestCases[i].Parent = Last;
2558 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2559 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2561 // Figure out which block is immediately after the current one.
2562 MachineBasicBlock *NextBlock = 0;
2563 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2565 // If there is only the default destination, branch to it if it is not the
2566 // next basic block. Otherwise, just fall through.
2567 if (!SI.getNumCases()) {
2568 // Update machine-CFG edges.
2570 // If this is not a fall-through branch, emit the branch.
2571 SwitchMBB->addSuccessor(Default);
2572 if (Default != NextBlock)
2573 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2574 MVT::Other, getControlRoot(),
2575 DAG.getBasicBlock(Default)));
2580 // If there are any non-default case statements, create a vector of Cases
2581 // representing each one, and sort the vector so that we can efficiently
2582 // create a binary search tree from them.
2584 size_t numCmps = Clusterify(Cases, SI);
2585 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2586 << ". Total compares: " << numCmps << '\n');
2589 // Get the Value to be switched on and default basic blocks, which will be
2590 // inserted into CaseBlock records, representing basic blocks in the binary
2592 const Value *SV = SI.getCondition();
2594 // Push the initial CaseRec onto the worklist
2595 CaseRecVector WorkList;
2596 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2597 CaseRange(Cases.begin(),Cases.end())));
2599 while (!WorkList.empty()) {
2600 // Grab a record representing a case range to process off the worklist
2601 CaseRec CR = WorkList.back();
2602 WorkList.pop_back();
2604 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2607 // If the range has few cases (two or less) emit a series of specific
2609 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2612 // If the switch has more than N blocks, and is at least 40% dense, and the
2613 // target supports indirect branches, then emit a jump table rather than
2614 // lowering the switch to a binary tree of conditional branches.
2615 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2616 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2619 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2620 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2621 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2625 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2626 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2628 // Update machine-CFG edges with unique successors.
2629 SmallSet<BasicBlock*, 32> Done;
2630 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2631 BasicBlock *BB = I.getSuccessor(i);
2632 bool Inserted = Done.insert(BB);
2636 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2637 addSuccessorWithWeight(IndirectBrMBB, Succ);
2640 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2641 MVT::Other, getControlRoot(),
2642 getValue(I.getAddress())));
2645 void SelectionDAGBuilder::visitFSub(const User &I) {
2646 // -0.0 - X --> fneg
2647 Type *Ty = I.getType();
2648 if (isa<Constant>(I.getOperand(0)) &&
2649 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2650 SDValue Op2 = getValue(I.getOperand(1));
2651 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2652 Op2.getValueType(), Op2));
2656 visitBinary(I, ISD::FSUB);
2659 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2660 SDValue Op1 = getValue(I.getOperand(0));
2661 SDValue Op2 = getValue(I.getOperand(1));
2662 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2663 Op1.getValueType(), Op1, Op2));
2666 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2667 SDValue Op1 = getValue(I.getOperand(0));
2668 SDValue Op2 = getValue(I.getOperand(1));
2670 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2672 // Coerce the shift amount to the right type if we can.
2673 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2674 unsigned ShiftSize = ShiftTy.getSizeInBits();
2675 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2676 SDLoc DL = getCurSDLoc();
2678 // If the operand is smaller than the shift count type, promote it.
2679 if (ShiftSize > Op2Size)
2680 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2682 // If the operand is larger than the shift count type but the shift
2683 // count type has enough bits to represent any shift value, truncate
2684 // it now. This is a common case and it exposes the truncate to
2685 // optimization early.
2686 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2687 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2688 // Otherwise we'll need to temporarily settle for some other convenient
2689 // type. Type legalization will make adjustments once the shiftee is split.
2691 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2694 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2695 Op1.getValueType(), Op1, Op2));
2698 void SelectionDAGBuilder::visitSDiv(const User &I) {
2699 SDValue Op1 = getValue(I.getOperand(0));
2700 SDValue Op2 = getValue(I.getOperand(1));
2702 // Turn exact SDivs into multiplications.
2703 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2705 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2706 !isa<ConstantSDNode>(Op1) &&
2707 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2708 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2709 getCurSDLoc(), DAG));
2711 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2715 void SelectionDAGBuilder::visitICmp(const User &I) {
2716 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2717 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2718 predicate = IC->getPredicate();
2719 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2720 predicate = ICmpInst::Predicate(IC->getPredicate());
2721 SDValue Op1 = getValue(I.getOperand(0));
2722 SDValue Op2 = getValue(I.getOperand(1));
2723 ISD::CondCode Opcode = getICmpCondCode(predicate);
2725 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2726 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2729 void SelectionDAGBuilder::visitFCmp(const User &I) {
2730 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2731 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2732 predicate = FC->getPredicate();
2733 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2734 predicate = FCmpInst::Predicate(FC->getPredicate());
2735 SDValue Op1 = getValue(I.getOperand(0));
2736 SDValue Op2 = getValue(I.getOperand(1));
2737 ISD::CondCode Condition = getFCmpCondCode(predicate);
2738 if (TM.Options.NoNaNsFPMath)
2739 Condition = getFCmpCodeWithoutNaN(Condition);
2740 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2741 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2744 void SelectionDAGBuilder::visitSelect(const User &I) {
2745 SmallVector<EVT, 4> ValueVTs;
2746 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2747 unsigned NumValues = ValueVTs.size();
2748 if (NumValues == 0) return;
2750 SmallVector<SDValue, 4> Values(NumValues);
2751 SDValue Cond = getValue(I.getOperand(0));
2752 SDValue TrueVal = getValue(I.getOperand(1));
2753 SDValue FalseVal = getValue(I.getOperand(2));
2754 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2755 ISD::VSELECT : ISD::SELECT;
2757 for (unsigned i = 0; i != NumValues; ++i)
2758 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2759 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2761 SDValue(TrueVal.getNode(),
2762 TrueVal.getResNo() + i),
2763 SDValue(FalseVal.getNode(),
2764 FalseVal.getResNo() + i));
2766 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2767 DAG.getVTList(&ValueVTs[0], NumValues),
2768 &Values[0], NumValues));
2771 void SelectionDAGBuilder::visitTrunc(const User &I) {
2772 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2773 SDValue N = getValue(I.getOperand(0));
2774 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2775 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2778 void SelectionDAGBuilder::visitZExt(const User &I) {
2779 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2780 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2781 SDValue N = getValue(I.getOperand(0));
2782 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2783 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2786 void SelectionDAGBuilder::visitSExt(const User &I) {
2787 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2788 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2789 SDValue N = getValue(I.getOperand(0));
2790 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2791 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2794 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2795 // FPTrunc is never a no-op cast, no need to check
2796 SDValue N = getValue(I.getOperand(0));
2797 const TargetLowering *TLI = TM.getTargetLowering();
2798 EVT DestVT = TLI->getValueType(I.getType());
2799 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2801 DAG.getTargetConstant(0, TLI->getPointerTy())));
2804 void SelectionDAGBuilder::visitFPExt(const User &I){
2805 // FPExt is never a no-op cast, no need to check
2806 SDValue N = getValue(I.getOperand(0));
2807 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2808 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2811 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2812 // FPToUI is never a no-op cast, no need to check
2813 SDValue N = getValue(I.getOperand(0));
2814 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2815 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2818 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2819 // FPToSI is never a no-op cast, no need to check
2820 SDValue N = getValue(I.getOperand(0));
2821 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2822 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2825 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2826 // UIToFP is never a no-op cast, no need to check
2827 SDValue N = getValue(I.getOperand(0));
2828 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2829 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2832 void SelectionDAGBuilder::visitSIToFP(const User &I){
2833 // SIToFP is never a no-op cast, no need to check
2834 SDValue N = getValue(I.getOperand(0));
2835 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2836 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2839 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2840 // What to do depends on the size of the integer and the size of the pointer.
2841 // We can either truncate, zero extend, or no-op, accordingly.
2842 SDValue N = getValue(I.getOperand(0));
2843 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2844 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2847 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2848 // What to do depends on the size of the integer and the size of the pointer.
2849 // We can either truncate, zero extend, or no-op, accordingly.
2850 SDValue N = getValue(I.getOperand(0));
2851 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2852 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2855 void SelectionDAGBuilder::visitBitCast(const User &I) {
2856 SDValue N = getValue(I.getOperand(0));
2857 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2859 // BitCast assures us that source and destination are the same size so this is
2860 // either a BITCAST or a no-op.
2861 if (DestVT != N.getValueType())
2862 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2863 DestVT, N)); // convert types.
2865 setValue(&I, N); // noop cast.
2868 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2869 SDValue InVec = getValue(I.getOperand(0));
2870 SDValue InVal = getValue(I.getOperand(1));
2871 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
2872 TM.getTargetLowering()->getPointerTy(),
2873 getValue(I.getOperand(2)));
2874 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2875 TM.getTargetLowering()->getValueType(I.getType()),
2876 InVec, InVal, InIdx));
2879 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2880 SDValue InVec = getValue(I.getOperand(0));
2881 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
2882 TM.getTargetLowering()->getPointerTy(),
2883 getValue(I.getOperand(1)));
2884 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2885 TM.getTargetLowering()->getValueType(I.getType()),
2889 // Utility for visitShuffleVector - Return true if every element in Mask,
2890 // beginning from position Pos and ending in Pos+Size, falls within the
2891 // specified sequential range [L, L+Pos). or is undef.
2892 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2893 unsigned Pos, unsigned Size, int Low) {
2894 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2895 if (Mask[i] >= 0 && Mask[i] != Low)
2900 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2901 SDValue Src1 = getValue(I.getOperand(0));
2902 SDValue Src2 = getValue(I.getOperand(1));
2904 SmallVector<int, 8> Mask;
2905 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2906 unsigned MaskNumElts = Mask.size();
2908 const TargetLowering *TLI = TM.getTargetLowering();
2909 EVT VT = TLI->getValueType(I.getType());
2910 EVT SrcVT = Src1.getValueType();
2911 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2913 if (SrcNumElts == MaskNumElts) {
2914 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2919 // Normalize the shuffle vector since mask and vector length don't match.
2920 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2921 // Mask is longer than the source vectors and is a multiple of the source
2922 // vectors. We can use concatenate vector to make the mask and vectors
2924 if (SrcNumElts*2 == MaskNumElts) {
2925 // First check for Src1 in low and Src2 in high
2926 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2927 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2928 // The shuffle is concatenating two vectors together.
2929 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2933 // Then check for Src2 in low and Src1 in high
2934 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2935 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2936 // The shuffle is concatenating two vectors together.
2937 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2943 // Pad both vectors with undefs to make them the same length as the mask.
2944 unsigned NumConcat = MaskNumElts / SrcNumElts;
2945 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2946 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2947 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2949 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2950 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2954 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2956 &MOps1[0], NumConcat);
2957 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2959 &MOps2[0], NumConcat);
2961 // Readjust mask for new input vector length.
2962 SmallVector<int, 8> MappedOps;
2963 for (unsigned i = 0; i != MaskNumElts; ++i) {
2965 if (Idx >= (int)SrcNumElts)
2966 Idx -= SrcNumElts - MaskNumElts;
2967 MappedOps.push_back(Idx);
2970 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2975 if (SrcNumElts > MaskNumElts) {
2976 // Analyze the access pattern of the vector to see if we can extract
2977 // two subvectors and do the shuffle. The analysis is done by calculating
2978 // the range of elements the mask access on both vectors.
2979 int MinRange[2] = { static_cast<int>(SrcNumElts),
2980 static_cast<int>(SrcNumElts)};
2981 int MaxRange[2] = {-1, -1};
2983 for (unsigned i = 0; i != MaskNumElts; ++i) {
2989 if (Idx >= (int)SrcNumElts) {
2993 if (Idx > MaxRange[Input])
2994 MaxRange[Input] = Idx;
2995 if (Idx < MinRange[Input])
2996 MinRange[Input] = Idx;
2999 // Check if the access is smaller than the vector size and can we find
3000 // a reasonable extract index.
3001 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3003 int StartIdx[2]; // StartIdx to extract from
3004 for (unsigned Input = 0; Input < 2; ++Input) {
3005 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3006 RangeUse[Input] = 0; // Unused
3007 StartIdx[Input] = 0;
3011 // Find a good start index that is a multiple of the mask length. Then
3012 // see if the rest of the elements are in range.
3013 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3014 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3015 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3016 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3019 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3020 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3023 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3024 // Extract appropriate subvector and generate a vector shuffle
3025 for (unsigned Input = 0; Input < 2; ++Input) {
3026 SDValue &Src = Input == 0 ? Src1 : Src2;
3027 if (RangeUse[Input] == 0)
3028 Src = DAG.getUNDEF(VT);
3030 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3031 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3034 // Calculate new mask.
3035 SmallVector<int, 8> MappedOps;
3036 for (unsigned i = 0; i != MaskNumElts; ++i) {
3039 if (Idx < (int)SrcNumElts)
3042 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3044 MappedOps.push_back(Idx);
3047 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3053 // We can't use either concat vectors or extract subvectors so fall back to
3054 // replacing the shuffle with extract and build vector.
3055 // to insert and build vector.
3056 EVT EltVT = VT.getVectorElementType();
3057 EVT PtrVT = TLI->getPointerTy();
3058 SmallVector<SDValue,8> Ops;
3059 for (unsigned i = 0; i != MaskNumElts; ++i) {
3064 Res = DAG.getUNDEF(EltVT);
3066 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3067 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3069 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3070 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3076 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3077 VT, &Ops[0], Ops.size()));
3080 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3081 const Value *Op0 = I.getOperand(0);
3082 const Value *Op1 = I.getOperand(1);
3083 Type *AggTy = I.getType();
3084 Type *ValTy = Op1->getType();
3085 bool IntoUndef = isa<UndefValue>(Op0);
3086 bool FromUndef = isa<UndefValue>(Op1);
3088 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3090 const TargetLowering *TLI = TM.getTargetLowering();
3091 SmallVector<EVT, 4> AggValueVTs;
3092 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3093 SmallVector<EVT, 4> ValValueVTs;
3094 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3096 unsigned NumAggValues = AggValueVTs.size();
3097 unsigned NumValValues = ValValueVTs.size();
3098 SmallVector<SDValue, 4> Values(NumAggValues);
3100 SDValue Agg = getValue(Op0);
3102 // Copy the beginning value(s) from the original aggregate.
3103 for (; i != LinearIndex; ++i)
3104 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3105 SDValue(Agg.getNode(), Agg.getResNo() + i);
3106 // Copy values from the inserted value(s).
3108 SDValue Val = getValue(Op1);
3109 for (; i != LinearIndex + NumValValues; ++i)
3110 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3111 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3113 // Copy remaining value(s) from the original aggregate.
3114 for (; i != NumAggValues; ++i)
3115 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3116 SDValue(Agg.getNode(), Agg.getResNo() + i);
3118 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3119 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3120 &Values[0], NumAggValues));
3123 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3124 const Value *Op0 = I.getOperand(0);
3125 Type *AggTy = Op0->getType();
3126 Type *ValTy = I.getType();
3127 bool OutOfUndef = isa<UndefValue>(Op0);
3129 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3131 const TargetLowering *TLI = TM.getTargetLowering();
3132 SmallVector<EVT, 4> ValValueVTs;
3133 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3135 unsigned NumValValues = ValValueVTs.size();
3137 // Ignore a extractvalue that produces an empty object
3138 if (!NumValValues) {
3139 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3143 SmallVector<SDValue, 4> Values(NumValValues);
3145 SDValue Agg = getValue(Op0);
3146 // Copy out the selected value(s).
3147 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3148 Values[i - LinearIndex] =
3150 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3151 SDValue(Agg.getNode(), Agg.getResNo() + i);
3153 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3154 DAG.getVTList(&ValValueVTs[0], NumValValues),
3155 &Values[0], NumValValues));
3158 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3159 SDValue N = getValue(I.getOperand(0));
3160 // Note that the pointer operand may be a vector of pointers. Take the scalar
3161 // element which holds a pointer.
3162 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3164 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3166 const Value *Idx = *OI;
3167 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3168 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3171 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3172 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3173 DAG.getConstant(Offset, N.getValueType()));
3176 Ty = StTy->getElementType(Field);
3178 Ty = cast<SequentialType>(Ty)->getElementType();
3180 // If this is a constant subscript, handle it quickly.
3181 const TargetLowering *TLI = TM.getTargetLowering();
3182 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3183 if (CI->isZero()) continue;
3185 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3187 EVT PTy = TLI->getPointerTy();
3188 unsigned PtrBits = PTy.getSizeInBits();
3190 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(),
3191 TLI->getPointerTy(),
3192 DAG.getConstant(Offs, MVT::i64));
3194 OffsVal = DAG.getIntPtrConstant(Offs);
3196 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3201 // N = N + Idx * ElementSize;
3202 APInt ElementSize = APInt(TLI->getPointerTy().getSizeInBits(),
3203 TD->getTypeAllocSize(Ty));
3204 SDValue IdxN = getValue(Idx);
3206 // If the index is smaller or larger than intptr_t, truncate or extend
3208 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3210 // If this is a multiply by a power of two, turn it into a shl
3211 // immediately. This is a very common case.
3212 if (ElementSize != 1) {
3213 if (ElementSize.isPowerOf2()) {
3214 unsigned Amt = ElementSize.logBase2();
3215 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3216 N.getValueType(), IdxN,
3217 DAG.getConstant(Amt, IdxN.getValueType()));
3219 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3220 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3221 N.getValueType(), IdxN, Scale);
3225 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3226 N.getValueType(), N, IdxN);
3233 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3234 // If this is a fixed sized alloca in the entry block of the function,
3235 // allocate it statically on the stack.
3236 if (FuncInfo.StaticAllocaMap.count(&I))
3237 return; // getValue will auto-populate this.
3239 Type *Ty = I.getAllocatedType();
3240 const TargetLowering *TLI = TM.getTargetLowering();
3241 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3243 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3246 SDValue AllocSize = getValue(I.getArraySize());
3248 EVT IntPtr = TLI->getPointerTy();
3249 if (AllocSize.getValueType() != IntPtr)
3250 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3252 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3254 DAG.getConstant(TySize, IntPtr));
3256 // Handle alignment. If the requested alignment is less than or equal to
3257 // the stack alignment, ignore it. If the size is greater than or equal to
3258 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3259 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3260 if (Align <= StackAlign)
3263 // Round the size of the allocation up to the stack alignment size
3264 // by add SA-1 to the size.
3265 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3266 AllocSize.getValueType(), AllocSize,
3267 DAG.getIntPtrConstant(StackAlign-1));
3269 // Mask out the low bits for alignment purposes.
3270 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3271 AllocSize.getValueType(), AllocSize,
3272 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3274 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3275 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3276 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3279 DAG.setRoot(DSA.getValue(1));
3281 // Inform the Frame Information that we have just allocated a variable-sized
3283 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3286 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3288 return visitAtomicLoad(I);
3290 const Value *SV = I.getOperand(0);
3291 SDValue Ptr = getValue(SV);
3293 Type *Ty = I.getType();
3295 bool isVolatile = I.isVolatile();
3296 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3297 bool isInvariant = I.getMetadata("invariant.load") != 0;
3298 unsigned Alignment = I.getAlignment();
3299 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3300 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3302 SmallVector<EVT, 4> ValueVTs;
3303 SmallVector<uint64_t, 4> Offsets;
3304 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3305 unsigned NumValues = ValueVTs.size();
3310 bool ConstantMemory = false;
3311 if (I.isVolatile() || NumValues > MaxParallelChains)
3312 // Serialize volatile loads with other side effects.
3314 else if (AA->pointsToConstantMemory(
3315 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3316 // Do not serialize (non-volatile) loads of constant memory with anything.
3317 Root = DAG.getEntryNode();
3318 ConstantMemory = true;
3320 // Do not serialize non-volatile loads against each other.
3321 Root = DAG.getRoot();
3324 SmallVector<SDValue, 4> Values(NumValues);
3325 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3327 EVT PtrVT = Ptr.getValueType();
3328 unsigned ChainI = 0;
3329 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3330 // Serializing loads here may result in excessive register pressure, and
3331 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3332 // could recover a bit by hoisting nodes upward in the chain by recognizing
3333 // they are side-effect free or do not alias. The optimizer should really
3334 // avoid this case by converting large object/array copies to llvm.memcpy
3335 // (MaxParallelChains should always remain as failsafe).
3336 if (ChainI == MaxParallelChains) {
3337 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3338 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3339 MVT::Other, &Chains[0], ChainI);
3343 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3345 DAG.getConstant(Offsets[i], PtrVT));
3346 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3347 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3348 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3352 Chains[ChainI] = L.getValue(1);
3355 if (!ConstantMemory) {
3356 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3357 MVT::Other, &Chains[0], ChainI);
3361 PendingLoads.push_back(Chain);
3364 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3365 DAG.getVTList(&ValueVTs[0], NumValues),
3366 &Values[0], NumValues));
3369 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3371 return visitAtomicStore(I);
3373 const Value *SrcV = I.getOperand(0);
3374 const Value *PtrV = I.getOperand(1);
3376 SmallVector<EVT, 4> ValueVTs;
3377 SmallVector<uint64_t, 4> Offsets;
3378 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3379 unsigned NumValues = ValueVTs.size();
3383 // Get the lowered operands. Note that we do this after
3384 // checking if NumResults is zero, because with zero results
3385 // the operands won't have values in the map.
3386 SDValue Src = getValue(SrcV);
3387 SDValue Ptr = getValue(PtrV);
3389 SDValue Root = getRoot();
3390 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3392 EVT PtrVT = Ptr.getValueType();
3393 bool isVolatile = I.isVolatile();
3394 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3395 unsigned Alignment = I.getAlignment();
3396 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3398 unsigned ChainI = 0;
3399 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3400 // See visitLoad comments.
3401 if (ChainI == MaxParallelChains) {
3402 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3403 MVT::Other, &Chains[0], ChainI);
3407 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3408 DAG.getConstant(Offsets[i], PtrVT));
3409 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3410 SDValue(Src.getNode(), Src.getResNo() + i),
3411 Add, MachinePointerInfo(PtrV, Offsets[i]),
3412 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3413 Chains[ChainI] = St;
3416 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3417 MVT::Other, &Chains[0], ChainI);
3418 DAG.setRoot(StoreNode);
3421 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3422 SynchronizationScope Scope,
3423 bool Before, SDLoc dl,
3425 const TargetLowering &TLI) {
3426 // Fence, if necessary
3428 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3430 else if (Order == Acquire || Order == Monotonic)
3433 if (Order == AcquireRelease)
3435 else if (Order == Release || Order == Monotonic)
3440 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3441 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3442 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3445 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3446 SDLoc dl = getCurSDLoc();
3447 AtomicOrdering Order = I.getOrdering();
3448 SynchronizationScope Scope = I.getSynchScope();
3450 SDValue InChain = getRoot();
3452 const TargetLowering *TLI = TM.getTargetLowering();
3453 if (TLI->getInsertFencesForAtomic())
3454 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3458 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3459 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3461 getValue(I.getPointerOperand()),
3462 getValue(I.getCompareOperand()),
3463 getValue(I.getNewValOperand()),
3464 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3465 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3468 SDValue OutChain = L.getValue(1);
3470 if (TLI->getInsertFencesForAtomic())
3471 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3475 DAG.setRoot(OutChain);
3478 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3479 SDLoc dl = getCurSDLoc();
3481 switch (I.getOperation()) {
3482 default: llvm_unreachable("Unknown atomicrmw operation");
3483 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3484 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3485 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3486 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3487 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3488 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3489 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3490 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3491 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3492 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3493 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3495 AtomicOrdering Order = I.getOrdering();
3496 SynchronizationScope Scope = I.getSynchScope();
3498 SDValue InChain = getRoot();
3500 const TargetLowering *TLI = TM.getTargetLowering();
3501 if (TLI->getInsertFencesForAtomic())
3502 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3506 DAG.getAtomic(NT, dl,
3507 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3509 getValue(I.getPointerOperand()),
3510 getValue(I.getValOperand()),
3511 I.getPointerOperand(), 0 /* Alignment */,
3512 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3515 SDValue OutChain = L.getValue(1);
3517 if (TLI->getInsertFencesForAtomic())
3518 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3522 DAG.setRoot(OutChain);
3525 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3526 SDLoc dl = getCurSDLoc();
3527 const TargetLowering *TLI = TM.getTargetLowering();
3530 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3531 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3532 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3535 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3536 SDLoc dl = getCurSDLoc();
3537 AtomicOrdering Order = I.getOrdering();
3538 SynchronizationScope Scope = I.getSynchScope();
3540 SDValue InChain = getRoot();
3542 const TargetLowering *TLI = TM.getTargetLowering();
3543 EVT VT = TLI->getValueType(I.getType());
3545 if (I.getAlignment() < VT.getSizeInBits() / 8)
3546 report_fatal_error("Cannot generate unaligned atomic load");
3549 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3550 getValue(I.getPointerOperand()),
3551 I.getPointerOperand(), I.getAlignment(),
3552 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3555 SDValue OutChain = L.getValue(1);
3557 if (TLI->getInsertFencesForAtomic())
3558 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3562 DAG.setRoot(OutChain);
3565 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3566 SDLoc dl = getCurSDLoc();
3568 AtomicOrdering Order = I.getOrdering();
3569 SynchronizationScope Scope = I.getSynchScope();
3571 SDValue InChain = getRoot();
3573 const TargetLowering *TLI = TM.getTargetLowering();
3574 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3576 if (I.getAlignment() < VT.getSizeInBits() / 8)
3577 report_fatal_error("Cannot generate unaligned atomic store");
3579 if (TLI->getInsertFencesForAtomic())
3580 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3584 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3586 getValue(I.getPointerOperand()),
3587 getValue(I.getValueOperand()),
3588 I.getPointerOperand(), I.getAlignment(),
3589 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3592 if (TLI->getInsertFencesForAtomic())
3593 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3596 DAG.setRoot(OutChain);
3599 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3601 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3602 unsigned Intrinsic) {
3603 bool HasChain = !I.doesNotAccessMemory();
3604 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3606 // Build the operand list.
3607 SmallVector<SDValue, 8> Ops;
3608 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3610 // We don't need to serialize loads against other loads.
3611 Ops.push_back(DAG.getRoot());
3613 Ops.push_back(getRoot());
3617 // Info is set by getTgtMemInstrinsic
3618 TargetLowering::IntrinsicInfo Info;
3619 const TargetLowering *TLI = TM.getTargetLowering();
3620 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3622 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3623 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3624 Info.opc == ISD::INTRINSIC_W_CHAIN)
3625 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3627 // Add all operands of the call to the operand list.
3628 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3629 SDValue Op = getValue(I.getArgOperand(i));
3633 SmallVector<EVT, 4> ValueVTs;
3634 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3637 ValueVTs.push_back(MVT::Other);
3639 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3643 if (IsTgtIntrinsic) {
3644 // This is target intrinsic that touches memory
3645 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3646 VTs, &Ops[0], Ops.size(),
3648 MachinePointerInfo(Info.ptrVal, Info.offset),
3649 Info.align, Info.vol,
3650 Info.readMem, Info.writeMem);
3651 } else if (!HasChain) {
3652 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3653 VTs, &Ops[0], Ops.size());
3654 } else if (!I.getType()->isVoidTy()) {
3655 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3656 VTs, &Ops[0], Ops.size());
3658 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3659 VTs, &Ops[0], Ops.size());
3663 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3665 PendingLoads.push_back(Chain);
3670 if (!I.getType()->isVoidTy()) {
3671 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3672 EVT VT = TLI->getValueType(PTy);
3673 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3676 setValue(&I, Result);
3680 /// GetSignificand - Get the significand and build it into a floating-point
3681 /// number with exponent of 1:
3683 /// Op = (Op & 0x007fffff) | 0x3f800000;
3685 /// where Op is the hexadecimal representation of floating point value.
3687 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3688 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3689 DAG.getConstant(0x007fffff, MVT::i32));
3690 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3691 DAG.getConstant(0x3f800000, MVT::i32));
3692 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3695 /// GetExponent - Get the exponent:
3697 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3699 /// where Op is the hexadecimal representation of floating point value.
3701 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3703 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3704 DAG.getConstant(0x7f800000, MVT::i32));
3705 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3706 DAG.getConstant(23, TLI.getPointerTy()));
3707 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3708 DAG.getConstant(127, MVT::i32));
3709 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3712 /// getF32Constant - Get 32-bit floating point constant.
3714 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3715 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3719 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3720 /// limited-precision mode.
3721 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3722 const TargetLowering &TLI) {
3723 if (Op.getValueType() == MVT::f32 &&
3724 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3726 // Put the exponent in the right bit position for later addition to the
3729 // #define LOG2OFe 1.4426950f
3730 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3731 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3732 getF32Constant(DAG, 0x3fb8aa3b));
3733 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3735 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3736 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3737 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3739 // IntegerPartOfX <<= 23;
3740 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3741 DAG.getConstant(23, TLI.getPointerTy()));
3743 SDValue TwoToFracPartOfX;
3744 if (LimitFloatPrecision <= 6) {
3745 // For floating-point precision of 6:
3747 // TwoToFractionalPartOfX =
3749 // (0.735607626f + 0.252464424f * x) * x;
3751 // error 0.0144103317, which is 6 bits
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0x3e814304));
3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3f3c50c8));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x3f7f5e7e));
3759 } else if (LimitFloatPrecision <= 12) {
3760 // For floating-point precision of 12:
3762 // TwoToFractionalPartOfX =
3765 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3767 // 0.000107046256 error, which is 13 to 14 bits
3768 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3769 getF32Constant(DAG, 0x3da235e3));
3770 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3771 getF32Constant(DAG, 0x3e65b8f3));
3772 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3773 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3774 getF32Constant(DAG, 0x3f324b07));
3775 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3776 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3777 getF32Constant(DAG, 0x3f7ff8fd));
3778 } else { // LimitFloatPrecision <= 18
3779 // For floating-point precision of 18:
3781 // TwoToFractionalPartOfX =
3785 // (0.554906021e-1f +
3786 // (0.961591928e-2f +
3787 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3789 // error 2.47208000*10^(-7), which is better than 18 bits
3790 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3791 getF32Constant(DAG, 0x3924b03e));
3792 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3793 getF32Constant(DAG, 0x3ab24b87));
3794 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3795 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3796 getF32Constant(DAG, 0x3c1d8c17));
3797 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3798 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3799 getF32Constant(DAG, 0x3d634a1d));
3800 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3801 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3802 getF32Constant(DAG, 0x3e75fe14));
3803 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3804 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3805 getF32Constant(DAG, 0x3f317234));
3806 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3807 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3808 getF32Constant(DAG, 0x3f800000));
3811 // Add the exponent into the result in integer domain.
3812 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3813 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3814 DAG.getNode(ISD::ADD, dl, MVT::i32,
3815 t13, IntegerPartOfX));
3818 // No special expansion.
3819 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3822 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3823 /// limited-precision mode.
3824 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3825 const TargetLowering &TLI) {
3826 if (Op.getValueType() == MVT::f32 &&
3827 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3828 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3830 // Scale the exponent by log(2) [0.69314718f].
3831 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3832 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3833 getF32Constant(DAG, 0x3f317218));
3835 // Get the significand and build it into a floating-point number with
3837 SDValue X = GetSignificand(DAG, Op1, dl);
3839 SDValue LogOfMantissa;
3840 if (LimitFloatPrecision <= 6) {
3841 // For floating-point precision of 6:
3845 // (1.4034025f - 0.23903021f * x) * x;
3847 // error 0.0034276066, which is better than 8 bits
3848 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3849 getF32Constant(DAG, 0xbe74c456));
3850 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3851 getF32Constant(DAG, 0x3fb3a2b1));
3852 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3853 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3854 getF32Constant(DAG, 0x3f949a29));
3855 } else if (LimitFloatPrecision <= 12) {
3856 // For floating-point precision of 12:
3862 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3864 // error 0.000061011436, which is 14 bits
3865 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3866 getF32Constant(DAG, 0xbd67b6d6));
3867 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3868 getF32Constant(DAG, 0x3ee4f4b8));
3869 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3870 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3871 getF32Constant(DAG, 0x3fbc278b));
3872 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3873 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3874 getF32Constant(DAG, 0x40348e95));
3875 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3876 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3877 getF32Constant(DAG, 0x3fdef31a));
3878 } else { // LimitFloatPrecision <= 18
3879 // For floating-point precision of 18:
3887 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3889 // error 0.0000023660568, which is better than 18 bits
3890 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3891 getF32Constant(DAG, 0xbc91e5ac));
3892 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3893 getF32Constant(DAG, 0x3e4350aa));
3894 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3895 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3896 getF32Constant(DAG, 0x3f60d3e3));
3897 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3898 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3899 getF32Constant(DAG, 0x4011cdf0));
3900 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3901 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3902 getF32Constant(DAG, 0x406cfd1c));
3903 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3904 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3905 getF32Constant(DAG, 0x408797cb));
3906 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3907 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3908 getF32Constant(DAG, 0x4006dcab));
3911 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3914 // No special expansion.
3915 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3918 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3919 /// limited-precision mode.
3920 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3921 const TargetLowering &TLI) {
3922 if (Op.getValueType() == MVT::f32 &&
3923 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3924 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3926 // Get the exponent.
3927 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3929 // Get the significand and build it into a floating-point number with
3931 SDValue X = GetSignificand(DAG, Op1, dl);
3933 // Different possible minimax approximations of significand in
3934 // floating-point for various degrees of accuracy over [1,2].
3935 SDValue Log2ofMantissa;
3936 if (LimitFloatPrecision <= 6) {
3937 // For floating-point precision of 6:
3939 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3941 // error 0.0049451742, which is more than 7 bits
3942 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3943 getF32Constant(DAG, 0xbeb08fe0));
3944 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3945 getF32Constant(DAG, 0x40019463));
3946 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3947 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3948 getF32Constant(DAG, 0x3fd6633d));
3949 } else if (LimitFloatPrecision <= 12) {
3950 // For floating-point precision of 12:
3956 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3958 // error 0.0000876136000, which is better than 13 bits
3959 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3960 getF32Constant(DAG, 0xbda7262e));
3961 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3962 getF32Constant(DAG, 0x3f25280b));
3963 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3964 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3965 getF32Constant(DAG, 0x4007b923));
3966 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3967 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3968 getF32Constant(DAG, 0x40823e2f));
3969 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3970 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3971 getF32Constant(DAG, 0x4020d29c));
3972 } else { // LimitFloatPrecision <= 18
3973 // For floating-point precision of 18:
3982 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3984 // error 0.0000018516, which is better than 18 bits
3985 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3986 getF32Constant(DAG, 0xbcd2769e));
3987 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3988 getF32Constant(DAG, 0x3e8ce0b9));
3989 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3990 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3991 getF32Constant(DAG, 0x3fa22ae7));
3992 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3993 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3994 getF32Constant(DAG, 0x40525723));
3995 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3996 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3997 getF32Constant(DAG, 0x40aaf200));
3998 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3999 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4000 getF32Constant(DAG, 0x40c39dad));
4001 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4002 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4003 getF32Constant(DAG, 0x4042902c));
4006 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4009 // No special expansion.
4010 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4013 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4014 /// limited-precision mode.
4015 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4016 const TargetLowering &TLI) {
4017 if (Op.getValueType() == MVT::f32 &&
4018 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4019 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4021 // Scale the exponent by log10(2) [0.30102999f].
4022 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4023 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4024 getF32Constant(DAG, 0x3e9a209a));
4026 // Get the significand and build it into a floating-point number with
4028 SDValue X = GetSignificand(DAG, Op1, dl);
4030 SDValue Log10ofMantissa;
4031 if (LimitFloatPrecision <= 6) {
4032 // For floating-point precision of 6:
4034 // Log10ofMantissa =
4036 // (0.60948995f - 0.10380950f * x) * x;
4038 // error 0.0014886165, which is 6 bits
4039 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4040 getF32Constant(DAG, 0xbdd49a13));
4041 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4042 getF32Constant(DAG, 0x3f1c0789));
4043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4044 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4045 getF32Constant(DAG, 0x3f011300));
4046 } else if (LimitFloatPrecision <= 12) {
4047 // For floating-point precision of 12:
4049 // Log10ofMantissa =
4052 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4054 // error 0.00019228036, which is better than 12 bits
4055 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4056 getF32Constant(DAG, 0x3d431f31));
4057 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4058 getF32Constant(DAG, 0x3ea21fb2));
4059 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4060 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4061 getF32Constant(DAG, 0x3f6ae232));
4062 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4063 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4064 getF32Constant(DAG, 0x3f25f7c3));
4065 } else { // LimitFloatPrecision <= 18
4066 // For floating-point precision of 18:
4068 // Log10ofMantissa =
4073 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4075 // error 0.0000037995730, which is better than 18 bits
4076 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4077 getF32Constant(DAG, 0x3c5d51ce));
4078 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4079 getF32Constant(DAG, 0x3e00685a));
4080 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4081 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4082 getF32Constant(DAG, 0x3efb6798));
4083 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4084 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4085 getF32Constant(DAG, 0x3f88d192));
4086 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4087 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4088 getF32Constant(DAG, 0x3fc4316c));
4089 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4090 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4091 getF32Constant(DAG, 0x3f57ce70));
4094 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4097 // No special expansion.
4098 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4101 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4102 /// limited-precision mode.
4103 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4104 const TargetLowering &TLI) {
4105 if (Op.getValueType() == MVT::f32 &&
4106 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4107 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4109 // FractionalPartOfX = x - (float)IntegerPartOfX;
4110 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4111 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4113 // IntegerPartOfX <<= 23;
4114 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4115 DAG.getConstant(23, TLI.getPointerTy()));
4117 SDValue TwoToFractionalPartOfX;
4118 if (LimitFloatPrecision <= 6) {
4119 // For floating-point precision of 6:
4121 // TwoToFractionalPartOfX =
4123 // (0.735607626f + 0.252464424f * x) * x;
4125 // error 0.0144103317, which is 6 bits
4126 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4127 getF32Constant(DAG, 0x3e814304));
4128 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4129 getF32Constant(DAG, 0x3f3c50c8));
4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4131 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4132 getF32Constant(DAG, 0x3f7f5e7e));
4133 } else if (LimitFloatPrecision <= 12) {
4134 // For floating-point precision of 12:
4136 // TwoToFractionalPartOfX =
4139 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4141 // error 0.000107046256, which is 13 to 14 bits
4142 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4143 getF32Constant(DAG, 0x3da235e3));
4144 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4145 getF32Constant(DAG, 0x3e65b8f3));
4146 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4147 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4148 getF32Constant(DAG, 0x3f324b07));
4149 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4150 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4151 getF32Constant(DAG, 0x3f7ff8fd));
4152 } else { // LimitFloatPrecision <= 18
4153 // For floating-point precision of 18:
4155 // TwoToFractionalPartOfX =
4159 // (0.554906021e-1f +
4160 // (0.961591928e-2f +
4161 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4162 // error 2.47208000*10^(-7), which is better than 18 bits
4163 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4164 getF32Constant(DAG, 0x3924b03e));
4165 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4166 getF32Constant(DAG, 0x3ab24b87));
4167 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4168 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4169 getF32Constant(DAG, 0x3c1d8c17));
4170 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4171 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4172 getF32Constant(DAG, 0x3d634a1d));
4173 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4174 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4175 getF32Constant(DAG, 0x3e75fe14));
4176 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4177 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4178 getF32Constant(DAG, 0x3f317234));
4179 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4180 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4181 getF32Constant(DAG, 0x3f800000));
4184 // Add the exponent into the result in integer domain.
4185 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4186 TwoToFractionalPartOfX);
4187 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4188 DAG.getNode(ISD::ADD, dl, MVT::i32,
4189 t13, IntegerPartOfX));
4192 // No special expansion.
4193 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4196 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4197 /// limited-precision mode with x == 10.0f.
4198 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4199 SelectionDAG &DAG, const TargetLowering &TLI) {
4200 bool IsExp10 = false;
4201 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4202 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4203 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4205 IsExp10 = LHSC->isExactlyValue(Ten);
4210 // Put the exponent in the right bit position for later addition to the
4213 // #define LOG2OF10 3.3219281f
4214 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4215 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4216 getF32Constant(DAG, 0x40549a78));
4217 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4219 // FractionalPartOfX = x - (float)IntegerPartOfX;
4220 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4221 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4223 // IntegerPartOfX <<= 23;
4224 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4225 DAG.getConstant(23, TLI.getPointerTy()));
4227 SDValue TwoToFractionalPartOfX;
4228 if (LimitFloatPrecision <= 6) {
4229 // For floating-point precision of 6:
4231 // twoToFractionalPartOfX =
4233 // (0.735607626f + 0.252464424f * x) * x;
4235 // error 0.0144103317, which is 6 bits
4236 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4237 getF32Constant(DAG, 0x3e814304));
4238 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4239 getF32Constant(DAG, 0x3f3c50c8));
4240 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4241 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4242 getF32Constant(DAG, 0x3f7f5e7e));
4243 } else if (LimitFloatPrecision <= 12) {
4244 // For floating-point precision of 12:
4246 // TwoToFractionalPartOfX =
4249 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4251 // error 0.000107046256, which is 13 to 14 bits
4252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4253 getF32Constant(DAG, 0x3da235e3));
4254 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4255 getF32Constant(DAG, 0x3e65b8f3));
4256 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4257 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4258 getF32Constant(DAG, 0x3f324b07));
4259 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4260 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4261 getF32Constant(DAG, 0x3f7ff8fd));
4262 } else { // LimitFloatPrecision <= 18
4263 // For floating-point precision of 18:
4265 // TwoToFractionalPartOfX =
4269 // (0.554906021e-1f +
4270 // (0.961591928e-2f +
4271 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4272 // error 2.47208000*10^(-7), which is better than 18 bits
4273 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4274 getF32Constant(DAG, 0x3924b03e));
4275 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4276 getF32Constant(DAG, 0x3ab24b87));
4277 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4278 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4279 getF32Constant(DAG, 0x3c1d8c17));
4280 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4281 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4282 getF32Constant(DAG, 0x3d634a1d));
4283 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4284 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4285 getF32Constant(DAG, 0x3e75fe14));
4286 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4287 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4288 getF32Constant(DAG, 0x3f317234));
4289 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4290 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4291 getF32Constant(DAG, 0x3f800000));
4294 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4295 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4296 DAG.getNode(ISD::ADD, dl, MVT::i32,
4297 t13, IntegerPartOfX));
4300 // No special expansion.
4301 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4305 /// ExpandPowI - Expand a llvm.powi intrinsic.
4306 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4307 SelectionDAG &DAG) {
4308 // If RHS is a constant, we can expand this out to a multiplication tree,
4309 // otherwise we end up lowering to a call to __powidf2 (for example). When
4310 // optimizing for size, we only want to do this if the expansion would produce
4311 // a small number of multiplies, otherwise we do the full expansion.
4312 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4313 // Get the exponent as a positive value.
4314 unsigned Val = RHSC->getSExtValue();
4315 if ((int)Val < 0) Val = -Val;
4317 // powi(x, 0) -> 1.0
4319 return DAG.getConstantFP(1.0, LHS.getValueType());
4321 const Function *F = DAG.getMachineFunction().getFunction();
4322 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4323 Attribute::OptimizeForSize) ||
4324 // If optimizing for size, don't insert too many multiplies. This
4325 // inserts up to 5 multiplies.
4326 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4327 // We use the simple binary decomposition method to generate the multiply
4328 // sequence. There are more optimal ways to do this (for example,
4329 // powi(x,15) generates one more multiply than it should), but this has
4330 // the benefit of being both really simple and much better than a libcall.
4331 SDValue Res; // Logically starts equal to 1.0
4332 SDValue CurSquare = LHS;
4336 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4338 Res = CurSquare; // 1.0*CurSquare.
4341 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4342 CurSquare, CurSquare);
4346 // If the original was negative, invert the result, producing 1/(x*x*x).
4347 if (RHSC->getSExtValue() < 0)
4348 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4349 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4354 // Otherwise, expand to a libcall.
4355 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4358 // getTruncatedArgReg - Find underlying register used for an truncated
4360 static unsigned getTruncatedArgReg(const SDValue &N) {
4361 if (N.getOpcode() != ISD::TRUNCATE)
4364 const SDValue &Ext = N.getOperand(0);
4365 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4366 const SDValue &CFR = Ext.getOperand(0);
4367 if (CFR.getOpcode() == ISD::CopyFromReg)
4368 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4369 if (CFR.getOpcode() == ISD::TRUNCATE)
4370 return getTruncatedArgReg(CFR);
4375 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4376 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4377 /// At the end of instruction selection, they will be inserted to the entry BB.
4379 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4382 const Argument *Arg = dyn_cast<Argument>(V);
4386 MachineFunction &MF = DAG.getMachineFunction();
4387 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4389 // Ignore inlined function arguments here.
4390 DIVariable DV(Variable);
4391 if (DV.isInlinedFnArgument(MF.getFunction()))
4394 Optional<MachineOperand> Op;
4395 // Some arguments' frame index is recorded during argument lowering.
4396 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4397 Op = MachineOperand::CreateFI(FI);
4399 if (!Op && N.getNode()) {
4401 if (N.getOpcode() == ISD::CopyFromReg)
4402 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4404 Reg = getTruncatedArgReg(N);
4405 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4406 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4407 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4412 Op = MachineOperand::CreateReg(Reg, false);
4416 // Check if ValueMap has reg number.
4417 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4418 if (VMI != FuncInfo.ValueMap.end())
4419 Op = MachineOperand::CreateReg(VMI->second, false);
4422 if (!Op && N.getNode())
4423 // Check if frame index is available.
4424 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4425 if (FrameIndexSDNode *FINode =
4426 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4427 Op = MachineOperand::CreateFI(FINode->getIndex());
4435 FuncInfo.ArgDbgValues.push_back(
4436 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4437 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4441 // VisualStudio defines setjmp as _setjmp
4442 #if defined(_MSC_VER) && defined(setjmp) && \
4443 !defined(setjmp_undefined_for_msvc)
4444 # pragma push_macro("setjmp")
4446 # define setjmp_undefined_for_msvc
4449 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4450 /// we want to emit this as a call to a named external function, return the name
4451 /// otherwise lower it and return null.
4453 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4454 const TargetLowering *TLI = TM.getTargetLowering();
4455 SDLoc sdl = getCurSDLoc();
4456 DebugLoc dl = getCurDebugLoc();
4459 switch (Intrinsic) {
4461 // By default, turn this into a target intrinsic node.
4462 visitTargetIntrinsic(I, Intrinsic);
4464 case Intrinsic::vastart: visitVAStart(I); return 0;
4465 case Intrinsic::vaend: visitVAEnd(I); return 0;
4466 case Intrinsic::vacopy: visitVACopy(I); return 0;
4467 case Intrinsic::returnaddress:
4468 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4469 getValue(I.getArgOperand(0))));
4471 case Intrinsic::frameaddress:
4472 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4473 getValue(I.getArgOperand(0))));
4475 case Intrinsic::setjmp:
4476 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4477 case Intrinsic::longjmp:
4478 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4479 case Intrinsic::memcpy: {
4480 // Assert for address < 256 since we support only user defined address
4482 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4484 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4486 "Unknown address space");
4487 SDValue Op1 = getValue(I.getArgOperand(0));
4488 SDValue Op2 = getValue(I.getArgOperand(1));
4489 SDValue Op3 = getValue(I.getArgOperand(2));
4490 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4492 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4493 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4494 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4495 MachinePointerInfo(I.getArgOperand(0)),
4496 MachinePointerInfo(I.getArgOperand(1))));
4499 case Intrinsic::memset: {
4500 // Assert for address < 256 since we support only user defined address
4502 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4504 "Unknown address space");
4505 SDValue Op1 = getValue(I.getArgOperand(0));
4506 SDValue Op2 = getValue(I.getArgOperand(1));
4507 SDValue Op3 = getValue(I.getArgOperand(2));
4508 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4510 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4511 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4512 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4513 MachinePointerInfo(I.getArgOperand(0))));
4516 case Intrinsic::memmove: {
4517 // Assert for address < 256 since we support only user defined address
4519 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4521 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4523 "Unknown address space");
4524 SDValue Op1 = getValue(I.getArgOperand(0));
4525 SDValue Op2 = getValue(I.getArgOperand(1));
4526 SDValue Op3 = getValue(I.getArgOperand(2));
4527 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4529 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4530 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4531 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4532 MachinePointerInfo(I.getArgOperand(0)),
4533 MachinePointerInfo(I.getArgOperand(1))));
4536 case Intrinsic::dbg_declare: {
4537 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4538 MDNode *Variable = DI.getVariable();
4539 const Value *Address = DI.getAddress();
4540 DIVariable DIVar(Variable);
4541 assert((!DIVar || DIVar.isVariable()) &&
4542 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4543 if (!Address || !DIVar) {
4544 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4548 // Check if address has undef value.
4549 if (isa<UndefValue>(Address) ||
4550 (Address->use_empty() && !isa<Argument>(Address))) {
4551 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4555 SDValue &N = NodeMap[Address];
4556 if (!N.getNode() && isa<Argument>(Address))
4557 // Check unused arguments map.
4558 N = UnusedArgNodeMap[Address];
4561 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4562 Address = BCI->getOperand(0);
4563 // Parameters are handled specially.
4565 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4566 isa<Argument>(Address));
4568 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4570 if (isParameter && !AI) {
4571 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4573 // Byval parameter. We have a frame index at this point.
4574 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4575 0, dl, SDNodeOrder);
4577 // Address is an argument, so try to emit its dbg value using
4578 // virtual register info from the FuncInfo.ValueMap.
4579 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4583 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4584 0, dl, SDNodeOrder);
4586 // Can't do anything with other non-AI cases yet.
4587 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4588 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4589 DEBUG(Address->dump());
4592 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4594 // If Address is an argument then try to emit its dbg value using
4595 // virtual register info from the FuncInfo.ValueMap.
4596 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4597 // If variable is pinned by a alloca in dominating bb then
4598 // use StaticAllocaMap.
4599 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4600 if (AI->getParent() != DI.getParent()) {
4601 DenseMap<const AllocaInst*, int>::iterator SI =
4602 FuncInfo.StaticAllocaMap.find(AI);
4603 if (SI != FuncInfo.StaticAllocaMap.end()) {
4604 SDV = DAG.getDbgValue(Variable, SI->second,
4605 0, dl, SDNodeOrder);
4606 DAG.AddDbgValue(SDV, 0, false);
4611 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4616 case Intrinsic::dbg_value: {
4617 const DbgValueInst &DI = cast<DbgValueInst>(I);
4618 DIVariable DIVar(DI.getVariable());
4619 assert((!DIVar || DIVar.isVariable()) &&
4620 "Variable in DbgValueInst should be either null or a DIVariable.");
4624 MDNode *Variable = DI.getVariable();
4625 uint64_t Offset = DI.getOffset();
4626 const Value *V = DI.getValue();
4631 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4632 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4633 DAG.AddDbgValue(SDV, 0, false);
4635 // Do not use getValue() in here; we don't want to generate code at
4636 // this point if it hasn't been done yet.
4637 SDValue N = NodeMap[V];
4638 if (!N.getNode() && isa<Argument>(V))
4639 // Check unused arguments map.
4640 N = UnusedArgNodeMap[V];
4642 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4643 SDV = DAG.getDbgValue(Variable, N.getNode(),
4644 N.getResNo(), Offset, dl, SDNodeOrder);
4645 DAG.AddDbgValue(SDV, N.getNode(), false);
4647 } else if (!V->use_empty() ) {
4648 // Do not call getValue(V) yet, as we don't want to generate code.
4649 // Remember it for later.
4650 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4651 DanglingDebugInfoMap[V] = DDI;
4653 // We may expand this to cover more cases. One case where we have no
4654 // data available is an unreferenced parameter.
4655 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4659 // Build a debug info table entry.
4660 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4661 V = BCI->getOperand(0);
4662 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4663 // Don't handle byval struct arguments or VLAs, for example.
4665 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4666 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4669 DenseMap<const AllocaInst*, int>::iterator SI =
4670 FuncInfo.StaticAllocaMap.find(AI);
4671 if (SI == FuncInfo.StaticAllocaMap.end())
4673 int FI = SI->second;
4675 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4676 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4677 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4681 case Intrinsic::eh_typeid_for: {
4682 // Find the type id for the given typeinfo.
4683 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4684 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4685 Res = DAG.getConstant(TypeID, MVT::i32);
4690 case Intrinsic::eh_return_i32:
4691 case Intrinsic::eh_return_i64:
4692 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4693 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4696 getValue(I.getArgOperand(0)),
4697 getValue(I.getArgOperand(1))));
4699 case Intrinsic::eh_unwind_init:
4700 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4702 case Intrinsic::eh_dwarf_cfa: {
4703 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4704 TLI->getPointerTy());
4705 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4706 TLI->getPointerTy(),
4707 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4708 TLI->getPointerTy()),
4710 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4711 TLI->getPointerTy(),
4712 DAG.getConstant(0, TLI->getPointerTy()));
4713 setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI->getPointerTy(),
4717 case Intrinsic::eh_sjlj_callsite: {
4718 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4719 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4720 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4721 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4723 MMI.setCurrentCallSite(CI->getZExtValue());
4726 case Intrinsic::eh_sjlj_functioncontext: {
4727 // Get and store the index of the function context.
4728 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4730 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4731 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4732 MFI->setFunctionContextIndex(FI);
4735 case Intrinsic::eh_sjlj_setjmp: {
4738 Ops[1] = getValue(I.getArgOperand(0));
4739 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4740 DAG.getVTList(MVT::i32, MVT::Other),
4742 setValue(&I, Op.getValue(0));
4743 DAG.setRoot(Op.getValue(1));
4746 case Intrinsic::eh_sjlj_longjmp: {
4747 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4748 getRoot(), getValue(I.getArgOperand(0))));
4752 case Intrinsic::x86_mmx_pslli_w:
4753 case Intrinsic::x86_mmx_pslli_d:
4754 case Intrinsic::x86_mmx_pslli_q:
4755 case Intrinsic::x86_mmx_psrli_w:
4756 case Intrinsic::x86_mmx_psrli_d:
4757 case Intrinsic::x86_mmx_psrli_q:
4758 case Intrinsic::x86_mmx_psrai_w:
4759 case Intrinsic::x86_mmx_psrai_d: {
4760 SDValue ShAmt = getValue(I.getArgOperand(1));
4761 if (isa<ConstantSDNode>(ShAmt)) {
4762 visitTargetIntrinsic(I, Intrinsic);
4765 unsigned NewIntrinsic = 0;
4766 EVT ShAmtVT = MVT::v2i32;
4767 switch (Intrinsic) {
4768 case Intrinsic::x86_mmx_pslli_w:
4769 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4771 case Intrinsic::x86_mmx_pslli_d:
4772 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4774 case Intrinsic::x86_mmx_pslli_q:
4775 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4777 case Intrinsic::x86_mmx_psrli_w:
4778 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4780 case Intrinsic::x86_mmx_psrli_d:
4781 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4783 case Intrinsic::x86_mmx_psrli_q:
4784 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4786 case Intrinsic::x86_mmx_psrai_w:
4787 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4789 case Intrinsic::x86_mmx_psrai_d:
4790 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4792 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4795 // The vector shift intrinsics with scalars uses 32b shift amounts but
4796 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4798 // We must do this early because v2i32 is not a legal type.
4801 ShOps[1] = DAG.getConstant(0, MVT::i32);
4802 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4803 EVT DestVT = TLI->getValueType(I.getType());
4804 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4805 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4806 DAG.getConstant(NewIntrinsic, MVT::i32),
4807 getValue(I.getArgOperand(0)), ShAmt);
4811 case Intrinsic::x86_avx_vinsertf128_pd_256:
4812 case Intrinsic::x86_avx_vinsertf128_ps_256:
4813 case Intrinsic::x86_avx_vinsertf128_si_256:
4814 case Intrinsic::x86_avx2_vinserti128: {
4815 EVT DestVT = TLI->getValueType(I.getType());
4816 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4817 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4818 ElVT.getVectorNumElements();
4819 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4820 getValue(I.getArgOperand(0)),
4821 getValue(I.getArgOperand(1)),
4822 DAG.getIntPtrConstant(Idx));
4826 case Intrinsic::x86_avx_vextractf128_pd_256:
4827 case Intrinsic::x86_avx_vextractf128_ps_256:
4828 case Intrinsic::x86_avx_vextractf128_si_256:
4829 case Intrinsic::x86_avx2_vextracti128: {
4830 EVT DestVT = TLI->getValueType(I.getType());
4831 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4832 DestVT.getVectorNumElements();
4833 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
4834 getValue(I.getArgOperand(0)),
4835 DAG.getIntPtrConstant(Idx));
4839 case Intrinsic::convertff:
4840 case Intrinsic::convertfsi:
4841 case Intrinsic::convertfui:
4842 case Intrinsic::convertsif:
4843 case Intrinsic::convertuif:
4844 case Intrinsic::convertss:
4845 case Intrinsic::convertsu:
4846 case Intrinsic::convertus:
4847 case Intrinsic::convertuu: {
4848 ISD::CvtCode Code = ISD::CVT_INVALID;
4849 switch (Intrinsic) {
4850 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4851 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4852 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4853 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4854 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4855 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4856 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4857 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4858 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4859 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4861 EVT DestVT = TLI->getValueType(I.getType());
4862 const Value *Op1 = I.getArgOperand(0);
4863 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4864 DAG.getValueType(DestVT),
4865 DAG.getValueType(getValue(Op1).getValueType()),
4866 getValue(I.getArgOperand(1)),
4867 getValue(I.getArgOperand(2)),
4872 case Intrinsic::powi:
4873 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4874 getValue(I.getArgOperand(1)), DAG));
4876 case Intrinsic::log:
4877 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4879 case Intrinsic::log2:
4880 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4882 case Intrinsic::log10:
4883 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4885 case Intrinsic::exp:
4886 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4888 case Intrinsic::exp2:
4889 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4891 case Intrinsic::pow:
4892 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4893 getValue(I.getArgOperand(1)), DAG, *TLI));
4895 case Intrinsic::sqrt:
4896 case Intrinsic::fabs:
4897 case Intrinsic::sin:
4898 case Intrinsic::cos:
4899 case Intrinsic::floor:
4900 case Intrinsic::ceil:
4901 case Intrinsic::trunc:
4902 case Intrinsic::rint:
4903 case Intrinsic::nearbyint: {
4905 switch (Intrinsic) {
4906 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4907 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4908 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4909 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4910 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4911 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4912 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4913 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4914 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4915 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4918 setValue(&I, DAG.getNode(Opcode, sdl,
4919 getValue(I.getArgOperand(0)).getValueType(),
4920 getValue(I.getArgOperand(0))));
4923 case Intrinsic::fma:
4924 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4925 getValue(I.getArgOperand(0)).getValueType(),
4926 getValue(I.getArgOperand(0)),
4927 getValue(I.getArgOperand(1)),
4928 getValue(I.getArgOperand(2))));
4930 case Intrinsic::fmuladd: {
4931 EVT VT = TLI->getValueType(I.getType());
4932 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4933 TLI->isFMAFasterThanMulAndAdd(VT)){
4934 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4935 getValue(I.getArgOperand(0)).getValueType(),
4936 getValue(I.getArgOperand(0)),
4937 getValue(I.getArgOperand(1)),
4938 getValue(I.getArgOperand(2))));
4940 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4941 getValue(I.getArgOperand(0)).getValueType(),
4942 getValue(I.getArgOperand(0)),
4943 getValue(I.getArgOperand(1)));
4944 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4945 getValue(I.getArgOperand(0)).getValueType(),
4947 getValue(I.getArgOperand(2)));
4952 case Intrinsic::convert_to_fp16:
4953 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
4954 MVT::i16, getValue(I.getArgOperand(0))));
4956 case Intrinsic::convert_from_fp16:
4957 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
4958 MVT::f32, getValue(I.getArgOperand(0))));
4960 case Intrinsic::pcmarker: {
4961 SDValue Tmp = getValue(I.getArgOperand(0));
4962 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4965 case Intrinsic::readcyclecounter: {
4966 SDValue Op = getRoot();
4967 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4968 DAG.getVTList(MVT::i64, MVT::Other),
4971 DAG.setRoot(Res.getValue(1));
4974 case Intrinsic::bswap:
4975 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4976 getValue(I.getArgOperand(0)).getValueType(),
4977 getValue(I.getArgOperand(0))));
4979 case Intrinsic::cttz: {
4980 SDValue Arg = getValue(I.getArgOperand(0));
4981 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4982 EVT Ty = Arg.getValueType();
4983 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4987 case Intrinsic::ctlz: {
4988 SDValue Arg = getValue(I.getArgOperand(0));
4989 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4990 EVT Ty = Arg.getValueType();
4991 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4995 case Intrinsic::ctpop: {
4996 SDValue Arg = getValue(I.getArgOperand(0));
4997 EVT Ty = Arg.getValueType();
4998 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5001 case Intrinsic::stacksave: {
5002 SDValue Op = getRoot();
5003 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5004 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5006 DAG.setRoot(Res.getValue(1));
5009 case Intrinsic::stackrestore: {
5010 Res = getValue(I.getArgOperand(0));
5011 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5014 case Intrinsic::stackprotector: {
5015 // Emit code into the DAG to store the stack guard onto the stack.
5016 MachineFunction &MF = DAG.getMachineFunction();
5017 MachineFrameInfo *MFI = MF.getFrameInfo();
5018 EVT PtrTy = TLI->getPointerTy();
5020 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5021 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5023 int FI = FuncInfo.StaticAllocaMap[Slot];
5024 MFI->setStackProtectorIndex(FI);
5026 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5028 // Store the stack protector onto the stack.
5029 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5030 MachinePointerInfo::getFixedStack(FI),
5036 case Intrinsic::objectsize: {
5037 // If we don't know by now, we're never going to know.
5038 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5040 assert(CI && "Non-constant type in __builtin_object_size?");
5042 SDValue Arg = getValue(I.getCalledValue());
5043 EVT Ty = Arg.getValueType();
5046 Res = DAG.getConstant(-1ULL, Ty);
5048 Res = DAG.getConstant(0, Ty);
5053 case Intrinsic::annotation:
5054 case Intrinsic::ptr_annotation:
5055 // Drop the intrinsic, but forward the value
5056 setValue(&I, getValue(I.getOperand(0)));
5058 case Intrinsic::var_annotation:
5059 // Discard annotate attributes
5062 case Intrinsic::init_trampoline: {
5063 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5067 Ops[1] = getValue(I.getArgOperand(0));
5068 Ops[2] = getValue(I.getArgOperand(1));
5069 Ops[3] = getValue(I.getArgOperand(2));
5070 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5071 Ops[5] = DAG.getSrcValue(F);
5073 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5078 case Intrinsic::adjust_trampoline: {
5079 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5080 TLI->getPointerTy(),
5081 getValue(I.getArgOperand(0))));
5084 case Intrinsic::gcroot:
5086 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5087 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5089 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5090 GFI->addStackRoot(FI->getIndex(), TypeMap);
5093 case Intrinsic::gcread:
5094 case Intrinsic::gcwrite:
5095 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5096 case Intrinsic::flt_rounds:
5097 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5100 case Intrinsic::expect: {
5101 // Just replace __builtin_expect(exp, c) with EXP.
5102 setValue(&I, getValue(I.getArgOperand(0)));
5106 case Intrinsic::debugtrap:
5107 case Intrinsic::trap: {
5108 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5109 if (TrapFuncName.empty()) {
5110 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5111 ISD::TRAP : ISD::DEBUGTRAP;
5112 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5115 TargetLowering::ArgListTy Args;
5117 CallLoweringInfo CLI(getRoot(), I.getType(),
5118 false, false, false, false, 0, CallingConv::C,
5119 /*isTailCall=*/false,
5120 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5121 DAG.getExternalSymbol(TrapFuncName.data(),
5122 TLI->getPointerTy()),
5124 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5125 DAG.setRoot(Result.second);
5129 case Intrinsic::uadd_with_overflow:
5130 case Intrinsic::sadd_with_overflow:
5131 case Intrinsic::usub_with_overflow:
5132 case Intrinsic::ssub_with_overflow:
5133 case Intrinsic::umul_with_overflow:
5134 case Intrinsic::smul_with_overflow: {
5136 switch (Intrinsic) {
5137 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5138 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5139 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5140 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5141 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5142 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5143 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5145 SDValue Op1 = getValue(I.getArgOperand(0));
5146 SDValue Op2 = getValue(I.getArgOperand(1));
5148 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5149 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5152 case Intrinsic::prefetch: {
5154 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5156 Ops[1] = getValue(I.getArgOperand(0));
5157 Ops[2] = getValue(I.getArgOperand(1));
5158 Ops[3] = getValue(I.getArgOperand(2));
5159 Ops[4] = getValue(I.getArgOperand(3));
5160 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5161 DAG.getVTList(MVT::Other),
5163 EVT::getIntegerVT(*Context, 8),
5164 MachinePointerInfo(I.getArgOperand(0)),
5166 false, /* volatile */
5168 rw==1)); /* write */
5171 case Intrinsic::lifetime_start:
5172 case Intrinsic::lifetime_end: {
5173 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5174 // Stack coloring is not enabled in O0, discard region information.
5175 if (TM.getOptLevel() == CodeGenOpt::None)
5178 SmallVector<Value *, 4> Allocas;
5179 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5181 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5182 E = Allocas.end(); Object != E; ++Object) {
5183 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5185 // Could not find an Alloca.
5186 if (!LifetimeObject)
5189 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5193 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5194 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5196 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5201 case Intrinsic::invariant_start:
5202 // Discard region information.
5203 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5205 case Intrinsic::invariant_end:
5206 // Discard region information.
5208 case Intrinsic::donothing:
5214 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5216 MachineBasicBlock *LandingPad) {
5217 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5218 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5219 Type *RetTy = FTy->getReturnType();
5220 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5221 MCSymbol *BeginLabel = 0;
5223 TargetLowering::ArgListTy Args;
5224 TargetLowering::ArgListEntry Entry;
5225 Args.reserve(CS.arg_size());
5227 // Check whether the function can return without sret-demotion.
5228 SmallVector<ISD::OutputArg, 4> Outs;
5229 const TargetLowering *TLI = TM.getTargetLowering();
5230 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5232 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5233 DAG.getMachineFunction(),
5234 FTy->isVarArg(), Outs,
5237 SDValue DemoteStackSlot;
5238 int DemoteStackIdx = -100;
5240 if (!CanLowerReturn) {
5241 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5242 FTy->getReturnType());
5243 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5244 FTy->getReturnType());
5245 MachineFunction &MF = DAG.getMachineFunction();
5246 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5247 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5249 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5250 Entry.Node = DemoteStackSlot;
5251 Entry.Ty = StackSlotPtrType;
5252 Entry.isSExt = false;
5253 Entry.isZExt = false;
5254 Entry.isInReg = false;
5255 Entry.isSRet = true;
5256 Entry.isNest = false;
5257 Entry.isByVal = false;
5258 Entry.isReturned = false;
5259 Entry.Alignment = Align;
5260 Args.push_back(Entry);
5261 RetTy = Type::getVoidTy(FTy->getContext());
5264 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5266 const Value *V = *i;
5269 if (V->getType()->isEmptyTy())
5272 SDValue ArgNode = getValue(V);
5273 Entry.Node = ArgNode; Entry.Ty = V->getType();
5275 unsigned attrInd = i - CS.arg_begin() + 1;
5276 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5277 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5278 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5279 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5280 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5281 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5282 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned);
5283 Entry.Alignment = CS.getParamAlignment(attrInd);
5284 Args.push_back(Entry);
5288 // Insert a label before the invoke call to mark the try range. This can be
5289 // used to detect deletion of the invoke via the MachineModuleInfo.
5290 BeginLabel = MMI.getContext().CreateTempSymbol();
5292 // For SjLj, keep track of which landing pads go with which invokes
5293 // so as to maintain the ordering of pads in the LSDA.
5294 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5295 if (CallSiteIndex) {
5296 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5297 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5299 // Now that the call site is handled, stop tracking it.
5300 MMI.setCurrentCallSite(0);
5303 // Both PendingLoads and PendingExports must be flushed here;
5304 // this call might not return.
5306 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5309 // Check if target-independent constraints permit a tail call here.
5310 // Target-dependent constraints are checked within TLI->LowerCallTo.
5311 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5315 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5317 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5318 assert((isTailCall || Result.second.getNode()) &&
5319 "Non-null chain expected with non-tail call!");
5320 assert((Result.second.getNode() || !Result.first.getNode()) &&
5321 "Null value expected with tail call!");
5322 if (Result.first.getNode()) {
5323 setValue(CS.getInstruction(), Result.first);
5324 } else if (!CanLowerReturn && Result.second.getNode()) {
5325 // The instruction result is the result of loading from the
5326 // hidden sret parameter.
5327 SmallVector<EVT, 1> PVTs;
5328 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5330 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5331 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5332 EVT PtrVT = PVTs[0];
5334 SmallVector<EVT, 4> RetTys;
5335 SmallVector<uint64_t, 4> Offsets;
5336 RetTy = FTy->getReturnType();
5337 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5339 unsigned NumValues = RetTys.size();
5340 SmallVector<SDValue, 4> Values(NumValues);
5341 SmallVector<SDValue, 4> Chains(NumValues);
5343 for (unsigned i = 0; i < NumValues; ++i) {
5344 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5346 DAG.getConstant(Offsets[i], PtrVT));
5347 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5348 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5349 false, false, false, 1);
5351 Chains[i] = L.getValue(1);
5354 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5355 MVT::Other, &Chains[0], NumValues);
5356 PendingLoads.push_back(Chain);
5358 setValue(CS.getInstruction(),
5359 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5360 DAG.getVTList(&RetTys[0], RetTys.size()),
5361 &Values[0], Values.size()));
5364 if (!Result.second.getNode()) {
5365 // As a special case, a null chain means that a tail call has been emitted and
5366 // the DAG root is already updated.
5369 DAG.setRoot(Result.second);
5373 // Insert a label at the end of the invoke call to mark the try range. This
5374 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5375 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5376 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5378 // Inform MachineModuleInfo of range.
5379 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5383 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5384 /// value is equal or not-equal to zero.
5385 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5386 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5388 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5389 if (IC->isEquality())
5390 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5391 if (C->isNullValue())
5393 // Unknown instruction.
5399 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5401 SelectionDAGBuilder &Builder) {
5403 // Check to see if this load can be trivially constant folded, e.g. if the
5404 // input is from a string literal.
5405 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5406 // Cast pointer to the type we really want to load.
5407 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5408 PointerType::getUnqual(LoadTy));
5410 if (const Constant *LoadCst =
5411 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5413 return Builder.getValue(LoadCst);
5416 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5417 // still constant memory, the input chain can be the entry node.
5419 bool ConstantMemory = false;
5421 // Do not serialize (non-volatile) loads of constant memory with anything.
5422 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5423 Root = Builder.DAG.getEntryNode();
5424 ConstantMemory = true;
5426 // Do not serialize non-volatile loads against each other.
5427 Root = Builder.DAG.getRoot();
5430 SDValue Ptr = Builder.getValue(PtrVal);
5431 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5432 Ptr, MachinePointerInfo(PtrVal),
5434 false /*nontemporal*/,
5435 false /*isinvariant*/, 1 /* align=1 */);
5437 if (!ConstantMemory)
5438 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5443 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5444 /// If so, return true and lower it, otherwise return false and it will be
5445 /// lowered like a normal call.
5446 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5447 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5448 if (I.getNumArgOperands() != 3)
5451 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5452 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5453 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5454 !I.getType()->isIntegerTy())
5457 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5459 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5460 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5461 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5462 bool ActuallyDoIt = true;
5465 switch (Size->getZExtValue()) {
5467 LoadVT = MVT::Other;
5469 ActuallyDoIt = false;
5473 LoadTy = Type::getInt16Ty(Size->getContext());
5477 LoadTy = Type::getInt32Ty(Size->getContext());
5481 LoadTy = Type::getInt64Ty(Size->getContext());
5485 LoadVT = MVT::v4i32;
5486 LoadTy = Type::getInt32Ty(Size->getContext());
5487 LoadTy = VectorType::get(LoadTy, 4);
5492 // This turns into unaligned loads. We only do this if the target natively
5493 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5494 // we'll only produce a small number of byte loads.
5496 // Require that we can find a legal MVT, and only do this if the target
5497 // supports unaligned loads of that type. Expanding into byte loads would
5499 const TargetLowering *TLI = TM.getTargetLowering();
5500 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5501 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5502 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5503 if (!TLI->isTypeLegal(LoadVT) ||!TLI->allowsUnalignedMemoryAccesses(LoadVT))
5504 ActuallyDoIt = false;
5508 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5509 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5511 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5513 EVT CallVT = TLI->getValueType(I.getType(), true);
5514 setValue(&I, DAG.getZExtOrTrunc(Res, getCurSDLoc(), CallVT));
5523 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5524 /// operation (as expected), translate it to an SDNode with the specified opcode
5525 /// and return true.
5526 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5528 // Sanity check that it really is a unary floating-point call.
5529 if (I.getNumArgOperands() != 1 ||
5530 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5531 I.getType() != I.getArgOperand(0)->getType() ||
5532 !I.onlyReadsMemory())
5535 SDValue Tmp = getValue(I.getArgOperand(0));
5536 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5540 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5541 // Handle inline assembly differently.
5542 if (isa<InlineAsm>(I.getCalledValue())) {
5547 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5548 ComputeUsesVAFloatArgument(I, &MMI);
5550 const char *RenameFn = 0;
5551 if (Function *F = I.getCalledFunction()) {
5552 if (F->isDeclaration()) {
5553 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5554 if (unsigned IID = II->getIntrinsicID(F)) {
5555 RenameFn = visitIntrinsicCall(I, IID);
5560 if (unsigned IID = F->getIntrinsicID()) {
5561 RenameFn = visitIntrinsicCall(I, IID);
5567 // Check for well-known libc/libm calls. If the function is internal, it
5568 // can't be a library call.
5570 if (!F->hasLocalLinkage() && F->hasName() &&
5571 LibInfo->getLibFunc(F->getName(), Func) &&
5572 LibInfo->hasOptimizedCodeGen(Func)) {
5575 case LibFunc::copysign:
5576 case LibFunc::copysignf:
5577 case LibFunc::copysignl:
5578 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5579 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5580 I.getType() == I.getArgOperand(0)->getType() &&
5581 I.getType() == I.getArgOperand(1)->getType() &&
5582 I.onlyReadsMemory()) {
5583 SDValue LHS = getValue(I.getArgOperand(0));
5584 SDValue RHS = getValue(I.getArgOperand(1));
5585 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5586 LHS.getValueType(), LHS, RHS));
5591 case LibFunc::fabsf:
5592 case LibFunc::fabsl:
5593 if (visitUnaryFloatCall(I, ISD::FABS))
5599 if (visitUnaryFloatCall(I, ISD::FSIN))
5605 if (visitUnaryFloatCall(I, ISD::FCOS))
5609 case LibFunc::sqrtf:
5610 case LibFunc::sqrtl:
5611 case LibFunc::sqrt_finite:
5612 case LibFunc::sqrtf_finite:
5613 case LibFunc::sqrtl_finite:
5614 if (visitUnaryFloatCall(I, ISD::FSQRT))
5617 case LibFunc::floor:
5618 case LibFunc::floorf:
5619 case LibFunc::floorl:
5620 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5623 case LibFunc::nearbyint:
5624 case LibFunc::nearbyintf:
5625 case LibFunc::nearbyintl:
5626 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5630 case LibFunc::ceilf:
5631 case LibFunc::ceill:
5632 if (visitUnaryFloatCall(I, ISD::FCEIL))
5636 case LibFunc::rintf:
5637 case LibFunc::rintl:
5638 if (visitUnaryFloatCall(I, ISD::FRINT))
5641 case LibFunc::trunc:
5642 case LibFunc::truncf:
5643 case LibFunc::truncl:
5644 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5648 case LibFunc::log2f:
5649 case LibFunc::log2l:
5650 if (visitUnaryFloatCall(I, ISD::FLOG2))
5654 case LibFunc::exp2f:
5655 case LibFunc::exp2l:
5656 if (visitUnaryFloatCall(I, ISD::FEXP2))
5659 case LibFunc::memcmp:
5660 if (visitMemCmpCall(I))
5669 Callee = getValue(I.getCalledValue());
5671 Callee = DAG.getExternalSymbol(RenameFn,
5672 TM.getTargetLowering()->getPointerTy());
5674 // Check if we can potentially perform a tail call. More detailed checking is
5675 // be done within LowerCallTo, after more information about the call is known.
5676 LowerCallTo(&I, Callee, I.isTailCall());
5681 /// AsmOperandInfo - This contains information for each constraint that we are
5683 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5685 /// CallOperand - If this is the result output operand or a clobber
5686 /// this is null, otherwise it is the incoming operand to the CallInst.
5687 /// This gets modified as the asm is processed.
5688 SDValue CallOperand;
5690 /// AssignedRegs - If this is a register or register class operand, this
5691 /// contains the set of register corresponding to the operand.
5692 RegsForValue AssignedRegs;
5694 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5695 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5698 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5699 /// corresponds to. If there is no Value* for this operand, it returns
5701 EVT getCallOperandValEVT(LLVMContext &Context,
5702 const TargetLowering &TLI,
5703 const DataLayout *TD) const {
5704 if (CallOperandVal == 0) return MVT::Other;
5706 if (isa<BasicBlock>(CallOperandVal))
5707 return TLI.getPointerTy();
5709 llvm::Type *OpTy = CallOperandVal->getType();
5711 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5712 // If this is an indirect operand, the operand is a pointer to the
5715 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5717 report_fatal_error("Indirect operand for inline asm not a pointer!");
5718 OpTy = PtrTy->getElementType();
5721 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5722 if (StructType *STy = dyn_cast<StructType>(OpTy))
5723 if (STy->getNumElements() == 1)
5724 OpTy = STy->getElementType(0);
5726 // If OpTy is not a single value, it may be a struct/union that we
5727 // can tile with integers.
5728 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5729 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5738 OpTy = IntegerType::get(Context, BitSize);
5743 return TLI.getValueType(OpTy, true);
5747 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5749 } // end anonymous namespace
5751 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5752 /// specified operand. We prefer to assign virtual registers, to allow the
5753 /// register allocator to handle the assignment process. However, if the asm
5754 /// uses features that we can't model on machineinstrs, we have SDISel do the
5755 /// allocation. This produces generally horrible, but correct, code.
5757 /// OpInfo describes the operand.
5759 static void GetRegistersForValue(SelectionDAG &DAG,
5760 const TargetLowering &TLI,
5762 SDISelAsmOperandInfo &OpInfo) {
5763 LLVMContext &Context = *DAG.getContext();
5765 MachineFunction &MF = DAG.getMachineFunction();
5766 SmallVector<unsigned, 4> Regs;
5768 // If this is a constraint for a single physreg, or a constraint for a
5769 // register class, find it.
5770 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5771 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5772 OpInfo.ConstraintVT);
5774 unsigned NumRegs = 1;
5775 if (OpInfo.ConstraintVT != MVT::Other) {
5776 // If this is a FP input in an integer register (or visa versa) insert a bit
5777 // cast of the input value. More generally, handle any case where the input
5778 // value disagrees with the register class we plan to stick this in.
5779 if (OpInfo.Type == InlineAsm::isInput &&
5780 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5781 // Try to convert to the first EVT that the reg class contains. If the
5782 // types are identical size, use a bitcast to convert (e.g. two differing
5784 MVT RegVT = *PhysReg.second->vt_begin();
5785 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5786 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5787 RegVT, OpInfo.CallOperand);
5788 OpInfo.ConstraintVT = RegVT;
5789 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5790 // If the input is a FP value and we want it in FP registers, do a
5791 // bitcast to the corresponding integer type. This turns an f64 value
5792 // into i64, which can be passed with two i32 values on a 32-bit
5794 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5795 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5796 RegVT, OpInfo.CallOperand);
5797 OpInfo.ConstraintVT = RegVT;
5801 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5805 EVT ValueVT = OpInfo.ConstraintVT;
5807 // If this is a constraint for a specific physical register, like {r17},
5809 if (unsigned AssignedReg = PhysReg.first) {
5810 const TargetRegisterClass *RC = PhysReg.second;
5811 if (OpInfo.ConstraintVT == MVT::Other)
5812 ValueVT = *RC->vt_begin();
5814 // Get the actual register value type. This is important, because the user
5815 // may have asked for (e.g.) the AX register in i32 type. We need to
5816 // remember that AX is actually i16 to get the right extension.
5817 RegVT = *RC->vt_begin();
5819 // This is a explicit reference to a physical register.
5820 Regs.push_back(AssignedReg);
5822 // If this is an expanded reference, add the rest of the regs to Regs.
5824 TargetRegisterClass::iterator I = RC->begin();
5825 for (; *I != AssignedReg; ++I)
5826 assert(I != RC->end() && "Didn't find reg!");
5828 // Already added the first reg.
5830 for (; NumRegs; --NumRegs, ++I) {
5831 assert(I != RC->end() && "Ran out of registers to allocate!");
5836 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5840 // Otherwise, if this was a reference to an LLVM register class, create vregs
5841 // for this reference.
5842 if (const TargetRegisterClass *RC = PhysReg.second) {
5843 RegVT = *RC->vt_begin();
5844 if (OpInfo.ConstraintVT == MVT::Other)
5847 // Create the appropriate number of virtual registers.
5848 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5849 for (; NumRegs; --NumRegs)
5850 Regs.push_back(RegInfo.createVirtualRegister(RC));
5852 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5856 // Otherwise, we couldn't allocate enough registers for this.
5859 /// visitInlineAsm - Handle a call to an InlineAsm object.
5861 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5862 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5864 /// ConstraintOperands - Information about all of the constraints.
5865 SDISelAsmOperandInfoVector ConstraintOperands;
5867 const TargetLowering *TLI = TM.getTargetLowering();
5868 TargetLowering::AsmOperandInfoVector
5869 TargetConstraints = TLI->ParseConstraints(CS);
5871 bool hasMemory = false;
5873 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5874 unsigned ResNo = 0; // ResNo - The result number of the next output.
5875 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5876 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5877 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5879 MVT OpVT = MVT::Other;
5881 // Compute the value type for each operand.
5882 switch (OpInfo.Type) {
5883 case InlineAsm::isOutput:
5884 // Indirect outputs just consume an argument.
5885 if (OpInfo.isIndirect) {
5886 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5890 // The return value of the call is this value. As such, there is no
5891 // corresponding argument.
5892 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5893 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5894 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
5896 assert(ResNo == 0 && "Asm only has one result!");
5897 OpVT = TLI->getSimpleValueType(CS.getType());
5901 case InlineAsm::isInput:
5902 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5904 case InlineAsm::isClobber:
5909 // If this is an input or an indirect output, process the call argument.
5910 // BasicBlocks are labels, currently appearing only in asm's.
5911 if (OpInfo.CallOperandVal) {
5912 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5913 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5915 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5918 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD).
5922 OpInfo.ConstraintVT = OpVT;
5924 // Indirect operand accesses access memory.
5925 if (OpInfo.isIndirect)
5928 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5929 TargetLowering::ConstraintType
5930 CType = TLI->getConstraintType(OpInfo.Codes[j]);
5931 if (CType == TargetLowering::C_Memory) {
5939 SDValue Chain, Flag;
5941 // We won't need to flush pending loads if this asm doesn't touch
5942 // memory and is nonvolatile.
5943 if (hasMemory || IA->hasSideEffects())
5946 Chain = DAG.getRoot();
5948 // Second pass over the constraints: compute which constraint option to use
5949 // and assign registers to constraints that want a specific physreg.
5950 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5951 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5953 // If this is an output operand with a matching input operand, look up the
5954 // matching input. If their types mismatch, e.g. one is an integer, the
5955 // other is floating point, or their sizes are different, flag it as an
5957 if (OpInfo.hasMatchingInput()) {
5958 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5960 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5961 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5962 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5963 OpInfo.ConstraintVT);
5964 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5965 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
5966 Input.ConstraintVT);
5967 if ((OpInfo.ConstraintVT.isInteger() !=
5968 Input.ConstraintVT.isInteger()) ||
5969 (MatchRC.second != InputRC.second)) {
5970 report_fatal_error("Unsupported asm: input constraint"
5971 " with a matching output constraint of"
5972 " incompatible type!");
5974 Input.ConstraintVT = OpInfo.ConstraintVT;
5978 // Compute the constraint code and ConstraintType to use.
5979 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5981 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5982 OpInfo.Type == InlineAsm::isClobber)
5985 // If this is a memory input, and if the operand is not indirect, do what we
5986 // need to to provide an address for the memory input.
5987 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5988 !OpInfo.isIndirect) {
5989 assert((OpInfo.isMultipleAlternative ||
5990 (OpInfo.Type == InlineAsm::isInput)) &&
5991 "Can only indirectify direct input operands!");
5993 // Memory operands really want the address of the value. If we don't have
5994 // an indirect input, put it in the constpool if we can, otherwise spill
5995 // it to a stack slot.
5996 // TODO: This isn't quite right. We need to handle these according to
5997 // the addressing mode that the constraint wants. Also, this may take
5998 // an additional register for the computation and we don't want that
6001 // If the operand is a float, integer, or vector constant, spill to a
6002 // constant pool entry to get its address.
6003 const Value *OpVal = OpInfo.CallOperandVal;
6004 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6005 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6006 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6007 TLI->getPointerTy());
6009 // Otherwise, create a stack slot and emit a store to it before the
6011 Type *Ty = OpVal->getType();
6012 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6013 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6014 MachineFunction &MF = DAG.getMachineFunction();
6015 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6016 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6017 Chain = DAG.getStore(Chain, getCurSDLoc(),
6018 OpInfo.CallOperand, StackSlot,
6019 MachinePointerInfo::getFixedStack(SSFI),
6021 OpInfo.CallOperand = StackSlot;
6024 // There is no longer a Value* corresponding to this operand.
6025 OpInfo.CallOperandVal = 0;
6027 // It is now an indirect operand.
6028 OpInfo.isIndirect = true;
6031 // If this constraint is for a specific register, allocate it before
6033 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6034 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6037 // Second pass - Loop over all of the operands, assigning virtual or physregs
6038 // to register class operands.
6039 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6040 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6042 // C_Register operands have already been allocated, Other/Memory don't need
6044 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6045 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6048 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6049 std::vector<SDValue> AsmNodeOperands;
6050 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6051 AsmNodeOperands.push_back(
6052 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6053 TLI->getPointerTy()));
6055 // If we have a !srcloc metadata node associated with it, we want to attach
6056 // this to the ultimately generated inline asm machineinstr. To do this, we
6057 // pass in the third operand as this (potentially null) inline asm MDNode.
6058 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6059 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6061 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6062 // bits as operand 3.
6063 unsigned ExtraInfo = 0;
6064 if (IA->hasSideEffects())
6065 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6066 if (IA->isAlignStack())
6067 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6068 // Set the asm dialect.
6069 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6071 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6072 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6073 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6075 // Compute the constraint code and ConstraintType to use.
6076 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6078 // Ideally, we would only check against memory constraints. However, the
6079 // meaning of an other constraint can be target-specific and we can't easily
6080 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6081 // for other constriants as well.
6082 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6083 OpInfo.ConstraintType == TargetLowering::C_Other) {
6084 if (OpInfo.Type == InlineAsm::isInput)
6085 ExtraInfo |= InlineAsm::Extra_MayLoad;
6086 else if (OpInfo.Type == InlineAsm::isOutput)
6087 ExtraInfo |= InlineAsm::Extra_MayStore;
6088 else if (OpInfo.Type == InlineAsm::isClobber)
6089 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6093 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6094 TLI->getPointerTy()));
6096 // Loop over all of the inputs, copying the operand values into the
6097 // appropriate registers and processing the output regs.
6098 RegsForValue RetValRegs;
6100 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6101 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6103 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6104 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6106 switch (OpInfo.Type) {
6107 case InlineAsm::isOutput: {
6108 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6109 OpInfo.ConstraintType != TargetLowering::C_Register) {
6110 // Memory output, or 'other' output (e.g. 'X' constraint).
6111 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6113 // Add information to the INLINEASM node to know about this output.
6114 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6115 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6116 TLI->getPointerTy()));
6117 AsmNodeOperands.push_back(OpInfo.CallOperand);
6121 // Otherwise, this is a register or register class output.
6123 // Copy the output from the appropriate register. Find a register that
6125 if (OpInfo.AssignedRegs.Regs.empty()) {
6126 LLVMContext &Ctx = *DAG.getContext();
6127 Ctx.emitError(CS.getInstruction(),
6128 "couldn't allocate output register for constraint '" +
6129 Twine(OpInfo.ConstraintCode) + "'");
6133 // If this is an indirect operand, store through the pointer after the
6135 if (OpInfo.isIndirect) {
6136 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6137 OpInfo.CallOperandVal));
6139 // This is the result value of the call.
6140 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6141 // Concatenate this output onto the outputs list.
6142 RetValRegs.append(OpInfo.AssignedRegs);
6145 // Add information to the INLINEASM node to know that this register is
6147 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6148 InlineAsm::Kind_RegDefEarlyClobber :
6149 InlineAsm::Kind_RegDef,
6156 case InlineAsm::isInput: {
6157 SDValue InOperandVal = OpInfo.CallOperand;
6159 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6160 // If this is required to match an output register we have already set,
6161 // just use its register.
6162 unsigned OperandNo = OpInfo.getMatchedOperand();
6164 // Scan until we find the definition we already emitted of this operand.
6165 // When we find it, create a RegsForValue operand.
6166 unsigned CurOp = InlineAsm::Op_FirstOperand;
6167 for (; OperandNo; --OperandNo) {
6168 // Advance to the next operand.
6170 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6171 assert((InlineAsm::isRegDefKind(OpFlag) ||
6172 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6173 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6174 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6178 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6179 if (InlineAsm::isRegDefKind(OpFlag) ||
6180 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6181 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6182 if (OpInfo.isIndirect) {
6183 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6184 LLVMContext &Ctx = *DAG.getContext();
6185 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6186 " don't know how to handle tied "
6187 "indirect register inputs");
6188 report_fatal_error("Cannot handle indirect register inputs!");
6191 RegsForValue MatchedRegs;
6192 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6193 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6194 MatchedRegs.RegVTs.push_back(RegVT);
6195 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6196 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6198 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6199 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6201 LLVMContext &Ctx = *DAG.getContext();
6202 Ctx.emitError(CS.getInstruction(), "inline asm error: This value"
6203 " type register class is not natively supported!");
6204 report_fatal_error("inline asm error: This value type register "
6205 "class is not natively supported!");
6208 // Use the produced MatchedRegs object to
6209 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6210 Chain, &Flag, CS.getInstruction());
6211 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6212 true, OpInfo.getMatchedOperand(),
6213 DAG, AsmNodeOperands);
6217 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6218 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6219 "Unexpected number of operands");
6220 // Add information to the INLINEASM node to know about this input.
6221 // See InlineAsm.h isUseOperandTiedToDef.
6222 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6223 OpInfo.getMatchedOperand());
6224 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6225 TLI->getPointerTy()));
6226 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6230 // Treat indirect 'X' constraint as memory.
6231 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6233 OpInfo.ConstraintType = TargetLowering::C_Memory;
6235 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6236 std::vector<SDValue> Ops;
6237 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6240 LLVMContext &Ctx = *DAG.getContext();
6241 Ctx.emitError(CS.getInstruction(),
6242 "invalid operand for inline asm constraint '" +
6243 Twine(OpInfo.ConstraintCode) + "'");
6247 // Add information to the INLINEASM node to know about this input.
6248 unsigned ResOpType =
6249 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6250 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6251 TLI->getPointerTy()));
6252 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6256 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6257 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6258 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6259 "Memory operands expect pointer values");
6261 // Add information to the INLINEASM node to know about this input.
6262 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6263 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6264 TLI->getPointerTy()));
6265 AsmNodeOperands.push_back(InOperandVal);
6269 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6270 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6271 "Unknown constraint type!");
6273 // TODO: Support this.
6274 if (OpInfo.isIndirect) {
6275 LLVMContext &Ctx = *DAG.getContext();
6276 Ctx.emitError(CS.getInstruction(),
6277 "Don't know how to handle indirect register inputs yet "
6278 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6282 // Copy the input into the appropriate registers.
6283 if (OpInfo.AssignedRegs.Regs.empty()) {
6284 LLVMContext &Ctx = *DAG.getContext();
6285 Ctx.emitError(CS.getInstruction(),
6286 "couldn't allocate input reg for constraint '" +
6287 Twine(OpInfo.ConstraintCode) + "'");
6291 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6292 Chain, &Flag, CS.getInstruction());
6294 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6295 DAG, AsmNodeOperands);
6298 case InlineAsm::isClobber: {
6299 // Add the clobbered value to the operand list, so that the register
6300 // allocator is aware that the physreg got clobbered.
6301 if (!OpInfo.AssignedRegs.Regs.empty())
6302 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6310 // Finish up input operands. Set the input chain and add the flag last.
6311 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6312 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6314 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6315 DAG.getVTList(MVT::Other, MVT::Glue),
6316 &AsmNodeOperands[0], AsmNodeOperands.size());
6317 Flag = Chain.getValue(1);
6319 // If this asm returns a register value, copy the result from that register
6320 // and set it as the value of the call.
6321 if (!RetValRegs.Regs.empty()) {
6322 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6323 Chain, &Flag, CS.getInstruction());
6325 // FIXME: Why don't we do this for inline asms with MRVs?
6326 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6327 EVT ResultType = TLI->getValueType(CS.getType());
6329 // If any of the results of the inline asm is a vector, it may have the
6330 // wrong width/num elts. This can happen for register classes that can
6331 // contain multiple different value types. The preg or vreg allocated may
6332 // not have the same VT as was expected. Convert it to the right type
6333 // with bit_convert.
6334 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6335 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6338 } else if (ResultType != Val.getValueType() &&
6339 ResultType.isInteger() && Val.getValueType().isInteger()) {
6340 // If a result value was tied to an input value, the computed result may
6341 // have a wider width than the expected result. Extract the relevant
6343 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6346 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6349 setValue(CS.getInstruction(), Val);
6350 // Don't need to use this as a chain in this case.
6351 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6355 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6357 // Process indirect outputs, first output all of the flagged copies out of
6359 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6360 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6361 const Value *Ptr = IndirectStoresToEmit[i].second;
6362 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6364 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6367 // Emit the non-flagged stores from the physregs.
6368 SmallVector<SDValue, 8> OutChains;
6369 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6370 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6371 StoresToEmit[i].first,
6372 getValue(StoresToEmit[i].second),
6373 MachinePointerInfo(StoresToEmit[i].second),
6375 OutChains.push_back(Val);
6378 if (!OutChains.empty())
6379 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6380 &OutChains[0], OutChains.size());
6385 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6386 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6387 MVT::Other, getRoot(),
6388 getValue(I.getArgOperand(0)),
6389 DAG.getSrcValue(I.getArgOperand(0))));
6392 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6393 const TargetLowering *TLI = TM.getTargetLowering();
6394 const DataLayout &TD = *TLI->getDataLayout();
6395 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6396 getRoot(), getValue(I.getOperand(0)),
6397 DAG.getSrcValue(I.getOperand(0)),
6398 TD.getABITypeAlignment(I.getType()));
6400 DAG.setRoot(V.getValue(1));
6403 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6404 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6405 MVT::Other, getRoot(),
6406 getValue(I.getArgOperand(0)),
6407 DAG.getSrcValue(I.getArgOperand(0))));
6410 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6411 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6412 MVT::Other, getRoot(),
6413 getValue(I.getArgOperand(0)),
6414 getValue(I.getArgOperand(1)),
6415 DAG.getSrcValue(I.getArgOperand(0)),
6416 DAG.getSrcValue(I.getArgOperand(1))));
6419 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6420 /// implementation, which just calls LowerCall.
6421 /// FIXME: When all targets are
6422 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6423 std::pair<SDValue, SDValue>
6424 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6425 // Handle the incoming return values from the call.
6427 SmallVector<EVT, 4> RetTys;
6428 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6429 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6431 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6432 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6433 for (unsigned i = 0; i != NumRegs; ++i) {
6434 ISD::InputArg MyFlags;
6435 MyFlags.VT = RegisterVT;
6436 MyFlags.Used = CLI.IsReturnValueUsed;
6438 MyFlags.Flags.setSExt();
6440 MyFlags.Flags.setZExt();
6442 MyFlags.Flags.setInReg();
6443 CLI.Ins.push_back(MyFlags);
6447 // Handle all of the outgoing arguments.
6449 CLI.OutVals.clear();
6450 ArgListTy &Args = CLI.Args;
6451 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6452 SmallVector<EVT, 4> ValueVTs;
6453 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6454 for (unsigned Value = 0, NumValues = ValueVTs.size();
6455 Value != NumValues; ++Value) {
6456 EVT VT = ValueVTs[Value];
6457 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6458 SDValue Op = SDValue(Args[i].Node.getNode(),
6459 Args[i].Node.getResNo() + Value);
6460 ISD::ArgFlagsTy Flags;
6461 unsigned OriginalAlignment =
6462 getDataLayout()->getABITypeAlignment(ArgTy);
6468 if (Args[i].isInReg)
6472 if (Args[i].isByVal) {
6474 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6475 Type *ElementTy = Ty->getElementType();
6476 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6477 // For ByVal, alignment should come from FE. BE will guess if this
6478 // info is not there but there are cases it cannot get right.
6479 unsigned FrameAlign;
6480 if (Args[i].Alignment)
6481 FrameAlign = Args[i].Alignment;
6483 FrameAlign = getByValTypeAlignment(ElementTy);
6484 Flags.setByValAlign(FrameAlign);
6488 Flags.setOrigAlign(OriginalAlignment);
6490 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6491 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6492 SmallVector<SDValue, 4> Parts(NumParts);
6493 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6496 ExtendKind = ISD::SIGN_EXTEND;
6497 else if (Args[i].isZExt)
6498 ExtendKind = ISD::ZERO_EXTEND;
6500 // Conservatively only handle 'returned' on non-vectors for now
6501 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6502 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6503 "unexpected use of 'returned'");
6504 // Before passing 'returned' to the target lowering code, ensure that
6505 // either the register MVT and the actual EVT are the same size or that
6506 // the return value and argument are extended in the same way; in these
6507 // cases it's safe to pass the argument register value unchanged as the
6508 // return register value (although it's at the target's option whether
6510 // TODO: allow code generation to take advantage of partially preserved
6511 // registers rather than clobbering the entire register when the
6512 // parameter extension method is not compatible with the return
6514 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6515 (ExtendKind != ISD::ANY_EXTEND &&
6516 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6517 Flags.setReturned();
6520 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6521 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6523 for (unsigned j = 0; j != NumParts; ++j) {
6524 // if it isn't first piece, alignment must be 1
6525 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6526 i < CLI.NumFixedArgs,
6527 i, j*Parts[j].getValueType().getStoreSize());
6528 if (NumParts > 1 && j == 0)
6529 MyFlags.Flags.setSplit();
6531 MyFlags.Flags.setOrigAlign(1);
6533 CLI.Outs.push_back(MyFlags);
6534 CLI.OutVals.push_back(Parts[j]);
6539 SmallVector<SDValue, 4> InVals;
6540 CLI.Chain = LowerCall(CLI, InVals);
6542 // Verify that the target's LowerCall behaved as expected.
6543 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6544 "LowerCall didn't return a valid chain!");
6545 assert((!CLI.IsTailCall || InVals.empty()) &&
6546 "LowerCall emitted a return value for a tail call!");
6547 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6548 "LowerCall didn't emit the correct number of values!");
6550 // For a tail call, the return value is merely live-out and there aren't
6551 // any nodes in the DAG representing it. Return a special value to
6552 // indicate that a tail call has been emitted and no more Instructions
6553 // should be processed in the current block.
6554 if (CLI.IsTailCall) {
6555 CLI.DAG.setRoot(CLI.Chain);
6556 return std::make_pair(SDValue(), SDValue());
6559 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6560 assert(InVals[i].getNode() &&
6561 "LowerCall emitted a null value!");
6562 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6563 "LowerCall emitted a value with the wrong type!");
6566 // Collect the legal value parts into potentially illegal values
6567 // that correspond to the original function's return values.
6568 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6570 AssertOp = ISD::AssertSext;
6571 else if (CLI.RetZExt)
6572 AssertOp = ISD::AssertZext;
6573 SmallVector<SDValue, 4> ReturnValues;
6574 unsigned CurReg = 0;
6575 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6577 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6578 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6580 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6581 NumRegs, RegisterVT, VT, NULL,
6586 // For a function returning void, there is no return value. We can't create
6587 // such a node, so we just return a null return value in that case. In
6588 // that case, nothing will actually look at the value.
6589 if (ReturnValues.empty())
6590 return std::make_pair(SDValue(), CLI.Chain);
6592 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6593 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6594 &ReturnValues[0], ReturnValues.size());
6595 return std::make_pair(Res, CLI.Chain);
6598 void TargetLowering::LowerOperationWrapper(SDNode *N,
6599 SmallVectorImpl<SDValue> &Results,
6600 SelectionDAG &DAG) const {
6601 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6603 Results.push_back(Res);
6606 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6607 llvm_unreachable("LowerOperation not implemented for this target!");
6611 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6612 SDValue Op = getNonRegisterValue(V);
6613 assert((Op.getOpcode() != ISD::CopyFromReg ||
6614 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6615 "Copy from a reg to the same reg!");
6616 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6618 const TargetLowering *TLI = TM.getTargetLowering();
6619 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
6620 SDValue Chain = DAG.getEntryNode();
6621 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
6622 PendingExports.push_back(Chain);
6625 #include "llvm/CodeGen/SelectionDAGISel.h"
6627 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6628 /// entry block, return true. This includes arguments used by switches, since
6629 /// the switch may expand into multiple basic blocks.
6630 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6631 // With FastISel active, we may be splitting blocks, so force creation
6632 // of virtual registers for all non-dead arguments.
6634 return A->use_empty();
6636 const BasicBlock *Entry = A->getParent()->begin();
6637 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6639 const User *U = *UI;
6640 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6641 return false; // Use not in entry block.
6646 void SelectionDAGISel::LowerArguments(const Function &F) {
6647 SelectionDAG &DAG = SDB->DAG;
6648 SDLoc dl = SDB->getCurSDLoc();
6649 const TargetLowering *TLI = getTargetLowering();
6650 const DataLayout *TD = TLI->getDataLayout();
6651 SmallVector<ISD::InputArg, 16> Ins;
6653 if (!FuncInfo->CanLowerReturn) {
6654 // Put in an sret pointer parameter before all the other parameters.
6655 SmallVector<EVT, 1> ValueVTs;
6656 ComputeValueVTs(*getTargetLowering(),
6657 PointerType::getUnqual(F.getReturnType()), ValueVTs);
6659 // NOTE: Assuming that a pointer will never break down to more than one VT
6661 ISD::ArgFlagsTy Flags;
6663 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
6664 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6665 Ins.push_back(RetArg);
6668 // Set up the incoming argument description vector.
6670 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6671 I != E; ++I, ++Idx) {
6672 SmallVector<EVT, 4> ValueVTs;
6673 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6674 bool isArgValueUsed = !I->use_empty();
6675 for (unsigned Value = 0, NumValues = ValueVTs.size();
6676 Value != NumValues; ++Value) {
6677 EVT VT = ValueVTs[Value];
6678 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6679 ISD::ArgFlagsTy Flags;
6680 unsigned OriginalAlignment =
6681 TD->getABITypeAlignment(ArgTy);
6683 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6685 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6687 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
6689 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
6691 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
6693 PointerType *Ty = cast<PointerType>(I->getType());
6694 Type *ElementTy = Ty->getElementType();
6695 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6696 // For ByVal, alignment should be passed from FE. BE will guess if
6697 // this info is not there but there are cases it cannot get right.
6698 unsigned FrameAlign;
6699 if (F.getParamAlignment(Idx))
6700 FrameAlign = F.getParamAlignment(Idx);
6702 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
6703 Flags.setByValAlign(FrameAlign);
6705 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
6707 Flags.setOrigAlign(OriginalAlignment);
6709 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6710 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
6711 for (unsigned i = 0; i != NumRegs; ++i) {
6712 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6713 Idx-1, i*RegisterVT.getStoreSize());
6714 if (NumRegs > 1 && i == 0)
6715 MyFlags.Flags.setSplit();
6716 // if it isn't first piece, alignment must be 1
6718 MyFlags.Flags.setOrigAlign(1);
6719 Ins.push_back(MyFlags);
6724 // Call the target to set up the argument values.
6725 SmallVector<SDValue, 8> InVals;
6726 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6730 // Verify that the target's LowerFormalArguments behaved as expected.
6731 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6732 "LowerFormalArguments didn't return a valid chain!");
6733 assert(InVals.size() == Ins.size() &&
6734 "LowerFormalArguments didn't emit the correct number of values!");
6736 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6737 assert(InVals[i].getNode() &&
6738 "LowerFormalArguments emitted a null value!");
6739 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6740 "LowerFormalArguments emitted a value with the wrong type!");
6744 // Update the DAG with the new chain value resulting from argument lowering.
6745 DAG.setRoot(NewRoot);
6747 // Set up the argument values.
6750 if (!FuncInfo->CanLowerReturn) {
6751 // Create a virtual register for the sret pointer, and put in a copy
6752 // from the sret argument into it.
6753 SmallVector<EVT, 1> ValueVTs;
6754 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6755 MVT VT = ValueVTs[0].getSimpleVT();
6756 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6757 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6758 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6759 RegVT, VT, NULL, AssertOp);
6761 MachineFunction& MF = SDB->DAG.getMachineFunction();
6762 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6763 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
6764 FuncInfo->DemoteRegister = SRetReg;
6765 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
6767 DAG.setRoot(NewRoot);
6769 // i indexes lowered arguments. Bump it past the hidden sret argument.
6770 // Idx indexes LLVM arguments. Don't touch it.
6774 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6776 SmallVector<SDValue, 4> ArgValues;
6777 SmallVector<EVT, 4> ValueVTs;
6778 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6779 unsigned NumValues = ValueVTs.size();
6781 // If this argument is unused then remember its value. It is used to generate
6782 // debugging information.
6783 if (I->use_empty() && NumValues) {
6784 SDB->setUnusedArgValue(I, InVals[i]);
6786 // Also remember any frame index for use in FastISel.
6787 if (FrameIndexSDNode *FI =
6788 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
6789 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6792 for (unsigned Val = 0; Val != NumValues; ++Val) {
6793 EVT VT = ValueVTs[Val];
6794 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6795 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
6797 if (!I->use_empty()) {
6798 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6799 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6800 AssertOp = ISD::AssertSext;
6801 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6802 AssertOp = ISD::AssertZext;
6804 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6805 NumParts, PartVT, VT,
6812 // We don't need to do anything else for unused arguments.
6813 if (ArgValues.empty())
6816 // Note down frame index.
6817 if (FrameIndexSDNode *FI =
6818 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6819 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6821 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6822 SDB->getCurSDLoc());
6824 SDB->setValue(I, Res);
6825 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6826 if (LoadSDNode *LNode =
6827 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6828 if (FrameIndexSDNode *FI =
6829 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6830 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6833 // If this argument is live outside of the entry block, insert a copy from
6834 // wherever we got it to the vreg that other BB's will reference it as.
6835 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6836 // If we can, though, try to skip creating an unnecessary vreg.
6837 // FIXME: This isn't very clean... it would be nice to make this more
6838 // general. It's also subtly incompatible with the hacks FastISel
6840 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6841 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6842 FuncInfo->ValueMap[I] = Reg;
6846 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6847 FuncInfo->InitializeRegForValue(I);
6848 SDB->CopyToExportRegsIfNeeded(I);
6852 assert(i == InVals.size() && "Argument register count mismatch!");
6854 // Finally, if the target has anything special to do, allow it to do so.
6855 // FIXME: this should insert code into the DAG!
6856 EmitFunctionEntryCode();
6859 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6860 /// ensure constants are generated when needed. Remember the virtual registers
6861 /// that need to be added to the Machine PHI nodes as input. We cannot just
6862 /// directly add them, because expansion might result in multiple MBB's for one
6863 /// BB. As such, the start of the BB might correspond to a different MBB than
6867 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6868 const TerminatorInst *TI = LLVMBB->getTerminator();
6870 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6872 // Check successor nodes' PHI nodes that expect a constant to be available
6874 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6875 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6876 if (!isa<PHINode>(SuccBB->begin())) continue;
6877 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6879 // If this terminator has multiple identical successors (common for
6880 // switches), only handle each succ once.
6881 if (!SuccsHandled.insert(SuccMBB)) continue;
6883 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6885 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6886 // nodes and Machine PHI nodes, but the incoming operands have not been
6888 for (BasicBlock::const_iterator I = SuccBB->begin();
6889 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6890 // Ignore dead phi's.
6891 if (PN->use_empty()) continue;
6894 if (PN->getType()->isEmptyTy())
6898 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6900 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6901 unsigned &RegOut = ConstantsOut[C];
6903 RegOut = FuncInfo.CreateRegs(C->getType());
6904 CopyValueToVirtualRegister(C, RegOut);
6908 DenseMap<const Value *, unsigned>::iterator I =
6909 FuncInfo.ValueMap.find(PHIOp);
6910 if (I != FuncInfo.ValueMap.end())
6913 assert(isa<AllocaInst>(PHIOp) &&
6914 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6915 "Didn't codegen value into a register!??");
6916 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6917 CopyValueToVirtualRegister(PHIOp, Reg);
6921 // Remember that this register needs to added to the machine PHI node as
6922 // the input for this MBB.
6923 SmallVector<EVT, 4> ValueVTs;
6924 const TargetLowering *TLI = TM.getTargetLowering();
6925 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
6926 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6927 EVT VT = ValueVTs[vti];
6928 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
6929 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6930 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6931 Reg += NumRegisters;
6936 ConstantsOut.clear();