1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/LLVMContext.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/IntegersSubsetMapping.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static const unsigned MaxParallelChains = 64;
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
91 const SDValue *Parts, unsigned NumParts,
92 MVT PartVT, EVT ValueVT, const Value *V);
94 /// getCopyFromParts - Create a value that contains the specified legal parts
95 /// combined into the value they represent. If the parts combine to a type
96 /// larger then ValueVT then AssertOp can be used to specify whether the extra
97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
98 /// (ISD::AssertSext).
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 const SDValue *Parts,
101 unsigned NumParts, MVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT, V);
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT, V);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 EVT PartEVT = Val.getValueType();
184 if (PartEVT == ValueVT)
187 if (PartEVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartEVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getTargetConstant(1, TLI.getPointerTy()));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromPartsVector - Create a value that contains the specified legal
216 /// parts combined into the value they represent. If the parts combine to a
217 /// type larger then ValueVT then AssertOp can be used to specify whether the
218 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
219 /// ValueVT (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 MVT PartVT, EVT ValueVT, const Value *V) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
232 unsigned NumIntermediates;
234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
235 NumIntermediates, RegisterVT);
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
239 assert(RegisterVT == Parts[0].getSimpleValueType() &&
240 "Part type doesn't match part!");
242 // Assemble the parts into intermediate operands.
243 SmallVector<SDValue, 8> Ops(NumIntermediates);
244 if (NumIntermediates == NumParts) {
245 // If the register was not expanded, truncate or copy the value,
247 for (unsigned i = 0; i != NumParts; ++i)
248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
249 PartVT, IntermediateVT, V);
250 } else if (NumParts > 0) {
251 // If the intermediate type was expanded, build the intermediate
252 // operands from the parts.
253 assert(NumParts % NumIntermediates == 0 &&
254 "Must expand into a divisible number of parts!");
255 unsigned Factor = NumParts / NumIntermediates;
256 for (unsigned i = 0; i != NumIntermediates; ++i)
257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
258 PartVT, IntermediateVT, V);
261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
262 // intermediate operands.
263 Val = DAG.getNode(IntermediateVT.isVector() ?
264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
265 ValueVT, &Ops[0], NumIntermediates);
268 // There is now one part, held in Val. Correct it to match ValueVT.
269 EVT PartEVT = Val.getValueType();
271 if (PartEVT == ValueVT)
274 if (PartEVT.isVector()) {
275 // If the element type of the source/dest vectors are the same, but the
276 // parts vector has more elements than the value vector, then we have a
277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
279 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
280 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
281 "Cannot narrow, it would be a lossy transformation");
282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
283 DAG.getIntPtrConstant(0));
286 // Vector/Vector bitcast.
287 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
290 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
291 "Cannot handle this kind of promotion");
292 // Promoted vector extract
293 bool Smaller = ValueVT.bitsLE(PartEVT);
294 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
299 // Trivial bitcast if the types are the same size and the destination
300 // vector type is legal.
301 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
302 TLI.isTypeLegal(ValueVT))
303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
305 // Handle cases such as i8 -> <1 x i1>
306 if (ValueVT.getVectorNumElements() != 1) {
307 LLVMContext &Ctx = *DAG.getContext();
308 Twine ErrMsg("non-trivial scalar-to-vector conversion");
309 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
310 if (const CallInst *CI = dyn_cast<CallInst>(I))
311 if (isa<InlineAsm>(CI->getCalledValue()))
312 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
313 Ctx.emitError(I, ErrMsg);
315 Ctx.emitError(ErrMsg);
317 return DAG.getUNDEF(ValueVT);
320 if (ValueVT.getVectorNumElements() == 1 &&
321 ValueVT.getVectorElementType() != PartEVT) {
322 bool Smaller = ValueVT.bitsLE(PartEVT);
323 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
324 DL, ValueVT.getScalarType(), Val);
327 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
330 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
331 SDValue Val, SDValue *Parts, unsigned NumParts,
332 MVT PartVT, const Value *V);
334 /// getCopyToParts - Create a series of nodes that contain the specified value
335 /// split into legal parts. If the parts contain more bits than Val, then, for
336 /// integers, ExtendKind can be used to specify how to generate the extra bits.
337 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
338 SDValue Val, SDValue *Parts, unsigned NumParts,
339 MVT PartVT, const Value *V,
340 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
341 EVT ValueVT = Val.getValueType();
343 // Handle the vector case separately.
344 if (ValueVT.isVector())
345 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
348 unsigned PartBits = PartVT.getSizeInBits();
349 unsigned OrigNumParts = NumParts;
350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
355 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
356 EVT PartEVT = PartVT;
357 if (PartEVT == ValueVT) {
358 assert(NumParts == 1 && "No-op copy with multiple parts!");
363 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
364 // If the parts cover more bits than the value has, promote the value.
365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
366 assert(NumParts == 1 && "Do not know what to promote to!");
367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
370 ValueVT.isInteger() &&
371 "Unknown mismatch!");
372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
374 if (PartVT == MVT::x86mmx)
375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
377 } else if (PartBits == ValueVT.getSizeInBits()) {
378 // Different types of the same size.
379 assert(NumParts == 1 && PartEVT != ValueVT);
380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
382 // If the parts cover less bits than value has, truncate the value.
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
392 // The value may have changed - recompute ValueVT.
393 ValueVT = Val.getValueType();
394 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
395 "Failed to tile the value with PartVT!");
398 if (PartEVT != ValueVT) {
399 LLVMContext &Ctx = *DAG.getContext();
400 Twine ErrMsg("scalar-to-vector conversion failed");
401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
402 if (const CallInst *CI = dyn_cast<CallInst>(I))
403 if (isa<InlineAsm>(CI->getCalledValue()))
404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
405 Ctx.emitError(I, ErrMsg);
407 Ctx.emitError(ErrMsg);
415 // Expand the value into multiple parts.
416 if (NumParts & (NumParts - 1)) {
417 // The number of parts is not a power of 2. Split off and copy the tail.
418 assert(PartVT.isInteger() && ValueVT.isInteger() &&
419 "Do not know what to expand to!");
420 unsigned RoundParts = 1 << Log2_32(NumParts);
421 unsigned RoundBits = RoundParts * PartBits;
422 unsigned OddParts = NumParts - RoundParts;
423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424 DAG.getIntPtrConstant(RoundBits));
425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
427 if (TLI.isBigEndian())
428 // The odd parts were reversed by getCopyToParts - unreverse them.
429 std::reverse(Parts + RoundParts, Parts + NumParts);
431 NumParts = RoundParts;
432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
436 // The number of parts is a power of 2. Repeatedly bisect the value using
438 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439 EVT::getIntegerVT(*DAG.getContext(),
440 ValueVT.getSizeInBits()),
443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444 for (unsigned i = 0; i < NumParts; i += StepSize) {
445 unsigned ThisBits = StepSize * PartBits / 2;
446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447 SDValue &Part0 = Parts[i];
448 SDValue &Part1 = Parts[i+StepSize/2];
450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(1));
452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(0));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 if (TLI.isBigEndian())
463 std::reverse(Parts, Parts + OrigNumParts);
467 /// getCopyToPartsVector - Create a series of nodes that contain the specified
468 /// value split into legal parts.
469 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
470 SDValue Val, SDValue *Parts, unsigned NumParts,
471 MVT PartVT, const Value *V) {
472 EVT ValueVT = Val.getValueType();
473 assert(ValueVT.isVector() && "Not a vector");
474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
477 EVT PartEVT = PartVT;
478 if (PartEVT == ValueVT) {
480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481 // Bitconvert vector->vector case.
482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483 } else if (PartVT.isVector() &&
484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486 EVT ElementVT = PartVT.getVectorElementType();
487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
489 SmallVector<SDValue, 16> Ops;
490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 ElementVT, Val, DAG.getIntPtrConstant(i)));
494 for (unsigned i = ValueVT.getVectorNumElements(),
495 e = PartVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getUNDEF(ElementVT));
498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
500 // FIXME: Use CONCAT for 2x -> 4x.
502 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
504 } else if (PartVT.isVector() &&
505 PartEVT.getVectorElementType().bitsGE(
506 ValueVT.getVectorElementType()) &&
507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509 // Promoted vector extract
510 bool Smaller = PartEVT.bitsLE(ValueVT);
511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
514 // Vector -> scalar conversion.
515 assert(ValueVT.getVectorNumElements() == 1 &&
516 "Only trivial vector-to-scalar conversions should get here!");
517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 PartVT, Val, DAG.getIntPtrConstant(0));
520 bool Smaller = ValueVT.bitsLE(PartVT);
521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
529 // Handle a multi-element vector.
532 unsigned NumIntermediates;
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 NumIntermediates, RegisterVT);
536 unsigned NumElements = ValueVT.getVectorNumElements();
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542 // Split the vector into intermediate operands.
543 SmallVector<SDValue, 8> Ops(NumIntermediates);
544 for (unsigned i = 0; i != NumIntermediates; ++i) {
545 if (IntermediateVT.isVector())
546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
551 IntermediateVT, Val, DAG.getIntPtrConstant(i));
554 // Split the intermediate operands into legal parts.
555 if (NumParts == NumIntermediates) {
556 // If the register was not expanded, promote or copy the value,
558 for (unsigned i = 0; i != NumParts; ++i)
559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
560 } else if (NumParts > 0) {
561 // If the intermediate type was expanded, split each the value into
563 assert(NumParts % NumIntermediates == 0 &&
564 "Must expand into a divisible number of parts!");
565 unsigned Factor = NumParts / NumIntermediates;
566 for (unsigned i = 0; i != NumIntermediates; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
572 /// RegsForValue - This struct represents the registers (physical or virtual)
573 /// that a particular set of values is assigned, and the type information
574 /// about the value. The most common situation is to represent one value at a
575 /// time, but struct or array values are handled element-wise as multiple
576 /// values. The splitting of aggregates is performed recursively, so that we
577 /// never have aggregate-typed registers. The values at this point do not
578 /// necessarily have legal types, so each value may require one or more
579 /// registers of some legal type.
581 struct RegsForValue {
582 /// ValueVTs - The value types of the values, which may not be legal, and
583 /// may need be promoted or synthesized from one or more registers.
585 SmallVector<EVT, 4> ValueVTs;
587 /// RegVTs - The value types of the registers. This is the same size as
588 /// ValueVTs and it records, for each value, what the type of the assigned
589 /// register or registers are. (Individual values are never synthesized
590 /// from more than one type of register.)
592 /// With virtual registers, the contents of RegVTs is redundant with TLI's
593 /// getRegisterType member function, however when with physical registers
594 /// it is necessary to have a separate record of the types.
596 SmallVector<MVT, 4> RegVTs;
598 /// Regs - This list holds the registers assigned to the values.
599 /// Each legal or promoted value requires one register, and each
600 /// expanded value requires multiple registers.
602 SmallVector<unsigned, 4> Regs;
606 RegsForValue(const SmallVector<unsigned, 4> ®s,
607 MVT regvt, EVT valuevt)
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
610 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
611 unsigned Reg, Type *Ty) {
612 ComputeValueVTs(tli, Ty, ValueVTs);
614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
615 EVT ValueVT = ValueVTs[Value];
616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
618 for (unsigned i = 0; i != NumRegs; ++i)
619 Regs.push_back(Reg + i);
620 RegVTs.push_back(RegisterVT);
625 /// areValueTypesLegal - Return true if types of all the values are legal.
626 bool areValueTypesLegal(const TargetLowering &TLI) {
627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
628 MVT RegisterVT = RegVTs[Value];
629 if (!TLI.isTypeLegal(RegisterVT))
635 /// append - Add the specified values to this one.
636 void append(const RegsForValue &RHS) {
637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
643 /// this value and returns the result as a ValueVTs value. This uses
644 /// Chain/Flag as the input and updates them for the output Chain/Flag.
645 /// If the Flag pointer is NULL, no flag is used.
646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
648 SDValue &Chain, SDValue *Flag,
649 const Value *V = 0) const;
651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
652 /// specified value into the registers specified by this object. This uses
653 /// Chain/Flag as the input and updates them for the output Chain/Flag.
654 /// If the Flag pointer is NULL, no flag is used.
655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
656 SDValue &Chain, SDValue *Flag, const Value *V) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 // FIXME: We capture more information than the dag can represent. For
721 // now, just use the tightest assertzext/assertsext possible.
723 EVT FromVT(MVT::Other);
724 if (NumSignBits == RegSize)
725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
726 else if (NumZeroBits >= RegSize-1)
727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
728 else if (NumSignBits > RegSize-8)
729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
730 else if (NumZeroBits >= RegSize-8)
731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
732 else if (NumSignBits > RegSize-16)
733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
734 else if (NumZeroBits >= RegSize-16)
735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
736 else if (NumSignBits > RegSize-32)
737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
738 else if (NumZeroBits >= RegSize-32)
739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
743 // Add an assertion node.
744 assert(FromVT != MVT::Other);
745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
746 RegisterVT, P, DAG.getValueType(FromVT));
749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
750 NumRegs, RegisterVT, ValueVT, V);
755 return DAG.getNode(ISD::MERGE_VALUES, dl,
756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
757 &Values[0], ValueVTs.size());
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
843 MVT RegisterVT = RegVTs[Value];
844 for (unsigned i = 0; i != NumRegs; ++i) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
851 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
852 const TargetLibraryInfo *li) {
856 TD = DAG.getTarget().getDataLayout();
857 Context = DAG.getContext();
858 LPadToCallSiteMap.clear();
861 /// clear - Clear out the current SelectionDAG and the associated
862 /// state and prepare this SelectionDAGBuilder object to be used
863 /// for a new block. This doesn't clear out information about
864 /// additional blocks that are needed to complete switch lowering
865 /// or PHI node updating; that information is cleared out as it is
867 void SelectionDAGBuilder::clear() {
869 UnusedArgNodeMap.clear();
870 PendingLoads.clear();
871 PendingExports.clear();
872 CurDebugLoc = DebugLoc();
876 /// clearDanglingDebugInfo - Clear the dangling debug information
877 /// map. This function is separated from the clear so that debug
878 /// information that is dangling in a basic block can be properly
879 /// resolved in a different basic block. This allows the
880 /// SelectionDAG to resolve dangling debug information attached
882 void SelectionDAGBuilder::clearDanglingDebugInfo() {
883 DanglingDebugInfoMap.clear();
886 /// getRoot - Return the current virtual root of the Selection DAG,
887 /// flushing any PendingLoad items. This must be done before emitting
888 /// a store or any other node that may need to be ordered after any
889 /// prior load instructions.
891 SDValue SelectionDAGBuilder::getRoot() {
892 if (PendingLoads.empty())
893 return DAG.getRoot();
895 if (PendingLoads.size() == 1) {
896 SDValue Root = PendingLoads[0];
898 PendingLoads.clear();
902 // Otherwise, we have to make a token factor node.
903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
904 &PendingLoads[0], PendingLoads.size());
905 PendingLoads.clear();
910 /// getControlRoot - Similar to getRoot, but instead of flushing all the
911 /// PendingLoad items, flush all the PendingExports items. It is necessary
912 /// to do this before emitting a terminator instruction.
914 SDValue SelectionDAGBuilder::getControlRoot() {
915 SDValue Root = DAG.getRoot();
917 if (PendingExports.empty())
920 // Turn all of the CopyToReg chains into one factored node.
921 if (Root.getOpcode() != ISD::EntryToken) {
922 unsigned i = 0, e = PendingExports.size();
923 for (; i != e; ++i) {
924 assert(PendingExports[i].getNode()->getNumOperands() > 1);
925 if (PendingExports[i].getNode()->getOperand(0) == Root)
926 break; // Don't add the root if we already indirectly depend on it.
930 PendingExports.push_back(Root);
933 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
935 PendingExports.size());
936 PendingExports.clear();
941 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
943 DAG.AssignOrdering(Node, SDNodeOrder);
945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
946 AssignOrderingToNode(Node->getOperand(I).getNode());
949 void SelectionDAGBuilder::visit(const Instruction &I) {
950 // Set up outgoing PHI node register values before emitting the terminator.
951 if (isa<TerminatorInst>(&I))
952 HandlePHINodesInSuccessorBlocks(I.getParent());
954 CurDebugLoc = I.getDebugLoc();
956 visit(I.getOpcode(), I);
958 if (!isa<TerminatorInst>(&I) && !HasTailCall)
959 CopyToExportRegsIfNeeded(&I);
961 CurDebugLoc = DebugLoc();
964 void SelectionDAGBuilder::visitPHI(const PHINode &) {
965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
968 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
969 // Note: this doesn't use InstVisitor, because it has to work with
970 // ConstantExpr's in addition to instructions.
972 default: llvm_unreachable("Unknown instruction type encountered!");
973 // Build the switch statement using the Instruction.def file.
974 #define HANDLE_INST(NUM, OPCODE, CLASS) \
975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
976 #include "llvm/IR/Instruction.def"
979 // Assign the ordering to the freshly created DAG nodes.
980 if (NodeMap.count(&I)) {
982 AssignOrderingToNode(getValue(&I).getNode());
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 uint64_t Offset = DI->getOffset();
999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
1000 SDV = DAG.getDbgValue(Variable, Val.getNode(),
1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
1002 DAG.AddDbgValue(SDV, Val.getNode(), false);
1005 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1006 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1010 /// getValue - Return an SDValue for the given Value.
1011 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1012 // If we already have an SDValue for this value, use it. It's important
1013 // to do this first, so that we don't create a CopyFromReg if we already
1014 // have a regular SDValue.
1015 SDValue &N = NodeMap[V];
1016 if (N.getNode()) return N;
1018 // If there's a virtual register allocated and initialized for this
1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1021 if (It != FuncInfo.ValueMap.end()) {
1022 unsigned InReg = It->second;
1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
1024 SDValue Chain = DAG.getEntryNode();
1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1026 resolveDanglingDebugInfo(V, N);
1030 // Otherwise create a new SDValue and remember it.
1031 SDValue Val = getValueImpl(V);
1033 resolveDanglingDebugInfo(V, Val);
1037 /// getNonRegisterValue - Return an SDValue for the given Value, but
1038 /// don't look in FuncInfo.ValueMap for a virtual register.
1039 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1040 // If we already have an SDValue for this value, use it.
1041 SDValue &N = NodeMap[V];
1042 if (N.getNode()) return N;
1044 // Otherwise create a new SDValue and remember it.
1045 SDValue Val = getValueImpl(V);
1047 resolveDanglingDebugInfo(V, Val);
1051 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1052 /// Create an SDValue for the given value.
1053 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI.getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1063 if (isa<ConstantPointerNull>(C))
1064 return DAG.getConstant(0, TLI.getPointerTy());
1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1067 return DAG.getConstantFP(*CFP, VT);
1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1070 return DAG.getUNDEF(VT);
1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1073 visit(CE->getOpcode(), *CE);
1074 SDValue N1 = NodeMap[V];
1075 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1080 SmallVector<SDValue, 4> Constants;
1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1083 SDNode *Val = getValue(*OI).getNode();
1084 // If the operand is an empty aggregate, there are no values.
1086 // Add each leaf value from the operand to the Constants list
1087 // to form a flattened list of all the values.
1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1089 Constants.push_back(SDValue(Val, i));
1092 return DAG.getMergeValues(&Constants[0], Constants.size(),
1096 if (const ConstantDataSequential *CDS =
1097 dyn_cast<ConstantDataSequential>(C)) {
1098 SmallVector<SDValue, 4> Ops;
1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Ops.push_back(SDValue(Val, i));
1107 if (isa<ArrayType>(CDS->getType()))
1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1110 VT, &Ops[0], Ops.size());
1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1115 "Unknown struct or array constant!");
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1119 unsigned NumElts = ValueVTs.size();
1121 return SDValue(); // empty struct
1122 SmallVector<SDValue, 4> Constants(NumElts);
1123 for (unsigned i = 0; i != NumElts; ++i) {
1124 EVT EltVT = ValueVTs[i];
1125 if (isa<UndefValue>(C))
1126 Constants[i] = DAG.getUNDEF(EltVT);
1127 else if (EltVT.isFloatingPoint())
1128 Constants[i] = DAG.getConstantFP(0, EltVT);
1130 Constants[i] = DAG.getConstant(0, EltVT);
1133 return DAG.getMergeValues(&Constants[0], NumElts,
1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1138 return DAG.getBlockAddress(BA, VT);
1140 VectorType *VecTy = cast<VectorType>(V->getType());
1141 unsigned NumElements = VecTy->getNumElements();
1143 // Now that we know the number and type of the elements, get that number of
1144 // elements into the Ops array based on what kind of constant it is.
1145 SmallVector<SDValue, 16> Ops;
1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1147 for (unsigned i = 0; i != NumElements; ++i)
1148 Ops.push_back(getValue(CV->getOperand(i)));
1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1151 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1154 if (EltVT.isFloatingPoint())
1155 Op = DAG.getConstantFP(0, EltVT);
1157 Op = DAG.getConstant(0, EltVT);
1158 Ops.assign(NumElements, Op);
1161 // Create a BUILD_VECTOR node.
1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1163 VT, &Ops[0], Ops.size());
1166 // If this is a static alloca, generate it as the frameindex instead of
1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1169 DenseMap<const AllocaInst*, int>::iterator SI =
1170 FuncInfo.StaticAllocaMap.find(AI);
1171 if (SI != FuncInfo.StaticAllocaMap.end())
1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1175 // If this is an instruction which fast-isel has deferred, select it now.
1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1179 SDValue Chain = DAG.getEntryNode();
1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1183 llvm_unreachable("Can't get register for value!");
1186 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1187 SDValue Chain = getControlRoot();
1188 SmallVector<ISD::OutputArg, 8> Outs;
1189 SmallVector<SDValue, 8> OutVals;
1191 if (!FuncInfo.CanLowerReturn) {
1192 unsigned DemoteReg = FuncInfo.DemoteRegister;
1193 const Function *F = I.getParent()->getParent();
1195 // Emit a store of the return value through the virtual register.
1196 // Leave Outs empty so that LowerReturn won't try to load return
1197 // registers the usual way.
1198 SmallVector<EVT, 1> PtrValueVTs;
1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1203 SDValue RetOp = getValue(I.getOperand(0));
1205 SmallVector<EVT, 4> ValueVTs;
1206 SmallVector<uint64_t, 4> Offsets;
1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1208 unsigned NumValues = ValueVTs.size();
1210 SmallVector<SDValue, 4> Chains(NumValues);
1211 for (unsigned i = 0; i != NumValues; ++i) {
1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1213 RetPtr.getValueType(), RetPtr,
1214 DAG.getIntPtrConstant(Offsets[i]));
1216 DAG.getStore(Chain, getCurDebugLoc(),
1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1218 // FIXME: better loc info would be nice.
1219 Add, MachinePointerInfo(), false, false, 0);
1222 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1223 MVT::Other, &Chains[0], NumValues);
1224 } else if (I.getNumOperands() != 0) {
1225 SmallVector<EVT, 4> ValueVTs;
1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1227 unsigned NumValues = ValueVTs.size();
1229 SDValue RetOp = getValue(I.getOperand(0));
1230 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1231 EVT VT = ValueVTs[j];
1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1235 const Function *F = I.getParent()->getParent();
1236 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1238 ExtendKind = ISD::SIGN_EXTEND;
1239 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::ZERO_EXTEND;
1243 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1244 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1246 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1247 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1248 SmallVector<SDValue, 4> Parts(NumParts);
1249 getCopyToParts(DAG, getCurDebugLoc(),
1250 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1251 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1253 // 'inreg' on function refers to return value
1254 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1255 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1259 // Propagate extension type if any
1260 if (ExtendKind == ISD::SIGN_EXTEND)
1262 else if (ExtendKind == ISD::ZERO_EXTEND)
1265 for (unsigned i = 0; i < NumParts; ++i) {
1266 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1267 /*isfixed=*/true, 0, 0));
1268 OutVals.push_back(Parts[i]);
1274 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1275 CallingConv::ID CallConv =
1276 DAG.getMachineFunction().getFunction()->getCallingConv();
1277 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1278 Outs, OutVals, getCurDebugLoc(), DAG);
1280 // Verify that the target's LowerReturn behaved as expected.
1281 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1282 "LowerReturn didn't return a valid chain!");
1284 // Update the DAG with the new chain value resulting from return lowering.
1288 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1289 /// created for it, emit nodes to copy the value into the virtual
1291 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1293 if (V->getType()->isEmptyTy())
1296 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1297 if (VMI != FuncInfo.ValueMap.end()) {
1298 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1299 CopyValueToVirtualRegister(V, VMI->second);
1303 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1304 /// the current basic block, add it to ValueMap now so that we'll get a
1306 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1307 // No need to export constants.
1308 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1310 // Already exported?
1311 if (FuncInfo.isExportedInst(V)) return;
1313 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1314 CopyValueToVirtualRegister(V, Reg);
1317 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1318 const BasicBlock *FromBB) {
1319 // The operands of the setcc have to be in this block. We don't know
1320 // how to export them from some other block.
1321 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1322 // Can export from current BB.
1323 if (VI->getParent() == FromBB)
1326 // Is already exported, noop.
1327 return FuncInfo.isExportedInst(V);
1330 // If this is an argument, we can export it if the BB is the entry block or
1331 // if it is already exported.
1332 if (isa<Argument>(V)) {
1333 if (FromBB == &FromBB->getParent()->getEntryBlock())
1336 // Otherwise, can only export this if it is already exported.
1337 return FuncInfo.isExportedInst(V);
1340 // Otherwise, constants can always be exported.
1344 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1345 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1346 const MachineBasicBlock *Dst) const {
1347 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1350 const BasicBlock *SrcBB = Src->getBasicBlock();
1351 const BasicBlock *DstBB = Dst->getBasicBlock();
1352 return BPI->getEdgeWeight(SrcBB, DstBB);
1355 void SelectionDAGBuilder::
1356 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1357 uint32_t Weight /* = 0 */) {
1359 Weight = getEdgeWeight(Src, Dst);
1360 Src->addSuccessor(Dst, Weight);
1364 static bool InBlock(const Value *V, const BasicBlock *BB) {
1365 if (const Instruction *I = dyn_cast<Instruction>(V))
1366 return I->getParent() == BB;
1370 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1371 /// This function emits a branch and is used at the leaves of an OR or an
1372 /// AND operator tree.
1375 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1376 MachineBasicBlock *TBB,
1377 MachineBasicBlock *FBB,
1378 MachineBasicBlock *CurBB,
1379 MachineBasicBlock *SwitchBB) {
1380 const BasicBlock *BB = CurBB->getBasicBlock();
1382 // If the leaf of the tree is a comparison, merge the condition into
1384 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1385 // The operands of the cmp have to be in this block. We don't know
1386 // how to export them from some other block. If this is the first block
1387 // of the sequence, no exporting is needed.
1388 if (CurBB == SwitchBB ||
1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1391 ISD::CondCode Condition;
1392 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1393 Condition = getICmpCondCode(IC->getPredicate());
1394 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1395 Condition = getFCmpCondCode(FC->getPredicate());
1396 if (TM.Options.NoNaNsFPMath)
1397 Condition = getFCmpCodeWithoutNaN(Condition);
1399 Condition = ISD::SETEQ; // silence warning.
1400 llvm_unreachable("Unknown compare instruction");
1403 CaseBlock CB(Condition, BOp->getOperand(0),
1404 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1405 SwitchCases.push_back(CB);
1410 // Create a CaseBlock record representing this branch.
1411 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1412 NULL, TBB, FBB, CurBB);
1413 SwitchCases.push_back(CB);
1416 /// FindMergedConditions - If Cond is an expression like
1417 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1418 MachineBasicBlock *TBB,
1419 MachineBasicBlock *FBB,
1420 MachineBasicBlock *CurBB,
1421 MachineBasicBlock *SwitchBB,
1423 // If this node is not part of the or/and tree, emit it as a branch.
1424 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1425 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1426 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1427 BOp->getParent() != CurBB->getBasicBlock() ||
1428 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1429 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1430 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1434 // Create TmpBB after CurBB.
1435 MachineFunction::iterator BBI = CurBB;
1436 MachineFunction &MF = DAG.getMachineFunction();
1437 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1438 CurBB->getParent()->insert(++BBI, TmpBB);
1440 if (Opc == Instruction::Or) {
1441 // Codegen X | Y as:
1449 // Emit the LHS condition.
1450 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1452 // Emit the RHS condition into TmpBB.
1453 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1455 assert(Opc == Instruction::And && "Unknown merge op!");
1456 // Codegen X & Y as:
1463 // This requires creation of TmpBB after CurBB.
1465 // Emit the LHS condition.
1466 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1468 // Emit the RHS condition into TmpBB.
1469 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1473 /// If the set of cases should be emitted as a series of branches, return true.
1474 /// If we should emit this as a bunch of and/or'd together conditions, return
1477 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1478 if (Cases.size() != 2) return true;
1480 // If this is two comparisons of the same values or'd or and'd together, they
1481 // will get folded into a single comparison, so don't emit two blocks.
1482 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1483 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1484 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1485 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1489 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1490 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1491 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1492 Cases[0].CC == Cases[1].CC &&
1493 isa<Constant>(Cases[0].CmpRHS) &&
1494 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1495 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1497 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1504 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1505 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1507 // Update machine-CFG edges.
1508 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1510 // Figure out which block is immediately after the current one.
1511 MachineBasicBlock *NextBlock = 0;
1512 MachineFunction::iterator BBI = BrMBB;
1513 if (++BBI != FuncInfo.MF->end())
1516 if (I.isUnconditional()) {
1517 // Update machine-CFG edges.
1518 BrMBB->addSuccessor(Succ0MBB);
1520 // If this is not a fall-through branch, emit the branch.
1521 if (Succ0MBB != NextBlock)
1522 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1523 MVT::Other, getControlRoot(),
1524 DAG.getBasicBlock(Succ0MBB)));
1529 // If this condition is one of the special cases we handle, do special stuff
1531 const Value *CondVal = I.getCondition();
1532 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1534 // If this is a series of conditions that are or'd or and'd together, emit
1535 // this as a sequence of branches instead of setcc's with and/or operations.
1536 // As long as jumps are not expensive, this should improve performance.
1537 // For example, instead of something like:
1550 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1551 if (!TLI.isJumpExpensive() &&
1553 (BOp->getOpcode() == Instruction::And ||
1554 BOp->getOpcode() == Instruction::Or)) {
1555 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1557 // If the compares in later blocks need to use values not currently
1558 // exported from this block, export them now. This block should always
1559 // be the first entry.
1560 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1562 // Allow some cases to be rejected.
1563 if (ShouldEmitAsBranches(SwitchCases)) {
1564 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1565 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1566 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1569 // Emit the branch for this block.
1570 visitSwitchCase(SwitchCases[0], BrMBB);
1571 SwitchCases.erase(SwitchCases.begin());
1575 // Okay, we decided not to do this, remove any inserted MBB's and clear
1577 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1578 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1580 SwitchCases.clear();
1584 // Create a CaseBlock record representing this branch.
1585 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1586 NULL, Succ0MBB, Succ1MBB, BrMBB);
1588 // Use visitSwitchCase to actually insert the fast branch sequence for this
1590 visitSwitchCase(CB, BrMBB);
1593 /// visitSwitchCase - Emits the necessary code to represent a single node in
1594 /// the binary search tree resulting from lowering a switch instruction.
1595 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1596 MachineBasicBlock *SwitchBB) {
1598 SDValue CondLHS = getValue(CB.CmpLHS);
1599 DebugLoc dl = getCurDebugLoc();
1601 // Build the setcc now.
1602 if (CB.CmpMHS == NULL) {
1603 // Fold "(X == true)" to X and "(X == false)" to !X to
1604 // handle common cases produced by branch lowering.
1605 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1606 CB.CC == ISD::SETEQ)
1608 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1609 CB.CC == ISD::SETEQ) {
1610 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1611 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1613 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1615 assert(CB.CC == ISD::SETCC_INVALID &&
1616 "Condition is undefined for to-the-range belonging check.");
1618 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1619 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1621 SDValue CmpOp = getValue(CB.CmpMHS);
1622 EVT VT = CmpOp.getValueType();
1624 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1625 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1628 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1629 VT, CmpOp, DAG.getConstant(Low, VT));
1630 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1631 DAG.getConstant(High-Low, VT), ISD::SETULE);
1635 // Update successor info
1636 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1637 // TrueBB and FalseBB are always different unless the incoming IR is
1638 // degenerate. This only happens when running llc on weird IR.
1639 if (CB.TrueBB != CB.FalseBB)
1640 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1642 // Set NextBlock to be the MBB immediately after the current one, if any.
1643 // This is used to avoid emitting unnecessary branches to the next block.
1644 MachineBasicBlock *NextBlock = 0;
1645 MachineFunction::iterator BBI = SwitchBB;
1646 if (++BBI != FuncInfo.MF->end())
1649 // If the lhs block is the next block, invert the condition so that we can
1650 // fall through to the lhs instead of the rhs block.
1651 if (CB.TrueBB == NextBlock) {
1652 std::swap(CB.TrueBB, CB.FalseBB);
1653 SDValue True = DAG.getConstant(1, Cond.getValueType());
1654 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1657 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1658 MVT::Other, getControlRoot(), Cond,
1659 DAG.getBasicBlock(CB.TrueBB));
1661 // Insert the false branch. Do this even if it's a fall through branch,
1662 // this makes it easier to do DAG optimizations which require inverting
1663 // the branch condition.
1664 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1665 DAG.getBasicBlock(CB.FalseBB));
1667 DAG.setRoot(BrCond);
1670 /// visitJumpTable - Emit JumpTable node in the current MBB
1671 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1672 // Emit the code for the jump table
1673 assert(JT.Reg != -1U && "Should lower JT Header first!");
1674 EVT PTy = TLI.getPointerTy();
1675 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1677 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1678 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1679 MVT::Other, Index.getValue(1),
1681 DAG.setRoot(BrJumpTable);
1684 /// visitJumpTableHeader - This function emits necessary code to produce index
1685 /// in the JumpTable from switch case.
1686 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1687 JumpTableHeader &JTH,
1688 MachineBasicBlock *SwitchBB) {
1689 // Subtract the lowest switch case value from the value being switched on and
1690 // conditional branch to default mbb if the result is greater than the
1691 // difference between smallest and largest cases.
1692 SDValue SwitchOp = getValue(JTH.SValue);
1693 EVT VT = SwitchOp.getValueType();
1694 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1695 DAG.getConstant(JTH.First, VT));
1697 // The SDNode we just created, which holds the value being switched on minus
1698 // the smallest case value, needs to be copied to a virtual register so it
1699 // can be used as an index into the jump table in a subsequent basic block.
1700 // This value may be smaller or larger than the target's pointer type, and
1701 // therefore require extension or truncating.
1702 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1704 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1705 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1706 JumpTableReg, SwitchOp);
1707 JT.Reg = JumpTableReg;
1709 // Emit the range check for the jump table, and branch to the default block
1710 // for the switch statement if the value being switched on exceeds the largest
1711 // case in the switch.
1712 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1713 TLI.getSetCCResultType(*DAG.getContext(),
1714 Sub.getValueType()),
1716 DAG.getConstant(JTH.Last - JTH.First,VT),
1719 // Set NextBlock to be the MBB immediately after the current one, if any.
1720 // This is used to avoid emitting unnecessary branches to the next block.
1721 MachineBasicBlock *NextBlock = 0;
1722 MachineFunction::iterator BBI = SwitchBB;
1724 if (++BBI != FuncInfo.MF->end())
1727 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1728 MVT::Other, CopyTo, CMP,
1729 DAG.getBasicBlock(JT.Default));
1731 if (JT.MBB != NextBlock)
1732 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1733 DAG.getBasicBlock(JT.MBB));
1735 DAG.setRoot(BrCond);
1738 /// visitBitTestHeader - This function emits necessary code to produce value
1739 /// suitable for "bit tests"
1740 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1741 MachineBasicBlock *SwitchBB) {
1742 // Subtract the minimum value
1743 SDValue SwitchOp = getValue(B.SValue);
1744 EVT VT = SwitchOp.getValueType();
1745 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1746 DAG.getConstant(B.First, VT));
1749 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1750 TLI.getSetCCResultType(*DAG.getContext(),
1751 Sub.getValueType()),
1752 Sub, DAG.getConstant(B.Range, VT),
1755 // Determine the type of the test operands.
1756 bool UsePtrType = false;
1757 if (!TLI.isTypeLegal(VT))
1760 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1761 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1762 // Switch table case range are encoded into series of masks.
1763 // Just use pointer type, it's guaranteed to fit.
1769 VT = TLI.getPointerTy();
1770 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1773 B.RegVT = VT.getSimpleVT();
1774 B.Reg = FuncInfo.CreateReg(B.RegVT);
1775 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1778 // Set NextBlock to be the MBB immediately after the current one, if any.
1779 // This is used to avoid emitting unnecessary branches to the next block.
1780 MachineBasicBlock *NextBlock = 0;
1781 MachineFunction::iterator BBI = SwitchBB;
1782 if (++BBI != FuncInfo.MF->end())
1785 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1787 addSuccessorWithWeight(SwitchBB, B.Default);
1788 addSuccessorWithWeight(SwitchBB, MBB);
1790 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1791 MVT::Other, CopyTo, RangeCmp,
1792 DAG.getBasicBlock(B.Default));
1794 if (MBB != NextBlock)
1795 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1796 DAG.getBasicBlock(MBB));
1798 DAG.setRoot(BrRange);
1801 /// visitBitTestCase - this function produces one "bit test"
1802 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1803 MachineBasicBlock* NextMBB,
1804 uint32_t BranchWeightToNext,
1807 MachineBasicBlock *SwitchBB) {
1809 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1812 unsigned PopCount = CountPopulation_64(B.Mask);
1813 if (PopCount == 1) {
1814 // Testing for a single bit; just compare the shift count with what it
1815 // would need to be to shift a 1 bit in that position.
1816 Cmp = DAG.getSetCC(getCurDebugLoc(),
1817 TLI.getSetCCResultType(*DAG.getContext(), VT),
1819 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1821 } else if (PopCount == BB.Range) {
1822 // There is only one zero bit in the range, test for it directly.
1823 Cmp = DAG.getSetCC(getCurDebugLoc(),
1824 TLI.getSetCCResultType(*DAG.getContext(), VT),
1826 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1829 // Make desired shift
1830 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1831 DAG.getConstant(1, VT), ShiftOp);
1833 // Emit bit tests and jumps
1834 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1835 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1836 Cmp = DAG.getSetCC(getCurDebugLoc(),
1837 TLI.getSetCCResultType(*DAG.getContext(), VT),
1838 AndOp, DAG.getConstant(0, VT),
1842 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1843 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1844 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1845 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1847 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1848 MVT::Other, getControlRoot(),
1849 Cmp, DAG.getBasicBlock(B.TargetBB));
1851 // Set NextBlock to be the MBB immediately after the current one, if any.
1852 // This is used to avoid emitting unnecessary branches to the next block.
1853 MachineBasicBlock *NextBlock = 0;
1854 MachineFunction::iterator BBI = SwitchBB;
1855 if (++BBI != FuncInfo.MF->end())
1858 if (NextMBB != NextBlock)
1859 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1860 DAG.getBasicBlock(NextMBB));
1865 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1866 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1868 // Retrieve successors.
1869 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1870 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1872 const Value *Callee(I.getCalledValue());
1873 const Function *Fn = dyn_cast<Function>(Callee);
1874 if (isa<InlineAsm>(Callee))
1876 else if (Fn && Fn->isIntrinsic()) {
1877 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1878 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1880 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1882 // If the value of the invoke is used outside of its defining block, make it
1883 // available as a virtual register.
1884 CopyToExportRegsIfNeeded(&I);
1886 // Update successor info
1887 addSuccessorWithWeight(InvokeMBB, Return);
1888 addSuccessorWithWeight(InvokeMBB, LandingPad);
1890 // Drop into normal successor.
1891 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1892 MVT::Other, getControlRoot(),
1893 DAG.getBasicBlock(Return)));
1896 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1897 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1900 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1901 assert(FuncInfo.MBB->isLandingPad() &&
1902 "Call to landingpad not in landing pad!");
1904 MachineBasicBlock *MBB = FuncInfo.MBB;
1905 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1906 AddLandingPadInfo(LP, MMI, MBB);
1908 // If there aren't registers to copy the values into (e.g., during SjLj
1909 // exceptions), then don't bother to create these DAG nodes.
1910 if (TLI.getExceptionPointerRegister() == 0 &&
1911 TLI.getExceptionSelectorRegister() == 0)
1914 SmallVector<EVT, 2> ValueVTs;
1915 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1917 // Insert the EXCEPTIONADDR instruction.
1918 assert(FuncInfo.MBB->isLandingPad() &&
1919 "Call to eh.exception not in landing pad!");
1920 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1922 Ops[0] = DAG.getRoot();
1923 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1924 SDValue Chain = Op1.getValue(1);
1926 // Insert the EHSELECTION instruction.
1927 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1930 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1931 Chain = Op2.getValue(1);
1932 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1936 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1937 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1940 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1941 setValue(&LP, RetPair.first);
1942 DAG.setRoot(RetPair.second);
1945 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1946 /// small case ranges).
1947 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1948 CaseRecVector& WorkList,
1950 MachineBasicBlock *Default,
1951 MachineBasicBlock *SwitchBB) {
1952 // Size is the number of Cases represented by this range.
1953 size_t Size = CR.Range.second - CR.Range.first;
1957 // Get the MachineFunction which holds the current MBB. This is used when
1958 // inserting any additional MBBs necessary to represent the switch.
1959 MachineFunction *CurMF = FuncInfo.MF;
1961 // Figure out which block is immediately after the current one.
1962 MachineBasicBlock *NextBlock = 0;
1963 MachineFunction::iterator BBI = CR.CaseBB;
1965 if (++BBI != FuncInfo.MF->end())
1968 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1969 // If any two of the cases has the same destination, and if one value
1970 // is the same as the other, but has one bit unset that the other has set,
1971 // use bit manipulation to do two compares at once. For example:
1972 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1973 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1974 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1975 if (Size == 2 && CR.CaseBB == SwitchBB) {
1976 Case &Small = *CR.Range.first;
1977 Case &Big = *(CR.Range.second-1);
1979 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1980 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1981 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1983 // Check that there is only one bit different.
1984 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1985 (SmallValue | BigValue) == BigValue) {
1986 // Isolate the common bit.
1987 APInt CommonBit = BigValue & ~SmallValue;
1988 assert((SmallValue | CommonBit) == BigValue &&
1989 CommonBit.countPopulation() == 1 && "Not a common bit?");
1991 SDValue CondLHS = getValue(SV);
1992 EVT VT = CondLHS.getValueType();
1993 DebugLoc DL = getCurDebugLoc();
1995 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1996 DAG.getConstant(CommonBit, VT));
1997 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1998 Or, DAG.getConstant(BigValue, VT),
2001 // Update successor info.
2002 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2003 addSuccessorWithWeight(SwitchBB, Small.BB,
2004 Small.ExtraWeight + Big.ExtraWeight);
2005 addSuccessorWithWeight(SwitchBB, Default,
2006 // The default destination is the first successor in IR.
2007 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2009 // Insert the true branch.
2010 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2011 getControlRoot(), Cond,
2012 DAG.getBasicBlock(Small.BB));
2014 // Insert the false branch.
2015 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2016 DAG.getBasicBlock(Default));
2018 DAG.setRoot(BrCond);
2024 // Order cases by weight so the most likely case will be checked first.
2025 uint32_t UnhandledWeights = 0;
2027 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2028 uint32_t IWeight = I->ExtraWeight;
2029 UnhandledWeights += IWeight;
2030 for (CaseItr J = CR.Range.first; J < I; ++J) {
2031 uint32_t JWeight = J->ExtraWeight;
2032 if (IWeight > JWeight)
2037 // Rearrange the case blocks so that the last one falls through if possible.
2038 Case &BackCase = *(CR.Range.second-1);
2040 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2041 // The last case block won't fall through into 'NextBlock' if we emit the
2042 // branches in this order. See if rearranging a case value would help.
2043 // We start at the bottom as it's the case with the least weight.
2044 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2045 if (I->BB == NextBlock) {
2046 std::swap(*I, BackCase);
2052 // Create a CaseBlock record representing a conditional branch to
2053 // the Case's target mbb if the value being switched on SV is equal
2055 MachineBasicBlock *CurBlock = CR.CaseBB;
2056 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2057 MachineBasicBlock *FallThrough;
2059 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2060 CurMF->insert(BBI, FallThrough);
2062 // Put SV in a virtual register to make it available from the new blocks.
2063 ExportFromCurrentBlock(SV);
2065 // If the last case doesn't match, go to the default block.
2066 FallThrough = Default;
2069 const Value *RHS, *LHS, *MHS;
2071 if (I->High == I->Low) {
2072 // This is just small small case range :) containing exactly 1 case
2074 LHS = SV; RHS = I->High; MHS = NULL;
2076 CC = ISD::SETCC_INVALID;
2077 LHS = I->Low; MHS = SV; RHS = I->High;
2080 // The false weight should be sum of all un-handled cases.
2081 UnhandledWeights -= I->ExtraWeight;
2082 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2084 /* trueweight */ I->ExtraWeight,
2085 /* falseweight */ UnhandledWeights);
2087 // If emitting the first comparison, just call visitSwitchCase to emit the
2088 // code into the current block. Otherwise, push the CaseBlock onto the
2089 // vector to be later processed by SDISel, and insert the node's MBB
2090 // before the next MBB.
2091 if (CurBlock == SwitchBB)
2092 visitSwitchCase(CB, SwitchBB);
2094 SwitchCases.push_back(CB);
2096 CurBlock = FallThrough;
2102 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2103 return TLI.supportJumpTables() &&
2104 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2105 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2108 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2109 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2110 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2111 return (LastExt - FirstExt + 1ULL);
2114 /// handleJTSwitchCase - Emit jumptable for current switch case range
2115 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2116 CaseRecVector &WorkList,
2118 MachineBasicBlock *Default,
2119 MachineBasicBlock *SwitchBB) {
2120 Case& FrontCase = *CR.Range.first;
2121 Case& BackCase = *(CR.Range.second-1);
2123 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2124 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2126 APInt TSize(First.getBitWidth(), 0);
2127 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2130 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2133 APInt Range = ComputeRange(First, Last);
2134 // The density is TSize / Range. Require at least 40%.
2135 // It should not be possible for IntTSize to saturate for sane code, but make
2136 // sure we handle Range saturation correctly.
2137 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2138 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2139 if (IntTSize * 10 < IntRange * 4)
2142 DEBUG(dbgs() << "Lowering jump table\n"
2143 << "First entry: " << First << ". Last entry: " << Last << '\n'
2144 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2146 // Get the MachineFunction which holds the current MBB. This is used when
2147 // inserting any additional MBBs necessary to represent the switch.
2148 MachineFunction *CurMF = FuncInfo.MF;
2150 // Figure out which block is immediately after the current one.
2151 MachineFunction::iterator BBI = CR.CaseBB;
2154 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2156 // Create a new basic block to hold the code for loading the address
2157 // of the jump table, and jumping to it. Update successor information;
2158 // we will either branch to the default case for the switch, or the jump
2160 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2161 CurMF->insert(BBI, JumpTableBB);
2163 addSuccessorWithWeight(CR.CaseBB, Default);
2164 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2166 // Build a vector of destination BBs, corresponding to each target
2167 // of the jump table. If the value of the jump table slot corresponds to
2168 // a case statement, push the case's BB onto the vector, otherwise, push
2170 std::vector<MachineBasicBlock*> DestBBs;
2172 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2173 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2174 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2176 if (Low.ule(TEI) && TEI.ule(High)) {
2177 DestBBs.push_back(I->BB);
2181 DestBBs.push_back(Default);
2185 // Calculate weight for each unique destination in CR.
2186 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2188 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2189 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2190 DestWeights.find(I->BB);
2191 if (Itr != DestWeights.end())
2192 Itr->second += I->ExtraWeight;
2194 DestWeights[I->BB] = I->ExtraWeight;
2197 // Update successor info. Add one edge to each unique successor.
2198 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2199 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2200 E = DestBBs.end(); I != E; ++I) {
2201 if (!SuccsHandled[(*I)->getNumber()]) {
2202 SuccsHandled[(*I)->getNumber()] = true;
2203 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2204 DestWeights.find(*I);
2205 addSuccessorWithWeight(JumpTableBB, *I,
2206 Itr != DestWeights.end() ? Itr->second : 0);
2210 // Create a jump table index for this jump table.
2211 unsigned JTEncoding = TLI.getJumpTableEncoding();
2212 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2213 ->createJumpTableIndex(DestBBs);
2215 // Set the jump table information so that we can codegen it as a second
2216 // MachineBasicBlock
2217 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2218 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2219 if (CR.CaseBB == SwitchBB)
2220 visitJumpTableHeader(JT, JTH, SwitchBB);
2222 JTCases.push_back(JumpTableBlock(JTH, JT));
2226 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2228 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2229 CaseRecVector& WorkList,
2231 MachineBasicBlock *Default,
2232 MachineBasicBlock *SwitchBB) {
2233 // Get the MachineFunction which holds the current MBB. This is used when
2234 // inserting any additional MBBs necessary to represent the switch.
2235 MachineFunction *CurMF = FuncInfo.MF;
2237 // Figure out which block is immediately after the current one.
2238 MachineFunction::iterator BBI = CR.CaseBB;
2241 Case& FrontCase = *CR.Range.first;
2242 Case& BackCase = *(CR.Range.second-1);
2243 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2245 // Size is the number of Cases represented by this range.
2246 unsigned Size = CR.Range.second - CR.Range.first;
2248 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2249 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2251 CaseItr Pivot = CR.Range.first + Size/2;
2253 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2254 // (heuristically) allow us to emit JumpTable's later.
2255 APInt TSize(First.getBitWidth(), 0);
2256 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2260 APInt LSize = FrontCase.size();
2261 APInt RSize = TSize-LSize;
2262 DEBUG(dbgs() << "Selecting best pivot: \n"
2263 << "First: " << First << ", Last: " << Last <<'\n'
2264 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2265 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2267 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2268 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2269 APInt Range = ComputeRange(LEnd, RBegin);
2270 assert((Range - 2ULL).isNonNegative() &&
2271 "Invalid case distance");
2272 // Use volatile double here to avoid excess precision issues on some hosts,
2273 // e.g. that use 80-bit X87 registers.
2274 volatile double LDensity =
2275 (double)LSize.roundToDouble() /
2276 (LEnd - First + 1ULL).roundToDouble();
2277 volatile double RDensity =
2278 (double)RSize.roundToDouble() /
2279 (Last - RBegin + 1ULL).roundToDouble();
2280 double Metric = Range.logBase2()*(LDensity+RDensity);
2281 // Should always split in some non-trivial place
2282 DEBUG(dbgs() <<"=>Step\n"
2283 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2284 << "LDensity: " << LDensity
2285 << ", RDensity: " << RDensity << '\n'
2286 << "Metric: " << Metric << '\n');
2287 if (FMetric < Metric) {
2290 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2296 if (areJTsAllowed(TLI)) {
2297 // If our case is dense we *really* should handle it earlier!
2298 assert((FMetric > 0) && "Should handle dense range earlier!");
2300 Pivot = CR.Range.first + Size/2;
2303 CaseRange LHSR(CR.Range.first, Pivot);
2304 CaseRange RHSR(Pivot, CR.Range.second);
2305 const Constant *C = Pivot->Low;
2306 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2308 // We know that we branch to the LHS if the Value being switched on is
2309 // less than the Pivot value, C. We use this to optimize our binary
2310 // tree a bit, by recognizing that if SV is greater than or equal to the
2311 // LHS's Case Value, and that Case Value is exactly one less than the
2312 // Pivot's Value, then we can branch directly to the LHS's Target,
2313 // rather than creating a leaf node for it.
2314 if ((LHSR.second - LHSR.first) == 1 &&
2315 LHSR.first->High == CR.GE &&
2316 cast<ConstantInt>(C)->getValue() ==
2317 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2318 TrueBB = LHSR.first->BB;
2320 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2321 CurMF->insert(BBI, TrueBB);
2322 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2324 // Put SV in a virtual register to make it available from the new blocks.
2325 ExportFromCurrentBlock(SV);
2328 // Similar to the optimization above, if the Value being switched on is
2329 // known to be less than the Constant CR.LT, and the current Case Value
2330 // is CR.LT - 1, then we can branch directly to the target block for
2331 // the current Case Value, rather than emitting a RHS leaf node for it.
2332 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2333 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2334 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2335 FalseBB = RHSR.first->BB;
2337 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2338 CurMF->insert(BBI, FalseBB);
2339 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2341 // Put SV in a virtual register to make it available from the new blocks.
2342 ExportFromCurrentBlock(SV);
2345 // Create a CaseBlock record representing a conditional branch to
2346 // the LHS node if the value being switched on SV is less than C.
2347 // Otherwise, branch to LHS.
2348 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2350 if (CR.CaseBB == SwitchBB)
2351 visitSwitchCase(CB, SwitchBB);
2353 SwitchCases.push_back(CB);
2358 /// handleBitTestsSwitchCase - if current case range has few destination and
2359 /// range span less, than machine word bitwidth, encode case range into series
2360 /// of masks and emit bit tests with these masks.
2361 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2362 CaseRecVector& WorkList,
2364 MachineBasicBlock* Default,
2365 MachineBasicBlock *SwitchBB){
2366 EVT PTy = TLI.getPointerTy();
2367 unsigned IntPtrBits = PTy.getSizeInBits();
2369 Case& FrontCase = *CR.Range.first;
2370 Case& BackCase = *(CR.Range.second-1);
2372 // Get the MachineFunction which holds the current MBB. This is used when
2373 // inserting any additional MBBs necessary to represent the switch.
2374 MachineFunction *CurMF = FuncInfo.MF;
2376 // If target does not have legal shift left, do not emit bit tests at all.
2377 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2381 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2383 // Single case counts one, case range - two.
2384 numCmps += (I->Low == I->High ? 1 : 2);
2387 // Count unique destinations
2388 SmallSet<MachineBasicBlock*, 4> Dests;
2389 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2390 Dests.insert(I->BB);
2391 if (Dests.size() > 3)
2392 // Don't bother the code below, if there are too much unique destinations
2395 DEBUG(dbgs() << "Total number of unique destinations: "
2396 << Dests.size() << '\n'
2397 << "Total number of comparisons: " << numCmps << '\n');
2399 // Compute span of values.
2400 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2401 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2402 APInt cmpRange = maxValue - minValue;
2404 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2405 << "Low bound: " << minValue << '\n'
2406 << "High bound: " << maxValue << '\n');
2408 if (cmpRange.uge(IntPtrBits) ||
2409 (!(Dests.size() == 1 && numCmps >= 3) &&
2410 !(Dests.size() == 2 && numCmps >= 5) &&
2411 !(Dests.size() >= 3 && numCmps >= 6)))
2414 DEBUG(dbgs() << "Emitting bit tests\n");
2415 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2417 // Optimize the case where all the case values fit in a
2418 // word without having to subtract minValue. In this case,
2419 // we can optimize away the subtraction.
2420 if (maxValue.ult(IntPtrBits)) {
2421 cmpRange = maxValue;
2423 lowBound = minValue;
2426 CaseBitsVector CasesBits;
2427 unsigned i, count = 0;
2429 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2430 MachineBasicBlock* Dest = I->BB;
2431 for (i = 0; i < count; ++i)
2432 if (Dest == CasesBits[i].BB)
2436 assert((count < 3) && "Too much destinations to test!");
2437 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2441 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2442 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2444 uint64_t lo = (lowValue - lowBound).getZExtValue();
2445 uint64_t hi = (highValue - lowBound).getZExtValue();
2446 CasesBits[i].ExtraWeight += I->ExtraWeight;
2448 for (uint64_t j = lo; j <= hi; j++) {
2449 CasesBits[i].Mask |= 1ULL << j;
2450 CasesBits[i].Bits++;
2454 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2458 // Figure out which block is immediately after the current one.
2459 MachineFunction::iterator BBI = CR.CaseBB;
2462 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2464 DEBUG(dbgs() << "Cases:\n");
2465 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2466 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2467 << ", Bits: " << CasesBits[i].Bits
2468 << ", BB: " << CasesBits[i].BB << '\n');
2470 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2471 CurMF->insert(BBI, CaseBB);
2472 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2474 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2476 // Put SV in a virtual register to make it available from the new blocks.
2477 ExportFromCurrentBlock(SV);
2480 BitTestBlock BTB(lowBound, cmpRange, SV,
2481 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2482 CR.CaseBB, Default, BTC);
2484 if (CR.CaseBB == SwitchBB)
2485 visitBitTestHeader(BTB, SwitchBB);
2487 BitTestCases.push_back(BTB);
2492 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2493 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2494 const SwitchInst& SI) {
2496 /// Use a shorter form of declaration, and also
2497 /// show the we want to use CRSBuilder as Clusterifier.
2498 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2500 Clusterifier TheClusterifier;
2502 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2503 // Start with "simple" cases
2504 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2506 const BasicBlock *SuccBB = i.getCaseSuccessor();
2507 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2509 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2510 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2513 TheClusterifier.optimize();
2516 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2517 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2518 Clusterifier::Cluster &C = *i;
2519 // Update edge weight for the cluster.
2520 unsigned W = C.first.Weight;
2522 // FIXME: Currently work with ConstantInt based numbers.
2523 // Changing it to APInt based is a pretty heavy for this commit.
2524 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2525 C.first.getHigh().toConstantInt(), C.second, W));
2527 if (C.first.getLow() != C.first.getHigh())
2528 // A range counts double, since it requires two compares.
2535 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2536 MachineBasicBlock *Last) {
2538 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2539 if (JTCases[i].first.HeaderBB == First)
2540 JTCases[i].first.HeaderBB = Last;
2542 // Update BitTestCases.
2543 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2544 if (BitTestCases[i].Parent == First)
2545 BitTestCases[i].Parent = Last;
2548 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2549 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2551 // Figure out which block is immediately after the current one.
2552 MachineBasicBlock *NextBlock = 0;
2553 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2555 // If there is only the default destination, branch to it if it is not the
2556 // next basic block. Otherwise, just fall through.
2557 if (!SI.getNumCases()) {
2558 // Update machine-CFG edges.
2560 // If this is not a fall-through branch, emit the branch.
2561 SwitchMBB->addSuccessor(Default);
2562 if (Default != NextBlock)
2563 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2564 MVT::Other, getControlRoot(),
2565 DAG.getBasicBlock(Default)));
2570 // If there are any non-default case statements, create a vector of Cases
2571 // representing each one, and sort the vector so that we can efficiently
2572 // create a binary search tree from them.
2574 size_t numCmps = Clusterify(Cases, SI);
2575 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2576 << ". Total compares: " << numCmps << '\n');
2579 // Get the Value to be switched on and default basic blocks, which will be
2580 // inserted into CaseBlock records, representing basic blocks in the binary
2582 const Value *SV = SI.getCondition();
2584 // Push the initial CaseRec onto the worklist
2585 CaseRecVector WorkList;
2586 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2587 CaseRange(Cases.begin(),Cases.end())));
2589 while (!WorkList.empty()) {
2590 // Grab a record representing a case range to process off the worklist
2591 CaseRec CR = WorkList.back();
2592 WorkList.pop_back();
2594 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2597 // If the range has few cases (two or less) emit a series of specific
2599 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2602 // If the switch has more than N blocks, and is at least 40% dense, and the
2603 // target supports indirect branches, then emit a jump table rather than
2604 // lowering the switch to a binary tree of conditional branches.
2605 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2606 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2609 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2610 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2611 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2615 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2616 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2618 // Update machine-CFG edges with unique successors.
2619 SmallSet<BasicBlock*, 32> Done;
2620 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2621 BasicBlock *BB = I.getSuccessor(i);
2622 bool Inserted = Done.insert(BB);
2626 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2627 addSuccessorWithWeight(IndirectBrMBB, Succ);
2630 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2631 MVT::Other, getControlRoot(),
2632 getValue(I.getAddress())));
2635 void SelectionDAGBuilder::visitFSub(const User &I) {
2636 // -0.0 - X --> fneg
2637 Type *Ty = I.getType();
2638 if (isa<Constant>(I.getOperand(0)) &&
2639 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2640 SDValue Op2 = getValue(I.getOperand(1));
2641 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2642 Op2.getValueType(), Op2));
2646 visitBinary(I, ISD::FSUB);
2649 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2650 SDValue Op1 = getValue(I.getOperand(0));
2651 SDValue Op2 = getValue(I.getOperand(1));
2652 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2653 Op1.getValueType(), Op1, Op2));
2656 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2657 SDValue Op1 = getValue(I.getOperand(0));
2658 SDValue Op2 = getValue(I.getOperand(1));
2660 EVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2662 // Coerce the shift amount to the right type if we can.
2663 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2664 unsigned ShiftSize = ShiftTy.getSizeInBits();
2665 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2666 DebugLoc DL = getCurDebugLoc();
2668 // If the operand is smaller than the shift count type, promote it.
2669 if (ShiftSize > Op2Size)
2670 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2672 // If the operand is larger than the shift count type but the shift
2673 // count type has enough bits to represent any shift value, truncate
2674 // it now. This is a common case and it exposes the truncate to
2675 // optimization early.
2676 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2677 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2678 // Otherwise we'll need to temporarily settle for some other convenient
2679 // type. Type legalization will make adjustments once the shiftee is split.
2681 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2684 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2685 Op1.getValueType(), Op1, Op2));
2688 void SelectionDAGBuilder::visitSDiv(const User &I) {
2689 SDValue Op1 = getValue(I.getOperand(0));
2690 SDValue Op2 = getValue(I.getOperand(1));
2692 // Turn exact SDivs into multiplications.
2693 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2695 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2696 !isa<ConstantSDNode>(Op1) &&
2697 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2698 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2700 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2704 void SelectionDAGBuilder::visitICmp(const User &I) {
2705 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2706 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2707 predicate = IC->getPredicate();
2708 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2709 predicate = ICmpInst::Predicate(IC->getPredicate());
2710 SDValue Op1 = getValue(I.getOperand(0));
2711 SDValue Op2 = getValue(I.getOperand(1));
2712 ISD::CondCode Opcode = getICmpCondCode(predicate);
2714 EVT DestVT = TLI.getValueType(I.getType());
2715 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2718 void SelectionDAGBuilder::visitFCmp(const User &I) {
2719 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2720 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2721 predicate = FC->getPredicate();
2722 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2723 predicate = FCmpInst::Predicate(FC->getPredicate());
2724 SDValue Op1 = getValue(I.getOperand(0));
2725 SDValue Op2 = getValue(I.getOperand(1));
2726 ISD::CondCode Condition = getFCmpCondCode(predicate);
2727 if (TM.Options.NoNaNsFPMath)
2728 Condition = getFCmpCodeWithoutNaN(Condition);
2729 EVT DestVT = TLI.getValueType(I.getType());
2730 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2733 void SelectionDAGBuilder::visitSelect(const User &I) {
2734 SmallVector<EVT, 4> ValueVTs;
2735 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2736 unsigned NumValues = ValueVTs.size();
2737 if (NumValues == 0) return;
2739 SmallVector<SDValue, 4> Values(NumValues);
2740 SDValue Cond = getValue(I.getOperand(0));
2741 SDValue TrueVal = getValue(I.getOperand(1));
2742 SDValue FalseVal = getValue(I.getOperand(2));
2743 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2744 ISD::VSELECT : ISD::SELECT;
2746 for (unsigned i = 0; i != NumValues; ++i)
2747 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2748 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2750 SDValue(TrueVal.getNode(),
2751 TrueVal.getResNo() + i),
2752 SDValue(FalseVal.getNode(),
2753 FalseVal.getResNo() + i));
2755 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2756 DAG.getVTList(&ValueVTs[0], NumValues),
2757 &Values[0], NumValues));
2760 void SelectionDAGBuilder::visitTrunc(const User &I) {
2761 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2762 SDValue N = getValue(I.getOperand(0));
2763 EVT DestVT = TLI.getValueType(I.getType());
2764 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2767 void SelectionDAGBuilder::visitZExt(const User &I) {
2768 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2769 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2770 SDValue N = getValue(I.getOperand(0));
2771 EVT DestVT = TLI.getValueType(I.getType());
2772 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2775 void SelectionDAGBuilder::visitSExt(const User &I) {
2776 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2777 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2778 SDValue N = getValue(I.getOperand(0));
2779 EVT DestVT = TLI.getValueType(I.getType());
2780 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2783 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2784 // FPTrunc is never a no-op cast, no need to check
2785 SDValue N = getValue(I.getOperand(0));
2786 EVT DestVT = TLI.getValueType(I.getType());
2787 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2789 DAG.getTargetConstant(0, TLI.getPointerTy())));
2792 void SelectionDAGBuilder::visitFPExt(const User &I){
2793 // FPExt is never a no-op cast, no need to check
2794 SDValue N = getValue(I.getOperand(0));
2795 EVT DestVT = TLI.getValueType(I.getType());
2796 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2799 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2800 // FPToUI is never a no-op cast, no need to check
2801 SDValue N = getValue(I.getOperand(0));
2802 EVT DestVT = TLI.getValueType(I.getType());
2803 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2806 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2807 // FPToSI is never a no-op cast, no need to check
2808 SDValue N = getValue(I.getOperand(0));
2809 EVT DestVT = TLI.getValueType(I.getType());
2810 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2813 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2814 // UIToFP is never a no-op cast, no need to check
2815 SDValue N = getValue(I.getOperand(0));
2816 EVT DestVT = TLI.getValueType(I.getType());
2817 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2820 void SelectionDAGBuilder::visitSIToFP(const User &I){
2821 // SIToFP is never a no-op cast, no need to check
2822 SDValue N = getValue(I.getOperand(0));
2823 EVT DestVT = TLI.getValueType(I.getType());
2824 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2827 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2828 // What to do depends on the size of the integer and the size of the pointer.
2829 // We can either truncate, zero extend, or no-op, accordingly.
2830 SDValue N = getValue(I.getOperand(0));
2831 EVT DestVT = TLI.getValueType(I.getType());
2832 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2835 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2836 // What to do depends on the size of the integer and the size of the pointer.
2837 // We can either truncate, zero extend, or no-op, accordingly.
2838 SDValue N = getValue(I.getOperand(0));
2839 EVT DestVT = TLI.getValueType(I.getType());
2840 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2843 void SelectionDAGBuilder::visitBitCast(const User &I) {
2844 SDValue N = getValue(I.getOperand(0));
2845 EVT DestVT = TLI.getValueType(I.getType());
2847 // BitCast assures us that source and destination are the same size so this is
2848 // either a BITCAST or a no-op.
2849 if (DestVT != N.getValueType())
2850 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2851 DestVT, N)); // convert types.
2853 setValue(&I, N); // noop cast.
2856 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2857 SDValue InVec = getValue(I.getOperand(0));
2858 SDValue InVal = getValue(I.getOperand(1));
2859 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2861 getValue(I.getOperand(2)));
2862 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2863 TLI.getValueType(I.getType()),
2864 InVec, InVal, InIdx));
2867 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2868 SDValue InVec = getValue(I.getOperand(0));
2869 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2871 getValue(I.getOperand(1)));
2872 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2873 TLI.getValueType(I.getType()), InVec, InIdx));
2876 // Utility for visitShuffleVector - Return true if every element in Mask,
2877 // beginning from position Pos and ending in Pos+Size, falls within the
2878 // specified sequential range [L, L+Pos). or is undef.
2879 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2880 unsigned Pos, unsigned Size, int Low) {
2881 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2882 if (Mask[i] >= 0 && Mask[i] != Low)
2887 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2888 SDValue Src1 = getValue(I.getOperand(0));
2889 SDValue Src2 = getValue(I.getOperand(1));
2891 SmallVector<int, 8> Mask;
2892 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2893 unsigned MaskNumElts = Mask.size();
2895 EVT VT = TLI.getValueType(I.getType());
2896 EVT SrcVT = Src1.getValueType();
2897 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2899 if (SrcNumElts == MaskNumElts) {
2900 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2905 // Normalize the shuffle vector since mask and vector length don't match.
2906 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2907 // Mask is longer than the source vectors and is a multiple of the source
2908 // vectors. We can use concatenate vector to make the mask and vectors
2910 if (SrcNumElts*2 == MaskNumElts) {
2911 // First check for Src1 in low and Src2 in high
2912 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2913 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2914 // The shuffle is concatenating two vectors together.
2915 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2919 // Then check for Src2 in low and Src1 in high
2920 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2921 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2922 // The shuffle is concatenating two vectors together.
2923 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2929 // Pad both vectors with undefs to make them the same length as the mask.
2930 unsigned NumConcat = MaskNumElts / SrcNumElts;
2931 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2932 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2933 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2935 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2936 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2940 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2941 getCurDebugLoc(), VT,
2942 &MOps1[0], NumConcat);
2943 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2944 getCurDebugLoc(), VT,
2945 &MOps2[0], NumConcat);
2947 // Readjust mask for new input vector length.
2948 SmallVector<int, 8> MappedOps;
2949 for (unsigned i = 0; i != MaskNumElts; ++i) {
2951 if (Idx >= (int)SrcNumElts)
2952 Idx -= SrcNumElts - MaskNumElts;
2953 MappedOps.push_back(Idx);
2956 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2961 if (SrcNumElts > MaskNumElts) {
2962 // Analyze the access pattern of the vector to see if we can extract
2963 // two subvectors and do the shuffle. The analysis is done by calculating
2964 // the range of elements the mask access on both vectors.
2965 int MinRange[2] = { static_cast<int>(SrcNumElts),
2966 static_cast<int>(SrcNumElts)};
2967 int MaxRange[2] = {-1, -1};
2969 for (unsigned i = 0; i != MaskNumElts; ++i) {
2975 if (Idx >= (int)SrcNumElts) {
2979 if (Idx > MaxRange[Input])
2980 MaxRange[Input] = Idx;
2981 if (Idx < MinRange[Input])
2982 MinRange[Input] = Idx;
2985 // Check if the access is smaller than the vector size and can we find
2986 // a reasonable extract index.
2987 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2989 int StartIdx[2]; // StartIdx to extract from
2990 for (unsigned Input = 0; Input < 2; ++Input) {
2991 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2992 RangeUse[Input] = 0; // Unused
2993 StartIdx[Input] = 0;
2997 // Find a good start index that is a multiple of the mask length. Then
2998 // see if the rest of the elements are in range.
2999 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3000 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3001 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3002 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3005 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3006 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3009 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3010 // Extract appropriate subvector and generate a vector shuffle
3011 for (unsigned Input = 0; Input < 2; ++Input) {
3012 SDValue &Src = Input == 0 ? Src1 : Src2;
3013 if (RangeUse[Input] == 0)
3014 Src = DAG.getUNDEF(VT);
3016 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
3017 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3020 // Calculate new mask.
3021 SmallVector<int, 8> MappedOps;
3022 for (unsigned i = 0; i != MaskNumElts; ++i) {
3025 if (Idx < (int)SrcNumElts)
3028 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3030 MappedOps.push_back(Idx);
3033 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
3039 // We can't use either concat vectors or extract subvectors so fall back to
3040 // replacing the shuffle with extract and build vector.
3041 // to insert and build vector.
3042 EVT EltVT = VT.getVectorElementType();
3043 EVT PtrVT = TLI.getPointerTy();
3044 SmallVector<SDValue,8> Ops;
3045 for (unsigned i = 0; i != MaskNumElts; ++i) {
3050 Res = DAG.getUNDEF(EltVT);
3052 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3053 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3055 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
3056 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3062 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
3063 VT, &Ops[0], Ops.size()));
3066 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3067 const Value *Op0 = I.getOperand(0);
3068 const Value *Op1 = I.getOperand(1);
3069 Type *AggTy = I.getType();
3070 Type *ValTy = Op1->getType();
3071 bool IntoUndef = isa<UndefValue>(Op0);
3072 bool FromUndef = isa<UndefValue>(Op1);
3074 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3076 SmallVector<EVT, 4> AggValueVTs;
3077 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3078 SmallVector<EVT, 4> ValValueVTs;
3079 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3081 unsigned NumAggValues = AggValueVTs.size();
3082 unsigned NumValValues = ValValueVTs.size();
3083 SmallVector<SDValue, 4> Values(NumAggValues);
3085 SDValue Agg = getValue(Op0);
3087 // Copy the beginning value(s) from the original aggregate.
3088 for (; i != LinearIndex; ++i)
3089 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3090 SDValue(Agg.getNode(), Agg.getResNo() + i);
3091 // Copy values from the inserted value(s).
3093 SDValue Val = getValue(Op1);
3094 for (; i != LinearIndex + NumValValues; ++i)
3095 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3096 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3098 // Copy remaining value(s) from the original aggregate.
3099 for (; i != NumAggValues; ++i)
3100 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3101 SDValue(Agg.getNode(), Agg.getResNo() + i);
3103 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3104 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3105 &Values[0], NumAggValues));
3108 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3109 const Value *Op0 = I.getOperand(0);
3110 Type *AggTy = Op0->getType();
3111 Type *ValTy = I.getType();
3112 bool OutOfUndef = isa<UndefValue>(Op0);
3114 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3116 SmallVector<EVT, 4> ValValueVTs;
3117 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3119 unsigned NumValValues = ValValueVTs.size();
3121 // Ignore a extractvalue that produces an empty object
3122 if (!NumValValues) {
3123 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3127 SmallVector<SDValue, 4> Values(NumValValues);
3129 SDValue Agg = getValue(Op0);
3130 // Copy out the selected value(s).
3131 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3132 Values[i - LinearIndex] =
3134 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3135 SDValue(Agg.getNode(), Agg.getResNo() + i);
3137 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3138 DAG.getVTList(&ValValueVTs[0], NumValValues),
3139 &Values[0], NumValValues));
3142 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3143 SDValue N = getValue(I.getOperand(0));
3144 // Note that the pointer operand may be a vector of pointers. Take the scalar
3145 // element which holds a pointer.
3146 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3148 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3150 const Value *Idx = *OI;
3151 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3152 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3155 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3156 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3157 DAG.getConstant(Offset, N.getValueType()));
3160 Ty = StTy->getElementType(Field);
3162 Ty = cast<SequentialType>(Ty)->getElementType();
3164 // If this is a constant subscript, handle it quickly.
3165 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3166 if (CI->isZero()) continue;
3168 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3170 EVT PTy = TLI.getPointerTy();
3171 unsigned PtrBits = PTy.getSizeInBits();
3173 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3175 DAG.getConstant(Offs, MVT::i64));
3177 OffsVal = DAG.getIntPtrConstant(Offs);
3179 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3184 // N = N + Idx * ElementSize;
3185 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3186 TD->getTypeAllocSize(Ty));
3187 SDValue IdxN = getValue(Idx);
3189 // If the index is smaller or larger than intptr_t, truncate or extend
3191 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3193 // If this is a multiply by a power of two, turn it into a shl
3194 // immediately. This is a very common case.
3195 if (ElementSize != 1) {
3196 if (ElementSize.isPowerOf2()) {
3197 unsigned Amt = ElementSize.logBase2();
3198 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3199 N.getValueType(), IdxN,
3200 DAG.getConstant(Amt, IdxN.getValueType()));
3202 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3203 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3204 N.getValueType(), IdxN, Scale);
3208 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3209 N.getValueType(), N, IdxN);
3216 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3217 // If this is a fixed sized alloca in the entry block of the function,
3218 // allocate it statically on the stack.
3219 if (FuncInfo.StaticAllocaMap.count(&I))
3220 return; // getValue will auto-populate this.
3222 Type *Ty = I.getAllocatedType();
3223 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3225 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3228 SDValue AllocSize = getValue(I.getArraySize());
3230 EVT IntPtr = TLI.getPointerTy();
3231 if (AllocSize.getValueType() != IntPtr)
3232 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3234 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3236 DAG.getConstant(TySize, IntPtr));
3238 // Handle alignment. If the requested alignment is less than or equal to
3239 // the stack alignment, ignore it. If the size is greater than or equal to
3240 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3241 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3242 if (Align <= StackAlign)
3245 // Round the size of the allocation up to the stack alignment size
3246 // by add SA-1 to the size.
3247 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3248 AllocSize.getValueType(), AllocSize,
3249 DAG.getIntPtrConstant(StackAlign-1));
3251 // Mask out the low bits for alignment purposes.
3252 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3253 AllocSize.getValueType(), AllocSize,
3254 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3256 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3257 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3258 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3261 DAG.setRoot(DSA.getValue(1));
3263 // Inform the Frame Information that we have just allocated a variable-sized
3265 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3268 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3270 return visitAtomicLoad(I);
3272 const Value *SV = I.getOperand(0);
3273 SDValue Ptr = getValue(SV);
3275 Type *Ty = I.getType();
3277 bool isVolatile = I.isVolatile();
3278 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3279 bool isInvariant = I.getMetadata("invariant.load") != 0;
3280 unsigned Alignment = I.getAlignment();
3281 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3282 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3284 SmallVector<EVT, 4> ValueVTs;
3285 SmallVector<uint64_t, 4> Offsets;
3286 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3287 unsigned NumValues = ValueVTs.size();
3292 bool ConstantMemory = false;
3293 if (I.isVolatile() || NumValues > MaxParallelChains)
3294 // Serialize volatile loads with other side effects.
3296 else if (AA->pointsToConstantMemory(
3297 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3298 // Do not serialize (non-volatile) loads of constant memory with anything.
3299 Root = DAG.getEntryNode();
3300 ConstantMemory = true;
3302 // Do not serialize non-volatile loads against each other.
3303 Root = DAG.getRoot();
3306 SmallVector<SDValue, 4> Values(NumValues);
3307 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3309 EVT PtrVT = Ptr.getValueType();
3310 unsigned ChainI = 0;
3311 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3312 // Serializing loads here may result in excessive register pressure, and
3313 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3314 // could recover a bit by hoisting nodes upward in the chain by recognizing
3315 // they are side-effect free or do not alias. The optimizer should really
3316 // avoid this case by converting large object/array copies to llvm.memcpy
3317 // (MaxParallelChains should always remain as failsafe).
3318 if (ChainI == MaxParallelChains) {
3319 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3321 MVT::Other, &Chains[0], ChainI);
3325 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3327 DAG.getConstant(Offsets[i], PtrVT));
3328 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3329 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3330 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3334 Chains[ChainI] = L.getValue(1);
3337 if (!ConstantMemory) {
3338 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3339 MVT::Other, &Chains[0], ChainI);
3343 PendingLoads.push_back(Chain);
3346 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3347 DAG.getVTList(&ValueVTs[0], NumValues),
3348 &Values[0], NumValues));
3351 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3353 return visitAtomicStore(I);
3355 const Value *SrcV = I.getOperand(0);
3356 const Value *PtrV = I.getOperand(1);
3358 SmallVector<EVT, 4> ValueVTs;
3359 SmallVector<uint64_t, 4> Offsets;
3360 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3361 unsigned NumValues = ValueVTs.size();
3365 // Get the lowered operands. Note that we do this after
3366 // checking if NumResults is zero, because with zero results
3367 // the operands won't have values in the map.
3368 SDValue Src = getValue(SrcV);
3369 SDValue Ptr = getValue(PtrV);
3371 SDValue Root = getRoot();
3372 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3374 EVT PtrVT = Ptr.getValueType();
3375 bool isVolatile = I.isVolatile();
3376 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3377 unsigned Alignment = I.getAlignment();
3378 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3380 unsigned ChainI = 0;
3381 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3382 // See visitLoad comments.
3383 if (ChainI == MaxParallelChains) {
3384 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3385 MVT::Other, &Chains[0], ChainI);
3389 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3390 DAG.getConstant(Offsets[i], PtrVT));
3391 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3392 SDValue(Src.getNode(), Src.getResNo() + i),
3393 Add, MachinePointerInfo(PtrV, Offsets[i]),
3394 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3395 Chains[ChainI] = St;
3398 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3399 MVT::Other, &Chains[0], ChainI);
3401 AssignOrderingToNode(StoreNode.getNode());
3402 DAG.setRoot(StoreNode);
3405 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3406 SynchronizationScope Scope,
3407 bool Before, DebugLoc dl,
3409 const TargetLowering &TLI) {
3410 // Fence, if necessary
3412 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3414 else if (Order == Acquire || Order == Monotonic)
3417 if (Order == AcquireRelease)
3419 else if (Order == Release || Order == Monotonic)
3424 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3425 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3426 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3429 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3430 DebugLoc dl = getCurDebugLoc();
3431 AtomicOrdering Order = I.getOrdering();
3432 SynchronizationScope Scope = I.getSynchScope();
3434 SDValue InChain = getRoot();
3436 if (TLI.getInsertFencesForAtomic())
3437 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3441 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3442 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3444 getValue(I.getPointerOperand()),
3445 getValue(I.getCompareOperand()),
3446 getValue(I.getNewValOperand()),
3447 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3448 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3451 SDValue OutChain = L.getValue(1);
3453 if (TLI.getInsertFencesForAtomic())
3454 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3458 DAG.setRoot(OutChain);
3461 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3462 DebugLoc dl = getCurDebugLoc();
3464 switch (I.getOperation()) {
3465 default: llvm_unreachable("Unknown atomicrmw operation");
3466 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3467 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3468 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3469 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3470 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3471 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3472 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3473 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3474 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3475 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3476 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3478 AtomicOrdering Order = I.getOrdering();
3479 SynchronizationScope Scope = I.getSynchScope();
3481 SDValue InChain = getRoot();
3483 if (TLI.getInsertFencesForAtomic())
3484 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3488 DAG.getAtomic(NT, dl,
3489 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3491 getValue(I.getPointerOperand()),
3492 getValue(I.getValOperand()),
3493 I.getPointerOperand(), 0 /* Alignment */,
3494 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3497 SDValue OutChain = L.getValue(1);
3499 if (TLI.getInsertFencesForAtomic())
3500 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3504 DAG.setRoot(OutChain);
3507 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3508 DebugLoc dl = getCurDebugLoc();
3511 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3512 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3513 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3516 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3517 DebugLoc dl = getCurDebugLoc();
3518 AtomicOrdering Order = I.getOrdering();
3519 SynchronizationScope Scope = I.getSynchScope();
3521 SDValue InChain = getRoot();
3523 EVT VT = TLI.getValueType(I.getType());
3525 if (I.getAlignment() < VT.getSizeInBits() / 8)
3526 report_fatal_error("Cannot generate unaligned atomic load");
3529 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3530 getValue(I.getPointerOperand()),
3531 I.getPointerOperand(), I.getAlignment(),
3532 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3535 SDValue OutChain = L.getValue(1);
3537 if (TLI.getInsertFencesForAtomic())
3538 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3542 DAG.setRoot(OutChain);
3545 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3546 DebugLoc dl = getCurDebugLoc();
3548 AtomicOrdering Order = I.getOrdering();
3549 SynchronizationScope Scope = I.getSynchScope();
3551 SDValue InChain = getRoot();
3553 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3555 if (I.getAlignment() < VT.getSizeInBits() / 8)
3556 report_fatal_error("Cannot generate unaligned atomic store");
3558 if (TLI.getInsertFencesForAtomic())
3559 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3563 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3565 getValue(I.getPointerOperand()),
3566 getValue(I.getValueOperand()),
3567 I.getPointerOperand(), I.getAlignment(),
3568 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3571 if (TLI.getInsertFencesForAtomic())
3572 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3575 DAG.setRoot(OutChain);
3578 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3580 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3581 unsigned Intrinsic) {
3582 bool HasChain = !I.doesNotAccessMemory();
3583 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3585 // Build the operand list.
3586 SmallVector<SDValue, 8> Ops;
3587 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3589 // We don't need to serialize loads against other loads.
3590 Ops.push_back(DAG.getRoot());
3592 Ops.push_back(getRoot());
3596 // Info is set by getTgtMemInstrinsic
3597 TargetLowering::IntrinsicInfo Info;
3598 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3600 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3601 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3602 Info.opc == ISD::INTRINSIC_W_CHAIN)
3603 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3605 // Add all operands of the call to the operand list.
3606 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3607 SDValue Op = getValue(I.getArgOperand(i));
3611 SmallVector<EVT, 4> ValueVTs;
3612 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3615 ValueVTs.push_back(MVT::Other);
3617 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3621 if (IsTgtIntrinsic) {
3622 // This is target intrinsic that touches memory
3623 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3624 VTs, &Ops[0], Ops.size(),
3626 MachinePointerInfo(Info.ptrVal, Info.offset),
3627 Info.align, Info.vol,
3628 Info.readMem, Info.writeMem);
3629 } else if (!HasChain) {
3630 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3631 VTs, &Ops[0], Ops.size());
3632 } else if (!I.getType()->isVoidTy()) {
3633 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3634 VTs, &Ops[0], Ops.size());
3636 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3637 VTs, &Ops[0], Ops.size());
3641 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3643 PendingLoads.push_back(Chain);
3648 if (!I.getType()->isVoidTy()) {
3649 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3650 EVT VT = TLI.getValueType(PTy);
3651 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3654 setValue(&I, Result);
3656 // Assign order to result here. If the intrinsic does not produce a result,
3657 // it won't be mapped to a SDNode and visit() will not assign it an order
3660 AssignOrderingToNode(Result.getNode());
3664 /// GetSignificand - Get the significand and build it into a floating-point
3665 /// number with exponent of 1:
3667 /// Op = (Op & 0x007fffff) | 0x3f800000;
3669 /// where Op is the hexadecimal representation of floating point value.
3671 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3672 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3673 DAG.getConstant(0x007fffff, MVT::i32));
3674 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3675 DAG.getConstant(0x3f800000, MVT::i32));
3676 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3679 /// GetExponent - Get the exponent:
3681 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3683 /// where Op is the hexadecimal representation of floating point value.
3685 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3687 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3688 DAG.getConstant(0x7f800000, MVT::i32));
3689 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3690 DAG.getConstant(23, TLI.getPointerTy()));
3691 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3692 DAG.getConstant(127, MVT::i32));
3693 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3696 /// getF32Constant - Get 32-bit floating point constant.
3698 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3699 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3703 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3704 /// limited-precision mode.
3705 static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3706 const TargetLowering &TLI) {
3707 if (Op.getValueType() == MVT::f32 &&
3708 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3710 // Put the exponent in the right bit position for later addition to the
3713 // #define LOG2OFe 1.4426950f
3714 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3715 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3716 getF32Constant(DAG, 0x3fb8aa3b));
3717 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3719 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3720 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3721 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3723 // IntegerPartOfX <<= 23;
3724 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3725 DAG.getConstant(23, TLI.getPointerTy()));
3727 SDValue TwoToFracPartOfX;
3728 if (LimitFloatPrecision <= 6) {
3729 // For floating-point precision of 6:
3731 // TwoToFractionalPartOfX =
3733 // (0.735607626f + 0.252464424f * x) * x;
3735 // error 0.0144103317, which is 6 bits
3736 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3737 getF32Constant(DAG, 0x3e814304));
3738 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3739 getF32Constant(DAG, 0x3f3c50c8));
3740 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3741 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3742 getF32Constant(DAG, 0x3f7f5e7e));
3743 } else if (LimitFloatPrecision <= 12) {
3744 // For floating-point precision of 12:
3746 // TwoToFractionalPartOfX =
3749 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3751 // 0.000107046256 error, which is 13 to 14 bits
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0x3da235e3));
3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3e65b8f3));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x3f324b07));
3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3760 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3761 getF32Constant(DAG, 0x3f7ff8fd));
3762 } else { // LimitFloatPrecision <= 18
3763 // For floating-point precision of 18:
3765 // TwoToFractionalPartOfX =
3769 // (0.554906021e-1f +
3770 // (0.961591928e-2f +
3771 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3773 // error 2.47208000*10^(-7), which is better than 18 bits
3774 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3775 getF32Constant(DAG, 0x3924b03e));
3776 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3777 getF32Constant(DAG, 0x3ab24b87));
3778 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3779 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3780 getF32Constant(DAG, 0x3c1d8c17));
3781 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3782 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3783 getF32Constant(DAG, 0x3d634a1d));
3784 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3785 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3786 getF32Constant(DAG, 0x3e75fe14));
3787 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3788 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3789 getF32Constant(DAG, 0x3f317234));
3790 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3791 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3792 getF32Constant(DAG, 0x3f800000));
3795 // Add the exponent into the result in integer domain.
3796 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3797 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3798 DAG.getNode(ISD::ADD, dl, MVT::i32,
3799 t13, IntegerPartOfX));
3802 // No special expansion.
3803 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3806 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3807 /// limited-precision mode.
3808 static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3809 const TargetLowering &TLI) {
3810 if (Op.getValueType() == MVT::f32 &&
3811 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3812 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3814 // Scale the exponent by log(2) [0.69314718f].
3815 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3816 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3817 getF32Constant(DAG, 0x3f317218));
3819 // Get the significand and build it into a floating-point number with
3821 SDValue X = GetSignificand(DAG, Op1, dl);
3823 SDValue LogOfMantissa;
3824 if (LimitFloatPrecision <= 6) {
3825 // For floating-point precision of 6:
3829 // (1.4034025f - 0.23903021f * x) * x;
3831 // error 0.0034276066, which is better than 8 bits
3832 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3833 getF32Constant(DAG, 0xbe74c456));
3834 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3835 getF32Constant(DAG, 0x3fb3a2b1));
3836 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3837 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3838 getF32Constant(DAG, 0x3f949a29));
3839 } else if (LimitFloatPrecision <= 12) {
3840 // For floating-point precision of 12:
3846 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3848 // error 0.000061011436, which is 14 bits
3849 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3850 getF32Constant(DAG, 0xbd67b6d6));
3851 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3852 getF32Constant(DAG, 0x3ee4f4b8));
3853 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3854 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3855 getF32Constant(DAG, 0x3fbc278b));
3856 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3857 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3858 getF32Constant(DAG, 0x40348e95));
3859 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3860 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3861 getF32Constant(DAG, 0x3fdef31a));
3862 } else { // LimitFloatPrecision <= 18
3863 // For floating-point precision of 18:
3871 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3873 // error 0.0000023660568, which is better than 18 bits
3874 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3875 getF32Constant(DAG, 0xbc91e5ac));
3876 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3877 getF32Constant(DAG, 0x3e4350aa));
3878 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3879 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3880 getF32Constant(DAG, 0x3f60d3e3));
3881 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3882 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3883 getF32Constant(DAG, 0x4011cdf0));
3884 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3885 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3886 getF32Constant(DAG, 0x406cfd1c));
3887 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3888 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3889 getF32Constant(DAG, 0x408797cb));
3890 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3891 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3892 getF32Constant(DAG, 0x4006dcab));
3895 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3898 // No special expansion.
3899 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3902 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3903 /// limited-precision mode.
3904 static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3905 const TargetLowering &TLI) {
3906 if (Op.getValueType() == MVT::f32 &&
3907 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3908 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3910 // Get the exponent.
3911 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3913 // Get the significand and build it into a floating-point number with
3915 SDValue X = GetSignificand(DAG, Op1, dl);
3917 // Different possible minimax approximations of significand in
3918 // floating-point for various degrees of accuracy over [1,2].
3919 SDValue Log2ofMantissa;
3920 if (LimitFloatPrecision <= 6) {
3921 // For floating-point precision of 6:
3923 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3925 // error 0.0049451742, which is more than 7 bits
3926 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3927 getF32Constant(DAG, 0xbeb08fe0));
3928 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3929 getF32Constant(DAG, 0x40019463));
3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3931 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3932 getF32Constant(DAG, 0x3fd6633d));
3933 } else if (LimitFloatPrecision <= 12) {
3934 // For floating-point precision of 12:
3940 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3942 // error 0.0000876136000, which is better than 13 bits
3943 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3944 getF32Constant(DAG, 0xbda7262e));
3945 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3946 getF32Constant(DAG, 0x3f25280b));
3947 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3948 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3949 getF32Constant(DAG, 0x4007b923));
3950 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3951 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3952 getF32Constant(DAG, 0x40823e2f));
3953 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3954 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3955 getF32Constant(DAG, 0x4020d29c));
3956 } else { // LimitFloatPrecision <= 18
3957 // For floating-point precision of 18:
3966 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3968 // error 0.0000018516, which is better than 18 bits
3969 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3970 getF32Constant(DAG, 0xbcd2769e));
3971 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3972 getF32Constant(DAG, 0x3e8ce0b9));
3973 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3974 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3975 getF32Constant(DAG, 0x3fa22ae7));
3976 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3977 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3978 getF32Constant(DAG, 0x40525723));
3979 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3980 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3981 getF32Constant(DAG, 0x40aaf200));
3982 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3983 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3984 getF32Constant(DAG, 0x40c39dad));
3985 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3986 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3987 getF32Constant(DAG, 0x4042902c));
3990 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3993 // No special expansion.
3994 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3997 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3998 /// limited-precision mode.
3999 static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
4000 const TargetLowering &TLI) {
4001 if (Op.getValueType() == MVT::f32 &&
4002 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4003 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4005 // Scale the exponent by log10(2) [0.30102999f].
4006 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4007 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4008 getF32Constant(DAG, 0x3e9a209a));
4010 // Get the significand and build it into a floating-point number with
4012 SDValue X = GetSignificand(DAG, Op1, dl);
4014 SDValue Log10ofMantissa;
4015 if (LimitFloatPrecision <= 6) {
4016 // For floating-point precision of 6:
4018 // Log10ofMantissa =
4020 // (0.60948995f - 0.10380950f * x) * x;
4022 // error 0.0014886165, which is 6 bits
4023 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4024 getF32Constant(DAG, 0xbdd49a13));
4025 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4026 getF32Constant(DAG, 0x3f1c0789));
4027 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4028 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4029 getF32Constant(DAG, 0x3f011300));
4030 } else if (LimitFloatPrecision <= 12) {
4031 // For floating-point precision of 12:
4033 // Log10ofMantissa =
4036 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4038 // error 0.00019228036, which is better than 12 bits
4039 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4040 getF32Constant(DAG, 0x3d431f31));
4041 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4042 getF32Constant(DAG, 0x3ea21fb2));
4043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4044 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4045 getF32Constant(DAG, 0x3f6ae232));
4046 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4047 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4048 getF32Constant(DAG, 0x3f25f7c3));
4049 } else { // LimitFloatPrecision <= 18
4050 // For floating-point precision of 18:
4052 // Log10ofMantissa =
4057 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4059 // error 0.0000037995730, which is better than 18 bits
4060 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4061 getF32Constant(DAG, 0x3c5d51ce));
4062 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4063 getF32Constant(DAG, 0x3e00685a));
4064 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4065 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4066 getF32Constant(DAG, 0x3efb6798));
4067 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4068 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4069 getF32Constant(DAG, 0x3f88d192));
4070 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4071 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4072 getF32Constant(DAG, 0x3fc4316c));
4073 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4074 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4075 getF32Constant(DAG, 0x3f57ce70));
4078 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4081 // No special expansion.
4082 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4085 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4086 /// limited-precision mode.
4087 static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
4088 const TargetLowering &TLI) {
4089 if (Op.getValueType() == MVT::f32 &&
4090 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4093 // FractionalPartOfX = x - (float)IntegerPartOfX;
4094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4097 // IntegerPartOfX <<= 23;
4098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4099 DAG.getConstant(23, TLI.getPointerTy()));
4101 SDValue TwoToFractionalPartOfX;
4102 if (LimitFloatPrecision <= 6) {
4103 // For floating-point precision of 6:
4105 // TwoToFractionalPartOfX =
4107 // (0.735607626f + 0.252464424f * x) * x;
4109 // error 0.0144103317, which is 6 bits
4110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4111 getF32Constant(DAG, 0x3e814304));
4112 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4113 getF32Constant(DAG, 0x3f3c50c8));
4114 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4115 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4116 getF32Constant(DAG, 0x3f7f5e7e));
4117 } else if (LimitFloatPrecision <= 12) {
4118 // For floating-point precision of 12:
4120 // TwoToFractionalPartOfX =
4123 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4125 // error 0.000107046256, which is 13 to 14 bits
4126 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4127 getF32Constant(DAG, 0x3da235e3));
4128 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4129 getF32Constant(DAG, 0x3e65b8f3));
4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4131 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4132 getF32Constant(DAG, 0x3f324b07));
4133 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4134 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4135 getF32Constant(DAG, 0x3f7ff8fd));
4136 } else { // LimitFloatPrecision <= 18
4137 // For floating-point precision of 18:
4139 // TwoToFractionalPartOfX =
4143 // (0.554906021e-1f +
4144 // (0.961591928e-2f +
4145 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4146 // error 2.47208000*10^(-7), which is better than 18 bits
4147 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4148 getF32Constant(DAG, 0x3924b03e));
4149 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4150 getF32Constant(DAG, 0x3ab24b87));
4151 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4152 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4153 getF32Constant(DAG, 0x3c1d8c17));
4154 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4155 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4156 getF32Constant(DAG, 0x3d634a1d));
4157 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4158 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4159 getF32Constant(DAG, 0x3e75fe14));
4160 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4161 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4162 getF32Constant(DAG, 0x3f317234));
4163 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4164 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4165 getF32Constant(DAG, 0x3f800000));
4168 // Add the exponent into the result in integer domain.
4169 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4170 TwoToFractionalPartOfX);
4171 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4172 DAG.getNode(ISD::ADD, dl, MVT::i32,
4173 t13, IntegerPartOfX));
4176 // No special expansion.
4177 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4180 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4181 /// limited-precision mode with x == 10.0f.
4182 static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS,
4183 SelectionDAG &DAG, const TargetLowering &TLI) {
4184 bool IsExp10 = false;
4185 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4186 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4187 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4189 IsExp10 = LHSC->isExactlyValue(Ten);
4194 // Put the exponent in the right bit position for later addition to the
4197 // #define LOG2OF10 3.3219281f
4198 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4199 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4200 getF32Constant(DAG, 0x40549a78));
4201 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4203 // FractionalPartOfX = x - (float)IntegerPartOfX;
4204 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4205 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4207 // IntegerPartOfX <<= 23;
4208 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4209 DAG.getConstant(23, TLI.getPointerTy()));
4211 SDValue TwoToFractionalPartOfX;
4212 if (LimitFloatPrecision <= 6) {
4213 // For floating-point precision of 6:
4215 // twoToFractionalPartOfX =
4217 // (0.735607626f + 0.252464424f * x) * x;
4219 // error 0.0144103317, which is 6 bits
4220 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4221 getF32Constant(DAG, 0x3e814304));
4222 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4223 getF32Constant(DAG, 0x3f3c50c8));
4224 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4225 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4226 getF32Constant(DAG, 0x3f7f5e7e));
4227 } else if (LimitFloatPrecision <= 12) {
4228 // For floating-point precision of 12:
4230 // TwoToFractionalPartOfX =
4233 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4235 // error 0.000107046256, which is 13 to 14 bits
4236 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4237 getF32Constant(DAG, 0x3da235e3));
4238 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4239 getF32Constant(DAG, 0x3e65b8f3));
4240 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4241 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4242 getF32Constant(DAG, 0x3f324b07));
4243 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4244 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4245 getF32Constant(DAG, 0x3f7ff8fd));
4246 } else { // LimitFloatPrecision <= 18
4247 // For floating-point precision of 18:
4249 // TwoToFractionalPartOfX =
4253 // (0.554906021e-1f +
4254 // (0.961591928e-2f +
4255 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4256 // error 2.47208000*10^(-7), which is better than 18 bits
4257 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4258 getF32Constant(DAG, 0x3924b03e));
4259 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4260 getF32Constant(DAG, 0x3ab24b87));
4261 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4262 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4263 getF32Constant(DAG, 0x3c1d8c17));
4264 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4265 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4266 getF32Constant(DAG, 0x3d634a1d));
4267 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4268 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4269 getF32Constant(DAG, 0x3e75fe14));
4270 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4271 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4272 getF32Constant(DAG, 0x3f317234));
4273 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4274 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4275 getF32Constant(DAG, 0x3f800000));
4278 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4279 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4280 DAG.getNode(ISD::ADD, dl, MVT::i32,
4281 t13, IntegerPartOfX));
4284 // No special expansion.
4285 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4289 /// ExpandPowI - Expand a llvm.powi intrinsic.
4290 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4291 SelectionDAG &DAG) {
4292 // If RHS is a constant, we can expand this out to a multiplication tree,
4293 // otherwise we end up lowering to a call to __powidf2 (for example). When
4294 // optimizing for size, we only want to do this if the expansion would produce
4295 // a small number of multiplies, otherwise we do the full expansion.
4296 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4297 // Get the exponent as a positive value.
4298 unsigned Val = RHSC->getSExtValue();
4299 if ((int)Val < 0) Val = -Val;
4301 // powi(x, 0) -> 1.0
4303 return DAG.getConstantFP(1.0, LHS.getValueType());
4305 const Function *F = DAG.getMachineFunction().getFunction();
4306 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4307 Attribute::OptimizeForSize) ||
4308 // If optimizing for size, don't insert too many multiplies. This
4309 // inserts up to 5 multiplies.
4310 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4311 // We use the simple binary decomposition method to generate the multiply
4312 // sequence. There are more optimal ways to do this (for example,
4313 // powi(x,15) generates one more multiply than it should), but this has
4314 // the benefit of being both really simple and much better than a libcall.
4315 SDValue Res; // Logically starts equal to 1.0
4316 SDValue CurSquare = LHS;
4320 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4322 Res = CurSquare; // 1.0*CurSquare.
4325 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4326 CurSquare, CurSquare);
4330 // If the original was negative, invert the result, producing 1/(x*x*x).
4331 if (RHSC->getSExtValue() < 0)
4332 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4333 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4338 // Otherwise, expand to a libcall.
4339 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4342 // getTruncatedArgReg - Find underlying register used for an truncated
4344 static unsigned getTruncatedArgReg(const SDValue &N) {
4345 if (N.getOpcode() != ISD::TRUNCATE)
4348 const SDValue &Ext = N.getOperand(0);
4349 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4350 const SDValue &CFR = Ext.getOperand(0);
4351 if (CFR.getOpcode() == ISD::CopyFromReg)
4352 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4353 if (CFR.getOpcode() == ISD::TRUNCATE)
4354 return getTruncatedArgReg(CFR);
4359 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4360 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4361 /// At the end of instruction selection, they will be inserted to the entry BB.
4363 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4366 const Argument *Arg = dyn_cast<Argument>(V);
4370 MachineFunction &MF = DAG.getMachineFunction();
4371 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4372 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4374 // Ignore inlined function arguments here.
4375 DIVariable DV(Variable);
4376 if (DV.isInlinedFnArgument(MF.getFunction()))
4380 // Some arguments' frame index is recorded during argument lowering.
4381 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4383 Reg = TRI->getFrameRegister(MF);
4385 if (!Reg && N.getNode()) {
4386 if (N.getOpcode() == ISD::CopyFromReg)
4387 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4389 Reg = getTruncatedArgReg(N);
4390 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4391 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4392 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4399 // Check if ValueMap has reg number.
4400 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4401 if (VMI != FuncInfo.ValueMap.end())
4405 if (!Reg && N.getNode()) {
4406 // Check if frame index is available.
4407 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4408 if (FrameIndexSDNode *FINode =
4409 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4410 Reg = TRI->getFrameRegister(MF);
4411 Offset = FINode->getIndex();
4418 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4419 TII->get(TargetOpcode::DBG_VALUE))
4420 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4421 FuncInfo.ArgDbgValues.push_back(&*MIB);
4425 // VisualStudio defines setjmp as _setjmp
4426 #if defined(_MSC_VER) && defined(setjmp) && \
4427 !defined(setjmp_undefined_for_msvc)
4428 # pragma push_macro("setjmp")
4430 # define setjmp_undefined_for_msvc
4433 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4434 /// we want to emit this as a call to a named external function, return the name
4435 /// otherwise lower it and return null.
4437 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4438 DebugLoc dl = getCurDebugLoc();
4441 switch (Intrinsic) {
4443 // By default, turn this into a target intrinsic node.
4444 visitTargetIntrinsic(I, Intrinsic);
4446 case Intrinsic::vastart: visitVAStart(I); return 0;
4447 case Intrinsic::vaend: visitVAEnd(I); return 0;
4448 case Intrinsic::vacopy: visitVACopy(I); return 0;
4449 case Intrinsic::returnaddress:
4450 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4451 getValue(I.getArgOperand(0))));
4453 case Intrinsic::frameaddress:
4454 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4455 getValue(I.getArgOperand(0))));
4457 case Intrinsic::setjmp:
4458 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4459 case Intrinsic::longjmp:
4460 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4461 case Intrinsic::memcpy: {
4462 // Assert for address < 256 since we support only user defined address
4464 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4466 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4468 "Unknown address space");
4469 SDValue Op1 = getValue(I.getArgOperand(0));
4470 SDValue Op2 = getValue(I.getArgOperand(1));
4471 SDValue Op3 = getValue(I.getArgOperand(2));
4472 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4474 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4475 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4476 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4477 MachinePointerInfo(I.getArgOperand(0)),
4478 MachinePointerInfo(I.getArgOperand(1))));
4481 case Intrinsic::memset: {
4482 // Assert for address < 256 since we support only user defined address
4484 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4486 "Unknown address space");
4487 SDValue Op1 = getValue(I.getArgOperand(0));
4488 SDValue Op2 = getValue(I.getArgOperand(1));
4489 SDValue Op3 = getValue(I.getArgOperand(2));
4490 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4492 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4493 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4494 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4495 MachinePointerInfo(I.getArgOperand(0))));
4498 case Intrinsic::memmove: {
4499 // Assert for address < 256 since we support only user defined address
4501 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4503 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4505 "Unknown address space");
4506 SDValue Op1 = getValue(I.getArgOperand(0));
4507 SDValue Op2 = getValue(I.getArgOperand(1));
4508 SDValue Op3 = getValue(I.getArgOperand(2));
4509 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4511 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4512 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4513 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4514 MachinePointerInfo(I.getArgOperand(0)),
4515 MachinePointerInfo(I.getArgOperand(1))));
4518 case Intrinsic::dbg_declare: {
4519 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4520 MDNode *Variable = DI.getVariable();
4521 const Value *Address = DI.getAddress();
4522 if (!Address || !DIVariable(Variable).Verify()) {
4523 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4527 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4528 // but do not always have a corresponding SDNode built. The SDNodeOrder
4529 // absolute, but not relative, values are different depending on whether
4530 // debug info exists.
4533 // Check if address has undef value.
4534 if (isa<UndefValue>(Address) ||
4535 (Address->use_empty() && !isa<Argument>(Address))) {
4536 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4540 SDValue &N = NodeMap[Address];
4541 if (!N.getNode() && isa<Argument>(Address))
4542 // Check unused arguments map.
4543 N = UnusedArgNodeMap[Address];
4546 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4547 Address = BCI->getOperand(0);
4548 // Parameters are handled specially.
4550 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4551 isa<Argument>(Address));
4553 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4555 if (isParameter && !AI) {
4556 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4558 // Byval parameter. We have a frame index at this point.
4559 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4560 0, dl, SDNodeOrder);
4562 // Address is an argument, so try to emit its dbg value using
4563 // virtual register info from the FuncInfo.ValueMap.
4564 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4568 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4569 0, dl, SDNodeOrder);
4571 // Can't do anything with other non-AI cases yet.
4572 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4573 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4574 DEBUG(Address->dump());
4577 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4579 // If Address is an argument then try to emit its dbg value using
4580 // virtual register info from the FuncInfo.ValueMap.
4581 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4582 // If variable is pinned by a alloca in dominating bb then
4583 // use StaticAllocaMap.
4584 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4585 if (AI->getParent() != DI.getParent()) {
4586 DenseMap<const AllocaInst*, int>::iterator SI =
4587 FuncInfo.StaticAllocaMap.find(AI);
4588 if (SI != FuncInfo.StaticAllocaMap.end()) {
4589 SDV = DAG.getDbgValue(Variable, SI->second,
4590 0, dl, SDNodeOrder);
4591 DAG.AddDbgValue(SDV, 0, false);
4596 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4601 case Intrinsic::dbg_value: {
4602 const DbgValueInst &DI = cast<DbgValueInst>(I);
4603 if (!DIVariable(DI.getVariable()).Verify())
4606 MDNode *Variable = DI.getVariable();
4607 uint64_t Offset = DI.getOffset();
4608 const Value *V = DI.getValue();
4612 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4613 // but do not always have a corresponding SDNode built. The SDNodeOrder
4614 // absolute, but not relative, values are different depending on whether
4615 // debug info exists.
4618 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4619 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4620 DAG.AddDbgValue(SDV, 0, false);
4622 // Do not use getValue() in here; we don't want to generate code at
4623 // this point if it hasn't been done yet.
4624 SDValue N = NodeMap[V];
4625 if (!N.getNode() && isa<Argument>(V))
4626 // Check unused arguments map.
4627 N = UnusedArgNodeMap[V];
4629 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4630 SDV = DAG.getDbgValue(Variable, N.getNode(),
4631 N.getResNo(), Offset, dl, SDNodeOrder);
4632 DAG.AddDbgValue(SDV, N.getNode(), false);
4634 } else if (!V->use_empty() ) {
4635 // Do not call getValue(V) yet, as we don't want to generate code.
4636 // Remember it for later.
4637 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4638 DanglingDebugInfoMap[V] = DDI;
4640 // We may expand this to cover more cases. One case where we have no
4641 // data available is an unreferenced parameter.
4642 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4646 // Build a debug info table entry.
4647 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4648 V = BCI->getOperand(0);
4649 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4650 // Don't handle byval struct arguments or VLAs, for example.
4652 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4653 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4656 DenseMap<const AllocaInst*, int>::iterator SI =
4657 FuncInfo.StaticAllocaMap.find(AI);
4658 if (SI == FuncInfo.StaticAllocaMap.end())
4660 int FI = SI->second;
4662 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4663 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4664 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4668 case Intrinsic::eh_typeid_for: {
4669 // Find the type id for the given typeinfo.
4670 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4671 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4672 Res = DAG.getConstant(TypeID, MVT::i32);
4677 case Intrinsic::eh_return_i32:
4678 case Intrinsic::eh_return_i64:
4679 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4680 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4683 getValue(I.getArgOperand(0)),
4684 getValue(I.getArgOperand(1))));
4686 case Intrinsic::eh_unwind_init:
4687 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4689 case Intrinsic::eh_dwarf_cfa: {
4690 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4691 TLI.getPointerTy());
4692 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4694 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4695 TLI.getPointerTy()),
4697 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4699 DAG.getConstant(0, TLI.getPointerTy()));
4700 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4704 case Intrinsic::eh_sjlj_callsite: {
4705 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4706 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4707 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4708 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4710 MMI.setCurrentCallSite(CI->getZExtValue());
4713 case Intrinsic::eh_sjlj_functioncontext: {
4714 // Get and store the index of the function context.
4715 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4717 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4718 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4719 MFI->setFunctionContextIndex(FI);
4722 case Intrinsic::eh_sjlj_setjmp: {
4725 Ops[1] = getValue(I.getArgOperand(0));
4726 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4727 DAG.getVTList(MVT::i32, MVT::Other),
4729 setValue(&I, Op.getValue(0));
4730 DAG.setRoot(Op.getValue(1));
4733 case Intrinsic::eh_sjlj_longjmp: {
4734 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4735 getRoot(), getValue(I.getArgOperand(0))));
4739 case Intrinsic::x86_mmx_pslli_w:
4740 case Intrinsic::x86_mmx_pslli_d:
4741 case Intrinsic::x86_mmx_pslli_q:
4742 case Intrinsic::x86_mmx_psrli_w:
4743 case Intrinsic::x86_mmx_psrli_d:
4744 case Intrinsic::x86_mmx_psrli_q:
4745 case Intrinsic::x86_mmx_psrai_w:
4746 case Intrinsic::x86_mmx_psrai_d: {
4747 SDValue ShAmt = getValue(I.getArgOperand(1));
4748 if (isa<ConstantSDNode>(ShAmt)) {
4749 visitTargetIntrinsic(I, Intrinsic);
4752 unsigned NewIntrinsic = 0;
4753 EVT ShAmtVT = MVT::v2i32;
4754 switch (Intrinsic) {
4755 case Intrinsic::x86_mmx_pslli_w:
4756 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4758 case Intrinsic::x86_mmx_pslli_d:
4759 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4761 case Intrinsic::x86_mmx_pslli_q:
4762 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4764 case Intrinsic::x86_mmx_psrli_w:
4765 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4767 case Intrinsic::x86_mmx_psrli_d:
4768 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4770 case Intrinsic::x86_mmx_psrli_q:
4771 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4773 case Intrinsic::x86_mmx_psrai_w:
4774 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4776 case Intrinsic::x86_mmx_psrai_d:
4777 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4779 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4782 // The vector shift intrinsics with scalars uses 32b shift amounts but
4783 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4785 // We must do this early because v2i32 is not a legal type.
4788 ShOps[1] = DAG.getConstant(0, MVT::i32);
4789 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4790 EVT DestVT = TLI.getValueType(I.getType());
4791 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4792 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4793 DAG.getConstant(NewIntrinsic, MVT::i32),
4794 getValue(I.getArgOperand(0)), ShAmt);
4798 case Intrinsic::x86_avx_vinsertf128_pd_256:
4799 case Intrinsic::x86_avx_vinsertf128_ps_256:
4800 case Intrinsic::x86_avx_vinsertf128_si_256:
4801 case Intrinsic::x86_avx2_vinserti128: {
4802 EVT DestVT = TLI.getValueType(I.getType());
4803 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4804 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4805 ElVT.getVectorNumElements();
4806 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4807 getValue(I.getArgOperand(0)),
4808 getValue(I.getArgOperand(1)),
4809 DAG.getIntPtrConstant(Idx));
4813 case Intrinsic::x86_avx_vextractf128_pd_256:
4814 case Intrinsic::x86_avx_vextractf128_ps_256:
4815 case Intrinsic::x86_avx_vextractf128_si_256:
4816 case Intrinsic::x86_avx2_vextracti128: {
4817 EVT DestVT = TLI.getValueType(I.getType());
4818 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4819 DestVT.getVectorNumElements();
4820 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4821 getValue(I.getArgOperand(0)),
4822 DAG.getIntPtrConstant(Idx));
4826 case Intrinsic::convertff:
4827 case Intrinsic::convertfsi:
4828 case Intrinsic::convertfui:
4829 case Intrinsic::convertsif:
4830 case Intrinsic::convertuif:
4831 case Intrinsic::convertss:
4832 case Intrinsic::convertsu:
4833 case Intrinsic::convertus:
4834 case Intrinsic::convertuu: {
4835 ISD::CvtCode Code = ISD::CVT_INVALID;
4836 switch (Intrinsic) {
4837 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4838 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4839 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4840 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4841 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4842 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4843 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4844 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4845 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4846 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4848 EVT DestVT = TLI.getValueType(I.getType());
4849 const Value *Op1 = I.getArgOperand(0);
4850 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1),
4851 DAG.getValueType(DestVT),
4852 DAG.getValueType(getValue(Op1).getValueType()),
4853 getValue(I.getArgOperand(1)),
4854 getValue(I.getArgOperand(2)),
4859 case Intrinsic::powi:
4860 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4861 getValue(I.getArgOperand(1)), DAG));
4863 case Intrinsic::log:
4864 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4866 case Intrinsic::log2:
4867 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4869 case Intrinsic::log10:
4870 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4872 case Intrinsic::exp:
4873 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4875 case Intrinsic::exp2:
4876 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4878 case Intrinsic::pow:
4879 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)),
4880 getValue(I.getArgOperand(1)), DAG, TLI));
4882 case Intrinsic::sqrt:
4883 case Intrinsic::fabs:
4884 case Intrinsic::sin:
4885 case Intrinsic::cos:
4886 case Intrinsic::floor:
4887 case Intrinsic::ceil:
4888 case Intrinsic::trunc:
4889 case Intrinsic::rint:
4890 case Intrinsic::nearbyint: {
4892 switch (Intrinsic) {
4893 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4894 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4895 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4896 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4897 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4898 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4899 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4900 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4901 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4902 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4905 setValue(&I, DAG.getNode(Opcode, dl,
4906 getValue(I.getArgOperand(0)).getValueType(),
4907 getValue(I.getArgOperand(0))));
4910 case Intrinsic::fma:
4911 setValue(&I, DAG.getNode(ISD::FMA, dl,
4912 getValue(I.getArgOperand(0)).getValueType(),
4913 getValue(I.getArgOperand(0)),
4914 getValue(I.getArgOperand(1)),
4915 getValue(I.getArgOperand(2))));
4917 case Intrinsic::fmuladd: {
4918 EVT VT = TLI.getValueType(I.getType());
4919 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4920 TLI.isFMAFasterThanMulAndAdd(VT)){
4921 setValue(&I, DAG.getNode(ISD::FMA, dl,
4922 getValue(I.getArgOperand(0)).getValueType(),
4923 getValue(I.getArgOperand(0)),
4924 getValue(I.getArgOperand(1)),
4925 getValue(I.getArgOperand(2))));
4927 SDValue Mul = DAG.getNode(ISD::FMUL, dl,
4928 getValue(I.getArgOperand(0)).getValueType(),
4929 getValue(I.getArgOperand(0)),
4930 getValue(I.getArgOperand(1)));
4931 SDValue Add = DAG.getNode(ISD::FADD, dl,
4932 getValue(I.getArgOperand(0)).getValueType(),
4934 getValue(I.getArgOperand(2)));
4939 case Intrinsic::convert_to_fp16:
4940 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4941 MVT::i16, getValue(I.getArgOperand(0))));
4943 case Intrinsic::convert_from_fp16:
4944 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4945 MVT::f32, getValue(I.getArgOperand(0))));
4947 case Intrinsic::pcmarker: {
4948 SDValue Tmp = getValue(I.getArgOperand(0));
4949 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4952 case Intrinsic::readcyclecounter: {
4953 SDValue Op = getRoot();
4954 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4955 DAG.getVTList(MVT::i64, MVT::Other),
4958 DAG.setRoot(Res.getValue(1));
4961 case Intrinsic::bswap:
4962 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4963 getValue(I.getArgOperand(0)).getValueType(),
4964 getValue(I.getArgOperand(0))));
4966 case Intrinsic::cttz: {
4967 SDValue Arg = getValue(I.getArgOperand(0));
4968 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4969 EVT Ty = Arg.getValueType();
4970 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4974 case Intrinsic::ctlz: {
4975 SDValue Arg = getValue(I.getArgOperand(0));
4976 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4977 EVT Ty = Arg.getValueType();
4978 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4982 case Intrinsic::ctpop: {
4983 SDValue Arg = getValue(I.getArgOperand(0));
4984 EVT Ty = Arg.getValueType();
4985 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4988 case Intrinsic::stacksave: {
4989 SDValue Op = getRoot();
4990 Res = DAG.getNode(ISD::STACKSAVE, dl,
4991 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4993 DAG.setRoot(Res.getValue(1));
4996 case Intrinsic::stackrestore: {
4997 Res = getValue(I.getArgOperand(0));
4998 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
5001 case Intrinsic::stackprotector: {
5002 // Emit code into the DAG to store the stack guard onto the stack.
5003 MachineFunction &MF = DAG.getMachineFunction();
5004 MachineFrameInfo *MFI = MF.getFrameInfo();
5005 EVT PtrTy = TLI.getPointerTy();
5007 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5008 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5010 int FI = FuncInfo.StaticAllocaMap[Slot];
5011 MFI->setStackProtectorIndex(FI);
5013 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5015 // Store the stack protector onto the stack.
5016 Res = DAG.getStore(getRoot(), dl, Src, FIN,
5017 MachinePointerInfo::getFixedStack(FI),
5023 case Intrinsic::objectsize: {
5024 // If we don't know by now, we're never going to know.
5025 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5027 assert(CI && "Non-constant type in __builtin_object_size?");
5029 SDValue Arg = getValue(I.getCalledValue());
5030 EVT Ty = Arg.getValueType();
5033 Res = DAG.getConstant(-1ULL, Ty);
5035 Res = DAG.getConstant(0, Ty);
5040 case Intrinsic::annotation:
5041 case Intrinsic::ptr_annotation:
5042 // Drop the intrinsic, but forward the value
5043 setValue(&I, getValue(I.getOperand(0)));
5045 case Intrinsic::var_annotation:
5046 // Discard annotate attributes
5049 case Intrinsic::init_trampoline: {
5050 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5054 Ops[1] = getValue(I.getArgOperand(0));
5055 Ops[2] = getValue(I.getArgOperand(1));
5056 Ops[3] = getValue(I.getArgOperand(2));
5057 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5058 Ops[5] = DAG.getSrcValue(F);
5060 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5065 case Intrinsic::adjust_trampoline: {
5066 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5068 getValue(I.getArgOperand(0))));
5071 case Intrinsic::gcroot:
5073 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5074 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5076 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5077 GFI->addStackRoot(FI->getIndex(), TypeMap);
5080 case Intrinsic::gcread:
5081 case Intrinsic::gcwrite:
5082 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5083 case Intrinsic::flt_rounds:
5084 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5087 case Intrinsic::expect: {
5088 // Just replace __builtin_expect(exp, c) with EXP.
5089 setValue(&I, getValue(I.getArgOperand(0)));
5093 case Intrinsic::debugtrap:
5094 case Intrinsic::trap: {
5095 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5096 if (TrapFuncName.empty()) {
5097 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5098 ISD::TRAP : ISD::DEBUGTRAP;
5099 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot()));
5102 TargetLowering::ArgListTy Args;
5104 CallLoweringInfo CLI(getRoot(), I.getType(),
5105 false, false, false, false, 0, CallingConv::C,
5106 /*isTailCall=*/false,
5107 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5108 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5110 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5111 DAG.setRoot(Result.second);
5115 case Intrinsic::uadd_with_overflow:
5116 case Intrinsic::sadd_with_overflow:
5117 case Intrinsic::usub_with_overflow:
5118 case Intrinsic::ssub_with_overflow:
5119 case Intrinsic::umul_with_overflow:
5120 case Intrinsic::smul_with_overflow: {
5122 switch (Intrinsic) {
5123 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5124 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5125 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5126 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5127 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5128 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5129 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5131 SDValue Op1 = getValue(I.getArgOperand(0));
5132 SDValue Op2 = getValue(I.getArgOperand(1));
5134 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5135 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2));
5138 case Intrinsic::prefetch: {
5140 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5142 Ops[1] = getValue(I.getArgOperand(0));
5143 Ops[2] = getValue(I.getArgOperand(1));
5144 Ops[3] = getValue(I.getArgOperand(2));
5145 Ops[4] = getValue(I.getArgOperand(3));
5146 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5147 DAG.getVTList(MVT::Other),
5149 EVT::getIntegerVT(*Context, 8),
5150 MachinePointerInfo(I.getArgOperand(0)),
5152 false, /* volatile */
5154 rw==1)); /* write */
5157 case Intrinsic::lifetime_start:
5158 case Intrinsic::lifetime_end: {
5159 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5160 // Stack coloring is not enabled in O0, discard region information.
5161 if (TM.getOptLevel() == CodeGenOpt::None)
5164 SmallVector<Value *, 4> Allocas;
5165 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5167 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(),
5168 E = Allocas.end(); Object != E; ++Object) {
5169 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5171 // Could not find an Alloca.
5172 if (!LifetimeObject)
5175 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5179 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5180 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5182 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2);
5187 case Intrinsic::invariant_start:
5188 // Discard region information.
5189 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5191 case Intrinsic::invariant_end:
5192 // Discard region information.
5194 case Intrinsic::donothing:
5200 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5202 MachineBasicBlock *LandingPad) {
5203 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5204 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5205 Type *RetTy = FTy->getReturnType();
5206 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5207 MCSymbol *BeginLabel = 0;
5209 TargetLowering::ArgListTy Args;
5210 TargetLowering::ArgListEntry Entry;
5211 Args.reserve(CS.arg_size());
5213 // Check whether the function can return without sret-demotion.
5214 SmallVector<ISD::OutputArg, 4> Outs;
5215 GetReturnInfo(RetTy, CS.getAttributes(), Outs, TLI);
5217 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5218 DAG.getMachineFunction(),
5219 FTy->isVarArg(), Outs,
5222 SDValue DemoteStackSlot;
5223 int DemoteStackIdx = -100;
5225 if (!CanLowerReturn) {
5226 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(
5227 FTy->getReturnType());
5228 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(
5229 FTy->getReturnType());
5230 MachineFunction &MF = DAG.getMachineFunction();
5231 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5232 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5234 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5235 Entry.Node = DemoteStackSlot;
5236 Entry.Ty = StackSlotPtrType;
5237 Entry.isSExt = false;
5238 Entry.isZExt = false;
5239 Entry.isInReg = false;
5240 Entry.isSRet = true;
5241 Entry.isNest = false;
5242 Entry.isByVal = false;
5243 Entry.isReturned = false;
5244 Entry.Alignment = Align;
5245 Args.push_back(Entry);
5246 RetTy = Type::getVoidTy(FTy->getContext());
5249 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5251 const Value *V = *i;
5254 if (V->getType()->isEmptyTy())
5257 SDValue ArgNode = getValue(V);
5258 Entry.Node = ArgNode; Entry.Ty = V->getType();
5260 unsigned attrInd = i - CS.arg_begin() + 1;
5261 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5262 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5263 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5264 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5265 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5266 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5267 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned);
5268 Entry.Alignment = CS.getParamAlignment(attrInd);
5269 Args.push_back(Entry);
5273 // Insert a label before the invoke call to mark the try range. This can be
5274 // used to detect deletion of the invoke via the MachineModuleInfo.
5275 BeginLabel = MMI.getContext().CreateTempSymbol();
5277 // For SjLj, keep track of which landing pads go with which invokes
5278 // so as to maintain the ordering of pads in the LSDA.
5279 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5280 if (CallSiteIndex) {
5281 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5282 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5284 // Now that the call site is handled, stop tracking it.
5285 MMI.setCurrentCallSite(0);
5288 // Both PendingLoads and PendingExports must be flushed here;
5289 // this call might not return.
5291 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5294 // Check if target-independent constraints permit a tail call here.
5295 // Target-dependent constraints are checked within TLI.LowerCallTo.
5296 if (isTailCall && !isInTailCallPosition(CS, TLI))
5300 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5301 getCurDebugLoc(), CS);
5302 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5303 assert((isTailCall || Result.second.getNode()) &&
5304 "Non-null chain expected with non-tail call!");
5305 assert((Result.second.getNode() || !Result.first.getNode()) &&
5306 "Null value expected with tail call!");
5307 if (Result.first.getNode()) {
5308 setValue(CS.getInstruction(), Result.first);
5309 } else if (!CanLowerReturn && Result.second.getNode()) {
5310 // The instruction result is the result of loading from the
5311 // hidden sret parameter.
5312 SmallVector<EVT, 1> PVTs;
5313 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5315 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5316 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5317 EVT PtrVT = PVTs[0];
5319 SmallVector<EVT, 4> RetTys;
5320 SmallVector<uint64_t, 4> Offsets;
5321 RetTy = FTy->getReturnType();
5322 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5324 unsigned NumValues = RetTys.size();
5325 SmallVector<SDValue, 4> Values(NumValues);
5326 SmallVector<SDValue, 4> Chains(NumValues);
5328 for (unsigned i = 0; i < NumValues; ++i) {
5329 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5331 DAG.getConstant(Offsets[i], PtrVT));
5332 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5333 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5334 false, false, false, 1);
5336 Chains[i] = L.getValue(1);
5339 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5340 MVT::Other, &Chains[0], NumValues);
5341 PendingLoads.push_back(Chain);
5343 setValue(CS.getInstruction(),
5344 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5345 DAG.getVTList(&RetTys[0], RetTys.size()),
5346 &Values[0], Values.size()));
5349 // Assign order to nodes here. If the call does not produce a result, it won't
5350 // be mapped to a SDNode and visit() will not assign it an order number.
5351 if (!Result.second.getNode()) {
5352 // As a special case, a null chain means that a tail call has been emitted and
5353 // the DAG root is already updated.
5356 AssignOrderingToNode(DAG.getRoot().getNode());
5358 DAG.setRoot(Result.second);
5360 AssignOrderingToNode(Result.second.getNode());
5364 // Insert a label at the end of the invoke call to mark the try range. This
5365 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5366 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5367 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5369 // Inform MachineModuleInfo of range.
5370 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5374 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5375 /// value is equal or not-equal to zero.
5376 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5377 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5379 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5380 if (IC->isEquality())
5381 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5382 if (C->isNullValue())
5384 // Unknown instruction.
5390 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5392 SelectionDAGBuilder &Builder) {
5394 // Check to see if this load can be trivially constant folded, e.g. if the
5395 // input is from a string literal.
5396 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5397 // Cast pointer to the type we really want to load.
5398 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5399 PointerType::getUnqual(LoadTy));
5401 if (const Constant *LoadCst =
5402 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5404 return Builder.getValue(LoadCst);
5407 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5408 // still constant memory, the input chain can be the entry node.
5410 bool ConstantMemory = false;
5412 // Do not serialize (non-volatile) loads of constant memory with anything.
5413 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5414 Root = Builder.DAG.getEntryNode();
5415 ConstantMemory = true;
5417 // Do not serialize non-volatile loads against each other.
5418 Root = Builder.DAG.getRoot();
5421 SDValue Ptr = Builder.getValue(PtrVal);
5422 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5423 Ptr, MachinePointerInfo(PtrVal),
5425 false /*nontemporal*/,
5426 false /*isinvariant*/, 1 /* align=1 */);
5428 if (!ConstantMemory)
5429 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5434 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5435 /// If so, return true and lower it, otherwise return false and it will be
5436 /// lowered like a normal call.
5437 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5438 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5439 if (I.getNumArgOperands() != 3)
5442 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5443 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5444 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5445 !I.getType()->isIntegerTy())
5448 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5450 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5451 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5452 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5453 bool ActuallyDoIt = true;
5456 switch (Size->getZExtValue()) {
5458 LoadVT = MVT::Other;
5460 ActuallyDoIt = false;
5464 LoadTy = Type::getInt16Ty(Size->getContext());
5468 LoadTy = Type::getInt32Ty(Size->getContext());
5472 LoadTy = Type::getInt64Ty(Size->getContext());
5476 LoadVT = MVT::v4i32;
5477 LoadTy = Type::getInt32Ty(Size->getContext());
5478 LoadTy = VectorType::get(LoadTy, 4);
5483 // This turns into unaligned loads. We only do this if the target natively
5484 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5485 // we'll only produce a small number of byte loads.
5487 // Require that we can find a legal MVT, and only do this if the target
5488 // supports unaligned loads of that type. Expanding into byte loads would
5490 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5491 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5492 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5493 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5494 ActuallyDoIt = false;
5498 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5499 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5501 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5503 EVT CallVT = TLI.getValueType(I.getType(), true);
5504 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5513 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5514 /// operation (as expected), translate it to an SDNode with the specified opcode
5515 /// and return true.
5516 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5518 // Sanity check that it really is a unary floating-point call.
5519 if (I.getNumArgOperands() != 1 ||
5520 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5521 I.getType() != I.getArgOperand(0)->getType() ||
5522 !I.onlyReadsMemory())
5525 SDValue Tmp = getValue(I.getArgOperand(0));
5526 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
5530 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5531 // Handle inline assembly differently.
5532 if (isa<InlineAsm>(I.getCalledValue())) {
5537 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5538 ComputeUsesVAFloatArgument(I, &MMI);
5540 const char *RenameFn = 0;
5541 if (Function *F = I.getCalledFunction()) {
5542 if (F->isDeclaration()) {
5543 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5544 if (unsigned IID = II->getIntrinsicID(F)) {
5545 RenameFn = visitIntrinsicCall(I, IID);
5550 if (unsigned IID = F->getIntrinsicID()) {
5551 RenameFn = visitIntrinsicCall(I, IID);
5557 // Check for well-known libc/libm calls. If the function is internal, it
5558 // can't be a library call.
5560 if (!F->hasLocalLinkage() && F->hasName() &&
5561 LibInfo->getLibFunc(F->getName(), Func) &&
5562 LibInfo->hasOptimizedCodeGen(Func)) {
5565 case LibFunc::copysign:
5566 case LibFunc::copysignf:
5567 case LibFunc::copysignl:
5568 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5569 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5570 I.getType() == I.getArgOperand(0)->getType() &&
5571 I.getType() == I.getArgOperand(1)->getType() &&
5572 I.onlyReadsMemory()) {
5573 SDValue LHS = getValue(I.getArgOperand(0));
5574 SDValue RHS = getValue(I.getArgOperand(1));
5575 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5576 LHS.getValueType(), LHS, RHS));
5581 case LibFunc::fabsf:
5582 case LibFunc::fabsl:
5583 if (visitUnaryFloatCall(I, ISD::FABS))
5589 if (visitUnaryFloatCall(I, ISD::FSIN))
5595 if (visitUnaryFloatCall(I, ISD::FCOS))
5599 case LibFunc::sqrtf:
5600 case LibFunc::sqrtl:
5601 if (visitUnaryFloatCall(I, ISD::FSQRT))
5604 case LibFunc::floor:
5605 case LibFunc::floorf:
5606 case LibFunc::floorl:
5607 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5610 case LibFunc::nearbyint:
5611 case LibFunc::nearbyintf:
5612 case LibFunc::nearbyintl:
5613 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5617 case LibFunc::ceilf:
5618 case LibFunc::ceill:
5619 if (visitUnaryFloatCall(I, ISD::FCEIL))
5623 case LibFunc::rintf:
5624 case LibFunc::rintl:
5625 if (visitUnaryFloatCall(I, ISD::FRINT))
5628 case LibFunc::trunc:
5629 case LibFunc::truncf:
5630 case LibFunc::truncl:
5631 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5635 case LibFunc::log2f:
5636 case LibFunc::log2l:
5637 if (visitUnaryFloatCall(I, ISD::FLOG2))
5641 case LibFunc::exp2f:
5642 case LibFunc::exp2l:
5643 if (visitUnaryFloatCall(I, ISD::FEXP2))
5646 case LibFunc::memcmp:
5647 if (visitMemCmpCall(I))
5656 Callee = getValue(I.getCalledValue());
5658 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5660 // Check if we can potentially perform a tail call. More detailed checking is
5661 // be done within LowerCallTo, after more information about the call is known.
5662 LowerCallTo(&I, Callee, I.isTailCall());
5667 /// AsmOperandInfo - This contains information for each constraint that we are
5669 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5671 /// CallOperand - If this is the result output operand or a clobber
5672 /// this is null, otherwise it is the incoming operand to the CallInst.
5673 /// This gets modified as the asm is processed.
5674 SDValue CallOperand;
5676 /// AssignedRegs - If this is a register or register class operand, this
5677 /// contains the set of register corresponding to the operand.
5678 RegsForValue AssignedRegs;
5680 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5681 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5684 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5685 /// corresponds to. If there is no Value* for this operand, it returns
5687 EVT getCallOperandValEVT(LLVMContext &Context,
5688 const TargetLowering &TLI,
5689 const DataLayout *TD) const {
5690 if (CallOperandVal == 0) return MVT::Other;
5692 if (isa<BasicBlock>(CallOperandVal))
5693 return TLI.getPointerTy();
5695 llvm::Type *OpTy = CallOperandVal->getType();
5697 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5698 // If this is an indirect operand, the operand is a pointer to the
5701 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5703 report_fatal_error("Indirect operand for inline asm not a pointer!");
5704 OpTy = PtrTy->getElementType();
5707 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5708 if (StructType *STy = dyn_cast<StructType>(OpTy))
5709 if (STy->getNumElements() == 1)
5710 OpTy = STy->getElementType(0);
5712 // If OpTy is not a single value, it may be a struct/union that we
5713 // can tile with integers.
5714 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5715 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5724 OpTy = IntegerType::get(Context, BitSize);
5729 return TLI.getValueType(OpTy, true);
5733 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5735 } // end anonymous namespace
5737 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5738 /// specified operand. We prefer to assign virtual registers, to allow the
5739 /// register allocator to handle the assignment process. However, if the asm
5740 /// uses features that we can't model on machineinstrs, we have SDISel do the
5741 /// allocation. This produces generally horrible, but correct, code.
5743 /// OpInfo describes the operand.
5745 static void GetRegistersForValue(SelectionDAG &DAG,
5746 const TargetLowering &TLI,
5748 SDISelAsmOperandInfo &OpInfo) {
5749 LLVMContext &Context = *DAG.getContext();
5751 MachineFunction &MF = DAG.getMachineFunction();
5752 SmallVector<unsigned, 4> Regs;
5754 // If this is a constraint for a single physreg, or a constraint for a
5755 // register class, find it.
5756 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5757 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5758 OpInfo.ConstraintVT);
5760 unsigned NumRegs = 1;
5761 if (OpInfo.ConstraintVT != MVT::Other) {
5762 // If this is a FP input in an integer register (or visa versa) insert a bit
5763 // cast of the input value. More generally, handle any case where the input
5764 // value disagrees with the register class we plan to stick this in.
5765 if (OpInfo.Type == InlineAsm::isInput &&
5766 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5767 // Try to convert to the first EVT that the reg class contains. If the
5768 // types are identical size, use a bitcast to convert (e.g. two differing
5770 MVT RegVT = *PhysReg.second->vt_begin();
5771 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5772 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5773 RegVT, OpInfo.CallOperand);
5774 OpInfo.ConstraintVT = RegVT;
5775 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5776 // If the input is a FP value and we want it in FP registers, do a
5777 // bitcast to the corresponding integer type. This turns an f64 value
5778 // into i64, which can be passed with two i32 values on a 32-bit
5780 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5781 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5782 RegVT, OpInfo.CallOperand);
5783 OpInfo.ConstraintVT = RegVT;
5787 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5791 EVT ValueVT = OpInfo.ConstraintVT;
5793 // If this is a constraint for a specific physical register, like {r17},
5795 if (unsigned AssignedReg = PhysReg.first) {
5796 const TargetRegisterClass *RC = PhysReg.second;
5797 if (OpInfo.ConstraintVT == MVT::Other)
5798 ValueVT = *RC->vt_begin();
5800 // Get the actual register value type. This is important, because the user
5801 // may have asked for (e.g.) the AX register in i32 type. We need to
5802 // remember that AX is actually i16 to get the right extension.
5803 RegVT = *RC->vt_begin();
5805 // This is a explicit reference to a physical register.
5806 Regs.push_back(AssignedReg);
5808 // If this is an expanded reference, add the rest of the regs to Regs.
5810 TargetRegisterClass::iterator I = RC->begin();
5811 for (; *I != AssignedReg; ++I)
5812 assert(I != RC->end() && "Didn't find reg!");
5814 // Already added the first reg.
5816 for (; NumRegs; --NumRegs, ++I) {
5817 assert(I != RC->end() && "Ran out of registers to allocate!");
5822 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5826 // Otherwise, if this was a reference to an LLVM register class, create vregs
5827 // for this reference.
5828 if (const TargetRegisterClass *RC = PhysReg.second) {
5829 RegVT = *RC->vt_begin();
5830 if (OpInfo.ConstraintVT == MVT::Other)
5833 // Create the appropriate number of virtual registers.
5834 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5835 for (; NumRegs; --NumRegs)
5836 Regs.push_back(RegInfo.createVirtualRegister(RC));
5838 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5842 // Otherwise, we couldn't allocate enough registers for this.
5845 /// visitInlineAsm - Handle a call to an InlineAsm object.
5847 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5848 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5850 /// ConstraintOperands - Information about all of the constraints.
5851 SDISelAsmOperandInfoVector ConstraintOperands;
5853 TargetLowering::AsmOperandInfoVector
5854 TargetConstraints = TLI.ParseConstraints(CS);
5856 bool hasMemory = false;
5858 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5859 unsigned ResNo = 0; // ResNo - The result number of the next output.
5860 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5861 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5862 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5864 MVT OpVT = MVT::Other;
5866 // Compute the value type for each operand.
5867 switch (OpInfo.Type) {
5868 case InlineAsm::isOutput:
5869 // Indirect outputs just consume an argument.
5870 if (OpInfo.isIndirect) {
5871 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5875 // The return value of the call is this value. As such, there is no
5876 // corresponding argument.
5877 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5878 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5879 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5881 assert(ResNo == 0 && "Asm only has one result!");
5882 OpVT = TLI.getSimpleValueType(CS.getType());
5886 case InlineAsm::isInput:
5887 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5889 case InlineAsm::isClobber:
5894 // If this is an input or an indirect output, process the call argument.
5895 // BasicBlocks are labels, currently appearing only in asm's.
5896 if (OpInfo.CallOperandVal) {
5897 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5898 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5900 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5903 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD).
5907 OpInfo.ConstraintVT = OpVT;
5909 // Indirect operand accesses access memory.
5910 if (OpInfo.isIndirect)
5913 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5914 TargetLowering::ConstraintType
5915 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5916 if (CType == TargetLowering::C_Memory) {
5924 SDValue Chain, Flag;
5926 // We won't need to flush pending loads if this asm doesn't touch
5927 // memory and is nonvolatile.
5928 if (hasMemory || IA->hasSideEffects())
5931 Chain = DAG.getRoot();
5933 // Second pass over the constraints: compute which constraint option to use
5934 // and assign registers to constraints that want a specific physreg.
5935 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5936 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5938 // If this is an output operand with a matching input operand, look up the
5939 // matching input. If their types mismatch, e.g. one is an integer, the
5940 // other is floating point, or their sizes are different, flag it as an
5942 if (OpInfo.hasMatchingInput()) {
5943 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5945 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5946 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5947 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5948 OpInfo.ConstraintVT);
5949 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5950 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5951 Input.ConstraintVT);
5952 if ((OpInfo.ConstraintVT.isInteger() !=
5953 Input.ConstraintVT.isInteger()) ||
5954 (MatchRC.second != InputRC.second)) {
5955 report_fatal_error("Unsupported asm: input constraint"
5956 " with a matching output constraint of"
5957 " incompatible type!");
5959 Input.ConstraintVT = OpInfo.ConstraintVT;
5963 // Compute the constraint code and ConstraintType to use.
5964 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5966 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5967 OpInfo.Type == InlineAsm::isClobber)
5970 // If this is a memory input, and if the operand is not indirect, do what we
5971 // need to to provide an address for the memory input.
5972 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5973 !OpInfo.isIndirect) {
5974 assert((OpInfo.isMultipleAlternative ||
5975 (OpInfo.Type == InlineAsm::isInput)) &&
5976 "Can only indirectify direct input operands!");
5978 // Memory operands really want the address of the value. If we don't have
5979 // an indirect input, put it in the constpool if we can, otherwise spill
5980 // it to a stack slot.
5981 // TODO: This isn't quite right. We need to handle these according to
5982 // the addressing mode that the constraint wants. Also, this may take
5983 // an additional register for the computation and we don't want that
5986 // If the operand is a float, integer, or vector constant, spill to a
5987 // constant pool entry to get its address.
5988 const Value *OpVal = OpInfo.CallOperandVal;
5989 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5990 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5991 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5992 TLI.getPointerTy());
5994 // Otherwise, create a stack slot and emit a store to it before the
5996 Type *Ty = OpVal->getType();
5997 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5998 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5999 MachineFunction &MF = DAG.getMachineFunction();
6000 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6001 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6002 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6003 OpInfo.CallOperand, StackSlot,
6004 MachinePointerInfo::getFixedStack(SSFI),
6006 OpInfo.CallOperand = StackSlot;
6009 // There is no longer a Value* corresponding to this operand.
6010 OpInfo.CallOperandVal = 0;
6012 // It is now an indirect operand.
6013 OpInfo.isIndirect = true;
6016 // If this constraint is for a specific register, allocate it before
6018 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6019 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6022 // Second pass - Loop over all of the operands, assigning virtual or physregs
6023 // to register class operands.
6024 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6025 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6027 // C_Register operands have already been allocated, Other/Memory don't need
6029 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6030 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6033 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6034 std::vector<SDValue> AsmNodeOperands;
6035 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6036 AsmNodeOperands.push_back(
6037 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6038 TLI.getPointerTy()));
6040 // If we have a !srcloc metadata node associated with it, we want to attach
6041 // this to the ultimately generated inline asm machineinstr. To do this, we
6042 // pass in the third operand as this (potentially null) inline asm MDNode.
6043 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6044 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6046 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6047 // bits as operand 3.
6048 unsigned ExtraInfo = 0;
6049 if (IA->hasSideEffects())
6050 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6051 if (IA->isAlignStack())
6052 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6053 // Set the asm dialect.
6054 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6056 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6057 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6058 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6060 // Compute the constraint code and ConstraintType to use.
6061 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6063 // Ideally, we would only check against memory constraints. However, the
6064 // meaning of an other constraint can be target-specific and we can't easily
6065 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6066 // for other constriants as well.
6067 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6068 OpInfo.ConstraintType == TargetLowering::C_Other) {
6069 if (OpInfo.Type == InlineAsm::isInput)
6070 ExtraInfo |= InlineAsm::Extra_MayLoad;
6071 else if (OpInfo.Type == InlineAsm::isOutput)
6072 ExtraInfo |= InlineAsm::Extra_MayStore;
6073 else if (OpInfo.Type == InlineAsm::isClobber)
6074 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6078 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6079 TLI.getPointerTy()));
6081 // Loop over all of the inputs, copying the operand values into the
6082 // appropriate registers and processing the output regs.
6083 RegsForValue RetValRegs;
6085 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6086 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6088 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6089 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6091 switch (OpInfo.Type) {
6092 case InlineAsm::isOutput: {
6093 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6094 OpInfo.ConstraintType != TargetLowering::C_Register) {
6095 // Memory output, or 'other' output (e.g. 'X' constraint).
6096 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6098 // Add information to the INLINEASM node to know about this output.
6099 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6100 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6101 TLI.getPointerTy()));
6102 AsmNodeOperands.push_back(OpInfo.CallOperand);
6106 // Otherwise, this is a register or register class output.
6108 // Copy the output from the appropriate register. Find a register that
6110 if (OpInfo.AssignedRegs.Regs.empty()) {
6111 LLVMContext &Ctx = *DAG.getContext();
6112 Ctx.emitError(CS.getInstruction(),
6113 "couldn't allocate output register for constraint '" +
6114 Twine(OpInfo.ConstraintCode) + "'");
6118 // If this is an indirect operand, store through the pointer after the
6120 if (OpInfo.isIndirect) {
6121 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6122 OpInfo.CallOperandVal));
6124 // This is the result value of the call.
6125 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6126 // Concatenate this output onto the outputs list.
6127 RetValRegs.append(OpInfo.AssignedRegs);
6130 // Add information to the INLINEASM node to know that this register is
6132 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6133 InlineAsm::Kind_RegDefEarlyClobber :
6134 InlineAsm::Kind_RegDef,
6141 case InlineAsm::isInput: {
6142 SDValue InOperandVal = OpInfo.CallOperand;
6144 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6145 // If this is required to match an output register we have already set,
6146 // just use its register.
6147 unsigned OperandNo = OpInfo.getMatchedOperand();
6149 // Scan until we find the definition we already emitted of this operand.
6150 // When we find it, create a RegsForValue operand.
6151 unsigned CurOp = InlineAsm::Op_FirstOperand;
6152 for (; OperandNo; --OperandNo) {
6153 // Advance to the next operand.
6155 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6156 assert((InlineAsm::isRegDefKind(OpFlag) ||
6157 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6158 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6159 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6163 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6164 if (InlineAsm::isRegDefKind(OpFlag) ||
6165 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6166 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6167 if (OpInfo.isIndirect) {
6168 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6169 LLVMContext &Ctx = *DAG.getContext();
6170 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6171 " don't know how to handle tied "
6172 "indirect register inputs");
6173 report_fatal_error("Cannot handle indirect register inputs!");
6176 RegsForValue MatchedRegs;
6177 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6178 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6179 MatchedRegs.RegVTs.push_back(RegVT);
6180 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6181 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6183 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6184 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6186 LLVMContext &Ctx = *DAG.getContext();
6187 Ctx.emitError(CS.getInstruction(), "inline asm error: This value"
6188 " type register class is not natively supported!");
6189 report_fatal_error("inline asm error: This value type register "
6190 "class is not natively supported!");
6193 // Use the produced MatchedRegs object to
6194 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6195 Chain, &Flag, CS.getInstruction());
6196 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6197 true, OpInfo.getMatchedOperand(),
6198 DAG, AsmNodeOperands);
6202 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6203 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6204 "Unexpected number of operands");
6205 // Add information to the INLINEASM node to know about this input.
6206 // See InlineAsm.h isUseOperandTiedToDef.
6207 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6208 OpInfo.getMatchedOperand());
6209 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6210 TLI.getPointerTy()));
6211 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6215 // Treat indirect 'X' constraint as memory.
6216 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6218 OpInfo.ConstraintType = TargetLowering::C_Memory;
6220 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6221 std::vector<SDValue> Ops;
6222 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6225 LLVMContext &Ctx = *DAG.getContext();
6226 Ctx.emitError(CS.getInstruction(),
6227 "invalid operand for inline asm constraint '" +
6228 Twine(OpInfo.ConstraintCode) + "'");
6232 // Add information to the INLINEASM node to know about this input.
6233 unsigned ResOpType =
6234 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6235 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6236 TLI.getPointerTy()));
6237 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6241 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6242 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6243 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6244 "Memory operands expect pointer values");
6246 // Add information to the INLINEASM node to know about this input.
6247 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6248 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6249 TLI.getPointerTy()));
6250 AsmNodeOperands.push_back(InOperandVal);
6254 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6255 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6256 "Unknown constraint type!");
6258 // TODO: Support this.
6259 if (OpInfo.isIndirect) {
6260 LLVMContext &Ctx = *DAG.getContext();
6261 Ctx.emitError(CS.getInstruction(),
6262 "Don't know how to handle indirect register inputs yet "
6263 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6267 // Copy the input into the appropriate registers.
6268 if (OpInfo.AssignedRegs.Regs.empty()) {
6269 LLVMContext &Ctx = *DAG.getContext();
6270 Ctx.emitError(CS.getInstruction(),
6271 "couldn't allocate input reg for constraint '" +
6272 Twine(OpInfo.ConstraintCode) + "'");
6276 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6277 Chain, &Flag, CS.getInstruction());
6279 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6280 DAG, AsmNodeOperands);
6283 case InlineAsm::isClobber: {
6284 // Add the clobbered value to the operand list, so that the register
6285 // allocator is aware that the physreg got clobbered.
6286 if (!OpInfo.AssignedRegs.Regs.empty())
6287 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6295 // Finish up input operands. Set the input chain and add the flag last.
6296 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6297 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6299 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6300 DAG.getVTList(MVT::Other, MVT::Glue),
6301 &AsmNodeOperands[0], AsmNodeOperands.size());
6302 Flag = Chain.getValue(1);
6304 // If this asm returns a register value, copy the result from that register
6305 // and set it as the value of the call.
6306 if (!RetValRegs.Regs.empty()) {
6307 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6308 Chain, &Flag, CS.getInstruction());
6310 // FIXME: Why don't we do this for inline asms with MRVs?
6311 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6312 EVT ResultType = TLI.getValueType(CS.getType());
6314 // If any of the results of the inline asm is a vector, it may have the
6315 // wrong width/num elts. This can happen for register classes that can
6316 // contain multiple different value types. The preg or vreg allocated may
6317 // not have the same VT as was expected. Convert it to the right type
6318 // with bit_convert.
6319 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6320 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6323 } else if (ResultType != Val.getValueType() &&
6324 ResultType.isInteger() && Val.getValueType().isInteger()) {
6325 // If a result value was tied to an input value, the computed result may
6326 // have a wider width than the expected result. Extract the relevant
6328 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6331 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6334 setValue(CS.getInstruction(), Val);
6335 // Don't need to use this as a chain in this case.
6336 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6340 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6342 // Process indirect outputs, first output all of the flagged copies out of
6344 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6345 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6346 const Value *Ptr = IndirectStoresToEmit[i].second;
6347 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6349 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6352 // Emit the non-flagged stores from the physregs.
6353 SmallVector<SDValue, 8> OutChains;
6354 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6355 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6356 StoresToEmit[i].first,
6357 getValue(StoresToEmit[i].second),
6358 MachinePointerInfo(StoresToEmit[i].second),
6360 OutChains.push_back(Val);
6363 if (!OutChains.empty())
6364 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6365 &OutChains[0], OutChains.size());
6370 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6371 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6372 MVT::Other, getRoot(),
6373 getValue(I.getArgOperand(0)),
6374 DAG.getSrcValue(I.getArgOperand(0))));
6377 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6378 const DataLayout &TD = *TLI.getDataLayout();
6379 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6380 getRoot(), getValue(I.getOperand(0)),
6381 DAG.getSrcValue(I.getOperand(0)),
6382 TD.getABITypeAlignment(I.getType()));
6384 DAG.setRoot(V.getValue(1));
6387 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6388 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6389 MVT::Other, getRoot(),
6390 getValue(I.getArgOperand(0)),
6391 DAG.getSrcValue(I.getArgOperand(0))));
6394 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6395 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6396 MVT::Other, getRoot(),
6397 getValue(I.getArgOperand(0)),
6398 getValue(I.getArgOperand(1)),
6399 DAG.getSrcValue(I.getArgOperand(0)),
6400 DAG.getSrcValue(I.getArgOperand(1))));
6403 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6404 /// implementation, which just calls LowerCall.
6405 /// FIXME: When all targets are
6406 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6407 std::pair<SDValue, SDValue>
6408 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6409 // Handle the incoming return values from the call.
6411 SmallVector<EVT, 4> RetTys;
6412 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6413 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6415 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6416 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6417 for (unsigned i = 0; i != NumRegs; ++i) {
6418 ISD::InputArg MyFlags;
6419 MyFlags.VT = RegisterVT;
6420 MyFlags.Used = CLI.IsReturnValueUsed;
6422 MyFlags.Flags.setSExt();
6424 MyFlags.Flags.setZExt();
6426 MyFlags.Flags.setInReg();
6427 CLI.Ins.push_back(MyFlags);
6431 // Handle all of the outgoing arguments.
6433 CLI.OutVals.clear();
6434 ArgListTy &Args = CLI.Args;
6435 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6436 SmallVector<EVT, 4> ValueVTs;
6437 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6438 for (unsigned Value = 0, NumValues = ValueVTs.size();
6439 Value != NumValues; ++Value) {
6440 EVT VT = ValueVTs[Value];
6441 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6442 SDValue Op = SDValue(Args[i].Node.getNode(),
6443 Args[i].Node.getResNo() + Value);
6444 ISD::ArgFlagsTy Flags;
6445 unsigned OriginalAlignment =
6446 getDataLayout()->getABITypeAlignment(ArgTy);
6452 if (Args[i].isInReg)
6456 if (Args[i].isByVal) {
6458 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6459 Type *ElementTy = Ty->getElementType();
6460 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6461 // For ByVal, alignment should come from FE. BE will guess if this
6462 // info is not there but there are cases it cannot get right.
6463 unsigned FrameAlign;
6464 if (Args[i].Alignment)
6465 FrameAlign = Args[i].Alignment;
6467 FrameAlign = getByValTypeAlignment(ElementTy);
6468 Flags.setByValAlign(FrameAlign);
6472 Flags.setOrigAlign(OriginalAlignment);
6474 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6475 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6476 SmallVector<SDValue, 4> Parts(NumParts);
6477 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6480 ExtendKind = ISD::SIGN_EXTEND;
6481 else if (Args[i].isZExt)
6482 ExtendKind = ISD::ZERO_EXTEND;
6484 // Conservatively only handle 'returned' on non-vectors for now
6485 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6486 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6487 "unexpected use of 'returned'");
6488 // Before passing 'returned' to the target lowering code, ensure that
6489 // either the register MVT and the actual EVT are the same size or that
6490 // the return value and argument are extended in the same way; in these
6491 // cases it's safe to pass the argument register value unchanged as the
6492 // return register value (although it's at the target's option whether
6494 // TODO: allow code generation to take advantage of partially preserved
6495 // registers rather than clobbering the entire register when the
6496 // parameter extension method is not compatible with the return
6498 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6499 (ExtendKind != ISD::ANY_EXTEND &&
6500 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6501 Flags.setReturned();
6504 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6505 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6507 for (unsigned j = 0; j != NumParts; ++j) {
6508 // if it isn't first piece, alignment must be 1
6509 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6510 i < CLI.NumFixedArgs,
6511 i, j*Parts[j].getValueType().getStoreSize());
6512 if (NumParts > 1 && j == 0)
6513 MyFlags.Flags.setSplit();
6515 MyFlags.Flags.setOrigAlign(1);
6517 CLI.Outs.push_back(MyFlags);
6518 CLI.OutVals.push_back(Parts[j]);
6523 SmallVector<SDValue, 4> InVals;
6524 CLI.Chain = LowerCall(CLI, InVals);
6526 // Verify that the target's LowerCall behaved as expected.
6527 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6528 "LowerCall didn't return a valid chain!");
6529 assert((!CLI.IsTailCall || InVals.empty()) &&
6530 "LowerCall emitted a return value for a tail call!");
6531 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6532 "LowerCall didn't emit the correct number of values!");
6534 // For a tail call, the return value is merely live-out and there aren't
6535 // any nodes in the DAG representing it. Return a special value to
6536 // indicate that a tail call has been emitted and no more Instructions
6537 // should be processed in the current block.
6538 if (CLI.IsTailCall) {
6539 CLI.DAG.setRoot(CLI.Chain);
6540 return std::make_pair(SDValue(), SDValue());
6543 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6544 assert(InVals[i].getNode() &&
6545 "LowerCall emitted a null value!");
6546 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6547 "LowerCall emitted a value with the wrong type!");
6550 // Collect the legal value parts into potentially illegal values
6551 // that correspond to the original function's return values.
6552 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6554 AssertOp = ISD::AssertSext;
6555 else if (CLI.RetZExt)
6556 AssertOp = ISD::AssertZext;
6557 SmallVector<SDValue, 4> ReturnValues;
6558 unsigned CurReg = 0;
6559 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6561 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6562 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6564 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6565 NumRegs, RegisterVT, VT, NULL,
6570 // For a function returning void, there is no return value. We can't create
6571 // such a node, so we just return a null return value in that case. In
6572 // that case, nothing will actually look at the value.
6573 if (ReturnValues.empty())
6574 return std::make_pair(SDValue(), CLI.Chain);
6576 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6577 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6578 &ReturnValues[0], ReturnValues.size());
6579 return std::make_pair(Res, CLI.Chain);
6582 void TargetLowering::LowerOperationWrapper(SDNode *N,
6583 SmallVectorImpl<SDValue> &Results,
6584 SelectionDAG &DAG) const {
6585 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6587 Results.push_back(Res);
6590 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6591 llvm_unreachable("LowerOperation not implemented for this target!");
6595 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6596 SDValue Op = getNonRegisterValue(V);
6597 assert((Op.getOpcode() != ISD::CopyFromReg ||
6598 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6599 "Copy from a reg to the same reg!");
6600 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6602 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6603 SDValue Chain = DAG.getEntryNode();
6604 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V);
6605 PendingExports.push_back(Chain);
6608 #include "llvm/CodeGen/SelectionDAGISel.h"
6610 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6611 /// entry block, return true. This includes arguments used by switches, since
6612 /// the switch may expand into multiple basic blocks.
6613 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6614 // With FastISel active, we may be splitting blocks, so force creation
6615 // of virtual registers for all non-dead arguments.
6617 return A->use_empty();
6619 const BasicBlock *Entry = A->getParent()->begin();
6620 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6622 const User *U = *UI;
6623 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6624 return false; // Use not in entry block.
6629 void SelectionDAGISel::LowerArguments(const Function &F) {
6630 SelectionDAG &DAG = SDB->DAG;
6631 DebugLoc dl = SDB->getCurDebugLoc();
6632 const DataLayout *TD = TLI.getDataLayout();
6633 SmallVector<ISD::InputArg, 16> Ins;
6635 if (!FuncInfo->CanLowerReturn) {
6636 // Put in an sret pointer parameter before all the other parameters.
6637 SmallVector<EVT, 1> ValueVTs;
6638 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6640 // NOTE: Assuming that a pointer will never break down to more than one VT
6642 ISD::ArgFlagsTy Flags;
6644 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6645 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6646 Ins.push_back(RetArg);
6649 // Set up the incoming argument description vector.
6651 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6652 I != E; ++I, ++Idx) {
6653 SmallVector<EVT, 4> ValueVTs;
6654 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6655 bool isArgValueUsed = !I->use_empty();
6656 for (unsigned Value = 0, NumValues = ValueVTs.size();
6657 Value != NumValues; ++Value) {
6658 EVT VT = ValueVTs[Value];
6659 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6660 ISD::ArgFlagsTy Flags;
6661 unsigned OriginalAlignment =
6662 TD->getABITypeAlignment(ArgTy);
6664 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6666 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6668 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
6670 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
6672 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
6674 PointerType *Ty = cast<PointerType>(I->getType());
6675 Type *ElementTy = Ty->getElementType();
6676 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6677 // For ByVal, alignment should be passed from FE. BE will guess if
6678 // this info is not there but there are cases it cannot get right.
6679 unsigned FrameAlign;
6680 if (F.getParamAlignment(Idx))
6681 FrameAlign = F.getParamAlignment(Idx);
6683 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6684 Flags.setByValAlign(FrameAlign);
6686 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
6688 Flags.setOrigAlign(OriginalAlignment);
6690 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6691 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6692 for (unsigned i = 0; i != NumRegs; ++i) {
6693 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6694 Idx-1, i*RegisterVT.getStoreSize());
6695 if (NumRegs > 1 && i == 0)
6696 MyFlags.Flags.setSplit();
6697 // if it isn't first piece, alignment must be 1
6699 MyFlags.Flags.setOrigAlign(1);
6700 Ins.push_back(MyFlags);
6705 // Call the target to set up the argument values.
6706 SmallVector<SDValue, 8> InVals;
6707 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6711 // Verify that the target's LowerFormalArguments behaved as expected.
6712 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6713 "LowerFormalArguments didn't return a valid chain!");
6714 assert(InVals.size() == Ins.size() &&
6715 "LowerFormalArguments didn't emit the correct number of values!");
6717 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6718 assert(InVals[i].getNode() &&
6719 "LowerFormalArguments emitted a null value!");
6720 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6721 "LowerFormalArguments emitted a value with the wrong type!");
6725 // Update the DAG with the new chain value resulting from argument lowering.
6726 DAG.setRoot(NewRoot);
6728 // Set up the argument values.
6731 if (!FuncInfo->CanLowerReturn) {
6732 // Create a virtual register for the sret pointer, and put in a copy
6733 // from the sret argument into it.
6734 SmallVector<EVT, 1> ValueVTs;
6735 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6736 MVT VT = ValueVTs[0].getSimpleVT();
6737 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6738 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6739 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6740 RegVT, VT, NULL, AssertOp);
6742 MachineFunction& MF = SDB->DAG.getMachineFunction();
6743 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6744 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6745 FuncInfo->DemoteRegister = SRetReg;
6746 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6748 DAG.setRoot(NewRoot);
6750 // i indexes lowered arguments. Bump it past the hidden sret argument.
6751 // Idx indexes LLVM arguments. Don't touch it.
6755 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6757 SmallVector<SDValue, 4> ArgValues;
6758 SmallVector<EVT, 4> ValueVTs;
6759 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6760 unsigned NumValues = ValueVTs.size();
6762 // If this argument is unused then remember its value. It is used to generate
6763 // debugging information.
6764 if (I->use_empty() && NumValues) {
6765 SDB->setUnusedArgValue(I, InVals[i]);
6767 // Also remember any frame index for use in FastISel.
6768 if (FrameIndexSDNode *FI =
6769 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
6770 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6773 for (unsigned Val = 0; Val != NumValues; ++Val) {
6774 EVT VT = ValueVTs[Val];
6775 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6776 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6778 if (!I->use_empty()) {
6779 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6780 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6781 AssertOp = ISD::AssertSext;
6782 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6783 AssertOp = ISD::AssertZext;
6785 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6786 NumParts, PartVT, VT,
6793 // We don't need to do anything else for unused arguments.
6794 if (ArgValues.empty())
6797 // Note down frame index.
6798 if (FrameIndexSDNode *FI =
6799 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6800 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6802 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6803 SDB->getCurDebugLoc());
6805 SDB->setValue(I, Res);
6806 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6807 if (LoadSDNode *LNode =
6808 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6809 if (FrameIndexSDNode *FI =
6810 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6811 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6814 // If this argument is live outside of the entry block, insert a copy from
6815 // wherever we got it to the vreg that other BB's will reference it as.
6816 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6817 // If we can, though, try to skip creating an unnecessary vreg.
6818 // FIXME: This isn't very clean... it would be nice to make this more
6819 // general. It's also subtly incompatible with the hacks FastISel
6821 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6822 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6823 FuncInfo->ValueMap[I] = Reg;
6827 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6828 FuncInfo->InitializeRegForValue(I);
6829 SDB->CopyToExportRegsIfNeeded(I);
6833 assert(i == InVals.size() && "Argument register count mismatch!");
6835 // Finally, if the target has anything special to do, allow it to do so.
6836 // FIXME: this should insert code into the DAG!
6837 EmitFunctionEntryCode();
6840 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6841 /// ensure constants are generated when needed. Remember the virtual registers
6842 /// that need to be added to the Machine PHI nodes as input. We cannot just
6843 /// directly add them, because expansion might result in multiple MBB's for one
6844 /// BB. As such, the start of the BB might correspond to a different MBB than
6848 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6849 const TerminatorInst *TI = LLVMBB->getTerminator();
6851 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6853 // Check successor nodes' PHI nodes that expect a constant to be available
6855 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6856 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6857 if (!isa<PHINode>(SuccBB->begin())) continue;
6858 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6860 // If this terminator has multiple identical successors (common for
6861 // switches), only handle each succ once.
6862 if (!SuccsHandled.insert(SuccMBB)) continue;
6864 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6866 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6867 // nodes and Machine PHI nodes, but the incoming operands have not been
6869 for (BasicBlock::const_iterator I = SuccBB->begin();
6870 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6871 // Ignore dead phi's.
6872 if (PN->use_empty()) continue;
6875 if (PN->getType()->isEmptyTy())
6879 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6881 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6882 unsigned &RegOut = ConstantsOut[C];
6884 RegOut = FuncInfo.CreateRegs(C->getType());
6885 CopyValueToVirtualRegister(C, RegOut);
6889 DenseMap<const Value *, unsigned>::iterator I =
6890 FuncInfo.ValueMap.find(PHIOp);
6891 if (I != FuncInfo.ValueMap.end())
6894 assert(isa<AllocaInst>(PHIOp) &&
6895 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6896 "Didn't codegen value into a register!??");
6897 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6898 CopyValueToVirtualRegister(PHIOp, Reg);
6902 // Remember that this register needs to added to the machine PHI node as
6903 // the input for this MBB.
6904 SmallVector<EVT, 4> ValueVTs;
6905 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6906 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6907 EVT VT = ValueVTs[vti];
6908 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6909 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6910 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6911 Reg += NumRegisters;
6915 ConstantsOut.clear();