1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 llvm_unreachable("should never codegen catchpads");
1166 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1167 // Update machine-CFG edge.
1168 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1169 FuncInfo.MBB->addSuccessor(TargetMBB);
1171 // Create the terminator node.
1172 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1173 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1177 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1178 llvm_unreachable("should never codegen catchendpads");
1181 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1182 // Don't emit any special code for the cleanuppad instruction. It just marks
1183 // the start of a funclet.
1184 FuncInfo.MBB->setIsEHFuncletEntry();
1187 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1188 /// many places it could ultimately go. In the IR, we have a single unwind
1189 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1190 /// This function skips over imaginary basic blocks that hold catchpad,
1191 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1192 /// basic block destinations.
1194 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1195 const BasicBlock *EHPadBB,
1196 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1197 bool IsMSVCCXX = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()) ==
1198 EHPersonality::MSVC_CXX;
1200 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1201 if (isa<LandingPadInst>(Pad)) {
1202 // Stop on landingpads. They are not funclets.
1203 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1205 } else if (isa<CleanupPadInst>(Pad) || isa<LandingPadInst>(Pad)) {
1206 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1208 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1209 UnwindDests.back()->setIsEHFuncletEntry();
1211 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1212 // Add the catchpad handler to the possible destinations.
1213 UnwindDests.push_back(FuncInfo.MBBMap[CPI->getNormalDest()]);
1214 // In MSVC C++, catchblocks are funclets and need prologues.
1216 UnwindDests.back()->setIsEHFuncletEntry();
1217 EHPadBB = CPI->getUnwindDest();
1218 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1219 EHPadBB = CEPI->getUnwindDest();
1220 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1221 EHPadBB = CEPI->getUnwindDest();
1226 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1227 // Update successor info.
1228 // FIXME: The weights for catchpads will be wrong.
1229 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1230 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1231 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1232 UnwindDest->setIsEHPad();
1233 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1236 // Create the terminator node.
1238 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1242 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1243 report_fatal_error("visitCleanupEndPad not yet implemented!");
1246 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1247 report_fatal_error("visitTerminatePad not yet implemented!");
1250 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1252 auto &DL = DAG.getDataLayout();
1253 SDValue Chain = getControlRoot();
1254 SmallVector<ISD::OutputArg, 8> Outs;
1255 SmallVector<SDValue, 8> OutVals;
1257 if (!FuncInfo.CanLowerReturn) {
1258 unsigned DemoteReg = FuncInfo.DemoteRegister;
1259 const Function *F = I.getParent()->getParent();
1261 // Emit a store of the return value through the virtual register.
1262 // Leave Outs empty so that LowerReturn won't try to load return
1263 // registers the usual way.
1264 SmallVector<EVT, 1> PtrValueVTs;
1265 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1268 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1269 SDValue RetOp = getValue(I.getOperand(0));
1271 SmallVector<EVT, 4> ValueVTs;
1272 SmallVector<uint64_t, 4> Offsets;
1273 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1274 unsigned NumValues = ValueVTs.size();
1276 SmallVector<SDValue, 4> Chains(NumValues);
1277 for (unsigned i = 0; i != NumValues; ++i) {
1278 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1279 RetPtr.getValueType(), RetPtr,
1280 DAG.getIntPtrConstant(Offsets[i],
1283 DAG.getStore(Chain, getCurSDLoc(),
1284 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1285 // FIXME: better loc info would be nice.
1286 Add, MachinePointerInfo(), false, false, 0);
1289 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1290 MVT::Other, Chains);
1291 } else if (I.getNumOperands() != 0) {
1292 SmallVector<EVT, 4> ValueVTs;
1293 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1294 unsigned NumValues = ValueVTs.size();
1296 SDValue RetOp = getValue(I.getOperand(0));
1298 const Function *F = I.getParent()->getParent();
1300 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1301 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1303 ExtendKind = ISD::SIGN_EXTEND;
1304 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1306 ExtendKind = ISD::ZERO_EXTEND;
1308 LLVMContext &Context = F->getContext();
1309 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1312 for (unsigned j = 0; j != NumValues; ++j) {
1313 EVT VT = ValueVTs[j];
1315 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1316 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1318 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1319 MVT PartVT = TLI.getRegisterType(Context, VT);
1320 SmallVector<SDValue, 4> Parts(NumParts);
1321 getCopyToParts(DAG, getCurSDLoc(),
1322 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1323 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1325 // 'inreg' on function refers to return value
1326 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1330 // Propagate extension type if any
1331 if (ExtendKind == ISD::SIGN_EXTEND)
1333 else if (ExtendKind == ISD::ZERO_EXTEND)
1336 for (unsigned i = 0; i < NumParts; ++i) {
1337 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1338 VT, /*isfixed=*/true, 0, 0));
1339 OutVals.push_back(Parts[i]);
1345 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1346 CallingConv::ID CallConv =
1347 DAG.getMachineFunction().getFunction()->getCallingConv();
1348 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1349 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1351 // Verify that the target's LowerReturn behaved as expected.
1352 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1353 "LowerReturn didn't return a valid chain!");
1355 // Update the DAG with the new chain value resulting from return lowering.
1359 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1360 /// created for it, emit nodes to copy the value into the virtual
1362 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1364 if (V->getType()->isEmptyTy())
1367 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1368 if (VMI != FuncInfo.ValueMap.end()) {
1369 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1370 CopyValueToVirtualRegister(V, VMI->second);
1374 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1375 /// the current basic block, add it to ValueMap now so that we'll get a
1377 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1378 // No need to export constants.
1379 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1381 // Already exported?
1382 if (FuncInfo.isExportedInst(V)) return;
1384 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1385 CopyValueToVirtualRegister(V, Reg);
1388 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1389 const BasicBlock *FromBB) {
1390 // The operands of the setcc have to be in this block. We don't know
1391 // how to export them from some other block.
1392 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1393 // Can export from current BB.
1394 if (VI->getParent() == FromBB)
1397 // Is already exported, noop.
1398 return FuncInfo.isExportedInst(V);
1401 // If this is an argument, we can export it if the BB is the entry block or
1402 // if it is already exported.
1403 if (isa<Argument>(V)) {
1404 if (FromBB == &FromBB->getParent()->getEntryBlock())
1407 // Otherwise, can only export this if it is already exported.
1408 return FuncInfo.isExportedInst(V);
1411 // Otherwise, constants can always be exported.
1415 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1416 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1417 const MachineBasicBlock *Dst) const {
1418 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1421 const BasicBlock *SrcBB = Src->getBasicBlock();
1422 const BasicBlock *DstBB = Dst->getBasicBlock();
1423 return BPI->getEdgeWeight(SrcBB, DstBB);
1426 void SelectionDAGBuilder::
1427 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1428 uint32_t Weight /* = 0 */) {
1430 Weight = getEdgeWeight(Src, Dst);
1431 Src->addSuccessor(Dst, Weight);
1435 static bool InBlock(const Value *V, const BasicBlock *BB) {
1436 if (const Instruction *I = dyn_cast<Instruction>(V))
1437 return I->getParent() == BB;
1441 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1442 /// This function emits a branch and is used at the leaves of an OR or an
1443 /// AND operator tree.
1446 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1447 MachineBasicBlock *TBB,
1448 MachineBasicBlock *FBB,
1449 MachineBasicBlock *CurBB,
1450 MachineBasicBlock *SwitchBB,
1453 const BasicBlock *BB = CurBB->getBasicBlock();
1455 // If the leaf of the tree is a comparison, merge the condition into
1457 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1458 // The operands of the cmp have to be in this block. We don't know
1459 // how to export them from some other block. If this is the first block
1460 // of the sequence, no exporting is needed.
1461 if (CurBB == SwitchBB ||
1462 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1463 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1464 ISD::CondCode Condition;
1465 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1466 Condition = getICmpCondCode(IC->getPredicate());
1468 const FCmpInst *FC = cast<FCmpInst>(Cond);
1469 Condition = getFCmpCondCode(FC->getPredicate());
1470 if (TM.Options.NoNaNsFPMath)
1471 Condition = getFCmpCodeWithoutNaN(Condition);
1474 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1475 TBB, FBB, CurBB, TWeight, FWeight);
1476 SwitchCases.push_back(CB);
1481 // Create a CaseBlock record representing this branch.
1482 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1483 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1484 SwitchCases.push_back(CB);
1487 /// Scale down both weights to fit into uint32_t.
1488 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1489 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1490 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1491 NewTrue = NewTrue / Scale;
1492 NewFalse = NewFalse / Scale;
1495 /// FindMergedConditions - If Cond is an expression like
1496 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1497 MachineBasicBlock *TBB,
1498 MachineBasicBlock *FBB,
1499 MachineBasicBlock *CurBB,
1500 MachineBasicBlock *SwitchBB,
1501 Instruction::BinaryOps Opc,
1504 // If this node is not part of the or/and tree, emit it as a branch.
1505 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1506 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1507 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1508 BOp->getParent() != CurBB->getBasicBlock() ||
1509 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1510 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1511 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1516 // Create TmpBB after CurBB.
1517 MachineFunction::iterator BBI = CurBB;
1518 MachineFunction &MF = DAG.getMachineFunction();
1519 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1520 CurBB->getParent()->insert(++BBI, TmpBB);
1522 if (Opc == Instruction::Or) {
1523 // Codegen X | Y as:
1532 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1533 // The requirement is that
1534 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1535 // = TrueProb for original BB.
1536 // Assuming the original weights are A and B, one choice is to set BB1's
1537 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1539 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1540 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1541 // TmpBB, but the math is more complicated.
1543 uint64_t NewTrueWeight = TWeight;
1544 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1545 ScaleWeights(NewTrueWeight, NewFalseWeight);
1546 // Emit the LHS condition.
1547 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1548 NewTrueWeight, NewFalseWeight);
1550 NewTrueWeight = TWeight;
1551 NewFalseWeight = 2 * (uint64_t)FWeight;
1552 ScaleWeights(NewTrueWeight, NewFalseWeight);
1553 // Emit the RHS condition into TmpBB.
1554 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1555 NewTrueWeight, NewFalseWeight);
1557 assert(Opc == Instruction::And && "Unknown merge op!");
1558 // Codegen X & Y as:
1566 // This requires creation of TmpBB after CurBB.
1568 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1569 // The requirement is that
1570 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1571 // = FalseProb for original BB.
1572 // Assuming the original weights are A and B, one choice is to set BB1's
1573 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1575 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1577 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1578 uint64_t NewFalseWeight = FWeight;
1579 ScaleWeights(NewTrueWeight, NewFalseWeight);
1580 // Emit the LHS condition.
1581 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1582 NewTrueWeight, NewFalseWeight);
1584 NewTrueWeight = 2 * (uint64_t)TWeight;
1585 NewFalseWeight = FWeight;
1586 ScaleWeights(NewTrueWeight, NewFalseWeight);
1587 // Emit the RHS condition into TmpBB.
1588 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1589 NewTrueWeight, NewFalseWeight);
1593 /// If the set of cases should be emitted as a series of branches, return true.
1594 /// If we should emit this as a bunch of and/or'd together conditions, return
1597 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1598 if (Cases.size() != 2) return true;
1600 // If this is two comparisons of the same values or'd or and'd together, they
1601 // will get folded into a single comparison, so don't emit two blocks.
1602 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1603 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1604 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1605 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1609 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1610 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1611 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1612 Cases[0].CC == Cases[1].CC &&
1613 isa<Constant>(Cases[0].CmpRHS) &&
1614 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1615 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1617 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1624 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1625 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1627 // Update machine-CFG edges.
1628 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1630 if (I.isUnconditional()) {
1631 // Update machine-CFG edges.
1632 BrMBB->addSuccessor(Succ0MBB);
1634 // If this is not a fall-through branch or optimizations are switched off,
1636 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1637 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1638 MVT::Other, getControlRoot(),
1639 DAG.getBasicBlock(Succ0MBB)));
1644 // If this condition is one of the special cases we handle, do special stuff
1646 const Value *CondVal = I.getCondition();
1647 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1649 // If this is a series of conditions that are or'd or and'd together, emit
1650 // this as a sequence of branches instead of setcc's with and/or operations.
1651 // As long as jumps are not expensive, this should improve performance.
1652 // For example, instead of something like:
1665 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1666 Instruction::BinaryOps Opcode = BOp->getOpcode();
1667 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1668 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1669 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1670 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1671 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1672 getEdgeWeight(BrMBB, Succ1MBB));
1673 // If the compares in later blocks need to use values not currently
1674 // exported from this block, export them now. This block should always
1675 // be the first entry.
1676 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1678 // Allow some cases to be rejected.
1679 if (ShouldEmitAsBranches(SwitchCases)) {
1680 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1681 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1682 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1685 // Emit the branch for this block.
1686 visitSwitchCase(SwitchCases[0], BrMBB);
1687 SwitchCases.erase(SwitchCases.begin());
1691 // Okay, we decided not to do this, remove any inserted MBB's and clear
1693 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1694 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1696 SwitchCases.clear();
1700 // Create a CaseBlock record representing this branch.
1701 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1702 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1704 // Use visitSwitchCase to actually insert the fast branch sequence for this
1706 visitSwitchCase(CB, BrMBB);
1709 /// visitSwitchCase - Emits the necessary code to represent a single node in
1710 /// the binary search tree resulting from lowering a switch instruction.
1711 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1712 MachineBasicBlock *SwitchBB) {
1714 SDValue CondLHS = getValue(CB.CmpLHS);
1715 SDLoc dl = getCurSDLoc();
1717 // Build the setcc now.
1719 // Fold "(X == true)" to X and "(X == false)" to !X to
1720 // handle common cases produced by branch lowering.
1721 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1722 CB.CC == ISD::SETEQ)
1724 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1725 CB.CC == ISD::SETEQ) {
1726 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1727 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1729 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1731 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1733 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1734 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1736 SDValue CmpOp = getValue(CB.CmpMHS);
1737 EVT VT = CmpOp.getValueType();
1739 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1740 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1743 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1744 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1745 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1746 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1750 // Update successor info
1751 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1752 // TrueBB and FalseBB are always different unless the incoming IR is
1753 // degenerate. This only happens when running llc on weird IR.
1754 if (CB.TrueBB != CB.FalseBB)
1755 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1757 // If the lhs block is the next block, invert the condition so that we can
1758 // fall through to the lhs instead of the rhs block.
1759 if (CB.TrueBB == NextBlock(SwitchBB)) {
1760 std::swap(CB.TrueBB, CB.FalseBB);
1761 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1762 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1765 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1766 MVT::Other, getControlRoot(), Cond,
1767 DAG.getBasicBlock(CB.TrueBB));
1769 // Insert the false branch. Do this even if it's a fall through branch,
1770 // this makes it easier to do DAG optimizations which require inverting
1771 // the branch condition.
1772 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1773 DAG.getBasicBlock(CB.FalseBB));
1775 DAG.setRoot(BrCond);
1778 /// visitJumpTable - Emit JumpTable node in the current MBB
1779 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1780 // Emit the code for the jump table
1781 assert(JT.Reg != -1U && "Should lower JT Header first!");
1782 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1783 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1785 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1786 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1787 MVT::Other, Index.getValue(1),
1789 DAG.setRoot(BrJumpTable);
1792 /// visitJumpTableHeader - This function emits necessary code to produce index
1793 /// in the JumpTable from switch case.
1794 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1795 JumpTableHeader &JTH,
1796 MachineBasicBlock *SwitchBB) {
1797 SDLoc dl = getCurSDLoc();
1799 // Subtract the lowest switch case value from the value being switched on and
1800 // conditional branch to default mbb if the result is greater than the
1801 // difference between smallest and largest cases.
1802 SDValue SwitchOp = getValue(JTH.SValue);
1803 EVT VT = SwitchOp.getValueType();
1804 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1805 DAG.getConstant(JTH.First, dl, VT));
1807 // The SDNode we just created, which holds the value being switched on minus
1808 // the smallest case value, needs to be copied to a virtual register so it
1809 // can be used as an index into the jump table in a subsequent basic block.
1810 // This value may be smaller or larger than the target's pointer type, and
1811 // therefore require extension or truncating.
1812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1813 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1815 unsigned JumpTableReg =
1816 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1817 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1818 JumpTableReg, SwitchOp);
1819 JT.Reg = JumpTableReg;
1821 // Emit the range check for the jump table, and branch to the default block
1822 // for the switch statement if the value being switched on exceeds the largest
1823 // case in the switch.
1824 SDValue CMP = DAG.getSetCC(
1825 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1826 Sub.getValueType()),
1827 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1829 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1830 MVT::Other, CopyTo, CMP,
1831 DAG.getBasicBlock(JT.Default));
1833 // Avoid emitting unnecessary branches to the next block.
1834 if (JT.MBB != NextBlock(SwitchBB))
1835 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1836 DAG.getBasicBlock(JT.MBB));
1838 DAG.setRoot(BrCond);
1841 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1842 /// tail spliced into a stack protector check success bb.
1844 /// For a high level explanation of how this fits into the stack protector
1845 /// generation see the comment on the declaration of class
1846 /// StackProtectorDescriptor.
1847 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1848 MachineBasicBlock *ParentBB) {
1850 // First create the loads to the guard/stack slot for the comparison.
1851 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1852 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1854 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1855 int FI = MFI->getStackProtectorIndex();
1857 const Value *IRGuard = SPD.getGuard();
1858 SDValue GuardPtr = getValue(IRGuard);
1859 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1861 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1864 SDLoc dl = getCurSDLoc();
1866 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1867 // guard value from the virtual register holding the value. Otherwise, emit a
1868 // volatile load to retrieve the stack guard value.
1869 unsigned GuardReg = SPD.getGuardReg();
1871 if (GuardReg && TLI.useLoadStackGuardNode())
1872 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1875 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1876 GuardPtr, MachinePointerInfo(IRGuard, 0),
1877 true, false, false, Align);
1879 SDValue StackSlot = DAG.getLoad(
1880 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1881 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1882 false, false, Align);
1884 // Perform the comparison via a subtract/getsetcc.
1885 EVT VT = Guard.getValueType();
1886 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1888 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1890 Sub.getValueType()),
1891 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1893 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1894 // branch to failure MBB.
1895 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1896 MVT::Other, StackSlot.getOperand(0),
1897 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1898 // Otherwise branch to success MBB.
1899 SDValue Br = DAG.getNode(ISD::BR, dl,
1901 DAG.getBasicBlock(SPD.getSuccessMBB()));
1906 /// Codegen the failure basic block for a stack protector check.
1908 /// A failure stack protector machine basic block consists simply of a call to
1909 /// __stack_chk_fail().
1911 /// For a high level explanation of how this fits into the stack protector
1912 /// generation see the comment on the declaration of class
1913 /// StackProtectorDescriptor.
1915 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1916 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1918 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1919 nullptr, 0, false, getCurSDLoc(), false, false).second;
1923 /// visitBitTestHeader - This function emits necessary code to produce value
1924 /// suitable for "bit tests"
1925 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1926 MachineBasicBlock *SwitchBB) {
1927 SDLoc dl = getCurSDLoc();
1929 // Subtract the minimum value
1930 SDValue SwitchOp = getValue(B.SValue);
1931 EVT VT = SwitchOp.getValueType();
1932 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1933 DAG.getConstant(B.First, dl, VT));
1936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1937 SDValue RangeCmp = DAG.getSetCC(
1938 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1939 Sub.getValueType()),
1940 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1942 // Determine the type of the test operands.
1943 bool UsePtrType = false;
1944 if (!TLI.isTypeLegal(VT))
1947 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1948 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1949 // Switch table case range are encoded into series of masks.
1950 // Just use pointer type, it's guaranteed to fit.
1956 VT = TLI.getPointerTy(DAG.getDataLayout());
1957 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1960 B.RegVT = VT.getSimpleVT();
1961 B.Reg = FuncInfo.CreateReg(B.RegVT);
1962 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1964 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1966 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1967 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1969 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1970 MVT::Other, CopyTo, RangeCmp,
1971 DAG.getBasicBlock(B.Default));
1973 // Avoid emitting unnecessary branches to the next block.
1974 if (MBB != NextBlock(SwitchBB))
1975 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1976 DAG.getBasicBlock(MBB));
1978 DAG.setRoot(BrRange);
1981 /// visitBitTestCase - this function produces one "bit test"
1982 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1983 MachineBasicBlock* NextMBB,
1984 uint32_t BranchWeightToNext,
1987 MachineBasicBlock *SwitchBB) {
1988 SDLoc dl = getCurSDLoc();
1990 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1992 unsigned PopCount = countPopulation(B.Mask);
1993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1994 if (PopCount == 1) {
1995 // Testing for a single bit; just compare the shift count with what it
1996 // would need to be to shift a 1 bit in that position.
1998 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1999 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2001 } else if (PopCount == BB.Range) {
2002 // There is only one zero bit in the range, test for it directly.
2004 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2005 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2008 // Make desired shift
2009 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2010 DAG.getConstant(1, dl, VT), ShiftOp);
2012 // Emit bit tests and jumps
2013 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2014 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2016 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2017 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2020 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2021 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2022 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2023 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2025 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2026 MVT::Other, getControlRoot(),
2027 Cmp, DAG.getBasicBlock(B.TargetBB));
2029 // Avoid emitting unnecessary branches to the next block.
2030 if (NextMBB != NextBlock(SwitchBB))
2031 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2032 DAG.getBasicBlock(NextMBB));
2037 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2038 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2040 // Retrieve successors. Look through artificial IR level blocks like catchpads
2041 // and catchendpads for successors.
2042 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2043 const BasicBlock *EHPadBB = I.getSuccessor(1);
2045 const Value *Callee(I.getCalledValue());
2046 const Function *Fn = dyn_cast<Function>(Callee);
2047 if (isa<InlineAsm>(Callee))
2049 else if (Fn && Fn->isIntrinsic()) {
2050 switch (Fn->getIntrinsicID()) {
2052 llvm_unreachable("Cannot invoke this intrinsic");
2053 case Intrinsic::donothing:
2054 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2056 case Intrinsic::experimental_patchpoint_void:
2057 case Intrinsic::experimental_patchpoint_i64:
2058 visitPatchpoint(&I, EHPadBB);
2060 case Intrinsic::experimental_gc_statepoint:
2061 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2065 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2067 // If the value of the invoke is used outside of its defining block, make it
2068 // available as a virtual register.
2069 // We already took care of the exported value for the statepoint instruction
2070 // during call to the LowerStatepoint.
2071 if (!isStatepoint(I)) {
2072 CopyToExportRegsIfNeeded(&I);
2075 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2076 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2078 // Update successor info.
2079 // FIXME: The weights for catchpads will be wrong.
2080 addSuccessorWithWeight(InvokeMBB, Return);
2081 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2082 UnwindDest->setIsEHPad();
2083 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2086 // Drop into normal successor.
2087 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2088 MVT::Other, getControlRoot(),
2089 DAG.getBasicBlock(Return)));
2092 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2093 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2096 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2097 assert(FuncInfo.MBB->isEHPad() &&
2098 "Call to landingpad not in landing pad!");
2100 MachineBasicBlock *MBB = FuncInfo.MBB;
2101 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2102 AddLandingPadInfo(LP, MMI, MBB);
2104 // If there aren't registers to copy the values into (e.g., during SjLj
2105 // exceptions), then don't bother to create these DAG nodes.
2106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2107 if (TLI.getExceptionPointerRegister() == 0 &&
2108 TLI.getExceptionSelectorRegister() == 0)
2111 SmallVector<EVT, 2> ValueVTs;
2112 SDLoc dl = getCurSDLoc();
2113 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2114 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2116 // Get the two live-in registers as SDValues. The physregs have already been
2117 // copied into virtual registers.
2119 if (FuncInfo.ExceptionPointerVirtReg) {
2120 Ops[0] = DAG.getZExtOrTrunc(
2121 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2122 FuncInfo.ExceptionPointerVirtReg,
2123 TLI.getPointerTy(DAG.getDataLayout())),
2126 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2128 Ops[1] = DAG.getZExtOrTrunc(
2129 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2130 FuncInfo.ExceptionSelectorVirtReg,
2131 TLI.getPointerTy(DAG.getDataLayout())),
2135 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2136 DAG.getVTList(ValueVTs), Ops);
2140 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2142 for (const CaseCluster &CC : Clusters)
2143 assert(CC.Low == CC.High && "Input clusters must be single-case");
2146 std::sort(Clusters.begin(), Clusters.end(),
2147 [](const CaseCluster &a, const CaseCluster &b) {
2148 return a.Low->getValue().slt(b.Low->getValue());
2151 // Merge adjacent clusters with the same destination.
2152 const unsigned N = Clusters.size();
2153 unsigned DstIndex = 0;
2154 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2155 CaseCluster &CC = Clusters[SrcIndex];
2156 const ConstantInt *CaseVal = CC.Low;
2157 MachineBasicBlock *Succ = CC.MBB;
2159 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2160 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2161 // If this case has the same successor and is a neighbour, merge it into
2162 // the previous cluster.
2163 Clusters[DstIndex - 1].High = CaseVal;
2164 Clusters[DstIndex - 1].Weight += CC.Weight;
2165 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2167 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2168 sizeof(Clusters[SrcIndex]));
2171 Clusters.resize(DstIndex);
2174 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2175 MachineBasicBlock *Last) {
2177 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2178 if (JTCases[i].first.HeaderBB == First)
2179 JTCases[i].first.HeaderBB = Last;
2181 // Update BitTestCases.
2182 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2183 if (BitTestCases[i].Parent == First)
2184 BitTestCases[i].Parent = Last;
2187 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2188 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2190 // Update machine-CFG edges with unique successors.
2191 SmallSet<BasicBlock*, 32> Done;
2192 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2193 BasicBlock *BB = I.getSuccessor(i);
2194 bool Inserted = Done.insert(BB).second;
2198 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2199 addSuccessorWithWeight(IndirectBrMBB, Succ);
2202 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2203 MVT::Other, getControlRoot(),
2204 getValue(I.getAddress())));
2207 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2208 if (DAG.getTarget().Options.TrapUnreachable)
2209 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2212 void SelectionDAGBuilder::visitFSub(const User &I) {
2213 // -0.0 - X --> fneg
2214 Type *Ty = I.getType();
2215 if (isa<Constant>(I.getOperand(0)) &&
2216 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2217 SDValue Op2 = getValue(I.getOperand(1));
2218 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2219 Op2.getValueType(), Op2));
2223 visitBinary(I, ISD::FSUB);
2226 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2227 SDValue Op1 = getValue(I.getOperand(0));
2228 SDValue Op2 = getValue(I.getOperand(1));
2235 if (const OverflowingBinaryOperator *OFBinOp =
2236 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2237 nuw = OFBinOp->hasNoUnsignedWrap();
2238 nsw = OFBinOp->hasNoSignedWrap();
2240 if (const PossiblyExactOperator *ExactOp =
2241 dyn_cast<const PossiblyExactOperator>(&I))
2242 exact = ExactOp->isExact();
2243 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2244 FMF = FPOp->getFastMathFlags();
2247 Flags.setExact(exact);
2248 Flags.setNoSignedWrap(nsw);
2249 Flags.setNoUnsignedWrap(nuw);
2250 if (EnableFMFInDAG) {
2251 Flags.setAllowReciprocal(FMF.allowReciprocal());
2252 Flags.setNoInfs(FMF.noInfs());
2253 Flags.setNoNaNs(FMF.noNaNs());
2254 Flags.setNoSignedZeros(FMF.noSignedZeros());
2255 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2257 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2259 setValue(&I, BinNodeValue);
2262 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2263 SDValue Op1 = getValue(I.getOperand(0));
2264 SDValue Op2 = getValue(I.getOperand(1));
2266 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2267 Op2.getValueType(), DAG.getDataLayout());
2269 // Coerce the shift amount to the right type if we can.
2270 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2271 unsigned ShiftSize = ShiftTy.getSizeInBits();
2272 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2273 SDLoc DL = getCurSDLoc();
2275 // If the operand is smaller than the shift count type, promote it.
2276 if (ShiftSize > Op2Size)
2277 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2279 // If the operand is larger than the shift count type but the shift
2280 // count type has enough bits to represent any shift value, truncate
2281 // it now. This is a common case and it exposes the truncate to
2282 // optimization early.
2283 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2284 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2285 // Otherwise we'll need to temporarily settle for some other convenient
2286 // type. Type legalization will make adjustments once the shiftee is split.
2288 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2295 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2297 if (const OverflowingBinaryOperator *OFBinOp =
2298 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2299 nuw = OFBinOp->hasNoUnsignedWrap();
2300 nsw = OFBinOp->hasNoSignedWrap();
2302 if (const PossiblyExactOperator *ExactOp =
2303 dyn_cast<const PossiblyExactOperator>(&I))
2304 exact = ExactOp->isExact();
2307 Flags.setExact(exact);
2308 Flags.setNoSignedWrap(nsw);
2309 Flags.setNoUnsignedWrap(nuw);
2310 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2315 void SelectionDAGBuilder::visitSDiv(const User &I) {
2316 SDValue Op1 = getValue(I.getOperand(0));
2317 SDValue Op2 = getValue(I.getOperand(1));
2320 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2321 cast<PossiblyExactOperator>(&I)->isExact());
2322 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2326 void SelectionDAGBuilder::visitICmp(const User &I) {
2327 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2328 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2329 predicate = IC->getPredicate();
2330 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2331 predicate = ICmpInst::Predicate(IC->getPredicate());
2332 SDValue Op1 = getValue(I.getOperand(0));
2333 SDValue Op2 = getValue(I.getOperand(1));
2334 ISD::CondCode Opcode = getICmpCondCode(predicate);
2336 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2338 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2341 void SelectionDAGBuilder::visitFCmp(const User &I) {
2342 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2343 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2344 predicate = FC->getPredicate();
2345 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2346 predicate = FCmpInst::Predicate(FC->getPredicate());
2347 SDValue Op1 = getValue(I.getOperand(0));
2348 SDValue Op2 = getValue(I.getOperand(1));
2349 ISD::CondCode Condition = getFCmpCondCode(predicate);
2350 if (TM.Options.NoNaNsFPMath)
2351 Condition = getFCmpCodeWithoutNaN(Condition);
2352 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2354 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2357 void SelectionDAGBuilder::visitSelect(const User &I) {
2358 SmallVector<EVT, 4> ValueVTs;
2359 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2361 unsigned NumValues = ValueVTs.size();
2362 if (NumValues == 0) return;
2364 SmallVector<SDValue, 4> Values(NumValues);
2365 SDValue Cond = getValue(I.getOperand(0));
2366 SDValue LHSVal = getValue(I.getOperand(1));
2367 SDValue RHSVal = getValue(I.getOperand(2));
2368 auto BaseOps = {Cond};
2369 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2370 ISD::VSELECT : ISD::SELECT;
2372 // Min/max matching is only viable if all output VTs are the same.
2373 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2374 EVT VT = ValueVTs[0];
2375 LLVMContext &Ctx = *DAG.getContext();
2376 auto &TLI = DAG.getTargetLoweringInfo();
2377 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2378 VT = TLI.getTypeToTransformTo(Ctx, VT);
2381 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2382 ISD::NodeType Opc = ISD::DELETED_NODE;
2383 switch (SPR.Flavor) {
2384 case SPF_UMAX: Opc = ISD::UMAX; break;
2385 case SPF_UMIN: Opc = ISD::UMIN; break;
2386 case SPF_SMAX: Opc = ISD::SMAX; break;
2387 case SPF_SMIN: Opc = ISD::SMIN; break;
2389 switch (SPR.NaNBehavior) {
2390 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2391 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2392 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2393 case SPNB_RETURNS_ANY:
2394 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2400 switch (SPR.NaNBehavior) {
2401 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2402 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2403 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2404 case SPNB_RETURNS_ANY:
2405 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2413 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2414 // If the underlying comparison instruction is used by any other instruction,
2415 // the consumed instructions won't be destroyed, so it is not profitable
2416 // to convert to a min/max.
2417 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2419 LHSVal = getValue(LHS);
2420 RHSVal = getValue(RHS);
2425 for (unsigned i = 0; i != NumValues; ++i) {
2426 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2427 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2428 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2429 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2430 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2434 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2435 DAG.getVTList(ValueVTs), Values));
2438 void SelectionDAGBuilder::visitTrunc(const User &I) {
2439 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2440 SDValue N = getValue(I.getOperand(0));
2441 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2443 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2446 void SelectionDAGBuilder::visitZExt(const User &I) {
2447 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2448 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2449 SDValue N = getValue(I.getOperand(0));
2450 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2452 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2455 void SelectionDAGBuilder::visitSExt(const User &I) {
2456 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2457 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2458 SDValue N = getValue(I.getOperand(0));
2459 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2461 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2464 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2465 // FPTrunc is never a no-op cast, no need to check
2466 SDValue N = getValue(I.getOperand(0));
2467 SDLoc dl = getCurSDLoc();
2468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2469 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2470 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2471 DAG.getTargetConstant(
2472 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2475 void SelectionDAGBuilder::visitFPExt(const User &I) {
2476 // FPExt is never a no-op cast, no need to check
2477 SDValue N = getValue(I.getOperand(0));
2478 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2480 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2483 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2484 // FPToUI is never a no-op cast, no need to check
2485 SDValue N = getValue(I.getOperand(0));
2486 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2488 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2491 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2492 // FPToSI is never a no-op cast, no need to check
2493 SDValue N = getValue(I.getOperand(0));
2494 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2496 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2499 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2500 // UIToFP is never a no-op cast, no need to check
2501 SDValue N = getValue(I.getOperand(0));
2502 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2504 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2507 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2508 // SIToFP is never a no-op cast, no need to check
2509 SDValue N = getValue(I.getOperand(0));
2510 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2512 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2515 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2516 // What to do depends on the size of the integer and the size of the pointer.
2517 // We can either truncate, zero extend, or no-op, accordingly.
2518 SDValue N = getValue(I.getOperand(0));
2519 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2521 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2524 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2525 // What to do depends on the size of the integer and the size of the pointer.
2526 // We can either truncate, zero extend, or no-op, accordingly.
2527 SDValue N = getValue(I.getOperand(0));
2528 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2530 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2533 void SelectionDAGBuilder::visitBitCast(const User &I) {
2534 SDValue N = getValue(I.getOperand(0));
2535 SDLoc dl = getCurSDLoc();
2536 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2539 // BitCast assures us that source and destination are the same size so this is
2540 // either a BITCAST or a no-op.
2541 if (DestVT != N.getValueType())
2542 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2543 DestVT, N)); // convert types.
2544 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2545 // might fold any kind of constant expression to an integer constant and that
2546 // is not what we are looking for. Only regcognize a bitcast of a genuine
2547 // constant integer as an opaque constant.
2548 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2549 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2552 setValue(&I, N); // noop cast.
2555 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2556 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2557 const Value *SV = I.getOperand(0);
2558 SDValue N = getValue(SV);
2559 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2561 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2562 unsigned DestAS = I.getType()->getPointerAddressSpace();
2564 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2565 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2570 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2571 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2572 SDValue InVec = getValue(I.getOperand(0));
2573 SDValue InVal = getValue(I.getOperand(1));
2574 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2575 TLI.getVectorIdxTy(DAG.getDataLayout()));
2576 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2577 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2578 InVec, InVal, InIdx));
2581 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2582 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2583 SDValue InVec = getValue(I.getOperand(0));
2584 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2585 TLI.getVectorIdxTy(DAG.getDataLayout()));
2586 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2587 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2591 // Utility for visitShuffleVector - Return true if every element in Mask,
2592 // beginning from position Pos and ending in Pos+Size, falls within the
2593 // specified sequential range [L, L+Pos). or is undef.
2594 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2595 unsigned Pos, unsigned Size, int Low) {
2596 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2597 if (Mask[i] >= 0 && Mask[i] != Low)
2602 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2603 SDValue Src1 = getValue(I.getOperand(0));
2604 SDValue Src2 = getValue(I.getOperand(1));
2606 SmallVector<int, 8> Mask;
2607 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2608 unsigned MaskNumElts = Mask.size();
2610 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2611 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2612 EVT SrcVT = Src1.getValueType();
2613 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2615 if (SrcNumElts == MaskNumElts) {
2616 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2621 // Normalize the shuffle vector since mask and vector length don't match.
2622 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2623 // Mask is longer than the source vectors and is a multiple of the source
2624 // vectors. We can use concatenate vector to make the mask and vectors
2626 if (SrcNumElts*2 == MaskNumElts) {
2627 // First check for Src1 in low and Src2 in high
2628 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2629 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2630 // The shuffle is concatenating two vectors together.
2631 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2635 // Then check for Src2 in low and Src1 in high
2636 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2637 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2638 // The shuffle is concatenating two vectors together.
2639 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2645 // Pad both vectors with undefs to make them the same length as the mask.
2646 unsigned NumConcat = MaskNumElts / SrcNumElts;
2647 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2648 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2649 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2651 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2652 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2656 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2657 getCurSDLoc(), VT, MOps1);
2658 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2659 getCurSDLoc(), VT, MOps2);
2661 // Readjust mask for new input vector length.
2662 SmallVector<int, 8> MappedOps;
2663 for (unsigned i = 0; i != MaskNumElts; ++i) {
2665 if (Idx >= (int)SrcNumElts)
2666 Idx -= SrcNumElts - MaskNumElts;
2667 MappedOps.push_back(Idx);
2670 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2675 if (SrcNumElts > MaskNumElts) {
2676 // Analyze the access pattern of the vector to see if we can extract
2677 // two subvectors and do the shuffle. The analysis is done by calculating
2678 // the range of elements the mask access on both vectors.
2679 int MinRange[2] = { static_cast<int>(SrcNumElts),
2680 static_cast<int>(SrcNumElts)};
2681 int MaxRange[2] = {-1, -1};
2683 for (unsigned i = 0; i != MaskNumElts; ++i) {
2689 if (Idx >= (int)SrcNumElts) {
2693 if (Idx > MaxRange[Input])
2694 MaxRange[Input] = Idx;
2695 if (Idx < MinRange[Input])
2696 MinRange[Input] = Idx;
2699 // Check if the access is smaller than the vector size and can we find
2700 // a reasonable extract index.
2701 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2703 int StartIdx[2]; // StartIdx to extract from
2704 for (unsigned Input = 0; Input < 2; ++Input) {
2705 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2706 RangeUse[Input] = 0; // Unused
2707 StartIdx[Input] = 0;
2711 // Find a good start index that is a multiple of the mask length. Then
2712 // see if the rest of the elements are in range.
2713 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2714 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2715 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2716 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2719 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2720 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2723 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2724 // Extract appropriate subvector and generate a vector shuffle
2725 for (unsigned Input = 0; Input < 2; ++Input) {
2726 SDValue &Src = Input == 0 ? Src1 : Src2;
2727 if (RangeUse[Input] == 0)
2728 Src = DAG.getUNDEF(VT);
2730 SDLoc dl = getCurSDLoc();
2732 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2733 DAG.getConstant(StartIdx[Input], dl,
2734 TLI.getVectorIdxTy(DAG.getDataLayout())));
2738 // Calculate new mask.
2739 SmallVector<int, 8> MappedOps;
2740 for (unsigned i = 0; i != MaskNumElts; ++i) {
2743 if (Idx < (int)SrcNumElts)
2746 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2748 MappedOps.push_back(Idx);
2751 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2757 // We can't use either concat vectors or extract subvectors so fall back to
2758 // replacing the shuffle with extract and build vector.
2759 // to insert and build vector.
2760 EVT EltVT = VT.getVectorElementType();
2761 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2762 SDLoc dl = getCurSDLoc();
2763 SmallVector<SDValue,8> Ops;
2764 for (unsigned i = 0; i != MaskNumElts; ++i) {
2769 Res = DAG.getUNDEF(EltVT);
2771 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2772 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2774 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2775 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2781 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2784 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2785 const Value *Op0 = I.getOperand(0);
2786 const Value *Op1 = I.getOperand(1);
2787 Type *AggTy = I.getType();
2788 Type *ValTy = Op1->getType();
2789 bool IntoUndef = isa<UndefValue>(Op0);
2790 bool FromUndef = isa<UndefValue>(Op1);
2792 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2794 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2795 SmallVector<EVT, 4> AggValueVTs;
2796 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2797 SmallVector<EVT, 4> ValValueVTs;
2798 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2800 unsigned NumAggValues = AggValueVTs.size();
2801 unsigned NumValValues = ValValueVTs.size();
2802 SmallVector<SDValue, 4> Values(NumAggValues);
2804 // Ignore an insertvalue that produces an empty object
2805 if (!NumAggValues) {
2806 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2810 SDValue Agg = getValue(Op0);
2812 // Copy the beginning value(s) from the original aggregate.
2813 for (; i != LinearIndex; ++i)
2814 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2815 SDValue(Agg.getNode(), Agg.getResNo() + i);
2816 // Copy values from the inserted value(s).
2818 SDValue Val = getValue(Op1);
2819 for (; i != LinearIndex + NumValValues; ++i)
2820 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2821 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2823 // Copy remaining value(s) from the original aggregate.
2824 for (; i != NumAggValues; ++i)
2825 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2826 SDValue(Agg.getNode(), Agg.getResNo() + i);
2828 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2829 DAG.getVTList(AggValueVTs), Values));
2832 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2833 const Value *Op0 = I.getOperand(0);
2834 Type *AggTy = Op0->getType();
2835 Type *ValTy = I.getType();
2836 bool OutOfUndef = isa<UndefValue>(Op0);
2838 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2841 SmallVector<EVT, 4> ValValueVTs;
2842 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2844 unsigned NumValValues = ValValueVTs.size();
2846 // Ignore a extractvalue that produces an empty object
2847 if (!NumValValues) {
2848 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2852 SmallVector<SDValue, 4> Values(NumValValues);
2854 SDValue Agg = getValue(Op0);
2855 // Copy out the selected value(s).
2856 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2857 Values[i - LinearIndex] =
2859 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2860 SDValue(Agg.getNode(), Agg.getResNo() + i);
2862 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2863 DAG.getVTList(ValValueVTs), Values));
2866 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2867 Value *Op0 = I.getOperand(0);
2868 // Note that the pointer operand may be a vector of pointers. Take the scalar
2869 // element which holds a pointer.
2870 Type *Ty = Op0->getType()->getScalarType();
2871 unsigned AS = Ty->getPointerAddressSpace();
2872 SDValue N = getValue(Op0);
2873 SDLoc dl = getCurSDLoc();
2875 // Normalize Vector GEP - all scalar operands should be converted to the
2877 unsigned VectorWidth = I.getType()->isVectorTy() ?
2878 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2880 if (VectorWidth && !N.getValueType().isVector()) {
2881 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2882 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2883 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2885 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2887 const Value *Idx = *OI;
2888 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2889 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2892 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2893 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2894 DAG.getConstant(Offset, dl, N.getValueType()));
2897 Ty = StTy->getElementType(Field);
2899 Ty = cast<SequentialType>(Ty)->getElementType();
2901 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2902 unsigned PtrSize = PtrTy.getSizeInBits();
2903 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2905 // If this is a scalar constant or a splat vector of constants,
2906 // handle it quickly.
2907 const auto *CI = dyn_cast<ConstantInt>(Idx);
2908 if (!CI && isa<ConstantDataVector>(Idx) &&
2909 cast<ConstantDataVector>(Idx)->getSplatValue())
2910 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2915 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2916 SDValue OffsVal = VectorWidth ?
2917 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2918 DAG.getConstant(Offs, dl, PtrTy);
2919 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2923 // N = N + Idx * ElementSize;
2924 SDValue IdxN = getValue(Idx);
2926 if (!IdxN.getValueType().isVector() && VectorWidth) {
2927 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2928 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2929 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2931 // If the index is smaller or larger than intptr_t, truncate or extend
2933 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2935 // If this is a multiply by a power of two, turn it into a shl
2936 // immediately. This is a very common case.
2937 if (ElementSize != 1) {
2938 if (ElementSize.isPowerOf2()) {
2939 unsigned Amt = ElementSize.logBase2();
2940 IdxN = DAG.getNode(ISD::SHL, dl,
2941 N.getValueType(), IdxN,
2942 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2944 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2945 IdxN = DAG.getNode(ISD::MUL, dl,
2946 N.getValueType(), IdxN, Scale);
2950 N = DAG.getNode(ISD::ADD, dl,
2951 N.getValueType(), N, IdxN);
2958 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2959 // If this is a fixed sized alloca in the entry block of the function,
2960 // allocate it statically on the stack.
2961 if (FuncInfo.StaticAllocaMap.count(&I))
2962 return; // getValue will auto-populate this.
2964 SDLoc dl = getCurSDLoc();
2965 Type *Ty = I.getAllocatedType();
2966 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2967 auto &DL = DAG.getDataLayout();
2968 uint64_t TySize = DL.getTypeAllocSize(Ty);
2970 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2972 SDValue AllocSize = getValue(I.getArraySize());
2974 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2975 if (AllocSize.getValueType() != IntPtr)
2976 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2978 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2980 DAG.getConstant(TySize, dl, IntPtr));
2982 // Handle alignment. If the requested alignment is less than or equal to
2983 // the stack alignment, ignore it. If the size is greater than or equal to
2984 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2985 unsigned StackAlign =
2986 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2987 if (Align <= StackAlign)
2990 // Round the size of the allocation up to the stack alignment size
2991 // by add SA-1 to the size.
2992 AllocSize = DAG.getNode(ISD::ADD, dl,
2993 AllocSize.getValueType(), AllocSize,
2994 DAG.getIntPtrConstant(StackAlign - 1, dl));
2996 // Mask out the low bits for alignment purposes.
2997 AllocSize = DAG.getNode(ISD::AND, dl,
2998 AllocSize.getValueType(), AllocSize,
2999 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3002 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3003 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3004 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3006 DAG.setRoot(DSA.getValue(1));
3008 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3011 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3013 return visitAtomicLoad(I);
3015 const Value *SV = I.getOperand(0);
3016 SDValue Ptr = getValue(SV);
3018 Type *Ty = I.getType();
3020 bool isVolatile = I.isVolatile();
3021 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3023 // The IR notion of invariant_load only guarantees that all *non-faulting*
3024 // invariant loads result in the same value. The MI notion of invariant load
3025 // guarantees that the load can be legally moved to any location within its
3026 // containing function. The MI notion of invariant_load is stronger than the
3027 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3028 // with a guarantee that the location being loaded from is dereferenceable
3029 // throughout the function's lifetime.
3031 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3032 isDereferenceablePointer(SV, DAG.getDataLayout());
3033 unsigned Alignment = I.getAlignment();
3036 I.getAAMetadata(AAInfo);
3037 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3040 SmallVector<EVT, 4> ValueVTs;
3041 SmallVector<uint64_t, 4> Offsets;
3042 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3043 unsigned NumValues = ValueVTs.size();
3048 bool ConstantMemory = false;
3049 if (isVolatile || NumValues > MaxParallelChains)
3050 // Serialize volatile loads with other side effects.
3052 else if (AA->pointsToConstantMemory(MemoryLocation(
3053 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3054 // Do not serialize (non-volatile) loads of constant memory with anything.
3055 Root = DAG.getEntryNode();
3056 ConstantMemory = true;
3058 // Do not serialize non-volatile loads against each other.
3059 Root = DAG.getRoot();
3062 SDLoc dl = getCurSDLoc();
3065 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3067 SmallVector<SDValue, 4> Values(NumValues);
3068 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3069 EVT PtrVT = Ptr.getValueType();
3070 unsigned ChainI = 0;
3071 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3072 // Serializing loads here may result in excessive register pressure, and
3073 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3074 // could recover a bit by hoisting nodes upward in the chain by recognizing
3075 // they are side-effect free or do not alias. The optimizer should really
3076 // avoid this case by converting large object/array copies to llvm.memcpy
3077 // (MaxParallelChains should always remain as failsafe).
3078 if (ChainI == MaxParallelChains) {
3079 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3080 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3081 makeArrayRef(Chains.data(), ChainI));
3085 SDValue A = DAG.getNode(ISD::ADD, dl,
3087 DAG.getConstant(Offsets[i], dl, PtrVT));
3088 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3089 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3090 isNonTemporal, isInvariant, Alignment, AAInfo,
3094 Chains[ChainI] = L.getValue(1);
3097 if (!ConstantMemory) {
3098 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3099 makeArrayRef(Chains.data(), ChainI));
3103 PendingLoads.push_back(Chain);
3106 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3107 DAG.getVTList(ValueVTs), Values));
3110 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3112 return visitAtomicStore(I);
3114 const Value *SrcV = I.getOperand(0);
3115 const Value *PtrV = I.getOperand(1);
3117 SmallVector<EVT, 4> ValueVTs;
3118 SmallVector<uint64_t, 4> Offsets;
3119 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3120 SrcV->getType(), ValueVTs, &Offsets);
3121 unsigned NumValues = ValueVTs.size();
3125 // Get the lowered operands. Note that we do this after
3126 // checking if NumResults is zero, because with zero results
3127 // the operands won't have values in the map.
3128 SDValue Src = getValue(SrcV);
3129 SDValue Ptr = getValue(PtrV);
3131 SDValue Root = getRoot();
3132 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3133 EVT PtrVT = Ptr.getValueType();
3134 bool isVolatile = I.isVolatile();
3135 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3136 unsigned Alignment = I.getAlignment();
3137 SDLoc dl = getCurSDLoc();
3140 I.getAAMetadata(AAInfo);
3142 unsigned ChainI = 0;
3143 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3144 // See visitLoad comments.
3145 if (ChainI == MaxParallelChains) {
3146 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3147 makeArrayRef(Chains.data(), ChainI));
3151 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3152 DAG.getConstant(Offsets[i], dl, PtrVT));
3153 SDValue St = DAG.getStore(Root, dl,
3154 SDValue(Src.getNode(), Src.getResNo() + i),
3155 Add, MachinePointerInfo(PtrV, Offsets[i]),
3156 isVolatile, isNonTemporal, Alignment, AAInfo);
3157 Chains[ChainI] = St;
3160 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3161 makeArrayRef(Chains.data(), ChainI));
3162 DAG.setRoot(StoreNode);
3165 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3166 SDLoc sdl = getCurSDLoc();
3168 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3169 Value *PtrOperand = I.getArgOperand(1);
3170 SDValue Ptr = getValue(PtrOperand);
3171 SDValue Src0 = getValue(I.getArgOperand(0));
3172 SDValue Mask = getValue(I.getArgOperand(3));
3173 EVT VT = Src0.getValueType();
3174 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3176 Alignment = DAG.getEVTAlignment(VT);
3179 I.getAAMetadata(AAInfo);
3181 MachineMemOperand *MMO =
3182 DAG.getMachineFunction().
3183 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3184 MachineMemOperand::MOStore, VT.getStoreSize(),
3186 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3188 DAG.setRoot(StoreNode);
3189 setValue(&I, StoreNode);
3192 // Get a uniform base for the Gather/Scatter intrinsic.
3193 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3194 // We try to represent it as a base pointer + vector of indices.
3195 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3196 // The first operand of the GEP may be a single pointer or a vector of pointers
3198 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3200 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3201 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3203 // When the first GEP operand is a single pointer - it is the uniform base we
3204 // are looking for. If first operand of the GEP is a splat vector - we
3205 // extract the spalt value and use it as a uniform base.
3206 // In all other cases the function returns 'false'.
3208 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3209 SelectionDAGBuilder* SDB) {
3211 SelectionDAG& DAG = SDB->DAG;
3212 LLVMContext &Context = *DAG.getContext();
3214 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3215 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3216 if (!GEP || GEP->getNumOperands() > 2)
3219 Value *GEPPtr = GEP->getPointerOperand();
3220 if (!GEPPtr->getType()->isVectorTy())
3222 else if (!(Ptr = getSplatValue(GEPPtr)))
3225 Value *IndexVal = GEP->getOperand(1);
3227 // The operands of the GEP may be defined in another basic block.
3228 // In this case we'll not find nodes for the operands.
3229 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3232 Base = SDB->getValue(Ptr);
3233 Index = SDB->getValue(IndexVal);
3235 // Suppress sign extension.
3236 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3237 if (SDB->findValue(Sext->getOperand(0))) {
3238 IndexVal = Sext->getOperand(0);
3239 Index = SDB->getValue(IndexVal);
3242 if (!Index.getValueType().isVector()) {
3243 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3244 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3245 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3246 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3251 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3252 SDLoc sdl = getCurSDLoc();
3254 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3255 Value *Ptr = I.getArgOperand(1);
3256 SDValue Src0 = getValue(I.getArgOperand(0));
3257 SDValue Mask = getValue(I.getArgOperand(3));
3258 EVT VT = Src0.getValueType();
3259 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3261 Alignment = DAG.getEVTAlignment(VT);
3262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3265 I.getAAMetadata(AAInfo);
3269 Value *BasePtr = Ptr;
3270 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3272 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3273 MachineMemOperand *MMO = DAG.getMachineFunction().
3274 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3275 MachineMemOperand::MOStore, VT.getStoreSize(),
3278 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3279 Index = getValue(Ptr);
3281 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3282 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3284 DAG.setRoot(Scatter);
3285 setValue(&I, Scatter);
3288 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3289 SDLoc sdl = getCurSDLoc();
3291 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3292 Value *PtrOperand = I.getArgOperand(0);
3293 SDValue Ptr = getValue(PtrOperand);
3294 SDValue Src0 = getValue(I.getArgOperand(3));
3295 SDValue Mask = getValue(I.getArgOperand(2));
3297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3298 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3299 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3301 Alignment = DAG.getEVTAlignment(VT);
3304 I.getAAMetadata(AAInfo);
3305 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3307 SDValue InChain = DAG.getRoot();
3308 if (AA->pointsToConstantMemory(MemoryLocation(
3309 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3311 // Do not serialize (non-volatile) loads of constant memory with anything.
3312 InChain = DAG.getEntryNode();
3315 MachineMemOperand *MMO =
3316 DAG.getMachineFunction().
3317 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3318 MachineMemOperand::MOLoad, VT.getStoreSize(),
3319 Alignment, AAInfo, Ranges);
3321 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3323 SDValue OutChain = Load.getValue(1);
3324 DAG.setRoot(OutChain);
3328 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3329 SDLoc sdl = getCurSDLoc();
3331 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3332 Value *Ptr = I.getArgOperand(0);
3333 SDValue Src0 = getValue(I.getArgOperand(3));
3334 SDValue Mask = getValue(I.getArgOperand(2));
3336 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3337 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3338 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3340 Alignment = DAG.getEVTAlignment(VT);
3343 I.getAAMetadata(AAInfo);
3344 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3346 SDValue Root = DAG.getRoot();
3349 Value *BasePtr = Ptr;
3350 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3351 bool ConstantMemory = false;
3353 AA->pointsToConstantMemory(MemoryLocation(
3354 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3356 // Do not serialize (non-volatile) loads of constant memory with anything.
3357 Root = DAG.getEntryNode();
3358 ConstantMemory = true;
3361 MachineMemOperand *MMO =
3362 DAG.getMachineFunction().
3363 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3364 MachineMemOperand::MOLoad, VT.getStoreSize(),
3365 Alignment, AAInfo, Ranges);
3368 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3369 Index = getValue(Ptr);
3371 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3372 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3375 SDValue OutChain = Gather.getValue(1);
3376 if (!ConstantMemory)
3377 PendingLoads.push_back(OutChain);
3378 setValue(&I, Gather);
3381 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3382 SDLoc dl = getCurSDLoc();
3383 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3384 AtomicOrdering FailureOrder = I.getFailureOrdering();
3385 SynchronizationScope Scope = I.getSynchScope();
3387 SDValue InChain = getRoot();
3389 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3390 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3391 SDValue L = DAG.getAtomicCmpSwap(
3392 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3393 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3394 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3395 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3397 SDValue OutChain = L.getValue(2);
3400 DAG.setRoot(OutChain);
3403 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3404 SDLoc dl = getCurSDLoc();
3406 switch (I.getOperation()) {
3407 default: llvm_unreachable("Unknown atomicrmw operation");
3408 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3409 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3410 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3411 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3412 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3413 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3414 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3415 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3416 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3417 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3418 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3420 AtomicOrdering Order = I.getOrdering();
3421 SynchronizationScope Scope = I.getSynchScope();
3423 SDValue InChain = getRoot();
3426 DAG.getAtomic(NT, dl,
3427 getValue(I.getValOperand()).getSimpleValueType(),
3429 getValue(I.getPointerOperand()),
3430 getValue(I.getValOperand()),
3431 I.getPointerOperand(),
3432 /* Alignment=*/ 0, Order, Scope);
3434 SDValue OutChain = L.getValue(1);
3437 DAG.setRoot(OutChain);
3440 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3441 SDLoc dl = getCurSDLoc();
3442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3445 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3446 TLI.getPointerTy(DAG.getDataLayout()));
3447 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3448 TLI.getPointerTy(DAG.getDataLayout()));
3449 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3452 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3453 SDLoc dl = getCurSDLoc();
3454 AtomicOrdering Order = I.getOrdering();
3455 SynchronizationScope Scope = I.getSynchScope();
3457 SDValue InChain = getRoot();
3459 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3460 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3462 if (I.getAlignment() < VT.getSizeInBits() / 8)
3463 report_fatal_error("Cannot generate unaligned atomic load");
3465 MachineMemOperand *MMO =
3466 DAG.getMachineFunction().
3467 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3468 MachineMemOperand::MOVolatile |
3469 MachineMemOperand::MOLoad,
3471 I.getAlignment() ? I.getAlignment() :
3472 DAG.getEVTAlignment(VT));
3474 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3476 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3477 getValue(I.getPointerOperand()), MMO,
3480 SDValue OutChain = L.getValue(1);
3483 DAG.setRoot(OutChain);
3486 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3487 SDLoc dl = getCurSDLoc();
3489 AtomicOrdering Order = I.getOrdering();
3490 SynchronizationScope Scope = I.getSynchScope();
3492 SDValue InChain = getRoot();
3494 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3496 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3498 if (I.getAlignment() < VT.getSizeInBits() / 8)
3499 report_fatal_error("Cannot generate unaligned atomic store");
3502 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3504 getValue(I.getPointerOperand()),
3505 getValue(I.getValueOperand()),
3506 I.getPointerOperand(), I.getAlignment(),
3509 DAG.setRoot(OutChain);
3512 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3514 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3515 unsigned Intrinsic) {
3516 bool HasChain = !I.doesNotAccessMemory();
3517 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3519 // Build the operand list.
3520 SmallVector<SDValue, 8> Ops;
3521 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3523 // We don't need to serialize loads against other loads.
3524 Ops.push_back(DAG.getRoot());
3526 Ops.push_back(getRoot());
3530 // Info is set by getTgtMemInstrinsic
3531 TargetLowering::IntrinsicInfo Info;
3532 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3533 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3535 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3536 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3537 Info.opc == ISD::INTRINSIC_W_CHAIN)
3538 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3539 TLI.getPointerTy(DAG.getDataLayout())));
3541 // Add all operands of the call to the operand list.
3542 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3543 SDValue Op = getValue(I.getArgOperand(i));
3547 SmallVector<EVT, 4> ValueVTs;
3548 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3551 ValueVTs.push_back(MVT::Other);
3553 SDVTList VTs = DAG.getVTList(ValueVTs);
3557 if (IsTgtIntrinsic) {
3558 // This is target intrinsic that touches memory
3559 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3560 VTs, Ops, Info.memVT,
3561 MachinePointerInfo(Info.ptrVal, Info.offset),
3562 Info.align, Info.vol,
3563 Info.readMem, Info.writeMem, Info.size);
3564 } else if (!HasChain) {
3565 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3566 } else if (!I.getType()->isVoidTy()) {
3567 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3569 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3573 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3575 PendingLoads.push_back(Chain);
3580 if (!I.getType()->isVoidTy()) {
3581 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3582 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3583 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3586 setValue(&I, Result);
3590 /// GetSignificand - Get the significand and build it into a floating-point
3591 /// number with exponent of 1:
3593 /// Op = (Op & 0x007fffff) | 0x3f800000;
3595 /// where Op is the hexadecimal representation of floating point value.
3597 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3598 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3599 DAG.getConstant(0x007fffff, dl, MVT::i32));
3600 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3601 DAG.getConstant(0x3f800000, dl, MVT::i32));
3602 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3605 /// GetExponent - Get the exponent:
3607 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3609 /// where Op is the hexadecimal representation of floating point value.
3611 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3613 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3614 DAG.getConstant(0x7f800000, dl, MVT::i32));
3615 SDValue t1 = DAG.getNode(
3616 ISD::SRL, dl, MVT::i32, t0,
3617 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3618 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3619 DAG.getConstant(127, dl, MVT::i32));
3620 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3623 /// getF32Constant - Get 32-bit floating point constant.
3625 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3626 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3630 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3631 SelectionDAG &DAG) {
3632 // IntegerPartOfX = ((int32_t)(t0);
3633 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3635 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3636 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3637 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3639 // IntegerPartOfX <<= 23;
3640 IntegerPartOfX = DAG.getNode(
3641 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3642 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3643 DAG.getDataLayout())));
3645 SDValue TwoToFractionalPartOfX;
3646 if (LimitFloatPrecision <= 6) {
3647 // For floating-point precision of 6:
3649 // TwoToFractionalPartOfX =
3651 // (0.735607626f + 0.252464424f * x) * x;
3653 // error 0.0144103317, which is 6 bits
3654 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3655 getF32Constant(DAG, 0x3e814304, dl));
3656 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3657 getF32Constant(DAG, 0x3f3c50c8, dl));
3658 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3659 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3660 getF32Constant(DAG, 0x3f7f5e7e, dl));
3661 } else if (LimitFloatPrecision <= 12) {
3662 // For floating-point precision of 12:
3664 // TwoToFractionalPartOfX =
3667 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3669 // error 0.000107046256, which is 13 to 14 bits
3670 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3671 getF32Constant(DAG, 0x3da235e3, dl));
3672 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3673 getF32Constant(DAG, 0x3e65b8f3, dl));
3674 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3675 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3676 getF32Constant(DAG, 0x3f324b07, dl));
3677 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3678 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3679 getF32Constant(DAG, 0x3f7ff8fd, dl));
3680 } else { // LimitFloatPrecision <= 18
3681 // For floating-point precision of 18:
3683 // TwoToFractionalPartOfX =
3687 // (0.554906021e-1f +
3688 // (0.961591928e-2f +
3689 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3690 // error 2.47208000*10^(-7), which is better than 18 bits
3691 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3692 getF32Constant(DAG, 0x3924b03e, dl));
3693 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3694 getF32Constant(DAG, 0x3ab24b87, dl));
3695 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3696 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3697 getF32Constant(DAG, 0x3c1d8c17, dl));
3698 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3699 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3700 getF32Constant(DAG, 0x3d634a1d, dl));
3701 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3702 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3703 getF32Constant(DAG, 0x3e75fe14, dl));
3704 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3705 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3706 getF32Constant(DAG, 0x3f317234, dl));
3707 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3708 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3709 getF32Constant(DAG, 0x3f800000, dl));
3712 // Add the exponent into the result in integer domain.
3713 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3714 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3715 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3718 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3719 /// limited-precision mode.
3720 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3721 const TargetLowering &TLI) {
3722 if (Op.getValueType() == MVT::f32 &&
3723 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3725 // Put the exponent in the right bit position for later addition to the
3728 // #define LOG2OFe 1.4426950f
3729 // t0 = Op * LOG2OFe
3730 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3731 getF32Constant(DAG, 0x3fb8aa3b, dl));
3732 return getLimitedPrecisionExp2(t0, dl, DAG);
3735 // No special expansion.
3736 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3739 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3740 /// limited-precision mode.
3741 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3742 const TargetLowering &TLI) {
3743 if (Op.getValueType() == MVT::f32 &&
3744 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3745 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3747 // Scale the exponent by log(2) [0.69314718f].
3748 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3749 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3750 getF32Constant(DAG, 0x3f317218, dl));
3752 // Get the significand and build it into a floating-point number with
3754 SDValue X = GetSignificand(DAG, Op1, dl);
3756 SDValue LogOfMantissa;
3757 if (LimitFloatPrecision <= 6) {
3758 // For floating-point precision of 6:
3762 // (1.4034025f - 0.23903021f * x) * x;
3764 // error 0.0034276066, which is better than 8 bits
3765 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3766 getF32Constant(DAG, 0xbe74c456, dl));
3767 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3768 getF32Constant(DAG, 0x3fb3a2b1, dl));
3769 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3770 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3771 getF32Constant(DAG, 0x3f949a29, dl));
3772 } else if (LimitFloatPrecision <= 12) {
3773 // For floating-point precision of 12:
3779 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3781 // error 0.000061011436, which is 14 bits
3782 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3783 getF32Constant(DAG, 0xbd67b6d6, dl));
3784 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3785 getF32Constant(DAG, 0x3ee4f4b8, dl));
3786 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3787 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3788 getF32Constant(DAG, 0x3fbc278b, dl));
3789 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3790 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3791 getF32Constant(DAG, 0x40348e95, dl));
3792 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3793 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3794 getF32Constant(DAG, 0x3fdef31a, dl));
3795 } else { // LimitFloatPrecision <= 18
3796 // For floating-point precision of 18:
3804 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3806 // error 0.0000023660568, which is better than 18 bits
3807 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3808 getF32Constant(DAG, 0xbc91e5ac, dl));
3809 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3810 getF32Constant(DAG, 0x3e4350aa, dl));
3811 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3812 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3813 getF32Constant(DAG, 0x3f60d3e3, dl));
3814 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3815 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3816 getF32Constant(DAG, 0x4011cdf0, dl));
3817 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3818 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3819 getF32Constant(DAG, 0x406cfd1c, dl));
3820 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3821 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3822 getF32Constant(DAG, 0x408797cb, dl));
3823 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3824 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3825 getF32Constant(DAG, 0x4006dcab, dl));
3828 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3831 // No special expansion.
3832 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3835 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3836 /// limited-precision mode.
3837 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3838 const TargetLowering &TLI) {
3839 if (Op.getValueType() == MVT::f32 &&
3840 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3841 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3843 // Get the exponent.
3844 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3846 // Get the significand and build it into a floating-point number with
3848 SDValue X = GetSignificand(DAG, Op1, dl);
3850 // Different possible minimax approximations of significand in
3851 // floating-point for various degrees of accuracy over [1,2].
3852 SDValue Log2ofMantissa;
3853 if (LimitFloatPrecision <= 6) {
3854 // For floating-point precision of 6:
3856 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3858 // error 0.0049451742, which is more than 7 bits
3859 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3860 getF32Constant(DAG, 0xbeb08fe0, dl));
3861 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3862 getF32Constant(DAG, 0x40019463, dl));
3863 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3864 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3865 getF32Constant(DAG, 0x3fd6633d, dl));
3866 } else if (LimitFloatPrecision <= 12) {
3867 // For floating-point precision of 12:
3873 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3875 // error 0.0000876136000, which is better than 13 bits
3876 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3877 getF32Constant(DAG, 0xbda7262e, dl));
3878 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3879 getF32Constant(DAG, 0x3f25280b, dl));
3880 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3881 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3882 getF32Constant(DAG, 0x4007b923, dl));
3883 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3884 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3885 getF32Constant(DAG, 0x40823e2f, dl));
3886 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3887 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3888 getF32Constant(DAG, 0x4020d29c, dl));
3889 } else { // LimitFloatPrecision <= 18
3890 // For floating-point precision of 18:
3899 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3901 // error 0.0000018516, which is better than 18 bits
3902 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3903 getF32Constant(DAG, 0xbcd2769e, dl));
3904 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3905 getF32Constant(DAG, 0x3e8ce0b9, dl));
3906 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3907 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3908 getF32Constant(DAG, 0x3fa22ae7, dl));
3909 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3910 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3911 getF32Constant(DAG, 0x40525723, dl));
3912 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3913 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3914 getF32Constant(DAG, 0x40aaf200, dl));
3915 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3916 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3917 getF32Constant(DAG, 0x40c39dad, dl));
3918 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3919 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3920 getF32Constant(DAG, 0x4042902c, dl));
3923 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3926 // No special expansion.
3927 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3930 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3931 /// limited-precision mode.
3932 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3933 const TargetLowering &TLI) {
3934 if (Op.getValueType() == MVT::f32 &&
3935 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3936 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3938 // Scale the exponent by log10(2) [0.30102999f].
3939 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3940 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3941 getF32Constant(DAG, 0x3e9a209a, dl));
3943 // Get the significand and build it into a floating-point number with
3945 SDValue X = GetSignificand(DAG, Op1, dl);
3947 SDValue Log10ofMantissa;
3948 if (LimitFloatPrecision <= 6) {
3949 // For floating-point precision of 6:
3951 // Log10ofMantissa =
3953 // (0.60948995f - 0.10380950f * x) * x;
3955 // error 0.0014886165, which is 6 bits
3956 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3957 getF32Constant(DAG, 0xbdd49a13, dl));
3958 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3959 getF32Constant(DAG, 0x3f1c0789, dl));
3960 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3961 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3962 getF32Constant(DAG, 0x3f011300, dl));
3963 } else if (LimitFloatPrecision <= 12) {
3964 // For floating-point precision of 12:
3966 // Log10ofMantissa =
3969 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3971 // error 0.00019228036, which is better than 12 bits
3972 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3973 getF32Constant(DAG, 0x3d431f31, dl));
3974 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3975 getF32Constant(DAG, 0x3ea21fb2, dl));
3976 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3977 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3978 getF32Constant(DAG, 0x3f6ae232, dl));
3979 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3980 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3981 getF32Constant(DAG, 0x3f25f7c3, dl));
3982 } else { // LimitFloatPrecision <= 18
3983 // For floating-point precision of 18:
3985 // Log10ofMantissa =
3990 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3992 // error 0.0000037995730, which is better than 18 bits
3993 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3994 getF32Constant(DAG, 0x3c5d51ce, dl));
3995 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3996 getF32Constant(DAG, 0x3e00685a, dl));
3997 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3998 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3999 getF32Constant(DAG, 0x3efb6798, dl));
4000 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4001 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4002 getF32Constant(DAG, 0x3f88d192, dl));
4003 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4004 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4005 getF32Constant(DAG, 0x3fc4316c, dl));
4006 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4007 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4008 getF32Constant(DAG, 0x3f57ce70, dl));
4011 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4014 // No special expansion.
4015 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4018 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4019 /// limited-precision mode.
4020 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4021 const TargetLowering &TLI) {
4022 if (Op.getValueType() == MVT::f32 &&
4023 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4024 return getLimitedPrecisionExp2(Op, dl, DAG);
4026 // No special expansion.
4027 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4030 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4031 /// limited-precision mode with x == 10.0f.
4032 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4033 SelectionDAG &DAG, const TargetLowering &TLI) {
4034 bool IsExp10 = false;
4035 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4036 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4037 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4039 IsExp10 = LHSC->isExactlyValue(Ten);
4044 // Put the exponent in the right bit position for later addition to the
4047 // #define LOG2OF10 3.3219281f
4048 // t0 = Op * LOG2OF10;
4049 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4050 getF32Constant(DAG, 0x40549a78, dl));
4051 return getLimitedPrecisionExp2(t0, dl, DAG);
4054 // No special expansion.
4055 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4059 /// ExpandPowI - Expand a llvm.powi intrinsic.
4060 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4061 SelectionDAG &DAG) {
4062 // If RHS is a constant, we can expand this out to a multiplication tree,
4063 // otherwise we end up lowering to a call to __powidf2 (for example). When
4064 // optimizing for size, we only want to do this if the expansion would produce
4065 // a small number of multiplies, otherwise we do the full expansion.
4066 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4067 // Get the exponent as a positive value.
4068 unsigned Val = RHSC->getSExtValue();
4069 if ((int)Val < 0) Val = -Val;
4071 // powi(x, 0) -> 1.0
4073 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4075 const Function *F = DAG.getMachineFunction().getFunction();
4076 if (!F->optForSize() ||
4077 // If optimizing for size, don't insert too many multiplies.
4078 // This inserts up to 5 multiplies.
4079 countPopulation(Val) + Log2_32(Val) < 7) {
4080 // We use the simple binary decomposition method to generate the multiply
4081 // sequence. There are more optimal ways to do this (for example,
4082 // powi(x,15) generates one more multiply than it should), but this has
4083 // the benefit of being both really simple and much better than a libcall.
4084 SDValue Res; // Logically starts equal to 1.0
4085 SDValue CurSquare = LHS;
4089 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4091 Res = CurSquare; // 1.0*CurSquare.
4094 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4095 CurSquare, CurSquare);
4099 // If the original was negative, invert the result, producing 1/(x*x*x).
4100 if (RHSC->getSExtValue() < 0)
4101 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4102 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4107 // Otherwise, expand to a libcall.
4108 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4111 // getTruncatedArgReg - Find underlying register used for an truncated
4113 static unsigned getTruncatedArgReg(const SDValue &N) {
4114 if (N.getOpcode() != ISD::TRUNCATE)
4117 const SDValue &Ext = N.getOperand(0);
4118 if (Ext.getOpcode() == ISD::AssertZext ||
4119 Ext.getOpcode() == ISD::AssertSext) {
4120 const SDValue &CFR = Ext.getOperand(0);
4121 if (CFR.getOpcode() == ISD::CopyFromReg)
4122 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4123 if (CFR.getOpcode() == ISD::TRUNCATE)
4124 return getTruncatedArgReg(CFR);
4129 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4130 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4131 /// At the end of instruction selection, they will be inserted to the entry BB.
4132 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4133 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4134 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4135 const Argument *Arg = dyn_cast<Argument>(V);
4139 MachineFunction &MF = DAG.getMachineFunction();
4140 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4142 // Ignore inlined function arguments here.
4144 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4145 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4148 Optional<MachineOperand> Op;
4149 // Some arguments' frame index is recorded during argument lowering.
4150 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4151 Op = MachineOperand::CreateFI(FI);
4153 if (!Op && N.getNode()) {
4155 if (N.getOpcode() == ISD::CopyFromReg)
4156 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4158 Reg = getTruncatedArgReg(N);
4159 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4160 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4161 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4166 Op = MachineOperand::CreateReg(Reg, false);
4170 // Check if ValueMap has reg number.
4171 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4172 if (VMI != FuncInfo.ValueMap.end())
4173 Op = MachineOperand::CreateReg(VMI->second, false);
4176 if (!Op && N.getNode())
4177 // Check if frame index is available.
4178 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4179 if (FrameIndexSDNode *FINode =
4180 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4181 Op = MachineOperand::CreateFI(FINode->getIndex());
4186 assert(Variable->isValidLocationForIntrinsic(DL) &&
4187 "Expected inlined-at fields to agree");
4189 FuncInfo.ArgDbgValues.push_back(
4190 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4191 Op->getReg(), Offset, Variable, Expr));
4193 FuncInfo.ArgDbgValues.push_back(
4194 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4197 .addMetadata(Variable)
4198 .addMetadata(Expr));
4203 // VisualStudio defines setjmp as _setjmp
4204 #if defined(_MSC_VER) && defined(setjmp) && \
4205 !defined(setjmp_undefined_for_msvc)
4206 # pragma push_macro("setjmp")
4208 # define setjmp_undefined_for_msvc
4211 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4212 /// we want to emit this as a call to a named external function, return the name
4213 /// otherwise lower it and return null.
4215 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4217 SDLoc sdl = getCurSDLoc();
4218 DebugLoc dl = getCurDebugLoc();
4221 switch (Intrinsic) {
4223 // By default, turn this into a target intrinsic node.
4224 visitTargetIntrinsic(I, Intrinsic);
4226 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4227 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4228 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4229 case Intrinsic::returnaddress:
4230 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4231 TLI.getPointerTy(DAG.getDataLayout()),
4232 getValue(I.getArgOperand(0))));
4234 case Intrinsic::frameaddress:
4235 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4236 TLI.getPointerTy(DAG.getDataLayout()),
4237 getValue(I.getArgOperand(0))));
4239 case Intrinsic::read_register: {
4240 Value *Reg = I.getArgOperand(0);
4241 SDValue Chain = getRoot();
4243 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4244 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4245 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4246 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4248 DAG.setRoot(Res.getValue(1));
4251 case Intrinsic::write_register: {
4252 Value *Reg = I.getArgOperand(0);
4253 Value *RegValue = I.getArgOperand(1);
4254 SDValue Chain = getRoot();
4256 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4257 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4258 RegName, getValue(RegValue)));
4261 case Intrinsic::setjmp:
4262 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4263 case Intrinsic::longjmp:
4264 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4265 case Intrinsic::memcpy: {
4266 // FIXME: this definition of "user defined address space" is x86-specific
4267 // Assert for address < 256 since we support only user defined address
4269 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4271 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4273 "Unknown address space");
4274 SDValue Op1 = getValue(I.getArgOperand(0));
4275 SDValue Op2 = getValue(I.getArgOperand(1));
4276 SDValue Op3 = getValue(I.getArgOperand(2));
4277 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4279 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4280 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4281 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4282 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4284 MachinePointerInfo(I.getArgOperand(0)),
4285 MachinePointerInfo(I.getArgOperand(1)));
4286 updateDAGForMaybeTailCall(MC);
4289 case Intrinsic::memset: {
4290 // FIXME: this definition of "user defined address space" is x86-specific
4291 // Assert for address < 256 since we support only user defined address
4293 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4295 "Unknown address space");
4296 SDValue Op1 = getValue(I.getArgOperand(0));
4297 SDValue Op2 = getValue(I.getArgOperand(1));
4298 SDValue Op3 = getValue(I.getArgOperand(2));
4299 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4301 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4302 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4303 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4304 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4305 isTC, MachinePointerInfo(I.getArgOperand(0)));
4306 updateDAGForMaybeTailCall(MS);
4309 case Intrinsic::memmove: {
4310 // FIXME: this definition of "user defined address space" is x86-specific
4311 // Assert for address < 256 since we support only user defined address
4313 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4315 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4317 "Unknown address space");
4318 SDValue Op1 = getValue(I.getArgOperand(0));
4319 SDValue Op2 = getValue(I.getArgOperand(1));
4320 SDValue Op3 = getValue(I.getArgOperand(2));
4321 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4323 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4324 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4325 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4326 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4327 isTC, MachinePointerInfo(I.getArgOperand(0)),
4328 MachinePointerInfo(I.getArgOperand(1)));
4329 updateDAGForMaybeTailCall(MM);
4332 case Intrinsic::dbg_declare: {
4333 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4334 DILocalVariable *Variable = DI.getVariable();
4335 DIExpression *Expression = DI.getExpression();
4336 const Value *Address = DI.getAddress();
4337 assert(Variable && "Missing variable");
4339 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4343 // Check if address has undef value.
4344 if (isa<UndefValue>(Address) ||
4345 (Address->use_empty() && !isa<Argument>(Address))) {
4346 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4350 SDValue &N = NodeMap[Address];
4351 if (!N.getNode() && isa<Argument>(Address))
4352 // Check unused arguments map.
4353 N = UnusedArgNodeMap[Address];
4356 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4357 Address = BCI->getOperand(0);
4358 // Parameters are handled specially.
4359 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4361 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4363 if (isParameter && !AI) {
4364 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4366 // Byval parameter. We have a frame index at this point.
4367 SDV = DAG.getFrameIndexDbgValue(
4368 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4370 // Address is an argument, so try to emit its dbg value using
4371 // virtual register info from the FuncInfo.ValueMap.
4372 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4377 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4378 true, 0, dl, SDNodeOrder);
4380 // Can't do anything with other non-AI cases yet.
4381 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4382 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4383 DEBUG(Address->dump());
4386 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4388 // If Address is an argument then try to emit its dbg value using
4389 // virtual register info from the FuncInfo.ValueMap.
4390 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4392 // If variable is pinned by a alloca in dominating bb then
4393 // use StaticAllocaMap.
4394 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4395 if (AI->getParent() != DI.getParent()) {
4396 DenseMap<const AllocaInst*, int>::iterator SI =
4397 FuncInfo.StaticAllocaMap.find(AI);
4398 if (SI != FuncInfo.StaticAllocaMap.end()) {
4399 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4400 0, dl, SDNodeOrder);
4401 DAG.AddDbgValue(SDV, nullptr, false);
4406 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4411 case Intrinsic::dbg_value: {
4412 const DbgValueInst &DI = cast<DbgValueInst>(I);
4413 assert(DI.getVariable() && "Missing variable");
4415 DILocalVariable *Variable = DI.getVariable();
4416 DIExpression *Expression = DI.getExpression();
4417 uint64_t Offset = DI.getOffset();
4418 const Value *V = DI.getValue();
4423 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4424 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4426 DAG.AddDbgValue(SDV, nullptr, false);
4428 // Do not use getValue() in here; we don't want to generate code at
4429 // this point if it hasn't been done yet.
4430 SDValue N = NodeMap[V];
4431 if (!N.getNode() && isa<Argument>(V))
4432 // Check unused arguments map.
4433 N = UnusedArgNodeMap[V];
4435 // A dbg.value for an alloca is always indirect.
4436 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4437 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4439 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4440 IsIndirect, Offset, dl, SDNodeOrder);
4441 DAG.AddDbgValue(SDV, N.getNode(), false);
4443 } else if (!V->use_empty() ) {
4444 // Do not call getValue(V) yet, as we don't want to generate code.
4445 // Remember it for later.
4446 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4447 DanglingDebugInfoMap[V] = DDI;
4449 // We may expand this to cover more cases. One case where we have no
4450 // data available is an unreferenced parameter.
4451 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4455 // Build a debug info table entry.
4456 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4457 V = BCI->getOperand(0);
4458 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4459 // Don't handle byval struct arguments or VLAs, for example.
4461 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4462 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4465 DenseMap<const AllocaInst*, int>::iterator SI =
4466 FuncInfo.StaticAllocaMap.find(AI);
4467 if (SI == FuncInfo.StaticAllocaMap.end())
4468 return nullptr; // VLAs.
4472 case Intrinsic::eh_typeid_for: {
4473 // Find the type id for the given typeinfo.
4474 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4475 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4476 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4481 case Intrinsic::eh_return_i32:
4482 case Intrinsic::eh_return_i64:
4483 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4484 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4487 getValue(I.getArgOperand(0)),
4488 getValue(I.getArgOperand(1))));
4490 case Intrinsic::eh_unwind_init:
4491 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4493 case Intrinsic::eh_dwarf_cfa: {
4494 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4495 TLI.getPointerTy(DAG.getDataLayout()));
4496 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4497 CfaArg.getValueType(),
4498 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4499 CfaArg.getValueType()),
4501 SDValue FA = DAG.getNode(
4502 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4503 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4504 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4508 case Intrinsic::eh_sjlj_callsite: {
4509 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4510 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4511 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4512 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4514 MMI.setCurrentCallSite(CI->getZExtValue());
4517 case Intrinsic::eh_sjlj_functioncontext: {
4518 // Get and store the index of the function context.
4519 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4521 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4522 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4523 MFI->setFunctionContextIndex(FI);
4526 case Intrinsic::eh_sjlj_setjmp: {
4529 Ops[1] = getValue(I.getArgOperand(0));
4530 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4531 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4532 setValue(&I, Op.getValue(0));
4533 DAG.setRoot(Op.getValue(1));
4536 case Intrinsic::eh_sjlj_longjmp: {
4537 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4538 getRoot(), getValue(I.getArgOperand(0))));
4541 case Intrinsic::eh_sjlj_setup_dispatch: {
4542 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4547 case Intrinsic::masked_gather:
4548 visitMaskedGather(I);
4550 case Intrinsic::masked_load:
4553 case Intrinsic::masked_scatter:
4554 visitMaskedScatter(I);
4556 case Intrinsic::masked_store:
4557 visitMaskedStore(I);
4559 case Intrinsic::x86_mmx_pslli_w:
4560 case Intrinsic::x86_mmx_pslli_d:
4561 case Intrinsic::x86_mmx_pslli_q:
4562 case Intrinsic::x86_mmx_psrli_w:
4563 case Intrinsic::x86_mmx_psrli_d:
4564 case Intrinsic::x86_mmx_psrli_q:
4565 case Intrinsic::x86_mmx_psrai_w:
4566 case Intrinsic::x86_mmx_psrai_d: {
4567 SDValue ShAmt = getValue(I.getArgOperand(1));
4568 if (isa<ConstantSDNode>(ShAmt)) {
4569 visitTargetIntrinsic(I, Intrinsic);
4572 unsigned NewIntrinsic = 0;
4573 EVT ShAmtVT = MVT::v2i32;
4574 switch (Intrinsic) {
4575 case Intrinsic::x86_mmx_pslli_w:
4576 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4578 case Intrinsic::x86_mmx_pslli_d:
4579 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4581 case Intrinsic::x86_mmx_pslli_q:
4582 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4584 case Intrinsic::x86_mmx_psrli_w:
4585 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4587 case Intrinsic::x86_mmx_psrli_d:
4588 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4590 case Intrinsic::x86_mmx_psrli_q:
4591 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4593 case Intrinsic::x86_mmx_psrai_w:
4594 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4596 case Intrinsic::x86_mmx_psrai_d:
4597 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4599 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4602 // The vector shift intrinsics with scalars uses 32b shift amounts but
4603 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4605 // We must do this early because v2i32 is not a legal type.
4608 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4609 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4610 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4611 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4612 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4613 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4614 getValue(I.getArgOperand(0)), ShAmt);
4618 case Intrinsic::convertff:
4619 case Intrinsic::convertfsi:
4620 case Intrinsic::convertfui:
4621 case Intrinsic::convertsif:
4622 case Intrinsic::convertuif:
4623 case Intrinsic::convertss:
4624 case Intrinsic::convertsu:
4625 case Intrinsic::convertus:
4626 case Intrinsic::convertuu: {
4627 ISD::CvtCode Code = ISD::CVT_INVALID;
4628 switch (Intrinsic) {
4629 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4630 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4631 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4632 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4633 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4634 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4635 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4636 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4637 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4638 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4640 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4641 const Value *Op1 = I.getArgOperand(0);
4642 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4643 DAG.getValueType(DestVT),
4644 DAG.getValueType(getValue(Op1).getValueType()),
4645 getValue(I.getArgOperand(1)),
4646 getValue(I.getArgOperand(2)),
4651 case Intrinsic::powi:
4652 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4653 getValue(I.getArgOperand(1)), DAG));
4655 case Intrinsic::log:
4656 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4658 case Intrinsic::log2:
4659 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4661 case Intrinsic::log10:
4662 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4664 case Intrinsic::exp:
4665 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4667 case Intrinsic::exp2:
4668 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4670 case Intrinsic::pow:
4671 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4672 getValue(I.getArgOperand(1)), DAG, TLI));
4674 case Intrinsic::sqrt:
4675 case Intrinsic::fabs:
4676 case Intrinsic::sin:
4677 case Intrinsic::cos:
4678 case Intrinsic::floor:
4679 case Intrinsic::ceil:
4680 case Intrinsic::trunc:
4681 case Intrinsic::rint:
4682 case Intrinsic::nearbyint:
4683 case Intrinsic::round: {
4685 switch (Intrinsic) {
4686 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4687 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4688 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4689 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4690 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4691 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4692 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4693 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4694 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4695 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4696 case Intrinsic::round: Opcode = ISD::FROUND; break;
4699 setValue(&I, DAG.getNode(Opcode, sdl,
4700 getValue(I.getArgOperand(0)).getValueType(),
4701 getValue(I.getArgOperand(0))));
4704 case Intrinsic::minnum:
4705 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4706 getValue(I.getArgOperand(0)).getValueType(),
4707 getValue(I.getArgOperand(0)),
4708 getValue(I.getArgOperand(1))));
4710 case Intrinsic::maxnum:
4711 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4712 getValue(I.getArgOperand(0)).getValueType(),
4713 getValue(I.getArgOperand(0)),
4714 getValue(I.getArgOperand(1))));
4716 case Intrinsic::copysign:
4717 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4718 getValue(I.getArgOperand(0)).getValueType(),
4719 getValue(I.getArgOperand(0)),
4720 getValue(I.getArgOperand(1))));
4722 case Intrinsic::fma:
4723 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4724 getValue(I.getArgOperand(0)).getValueType(),
4725 getValue(I.getArgOperand(0)),
4726 getValue(I.getArgOperand(1)),
4727 getValue(I.getArgOperand(2))));
4729 case Intrinsic::fmuladd: {
4730 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4731 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4732 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4733 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4734 getValue(I.getArgOperand(0)).getValueType(),
4735 getValue(I.getArgOperand(0)),
4736 getValue(I.getArgOperand(1)),
4737 getValue(I.getArgOperand(2))));
4739 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4740 getValue(I.getArgOperand(0)).getValueType(),
4741 getValue(I.getArgOperand(0)),
4742 getValue(I.getArgOperand(1)));
4743 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4744 getValue(I.getArgOperand(0)).getValueType(),
4746 getValue(I.getArgOperand(2)));
4751 case Intrinsic::convert_to_fp16:
4752 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4753 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4754 getValue(I.getArgOperand(0)),
4755 DAG.getTargetConstant(0, sdl,
4758 case Intrinsic::convert_from_fp16:
4759 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4760 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4761 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4762 getValue(I.getArgOperand(0)))));
4764 case Intrinsic::pcmarker: {
4765 SDValue Tmp = getValue(I.getArgOperand(0));
4766 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4769 case Intrinsic::readcyclecounter: {
4770 SDValue Op = getRoot();
4771 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4772 DAG.getVTList(MVT::i64, MVT::Other), Op);
4774 DAG.setRoot(Res.getValue(1));
4777 case Intrinsic::bswap:
4778 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4779 getValue(I.getArgOperand(0)).getValueType(),
4780 getValue(I.getArgOperand(0))));
4782 case Intrinsic::uabsdiff:
4783 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4784 getValue(I.getArgOperand(0)).getValueType(),
4785 getValue(I.getArgOperand(0)),
4786 getValue(I.getArgOperand(1))));
4788 case Intrinsic::sabsdiff:
4789 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4790 getValue(I.getArgOperand(0)).getValueType(),
4791 getValue(I.getArgOperand(0)),
4792 getValue(I.getArgOperand(1))));
4794 case Intrinsic::cttz: {
4795 SDValue Arg = getValue(I.getArgOperand(0));
4796 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4797 EVT Ty = Arg.getValueType();
4798 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4802 case Intrinsic::ctlz: {
4803 SDValue Arg = getValue(I.getArgOperand(0));
4804 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4805 EVT Ty = Arg.getValueType();
4806 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4810 case Intrinsic::ctpop: {
4811 SDValue Arg = getValue(I.getArgOperand(0));
4812 EVT Ty = Arg.getValueType();
4813 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4816 case Intrinsic::stacksave: {
4817 SDValue Op = getRoot();
4819 ISD::STACKSAVE, sdl,
4820 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4822 DAG.setRoot(Res.getValue(1));
4825 case Intrinsic::stackrestore: {
4826 Res = getValue(I.getArgOperand(0));
4827 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4830 case Intrinsic::stackprotector: {
4831 // Emit code into the DAG to store the stack guard onto the stack.
4832 MachineFunction &MF = DAG.getMachineFunction();
4833 MachineFrameInfo *MFI = MF.getFrameInfo();
4834 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4835 SDValue Src, Chain = getRoot();
4836 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4837 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4839 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4840 // global variable __stack_chk_guard.
4842 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4843 if (BC->getOpcode() == Instruction::BitCast)
4844 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4846 if (GV && TLI.useLoadStackGuardNode()) {
4847 // Emit a LOAD_STACK_GUARD node.
4848 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4850 MachinePointerInfo MPInfo(GV);
4851 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4852 unsigned Flags = MachineMemOperand::MOLoad |
4853 MachineMemOperand::MOInvariant;
4854 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4855 PtrTy.getSizeInBits() / 8,
4856 DAG.getEVTAlignment(PtrTy));
4857 Node->setMemRefs(MemRefs, MemRefs + 1);
4859 // Copy the guard value to a virtual register so that it can be
4860 // retrieved in the epilogue.
4861 Src = SDValue(Node, 0);
4862 const TargetRegisterClass *RC =
4863 TLI.getRegClassFor(Src.getSimpleValueType());
4864 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4866 SPDescriptor.setGuardReg(Reg);
4867 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4869 Src = getValue(I.getArgOperand(0)); // The guard's value.
4872 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4874 int FI = FuncInfo.StaticAllocaMap[Slot];
4875 MFI->setStackProtectorIndex(FI);
4877 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4879 // Store the stack protector onto the stack.
4880 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4881 DAG.getMachineFunction(), FI),
4887 case Intrinsic::objectsize: {
4888 // If we don't know by now, we're never going to know.
4889 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4891 assert(CI && "Non-constant type in __builtin_object_size?");
4893 SDValue Arg = getValue(I.getCalledValue());
4894 EVT Ty = Arg.getValueType();
4897 Res = DAG.getConstant(-1ULL, sdl, Ty);
4899 Res = DAG.getConstant(0, sdl, Ty);
4904 case Intrinsic::annotation:
4905 case Intrinsic::ptr_annotation:
4906 // Drop the intrinsic, but forward the value
4907 setValue(&I, getValue(I.getOperand(0)));
4909 case Intrinsic::assume:
4910 case Intrinsic::var_annotation:
4911 // Discard annotate attributes and assumptions
4914 case Intrinsic::init_trampoline: {
4915 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4919 Ops[1] = getValue(I.getArgOperand(0));
4920 Ops[2] = getValue(I.getArgOperand(1));
4921 Ops[3] = getValue(I.getArgOperand(2));
4922 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4923 Ops[5] = DAG.getSrcValue(F);
4925 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4930 case Intrinsic::adjust_trampoline: {
4931 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4932 TLI.getPointerTy(DAG.getDataLayout()),
4933 getValue(I.getArgOperand(0))));
4936 case Intrinsic::gcroot:
4938 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4939 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4941 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4942 GFI->addStackRoot(FI->getIndex(), TypeMap);
4945 case Intrinsic::gcread:
4946 case Intrinsic::gcwrite:
4947 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4948 case Intrinsic::flt_rounds:
4949 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4952 case Intrinsic::expect: {
4953 // Just replace __builtin_expect(exp, c) with EXP.
4954 setValue(&I, getValue(I.getArgOperand(0)));
4958 case Intrinsic::debugtrap:
4959 case Intrinsic::trap: {
4960 StringRef TrapFuncName =
4962 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4963 .getValueAsString();
4964 if (TrapFuncName.empty()) {
4965 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4966 ISD::TRAP : ISD::DEBUGTRAP;
4967 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4970 TargetLowering::ArgListTy Args;
4972 TargetLowering::CallLoweringInfo CLI(DAG);
4973 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4974 CallingConv::C, I.getType(),
4975 DAG.getExternalSymbol(TrapFuncName.data(),
4976 TLI.getPointerTy(DAG.getDataLayout())),
4977 std::move(Args), 0);
4979 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4980 DAG.setRoot(Result.second);
4984 case Intrinsic::uadd_with_overflow:
4985 case Intrinsic::sadd_with_overflow:
4986 case Intrinsic::usub_with_overflow:
4987 case Intrinsic::ssub_with_overflow:
4988 case Intrinsic::umul_with_overflow:
4989 case Intrinsic::smul_with_overflow: {
4991 switch (Intrinsic) {
4992 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4993 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4994 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4995 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4996 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4997 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4998 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5000 SDValue Op1 = getValue(I.getArgOperand(0));
5001 SDValue Op2 = getValue(I.getArgOperand(1));
5003 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5004 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5007 case Intrinsic::prefetch: {
5009 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5011 Ops[1] = getValue(I.getArgOperand(0));
5012 Ops[2] = getValue(I.getArgOperand(1));
5013 Ops[3] = getValue(I.getArgOperand(2));
5014 Ops[4] = getValue(I.getArgOperand(3));
5015 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5016 DAG.getVTList(MVT::Other), Ops,
5017 EVT::getIntegerVT(*Context, 8),
5018 MachinePointerInfo(I.getArgOperand(0)),
5020 false, /* volatile */
5022 rw==1)); /* write */
5025 case Intrinsic::lifetime_start:
5026 case Intrinsic::lifetime_end: {
5027 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5028 // Stack coloring is not enabled in O0, discard region information.
5029 if (TM.getOptLevel() == CodeGenOpt::None)
5032 SmallVector<Value *, 4> Allocas;
5033 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5035 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5036 E = Allocas.end(); Object != E; ++Object) {
5037 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5039 // Could not find an Alloca.
5040 if (!LifetimeObject)
5043 // First check that the Alloca is static, otherwise it won't have a
5044 // valid frame index.
5045 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5046 if (SI == FuncInfo.StaticAllocaMap.end())
5049 int FI = SI->second;
5054 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5055 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5057 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5062 case Intrinsic::invariant_start:
5063 // Discard region information.
5064 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5066 case Intrinsic::invariant_end:
5067 // Discard region information.
5069 case Intrinsic::stackprotectorcheck: {
5070 // Do not actually emit anything for this basic block. Instead we initialize
5071 // the stack protector descriptor and export the guard variable so we can
5072 // access it in FinishBasicBlock.
5073 const BasicBlock *BB = I.getParent();
5074 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5075 ExportFromCurrentBlock(SPDescriptor.getGuard());
5077 // Flush our exports since we are going to process a terminator.
5078 (void)getControlRoot();
5081 case Intrinsic::clear_cache:
5082 return TLI.getClearCacheBuiltinName();
5083 case Intrinsic::eh_actions:
5084 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5086 case Intrinsic::donothing:
5089 case Intrinsic::experimental_stackmap: {
5093 case Intrinsic::experimental_patchpoint_void:
5094 case Intrinsic::experimental_patchpoint_i64: {
5095 visitPatchpoint(&I);
5098 case Intrinsic::experimental_gc_statepoint: {
5102 case Intrinsic::experimental_gc_result_int:
5103 case Intrinsic::experimental_gc_result_float:
5104 case Intrinsic::experimental_gc_result_ptr:
5105 case Intrinsic::experimental_gc_result: {
5109 case Intrinsic::experimental_gc_relocate: {
5113 case Intrinsic::instrprof_increment:
5114 llvm_unreachable("instrprof failed to lower an increment");
5116 case Intrinsic::localescape: {
5117 MachineFunction &MF = DAG.getMachineFunction();
5118 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5120 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5121 // is the same on all targets.
5122 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5123 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5124 if (isa<ConstantPointerNull>(Arg))
5125 continue; // Skip null pointers. They represent a hole in index space.
5126 AllocaInst *Slot = cast<AllocaInst>(Arg);
5127 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5128 "can only escape static allocas");
5129 int FI = FuncInfo.StaticAllocaMap[Slot];
5130 MCSymbol *FrameAllocSym =
5131 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5132 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5134 TII->get(TargetOpcode::LOCAL_ESCAPE))
5135 .addSym(FrameAllocSym)
5142 case Intrinsic::localrecover: {
5143 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5144 MachineFunction &MF = DAG.getMachineFunction();
5145 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5147 // Get the symbol that defines the frame offset.
5148 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5149 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5150 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5151 MCSymbol *FrameAllocSym =
5152 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5153 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5155 // Create a MCSymbol for the label to avoid any target lowering
5156 // that would make this PC relative.
5157 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5159 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5161 // Add the offset to the FP.
5162 Value *FP = I.getArgOperand(1);
5163 SDValue FPVal = getValue(FP);
5164 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5169 case Intrinsic::eh_begincatch:
5170 case Intrinsic::eh_endcatch:
5171 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5172 case Intrinsic::eh_exceptioncode: {
5173 unsigned Reg = TLI.getExceptionPointerRegister();
5174 assert(Reg && "cannot get exception code on this platform");
5175 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5176 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5177 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5178 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5180 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5181 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5188 std::pair<SDValue, SDValue>
5189 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5190 const BasicBlock *EHPadBB) {
5191 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5192 MCSymbol *BeginLabel = nullptr;
5195 // Insert a label before the invoke call to mark the try range. This can be
5196 // used to detect deletion of the invoke via the MachineModuleInfo.
5197 BeginLabel = MMI.getContext().createTempSymbol();
5199 // For SjLj, keep track of which landing pads go with which invokes
5200 // so as to maintain the ordering of pads in the LSDA.
5201 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5202 if (CallSiteIndex) {
5203 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5204 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5206 // Now that the call site is handled, stop tracking it.
5207 MMI.setCurrentCallSite(0);
5210 // Both PendingLoads and PendingExports must be flushed here;
5211 // this call might not return.
5213 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5215 CLI.setChain(getRoot());
5217 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5218 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5220 assert((CLI.IsTailCall || Result.second.getNode()) &&
5221 "Non-null chain expected with non-tail call!");
5222 assert((Result.second.getNode() || !Result.first.getNode()) &&
5223 "Null value expected with tail call!");
5225 if (!Result.second.getNode()) {
5226 // As a special case, a null chain means that a tail call has been emitted
5227 // and the DAG root is already updated.
5230 // Since there's no actual continuation from this block, nothing can be
5231 // relying on us setting vregs for them.
5232 PendingExports.clear();
5234 DAG.setRoot(Result.second);
5238 // Insert a label at the end of the invoke call to mark the try range. This
5239 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5240 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5241 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5243 // Inform MachineModuleInfo of range.
5244 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5250 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5252 const BasicBlock *EHPadBB) {
5253 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5254 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5255 Type *RetTy = FTy->getReturnType();
5257 TargetLowering::ArgListTy Args;
5258 TargetLowering::ArgListEntry Entry;
5259 Args.reserve(CS.arg_size());
5261 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5263 const Value *V = *i;
5266 if (V->getType()->isEmptyTy())
5269 SDValue ArgNode = getValue(V);
5270 Entry.Node = ArgNode; Entry.Ty = V->getType();
5272 // Skip the first return-type Attribute to get to params.
5273 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5274 Args.push_back(Entry);
5276 // If we have an explicit sret argument that is an Instruction, (i.e., it
5277 // might point to function-local memory), we can't meaningfully tail-call.
5278 if (Entry.isSRet && isa<Instruction>(V))
5282 // Check if target-independent constraints permit a tail call here.
5283 // Target-dependent constraints are checked within TLI->LowerCallTo.
5284 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5287 TargetLowering::CallLoweringInfo CLI(DAG);
5288 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5289 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5290 .setTailCall(isTailCall);
5291 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5293 if (Result.first.getNode())
5294 setValue(CS.getInstruction(), Result.first);
5297 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5298 /// value is equal or not-equal to zero.
5299 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5300 for (const User *U : V->users()) {
5301 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5302 if (IC->isEquality())
5303 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5304 if (C->isNullValue())
5306 // Unknown instruction.
5312 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5314 SelectionDAGBuilder &Builder) {
5316 // Check to see if this load can be trivially constant folded, e.g. if the
5317 // input is from a string literal.
5318 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5319 // Cast pointer to the type we really want to load.
5320 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5321 PointerType::getUnqual(LoadTy));
5323 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5324 const_cast<Constant *>(LoadInput), *Builder.DL))
5325 return Builder.getValue(LoadCst);
5328 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5329 // still constant memory, the input chain can be the entry node.
5331 bool ConstantMemory = false;
5333 // Do not serialize (non-volatile) loads of constant memory with anything.
5334 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5335 Root = Builder.DAG.getEntryNode();
5336 ConstantMemory = true;
5338 // Do not serialize non-volatile loads against each other.
5339 Root = Builder.DAG.getRoot();
5342 SDValue Ptr = Builder.getValue(PtrVal);
5343 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5344 Ptr, MachinePointerInfo(PtrVal),
5346 false /*nontemporal*/,
5347 false /*isinvariant*/, 1 /* align=1 */);
5349 if (!ConstantMemory)
5350 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5354 /// processIntegerCallValue - Record the value for an instruction that
5355 /// produces an integer result, converting the type where necessary.
5356 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5359 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5362 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5364 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5365 setValue(&I, Value);
5368 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5369 /// If so, return true and lower it, otherwise return false and it will be
5370 /// lowered like a normal call.
5371 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5372 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5373 if (I.getNumArgOperands() != 3)
5376 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5377 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5378 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5379 !I.getType()->isIntegerTy())
5382 const Value *Size = I.getArgOperand(2);
5383 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5384 if (CSize && CSize->getZExtValue() == 0) {
5385 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5387 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5391 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5392 std::pair<SDValue, SDValue> Res =
5393 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5394 getValue(LHS), getValue(RHS), getValue(Size),
5395 MachinePointerInfo(LHS),
5396 MachinePointerInfo(RHS));
5397 if (Res.first.getNode()) {
5398 processIntegerCallValue(I, Res.first, true);
5399 PendingLoads.push_back(Res.second);
5403 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5404 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5405 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5406 bool ActuallyDoIt = true;
5409 switch (CSize->getZExtValue()) {
5411 LoadVT = MVT::Other;
5413 ActuallyDoIt = false;
5417 LoadTy = Type::getInt16Ty(CSize->getContext());
5421 LoadTy = Type::getInt32Ty(CSize->getContext());
5425 LoadTy = Type::getInt64Ty(CSize->getContext());
5429 LoadVT = MVT::v4i32;
5430 LoadTy = Type::getInt32Ty(CSize->getContext());
5431 LoadTy = VectorType::get(LoadTy, 4);
5436 // This turns into unaligned loads. We only do this if the target natively
5437 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5438 // we'll only produce a small number of byte loads.
5440 // Require that we can find a legal MVT, and only do this if the target
5441 // supports unaligned loads of that type. Expanding into byte loads would
5443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5444 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5445 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5446 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5447 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5448 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5449 // TODO: Check alignment of src and dest ptrs.
5450 if (!TLI.isTypeLegal(LoadVT) ||
5451 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5452 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5453 ActuallyDoIt = false;
5457 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5458 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5460 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5462 processIntegerCallValue(I, Res, false);
5471 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5472 /// form. If so, return true and lower it, otherwise return false and it
5473 /// will be lowered like a normal call.
5474 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5475 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5476 if (I.getNumArgOperands() != 3)
5479 const Value *Src = I.getArgOperand(0);
5480 const Value *Char = I.getArgOperand(1);
5481 const Value *Length = I.getArgOperand(2);
5482 if (!Src->getType()->isPointerTy() ||
5483 !Char->getType()->isIntegerTy() ||
5484 !Length->getType()->isIntegerTy() ||
5485 !I.getType()->isPointerTy())
5488 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5489 std::pair<SDValue, SDValue> Res =
5490 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5491 getValue(Src), getValue(Char), getValue(Length),
5492 MachinePointerInfo(Src));
5493 if (Res.first.getNode()) {
5494 setValue(&I, Res.first);
5495 PendingLoads.push_back(Res.second);
5502 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5503 /// optimized form. If so, return true and lower it, otherwise return false
5504 /// and it will be lowered like a normal call.
5505 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5506 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5507 if (I.getNumArgOperands() != 2)
5510 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5511 if (!Arg0->getType()->isPointerTy() ||
5512 !Arg1->getType()->isPointerTy() ||
5513 !I.getType()->isPointerTy())
5516 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5517 std::pair<SDValue, SDValue> Res =
5518 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5519 getValue(Arg0), getValue(Arg1),
5520 MachinePointerInfo(Arg0),
5521 MachinePointerInfo(Arg1), isStpcpy);
5522 if (Res.first.getNode()) {
5523 setValue(&I, Res.first);
5524 DAG.setRoot(Res.second);
5531 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5532 /// If so, return true and lower it, otherwise return false and it will be
5533 /// lowered like a normal call.
5534 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5535 // Verify that the prototype makes sense. int strcmp(void*,void*)
5536 if (I.getNumArgOperands() != 2)
5539 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5540 if (!Arg0->getType()->isPointerTy() ||
5541 !Arg1->getType()->isPointerTy() ||
5542 !I.getType()->isIntegerTy())
5545 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5546 std::pair<SDValue, SDValue> Res =
5547 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5548 getValue(Arg0), getValue(Arg1),
5549 MachinePointerInfo(Arg0),
5550 MachinePointerInfo(Arg1));
5551 if (Res.first.getNode()) {
5552 processIntegerCallValue(I, Res.first, true);
5553 PendingLoads.push_back(Res.second);
5560 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5561 /// form. If so, return true and lower it, otherwise return false and it
5562 /// will be lowered like a normal call.
5563 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5564 // Verify that the prototype makes sense. size_t strlen(char *)
5565 if (I.getNumArgOperands() != 1)
5568 const Value *Arg0 = I.getArgOperand(0);
5569 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5572 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5573 std::pair<SDValue, SDValue> Res =
5574 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5575 getValue(Arg0), MachinePointerInfo(Arg0));
5576 if (Res.first.getNode()) {
5577 processIntegerCallValue(I, Res.first, false);
5578 PendingLoads.push_back(Res.second);
5585 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5586 /// form. If so, return true and lower it, otherwise return false and it
5587 /// will be lowered like a normal call.
5588 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5589 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5590 if (I.getNumArgOperands() != 2)
5593 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5594 if (!Arg0->getType()->isPointerTy() ||
5595 !Arg1->getType()->isIntegerTy() ||
5596 !I.getType()->isIntegerTy())
5599 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5600 std::pair<SDValue, SDValue> Res =
5601 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5602 getValue(Arg0), getValue(Arg1),
5603 MachinePointerInfo(Arg0));
5604 if (Res.first.getNode()) {
5605 processIntegerCallValue(I, Res.first, false);
5606 PendingLoads.push_back(Res.second);
5613 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5614 /// operation (as expected), translate it to an SDNode with the specified opcode
5615 /// and return true.
5616 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5618 // Sanity check that it really is a unary floating-point call.
5619 if (I.getNumArgOperands() != 1 ||
5620 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5621 I.getType() != I.getArgOperand(0)->getType() ||
5622 !I.onlyReadsMemory())
5625 SDValue Tmp = getValue(I.getArgOperand(0));
5626 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5630 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5631 /// operation (as expected), translate it to an SDNode with the specified opcode
5632 /// and return true.
5633 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5635 // Sanity check that it really is a binary floating-point call.
5636 if (I.getNumArgOperands() != 2 ||
5637 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5638 I.getType() != I.getArgOperand(0)->getType() ||
5639 I.getType() != I.getArgOperand(1)->getType() ||
5640 !I.onlyReadsMemory())
5643 SDValue Tmp0 = getValue(I.getArgOperand(0));
5644 SDValue Tmp1 = getValue(I.getArgOperand(1));
5645 EVT VT = Tmp0.getValueType();
5646 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5650 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5651 // Handle inline assembly differently.
5652 if (isa<InlineAsm>(I.getCalledValue())) {
5657 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5658 ComputeUsesVAFloatArgument(I, &MMI);
5660 const char *RenameFn = nullptr;
5661 if (Function *F = I.getCalledFunction()) {
5662 if (F->isDeclaration()) {
5663 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5664 if (unsigned IID = II->getIntrinsicID(F)) {
5665 RenameFn = visitIntrinsicCall(I, IID);
5670 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5671 RenameFn = visitIntrinsicCall(I, IID);
5677 // Check for well-known libc/libm calls. If the function is internal, it
5678 // can't be a library call.
5680 if (!F->hasLocalLinkage() && F->hasName() &&
5681 LibInfo->getLibFunc(F->getName(), Func) &&
5682 LibInfo->hasOptimizedCodeGen(Func)) {
5685 case LibFunc::copysign:
5686 case LibFunc::copysignf:
5687 case LibFunc::copysignl:
5688 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5689 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5690 I.getType() == I.getArgOperand(0)->getType() &&
5691 I.getType() == I.getArgOperand(1)->getType() &&
5692 I.onlyReadsMemory()) {
5693 SDValue LHS = getValue(I.getArgOperand(0));
5694 SDValue RHS = getValue(I.getArgOperand(1));
5695 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5696 LHS.getValueType(), LHS, RHS));
5701 case LibFunc::fabsf:
5702 case LibFunc::fabsl:
5703 if (visitUnaryFloatCall(I, ISD::FABS))
5707 case LibFunc::fminf:
5708 case LibFunc::fminl:
5709 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5713 case LibFunc::fmaxf:
5714 case LibFunc::fmaxl:
5715 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5721 if (visitUnaryFloatCall(I, ISD::FSIN))
5727 if (visitUnaryFloatCall(I, ISD::FCOS))
5731 case LibFunc::sqrtf:
5732 case LibFunc::sqrtl:
5733 case LibFunc::sqrt_finite:
5734 case LibFunc::sqrtf_finite:
5735 case LibFunc::sqrtl_finite:
5736 if (visitUnaryFloatCall(I, ISD::FSQRT))
5739 case LibFunc::floor:
5740 case LibFunc::floorf:
5741 case LibFunc::floorl:
5742 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5745 case LibFunc::nearbyint:
5746 case LibFunc::nearbyintf:
5747 case LibFunc::nearbyintl:
5748 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5752 case LibFunc::ceilf:
5753 case LibFunc::ceill:
5754 if (visitUnaryFloatCall(I, ISD::FCEIL))
5758 case LibFunc::rintf:
5759 case LibFunc::rintl:
5760 if (visitUnaryFloatCall(I, ISD::FRINT))
5763 case LibFunc::round:
5764 case LibFunc::roundf:
5765 case LibFunc::roundl:
5766 if (visitUnaryFloatCall(I, ISD::FROUND))
5769 case LibFunc::trunc:
5770 case LibFunc::truncf:
5771 case LibFunc::truncl:
5772 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5776 case LibFunc::log2f:
5777 case LibFunc::log2l:
5778 if (visitUnaryFloatCall(I, ISD::FLOG2))
5782 case LibFunc::exp2f:
5783 case LibFunc::exp2l:
5784 if (visitUnaryFloatCall(I, ISD::FEXP2))
5787 case LibFunc::memcmp:
5788 if (visitMemCmpCall(I))
5791 case LibFunc::memchr:
5792 if (visitMemChrCall(I))
5795 case LibFunc::strcpy:
5796 if (visitStrCpyCall(I, false))
5799 case LibFunc::stpcpy:
5800 if (visitStrCpyCall(I, true))
5803 case LibFunc::strcmp:
5804 if (visitStrCmpCall(I))
5807 case LibFunc::strlen:
5808 if (visitStrLenCall(I))
5811 case LibFunc::strnlen:
5812 if (visitStrNLenCall(I))
5821 Callee = getValue(I.getCalledValue());
5823 Callee = DAG.getExternalSymbol(
5825 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5827 // Check if we can potentially perform a tail call. More detailed checking is
5828 // be done within LowerCallTo, after more information about the call is known.
5829 LowerCallTo(&I, Callee, I.isTailCall());
5834 /// AsmOperandInfo - This contains information for each constraint that we are
5836 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5838 /// CallOperand - If this is the result output operand or a clobber
5839 /// this is null, otherwise it is the incoming operand to the CallInst.
5840 /// This gets modified as the asm is processed.
5841 SDValue CallOperand;
5843 /// AssignedRegs - If this is a register or register class operand, this
5844 /// contains the set of register corresponding to the operand.
5845 RegsForValue AssignedRegs;
5847 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5848 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5851 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5852 /// corresponds to. If there is no Value* for this operand, it returns
5854 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5855 const DataLayout &DL) const {
5856 if (!CallOperandVal) return MVT::Other;
5858 if (isa<BasicBlock>(CallOperandVal))
5859 return TLI.getPointerTy(DL);
5861 llvm::Type *OpTy = CallOperandVal->getType();
5863 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5864 // If this is an indirect operand, the operand is a pointer to the
5867 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5869 report_fatal_error("Indirect operand for inline asm not a pointer!");
5870 OpTy = PtrTy->getElementType();
5873 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5874 if (StructType *STy = dyn_cast<StructType>(OpTy))
5875 if (STy->getNumElements() == 1)
5876 OpTy = STy->getElementType(0);
5878 // If OpTy is not a single value, it may be a struct/union that we
5879 // can tile with integers.
5880 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5881 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5890 OpTy = IntegerType::get(Context, BitSize);
5895 return TLI.getValueType(DL, OpTy, true);
5899 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5901 } // end anonymous namespace
5903 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5904 /// specified operand. We prefer to assign virtual registers, to allow the
5905 /// register allocator to handle the assignment process. However, if the asm
5906 /// uses features that we can't model on machineinstrs, we have SDISel do the
5907 /// allocation. This produces generally horrible, but correct, code.
5909 /// OpInfo describes the operand.
5911 static void GetRegistersForValue(SelectionDAG &DAG,
5912 const TargetLowering &TLI,
5914 SDISelAsmOperandInfo &OpInfo) {
5915 LLVMContext &Context = *DAG.getContext();
5917 MachineFunction &MF = DAG.getMachineFunction();
5918 SmallVector<unsigned, 4> Regs;
5920 // If this is a constraint for a single physreg, or a constraint for a
5921 // register class, find it.
5922 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5923 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5924 OpInfo.ConstraintCode,
5925 OpInfo.ConstraintVT);
5927 unsigned NumRegs = 1;
5928 if (OpInfo.ConstraintVT != MVT::Other) {
5929 // If this is a FP input in an integer register (or visa versa) insert a bit
5930 // cast of the input value. More generally, handle any case where the input
5931 // value disagrees with the register class we plan to stick this in.
5932 if (OpInfo.Type == InlineAsm::isInput &&
5933 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5934 // Try to convert to the first EVT that the reg class contains. If the
5935 // types are identical size, use a bitcast to convert (e.g. two differing
5937 MVT RegVT = *PhysReg.second->vt_begin();
5938 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5939 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5940 RegVT, OpInfo.CallOperand);
5941 OpInfo.ConstraintVT = RegVT;
5942 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5943 // If the input is a FP value and we want it in FP registers, do a
5944 // bitcast to the corresponding integer type. This turns an f64 value
5945 // into i64, which can be passed with two i32 values on a 32-bit
5947 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5948 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5949 RegVT, OpInfo.CallOperand);
5950 OpInfo.ConstraintVT = RegVT;
5954 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5958 EVT ValueVT = OpInfo.ConstraintVT;
5960 // If this is a constraint for a specific physical register, like {r17},
5962 if (unsigned AssignedReg = PhysReg.first) {
5963 const TargetRegisterClass *RC = PhysReg.second;
5964 if (OpInfo.ConstraintVT == MVT::Other)
5965 ValueVT = *RC->vt_begin();
5967 // Get the actual register value type. This is important, because the user
5968 // may have asked for (e.g.) the AX register in i32 type. We need to
5969 // remember that AX is actually i16 to get the right extension.
5970 RegVT = *RC->vt_begin();
5972 // This is a explicit reference to a physical register.
5973 Regs.push_back(AssignedReg);
5975 // If this is an expanded reference, add the rest of the regs to Regs.
5977 TargetRegisterClass::iterator I = RC->begin();
5978 for (; *I != AssignedReg; ++I)
5979 assert(I != RC->end() && "Didn't find reg!");
5981 // Already added the first reg.
5983 for (; NumRegs; --NumRegs, ++I) {
5984 assert(I != RC->end() && "Ran out of registers to allocate!");
5989 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5993 // Otherwise, if this was a reference to an LLVM register class, create vregs
5994 // for this reference.
5995 if (const TargetRegisterClass *RC = PhysReg.second) {
5996 RegVT = *RC->vt_begin();
5997 if (OpInfo.ConstraintVT == MVT::Other)
6000 // Create the appropriate number of virtual registers.
6001 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6002 for (; NumRegs; --NumRegs)
6003 Regs.push_back(RegInfo.createVirtualRegister(RC));
6005 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6009 // Otherwise, we couldn't allocate enough registers for this.
6012 /// visitInlineAsm - Handle a call to an InlineAsm object.
6014 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6015 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6017 /// ConstraintOperands - Information about all of the constraints.
6018 SDISelAsmOperandInfoVector ConstraintOperands;
6020 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6021 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6022 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6024 bool hasMemory = false;
6026 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6027 unsigned ResNo = 0; // ResNo - The result number of the next output.
6028 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6029 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6030 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6032 MVT OpVT = MVT::Other;
6034 // Compute the value type for each operand.
6035 switch (OpInfo.Type) {
6036 case InlineAsm::isOutput:
6037 // Indirect outputs just consume an argument.
6038 if (OpInfo.isIndirect) {
6039 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6043 // The return value of the call is this value. As such, there is no
6044 // corresponding argument.
6045 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6046 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6047 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6048 STy->getElementType(ResNo));
6050 assert(ResNo == 0 && "Asm only has one result!");
6051 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6055 case InlineAsm::isInput:
6056 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6058 case InlineAsm::isClobber:
6063 // If this is an input or an indirect output, process the call argument.
6064 // BasicBlocks are labels, currently appearing only in asm's.
6065 if (OpInfo.CallOperandVal) {
6066 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6067 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6069 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6072 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6073 DAG.getDataLayout()).getSimpleVT();
6076 OpInfo.ConstraintVT = OpVT;
6078 // Indirect operand accesses access memory.
6079 if (OpInfo.isIndirect)
6082 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6083 TargetLowering::ConstraintType
6084 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6085 if (CType == TargetLowering::C_Memory) {
6093 SDValue Chain, Flag;
6095 // We won't need to flush pending loads if this asm doesn't touch
6096 // memory and is nonvolatile.
6097 if (hasMemory || IA->hasSideEffects())
6100 Chain = DAG.getRoot();
6102 // Second pass over the constraints: compute which constraint option to use
6103 // and assign registers to constraints that want a specific physreg.
6104 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6105 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6107 // If this is an output operand with a matching input operand, look up the
6108 // matching input. If their types mismatch, e.g. one is an integer, the
6109 // other is floating point, or their sizes are different, flag it as an
6111 if (OpInfo.hasMatchingInput()) {
6112 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6114 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6115 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6116 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6117 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6118 OpInfo.ConstraintVT);
6119 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6120 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6121 Input.ConstraintVT);
6122 if ((OpInfo.ConstraintVT.isInteger() !=
6123 Input.ConstraintVT.isInteger()) ||
6124 (MatchRC.second != InputRC.second)) {
6125 report_fatal_error("Unsupported asm: input constraint"
6126 " with a matching output constraint of"
6127 " incompatible type!");
6129 Input.ConstraintVT = OpInfo.ConstraintVT;
6133 // Compute the constraint code and ConstraintType to use.
6134 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6136 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6137 OpInfo.Type == InlineAsm::isClobber)
6140 // If this is a memory input, and if the operand is not indirect, do what we
6141 // need to to provide an address for the memory input.
6142 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6143 !OpInfo.isIndirect) {
6144 assert((OpInfo.isMultipleAlternative ||
6145 (OpInfo.Type == InlineAsm::isInput)) &&
6146 "Can only indirectify direct input operands!");
6148 // Memory operands really want the address of the value. If we don't have
6149 // an indirect input, put it in the constpool if we can, otherwise spill
6150 // it to a stack slot.
6151 // TODO: This isn't quite right. We need to handle these according to
6152 // the addressing mode that the constraint wants. Also, this may take
6153 // an additional register for the computation and we don't want that
6156 // If the operand is a float, integer, or vector constant, spill to a
6157 // constant pool entry to get its address.
6158 const Value *OpVal = OpInfo.CallOperandVal;
6159 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6160 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6161 OpInfo.CallOperand = DAG.getConstantPool(
6162 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6164 // Otherwise, create a stack slot and emit a store to it before the
6166 Type *Ty = OpVal->getType();
6167 auto &DL = DAG.getDataLayout();
6168 uint64_t TySize = DL.getTypeAllocSize(Ty);
6169 unsigned Align = DL.getPrefTypeAlignment(Ty);
6170 MachineFunction &MF = DAG.getMachineFunction();
6171 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6173 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6174 Chain = DAG.getStore(
6175 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6176 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6178 OpInfo.CallOperand = StackSlot;
6181 // There is no longer a Value* corresponding to this operand.
6182 OpInfo.CallOperandVal = nullptr;
6184 // It is now an indirect operand.
6185 OpInfo.isIndirect = true;
6188 // If this constraint is for a specific register, allocate it before
6190 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6191 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6194 // Second pass - Loop over all of the operands, assigning virtual or physregs
6195 // to register class operands.
6196 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6197 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6199 // C_Register operands have already been allocated, Other/Memory don't need
6201 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6202 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6205 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6206 std::vector<SDValue> AsmNodeOperands;
6207 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6208 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6209 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6211 // If we have a !srcloc metadata node associated with it, we want to attach
6212 // this to the ultimately generated inline asm machineinstr. To do this, we
6213 // pass in the third operand as this (potentially null) inline asm MDNode.
6214 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6215 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6217 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6218 // bits as operand 3.
6219 unsigned ExtraInfo = 0;
6220 if (IA->hasSideEffects())
6221 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6222 if (IA->isAlignStack())
6223 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6224 // Set the asm dialect.
6225 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6227 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6228 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6229 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6231 // Compute the constraint code and ConstraintType to use.
6232 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6234 // Ideally, we would only check against memory constraints. However, the
6235 // meaning of an other constraint can be target-specific and we can't easily
6236 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6237 // for other constriants as well.
6238 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6239 OpInfo.ConstraintType == TargetLowering::C_Other) {
6240 if (OpInfo.Type == InlineAsm::isInput)
6241 ExtraInfo |= InlineAsm::Extra_MayLoad;
6242 else if (OpInfo.Type == InlineAsm::isOutput)
6243 ExtraInfo |= InlineAsm::Extra_MayStore;
6244 else if (OpInfo.Type == InlineAsm::isClobber)
6245 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6249 AsmNodeOperands.push_back(DAG.getTargetConstant(
6250 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6252 // Loop over all of the inputs, copying the operand values into the
6253 // appropriate registers and processing the output regs.
6254 RegsForValue RetValRegs;
6256 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6257 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6259 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6260 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6262 switch (OpInfo.Type) {
6263 case InlineAsm::isOutput: {
6264 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6265 OpInfo.ConstraintType != TargetLowering::C_Register) {
6266 // Memory output, or 'other' output (e.g. 'X' constraint).
6267 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6269 unsigned ConstraintID =
6270 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6271 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6272 "Failed to convert memory constraint code to constraint id.");
6274 // Add information to the INLINEASM node to know about this output.
6275 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6276 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6277 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6279 AsmNodeOperands.push_back(OpInfo.CallOperand);
6283 // Otherwise, this is a register or register class output.
6285 // Copy the output from the appropriate register. Find a register that
6287 if (OpInfo.AssignedRegs.Regs.empty()) {
6288 LLVMContext &Ctx = *DAG.getContext();
6289 Ctx.emitError(CS.getInstruction(),
6290 "couldn't allocate output register for constraint '" +
6291 Twine(OpInfo.ConstraintCode) + "'");
6295 // If this is an indirect operand, store through the pointer after the
6297 if (OpInfo.isIndirect) {
6298 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6299 OpInfo.CallOperandVal));
6301 // This is the result value of the call.
6302 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6303 // Concatenate this output onto the outputs list.
6304 RetValRegs.append(OpInfo.AssignedRegs);
6307 // Add information to the INLINEASM node to know that this register is
6310 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6311 ? InlineAsm::Kind_RegDefEarlyClobber
6312 : InlineAsm::Kind_RegDef,
6313 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6316 case InlineAsm::isInput: {
6317 SDValue InOperandVal = OpInfo.CallOperand;
6319 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6320 // If this is required to match an output register we have already set,
6321 // just use its register.
6322 unsigned OperandNo = OpInfo.getMatchedOperand();
6324 // Scan until we find the definition we already emitted of this operand.
6325 // When we find it, create a RegsForValue operand.
6326 unsigned CurOp = InlineAsm::Op_FirstOperand;
6327 for (; OperandNo; --OperandNo) {
6328 // Advance to the next operand.
6330 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6331 assert((InlineAsm::isRegDefKind(OpFlag) ||
6332 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6333 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6334 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6338 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6339 if (InlineAsm::isRegDefKind(OpFlag) ||
6340 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6341 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6342 if (OpInfo.isIndirect) {
6343 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6344 LLVMContext &Ctx = *DAG.getContext();
6345 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6346 " don't know how to handle tied "
6347 "indirect register inputs");
6351 RegsForValue MatchedRegs;
6352 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6353 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6354 MatchedRegs.RegVTs.push_back(RegVT);
6355 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6356 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6358 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6359 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6361 LLVMContext &Ctx = *DAG.getContext();
6362 Ctx.emitError(CS.getInstruction(),
6363 "inline asm error: This value"
6364 " type register class is not natively supported!");
6368 SDLoc dl = getCurSDLoc();
6369 // Use the produced MatchedRegs object to
6370 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6371 Chain, &Flag, CS.getInstruction());
6372 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6373 true, OpInfo.getMatchedOperand(), dl,
6374 DAG, AsmNodeOperands);
6378 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6379 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6380 "Unexpected number of operands");
6381 // Add information to the INLINEASM node to know about this input.
6382 // See InlineAsm.h isUseOperandTiedToDef.
6383 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6384 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6385 OpInfo.getMatchedOperand());
6386 AsmNodeOperands.push_back(DAG.getTargetConstant(
6387 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6388 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6392 // Treat indirect 'X' constraint as memory.
6393 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6395 OpInfo.ConstraintType = TargetLowering::C_Memory;
6397 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6398 std::vector<SDValue> Ops;
6399 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6402 LLVMContext &Ctx = *DAG.getContext();
6403 Ctx.emitError(CS.getInstruction(),
6404 "invalid operand for inline asm constraint '" +
6405 Twine(OpInfo.ConstraintCode) + "'");
6409 // Add information to the INLINEASM node to know about this input.
6410 unsigned ResOpType =
6411 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6412 AsmNodeOperands.push_back(DAG.getTargetConstant(
6413 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6414 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6418 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6419 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6420 assert(InOperandVal.getValueType() ==
6421 TLI.getPointerTy(DAG.getDataLayout()) &&
6422 "Memory operands expect pointer values");
6424 unsigned ConstraintID =
6425 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6426 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6427 "Failed to convert memory constraint code to constraint id.");
6429 // Add information to the INLINEASM node to know about this input.
6430 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6431 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6432 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6435 AsmNodeOperands.push_back(InOperandVal);
6439 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6440 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6441 "Unknown constraint type!");
6443 // TODO: Support this.
6444 if (OpInfo.isIndirect) {
6445 LLVMContext &Ctx = *DAG.getContext();
6446 Ctx.emitError(CS.getInstruction(),
6447 "Don't know how to handle indirect register inputs yet "
6448 "for constraint '" +
6449 Twine(OpInfo.ConstraintCode) + "'");
6453 // Copy the input into the appropriate registers.
6454 if (OpInfo.AssignedRegs.Regs.empty()) {
6455 LLVMContext &Ctx = *DAG.getContext();
6456 Ctx.emitError(CS.getInstruction(),
6457 "couldn't allocate input reg for constraint '" +
6458 Twine(OpInfo.ConstraintCode) + "'");
6462 SDLoc dl = getCurSDLoc();
6464 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6465 Chain, &Flag, CS.getInstruction());
6467 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6468 dl, DAG, AsmNodeOperands);
6471 case InlineAsm::isClobber: {
6472 // Add the clobbered value to the operand list, so that the register
6473 // allocator is aware that the physreg got clobbered.
6474 if (!OpInfo.AssignedRegs.Regs.empty())
6475 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6476 false, 0, getCurSDLoc(), DAG,
6483 // Finish up input operands. Set the input chain and add the flag last.
6484 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6485 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6487 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6488 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6489 Flag = Chain.getValue(1);
6491 // If this asm returns a register value, copy the result from that register
6492 // and set it as the value of the call.
6493 if (!RetValRegs.Regs.empty()) {
6494 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6495 Chain, &Flag, CS.getInstruction());
6497 // FIXME: Why don't we do this for inline asms with MRVs?
6498 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6499 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6501 // If any of the results of the inline asm is a vector, it may have the
6502 // wrong width/num elts. This can happen for register classes that can
6503 // contain multiple different value types. The preg or vreg allocated may
6504 // not have the same VT as was expected. Convert it to the right type
6505 // with bit_convert.
6506 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6507 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6510 } else if (ResultType != Val.getValueType() &&
6511 ResultType.isInteger() && Val.getValueType().isInteger()) {
6512 // If a result value was tied to an input value, the computed result may
6513 // have a wider width than the expected result. Extract the relevant
6515 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6518 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6521 setValue(CS.getInstruction(), Val);
6522 // Don't need to use this as a chain in this case.
6523 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6527 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6529 // Process indirect outputs, first output all of the flagged copies out of
6531 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6532 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6533 const Value *Ptr = IndirectStoresToEmit[i].second;
6534 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6536 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6539 // Emit the non-flagged stores from the physregs.
6540 SmallVector<SDValue, 8> OutChains;
6541 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6542 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6543 StoresToEmit[i].first,
6544 getValue(StoresToEmit[i].second),
6545 MachinePointerInfo(StoresToEmit[i].second),
6547 OutChains.push_back(Val);
6550 if (!OutChains.empty())
6551 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6556 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6557 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6558 MVT::Other, getRoot(),
6559 getValue(I.getArgOperand(0)),
6560 DAG.getSrcValue(I.getArgOperand(0))));
6563 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6565 const DataLayout &DL = DAG.getDataLayout();
6566 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6567 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6568 DAG.getSrcValue(I.getOperand(0)),
6569 DL.getABITypeAlignment(I.getType()));
6571 DAG.setRoot(V.getValue(1));
6574 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6575 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6576 MVT::Other, getRoot(),
6577 getValue(I.getArgOperand(0)),
6578 DAG.getSrcValue(I.getArgOperand(0))));
6581 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6582 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6583 MVT::Other, getRoot(),
6584 getValue(I.getArgOperand(0)),
6585 getValue(I.getArgOperand(1)),
6586 DAG.getSrcValue(I.getArgOperand(0)),
6587 DAG.getSrcValue(I.getArgOperand(1))));
6590 /// \brief Lower an argument list according to the target calling convention.
6592 /// \return A tuple of <return-value, token-chain>
6594 /// This is a helper for lowering intrinsics that follow a target calling
6595 /// convention or require stack pointer adjustment. Only a subset of the
6596 /// intrinsic's operands need to participate in the calling convention.
6597 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6598 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6599 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6600 TargetLowering::ArgListTy Args;
6601 Args.reserve(NumArgs);
6603 // Populate the argument list.
6604 // Attributes for args start at offset 1, after the return attribute.
6605 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6606 ArgI != ArgE; ++ArgI) {
6607 const Value *V = CS->getOperand(ArgI);
6609 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6611 TargetLowering::ArgListEntry Entry;
6612 Entry.Node = getValue(V);
6613 Entry.Ty = V->getType();
6614 Entry.setAttributes(&CS, AttrI);
6615 Args.push_back(Entry);
6618 TargetLowering::CallLoweringInfo CLI(DAG);
6619 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6620 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6621 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6623 return lowerInvokable(CLI, EHPadBB);
6626 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6627 /// or patchpoint target node's operand list.
6629 /// Constants are converted to TargetConstants purely as an optimization to
6630 /// avoid constant materialization and register allocation.
6632 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6633 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6634 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6635 /// address materialization and register allocation, but may also be required
6636 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6637 /// alloca in the entry block, then the runtime may assume that the alloca's
6638 /// StackMap location can be read immediately after compilation and that the
6639 /// location is valid at any point during execution (this is similar to the
6640 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6641 /// only available in a register, then the runtime would need to trap when
6642 /// execution reaches the StackMap in order to read the alloca's location.
6643 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6644 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6645 SelectionDAGBuilder &Builder) {
6646 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6647 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6648 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6650 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6652 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6653 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6654 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6655 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6656 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6658 Ops.push_back(OpVal);
6662 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6663 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6664 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6665 // [live variables...])
6667 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6669 SDValue Chain, InFlag, Callee, NullPtr;
6670 SmallVector<SDValue, 32> Ops;
6672 SDLoc DL = getCurSDLoc();
6673 Callee = getValue(CI.getCalledValue());
6674 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6676 // The stackmap intrinsic only records the live variables (the arguemnts
6677 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6678 // intrinsic, this won't be lowered to a function call. This means we don't
6679 // have to worry about calling conventions and target specific lowering code.
6680 // Instead we perform the call lowering right here.
6682 // chain, flag = CALLSEQ_START(chain, 0)
6683 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6684 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6686 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6687 InFlag = Chain.getValue(1);
6689 // Add the <id> and <numBytes> constants.
6690 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6691 Ops.push_back(DAG.getTargetConstant(
6692 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6693 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6694 Ops.push_back(DAG.getTargetConstant(
6695 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6698 // Push live variables for the stack map.
6699 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6701 // We are not pushing any register mask info here on the operands list,
6702 // because the stackmap doesn't clobber anything.
6704 // Push the chain and the glue flag.
6705 Ops.push_back(Chain);
6706 Ops.push_back(InFlag);
6708 // Create the STACKMAP node.
6709 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6710 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6711 Chain = SDValue(SM, 0);
6712 InFlag = Chain.getValue(1);
6714 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6716 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6718 // Set the root to the target-lowered call chain.
6721 // Inform the Frame Information that we have a stackmap in this function.
6722 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6725 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6726 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6727 const BasicBlock *EHPadBB) {
6728 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6733 // [live variables...])
6735 CallingConv::ID CC = CS.getCallingConv();
6736 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6737 bool HasDef = !CS->getType()->isVoidTy();
6738 SDLoc dl = getCurSDLoc();
6739 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6741 // Handle immediate and symbolic callees.
6742 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6743 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6745 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6746 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6747 SDLoc(SymbolicCallee),
6748 SymbolicCallee->getValueType(0));
6750 // Get the real number of arguments participating in the call <numArgs>
6751 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6752 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6754 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6755 // Intrinsics include all meta-operands up to but not including CC.
6756 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6757 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6758 "Not enough arguments provided to the patchpoint intrinsic");
6760 // For AnyRegCC the arguments are lowered later on manually.
6761 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6763 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6764 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6765 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6767 SDNode *CallEnd = Result.second.getNode();
6768 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6769 CallEnd = CallEnd->getOperand(0).getNode();
6771 /// Get a call instruction from the call sequence chain.
6772 /// Tail calls are not allowed.
6773 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6774 "Expected a callseq node.");
6775 SDNode *Call = CallEnd->getOperand(0).getNode();
6776 bool HasGlue = Call->getGluedNode();
6778 // Replace the target specific call node with the patchable intrinsic.
6779 SmallVector<SDValue, 8> Ops;
6781 // Add the <id> and <numBytes> constants.
6782 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6783 Ops.push_back(DAG.getTargetConstant(
6784 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6785 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6786 Ops.push_back(DAG.getTargetConstant(
6787 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6791 Ops.push_back(Callee);
6793 // Adjust <numArgs> to account for any arguments that have been passed on the
6795 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6796 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6797 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6798 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6800 // Add the calling convention
6801 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6803 // Add the arguments we omitted previously. The register allocator should
6804 // place these in any free register.
6806 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6807 Ops.push_back(getValue(CS.getArgument(i)));
6809 // Push the arguments from the call instruction up to the register mask.
6810 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6811 Ops.append(Call->op_begin() + 2, e);
6813 // Push live variables for the stack map.
6814 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6816 // Push the register mask info.
6818 Ops.push_back(*(Call->op_end()-2));
6820 Ops.push_back(*(Call->op_end()-1));
6822 // Push the chain (this is originally the first operand of the call, but
6823 // becomes now the last or second to last operand).
6824 Ops.push_back(*(Call->op_begin()));
6826 // Push the glue flag (last operand).
6828 Ops.push_back(*(Call->op_end()-1));
6831 if (IsAnyRegCC && HasDef) {
6832 // Create the return types based on the intrinsic definition
6833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6834 SmallVector<EVT, 3> ValueVTs;
6835 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6836 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6838 // There is always a chain and a glue type at the end
6839 ValueVTs.push_back(MVT::Other);
6840 ValueVTs.push_back(MVT::Glue);
6841 NodeTys = DAG.getVTList(ValueVTs);
6843 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6845 // Replace the target specific call node with a PATCHPOINT node.
6846 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6849 // Update the NodeMap.
6852 setValue(CS.getInstruction(), SDValue(MN, 0));
6854 setValue(CS.getInstruction(), Result.first);
6857 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6858 // call sequence. Furthermore the location of the chain and glue can change
6859 // when the AnyReg calling convention is used and the intrinsic returns a
6861 if (IsAnyRegCC && HasDef) {
6862 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6863 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6864 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6866 DAG.ReplaceAllUsesWith(Call, MN);
6867 DAG.DeleteNode(Call);
6869 // Inform the Frame Information that we have a patchpoint in this function.
6870 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6873 /// Returns an AttributeSet representing the attributes applied to the return
6874 /// value of the given call.
6875 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6876 SmallVector<Attribute::AttrKind, 2> Attrs;
6878 Attrs.push_back(Attribute::SExt);
6880 Attrs.push_back(Attribute::ZExt);
6882 Attrs.push_back(Attribute::InReg);
6884 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6888 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6889 /// implementation, which just calls LowerCall.
6890 /// FIXME: When all targets are
6891 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6892 std::pair<SDValue, SDValue>
6893 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6894 // Handle the incoming return values from the call.
6896 Type *OrigRetTy = CLI.RetTy;
6897 SmallVector<EVT, 4> RetTys;
6898 SmallVector<uint64_t, 4> Offsets;
6899 auto &DL = CLI.DAG.getDataLayout();
6900 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6902 SmallVector<ISD::OutputArg, 4> Outs;
6903 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6905 bool CanLowerReturn =
6906 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6907 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6909 SDValue DemoteStackSlot;
6910 int DemoteStackIdx = -100;
6911 if (!CanLowerReturn) {
6912 // FIXME: equivalent assert?
6913 // assert(!CS.hasInAllocaArgument() &&
6914 // "sret demotion is incompatible with inalloca");
6915 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6916 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6917 MachineFunction &MF = CLI.DAG.getMachineFunction();
6918 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6919 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6921 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6923 Entry.Node = DemoteStackSlot;
6924 Entry.Ty = StackSlotPtrType;
6925 Entry.isSExt = false;
6926 Entry.isZExt = false;
6927 Entry.isInReg = false;
6928 Entry.isSRet = true;
6929 Entry.isNest = false;
6930 Entry.isByVal = false;
6931 Entry.isReturned = false;
6932 Entry.Alignment = Align;
6933 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6934 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6936 // sret demotion isn't compatible with tail-calls, since the sret argument
6937 // points into the callers stack frame.
6938 CLI.IsTailCall = false;
6940 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6942 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6943 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6944 for (unsigned i = 0; i != NumRegs; ++i) {
6945 ISD::InputArg MyFlags;
6946 MyFlags.VT = RegisterVT;
6948 MyFlags.Used = CLI.IsReturnValueUsed;
6950 MyFlags.Flags.setSExt();
6952 MyFlags.Flags.setZExt();
6954 MyFlags.Flags.setInReg();
6955 CLI.Ins.push_back(MyFlags);
6960 // Handle all of the outgoing arguments.
6962 CLI.OutVals.clear();
6963 ArgListTy &Args = CLI.getArgs();
6964 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6965 SmallVector<EVT, 4> ValueVTs;
6966 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6967 Type *FinalType = Args[i].Ty;
6968 if (Args[i].isByVal)
6969 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6970 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6971 FinalType, CLI.CallConv, CLI.IsVarArg);
6972 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6974 EVT VT = ValueVTs[Value];
6975 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6976 SDValue Op = SDValue(Args[i].Node.getNode(),
6977 Args[i].Node.getResNo() + Value);
6978 ISD::ArgFlagsTy Flags;
6979 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6985 if (Args[i].isInReg)
6989 if (Args[i].isByVal)
6991 if (Args[i].isInAlloca) {
6992 Flags.setInAlloca();
6993 // Set the byval flag for CCAssignFn callbacks that don't know about
6994 // inalloca. This way we can know how many bytes we should've allocated
6995 // and how many bytes a callee cleanup function will pop. If we port
6996 // inalloca to more targets, we'll have to add custom inalloca handling
6997 // in the various CC lowering callbacks.
7000 if (Args[i].isByVal || Args[i].isInAlloca) {
7001 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7002 Type *ElementTy = Ty->getElementType();
7003 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7004 // For ByVal, alignment should come from FE. BE will guess if this
7005 // info is not there but there are cases it cannot get right.
7006 unsigned FrameAlign;
7007 if (Args[i].Alignment)
7008 FrameAlign = Args[i].Alignment;
7010 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7011 Flags.setByValAlign(FrameAlign);
7016 Flags.setInConsecutiveRegs();
7017 Flags.setOrigAlign(OriginalAlignment);
7019 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7020 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7021 SmallVector<SDValue, 4> Parts(NumParts);
7022 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7025 ExtendKind = ISD::SIGN_EXTEND;
7026 else if (Args[i].isZExt)
7027 ExtendKind = ISD::ZERO_EXTEND;
7029 // Conservatively only handle 'returned' on non-vectors for now
7030 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7031 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7032 "unexpected use of 'returned'");
7033 // Before passing 'returned' to the target lowering code, ensure that
7034 // either the register MVT and the actual EVT are the same size or that
7035 // the return value and argument are extended in the same way; in these
7036 // cases it's safe to pass the argument register value unchanged as the
7037 // return register value (although it's at the target's option whether
7039 // TODO: allow code generation to take advantage of partially preserved
7040 // registers rather than clobbering the entire register when the
7041 // parameter extension method is not compatible with the return
7043 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7044 (ExtendKind != ISD::ANY_EXTEND &&
7045 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7046 Flags.setReturned();
7049 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7050 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7052 for (unsigned j = 0; j != NumParts; ++j) {
7053 // if it isn't first piece, alignment must be 1
7054 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7055 i < CLI.NumFixedArgs,
7056 i, j*Parts[j].getValueType().getStoreSize());
7057 if (NumParts > 1 && j == 0)
7058 MyFlags.Flags.setSplit();
7060 MyFlags.Flags.setOrigAlign(1);
7062 CLI.Outs.push_back(MyFlags);
7063 CLI.OutVals.push_back(Parts[j]);
7066 if (NeedsRegBlock && Value == NumValues - 1)
7067 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7071 SmallVector<SDValue, 4> InVals;
7072 CLI.Chain = LowerCall(CLI, InVals);
7074 // Verify that the target's LowerCall behaved as expected.
7075 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7076 "LowerCall didn't return a valid chain!");
7077 assert((!CLI.IsTailCall || InVals.empty()) &&
7078 "LowerCall emitted a return value for a tail call!");
7079 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7080 "LowerCall didn't emit the correct number of values!");
7082 // For a tail call, the return value is merely live-out and there aren't
7083 // any nodes in the DAG representing it. Return a special value to
7084 // indicate that a tail call has been emitted and no more Instructions
7085 // should be processed in the current block.
7086 if (CLI.IsTailCall) {
7087 CLI.DAG.setRoot(CLI.Chain);
7088 return std::make_pair(SDValue(), SDValue());
7091 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7092 assert(InVals[i].getNode() &&
7093 "LowerCall emitted a null value!");
7094 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7095 "LowerCall emitted a value with the wrong type!");
7098 SmallVector<SDValue, 4> ReturnValues;
7099 if (!CanLowerReturn) {
7100 // The instruction result is the result of loading from the
7101 // hidden sret parameter.
7102 SmallVector<EVT, 1> PVTs;
7103 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7105 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7106 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7107 EVT PtrVT = PVTs[0];
7109 unsigned NumValues = RetTys.size();
7110 ReturnValues.resize(NumValues);
7111 SmallVector<SDValue, 4> Chains(NumValues);
7113 for (unsigned i = 0; i < NumValues; ++i) {
7114 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7115 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7117 SDValue L = CLI.DAG.getLoad(
7118 RetTys[i], CLI.DL, CLI.Chain, Add,
7119 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7120 DemoteStackIdx, Offsets[i]),
7121 false, false, false, 1);
7122 ReturnValues[i] = L;
7123 Chains[i] = L.getValue(1);
7126 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7128 // Collect the legal value parts into potentially illegal values
7129 // that correspond to the original function's return values.
7130 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7132 AssertOp = ISD::AssertSext;
7133 else if (CLI.RetZExt)
7134 AssertOp = ISD::AssertZext;
7135 unsigned CurReg = 0;
7136 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7138 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7139 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7141 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7142 NumRegs, RegisterVT, VT, nullptr,
7147 // For a function returning void, there is no return value. We can't create
7148 // such a node, so we just return a null return value in that case. In
7149 // that case, nothing will actually look at the value.
7150 if (ReturnValues.empty())
7151 return std::make_pair(SDValue(), CLI.Chain);
7154 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7155 CLI.DAG.getVTList(RetTys), ReturnValues);
7156 return std::make_pair(Res, CLI.Chain);
7159 void TargetLowering::LowerOperationWrapper(SDNode *N,
7160 SmallVectorImpl<SDValue> &Results,
7161 SelectionDAG &DAG) const {
7162 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7164 Results.push_back(Res);
7167 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7168 llvm_unreachable("LowerOperation not implemented for this target!");
7172 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7173 SDValue Op = getNonRegisterValue(V);
7174 assert((Op.getOpcode() != ISD::CopyFromReg ||
7175 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7176 "Copy from a reg to the same reg!");
7177 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7180 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7182 SDValue Chain = DAG.getEntryNode();
7184 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7185 FuncInfo.PreferredExtendType.end())
7187 : FuncInfo.PreferredExtendType[V];
7188 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7189 PendingExports.push_back(Chain);
7192 #include "llvm/CodeGen/SelectionDAGISel.h"
7194 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7195 /// entry block, return true. This includes arguments used by switches, since
7196 /// the switch may expand into multiple basic blocks.
7197 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7198 // With FastISel active, we may be splitting blocks, so force creation
7199 // of virtual registers for all non-dead arguments.
7201 return A->use_empty();
7203 const BasicBlock *Entry = A->getParent()->begin();
7204 for (const User *U : A->users())
7205 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7206 return false; // Use not in entry block.
7211 void SelectionDAGISel::LowerArguments(const Function &F) {
7212 SelectionDAG &DAG = SDB->DAG;
7213 SDLoc dl = SDB->getCurSDLoc();
7214 const DataLayout &DL = DAG.getDataLayout();
7215 SmallVector<ISD::InputArg, 16> Ins;
7217 if (!FuncInfo->CanLowerReturn) {
7218 // Put in an sret pointer parameter before all the other parameters.
7219 SmallVector<EVT, 1> ValueVTs;
7220 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7221 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7223 // NOTE: Assuming that a pointer will never break down to more than one VT
7225 ISD::ArgFlagsTy Flags;
7227 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7228 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7229 ISD::InputArg::NoArgIndex, 0);
7230 Ins.push_back(RetArg);
7233 // Set up the incoming argument description vector.
7235 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7236 I != E; ++I, ++Idx) {
7237 SmallVector<EVT, 4> ValueVTs;
7238 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7239 bool isArgValueUsed = !I->use_empty();
7240 unsigned PartBase = 0;
7241 Type *FinalType = I->getType();
7242 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7243 FinalType = cast<PointerType>(FinalType)->getElementType();
7244 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7245 FinalType, F.getCallingConv(), F.isVarArg());
7246 for (unsigned Value = 0, NumValues = ValueVTs.size();
7247 Value != NumValues; ++Value) {
7248 EVT VT = ValueVTs[Value];
7249 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7250 ISD::ArgFlagsTy Flags;
7251 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7253 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7255 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7257 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7259 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7261 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7263 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7264 Flags.setInAlloca();
7265 // Set the byval flag for CCAssignFn callbacks that don't know about
7266 // inalloca. This way we can know how many bytes we should've allocated
7267 // and how many bytes a callee cleanup function will pop. If we port
7268 // inalloca to more targets, we'll have to add custom inalloca handling
7269 // in the various CC lowering callbacks.
7272 if (Flags.isByVal() || Flags.isInAlloca()) {
7273 PointerType *Ty = cast<PointerType>(I->getType());
7274 Type *ElementTy = Ty->getElementType();
7275 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7276 // For ByVal, alignment should be passed from FE. BE will guess if
7277 // this info is not there but there are cases it cannot get right.
7278 unsigned FrameAlign;
7279 if (F.getParamAlignment(Idx))
7280 FrameAlign = F.getParamAlignment(Idx);
7282 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7283 Flags.setByValAlign(FrameAlign);
7285 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7288 Flags.setInConsecutiveRegs();
7289 Flags.setOrigAlign(OriginalAlignment);
7291 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7292 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7293 for (unsigned i = 0; i != NumRegs; ++i) {
7294 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7295 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7296 if (NumRegs > 1 && i == 0)
7297 MyFlags.Flags.setSplit();
7298 // if it isn't first piece, alignment must be 1
7300 MyFlags.Flags.setOrigAlign(1);
7301 Ins.push_back(MyFlags);
7303 if (NeedsRegBlock && Value == NumValues - 1)
7304 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7305 PartBase += VT.getStoreSize();
7309 // Call the target to set up the argument values.
7310 SmallVector<SDValue, 8> InVals;
7311 SDValue NewRoot = TLI->LowerFormalArguments(
7312 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7314 // Verify that the target's LowerFormalArguments behaved as expected.
7315 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7316 "LowerFormalArguments didn't return a valid chain!");
7317 assert(InVals.size() == Ins.size() &&
7318 "LowerFormalArguments didn't emit the correct number of values!");
7320 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7321 assert(InVals[i].getNode() &&
7322 "LowerFormalArguments emitted a null value!");
7323 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7324 "LowerFormalArguments emitted a value with the wrong type!");
7328 // Update the DAG with the new chain value resulting from argument lowering.
7329 DAG.setRoot(NewRoot);
7331 // Set up the argument values.
7334 if (!FuncInfo->CanLowerReturn) {
7335 // Create a virtual register for the sret pointer, and put in a copy
7336 // from the sret argument into it.
7337 SmallVector<EVT, 1> ValueVTs;
7338 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7339 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7340 MVT VT = ValueVTs[0].getSimpleVT();
7341 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7342 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7343 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7344 RegVT, VT, nullptr, AssertOp);
7346 MachineFunction& MF = SDB->DAG.getMachineFunction();
7347 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7348 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7349 FuncInfo->DemoteRegister = SRetReg;
7351 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7352 DAG.setRoot(NewRoot);
7354 // i indexes lowered arguments. Bump it past the hidden sret argument.
7355 // Idx indexes LLVM arguments. Don't touch it.
7359 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7361 SmallVector<SDValue, 4> ArgValues;
7362 SmallVector<EVT, 4> ValueVTs;
7363 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7364 unsigned NumValues = ValueVTs.size();
7366 // If this argument is unused then remember its value. It is used to generate
7367 // debugging information.
7368 if (I->use_empty() && NumValues) {
7369 SDB->setUnusedArgValue(I, InVals[i]);
7371 // Also remember any frame index for use in FastISel.
7372 if (FrameIndexSDNode *FI =
7373 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7374 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7377 for (unsigned Val = 0; Val != NumValues; ++Val) {
7378 EVT VT = ValueVTs[Val];
7379 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7380 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7382 if (!I->use_empty()) {
7383 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7384 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7385 AssertOp = ISD::AssertSext;
7386 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7387 AssertOp = ISD::AssertZext;
7389 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7390 NumParts, PartVT, VT,
7391 nullptr, AssertOp));
7397 // We don't need to do anything else for unused arguments.
7398 if (ArgValues.empty())
7401 // Note down frame index.
7402 if (FrameIndexSDNode *FI =
7403 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7404 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7406 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7407 SDB->getCurSDLoc());
7409 SDB->setValue(I, Res);
7410 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7411 if (LoadSDNode *LNode =
7412 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7413 if (FrameIndexSDNode *FI =
7414 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7415 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7418 // If this argument is live outside of the entry block, insert a copy from
7419 // wherever we got it to the vreg that other BB's will reference it as.
7420 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7421 // If we can, though, try to skip creating an unnecessary vreg.
7422 // FIXME: This isn't very clean... it would be nice to make this more
7423 // general. It's also subtly incompatible with the hacks FastISel
7425 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7426 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7427 FuncInfo->ValueMap[I] = Reg;
7431 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7432 FuncInfo->InitializeRegForValue(I);
7433 SDB->CopyToExportRegsIfNeeded(I);
7437 assert(i == InVals.size() && "Argument register count mismatch!");
7439 // Finally, if the target has anything special to do, allow it to do so.
7440 EmitFunctionEntryCode();
7443 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7444 /// ensure constants are generated when needed. Remember the virtual registers
7445 /// that need to be added to the Machine PHI nodes as input. We cannot just
7446 /// directly add them, because expansion might result in multiple MBB's for one
7447 /// BB. As such, the start of the BB might correspond to a different MBB than
7451 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7452 const TerminatorInst *TI = LLVMBB->getTerminator();
7454 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7456 // Check PHI nodes in successors that expect a value to be available from this
7458 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7459 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7460 if (!isa<PHINode>(SuccBB->begin())) continue;
7461 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7463 // If this terminator has multiple identical successors (common for
7464 // switches), only handle each succ once.
7465 if (!SuccsHandled.insert(SuccMBB).second)
7468 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7470 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7471 // nodes and Machine PHI nodes, but the incoming operands have not been
7473 for (BasicBlock::const_iterator I = SuccBB->begin();
7474 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7475 // Ignore dead phi's.
7476 if (PN->use_empty()) continue;
7479 if (PN->getType()->isEmptyTy())
7483 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7485 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7486 unsigned &RegOut = ConstantsOut[C];
7488 RegOut = FuncInfo.CreateRegs(C->getType());
7489 CopyValueToVirtualRegister(C, RegOut);
7493 DenseMap<const Value *, unsigned>::iterator I =
7494 FuncInfo.ValueMap.find(PHIOp);
7495 if (I != FuncInfo.ValueMap.end())
7498 assert(isa<AllocaInst>(PHIOp) &&
7499 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7500 "Didn't codegen value into a register!??");
7501 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7502 CopyValueToVirtualRegister(PHIOp, Reg);
7506 // Remember that this register needs to added to the machine PHI node as
7507 // the input for this MBB.
7508 SmallVector<EVT, 4> ValueVTs;
7509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7510 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7511 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7512 EVT VT = ValueVTs[vti];
7513 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7514 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7515 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7516 Reg += NumRegisters;
7521 ConstantsOut.clear();
7524 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7527 SelectionDAGBuilder::StackProtectorDescriptor::
7528 AddSuccessorMBB(const BasicBlock *BB,
7529 MachineBasicBlock *ParentMBB,
7531 MachineBasicBlock *SuccMBB) {
7532 // If SuccBB has not been created yet, create it.
7534 MachineFunction *MF = ParentMBB->getParent();
7535 MachineFunction::iterator BBI = ParentMBB;
7536 SuccMBB = MF->CreateMachineBasicBlock(BB);
7537 MF->insert(++BBI, SuccMBB);
7539 // Add it as a successor of ParentMBB.
7540 ParentMBB->addSuccessor(
7541 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7545 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7546 MachineFunction::iterator I = MBB;
7547 if (++I == FuncInfo.MF->end())
7552 /// During lowering new call nodes can be created (such as memset, etc.).
7553 /// Those will become new roots of the current DAG, but complications arise
7554 /// when they are tail calls. In such cases, the call lowering will update
7555 /// the root, but the builder still needs to know that a tail call has been
7556 /// lowered in order to avoid generating an additional return.
7557 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7558 // If the node is null, we do have a tail call.
7559 if (MaybeTC.getNode() != nullptr)
7560 DAG.setRoot(MaybeTC);
7565 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7566 unsigned *TotalCases, unsigned First,
7568 assert(Last >= First);
7569 assert(TotalCases[Last] >= TotalCases[First]);
7571 APInt LowCase = Clusters[First].Low->getValue();
7572 APInt HighCase = Clusters[Last].High->getValue();
7573 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7575 // FIXME: A range of consecutive cases has 100% density, but only requires one
7576 // comparison to lower. We should discriminate against such consecutive ranges
7579 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7580 uint64_t Range = Diff + 1;
7583 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7585 assert(NumCases < UINT64_MAX / 100);
7586 assert(Range >= NumCases);
7588 return NumCases * 100 >= Range * MinJumpTableDensity;
7591 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7592 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7593 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7596 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7597 unsigned First, unsigned Last,
7598 const SwitchInst *SI,
7599 MachineBasicBlock *DefaultMBB,
7600 CaseCluster &JTCluster) {
7601 assert(First <= Last);
7603 uint32_t Weight = 0;
7604 unsigned NumCmps = 0;
7605 std::vector<MachineBasicBlock*> Table;
7606 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7607 for (unsigned I = First; I <= Last; ++I) {
7608 assert(Clusters[I].Kind == CC_Range);
7609 Weight += Clusters[I].Weight;
7610 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7611 APInt Low = Clusters[I].Low->getValue();
7612 APInt High = Clusters[I].High->getValue();
7613 NumCmps += (Low == High) ? 1 : 2;
7615 // Fill the gap between this and the previous cluster.
7616 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7617 assert(PreviousHigh.slt(Low));
7618 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7619 for (uint64_t J = 0; J < Gap; J++)
7620 Table.push_back(DefaultMBB);
7622 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7623 for (uint64_t J = 0; J < ClusterSize; ++J)
7624 Table.push_back(Clusters[I].MBB);
7625 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7628 unsigned NumDests = JTWeights.size();
7629 if (isSuitableForBitTests(NumDests, NumCmps,
7630 Clusters[First].Low->getValue(),
7631 Clusters[Last].High->getValue())) {
7632 // Clusters[First..Last] should be lowered as bit tests instead.
7636 // Create the MBB that will load from and jump through the table.
7637 // Note: We create it here, but it's not inserted into the function yet.
7638 MachineFunction *CurMF = FuncInfo.MF;
7639 MachineBasicBlock *JumpTableMBB =
7640 CurMF->CreateMachineBasicBlock(SI->getParent());
7642 // Add successors. Note: use table order for determinism.
7643 SmallPtrSet<MachineBasicBlock *, 8> Done;
7644 for (MachineBasicBlock *Succ : Table) {
7645 if (Done.count(Succ))
7647 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7652 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7653 ->createJumpTableIndex(Table);
7655 // Set up the jump table info.
7656 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7657 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7658 Clusters[Last].High->getValue(), SI->getCondition(),
7660 JTCases.emplace_back(std::move(JTH), std::move(JT));
7662 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7663 JTCases.size() - 1, Weight);
7667 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7668 const SwitchInst *SI,
7669 MachineBasicBlock *DefaultMBB) {
7671 // Clusters must be non-empty, sorted, and only contain Range clusters.
7672 assert(!Clusters.empty());
7673 for (CaseCluster &C : Clusters)
7674 assert(C.Kind == CC_Range);
7675 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7676 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7680 if (!areJTsAllowed(TLI))
7683 const int64_t N = Clusters.size();
7684 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7686 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7687 SmallVector<unsigned, 8> TotalCases(N);
7689 for (unsigned i = 0; i < N; ++i) {
7690 APInt Hi = Clusters[i].High->getValue();
7691 APInt Lo = Clusters[i].Low->getValue();
7692 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7694 TotalCases[i] += TotalCases[i - 1];
7697 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7698 // Cheap case: the whole range might be suitable for jump table.
7699 CaseCluster JTCluster;
7700 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7701 Clusters[0] = JTCluster;
7707 // The algorithm below is not suitable for -O0.
7708 if (TM.getOptLevel() == CodeGenOpt::None)
7711 // Split Clusters into minimum number of dense partitions. The algorithm uses
7712 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7713 // for the Case Statement'" (1994), but builds the MinPartitions array in
7714 // reverse order to make it easier to reconstruct the partitions in ascending
7715 // order. In the choice between two optimal partitionings, it picks the one
7716 // which yields more jump tables.
7718 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7719 SmallVector<unsigned, 8> MinPartitions(N);
7720 // LastElement[i] is the last element of the partition starting at i.
7721 SmallVector<unsigned, 8> LastElement(N);
7722 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7723 SmallVector<unsigned, 8> NumTables(N);
7725 // Base case: There is only one way to partition Clusters[N-1].
7726 MinPartitions[N - 1] = 1;
7727 LastElement[N - 1] = N - 1;
7728 assert(MinJumpTableSize > 1);
7729 NumTables[N - 1] = 0;
7731 // Note: loop indexes are signed to avoid underflow.
7732 for (int64_t i = N - 2; i >= 0; i--) {
7733 // Find optimal partitioning of Clusters[i..N-1].
7734 // Baseline: Put Clusters[i] into a partition on its own.
7735 MinPartitions[i] = MinPartitions[i + 1] + 1;
7737 NumTables[i] = NumTables[i + 1];
7739 // Search for a solution that results in fewer partitions.
7740 for (int64_t j = N - 1; j > i; j--) {
7741 // Try building a partition from Clusters[i..j].
7742 if (isDense(Clusters, &TotalCases[0], i, j)) {
7743 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7744 bool IsTable = j - i + 1 >= MinJumpTableSize;
7745 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7747 // If this j leads to fewer partitions, or same number of partitions
7748 // with more lookup tables, it is a better partitioning.
7749 if (NumPartitions < MinPartitions[i] ||
7750 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7751 MinPartitions[i] = NumPartitions;
7753 NumTables[i] = Tables;
7759 // Iterate over the partitions, replacing some with jump tables in-place.
7760 unsigned DstIndex = 0;
7761 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7762 Last = LastElement[First];
7763 assert(Last >= First);
7764 assert(DstIndex <= First);
7765 unsigned NumClusters = Last - First + 1;
7767 CaseCluster JTCluster;
7768 if (NumClusters >= MinJumpTableSize &&
7769 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7770 Clusters[DstIndex++] = JTCluster;
7772 for (unsigned I = First; I <= Last; ++I)
7773 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7776 Clusters.resize(DstIndex);
7779 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7780 // FIXME: Using the pointer type doesn't seem ideal.
7781 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7782 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7786 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7789 const APInt &High) {
7790 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7791 // range of cases both require only one branch to lower. Just looking at the
7792 // number of clusters and destinations should be enough to decide whether to
7795 // To lower a range with bit tests, the range must fit the bitwidth of a
7797 if (!rangeFitsInWord(Low, High))
7800 // Decide whether it's profitable to lower this range with bit tests. Each
7801 // destination requires a bit test and branch, and there is an overall range
7802 // check branch. For a small number of clusters, separate comparisons might be
7803 // cheaper, and for many destinations, splitting the range might be better.
7804 return (NumDests == 1 && NumCmps >= 3) ||
7805 (NumDests == 2 && NumCmps >= 5) ||
7806 (NumDests == 3 && NumCmps >= 6);
7809 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7810 unsigned First, unsigned Last,
7811 const SwitchInst *SI,
7812 CaseCluster &BTCluster) {
7813 assert(First <= Last);
7817 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7818 unsigned NumCmps = 0;
7819 for (int64_t I = First; I <= Last; ++I) {
7820 assert(Clusters[I].Kind == CC_Range);
7821 Dests.set(Clusters[I].MBB->getNumber());
7822 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7824 unsigned NumDests = Dests.count();
7826 APInt Low = Clusters[First].Low->getValue();
7827 APInt High = Clusters[Last].High->getValue();
7828 assert(Low.slt(High));
7830 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7836 const int BitWidth = DAG.getTargetLoweringInfo()
7837 .getPointerTy(DAG.getDataLayout())
7839 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7841 // Check if the clusters cover a contiguous range such that no value in the
7842 // range will jump to the default statement.
7843 bool ContiguousRange = true;
7844 for (int64_t I = First + 1; I <= Last; ++I) {
7845 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7846 ContiguousRange = false;
7851 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7852 // Optimize the case where all the case values fit in a word without having
7853 // to subtract minValue. In this case, we can optimize away the subtraction.
7854 LowBound = APInt::getNullValue(Low.getBitWidth());
7856 ContiguousRange = false;
7859 CmpRange = High - Low;
7863 uint32_t TotalWeight = 0;
7864 for (unsigned i = First; i <= Last; ++i) {
7865 // Find the CaseBits for this destination.
7867 for (j = 0; j < CBV.size(); ++j)
7868 if (CBV[j].BB == Clusters[i].MBB)
7870 if (j == CBV.size())
7871 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7872 CaseBits *CB = &CBV[j];
7874 // Update Mask, Bits and ExtraWeight.
7875 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7876 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7877 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7878 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7879 CB->Bits += Hi - Lo + 1;
7880 CB->ExtraWeight += Clusters[i].Weight;
7881 TotalWeight += Clusters[i].Weight;
7882 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7886 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7887 // Sort by weight first, number of bits second.
7888 if (a.ExtraWeight != b.ExtraWeight)
7889 return a.ExtraWeight > b.ExtraWeight;
7890 return a.Bits > b.Bits;
7893 for (auto &CB : CBV) {
7894 MachineBasicBlock *BitTestBB =
7895 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7896 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7898 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7899 SI->getCondition(), -1U, MVT::Other, false,
7900 ContiguousRange, nullptr, nullptr, std::move(BTI),
7903 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7904 BitTestCases.size() - 1, TotalWeight);
7908 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7909 const SwitchInst *SI) {
7910 // Partition Clusters into as few subsets as possible, where each subset has a
7911 // range that fits in a machine word and has <= 3 unique destinations.
7914 // Clusters must be sorted and contain Range or JumpTable clusters.
7915 assert(!Clusters.empty());
7916 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7917 for (const CaseCluster &C : Clusters)
7918 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7919 for (unsigned i = 1; i < Clusters.size(); ++i)
7920 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7923 // The algorithm below is not suitable for -O0.
7924 if (TM.getOptLevel() == CodeGenOpt::None)
7927 // If target does not have legal shift left, do not emit bit tests at all.
7928 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7929 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7930 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7933 int BitWidth = PTy.getSizeInBits();
7934 const int64_t N = Clusters.size();
7936 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7937 SmallVector<unsigned, 8> MinPartitions(N);
7938 // LastElement[i] is the last element of the partition starting at i.
7939 SmallVector<unsigned, 8> LastElement(N);
7941 // FIXME: This might not be the best algorithm for finding bit test clusters.
7943 // Base case: There is only one way to partition Clusters[N-1].
7944 MinPartitions[N - 1] = 1;
7945 LastElement[N - 1] = N - 1;
7947 // Note: loop indexes are signed to avoid underflow.
7948 for (int64_t i = N - 2; i >= 0; --i) {
7949 // Find optimal partitioning of Clusters[i..N-1].
7950 // Baseline: Put Clusters[i] into a partition on its own.
7951 MinPartitions[i] = MinPartitions[i + 1] + 1;
7954 // Search for a solution that results in fewer partitions.
7955 // Note: the search is limited by BitWidth, reducing time complexity.
7956 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7957 // Try building a partition from Clusters[i..j].
7960 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7961 Clusters[j].High->getValue()))
7964 // Check nbr of destinations and cluster types.
7965 // FIXME: This works, but doesn't seem very efficient.
7966 bool RangesOnly = true;
7967 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7968 for (int64_t k = i; k <= j; k++) {
7969 if (Clusters[k].Kind != CC_Range) {
7973 Dests.set(Clusters[k].MBB->getNumber());
7975 if (!RangesOnly || Dests.count() > 3)
7978 // Check if it's a better partition.
7979 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7980 if (NumPartitions < MinPartitions[i]) {
7981 // Found a better partition.
7982 MinPartitions[i] = NumPartitions;
7988 // Iterate over the partitions, replacing with bit-test clusters in-place.
7989 unsigned DstIndex = 0;
7990 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7991 Last = LastElement[First];
7992 assert(First <= Last);
7993 assert(DstIndex <= First);
7995 CaseCluster BitTestCluster;
7996 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7997 Clusters[DstIndex++] = BitTestCluster;
7999 size_t NumClusters = Last - First + 1;
8000 std::memmove(&Clusters[DstIndex], &Clusters[First],
8001 sizeof(Clusters[0]) * NumClusters);
8002 DstIndex += NumClusters;
8005 Clusters.resize(DstIndex);
8008 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8009 MachineBasicBlock *SwitchMBB,
8010 MachineBasicBlock *DefaultMBB) {
8011 MachineFunction *CurMF = FuncInfo.MF;
8012 MachineBasicBlock *NextMBB = nullptr;
8013 MachineFunction::iterator BBI = W.MBB;
8014 if (++BBI != FuncInfo.MF->end())
8017 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8019 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8021 if (Size == 2 && W.MBB == SwitchMBB) {
8022 // If any two of the cases has the same destination, and if one value
8023 // is the same as the other, but has one bit unset that the other has set,
8024 // use bit manipulation to do two compares at once. For example:
8025 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8026 // TODO: This could be extended to merge any 2 cases in switches with 3
8028 // TODO: Handle cases where W.CaseBB != SwitchBB.
8029 CaseCluster &Small = *W.FirstCluster;
8030 CaseCluster &Big = *W.LastCluster;
8032 if (Small.Low == Small.High && Big.Low == Big.High &&
8033 Small.MBB == Big.MBB) {
8034 const APInt &SmallValue = Small.Low->getValue();
8035 const APInt &BigValue = Big.Low->getValue();
8037 // Check that there is only one bit different.
8038 APInt CommonBit = BigValue ^ SmallValue;
8039 if (CommonBit.isPowerOf2()) {
8040 SDValue CondLHS = getValue(Cond);
8041 EVT VT = CondLHS.getValueType();
8042 SDLoc DL = getCurSDLoc();
8044 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8045 DAG.getConstant(CommonBit, DL, VT));
8046 SDValue Cond = DAG.getSetCC(
8047 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8050 // Update successor info.
8051 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8052 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8053 addSuccessorWithWeight(
8054 SwitchMBB, DefaultMBB,
8055 // The default destination is the first successor in IR.
8056 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8059 // Insert the true branch.
8061 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8062 DAG.getBasicBlock(Small.MBB));
8063 // Insert the false branch.
8064 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8065 DAG.getBasicBlock(DefaultMBB));
8067 DAG.setRoot(BrCond);
8073 if (TM.getOptLevel() != CodeGenOpt::None) {
8074 // Order cases by weight so the most likely case will be checked first.
8075 std::sort(W.FirstCluster, W.LastCluster + 1,
8076 [](const CaseCluster &a, const CaseCluster &b) {
8077 return a.Weight > b.Weight;
8080 // Rearrange the case blocks so that the last one falls through if possible
8081 // without without changing the order of weights.
8082 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8084 if (I->Weight > W.LastCluster->Weight)
8086 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8087 std::swap(*I, *W.LastCluster);
8093 // Compute total weight.
8094 uint32_t DefaultWeight = W.DefaultWeight;
8095 uint32_t UnhandledWeights = DefaultWeight;
8096 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8097 UnhandledWeights += I->Weight;
8098 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8101 MachineBasicBlock *CurMBB = W.MBB;
8102 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8103 MachineBasicBlock *Fallthrough;
8104 if (I == W.LastCluster) {
8105 // For the last cluster, fall through to the default destination.
8106 Fallthrough = DefaultMBB;
8108 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8109 CurMF->insert(BBI, Fallthrough);
8110 // Put Cond in a virtual register to make it available from the new blocks.
8111 ExportFromCurrentBlock(Cond);
8113 UnhandledWeights -= I->Weight;
8116 case CC_JumpTable: {
8117 // FIXME: Optimize away range check based on pivot comparisons.
8118 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8119 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8121 // The jump block hasn't been inserted yet; insert it here.
8122 MachineBasicBlock *JumpMBB = JT->MBB;
8123 CurMF->insert(BBI, JumpMBB);
8125 uint32_t JumpWeight = I->Weight;
8126 uint32_t FallthroughWeight = UnhandledWeights;
8128 // If Fallthrough is a target of the jump table, we evenly distribute
8129 // the weight on the edge to Fallthrough to successors of CurMBB.
8130 // Also update the weight on the edge from JumpMBB to Fallthrough.
8131 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8132 SE = JumpMBB->succ_end();
8134 if (*SI == Fallthrough) {
8135 JumpWeight += DefaultWeight / 2;
8136 FallthroughWeight -= DefaultWeight / 2;
8137 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8142 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8143 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8145 // The jump table header will be inserted in our current block, do the
8146 // range check, and fall through to our fallthrough block.
8147 JTH->HeaderBB = CurMBB;
8148 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8150 // If we're in the right place, emit the jump table header right now.
8151 if (CurMBB == SwitchMBB) {
8152 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8153 JTH->Emitted = true;
8158 // FIXME: Optimize away range check based on pivot comparisons.
8159 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8161 // The bit test blocks haven't been inserted yet; insert them here.
8162 for (BitTestCase &BTC : BTB->Cases)
8163 CurMF->insert(BBI, BTC.ThisBB);
8165 // Fill in fields of the BitTestBlock.
8166 BTB->Parent = CurMBB;
8167 BTB->Default = Fallthrough;
8169 BTB->DefaultWeight = UnhandledWeights;
8170 // If the cases in bit test don't form a contiguous range, we evenly
8171 // distribute the weight on the edge to Fallthrough to two successors
8173 if (!BTB->ContiguousRange) {
8174 BTB->Weight += DefaultWeight / 2;
8175 BTB->DefaultWeight -= DefaultWeight / 2;
8178 // If we're in the right place, emit the bit test header right now.
8179 if (CurMBB == SwitchMBB) {
8180 visitBitTestHeader(*BTB, SwitchMBB);
8181 BTB->Emitted = true;
8186 const Value *RHS, *LHS, *MHS;
8188 if (I->Low == I->High) {
8189 // Check Cond == I->Low.
8195 // Check I->Low <= Cond <= I->High.
8202 // The false weight is the sum of all unhandled cases.
8203 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8206 if (CurMBB == SwitchMBB)
8207 visitSwitchCase(CB, SwitchMBB);
8209 SwitchCases.push_back(CB);
8214 CurMBB = Fallthrough;
8218 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8219 CaseClusterIt First,
8220 CaseClusterIt Last) {
8221 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8222 if (X.Weight != CC.Weight)
8223 return X.Weight > CC.Weight;
8225 // Ties are broken by comparing the case value.
8226 return X.Low->getValue().slt(CC.Low->getValue());
8230 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8231 const SwitchWorkListItem &W,
8233 MachineBasicBlock *SwitchMBB) {
8234 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8235 "Clusters not sorted?");
8237 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8239 // Balance the tree based on branch weights to create a near-optimal (in terms
8240 // of search time given key frequency) binary search tree. See e.g. Kurt
8241 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8242 CaseClusterIt LastLeft = W.FirstCluster;
8243 CaseClusterIt FirstRight = W.LastCluster;
8244 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8245 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8247 // Move LastLeft and FirstRight towards each other from opposite directions to
8248 // find a partitioning of the clusters which balances the weight on both
8249 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8250 // taken to ensure 0-weight nodes are distributed evenly.
8252 while (LastLeft + 1 < FirstRight) {
8253 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8254 LeftWeight += (++LastLeft)->Weight;
8256 RightWeight += (--FirstRight)->Weight;
8261 // Our binary search tree differs from a typical BST in that ours can have up
8262 // to three values in each leaf. The pivot selection above doesn't take that
8263 // into account, which means the tree might require more nodes and be less
8264 // efficient. We compensate for this here.
8266 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8267 unsigned NumRight = W.LastCluster - FirstRight + 1;
8269 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8270 // If one side has less than 3 clusters, and the other has more than 3,
8271 // consider taking a cluster from the other side.
8273 if (NumLeft < NumRight) {
8274 // Consider moving the first cluster on the right to the left side.
8275 CaseCluster &CC = *FirstRight;
8276 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8277 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8278 if (LeftSideRank <= RightSideRank) {
8279 // Moving the cluster to the left does not demote it.
8285 assert(NumRight < NumLeft);
8286 // Consider moving the last element on the left to the right side.
8287 CaseCluster &CC = *LastLeft;
8288 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8289 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8290 if (RightSideRank <= LeftSideRank) {
8291 // Moving the cluster to the right does not demot it.
8301 assert(LastLeft + 1 == FirstRight);
8302 assert(LastLeft >= W.FirstCluster);
8303 assert(FirstRight <= W.LastCluster);
8305 // Use the first element on the right as pivot since we will make less-than
8306 // comparisons against it.
8307 CaseClusterIt PivotCluster = FirstRight;
8308 assert(PivotCluster > W.FirstCluster);
8309 assert(PivotCluster <= W.LastCluster);
8311 CaseClusterIt FirstLeft = W.FirstCluster;
8312 CaseClusterIt LastRight = W.LastCluster;
8314 const ConstantInt *Pivot = PivotCluster->Low;
8316 // New blocks will be inserted immediately after the current one.
8317 MachineFunction::iterator BBI = W.MBB;
8320 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8321 // we can branch to its destination directly if it's squeezed exactly in
8322 // between the known lower bound and Pivot - 1.
8323 MachineBasicBlock *LeftMBB;
8324 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8325 FirstLeft->Low == W.GE &&
8326 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8327 LeftMBB = FirstLeft->MBB;
8329 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8330 FuncInfo.MF->insert(BBI, LeftMBB);
8332 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8333 // Put Cond in a virtual register to make it available from the new blocks.
8334 ExportFromCurrentBlock(Cond);
8337 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8338 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8339 // directly if RHS.High equals the current upper bound.
8340 MachineBasicBlock *RightMBB;
8341 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8342 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8343 RightMBB = FirstRight->MBB;
8345 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8346 FuncInfo.MF->insert(BBI, RightMBB);
8348 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8349 // Put Cond in a virtual register to make it available from the new blocks.
8350 ExportFromCurrentBlock(Cond);
8353 // Create the CaseBlock record that will be used to lower the branch.
8354 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8355 LeftWeight, RightWeight);
8357 if (W.MBB == SwitchMBB)
8358 visitSwitchCase(CB, SwitchMBB);
8360 SwitchCases.push_back(CB);
8363 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8364 // Extract cases from the switch.
8365 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8366 CaseClusterVector Clusters;
8367 Clusters.reserve(SI.getNumCases());
8368 for (auto I : SI.cases()) {
8369 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8370 const ConstantInt *CaseVal = I.getCaseValue();
8372 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8373 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8376 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8378 // Cluster adjacent cases with the same destination. We do this at all
8379 // optimization levels because it's cheap to do and will make codegen faster
8380 // if there are many clusters.
8381 sortAndRangeify(Clusters);
8383 if (TM.getOptLevel() != CodeGenOpt::None) {
8384 // Replace an unreachable default with the most popular destination.
8385 // FIXME: Exploit unreachable default more aggressively.
8386 bool UnreachableDefault =
8387 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8388 if (UnreachableDefault && !Clusters.empty()) {
8389 DenseMap<const BasicBlock *, unsigned> Popularity;
8390 unsigned MaxPop = 0;
8391 const BasicBlock *MaxBB = nullptr;
8392 for (auto I : SI.cases()) {
8393 const BasicBlock *BB = I.getCaseSuccessor();
8394 if (++Popularity[BB] > MaxPop) {
8395 MaxPop = Popularity[BB];
8400 assert(MaxPop > 0 && MaxBB);
8401 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8403 // Remove cases that were pointing to the destination that is now the
8405 CaseClusterVector New;
8406 New.reserve(Clusters.size());
8407 for (CaseCluster &CC : Clusters) {
8408 if (CC.MBB != DefaultMBB)
8411 Clusters = std::move(New);
8415 // If there is only the default destination, jump there directly.
8416 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8417 if (Clusters.empty()) {
8418 SwitchMBB->addSuccessor(DefaultMBB);
8419 if (DefaultMBB != NextBlock(SwitchMBB)) {
8420 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8421 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8426 findJumpTables(Clusters, &SI, DefaultMBB);
8427 findBitTestClusters(Clusters, &SI);
8430 dbgs() << "Case clusters: ";
8431 for (const CaseCluster &C : Clusters) {
8432 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8433 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8435 C.Low->getValue().print(dbgs(), true);
8436 if (C.Low != C.High) {
8438 C.High->getValue().print(dbgs(), true);
8445 assert(!Clusters.empty());
8446 SwitchWorkList WorkList;
8447 CaseClusterIt First = Clusters.begin();
8448 CaseClusterIt Last = Clusters.end() - 1;
8449 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8450 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8452 while (!WorkList.empty()) {
8453 SwitchWorkListItem W = WorkList.back();
8454 WorkList.pop_back();
8455 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8457 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8458 // For optimized builds, lower large range as a balanced binary tree.
8459 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8463 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);