1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, DL, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits, DL));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i, DL,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
526 bool Smaller = ValueVT.bitsLE(PartVT);
527 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
552 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy()));
557 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
602 /// this value and returns the result as a ValueVT value. This uses
603 /// Chain/Flag as the input and updates them for the output Chain/Flag.
604 /// If the Flag pointer is NULL, no flag is used.
605 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
606 FunctionLoweringInfo &FuncInfo,
608 SDValue &Chain, SDValue *Flag,
609 const Value *V) const {
610 // A Value with type {} or [0 x %t] needs no registers.
611 if (ValueVTs.empty())
614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
616 // Assemble the legal parts into the final values.
617 SmallVector<SDValue, 4> Values(ValueVTs.size());
618 SmallVector<SDValue, 8> Parts;
619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 // Copy the legal parts from the registers.
621 EVT ValueVT = ValueVTs[Value];
622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
623 MVT RegisterVT = RegVTs[Value];
625 Parts.resize(NumRegs);
626 for (unsigned i = 0; i != NumRegs; ++i) {
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
632 *Flag = P.getValue(2);
635 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
641 !RegisterVT.isInteger() || RegisterVT.isVector())
644 const FunctionLoweringInfo::LiveOutInfo *LOI =
645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
649 unsigned RegSize = RegisterVT.getSizeInBits();
650 unsigned NumSignBits = LOI->NumSignBits;
651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
653 if (NumZeroBits == RegSize) {
654 // The current value is a zero.
655 // Explicitly express that as it would be easier for
656 // optimizations to kick in.
657 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
661 // FIXME: We capture more information than the dag can represent. For
662 // now, just use the tightest assertzext/assertsext possible.
664 EVT FromVT(MVT::Other);
665 if (NumSignBits == RegSize)
666 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
667 else if (NumZeroBits >= RegSize-1)
668 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
669 else if (NumSignBits > RegSize-8)
670 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
671 else if (NumZeroBits >= RegSize-8)
672 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
673 else if (NumSignBits > RegSize-16)
674 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
675 else if (NumZeroBits >= RegSize-16)
676 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
677 else if (NumSignBits > RegSize-32)
678 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
679 else if (NumZeroBits >= RegSize-32)
680 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
684 // Add an assertion node.
685 assert(FromVT != MVT::Other);
686 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
687 RegisterVT, P, DAG.getValueType(FromVT));
690 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
691 NumRegs, RegisterVT, ValueVT, V);
696 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
699 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
700 /// specified value into the registers specified by this object. This uses
701 /// Chain/Flag as the input and updates them for the output Chain/Flag.
702 /// If the Flag pointer is NULL, no flag is used.
703 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
704 SDValue &Chain, SDValue *Flag, const Value *V,
705 ISD::NodeType PreferredExtendType) const {
706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
707 ISD::NodeType ExtendKind = PreferredExtendType;
709 // Get the list of the values's legal parts.
710 unsigned NumRegs = Regs.size();
711 SmallVector<SDValue, 8> Parts(NumRegs);
712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
713 EVT ValueVT = ValueVTs[Value];
714 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
715 MVT RegisterVT = RegVTs[Value];
717 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
718 ExtendKind = ISD::ZERO_EXTEND;
720 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
721 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
725 // Copy the parts into the registers.
726 SmallVector<SDValue, 8> Chains(NumRegs);
727 for (unsigned i = 0; i != NumRegs; ++i) {
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
732 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
733 *Flag = Part.getValue(1);
736 Chains[i] = Part.getValue(0);
739 if (NumRegs == 1 || Flag)
740 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
741 // flagged to it. That is the CopyToReg nodes and the user are considered
742 // a single scheduling unit. If we create a TokenFactor and return it as
743 // chain, then the TokenFactor is both a predecessor (operand) of the
744 // user as well as a successor (the TF operands are flagged to the user).
745 // c1, f1 = CopyToReg
746 // c2, f2 = CopyToReg
747 // c3 = TokenFactor c1, c2
750 Chain = Chains[NumRegs-1];
752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
755 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
756 /// operand list. This adds the code marker and includes the number of
757 /// values added into it.
758 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
759 unsigned MatchingIdx, SDLoc dl,
761 std::vector<SDValue> &Ops) const {
762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
764 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
766 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
767 else if (!Regs.empty() &&
768 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
769 // Put the register class of the virtual registers in the flag word. That
770 // way, later passes can recompute register class constraints for inline
771 // assembly as well as normal instructions.
772 // Don't do this for tied operands that can use the regclass information
774 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
775 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
776 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
779 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
782 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
783 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
784 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
785 MVT RegisterVT = RegVTs[Value];
786 for (unsigned i = 0; i != NumRegs; ++i) {
787 assert(Reg < Regs.size() && "Mismatch in # registers expected");
788 unsigned TheReg = Regs[Reg++];
789 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
791 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
792 // If we clobbered the stack pointer, MFI should know about it.
793 assert(DAG.getMachineFunction().getFrameInfo()->
794 hasInlineAsmWithSPAdjust());
800 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
801 const TargetLibraryInfo *li) {
805 DL = DAG.getTarget().getDataLayout();
806 Context = DAG.getContext();
807 LPadToCallSiteMap.clear();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
823 SDNodeOrder = LowestSDNodeOrder;
824 StatepointLowering.clear();
827 /// clearDanglingDebugInfo - Clear the dangling debug information
828 /// map. This function is separated from the clear so that debug
829 /// information that is dangling in a basic block can be properly
830 /// resolved in a different basic block. This allows the
831 /// SelectionDAG to resolve dangling debug information attached
833 void SelectionDAGBuilder::clearDanglingDebugInfo() {
834 DanglingDebugInfoMap.clear();
837 /// getRoot - Return the current virtual root of the Selection DAG,
838 /// flushing any PendingLoad items. This must be done before emitting
839 /// a store or any other node that may need to be ordered after any
840 /// prior load instructions.
842 SDValue SelectionDAGBuilder::getRoot() {
843 if (PendingLoads.empty())
844 return DAG.getRoot();
846 if (PendingLoads.size() == 1) {
847 SDValue Root = PendingLoads[0];
849 PendingLoads.clear();
853 // Otherwise, we have to make a token factor node.
854 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
856 PendingLoads.clear();
861 /// getControlRoot - Similar to getRoot, but instead of flushing all the
862 /// PendingLoad items, flush all the PendingExports items. It is necessary
863 /// to do this before emitting a terminator instruction.
865 SDValue SelectionDAGBuilder::getControlRoot() {
866 SDValue Root = DAG.getRoot();
868 if (PendingExports.empty())
871 // Turn all of the CopyToReg chains into one factored node.
872 if (Root.getOpcode() != ISD::EntryToken) {
873 unsigned i = 0, e = PendingExports.size();
874 for (; i != e; ++i) {
875 assert(PendingExports[i].getNode()->getNumOperands() > 1);
876 if (PendingExports[i].getNode()->getOperand(0) == Root)
877 break; // Don't add the root if we already indirectly depend on it.
881 PendingExports.push_back(Root);
884 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
886 PendingExports.clear();
891 void SelectionDAGBuilder::visit(const Instruction &I) {
892 // Set up outgoing PHI node register values before emitting the terminator.
893 if (isa<TerminatorInst>(&I))
894 HandlePHINodesInSuccessorBlocks(I.getParent());
900 visit(I.getOpcode(), I);
902 if (!isa<TerminatorInst>(&I) && !HasTailCall)
903 CopyToExportRegsIfNeeded(&I);
908 void SelectionDAGBuilder::visitPHI(const PHINode &) {
909 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
912 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
913 // Note: this doesn't use InstVisitor, because it has to work with
914 // ConstantExpr's in addition to instructions.
916 default: llvm_unreachable("Unknown instruction type encountered!");
917 // Build the switch statement using the Instruction.def file.
918 #define HANDLE_INST(NUM, OPCODE, CLASS) \
919 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
920 #include "llvm/IR/Instruction.def"
924 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
925 // generate the debug data structures now that we've seen its definition.
926 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
928 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
930 const DbgValueInst *DI = DDI.getDI();
931 DebugLoc dl = DDI.getdl();
932 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
933 DILocalVariable *Variable = DI->getVariable();
934 DIExpression *Expr = DI->getExpression();
935 assert(Variable->isValidLocationForIntrinsic(dl) &&
936 "Expected inlined-at fields to agree");
937 uint64_t Offset = DI->getOffset();
938 // A dbg.value for an alloca is always indirect.
939 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
942 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
944 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
945 IsIndirect, Offset, dl, DbgSDNodeOrder);
946 DAG.AddDbgValue(SDV, Val.getNode(), false);
949 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
950 DanglingDebugInfoMap[V] = DanglingDebugInfo();
954 /// getCopyFromRegs - If there was virtual register allocated for the value V
955 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
956 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
957 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
960 if (It != FuncInfo.ValueMap.end()) {
961 unsigned InReg = It->second;
962 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
964 SDValue Chain = DAG.getEntryNode();
965 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
966 resolveDanglingDebugInfo(V, Result);
972 /// getValue - Return an SDValue for the given Value.
973 SDValue SelectionDAGBuilder::getValue(const Value *V) {
974 // If we already have an SDValue for this value, use it. It's important
975 // to do this first, so that we don't create a CopyFromReg if we already
976 // have a regular SDValue.
977 SDValue &N = NodeMap[V];
978 if (N.getNode()) return N;
980 // If there's a virtual register allocated and initialized for this
982 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
983 if (copyFromReg.getNode()) {
987 // Otherwise create a new SDValue and remember it.
988 SDValue Val = getValueImpl(V);
990 resolveDanglingDebugInfo(V, Val);
994 // Return true if SDValue exists for the given Value
995 bool SelectionDAGBuilder::findValue(const Value *V) const {
996 return (NodeMap.find(V) != NodeMap.end()) ||
997 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1000 /// getNonRegisterValue - Return an SDValue for the given Value, but
1001 /// don't look in FuncInfo.ValueMap for a virtual register.
1002 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1003 // If we already have an SDValue for this value, use it.
1004 SDValue &N = NodeMap[V];
1006 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1007 // Remove the debug location from the node as the node is about to be used
1008 // in a location which may differ from the original debug location. This
1009 // is relevant to Constant and ConstantFP nodes because they can appear
1010 // as constant expressions inside PHI nodes.
1011 N->setDebugLoc(DebugLoc());
1016 // Otherwise create a new SDValue and remember it.
1017 SDValue Val = getValueImpl(V);
1019 resolveDanglingDebugInfo(V, Val);
1023 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1024 /// Create an SDValue for the given value.
1025 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1028 if (const Constant *C = dyn_cast<Constant>(V)) {
1029 EVT VT = TLI.getValueType(V->getType(), true);
1031 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1032 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1034 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1035 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1037 if (isa<ConstantPointerNull>(C)) {
1038 unsigned AS = V->getType()->getPointerAddressSpace();
1039 return DAG.getConstant(0, getCurSDLoc(), TLI.getPointerTy(AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1125 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1128 if (EltVT.isFloatingPoint())
1129 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1131 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1132 Ops.assign(NumElements, Op);
1135 // Create a BUILD_VECTOR node.
1136 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1139 // If this is a static alloca, generate it as the frameindex instead of
1141 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1142 DenseMap<const AllocaInst*, int>::iterator SI =
1143 FuncInfo.StaticAllocaMap.find(AI);
1144 if (SI != FuncInfo.StaticAllocaMap.end())
1145 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1148 // If this is an instruction which fast-isel has deferred, select it now.
1149 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1150 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1151 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1152 SDValue Chain = DAG.getEntryNode();
1153 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1156 llvm_unreachable("Can't get register for value!");
1159 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1160 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1161 SDValue Chain = getControlRoot();
1162 SmallVector<ISD::OutputArg, 8> Outs;
1163 SmallVector<SDValue, 8> OutVals;
1165 if (!FuncInfo.CanLowerReturn) {
1166 unsigned DemoteReg = FuncInfo.DemoteRegister;
1167 const Function *F = I.getParent()->getParent();
1169 // Emit a store of the return value through the virtual register.
1170 // Leave Outs empty so that LowerReturn won't try to load return
1171 // registers the usual way.
1172 SmallVector<EVT, 1> PtrValueVTs;
1173 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1176 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1177 SDValue RetOp = getValue(I.getOperand(0));
1179 SmallVector<EVT, 4> ValueVTs;
1180 SmallVector<uint64_t, 4> Offsets;
1181 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1182 unsigned NumValues = ValueVTs.size();
1184 SmallVector<SDValue, 4> Chains(NumValues);
1185 for (unsigned i = 0; i != NumValues; ++i) {
1186 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1187 RetPtr.getValueType(), RetPtr,
1188 DAG.getIntPtrConstant(Offsets[i],
1191 DAG.getStore(Chain, getCurSDLoc(),
1192 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1193 // FIXME: better loc info would be nice.
1194 Add, MachinePointerInfo(), false, false, 0);
1197 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1198 MVT::Other, Chains);
1199 } else if (I.getNumOperands() != 0) {
1200 SmallVector<EVT, 4> ValueVTs;
1201 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1202 unsigned NumValues = ValueVTs.size();
1204 SDValue RetOp = getValue(I.getOperand(0));
1206 const Function *F = I.getParent()->getParent();
1208 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1209 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1211 ExtendKind = ISD::SIGN_EXTEND;
1212 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1214 ExtendKind = ISD::ZERO_EXTEND;
1216 LLVMContext &Context = F->getContext();
1217 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1220 for (unsigned j = 0; j != NumValues; ++j) {
1221 EVT VT = ValueVTs[j];
1223 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1224 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1226 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1227 MVT PartVT = TLI.getRegisterType(Context, VT);
1228 SmallVector<SDValue, 4> Parts(NumParts);
1229 getCopyToParts(DAG, getCurSDLoc(),
1230 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1231 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1233 // 'inreg' on function refers to return value
1234 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1238 // Propagate extension type if any
1239 if (ExtendKind == ISD::SIGN_EXTEND)
1241 else if (ExtendKind == ISD::ZERO_EXTEND)
1244 for (unsigned i = 0; i < NumParts; ++i) {
1245 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1246 VT, /*isfixed=*/true, 0, 0));
1247 OutVals.push_back(Parts[i]);
1253 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1254 CallingConv::ID CallConv =
1255 DAG.getMachineFunction().getFunction()->getCallingConv();
1256 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1257 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1259 // Verify that the target's LowerReturn behaved as expected.
1260 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1261 "LowerReturn didn't return a valid chain!");
1263 // Update the DAG with the new chain value resulting from return lowering.
1267 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1268 /// created for it, emit nodes to copy the value into the virtual
1270 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1272 if (V->getType()->isEmptyTy())
1275 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1276 if (VMI != FuncInfo.ValueMap.end()) {
1277 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1278 CopyValueToVirtualRegister(V, VMI->second);
1282 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1283 /// the current basic block, add it to ValueMap now so that we'll get a
1285 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1286 // No need to export constants.
1287 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1289 // Already exported?
1290 if (FuncInfo.isExportedInst(V)) return;
1292 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1293 CopyValueToVirtualRegister(V, Reg);
1296 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1297 const BasicBlock *FromBB) {
1298 // The operands of the setcc have to be in this block. We don't know
1299 // how to export them from some other block.
1300 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1301 // Can export from current BB.
1302 if (VI->getParent() == FromBB)
1305 // Is already exported, noop.
1306 return FuncInfo.isExportedInst(V);
1309 // If this is an argument, we can export it if the BB is the entry block or
1310 // if it is already exported.
1311 if (isa<Argument>(V)) {
1312 if (FromBB == &FromBB->getParent()->getEntryBlock())
1315 // Otherwise, can only export this if it is already exported.
1316 return FuncInfo.isExportedInst(V);
1319 // Otherwise, constants can always be exported.
1323 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1324 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1325 const MachineBasicBlock *Dst) const {
1326 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1329 const BasicBlock *SrcBB = Src->getBasicBlock();
1330 const BasicBlock *DstBB = Dst->getBasicBlock();
1331 return BPI->getEdgeWeight(SrcBB, DstBB);
1334 void SelectionDAGBuilder::
1335 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1336 uint32_t Weight /* = 0 */) {
1338 Weight = getEdgeWeight(Src, Dst);
1339 Src->addSuccessor(Dst, Weight);
1343 static bool InBlock(const Value *V, const BasicBlock *BB) {
1344 if (const Instruction *I = dyn_cast<Instruction>(V))
1345 return I->getParent() == BB;
1349 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1350 /// This function emits a branch and is used at the leaves of an OR or an
1351 /// AND operator tree.
1354 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1355 MachineBasicBlock *TBB,
1356 MachineBasicBlock *FBB,
1357 MachineBasicBlock *CurBB,
1358 MachineBasicBlock *SwitchBB,
1361 const BasicBlock *BB = CurBB->getBasicBlock();
1363 // If the leaf of the tree is a comparison, merge the condition into
1365 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1366 // The operands of the cmp have to be in this block. We don't know
1367 // how to export them from some other block. If this is the first block
1368 // of the sequence, no exporting is needed.
1369 if (CurBB == SwitchBB ||
1370 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1371 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1372 ISD::CondCode Condition;
1373 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1374 Condition = getICmpCondCode(IC->getPredicate());
1375 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1376 Condition = getFCmpCondCode(FC->getPredicate());
1377 if (TM.Options.NoNaNsFPMath)
1378 Condition = getFCmpCodeWithoutNaN(Condition);
1380 (void)Condition; // silence warning.
1381 llvm_unreachable("Unknown compare instruction");
1384 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1385 TBB, FBB, CurBB, TWeight, FWeight);
1386 SwitchCases.push_back(CB);
1391 // Create a CaseBlock record representing this branch.
1392 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1393 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1394 SwitchCases.push_back(CB);
1397 /// Scale down both weights to fit into uint32_t.
1398 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1399 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1400 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1401 NewTrue = NewTrue / Scale;
1402 NewFalse = NewFalse / Scale;
1405 /// FindMergedConditions - If Cond is an expression like
1406 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1407 MachineBasicBlock *TBB,
1408 MachineBasicBlock *FBB,
1409 MachineBasicBlock *CurBB,
1410 MachineBasicBlock *SwitchBB,
1411 unsigned Opc, uint32_t TWeight,
1413 // If this node is not part of the or/and tree, emit it as a branch.
1414 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1415 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1416 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1417 BOp->getParent() != CurBB->getBasicBlock() ||
1418 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1419 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1420 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1425 // Create TmpBB after CurBB.
1426 MachineFunction::iterator BBI = CurBB;
1427 MachineFunction &MF = DAG.getMachineFunction();
1428 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1429 CurBB->getParent()->insert(++BBI, TmpBB);
1431 if (Opc == Instruction::Or) {
1432 // Codegen X | Y as:
1441 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1442 // The requirement is that
1443 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1444 // = TrueProb for orignal BB.
1445 // Assuming the orignal weights are A and B, one choice is to set BB1's
1446 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1448 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1449 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1450 // TmpBB, but the math is more complicated.
1452 uint64_t NewTrueWeight = TWeight;
1453 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1454 ScaleWeights(NewTrueWeight, NewFalseWeight);
1455 // Emit the LHS condition.
1456 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1457 NewTrueWeight, NewFalseWeight);
1459 NewTrueWeight = TWeight;
1460 NewFalseWeight = 2 * (uint64_t)FWeight;
1461 ScaleWeights(NewTrueWeight, NewFalseWeight);
1462 // Emit the RHS condition into TmpBB.
1463 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1464 NewTrueWeight, NewFalseWeight);
1466 assert(Opc == Instruction::And && "Unknown merge op!");
1467 // Codegen X & Y as:
1475 // This requires creation of TmpBB after CurBB.
1477 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1478 // The requirement is that
1479 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1480 // = FalseProb for orignal BB.
1481 // Assuming the orignal weights are A and B, one choice is to set BB1's
1482 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1484 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1486 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1487 uint64_t NewFalseWeight = FWeight;
1488 ScaleWeights(NewTrueWeight, NewFalseWeight);
1489 // Emit the LHS condition.
1490 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1491 NewTrueWeight, NewFalseWeight);
1493 NewTrueWeight = 2 * (uint64_t)TWeight;
1494 NewFalseWeight = FWeight;
1495 ScaleWeights(NewTrueWeight, NewFalseWeight);
1496 // Emit the RHS condition into TmpBB.
1497 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1498 NewTrueWeight, NewFalseWeight);
1502 /// If the set of cases should be emitted as a series of branches, return true.
1503 /// If we should emit this as a bunch of and/or'd together conditions, return
1506 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1507 if (Cases.size() != 2) return true;
1509 // If this is two comparisons of the same values or'd or and'd together, they
1510 // will get folded into a single comparison, so don't emit two blocks.
1511 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1512 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1513 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1514 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1518 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1519 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1520 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1521 Cases[0].CC == Cases[1].CC &&
1522 isa<Constant>(Cases[0].CmpRHS) &&
1523 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1524 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1526 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1533 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1534 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1536 // Update machine-CFG edges.
1537 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1539 if (I.isUnconditional()) {
1540 // Update machine-CFG edges.
1541 BrMBB->addSuccessor(Succ0MBB);
1543 // If this is not a fall-through branch or optimizations are switched off,
1545 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1546 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1547 MVT::Other, getControlRoot(),
1548 DAG.getBasicBlock(Succ0MBB)));
1553 // If this condition is one of the special cases we handle, do special stuff
1555 const Value *CondVal = I.getCondition();
1556 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1558 // If this is a series of conditions that are or'd or and'd together, emit
1559 // this as a sequence of branches instead of setcc's with and/or operations.
1560 // As long as jumps are not expensive, this should improve performance.
1561 // For example, instead of something like:
1574 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1575 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1576 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1577 BOp->getOpcode() == Instruction::Or)) {
1578 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1579 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1580 getEdgeWeight(BrMBB, Succ1MBB));
1581 // If the compares in later blocks need to use values not currently
1582 // exported from this block, export them now. This block should always
1583 // be the first entry.
1584 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1586 // Allow some cases to be rejected.
1587 if (ShouldEmitAsBranches(SwitchCases)) {
1588 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1589 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1590 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1593 // Emit the branch for this block.
1594 visitSwitchCase(SwitchCases[0], BrMBB);
1595 SwitchCases.erase(SwitchCases.begin());
1599 // Okay, we decided not to do this, remove any inserted MBB's and clear
1601 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1602 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1604 SwitchCases.clear();
1608 // Create a CaseBlock record representing this branch.
1609 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1610 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1612 // Use visitSwitchCase to actually insert the fast branch sequence for this
1614 visitSwitchCase(CB, BrMBB);
1617 /// visitSwitchCase - Emits the necessary code to represent a single node in
1618 /// the binary search tree resulting from lowering a switch instruction.
1619 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1620 MachineBasicBlock *SwitchBB) {
1622 SDValue CondLHS = getValue(CB.CmpLHS);
1623 SDLoc dl = getCurSDLoc();
1625 // Build the setcc now.
1627 // Fold "(X == true)" to X and "(X == false)" to !X to
1628 // handle common cases produced by branch lowering.
1629 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1630 CB.CC == ISD::SETEQ)
1632 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1633 CB.CC == ISD::SETEQ) {
1634 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1635 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1637 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1639 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1641 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1642 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1644 SDValue CmpOp = getValue(CB.CmpMHS);
1645 EVT VT = CmpOp.getValueType();
1647 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1648 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1651 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1652 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1653 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1654 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1658 // Update successor info
1659 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1660 // TrueBB and FalseBB are always different unless the incoming IR is
1661 // degenerate. This only happens when running llc on weird IR.
1662 if (CB.TrueBB != CB.FalseBB)
1663 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1665 // If the lhs block is the next block, invert the condition so that we can
1666 // fall through to the lhs instead of the rhs block.
1667 if (CB.TrueBB == NextBlock(SwitchBB)) {
1668 std::swap(CB.TrueBB, CB.FalseBB);
1669 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1670 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1673 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1674 MVT::Other, getControlRoot(), Cond,
1675 DAG.getBasicBlock(CB.TrueBB));
1677 // Insert the false branch. Do this even if it's a fall through branch,
1678 // this makes it easier to do DAG optimizations which require inverting
1679 // the branch condition.
1680 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1681 DAG.getBasicBlock(CB.FalseBB));
1683 DAG.setRoot(BrCond);
1686 /// visitJumpTable - Emit JumpTable node in the current MBB
1687 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1688 // Emit the code for the jump table
1689 assert(JT.Reg != -1U && "Should lower JT Header first!");
1690 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1691 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1693 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1694 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1695 MVT::Other, Index.getValue(1),
1697 DAG.setRoot(BrJumpTable);
1700 /// visitJumpTableHeader - This function emits necessary code to produce index
1701 /// in the JumpTable from switch case.
1702 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1703 JumpTableHeader &JTH,
1704 MachineBasicBlock *SwitchBB) {
1705 SDLoc dl = getCurSDLoc();
1707 // Subtract the lowest switch case value from the value being switched on and
1708 // conditional branch to default mbb if the result is greater than the
1709 // difference between smallest and largest cases.
1710 SDValue SwitchOp = getValue(JTH.SValue);
1711 EVT VT = SwitchOp.getValueType();
1712 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1713 DAG.getConstant(JTH.First, dl, VT));
1715 // The SDNode we just created, which holds the value being switched on minus
1716 // the smallest case value, needs to be copied to a virtual register so it
1717 // can be used as an index into the jump table in a subsequent basic block.
1718 // This value may be smaller or larger than the target's pointer type, and
1719 // therefore require extension or truncating.
1720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1721 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy());
1723 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1724 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1725 JumpTableReg, SwitchOp);
1726 JT.Reg = JumpTableReg;
1728 // Emit the range check for the jump table, and branch to the default block
1729 // for the switch statement if the value being switched on exceeds the largest
1730 // case in the switch.
1732 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1733 Sub.getValueType()),
1734 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT),
1737 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1738 MVT::Other, CopyTo, CMP,
1739 DAG.getBasicBlock(JT.Default));
1741 // Avoid emitting unnecessary branches to the next block.
1742 if (JT.MBB != NextBlock(SwitchBB))
1743 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1744 DAG.getBasicBlock(JT.MBB));
1746 DAG.setRoot(BrCond);
1749 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1750 /// tail spliced into a stack protector check success bb.
1752 /// For a high level explanation of how this fits into the stack protector
1753 /// generation see the comment on the declaration of class
1754 /// StackProtectorDescriptor.
1755 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1756 MachineBasicBlock *ParentBB) {
1758 // First create the loads to the guard/stack slot for the comparison.
1759 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1760 EVT PtrTy = TLI.getPointerTy();
1762 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1763 int FI = MFI->getStackProtectorIndex();
1765 const Value *IRGuard = SPD.getGuard();
1766 SDValue GuardPtr = getValue(IRGuard);
1767 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1770 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1773 SDLoc dl = getCurSDLoc();
1775 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1776 // guard value from the virtual register holding the value. Otherwise, emit a
1777 // volatile load to retrieve the stack guard value.
1778 unsigned GuardReg = SPD.getGuardReg();
1780 if (GuardReg && TLI.useLoadStackGuardNode())
1781 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1784 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1785 GuardPtr, MachinePointerInfo(IRGuard, 0),
1786 true, false, false, Align);
1788 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1790 MachinePointerInfo::getFixedStack(FI),
1791 true, false, false, Align);
1793 // Perform the comparison via a subtract/getsetcc.
1794 EVT VT = Guard.getValueType();
1795 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1798 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1799 Sub.getValueType()),
1800 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1802 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1803 // branch to failure MBB.
1804 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1805 MVT::Other, StackSlot.getOperand(0),
1806 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1807 // Otherwise branch to success MBB.
1808 SDValue Br = DAG.getNode(ISD::BR, dl,
1810 DAG.getBasicBlock(SPD.getSuccessMBB()));
1815 /// Codegen the failure basic block for a stack protector check.
1817 /// A failure stack protector machine basic block consists simply of a call to
1818 /// __stack_chk_fail().
1820 /// For a high level explanation of how this fits into the stack protector
1821 /// generation see the comment on the declaration of class
1822 /// StackProtectorDescriptor.
1824 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1827 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1828 nullptr, 0, false, getCurSDLoc(), false, false).second;
1832 /// visitBitTestHeader - This function emits necessary code to produce value
1833 /// suitable for "bit tests"
1834 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1835 MachineBasicBlock *SwitchBB) {
1836 SDLoc dl = getCurSDLoc();
1838 // Subtract the minimum value
1839 SDValue SwitchOp = getValue(B.SValue);
1840 EVT VT = SwitchOp.getValueType();
1841 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1842 DAG.getConstant(B.First, dl, VT));
1845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1847 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1848 Sub.getValueType()),
1849 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1851 // Determine the type of the test operands.
1852 bool UsePtrType = false;
1853 if (!TLI.isTypeLegal(VT))
1856 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1857 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1858 // Switch table case range are encoded into series of masks.
1859 // Just use pointer type, it's guaranteed to fit.
1865 VT = TLI.getPointerTy();
1866 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1869 B.RegVT = VT.getSimpleVT();
1870 B.Reg = FuncInfo.CreateReg(B.RegVT);
1871 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1873 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1875 addSuccessorWithWeight(SwitchBB, B.Default);
1876 addSuccessorWithWeight(SwitchBB, MBB);
1878 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1879 MVT::Other, CopyTo, RangeCmp,
1880 DAG.getBasicBlock(B.Default));
1882 // Avoid emitting unnecessary branches to the next block.
1883 if (MBB != NextBlock(SwitchBB))
1884 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1885 DAG.getBasicBlock(MBB));
1887 DAG.setRoot(BrRange);
1890 /// visitBitTestCase - this function produces one "bit test"
1891 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1892 MachineBasicBlock* NextMBB,
1893 uint32_t BranchWeightToNext,
1896 MachineBasicBlock *SwitchBB) {
1897 SDLoc dl = getCurSDLoc();
1899 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1901 unsigned PopCount = countPopulation(B.Mask);
1902 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1903 if (PopCount == 1) {
1904 // Testing for a single bit; just compare the shift count with what it
1905 // would need to be to shift a 1 bit in that position.
1907 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1908 DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), ISD::SETEQ);
1909 } else if (PopCount == BB.Range) {
1910 // There is only one zero bit in the range, test for it directly.
1912 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1913 DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), ISD::SETNE);
1915 // Make desired shift
1916 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1917 DAG.getConstant(1, dl, VT), ShiftOp);
1919 // Emit bit tests and jumps
1920 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1921 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1922 Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1923 DAG.getConstant(0, dl, VT), ISD::SETNE);
1926 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1927 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1928 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1929 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1931 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1932 MVT::Other, getControlRoot(),
1933 Cmp, DAG.getBasicBlock(B.TargetBB));
1935 // Avoid emitting unnecessary branches to the next block.
1936 if (NextMBB != NextBlock(SwitchBB))
1937 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1938 DAG.getBasicBlock(NextMBB));
1943 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1944 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1946 // Retrieve successors.
1947 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1948 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1950 const Value *Callee(I.getCalledValue());
1951 const Function *Fn = dyn_cast<Function>(Callee);
1952 if (isa<InlineAsm>(Callee))
1954 else if (Fn && Fn->isIntrinsic()) {
1955 switch (Fn->getIntrinsicID()) {
1957 llvm_unreachable("Cannot invoke this intrinsic");
1958 case Intrinsic::donothing:
1959 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1961 case Intrinsic::experimental_patchpoint_void:
1962 case Intrinsic::experimental_patchpoint_i64:
1963 visitPatchpoint(&I, LandingPad);
1965 case Intrinsic::experimental_gc_statepoint:
1966 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1970 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1972 // If the value of the invoke is used outside of its defining block, make it
1973 // available as a virtual register.
1974 // We already took care of the exported value for the statepoint instruction
1975 // during call to the LowerStatepoint.
1976 if (!isStatepoint(I)) {
1977 CopyToExportRegsIfNeeded(&I);
1980 // Update successor info
1981 addSuccessorWithWeight(InvokeMBB, Return);
1982 addSuccessorWithWeight(InvokeMBB, LandingPad);
1984 // Drop into normal successor.
1985 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1986 MVT::Other, getControlRoot(),
1987 DAG.getBasicBlock(Return)));
1990 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1991 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1994 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1995 assert(FuncInfo.MBB->isLandingPad() &&
1996 "Call to landingpad not in landing pad!");
1998 MachineBasicBlock *MBB = FuncInfo.MBB;
1999 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2000 AddLandingPadInfo(LP, MMI, MBB);
2002 // If there aren't registers to copy the values into (e.g., during SjLj
2003 // exceptions), then don't bother to create these DAG nodes.
2004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2005 if (TLI.getExceptionPointerRegister() == 0 &&
2006 TLI.getExceptionSelectorRegister() == 0)
2009 SmallVector<EVT, 2> ValueVTs;
2010 SDLoc dl = getCurSDLoc();
2011 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2012 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2014 // Get the two live-in registers as SDValues. The physregs have already been
2015 // copied into virtual registers.
2017 if (FuncInfo.ExceptionPointerVirtReg) {
2018 Ops[0] = DAG.getZExtOrTrunc(
2019 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2020 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2023 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy());
2025 Ops[1] = DAG.getZExtOrTrunc(
2026 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2027 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2031 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2032 DAG.getVTList(ValueVTs), Ops);
2037 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2038 MachineBasicBlock *LPadBB) {
2039 SDValue Chain = getControlRoot();
2040 SDLoc dl = getCurSDLoc();
2042 // Get the typeid that we will dispatch on later.
2043 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2044 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2045 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2046 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2047 SDValue Sel = DAG.getConstant(TypeID, dl, TLI.getPointerTy());
2048 Chain = DAG.getCopyToReg(Chain, dl, VReg, Sel);
2050 // Branch to the main landing pad block.
2051 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2052 ClauseMBB->addSuccessor(LPadBB);
2053 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, Chain,
2054 DAG.getBasicBlock(LPadBB)));
2058 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2060 for (const CaseCluster &CC : Clusters)
2061 assert(CC.Low == CC.High && "Input clusters must be single-case");
2064 std::sort(Clusters.begin(), Clusters.end(),
2065 [](const CaseCluster &a, const CaseCluster &b) {
2066 return a.Low->getValue().slt(b.Low->getValue());
2069 // Merge adjacent clusters with the same destination.
2070 const unsigned N = Clusters.size();
2071 unsigned DstIndex = 0;
2072 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2073 CaseCluster &CC = Clusters[SrcIndex];
2074 const ConstantInt *CaseVal = CC.Low;
2075 MachineBasicBlock *Succ = CC.MBB;
2077 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2078 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2079 // If this case has the same successor and is a neighbour, merge it into
2080 // the previous cluster.
2081 Clusters[DstIndex - 1].High = CaseVal;
2082 Clusters[DstIndex - 1].Weight += CC.Weight;
2083 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2085 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2086 sizeof(Clusters[SrcIndex]));
2089 Clusters.resize(DstIndex);
2092 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2093 MachineBasicBlock *Last) {
2095 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2096 if (JTCases[i].first.HeaderBB == First)
2097 JTCases[i].first.HeaderBB = Last;
2099 // Update BitTestCases.
2100 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2101 if (BitTestCases[i].Parent == First)
2102 BitTestCases[i].Parent = Last;
2105 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2106 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2108 // Update machine-CFG edges with unique successors.
2109 SmallSet<BasicBlock*, 32> Done;
2110 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2111 BasicBlock *BB = I.getSuccessor(i);
2112 bool Inserted = Done.insert(BB).second;
2116 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2117 addSuccessorWithWeight(IndirectBrMBB, Succ);
2120 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2121 MVT::Other, getControlRoot(),
2122 getValue(I.getAddress())));
2125 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2126 if (DAG.getTarget().Options.TrapUnreachable)
2127 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2130 void SelectionDAGBuilder::visitFSub(const User &I) {
2131 // -0.0 - X --> fneg
2132 Type *Ty = I.getType();
2133 if (isa<Constant>(I.getOperand(0)) &&
2134 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2135 SDValue Op2 = getValue(I.getOperand(1));
2136 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2137 Op2.getValueType(), Op2));
2141 visitBinary(I, ISD::FSUB);
2144 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2145 SDValue Op1 = getValue(I.getOperand(0));
2146 SDValue Op2 = getValue(I.getOperand(1));
2151 if (const OverflowingBinaryOperator *OFBinOp =
2152 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2153 nuw = OFBinOp->hasNoUnsignedWrap();
2154 nsw = OFBinOp->hasNoSignedWrap();
2156 if (const PossiblyExactOperator *ExactOp =
2157 dyn_cast<const PossiblyExactOperator>(&I))
2158 exact = ExactOp->isExact();
2160 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2161 Op1, Op2, nuw, nsw, exact);
2162 setValue(&I, BinNodeValue);
2165 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2166 SDValue Op1 = getValue(I.getOperand(0));
2167 SDValue Op2 = getValue(I.getOperand(1));
2170 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2172 // Coerce the shift amount to the right type if we can.
2173 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2174 unsigned ShiftSize = ShiftTy.getSizeInBits();
2175 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2176 SDLoc DL = getCurSDLoc();
2178 // If the operand is smaller than the shift count type, promote it.
2179 if (ShiftSize > Op2Size)
2180 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2182 // If the operand is larger than the shift count type but the shift
2183 // count type has enough bits to represent any shift value, truncate
2184 // it now. This is a common case and it exposes the truncate to
2185 // optimization early.
2186 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2187 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2188 // Otherwise we'll need to temporarily settle for some other convenient
2189 // type. Type legalization will make adjustments once the shiftee is split.
2191 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2198 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2200 if (const OverflowingBinaryOperator *OFBinOp =
2201 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2202 nuw = OFBinOp->hasNoUnsignedWrap();
2203 nsw = OFBinOp->hasNoSignedWrap();
2205 if (const PossiblyExactOperator *ExactOp =
2206 dyn_cast<const PossiblyExactOperator>(&I))
2207 exact = ExactOp->isExact();
2210 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2215 void SelectionDAGBuilder::visitSDiv(const User &I) {
2216 SDValue Op1 = getValue(I.getOperand(0));
2217 SDValue Op2 = getValue(I.getOperand(1));
2219 // Turn exact SDivs into multiplications.
2220 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2222 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2223 !isa<ConstantSDNode>(Op1) &&
2224 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2225 setValue(&I, DAG.getTargetLoweringInfo()
2226 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2228 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2232 void SelectionDAGBuilder::visitICmp(const User &I) {
2233 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2234 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2235 predicate = IC->getPredicate();
2236 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2237 predicate = ICmpInst::Predicate(IC->getPredicate());
2238 SDValue Op1 = getValue(I.getOperand(0));
2239 SDValue Op2 = getValue(I.getOperand(1));
2240 ISD::CondCode Opcode = getICmpCondCode(predicate);
2242 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2243 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2246 void SelectionDAGBuilder::visitFCmp(const User &I) {
2247 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2248 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2249 predicate = FC->getPredicate();
2250 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2251 predicate = FCmpInst::Predicate(FC->getPredicate());
2252 SDValue Op1 = getValue(I.getOperand(0));
2253 SDValue Op2 = getValue(I.getOperand(1));
2254 ISD::CondCode Condition = getFCmpCondCode(predicate);
2255 if (TM.Options.NoNaNsFPMath)
2256 Condition = getFCmpCodeWithoutNaN(Condition);
2257 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2258 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2261 void SelectionDAGBuilder::visitSelect(const User &I) {
2262 SmallVector<EVT, 4> ValueVTs;
2263 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2264 unsigned NumValues = ValueVTs.size();
2265 if (NumValues == 0) return;
2267 SmallVector<SDValue, 4> Values(NumValues);
2268 SDValue Cond = getValue(I.getOperand(0));
2269 SDValue LHSVal = getValue(I.getOperand(1));
2270 SDValue RHSVal = getValue(I.getOperand(2));
2271 auto BaseOps = {Cond};
2272 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2273 ISD::VSELECT : ISD::SELECT;
2275 // Min/max matching is only viable if all output VTs are the same.
2276 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2278 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2279 ISD::NodeType Opc = ISD::DELETED_NODE;
2281 case SPF_UMAX: Opc = ISD::UMAX; break;
2282 case SPF_UMIN: Opc = ISD::UMIN; break;
2283 case SPF_SMAX: Opc = ISD::SMAX; break;
2284 case SPF_SMIN: Opc = ISD::SMIN; break;
2288 EVT VT = ValueVTs[0];
2289 LLVMContext &Ctx = *DAG.getContext();
2290 auto &TLI = DAG.getTargetLoweringInfo();
2291 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2292 VT = TLI.getTypeToTransformTo(Ctx, VT);
2294 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2295 // If the underlying comparison instruction is used by any other instruction,
2296 // the consumed instructions won't be destroyed, so it is not profitable
2297 // to convert to a min/max.
2298 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2300 LHSVal = getValue(LHS);
2301 RHSVal = getValue(RHS);
2306 for (unsigned i = 0; i != NumValues; ++i) {
2307 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2308 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2309 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2310 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2311 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2315 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2316 DAG.getVTList(ValueVTs), Values));
2319 void SelectionDAGBuilder::visitTrunc(const User &I) {
2320 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2321 SDValue N = getValue(I.getOperand(0));
2322 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2323 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2326 void SelectionDAGBuilder::visitZExt(const User &I) {
2327 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2328 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2329 SDValue N = getValue(I.getOperand(0));
2330 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2331 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2334 void SelectionDAGBuilder::visitSExt(const User &I) {
2335 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2336 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2337 SDValue N = getValue(I.getOperand(0));
2338 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2339 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2342 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2343 // FPTrunc is never a no-op cast, no need to check
2344 SDValue N = getValue(I.getOperand(0));
2345 SDLoc dl = getCurSDLoc();
2346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2347 EVT DestVT = TLI.getValueType(I.getType());
2348 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2349 DAG.getTargetConstant(0, dl, TLI.getPointerTy())));
2352 void SelectionDAGBuilder::visitFPExt(const User &I) {
2353 // FPExt is never a no-op cast, no need to check
2354 SDValue N = getValue(I.getOperand(0));
2355 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2356 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2359 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2360 // FPToUI is never a no-op cast, no need to check
2361 SDValue N = getValue(I.getOperand(0));
2362 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2363 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2366 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2367 // FPToSI is never a no-op cast, no need to check
2368 SDValue N = getValue(I.getOperand(0));
2369 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2370 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2373 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2374 // UIToFP is never a no-op cast, no need to check
2375 SDValue N = getValue(I.getOperand(0));
2376 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2377 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2380 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2381 // SIToFP is never a no-op cast, no need to check
2382 SDValue N = getValue(I.getOperand(0));
2383 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2384 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2387 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2388 // What to do depends on the size of the integer and the size of the pointer.
2389 // We can either truncate, zero extend, or no-op, accordingly.
2390 SDValue N = getValue(I.getOperand(0));
2391 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2392 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2395 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2396 // What to do depends on the size of the integer and the size of the pointer.
2397 // We can either truncate, zero extend, or no-op, accordingly.
2398 SDValue N = getValue(I.getOperand(0));
2399 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2400 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2403 void SelectionDAGBuilder::visitBitCast(const User &I) {
2404 SDValue N = getValue(I.getOperand(0));
2405 SDLoc dl = getCurSDLoc();
2406 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2408 // BitCast assures us that source and destination are the same size so this is
2409 // either a BITCAST or a no-op.
2410 if (DestVT != N.getValueType())
2411 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2412 DestVT, N)); // convert types.
2413 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2414 // might fold any kind of constant expression to an integer constant and that
2415 // is not what we are looking for. Only regcognize a bitcast of a genuine
2416 // constant integer as an opaque constant.
2417 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2418 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2421 setValue(&I, N); // noop cast.
2424 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2426 const Value *SV = I.getOperand(0);
2427 SDValue N = getValue(SV);
2428 EVT DestVT = TLI.getValueType(I.getType());
2430 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2431 unsigned DestAS = I.getType()->getPointerAddressSpace();
2433 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2434 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2439 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2441 SDValue InVec = getValue(I.getOperand(0));
2442 SDValue InVal = getValue(I.getOperand(1));
2443 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2444 getCurSDLoc(), TLI.getVectorIdxTy());
2445 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2446 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2449 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2451 SDValue InVec = getValue(I.getOperand(0));
2452 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2453 getCurSDLoc(), TLI.getVectorIdxTy());
2454 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2455 TLI.getValueType(I.getType()), InVec, InIdx));
2458 // Utility for visitShuffleVector - Return true if every element in Mask,
2459 // beginning from position Pos and ending in Pos+Size, falls within the
2460 // specified sequential range [L, L+Pos). or is undef.
2461 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2462 unsigned Pos, unsigned Size, int Low) {
2463 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2464 if (Mask[i] >= 0 && Mask[i] != Low)
2469 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2470 SDValue Src1 = getValue(I.getOperand(0));
2471 SDValue Src2 = getValue(I.getOperand(1));
2473 SmallVector<int, 8> Mask;
2474 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2475 unsigned MaskNumElts = Mask.size();
2477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2478 EVT VT = TLI.getValueType(I.getType());
2479 EVT SrcVT = Src1.getValueType();
2480 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2482 if (SrcNumElts == MaskNumElts) {
2483 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2488 // Normalize the shuffle vector since mask and vector length don't match.
2489 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2490 // Mask is longer than the source vectors and is a multiple of the source
2491 // vectors. We can use concatenate vector to make the mask and vectors
2493 if (SrcNumElts*2 == MaskNumElts) {
2494 // First check for Src1 in low and Src2 in high
2495 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2496 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2497 // The shuffle is concatenating two vectors together.
2498 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2502 // Then check for Src2 in low and Src1 in high
2503 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2504 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2505 // The shuffle is concatenating two vectors together.
2506 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2512 // Pad both vectors with undefs to make them the same length as the mask.
2513 unsigned NumConcat = MaskNumElts / SrcNumElts;
2514 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2515 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2516 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2518 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2519 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2523 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2524 getCurSDLoc(), VT, MOps1);
2525 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2526 getCurSDLoc(), VT, MOps2);
2528 // Readjust mask for new input vector length.
2529 SmallVector<int, 8> MappedOps;
2530 for (unsigned i = 0; i != MaskNumElts; ++i) {
2532 if (Idx >= (int)SrcNumElts)
2533 Idx -= SrcNumElts - MaskNumElts;
2534 MappedOps.push_back(Idx);
2537 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2542 if (SrcNumElts > MaskNumElts) {
2543 // Analyze the access pattern of the vector to see if we can extract
2544 // two subvectors and do the shuffle. The analysis is done by calculating
2545 // the range of elements the mask access on both vectors.
2546 int MinRange[2] = { static_cast<int>(SrcNumElts),
2547 static_cast<int>(SrcNumElts)};
2548 int MaxRange[2] = {-1, -1};
2550 for (unsigned i = 0; i != MaskNumElts; ++i) {
2556 if (Idx >= (int)SrcNumElts) {
2560 if (Idx > MaxRange[Input])
2561 MaxRange[Input] = Idx;
2562 if (Idx < MinRange[Input])
2563 MinRange[Input] = Idx;
2566 // Check if the access is smaller than the vector size and can we find
2567 // a reasonable extract index.
2568 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2570 int StartIdx[2]; // StartIdx to extract from
2571 for (unsigned Input = 0; Input < 2; ++Input) {
2572 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2573 RangeUse[Input] = 0; // Unused
2574 StartIdx[Input] = 0;
2578 // Find a good start index that is a multiple of the mask length. Then
2579 // see if the rest of the elements are in range.
2580 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2581 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2582 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2583 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2586 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2587 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2590 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2591 // Extract appropriate subvector and generate a vector shuffle
2592 for (unsigned Input = 0; Input < 2; ++Input) {
2593 SDValue &Src = Input == 0 ? Src1 : Src2;
2594 if (RangeUse[Input] == 0)
2595 Src = DAG.getUNDEF(VT);
2597 SDLoc dl = getCurSDLoc();
2599 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2600 DAG.getConstant(StartIdx[Input], dl, TLI.getVectorIdxTy()));
2604 // Calculate new mask.
2605 SmallVector<int, 8> MappedOps;
2606 for (unsigned i = 0; i != MaskNumElts; ++i) {
2609 if (Idx < (int)SrcNumElts)
2612 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2614 MappedOps.push_back(Idx);
2617 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2623 // We can't use either concat vectors or extract subvectors so fall back to
2624 // replacing the shuffle with extract and build vector.
2625 // to insert and build vector.
2626 EVT EltVT = VT.getVectorElementType();
2627 EVT IdxVT = TLI.getVectorIdxTy();
2628 SDLoc dl = getCurSDLoc();
2629 SmallVector<SDValue,8> Ops;
2630 for (unsigned i = 0; i != MaskNumElts; ++i) {
2635 Res = DAG.getUNDEF(EltVT);
2637 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2638 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2640 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2641 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2647 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2650 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2651 const Value *Op0 = I.getOperand(0);
2652 const Value *Op1 = I.getOperand(1);
2653 Type *AggTy = I.getType();
2654 Type *ValTy = Op1->getType();
2655 bool IntoUndef = isa<UndefValue>(Op0);
2656 bool FromUndef = isa<UndefValue>(Op1);
2658 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2661 SmallVector<EVT, 4> AggValueVTs;
2662 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2663 SmallVector<EVT, 4> ValValueVTs;
2664 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2666 unsigned NumAggValues = AggValueVTs.size();
2667 unsigned NumValValues = ValValueVTs.size();
2668 SmallVector<SDValue, 4> Values(NumAggValues);
2670 // Ignore an insertvalue that produces an empty object
2671 if (!NumAggValues) {
2672 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2676 SDValue Agg = getValue(Op0);
2678 // Copy the beginning value(s) from the original aggregate.
2679 for (; i != LinearIndex; ++i)
2680 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2681 SDValue(Agg.getNode(), Agg.getResNo() + i);
2682 // Copy values from the inserted value(s).
2684 SDValue Val = getValue(Op1);
2685 for (; i != LinearIndex + NumValValues; ++i)
2686 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2687 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2689 // Copy remaining value(s) from the original aggregate.
2690 for (; i != NumAggValues; ++i)
2691 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2692 SDValue(Agg.getNode(), Agg.getResNo() + i);
2694 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2695 DAG.getVTList(AggValueVTs), Values));
2698 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2699 const Value *Op0 = I.getOperand(0);
2700 Type *AggTy = Op0->getType();
2701 Type *ValTy = I.getType();
2702 bool OutOfUndef = isa<UndefValue>(Op0);
2704 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2707 SmallVector<EVT, 4> ValValueVTs;
2708 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2710 unsigned NumValValues = ValValueVTs.size();
2712 // Ignore a extractvalue that produces an empty object
2713 if (!NumValValues) {
2714 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2718 SmallVector<SDValue, 4> Values(NumValValues);
2720 SDValue Agg = getValue(Op0);
2721 // Copy out the selected value(s).
2722 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2723 Values[i - LinearIndex] =
2725 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2726 SDValue(Agg.getNode(), Agg.getResNo() + i);
2728 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2729 DAG.getVTList(ValValueVTs), Values));
2732 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2733 Value *Op0 = I.getOperand(0);
2734 // Note that the pointer operand may be a vector of pointers. Take the scalar
2735 // element which holds a pointer.
2736 Type *Ty = Op0->getType()->getScalarType();
2737 unsigned AS = Ty->getPointerAddressSpace();
2738 SDValue N = getValue(Op0);
2739 SDLoc dl = getCurSDLoc();
2741 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2743 const Value *Idx = *OI;
2744 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2745 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2748 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2749 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2750 DAG.getConstant(Offset, dl, N.getValueType()));
2753 Ty = StTy->getElementType(Field);
2755 Ty = cast<SequentialType>(Ty)->getElementType();
2756 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2757 unsigned PtrSize = PtrTy.getSizeInBits();
2758 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2760 // If this is a constant subscript, handle it quickly.
2761 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2764 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2765 SDValue OffsVal = DAG.getConstant(Offs, dl, PtrTy);
2766 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2770 // N = N + Idx * ElementSize;
2771 SDValue IdxN = getValue(Idx);
2773 // If the index is smaller or larger than intptr_t, truncate or extend
2775 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2777 // If this is a multiply by a power of two, turn it into a shl
2778 // immediately. This is a very common case.
2779 if (ElementSize != 1) {
2780 if (ElementSize.isPowerOf2()) {
2781 unsigned Amt = ElementSize.logBase2();
2782 IdxN = DAG.getNode(ISD::SHL, dl,
2783 N.getValueType(), IdxN,
2784 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2786 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2787 IdxN = DAG.getNode(ISD::MUL, dl,
2788 N.getValueType(), IdxN, Scale);
2792 N = DAG.getNode(ISD::ADD, dl,
2793 N.getValueType(), N, IdxN);
2800 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2801 // If this is a fixed sized alloca in the entry block of the function,
2802 // allocate it statically on the stack.
2803 if (FuncInfo.StaticAllocaMap.count(&I))
2804 return; // getValue will auto-populate this.
2806 SDLoc dl = getCurSDLoc();
2807 Type *Ty = I.getAllocatedType();
2808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2809 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2811 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2814 SDValue AllocSize = getValue(I.getArraySize());
2816 EVT IntPtr = TLI.getPointerTy();
2817 if (AllocSize.getValueType() != IntPtr)
2818 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2820 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2822 DAG.getConstant(TySize, dl, IntPtr));
2824 // Handle alignment. If the requested alignment is less than or equal to
2825 // the stack alignment, ignore it. If the size is greater than or equal to
2826 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2827 unsigned StackAlign =
2828 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2829 if (Align <= StackAlign)
2832 // Round the size of the allocation up to the stack alignment size
2833 // by add SA-1 to the size.
2834 AllocSize = DAG.getNode(ISD::ADD, dl,
2835 AllocSize.getValueType(), AllocSize,
2836 DAG.getIntPtrConstant(StackAlign - 1, dl));
2838 // Mask out the low bits for alignment purposes.
2839 AllocSize = DAG.getNode(ISD::AND, dl,
2840 AllocSize.getValueType(), AllocSize,
2841 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2844 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2845 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2846 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2848 DAG.setRoot(DSA.getValue(1));
2850 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2853 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2855 return visitAtomicLoad(I);
2857 const Value *SV = I.getOperand(0);
2858 SDValue Ptr = getValue(SV);
2860 Type *Ty = I.getType();
2862 bool isVolatile = I.isVolatile();
2863 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2865 // The IR notion of invariant_load only guarantees that all *non-faulting*
2866 // invariant loads result in the same value. The MI notion of invariant load
2867 // guarantees that the load can be legally moved to any location within its
2868 // containing function. The MI notion of invariant_load is stronger than the
2869 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2870 // with a guarantee that the location being loaded from is dereferenceable
2871 // throughout the function's lifetime.
2873 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2874 isDereferenceablePointer(SV, *DAG.getTarget().getDataLayout());
2875 unsigned Alignment = I.getAlignment();
2878 I.getAAMetadata(AAInfo);
2879 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2881 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2882 SmallVector<EVT, 4> ValueVTs;
2883 SmallVector<uint64_t, 4> Offsets;
2884 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2885 unsigned NumValues = ValueVTs.size();
2890 bool ConstantMemory = false;
2891 if (isVolatile || NumValues > MaxParallelChains)
2892 // Serialize volatile loads with other side effects.
2894 else if (AA->pointsToConstantMemory(
2895 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2896 // Do not serialize (non-volatile) loads of constant memory with anything.
2897 Root = DAG.getEntryNode();
2898 ConstantMemory = true;
2900 // Do not serialize non-volatile loads against each other.
2901 Root = DAG.getRoot();
2904 SDLoc dl = getCurSDLoc();
2907 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2909 SmallVector<SDValue, 4> Values(NumValues);
2910 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2912 EVT PtrVT = Ptr.getValueType();
2913 unsigned ChainI = 0;
2914 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2915 // Serializing loads here may result in excessive register pressure, and
2916 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2917 // could recover a bit by hoisting nodes upward in the chain by recognizing
2918 // they are side-effect free or do not alias. The optimizer should really
2919 // avoid this case by converting large object/array copies to llvm.memcpy
2920 // (MaxParallelChains should always remain as failsafe).
2921 if (ChainI == MaxParallelChains) {
2922 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2923 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2924 makeArrayRef(Chains.data(), ChainI));
2928 SDValue A = DAG.getNode(ISD::ADD, dl,
2930 DAG.getConstant(Offsets[i], dl, PtrVT));
2931 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2932 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2933 isNonTemporal, isInvariant, Alignment, AAInfo,
2937 Chains[ChainI] = L.getValue(1);
2940 if (!ConstantMemory) {
2941 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2942 makeArrayRef(Chains.data(), ChainI));
2946 PendingLoads.push_back(Chain);
2949 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2950 DAG.getVTList(ValueVTs), Values));
2953 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2955 return visitAtomicStore(I);
2957 const Value *SrcV = I.getOperand(0);
2958 const Value *PtrV = I.getOperand(1);
2960 SmallVector<EVT, 4> ValueVTs;
2961 SmallVector<uint64_t, 4> Offsets;
2962 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2963 ValueVTs, &Offsets);
2964 unsigned NumValues = ValueVTs.size();
2968 // Get the lowered operands. Note that we do this after
2969 // checking if NumResults is zero, because with zero results
2970 // the operands won't have values in the map.
2971 SDValue Src = getValue(SrcV);
2972 SDValue Ptr = getValue(PtrV);
2974 SDValue Root = getRoot();
2975 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2977 EVT PtrVT = Ptr.getValueType();
2978 bool isVolatile = I.isVolatile();
2979 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2980 unsigned Alignment = I.getAlignment();
2981 SDLoc dl = getCurSDLoc();
2984 I.getAAMetadata(AAInfo);
2986 unsigned ChainI = 0;
2987 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2988 // See visitLoad comments.
2989 if (ChainI == MaxParallelChains) {
2990 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2991 makeArrayRef(Chains.data(), ChainI));
2995 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
2996 DAG.getConstant(Offsets[i], dl, PtrVT));
2997 SDValue St = DAG.getStore(Root, dl,
2998 SDValue(Src.getNode(), Src.getResNo() + i),
2999 Add, MachinePointerInfo(PtrV, Offsets[i]),
3000 isVolatile, isNonTemporal, Alignment, AAInfo);
3001 Chains[ChainI] = St;
3004 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3005 makeArrayRef(Chains.data(), ChainI));
3006 DAG.setRoot(StoreNode);
3009 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3010 SDLoc sdl = getCurSDLoc();
3012 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3013 Value *PtrOperand = I.getArgOperand(1);
3014 SDValue Ptr = getValue(PtrOperand);
3015 SDValue Src0 = getValue(I.getArgOperand(0));
3016 SDValue Mask = getValue(I.getArgOperand(3));
3017 EVT VT = Src0.getValueType();
3018 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3020 Alignment = DAG.getEVTAlignment(VT);
3023 I.getAAMetadata(AAInfo);
3025 MachineMemOperand *MMO =
3026 DAG.getMachineFunction().
3027 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3028 MachineMemOperand::MOStore, VT.getStoreSize(),
3030 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3032 DAG.setRoot(StoreNode);
3033 setValue(&I, StoreNode);
3036 // Gather/scatter receive a vector of pointers.
3037 // This vector of pointers may be represented as a base pointer + vector of
3038 // indices, it depends on GEP and instruction preceeding GEP
3039 // that calculates indices
3040 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3041 SelectionDAGBuilder* SDB) {
3043 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3044 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3045 if (!Gep || Gep->getNumOperands() > 2)
3047 ShuffleVectorInst *ShuffleInst =
3048 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3049 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3050 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3051 Instruction::InsertElement)
3054 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3056 SelectionDAG& DAG = SDB->DAG;
3057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3058 // Check is the Ptr is inside current basic block
3059 // If not, look for the shuffle instruction
3060 if (SDB->findValue(Ptr))
3061 Base = SDB->getValue(Ptr);
3062 else if (SDB->findValue(ShuffleInst)) {
3063 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3064 SDLoc sdl = ShuffleNode;
3065 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3066 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3067 DAG.getConstant(0, sdl, TLI.getVectorIdxTy()));
3068 SDB->setValue(Ptr, Base);
3073 Value *IndexVal = Gep->getOperand(1);
3074 if (SDB->findValue(IndexVal)) {
3075 Index = SDB->getValue(IndexVal);
3077 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3078 IndexVal = Sext->getOperand(0);
3079 if (SDB->findValue(IndexVal))
3080 Index = SDB->getValue(IndexVal);
3087 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3088 SDLoc sdl = getCurSDLoc();
3090 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3091 Value *Ptr = I.getArgOperand(1);
3092 SDValue Src0 = getValue(I.getArgOperand(0));
3093 SDValue Mask = getValue(I.getArgOperand(3));
3094 EVT VT = Src0.getValueType();
3095 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3097 Alignment = DAG.getEVTAlignment(VT);
3098 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3101 I.getAAMetadata(AAInfo);
3105 Value *BasePtr = Ptr;
3106 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3108 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3109 MachineMemOperand *MMO = DAG.getMachineFunction().
3110 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3111 MachineMemOperand::MOStore, VT.getStoreSize(),
3114 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3115 Index = getValue(Ptr);
3117 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3118 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3120 DAG.setRoot(Scatter);
3121 setValue(&I, Scatter);
3124 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3125 SDLoc sdl = getCurSDLoc();
3127 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3128 Value *PtrOperand = I.getArgOperand(0);
3129 SDValue Ptr = getValue(PtrOperand);
3130 SDValue Src0 = getValue(I.getArgOperand(3));
3131 SDValue Mask = getValue(I.getArgOperand(2));
3133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3134 EVT VT = TLI.getValueType(I.getType());
3135 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3137 Alignment = DAG.getEVTAlignment(VT);
3140 I.getAAMetadata(AAInfo);
3141 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3143 SDValue InChain = DAG.getRoot();
3144 if (AA->pointsToConstantMemory(
3145 AliasAnalysis::Location(PtrOperand,
3146 AA->getTypeStoreSize(I.getType()),
3148 // Do not serialize (non-volatile) loads of constant memory with anything.
3149 InChain = DAG.getEntryNode();
3152 MachineMemOperand *MMO =
3153 DAG.getMachineFunction().
3154 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3155 MachineMemOperand::MOLoad, VT.getStoreSize(),
3156 Alignment, AAInfo, Ranges);
3158 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3160 SDValue OutChain = Load.getValue(1);
3161 DAG.setRoot(OutChain);
3165 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3166 SDLoc sdl = getCurSDLoc();
3168 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3169 Value *Ptr = I.getArgOperand(0);
3170 SDValue Src0 = getValue(I.getArgOperand(3));
3171 SDValue Mask = getValue(I.getArgOperand(2));
3173 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3174 EVT VT = TLI.getValueType(I.getType());
3175 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3177 Alignment = DAG.getEVTAlignment(VT);
3180 I.getAAMetadata(AAInfo);
3181 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3183 SDValue Root = DAG.getRoot();
3186 Value *BasePtr = Ptr;
3187 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3188 bool ConstantMemory = false;
3189 if (UniformBase && AA->pointsToConstantMemory(
3190 AliasAnalysis::Location(BasePtr,
3191 AA->getTypeStoreSize(I.getType()),
3193 // Do not serialize (non-volatile) loads of constant memory with anything.
3194 Root = DAG.getEntryNode();
3195 ConstantMemory = true;
3198 MachineMemOperand *MMO =
3199 DAG.getMachineFunction().
3200 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3201 MachineMemOperand::MOLoad, VT.getStoreSize(),
3202 Alignment, AAInfo, Ranges);
3205 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3206 Index = getValue(Ptr);
3208 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3209 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3212 SDValue OutChain = Gather.getValue(1);
3213 if (!ConstantMemory)
3214 PendingLoads.push_back(OutChain);
3215 setValue(&I, Gather);
3218 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3219 SDLoc dl = getCurSDLoc();
3220 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3221 AtomicOrdering FailureOrder = I.getFailureOrdering();
3222 SynchronizationScope Scope = I.getSynchScope();
3224 SDValue InChain = getRoot();
3226 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3227 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3228 SDValue L = DAG.getAtomicCmpSwap(
3229 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3230 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3231 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3232 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3234 SDValue OutChain = L.getValue(2);
3237 DAG.setRoot(OutChain);
3240 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3241 SDLoc dl = getCurSDLoc();
3243 switch (I.getOperation()) {
3244 default: llvm_unreachable("Unknown atomicrmw operation");
3245 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3246 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3247 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3248 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3249 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3250 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3251 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3252 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3253 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3254 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3255 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3257 AtomicOrdering Order = I.getOrdering();
3258 SynchronizationScope Scope = I.getSynchScope();
3260 SDValue InChain = getRoot();
3263 DAG.getAtomic(NT, dl,
3264 getValue(I.getValOperand()).getSimpleValueType(),
3266 getValue(I.getPointerOperand()),
3267 getValue(I.getValOperand()),
3268 I.getPointerOperand(),
3269 /* Alignment=*/ 0, Order, Scope);
3271 SDValue OutChain = L.getValue(1);
3274 DAG.setRoot(OutChain);
3277 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3278 SDLoc dl = getCurSDLoc();
3279 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3282 Ops[1] = DAG.getConstant(I.getOrdering(), dl, TLI.getPointerTy());
3283 Ops[2] = DAG.getConstant(I.getSynchScope(), dl, TLI.getPointerTy());
3284 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3287 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3288 SDLoc dl = getCurSDLoc();
3289 AtomicOrdering Order = I.getOrdering();
3290 SynchronizationScope Scope = I.getSynchScope();
3292 SDValue InChain = getRoot();
3294 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3295 EVT VT = TLI.getValueType(I.getType());
3297 if (I.getAlignment() < VT.getSizeInBits() / 8)
3298 report_fatal_error("Cannot generate unaligned atomic load");
3300 MachineMemOperand *MMO =
3301 DAG.getMachineFunction().
3302 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3303 MachineMemOperand::MOVolatile |
3304 MachineMemOperand::MOLoad,
3306 I.getAlignment() ? I.getAlignment() :
3307 DAG.getEVTAlignment(VT));
3309 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3311 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3312 getValue(I.getPointerOperand()), MMO,
3315 SDValue OutChain = L.getValue(1);
3318 DAG.setRoot(OutChain);
3321 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3322 SDLoc dl = getCurSDLoc();
3324 AtomicOrdering Order = I.getOrdering();
3325 SynchronizationScope Scope = I.getSynchScope();
3327 SDValue InChain = getRoot();
3329 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3330 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3332 if (I.getAlignment() < VT.getSizeInBits() / 8)
3333 report_fatal_error("Cannot generate unaligned atomic store");
3336 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3338 getValue(I.getPointerOperand()),
3339 getValue(I.getValueOperand()),
3340 I.getPointerOperand(), I.getAlignment(),
3343 DAG.setRoot(OutChain);
3346 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3348 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3349 unsigned Intrinsic) {
3350 bool HasChain = !I.doesNotAccessMemory();
3351 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3353 // Build the operand list.
3354 SmallVector<SDValue, 8> Ops;
3355 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3357 // We don't need to serialize loads against other loads.
3358 Ops.push_back(DAG.getRoot());
3360 Ops.push_back(getRoot());
3364 // Info is set by getTgtMemInstrinsic
3365 TargetLowering::IntrinsicInfo Info;
3366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3367 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3369 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3370 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3371 Info.opc == ISD::INTRINSIC_W_CHAIN)
3372 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3373 TLI.getPointerTy()));
3375 // Add all operands of the call to the operand list.
3376 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3377 SDValue Op = getValue(I.getArgOperand(i));
3381 SmallVector<EVT, 4> ValueVTs;
3382 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3385 ValueVTs.push_back(MVT::Other);
3387 SDVTList VTs = DAG.getVTList(ValueVTs);
3391 if (IsTgtIntrinsic) {
3392 // This is target intrinsic that touches memory
3393 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3394 VTs, Ops, Info.memVT,
3395 MachinePointerInfo(Info.ptrVal, Info.offset),
3396 Info.align, Info.vol,
3397 Info.readMem, Info.writeMem, Info.size);
3398 } else if (!HasChain) {
3399 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3400 } else if (!I.getType()->isVoidTy()) {
3401 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3403 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3407 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3409 PendingLoads.push_back(Chain);
3414 if (!I.getType()->isVoidTy()) {
3415 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3416 EVT VT = TLI.getValueType(PTy);
3417 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3420 setValue(&I, Result);
3424 /// GetSignificand - Get the significand and build it into a floating-point
3425 /// number with exponent of 1:
3427 /// Op = (Op & 0x007fffff) | 0x3f800000;
3429 /// where Op is the hexadecimal representation of floating point value.
3431 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3432 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3433 DAG.getConstant(0x007fffff, dl, MVT::i32));
3434 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3435 DAG.getConstant(0x3f800000, dl, MVT::i32));
3436 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3439 /// GetExponent - Get the exponent:
3441 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3443 /// where Op is the hexadecimal representation of floating point value.
3445 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3447 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3448 DAG.getConstant(0x7f800000, dl, MVT::i32));
3449 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3450 DAG.getConstant(23, dl, TLI.getPointerTy()));
3451 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3452 DAG.getConstant(127, dl, MVT::i32));
3453 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3456 /// getF32Constant - Get 32-bit floating point constant.
3458 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3459 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3463 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3464 SelectionDAG &DAG) {
3465 // IntegerPartOfX = ((int32_t)(t0);
3466 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3468 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3469 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3470 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3472 // IntegerPartOfX <<= 23;
3473 IntegerPartOfX = DAG.getNode(
3474 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3475 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy()));
3477 SDValue TwoToFractionalPartOfX;
3478 if (LimitFloatPrecision <= 6) {
3479 // For floating-point precision of 6:
3481 // TwoToFractionalPartOfX =
3483 // (0.735607626f + 0.252464424f * x) * x;
3485 // error 0.0144103317, which is 6 bits
3486 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3487 getF32Constant(DAG, 0x3e814304, dl));
3488 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3489 getF32Constant(DAG, 0x3f3c50c8, dl));
3490 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3491 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3492 getF32Constant(DAG, 0x3f7f5e7e, dl));
3493 } else if (LimitFloatPrecision <= 12) {
3494 // For floating-point precision of 12:
3496 // TwoToFractionalPartOfX =
3499 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3501 // error 0.000107046256, which is 13 to 14 bits
3502 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3503 getF32Constant(DAG, 0x3da235e3, dl));
3504 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3505 getF32Constant(DAG, 0x3e65b8f3, dl));
3506 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3507 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3508 getF32Constant(DAG, 0x3f324b07, dl));
3509 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3510 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3511 getF32Constant(DAG, 0x3f7ff8fd, dl));
3512 } else { // LimitFloatPrecision <= 18
3513 // For floating-point precision of 18:
3515 // TwoToFractionalPartOfX =
3519 // (0.554906021e-1f +
3520 // (0.961591928e-2f +
3521 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3522 // error 2.47208000*10^(-7), which is better than 18 bits
3523 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3524 getF32Constant(DAG, 0x3924b03e, dl));
3525 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3526 getF32Constant(DAG, 0x3ab24b87, dl));
3527 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3528 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3529 getF32Constant(DAG, 0x3c1d8c17, dl));
3530 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3531 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3532 getF32Constant(DAG, 0x3d634a1d, dl));
3533 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3534 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3535 getF32Constant(DAG, 0x3e75fe14, dl));
3536 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3537 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3538 getF32Constant(DAG, 0x3f317234, dl));
3539 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3540 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3541 getF32Constant(DAG, 0x3f800000, dl));
3544 // Add the exponent into the result in integer domain.
3545 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3546 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3547 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3550 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3551 /// limited-precision mode.
3552 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3553 const TargetLowering &TLI) {
3554 if (Op.getValueType() == MVT::f32 &&
3555 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3557 // Put the exponent in the right bit position for later addition to the
3560 // #define LOG2OFe 1.4426950f
3561 // t0 = Op * LOG2OFe
3562 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3563 getF32Constant(DAG, 0x3fb8aa3b, dl));
3564 return getLimitedPrecisionExp2(t0, dl, DAG);
3567 // No special expansion.
3568 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3571 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3572 /// limited-precision mode.
3573 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3574 const TargetLowering &TLI) {
3575 if (Op.getValueType() == MVT::f32 &&
3576 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3577 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3579 // Scale the exponent by log(2) [0.69314718f].
3580 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3581 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3582 getF32Constant(DAG, 0x3f317218, dl));
3584 // Get the significand and build it into a floating-point number with
3586 SDValue X = GetSignificand(DAG, Op1, dl);
3588 SDValue LogOfMantissa;
3589 if (LimitFloatPrecision <= 6) {
3590 // For floating-point precision of 6:
3594 // (1.4034025f - 0.23903021f * x) * x;
3596 // error 0.0034276066, which is better than 8 bits
3597 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3598 getF32Constant(DAG, 0xbe74c456, dl));
3599 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3600 getF32Constant(DAG, 0x3fb3a2b1, dl));
3601 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3602 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3603 getF32Constant(DAG, 0x3f949a29, dl));
3604 } else if (LimitFloatPrecision <= 12) {
3605 // For floating-point precision of 12:
3611 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3613 // error 0.000061011436, which is 14 bits
3614 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3615 getF32Constant(DAG, 0xbd67b6d6, dl));
3616 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3617 getF32Constant(DAG, 0x3ee4f4b8, dl));
3618 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3619 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3620 getF32Constant(DAG, 0x3fbc278b, dl));
3621 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3622 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3623 getF32Constant(DAG, 0x40348e95, dl));
3624 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3625 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3626 getF32Constant(DAG, 0x3fdef31a, dl));
3627 } else { // LimitFloatPrecision <= 18
3628 // For floating-point precision of 18:
3636 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3638 // error 0.0000023660568, which is better than 18 bits
3639 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3640 getF32Constant(DAG, 0xbc91e5ac, dl));
3641 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3642 getF32Constant(DAG, 0x3e4350aa, dl));
3643 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3644 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3645 getF32Constant(DAG, 0x3f60d3e3, dl));
3646 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3647 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3648 getF32Constant(DAG, 0x4011cdf0, dl));
3649 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3650 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3651 getF32Constant(DAG, 0x406cfd1c, dl));
3652 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3653 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3654 getF32Constant(DAG, 0x408797cb, dl));
3655 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3656 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3657 getF32Constant(DAG, 0x4006dcab, dl));
3660 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3663 // No special expansion.
3664 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3667 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3668 /// limited-precision mode.
3669 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3670 const TargetLowering &TLI) {
3671 if (Op.getValueType() == MVT::f32 &&
3672 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3673 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3675 // Get the exponent.
3676 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3678 // Get the significand and build it into a floating-point number with
3680 SDValue X = GetSignificand(DAG, Op1, dl);
3682 // Different possible minimax approximations of significand in
3683 // floating-point for various degrees of accuracy over [1,2].
3684 SDValue Log2ofMantissa;
3685 if (LimitFloatPrecision <= 6) {
3686 // For floating-point precision of 6:
3688 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3690 // error 0.0049451742, which is more than 7 bits
3691 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3692 getF32Constant(DAG, 0xbeb08fe0, dl));
3693 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3694 getF32Constant(DAG, 0x40019463, dl));
3695 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3696 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3697 getF32Constant(DAG, 0x3fd6633d, dl));
3698 } else if (LimitFloatPrecision <= 12) {
3699 // For floating-point precision of 12:
3705 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3707 // error 0.0000876136000, which is better than 13 bits
3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3709 getF32Constant(DAG, 0xbda7262e, dl));
3710 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3711 getF32Constant(DAG, 0x3f25280b, dl));
3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3713 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3714 getF32Constant(DAG, 0x4007b923, dl));
3715 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3716 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3717 getF32Constant(DAG, 0x40823e2f, dl));
3718 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3719 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3720 getF32Constant(DAG, 0x4020d29c, dl));
3721 } else { // LimitFloatPrecision <= 18
3722 // For floating-point precision of 18:
3731 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3733 // error 0.0000018516, which is better than 18 bits
3734 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3735 getF32Constant(DAG, 0xbcd2769e, dl));
3736 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3737 getF32Constant(DAG, 0x3e8ce0b9, dl));
3738 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3739 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3740 getF32Constant(DAG, 0x3fa22ae7, dl));
3741 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3742 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3743 getF32Constant(DAG, 0x40525723, dl));
3744 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3745 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3746 getF32Constant(DAG, 0x40aaf200, dl));
3747 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3748 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3749 getF32Constant(DAG, 0x40c39dad, dl));
3750 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3751 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3752 getF32Constant(DAG, 0x4042902c, dl));
3755 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3758 // No special expansion.
3759 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3762 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3763 /// limited-precision mode.
3764 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3765 const TargetLowering &TLI) {
3766 if (Op.getValueType() == MVT::f32 &&
3767 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3768 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3770 // Scale the exponent by log10(2) [0.30102999f].
3771 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3772 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3773 getF32Constant(DAG, 0x3e9a209a, dl));
3775 // Get the significand and build it into a floating-point number with
3777 SDValue X = GetSignificand(DAG, Op1, dl);
3779 SDValue Log10ofMantissa;
3780 if (LimitFloatPrecision <= 6) {
3781 // For floating-point precision of 6:
3783 // Log10ofMantissa =
3785 // (0.60948995f - 0.10380950f * x) * x;
3787 // error 0.0014886165, which is 6 bits
3788 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3789 getF32Constant(DAG, 0xbdd49a13, dl));
3790 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3791 getF32Constant(DAG, 0x3f1c0789, dl));
3792 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3793 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3794 getF32Constant(DAG, 0x3f011300, dl));
3795 } else if (LimitFloatPrecision <= 12) {
3796 // For floating-point precision of 12:
3798 // Log10ofMantissa =
3801 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3803 // error 0.00019228036, which is better than 12 bits
3804 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3805 getF32Constant(DAG, 0x3d431f31, dl));
3806 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3807 getF32Constant(DAG, 0x3ea21fb2, dl));
3808 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3809 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3810 getF32Constant(DAG, 0x3f6ae232, dl));
3811 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3812 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3813 getF32Constant(DAG, 0x3f25f7c3, dl));
3814 } else { // LimitFloatPrecision <= 18
3815 // For floating-point precision of 18:
3817 // Log10ofMantissa =
3822 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3824 // error 0.0000037995730, which is better than 18 bits
3825 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3826 getF32Constant(DAG, 0x3c5d51ce, dl));
3827 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3828 getF32Constant(DAG, 0x3e00685a, dl));
3829 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3830 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3831 getF32Constant(DAG, 0x3efb6798, dl));
3832 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3833 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3834 getF32Constant(DAG, 0x3f88d192, dl));
3835 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3836 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3837 getF32Constant(DAG, 0x3fc4316c, dl));
3838 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3839 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3840 getF32Constant(DAG, 0x3f57ce70, dl));
3843 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3846 // No special expansion.
3847 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3850 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3851 /// limited-precision mode.
3852 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3853 const TargetLowering &TLI) {
3854 if (Op.getValueType() == MVT::f32 &&
3855 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3856 return getLimitedPrecisionExp2(Op, dl, DAG);
3858 // No special expansion.
3859 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3862 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3863 /// limited-precision mode with x == 10.0f.
3864 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3865 SelectionDAG &DAG, const TargetLowering &TLI) {
3866 bool IsExp10 = false;
3867 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3868 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3869 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3871 IsExp10 = LHSC->isExactlyValue(Ten);
3876 // Put the exponent in the right bit position for later addition to the
3879 // #define LOG2OF10 3.3219281f
3880 // t0 = Op * LOG2OF10;
3881 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3882 getF32Constant(DAG, 0x40549a78, dl));
3883 return getLimitedPrecisionExp2(t0, dl, DAG);
3886 // No special expansion.
3887 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3891 /// ExpandPowI - Expand a llvm.powi intrinsic.
3892 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3893 SelectionDAG &DAG) {
3894 // If RHS is a constant, we can expand this out to a multiplication tree,
3895 // otherwise we end up lowering to a call to __powidf2 (for example). When
3896 // optimizing for size, we only want to do this if the expansion would produce
3897 // a small number of multiplies, otherwise we do the full expansion.
3898 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3899 // Get the exponent as a positive value.
3900 unsigned Val = RHSC->getSExtValue();
3901 if ((int)Val < 0) Val = -Val;
3903 // powi(x, 0) -> 1.0
3905 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3907 const Function *F = DAG.getMachineFunction().getFunction();
3908 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3909 // If optimizing for size, don't insert too many multiplies. This
3910 // inserts up to 5 multiplies.
3911 countPopulation(Val) + Log2_32(Val) < 7) {
3912 // We use the simple binary decomposition method to generate the multiply
3913 // sequence. There are more optimal ways to do this (for example,
3914 // powi(x,15) generates one more multiply than it should), but this has
3915 // the benefit of being both really simple and much better than a libcall.
3916 SDValue Res; // Logically starts equal to 1.0
3917 SDValue CurSquare = LHS;
3921 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3923 Res = CurSquare; // 1.0*CurSquare.
3926 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3927 CurSquare, CurSquare);
3931 // If the original was negative, invert the result, producing 1/(x*x*x).
3932 if (RHSC->getSExtValue() < 0)
3933 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3934 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3939 // Otherwise, expand to a libcall.
3940 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3943 // getTruncatedArgReg - Find underlying register used for an truncated
3945 static unsigned getTruncatedArgReg(const SDValue &N) {
3946 if (N.getOpcode() != ISD::TRUNCATE)
3949 const SDValue &Ext = N.getOperand(0);
3950 if (Ext.getOpcode() == ISD::AssertZext ||
3951 Ext.getOpcode() == ISD::AssertSext) {
3952 const SDValue &CFR = Ext.getOperand(0);
3953 if (CFR.getOpcode() == ISD::CopyFromReg)
3954 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3955 if (CFR.getOpcode() == ISD::TRUNCATE)
3956 return getTruncatedArgReg(CFR);
3961 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3962 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3963 /// At the end of instruction selection, they will be inserted to the entry BB.
3964 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3965 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
3966 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3967 const Argument *Arg = dyn_cast<Argument>(V);
3971 MachineFunction &MF = DAG.getMachineFunction();
3972 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3974 // Ignore inlined function arguments here.
3976 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3977 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
3980 Optional<MachineOperand> Op;
3981 // Some arguments' frame index is recorded during argument lowering.
3982 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
3983 Op = MachineOperand::CreateFI(FI);
3985 if (!Op && N.getNode()) {
3987 if (N.getOpcode() == ISD::CopyFromReg)
3988 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3990 Reg = getTruncatedArgReg(N);
3991 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3992 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3993 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3998 Op = MachineOperand::CreateReg(Reg, false);
4002 // Check if ValueMap has reg number.
4003 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4004 if (VMI != FuncInfo.ValueMap.end())
4005 Op = MachineOperand::CreateReg(VMI->second, false);
4008 if (!Op && N.getNode())
4009 // Check if frame index is available.
4010 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4011 if (FrameIndexSDNode *FINode =
4012 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4013 Op = MachineOperand::CreateFI(FINode->getIndex());
4018 assert(Variable->isValidLocationForIntrinsic(DL) &&
4019 "Expected inlined-at fields to agree");
4021 FuncInfo.ArgDbgValues.push_back(
4022 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4023 Op->getReg(), Offset, Variable, Expr));
4025 FuncInfo.ArgDbgValues.push_back(
4026 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4029 .addMetadata(Variable)
4030 .addMetadata(Expr));
4035 // VisualStudio defines setjmp as _setjmp
4036 #if defined(_MSC_VER) && defined(setjmp) && \
4037 !defined(setjmp_undefined_for_msvc)
4038 # pragma push_macro("setjmp")
4040 # define setjmp_undefined_for_msvc
4043 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4044 /// we want to emit this as a call to a named external function, return the name
4045 /// otherwise lower it and return null.
4047 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4049 SDLoc sdl = getCurSDLoc();
4050 DebugLoc dl = getCurDebugLoc();
4053 switch (Intrinsic) {
4055 // By default, turn this into a target intrinsic node.
4056 visitTargetIntrinsic(I, Intrinsic);
4058 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4059 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4060 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4061 case Intrinsic::returnaddress:
4062 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4063 getValue(I.getArgOperand(0))));
4065 case Intrinsic::frameaddress:
4066 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4067 getValue(I.getArgOperand(0))));
4069 case Intrinsic::read_register: {
4070 Value *Reg = I.getArgOperand(0);
4071 SDValue Chain = getRoot();
4073 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4074 EVT VT = TLI.getValueType(I.getType());
4075 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4076 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4078 DAG.setRoot(Res.getValue(1));
4081 case Intrinsic::write_register: {
4082 Value *Reg = I.getArgOperand(0);
4083 Value *RegValue = I.getArgOperand(1);
4084 SDValue Chain = getRoot();
4086 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4087 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4088 RegName, getValue(RegValue)));
4091 case Intrinsic::setjmp:
4092 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4093 case Intrinsic::longjmp:
4094 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4095 case Intrinsic::memcpy: {
4096 // FIXME: this definition of "user defined address space" is x86-specific
4097 // Assert for address < 256 since we support only user defined address
4099 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4101 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4103 "Unknown address space");
4104 SDValue Op1 = getValue(I.getArgOperand(0));
4105 SDValue Op2 = getValue(I.getArgOperand(1));
4106 SDValue Op3 = getValue(I.getArgOperand(2));
4107 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4109 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4110 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4111 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4112 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4114 MachinePointerInfo(I.getArgOperand(0)),
4115 MachinePointerInfo(I.getArgOperand(1)));
4116 updateDAGForMaybeTailCall(MC);
4119 case Intrinsic::memset: {
4120 // FIXME: this definition of "user defined address space" is x86-specific
4121 // Assert for address < 256 since we support only user defined address
4123 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4125 "Unknown address space");
4126 SDValue Op1 = getValue(I.getArgOperand(0));
4127 SDValue Op2 = getValue(I.getArgOperand(1));
4128 SDValue Op3 = getValue(I.getArgOperand(2));
4129 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4131 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4132 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4133 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4134 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4135 isTC, MachinePointerInfo(I.getArgOperand(0)));
4136 updateDAGForMaybeTailCall(MS);
4139 case Intrinsic::memmove: {
4140 // FIXME: this definition of "user defined address space" is x86-specific
4141 // Assert for address < 256 since we support only user defined address
4143 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4145 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4147 "Unknown address space");
4148 SDValue Op1 = getValue(I.getArgOperand(0));
4149 SDValue Op2 = getValue(I.getArgOperand(1));
4150 SDValue Op3 = getValue(I.getArgOperand(2));
4151 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4153 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4154 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4155 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4156 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4157 isTC, MachinePointerInfo(I.getArgOperand(0)),
4158 MachinePointerInfo(I.getArgOperand(1)));
4159 updateDAGForMaybeTailCall(MM);
4162 case Intrinsic::dbg_declare: {
4163 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4164 DILocalVariable *Variable = DI.getVariable();
4165 DIExpression *Expression = DI.getExpression();
4166 const Value *Address = DI.getAddress();
4167 assert(Variable && "Missing variable");
4169 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4173 // Check if address has undef value.
4174 if (isa<UndefValue>(Address) ||
4175 (Address->use_empty() && !isa<Argument>(Address))) {
4176 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4180 SDValue &N = NodeMap[Address];
4181 if (!N.getNode() && isa<Argument>(Address))
4182 // Check unused arguments map.
4183 N = UnusedArgNodeMap[Address];
4186 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4187 Address = BCI->getOperand(0);
4188 // Parameters are handled specially.
4189 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4190 isa<Argument>(Address);
4192 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4194 if (isParameter && !AI) {
4195 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4197 // Byval parameter. We have a frame index at this point.
4198 SDV = DAG.getFrameIndexDbgValue(
4199 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4201 // Address is an argument, so try to emit its dbg value using
4202 // virtual register info from the FuncInfo.ValueMap.
4203 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4208 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4209 true, 0, dl, SDNodeOrder);
4211 // Can't do anything with other non-AI cases yet.
4212 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4213 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4214 DEBUG(Address->dump());
4217 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4219 // If Address is an argument then try to emit its dbg value using
4220 // virtual register info from the FuncInfo.ValueMap.
4221 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4223 // If variable is pinned by a alloca in dominating bb then
4224 // use StaticAllocaMap.
4225 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4226 if (AI->getParent() != DI.getParent()) {
4227 DenseMap<const AllocaInst*, int>::iterator SI =
4228 FuncInfo.StaticAllocaMap.find(AI);
4229 if (SI != FuncInfo.StaticAllocaMap.end()) {
4230 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4231 0, dl, SDNodeOrder);
4232 DAG.AddDbgValue(SDV, nullptr, false);
4237 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4242 case Intrinsic::dbg_value: {
4243 const DbgValueInst &DI = cast<DbgValueInst>(I);
4244 assert(DI.getVariable() && "Missing variable");
4246 DILocalVariable *Variable = DI.getVariable();
4247 DIExpression *Expression = DI.getExpression();
4248 uint64_t Offset = DI.getOffset();
4249 const Value *V = DI.getValue();
4254 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4255 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4257 DAG.AddDbgValue(SDV, nullptr, false);
4259 // Do not use getValue() in here; we don't want to generate code at
4260 // this point if it hasn't been done yet.
4261 SDValue N = NodeMap[V];
4262 if (!N.getNode() && isa<Argument>(V))
4263 // Check unused arguments map.
4264 N = UnusedArgNodeMap[V];
4266 // A dbg.value for an alloca is always indirect.
4267 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4268 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4270 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4271 IsIndirect, Offset, dl, SDNodeOrder);
4272 DAG.AddDbgValue(SDV, N.getNode(), false);
4274 } else if (!V->use_empty() ) {
4275 // Do not call getValue(V) yet, as we don't want to generate code.
4276 // Remember it for later.
4277 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4278 DanglingDebugInfoMap[V] = DDI;
4280 // We may expand this to cover more cases. One case where we have no
4281 // data available is an unreferenced parameter.
4282 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4286 // Build a debug info table entry.
4287 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4288 V = BCI->getOperand(0);
4289 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4290 // Don't handle byval struct arguments or VLAs, for example.
4292 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4293 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4296 DenseMap<const AllocaInst*, int>::iterator SI =
4297 FuncInfo.StaticAllocaMap.find(AI);
4298 if (SI == FuncInfo.StaticAllocaMap.end())
4299 return nullptr; // VLAs.
4303 case Intrinsic::eh_typeid_for: {
4304 // Find the type id for the given typeinfo.
4305 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4306 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4307 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4312 case Intrinsic::eh_return_i32:
4313 case Intrinsic::eh_return_i64:
4314 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4315 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4318 getValue(I.getArgOperand(0)),
4319 getValue(I.getArgOperand(1))));
4321 case Intrinsic::eh_unwind_init:
4322 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4324 case Intrinsic::eh_dwarf_cfa: {
4325 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4326 TLI.getPointerTy());
4327 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4328 CfaArg.getValueType(),
4329 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4330 CfaArg.getValueType()),
4332 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4333 DAG.getConstant(0, sdl, TLI.getPointerTy()));
4334 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4338 case Intrinsic::eh_sjlj_callsite: {
4339 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4340 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4341 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4342 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4344 MMI.setCurrentCallSite(CI->getZExtValue());
4347 case Intrinsic::eh_sjlj_functioncontext: {
4348 // Get and store the index of the function context.
4349 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4351 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4352 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4353 MFI->setFunctionContextIndex(FI);
4356 case Intrinsic::eh_sjlj_setjmp: {
4359 Ops[1] = getValue(I.getArgOperand(0));
4360 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4361 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4362 setValue(&I, Op.getValue(0));
4363 DAG.setRoot(Op.getValue(1));
4366 case Intrinsic::eh_sjlj_longjmp: {
4367 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4368 getRoot(), getValue(I.getArgOperand(0))));
4372 case Intrinsic::masked_gather:
4373 visitMaskedGather(I);
4375 case Intrinsic::masked_load:
4378 case Intrinsic::masked_scatter:
4379 visitMaskedScatter(I);
4381 case Intrinsic::masked_store:
4382 visitMaskedStore(I);
4384 case Intrinsic::x86_mmx_pslli_w:
4385 case Intrinsic::x86_mmx_pslli_d:
4386 case Intrinsic::x86_mmx_pslli_q:
4387 case Intrinsic::x86_mmx_psrli_w:
4388 case Intrinsic::x86_mmx_psrli_d:
4389 case Intrinsic::x86_mmx_psrli_q:
4390 case Intrinsic::x86_mmx_psrai_w:
4391 case Intrinsic::x86_mmx_psrai_d: {
4392 SDValue ShAmt = getValue(I.getArgOperand(1));
4393 if (isa<ConstantSDNode>(ShAmt)) {
4394 visitTargetIntrinsic(I, Intrinsic);
4397 unsigned NewIntrinsic = 0;
4398 EVT ShAmtVT = MVT::v2i32;
4399 switch (Intrinsic) {
4400 case Intrinsic::x86_mmx_pslli_w:
4401 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4403 case Intrinsic::x86_mmx_pslli_d:
4404 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4406 case Intrinsic::x86_mmx_pslli_q:
4407 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4409 case Intrinsic::x86_mmx_psrli_w:
4410 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4412 case Intrinsic::x86_mmx_psrli_d:
4413 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4415 case Intrinsic::x86_mmx_psrli_q:
4416 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4418 case Intrinsic::x86_mmx_psrai_w:
4419 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4421 case Intrinsic::x86_mmx_psrai_d:
4422 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4424 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4427 // The vector shift intrinsics with scalars uses 32b shift amounts but
4428 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4430 // We must do this early because v2i32 is not a legal type.
4433 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4434 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4435 EVT DestVT = TLI.getValueType(I.getType());
4436 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4437 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4438 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4439 getValue(I.getArgOperand(0)), ShAmt);
4443 case Intrinsic::convertff:
4444 case Intrinsic::convertfsi:
4445 case Intrinsic::convertfui:
4446 case Intrinsic::convertsif:
4447 case Intrinsic::convertuif:
4448 case Intrinsic::convertss:
4449 case Intrinsic::convertsu:
4450 case Intrinsic::convertus:
4451 case Intrinsic::convertuu: {
4452 ISD::CvtCode Code = ISD::CVT_INVALID;
4453 switch (Intrinsic) {
4454 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4455 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4456 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4457 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4458 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4459 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4460 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4461 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4462 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4463 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4465 EVT DestVT = TLI.getValueType(I.getType());
4466 const Value *Op1 = I.getArgOperand(0);
4467 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4468 DAG.getValueType(DestVT),
4469 DAG.getValueType(getValue(Op1).getValueType()),
4470 getValue(I.getArgOperand(1)),
4471 getValue(I.getArgOperand(2)),
4476 case Intrinsic::powi:
4477 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4478 getValue(I.getArgOperand(1)), DAG));
4480 case Intrinsic::log:
4481 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4483 case Intrinsic::log2:
4484 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4486 case Intrinsic::log10:
4487 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4489 case Intrinsic::exp:
4490 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4492 case Intrinsic::exp2:
4493 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4495 case Intrinsic::pow:
4496 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4497 getValue(I.getArgOperand(1)), DAG, TLI));
4499 case Intrinsic::sqrt:
4500 case Intrinsic::fabs:
4501 case Intrinsic::sin:
4502 case Intrinsic::cos:
4503 case Intrinsic::floor:
4504 case Intrinsic::ceil:
4505 case Intrinsic::trunc:
4506 case Intrinsic::rint:
4507 case Intrinsic::nearbyint:
4508 case Intrinsic::round: {
4510 switch (Intrinsic) {
4511 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4512 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4513 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4514 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4515 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4516 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4517 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4518 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4519 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4520 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4521 case Intrinsic::round: Opcode = ISD::FROUND; break;
4524 setValue(&I, DAG.getNode(Opcode, sdl,
4525 getValue(I.getArgOperand(0)).getValueType(),
4526 getValue(I.getArgOperand(0))));
4529 case Intrinsic::minnum:
4530 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4531 getValue(I.getArgOperand(0)).getValueType(),
4532 getValue(I.getArgOperand(0)),
4533 getValue(I.getArgOperand(1))));
4535 case Intrinsic::maxnum:
4536 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4537 getValue(I.getArgOperand(0)).getValueType(),
4538 getValue(I.getArgOperand(0)),
4539 getValue(I.getArgOperand(1))));
4541 case Intrinsic::copysign:
4542 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4543 getValue(I.getArgOperand(0)).getValueType(),
4544 getValue(I.getArgOperand(0)),
4545 getValue(I.getArgOperand(1))));
4547 case Intrinsic::fma:
4548 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4549 getValue(I.getArgOperand(0)).getValueType(),
4550 getValue(I.getArgOperand(0)),
4551 getValue(I.getArgOperand(1)),
4552 getValue(I.getArgOperand(2))));
4554 case Intrinsic::fmuladd: {
4555 EVT VT = TLI.getValueType(I.getType());
4556 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4557 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4558 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4559 getValue(I.getArgOperand(0)).getValueType(),
4560 getValue(I.getArgOperand(0)),
4561 getValue(I.getArgOperand(1)),
4562 getValue(I.getArgOperand(2))));
4564 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4565 getValue(I.getArgOperand(0)).getValueType(),
4566 getValue(I.getArgOperand(0)),
4567 getValue(I.getArgOperand(1)));
4568 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4569 getValue(I.getArgOperand(0)).getValueType(),
4571 getValue(I.getArgOperand(2)));
4576 case Intrinsic::convert_to_fp16:
4577 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4578 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4579 getValue(I.getArgOperand(0)),
4580 DAG.getTargetConstant(0, sdl,
4583 case Intrinsic::convert_from_fp16:
4585 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4586 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4587 getValue(I.getArgOperand(0)))));
4589 case Intrinsic::pcmarker: {
4590 SDValue Tmp = getValue(I.getArgOperand(0));
4591 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4594 case Intrinsic::readcyclecounter: {
4595 SDValue Op = getRoot();
4596 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4597 DAG.getVTList(MVT::i64, MVT::Other), Op);
4599 DAG.setRoot(Res.getValue(1));
4602 case Intrinsic::bswap:
4603 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4604 getValue(I.getArgOperand(0)).getValueType(),
4605 getValue(I.getArgOperand(0))));
4607 case Intrinsic::cttz: {
4608 SDValue Arg = getValue(I.getArgOperand(0));
4609 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4610 EVT Ty = Arg.getValueType();
4611 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4615 case Intrinsic::ctlz: {
4616 SDValue Arg = getValue(I.getArgOperand(0));
4617 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4618 EVT Ty = Arg.getValueType();
4619 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4623 case Intrinsic::ctpop: {
4624 SDValue Arg = getValue(I.getArgOperand(0));
4625 EVT Ty = Arg.getValueType();
4626 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4629 case Intrinsic::stacksave: {
4630 SDValue Op = getRoot();
4631 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4632 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4634 DAG.setRoot(Res.getValue(1));
4637 case Intrinsic::stackrestore: {
4638 Res = getValue(I.getArgOperand(0));
4639 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4642 case Intrinsic::stackprotector: {
4643 // Emit code into the DAG to store the stack guard onto the stack.
4644 MachineFunction &MF = DAG.getMachineFunction();
4645 MachineFrameInfo *MFI = MF.getFrameInfo();
4646 EVT PtrTy = TLI.getPointerTy();
4647 SDValue Src, Chain = getRoot();
4648 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4649 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4651 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4652 // global variable __stack_chk_guard.
4654 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4655 if (BC->getOpcode() == Instruction::BitCast)
4656 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4658 if (GV && TLI.useLoadStackGuardNode()) {
4659 // Emit a LOAD_STACK_GUARD node.
4660 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4662 MachinePointerInfo MPInfo(GV);
4663 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4664 unsigned Flags = MachineMemOperand::MOLoad |
4665 MachineMemOperand::MOInvariant;
4666 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4667 PtrTy.getSizeInBits() / 8,
4668 DAG.getEVTAlignment(PtrTy));
4669 Node->setMemRefs(MemRefs, MemRefs + 1);
4671 // Copy the guard value to a virtual register so that it can be
4672 // retrieved in the epilogue.
4673 Src = SDValue(Node, 0);
4674 const TargetRegisterClass *RC =
4675 TLI.getRegClassFor(Src.getSimpleValueType());
4676 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4678 SPDescriptor.setGuardReg(Reg);
4679 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4681 Src = getValue(I.getArgOperand(0)); // The guard's value.
4684 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4686 int FI = FuncInfo.StaticAllocaMap[Slot];
4687 MFI->setStackProtectorIndex(FI);
4689 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4691 // Store the stack protector onto the stack.
4692 Res = DAG.getStore(Chain, sdl, Src, FIN,
4693 MachinePointerInfo::getFixedStack(FI),
4699 case Intrinsic::objectsize: {
4700 // If we don't know by now, we're never going to know.
4701 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4703 assert(CI && "Non-constant type in __builtin_object_size?");
4705 SDValue Arg = getValue(I.getCalledValue());
4706 EVT Ty = Arg.getValueType();
4709 Res = DAG.getConstant(-1ULL, sdl, Ty);
4711 Res = DAG.getConstant(0, sdl, Ty);
4716 case Intrinsic::annotation:
4717 case Intrinsic::ptr_annotation:
4718 // Drop the intrinsic, but forward the value
4719 setValue(&I, getValue(I.getOperand(0)));
4721 case Intrinsic::assume:
4722 case Intrinsic::var_annotation:
4723 // Discard annotate attributes and assumptions
4726 case Intrinsic::init_trampoline: {
4727 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4731 Ops[1] = getValue(I.getArgOperand(0));
4732 Ops[2] = getValue(I.getArgOperand(1));
4733 Ops[3] = getValue(I.getArgOperand(2));
4734 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4735 Ops[5] = DAG.getSrcValue(F);
4737 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4742 case Intrinsic::adjust_trampoline: {
4743 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4745 getValue(I.getArgOperand(0))));
4748 case Intrinsic::gcroot:
4750 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4751 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4753 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4754 GFI->addStackRoot(FI->getIndex(), TypeMap);
4757 case Intrinsic::gcread:
4758 case Intrinsic::gcwrite:
4759 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4760 case Intrinsic::flt_rounds:
4761 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4764 case Intrinsic::expect: {
4765 // Just replace __builtin_expect(exp, c) with EXP.
4766 setValue(&I, getValue(I.getArgOperand(0)));
4770 case Intrinsic::debugtrap:
4771 case Intrinsic::trap: {
4772 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4773 if (TrapFuncName.empty()) {
4774 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4775 ISD::TRAP : ISD::DEBUGTRAP;
4776 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4779 TargetLowering::ArgListTy Args;
4781 TargetLowering::CallLoweringInfo CLI(DAG);
4782 CLI.setDebugLoc(sdl).setChain(getRoot())
4783 .setCallee(CallingConv::C, I.getType(),
4784 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4785 std::move(Args), 0);
4787 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4788 DAG.setRoot(Result.second);
4792 case Intrinsic::uadd_with_overflow:
4793 case Intrinsic::sadd_with_overflow:
4794 case Intrinsic::usub_with_overflow:
4795 case Intrinsic::ssub_with_overflow:
4796 case Intrinsic::umul_with_overflow:
4797 case Intrinsic::smul_with_overflow: {
4799 switch (Intrinsic) {
4800 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4801 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4802 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4803 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4804 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4805 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4806 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4808 SDValue Op1 = getValue(I.getArgOperand(0));
4809 SDValue Op2 = getValue(I.getArgOperand(1));
4811 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4812 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4815 case Intrinsic::prefetch: {
4817 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4819 Ops[1] = getValue(I.getArgOperand(0));
4820 Ops[2] = getValue(I.getArgOperand(1));
4821 Ops[3] = getValue(I.getArgOperand(2));
4822 Ops[4] = getValue(I.getArgOperand(3));
4823 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4824 DAG.getVTList(MVT::Other), Ops,
4825 EVT::getIntegerVT(*Context, 8),
4826 MachinePointerInfo(I.getArgOperand(0)),
4828 false, /* volatile */
4830 rw==1)); /* write */
4833 case Intrinsic::lifetime_start:
4834 case Intrinsic::lifetime_end: {
4835 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4836 // Stack coloring is not enabled in O0, discard region information.
4837 if (TM.getOptLevel() == CodeGenOpt::None)
4840 SmallVector<Value *, 4> Allocas;
4841 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4843 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4844 E = Allocas.end(); Object != E; ++Object) {
4845 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4847 // Could not find an Alloca.
4848 if (!LifetimeObject)
4851 // First check that the Alloca is static, otherwise it won't have a
4852 // valid frame index.
4853 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4854 if (SI == FuncInfo.StaticAllocaMap.end())
4857 int FI = SI->second;
4861 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4862 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4864 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4869 case Intrinsic::invariant_start:
4870 // Discard region information.
4871 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4873 case Intrinsic::invariant_end:
4874 // Discard region information.
4876 case Intrinsic::stackprotectorcheck: {
4877 // Do not actually emit anything for this basic block. Instead we initialize
4878 // the stack protector descriptor and export the guard variable so we can
4879 // access it in FinishBasicBlock.
4880 const BasicBlock *BB = I.getParent();
4881 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4882 ExportFromCurrentBlock(SPDescriptor.getGuard());
4884 // Flush our exports since we are going to process a terminator.
4885 (void)getControlRoot();
4888 case Intrinsic::clear_cache:
4889 return TLI.getClearCacheBuiltinName();
4890 case Intrinsic::eh_actions:
4891 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4893 case Intrinsic::donothing:
4896 case Intrinsic::experimental_stackmap: {
4900 case Intrinsic::experimental_patchpoint_void:
4901 case Intrinsic::experimental_patchpoint_i64: {
4902 visitPatchpoint(&I);
4905 case Intrinsic::experimental_gc_statepoint: {
4909 case Intrinsic::experimental_gc_result_int:
4910 case Intrinsic::experimental_gc_result_float:
4911 case Intrinsic::experimental_gc_result_ptr:
4912 case Intrinsic::experimental_gc_result: {
4916 case Intrinsic::experimental_gc_relocate: {
4920 case Intrinsic::instrprof_increment:
4921 llvm_unreachable("instrprof failed to lower an increment");
4923 case Intrinsic::frameescape: {
4924 MachineFunction &MF = DAG.getMachineFunction();
4925 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4927 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4928 // is the same on all targets.
4929 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4930 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4931 if (isa<ConstantPointerNull>(Arg))
4932 continue; // Skip null pointers. They represent a hole in index space.
4933 AllocaInst *Slot = cast<AllocaInst>(Arg);
4934 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4935 "can only escape static allocas");
4936 int FI = FuncInfo.StaticAllocaMap[Slot];
4937 MCSymbol *FrameAllocSym =
4938 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4939 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4940 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4941 TII->get(TargetOpcode::FRAME_ALLOC))
4942 .addSym(FrameAllocSym)
4949 case Intrinsic::framerecover: {
4950 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4951 MachineFunction &MF = DAG.getMachineFunction();
4952 MVT PtrVT = TLI.getPointerTy(0);
4954 // Get the symbol that defines the frame offset.
4955 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4956 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4957 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4958 MCSymbol *FrameAllocSym =
4959 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4960 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4962 // Create a TargetExternalSymbol for the label to avoid any target lowering
4963 // that would make this PC relative.
4964 StringRef Name = FrameAllocSym->getName();
4965 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4966 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4968 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4970 // Add the offset to the FP.
4971 Value *FP = I.getArgOperand(1);
4972 SDValue FPVal = getValue(FP);
4973 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4978 case Intrinsic::eh_begincatch:
4979 case Intrinsic::eh_endcatch:
4980 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4981 case Intrinsic::eh_exceptioncode: {
4982 unsigned Reg = TLI.getExceptionPointerRegister();
4983 assert(Reg && "cannot get exception code on this platform");
4984 MVT PtrVT = TLI.getPointerTy();
4985 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
4986 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
4987 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
4989 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
4990 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
4997 std::pair<SDValue, SDValue>
4998 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
4999 MachineBasicBlock *LandingPad) {
5000 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5001 MCSymbol *BeginLabel = nullptr;
5004 // Insert a label before the invoke call to mark the try range. This can be
5005 // used to detect deletion of the invoke via the MachineModuleInfo.
5006 BeginLabel = MMI.getContext().createTempSymbol();
5008 // For SjLj, keep track of which landing pads go with which invokes
5009 // so as to maintain the ordering of pads in the LSDA.
5010 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5011 if (CallSiteIndex) {
5012 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5013 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5015 // Now that the call site is handled, stop tracking it.
5016 MMI.setCurrentCallSite(0);
5019 // Both PendingLoads and PendingExports must be flushed here;
5020 // this call might not return.
5022 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5024 CLI.setChain(getRoot());
5026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5027 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5029 assert((CLI.IsTailCall || Result.second.getNode()) &&
5030 "Non-null chain expected with non-tail call!");
5031 assert((Result.second.getNode() || !Result.first.getNode()) &&
5032 "Null value expected with tail call!");
5034 if (!Result.second.getNode()) {
5035 // As a special case, a null chain means that a tail call has been emitted
5036 // and the DAG root is already updated.
5039 // Since there's no actual continuation from this block, nothing can be
5040 // relying on us setting vregs for them.
5041 PendingExports.clear();
5043 DAG.setRoot(Result.second);
5047 // Insert a label at the end of the invoke call to mark the try range. This
5048 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5049 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5050 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5052 // Inform MachineModuleInfo of range.
5053 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5059 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5061 MachineBasicBlock *LandingPad) {
5062 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5063 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5064 Type *RetTy = FTy->getReturnType();
5066 TargetLowering::ArgListTy Args;
5067 TargetLowering::ArgListEntry Entry;
5068 Args.reserve(CS.arg_size());
5070 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5072 const Value *V = *i;
5075 if (V->getType()->isEmptyTy())
5078 SDValue ArgNode = getValue(V);
5079 Entry.Node = ArgNode; Entry.Ty = V->getType();
5081 // Skip the first return-type Attribute to get to params.
5082 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5083 Args.push_back(Entry);
5085 // If we have an explicit sret argument that is an Instruction, (i.e., it
5086 // might point to function-local memory), we can't meaningfully tail-call.
5087 if (Entry.isSRet && isa<Instruction>(V))
5091 // Check if target-independent constraints permit a tail call here.
5092 // Target-dependent constraints are checked within TLI->LowerCallTo.
5093 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5096 TargetLowering::CallLoweringInfo CLI(DAG);
5097 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5098 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5099 .setTailCall(isTailCall);
5100 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5102 if (Result.first.getNode())
5103 setValue(CS.getInstruction(), Result.first);
5106 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5107 /// value is equal or not-equal to zero.
5108 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5109 for (const User *U : V->users()) {
5110 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5111 if (IC->isEquality())
5112 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5113 if (C->isNullValue())
5115 // Unknown instruction.
5121 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5123 SelectionDAGBuilder &Builder) {
5125 // Check to see if this load can be trivially constant folded, e.g. if the
5126 // input is from a string literal.
5127 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5128 // Cast pointer to the type we really want to load.
5129 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5130 PointerType::getUnqual(LoadTy));
5132 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5133 const_cast<Constant *>(LoadInput), *Builder.DL))
5134 return Builder.getValue(LoadCst);
5137 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5138 // still constant memory, the input chain can be the entry node.
5140 bool ConstantMemory = false;
5142 // Do not serialize (non-volatile) loads of constant memory with anything.
5143 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5144 Root = Builder.DAG.getEntryNode();
5145 ConstantMemory = true;
5147 // Do not serialize non-volatile loads against each other.
5148 Root = Builder.DAG.getRoot();
5151 SDValue Ptr = Builder.getValue(PtrVal);
5152 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5153 Ptr, MachinePointerInfo(PtrVal),
5155 false /*nontemporal*/,
5156 false /*isinvariant*/, 1 /* align=1 */);
5158 if (!ConstantMemory)
5159 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5163 /// processIntegerCallValue - Record the value for an instruction that
5164 /// produces an integer result, converting the type where necessary.
5165 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5168 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5170 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5172 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5173 setValue(&I, Value);
5176 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5177 /// If so, return true and lower it, otherwise return false and it will be
5178 /// lowered like a normal call.
5179 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5180 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5181 if (I.getNumArgOperands() != 3)
5184 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5185 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5186 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5187 !I.getType()->isIntegerTy())
5190 const Value *Size = I.getArgOperand(2);
5191 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5192 if (CSize && CSize->getZExtValue() == 0) {
5193 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5194 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5198 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5199 std::pair<SDValue, SDValue> Res =
5200 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5201 getValue(LHS), getValue(RHS), getValue(Size),
5202 MachinePointerInfo(LHS),
5203 MachinePointerInfo(RHS));
5204 if (Res.first.getNode()) {
5205 processIntegerCallValue(I, Res.first, true);
5206 PendingLoads.push_back(Res.second);
5210 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5211 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5212 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5213 bool ActuallyDoIt = true;
5216 switch (CSize->getZExtValue()) {
5218 LoadVT = MVT::Other;
5220 ActuallyDoIt = false;
5224 LoadTy = Type::getInt16Ty(CSize->getContext());
5228 LoadTy = Type::getInt32Ty(CSize->getContext());
5232 LoadTy = Type::getInt64Ty(CSize->getContext());
5236 LoadVT = MVT::v4i32;
5237 LoadTy = Type::getInt32Ty(CSize->getContext());
5238 LoadTy = VectorType::get(LoadTy, 4);
5243 // This turns into unaligned loads. We only do this if the target natively
5244 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5245 // we'll only produce a small number of byte loads.
5247 // Require that we can find a legal MVT, and only do this if the target
5248 // supports unaligned loads of that type. Expanding into byte loads would
5250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5251 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5252 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5253 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5254 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5255 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5256 // TODO: Check alignment of src and dest ptrs.
5257 if (!TLI.isTypeLegal(LoadVT) ||
5258 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5259 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5260 ActuallyDoIt = false;
5264 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5265 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5267 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5269 processIntegerCallValue(I, Res, false);
5278 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5279 /// form. If so, return true and lower it, otherwise return false and it
5280 /// will be lowered like a normal call.
5281 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5282 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5283 if (I.getNumArgOperands() != 3)
5286 const Value *Src = I.getArgOperand(0);
5287 const Value *Char = I.getArgOperand(1);
5288 const Value *Length = I.getArgOperand(2);
5289 if (!Src->getType()->isPointerTy() ||
5290 !Char->getType()->isIntegerTy() ||
5291 !Length->getType()->isIntegerTy() ||
5292 !I.getType()->isPointerTy())
5295 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5296 std::pair<SDValue, SDValue> Res =
5297 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5298 getValue(Src), getValue(Char), getValue(Length),
5299 MachinePointerInfo(Src));
5300 if (Res.first.getNode()) {
5301 setValue(&I, Res.first);
5302 PendingLoads.push_back(Res.second);
5309 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5310 /// optimized form. If so, return true and lower it, otherwise return false
5311 /// and it will be lowered like a normal call.
5312 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5313 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5314 if (I.getNumArgOperands() != 2)
5317 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5318 if (!Arg0->getType()->isPointerTy() ||
5319 !Arg1->getType()->isPointerTy() ||
5320 !I.getType()->isPointerTy())
5323 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5324 std::pair<SDValue, SDValue> Res =
5325 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5326 getValue(Arg0), getValue(Arg1),
5327 MachinePointerInfo(Arg0),
5328 MachinePointerInfo(Arg1), isStpcpy);
5329 if (Res.first.getNode()) {
5330 setValue(&I, Res.first);
5331 DAG.setRoot(Res.second);
5338 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5339 /// If so, return true and lower it, otherwise return false and it will be
5340 /// lowered like a normal call.
5341 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5342 // Verify that the prototype makes sense. int strcmp(void*,void*)
5343 if (I.getNumArgOperands() != 2)
5346 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5347 if (!Arg0->getType()->isPointerTy() ||
5348 !Arg1->getType()->isPointerTy() ||
5349 !I.getType()->isIntegerTy())
5352 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5353 std::pair<SDValue, SDValue> Res =
5354 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5355 getValue(Arg0), getValue(Arg1),
5356 MachinePointerInfo(Arg0),
5357 MachinePointerInfo(Arg1));
5358 if (Res.first.getNode()) {
5359 processIntegerCallValue(I, Res.first, true);
5360 PendingLoads.push_back(Res.second);
5367 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5368 /// form. If so, return true and lower it, otherwise return false and it
5369 /// will be lowered like a normal call.
5370 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5371 // Verify that the prototype makes sense. size_t strlen(char *)
5372 if (I.getNumArgOperands() != 1)
5375 const Value *Arg0 = I.getArgOperand(0);
5376 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5379 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5380 std::pair<SDValue, SDValue> Res =
5381 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5382 getValue(Arg0), MachinePointerInfo(Arg0));
5383 if (Res.first.getNode()) {
5384 processIntegerCallValue(I, Res.first, false);
5385 PendingLoads.push_back(Res.second);
5392 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5393 /// form. If so, return true and lower it, otherwise return false and it
5394 /// will be lowered like a normal call.
5395 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5396 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5397 if (I.getNumArgOperands() != 2)
5400 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5401 if (!Arg0->getType()->isPointerTy() ||
5402 !Arg1->getType()->isIntegerTy() ||
5403 !I.getType()->isIntegerTy())
5406 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5407 std::pair<SDValue, SDValue> Res =
5408 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5409 getValue(Arg0), getValue(Arg1),
5410 MachinePointerInfo(Arg0));
5411 if (Res.first.getNode()) {
5412 processIntegerCallValue(I, Res.first, false);
5413 PendingLoads.push_back(Res.second);
5420 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5421 /// operation (as expected), translate it to an SDNode with the specified opcode
5422 /// and return true.
5423 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5425 // Sanity check that it really is a unary floating-point call.
5426 if (I.getNumArgOperands() != 1 ||
5427 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5428 I.getType() != I.getArgOperand(0)->getType() ||
5429 !I.onlyReadsMemory())
5432 SDValue Tmp = getValue(I.getArgOperand(0));
5433 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5437 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5438 /// operation (as expected), translate it to an SDNode with the specified opcode
5439 /// and return true.
5440 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5442 // Sanity check that it really is a binary floating-point call.
5443 if (I.getNumArgOperands() != 2 ||
5444 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5445 I.getType() != I.getArgOperand(0)->getType() ||
5446 I.getType() != I.getArgOperand(1)->getType() ||
5447 !I.onlyReadsMemory())
5450 SDValue Tmp0 = getValue(I.getArgOperand(0));
5451 SDValue Tmp1 = getValue(I.getArgOperand(1));
5452 EVT VT = Tmp0.getValueType();
5453 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5457 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5458 // Handle inline assembly differently.
5459 if (isa<InlineAsm>(I.getCalledValue())) {
5464 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5465 ComputeUsesVAFloatArgument(I, &MMI);
5467 const char *RenameFn = nullptr;
5468 if (Function *F = I.getCalledFunction()) {
5469 if (F->isDeclaration()) {
5470 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5471 if (unsigned IID = II->getIntrinsicID(F)) {
5472 RenameFn = visitIntrinsicCall(I, IID);
5477 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5478 RenameFn = visitIntrinsicCall(I, IID);
5484 // Check for well-known libc/libm calls. If the function is internal, it
5485 // can't be a library call.
5487 if (!F->hasLocalLinkage() && F->hasName() &&
5488 LibInfo->getLibFunc(F->getName(), Func) &&
5489 LibInfo->hasOptimizedCodeGen(Func)) {
5492 case LibFunc::copysign:
5493 case LibFunc::copysignf:
5494 case LibFunc::copysignl:
5495 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5496 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5497 I.getType() == I.getArgOperand(0)->getType() &&
5498 I.getType() == I.getArgOperand(1)->getType() &&
5499 I.onlyReadsMemory()) {
5500 SDValue LHS = getValue(I.getArgOperand(0));
5501 SDValue RHS = getValue(I.getArgOperand(1));
5502 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5503 LHS.getValueType(), LHS, RHS));
5508 case LibFunc::fabsf:
5509 case LibFunc::fabsl:
5510 if (visitUnaryFloatCall(I, ISD::FABS))
5514 case LibFunc::fminf:
5515 case LibFunc::fminl:
5516 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5520 case LibFunc::fmaxf:
5521 case LibFunc::fmaxl:
5522 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5528 if (visitUnaryFloatCall(I, ISD::FSIN))
5534 if (visitUnaryFloatCall(I, ISD::FCOS))
5538 case LibFunc::sqrtf:
5539 case LibFunc::sqrtl:
5540 case LibFunc::sqrt_finite:
5541 case LibFunc::sqrtf_finite:
5542 case LibFunc::sqrtl_finite:
5543 if (visitUnaryFloatCall(I, ISD::FSQRT))
5546 case LibFunc::floor:
5547 case LibFunc::floorf:
5548 case LibFunc::floorl:
5549 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5552 case LibFunc::nearbyint:
5553 case LibFunc::nearbyintf:
5554 case LibFunc::nearbyintl:
5555 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5559 case LibFunc::ceilf:
5560 case LibFunc::ceill:
5561 if (visitUnaryFloatCall(I, ISD::FCEIL))
5565 case LibFunc::rintf:
5566 case LibFunc::rintl:
5567 if (visitUnaryFloatCall(I, ISD::FRINT))
5570 case LibFunc::round:
5571 case LibFunc::roundf:
5572 case LibFunc::roundl:
5573 if (visitUnaryFloatCall(I, ISD::FROUND))
5576 case LibFunc::trunc:
5577 case LibFunc::truncf:
5578 case LibFunc::truncl:
5579 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5583 case LibFunc::log2f:
5584 case LibFunc::log2l:
5585 if (visitUnaryFloatCall(I, ISD::FLOG2))
5589 case LibFunc::exp2f:
5590 case LibFunc::exp2l:
5591 if (visitUnaryFloatCall(I, ISD::FEXP2))
5594 case LibFunc::memcmp:
5595 if (visitMemCmpCall(I))
5598 case LibFunc::memchr:
5599 if (visitMemChrCall(I))
5602 case LibFunc::strcpy:
5603 if (visitStrCpyCall(I, false))
5606 case LibFunc::stpcpy:
5607 if (visitStrCpyCall(I, true))
5610 case LibFunc::strcmp:
5611 if (visitStrCmpCall(I))
5614 case LibFunc::strlen:
5615 if (visitStrLenCall(I))
5618 case LibFunc::strnlen:
5619 if (visitStrNLenCall(I))
5628 Callee = getValue(I.getCalledValue());
5630 Callee = DAG.getExternalSymbol(RenameFn,
5631 DAG.getTargetLoweringInfo().getPointerTy());
5633 // Check if we can potentially perform a tail call. More detailed checking is
5634 // be done within LowerCallTo, after more information about the call is known.
5635 LowerCallTo(&I, Callee, I.isTailCall());
5640 /// AsmOperandInfo - This contains information for each constraint that we are
5642 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5644 /// CallOperand - If this is the result output operand or a clobber
5645 /// this is null, otherwise it is the incoming operand to the CallInst.
5646 /// This gets modified as the asm is processed.
5647 SDValue CallOperand;
5649 /// AssignedRegs - If this is a register or register class operand, this
5650 /// contains the set of register corresponding to the operand.
5651 RegsForValue AssignedRegs;
5653 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5654 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5657 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5658 /// corresponds to. If there is no Value* for this operand, it returns
5660 EVT getCallOperandValEVT(LLVMContext &Context,
5661 const TargetLowering &TLI,
5662 const DataLayout *DL) const {
5663 if (!CallOperandVal) return MVT::Other;
5665 if (isa<BasicBlock>(CallOperandVal))
5666 return TLI.getPointerTy();
5668 llvm::Type *OpTy = CallOperandVal->getType();
5670 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5671 // If this is an indirect operand, the operand is a pointer to the
5674 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5676 report_fatal_error("Indirect operand for inline asm not a pointer!");
5677 OpTy = PtrTy->getElementType();
5680 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5681 if (StructType *STy = dyn_cast<StructType>(OpTy))
5682 if (STy->getNumElements() == 1)
5683 OpTy = STy->getElementType(0);
5685 // If OpTy is not a single value, it may be a struct/union that we
5686 // can tile with integers.
5687 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5688 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5697 OpTy = IntegerType::get(Context, BitSize);
5702 return TLI.getValueType(OpTy, true);
5706 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5708 } // end anonymous namespace
5710 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5711 /// specified operand. We prefer to assign virtual registers, to allow the
5712 /// register allocator to handle the assignment process. However, if the asm
5713 /// uses features that we can't model on machineinstrs, we have SDISel do the
5714 /// allocation. This produces generally horrible, but correct, code.
5716 /// OpInfo describes the operand.
5718 static void GetRegistersForValue(SelectionDAG &DAG,
5719 const TargetLowering &TLI,
5721 SDISelAsmOperandInfo &OpInfo) {
5722 LLVMContext &Context = *DAG.getContext();
5724 MachineFunction &MF = DAG.getMachineFunction();
5725 SmallVector<unsigned, 4> Regs;
5727 // If this is a constraint for a single physreg, or a constraint for a
5728 // register class, find it.
5729 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5730 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5731 OpInfo.ConstraintCode,
5732 OpInfo.ConstraintVT);
5734 unsigned NumRegs = 1;
5735 if (OpInfo.ConstraintVT != MVT::Other) {
5736 // If this is a FP input in an integer register (or visa versa) insert a bit
5737 // cast of the input value. More generally, handle any case where the input
5738 // value disagrees with the register class we plan to stick this in.
5739 if (OpInfo.Type == InlineAsm::isInput &&
5740 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5741 // Try to convert to the first EVT that the reg class contains. If the
5742 // types are identical size, use a bitcast to convert (e.g. two differing
5744 MVT RegVT = *PhysReg.second->vt_begin();
5745 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5746 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5747 RegVT, OpInfo.CallOperand);
5748 OpInfo.ConstraintVT = RegVT;
5749 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5750 // If the input is a FP value and we want it in FP registers, do a
5751 // bitcast to the corresponding integer type. This turns an f64 value
5752 // into i64, which can be passed with two i32 values on a 32-bit
5754 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5755 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5756 RegVT, OpInfo.CallOperand);
5757 OpInfo.ConstraintVT = RegVT;
5761 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5765 EVT ValueVT = OpInfo.ConstraintVT;
5767 // If this is a constraint for a specific physical register, like {r17},
5769 if (unsigned AssignedReg = PhysReg.first) {
5770 const TargetRegisterClass *RC = PhysReg.second;
5771 if (OpInfo.ConstraintVT == MVT::Other)
5772 ValueVT = *RC->vt_begin();
5774 // Get the actual register value type. This is important, because the user
5775 // may have asked for (e.g.) the AX register in i32 type. We need to
5776 // remember that AX is actually i16 to get the right extension.
5777 RegVT = *RC->vt_begin();
5779 // This is a explicit reference to a physical register.
5780 Regs.push_back(AssignedReg);
5782 // If this is an expanded reference, add the rest of the regs to Regs.
5784 TargetRegisterClass::iterator I = RC->begin();
5785 for (; *I != AssignedReg; ++I)
5786 assert(I != RC->end() && "Didn't find reg!");
5788 // Already added the first reg.
5790 for (; NumRegs; --NumRegs, ++I) {
5791 assert(I != RC->end() && "Ran out of registers to allocate!");
5796 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5800 // Otherwise, if this was a reference to an LLVM register class, create vregs
5801 // for this reference.
5802 if (const TargetRegisterClass *RC = PhysReg.second) {
5803 RegVT = *RC->vt_begin();
5804 if (OpInfo.ConstraintVT == MVT::Other)
5807 // Create the appropriate number of virtual registers.
5808 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5809 for (; NumRegs; --NumRegs)
5810 Regs.push_back(RegInfo.createVirtualRegister(RC));
5812 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5816 // Otherwise, we couldn't allocate enough registers for this.
5819 /// visitInlineAsm - Handle a call to an InlineAsm object.
5821 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5822 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5824 /// ConstraintOperands - Information about all of the constraints.
5825 SDISelAsmOperandInfoVector ConstraintOperands;
5827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5828 TargetLowering::AsmOperandInfoVector TargetConstraints =
5829 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5831 bool hasMemory = false;
5833 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5834 unsigned ResNo = 0; // ResNo - The result number of the next output.
5835 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5836 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5837 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5839 MVT OpVT = MVT::Other;
5841 // Compute the value type for each operand.
5842 switch (OpInfo.Type) {
5843 case InlineAsm::isOutput:
5844 // Indirect outputs just consume an argument.
5845 if (OpInfo.isIndirect) {
5846 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5850 // The return value of the call is this value. As such, there is no
5851 // corresponding argument.
5852 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5853 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5854 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5856 assert(ResNo == 0 && "Asm only has one result!");
5857 OpVT = TLI.getSimpleValueType(CS.getType());
5861 case InlineAsm::isInput:
5862 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5864 case InlineAsm::isClobber:
5869 // If this is an input or an indirect output, process the call argument.
5870 // BasicBlocks are labels, currently appearing only in asm's.
5871 if (OpInfo.CallOperandVal) {
5872 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5873 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5875 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5879 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5882 OpInfo.ConstraintVT = OpVT;
5884 // Indirect operand accesses access memory.
5885 if (OpInfo.isIndirect)
5888 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5889 TargetLowering::ConstraintType
5890 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5891 if (CType == TargetLowering::C_Memory) {
5899 SDValue Chain, Flag;
5901 // We won't need to flush pending loads if this asm doesn't touch
5902 // memory and is nonvolatile.
5903 if (hasMemory || IA->hasSideEffects())
5906 Chain = DAG.getRoot();
5908 // Second pass over the constraints: compute which constraint option to use
5909 // and assign registers to constraints that want a specific physreg.
5910 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5911 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5913 // If this is an output operand with a matching input operand, look up the
5914 // matching input. If their types mismatch, e.g. one is an integer, the
5915 // other is floating point, or their sizes are different, flag it as an
5917 if (OpInfo.hasMatchingInput()) {
5918 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5920 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5921 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5922 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5923 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5924 OpInfo.ConstraintVT);
5925 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5926 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5927 Input.ConstraintVT);
5928 if ((OpInfo.ConstraintVT.isInteger() !=
5929 Input.ConstraintVT.isInteger()) ||
5930 (MatchRC.second != InputRC.second)) {
5931 report_fatal_error("Unsupported asm: input constraint"
5932 " with a matching output constraint of"
5933 " incompatible type!");
5935 Input.ConstraintVT = OpInfo.ConstraintVT;
5939 // Compute the constraint code and ConstraintType to use.
5940 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5942 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5943 OpInfo.Type == InlineAsm::isClobber)
5946 // If this is a memory input, and if the operand is not indirect, do what we
5947 // need to to provide an address for the memory input.
5948 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5949 !OpInfo.isIndirect) {
5950 assert((OpInfo.isMultipleAlternative ||
5951 (OpInfo.Type == InlineAsm::isInput)) &&
5952 "Can only indirectify direct input operands!");
5954 // Memory operands really want the address of the value. If we don't have
5955 // an indirect input, put it in the constpool if we can, otherwise spill
5956 // it to a stack slot.
5957 // TODO: This isn't quite right. We need to handle these according to
5958 // the addressing mode that the constraint wants. Also, this may take
5959 // an additional register for the computation and we don't want that
5962 // If the operand is a float, integer, or vector constant, spill to a
5963 // constant pool entry to get its address.
5964 const Value *OpVal = OpInfo.CallOperandVal;
5965 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5966 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5967 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5968 TLI.getPointerTy());
5970 // Otherwise, create a stack slot and emit a store to it before the
5972 Type *Ty = OpVal->getType();
5973 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5974 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5975 MachineFunction &MF = DAG.getMachineFunction();
5976 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5977 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5978 Chain = DAG.getStore(Chain, getCurSDLoc(),
5979 OpInfo.CallOperand, StackSlot,
5980 MachinePointerInfo::getFixedStack(SSFI),
5982 OpInfo.CallOperand = StackSlot;
5985 // There is no longer a Value* corresponding to this operand.
5986 OpInfo.CallOperandVal = nullptr;
5988 // It is now an indirect operand.
5989 OpInfo.isIndirect = true;
5992 // If this constraint is for a specific register, allocate it before
5994 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5995 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5998 // Second pass - Loop over all of the operands, assigning virtual or physregs
5999 // to register class operands.
6000 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6001 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6003 // C_Register operands have already been allocated, Other/Memory don't need
6005 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6006 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6009 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6010 std::vector<SDValue> AsmNodeOperands;
6011 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6012 AsmNodeOperands.push_back(
6013 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6014 TLI.getPointerTy()));
6016 // If we have a !srcloc metadata node associated with it, we want to attach
6017 // this to the ultimately generated inline asm machineinstr. To do this, we
6018 // pass in the third operand as this (potentially null) inline asm MDNode.
6019 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6020 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6022 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6023 // bits as operand 3.
6024 unsigned ExtraInfo = 0;
6025 if (IA->hasSideEffects())
6026 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6027 if (IA->isAlignStack())
6028 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6029 // Set the asm dialect.
6030 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6032 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6033 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6034 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6036 // Compute the constraint code and ConstraintType to use.
6037 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6039 // Ideally, we would only check against memory constraints. However, the
6040 // meaning of an other constraint can be target-specific and we can't easily
6041 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6042 // for other constriants as well.
6043 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6044 OpInfo.ConstraintType == TargetLowering::C_Other) {
6045 if (OpInfo.Type == InlineAsm::isInput)
6046 ExtraInfo |= InlineAsm::Extra_MayLoad;
6047 else if (OpInfo.Type == InlineAsm::isOutput)
6048 ExtraInfo |= InlineAsm::Extra_MayStore;
6049 else if (OpInfo.Type == InlineAsm::isClobber)
6050 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6054 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, getCurSDLoc(),
6055 TLI.getPointerTy()));
6057 // Loop over all of the inputs, copying the operand values into the
6058 // appropriate registers and processing the output regs.
6059 RegsForValue RetValRegs;
6061 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6062 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6064 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6065 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6067 switch (OpInfo.Type) {
6068 case InlineAsm::isOutput: {
6069 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6070 OpInfo.ConstraintType != TargetLowering::C_Register) {
6071 // Memory output, or 'other' output (e.g. 'X' constraint).
6072 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6074 unsigned ConstraintID =
6075 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6076 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6077 "Failed to convert memory constraint code to constraint id.");
6079 // Add information to the INLINEASM node to know about this output.
6080 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6081 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6082 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6084 AsmNodeOperands.push_back(OpInfo.CallOperand);
6088 // Otherwise, this is a register or register class output.
6090 // Copy the output from the appropriate register. Find a register that
6092 if (OpInfo.AssignedRegs.Regs.empty()) {
6093 LLVMContext &Ctx = *DAG.getContext();
6094 Ctx.emitError(CS.getInstruction(),
6095 "couldn't allocate output register for constraint '" +
6096 Twine(OpInfo.ConstraintCode) + "'");
6100 // If this is an indirect operand, store through the pointer after the
6102 if (OpInfo.isIndirect) {
6103 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6104 OpInfo.CallOperandVal));
6106 // This is the result value of the call.
6107 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6108 // Concatenate this output onto the outputs list.
6109 RetValRegs.append(OpInfo.AssignedRegs);
6112 // Add information to the INLINEASM node to know that this register is
6115 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6116 ? InlineAsm::Kind_RegDefEarlyClobber
6117 : InlineAsm::Kind_RegDef,
6118 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6121 case InlineAsm::isInput: {
6122 SDValue InOperandVal = OpInfo.CallOperand;
6124 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6125 // If this is required to match an output register we have already set,
6126 // just use its register.
6127 unsigned OperandNo = OpInfo.getMatchedOperand();
6129 // Scan until we find the definition we already emitted of this operand.
6130 // When we find it, create a RegsForValue operand.
6131 unsigned CurOp = InlineAsm::Op_FirstOperand;
6132 for (; OperandNo; --OperandNo) {
6133 // Advance to the next operand.
6135 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6136 assert((InlineAsm::isRegDefKind(OpFlag) ||
6137 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6138 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6139 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6143 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6144 if (InlineAsm::isRegDefKind(OpFlag) ||
6145 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6146 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6147 if (OpInfo.isIndirect) {
6148 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6149 LLVMContext &Ctx = *DAG.getContext();
6150 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6151 " don't know how to handle tied "
6152 "indirect register inputs");
6156 RegsForValue MatchedRegs;
6157 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6158 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6159 MatchedRegs.RegVTs.push_back(RegVT);
6160 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6161 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6163 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6164 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6166 LLVMContext &Ctx = *DAG.getContext();
6167 Ctx.emitError(CS.getInstruction(),
6168 "inline asm error: This value"
6169 " type register class is not natively supported!");
6173 SDLoc dl = getCurSDLoc();
6174 // Use the produced MatchedRegs object to
6175 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6176 Chain, &Flag, CS.getInstruction());
6177 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6178 true, OpInfo.getMatchedOperand(), dl,
6179 DAG, AsmNodeOperands);
6183 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6184 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6185 "Unexpected number of operands");
6186 // Add information to the INLINEASM node to know about this input.
6187 // See InlineAsm.h isUseOperandTiedToDef.
6188 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6189 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6190 OpInfo.getMatchedOperand());
6191 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, getCurSDLoc(),
6192 TLI.getPointerTy()));
6193 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6197 // Treat indirect 'X' constraint as memory.
6198 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6200 OpInfo.ConstraintType = TargetLowering::C_Memory;
6202 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6203 std::vector<SDValue> Ops;
6204 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6207 LLVMContext &Ctx = *DAG.getContext();
6208 Ctx.emitError(CS.getInstruction(),
6209 "invalid operand for inline asm constraint '" +
6210 Twine(OpInfo.ConstraintCode) + "'");
6214 // Add information to the INLINEASM node to know about this input.
6215 unsigned ResOpType =
6216 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6217 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6219 TLI.getPointerTy()));
6220 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6224 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6225 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6226 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6227 "Memory operands expect pointer values");
6229 unsigned ConstraintID =
6230 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6231 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6232 "Failed to convert memory constraint code to constraint id.");
6234 // Add information to the INLINEASM node to know about this input.
6235 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6236 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6237 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6240 AsmNodeOperands.push_back(InOperandVal);
6244 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6245 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6246 "Unknown constraint type!");
6248 // TODO: Support this.
6249 if (OpInfo.isIndirect) {
6250 LLVMContext &Ctx = *DAG.getContext();
6251 Ctx.emitError(CS.getInstruction(),
6252 "Don't know how to handle indirect register inputs yet "
6253 "for constraint '" +
6254 Twine(OpInfo.ConstraintCode) + "'");
6258 // Copy the input into the appropriate registers.
6259 if (OpInfo.AssignedRegs.Regs.empty()) {
6260 LLVMContext &Ctx = *DAG.getContext();
6261 Ctx.emitError(CS.getInstruction(),
6262 "couldn't allocate input reg for constraint '" +
6263 Twine(OpInfo.ConstraintCode) + "'");
6267 SDLoc dl = getCurSDLoc();
6269 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6270 Chain, &Flag, CS.getInstruction());
6272 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6273 dl, DAG, AsmNodeOperands);
6276 case InlineAsm::isClobber: {
6277 // Add the clobbered value to the operand list, so that the register
6278 // allocator is aware that the physreg got clobbered.
6279 if (!OpInfo.AssignedRegs.Regs.empty())
6280 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6281 false, 0, getCurSDLoc(), DAG,
6288 // Finish up input operands. Set the input chain and add the flag last.
6289 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6290 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6292 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6293 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6294 Flag = Chain.getValue(1);
6296 // If this asm returns a register value, copy the result from that register
6297 // and set it as the value of the call.
6298 if (!RetValRegs.Regs.empty()) {
6299 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6300 Chain, &Flag, CS.getInstruction());
6302 // FIXME: Why don't we do this for inline asms with MRVs?
6303 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6304 EVT ResultType = TLI.getValueType(CS.getType());
6306 // If any of the results of the inline asm is a vector, it may have the
6307 // wrong width/num elts. This can happen for register classes that can
6308 // contain multiple different value types. The preg or vreg allocated may
6309 // not have the same VT as was expected. Convert it to the right type
6310 // with bit_convert.
6311 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6312 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6315 } else if (ResultType != Val.getValueType() &&
6316 ResultType.isInteger() && Val.getValueType().isInteger()) {
6317 // If a result value was tied to an input value, the computed result may
6318 // have a wider width than the expected result. Extract the relevant
6320 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6323 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6326 setValue(CS.getInstruction(), Val);
6327 // Don't need to use this as a chain in this case.
6328 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6332 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6334 // Process indirect outputs, first output all of the flagged copies out of
6336 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6337 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6338 const Value *Ptr = IndirectStoresToEmit[i].second;
6339 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6341 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6344 // Emit the non-flagged stores from the physregs.
6345 SmallVector<SDValue, 8> OutChains;
6346 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6347 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6348 StoresToEmit[i].first,
6349 getValue(StoresToEmit[i].second),
6350 MachinePointerInfo(StoresToEmit[i].second),
6352 OutChains.push_back(Val);
6355 if (!OutChains.empty())
6356 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6361 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6362 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6363 MVT::Other, getRoot(),
6364 getValue(I.getArgOperand(0)),
6365 DAG.getSrcValue(I.getArgOperand(0))));
6368 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6370 const DataLayout &DL = *TLI.getDataLayout();
6371 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6372 getRoot(), getValue(I.getOperand(0)),
6373 DAG.getSrcValue(I.getOperand(0)),
6374 DL.getABITypeAlignment(I.getType()));
6376 DAG.setRoot(V.getValue(1));
6379 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6380 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6381 MVT::Other, getRoot(),
6382 getValue(I.getArgOperand(0)),
6383 DAG.getSrcValue(I.getArgOperand(0))));
6386 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6387 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6388 MVT::Other, getRoot(),
6389 getValue(I.getArgOperand(0)),
6390 getValue(I.getArgOperand(1)),
6391 DAG.getSrcValue(I.getArgOperand(0)),
6392 DAG.getSrcValue(I.getArgOperand(1))));
6395 /// \brief Lower an argument list according to the target calling convention.
6397 /// \return A tuple of <return-value, token-chain>
6399 /// This is a helper for lowering intrinsics that follow a target calling
6400 /// convention or require stack pointer adjustment. Only a subset of the
6401 /// intrinsic's operands need to participate in the calling convention.
6402 std::pair<SDValue, SDValue>
6403 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6404 unsigned NumArgs, SDValue Callee,
6406 MachineBasicBlock *LandingPad,
6407 bool IsPatchPoint) {
6408 TargetLowering::ArgListTy Args;
6409 Args.reserve(NumArgs);
6411 // Populate the argument list.
6412 // Attributes for args start at offset 1, after the return attribute.
6413 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6414 ArgI != ArgE; ++ArgI) {
6415 const Value *V = CS->getOperand(ArgI);
6417 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6419 TargetLowering::ArgListEntry Entry;
6420 Entry.Node = getValue(V);
6421 Entry.Ty = V->getType();
6422 Entry.setAttributes(&CS, AttrI);
6423 Args.push_back(Entry);
6426 TargetLowering::CallLoweringInfo CLI(DAG);
6427 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6428 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6429 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6431 return lowerInvokable(CLI, LandingPad);
6434 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6435 /// or patchpoint target node's operand list.
6437 /// Constants are converted to TargetConstants purely as an optimization to
6438 /// avoid constant materialization and register allocation.
6440 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6441 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6442 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6443 /// address materialization and register allocation, but may also be required
6444 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6445 /// alloca in the entry block, then the runtime may assume that the alloca's
6446 /// StackMap location can be read immediately after compilation and that the
6447 /// location is valid at any point during execution (this is similar to the
6448 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6449 /// only available in a register, then the runtime would need to trap when
6450 /// execution reaches the StackMap in order to read the alloca's location.
6451 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6452 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6453 SelectionDAGBuilder &Builder) {
6454 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6455 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6458 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6460 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6461 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6462 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6464 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6466 Ops.push_back(OpVal);
6470 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6471 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6472 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6473 // [live variables...])
6475 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6477 SDValue Chain, InFlag, Callee, NullPtr;
6478 SmallVector<SDValue, 32> Ops;
6480 SDLoc DL = getCurSDLoc();
6481 Callee = getValue(CI.getCalledValue());
6482 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6484 // The stackmap intrinsic only records the live variables (the arguemnts
6485 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6486 // intrinsic, this won't be lowered to a function call. This means we don't
6487 // have to worry about calling conventions and target specific lowering code.
6488 // Instead we perform the call lowering right here.
6490 // chain, flag = CALLSEQ_START(chain, 0)
6491 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6492 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6494 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6495 InFlag = Chain.getValue(1);
6497 // Add the <id> and <numBytes> constants.
6498 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6499 Ops.push_back(DAG.getTargetConstant(
6500 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6501 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6502 Ops.push_back(DAG.getTargetConstant(
6503 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6506 // Push live variables for the stack map.
6507 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6509 // We are not pushing any register mask info here on the operands list,
6510 // because the stackmap doesn't clobber anything.
6512 // Push the chain and the glue flag.
6513 Ops.push_back(Chain);
6514 Ops.push_back(InFlag);
6516 // Create the STACKMAP node.
6517 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6518 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6519 Chain = SDValue(SM, 0);
6520 InFlag = Chain.getValue(1);
6522 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6524 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6526 // Set the root to the target-lowered call chain.
6529 // Inform the Frame Information that we have a stackmap in this function.
6530 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6533 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6534 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6535 MachineBasicBlock *LandingPad) {
6536 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6541 // [live variables...])
6543 CallingConv::ID CC = CS.getCallingConv();
6544 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6545 bool HasDef = !CS->getType()->isVoidTy();
6546 SDLoc dl = getCurSDLoc();
6547 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6549 // Handle immediate and symbolic callees.
6550 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6551 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6553 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6554 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6555 SDLoc(SymbolicCallee),
6556 SymbolicCallee->getValueType(0));
6558 // Get the real number of arguments participating in the call <numArgs>
6559 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6560 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6562 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6563 // Intrinsics include all meta-operands up to but not including CC.
6564 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6565 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6566 "Not enough arguments provided to the patchpoint intrinsic");
6568 // For AnyRegCC the arguments are lowered later on manually.
6569 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6571 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6572 std::pair<SDValue, SDValue> Result =
6573 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6576 SDNode *CallEnd = Result.second.getNode();
6577 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6578 CallEnd = CallEnd->getOperand(0).getNode();
6580 /// Get a call instruction from the call sequence chain.
6581 /// Tail calls are not allowed.
6582 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6583 "Expected a callseq node.");
6584 SDNode *Call = CallEnd->getOperand(0).getNode();
6585 bool HasGlue = Call->getGluedNode();
6587 // Replace the target specific call node with the patchable intrinsic.
6588 SmallVector<SDValue, 8> Ops;
6590 // Add the <id> and <numBytes> constants.
6591 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6592 Ops.push_back(DAG.getTargetConstant(
6593 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6594 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6595 Ops.push_back(DAG.getTargetConstant(
6596 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6600 Ops.push_back(Callee);
6602 // Adjust <numArgs> to account for any arguments that have been passed on the
6604 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6605 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6606 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6607 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6609 // Add the calling convention
6610 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6612 // Add the arguments we omitted previously. The register allocator should
6613 // place these in any free register.
6615 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6616 Ops.push_back(getValue(CS.getArgument(i)));
6618 // Push the arguments from the call instruction up to the register mask.
6619 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6620 Ops.append(Call->op_begin() + 2, e);
6622 // Push live variables for the stack map.
6623 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6625 // Push the register mask info.
6627 Ops.push_back(*(Call->op_end()-2));
6629 Ops.push_back(*(Call->op_end()-1));
6631 // Push the chain (this is originally the first operand of the call, but
6632 // becomes now the last or second to last operand).
6633 Ops.push_back(*(Call->op_begin()));
6635 // Push the glue flag (last operand).
6637 Ops.push_back(*(Call->op_end()-1));
6640 if (IsAnyRegCC && HasDef) {
6641 // Create the return types based on the intrinsic definition
6642 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6643 SmallVector<EVT, 3> ValueVTs;
6644 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6645 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6647 // There is always a chain and a glue type at the end
6648 ValueVTs.push_back(MVT::Other);
6649 ValueVTs.push_back(MVT::Glue);
6650 NodeTys = DAG.getVTList(ValueVTs);
6652 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6654 // Replace the target specific call node with a PATCHPOINT node.
6655 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6658 // Update the NodeMap.
6661 setValue(CS.getInstruction(), SDValue(MN, 0));
6663 setValue(CS.getInstruction(), Result.first);
6666 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6667 // call sequence. Furthermore the location of the chain and glue can change
6668 // when the AnyReg calling convention is used and the intrinsic returns a
6670 if (IsAnyRegCC && HasDef) {
6671 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6672 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6673 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6675 DAG.ReplaceAllUsesWith(Call, MN);
6676 DAG.DeleteNode(Call);
6678 // Inform the Frame Information that we have a patchpoint in this function.
6679 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6682 /// Returns an AttributeSet representing the attributes applied to the return
6683 /// value of the given call.
6684 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6685 SmallVector<Attribute::AttrKind, 2> Attrs;
6687 Attrs.push_back(Attribute::SExt);
6689 Attrs.push_back(Attribute::ZExt);
6691 Attrs.push_back(Attribute::InReg);
6693 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6697 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6698 /// implementation, which just calls LowerCall.
6699 /// FIXME: When all targets are
6700 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6701 std::pair<SDValue, SDValue>
6702 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6703 // Handle the incoming return values from the call.
6705 Type *OrigRetTy = CLI.RetTy;
6706 SmallVector<EVT, 4> RetTys;
6707 SmallVector<uint64_t, 4> Offsets;
6708 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6710 SmallVector<ISD::OutputArg, 4> Outs;
6711 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6713 bool CanLowerReturn =
6714 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6715 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6717 SDValue DemoteStackSlot;
6718 int DemoteStackIdx = -100;
6719 if (!CanLowerReturn) {
6720 // FIXME: equivalent assert?
6721 // assert(!CS.hasInAllocaArgument() &&
6722 // "sret demotion is incompatible with inalloca");
6723 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6724 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6725 MachineFunction &MF = CLI.DAG.getMachineFunction();
6726 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6727 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6729 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6731 Entry.Node = DemoteStackSlot;
6732 Entry.Ty = StackSlotPtrType;
6733 Entry.isSExt = false;
6734 Entry.isZExt = false;
6735 Entry.isInReg = false;
6736 Entry.isSRet = true;
6737 Entry.isNest = false;
6738 Entry.isByVal = false;
6739 Entry.isReturned = false;
6740 Entry.Alignment = Align;
6741 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6742 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6744 // sret demotion isn't compatible with tail-calls, since the sret argument
6745 // points into the callers stack frame.
6746 CLI.IsTailCall = false;
6748 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6750 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6751 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6752 for (unsigned i = 0; i != NumRegs; ++i) {
6753 ISD::InputArg MyFlags;
6754 MyFlags.VT = RegisterVT;
6756 MyFlags.Used = CLI.IsReturnValueUsed;
6758 MyFlags.Flags.setSExt();
6760 MyFlags.Flags.setZExt();
6762 MyFlags.Flags.setInReg();
6763 CLI.Ins.push_back(MyFlags);
6768 // Handle all of the outgoing arguments.
6770 CLI.OutVals.clear();
6771 ArgListTy &Args = CLI.getArgs();
6772 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6773 SmallVector<EVT, 4> ValueVTs;
6774 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6775 Type *FinalType = Args[i].Ty;
6776 if (Args[i].isByVal)
6777 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6778 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6779 FinalType, CLI.CallConv, CLI.IsVarArg);
6780 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6782 EVT VT = ValueVTs[Value];
6783 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6784 SDValue Op = SDValue(Args[i].Node.getNode(),
6785 Args[i].Node.getResNo() + Value);
6786 ISD::ArgFlagsTy Flags;
6787 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6793 if (Args[i].isInReg)
6797 if (Args[i].isByVal)
6799 if (Args[i].isInAlloca) {
6800 Flags.setInAlloca();
6801 // Set the byval flag for CCAssignFn callbacks that don't know about
6802 // inalloca. This way we can know how many bytes we should've allocated
6803 // and how many bytes a callee cleanup function will pop. If we port
6804 // inalloca to more targets, we'll have to add custom inalloca handling
6805 // in the various CC lowering callbacks.
6808 if (Args[i].isByVal || Args[i].isInAlloca) {
6809 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6810 Type *ElementTy = Ty->getElementType();
6811 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6812 // For ByVal, alignment should come from FE. BE will guess if this
6813 // info is not there but there are cases it cannot get right.
6814 unsigned FrameAlign;
6815 if (Args[i].Alignment)
6816 FrameAlign = Args[i].Alignment;
6818 FrameAlign = getByValTypeAlignment(ElementTy);
6819 Flags.setByValAlign(FrameAlign);
6824 Flags.setInConsecutiveRegs();
6825 Flags.setOrigAlign(OriginalAlignment);
6827 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6828 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6829 SmallVector<SDValue, 4> Parts(NumParts);
6830 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6833 ExtendKind = ISD::SIGN_EXTEND;
6834 else if (Args[i].isZExt)
6835 ExtendKind = ISD::ZERO_EXTEND;
6837 // Conservatively only handle 'returned' on non-vectors for now
6838 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6839 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6840 "unexpected use of 'returned'");
6841 // Before passing 'returned' to the target lowering code, ensure that
6842 // either the register MVT and the actual EVT are the same size or that
6843 // the return value and argument are extended in the same way; in these
6844 // cases it's safe to pass the argument register value unchanged as the
6845 // return register value (although it's at the target's option whether
6847 // TODO: allow code generation to take advantage of partially preserved
6848 // registers rather than clobbering the entire register when the
6849 // parameter extension method is not compatible with the return
6851 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6852 (ExtendKind != ISD::ANY_EXTEND &&
6853 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6854 Flags.setReturned();
6857 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6858 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6860 for (unsigned j = 0; j != NumParts; ++j) {
6861 // if it isn't first piece, alignment must be 1
6862 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6863 i < CLI.NumFixedArgs,
6864 i, j*Parts[j].getValueType().getStoreSize());
6865 if (NumParts > 1 && j == 0)
6866 MyFlags.Flags.setSplit();
6868 MyFlags.Flags.setOrigAlign(1);
6870 CLI.Outs.push_back(MyFlags);
6871 CLI.OutVals.push_back(Parts[j]);
6874 if (NeedsRegBlock && Value == NumValues - 1)
6875 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6879 SmallVector<SDValue, 4> InVals;
6880 CLI.Chain = LowerCall(CLI, InVals);
6882 // Verify that the target's LowerCall behaved as expected.
6883 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6884 "LowerCall didn't return a valid chain!");
6885 assert((!CLI.IsTailCall || InVals.empty()) &&
6886 "LowerCall emitted a return value for a tail call!");
6887 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6888 "LowerCall didn't emit the correct number of values!");
6890 // For a tail call, the return value is merely live-out and there aren't
6891 // any nodes in the DAG representing it. Return a special value to
6892 // indicate that a tail call has been emitted and no more Instructions
6893 // should be processed in the current block.
6894 if (CLI.IsTailCall) {
6895 CLI.DAG.setRoot(CLI.Chain);
6896 return std::make_pair(SDValue(), SDValue());
6899 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6900 assert(InVals[i].getNode() &&
6901 "LowerCall emitted a null value!");
6902 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6903 "LowerCall emitted a value with the wrong type!");
6906 SmallVector<SDValue, 4> ReturnValues;
6907 if (!CanLowerReturn) {
6908 // The instruction result is the result of loading from the
6909 // hidden sret parameter.
6910 SmallVector<EVT, 1> PVTs;
6911 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6913 ComputeValueVTs(*this, PtrRetTy, PVTs);
6914 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6915 EVT PtrVT = PVTs[0];
6917 unsigned NumValues = RetTys.size();
6918 ReturnValues.resize(NumValues);
6919 SmallVector<SDValue, 4> Chains(NumValues);
6921 for (unsigned i = 0; i < NumValues; ++i) {
6922 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6923 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6925 SDValue L = CLI.DAG.getLoad(
6926 RetTys[i], CLI.DL, CLI.Chain, Add,
6927 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6929 ReturnValues[i] = L;
6930 Chains[i] = L.getValue(1);
6933 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6935 // Collect the legal value parts into potentially illegal values
6936 // that correspond to the original function's return values.
6937 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6939 AssertOp = ISD::AssertSext;
6940 else if (CLI.RetZExt)
6941 AssertOp = ISD::AssertZext;
6942 unsigned CurReg = 0;
6943 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6945 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6946 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6948 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6949 NumRegs, RegisterVT, VT, nullptr,
6954 // For a function returning void, there is no return value. We can't create
6955 // such a node, so we just return a null return value in that case. In
6956 // that case, nothing will actually look at the value.
6957 if (ReturnValues.empty())
6958 return std::make_pair(SDValue(), CLI.Chain);
6961 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6962 CLI.DAG.getVTList(RetTys), ReturnValues);
6963 return std::make_pair(Res, CLI.Chain);
6966 void TargetLowering::LowerOperationWrapper(SDNode *N,
6967 SmallVectorImpl<SDValue> &Results,
6968 SelectionDAG &DAG) const {
6969 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6971 Results.push_back(Res);
6974 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6975 llvm_unreachable("LowerOperation not implemented for this target!");
6979 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6980 SDValue Op = getNonRegisterValue(V);
6981 assert((Op.getOpcode() != ISD::CopyFromReg ||
6982 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6983 "Copy from a reg to the same reg!");
6984 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6986 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6987 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6988 SDValue Chain = DAG.getEntryNode();
6990 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
6991 FuncInfo.PreferredExtendType.end())
6993 : FuncInfo.PreferredExtendType[V];
6994 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
6995 PendingExports.push_back(Chain);
6998 #include "llvm/CodeGen/SelectionDAGISel.h"
7000 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7001 /// entry block, return true. This includes arguments used by switches, since
7002 /// the switch may expand into multiple basic blocks.
7003 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7004 // With FastISel active, we may be splitting blocks, so force creation
7005 // of virtual registers for all non-dead arguments.
7007 return A->use_empty();
7009 const BasicBlock *Entry = A->getParent()->begin();
7010 for (const User *U : A->users())
7011 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7012 return false; // Use not in entry block.
7017 void SelectionDAGISel::LowerArguments(const Function &F) {
7018 SelectionDAG &DAG = SDB->DAG;
7019 SDLoc dl = SDB->getCurSDLoc();
7020 const DataLayout *DL = TLI->getDataLayout();
7021 SmallVector<ISD::InputArg, 16> Ins;
7023 if (!FuncInfo->CanLowerReturn) {
7024 // Put in an sret pointer parameter before all the other parameters.
7025 SmallVector<EVT, 1> ValueVTs;
7026 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7028 // NOTE: Assuming that a pointer will never break down to more than one VT
7030 ISD::ArgFlagsTy Flags;
7032 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7033 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7034 ISD::InputArg::NoArgIndex, 0);
7035 Ins.push_back(RetArg);
7038 // Set up the incoming argument description vector.
7040 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7041 I != E; ++I, ++Idx) {
7042 SmallVector<EVT, 4> ValueVTs;
7043 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7044 bool isArgValueUsed = !I->use_empty();
7045 unsigned PartBase = 0;
7046 Type *FinalType = I->getType();
7047 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7048 FinalType = cast<PointerType>(FinalType)->getElementType();
7049 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7050 FinalType, F.getCallingConv(), F.isVarArg());
7051 for (unsigned Value = 0, NumValues = ValueVTs.size();
7052 Value != NumValues; ++Value) {
7053 EVT VT = ValueVTs[Value];
7054 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7055 ISD::ArgFlagsTy Flags;
7056 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7058 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7060 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7062 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7064 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7066 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7068 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7069 Flags.setInAlloca();
7070 // Set the byval flag for CCAssignFn callbacks that don't know about
7071 // inalloca. This way we can know how many bytes we should've allocated
7072 // and how many bytes a callee cleanup function will pop. If we port
7073 // inalloca to more targets, we'll have to add custom inalloca handling
7074 // in the various CC lowering callbacks.
7077 if (Flags.isByVal() || Flags.isInAlloca()) {
7078 PointerType *Ty = cast<PointerType>(I->getType());
7079 Type *ElementTy = Ty->getElementType();
7080 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7081 // For ByVal, alignment should be passed from FE. BE will guess if
7082 // this info is not there but there are cases it cannot get right.
7083 unsigned FrameAlign;
7084 if (F.getParamAlignment(Idx))
7085 FrameAlign = F.getParamAlignment(Idx);
7087 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7088 Flags.setByValAlign(FrameAlign);
7090 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7093 Flags.setInConsecutiveRegs();
7094 Flags.setOrigAlign(OriginalAlignment);
7096 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7097 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7098 for (unsigned i = 0; i != NumRegs; ++i) {
7099 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7100 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7101 if (NumRegs > 1 && i == 0)
7102 MyFlags.Flags.setSplit();
7103 // if it isn't first piece, alignment must be 1
7105 MyFlags.Flags.setOrigAlign(1);
7106 Ins.push_back(MyFlags);
7108 if (NeedsRegBlock && Value == NumValues - 1)
7109 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7110 PartBase += VT.getStoreSize();
7114 // Call the target to set up the argument values.
7115 SmallVector<SDValue, 8> InVals;
7116 SDValue NewRoot = TLI->LowerFormalArguments(
7117 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7119 // Verify that the target's LowerFormalArguments behaved as expected.
7120 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7121 "LowerFormalArguments didn't return a valid chain!");
7122 assert(InVals.size() == Ins.size() &&
7123 "LowerFormalArguments didn't emit the correct number of values!");
7125 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7126 assert(InVals[i].getNode() &&
7127 "LowerFormalArguments emitted a null value!");
7128 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7129 "LowerFormalArguments emitted a value with the wrong type!");
7133 // Update the DAG with the new chain value resulting from argument lowering.
7134 DAG.setRoot(NewRoot);
7136 // Set up the argument values.
7139 if (!FuncInfo->CanLowerReturn) {
7140 // Create a virtual register for the sret pointer, and put in a copy
7141 // from the sret argument into it.
7142 SmallVector<EVT, 1> ValueVTs;
7143 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7144 MVT VT = ValueVTs[0].getSimpleVT();
7145 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7146 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7147 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7148 RegVT, VT, nullptr, AssertOp);
7150 MachineFunction& MF = SDB->DAG.getMachineFunction();
7151 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7152 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7153 FuncInfo->DemoteRegister = SRetReg;
7155 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7156 DAG.setRoot(NewRoot);
7158 // i indexes lowered arguments. Bump it past the hidden sret argument.
7159 // Idx indexes LLVM arguments. Don't touch it.
7163 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7165 SmallVector<SDValue, 4> ArgValues;
7166 SmallVector<EVT, 4> ValueVTs;
7167 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7168 unsigned NumValues = ValueVTs.size();
7170 // If this argument is unused then remember its value. It is used to generate
7171 // debugging information.
7172 if (I->use_empty() && NumValues) {
7173 SDB->setUnusedArgValue(I, InVals[i]);
7175 // Also remember any frame index for use in FastISel.
7176 if (FrameIndexSDNode *FI =
7177 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7178 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7181 for (unsigned Val = 0; Val != NumValues; ++Val) {
7182 EVT VT = ValueVTs[Val];
7183 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7184 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7186 if (!I->use_empty()) {
7187 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7188 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7189 AssertOp = ISD::AssertSext;
7190 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7191 AssertOp = ISD::AssertZext;
7193 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7194 NumParts, PartVT, VT,
7195 nullptr, AssertOp));
7201 // We don't need to do anything else for unused arguments.
7202 if (ArgValues.empty())
7205 // Note down frame index.
7206 if (FrameIndexSDNode *FI =
7207 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7208 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7210 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7211 SDB->getCurSDLoc());
7213 SDB->setValue(I, Res);
7214 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7215 if (LoadSDNode *LNode =
7216 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7217 if (FrameIndexSDNode *FI =
7218 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7219 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7222 // If this argument is live outside of the entry block, insert a copy from
7223 // wherever we got it to the vreg that other BB's will reference it as.
7224 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7225 // If we can, though, try to skip creating an unnecessary vreg.
7226 // FIXME: This isn't very clean... it would be nice to make this more
7227 // general. It's also subtly incompatible with the hacks FastISel
7229 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7230 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7231 FuncInfo->ValueMap[I] = Reg;
7235 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7236 FuncInfo->InitializeRegForValue(I);
7237 SDB->CopyToExportRegsIfNeeded(I);
7241 assert(i == InVals.size() && "Argument register count mismatch!");
7243 // Finally, if the target has anything special to do, allow it to do so.
7244 EmitFunctionEntryCode();
7247 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7248 /// ensure constants are generated when needed. Remember the virtual registers
7249 /// that need to be added to the Machine PHI nodes as input. We cannot just
7250 /// directly add them, because expansion might result in multiple MBB's for one
7251 /// BB. As such, the start of the BB might correspond to a different MBB than
7255 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7256 const TerminatorInst *TI = LLVMBB->getTerminator();
7258 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7260 // Check PHI nodes in successors that expect a value to be available from this
7262 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7263 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7264 if (!isa<PHINode>(SuccBB->begin())) continue;
7265 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7267 // If this terminator has multiple identical successors (common for
7268 // switches), only handle each succ once.
7269 if (!SuccsHandled.insert(SuccMBB).second)
7272 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7274 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7275 // nodes and Machine PHI nodes, but the incoming operands have not been
7277 for (BasicBlock::const_iterator I = SuccBB->begin();
7278 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7279 // Ignore dead phi's.
7280 if (PN->use_empty()) continue;
7283 if (PN->getType()->isEmptyTy())
7287 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7289 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7290 unsigned &RegOut = ConstantsOut[C];
7292 RegOut = FuncInfo.CreateRegs(C->getType());
7293 CopyValueToVirtualRegister(C, RegOut);
7297 DenseMap<const Value *, unsigned>::iterator I =
7298 FuncInfo.ValueMap.find(PHIOp);
7299 if (I != FuncInfo.ValueMap.end())
7302 assert(isa<AllocaInst>(PHIOp) &&
7303 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7304 "Didn't codegen value into a register!??");
7305 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7306 CopyValueToVirtualRegister(PHIOp, Reg);
7310 // Remember that this register needs to added to the machine PHI node as
7311 // the input for this MBB.
7312 SmallVector<EVT, 4> ValueVTs;
7313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7314 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7315 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7316 EVT VT = ValueVTs[vti];
7317 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7318 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7319 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7320 Reg += NumRegisters;
7325 ConstantsOut.clear();
7328 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7331 SelectionDAGBuilder::StackProtectorDescriptor::
7332 AddSuccessorMBB(const BasicBlock *BB,
7333 MachineBasicBlock *ParentMBB,
7335 MachineBasicBlock *SuccMBB) {
7336 // If SuccBB has not been created yet, create it.
7338 MachineFunction *MF = ParentMBB->getParent();
7339 MachineFunction::iterator BBI = ParentMBB;
7340 SuccMBB = MF->CreateMachineBasicBlock(BB);
7341 MF->insert(++BBI, SuccMBB);
7343 // Add it as a successor of ParentMBB.
7344 ParentMBB->addSuccessor(
7345 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7349 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7350 MachineFunction::iterator I = MBB;
7351 if (++I == FuncInfo.MF->end())
7356 /// During lowering new call nodes can be created (such as memset, etc.).
7357 /// Those will become new roots of the current DAG, but complications arise
7358 /// when they are tail calls. In such cases, the call lowering will update
7359 /// the root, but the builder still needs to know that a tail call has been
7360 /// lowered in order to avoid generating an additional return.
7361 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7362 // If the node is null, we do have a tail call.
7363 if (MaybeTC.getNode() != nullptr)
7364 DAG.setRoot(MaybeTC);
7369 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7370 unsigned *TotalCases, unsigned First,
7372 assert(Last >= First);
7373 assert(TotalCases[Last] >= TotalCases[First]);
7375 APInt LowCase = Clusters[First].Low->getValue();
7376 APInt HighCase = Clusters[Last].High->getValue();
7377 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7379 // FIXME: A range of consecutive cases has 100% density, but only requires one
7380 // comparison to lower. We should discriminate against such consecutive ranges
7383 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7384 uint64_t Range = Diff + 1;
7387 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7389 assert(NumCases < UINT64_MAX / 100);
7390 assert(Range >= NumCases);
7392 return NumCases * 100 >= Range * MinJumpTableDensity;
7395 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7396 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7397 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7400 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7401 unsigned First, unsigned Last,
7402 const SwitchInst *SI,
7403 MachineBasicBlock *DefaultMBB,
7404 CaseCluster &JTCluster) {
7405 assert(First <= Last);
7407 uint32_t Weight = 0;
7408 unsigned NumCmps = 0;
7409 std::vector<MachineBasicBlock*> Table;
7410 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7411 for (unsigned I = First; I <= Last; ++I) {
7412 assert(Clusters[I].Kind == CC_Range);
7413 Weight += Clusters[I].Weight;
7414 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7415 APInt Low = Clusters[I].Low->getValue();
7416 APInt High = Clusters[I].High->getValue();
7417 NumCmps += (Low == High) ? 1 : 2;
7419 // Fill the gap between this and the previous cluster.
7420 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7421 assert(PreviousHigh.slt(Low));
7422 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7423 for (uint64_t J = 0; J < Gap; J++)
7424 Table.push_back(DefaultMBB);
7426 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7427 for (uint64_t J = 0; J < ClusterSize; ++J)
7428 Table.push_back(Clusters[I].MBB);
7429 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7432 unsigned NumDests = JTWeights.size();
7433 if (isSuitableForBitTests(NumDests, NumCmps,
7434 Clusters[First].Low->getValue(),
7435 Clusters[Last].High->getValue())) {
7436 // Clusters[First..Last] should be lowered as bit tests instead.
7440 // Create the MBB that will load from and jump through the table.
7441 // Note: We create it here, but it's not inserted into the function yet.
7442 MachineFunction *CurMF = FuncInfo.MF;
7443 MachineBasicBlock *JumpTableMBB =
7444 CurMF->CreateMachineBasicBlock(SI->getParent());
7446 // Add successors. Note: use table order for determinism.
7447 SmallPtrSet<MachineBasicBlock *, 8> Done;
7448 for (MachineBasicBlock *Succ : Table) {
7449 if (Done.count(Succ))
7451 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7456 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7457 ->createJumpTableIndex(Table);
7459 // Set up the jump table info.
7460 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7461 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7462 Clusters[Last].High->getValue(), SI->getCondition(),
7464 JTCases.emplace_back(std::move(JTH), std::move(JT));
7466 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7467 JTCases.size() - 1, Weight);
7471 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7472 const SwitchInst *SI,
7473 MachineBasicBlock *DefaultMBB) {
7475 // Clusters must be non-empty, sorted, and only contain Range clusters.
7476 assert(!Clusters.empty());
7477 for (CaseCluster &C : Clusters)
7478 assert(C.Kind == CC_Range);
7479 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7480 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7484 if (!areJTsAllowed(TLI))
7487 const int64_t N = Clusters.size();
7488 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7490 // Split Clusters into minimum number of dense partitions. The algorithm uses
7491 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7492 // for the Case Statement'" (1994), but builds the MinPartitions array in
7493 // reverse order to make it easier to reconstruct the partitions in ascending
7494 // order. In the choice between two optimal partitionings, it picks the one
7495 // which yields more jump tables.
7497 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7498 SmallVector<unsigned, 8> MinPartitions(N);
7499 // LastElement[i] is the last element of the partition starting at i.
7500 SmallVector<unsigned, 8> LastElement(N);
7501 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7502 SmallVector<unsigned, 8> NumTables(N);
7503 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7504 SmallVector<unsigned, 8> TotalCases(N);
7506 for (unsigned i = 0; i < N; ++i) {
7507 APInt Hi = Clusters[i].High->getValue();
7508 APInt Lo = Clusters[i].Low->getValue();
7509 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7511 TotalCases[i] += TotalCases[i - 1];
7514 // Base case: There is only one way to partition Clusters[N-1].
7515 MinPartitions[N - 1] = 1;
7516 LastElement[N - 1] = N - 1;
7517 assert(MinJumpTableSize > 1);
7518 NumTables[N - 1] = 0;
7520 // Note: loop indexes are signed to avoid underflow.
7521 for (int64_t i = N - 2; i >= 0; i--) {
7522 // Find optimal partitioning of Clusters[i..N-1].
7523 // Baseline: Put Clusters[i] into a partition on its own.
7524 MinPartitions[i] = MinPartitions[i + 1] + 1;
7526 NumTables[i] = NumTables[i + 1];
7528 // Search for a solution that results in fewer partitions.
7529 for (int64_t j = N - 1; j > i; j--) {
7530 // Try building a partition from Clusters[i..j].
7531 if (isDense(Clusters, &TotalCases[0], i, j)) {
7532 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7533 bool IsTable = j - i + 1 >= MinJumpTableSize;
7534 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7536 // If this j leads to fewer partitions, or same number of partitions
7537 // with more lookup tables, it is a better partitioning.
7538 if (NumPartitions < MinPartitions[i] ||
7539 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7540 MinPartitions[i] = NumPartitions;
7542 NumTables[i] = Tables;
7548 // Iterate over the partitions, replacing some with jump tables in-place.
7549 unsigned DstIndex = 0;
7550 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7551 Last = LastElement[First];
7552 assert(Last >= First);
7553 assert(DstIndex <= First);
7554 unsigned NumClusters = Last - First + 1;
7556 CaseCluster JTCluster;
7557 if (NumClusters >= MinJumpTableSize &&
7558 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7559 Clusters[DstIndex++] = JTCluster;
7561 for (unsigned I = First; I <= Last; ++I)
7562 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7565 Clusters.resize(DstIndex);
7568 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7569 // FIXME: Using the pointer type doesn't seem ideal.
7570 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7571 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7575 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7578 const APInt &High) {
7579 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7580 // range of cases both require only one branch to lower. Just looking at the
7581 // number of clusters and destinations should be enough to decide whether to
7584 // To lower a range with bit tests, the range must fit the bitwidth of a
7586 if (!rangeFitsInWord(Low, High))
7589 // Decide whether it's profitable to lower this range with bit tests. Each
7590 // destination requires a bit test and branch, and there is an overall range
7591 // check branch. For a small number of clusters, separate comparisons might be
7592 // cheaper, and for many destinations, splitting the range might be better.
7593 return (NumDests == 1 && NumCmps >= 3) ||
7594 (NumDests == 2 && NumCmps >= 5) ||
7595 (NumDests == 3 && NumCmps >= 6);
7598 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7599 unsigned First, unsigned Last,
7600 const SwitchInst *SI,
7601 CaseCluster &BTCluster) {
7602 assert(First <= Last);
7606 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7607 unsigned NumCmps = 0;
7608 for (int64_t I = First; I <= Last; ++I) {
7609 assert(Clusters[I].Kind == CC_Range);
7610 Dests.set(Clusters[I].MBB->getNumber());
7611 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7613 unsigned NumDests = Dests.count();
7615 APInt Low = Clusters[First].Low->getValue();
7616 APInt High = Clusters[Last].High->getValue();
7617 assert(Low.slt(High));
7619 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7625 const int BitWidth =
7626 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7627 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7629 if (Low.isNonNegative() && High.slt(BitWidth)) {
7630 // Optimize the case where all the case values fit in a
7631 // word without having to subtract minValue. In this case,
7632 // we can optimize away the subtraction.
7633 LowBound = APInt::getNullValue(Low.getBitWidth());
7637 CmpRange = High - Low;
7641 uint32_t TotalWeight = 0;
7642 for (unsigned i = First; i <= Last; ++i) {
7643 // Find the CaseBits for this destination.
7645 for (j = 0; j < CBV.size(); ++j)
7646 if (CBV[j].BB == Clusters[i].MBB)
7648 if (j == CBV.size())
7649 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7650 CaseBits *CB = &CBV[j];
7652 // Update Mask, Bits and ExtraWeight.
7653 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7654 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7655 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7656 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7657 CB->Bits += Hi - Lo + 1;
7658 CB->ExtraWeight += Clusters[i].Weight;
7659 TotalWeight += Clusters[i].Weight;
7660 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7664 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7665 // Sort by weight first, number of bits second.
7666 if (a.ExtraWeight != b.ExtraWeight)
7667 return a.ExtraWeight > b.ExtraWeight;
7668 return a.Bits > b.Bits;
7671 for (auto &CB : CBV) {
7672 MachineBasicBlock *BitTestBB =
7673 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7674 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7676 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7677 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7678 nullptr, std::move(BTI));
7680 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7681 BitTestCases.size() - 1, TotalWeight);
7685 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7686 const SwitchInst *SI) {
7687 // Partition Clusters into as few subsets as possible, where each subset has a
7688 // range that fits in a machine word and has <= 3 unique destinations.
7691 // Clusters must be sorted and contain Range or JumpTable clusters.
7692 assert(!Clusters.empty());
7693 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7694 for (const CaseCluster &C : Clusters)
7695 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7696 for (unsigned i = 1; i < Clusters.size(); ++i)
7697 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7700 // If target does not have legal shift left, do not emit bit tests at all.
7701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7702 EVT PTy = TLI.getPointerTy();
7703 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7706 int BitWidth = PTy.getSizeInBits();
7707 const int64_t N = Clusters.size();
7709 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7710 SmallVector<unsigned, 8> MinPartitions(N);
7711 // LastElement[i] is the last element of the partition starting at i.
7712 SmallVector<unsigned, 8> LastElement(N);
7714 // FIXME: This might not be the best algorithm for finding bit test clusters.
7716 // Base case: There is only one way to partition Clusters[N-1].
7717 MinPartitions[N - 1] = 1;
7718 LastElement[N - 1] = N - 1;
7720 // Note: loop indexes are signed to avoid underflow.
7721 for (int64_t i = N - 2; i >= 0; --i) {
7722 // Find optimal partitioning of Clusters[i..N-1].
7723 // Baseline: Put Clusters[i] into a partition on its own.
7724 MinPartitions[i] = MinPartitions[i + 1] + 1;
7727 // Search for a solution that results in fewer partitions.
7728 // Note: the search is limited by BitWidth, reducing time complexity.
7729 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7730 // Try building a partition from Clusters[i..j].
7733 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7734 Clusters[j].High->getValue()))
7737 // Check nbr of destinations and cluster types.
7738 // FIXME: This works, but doesn't seem very efficient.
7739 bool RangesOnly = true;
7740 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7741 for (int64_t k = i; k <= j; k++) {
7742 if (Clusters[k].Kind != CC_Range) {
7746 Dests.set(Clusters[k].MBB->getNumber());
7748 if (!RangesOnly || Dests.count() > 3)
7751 // Check if it's a better partition.
7752 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7753 if (NumPartitions < MinPartitions[i]) {
7754 // Found a better partition.
7755 MinPartitions[i] = NumPartitions;
7761 // Iterate over the partitions, replacing with bit-test clusters in-place.
7762 unsigned DstIndex = 0;
7763 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7764 Last = LastElement[First];
7765 assert(First <= Last);
7766 assert(DstIndex <= First);
7768 CaseCluster BitTestCluster;
7769 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7770 Clusters[DstIndex++] = BitTestCluster;
7772 size_t NumClusters = Last - First + 1;
7773 std::memmove(&Clusters[DstIndex], &Clusters[First],
7774 sizeof(Clusters[0]) * NumClusters);
7775 DstIndex += NumClusters;
7778 Clusters.resize(DstIndex);
7781 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7782 MachineBasicBlock *SwitchMBB,
7783 MachineBasicBlock *DefaultMBB) {
7784 MachineFunction *CurMF = FuncInfo.MF;
7785 MachineBasicBlock *NextMBB = nullptr;
7786 MachineFunction::iterator BBI = W.MBB;
7787 if (++BBI != FuncInfo.MF->end())
7790 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7792 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7794 if (Size == 2 && W.MBB == SwitchMBB) {
7795 // If any two of the cases has the same destination, and if one value
7796 // is the same as the other, but has one bit unset that the other has set,
7797 // use bit manipulation to do two compares at once. For example:
7798 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7799 // TODO: This could be extended to merge any 2 cases in switches with 3
7801 // TODO: Handle cases where W.CaseBB != SwitchBB.
7802 CaseCluster &Small = *W.FirstCluster;
7803 CaseCluster &Big = *W.LastCluster;
7805 if (Small.Low == Small.High && Big.Low == Big.High &&
7806 Small.MBB == Big.MBB) {
7807 const APInt &SmallValue = Small.Low->getValue();
7808 const APInt &BigValue = Big.Low->getValue();
7810 // Check that there is only one bit different.
7811 APInt CommonBit = BigValue ^ SmallValue;
7812 if (CommonBit.isPowerOf2()) {
7813 SDValue CondLHS = getValue(Cond);
7814 EVT VT = CondLHS.getValueType();
7815 SDLoc DL = getCurSDLoc();
7817 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7818 DAG.getConstant(CommonBit, DL, VT));
7819 SDValue Cond = DAG.getSetCC(
7820 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7823 // Update successor info.
7824 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7825 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7826 addSuccessorWithWeight(
7827 SwitchMBB, DefaultMBB,
7828 // The default destination is the first successor in IR.
7829 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7832 // Insert the true branch.
7834 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7835 DAG.getBasicBlock(Small.MBB));
7836 // Insert the false branch.
7837 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7838 DAG.getBasicBlock(DefaultMBB));
7840 DAG.setRoot(BrCond);
7846 if (TM.getOptLevel() != CodeGenOpt::None) {
7847 // Order cases by weight so the most likely case will be checked first.
7848 std::sort(W.FirstCluster, W.LastCluster + 1,
7849 [](const CaseCluster &a, const CaseCluster &b) {
7850 return a.Weight > b.Weight;
7853 // Rearrange the case blocks so that the last one falls through if possible
7854 // without without changing the order of weights.
7855 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7857 if (I->Weight > W.LastCluster->Weight)
7859 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7860 std::swap(*I, *W.LastCluster);
7866 // Compute total weight.
7867 uint32_t UnhandledWeights = 0;
7868 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7869 UnhandledWeights += I->Weight;
7870 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7873 MachineBasicBlock *CurMBB = W.MBB;
7874 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7875 MachineBasicBlock *Fallthrough;
7876 if (I == W.LastCluster) {
7877 // For the last cluster, fall through to the default destination.
7878 Fallthrough = DefaultMBB;
7880 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7881 CurMF->insert(BBI, Fallthrough);
7882 // Put Cond in a virtual register to make it available from the new blocks.
7883 ExportFromCurrentBlock(Cond);
7887 case CC_JumpTable: {
7888 // FIXME: Optimize away range check based on pivot comparisons.
7889 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7890 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7892 // The jump block hasn't been inserted yet; insert it here.
7893 MachineBasicBlock *JumpMBB = JT->MBB;
7894 CurMF->insert(BBI, JumpMBB);
7895 addSuccessorWithWeight(CurMBB, Fallthrough);
7896 addSuccessorWithWeight(CurMBB, JumpMBB);
7898 // The jump table header will be inserted in our current block, do the
7899 // range check, and fall through to our fallthrough block.
7900 JTH->HeaderBB = CurMBB;
7901 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7903 // If we're in the right place, emit the jump table header right now.
7904 if (CurMBB == SwitchMBB) {
7905 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7906 JTH->Emitted = true;
7911 // FIXME: Optimize away range check based on pivot comparisons.
7912 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7914 // The bit test blocks haven't been inserted yet; insert them here.
7915 for (BitTestCase &BTC : BTB->Cases)
7916 CurMF->insert(BBI, BTC.ThisBB);
7918 // Fill in fields of the BitTestBlock.
7919 BTB->Parent = CurMBB;
7920 BTB->Default = Fallthrough;
7922 // If we're in the right place, emit the bit test header header right now.
7923 if (CurMBB ==SwitchMBB) {
7924 visitBitTestHeader(*BTB, SwitchMBB);
7925 BTB->Emitted = true;
7930 const Value *RHS, *LHS, *MHS;
7932 if (I->Low == I->High) {
7933 // Check Cond == I->Low.
7939 // Check I->Low <= Cond <= I->High.
7946 // The false weight is the sum of all unhandled cases.
7947 UnhandledWeights -= I->Weight;
7948 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7951 if (CurMBB == SwitchMBB)
7952 visitSwitchCase(CB, SwitchMBB);
7954 SwitchCases.push_back(CB);
7959 CurMBB = Fallthrough;
7963 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7964 const SwitchWorkListItem &W,
7966 MachineBasicBlock *SwitchMBB) {
7967 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7968 "Clusters not sorted?");
7970 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
7972 // Balance the tree based on branch weights to create a near-optimal (in terms
7973 // of search time given key frequency) binary search tree. See e.g. Kurt
7974 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
7975 CaseClusterIt LastLeft = W.FirstCluster;
7976 CaseClusterIt FirstRight = W.LastCluster;
7977 uint32_t LeftWeight = LastLeft->Weight;
7978 uint32_t RightWeight = FirstRight->Weight;
7980 // Move LastLeft and FirstRight towards each other from opposite directions to
7981 // find a partitioning of the clusters which balances the weight on both
7982 // sides. If LeftWeight and RightWeight are equal, alternate which side is
7983 // taken to ensure 0-weight nodes are distributed evenly.
7985 while (LastLeft + 1 < FirstRight) {
7986 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
7987 LeftWeight += (++LastLeft)->Weight;
7989 RightWeight += (--FirstRight)->Weight;
7992 assert(LastLeft + 1 == FirstRight);
7993 assert(LastLeft >= W.FirstCluster);
7994 assert(FirstRight <= W.LastCluster);
7996 // Use the first element on the right as pivot since we will make less-than
7997 // comparisons against it.
7998 CaseClusterIt PivotCluster = FirstRight;
7999 assert(PivotCluster > W.FirstCluster);
8000 assert(PivotCluster <= W.LastCluster);
8002 CaseClusterIt FirstLeft = W.FirstCluster;
8003 CaseClusterIt LastRight = W.LastCluster;
8005 const ConstantInt *Pivot = PivotCluster->Low;
8007 // New blocks will be inserted immediately after the current one.
8008 MachineFunction::iterator BBI = W.MBB;
8011 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8012 // we can branch to its destination directly if it's squeezed exactly in
8013 // between the known lower bound and Pivot - 1.
8014 MachineBasicBlock *LeftMBB;
8015 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8016 FirstLeft->Low == W.GE &&
8017 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8018 LeftMBB = FirstLeft->MBB;
8020 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8021 FuncInfo.MF->insert(BBI, LeftMBB);
8022 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8023 // Put Cond in a virtual register to make it available from the new blocks.
8024 ExportFromCurrentBlock(Cond);
8027 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8028 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8029 // directly if RHS.High equals the current upper bound.
8030 MachineBasicBlock *RightMBB;
8031 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8032 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8033 RightMBB = FirstRight->MBB;
8035 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8036 FuncInfo.MF->insert(BBI, RightMBB);
8037 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8038 // Put Cond in a virtual register to make it available from the new blocks.
8039 ExportFromCurrentBlock(Cond);
8042 // Create the CaseBlock record that will be used to lower the branch.
8043 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8044 LeftWeight, RightWeight);
8046 if (W.MBB == SwitchMBB)
8047 visitSwitchCase(CB, SwitchMBB);
8049 SwitchCases.push_back(CB);
8052 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8053 // Extract cases from the switch.
8054 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8055 CaseClusterVector Clusters;
8056 Clusters.reserve(SI.getNumCases());
8057 for (auto I : SI.cases()) {
8058 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8059 const ConstantInt *CaseVal = I.getCaseValue();
8061 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8062 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8065 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8067 // Cluster adjacent cases with the same destination. We do this at all
8068 // optimization levels because it's cheap to do and will make codegen faster
8069 // if there are many clusters.
8070 sortAndRangeify(Clusters);
8072 if (TM.getOptLevel() != CodeGenOpt::None) {
8073 // Replace an unreachable default with the most popular destination.
8074 // FIXME: Exploit unreachable default more aggressively.
8075 bool UnreachableDefault =
8076 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8077 if (UnreachableDefault && !Clusters.empty()) {
8078 DenseMap<const BasicBlock *, unsigned> Popularity;
8079 unsigned MaxPop = 0;
8080 const BasicBlock *MaxBB = nullptr;
8081 for (auto I : SI.cases()) {
8082 const BasicBlock *BB = I.getCaseSuccessor();
8083 if (++Popularity[BB] > MaxPop) {
8084 MaxPop = Popularity[BB];
8089 assert(MaxPop > 0 && MaxBB);
8090 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8092 // Remove cases that were pointing to the destination that is now the
8094 CaseClusterVector New;
8095 New.reserve(Clusters.size());
8096 for (CaseCluster &CC : Clusters) {
8097 if (CC.MBB != DefaultMBB)
8100 Clusters = std::move(New);
8104 // If there is only the default destination, jump there directly.
8105 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8106 if (Clusters.empty()) {
8107 SwitchMBB->addSuccessor(DefaultMBB);
8108 if (DefaultMBB != NextBlock(SwitchMBB)) {
8109 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8110 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8115 if (TM.getOptLevel() != CodeGenOpt::None) {
8116 findJumpTables(Clusters, &SI, DefaultMBB);
8117 findBitTestClusters(Clusters, &SI);
8122 dbgs() << "Case clusters: ";
8123 for (const CaseCluster &C : Clusters) {
8124 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8125 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8127 C.Low->getValue().print(dbgs(), true);
8128 if (C.Low != C.High) {
8130 C.High->getValue().print(dbgs(), true);
8137 assert(!Clusters.empty());
8138 SwitchWorkList WorkList;
8139 CaseClusterIt First = Clusters.begin();
8140 CaseClusterIt Last = Clusters.end() - 1;
8141 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8143 while (!WorkList.empty()) {
8144 SwitchWorkListItem W = WorkList.back();
8145 WorkList.pop_back();
8146 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8148 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8149 // For optimized builds, lower large range as a balanced binary tree.
8150 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8154 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);