1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetIntrinsicInfo.h"
58 #include "llvm/Target/TargetLibraryInfo.h"
59 #include "llvm/Target/TargetLowering.h"
60 #include "llvm/Target/TargetOptions.h"
61 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 /// LimitFloatPrecision - Generate low-precision inline sequences for
66 /// some float libcalls (6, 8 or 12 bits).
67 static unsigned LimitFloatPrecision;
69 static cl::opt<unsigned, true>
70 LimitFPPrecision("limit-float-precision",
71 cl::desc("Generate low-precision inline sequences "
72 "for some float libcalls"),
73 cl::location(LimitFloatPrecision),
76 // Limit the width of DAG chains. This is important in general to prevent
77 // prevent DAG-based analysis from blowing up. For example, alias analysis and
78 // load clustering may not complete in reasonable time. It is difficult to
79 // recognize and avoid this situation within each individual analysis, and
80 // future analyses are likely to have the same behavior. Limiting DAG width is
81 // the safe approach, and will be especially important with global DAGs.
83 // MaxParallelChains default is arbitrarily high to avoid affecting
84 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
85 // sequence over this should have been converted to llvm.memcpy by the
86 // frontend. It easy to induce this behavior with .ll code such as:
87 // %buffer = alloca [4096 x i8]
88 // %data = load [4096 x i8]* %argPtr
89 // store [4096 x i8] %data, [4096 x i8]* %buffer
90 static const unsigned MaxParallelChains = 64;
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
93 const SDValue *Parts, unsigned NumParts,
94 MVT PartVT, EVT ValueVT, const Value *V);
96 /// getCopyFromParts - Create a value that contains the specified legal parts
97 /// combined into the value they represent. If the parts combine to a type
98 /// larger then ValueVT then AssertOp can be used to specify whether the extra
99 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
100 /// (ISD::AssertSext).
101 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts,
103 unsigned NumParts, MVT PartVT, EVT ValueVT,
105 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
106 if (ValueVT.isVector())
107 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
110 assert(NumParts > 0 && "No parts to assemble!");
111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
112 SDValue Val = Parts[0];
115 // Assemble the value from multiple parts.
116 if (ValueVT.isInteger()) {
117 unsigned PartBits = PartVT.getSizeInBits();
118 unsigned ValueBits = ValueVT.getSizeInBits();
120 // Assemble the power of 2 part.
121 unsigned RoundParts = NumParts & (NumParts - 1) ?
122 1 << Log2_32(NumParts) : NumParts;
123 unsigned RoundBits = PartBits * RoundParts;
124 EVT RoundVT = RoundBits == ValueBits ?
125 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
128 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
130 if (RoundParts > 2) {
131 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
133 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
134 RoundParts / 2, PartVT, HalfVT, V);
136 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
137 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
140 if (TLI.isBigEndian())
143 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
145 if (RoundParts < NumParts) {
146 // Assemble the trailing non-power-of-2 part.
147 unsigned OddParts = NumParts - RoundParts;
148 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
149 Hi = getCopyFromParts(DAG, DL,
150 Parts + RoundParts, OddParts, PartVT, OddVT, V);
152 // Combine the round and odd parts.
154 if (TLI.isBigEndian())
156 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
157 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
158 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
159 DAG.getConstant(Lo.getValueType().getSizeInBits(),
160 TLI.getPointerTy()));
161 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
162 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
164 } else if (PartVT.isFloatingPoint()) {
165 // FP split into multiple FP parts (for ppcf128)
166 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
171 if (TLI.isBigEndian())
173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
175 // FP split into integer parts (soft fp)
176 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
177 !PartVT.isVector() && "Unexpected split");
178 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
179 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
183 // There is now one part, held in Val. Correct it to match ValueVT.
184 EVT PartEVT = Val.getValueType();
186 if (PartEVT == ValueVT)
189 if (PartEVT.isInteger() && ValueVT.isInteger()) {
190 if (ValueVT.bitsLT(PartEVT)) {
191 // For a truncate, see if we have any information to
192 // indicate whether the truncated bits will always be
193 // zero or sign-extension.
194 if (AssertOp != ISD::DELETED_NODE)
195 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
196 DAG.getValueType(ValueVT));
197 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
199 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
202 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
203 // FP_ROUND's are always exact here.
204 if (ValueVT.bitsLT(Val.getValueType()))
205 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
206 DAG.getTargetConstant(1, TLI.getPointerTy()));
208 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
211 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
212 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
214 llvm_unreachable("Unknown mismatch!");
217 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
218 const Twine &ErrMsg) {
219 const Instruction *I = dyn_cast_or_null<Instruction>(V);
221 return Ctx.emitError(ErrMsg);
223 const char *AsmError = ", possible invalid constraint for vector type";
224 if (const CallInst *CI = dyn_cast<CallInst>(I))
225 if (isa<InlineAsm>(CI->getCalledValue()))
226 return Ctx.emitError(I, ErrMsg + AsmError);
228 return Ctx.emitError(I, ErrMsg);
231 /// getCopyFromPartsVector - Create a value that contains the specified legal
232 /// parts combined into the value they represent. If the parts combine to a
233 /// type larger then ValueVT then AssertOp can be used to specify whether the
234 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
235 /// ValueVT (ISD::AssertSext).
236 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
237 const SDValue *Parts, unsigned NumParts,
238 MVT PartVT, EVT ValueVT, const Value *V) {
239 assert(ValueVT.isVector() && "Not a vector value");
240 assert(NumParts > 0 && "No parts to assemble!");
241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
242 SDValue Val = Parts[0];
244 // Handle a multi-element vector.
248 unsigned NumIntermediates;
250 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
251 NumIntermediates, RegisterVT);
252 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
253 NumParts = NumRegs; // Silence a compiler warning.
254 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
255 assert(RegisterVT == Parts[0].getSimpleValueType() &&
256 "Part type doesn't match part!");
258 // Assemble the parts into intermediate operands.
259 SmallVector<SDValue, 8> Ops(NumIntermediates);
260 if (NumIntermediates == NumParts) {
261 // If the register was not expanded, truncate or copy the value,
263 for (unsigned i = 0; i != NumParts; ++i)
264 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
265 PartVT, IntermediateVT, V);
266 } else if (NumParts > 0) {
267 // If the intermediate type was expanded, build the intermediate
268 // operands from the parts.
269 assert(NumParts % NumIntermediates == 0 &&
270 "Must expand into a divisible number of parts!");
271 unsigned Factor = NumParts / NumIntermediates;
272 for (unsigned i = 0; i != NumIntermediates; ++i)
273 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
274 PartVT, IntermediateVT, V);
277 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
278 // intermediate operands.
279 Val = DAG.getNode(IntermediateVT.isVector() ?
280 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
281 ValueVT, &Ops[0], NumIntermediates);
284 // There is now one part, held in Val. Correct it to match ValueVT.
285 EVT PartEVT = Val.getValueType();
287 if (PartEVT == ValueVT)
290 if (PartEVT.isVector()) {
291 // If the element type of the source/dest vectors are the same, but the
292 // parts vector has more elements than the value vector, then we have a
293 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
295 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
296 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
297 "Cannot narrow, it would be a lossy transformation");
298 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
299 DAG.getConstant(0, TLI.getVectorIdxTy()));
302 // Vector/Vector bitcast.
303 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
306 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
307 "Cannot handle this kind of promotion");
308 // Promoted vector extract
309 bool Smaller = ValueVT.bitsLE(PartEVT);
310 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
315 // Trivial bitcast if the types are the same size and the destination
316 // vector type is legal.
317 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
318 TLI.isTypeLegal(ValueVT))
319 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
321 // Handle cases such as i8 -> <1 x i1>
322 if (ValueVT.getVectorNumElements() != 1) {
323 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
324 "non-trivial scalar-to-vector conversion");
325 return DAG.getUNDEF(ValueVT);
328 if (ValueVT.getVectorNumElements() == 1 &&
329 ValueVT.getVectorElementType() != PartEVT) {
330 bool Smaller = ValueVT.bitsLE(PartEVT);
331 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
332 DL, ValueVT.getScalarType(), Val);
335 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
338 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
339 SDValue Val, SDValue *Parts, unsigned NumParts,
340 MVT PartVT, const Value *V);
342 /// getCopyToParts - Create a series of nodes that contain the specified value
343 /// split into legal parts. If the parts contain more bits than Val, then, for
344 /// integers, ExtendKind can be used to specify how to generate the extra bits.
345 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
346 SDValue Val, SDValue *Parts, unsigned NumParts,
347 MVT PartVT, const Value *V,
348 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
349 EVT ValueVT = Val.getValueType();
351 // Handle the vector case separately.
352 if (ValueVT.isVector())
353 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
356 unsigned PartBits = PartVT.getSizeInBits();
357 unsigned OrigNumParts = NumParts;
358 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
363 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
364 EVT PartEVT = PartVT;
365 if (PartEVT == ValueVT) {
366 assert(NumParts == 1 && "No-op copy with multiple parts!");
371 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
372 // If the parts cover more bits than the value has, promote the value.
373 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
374 assert(NumParts == 1 && "Do not know what to promote to!");
375 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
377 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
378 ValueVT.isInteger() &&
379 "Unknown mismatch!");
380 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
381 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
382 if (PartVT == MVT::x86mmx)
383 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
385 } else if (PartBits == ValueVT.getSizeInBits()) {
386 // Different types of the same size.
387 assert(NumParts == 1 && PartEVT != ValueVT);
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
389 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
390 // If the parts cover less bits than value has, truncate the value.
391 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
392 ValueVT.isInteger() &&
393 "Unknown mismatch!");
394 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
395 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
396 if (PartVT == MVT::x86mmx)
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
400 // The value may have changed - recompute ValueVT.
401 ValueVT = Val.getValueType();
402 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
403 "Failed to tile the value with PartVT!");
406 if (PartEVT != ValueVT)
407 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
408 "scalar-to-vector conversion failed");
414 // Expand the value into multiple parts.
415 if (NumParts & (NumParts - 1)) {
416 // The number of parts is not a power of 2. Split off and copy the tail.
417 assert(PartVT.isInteger() && ValueVT.isInteger() &&
418 "Do not know what to expand to!");
419 unsigned RoundParts = 1 << Log2_32(NumParts);
420 unsigned RoundBits = RoundParts * PartBits;
421 unsigned OddParts = NumParts - RoundParts;
422 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
423 DAG.getIntPtrConstant(RoundBits));
424 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
426 if (TLI.isBigEndian())
427 // The odd parts were reversed by getCopyToParts - unreverse them.
428 std::reverse(Parts + RoundParts, Parts + NumParts);
430 NumParts = RoundParts;
431 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
432 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
435 // The number of parts is a power of 2. Repeatedly bisect the value using
437 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
438 EVT::getIntegerVT(*DAG.getContext(),
439 ValueVT.getSizeInBits()),
442 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
443 for (unsigned i = 0; i < NumParts; i += StepSize) {
444 unsigned ThisBits = StepSize * PartBits / 2;
445 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
446 SDValue &Part0 = Parts[i];
447 SDValue &Part1 = Parts[i+StepSize/2];
449 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
450 ThisVT, Part0, DAG.getIntPtrConstant(1));
451 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(0));
454 if (ThisBits == PartBits && ThisVT != PartVT) {
455 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
456 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
461 if (TLI.isBigEndian())
462 std::reverse(Parts, Parts + OrigNumParts);
466 /// getCopyToPartsVector - Create a series of nodes that contain the specified
467 /// value split into legal parts.
468 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
469 SDValue Val, SDValue *Parts, unsigned NumParts,
470 MVT PartVT, const Value *V) {
471 EVT ValueVT = Val.getValueType();
472 assert(ValueVT.isVector() && "Not a vector");
473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
476 EVT PartEVT = PartVT;
477 if (PartEVT == ValueVT) {
479 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
480 // Bitconvert vector->vector case.
481 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
482 } else if (PartVT.isVector() &&
483 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
484 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
485 EVT ElementVT = PartVT.getVectorElementType();
486 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
488 SmallVector<SDValue, 16> Ops;
489 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
490 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
491 ElementVT, Val, DAG.getConstant(i,
492 TLI.getVectorIdxTy())));
494 for (unsigned i = ValueVT.getVectorNumElements(),
495 e = PartVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getUNDEF(ElementVT));
498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
500 // FIXME: Use CONCAT for 2x -> 4x.
502 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
504 } else if (PartVT.isVector() &&
505 PartEVT.getVectorElementType().bitsGE(
506 ValueVT.getVectorElementType()) &&
507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509 // Promoted vector extract
510 bool Smaller = PartEVT.bitsLE(ValueVT);
511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
514 // Vector -> scalar conversion.
515 assert(ValueVT.getVectorNumElements() == 1 &&
516 "Only trivial vector-to-scalar conversions should get here!");
517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
520 bool Smaller = ValueVT.bitsLE(PartVT);
521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
529 // Handle a multi-element vector.
532 unsigned NumIntermediates;
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 NumIntermediates, RegisterVT);
536 unsigned NumElements = ValueVT.getVectorNumElements();
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542 // Split the vector into intermediate operands.
543 SmallVector<SDValue, 8> Ops(NumIntermediates);
544 for (unsigned i = 0; i != NumIntermediates; ++i) {
545 if (IntermediateVT.isVector())
546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 DAG.getConstant(i * (NumElements / NumIntermediates),
549 TLI.getVectorIdxTy()));
551 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
553 DAG.getConstant(i, TLI.getVectorIdxTy()));
556 // Split the intermediate operands into legal parts.
557 if (NumParts == NumIntermediates) {
558 // If the register was not expanded, promote or copy the value,
560 for (unsigned i = 0; i != NumParts; ++i)
561 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
562 } else if (NumParts > 0) {
563 // If the intermediate type was expanded, split each the value into
565 assert(NumParts % NumIntermediates == 0 &&
566 "Must expand into a divisible number of parts!");
567 unsigned Factor = NumParts / NumIntermediates;
568 for (unsigned i = 0; i != NumIntermediates; ++i)
569 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
574 /// RegsForValue - This struct represents the registers (physical or virtual)
575 /// that a particular set of values is assigned, and the type information
576 /// about the value. The most common situation is to represent one value at a
577 /// time, but struct or array values are handled element-wise as multiple
578 /// values. The splitting of aggregates is performed recursively, so that we
579 /// never have aggregate-typed registers. The values at this point do not
580 /// necessarily have legal types, so each value may require one or more
581 /// registers of some legal type.
583 struct RegsForValue {
584 /// ValueVTs - The value types of the values, which may not be legal, and
585 /// may need be promoted or synthesized from one or more registers.
587 SmallVector<EVT, 4> ValueVTs;
589 /// RegVTs - The value types of the registers. This is the same size as
590 /// ValueVTs and it records, for each value, what the type of the assigned
591 /// register or registers are. (Individual values are never synthesized
592 /// from more than one type of register.)
594 /// With virtual registers, the contents of RegVTs is redundant with TLI's
595 /// getRegisterType member function, however when with physical registers
596 /// it is necessary to have a separate record of the types.
598 SmallVector<MVT, 4> RegVTs;
600 /// Regs - This list holds the registers assigned to the values.
601 /// Each legal or promoted value requires one register, and each
602 /// expanded value requires multiple registers.
604 SmallVector<unsigned, 4> Regs;
608 RegsForValue(const SmallVector<unsigned, 4> ®s,
609 MVT regvt, EVT valuevt)
610 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
612 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
613 unsigned Reg, Type *Ty) {
614 ComputeValueVTs(tli, Ty, ValueVTs);
616 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
617 EVT ValueVT = ValueVTs[Value];
618 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
619 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
620 for (unsigned i = 0; i != NumRegs; ++i)
621 Regs.push_back(Reg + i);
622 RegVTs.push_back(RegisterVT);
627 /// append - Add the specified values to this one.
628 void append(const RegsForValue &RHS) {
629 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
630 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
631 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
634 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
635 /// this value and returns the result as a ValueVTs value. This uses
636 /// Chain/Flag as the input and updates them for the output Chain/Flag.
637 /// If the Flag pointer is NULL, no flag is used.
638 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
640 SDValue &Chain, SDValue *Flag,
641 const Value *V = 0) const;
643 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
644 /// specified value into the registers specified by this object. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
648 SDValue &Chain, SDValue *Flag, const Value *V) const;
650 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
651 /// operand list. This adds the code marker, matching input operand index
652 /// (if applicable), and includes the number of values added into it.
653 void AddInlineAsmOperands(unsigned Kind,
654 bool HasMatching, unsigned MatchingIdx,
656 std::vector<SDValue> &Ops) const;
660 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
661 /// this value and returns the result as a ValueVT value. This uses
662 /// Chain/Flag as the input and updates them for the output Chain/Flag.
663 /// If the Flag pointer is NULL, no flag is used.
664 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
665 FunctionLoweringInfo &FuncInfo,
667 SDValue &Chain, SDValue *Flag,
668 const Value *V) const {
669 // A Value with type {} or [0 x %t] needs no registers.
670 if (ValueVTs.empty())
673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
675 // Assemble the legal parts into the final values.
676 SmallVector<SDValue, 4> Values(ValueVTs.size());
677 SmallVector<SDValue, 8> Parts;
678 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
679 // Copy the legal parts from the registers.
680 EVT ValueVT = ValueVTs[Value];
681 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
682 MVT RegisterVT = RegVTs[Value];
684 Parts.resize(NumRegs);
685 for (unsigned i = 0; i != NumRegs; ++i) {
688 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
690 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
691 *Flag = P.getValue(2);
694 Chain = P.getValue(1);
697 // If the source register was virtual and if we know something about it,
698 // add an assert node.
699 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
700 !RegisterVT.isInteger() || RegisterVT.isVector())
703 const FunctionLoweringInfo::LiveOutInfo *LOI =
704 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
708 unsigned RegSize = RegisterVT.getSizeInBits();
709 unsigned NumSignBits = LOI->NumSignBits;
710 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
712 if (NumZeroBits == RegSize) {
713 // The current value is a zero.
714 // Explicitly express that as it would be easier for
715 // optimizations to kick in.
716 Parts[i] = DAG.getConstant(0, RegisterVT);
720 // FIXME: We capture more information than the dag can represent. For
721 // now, just use the tightest assertzext/assertsext possible.
723 EVT FromVT(MVT::Other);
724 if (NumSignBits == RegSize)
725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
726 else if (NumZeroBits >= RegSize-1)
727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
728 else if (NumSignBits > RegSize-8)
729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
730 else if (NumZeroBits >= RegSize-8)
731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
732 else if (NumSignBits > RegSize-16)
733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
734 else if (NumZeroBits >= RegSize-16)
735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
736 else if (NumSignBits > RegSize-32)
737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
738 else if (NumZeroBits >= RegSize-32)
739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
743 // Add an assertion node.
744 assert(FromVT != MVT::Other);
745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
746 RegisterVT, P, DAG.getValueType(FromVT));
749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
750 NumRegs, RegisterVT, ValueVT, V);
755 return DAG.getNode(ISD::MERGE_VALUES, dl,
756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
757 &Values[0], ValueVTs.size());
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
842 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
843 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
844 MVT RegisterVT = RegVTs[Value];
845 for (unsigned i = 0; i != NumRegs; ++i) {
846 assert(Reg < Regs.size() && "Mismatch in # registers expected");
847 unsigned TheReg = Regs[Reg++];
848 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
850 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
851 // If we clobbered the stack pointer, MFI should know about it.
852 assert(DAG.getMachineFunction().getFrameInfo()->
853 hasInlineAsmWithSPAdjust());
859 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
860 const TargetLibraryInfo *li) {
864 DL = DAG.getTarget().getDataLayout();
865 Context = DAG.getContext();
866 LPadToCallSiteMap.clear();
869 /// clear - Clear out the current SelectionDAG and the associated
870 /// state and prepare this SelectionDAGBuilder object to be used
871 /// for a new block. This doesn't clear out information about
872 /// additional blocks that are needed to complete switch lowering
873 /// or PHI node updating; that information is cleared out as it is
875 void SelectionDAGBuilder::clear() {
877 UnusedArgNodeMap.clear();
878 PendingLoads.clear();
879 PendingExports.clear();
882 SDNodeOrder = LowestSDNodeOrder;
885 /// clearDanglingDebugInfo - Clear the dangling debug information
886 /// map. This function is separated from the clear so that debug
887 /// information that is dangling in a basic block can be properly
888 /// resolved in a different basic block. This allows the
889 /// SelectionDAG to resolve dangling debug information attached
891 void SelectionDAGBuilder::clearDanglingDebugInfo() {
892 DanglingDebugInfoMap.clear();
895 /// getRoot - Return the current virtual root of the Selection DAG,
896 /// flushing any PendingLoad items. This must be done before emitting
897 /// a store or any other node that may need to be ordered after any
898 /// prior load instructions.
900 SDValue SelectionDAGBuilder::getRoot() {
901 if (PendingLoads.empty())
902 return DAG.getRoot();
904 if (PendingLoads.size() == 1) {
905 SDValue Root = PendingLoads[0];
907 PendingLoads.clear();
911 // Otherwise, we have to make a token factor node.
912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
913 &PendingLoads[0], PendingLoads.size());
914 PendingLoads.clear();
919 /// getControlRoot - Similar to getRoot, but instead of flushing all the
920 /// PendingLoad items, flush all the PendingExports items. It is necessary
921 /// to do this before emitting a terminator instruction.
923 SDValue SelectionDAGBuilder::getControlRoot() {
924 SDValue Root = DAG.getRoot();
926 if (PendingExports.empty())
929 // Turn all of the CopyToReg chains into one factored node.
930 if (Root.getOpcode() != ISD::EntryToken) {
931 unsigned i = 0, e = PendingExports.size();
932 for (; i != e; ++i) {
933 assert(PendingExports[i].getNode()->getNumOperands() > 1);
934 if (PendingExports[i].getNode()->getOperand(0) == Root)
935 break; // Don't add the root if we already indirectly depend on it.
939 PendingExports.push_back(Root);
942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 PendingExports.size());
945 PendingExports.clear();
950 void SelectionDAGBuilder::visit(const Instruction &I) {
951 // Set up outgoing PHI node register values before emitting the terminator.
952 if (isa<TerminatorInst>(&I))
953 HandlePHINodesInSuccessorBlocks(I.getParent());
959 visit(I.getOpcode(), I);
961 if (!isa<TerminatorInst>(&I) && !HasTailCall)
962 CopyToExportRegsIfNeeded(&I);
967 void SelectionDAGBuilder::visitPHI(const PHINode &) {
968 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
971 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
972 // Note: this doesn't use InstVisitor, because it has to work with
973 // ConstantExpr's in addition to instructions.
975 default: llvm_unreachable("Unknown instruction type encountered!");
976 // Build the switch statement using the Instruction.def file.
977 #define HANDLE_INST(NUM, OPCODE, CLASS) \
978 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
979 #include "llvm/IR/Instruction.def"
983 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
984 // generate the debug data structures now that we've seen its definition.
985 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
987 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
989 const DbgValueInst *DI = DDI.getDI();
990 DebugLoc dl = DDI.getdl();
991 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
992 MDNode *Variable = DI->getVariable();
993 uint64_t Offset = DI->getOffset();
996 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
997 SDV = DAG.getDbgValue(Variable, Val.getNode(),
998 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
999 DAG.AddDbgValue(SDV, Val.getNode(), false);
1002 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1003 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1007 /// getValue - Return an SDValue for the given Value.
1008 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1009 // If we already have an SDValue for this value, use it. It's important
1010 // to do this first, so that we don't create a CopyFromReg if we already
1011 // have a regular SDValue.
1012 SDValue &N = NodeMap[V];
1013 if (N.getNode()) return N;
1015 // If there's a virtual register allocated and initialized for this
1017 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1018 if (It != FuncInfo.ValueMap.end()) {
1019 unsigned InReg = It->second;
1020 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1021 InReg, V->getType());
1022 SDValue Chain = DAG.getEntryNode();
1023 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1024 resolveDanglingDebugInfo(V, N);
1028 // Otherwise create a new SDValue and remember it.
1029 SDValue Val = getValueImpl(V);
1031 resolveDanglingDebugInfo(V, Val);
1035 /// getNonRegisterValue - Return an SDValue for the given Value, but
1036 /// don't look in FuncInfo.ValueMap for a virtual register.
1037 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1038 // If we already have an SDValue for this value, use it.
1039 SDValue &N = NodeMap[V];
1040 if (N.getNode()) return N;
1042 // Otherwise create a new SDValue and remember it.
1043 SDValue Val = getValueImpl(V);
1045 resolveDanglingDebugInfo(V, Val);
1049 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1050 /// Create an SDValue for the given value.
1051 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1052 const TargetLowering *TLI = TM.getTargetLowering();
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI->getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1063 if (isa<ConstantPointerNull>(C)) {
1064 unsigned AS = V->getType()->getPointerAddressSpace();
1065 return DAG.getConstant(0, TLI->getPointerTy(AS));
1068 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1069 return DAG.getConstantFP(*CFP, VT);
1071 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1072 return DAG.getUNDEF(VT);
1074 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1075 visit(CE->getOpcode(), *CE);
1076 SDValue N1 = NodeMap[V];
1077 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1081 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1082 SmallVector<SDValue, 4> Constants;
1083 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1085 SDNode *Val = getValue(*OI).getNode();
1086 // If the operand is an empty aggregate, there are no values.
1088 // Add each leaf value from the operand to the Constants list
1089 // to form a flattened list of all the values.
1090 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1091 Constants.push_back(SDValue(Val, i));
1094 return DAG.getMergeValues(&Constants[0], Constants.size(),
1098 if (const ConstantDataSequential *CDS =
1099 dyn_cast<ConstantDataSequential>(C)) {
1100 SmallVector<SDValue, 4> Ops;
1101 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1102 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1103 // Add each leaf value from the operand to the Constants list
1104 // to form a flattened list of all the values.
1105 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1106 Ops.push_back(SDValue(Val, i));
1109 if (isa<ArrayType>(CDS->getType()))
1110 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1111 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1112 VT, &Ops[0], Ops.size());
1115 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1116 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1117 "Unknown struct or array constant!");
1119 SmallVector<EVT, 4> ValueVTs;
1120 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1121 unsigned NumElts = ValueVTs.size();
1123 return SDValue(); // empty struct
1124 SmallVector<SDValue, 4> Constants(NumElts);
1125 for (unsigned i = 0; i != NumElts; ++i) {
1126 EVT EltVT = ValueVTs[i];
1127 if (isa<UndefValue>(C))
1128 Constants[i] = DAG.getUNDEF(EltVT);
1129 else if (EltVT.isFloatingPoint())
1130 Constants[i] = DAG.getConstantFP(0, EltVT);
1132 Constants[i] = DAG.getConstant(0, EltVT);
1135 return DAG.getMergeValues(&Constants[0], NumElts,
1139 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1140 return DAG.getBlockAddress(BA, VT);
1142 VectorType *VecTy = cast<VectorType>(V->getType());
1143 unsigned NumElements = VecTy->getNumElements();
1145 // Now that we know the number and type of the elements, get that number of
1146 // elements into the Ops array based on what kind of constant it is.
1147 SmallVector<SDValue, 16> Ops;
1148 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1149 for (unsigned i = 0; i != NumElements; ++i)
1150 Ops.push_back(getValue(CV->getOperand(i)));
1152 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1153 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1156 if (EltVT.isFloatingPoint())
1157 Op = DAG.getConstantFP(0, EltVT);
1159 Op = DAG.getConstant(0, EltVT);
1160 Ops.assign(NumElements, Op);
1163 // Create a BUILD_VECTOR node.
1164 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1165 VT, &Ops[0], Ops.size());
1168 // If this is a static alloca, generate it as the frameindex instead of
1170 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1171 DenseMap<const AllocaInst*, int>::iterator SI =
1172 FuncInfo.StaticAllocaMap.find(AI);
1173 if (SI != FuncInfo.StaticAllocaMap.end())
1174 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1177 // If this is an instruction which fast-isel has deferred, select it now.
1178 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1179 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1180 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1181 SDValue Chain = DAG.getEntryNode();
1182 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1185 llvm_unreachable("Can't get register for value!");
1188 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1189 const TargetLowering *TLI = TM.getTargetLowering();
1190 SDValue Chain = getControlRoot();
1191 SmallVector<ISD::OutputArg, 8> Outs;
1192 SmallVector<SDValue, 8> OutVals;
1194 if (!FuncInfo.CanLowerReturn) {
1195 unsigned DemoteReg = FuncInfo.DemoteRegister;
1196 const Function *F = I.getParent()->getParent();
1198 // Emit a store of the return value through the virtual register.
1199 // Leave Outs empty so that LowerReturn won't try to load return
1200 // registers the usual way.
1201 SmallVector<EVT, 1> PtrValueVTs;
1202 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1205 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1206 SDValue RetOp = getValue(I.getOperand(0));
1208 SmallVector<EVT, 4> ValueVTs;
1209 SmallVector<uint64_t, 4> Offsets;
1210 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1211 unsigned NumValues = ValueVTs.size();
1213 SmallVector<SDValue, 4> Chains(NumValues);
1214 for (unsigned i = 0; i != NumValues; ++i) {
1215 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1216 RetPtr.getValueType(), RetPtr,
1217 DAG.getIntPtrConstant(Offsets[i]));
1219 DAG.getStore(Chain, getCurSDLoc(),
1220 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1221 // FIXME: better loc info would be nice.
1222 Add, MachinePointerInfo(), false, false, 0);
1225 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1226 MVT::Other, &Chains[0], NumValues);
1227 } else if (I.getNumOperands() != 0) {
1228 SmallVector<EVT, 4> ValueVTs;
1229 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1230 unsigned NumValues = ValueVTs.size();
1232 SDValue RetOp = getValue(I.getOperand(0));
1233 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1234 EVT VT = ValueVTs[j];
1236 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1238 const Function *F = I.getParent()->getParent();
1239 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::SIGN_EXTEND;
1242 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1244 ExtendKind = ISD::ZERO_EXTEND;
1246 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1247 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1249 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1250 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1251 SmallVector<SDValue, 4> Parts(NumParts);
1252 getCopyToParts(DAG, getCurSDLoc(),
1253 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1254 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1256 // 'inreg' on function refers to return value
1257 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1262 // Propagate extension type if any
1263 if (ExtendKind == ISD::SIGN_EXTEND)
1265 else if (ExtendKind == ISD::ZERO_EXTEND)
1268 for (unsigned i = 0; i < NumParts; ++i) {
1269 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1270 VT, /*isfixed=*/true, 0, 0));
1271 OutVals.push_back(Parts[i]);
1277 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1278 CallingConv::ID CallConv =
1279 DAG.getMachineFunction().getFunction()->getCallingConv();
1280 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1281 Outs, OutVals, getCurSDLoc(),
1284 // Verify that the target's LowerReturn behaved as expected.
1285 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1286 "LowerReturn didn't return a valid chain!");
1288 // Update the DAG with the new chain value resulting from return lowering.
1292 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1293 /// created for it, emit nodes to copy the value into the virtual
1295 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1297 if (V->getType()->isEmptyTy())
1300 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1301 if (VMI != FuncInfo.ValueMap.end()) {
1302 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1303 CopyValueToVirtualRegister(V, VMI->second);
1307 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1308 /// the current basic block, add it to ValueMap now so that we'll get a
1310 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1311 // No need to export constants.
1312 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1314 // Already exported?
1315 if (FuncInfo.isExportedInst(V)) return;
1317 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1318 CopyValueToVirtualRegister(V, Reg);
1321 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1322 const BasicBlock *FromBB) {
1323 // The operands of the setcc have to be in this block. We don't know
1324 // how to export them from some other block.
1325 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1326 // Can export from current BB.
1327 if (VI->getParent() == FromBB)
1330 // Is already exported, noop.
1331 return FuncInfo.isExportedInst(V);
1334 // If this is an argument, we can export it if the BB is the entry block or
1335 // if it is already exported.
1336 if (isa<Argument>(V)) {
1337 if (FromBB == &FromBB->getParent()->getEntryBlock())
1340 // Otherwise, can only export this if it is already exported.
1341 return FuncInfo.isExportedInst(V);
1344 // Otherwise, constants can always be exported.
1348 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1349 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1350 const MachineBasicBlock *Dst) const {
1351 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1354 const BasicBlock *SrcBB = Src->getBasicBlock();
1355 const BasicBlock *DstBB = Dst->getBasicBlock();
1356 return BPI->getEdgeWeight(SrcBB, DstBB);
1359 void SelectionDAGBuilder::
1360 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1361 uint32_t Weight /* = 0 */) {
1363 Weight = getEdgeWeight(Src, Dst);
1364 Src->addSuccessor(Dst, Weight);
1368 static bool InBlock(const Value *V, const BasicBlock *BB) {
1369 if (const Instruction *I = dyn_cast<Instruction>(V))
1370 return I->getParent() == BB;
1374 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1375 /// This function emits a branch and is used at the leaves of an OR or an
1376 /// AND operator tree.
1379 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1380 MachineBasicBlock *TBB,
1381 MachineBasicBlock *FBB,
1382 MachineBasicBlock *CurBB,
1383 MachineBasicBlock *SwitchBB,
1386 const BasicBlock *BB = CurBB->getBasicBlock();
1388 // If the leaf of the tree is a comparison, merge the condition into
1390 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1391 // The operands of the cmp have to be in this block. We don't know
1392 // how to export them from some other block. If this is the first block
1393 // of the sequence, no exporting is needed.
1394 if (CurBB == SwitchBB ||
1395 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1396 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1397 ISD::CondCode Condition;
1398 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1399 Condition = getICmpCondCode(IC->getPredicate());
1400 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1401 Condition = getFCmpCondCode(FC->getPredicate());
1402 if (TM.Options.NoNaNsFPMath)
1403 Condition = getFCmpCodeWithoutNaN(Condition);
1405 Condition = ISD::SETEQ; // silence warning.
1406 llvm_unreachable("Unknown compare instruction");
1409 CaseBlock CB(Condition, BOp->getOperand(0),
1410 BOp->getOperand(1), NULL, TBB, FBB, CurBB, TWeight, FWeight);
1411 SwitchCases.push_back(CB);
1416 // Create a CaseBlock record representing this branch.
1417 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1418 NULL, TBB, FBB, CurBB, TWeight, FWeight);
1419 SwitchCases.push_back(CB);
1422 /// Scale down both weights to fit into uint32_t.
1423 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1424 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1425 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1426 NewTrue = NewTrue / Scale;
1427 NewFalse = NewFalse / Scale;
1430 /// FindMergedConditions - If Cond is an expression like
1431 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1432 MachineBasicBlock *TBB,
1433 MachineBasicBlock *FBB,
1434 MachineBasicBlock *CurBB,
1435 MachineBasicBlock *SwitchBB,
1436 unsigned Opc, uint32_t TWeight,
1438 // If this node is not part of the or/and tree, emit it as a branch.
1439 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1440 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1441 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1442 BOp->getParent() != CurBB->getBasicBlock() ||
1443 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1444 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1445 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1450 // Create TmpBB after CurBB.
1451 MachineFunction::iterator BBI = CurBB;
1452 MachineFunction &MF = DAG.getMachineFunction();
1453 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1454 CurBB->getParent()->insert(++BBI, TmpBB);
1456 if (Opc == Instruction::Or) {
1457 // Codegen X | Y as:
1466 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1467 // The requirement is that
1468 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1469 // = TrueProb for orignal BB.
1470 // Assuming the orignal weights are A and B, one choice is to set BB1's
1471 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1473 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1474 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1475 // TmpBB, but the math is more complicated.
1477 uint64_t NewTrueWeight = TWeight;
1478 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1479 ScaleWeights(NewTrueWeight, NewFalseWeight);
1480 // Emit the LHS condition.
1481 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1482 NewTrueWeight, NewFalseWeight);
1484 NewTrueWeight = TWeight;
1485 NewFalseWeight = 2 * (uint64_t)FWeight;
1486 ScaleWeights(NewTrueWeight, NewFalseWeight);
1487 // Emit the RHS condition into TmpBB.
1488 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1489 NewTrueWeight, NewFalseWeight);
1491 assert(Opc == Instruction::And && "Unknown merge op!");
1492 // Codegen X & Y as:
1500 // This requires creation of TmpBB after CurBB.
1502 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1503 // The requirement is that
1504 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1505 // = FalseProb for orignal BB.
1506 // Assuming the orignal weights are A and B, one choice is to set BB1's
1507 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1509 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1511 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1512 uint64_t NewFalseWeight = FWeight;
1513 ScaleWeights(NewTrueWeight, NewFalseWeight);
1514 // Emit the LHS condition.
1515 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1516 NewTrueWeight, NewFalseWeight);
1518 NewTrueWeight = 2 * (uint64_t)TWeight;
1519 NewFalseWeight = FWeight;
1520 ScaleWeights(NewTrueWeight, NewFalseWeight);
1521 // Emit the RHS condition into TmpBB.
1522 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1523 NewTrueWeight, NewFalseWeight);
1527 /// If the set of cases should be emitted as a series of branches, return true.
1528 /// If we should emit this as a bunch of and/or'd together conditions, return
1531 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1532 if (Cases.size() != 2) return true;
1534 // If this is two comparisons of the same values or'd or and'd together, they
1535 // will get folded into a single comparison, so don't emit two blocks.
1536 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1537 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1538 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1539 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1543 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1544 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1545 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1546 Cases[0].CC == Cases[1].CC &&
1547 isa<Constant>(Cases[0].CmpRHS) &&
1548 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1549 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1551 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1558 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1559 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1561 // Update machine-CFG edges.
1562 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1564 // Figure out which block is immediately after the current one.
1565 MachineBasicBlock *NextBlock = 0;
1566 MachineFunction::iterator BBI = BrMBB;
1567 if (++BBI != FuncInfo.MF->end())
1570 if (I.isUnconditional()) {
1571 // Update machine-CFG edges.
1572 BrMBB->addSuccessor(Succ0MBB);
1574 // If this is not a fall-through branch, emit the branch.
1575 if (Succ0MBB != NextBlock)
1576 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1577 MVT::Other, getControlRoot(),
1578 DAG.getBasicBlock(Succ0MBB)));
1583 // If this condition is one of the special cases we handle, do special stuff
1585 const Value *CondVal = I.getCondition();
1586 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1588 // If this is a series of conditions that are or'd or and'd together, emit
1589 // this as a sequence of branches instead of setcc's with and/or operations.
1590 // As long as jumps are not expensive, this should improve performance.
1591 // For example, instead of something like:
1604 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1605 if (!TM.getTargetLowering()->isJumpExpensive() &&
1607 (BOp->getOpcode() == Instruction::And ||
1608 BOp->getOpcode() == Instruction::Or)) {
1609 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1610 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1611 getEdgeWeight(BrMBB, Succ1MBB));
1612 // If the compares in later blocks need to use values not currently
1613 // exported from this block, export them now. This block should always
1614 // be the first entry.
1615 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1617 // Allow some cases to be rejected.
1618 if (ShouldEmitAsBranches(SwitchCases)) {
1619 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1620 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1621 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1624 // Emit the branch for this block.
1625 visitSwitchCase(SwitchCases[0], BrMBB);
1626 SwitchCases.erase(SwitchCases.begin());
1630 // Okay, we decided not to do this, remove any inserted MBB's and clear
1632 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1633 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1635 SwitchCases.clear();
1639 // Create a CaseBlock record representing this branch.
1640 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1641 NULL, Succ0MBB, Succ1MBB, BrMBB);
1643 // Use visitSwitchCase to actually insert the fast branch sequence for this
1645 visitSwitchCase(CB, BrMBB);
1648 /// visitSwitchCase - Emits the necessary code to represent a single node in
1649 /// the binary search tree resulting from lowering a switch instruction.
1650 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1651 MachineBasicBlock *SwitchBB) {
1653 SDValue CondLHS = getValue(CB.CmpLHS);
1654 SDLoc dl = getCurSDLoc();
1656 // Build the setcc now.
1657 if (CB.CmpMHS == NULL) {
1658 // Fold "(X == true)" to X and "(X == false)" to !X to
1659 // handle common cases produced by branch lowering.
1660 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1661 CB.CC == ISD::SETEQ)
1663 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1664 CB.CC == ISD::SETEQ) {
1665 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1666 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1668 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1670 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1672 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1673 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1675 SDValue CmpOp = getValue(CB.CmpMHS);
1676 EVT VT = CmpOp.getValueType();
1678 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1679 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1682 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1683 VT, CmpOp, DAG.getConstant(Low, VT));
1684 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1685 DAG.getConstant(High-Low, VT), ISD::SETULE);
1689 // Update successor info
1690 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1691 // TrueBB and FalseBB are always different unless the incoming IR is
1692 // degenerate. This only happens when running llc on weird IR.
1693 if (CB.TrueBB != CB.FalseBB)
1694 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1696 // Set NextBlock to be the MBB immediately after the current one, if any.
1697 // This is used to avoid emitting unnecessary branches to the next block.
1698 MachineBasicBlock *NextBlock = 0;
1699 MachineFunction::iterator BBI = SwitchBB;
1700 if (++BBI != FuncInfo.MF->end())
1703 // If the lhs block is the next block, invert the condition so that we can
1704 // fall through to the lhs instead of the rhs block.
1705 if (CB.TrueBB == NextBlock) {
1706 std::swap(CB.TrueBB, CB.FalseBB);
1707 SDValue True = DAG.getConstant(1, Cond.getValueType());
1708 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1711 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1712 MVT::Other, getControlRoot(), Cond,
1713 DAG.getBasicBlock(CB.TrueBB));
1715 // Insert the false branch. Do this even if it's a fall through branch,
1716 // this makes it easier to do DAG optimizations which require inverting
1717 // the branch condition.
1718 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1719 DAG.getBasicBlock(CB.FalseBB));
1721 DAG.setRoot(BrCond);
1724 /// visitJumpTable - Emit JumpTable node in the current MBB
1725 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1726 // Emit the code for the jump table
1727 assert(JT.Reg != -1U && "Should lower JT Header first!");
1728 EVT PTy = TM.getTargetLowering()->getPointerTy();
1729 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1731 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1732 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1733 MVT::Other, Index.getValue(1),
1735 DAG.setRoot(BrJumpTable);
1738 /// visitJumpTableHeader - This function emits necessary code to produce index
1739 /// in the JumpTable from switch case.
1740 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1741 JumpTableHeader &JTH,
1742 MachineBasicBlock *SwitchBB) {
1743 // Subtract the lowest switch case value from the value being switched on and
1744 // conditional branch to default mbb if the result is greater than the
1745 // difference between smallest and largest cases.
1746 SDValue SwitchOp = getValue(JTH.SValue);
1747 EVT VT = SwitchOp.getValueType();
1748 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1749 DAG.getConstant(JTH.First, VT));
1751 // The SDNode we just created, which holds the value being switched on minus
1752 // the smallest case value, needs to be copied to a virtual register so it
1753 // can be used as an index into the jump table in a subsequent basic block.
1754 // This value may be smaller or larger than the target's pointer type, and
1755 // therefore require extension or truncating.
1756 const TargetLowering *TLI = TM.getTargetLowering();
1757 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1759 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1760 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1761 JumpTableReg, SwitchOp);
1762 JT.Reg = JumpTableReg;
1764 // Emit the range check for the jump table, and branch to the default block
1765 // for the switch statement if the value being switched on exceeds the largest
1766 // case in the switch.
1767 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1768 TLI->getSetCCResultType(*DAG.getContext(),
1769 Sub.getValueType()),
1771 DAG.getConstant(JTH.Last - JTH.First,VT),
1774 // Set NextBlock to be the MBB immediately after the current one, if any.
1775 // This is used to avoid emitting unnecessary branches to the next block.
1776 MachineBasicBlock *NextBlock = 0;
1777 MachineFunction::iterator BBI = SwitchBB;
1779 if (++BBI != FuncInfo.MF->end())
1782 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1783 MVT::Other, CopyTo, CMP,
1784 DAG.getBasicBlock(JT.Default));
1786 if (JT.MBB != NextBlock)
1787 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1788 DAG.getBasicBlock(JT.MBB));
1790 DAG.setRoot(BrCond);
1793 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1794 /// tail spliced into a stack protector check success bb.
1796 /// For a high level explanation of how this fits into the stack protector
1797 /// generation see the comment on the declaration of class
1798 /// StackProtectorDescriptor.
1799 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1800 MachineBasicBlock *ParentBB) {
1802 // First create the loads to the guard/stack slot for the comparison.
1803 const TargetLowering *TLI = TM.getTargetLowering();
1804 EVT PtrTy = TLI->getPointerTy();
1806 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1807 int FI = MFI->getStackProtectorIndex();
1809 const Value *IRGuard = SPD.getGuard();
1810 SDValue GuardPtr = getValue(IRGuard);
1811 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1814 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1815 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1816 GuardPtr, MachinePointerInfo(IRGuard, 0),
1817 true, false, false, Align);
1819 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1821 MachinePointerInfo::getFixedStack(FI),
1822 true, false, false, Align);
1824 // Perform the comparison via a subtract/getsetcc.
1825 EVT VT = Guard.getValueType();
1826 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1828 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1829 TLI->getSetCCResultType(*DAG.getContext(),
1830 Sub.getValueType()),
1831 Sub, DAG.getConstant(0, VT),
1834 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1835 // branch to failure MBB.
1836 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1837 MVT::Other, StackSlot.getOperand(0),
1838 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1839 // Otherwise branch to success MBB.
1840 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1842 DAG.getBasicBlock(SPD.getSuccessMBB()));
1847 /// Codegen the failure basic block for a stack protector check.
1849 /// A failure stack protector machine basic block consists simply of a call to
1850 /// __stack_chk_fail().
1852 /// For a high level explanation of how this fits into the stack protector
1853 /// generation see the comment on the declaration of class
1854 /// StackProtectorDescriptor.
1856 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1857 const TargetLowering *TLI = TM.getTargetLowering();
1858 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1859 MVT::isVoid, 0, 0, false, getCurSDLoc(),
1860 false, false).second;
1864 /// visitBitTestHeader - This function emits necessary code to produce value
1865 /// suitable for "bit tests"
1866 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1867 MachineBasicBlock *SwitchBB) {
1868 // Subtract the minimum value
1869 SDValue SwitchOp = getValue(B.SValue);
1870 EVT VT = SwitchOp.getValueType();
1871 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1872 DAG.getConstant(B.First, VT));
1875 const TargetLowering *TLI = TM.getTargetLowering();
1876 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1877 TLI->getSetCCResultType(*DAG.getContext(),
1878 Sub.getValueType()),
1879 Sub, DAG.getConstant(B.Range, VT),
1882 // Determine the type of the test operands.
1883 bool UsePtrType = false;
1884 if (!TLI->isTypeLegal(VT))
1887 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1888 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1889 // Switch table case range are encoded into series of masks.
1890 // Just use pointer type, it's guaranteed to fit.
1896 VT = TLI->getPointerTy();
1897 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1900 B.RegVT = VT.getSimpleVT();
1901 B.Reg = FuncInfo.CreateReg(B.RegVT);
1902 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1905 // Set NextBlock to be the MBB immediately after the current one, if any.
1906 // This is used to avoid emitting unnecessary branches to the next block.
1907 MachineBasicBlock *NextBlock = 0;
1908 MachineFunction::iterator BBI = SwitchBB;
1909 if (++BBI != FuncInfo.MF->end())
1912 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1914 addSuccessorWithWeight(SwitchBB, B.Default);
1915 addSuccessorWithWeight(SwitchBB, MBB);
1917 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1918 MVT::Other, CopyTo, RangeCmp,
1919 DAG.getBasicBlock(B.Default));
1921 if (MBB != NextBlock)
1922 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1923 DAG.getBasicBlock(MBB));
1925 DAG.setRoot(BrRange);
1928 /// visitBitTestCase - this function produces one "bit test"
1929 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1930 MachineBasicBlock* NextMBB,
1931 uint32_t BranchWeightToNext,
1934 MachineBasicBlock *SwitchBB) {
1936 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1939 unsigned PopCount = CountPopulation_64(B.Mask);
1940 const TargetLowering *TLI = TM.getTargetLowering();
1941 if (PopCount == 1) {
1942 // Testing for a single bit; just compare the shift count with what it
1943 // would need to be to shift a 1 bit in that position.
1944 Cmp = DAG.getSetCC(getCurSDLoc(),
1945 TLI->getSetCCResultType(*DAG.getContext(), VT),
1947 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1949 } else if (PopCount == BB.Range) {
1950 // There is only one zero bit in the range, test for it directly.
1951 Cmp = DAG.getSetCC(getCurSDLoc(),
1952 TLI->getSetCCResultType(*DAG.getContext(), VT),
1954 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1957 // Make desired shift
1958 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1959 DAG.getConstant(1, VT), ShiftOp);
1961 // Emit bit tests and jumps
1962 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1963 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1964 Cmp = DAG.getSetCC(getCurSDLoc(),
1965 TLI->getSetCCResultType(*DAG.getContext(), VT),
1966 AndOp, DAG.getConstant(0, VT),
1970 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1971 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1972 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1973 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1975 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1976 MVT::Other, getControlRoot(),
1977 Cmp, DAG.getBasicBlock(B.TargetBB));
1979 // Set NextBlock to be the MBB immediately after the current one, if any.
1980 // This is used to avoid emitting unnecessary branches to the next block.
1981 MachineBasicBlock *NextBlock = 0;
1982 MachineFunction::iterator BBI = SwitchBB;
1983 if (++BBI != FuncInfo.MF->end())
1986 if (NextMBB != NextBlock)
1987 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1988 DAG.getBasicBlock(NextMBB));
1993 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1994 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1996 // Retrieve successors.
1997 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1998 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2000 const Value *Callee(I.getCalledValue());
2001 const Function *Fn = dyn_cast<Function>(Callee);
2002 if (isa<InlineAsm>(Callee))
2004 else if (Fn && Fn->isIntrinsic()) {
2005 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2006 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2008 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2010 // If the value of the invoke is used outside of its defining block, make it
2011 // available as a virtual register.
2012 CopyToExportRegsIfNeeded(&I);
2014 // Update successor info
2015 addSuccessorWithWeight(InvokeMBB, Return);
2016 addSuccessorWithWeight(InvokeMBB, LandingPad);
2018 // Drop into normal successor.
2019 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2020 MVT::Other, getControlRoot(),
2021 DAG.getBasicBlock(Return)));
2024 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2025 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2028 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2029 assert(FuncInfo.MBB->isLandingPad() &&
2030 "Call to landingpad not in landing pad!");
2032 MachineBasicBlock *MBB = FuncInfo.MBB;
2033 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2034 AddLandingPadInfo(LP, MMI, MBB);
2036 // If there aren't registers to copy the values into (e.g., during SjLj
2037 // exceptions), then don't bother to create these DAG nodes.
2038 const TargetLowering *TLI = TM.getTargetLowering();
2039 if (TLI->getExceptionPointerRegister() == 0 &&
2040 TLI->getExceptionSelectorRegister() == 0)
2043 SmallVector<EVT, 2> ValueVTs;
2044 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2045 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2047 // Get the two live-in registers as SDValues. The physregs have already been
2048 // copied into virtual registers.
2050 Ops[0] = DAG.getZExtOrTrunc(
2051 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2052 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2053 getCurSDLoc(), ValueVTs[0]);
2054 Ops[1] = DAG.getZExtOrTrunc(
2055 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2056 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2057 getCurSDLoc(), ValueVTs[1]);
2060 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2061 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
2066 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2067 /// small case ranges).
2068 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2069 CaseRecVector& WorkList,
2071 MachineBasicBlock *Default,
2072 MachineBasicBlock *SwitchBB) {
2073 // Size is the number of Cases represented by this range.
2074 size_t Size = CR.Range.second - CR.Range.first;
2078 // Get the MachineFunction which holds the current MBB. This is used when
2079 // inserting any additional MBBs necessary to represent the switch.
2080 MachineFunction *CurMF = FuncInfo.MF;
2082 // Figure out which block is immediately after the current one.
2083 MachineBasicBlock *NextBlock = 0;
2084 MachineFunction::iterator BBI = CR.CaseBB;
2086 if (++BBI != FuncInfo.MF->end())
2089 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2090 // If any two of the cases has the same destination, and if one value
2091 // is the same as the other, but has one bit unset that the other has set,
2092 // use bit manipulation to do two compares at once. For example:
2093 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2094 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2095 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2096 if (Size == 2 && CR.CaseBB == SwitchBB) {
2097 Case &Small = *CR.Range.first;
2098 Case &Big = *(CR.Range.second-1);
2100 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2101 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2102 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2104 // Check that there is only one bit different.
2105 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2106 (SmallValue | BigValue) == BigValue) {
2107 // Isolate the common bit.
2108 APInt CommonBit = BigValue & ~SmallValue;
2109 assert((SmallValue | CommonBit) == BigValue &&
2110 CommonBit.countPopulation() == 1 && "Not a common bit?");
2112 SDValue CondLHS = getValue(SV);
2113 EVT VT = CondLHS.getValueType();
2114 SDLoc DL = getCurSDLoc();
2116 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2117 DAG.getConstant(CommonBit, VT));
2118 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2119 Or, DAG.getConstant(BigValue, VT),
2122 // Update successor info.
2123 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2124 addSuccessorWithWeight(SwitchBB, Small.BB,
2125 Small.ExtraWeight + Big.ExtraWeight);
2126 addSuccessorWithWeight(SwitchBB, Default,
2127 // The default destination is the first successor in IR.
2128 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2130 // Insert the true branch.
2131 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2132 getControlRoot(), Cond,
2133 DAG.getBasicBlock(Small.BB));
2135 // Insert the false branch.
2136 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2137 DAG.getBasicBlock(Default));
2139 DAG.setRoot(BrCond);
2145 // Order cases by weight so the most likely case will be checked first.
2146 uint32_t UnhandledWeights = 0;
2148 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2149 uint32_t IWeight = I->ExtraWeight;
2150 UnhandledWeights += IWeight;
2151 for (CaseItr J = CR.Range.first; J < I; ++J) {
2152 uint32_t JWeight = J->ExtraWeight;
2153 if (IWeight > JWeight)
2158 // Rearrange the case blocks so that the last one falls through if possible.
2159 Case &BackCase = *(CR.Range.second-1);
2161 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2162 // The last case block won't fall through into 'NextBlock' if we emit the
2163 // branches in this order. See if rearranging a case value would help.
2164 // We start at the bottom as it's the case with the least weight.
2165 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2166 if (I->BB == NextBlock) {
2167 std::swap(*I, BackCase);
2172 // Create a CaseBlock record representing a conditional branch to
2173 // the Case's target mbb if the value being switched on SV is equal
2175 MachineBasicBlock *CurBlock = CR.CaseBB;
2176 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2177 MachineBasicBlock *FallThrough;
2179 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2180 CurMF->insert(BBI, FallThrough);
2182 // Put SV in a virtual register to make it available from the new blocks.
2183 ExportFromCurrentBlock(SV);
2185 // If the last case doesn't match, go to the default block.
2186 FallThrough = Default;
2189 const Value *RHS, *LHS, *MHS;
2191 if (I->High == I->Low) {
2192 // This is just small small case range :) containing exactly 1 case
2194 LHS = SV; RHS = I->High; MHS = NULL;
2197 LHS = I->Low; MHS = SV; RHS = I->High;
2200 // The false weight should be sum of all un-handled cases.
2201 UnhandledWeights -= I->ExtraWeight;
2202 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2204 /* trueweight */ I->ExtraWeight,
2205 /* falseweight */ UnhandledWeights);
2207 // If emitting the first comparison, just call visitSwitchCase to emit the
2208 // code into the current block. Otherwise, push the CaseBlock onto the
2209 // vector to be later processed by SDISel, and insert the node's MBB
2210 // before the next MBB.
2211 if (CurBlock == SwitchBB)
2212 visitSwitchCase(CB, SwitchBB);
2214 SwitchCases.push_back(CB);
2216 CurBlock = FallThrough;
2222 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2223 return TLI.supportJumpTables() &&
2224 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2225 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2228 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2229 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2230 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2231 return (LastExt - FirstExt + 1ULL);
2234 /// handleJTSwitchCase - Emit jumptable for current switch case range
2235 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2236 CaseRecVector &WorkList,
2238 MachineBasicBlock *Default,
2239 MachineBasicBlock *SwitchBB) {
2240 Case& FrontCase = *CR.Range.first;
2241 Case& BackCase = *(CR.Range.second-1);
2243 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2244 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2246 APInt TSize(First.getBitWidth(), 0);
2247 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2250 const TargetLowering *TLI = TM.getTargetLowering();
2251 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2254 APInt Range = ComputeRange(First, Last);
2255 // The density is TSize / Range. Require at least 40%.
2256 // It should not be possible for IntTSize to saturate for sane code, but make
2257 // sure we handle Range saturation correctly.
2258 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2259 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2260 if (IntTSize * 10 < IntRange * 4)
2263 DEBUG(dbgs() << "Lowering jump table\n"
2264 << "First entry: " << First << ". Last entry: " << Last << '\n'
2265 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2267 // Get the MachineFunction which holds the current MBB. This is used when
2268 // inserting any additional MBBs necessary to represent the switch.
2269 MachineFunction *CurMF = FuncInfo.MF;
2271 // Figure out which block is immediately after the current one.
2272 MachineFunction::iterator BBI = CR.CaseBB;
2275 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2277 // Create a new basic block to hold the code for loading the address
2278 // of the jump table, and jumping to it. Update successor information;
2279 // we will either branch to the default case for the switch, or the jump
2281 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2282 CurMF->insert(BBI, JumpTableBB);
2284 addSuccessorWithWeight(CR.CaseBB, Default);
2285 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2287 // Build a vector of destination BBs, corresponding to each target
2288 // of the jump table. If the value of the jump table slot corresponds to
2289 // a case statement, push the case's BB onto the vector, otherwise, push
2291 std::vector<MachineBasicBlock*> DestBBs;
2293 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2294 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2295 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2297 if (Low.sle(TEI) && TEI.sle(High)) {
2298 DestBBs.push_back(I->BB);
2302 DestBBs.push_back(Default);
2306 // Calculate weight for each unique destination in CR.
2307 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2309 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2310 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2311 DestWeights.find(I->BB);
2312 if (Itr != DestWeights.end())
2313 Itr->second += I->ExtraWeight;
2315 DestWeights[I->BB] = I->ExtraWeight;
2318 // Update successor info. Add one edge to each unique successor.
2319 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2320 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2321 E = DestBBs.end(); I != E; ++I) {
2322 if (!SuccsHandled[(*I)->getNumber()]) {
2323 SuccsHandled[(*I)->getNumber()] = true;
2324 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2325 DestWeights.find(*I);
2326 addSuccessorWithWeight(JumpTableBB, *I,
2327 Itr != DestWeights.end() ? Itr->second : 0);
2331 // Create a jump table index for this jump table.
2332 unsigned JTEncoding = TLI->getJumpTableEncoding();
2333 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2334 ->createJumpTableIndex(DestBBs);
2336 // Set the jump table information so that we can codegen it as a second
2337 // MachineBasicBlock
2338 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2339 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2340 if (CR.CaseBB == SwitchBB)
2341 visitJumpTableHeader(JT, JTH, SwitchBB);
2343 JTCases.push_back(JumpTableBlock(JTH, JT));
2347 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2349 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2350 CaseRecVector& WorkList,
2352 MachineBasicBlock* Default,
2353 MachineBasicBlock* SwitchBB) {
2354 // Get the MachineFunction which holds the current MBB. This is used when
2355 // inserting any additional MBBs necessary to represent the switch.
2356 MachineFunction *CurMF = FuncInfo.MF;
2358 // Figure out which block is immediately after the current one.
2359 MachineFunction::iterator BBI = CR.CaseBB;
2362 Case& FrontCase = *CR.Range.first;
2363 Case& BackCase = *(CR.Range.second-1);
2364 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2366 // Size is the number of Cases represented by this range.
2367 unsigned Size = CR.Range.second - CR.Range.first;
2369 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2370 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2372 CaseItr Pivot = CR.Range.first + Size/2;
2374 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2375 // (heuristically) allow us to emit JumpTable's later.
2376 APInt TSize(First.getBitWidth(), 0);
2377 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2381 APInt LSize = FrontCase.size();
2382 APInt RSize = TSize-LSize;
2383 DEBUG(dbgs() << "Selecting best pivot: \n"
2384 << "First: " << First << ", Last: " << Last <<'\n'
2385 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2386 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2388 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2389 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2390 APInt Range = ComputeRange(LEnd, RBegin);
2391 assert((Range - 2ULL).isNonNegative() &&
2392 "Invalid case distance");
2393 // Use volatile double here to avoid excess precision issues on some hosts,
2394 // e.g. that use 80-bit X87 registers.
2395 volatile double LDensity =
2396 (double)LSize.roundToDouble() /
2397 (LEnd - First + 1ULL).roundToDouble();
2398 volatile double RDensity =
2399 (double)RSize.roundToDouble() /
2400 (Last - RBegin + 1ULL).roundToDouble();
2401 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2402 // Should always split in some non-trivial place
2403 DEBUG(dbgs() <<"=>Step\n"
2404 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2405 << "LDensity: " << LDensity
2406 << ", RDensity: " << RDensity << '\n'
2407 << "Metric: " << Metric << '\n');
2408 if (FMetric < Metric) {
2411 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2418 const TargetLowering *TLI = TM.getTargetLowering();
2419 if (areJTsAllowed(*TLI)) {
2420 // If our case is dense we *really* should handle it earlier!
2421 assert((FMetric > 0) && "Should handle dense range earlier!");
2423 Pivot = CR.Range.first + Size/2;
2426 CaseRange LHSR(CR.Range.first, Pivot);
2427 CaseRange RHSR(Pivot, CR.Range.second);
2428 const Constant *C = Pivot->Low;
2429 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2431 // We know that we branch to the LHS if the Value being switched on is
2432 // less than the Pivot value, C. We use this to optimize our binary
2433 // tree a bit, by recognizing that if SV is greater than or equal to the
2434 // LHS's Case Value, and that Case Value is exactly one less than the
2435 // Pivot's Value, then we can branch directly to the LHS's Target,
2436 // rather than creating a leaf node for it.
2437 if ((LHSR.second - LHSR.first) == 1 &&
2438 LHSR.first->High == CR.GE &&
2439 cast<ConstantInt>(C)->getValue() ==
2440 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2441 TrueBB = LHSR.first->BB;
2443 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2444 CurMF->insert(BBI, TrueBB);
2445 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2447 // Put SV in a virtual register to make it available from the new blocks.
2448 ExportFromCurrentBlock(SV);
2451 // Similar to the optimization above, if the Value being switched on is
2452 // known to be less than the Constant CR.LT, and the current Case Value
2453 // is CR.LT - 1, then we can branch directly to the target block for
2454 // the current Case Value, rather than emitting a RHS leaf node for it.
2455 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2456 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2457 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2458 FalseBB = RHSR.first->BB;
2460 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2461 CurMF->insert(BBI, FalseBB);
2462 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2464 // Put SV in a virtual register to make it available from the new blocks.
2465 ExportFromCurrentBlock(SV);
2468 // Create a CaseBlock record representing a conditional branch to
2469 // the LHS node if the value being switched on SV is less than C.
2470 // Otherwise, branch to LHS.
2471 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2473 if (CR.CaseBB == SwitchBB)
2474 visitSwitchCase(CB, SwitchBB);
2476 SwitchCases.push_back(CB);
2481 /// handleBitTestsSwitchCase - if current case range has few destination and
2482 /// range span less, than machine word bitwidth, encode case range into series
2483 /// of masks and emit bit tests with these masks.
2484 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2485 CaseRecVector& WorkList,
2487 MachineBasicBlock* Default,
2488 MachineBasicBlock* SwitchBB) {
2489 const TargetLowering *TLI = TM.getTargetLowering();
2490 EVT PTy = TLI->getPointerTy();
2491 unsigned IntPtrBits = PTy.getSizeInBits();
2493 Case& FrontCase = *CR.Range.first;
2494 Case& BackCase = *(CR.Range.second-1);
2496 // Get the MachineFunction which holds the current MBB. This is used when
2497 // inserting any additional MBBs necessary to represent the switch.
2498 MachineFunction *CurMF = FuncInfo.MF;
2500 // If target does not have legal shift left, do not emit bit tests at all.
2501 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2505 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2507 // Single case counts one, case range - two.
2508 numCmps += (I->Low == I->High ? 1 : 2);
2511 // Count unique destinations
2512 SmallSet<MachineBasicBlock*, 4> Dests;
2513 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2514 Dests.insert(I->BB);
2515 if (Dests.size() > 3)
2516 // Don't bother the code below, if there are too much unique destinations
2519 DEBUG(dbgs() << "Total number of unique destinations: "
2520 << Dests.size() << '\n'
2521 << "Total number of comparisons: " << numCmps << '\n');
2523 // Compute span of values.
2524 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2525 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2526 APInt cmpRange = maxValue - minValue;
2528 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2529 << "Low bound: " << minValue << '\n'
2530 << "High bound: " << maxValue << '\n');
2532 if (cmpRange.uge(IntPtrBits) ||
2533 (!(Dests.size() == 1 && numCmps >= 3) &&
2534 !(Dests.size() == 2 && numCmps >= 5) &&
2535 !(Dests.size() >= 3 && numCmps >= 6)))
2538 DEBUG(dbgs() << "Emitting bit tests\n");
2539 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2541 // Optimize the case where all the case values fit in a
2542 // word without having to subtract minValue. In this case,
2543 // we can optimize away the subtraction.
2544 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2545 cmpRange = maxValue;
2547 lowBound = minValue;
2550 CaseBitsVector CasesBits;
2551 unsigned i, count = 0;
2553 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2554 MachineBasicBlock* Dest = I->BB;
2555 for (i = 0; i < count; ++i)
2556 if (Dest == CasesBits[i].BB)
2560 assert((count < 3) && "Too much destinations to test!");
2561 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2565 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2566 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2568 uint64_t lo = (lowValue - lowBound).getZExtValue();
2569 uint64_t hi = (highValue - lowBound).getZExtValue();
2570 CasesBits[i].ExtraWeight += I->ExtraWeight;
2572 for (uint64_t j = lo; j <= hi; j++) {
2573 CasesBits[i].Mask |= 1ULL << j;
2574 CasesBits[i].Bits++;
2578 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2582 // Figure out which block is immediately after the current one.
2583 MachineFunction::iterator BBI = CR.CaseBB;
2586 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2588 DEBUG(dbgs() << "Cases:\n");
2589 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2590 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2591 << ", Bits: " << CasesBits[i].Bits
2592 << ", BB: " << CasesBits[i].BB << '\n');
2594 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2595 CurMF->insert(BBI, CaseBB);
2596 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2598 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2600 // Put SV in a virtual register to make it available from the new blocks.
2601 ExportFromCurrentBlock(SV);
2604 BitTestBlock BTB(lowBound, cmpRange, SV,
2605 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2606 CR.CaseBB, Default, BTC);
2608 if (CR.CaseBB == SwitchBB)
2609 visitBitTestHeader(BTB, SwitchBB);
2611 BitTestCases.push_back(BTB);
2616 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2617 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2618 const SwitchInst& SI) {
2621 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2622 // Start with "simple" cases
2623 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2625 const BasicBlock *SuccBB = i.getCaseSuccessor();
2626 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2628 uint32_t ExtraWeight =
2629 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2631 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2632 SMBB, ExtraWeight));
2634 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2636 // Merge case into clusters
2637 if (Cases.size() >= 2)
2638 // Must recompute end() each iteration because it may be
2639 // invalidated by erase if we hold on to it
2640 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2641 J != Cases.end(); ) {
2642 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2643 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2644 MachineBasicBlock* nextBB = J->BB;
2645 MachineBasicBlock* currentBB = I->BB;
2647 // If the two neighboring cases go to the same destination, merge them
2648 // into a single case.
2649 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2651 I->ExtraWeight += J->ExtraWeight;
2658 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2659 if (I->Low != I->High)
2660 // A range counts double, since it requires two compares.
2667 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2668 MachineBasicBlock *Last) {
2670 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2671 if (JTCases[i].first.HeaderBB == First)
2672 JTCases[i].first.HeaderBB = Last;
2674 // Update BitTestCases.
2675 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2676 if (BitTestCases[i].Parent == First)
2677 BitTestCases[i].Parent = Last;
2680 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2681 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2683 // Figure out which block is immediately after the current one.
2684 MachineBasicBlock *NextBlock = 0;
2685 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2687 // If there is only the default destination, branch to it if it is not the
2688 // next basic block. Otherwise, just fall through.
2689 if (!SI.getNumCases()) {
2690 // Update machine-CFG edges.
2692 // If this is not a fall-through branch, emit the branch.
2693 SwitchMBB->addSuccessor(Default);
2694 if (Default != NextBlock)
2695 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2696 MVT::Other, getControlRoot(),
2697 DAG.getBasicBlock(Default)));
2702 // If there are any non-default case statements, create a vector of Cases
2703 // representing each one, and sort the vector so that we can efficiently
2704 // create a binary search tree from them.
2706 size_t numCmps = Clusterify(Cases, SI);
2707 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2708 << ". Total compares: " << numCmps << '\n');
2711 // Get the Value to be switched on and default basic blocks, which will be
2712 // inserted into CaseBlock records, representing basic blocks in the binary
2714 const Value *SV = SI.getCondition();
2716 // Push the initial CaseRec onto the worklist
2717 CaseRecVector WorkList;
2718 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2719 CaseRange(Cases.begin(),Cases.end())));
2721 while (!WorkList.empty()) {
2722 // Grab a record representing a case range to process off the worklist
2723 CaseRec CR = WorkList.back();
2724 WorkList.pop_back();
2726 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2729 // If the range has few cases (two or less) emit a series of specific
2731 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2734 // If the switch has more than N blocks, and is at least 40% dense, and the
2735 // target supports indirect branches, then emit a jump table rather than
2736 // lowering the switch to a binary tree of conditional branches.
2737 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2738 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2741 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2742 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2743 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2747 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2748 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2750 // Update machine-CFG edges with unique successors.
2751 SmallSet<BasicBlock*, 32> Done;
2752 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2753 BasicBlock *BB = I.getSuccessor(i);
2754 bool Inserted = Done.insert(BB);
2758 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2759 addSuccessorWithWeight(IndirectBrMBB, Succ);
2762 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2763 MVT::Other, getControlRoot(),
2764 getValue(I.getAddress())));
2767 void SelectionDAGBuilder::visitFSub(const User &I) {
2768 // -0.0 - X --> fneg
2769 Type *Ty = I.getType();
2770 if (isa<Constant>(I.getOperand(0)) &&
2771 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2772 SDValue Op2 = getValue(I.getOperand(1));
2773 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2774 Op2.getValueType(), Op2));
2778 visitBinary(I, ISD::FSUB);
2781 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2782 SDValue Op1 = getValue(I.getOperand(0));
2783 SDValue Op2 = getValue(I.getOperand(1));
2784 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2785 Op1.getValueType(), Op1, Op2));
2788 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2789 SDValue Op1 = getValue(I.getOperand(0));
2790 SDValue Op2 = getValue(I.getOperand(1));
2792 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2794 // Coerce the shift amount to the right type if we can.
2795 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2796 unsigned ShiftSize = ShiftTy.getSizeInBits();
2797 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2798 SDLoc DL = getCurSDLoc();
2800 // If the operand is smaller than the shift count type, promote it.
2801 if (ShiftSize > Op2Size)
2802 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2804 // If the operand is larger than the shift count type but the shift
2805 // count type has enough bits to represent any shift value, truncate
2806 // it now. This is a common case and it exposes the truncate to
2807 // optimization early.
2808 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2809 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2810 // Otherwise we'll need to temporarily settle for some other convenient
2811 // type. Type legalization will make adjustments once the shiftee is split.
2813 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2816 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2817 Op1.getValueType(), Op1, Op2));
2820 void SelectionDAGBuilder::visitSDiv(const User &I) {
2821 SDValue Op1 = getValue(I.getOperand(0));
2822 SDValue Op2 = getValue(I.getOperand(1));
2824 // Turn exact SDivs into multiplications.
2825 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2827 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2828 !isa<ConstantSDNode>(Op1) &&
2829 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2830 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2831 getCurSDLoc(), DAG));
2833 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2837 void SelectionDAGBuilder::visitICmp(const User &I) {
2838 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2839 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2840 predicate = IC->getPredicate();
2841 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2842 predicate = ICmpInst::Predicate(IC->getPredicate());
2843 SDValue Op1 = getValue(I.getOperand(0));
2844 SDValue Op2 = getValue(I.getOperand(1));
2845 ISD::CondCode Opcode = getICmpCondCode(predicate);
2847 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2848 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2851 void SelectionDAGBuilder::visitFCmp(const User &I) {
2852 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2853 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2854 predicate = FC->getPredicate();
2855 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2856 predicate = FCmpInst::Predicate(FC->getPredicate());
2857 SDValue Op1 = getValue(I.getOperand(0));
2858 SDValue Op2 = getValue(I.getOperand(1));
2859 ISD::CondCode Condition = getFCmpCondCode(predicate);
2860 if (TM.Options.NoNaNsFPMath)
2861 Condition = getFCmpCodeWithoutNaN(Condition);
2862 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2863 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2866 void SelectionDAGBuilder::visitSelect(const User &I) {
2867 SmallVector<EVT, 4> ValueVTs;
2868 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2869 unsigned NumValues = ValueVTs.size();
2870 if (NumValues == 0) return;
2872 SmallVector<SDValue, 4> Values(NumValues);
2873 SDValue Cond = getValue(I.getOperand(0));
2874 SDValue TrueVal = getValue(I.getOperand(1));
2875 SDValue FalseVal = getValue(I.getOperand(2));
2876 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2877 ISD::VSELECT : ISD::SELECT;
2879 for (unsigned i = 0; i != NumValues; ++i)
2880 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2881 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2883 SDValue(TrueVal.getNode(),
2884 TrueVal.getResNo() + i),
2885 SDValue(FalseVal.getNode(),
2886 FalseVal.getResNo() + i));
2888 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2889 DAG.getVTList(&ValueVTs[0], NumValues),
2890 &Values[0], NumValues));
2893 void SelectionDAGBuilder::visitTrunc(const User &I) {
2894 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2895 SDValue N = getValue(I.getOperand(0));
2896 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2897 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2900 void SelectionDAGBuilder::visitZExt(const User &I) {
2901 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2902 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2903 SDValue N = getValue(I.getOperand(0));
2904 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2905 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2908 void SelectionDAGBuilder::visitSExt(const User &I) {
2909 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2910 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2911 SDValue N = getValue(I.getOperand(0));
2912 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2913 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2916 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2917 // FPTrunc is never a no-op cast, no need to check
2918 SDValue N = getValue(I.getOperand(0));
2919 const TargetLowering *TLI = TM.getTargetLowering();
2920 EVT DestVT = TLI->getValueType(I.getType());
2921 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2923 DAG.getTargetConstant(0, TLI->getPointerTy())));
2926 void SelectionDAGBuilder::visitFPExt(const User &I) {
2927 // FPExt is never a no-op cast, no need to check
2928 SDValue N = getValue(I.getOperand(0));
2929 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2930 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2933 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2934 // FPToUI is never a no-op cast, no need to check
2935 SDValue N = getValue(I.getOperand(0));
2936 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2937 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2940 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2941 // FPToSI is never a no-op cast, no need to check
2942 SDValue N = getValue(I.getOperand(0));
2943 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2944 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2947 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2948 // UIToFP is never a no-op cast, no need to check
2949 SDValue N = getValue(I.getOperand(0));
2950 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2951 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2954 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2955 // SIToFP is never a no-op cast, no need to check
2956 SDValue N = getValue(I.getOperand(0));
2957 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2958 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2961 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2962 // What to do depends on the size of the integer and the size of the pointer.
2963 // We can either truncate, zero extend, or no-op, accordingly.
2964 SDValue N = getValue(I.getOperand(0));
2965 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2966 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2969 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2970 // What to do depends on the size of the integer and the size of the pointer.
2971 // We can either truncate, zero extend, or no-op, accordingly.
2972 SDValue N = getValue(I.getOperand(0));
2973 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2974 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2977 void SelectionDAGBuilder::visitBitCast(const User &I) {
2978 SDValue N = getValue(I.getOperand(0));
2979 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2981 // BitCast assures us that source and destination are the same size so this is
2982 // either a BITCAST or a no-op.
2983 if (DestVT != N.getValueType())
2984 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2985 DestVT, N)); // convert types.
2986 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2987 // might fold any kind of constant expression to an integer constant and that
2988 // is not what we are looking for. Only regcognize a bitcast of a genuine
2989 // constant integer as an opaque constant.
2990 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2991 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
2994 setValue(&I, N); // noop cast.
2997 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2999 const Value *SV = I.getOperand(0);
3000 SDValue N = getValue(SV);
3001 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3003 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3004 unsigned DestAS = I.getType()->getPointerAddressSpace();
3006 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3007 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3012 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3013 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3014 SDValue InVec = getValue(I.getOperand(0));
3015 SDValue InVal = getValue(I.getOperand(1));
3016 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3017 getCurSDLoc(), TLI.getVectorIdxTy());
3018 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3019 TM.getTargetLowering()->getValueType(I.getType()),
3020 InVec, InVal, InIdx));
3023 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3025 SDValue InVec = getValue(I.getOperand(0));
3026 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3027 getCurSDLoc(), TLI.getVectorIdxTy());
3028 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3029 TM.getTargetLowering()->getValueType(I.getType()),
3033 // Utility for visitShuffleVector - Return true if every element in Mask,
3034 // beginning from position Pos and ending in Pos+Size, falls within the
3035 // specified sequential range [L, L+Pos). or is undef.
3036 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3037 unsigned Pos, unsigned Size, int Low) {
3038 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3039 if (Mask[i] >= 0 && Mask[i] != Low)
3044 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3045 SDValue Src1 = getValue(I.getOperand(0));
3046 SDValue Src2 = getValue(I.getOperand(1));
3048 SmallVector<int, 8> Mask;
3049 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3050 unsigned MaskNumElts = Mask.size();
3052 const TargetLowering *TLI = TM.getTargetLowering();
3053 EVT VT = TLI->getValueType(I.getType());
3054 EVT SrcVT = Src1.getValueType();
3055 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3057 if (SrcNumElts == MaskNumElts) {
3058 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3063 // Normalize the shuffle vector since mask and vector length don't match.
3064 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3065 // Mask is longer than the source vectors and is a multiple of the source
3066 // vectors. We can use concatenate vector to make the mask and vectors
3068 if (SrcNumElts*2 == MaskNumElts) {
3069 // First check for Src1 in low and Src2 in high
3070 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3071 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3072 // The shuffle is concatenating two vectors together.
3073 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3077 // Then check for Src2 in low and Src1 in high
3078 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3079 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3080 // The shuffle is concatenating two vectors together.
3081 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3087 // Pad both vectors with undefs to make them the same length as the mask.
3088 unsigned NumConcat = MaskNumElts / SrcNumElts;
3089 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3090 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3091 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3093 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3094 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3098 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3100 &MOps1[0], NumConcat);
3101 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3103 &MOps2[0], NumConcat);
3105 // Readjust mask for new input vector length.
3106 SmallVector<int, 8> MappedOps;
3107 for (unsigned i = 0; i != MaskNumElts; ++i) {
3109 if (Idx >= (int)SrcNumElts)
3110 Idx -= SrcNumElts - MaskNumElts;
3111 MappedOps.push_back(Idx);
3114 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3119 if (SrcNumElts > MaskNumElts) {
3120 // Analyze the access pattern of the vector to see if we can extract
3121 // two subvectors and do the shuffle. The analysis is done by calculating
3122 // the range of elements the mask access on both vectors.
3123 int MinRange[2] = { static_cast<int>(SrcNumElts),
3124 static_cast<int>(SrcNumElts)};
3125 int MaxRange[2] = {-1, -1};
3127 for (unsigned i = 0; i != MaskNumElts; ++i) {
3133 if (Idx >= (int)SrcNumElts) {
3137 if (Idx > MaxRange[Input])
3138 MaxRange[Input] = Idx;
3139 if (Idx < MinRange[Input])
3140 MinRange[Input] = Idx;
3143 // Check if the access is smaller than the vector size and can we find
3144 // a reasonable extract index.
3145 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3147 int StartIdx[2]; // StartIdx to extract from
3148 for (unsigned Input = 0; Input < 2; ++Input) {
3149 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3150 RangeUse[Input] = 0; // Unused
3151 StartIdx[Input] = 0;
3155 // Find a good start index that is a multiple of the mask length. Then
3156 // see if the rest of the elements are in range.
3157 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3158 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3159 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3160 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3163 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3164 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3167 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3168 // Extract appropriate subvector and generate a vector shuffle
3169 for (unsigned Input = 0; Input < 2; ++Input) {
3170 SDValue &Src = Input == 0 ? Src1 : Src2;
3171 if (RangeUse[Input] == 0)
3172 Src = DAG.getUNDEF(VT);
3174 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3175 Src, DAG.getConstant(StartIdx[Input],
3176 TLI->getVectorIdxTy()));
3179 // Calculate new mask.
3180 SmallVector<int, 8> MappedOps;
3181 for (unsigned i = 0; i != MaskNumElts; ++i) {
3184 if (Idx < (int)SrcNumElts)
3187 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3189 MappedOps.push_back(Idx);
3192 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3198 // We can't use either concat vectors or extract subvectors so fall back to
3199 // replacing the shuffle with extract and build vector.
3200 // to insert and build vector.
3201 EVT EltVT = VT.getVectorElementType();
3202 EVT IdxVT = TLI->getVectorIdxTy();
3203 SmallVector<SDValue,8> Ops;
3204 for (unsigned i = 0; i != MaskNumElts; ++i) {
3209 Res = DAG.getUNDEF(EltVT);
3211 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3212 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3214 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3215 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3221 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3222 VT, &Ops[0], Ops.size()));
3225 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3226 const Value *Op0 = I.getOperand(0);
3227 const Value *Op1 = I.getOperand(1);
3228 Type *AggTy = I.getType();
3229 Type *ValTy = Op1->getType();
3230 bool IntoUndef = isa<UndefValue>(Op0);
3231 bool FromUndef = isa<UndefValue>(Op1);
3233 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3235 const TargetLowering *TLI = TM.getTargetLowering();
3236 SmallVector<EVT, 4> AggValueVTs;
3237 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3238 SmallVector<EVT, 4> ValValueVTs;
3239 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3241 unsigned NumAggValues = AggValueVTs.size();
3242 unsigned NumValValues = ValValueVTs.size();
3243 SmallVector<SDValue, 4> Values(NumAggValues);
3245 SDValue Agg = getValue(Op0);
3247 // Copy the beginning value(s) from the original aggregate.
3248 for (; i != LinearIndex; ++i)
3249 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3250 SDValue(Agg.getNode(), Agg.getResNo() + i);
3251 // Copy values from the inserted value(s).
3253 SDValue Val = getValue(Op1);
3254 for (; i != LinearIndex + NumValValues; ++i)
3255 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3256 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3258 // Copy remaining value(s) from the original aggregate.
3259 for (; i != NumAggValues; ++i)
3260 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3261 SDValue(Agg.getNode(), Agg.getResNo() + i);
3263 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3264 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3265 &Values[0], NumAggValues));
3268 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3269 const Value *Op0 = I.getOperand(0);
3270 Type *AggTy = Op0->getType();
3271 Type *ValTy = I.getType();
3272 bool OutOfUndef = isa<UndefValue>(Op0);
3274 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3276 const TargetLowering *TLI = TM.getTargetLowering();
3277 SmallVector<EVT, 4> ValValueVTs;
3278 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3280 unsigned NumValValues = ValValueVTs.size();
3282 // Ignore a extractvalue that produces an empty object
3283 if (!NumValValues) {
3284 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3288 SmallVector<SDValue, 4> Values(NumValValues);
3290 SDValue Agg = getValue(Op0);
3291 // Copy out the selected value(s).
3292 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3293 Values[i - LinearIndex] =
3295 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3296 SDValue(Agg.getNode(), Agg.getResNo() + i);
3298 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3299 DAG.getVTList(&ValValueVTs[0], NumValValues),
3300 &Values[0], NumValValues));
3303 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3304 Value *Op0 = I.getOperand(0);
3305 // Note that the pointer operand may be a vector of pointers. Take the scalar
3306 // element which holds a pointer.
3307 Type *Ty = Op0->getType()->getScalarType();
3308 unsigned AS = Ty->getPointerAddressSpace();
3309 SDValue N = getValue(Op0);
3311 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3313 const Value *Idx = *OI;
3314 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3315 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3318 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3319 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3320 DAG.getConstant(Offset, N.getValueType()));
3323 Ty = StTy->getElementType(Field);
3325 Ty = cast<SequentialType>(Ty)->getElementType();
3327 // If this is a constant subscript, handle it quickly.
3328 const TargetLowering *TLI = TM.getTargetLowering();
3329 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3330 if (CI->isZero()) continue;
3332 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3334 EVT PTy = TLI->getPointerTy(AS);
3335 unsigned PtrBits = PTy.getSizeInBits();
3337 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3338 DAG.getConstant(Offs, MVT::i64));
3340 OffsVal = DAG.getConstant(Offs, PTy);
3342 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3347 // N = N + Idx * ElementSize;
3348 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3349 DL->getTypeAllocSize(Ty));
3350 SDValue IdxN = getValue(Idx);
3352 // If the index is smaller or larger than intptr_t, truncate or extend
3354 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3356 // If this is a multiply by a power of two, turn it into a shl
3357 // immediately. This is a very common case.
3358 if (ElementSize != 1) {
3359 if (ElementSize.isPowerOf2()) {
3360 unsigned Amt = ElementSize.logBase2();
3361 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3362 N.getValueType(), IdxN,
3363 DAG.getConstant(Amt, IdxN.getValueType()));
3365 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3366 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3367 N.getValueType(), IdxN, Scale);
3371 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3372 N.getValueType(), N, IdxN);
3379 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3380 // If this is a fixed sized alloca in the entry block of the function,
3381 // allocate it statically on the stack.
3382 if (FuncInfo.StaticAllocaMap.count(&I))
3383 return; // getValue will auto-populate this.
3385 Type *Ty = I.getAllocatedType();
3386 const TargetLowering *TLI = TM.getTargetLowering();
3387 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3389 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3392 SDValue AllocSize = getValue(I.getArraySize());
3394 EVT IntPtr = TLI->getPointerTy();
3395 if (AllocSize.getValueType() != IntPtr)
3396 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3398 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3400 DAG.getConstant(TySize, IntPtr));
3402 // Handle alignment. If the requested alignment is less than or equal to
3403 // the stack alignment, ignore it. If the size is greater than or equal to
3404 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3405 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3406 if (Align <= StackAlign)
3409 // Round the size of the allocation up to the stack alignment size
3410 // by add SA-1 to the size.
3411 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3412 AllocSize.getValueType(), AllocSize,
3413 DAG.getIntPtrConstant(StackAlign-1));
3415 // Mask out the low bits for alignment purposes.
3416 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3417 AllocSize.getValueType(), AllocSize,
3418 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3420 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3421 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3422 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3425 DAG.setRoot(DSA.getValue(1));
3427 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3430 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3432 return visitAtomicLoad(I);
3434 const Value *SV = I.getOperand(0);
3435 SDValue Ptr = getValue(SV);
3437 Type *Ty = I.getType();
3439 bool isVolatile = I.isVolatile();
3440 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3441 bool isInvariant = I.getMetadata("invariant.load") != 0;
3442 unsigned Alignment = I.getAlignment();
3443 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3444 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3446 SmallVector<EVT, 4> ValueVTs;
3447 SmallVector<uint64_t, 4> Offsets;
3448 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3449 unsigned NumValues = ValueVTs.size();
3454 bool ConstantMemory = false;
3455 if (isVolatile || NumValues > MaxParallelChains)
3456 // Serialize volatile loads with other side effects.
3458 else if (AA->pointsToConstantMemory(
3459 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3460 // Do not serialize (non-volatile) loads of constant memory with anything.
3461 Root = DAG.getEntryNode();
3462 ConstantMemory = true;
3464 // Do not serialize non-volatile loads against each other.
3465 Root = DAG.getRoot();
3468 const TargetLowering *TLI = TM.getTargetLowering();
3470 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3472 SmallVector<SDValue, 4> Values(NumValues);
3473 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3475 EVT PtrVT = Ptr.getValueType();
3476 unsigned ChainI = 0;
3477 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3478 // Serializing loads here may result in excessive register pressure, and
3479 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3480 // could recover a bit by hoisting nodes upward in the chain by recognizing
3481 // they are side-effect free or do not alias. The optimizer should really
3482 // avoid this case by converting large object/array copies to llvm.memcpy
3483 // (MaxParallelChains should always remain as failsafe).
3484 if (ChainI == MaxParallelChains) {
3485 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3486 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3487 MVT::Other, &Chains[0], ChainI);
3491 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3493 DAG.getConstant(Offsets[i], PtrVT));
3494 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3495 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3496 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3500 Chains[ChainI] = L.getValue(1);
3503 if (!ConstantMemory) {
3504 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3505 MVT::Other, &Chains[0], ChainI);
3509 PendingLoads.push_back(Chain);
3512 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3513 DAG.getVTList(&ValueVTs[0], NumValues),
3514 &Values[0], NumValues));
3517 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3519 return visitAtomicStore(I);
3521 const Value *SrcV = I.getOperand(0);
3522 const Value *PtrV = I.getOperand(1);
3524 SmallVector<EVT, 4> ValueVTs;
3525 SmallVector<uint64_t, 4> Offsets;
3526 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3527 unsigned NumValues = ValueVTs.size();
3531 // Get the lowered operands. Note that we do this after
3532 // checking if NumResults is zero, because with zero results
3533 // the operands won't have values in the map.
3534 SDValue Src = getValue(SrcV);
3535 SDValue Ptr = getValue(PtrV);
3537 SDValue Root = getRoot();
3538 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3540 EVT PtrVT = Ptr.getValueType();
3541 bool isVolatile = I.isVolatile();
3542 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3543 unsigned Alignment = I.getAlignment();
3544 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3546 unsigned ChainI = 0;
3547 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3548 // See visitLoad comments.
3549 if (ChainI == MaxParallelChains) {
3550 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3551 MVT::Other, &Chains[0], ChainI);
3555 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3556 DAG.getConstant(Offsets[i], PtrVT));
3557 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3558 SDValue(Src.getNode(), Src.getResNo() + i),
3559 Add, MachinePointerInfo(PtrV, Offsets[i]),
3560 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3561 Chains[ChainI] = St;
3564 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3565 MVT::Other, &Chains[0], ChainI);
3566 DAG.setRoot(StoreNode);
3569 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3570 SynchronizationScope Scope,
3571 bool Before, SDLoc dl,
3573 const TargetLowering &TLI) {
3574 // Fence, if necessary
3576 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3578 else if (Order == Acquire || Order == Monotonic)
3581 if (Order == AcquireRelease)
3583 else if (Order == Release || Order == Monotonic)
3588 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3589 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3590 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3593 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3594 SDLoc dl = getCurSDLoc();
3595 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3596 AtomicOrdering FailureOrder = I.getFailureOrdering();
3597 SynchronizationScope Scope = I.getSynchScope();
3599 SDValue InChain = getRoot();
3601 const TargetLowering *TLI = TM.getTargetLowering();
3602 if (TLI->getInsertFencesForAtomic())
3603 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3607 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3608 getValue(I.getCompareOperand()).getSimpleValueType(),
3610 getValue(I.getPointerOperand()),
3611 getValue(I.getCompareOperand()),
3612 getValue(I.getNewValOperand()),
3613 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3614 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3615 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder,
3618 SDValue OutChain = L.getValue(1);
3620 if (TLI->getInsertFencesForAtomic())
3621 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3625 DAG.setRoot(OutChain);
3628 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3629 SDLoc dl = getCurSDLoc();
3631 switch (I.getOperation()) {
3632 default: llvm_unreachable("Unknown atomicrmw operation");
3633 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3634 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3635 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3636 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3637 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3638 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3639 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3640 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3641 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3642 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3643 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3645 AtomicOrdering Order = I.getOrdering();
3646 SynchronizationScope Scope = I.getSynchScope();
3648 SDValue InChain = getRoot();
3650 const TargetLowering *TLI = TM.getTargetLowering();
3651 if (TLI->getInsertFencesForAtomic())
3652 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3656 DAG.getAtomic(NT, dl,
3657 getValue(I.getValOperand()).getSimpleValueType(),
3659 getValue(I.getPointerOperand()),
3660 getValue(I.getValOperand()),
3661 I.getPointerOperand(), 0 /* Alignment */,
3662 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3665 SDValue OutChain = L.getValue(1);
3667 if (TLI->getInsertFencesForAtomic())
3668 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3672 DAG.setRoot(OutChain);
3675 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3676 SDLoc dl = getCurSDLoc();
3677 const TargetLowering *TLI = TM.getTargetLowering();
3680 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3681 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3682 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3685 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3686 SDLoc dl = getCurSDLoc();
3687 AtomicOrdering Order = I.getOrdering();
3688 SynchronizationScope Scope = I.getSynchScope();
3690 SDValue InChain = getRoot();
3692 const TargetLowering *TLI = TM.getTargetLowering();
3693 EVT VT = TLI->getValueType(I.getType());
3695 if (I.getAlignment() < VT.getSizeInBits() / 8)
3696 report_fatal_error("Cannot generate unaligned atomic load");
3698 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3700 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3701 getValue(I.getPointerOperand()),
3702 I.getPointerOperand(), I.getAlignment(),
3703 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3706 SDValue OutChain = L.getValue(1);
3708 if (TLI->getInsertFencesForAtomic())
3709 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3713 DAG.setRoot(OutChain);
3716 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3717 SDLoc dl = getCurSDLoc();
3719 AtomicOrdering Order = I.getOrdering();
3720 SynchronizationScope Scope = I.getSynchScope();
3722 SDValue InChain = getRoot();
3724 const TargetLowering *TLI = TM.getTargetLowering();
3725 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3727 if (I.getAlignment() < VT.getSizeInBits() / 8)
3728 report_fatal_error("Cannot generate unaligned atomic store");
3730 if (TLI->getInsertFencesForAtomic())
3731 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3735 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3737 getValue(I.getPointerOperand()),
3738 getValue(I.getValueOperand()),
3739 I.getPointerOperand(), I.getAlignment(),
3740 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3743 if (TLI->getInsertFencesForAtomic())
3744 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3747 DAG.setRoot(OutChain);
3750 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3752 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3753 unsigned Intrinsic) {
3754 bool HasChain = !I.doesNotAccessMemory();
3755 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3757 // Build the operand list.
3758 SmallVector<SDValue, 8> Ops;
3759 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3761 // We don't need to serialize loads against other loads.
3762 Ops.push_back(DAG.getRoot());
3764 Ops.push_back(getRoot());
3768 // Info is set by getTgtMemInstrinsic
3769 TargetLowering::IntrinsicInfo Info;
3770 const TargetLowering *TLI = TM.getTargetLowering();
3771 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3773 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3774 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3775 Info.opc == ISD::INTRINSIC_W_CHAIN)
3776 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3778 // Add all operands of the call to the operand list.
3779 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3780 SDValue Op = getValue(I.getArgOperand(i));
3784 SmallVector<EVT, 4> ValueVTs;
3785 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3788 ValueVTs.push_back(MVT::Other);
3790 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3794 if (IsTgtIntrinsic) {
3795 // This is target intrinsic that touches memory
3796 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3797 VTs, &Ops[0], Ops.size(),
3799 MachinePointerInfo(Info.ptrVal, Info.offset),
3800 Info.align, Info.vol,
3801 Info.readMem, Info.writeMem);
3802 } else if (!HasChain) {
3803 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3804 VTs, &Ops[0], Ops.size());
3805 } else if (!I.getType()->isVoidTy()) {
3806 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3807 VTs, &Ops[0], Ops.size());
3809 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3810 VTs, &Ops[0], Ops.size());
3814 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3816 PendingLoads.push_back(Chain);
3821 if (!I.getType()->isVoidTy()) {
3822 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3823 EVT VT = TLI->getValueType(PTy);
3824 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3827 setValue(&I, Result);
3831 /// GetSignificand - Get the significand and build it into a floating-point
3832 /// number with exponent of 1:
3834 /// Op = (Op & 0x007fffff) | 0x3f800000;
3836 /// where Op is the hexadecimal representation of floating point value.
3838 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3839 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3840 DAG.getConstant(0x007fffff, MVT::i32));
3841 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3842 DAG.getConstant(0x3f800000, MVT::i32));
3843 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3846 /// GetExponent - Get the exponent:
3848 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3850 /// where Op is the hexadecimal representation of floating point value.
3852 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3854 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3855 DAG.getConstant(0x7f800000, MVT::i32));
3856 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3857 DAG.getConstant(23, TLI.getPointerTy()));
3858 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3859 DAG.getConstant(127, MVT::i32));
3860 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3863 /// getF32Constant - Get 32-bit floating point constant.
3865 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3866 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3870 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3871 /// limited-precision mode.
3872 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3873 const TargetLowering &TLI) {
3874 if (Op.getValueType() == MVT::f32 &&
3875 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3877 // Put the exponent in the right bit position for later addition to the
3880 // #define LOG2OFe 1.4426950f
3881 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3882 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3883 getF32Constant(DAG, 0x3fb8aa3b));
3884 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3886 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3887 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3888 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3890 // IntegerPartOfX <<= 23;
3891 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3892 DAG.getConstant(23, TLI.getPointerTy()));
3894 SDValue TwoToFracPartOfX;
3895 if (LimitFloatPrecision <= 6) {
3896 // For floating-point precision of 6:
3898 // TwoToFractionalPartOfX =
3900 // (0.735607626f + 0.252464424f * x) * x;
3902 // error 0.0144103317, which is 6 bits
3903 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3904 getF32Constant(DAG, 0x3e814304));
3905 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3906 getF32Constant(DAG, 0x3f3c50c8));
3907 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3908 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3909 getF32Constant(DAG, 0x3f7f5e7e));
3910 } else if (LimitFloatPrecision <= 12) {
3911 // For floating-point precision of 12:
3913 // TwoToFractionalPartOfX =
3916 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3918 // 0.000107046256 error, which is 13 to 14 bits
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3920 getF32Constant(DAG, 0x3da235e3));
3921 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3922 getF32Constant(DAG, 0x3e65b8f3));
3923 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3924 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3925 getF32Constant(DAG, 0x3f324b07));
3926 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3927 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3928 getF32Constant(DAG, 0x3f7ff8fd));
3929 } else { // LimitFloatPrecision <= 18
3930 // For floating-point precision of 18:
3932 // TwoToFractionalPartOfX =
3936 // (0.554906021e-1f +
3937 // (0.961591928e-2f +
3938 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3940 // error 2.47208000*10^(-7), which is better than 18 bits
3941 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3942 getF32Constant(DAG, 0x3924b03e));
3943 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3944 getF32Constant(DAG, 0x3ab24b87));
3945 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3946 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3947 getF32Constant(DAG, 0x3c1d8c17));
3948 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3949 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3950 getF32Constant(DAG, 0x3d634a1d));
3951 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3952 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3953 getF32Constant(DAG, 0x3e75fe14));
3954 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3955 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3956 getF32Constant(DAG, 0x3f317234));
3957 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3958 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3959 getF32Constant(DAG, 0x3f800000));
3962 // Add the exponent into the result in integer domain.
3963 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3964 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3965 DAG.getNode(ISD::ADD, dl, MVT::i32,
3966 t13, IntegerPartOfX));
3969 // No special expansion.
3970 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3973 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3974 /// limited-precision mode.
3975 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3976 const TargetLowering &TLI) {
3977 if (Op.getValueType() == MVT::f32 &&
3978 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3979 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3981 // Scale the exponent by log(2) [0.69314718f].
3982 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3983 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3984 getF32Constant(DAG, 0x3f317218));
3986 // Get the significand and build it into a floating-point number with
3988 SDValue X = GetSignificand(DAG, Op1, dl);
3990 SDValue LogOfMantissa;
3991 if (LimitFloatPrecision <= 6) {
3992 // For floating-point precision of 6:
3996 // (1.4034025f - 0.23903021f * x) * x;
3998 // error 0.0034276066, which is better than 8 bits
3999 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4000 getF32Constant(DAG, 0xbe74c456));
4001 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4002 getF32Constant(DAG, 0x3fb3a2b1));
4003 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4004 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4005 getF32Constant(DAG, 0x3f949a29));
4006 } else if (LimitFloatPrecision <= 12) {
4007 // For floating-point precision of 12:
4013 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4015 // error 0.000061011436, which is 14 bits
4016 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4017 getF32Constant(DAG, 0xbd67b6d6));
4018 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4019 getF32Constant(DAG, 0x3ee4f4b8));
4020 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4021 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4022 getF32Constant(DAG, 0x3fbc278b));
4023 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4024 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4025 getF32Constant(DAG, 0x40348e95));
4026 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4027 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4028 getF32Constant(DAG, 0x3fdef31a));
4029 } else { // LimitFloatPrecision <= 18
4030 // For floating-point precision of 18:
4038 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4040 // error 0.0000023660568, which is better than 18 bits
4041 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4042 getF32Constant(DAG, 0xbc91e5ac));
4043 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4044 getF32Constant(DAG, 0x3e4350aa));
4045 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4046 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4047 getF32Constant(DAG, 0x3f60d3e3));
4048 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4049 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4050 getF32Constant(DAG, 0x4011cdf0));
4051 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4052 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4053 getF32Constant(DAG, 0x406cfd1c));
4054 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4055 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4056 getF32Constant(DAG, 0x408797cb));
4057 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4058 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4059 getF32Constant(DAG, 0x4006dcab));
4062 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4065 // No special expansion.
4066 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4069 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4070 /// limited-precision mode.
4071 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4072 const TargetLowering &TLI) {
4073 if (Op.getValueType() == MVT::f32 &&
4074 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4075 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4077 // Get the exponent.
4078 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4080 // Get the significand and build it into a floating-point number with
4082 SDValue X = GetSignificand(DAG, Op1, dl);
4084 // Different possible minimax approximations of significand in
4085 // floating-point for various degrees of accuracy over [1,2].
4086 SDValue Log2ofMantissa;
4087 if (LimitFloatPrecision <= 6) {
4088 // For floating-point precision of 6:
4090 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4092 // error 0.0049451742, which is more than 7 bits
4093 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4094 getF32Constant(DAG, 0xbeb08fe0));
4095 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4096 getF32Constant(DAG, 0x40019463));
4097 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4098 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4099 getF32Constant(DAG, 0x3fd6633d));
4100 } else if (LimitFloatPrecision <= 12) {
4101 // For floating-point precision of 12:
4107 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4109 // error 0.0000876136000, which is better than 13 bits
4110 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4111 getF32Constant(DAG, 0xbda7262e));
4112 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4113 getF32Constant(DAG, 0x3f25280b));
4114 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4115 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4116 getF32Constant(DAG, 0x4007b923));
4117 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4118 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4119 getF32Constant(DAG, 0x40823e2f));
4120 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4121 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4122 getF32Constant(DAG, 0x4020d29c));
4123 } else { // LimitFloatPrecision <= 18
4124 // For floating-point precision of 18:
4133 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4135 // error 0.0000018516, which is better than 18 bits
4136 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4137 getF32Constant(DAG, 0xbcd2769e));
4138 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4139 getF32Constant(DAG, 0x3e8ce0b9));
4140 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4141 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4142 getF32Constant(DAG, 0x3fa22ae7));
4143 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4144 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4145 getF32Constant(DAG, 0x40525723));
4146 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4147 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4148 getF32Constant(DAG, 0x40aaf200));
4149 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4150 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4151 getF32Constant(DAG, 0x40c39dad));
4152 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4153 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4154 getF32Constant(DAG, 0x4042902c));
4157 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4160 // No special expansion.
4161 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4164 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4165 /// limited-precision mode.
4166 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4167 const TargetLowering &TLI) {
4168 if (Op.getValueType() == MVT::f32 &&
4169 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4170 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4172 // Scale the exponent by log10(2) [0.30102999f].
4173 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4174 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4175 getF32Constant(DAG, 0x3e9a209a));
4177 // Get the significand and build it into a floating-point number with
4179 SDValue X = GetSignificand(DAG, Op1, dl);
4181 SDValue Log10ofMantissa;
4182 if (LimitFloatPrecision <= 6) {
4183 // For floating-point precision of 6:
4185 // Log10ofMantissa =
4187 // (0.60948995f - 0.10380950f * x) * x;
4189 // error 0.0014886165, which is 6 bits
4190 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4191 getF32Constant(DAG, 0xbdd49a13));
4192 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4193 getF32Constant(DAG, 0x3f1c0789));
4194 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4195 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4196 getF32Constant(DAG, 0x3f011300));
4197 } else if (LimitFloatPrecision <= 12) {
4198 // For floating-point precision of 12:
4200 // Log10ofMantissa =
4203 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4205 // error 0.00019228036, which is better than 12 bits
4206 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4207 getF32Constant(DAG, 0x3d431f31));
4208 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4209 getF32Constant(DAG, 0x3ea21fb2));
4210 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4211 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4212 getF32Constant(DAG, 0x3f6ae232));
4213 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4214 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4215 getF32Constant(DAG, 0x3f25f7c3));
4216 } else { // LimitFloatPrecision <= 18
4217 // For floating-point precision of 18:
4219 // Log10ofMantissa =
4224 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4226 // error 0.0000037995730, which is better than 18 bits
4227 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4228 getF32Constant(DAG, 0x3c5d51ce));
4229 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4230 getF32Constant(DAG, 0x3e00685a));
4231 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4232 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4233 getF32Constant(DAG, 0x3efb6798));
4234 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4235 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4236 getF32Constant(DAG, 0x3f88d192));
4237 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4238 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4239 getF32Constant(DAG, 0x3fc4316c));
4240 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4241 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4242 getF32Constant(DAG, 0x3f57ce70));
4245 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4248 // No special expansion.
4249 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4252 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4253 /// limited-precision mode.
4254 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4255 const TargetLowering &TLI) {
4256 if (Op.getValueType() == MVT::f32 &&
4257 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4258 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4260 // FractionalPartOfX = x - (float)IntegerPartOfX;
4261 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4262 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4264 // IntegerPartOfX <<= 23;
4265 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4266 DAG.getConstant(23, TLI.getPointerTy()));
4268 SDValue TwoToFractionalPartOfX;
4269 if (LimitFloatPrecision <= 6) {
4270 // For floating-point precision of 6:
4272 // TwoToFractionalPartOfX =
4274 // (0.735607626f + 0.252464424f * x) * x;
4276 // error 0.0144103317, which is 6 bits
4277 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4278 getF32Constant(DAG, 0x3e814304));
4279 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4280 getF32Constant(DAG, 0x3f3c50c8));
4281 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4282 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4283 getF32Constant(DAG, 0x3f7f5e7e));
4284 } else if (LimitFloatPrecision <= 12) {
4285 // For floating-point precision of 12:
4287 // TwoToFractionalPartOfX =
4290 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4292 // error 0.000107046256, which is 13 to 14 bits
4293 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4294 getF32Constant(DAG, 0x3da235e3));
4295 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4296 getF32Constant(DAG, 0x3e65b8f3));
4297 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4298 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4299 getF32Constant(DAG, 0x3f324b07));
4300 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4301 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4302 getF32Constant(DAG, 0x3f7ff8fd));
4303 } else { // LimitFloatPrecision <= 18
4304 // For floating-point precision of 18:
4306 // TwoToFractionalPartOfX =
4310 // (0.554906021e-1f +
4311 // (0.961591928e-2f +
4312 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4313 // error 2.47208000*10^(-7), which is better than 18 bits
4314 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4315 getF32Constant(DAG, 0x3924b03e));
4316 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4317 getF32Constant(DAG, 0x3ab24b87));
4318 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4319 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4320 getF32Constant(DAG, 0x3c1d8c17));
4321 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4322 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4323 getF32Constant(DAG, 0x3d634a1d));
4324 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4325 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4326 getF32Constant(DAG, 0x3e75fe14));
4327 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4328 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4329 getF32Constant(DAG, 0x3f317234));
4330 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4331 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4332 getF32Constant(DAG, 0x3f800000));
4335 // Add the exponent into the result in integer domain.
4336 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4337 TwoToFractionalPartOfX);
4338 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4339 DAG.getNode(ISD::ADD, dl, MVT::i32,
4340 t13, IntegerPartOfX));
4343 // No special expansion.
4344 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4347 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4348 /// limited-precision mode with x == 10.0f.
4349 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4350 SelectionDAG &DAG, const TargetLowering &TLI) {
4351 bool IsExp10 = false;
4352 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4353 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4354 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4356 IsExp10 = LHSC->isExactlyValue(Ten);
4361 // Put the exponent in the right bit position for later addition to the
4364 // #define LOG2OF10 3.3219281f
4365 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4366 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4367 getF32Constant(DAG, 0x40549a78));
4368 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4370 // FractionalPartOfX = x - (float)IntegerPartOfX;
4371 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4372 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4374 // IntegerPartOfX <<= 23;
4375 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4376 DAG.getConstant(23, TLI.getPointerTy()));
4378 SDValue TwoToFractionalPartOfX;
4379 if (LimitFloatPrecision <= 6) {
4380 // For floating-point precision of 6:
4382 // twoToFractionalPartOfX =
4384 // (0.735607626f + 0.252464424f * x) * x;
4386 // error 0.0144103317, which is 6 bits
4387 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4388 getF32Constant(DAG, 0x3e814304));
4389 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4390 getF32Constant(DAG, 0x3f3c50c8));
4391 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4392 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4393 getF32Constant(DAG, 0x3f7f5e7e));
4394 } else if (LimitFloatPrecision <= 12) {
4395 // For floating-point precision of 12:
4397 // TwoToFractionalPartOfX =
4400 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4402 // error 0.000107046256, which is 13 to 14 bits
4403 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4404 getF32Constant(DAG, 0x3da235e3));
4405 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4406 getF32Constant(DAG, 0x3e65b8f3));
4407 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4408 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4409 getF32Constant(DAG, 0x3f324b07));
4410 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4411 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4412 getF32Constant(DAG, 0x3f7ff8fd));
4413 } else { // LimitFloatPrecision <= 18
4414 // For floating-point precision of 18:
4416 // TwoToFractionalPartOfX =
4420 // (0.554906021e-1f +
4421 // (0.961591928e-2f +
4422 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4423 // error 2.47208000*10^(-7), which is better than 18 bits
4424 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4425 getF32Constant(DAG, 0x3924b03e));
4426 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4427 getF32Constant(DAG, 0x3ab24b87));
4428 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4429 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4430 getF32Constant(DAG, 0x3c1d8c17));
4431 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4432 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4433 getF32Constant(DAG, 0x3d634a1d));
4434 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4435 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4436 getF32Constant(DAG, 0x3e75fe14));
4437 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4438 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4439 getF32Constant(DAG, 0x3f317234));
4440 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4441 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4442 getF32Constant(DAG, 0x3f800000));
4445 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4446 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4447 DAG.getNode(ISD::ADD, dl, MVT::i32,
4448 t13, IntegerPartOfX));
4451 // No special expansion.
4452 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4456 /// ExpandPowI - Expand a llvm.powi intrinsic.
4457 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4458 SelectionDAG &DAG) {
4459 // If RHS is a constant, we can expand this out to a multiplication tree,
4460 // otherwise we end up lowering to a call to __powidf2 (for example). When
4461 // optimizing for size, we only want to do this if the expansion would produce
4462 // a small number of multiplies, otherwise we do the full expansion.
4463 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4464 // Get the exponent as a positive value.
4465 unsigned Val = RHSC->getSExtValue();
4466 if ((int)Val < 0) Val = -Val;
4468 // powi(x, 0) -> 1.0
4470 return DAG.getConstantFP(1.0, LHS.getValueType());
4472 const Function *F = DAG.getMachineFunction().getFunction();
4473 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4474 Attribute::OptimizeForSize) ||
4475 // If optimizing for size, don't insert too many multiplies. This
4476 // inserts up to 5 multiplies.
4477 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4478 // We use the simple binary decomposition method to generate the multiply
4479 // sequence. There are more optimal ways to do this (for example,
4480 // powi(x,15) generates one more multiply than it should), but this has
4481 // the benefit of being both really simple and much better than a libcall.
4482 SDValue Res; // Logically starts equal to 1.0
4483 SDValue CurSquare = LHS;
4487 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4489 Res = CurSquare; // 1.0*CurSquare.
4492 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4493 CurSquare, CurSquare);
4497 // If the original was negative, invert the result, producing 1/(x*x*x).
4498 if (RHSC->getSExtValue() < 0)
4499 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4500 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4505 // Otherwise, expand to a libcall.
4506 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4509 // getTruncatedArgReg - Find underlying register used for an truncated
4511 static unsigned getTruncatedArgReg(const SDValue &N) {
4512 if (N.getOpcode() != ISD::TRUNCATE)
4515 const SDValue &Ext = N.getOperand(0);
4516 if (Ext.getOpcode() == ISD::AssertZext ||
4517 Ext.getOpcode() == ISD::AssertSext) {
4518 const SDValue &CFR = Ext.getOperand(0);
4519 if (CFR.getOpcode() == ISD::CopyFromReg)
4520 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4521 if (CFR.getOpcode() == ISD::TRUNCATE)
4522 return getTruncatedArgReg(CFR);
4527 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4528 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4529 /// At the end of instruction selection, they will be inserted to the entry BB.
4531 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4534 const Argument *Arg = dyn_cast<Argument>(V);
4538 MachineFunction &MF = DAG.getMachineFunction();
4539 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4541 // Ignore inlined function arguments here.
4542 DIVariable DV(Variable);
4543 if (DV.isInlinedFnArgument(MF.getFunction()))
4546 Optional<MachineOperand> Op;
4547 // Some arguments' frame index is recorded during argument lowering.
4548 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4549 Op = MachineOperand::CreateFI(FI);
4551 if (!Op && N.getNode()) {
4553 if (N.getOpcode() == ISD::CopyFromReg)
4554 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4556 Reg = getTruncatedArgReg(N);
4557 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4558 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4559 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4564 Op = MachineOperand::CreateReg(Reg, false);
4568 // Check if ValueMap has reg number.
4569 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4570 if (VMI != FuncInfo.ValueMap.end())
4571 Op = MachineOperand::CreateReg(VMI->second, false);
4574 if (!Op && N.getNode())
4575 // Check if frame index is available.
4576 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4577 if (FrameIndexSDNode *FINode =
4578 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4579 Op = MachineOperand::CreateFI(FINode->getIndex());
4584 // FIXME: This does not handle register-indirect values at offset 0.
4585 bool IsIndirect = Offset != 0;
4587 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4588 TII->get(TargetOpcode::DBG_VALUE),
4590 Op->getReg(), Offset, Variable));
4592 FuncInfo.ArgDbgValues.push_back(
4593 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4594 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4599 // VisualStudio defines setjmp as _setjmp
4600 #if defined(_MSC_VER) && defined(setjmp) && \
4601 !defined(setjmp_undefined_for_msvc)
4602 # pragma push_macro("setjmp")
4604 # define setjmp_undefined_for_msvc
4607 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4608 /// we want to emit this as a call to a named external function, return the name
4609 /// otherwise lower it and return null.
4611 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4612 const TargetLowering *TLI = TM.getTargetLowering();
4613 SDLoc sdl = getCurSDLoc();
4614 DebugLoc dl = getCurDebugLoc();
4617 switch (Intrinsic) {
4619 // By default, turn this into a target intrinsic node.
4620 visitTargetIntrinsic(I, Intrinsic);
4622 case Intrinsic::vastart: visitVAStart(I); return 0;
4623 case Intrinsic::vaend: visitVAEnd(I); return 0;
4624 case Intrinsic::vacopy: visitVACopy(I); return 0;
4625 case Intrinsic::returnaddress:
4626 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4627 getValue(I.getArgOperand(0))));
4629 case Intrinsic::frameaddress:
4630 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4631 getValue(I.getArgOperand(0))));
4633 case Intrinsic::setjmp:
4634 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4635 case Intrinsic::longjmp:
4636 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4637 case Intrinsic::memcpy: {
4638 // Assert for address < 256 since we support only user defined address
4640 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4642 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4644 "Unknown address space");
4645 SDValue Op1 = getValue(I.getArgOperand(0));
4646 SDValue Op2 = getValue(I.getArgOperand(1));
4647 SDValue Op3 = getValue(I.getArgOperand(2));
4648 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4650 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4651 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4652 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4653 MachinePointerInfo(I.getArgOperand(0)),
4654 MachinePointerInfo(I.getArgOperand(1))));
4657 case Intrinsic::memset: {
4658 // Assert for address < 256 since we support only user defined address
4660 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4662 "Unknown address space");
4663 SDValue Op1 = getValue(I.getArgOperand(0));
4664 SDValue Op2 = getValue(I.getArgOperand(1));
4665 SDValue Op3 = getValue(I.getArgOperand(2));
4666 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4668 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4669 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4670 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4671 MachinePointerInfo(I.getArgOperand(0))));
4674 case Intrinsic::memmove: {
4675 // Assert for address < 256 since we support only user defined address
4677 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4679 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4681 "Unknown address space");
4682 SDValue Op1 = getValue(I.getArgOperand(0));
4683 SDValue Op2 = getValue(I.getArgOperand(1));
4684 SDValue Op3 = getValue(I.getArgOperand(2));
4685 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4687 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4688 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4689 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4690 MachinePointerInfo(I.getArgOperand(0)),
4691 MachinePointerInfo(I.getArgOperand(1))));
4694 case Intrinsic::dbg_declare: {
4695 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4696 MDNode *Variable = DI.getVariable();
4697 const Value *Address = DI.getAddress();
4698 DIVariable DIVar(Variable);
4699 assert((!DIVar || DIVar.isVariable()) &&
4700 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4701 if (!Address || !DIVar) {
4702 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4706 // Check if address has undef value.
4707 if (isa<UndefValue>(Address) ||
4708 (Address->use_empty() && !isa<Argument>(Address))) {
4709 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4713 SDValue &N = NodeMap[Address];
4714 if (!N.getNode() && isa<Argument>(Address))
4715 // Check unused arguments map.
4716 N = UnusedArgNodeMap[Address];
4719 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4720 Address = BCI->getOperand(0);
4721 // Parameters are handled specially.
4723 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4724 isa<Argument>(Address));
4726 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4728 if (isParameter && !AI) {
4729 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4731 // Byval parameter. We have a frame index at this point.
4732 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4733 0, dl, SDNodeOrder);
4735 // Address is an argument, so try to emit its dbg value using
4736 // virtual register info from the FuncInfo.ValueMap.
4737 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4741 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4742 0, dl, SDNodeOrder);
4744 // Can't do anything with other non-AI cases yet.
4745 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4746 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4747 DEBUG(Address->dump());
4750 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4752 // If Address is an argument then try to emit its dbg value using
4753 // virtual register info from the FuncInfo.ValueMap.
4754 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4755 // If variable is pinned by a alloca in dominating bb then
4756 // use StaticAllocaMap.
4757 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4758 if (AI->getParent() != DI.getParent()) {
4759 DenseMap<const AllocaInst*, int>::iterator SI =
4760 FuncInfo.StaticAllocaMap.find(AI);
4761 if (SI != FuncInfo.StaticAllocaMap.end()) {
4762 SDV = DAG.getDbgValue(Variable, SI->second,
4763 0, dl, SDNodeOrder);
4764 DAG.AddDbgValue(SDV, 0, false);
4769 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4774 case Intrinsic::dbg_value: {
4775 const DbgValueInst &DI = cast<DbgValueInst>(I);
4776 DIVariable DIVar(DI.getVariable());
4777 assert((!DIVar || DIVar.isVariable()) &&
4778 "Variable in DbgValueInst should be either null or a DIVariable.");
4782 MDNode *Variable = DI.getVariable();
4783 uint64_t Offset = DI.getOffset();
4784 const Value *V = DI.getValue();
4789 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4790 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4791 DAG.AddDbgValue(SDV, 0, false);
4793 // Do not use getValue() in here; we don't want to generate code at
4794 // this point if it hasn't been done yet.
4795 SDValue N = NodeMap[V];
4796 if (!N.getNode() && isa<Argument>(V))
4797 // Check unused arguments map.
4798 N = UnusedArgNodeMap[V];
4800 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4801 SDV = DAG.getDbgValue(Variable, N.getNode(),
4802 N.getResNo(), Offset, dl, SDNodeOrder);
4803 DAG.AddDbgValue(SDV, N.getNode(), false);
4805 } else if (!V->use_empty() ) {
4806 // Do not call getValue(V) yet, as we don't want to generate code.
4807 // Remember it for later.
4808 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4809 DanglingDebugInfoMap[V] = DDI;
4811 // We may expand this to cover more cases. One case where we have no
4812 // data available is an unreferenced parameter.
4813 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4817 // Build a debug info table entry.
4818 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4819 V = BCI->getOperand(0);
4820 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4821 // Don't handle byval struct arguments or VLAs, for example.
4823 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4824 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4827 DenseMap<const AllocaInst*, int>::iterator SI =
4828 FuncInfo.StaticAllocaMap.find(AI);
4829 if (SI == FuncInfo.StaticAllocaMap.end())
4831 int FI = SI->second;
4833 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4834 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4835 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4839 case Intrinsic::eh_typeid_for: {
4840 // Find the type id for the given typeinfo.
4841 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4842 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4843 Res = DAG.getConstant(TypeID, MVT::i32);
4848 case Intrinsic::eh_return_i32:
4849 case Intrinsic::eh_return_i64:
4850 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4851 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4854 getValue(I.getArgOperand(0)),
4855 getValue(I.getArgOperand(1))));
4857 case Intrinsic::eh_unwind_init:
4858 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4860 case Intrinsic::eh_dwarf_cfa: {
4861 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4862 TLI->getPointerTy());
4863 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4864 CfaArg.getValueType(),
4865 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4866 CfaArg.getValueType()),
4868 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4869 TLI->getPointerTy(),
4870 DAG.getConstant(0, TLI->getPointerTy()));
4871 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4875 case Intrinsic::eh_sjlj_callsite: {
4876 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4877 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4878 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4879 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4881 MMI.setCurrentCallSite(CI->getZExtValue());
4884 case Intrinsic::eh_sjlj_functioncontext: {
4885 // Get and store the index of the function context.
4886 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4888 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4889 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4890 MFI->setFunctionContextIndex(FI);
4893 case Intrinsic::eh_sjlj_setjmp: {
4896 Ops[1] = getValue(I.getArgOperand(0));
4897 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4898 DAG.getVTList(MVT::i32, MVT::Other),
4900 setValue(&I, Op.getValue(0));
4901 DAG.setRoot(Op.getValue(1));
4904 case Intrinsic::eh_sjlj_longjmp: {
4905 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4906 getRoot(), getValue(I.getArgOperand(0))));
4910 case Intrinsic::x86_mmx_pslli_w:
4911 case Intrinsic::x86_mmx_pslli_d:
4912 case Intrinsic::x86_mmx_pslli_q:
4913 case Intrinsic::x86_mmx_psrli_w:
4914 case Intrinsic::x86_mmx_psrli_d:
4915 case Intrinsic::x86_mmx_psrli_q:
4916 case Intrinsic::x86_mmx_psrai_w:
4917 case Intrinsic::x86_mmx_psrai_d: {
4918 SDValue ShAmt = getValue(I.getArgOperand(1));
4919 if (isa<ConstantSDNode>(ShAmt)) {
4920 visitTargetIntrinsic(I, Intrinsic);
4923 unsigned NewIntrinsic = 0;
4924 EVT ShAmtVT = MVT::v2i32;
4925 switch (Intrinsic) {
4926 case Intrinsic::x86_mmx_pslli_w:
4927 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4929 case Intrinsic::x86_mmx_pslli_d:
4930 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4932 case Intrinsic::x86_mmx_pslli_q:
4933 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4935 case Intrinsic::x86_mmx_psrli_w:
4936 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4938 case Intrinsic::x86_mmx_psrli_d:
4939 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4941 case Intrinsic::x86_mmx_psrli_q:
4942 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4944 case Intrinsic::x86_mmx_psrai_w:
4945 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4947 case Intrinsic::x86_mmx_psrai_d:
4948 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4953 // The vector shift intrinsics with scalars uses 32b shift amounts but
4954 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4956 // We must do this early because v2i32 is not a legal type.
4959 ShOps[1] = DAG.getConstant(0, MVT::i32);
4960 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4961 EVT DestVT = TLI->getValueType(I.getType());
4962 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4963 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4964 DAG.getConstant(NewIntrinsic, MVT::i32),
4965 getValue(I.getArgOperand(0)), ShAmt);
4969 case Intrinsic::x86_avx_vinsertf128_pd_256:
4970 case Intrinsic::x86_avx_vinsertf128_ps_256:
4971 case Intrinsic::x86_avx_vinsertf128_si_256:
4972 case Intrinsic::x86_avx2_vinserti128: {
4973 EVT DestVT = TLI->getValueType(I.getType());
4974 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4975 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4976 ElVT.getVectorNumElements();
4977 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4978 getValue(I.getArgOperand(0)),
4979 getValue(I.getArgOperand(1)),
4980 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4984 case Intrinsic::x86_avx_vextractf128_pd_256:
4985 case Intrinsic::x86_avx_vextractf128_ps_256:
4986 case Intrinsic::x86_avx_vextractf128_si_256:
4987 case Intrinsic::x86_avx2_vextracti128: {
4988 EVT DestVT = TLI->getValueType(I.getType());
4989 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4990 DestVT.getVectorNumElements();
4991 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
4992 getValue(I.getArgOperand(0)),
4993 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4997 case Intrinsic::convertff:
4998 case Intrinsic::convertfsi:
4999 case Intrinsic::convertfui:
5000 case Intrinsic::convertsif:
5001 case Intrinsic::convertuif:
5002 case Intrinsic::convertss:
5003 case Intrinsic::convertsu:
5004 case Intrinsic::convertus:
5005 case Intrinsic::convertuu: {
5006 ISD::CvtCode Code = ISD::CVT_INVALID;
5007 switch (Intrinsic) {
5008 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5009 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5010 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5011 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5012 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5013 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5014 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5015 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5016 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5017 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5019 EVT DestVT = TLI->getValueType(I.getType());
5020 const Value *Op1 = I.getArgOperand(0);
5021 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5022 DAG.getValueType(DestVT),
5023 DAG.getValueType(getValue(Op1).getValueType()),
5024 getValue(I.getArgOperand(1)),
5025 getValue(I.getArgOperand(2)),
5030 case Intrinsic::powi:
5031 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5032 getValue(I.getArgOperand(1)), DAG));
5034 case Intrinsic::log:
5035 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5037 case Intrinsic::log2:
5038 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5040 case Intrinsic::log10:
5041 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5043 case Intrinsic::exp:
5044 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5046 case Intrinsic::exp2:
5047 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5049 case Intrinsic::pow:
5050 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5051 getValue(I.getArgOperand(1)), DAG, *TLI));
5053 case Intrinsic::sqrt:
5054 case Intrinsic::fabs:
5055 case Intrinsic::sin:
5056 case Intrinsic::cos:
5057 case Intrinsic::floor:
5058 case Intrinsic::ceil:
5059 case Intrinsic::trunc:
5060 case Intrinsic::rint:
5061 case Intrinsic::nearbyint:
5062 case Intrinsic::round: {
5064 switch (Intrinsic) {
5065 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5066 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5067 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5068 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5069 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5070 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5071 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5072 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5073 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5074 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5075 case Intrinsic::round: Opcode = ISD::FROUND; break;
5078 setValue(&I, DAG.getNode(Opcode, sdl,
5079 getValue(I.getArgOperand(0)).getValueType(),
5080 getValue(I.getArgOperand(0))));
5083 case Intrinsic::copysign:
5084 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5085 getValue(I.getArgOperand(0)).getValueType(),
5086 getValue(I.getArgOperand(0)),
5087 getValue(I.getArgOperand(1))));
5089 case Intrinsic::fma:
5090 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5091 getValue(I.getArgOperand(0)).getValueType(),
5092 getValue(I.getArgOperand(0)),
5093 getValue(I.getArgOperand(1)),
5094 getValue(I.getArgOperand(2))));
5096 case Intrinsic::fmuladd: {
5097 EVT VT = TLI->getValueType(I.getType());
5098 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5099 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5100 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5101 getValue(I.getArgOperand(0)).getValueType(),
5102 getValue(I.getArgOperand(0)),
5103 getValue(I.getArgOperand(1)),
5104 getValue(I.getArgOperand(2))));
5106 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5107 getValue(I.getArgOperand(0)).getValueType(),
5108 getValue(I.getArgOperand(0)),
5109 getValue(I.getArgOperand(1)));
5110 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5111 getValue(I.getArgOperand(0)).getValueType(),
5113 getValue(I.getArgOperand(2)));
5118 case Intrinsic::convert_to_fp16:
5119 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
5120 MVT::i16, getValue(I.getArgOperand(0))));
5122 case Intrinsic::convert_from_fp16:
5123 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
5124 MVT::f32, getValue(I.getArgOperand(0))));
5126 case Intrinsic::pcmarker: {
5127 SDValue Tmp = getValue(I.getArgOperand(0));
5128 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5131 case Intrinsic::readcyclecounter: {
5132 SDValue Op = getRoot();
5133 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5134 DAG.getVTList(MVT::i64, MVT::Other),
5137 DAG.setRoot(Res.getValue(1));
5140 case Intrinsic::bswap:
5141 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5142 getValue(I.getArgOperand(0)).getValueType(),
5143 getValue(I.getArgOperand(0))));
5145 case Intrinsic::cttz: {
5146 SDValue Arg = getValue(I.getArgOperand(0));
5147 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5148 EVT Ty = Arg.getValueType();
5149 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5153 case Intrinsic::ctlz: {
5154 SDValue Arg = getValue(I.getArgOperand(0));
5155 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5156 EVT Ty = Arg.getValueType();
5157 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5161 case Intrinsic::ctpop: {
5162 SDValue Arg = getValue(I.getArgOperand(0));
5163 EVT Ty = Arg.getValueType();
5164 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5167 case Intrinsic::stacksave: {
5168 SDValue Op = getRoot();
5169 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5170 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5172 DAG.setRoot(Res.getValue(1));
5175 case Intrinsic::stackrestore: {
5176 Res = getValue(I.getArgOperand(0));
5177 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5180 case Intrinsic::stackprotector: {
5181 // Emit code into the DAG to store the stack guard onto the stack.
5182 MachineFunction &MF = DAG.getMachineFunction();
5183 MachineFrameInfo *MFI = MF.getFrameInfo();
5184 EVT PtrTy = TLI->getPointerTy();
5186 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5187 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5189 int FI = FuncInfo.StaticAllocaMap[Slot];
5190 MFI->setStackProtectorIndex(FI);
5192 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5194 // Store the stack protector onto the stack.
5195 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5196 MachinePointerInfo::getFixedStack(FI),
5202 case Intrinsic::objectsize: {
5203 // If we don't know by now, we're never going to know.
5204 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5206 assert(CI && "Non-constant type in __builtin_object_size?");
5208 SDValue Arg = getValue(I.getCalledValue());
5209 EVT Ty = Arg.getValueType();
5212 Res = DAG.getConstant(-1ULL, Ty);
5214 Res = DAG.getConstant(0, Ty);
5219 case Intrinsic::annotation:
5220 case Intrinsic::ptr_annotation:
5221 // Drop the intrinsic, but forward the value
5222 setValue(&I, getValue(I.getOperand(0)));
5224 case Intrinsic::var_annotation:
5225 // Discard annotate attributes
5228 case Intrinsic::init_trampoline: {
5229 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5233 Ops[1] = getValue(I.getArgOperand(0));
5234 Ops[2] = getValue(I.getArgOperand(1));
5235 Ops[3] = getValue(I.getArgOperand(2));
5236 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5237 Ops[5] = DAG.getSrcValue(F);
5239 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5244 case Intrinsic::adjust_trampoline: {
5245 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5246 TLI->getPointerTy(),
5247 getValue(I.getArgOperand(0))));
5250 case Intrinsic::gcroot:
5252 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5253 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5255 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5256 GFI->addStackRoot(FI->getIndex(), TypeMap);
5259 case Intrinsic::gcread:
5260 case Intrinsic::gcwrite:
5261 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5262 case Intrinsic::flt_rounds:
5263 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5266 case Intrinsic::expect: {
5267 // Just replace __builtin_expect(exp, c) with EXP.
5268 setValue(&I, getValue(I.getArgOperand(0)));
5272 case Intrinsic::debugtrap:
5273 case Intrinsic::trap: {
5274 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5275 if (TrapFuncName.empty()) {
5276 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5277 ISD::TRAP : ISD::DEBUGTRAP;
5278 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5281 TargetLowering::ArgListTy Args;
5283 CallLoweringInfo CLI(getRoot(), I.getType(),
5284 false, false, false, false, 0, CallingConv::C,
5285 /*isTailCall=*/false,
5286 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5287 DAG.getExternalSymbol(TrapFuncName.data(),
5288 TLI->getPointerTy()),
5290 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5291 DAG.setRoot(Result.second);
5295 case Intrinsic::uadd_with_overflow:
5296 case Intrinsic::sadd_with_overflow:
5297 case Intrinsic::usub_with_overflow:
5298 case Intrinsic::ssub_with_overflow:
5299 case Intrinsic::umul_with_overflow:
5300 case Intrinsic::smul_with_overflow: {
5302 switch (Intrinsic) {
5303 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5304 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5305 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5306 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5307 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5308 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5309 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5311 SDValue Op1 = getValue(I.getArgOperand(0));
5312 SDValue Op2 = getValue(I.getArgOperand(1));
5314 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5315 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5318 case Intrinsic::prefetch: {
5320 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5322 Ops[1] = getValue(I.getArgOperand(0));
5323 Ops[2] = getValue(I.getArgOperand(1));
5324 Ops[3] = getValue(I.getArgOperand(2));
5325 Ops[4] = getValue(I.getArgOperand(3));
5326 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5327 DAG.getVTList(MVT::Other),
5329 EVT::getIntegerVT(*Context, 8),
5330 MachinePointerInfo(I.getArgOperand(0)),
5332 false, /* volatile */
5334 rw==1)); /* write */
5337 case Intrinsic::lifetime_start:
5338 case Intrinsic::lifetime_end: {
5339 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5340 // Stack coloring is not enabled in O0, discard region information.
5341 if (TM.getOptLevel() == CodeGenOpt::None)
5344 SmallVector<Value *, 4> Allocas;
5345 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5347 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5348 E = Allocas.end(); Object != E; ++Object) {
5349 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5351 // Could not find an Alloca.
5352 if (!LifetimeObject)
5355 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5359 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5360 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5362 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5367 case Intrinsic::invariant_start:
5368 // Discard region information.
5369 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5371 case Intrinsic::invariant_end:
5372 // Discard region information.
5374 case Intrinsic::stackprotectorcheck: {
5375 // Do not actually emit anything for this basic block. Instead we initialize
5376 // the stack protector descriptor and export the guard variable so we can
5377 // access it in FinishBasicBlock.
5378 const BasicBlock *BB = I.getParent();
5379 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5380 ExportFromCurrentBlock(SPDescriptor.getGuard());
5382 // Flush our exports since we are going to process a terminator.
5383 (void)getControlRoot();
5386 case Intrinsic::clear_cache:
5387 return TLI->getClearCacheBuiltinName();
5388 case Intrinsic::donothing:
5391 case Intrinsic::experimental_stackmap: {
5395 case Intrinsic::experimental_patchpoint_void:
5396 case Intrinsic::experimental_patchpoint_i64: {
5403 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5405 MachineBasicBlock *LandingPad) {
5406 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5407 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5408 Type *RetTy = FTy->getReturnType();
5409 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5410 MCSymbol *BeginLabel = 0;
5412 TargetLowering::ArgListTy Args;
5413 TargetLowering::ArgListEntry Entry;
5414 Args.reserve(CS.arg_size());
5416 // Check whether the function can return without sret-demotion.
5417 SmallVector<ISD::OutputArg, 4> Outs;
5418 const TargetLowering *TLI = TM.getTargetLowering();
5419 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5421 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5422 DAG.getMachineFunction(),
5423 FTy->isVarArg(), Outs,
5426 SDValue DemoteStackSlot;
5427 int DemoteStackIdx = -100;
5429 if (!CanLowerReturn) {
5430 assert(!CS.hasInAllocaArgument() &&
5431 "sret demotion is incompatible with inalloca");
5432 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5433 FTy->getReturnType());
5434 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5435 FTy->getReturnType());
5436 MachineFunction &MF = DAG.getMachineFunction();
5437 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5438 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5440 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5441 Entry.Node = DemoteStackSlot;
5442 Entry.Ty = StackSlotPtrType;
5443 Entry.isSExt = false;
5444 Entry.isZExt = false;
5445 Entry.isInReg = false;
5446 Entry.isSRet = true;
5447 Entry.isNest = false;
5448 Entry.isByVal = false;
5449 Entry.isReturned = false;
5450 Entry.Alignment = Align;
5451 Args.push_back(Entry);
5452 RetTy = Type::getVoidTy(FTy->getContext());
5455 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5457 const Value *V = *i;
5460 if (V->getType()->isEmptyTy())
5463 SDValue ArgNode = getValue(V);
5464 Entry.Node = ArgNode; Entry.Ty = V->getType();
5466 // Skip the first return-type Attribute to get to params.
5467 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5468 Args.push_back(Entry);
5472 // Insert a label before the invoke call to mark the try range. This can be
5473 // used to detect deletion of the invoke via the MachineModuleInfo.
5474 BeginLabel = MMI.getContext().CreateTempSymbol();
5476 // For SjLj, keep track of which landing pads go with which invokes
5477 // so as to maintain the ordering of pads in the LSDA.
5478 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5479 if (CallSiteIndex) {
5480 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5481 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5483 // Now that the call site is handled, stop tracking it.
5484 MMI.setCurrentCallSite(0);
5487 // Both PendingLoads and PendingExports must be flushed here;
5488 // this call might not return.
5490 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5493 // Check if target-independent constraints permit a tail call here.
5494 // Target-dependent constraints are checked within TLI->LowerCallTo.
5495 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5499 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5501 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5502 assert((isTailCall || Result.second.getNode()) &&
5503 "Non-null chain expected with non-tail call!");
5504 assert((Result.second.getNode() || !Result.first.getNode()) &&
5505 "Null value expected with tail call!");
5506 if (Result.first.getNode()) {
5507 setValue(CS.getInstruction(), Result.first);
5508 } else if (!CanLowerReturn && Result.second.getNode()) {
5509 // The instruction result is the result of loading from the
5510 // hidden sret parameter.
5511 SmallVector<EVT, 1> PVTs;
5512 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5514 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5515 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5516 EVT PtrVT = PVTs[0];
5518 SmallVector<EVT, 4> RetTys;
5519 SmallVector<uint64_t, 4> Offsets;
5520 RetTy = FTy->getReturnType();
5521 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5523 unsigned NumValues = RetTys.size();
5524 SmallVector<SDValue, 4> Values(NumValues);
5525 SmallVector<SDValue, 4> Chains(NumValues);
5527 for (unsigned i = 0; i < NumValues; ++i) {
5528 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5530 DAG.getConstant(Offsets[i], PtrVT));
5531 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5532 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5533 false, false, false, 1);
5535 Chains[i] = L.getValue(1);
5538 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5539 MVT::Other, &Chains[0], NumValues);
5540 PendingLoads.push_back(Chain);
5542 setValue(CS.getInstruction(),
5543 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5544 DAG.getVTList(&RetTys[0], RetTys.size()),
5545 &Values[0], Values.size()));
5548 if (!Result.second.getNode()) {
5549 // As a special case, a null chain means that a tail call has been emitted
5550 // and the DAG root is already updated.
5553 // Since there's no actual continuation from this block, nothing can be
5554 // relying on us setting vregs for them.
5555 PendingExports.clear();
5557 DAG.setRoot(Result.second);
5561 // Insert a label at the end of the invoke call to mark the try range. This
5562 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5563 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5564 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5566 // Inform MachineModuleInfo of range.
5567 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5571 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5572 /// value is equal or not-equal to zero.
5573 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5574 for (const User *U : V->users()) {
5575 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5576 if (IC->isEquality())
5577 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5578 if (C->isNullValue())
5580 // Unknown instruction.
5586 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5588 SelectionDAGBuilder &Builder) {
5590 // Check to see if this load can be trivially constant folded, e.g. if the
5591 // input is from a string literal.
5592 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5593 // Cast pointer to the type we really want to load.
5594 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5595 PointerType::getUnqual(LoadTy));
5597 if (const Constant *LoadCst =
5598 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5600 return Builder.getValue(LoadCst);
5603 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5604 // still constant memory, the input chain can be the entry node.
5606 bool ConstantMemory = false;
5608 // Do not serialize (non-volatile) loads of constant memory with anything.
5609 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5610 Root = Builder.DAG.getEntryNode();
5611 ConstantMemory = true;
5613 // Do not serialize non-volatile loads against each other.
5614 Root = Builder.DAG.getRoot();
5617 SDValue Ptr = Builder.getValue(PtrVal);
5618 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5619 Ptr, MachinePointerInfo(PtrVal),
5621 false /*nontemporal*/,
5622 false /*isinvariant*/, 1 /* align=1 */);
5624 if (!ConstantMemory)
5625 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5629 /// processIntegerCallValue - Record the value for an instruction that
5630 /// produces an integer result, converting the type where necessary.
5631 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5634 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true);
5636 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5638 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5639 setValue(&I, Value);
5642 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5643 /// If so, return true and lower it, otherwise return false and it will be
5644 /// lowered like a normal call.
5645 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5646 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5647 if (I.getNumArgOperands() != 3)
5650 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5651 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5652 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5653 !I.getType()->isIntegerTy())
5656 const Value *Size = I.getArgOperand(2);
5657 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5658 if (CSize && CSize->getZExtValue() == 0) {
5659 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true);
5660 setValue(&I, DAG.getConstant(0, CallVT));
5664 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5665 std::pair<SDValue, SDValue> Res =
5666 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5667 getValue(LHS), getValue(RHS), getValue(Size),
5668 MachinePointerInfo(LHS),
5669 MachinePointerInfo(RHS));
5670 if (Res.first.getNode()) {
5671 processIntegerCallValue(I, Res.first, true);
5672 PendingLoads.push_back(Res.second);
5676 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5677 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5678 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5679 bool ActuallyDoIt = true;
5682 switch (CSize->getZExtValue()) {
5684 LoadVT = MVT::Other;
5686 ActuallyDoIt = false;
5690 LoadTy = Type::getInt16Ty(CSize->getContext());
5694 LoadTy = Type::getInt32Ty(CSize->getContext());
5698 LoadTy = Type::getInt64Ty(CSize->getContext());
5702 LoadVT = MVT::v4i32;
5703 LoadTy = Type::getInt32Ty(CSize->getContext());
5704 LoadTy = VectorType::get(LoadTy, 4);
5709 // This turns into unaligned loads. We only do this if the target natively
5710 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5711 // we'll only produce a small number of byte loads.
5713 // Require that we can find a legal MVT, and only do this if the target
5714 // supports unaligned loads of that type. Expanding into byte loads would
5716 const TargetLowering *TLI = TM.getTargetLowering();
5717 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5718 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5719 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5720 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5721 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5722 if (!TLI->isTypeLegal(LoadVT) ||
5723 !TLI->allowsUnalignedMemoryAccesses(LoadVT, SrcAS) ||
5724 !TLI->allowsUnalignedMemoryAccesses(LoadVT, DstAS))
5725 ActuallyDoIt = false;
5729 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5730 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5732 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5734 processIntegerCallValue(I, Res, false);
5743 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5744 /// form. If so, return true and lower it, otherwise return false and it
5745 /// will be lowered like a normal call.
5746 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5747 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5748 if (I.getNumArgOperands() != 3)
5751 const Value *Src = I.getArgOperand(0);
5752 const Value *Char = I.getArgOperand(1);
5753 const Value *Length = I.getArgOperand(2);
5754 if (!Src->getType()->isPointerTy() ||
5755 !Char->getType()->isIntegerTy() ||
5756 !Length->getType()->isIntegerTy() ||
5757 !I.getType()->isPointerTy())
5760 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5761 std::pair<SDValue, SDValue> Res =
5762 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5763 getValue(Src), getValue(Char), getValue(Length),
5764 MachinePointerInfo(Src));
5765 if (Res.first.getNode()) {
5766 setValue(&I, Res.first);
5767 PendingLoads.push_back(Res.second);
5774 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5775 /// optimized form. If so, return true and lower it, otherwise return false
5776 /// and it will be lowered like a normal call.
5777 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5778 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5779 if (I.getNumArgOperands() != 2)
5782 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5783 if (!Arg0->getType()->isPointerTy() ||
5784 !Arg1->getType()->isPointerTy() ||
5785 !I.getType()->isPointerTy())
5788 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5789 std::pair<SDValue, SDValue> Res =
5790 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5791 getValue(Arg0), getValue(Arg1),
5792 MachinePointerInfo(Arg0),
5793 MachinePointerInfo(Arg1), isStpcpy);
5794 if (Res.first.getNode()) {
5795 setValue(&I, Res.first);
5796 DAG.setRoot(Res.second);
5803 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5804 /// If so, return true and lower it, otherwise return false and it will be
5805 /// lowered like a normal call.
5806 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5807 // Verify that the prototype makes sense. int strcmp(void*,void*)
5808 if (I.getNumArgOperands() != 2)
5811 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5812 if (!Arg0->getType()->isPointerTy() ||
5813 !Arg1->getType()->isPointerTy() ||
5814 !I.getType()->isIntegerTy())
5817 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5818 std::pair<SDValue, SDValue> Res =
5819 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5820 getValue(Arg0), getValue(Arg1),
5821 MachinePointerInfo(Arg0),
5822 MachinePointerInfo(Arg1));
5823 if (Res.first.getNode()) {
5824 processIntegerCallValue(I, Res.first, true);
5825 PendingLoads.push_back(Res.second);
5832 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5833 /// form. If so, return true and lower it, otherwise return false and it
5834 /// will be lowered like a normal call.
5835 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5836 // Verify that the prototype makes sense. size_t strlen(char *)
5837 if (I.getNumArgOperands() != 1)
5840 const Value *Arg0 = I.getArgOperand(0);
5841 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5844 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5845 std::pair<SDValue, SDValue> Res =
5846 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5847 getValue(Arg0), MachinePointerInfo(Arg0));
5848 if (Res.first.getNode()) {
5849 processIntegerCallValue(I, Res.first, false);
5850 PendingLoads.push_back(Res.second);
5857 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5858 /// form. If so, return true and lower it, otherwise return false and it
5859 /// will be lowered like a normal call.
5860 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5861 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5862 if (I.getNumArgOperands() != 2)
5865 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5866 if (!Arg0->getType()->isPointerTy() ||
5867 !Arg1->getType()->isIntegerTy() ||
5868 !I.getType()->isIntegerTy())
5871 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5872 std::pair<SDValue, SDValue> Res =
5873 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5874 getValue(Arg0), getValue(Arg1),
5875 MachinePointerInfo(Arg0));
5876 if (Res.first.getNode()) {
5877 processIntegerCallValue(I, Res.first, false);
5878 PendingLoads.push_back(Res.second);
5885 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5886 /// operation (as expected), translate it to an SDNode with the specified opcode
5887 /// and return true.
5888 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5890 // Sanity check that it really is a unary floating-point call.
5891 if (I.getNumArgOperands() != 1 ||
5892 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5893 I.getType() != I.getArgOperand(0)->getType() ||
5894 !I.onlyReadsMemory())
5897 SDValue Tmp = getValue(I.getArgOperand(0));
5898 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5902 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5903 // Handle inline assembly differently.
5904 if (isa<InlineAsm>(I.getCalledValue())) {
5909 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5910 ComputeUsesVAFloatArgument(I, &MMI);
5912 const char *RenameFn = 0;
5913 if (Function *F = I.getCalledFunction()) {
5914 if (F->isDeclaration()) {
5915 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5916 if (unsigned IID = II->getIntrinsicID(F)) {
5917 RenameFn = visitIntrinsicCall(I, IID);
5922 if (unsigned IID = F->getIntrinsicID()) {
5923 RenameFn = visitIntrinsicCall(I, IID);
5929 // Check for well-known libc/libm calls. If the function is internal, it
5930 // can't be a library call.
5932 if (!F->hasLocalLinkage() && F->hasName() &&
5933 LibInfo->getLibFunc(F->getName(), Func) &&
5934 LibInfo->hasOptimizedCodeGen(Func)) {
5937 case LibFunc::copysign:
5938 case LibFunc::copysignf:
5939 case LibFunc::copysignl:
5940 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5941 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5942 I.getType() == I.getArgOperand(0)->getType() &&
5943 I.getType() == I.getArgOperand(1)->getType() &&
5944 I.onlyReadsMemory()) {
5945 SDValue LHS = getValue(I.getArgOperand(0));
5946 SDValue RHS = getValue(I.getArgOperand(1));
5947 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5948 LHS.getValueType(), LHS, RHS));
5953 case LibFunc::fabsf:
5954 case LibFunc::fabsl:
5955 if (visitUnaryFloatCall(I, ISD::FABS))
5961 if (visitUnaryFloatCall(I, ISD::FSIN))
5967 if (visitUnaryFloatCall(I, ISD::FCOS))
5971 case LibFunc::sqrtf:
5972 case LibFunc::sqrtl:
5973 case LibFunc::sqrt_finite:
5974 case LibFunc::sqrtf_finite:
5975 case LibFunc::sqrtl_finite:
5976 if (visitUnaryFloatCall(I, ISD::FSQRT))
5979 case LibFunc::floor:
5980 case LibFunc::floorf:
5981 case LibFunc::floorl:
5982 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5985 case LibFunc::nearbyint:
5986 case LibFunc::nearbyintf:
5987 case LibFunc::nearbyintl:
5988 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5992 case LibFunc::ceilf:
5993 case LibFunc::ceill:
5994 if (visitUnaryFloatCall(I, ISD::FCEIL))
5998 case LibFunc::rintf:
5999 case LibFunc::rintl:
6000 if (visitUnaryFloatCall(I, ISD::FRINT))
6003 case LibFunc::round:
6004 case LibFunc::roundf:
6005 case LibFunc::roundl:
6006 if (visitUnaryFloatCall(I, ISD::FROUND))
6009 case LibFunc::trunc:
6010 case LibFunc::truncf:
6011 case LibFunc::truncl:
6012 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6016 case LibFunc::log2f:
6017 case LibFunc::log2l:
6018 if (visitUnaryFloatCall(I, ISD::FLOG2))
6022 case LibFunc::exp2f:
6023 case LibFunc::exp2l:
6024 if (visitUnaryFloatCall(I, ISD::FEXP2))
6027 case LibFunc::memcmp:
6028 if (visitMemCmpCall(I))
6031 case LibFunc::memchr:
6032 if (visitMemChrCall(I))
6035 case LibFunc::strcpy:
6036 if (visitStrCpyCall(I, false))
6039 case LibFunc::stpcpy:
6040 if (visitStrCpyCall(I, true))
6043 case LibFunc::strcmp:
6044 if (visitStrCmpCall(I))
6047 case LibFunc::strlen:
6048 if (visitStrLenCall(I))
6051 case LibFunc::strnlen:
6052 if (visitStrNLenCall(I))
6061 Callee = getValue(I.getCalledValue());
6063 Callee = DAG.getExternalSymbol(RenameFn,
6064 TM.getTargetLowering()->getPointerTy());
6066 // Check if we can potentially perform a tail call. More detailed checking is
6067 // be done within LowerCallTo, after more information about the call is known.
6068 LowerCallTo(&I, Callee, I.isTailCall());
6073 /// AsmOperandInfo - This contains information for each constraint that we are
6075 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6077 /// CallOperand - If this is the result output operand or a clobber
6078 /// this is null, otherwise it is the incoming operand to the CallInst.
6079 /// This gets modified as the asm is processed.
6080 SDValue CallOperand;
6082 /// AssignedRegs - If this is a register or register class operand, this
6083 /// contains the set of register corresponding to the operand.
6084 RegsForValue AssignedRegs;
6086 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6087 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
6090 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6091 /// corresponds to. If there is no Value* for this operand, it returns
6093 EVT getCallOperandValEVT(LLVMContext &Context,
6094 const TargetLowering &TLI,
6095 const DataLayout *DL) const {
6096 if (CallOperandVal == 0) return MVT::Other;
6098 if (isa<BasicBlock>(CallOperandVal))
6099 return TLI.getPointerTy();
6101 llvm::Type *OpTy = CallOperandVal->getType();
6103 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6104 // If this is an indirect operand, the operand is a pointer to the
6107 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6109 report_fatal_error("Indirect operand for inline asm not a pointer!");
6110 OpTy = PtrTy->getElementType();
6113 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6114 if (StructType *STy = dyn_cast<StructType>(OpTy))
6115 if (STy->getNumElements() == 1)
6116 OpTy = STy->getElementType(0);
6118 // If OpTy is not a single value, it may be a struct/union that we
6119 // can tile with integers.
6120 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6121 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6130 OpTy = IntegerType::get(Context, BitSize);
6135 return TLI.getValueType(OpTy, true);
6139 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6141 } // end anonymous namespace
6143 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6144 /// specified operand. We prefer to assign virtual registers, to allow the
6145 /// register allocator to handle the assignment process. However, if the asm
6146 /// uses features that we can't model on machineinstrs, we have SDISel do the
6147 /// allocation. This produces generally horrible, but correct, code.
6149 /// OpInfo describes the operand.
6151 static void GetRegistersForValue(SelectionDAG &DAG,
6152 const TargetLowering &TLI,
6154 SDISelAsmOperandInfo &OpInfo) {
6155 LLVMContext &Context = *DAG.getContext();
6157 MachineFunction &MF = DAG.getMachineFunction();
6158 SmallVector<unsigned, 4> Regs;
6160 // If this is a constraint for a single physreg, or a constraint for a
6161 // register class, find it.
6162 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6163 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6164 OpInfo.ConstraintVT);
6166 unsigned NumRegs = 1;
6167 if (OpInfo.ConstraintVT != MVT::Other) {
6168 // If this is a FP input in an integer register (or visa versa) insert a bit
6169 // cast of the input value. More generally, handle any case where the input
6170 // value disagrees with the register class we plan to stick this in.
6171 if (OpInfo.Type == InlineAsm::isInput &&
6172 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6173 // Try to convert to the first EVT that the reg class contains. If the
6174 // types are identical size, use a bitcast to convert (e.g. two differing
6176 MVT RegVT = *PhysReg.second->vt_begin();
6177 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6178 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6179 RegVT, OpInfo.CallOperand);
6180 OpInfo.ConstraintVT = RegVT;
6181 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6182 // If the input is a FP value and we want it in FP registers, do a
6183 // bitcast to the corresponding integer type. This turns an f64 value
6184 // into i64, which can be passed with two i32 values on a 32-bit
6186 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6187 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6188 RegVT, OpInfo.CallOperand);
6189 OpInfo.ConstraintVT = RegVT;
6193 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6197 EVT ValueVT = OpInfo.ConstraintVT;
6199 // If this is a constraint for a specific physical register, like {r17},
6201 if (unsigned AssignedReg = PhysReg.first) {
6202 const TargetRegisterClass *RC = PhysReg.second;
6203 if (OpInfo.ConstraintVT == MVT::Other)
6204 ValueVT = *RC->vt_begin();
6206 // Get the actual register value type. This is important, because the user
6207 // may have asked for (e.g.) the AX register in i32 type. We need to
6208 // remember that AX is actually i16 to get the right extension.
6209 RegVT = *RC->vt_begin();
6211 // This is a explicit reference to a physical register.
6212 Regs.push_back(AssignedReg);
6214 // If this is an expanded reference, add the rest of the regs to Regs.
6216 TargetRegisterClass::iterator I = RC->begin();
6217 for (; *I != AssignedReg; ++I)
6218 assert(I != RC->end() && "Didn't find reg!");
6220 // Already added the first reg.
6222 for (; NumRegs; --NumRegs, ++I) {
6223 assert(I != RC->end() && "Ran out of registers to allocate!");
6228 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6232 // Otherwise, if this was a reference to an LLVM register class, create vregs
6233 // for this reference.
6234 if (const TargetRegisterClass *RC = PhysReg.second) {
6235 RegVT = *RC->vt_begin();
6236 if (OpInfo.ConstraintVT == MVT::Other)
6239 // Create the appropriate number of virtual registers.
6240 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6241 for (; NumRegs; --NumRegs)
6242 Regs.push_back(RegInfo.createVirtualRegister(RC));
6244 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6248 // Otherwise, we couldn't allocate enough registers for this.
6251 /// visitInlineAsm - Handle a call to an InlineAsm object.
6253 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6254 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6256 /// ConstraintOperands - Information about all of the constraints.
6257 SDISelAsmOperandInfoVector ConstraintOperands;
6259 const TargetLowering *TLI = TM.getTargetLowering();
6260 TargetLowering::AsmOperandInfoVector
6261 TargetConstraints = TLI->ParseConstraints(CS);
6263 bool hasMemory = false;
6265 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6266 unsigned ResNo = 0; // ResNo - The result number of the next output.
6267 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6268 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6269 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6271 MVT OpVT = MVT::Other;
6273 // Compute the value type for each operand.
6274 switch (OpInfo.Type) {
6275 case InlineAsm::isOutput:
6276 // Indirect outputs just consume an argument.
6277 if (OpInfo.isIndirect) {
6278 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6282 // The return value of the call is this value. As such, there is no
6283 // corresponding argument.
6284 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6285 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6286 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6288 assert(ResNo == 0 && "Asm only has one result!");
6289 OpVT = TLI->getSimpleValueType(CS.getType());
6293 case InlineAsm::isInput:
6294 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6296 case InlineAsm::isClobber:
6301 // If this is an input or an indirect output, process the call argument.
6302 // BasicBlocks are labels, currently appearing only in asm's.
6303 if (OpInfo.CallOperandVal) {
6304 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6305 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6307 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6310 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6314 OpInfo.ConstraintVT = OpVT;
6316 // Indirect operand accesses access memory.
6317 if (OpInfo.isIndirect)
6320 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6321 TargetLowering::ConstraintType
6322 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6323 if (CType == TargetLowering::C_Memory) {
6331 SDValue Chain, Flag;
6333 // We won't need to flush pending loads if this asm doesn't touch
6334 // memory and is nonvolatile.
6335 if (hasMemory || IA->hasSideEffects())
6338 Chain = DAG.getRoot();
6340 // Second pass over the constraints: compute which constraint option to use
6341 // and assign registers to constraints that want a specific physreg.
6342 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6343 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6345 // If this is an output operand with a matching input operand, look up the
6346 // matching input. If their types mismatch, e.g. one is an integer, the
6347 // other is floating point, or their sizes are different, flag it as an
6349 if (OpInfo.hasMatchingInput()) {
6350 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6352 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6353 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6354 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6355 OpInfo.ConstraintVT);
6356 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6357 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6358 Input.ConstraintVT);
6359 if ((OpInfo.ConstraintVT.isInteger() !=
6360 Input.ConstraintVT.isInteger()) ||
6361 (MatchRC.second != InputRC.second)) {
6362 report_fatal_error("Unsupported asm: input constraint"
6363 " with a matching output constraint of"
6364 " incompatible type!");
6366 Input.ConstraintVT = OpInfo.ConstraintVT;
6370 // Compute the constraint code and ConstraintType to use.
6371 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6373 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6374 OpInfo.Type == InlineAsm::isClobber)
6377 // If this is a memory input, and if the operand is not indirect, do what we
6378 // need to to provide an address for the memory input.
6379 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6380 !OpInfo.isIndirect) {
6381 assert((OpInfo.isMultipleAlternative ||
6382 (OpInfo.Type == InlineAsm::isInput)) &&
6383 "Can only indirectify direct input operands!");
6385 // Memory operands really want the address of the value. If we don't have
6386 // an indirect input, put it in the constpool if we can, otherwise spill
6387 // it to a stack slot.
6388 // TODO: This isn't quite right. We need to handle these according to
6389 // the addressing mode that the constraint wants. Also, this may take
6390 // an additional register for the computation and we don't want that
6393 // If the operand is a float, integer, or vector constant, spill to a
6394 // constant pool entry to get its address.
6395 const Value *OpVal = OpInfo.CallOperandVal;
6396 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6397 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6398 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6399 TLI->getPointerTy());
6401 // Otherwise, create a stack slot and emit a store to it before the
6403 Type *Ty = OpVal->getType();
6404 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6405 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6406 MachineFunction &MF = DAG.getMachineFunction();
6407 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6408 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6409 Chain = DAG.getStore(Chain, getCurSDLoc(),
6410 OpInfo.CallOperand, StackSlot,
6411 MachinePointerInfo::getFixedStack(SSFI),
6413 OpInfo.CallOperand = StackSlot;
6416 // There is no longer a Value* corresponding to this operand.
6417 OpInfo.CallOperandVal = 0;
6419 // It is now an indirect operand.
6420 OpInfo.isIndirect = true;
6423 // If this constraint is for a specific register, allocate it before
6425 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6426 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6429 // Second pass - Loop over all of the operands, assigning virtual or physregs
6430 // to register class operands.
6431 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6432 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6434 // C_Register operands have already been allocated, Other/Memory don't need
6436 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6437 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6440 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6441 std::vector<SDValue> AsmNodeOperands;
6442 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6443 AsmNodeOperands.push_back(
6444 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6445 TLI->getPointerTy()));
6447 // If we have a !srcloc metadata node associated with it, we want to attach
6448 // this to the ultimately generated inline asm machineinstr. To do this, we
6449 // pass in the third operand as this (potentially null) inline asm MDNode.
6450 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6451 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6453 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6454 // bits as operand 3.
6455 unsigned ExtraInfo = 0;
6456 if (IA->hasSideEffects())
6457 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6458 if (IA->isAlignStack())
6459 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6460 // Set the asm dialect.
6461 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6463 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6464 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6465 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6467 // Compute the constraint code and ConstraintType to use.
6468 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6470 // Ideally, we would only check against memory constraints. However, the
6471 // meaning of an other constraint can be target-specific and we can't easily
6472 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6473 // for other constriants as well.
6474 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6475 OpInfo.ConstraintType == TargetLowering::C_Other) {
6476 if (OpInfo.Type == InlineAsm::isInput)
6477 ExtraInfo |= InlineAsm::Extra_MayLoad;
6478 else if (OpInfo.Type == InlineAsm::isOutput)
6479 ExtraInfo |= InlineAsm::Extra_MayStore;
6480 else if (OpInfo.Type == InlineAsm::isClobber)
6481 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6485 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6486 TLI->getPointerTy()));
6488 // Loop over all of the inputs, copying the operand values into the
6489 // appropriate registers and processing the output regs.
6490 RegsForValue RetValRegs;
6492 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6493 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6495 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6496 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6498 switch (OpInfo.Type) {
6499 case InlineAsm::isOutput: {
6500 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6501 OpInfo.ConstraintType != TargetLowering::C_Register) {
6502 // Memory output, or 'other' output (e.g. 'X' constraint).
6503 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6505 // Add information to the INLINEASM node to know about this output.
6506 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6507 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6508 TLI->getPointerTy()));
6509 AsmNodeOperands.push_back(OpInfo.CallOperand);
6513 // Otherwise, this is a register or register class output.
6515 // Copy the output from the appropriate register. Find a register that
6517 if (OpInfo.AssignedRegs.Regs.empty()) {
6518 LLVMContext &Ctx = *DAG.getContext();
6519 Ctx.emitError(CS.getInstruction(),
6520 "couldn't allocate output register for constraint '" +
6521 Twine(OpInfo.ConstraintCode) + "'");
6525 // If this is an indirect operand, store through the pointer after the
6527 if (OpInfo.isIndirect) {
6528 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6529 OpInfo.CallOperandVal));
6531 // This is the result value of the call.
6532 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6533 // Concatenate this output onto the outputs list.
6534 RetValRegs.append(OpInfo.AssignedRegs);
6537 // Add information to the INLINEASM node to know that this register is
6540 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6541 ? InlineAsm::Kind_RegDefEarlyClobber
6542 : InlineAsm::Kind_RegDef,
6543 false, 0, DAG, AsmNodeOperands);
6546 case InlineAsm::isInput: {
6547 SDValue InOperandVal = OpInfo.CallOperand;
6549 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6550 // If this is required to match an output register we have already set,
6551 // just use its register.
6552 unsigned OperandNo = OpInfo.getMatchedOperand();
6554 // Scan until we find the definition we already emitted of this operand.
6555 // When we find it, create a RegsForValue operand.
6556 unsigned CurOp = InlineAsm::Op_FirstOperand;
6557 for (; OperandNo; --OperandNo) {
6558 // Advance to the next operand.
6560 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6561 assert((InlineAsm::isRegDefKind(OpFlag) ||
6562 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6563 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6564 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6568 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6569 if (InlineAsm::isRegDefKind(OpFlag) ||
6570 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6571 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6572 if (OpInfo.isIndirect) {
6573 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6574 LLVMContext &Ctx = *DAG.getContext();
6575 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6576 " don't know how to handle tied "
6577 "indirect register inputs");
6581 RegsForValue MatchedRegs;
6582 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6583 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6584 MatchedRegs.RegVTs.push_back(RegVT);
6585 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6586 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6588 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6589 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6591 LLVMContext &Ctx = *DAG.getContext();
6592 Ctx.emitError(CS.getInstruction(),
6593 "inline asm error: This value"
6594 " type register class is not natively supported!");
6598 // Use the produced MatchedRegs object to
6599 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6600 Chain, &Flag, CS.getInstruction());
6601 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6602 true, OpInfo.getMatchedOperand(),
6603 DAG, AsmNodeOperands);
6607 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6608 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6609 "Unexpected number of operands");
6610 // Add information to the INLINEASM node to know about this input.
6611 // See InlineAsm.h isUseOperandTiedToDef.
6612 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6613 OpInfo.getMatchedOperand());
6614 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6615 TLI->getPointerTy()));
6616 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6620 // Treat indirect 'X' constraint as memory.
6621 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6623 OpInfo.ConstraintType = TargetLowering::C_Memory;
6625 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6626 std::vector<SDValue> Ops;
6627 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6630 LLVMContext &Ctx = *DAG.getContext();
6631 Ctx.emitError(CS.getInstruction(),
6632 "invalid operand for inline asm constraint '" +
6633 Twine(OpInfo.ConstraintCode) + "'");
6637 // Add information to the INLINEASM node to know about this input.
6638 unsigned ResOpType =
6639 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6640 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6641 TLI->getPointerTy()));
6642 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6646 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6647 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6648 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6649 "Memory operands expect pointer values");
6651 // Add information to the INLINEASM node to know about this input.
6652 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6653 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6654 TLI->getPointerTy()));
6655 AsmNodeOperands.push_back(InOperandVal);
6659 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6660 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6661 "Unknown constraint type!");
6663 // TODO: Support this.
6664 if (OpInfo.isIndirect) {
6665 LLVMContext &Ctx = *DAG.getContext();
6666 Ctx.emitError(CS.getInstruction(),
6667 "Don't know how to handle indirect register inputs yet "
6668 "for constraint '" +
6669 Twine(OpInfo.ConstraintCode) + "'");
6673 // Copy the input into the appropriate registers.
6674 if (OpInfo.AssignedRegs.Regs.empty()) {
6675 LLVMContext &Ctx = *DAG.getContext();
6676 Ctx.emitError(CS.getInstruction(),
6677 "couldn't allocate input reg for constraint '" +
6678 Twine(OpInfo.ConstraintCode) + "'");
6682 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6683 Chain, &Flag, CS.getInstruction());
6685 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6686 DAG, AsmNodeOperands);
6689 case InlineAsm::isClobber: {
6690 // Add the clobbered value to the operand list, so that the register
6691 // allocator is aware that the physreg got clobbered.
6692 if (!OpInfo.AssignedRegs.Regs.empty())
6693 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6701 // Finish up input operands. Set the input chain and add the flag last.
6702 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6703 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6705 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6706 DAG.getVTList(MVT::Other, MVT::Glue),
6707 &AsmNodeOperands[0], AsmNodeOperands.size());
6708 Flag = Chain.getValue(1);
6710 // If this asm returns a register value, copy the result from that register
6711 // and set it as the value of the call.
6712 if (!RetValRegs.Regs.empty()) {
6713 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6714 Chain, &Flag, CS.getInstruction());
6716 // FIXME: Why don't we do this for inline asms with MRVs?
6717 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6718 EVT ResultType = TLI->getValueType(CS.getType());
6720 // If any of the results of the inline asm is a vector, it may have the
6721 // wrong width/num elts. This can happen for register classes that can
6722 // contain multiple different value types. The preg or vreg allocated may
6723 // not have the same VT as was expected. Convert it to the right type
6724 // with bit_convert.
6725 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6726 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6729 } else if (ResultType != Val.getValueType() &&
6730 ResultType.isInteger() && Val.getValueType().isInteger()) {
6731 // If a result value was tied to an input value, the computed result may
6732 // have a wider width than the expected result. Extract the relevant
6734 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6737 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6740 setValue(CS.getInstruction(), Val);
6741 // Don't need to use this as a chain in this case.
6742 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6746 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6748 // Process indirect outputs, first output all of the flagged copies out of
6750 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6751 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6752 const Value *Ptr = IndirectStoresToEmit[i].second;
6753 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6755 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6758 // Emit the non-flagged stores from the physregs.
6759 SmallVector<SDValue, 8> OutChains;
6760 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6761 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6762 StoresToEmit[i].first,
6763 getValue(StoresToEmit[i].second),
6764 MachinePointerInfo(StoresToEmit[i].second),
6766 OutChains.push_back(Val);
6769 if (!OutChains.empty())
6770 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6771 &OutChains[0], OutChains.size());
6776 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6777 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6778 MVT::Other, getRoot(),
6779 getValue(I.getArgOperand(0)),
6780 DAG.getSrcValue(I.getArgOperand(0))));
6783 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6784 const TargetLowering *TLI = TM.getTargetLowering();
6785 const DataLayout &DL = *TLI->getDataLayout();
6786 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6787 getRoot(), getValue(I.getOperand(0)),
6788 DAG.getSrcValue(I.getOperand(0)),
6789 DL.getABITypeAlignment(I.getType()));
6791 DAG.setRoot(V.getValue(1));
6794 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6795 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6796 MVT::Other, getRoot(),
6797 getValue(I.getArgOperand(0)),
6798 DAG.getSrcValue(I.getArgOperand(0))));
6801 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6802 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6803 MVT::Other, getRoot(),
6804 getValue(I.getArgOperand(0)),
6805 getValue(I.getArgOperand(1)),
6806 DAG.getSrcValue(I.getArgOperand(0)),
6807 DAG.getSrcValue(I.getArgOperand(1))));
6810 /// \brief Lower an argument list according to the target calling convention.
6812 /// \return A tuple of <return-value, token-chain>
6814 /// This is a helper for lowering intrinsics that follow a target calling
6815 /// convention or require stack pointer adjustment. Only a subset of the
6816 /// intrinsic's operands need to participate in the calling convention.
6817 std::pair<SDValue, SDValue>
6818 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6819 unsigned NumArgs, SDValue Callee,
6821 TargetLowering::ArgListTy Args;
6822 Args.reserve(NumArgs);
6824 // Populate the argument list.
6825 // Attributes for args start at offset 1, after the return attribute.
6826 ImmutableCallSite CS(&CI);
6827 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6828 ArgI != ArgE; ++ArgI) {
6829 const Value *V = CI.getOperand(ArgI);
6831 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6833 TargetLowering::ArgListEntry Entry;
6834 Entry.Node = getValue(V);
6835 Entry.Ty = V->getType();
6836 Entry.setAttributes(&CS, AttrI);
6837 Args.push_back(Entry);
6840 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6841 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false,
6842 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs,
6843 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false,
6844 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc());
6846 const TargetLowering *TLI = TM.getTargetLowering();
6847 return TLI->LowerCallTo(CLI);
6850 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6851 /// or patchpoint target node's operand list.
6853 /// Constants are converted to TargetConstants purely as an optimization to
6854 /// avoid constant materialization and register allocation.
6856 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6857 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6858 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6859 /// address materialization and register allocation, but may also be required
6860 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6861 /// alloca in the entry block, then the runtime may assume that the alloca's
6862 /// StackMap location can be read immediately after compilation and that the
6863 /// location is valid at any point during execution (this is similar to the
6864 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6865 /// only available in a register, then the runtime would need to trap when
6866 /// execution reaches the StackMap in order to read the alloca's location.
6867 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6868 SmallVectorImpl<SDValue> &Ops,
6869 SelectionDAGBuilder &Builder) {
6870 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6871 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6872 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6874 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6876 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6877 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6878 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6880 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6882 Ops.push_back(OpVal);
6886 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6887 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6888 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6889 // [live variables...])
6891 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6893 SDValue Chain, InFlag, Callee, NullPtr;
6894 SmallVector<SDValue, 32> Ops;
6896 SDLoc DL = getCurSDLoc();
6897 Callee = getValue(CI.getCalledValue());
6898 NullPtr = DAG.getIntPtrConstant(0, true);
6900 // The stackmap intrinsic only records the live variables (the arguemnts
6901 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6902 // intrinsic, this won't be lowered to a function call. This means we don't
6903 // have to worry about calling conventions and target specific lowering code.
6904 // Instead we perform the call lowering right here.
6906 // chain, flag = CALLSEQ_START(chain, 0)
6907 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6908 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6910 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6911 InFlag = Chain.getValue(1);
6913 // Add the <id> and <numBytes> constants.
6914 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6915 Ops.push_back(DAG.getTargetConstant(
6916 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6917 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6918 Ops.push_back(DAG.getTargetConstant(
6919 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6921 // Push live variables for the stack map.
6922 addStackMapLiveVars(CI, 2, Ops, *this);
6924 // We are not pushing any register mask info here on the operands list,
6925 // because the stackmap doesn't clobber anything.
6927 // Push the chain and the glue flag.
6928 Ops.push_back(Chain);
6929 Ops.push_back(InFlag);
6931 // Create the STACKMAP node.
6932 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6933 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6934 Chain = SDValue(SM, 0);
6935 InFlag = Chain.getValue(1);
6937 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6939 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6941 // Set the root to the target-lowered call chain.
6944 // Inform the Frame Information that we have a stackmap in this function.
6945 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6948 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6949 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6950 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6955 // [live variables...])
6957 CallingConv::ID CC = CI.getCallingConv();
6958 bool isAnyRegCC = CC == CallingConv::AnyReg;
6959 bool hasDef = !CI.getType()->isVoidTy();
6960 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6962 // Get the real number of arguments participating in the call <numArgs>
6963 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6964 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6966 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6967 // Intrinsics include all meta-operands up to but not including CC.
6968 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6969 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6970 "Not enough arguments provided to the patchpoint intrinsic");
6972 // For AnyRegCC the arguments are lowered later on manually.
6973 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6974 std::pair<SDValue, SDValue> Result =
6975 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6977 // Set the root to the target-lowered call chain.
6978 SDValue Chain = Result.second;
6981 SDNode *CallEnd = Chain.getNode();
6982 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6983 CallEnd = CallEnd->getOperand(0).getNode();
6985 /// Get a call instruction from the call sequence chain.
6986 /// Tail calls are not allowed.
6987 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6988 "Expected a callseq node.");
6989 SDNode *Call = CallEnd->getOperand(0).getNode();
6990 bool hasGlue = Call->getGluedNode();
6992 // Replace the target specific call node with the patchable intrinsic.
6993 SmallVector<SDValue, 8> Ops;
6995 // Add the <id> and <numBytes> constants.
6996 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6997 Ops.push_back(DAG.getTargetConstant(
6998 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6999 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7000 Ops.push_back(DAG.getTargetConstant(
7001 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7003 // Assume that the Callee is a constant address.
7004 // FIXME: handle function symbols in the future.
7006 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7007 /*isTarget=*/true));
7009 // Adjust <numArgs> to account for any arguments that have been passed on the
7011 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7012 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7013 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7014 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7016 // Add the calling convention
7017 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7019 // Add the arguments we omitted previously. The register allocator should
7020 // place these in any free register.
7022 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7023 Ops.push_back(getValue(CI.getArgOperand(i)));
7025 // Push the arguments from the call instruction up to the register mask.
7026 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7027 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7030 // Push live variables for the stack map.
7031 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7033 // Push the register mask info.
7035 Ops.push_back(*(Call->op_end()-2));
7037 Ops.push_back(*(Call->op_end()-1));
7039 // Push the chain (this is originally the first operand of the call, but
7040 // becomes now the last or second to last operand).
7041 Ops.push_back(*(Call->op_begin()));
7043 // Push the glue flag (last operand).
7045 Ops.push_back(*(Call->op_end()-1));
7048 if (isAnyRegCC && hasDef) {
7049 // Create the return types based on the intrinsic definition
7050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7051 SmallVector<EVT, 3> ValueVTs;
7052 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7053 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7055 // There is always a chain and a glue type at the end
7056 ValueVTs.push_back(MVT::Other);
7057 ValueVTs.push_back(MVT::Glue);
7058 NodeTys = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
7060 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7062 // Replace the target specific call node with a PATCHPOINT node.
7063 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7064 getCurSDLoc(), NodeTys, Ops);
7066 // Update the NodeMap.
7069 setValue(&CI, SDValue(MN, 0));
7071 setValue(&CI, Result.first);
7074 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7075 // call sequence. Furthermore the location of the chain and glue can change
7076 // when the AnyReg calling convention is used and the intrinsic returns a
7078 if (isAnyRegCC && hasDef) {
7079 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7080 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7081 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7083 DAG.ReplaceAllUsesWith(Call, MN);
7084 DAG.DeleteNode(Call);
7086 // Inform the Frame Information that we have a patchpoint in this function.
7087 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7090 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7091 /// implementation, which just calls LowerCall.
7092 /// FIXME: When all targets are
7093 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7094 std::pair<SDValue, SDValue>
7095 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7096 // Handle the incoming return values from the call.
7098 SmallVector<EVT, 4> RetTys;
7099 ComputeValueVTs(*this, CLI.RetTy, RetTys);
7100 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7102 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7103 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7104 for (unsigned i = 0; i != NumRegs; ++i) {
7105 ISD::InputArg MyFlags;
7106 MyFlags.VT = RegisterVT;
7108 MyFlags.Used = CLI.IsReturnValueUsed;
7110 MyFlags.Flags.setSExt();
7112 MyFlags.Flags.setZExt();
7114 MyFlags.Flags.setInReg();
7115 CLI.Ins.push_back(MyFlags);
7119 // Handle all of the outgoing arguments.
7121 CLI.OutVals.clear();
7122 ArgListTy &Args = CLI.Args;
7123 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7124 SmallVector<EVT, 4> ValueVTs;
7125 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7126 for (unsigned Value = 0, NumValues = ValueVTs.size();
7127 Value != NumValues; ++Value) {
7128 EVT VT = ValueVTs[Value];
7129 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7130 SDValue Op = SDValue(Args[i].Node.getNode(),
7131 Args[i].Node.getResNo() + Value);
7132 ISD::ArgFlagsTy Flags;
7133 unsigned OriginalAlignment =
7134 getDataLayout()->getABITypeAlignment(ArgTy);
7140 if (Args[i].isInReg)
7144 if (Args[i].isByVal)
7146 if (Args[i].isInAlloca) {
7147 Flags.setInAlloca();
7148 // Set the byval flag for CCAssignFn callbacks that don't know about
7149 // inalloca. This way we can know how many bytes we should've allocated
7150 // and how many bytes a callee cleanup function will pop. If we port
7151 // inalloca to more targets, we'll have to add custom inalloca handling
7152 // in the various CC lowering callbacks.
7155 if (Args[i].isByVal || Args[i].isInAlloca) {
7156 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7157 Type *ElementTy = Ty->getElementType();
7158 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7159 // For ByVal, alignment should come from FE. BE will guess if this
7160 // info is not there but there are cases it cannot get right.
7161 unsigned FrameAlign;
7162 if (Args[i].Alignment)
7163 FrameAlign = Args[i].Alignment;
7165 FrameAlign = getByValTypeAlignment(ElementTy);
7166 Flags.setByValAlign(FrameAlign);
7170 Flags.setOrigAlign(OriginalAlignment);
7172 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7173 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7174 SmallVector<SDValue, 4> Parts(NumParts);
7175 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7178 ExtendKind = ISD::SIGN_EXTEND;
7179 else if (Args[i].isZExt)
7180 ExtendKind = ISD::ZERO_EXTEND;
7182 // Conservatively only handle 'returned' on non-vectors for now
7183 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7184 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7185 "unexpected use of 'returned'");
7186 // Before passing 'returned' to the target lowering code, ensure that
7187 // either the register MVT and the actual EVT are the same size or that
7188 // the return value and argument are extended in the same way; in these
7189 // cases it's safe to pass the argument register value unchanged as the
7190 // return register value (although it's at the target's option whether
7192 // TODO: allow code generation to take advantage of partially preserved
7193 // registers rather than clobbering the entire register when the
7194 // parameter extension method is not compatible with the return
7196 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7197 (ExtendKind != ISD::ANY_EXTEND &&
7198 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7199 Flags.setReturned();
7202 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
7203 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
7205 for (unsigned j = 0; j != NumParts; ++j) {
7206 // if it isn't first piece, alignment must be 1
7207 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7208 i < CLI.NumFixedArgs,
7209 i, j*Parts[j].getValueType().getStoreSize());
7210 if (NumParts > 1 && j == 0)
7211 MyFlags.Flags.setSplit();
7213 MyFlags.Flags.setOrigAlign(1);
7215 CLI.Outs.push_back(MyFlags);
7216 CLI.OutVals.push_back(Parts[j]);
7221 SmallVector<SDValue, 4> InVals;
7222 CLI.Chain = LowerCall(CLI, InVals);
7224 // Verify that the target's LowerCall behaved as expected.
7225 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7226 "LowerCall didn't return a valid chain!");
7227 assert((!CLI.IsTailCall || InVals.empty()) &&
7228 "LowerCall emitted a return value for a tail call!");
7229 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7230 "LowerCall didn't emit the correct number of values!");
7232 // For a tail call, the return value is merely live-out and there aren't
7233 // any nodes in the DAG representing it. Return a special value to
7234 // indicate that a tail call has been emitted and no more Instructions
7235 // should be processed in the current block.
7236 if (CLI.IsTailCall) {
7237 CLI.DAG.setRoot(CLI.Chain);
7238 return std::make_pair(SDValue(), SDValue());
7241 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7242 assert(InVals[i].getNode() &&
7243 "LowerCall emitted a null value!");
7244 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7245 "LowerCall emitted a value with the wrong type!");
7248 // Collect the legal value parts into potentially illegal values
7249 // that correspond to the original function's return values.
7250 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7252 AssertOp = ISD::AssertSext;
7253 else if (CLI.RetZExt)
7254 AssertOp = ISD::AssertZext;
7255 SmallVector<SDValue, 4> ReturnValues;
7256 unsigned CurReg = 0;
7257 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7259 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7260 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7262 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7263 NumRegs, RegisterVT, VT, NULL,
7268 // For a function returning void, there is no return value. We can't create
7269 // such a node, so we just return a null return value in that case. In
7270 // that case, nothing will actually look at the value.
7271 if (ReturnValues.empty())
7272 return std::make_pair(SDValue(), CLI.Chain);
7274 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7275 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
7276 &ReturnValues[0], ReturnValues.size());
7277 return std::make_pair(Res, CLI.Chain);
7280 void TargetLowering::LowerOperationWrapper(SDNode *N,
7281 SmallVectorImpl<SDValue> &Results,
7282 SelectionDAG &DAG) const {
7283 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7285 Results.push_back(Res);
7288 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7289 llvm_unreachable("LowerOperation not implemented for this target!");
7293 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7294 SDValue Op = getNonRegisterValue(V);
7295 assert((Op.getOpcode() != ISD::CopyFromReg ||
7296 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7297 "Copy from a reg to the same reg!");
7298 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7300 const TargetLowering *TLI = TM.getTargetLowering();
7301 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7302 SDValue Chain = DAG.getEntryNode();
7303 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
7304 PendingExports.push_back(Chain);
7307 #include "llvm/CodeGen/SelectionDAGISel.h"
7309 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7310 /// entry block, return true. This includes arguments used by switches, since
7311 /// the switch may expand into multiple basic blocks.
7312 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7313 // With FastISel active, we may be splitting blocks, so force creation
7314 // of virtual registers for all non-dead arguments.
7316 return A->use_empty();
7318 const BasicBlock *Entry = A->getParent()->begin();
7319 for (const User *U : A->users())
7320 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7321 return false; // Use not in entry block.
7326 void SelectionDAGISel::LowerArguments(const Function &F) {
7327 SelectionDAG &DAG = SDB->DAG;
7328 SDLoc dl = SDB->getCurSDLoc();
7329 const TargetLowering *TLI = getTargetLowering();
7330 const DataLayout *DL = TLI->getDataLayout();
7331 SmallVector<ISD::InputArg, 16> Ins;
7333 if (!FuncInfo->CanLowerReturn) {
7334 // Put in an sret pointer parameter before all the other parameters.
7335 SmallVector<EVT, 1> ValueVTs;
7336 ComputeValueVTs(*getTargetLowering(),
7337 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7339 // NOTE: Assuming that a pointer will never break down to more than one VT
7341 ISD::ArgFlagsTy Flags;
7343 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7344 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7345 Ins.push_back(RetArg);
7348 // Set up the incoming argument description vector.
7350 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7351 I != E; ++I, ++Idx) {
7352 SmallVector<EVT, 4> ValueVTs;
7353 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7354 bool isArgValueUsed = !I->use_empty();
7355 unsigned PartBase = 0;
7356 for (unsigned Value = 0, NumValues = ValueVTs.size();
7357 Value != NumValues; ++Value) {
7358 EVT VT = ValueVTs[Value];
7359 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7360 ISD::ArgFlagsTy Flags;
7361 unsigned OriginalAlignment =
7362 DL->getABITypeAlignment(ArgTy);
7364 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7366 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7368 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7370 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7372 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7374 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7375 Flags.setInAlloca();
7376 // Set the byval flag for CCAssignFn callbacks that don't know about
7377 // inalloca. This way we can know how many bytes we should've allocated
7378 // and how many bytes a callee cleanup function will pop. If we port
7379 // inalloca to more targets, we'll have to add custom inalloca handling
7380 // in the various CC lowering callbacks.
7383 if (Flags.isByVal() || Flags.isInAlloca()) {
7384 PointerType *Ty = cast<PointerType>(I->getType());
7385 Type *ElementTy = Ty->getElementType();
7386 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7387 // For ByVal, alignment should be passed from FE. BE will guess if
7388 // this info is not there but there are cases it cannot get right.
7389 unsigned FrameAlign;
7390 if (F.getParamAlignment(Idx))
7391 FrameAlign = F.getParamAlignment(Idx);
7393 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7394 Flags.setByValAlign(FrameAlign);
7396 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7398 Flags.setOrigAlign(OriginalAlignment);
7400 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7401 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7402 for (unsigned i = 0; i != NumRegs; ++i) {
7403 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7404 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7405 if (NumRegs > 1 && i == 0)
7406 MyFlags.Flags.setSplit();
7407 // if it isn't first piece, alignment must be 1
7409 MyFlags.Flags.setOrigAlign(1);
7410 Ins.push_back(MyFlags);
7412 PartBase += VT.getStoreSize();
7416 // Call the target to set up the argument values.
7417 SmallVector<SDValue, 8> InVals;
7418 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7422 // Verify that the target's LowerFormalArguments behaved as expected.
7423 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7424 "LowerFormalArguments didn't return a valid chain!");
7425 assert(InVals.size() == Ins.size() &&
7426 "LowerFormalArguments didn't emit the correct number of values!");
7428 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7429 assert(InVals[i].getNode() &&
7430 "LowerFormalArguments emitted a null value!");
7431 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7432 "LowerFormalArguments emitted a value with the wrong type!");
7436 // Update the DAG with the new chain value resulting from argument lowering.
7437 DAG.setRoot(NewRoot);
7439 // Set up the argument values.
7442 if (!FuncInfo->CanLowerReturn) {
7443 // Create a virtual register for the sret pointer, and put in a copy
7444 // from the sret argument into it.
7445 SmallVector<EVT, 1> ValueVTs;
7446 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7447 MVT VT = ValueVTs[0].getSimpleVT();
7448 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7449 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7450 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7451 RegVT, VT, NULL, AssertOp);
7453 MachineFunction& MF = SDB->DAG.getMachineFunction();
7454 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7455 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7456 FuncInfo->DemoteRegister = SRetReg;
7457 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7459 DAG.setRoot(NewRoot);
7461 // i indexes lowered arguments. Bump it past the hidden sret argument.
7462 // Idx indexes LLVM arguments. Don't touch it.
7466 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7468 SmallVector<SDValue, 4> ArgValues;
7469 SmallVector<EVT, 4> ValueVTs;
7470 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7471 unsigned NumValues = ValueVTs.size();
7473 // If this argument is unused then remember its value. It is used to generate
7474 // debugging information.
7475 if (I->use_empty() && NumValues) {
7476 SDB->setUnusedArgValue(I, InVals[i]);
7478 // Also remember any frame index for use in FastISel.
7479 if (FrameIndexSDNode *FI =
7480 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7481 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7484 for (unsigned Val = 0; Val != NumValues; ++Val) {
7485 EVT VT = ValueVTs[Val];
7486 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7487 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7489 if (!I->use_empty()) {
7490 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7491 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7492 AssertOp = ISD::AssertSext;
7493 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7494 AssertOp = ISD::AssertZext;
7496 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7497 NumParts, PartVT, VT,
7504 // We don't need to do anything else for unused arguments.
7505 if (ArgValues.empty())
7508 // Note down frame index.
7509 if (FrameIndexSDNode *FI =
7510 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7511 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7513 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7514 SDB->getCurSDLoc());
7516 SDB->setValue(I, Res);
7517 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7518 if (LoadSDNode *LNode =
7519 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7520 if (FrameIndexSDNode *FI =
7521 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7522 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7525 // If this argument is live outside of the entry block, insert a copy from
7526 // wherever we got it to the vreg that other BB's will reference it as.
7527 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7528 // If we can, though, try to skip creating an unnecessary vreg.
7529 // FIXME: This isn't very clean... it would be nice to make this more
7530 // general. It's also subtly incompatible with the hacks FastISel
7532 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7533 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7534 FuncInfo->ValueMap[I] = Reg;
7538 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7539 FuncInfo->InitializeRegForValue(I);
7540 SDB->CopyToExportRegsIfNeeded(I);
7544 assert(i == InVals.size() && "Argument register count mismatch!");
7546 // Finally, if the target has anything special to do, allow it to do so.
7547 // FIXME: this should insert code into the DAG!
7548 EmitFunctionEntryCode();
7551 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7552 /// ensure constants are generated when needed. Remember the virtual registers
7553 /// that need to be added to the Machine PHI nodes as input. We cannot just
7554 /// directly add them, because expansion might result in multiple MBB's for one
7555 /// BB. As such, the start of the BB might correspond to a different MBB than
7559 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7560 const TerminatorInst *TI = LLVMBB->getTerminator();
7562 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7564 // Check successor nodes' PHI nodes that expect a constant to be available
7566 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7567 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7568 if (!isa<PHINode>(SuccBB->begin())) continue;
7569 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7571 // If this terminator has multiple identical successors (common for
7572 // switches), only handle each succ once.
7573 if (!SuccsHandled.insert(SuccMBB)) continue;
7575 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7577 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7578 // nodes and Machine PHI nodes, but the incoming operands have not been
7580 for (BasicBlock::const_iterator I = SuccBB->begin();
7581 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7582 // Ignore dead phi's.
7583 if (PN->use_empty()) continue;
7586 if (PN->getType()->isEmptyTy())
7590 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7592 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7593 unsigned &RegOut = ConstantsOut[C];
7595 RegOut = FuncInfo.CreateRegs(C->getType());
7596 CopyValueToVirtualRegister(C, RegOut);
7600 DenseMap<const Value *, unsigned>::iterator I =
7601 FuncInfo.ValueMap.find(PHIOp);
7602 if (I != FuncInfo.ValueMap.end())
7605 assert(isa<AllocaInst>(PHIOp) &&
7606 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7607 "Didn't codegen value into a register!??");
7608 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7609 CopyValueToVirtualRegister(PHIOp, Reg);
7613 // Remember that this register needs to added to the machine PHI node as
7614 // the input for this MBB.
7615 SmallVector<EVT, 4> ValueVTs;
7616 const TargetLowering *TLI = TM.getTargetLowering();
7617 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7618 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7619 EVT VT = ValueVTs[vti];
7620 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7621 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7622 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7623 Reg += NumRegisters;
7628 ConstantsOut.clear();
7631 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7634 SelectionDAGBuilder::StackProtectorDescriptor::
7635 AddSuccessorMBB(const BasicBlock *BB,
7636 MachineBasicBlock *ParentMBB,
7637 MachineBasicBlock *SuccMBB) {
7638 // If SuccBB has not been created yet, create it.
7640 MachineFunction *MF = ParentMBB->getParent();
7641 MachineFunction::iterator BBI = ParentMBB;
7642 SuccMBB = MF->CreateMachineBasicBlock(BB);
7643 MF->insert(++BBI, SuccMBB);
7645 // Add it as a successor of ParentMBB.
7646 ParentMBB->addSuccessor(SuccMBB);