1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert(PartVT.isInteger() && ValueVT.isInteger() &&
357 "Unknown mismatch!");
358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 } else if (PartBits == ValueVT.getSizeInBits()) {
362 // Different types of the same size.
363 assert(NumParts == 1 && PartVT != ValueVT);
364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
366 // If the parts cover less bits than value has, truncate the value.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Unknown mismatch!");
369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
373 // The value may have changed - recompute ValueVT.
374 ValueVT = Val.getValueType();
375 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
376 "Failed to tile the value with PartVT!");
379 assert(PartVT == ValueVT && "Type conversion failed!");
384 // Expand the value into multiple parts.
385 if (NumParts & (NumParts - 1)) {
386 // The number of parts is not a power of 2. Split off and copy the tail.
387 assert(PartVT.isInteger() && ValueVT.isInteger() &&
388 "Do not know what to expand to!");
389 unsigned RoundParts = 1 << Log2_32(NumParts);
390 unsigned RoundBits = RoundParts * PartBits;
391 unsigned OddParts = NumParts - RoundParts;
392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
393 DAG.getIntPtrConstant(RoundBits));
394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
396 if (TLI.isBigEndian())
397 // The odd parts were reversed by getCopyToParts - unreverse them.
398 std::reverse(Parts + RoundParts, Parts + NumParts);
400 NumParts = RoundParts;
401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 // The number of parts is a power of 2. Repeatedly bisect the value using
407 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
408 EVT::getIntegerVT(*DAG.getContext(),
409 ValueVT.getSizeInBits()),
412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
413 for (unsigned i = 0; i < NumParts; i += StepSize) {
414 unsigned ThisBits = StepSize * PartBits / 2;
415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
416 SDValue &Part0 = Parts[i];
417 SDValue &Part1 = Parts[i+StepSize/2];
419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
420 ThisVT, Part0, DAG.getIntPtrConstant(1));
421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
422 ThisVT, Part0, DAG.getIntPtrConstant(0));
424 if (ThisBits == PartBits && ThisVT != PartVT) {
425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
431 if (TLI.isBigEndian())
432 std::reverse(Parts, Parts + OrigNumParts);
436 /// getCopyToPartsVector - Create a series of nodes that contain the specified
437 /// value split into legal parts.
438 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
439 SDValue Val, SDValue *Parts, unsigned NumParts,
441 EVT ValueVT = Val.getValueType();
442 assert(ValueVT.isVector() && "Not a vector");
443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
446 if (PartVT == ValueVT) {
448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
449 // Bitconvert vector->vector case.
450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
451 } else if (PartVT.isVector() &&
452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
454 EVT ElementVT = PartVT.getVectorElementType();
455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
457 SmallVector<SDValue, 16> Ops;
458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
460 ElementVT, Val, DAG.getIntPtrConstant(i)));
462 for (unsigned i = ValueVT.getVectorNumElements(),
463 e = PartVT.getVectorNumElements(); i != e; ++i)
464 Ops.push_back(DAG.getUNDEF(ElementVT));
466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
468 // FIXME: Use CONCAT for 2x -> 4x.
470 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
472 } else if (PartVT.isVector() &&
473 PartVT.getVectorElementType().bitsGE(
474 ValueVT.getVectorElementType()) &&
475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
477 // Promoted vector extract
478 bool Smaller = PartVT.bitsLE(ValueVT);
479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
482 // Vector -> scalar conversion.
483 assert(ValueVT.getVectorNumElements() == 1 &&
484 "Only trivial vector-to-scalar conversions should get here!");
485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 PartVT, Val, DAG.getIntPtrConstant(0));
488 bool Smaller = ValueVT.bitsLE(PartVT);
489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
497 // Handle a multi-element vector.
498 EVT IntermediateVT, RegisterVT;
499 unsigned NumIntermediates;
500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
502 NumIntermediates, RegisterVT);
503 unsigned NumElements = ValueVT.getVectorNumElements();
505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
506 NumParts = NumRegs; // Silence a compiler warning.
507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
509 // Split the vector into intermediate operands.
510 SmallVector<SDValue, 8> Ops(NumIntermediates);
511 for (unsigned i = 0; i != NumIntermediates; ++i) {
512 if (IntermediateVT.isVector())
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 IntermediateVT, Val, DAG.getIntPtrConstant(i));
521 // Split the intermediate operands into legal parts.
522 if (NumParts == NumIntermediates) {
523 // If the register was not expanded, promote or copy the value,
525 for (unsigned i = 0; i != NumParts; ++i)
526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
527 } else if (NumParts > 0) {
528 // If the intermediate type was expanded, split each the value into
530 assert(NumParts % NumIntermediates == 0 &&
531 "Must expand into a divisible number of parts!");
532 unsigned Factor = NumParts / NumIntermediates;
533 for (unsigned i = 0; i != NumIntermediates; ++i)
534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
542 /// RegsForValue - This struct represents the registers (physical or virtual)
543 /// that a particular set of values is assigned, and the type information
544 /// about the value. The most common situation is to represent one value at a
545 /// time, but struct or array values are handled element-wise as multiple
546 /// values. The splitting of aggregates is performed recursively, so that we
547 /// never have aggregate-typed registers. The values at this point do not
548 /// necessarily have legal types, so each value may require one or more
549 /// registers of some legal type.
551 struct RegsForValue {
552 /// ValueVTs - The value types of the values, which may not be legal, and
553 /// may need be promoted or synthesized from one or more registers.
555 SmallVector<EVT, 4> ValueVTs;
557 /// RegVTs - The value types of the registers. This is the same size as
558 /// ValueVTs and it records, for each value, what the type of the assigned
559 /// register or registers are. (Individual values are never synthesized
560 /// from more than one type of register.)
562 /// With virtual registers, the contents of RegVTs is redundant with TLI's
563 /// getRegisterType member function, however when with physical registers
564 /// it is necessary to have a separate record of the types.
566 SmallVector<EVT, 4> RegVTs;
568 /// Regs - This list holds the registers assigned to the values.
569 /// Each legal or promoted value requires one register, and each
570 /// expanded value requires multiple registers.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> ®s,
577 EVT regvt, EVT valuevt)
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
580 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
581 unsigned Reg, Type *Ty) {
582 ComputeValueVTs(tli, Ty, ValueVTs);
584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
585 EVT ValueVT = ValueVTs[Value];
586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
588 for (unsigned i = 0; i != NumRegs; ++i)
589 Regs.push_back(Reg + i);
590 RegVTs.push_back(RegisterVT);
595 /// areValueTypesLegal - Return true if types of all the values are legal.
596 bool areValueTypesLegal(const TargetLowering &TLI) {
597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
598 EVT RegisterVT = RegVTs[Value];
599 if (!TLI.isTypeLegal(RegisterVT))
605 /// append - Add the specified values to this one.
606 void append(const RegsForValue &RHS) {
607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
613 /// this value and returns the result as a ValueVTs value. This uses
614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
615 /// If the Flag pointer is NULL, no flag is used.
616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
618 SDValue &Chain, SDValue *Flag) const;
620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
621 /// specified value into the registers specified by this object. This uses
622 /// Chain/Flag as the input and updates them for the output Chain/Flag.
623 /// If the Flag pointer is NULL, no flag is used.
624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
625 SDValue &Chain, SDValue *Flag) const;
627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
628 /// operand list. This adds the code marker, matching input operand index
629 /// (if applicable), and includes the number of values added into it.
630 void AddInlineAsmOperands(unsigned Kind,
631 bool HasMatching, unsigned MatchingIdx,
633 std::vector<SDValue> &Ops) const;
637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
638 /// this value and returns the result as a ValueVT value. This uses
639 /// Chain/Flag as the input and updates them for the output Chain/Flag.
640 /// If the Flag pointer is NULL, no flag is used.
641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
642 FunctionLoweringInfo &FuncInfo,
644 SDValue &Chain, SDValue *Flag) const {
645 // A Value with type {} or [0 x %t] needs no registers.
646 if (ValueVTs.empty())
649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
651 // Assemble the legal parts into the final values.
652 SmallVector<SDValue, 4> Values(ValueVTs.size());
653 SmallVector<SDValue, 8> Parts;
654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
655 // Copy the legal parts from the registers.
656 EVT ValueVT = ValueVTs[Value];
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
658 EVT RegisterVT = RegVTs[Value];
660 Parts.resize(NumRegs);
661 for (unsigned i = 0; i != NumRegs; ++i) {
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
667 *Flag = P.getValue(2);
670 Chain = P.getValue(1);
673 // If the source register was virtual and if we know something about it,
674 // add an assert node.
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
676 !RegisterVT.isInteger() || RegisterVT.isVector())
679 const FunctionLoweringInfo::LiveOutInfo *LOI =
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
684 unsigned RegSize = RegisterVT.getSizeInBits();
685 unsigned NumSignBits = LOI->NumSignBits;
686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
688 // FIXME: We capture more information than the dag can represent. For
689 // now, just use the tightest assertzext/assertsext possible.
691 EVT FromVT(MVT::Other);
692 if (NumSignBits == RegSize)
693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
694 else if (NumZeroBits >= RegSize-1)
695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
696 else if (NumSignBits > RegSize-8)
697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
698 else if (NumZeroBits >= RegSize-8)
699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
700 else if (NumSignBits > RegSize-16)
701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
702 else if (NumZeroBits >= RegSize-16)
703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
704 else if (NumSignBits > RegSize-32)
705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
706 else if (NumZeroBits >= RegSize-32)
707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
711 // Add an assertion node.
712 assert(FromVT != MVT::Other);
713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
714 RegisterVT, P, DAG.getValueType(FromVT));
717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
718 NumRegs, RegisterVT, ValueVT);
723 return DAG.getNode(ISD::MERGE_VALUES, dl,
724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
725 &Values[0], ValueVTs.size());
728 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
729 /// specified value into the registers specified by this object. This uses
730 /// Chain/Flag as the input and updates them for the output Chain/Flag.
731 /// If the Flag pointer is NULL, no flag is used.
732 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
733 SDValue &Chain, SDValue *Flag) const {
734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 // Get the list of the values's legal parts.
737 unsigned NumRegs = Regs.size();
738 SmallVector<SDValue, 8> Parts(NumRegs);
739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
740 EVT ValueVT = ValueVTs[Value];
741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
742 EVT RegisterVT = RegVTs[Value];
744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
745 &Parts[Part], NumParts, RegisterVT);
749 // Copy the parts into the registers.
750 SmallVector<SDValue, 8> Chains(NumRegs);
751 for (unsigned i = 0; i != NumRegs; ++i) {
754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
757 *Flag = Part.getValue(1);
760 Chains[i] = Part.getValue(0);
763 if (NumRegs == 1 || Flag)
764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
765 // flagged to it. That is the CopyToReg nodes and the user are considered
766 // a single scheduling unit. If we create a TokenFactor and return it as
767 // chain, then the TokenFactor is both a predecessor (operand) of the
768 // user as well as a successor (the TF operands are flagged to the user).
769 // c1, f1 = CopyToReg
770 // c2, f2 = CopyToReg
771 // c3 = TokenFactor c1, c2
774 Chain = Chains[NumRegs-1];
776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
779 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
780 /// operand list. This adds the code marker and includes the number of
781 /// values added into it.
782 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
783 unsigned MatchingIdx,
785 std::vector<SDValue> &Ops) const {
786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
791 else if (!Regs.empty() &&
792 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
793 // Put the register class of the virtual registers in the flag word. That
794 // way, later passes can recompute register class constraints for inline
795 // assembly as well as normal instructions.
796 // Don't do this for tied operands that can use the regclass information
798 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
799 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
800 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
803 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
806 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
807 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
808 EVT RegisterVT = RegVTs[Value];
809 for (unsigned i = 0; i != NumRegs; ++i) {
810 assert(Reg < Regs.size() && "Mismatch in # registers expected");
811 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
816 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
817 const TargetLibraryInfo *li) {
821 TD = DAG.getTarget().getTargetData();
822 LPadToCallSiteMap.clear();
825 /// clear - Clear out the current SelectionDAG and the associated
826 /// state and prepare this SelectionDAGBuilder object to be used
827 /// for a new block. This doesn't clear out information about
828 /// additional blocks that are needed to complete switch lowering
829 /// or PHI node updating; that information is cleared out as it is
831 void SelectionDAGBuilder::clear() {
833 UnusedArgNodeMap.clear();
834 PendingLoads.clear();
835 PendingExports.clear();
836 CurDebugLoc = DebugLoc();
840 /// clearDanglingDebugInfo - Clear the dangling debug information
841 /// map. This function is seperated from the clear so that debug
842 /// information that is dangling in a basic block can be properly
843 /// resolved in a different basic block. This allows the
844 /// SelectionDAG to resolve dangling debug information attached
846 void SelectionDAGBuilder::clearDanglingDebugInfo() {
847 DanglingDebugInfoMap.clear();
850 /// getRoot - Return the current virtual root of the Selection DAG,
851 /// flushing any PendingLoad items. This must be done before emitting
852 /// a store or any other node that may need to be ordered after any
853 /// prior load instructions.
855 SDValue SelectionDAGBuilder::getRoot() {
856 if (PendingLoads.empty())
857 return DAG.getRoot();
859 if (PendingLoads.size() == 1) {
860 SDValue Root = PendingLoads[0];
862 PendingLoads.clear();
866 // Otherwise, we have to make a token factor node.
867 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
868 &PendingLoads[0], PendingLoads.size());
869 PendingLoads.clear();
874 /// getControlRoot - Similar to getRoot, but instead of flushing all the
875 /// PendingLoad items, flush all the PendingExports items. It is necessary
876 /// to do this before emitting a terminator instruction.
878 SDValue SelectionDAGBuilder::getControlRoot() {
879 SDValue Root = DAG.getRoot();
881 if (PendingExports.empty())
884 // Turn all of the CopyToReg chains into one factored node.
885 if (Root.getOpcode() != ISD::EntryToken) {
886 unsigned i = 0, e = PendingExports.size();
887 for (; i != e; ++i) {
888 assert(PendingExports[i].getNode()->getNumOperands() > 1);
889 if (PendingExports[i].getNode()->getOperand(0) == Root)
890 break; // Don't add the root if we already indirectly depend on it.
894 PendingExports.push_back(Root);
897 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
899 PendingExports.size());
900 PendingExports.clear();
905 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
906 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
907 DAG.AssignOrdering(Node, SDNodeOrder);
909 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
910 AssignOrderingToNode(Node->getOperand(I).getNode());
913 void SelectionDAGBuilder::visit(const Instruction &I) {
914 // Set up outgoing PHI node register values before emitting the terminator.
915 if (isa<TerminatorInst>(&I))
916 HandlePHINodesInSuccessorBlocks(I.getParent());
918 CurDebugLoc = I.getDebugLoc();
920 visit(I.getOpcode(), I);
922 if (!isa<TerminatorInst>(&I) && !HasTailCall)
923 CopyToExportRegsIfNeeded(&I);
925 CurDebugLoc = DebugLoc();
928 void SelectionDAGBuilder::visitPHI(const PHINode &) {
929 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
932 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
933 // Note: this doesn't use InstVisitor, because it has to work with
934 // ConstantExpr's in addition to instructions.
936 default: llvm_unreachable("Unknown instruction type encountered!");
937 // Build the switch statement using the Instruction.def file.
938 #define HANDLE_INST(NUM, OPCODE, CLASS) \
939 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
940 #include "llvm/Instruction.def"
943 // Assign the ordering to the freshly created DAG nodes.
944 if (NodeMap.count(&I)) {
946 AssignOrderingToNode(getValue(&I).getNode());
950 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
951 // generate the debug data structures now that we've seen its definition.
952 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
954 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
956 const DbgValueInst *DI = DDI.getDI();
957 DebugLoc dl = DDI.getdl();
958 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
959 MDNode *Variable = DI->getVariable();
960 uint64_t Offset = DI->getOffset();
963 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
964 SDV = DAG.getDbgValue(Variable, Val.getNode(),
965 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
966 DAG.AddDbgValue(SDV, Val.getNode(), false);
969 DEBUG(dbgs() << "Dropping debug info for " << DI);
970 DanglingDebugInfoMap[V] = DanglingDebugInfo();
974 /// getValue - Return an SDValue for the given Value.
975 SDValue SelectionDAGBuilder::getValue(const Value *V) {
976 // If we already have an SDValue for this value, use it. It's important
977 // to do this first, so that we don't create a CopyFromReg if we already
978 // have a regular SDValue.
979 SDValue &N = NodeMap[V];
980 if (N.getNode()) return N;
982 // If there's a virtual register allocated and initialized for this
984 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
985 if (It != FuncInfo.ValueMap.end()) {
986 unsigned InReg = It->second;
987 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
988 SDValue Chain = DAG.getEntryNode();
989 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
990 resolveDanglingDebugInfo(V, N);
994 // Otherwise create a new SDValue and remember it.
995 SDValue Val = getValueImpl(V);
997 resolveDanglingDebugInfo(V, Val);
1001 /// getNonRegisterValue - Return an SDValue for the given Value, but
1002 /// don't look in FuncInfo.ValueMap for a virtual register.
1003 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1004 // If we already have an SDValue for this value, use it.
1005 SDValue &N = NodeMap[V];
1006 if (N.getNode()) return N;
1008 // Otherwise create a new SDValue and remember it.
1009 SDValue Val = getValueImpl(V);
1011 resolveDanglingDebugInfo(V, Val);
1015 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1016 /// Create an SDValue for the given value.
1017 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1018 if (const Constant *C = dyn_cast<Constant>(V)) {
1019 EVT VT = TLI.getValueType(V->getType(), true);
1021 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1022 return DAG.getConstant(*CI, VT);
1024 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1025 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1027 if (isa<ConstantPointerNull>(C))
1028 return DAG.getConstant(0, TLI.getPointerTy());
1030 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1031 return DAG.getConstantFP(*CFP, VT);
1033 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1034 return DAG.getUNDEF(VT);
1036 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1037 visit(CE->getOpcode(), *CE);
1038 SDValue N1 = NodeMap[V];
1039 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1043 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1044 SmallVector<SDValue, 4> Constants;
1045 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1047 SDNode *Val = getValue(*OI).getNode();
1048 // If the operand is an empty aggregate, there are no values.
1050 // Add each leaf value from the operand to the Constants list
1051 // to form a flattened list of all the values.
1052 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1053 Constants.push_back(SDValue(Val, i));
1056 return DAG.getMergeValues(&Constants[0], Constants.size(),
1060 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1061 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1062 "Unknown struct or array constant!");
1064 SmallVector<EVT, 4> ValueVTs;
1065 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1066 unsigned NumElts = ValueVTs.size();
1068 return SDValue(); // empty struct
1069 SmallVector<SDValue, 4> Constants(NumElts);
1070 for (unsigned i = 0; i != NumElts; ++i) {
1071 EVT EltVT = ValueVTs[i];
1072 if (isa<UndefValue>(C))
1073 Constants[i] = DAG.getUNDEF(EltVT);
1074 else if (EltVT.isFloatingPoint())
1075 Constants[i] = DAG.getConstantFP(0, EltVT);
1077 Constants[i] = DAG.getConstant(0, EltVT);
1080 return DAG.getMergeValues(&Constants[0], NumElts,
1084 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1085 return DAG.getBlockAddress(BA, VT);
1087 VectorType *VecTy = cast<VectorType>(V->getType());
1088 unsigned NumElements = VecTy->getNumElements();
1090 // Now that we know the number and type of the elements, get that number of
1091 // elements into the Ops array based on what kind of constant it is.
1092 SmallVector<SDValue, 16> Ops;
1093 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1094 for (unsigned i = 0; i != NumElements; ++i)
1095 Ops.push_back(getValue(CP->getOperand(i)));
1097 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1098 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1101 if (EltVT.isFloatingPoint())
1102 Op = DAG.getConstantFP(0, EltVT);
1104 Op = DAG.getConstant(0, EltVT);
1105 Ops.assign(NumElements, Op);
1108 // Create a BUILD_VECTOR node.
1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1110 VT, &Ops[0], Ops.size());
1113 // If this is a static alloca, generate it as the frameindex instead of
1115 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1116 DenseMap<const AllocaInst*, int>::iterator SI =
1117 FuncInfo.StaticAllocaMap.find(AI);
1118 if (SI != FuncInfo.StaticAllocaMap.end())
1119 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1122 // If this is an instruction which fast-isel has deferred, select it now.
1123 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1124 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1125 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1126 SDValue Chain = DAG.getEntryNode();
1127 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1130 llvm_unreachable("Can't get register for value!");
1134 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1135 SDValue Chain = getControlRoot();
1136 SmallVector<ISD::OutputArg, 8> Outs;
1137 SmallVector<SDValue, 8> OutVals;
1139 if (!FuncInfo.CanLowerReturn) {
1140 unsigned DemoteReg = FuncInfo.DemoteRegister;
1141 const Function *F = I.getParent()->getParent();
1143 // Emit a store of the return value through the virtual register.
1144 // Leave Outs empty so that LowerReturn won't try to load return
1145 // registers the usual way.
1146 SmallVector<EVT, 1> PtrValueVTs;
1147 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1150 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1151 SDValue RetOp = getValue(I.getOperand(0));
1153 SmallVector<EVT, 4> ValueVTs;
1154 SmallVector<uint64_t, 4> Offsets;
1155 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1156 unsigned NumValues = ValueVTs.size();
1158 SmallVector<SDValue, 4> Chains(NumValues);
1159 for (unsigned i = 0; i != NumValues; ++i) {
1160 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1161 RetPtr.getValueType(), RetPtr,
1162 DAG.getIntPtrConstant(Offsets[i]));
1164 DAG.getStore(Chain, getCurDebugLoc(),
1165 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1166 // FIXME: better loc info would be nice.
1167 Add, MachinePointerInfo(), false, false, 0);
1170 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1171 MVT::Other, &Chains[0], NumValues);
1172 } else if (I.getNumOperands() != 0) {
1173 SmallVector<EVT, 4> ValueVTs;
1174 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1175 unsigned NumValues = ValueVTs.size();
1177 SDValue RetOp = getValue(I.getOperand(0));
1178 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1179 EVT VT = ValueVTs[j];
1181 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1183 const Function *F = I.getParent()->getParent();
1184 if (F->paramHasAttr(0, Attribute::SExt))
1185 ExtendKind = ISD::SIGN_EXTEND;
1186 else if (F->paramHasAttr(0, Attribute::ZExt))
1187 ExtendKind = ISD::ZERO_EXTEND;
1189 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1190 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1192 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1193 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1194 SmallVector<SDValue, 4> Parts(NumParts);
1195 getCopyToParts(DAG, getCurDebugLoc(),
1196 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1197 &Parts[0], NumParts, PartVT, ExtendKind);
1199 // 'inreg' on function refers to return value
1200 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1201 if (F->paramHasAttr(0, Attribute::InReg))
1204 // Propagate extension type if any
1205 if (ExtendKind == ISD::SIGN_EXTEND)
1207 else if (ExtendKind == ISD::ZERO_EXTEND)
1210 for (unsigned i = 0; i < NumParts; ++i) {
1211 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1213 OutVals.push_back(Parts[i]);
1219 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1220 CallingConv::ID CallConv =
1221 DAG.getMachineFunction().getFunction()->getCallingConv();
1222 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1223 Outs, OutVals, getCurDebugLoc(), DAG);
1225 // Verify that the target's LowerReturn behaved as expected.
1226 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1227 "LowerReturn didn't return a valid chain!");
1229 // Update the DAG with the new chain value resulting from return lowering.
1233 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1234 /// created for it, emit nodes to copy the value into the virtual
1236 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1238 if (V->getType()->isEmptyTy())
1241 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1242 if (VMI != FuncInfo.ValueMap.end()) {
1243 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1244 CopyValueToVirtualRegister(V, VMI->second);
1248 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1249 /// the current basic block, add it to ValueMap now so that we'll get a
1251 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1252 // No need to export constants.
1253 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1255 // Already exported?
1256 if (FuncInfo.isExportedInst(V)) return;
1258 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1259 CopyValueToVirtualRegister(V, Reg);
1262 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1263 const BasicBlock *FromBB) {
1264 // The operands of the setcc have to be in this block. We don't know
1265 // how to export them from some other block.
1266 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1267 // Can export from current BB.
1268 if (VI->getParent() == FromBB)
1271 // Is already exported, noop.
1272 return FuncInfo.isExportedInst(V);
1275 // If this is an argument, we can export it if the BB is the entry block or
1276 // if it is already exported.
1277 if (isa<Argument>(V)) {
1278 if (FromBB == &FromBB->getParent()->getEntryBlock())
1281 // Otherwise, can only export this if it is already exported.
1282 return FuncInfo.isExportedInst(V);
1285 // Otherwise, constants can always be exported.
1289 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1290 uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src,
1291 MachineBasicBlock *Dst) {
1292 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1295 const BasicBlock *SrcBB = Src->getBasicBlock();
1296 const BasicBlock *DstBB = Dst->getBasicBlock();
1297 return BPI->getEdgeWeight(SrcBB, DstBB);
1300 void SelectionDAGBuilder::
1301 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1302 uint32_t Weight /* = 0 */) {
1304 Weight = getEdgeWeight(Src, Dst);
1305 Src->addSuccessor(Dst, Weight);
1309 static bool InBlock(const Value *V, const BasicBlock *BB) {
1310 if (const Instruction *I = dyn_cast<Instruction>(V))
1311 return I->getParent() == BB;
1315 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1316 /// This function emits a branch and is used at the leaves of an OR or an
1317 /// AND operator tree.
1320 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1321 MachineBasicBlock *TBB,
1322 MachineBasicBlock *FBB,
1323 MachineBasicBlock *CurBB,
1324 MachineBasicBlock *SwitchBB) {
1325 const BasicBlock *BB = CurBB->getBasicBlock();
1327 // If the leaf of the tree is a comparison, merge the condition into
1329 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1330 // The operands of the cmp have to be in this block. We don't know
1331 // how to export them from some other block. If this is the first block
1332 // of the sequence, no exporting is needed.
1333 if (CurBB == SwitchBB ||
1334 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1335 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1336 ISD::CondCode Condition;
1337 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1338 Condition = getICmpCondCode(IC->getPredicate());
1339 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1340 Condition = getFCmpCondCode(FC->getPredicate());
1341 if (TM.Options.NoNaNsFPMath)
1342 Condition = getFCmpCodeWithoutNaN(Condition);
1344 Condition = ISD::SETEQ; // silence warning.
1345 llvm_unreachable("Unknown compare instruction");
1348 CaseBlock CB(Condition, BOp->getOperand(0),
1349 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1350 SwitchCases.push_back(CB);
1355 // Create a CaseBlock record representing this branch.
1356 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1357 NULL, TBB, FBB, CurBB);
1358 SwitchCases.push_back(CB);
1361 /// FindMergedConditions - If Cond is an expression like
1362 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1363 MachineBasicBlock *TBB,
1364 MachineBasicBlock *FBB,
1365 MachineBasicBlock *CurBB,
1366 MachineBasicBlock *SwitchBB,
1368 // If this node is not part of the or/and tree, emit it as a branch.
1369 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1370 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1371 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1372 BOp->getParent() != CurBB->getBasicBlock() ||
1373 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1374 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1375 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1379 // Create TmpBB after CurBB.
1380 MachineFunction::iterator BBI = CurBB;
1381 MachineFunction &MF = DAG.getMachineFunction();
1382 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1383 CurBB->getParent()->insert(++BBI, TmpBB);
1385 if (Opc == Instruction::Or) {
1386 // Codegen X | Y as:
1394 // Emit the LHS condition.
1395 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1397 // Emit the RHS condition into TmpBB.
1398 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1400 assert(Opc == Instruction::And && "Unknown merge op!");
1401 // Codegen X & Y as:
1408 // This requires creation of TmpBB after CurBB.
1410 // Emit the LHS condition.
1411 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1413 // Emit the RHS condition into TmpBB.
1414 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1418 /// If the set of cases should be emitted as a series of branches, return true.
1419 /// If we should emit this as a bunch of and/or'd together conditions, return
1422 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1423 if (Cases.size() != 2) return true;
1425 // If this is two comparisons of the same values or'd or and'd together, they
1426 // will get folded into a single comparison, so don't emit two blocks.
1427 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1428 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1429 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1430 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1434 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1435 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1436 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1437 Cases[0].CC == Cases[1].CC &&
1438 isa<Constant>(Cases[0].CmpRHS) &&
1439 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1440 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1442 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1449 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1450 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1452 // Update machine-CFG edges.
1453 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1455 // Figure out which block is immediately after the current one.
1456 MachineBasicBlock *NextBlock = 0;
1457 MachineFunction::iterator BBI = BrMBB;
1458 if (++BBI != FuncInfo.MF->end())
1461 if (I.isUnconditional()) {
1462 // Update machine-CFG edges.
1463 BrMBB->addSuccessor(Succ0MBB);
1465 // If this is not a fall-through branch, emit the branch.
1466 if (Succ0MBB != NextBlock)
1467 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1468 MVT::Other, getControlRoot(),
1469 DAG.getBasicBlock(Succ0MBB)));
1474 // If this condition is one of the special cases we handle, do special stuff
1476 const Value *CondVal = I.getCondition();
1477 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1479 // If this is a series of conditions that are or'd or and'd together, emit
1480 // this as a sequence of branches instead of setcc's with and/or operations.
1481 // As long as jumps are not expensive, this should improve performance.
1482 // For example, instead of something like:
1495 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1496 if (!TLI.isJumpExpensive() &&
1498 (BOp->getOpcode() == Instruction::And ||
1499 BOp->getOpcode() == Instruction::Or)) {
1500 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1502 // If the compares in later blocks need to use values not currently
1503 // exported from this block, export them now. This block should always
1504 // be the first entry.
1505 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1507 // Allow some cases to be rejected.
1508 if (ShouldEmitAsBranches(SwitchCases)) {
1509 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1510 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1511 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1514 // Emit the branch for this block.
1515 visitSwitchCase(SwitchCases[0], BrMBB);
1516 SwitchCases.erase(SwitchCases.begin());
1520 // Okay, we decided not to do this, remove any inserted MBB's and clear
1522 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1523 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1525 SwitchCases.clear();
1529 // Create a CaseBlock record representing this branch.
1530 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1531 NULL, Succ0MBB, Succ1MBB, BrMBB);
1533 // Use visitSwitchCase to actually insert the fast branch sequence for this
1535 visitSwitchCase(CB, BrMBB);
1538 /// visitSwitchCase - Emits the necessary code to represent a single node in
1539 /// the binary search tree resulting from lowering a switch instruction.
1540 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1541 MachineBasicBlock *SwitchBB) {
1543 SDValue CondLHS = getValue(CB.CmpLHS);
1544 DebugLoc dl = getCurDebugLoc();
1546 // Build the setcc now.
1547 if (CB.CmpMHS == NULL) {
1548 // Fold "(X == true)" to X and "(X == false)" to !X to
1549 // handle common cases produced by branch lowering.
1550 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1551 CB.CC == ISD::SETEQ)
1553 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1554 CB.CC == ISD::SETEQ) {
1555 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1556 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1558 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1560 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1562 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1563 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1565 SDValue CmpOp = getValue(CB.CmpMHS);
1566 EVT VT = CmpOp.getValueType();
1568 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1569 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1572 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1573 VT, CmpOp, DAG.getConstant(Low, VT));
1574 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1575 DAG.getConstant(High-Low, VT), ISD::SETULE);
1579 // Update successor info
1580 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1581 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1583 // Set NextBlock to be the MBB immediately after the current one, if any.
1584 // This is used to avoid emitting unnecessary branches to the next block.
1585 MachineBasicBlock *NextBlock = 0;
1586 MachineFunction::iterator BBI = SwitchBB;
1587 if (++BBI != FuncInfo.MF->end())
1590 // If the lhs block is the next block, invert the condition so that we can
1591 // fall through to the lhs instead of the rhs block.
1592 if (CB.TrueBB == NextBlock) {
1593 std::swap(CB.TrueBB, CB.FalseBB);
1594 SDValue True = DAG.getConstant(1, Cond.getValueType());
1595 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1598 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1599 MVT::Other, getControlRoot(), Cond,
1600 DAG.getBasicBlock(CB.TrueBB));
1602 // Insert the false branch. Do this even if it's a fall through branch,
1603 // this makes it easier to do DAG optimizations which require inverting
1604 // the branch condition.
1605 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1606 DAG.getBasicBlock(CB.FalseBB));
1608 DAG.setRoot(BrCond);
1611 /// visitJumpTable - Emit JumpTable node in the current MBB
1612 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1613 // Emit the code for the jump table
1614 assert(JT.Reg != -1U && "Should lower JT Header first!");
1615 EVT PTy = TLI.getPointerTy();
1616 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1618 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1619 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1620 MVT::Other, Index.getValue(1),
1622 DAG.setRoot(BrJumpTable);
1625 /// visitJumpTableHeader - This function emits necessary code to produce index
1626 /// in the JumpTable from switch case.
1627 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1628 JumpTableHeader &JTH,
1629 MachineBasicBlock *SwitchBB) {
1630 // Subtract the lowest switch case value from the value being switched on and
1631 // conditional branch to default mbb if the result is greater than the
1632 // difference between smallest and largest cases.
1633 SDValue SwitchOp = getValue(JTH.SValue);
1634 EVT VT = SwitchOp.getValueType();
1635 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1636 DAG.getConstant(JTH.First, VT));
1638 // The SDNode we just created, which holds the value being switched on minus
1639 // the smallest case value, needs to be copied to a virtual register so it
1640 // can be used as an index into the jump table in a subsequent basic block.
1641 // This value may be smaller or larger than the target's pointer type, and
1642 // therefore require extension or truncating.
1643 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1645 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1646 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1647 JumpTableReg, SwitchOp);
1648 JT.Reg = JumpTableReg;
1650 // Emit the range check for the jump table, and branch to the default block
1651 // for the switch statement if the value being switched on exceeds the largest
1652 // case in the switch.
1653 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1654 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1655 DAG.getConstant(JTH.Last-JTH.First,VT),
1658 // Set NextBlock to be the MBB immediately after the current one, if any.
1659 // This is used to avoid emitting unnecessary branches to the next block.
1660 MachineBasicBlock *NextBlock = 0;
1661 MachineFunction::iterator BBI = SwitchBB;
1663 if (++BBI != FuncInfo.MF->end())
1666 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1667 MVT::Other, CopyTo, CMP,
1668 DAG.getBasicBlock(JT.Default));
1670 if (JT.MBB != NextBlock)
1671 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1672 DAG.getBasicBlock(JT.MBB));
1674 DAG.setRoot(BrCond);
1677 /// visitBitTestHeader - This function emits necessary code to produce value
1678 /// suitable for "bit tests"
1679 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1680 MachineBasicBlock *SwitchBB) {
1681 // Subtract the minimum value
1682 SDValue SwitchOp = getValue(B.SValue);
1683 EVT VT = SwitchOp.getValueType();
1684 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1685 DAG.getConstant(B.First, VT));
1688 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1689 TLI.getSetCCResultType(Sub.getValueType()),
1690 Sub, DAG.getConstant(B.Range, VT),
1693 // Determine the type of the test operands.
1694 bool UsePtrType = false;
1695 if (!TLI.isTypeLegal(VT))
1698 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1699 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1700 // Switch table case range are encoded into series of masks.
1701 // Just use pointer type, it's guaranteed to fit.
1707 VT = TLI.getPointerTy();
1708 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1712 B.Reg = FuncInfo.CreateReg(VT);
1713 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1716 // Set NextBlock to be the MBB immediately after the current one, if any.
1717 // This is used to avoid emitting unnecessary branches to the next block.
1718 MachineBasicBlock *NextBlock = 0;
1719 MachineFunction::iterator BBI = SwitchBB;
1720 if (++BBI != FuncInfo.MF->end())
1723 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1725 addSuccessorWithWeight(SwitchBB, B.Default);
1726 addSuccessorWithWeight(SwitchBB, MBB);
1728 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1729 MVT::Other, CopyTo, RangeCmp,
1730 DAG.getBasicBlock(B.Default));
1732 if (MBB != NextBlock)
1733 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1734 DAG.getBasicBlock(MBB));
1736 DAG.setRoot(BrRange);
1739 /// visitBitTestCase - this function produces one "bit test"
1740 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1741 MachineBasicBlock* NextMBB,
1744 MachineBasicBlock *SwitchBB) {
1746 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1749 unsigned PopCount = CountPopulation_64(B.Mask);
1750 if (PopCount == 1) {
1751 // Testing for a single bit; just compare the shift count with what it
1752 // would need to be to shift a 1 bit in that position.
1753 Cmp = DAG.getSetCC(getCurDebugLoc(),
1754 TLI.getSetCCResultType(VT),
1756 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1758 } else if (PopCount == BB.Range) {
1759 // There is only one zero bit in the range, test for it directly.
1760 Cmp = DAG.getSetCC(getCurDebugLoc(),
1761 TLI.getSetCCResultType(VT),
1763 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1766 // Make desired shift
1767 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1768 DAG.getConstant(1, VT), ShiftOp);
1770 // Emit bit tests and jumps
1771 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1772 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1773 Cmp = DAG.getSetCC(getCurDebugLoc(),
1774 TLI.getSetCCResultType(VT),
1775 AndOp, DAG.getConstant(0, VT),
1779 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1780 addSuccessorWithWeight(SwitchBB, NextMBB);
1782 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1783 MVT::Other, getControlRoot(),
1784 Cmp, DAG.getBasicBlock(B.TargetBB));
1786 // Set NextBlock to be the MBB immediately after the current one, if any.
1787 // This is used to avoid emitting unnecessary branches to the next block.
1788 MachineBasicBlock *NextBlock = 0;
1789 MachineFunction::iterator BBI = SwitchBB;
1790 if (++BBI != FuncInfo.MF->end())
1793 if (NextMBB != NextBlock)
1794 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1795 DAG.getBasicBlock(NextMBB));
1800 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1801 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1803 // Retrieve successors.
1804 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1805 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1807 const Value *Callee(I.getCalledValue());
1808 if (isa<InlineAsm>(Callee))
1811 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1813 // If the value of the invoke is used outside of its defining block, make it
1814 // available as a virtual register.
1815 CopyToExportRegsIfNeeded(&I);
1817 // Update successor info
1818 addSuccessorWithWeight(InvokeMBB, Return);
1819 addSuccessorWithWeight(InvokeMBB, LandingPad);
1821 // Drop into normal successor.
1822 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1823 MVT::Other, getControlRoot(),
1824 DAG.getBasicBlock(Return)));
1827 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1830 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1831 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1834 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1835 assert(FuncInfo.MBB->isLandingPad() &&
1836 "Call to landingpad not in landing pad!");
1838 MachineBasicBlock *MBB = FuncInfo.MBB;
1839 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1840 AddLandingPadInfo(LP, MMI, MBB);
1842 SmallVector<EVT, 2> ValueVTs;
1843 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1845 // Insert the EXCEPTIONADDR instruction.
1846 assert(FuncInfo.MBB->isLandingPad() &&
1847 "Call to eh.exception not in landing pad!");
1848 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1850 Ops[0] = DAG.getRoot();
1851 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1852 SDValue Chain = Op1.getValue(1);
1854 // Insert the EHSELECTION instruction.
1855 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1858 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1859 Chain = Op2.getValue(1);
1860 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1864 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1865 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1868 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1869 setValue(&LP, RetPair.first);
1870 DAG.setRoot(RetPair.second);
1873 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1874 /// small case ranges).
1875 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1876 CaseRecVector& WorkList,
1878 MachineBasicBlock *Default,
1879 MachineBasicBlock *SwitchBB) {
1880 Case& BackCase = *(CR.Range.second-1);
1882 // Size is the number of Cases represented by this range.
1883 size_t Size = CR.Range.second - CR.Range.first;
1887 // Get the MachineFunction which holds the current MBB. This is used when
1888 // inserting any additional MBBs necessary to represent the switch.
1889 MachineFunction *CurMF = FuncInfo.MF;
1891 // Figure out which block is immediately after the current one.
1892 MachineBasicBlock *NextBlock = 0;
1893 MachineFunction::iterator BBI = CR.CaseBB;
1895 if (++BBI != FuncInfo.MF->end())
1898 // If any two of the cases has the same destination, and if one value
1899 // is the same as the other, but has one bit unset that the other has set,
1900 // use bit manipulation to do two compares at once. For example:
1901 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1902 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1903 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1904 if (Size == 2 && CR.CaseBB == SwitchBB) {
1905 Case &Small = *CR.Range.first;
1906 Case &Big = *(CR.Range.second-1);
1908 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1909 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1910 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1912 // Check that there is only one bit different.
1913 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1914 (SmallValue | BigValue) == BigValue) {
1915 // Isolate the common bit.
1916 APInt CommonBit = BigValue & ~SmallValue;
1917 assert((SmallValue | CommonBit) == BigValue &&
1918 CommonBit.countPopulation() == 1 && "Not a common bit?");
1920 SDValue CondLHS = getValue(SV);
1921 EVT VT = CondLHS.getValueType();
1922 DebugLoc DL = getCurDebugLoc();
1924 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1925 DAG.getConstant(CommonBit, VT));
1926 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1927 Or, DAG.getConstant(BigValue, VT),
1930 // Update successor info.
1931 addSuccessorWithWeight(SwitchBB, Small.BB);
1932 addSuccessorWithWeight(SwitchBB, Default);
1934 // Insert the true branch.
1935 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1936 getControlRoot(), Cond,
1937 DAG.getBasicBlock(Small.BB));
1939 // Insert the false branch.
1940 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1941 DAG.getBasicBlock(Default));
1943 DAG.setRoot(BrCond);
1949 // Rearrange the case blocks so that the last one falls through if possible.
1950 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1951 // The last case block won't fall through into 'NextBlock' if we emit the
1952 // branches in this order. See if rearranging a case value would help.
1953 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1954 if (I->BB == NextBlock) {
1955 std::swap(*I, BackCase);
1961 // Create a CaseBlock record representing a conditional branch to
1962 // the Case's target mbb if the value being switched on SV is equal
1964 MachineBasicBlock *CurBlock = CR.CaseBB;
1965 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1966 MachineBasicBlock *FallThrough;
1968 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1969 CurMF->insert(BBI, FallThrough);
1971 // Put SV in a virtual register to make it available from the new blocks.
1972 ExportFromCurrentBlock(SV);
1974 // If the last case doesn't match, go to the default block.
1975 FallThrough = Default;
1978 const Value *RHS, *LHS, *MHS;
1980 if (I->High == I->Low) {
1981 // This is just small small case range :) containing exactly 1 case
1983 LHS = SV; RHS = I->High; MHS = NULL;
1986 LHS = I->Low; MHS = SV; RHS = I->High;
1989 uint32_t ExtraWeight = I->ExtraWeight;
1990 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
1992 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
1994 // If emitting the first comparison, just call visitSwitchCase to emit the
1995 // code into the current block. Otherwise, push the CaseBlock onto the
1996 // vector to be later processed by SDISel, and insert the node's MBB
1997 // before the next MBB.
1998 if (CurBlock == SwitchBB)
1999 visitSwitchCase(CB, SwitchBB);
2001 SwitchCases.push_back(CB);
2003 CurBlock = FallThrough;
2009 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2010 return !TLI.getTargetMachine().Options.DisableJumpTables &&
2011 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2012 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2015 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2016 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2017 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2018 return (LastExt - FirstExt + 1ULL);
2021 /// handleJTSwitchCase - Emit jumptable for current switch case range
2022 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2023 CaseRecVector &WorkList,
2025 MachineBasicBlock *Default,
2026 MachineBasicBlock *SwitchBB) {
2027 Case& FrontCase = *CR.Range.first;
2028 Case& BackCase = *(CR.Range.second-1);
2030 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2031 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2033 APInt TSize(First.getBitWidth(), 0);
2034 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2037 if (!areJTsAllowed(TLI) || TSize.ult(4))
2040 APInt Range = ComputeRange(First, Last);
2041 // The density is TSize / Range. Require at least 40%.
2042 // It should not be possible for IntTSize to saturate for sane code, but make
2043 // sure we handle Range saturation correctly.
2044 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2045 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2046 if (IntTSize * 10 < IntRange * 4)
2049 DEBUG(dbgs() << "Lowering jump table\n"
2050 << "First entry: " << First << ". Last entry: " << Last << '\n'
2051 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2053 // Get the MachineFunction which holds the current MBB. This is used when
2054 // inserting any additional MBBs necessary to represent the switch.
2055 MachineFunction *CurMF = FuncInfo.MF;
2057 // Figure out which block is immediately after the current one.
2058 MachineFunction::iterator BBI = CR.CaseBB;
2061 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2063 // Create a new basic block to hold the code for loading the address
2064 // of the jump table, and jumping to it. Update successor information;
2065 // we will either branch to the default case for the switch, or the jump
2067 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2068 CurMF->insert(BBI, JumpTableBB);
2070 addSuccessorWithWeight(CR.CaseBB, Default);
2071 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2073 // Build a vector of destination BBs, corresponding to each target
2074 // of the jump table. If the value of the jump table slot corresponds to
2075 // a case statement, push the case's BB onto the vector, otherwise, push
2077 std::vector<MachineBasicBlock*> DestBBs;
2079 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2080 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2081 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2083 if (Low.sle(TEI) && TEI.sle(High)) {
2084 DestBBs.push_back(I->BB);
2088 DestBBs.push_back(Default);
2092 // Update successor info. Add one edge to each unique successor.
2093 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2094 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2095 E = DestBBs.end(); I != E; ++I) {
2096 if (!SuccsHandled[(*I)->getNumber()]) {
2097 SuccsHandled[(*I)->getNumber()] = true;
2098 addSuccessorWithWeight(JumpTableBB, *I);
2102 // Create a jump table index for this jump table.
2103 unsigned JTEncoding = TLI.getJumpTableEncoding();
2104 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2105 ->createJumpTableIndex(DestBBs);
2107 // Set the jump table information so that we can codegen it as a second
2108 // MachineBasicBlock
2109 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2110 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2111 if (CR.CaseBB == SwitchBB)
2112 visitJumpTableHeader(JT, JTH, SwitchBB);
2114 JTCases.push_back(JumpTableBlock(JTH, JT));
2118 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2120 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2121 CaseRecVector& WorkList,
2123 MachineBasicBlock *Default,
2124 MachineBasicBlock *SwitchBB) {
2125 // Get the MachineFunction which holds the current MBB. This is used when
2126 // inserting any additional MBBs necessary to represent the switch.
2127 MachineFunction *CurMF = FuncInfo.MF;
2129 // Figure out which block is immediately after the current one.
2130 MachineFunction::iterator BBI = CR.CaseBB;
2133 Case& FrontCase = *CR.Range.first;
2134 Case& BackCase = *(CR.Range.second-1);
2135 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2137 // Size is the number of Cases represented by this range.
2138 unsigned Size = CR.Range.second - CR.Range.first;
2140 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2141 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2143 CaseItr Pivot = CR.Range.first + Size/2;
2145 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2146 // (heuristically) allow us to emit JumpTable's later.
2147 APInt TSize(First.getBitWidth(), 0);
2148 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2152 APInt LSize = FrontCase.size();
2153 APInt RSize = TSize-LSize;
2154 DEBUG(dbgs() << "Selecting best pivot: \n"
2155 << "First: " << First << ", Last: " << Last <<'\n'
2156 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2157 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2159 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2160 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2161 APInt Range = ComputeRange(LEnd, RBegin);
2162 assert((Range - 2ULL).isNonNegative() &&
2163 "Invalid case distance");
2164 // Use volatile double here to avoid excess precision issues on some hosts,
2165 // e.g. that use 80-bit X87 registers.
2166 volatile double LDensity =
2167 (double)LSize.roundToDouble() /
2168 (LEnd - First + 1ULL).roundToDouble();
2169 volatile double RDensity =
2170 (double)RSize.roundToDouble() /
2171 (Last - RBegin + 1ULL).roundToDouble();
2172 double Metric = Range.logBase2()*(LDensity+RDensity);
2173 // Should always split in some non-trivial place
2174 DEBUG(dbgs() <<"=>Step\n"
2175 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2176 << "LDensity: " << LDensity
2177 << ", RDensity: " << RDensity << '\n'
2178 << "Metric: " << Metric << '\n');
2179 if (FMetric < Metric) {
2182 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2188 if (areJTsAllowed(TLI)) {
2189 // If our case is dense we *really* should handle it earlier!
2190 assert((FMetric > 0) && "Should handle dense range earlier!");
2192 Pivot = CR.Range.first + Size/2;
2195 CaseRange LHSR(CR.Range.first, Pivot);
2196 CaseRange RHSR(Pivot, CR.Range.second);
2197 Constant *C = Pivot->Low;
2198 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2200 // We know that we branch to the LHS if the Value being switched on is
2201 // less than the Pivot value, C. We use this to optimize our binary
2202 // tree a bit, by recognizing that if SV is greater than or equal to the
2203 // LHS's Case Value, and that Case Value is exactly one less than the
2204 // Pivot's Value, then we can branch directly to the LHS's Target,
2205 // rather than creating a leaf node for it.
2206 if ((LHSR.second - LHSR.first) == 1 &&
2207 LHSR.first->High == CR.GE &&
2208 cast<ConstantInt>(C)->getValue() ==
2209 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2210 TrueBB = LHSR.first->BB;
2212 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2213 CurMF->insert(BBI, TrueBB);
2214 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2216 // Put SV in a virtual register to make it available from the new blocks.
2217 ExportFromCurrentBlock(SV);
2220 // Similar to the optimization above, if the Value being switched on is
2221 // known to be less than the Constant CR.LT, and the current Case Value
2222 // is CR.LT - 1, then we can branch directly to the target block for
2223 // the current Case Value, rather than emitting a RHS leaf node for it.
2224 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2225 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2226 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2227 FalseBB = RHSR.first->BB;
2229 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2230 CurMF->insert(BBI, FalseBB);
2231 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2233 // Put SV in a virtual register to make it available from the new blocks.
2234 ExportFromCurrentBlock(SV);
2237 // Create a CaseBlock record representing a conditional branch to
2238 // the LHS node if the value being switched on SV is less than C.
2239 // Otherwise, branch to LHS.
2240 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2242 if (CR.CaseBB == SwitchBB)
2243 visitSwitchCase(CB, SwitchBB);
2245 SwitchCases.push_back(CB);
2250 /// handleBitTestsSwitchCase - if current case range has few destination and
2251 /// range span less, than machine word bitwidth, encode case range into series
2252 /// of masks and emit bit tests with these masks.
2253 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2254 CaseRecVector& WorkList,
2256 MachineBasicBlock* Default,
2257 MachineBasicBlock *SwitchBB){
2258 EVT PTy = TLI.getPointerTy();
2259 unsigned IntPtrBits = PTy.getSizeInBits();
2261 Case& FrontCase = *CR.Range.first;
2262 Case& BackCase = *(CR.Range.second-1);
2264 // Get the MachineFunction which holds the current MBB. This is used when
2265 // inserting any additional MBBs necessary to represent the switch.
2266 MachineFunction *CurMF = FuncInfo.MF;
2268 // If target does not have legal shift left, do not emit bit tests at all.
2269 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2273 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2275 // Single case counts one, case range - two.
2276 numCmps += (I->Low == I->High ? 1 : 2);
2279 // Count unique destinations
2280 SmallSet<MachineBasicBlock*, 4> Dests;
2281 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2282 Dests.insert(I->BB);
2283 if (Dests.size() > 3)
2284 // Don't bother the code below, if there are too much unique destinations
2287 DEBUG(dbgs() << "Total number of unique destinations: "
2288 << Dests.size() << '\n'
2289 << "Total number of comparisons: " << numCmps << '\n');
2291 // Compute span of values.
2292 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2293 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2294 APInt cmpRange = maxValue - minValue;
2296 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2297 << "Low bound: " << minValue << '\n'
2298 << "High bound: " << maxValue << '\n');
2300 if (cmpRange.uge(IntPtrBits) ||
2301 (!(Dests.size() == 1 && numCmps >= 3) &&
2302 !(Dests.size() == 2 && numCmps >= 5) &&
2303 !(Dests.size() >= 3 && numCmps >= 6)))
2306 DEBUG(dbgs() << "Emitting bit tests\n");
2307 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2309 // Optimize the case where all the case values fit in a
2310 // word without having to subtract minValue. In this case,
2311 // we can optimize away the subtraction.
2312 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2313 cmpRange = maxValue;
2315 lowBound = minValue;
2318 CaseBitsVector CasesBits;
2319 unsigned i, count = 0;
2321 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2322 MachineBasicBlock* Dest = I->BB;
2323 for (i = 0; i < count; ++i)
2324 if (Dest == CasesBits[i].BB)
2328 assert((count < 3) && "Too much destinations to test!");
2329 CasesBits.push_back(CaseBits(0, Dest, 0));
2333 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2334 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2336 uint64_t lo = (lowValue - lowBound).getZExtValue();
2337 uint64_t hi = (highValue - lowBound).getZExtValue();
2339 for (uint64_t j = lo; j <= hi; j++) {
2340 CasesBits[i].Mask |= 1ULL << j;
2341 CasesBits[i].Bits++;
2345 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2349 // Figure out which block is immediately after the current one.
2350 MachineFunction::iterator BBI = CR.CaseBB;
2353 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2355 DEBUG(dbgs() << "Cases:\n");
2356 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2357 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2358 << ", Bits: " << CasesBits[i].Bits
2359 << ", BB: " << CasesBits[i].BB << '\n');
2361 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2362 CurMF->insert(BBI, CaseBB);
2363 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2367 // Put SV in a virtual register to make it available from the new blocks.
2368 ExportFromCurrentBlock(SV);
2371 BitTestBlock BTB(lowBound, cmpRange, SV,
2372 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2373 CR.CaseBB, Default, BTC);
2375 if (CR.CaseBB == SwitchBB)
2376 visitBitTestHeader(BTB, SwitchBB);
2378 BitTestCases.push_back(BTB);
2383 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2384 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2385 const SwitchInst& SI) {
2388 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2389 // Start with "simple" cases
2390 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2391 BasicBlock *SuccBB = SI.getSuccessor(i);
2392 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2394 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0;
2396 Cases.push_back(Case(SI.getSuccessorValue(i),
2397 SI.getSuccessorValue(i),
2398 SMBB, ExtraWeight));
2400 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2402 // Merge case into clusters
2403 if (Cases.size() >= 2)
2404 // Must recompute end() each iteration because it may be
2405 // invalidated by erase if we hold on to it
2406 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2407 J != Cases.end(); ) {
2408 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2409 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2410 MachineBasicBlock* nextBB = J->BB;
2411 MachineBasicBlock* currentBB = I->BB;
2413 // If the two neighboring cases go to the same destination, merge them
2414 // into a single case.
2415 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2419 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) {
2420 uint32_t CurWeight = currentBB->getBasicBlock() ?
2421 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16;
2422 uint32_t NextWeight = nextBB->getBasicBlock() ?
2423 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16;
2425 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(),
2426 CurWeight + NextWeight);
2433 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2434 if (I->Low != I->High)
2435 // A range counts double, since it requires two compares.
2442 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2443 MachineBasicBlock *Last) {
2445 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2446 if (JTCases[i].first.HeaderBB == First)
2447 JTCases[i].first.HeaderBB = Last;
2449 // Update BitTestCases.
2450 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2451 if (BitTestCases[i].Parent == First)
2452 BitTestCases[i].Parent = Last;
2455 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2456 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2458 // Figure out which block is immediately after the current one.
2459 MachineBasicBlock *NextBlock = 0;
2460 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2462 // If there is only the default destination, branch to it if it is not the
2463 // next basic block. Otherwise, just fall through.
2464 if (SI.getNumCases() == 1) {
2465 // Update machine-CFG edges.
2467 // If this is not a fall-through branch, emit the branch.
2468 SwitchMBB->addSuccessor(Default);
2469 if (Default != NextBlock)
2470 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2471 MVT::Other, getControlRoot(),
2472 DAG.getBasicBlock(Default)));
2477 // If there are any non-default case statements, create a vector of Cases
2478 // representing each one, and sort the vector so that we can efficiently
2479 // create a binary search tree from them.
2481 size_t numCmps = Clusterify(Cases, SI);
2482 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2483 << ". Total compares: " << numCmps << '\n');
2486 // Get the Value to be switched on and default basic blocks, which will be
2487 // inserted into CaseBlock records, representing basic blocks in the binary
2489 const Value *SV = SI.getCondition();
2491 // Push the initial CaseRec onto the worklist
2492 CaseRecVector WorkList;
2493 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2494 CaseRange(Cases.begin(),Cases.end())));
2496 while (!WorkList.empty()) {
2497 // Grab a record representing a case range to process off the worklist
2498 CaseRec CR = WorkList.back();
2499 WorkList.pop_back();
2501 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2504 // If the range has few cases (two or less) emit a series of specific
2506 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2509 // If the switch has more than 5 blocks, and at least 40% dense, and the
2510 // target supports indirect branches, then emit a jump table rather than
2511 // lowering the switch to a binary tree of conditional branches.
2512 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2515 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2516 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2517 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2521 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2522 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2524 // Update machine-CFG edges with unique successors.
2525 SmallVector<BasicBlock*, 32> succs;
2526 succs.reserve(I.getNumSuccessors());
2527 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2528 succs.push_back(I.getSuccessor(i));
2529 array_pod_sort(succs.begin(), succs.end());
2530 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2531 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2532 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2533 addSuccessorWithWeight(IndirectBrMBB, Succ);
2536 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2537 MVT::Other, getControlRoot(),
2538 getValue(I.getAddress())));
2541 void SelectionDAGBuilder::visitFSub(const User &I) {
2542 // -0.0 - X --> fneg
2543 Type *Ty = I.getType();
2544 if (isa<Constant>(I.getOperand(0)) &&
2545 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2546 SDValue Op2 = getValue(I.getOperand(1));
2547 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2548 Op2.getValueType(), Op2));
2552 visitBinary(I, ISD::FSUB);
2555 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2556 SDValue Op1 = getValue(I.getOperand(0));
2557 SDValue Op2 = getValue(I.getOperand(1));
2558 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2559 Op1.getValueType(), Op1, Op2));
2562 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2563 SDValue Op1 = getValue(I.getOperand(0));
2564 SDValue Op2 = getValue(I.getOperand(1));
2566 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2568 // Coerce the shift amount to the right type if we can.
2569 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2570 unsigned ShiftSize = ShiftTy.getSizeInBits();
2571 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2572 DebugLoc DL = getCurDebugLoc();
2574 // If the operand is smaller than the shift count type, promote it.
2575 if (ShiftSize > Op2Size)
2576 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2578 // If the operand is larger than the shift count type but the shift
2579 // count type has enough bits to represent any shift value, truncate
2580 // it now. This is a common case and it exposes the truncate to
2581 // optimization early.
2582 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2583 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2584 // Otherwise we'll need to temporarily settle for some other convenient
2585 // type. Type legalization will make adjustments once the shiftee is split.
2587 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2590 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2591 Op1.getValueType(), Op1, Op2));
2594 void SelectionDAGBuilder::visitSDiv(const User &I) {
2595 SDValue Op1 = getValue(I.getOperand(0));
2596 SDValue Op2 = getValue(I.getOperand(1));
2598 // Turn exact SDivs into multiplications.
2599 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2601 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2602 !isa<ConstantSDNode>(Op1) &&
2603 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2604 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2606 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2610 void SelectionDAGBuilder::visitICmp(const User &I) {
2611 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2612 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2613 predicate = IC->getPredicate();
2614 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2615 predicate = ICmpInst::Predicate(IC->getPredicate());
2616 SDValue Op1 = getValue(I.getOperand(0));
2617 SDValue Op2 = getValue(I.getOperand(1));
2618 ISD::CondCode Opcode = getICmpCondCode(predicate);
2620 EVT DestVT = TLI.getValueType(I.getType());
2621 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2624 void SelectionDAGBuilder::visitFCmp(const User &I) {
2625 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2626 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2627 predicate = FC->getPredicate();
2628 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2629 predicate = FCmpInst::Predicate(FC->getPredicate());
2630 SDValue Op1 = getValue(I.getOperand(0));
2631 SDValue Op2 = getValue(I.getOperand(1));
2632 ISD::CondCode Condition = getFCmpCondCode(predicate);
2633 if (TM.Options.NoNaNsFPMath)
2634 Condition = getFCmpCodeWithoutNaN(Condition);
2635 EVT DestVT = TLI.getValueType(I.getType());
2636 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2639 void SelectionDAGBuilder::visitSelect(const User &I) {
2640 SmallVector<EVT, 4> ValueVTs;
2641 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2642 unsigned NumValues = ValueVTs.size();
2643 if (NumValues == 0) return;
2645 SmallVector<SDValue, 4> Values(NumValues);
2646 SDValue Cond = getValue(I.getOperand(0));
2647 SDValue TrueVal = getValue(I.getOperand(1));
2648 SDValue FalseVal = getValue(I.getOperand(2));
2649 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2650 ISD::VSELECT : ISD::SELECT;
2652 for (unsigned i = 0; i != NumValues; ++i)
2653 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2654 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2656 SDValue(TrueVal.getNode(),
2657 TrueVal.getResNo() + i),
2658 SDValue(FalseVal.getNode(),
2659 FalseVal.getResNo() + i));
2661 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2662 DAG.getVTList(&ValueVTs[0], NumValues),
2663 &Values[0], NumValues));
2666 void SelectionDAGBuilder::visitTrunc(const User &I) {
2667 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2668 SDValue N = getValue(I.getOperand(0));
2669 EVT DestVT = TLI.getValueType(I.getType());
2670 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2673 void SelectionDAGBuilder::visitZExt(const User &I) {
2674 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2675 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2676 SDValue N = getValue(I.getOperand(0));
2677 EVT DestVT = TLI.getValueType(I.getType());
2678 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2681 void SelectionDAGBuilder::visitSExt(const User &I) {
2682 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2683 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2684 SDValue N = getValue(I.getOperand(0));
2685 EVT DestVT = TLI.getValueType(I.getType());
2686 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2689 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2690 // FPTrunc is never a no-op cast, no need to check
2691 SDValue N = getValue(I.getOperand(0));
2692 EVT DestVT = TLI.getValueType(I.getType());
2693 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2694 DestVT, N, DAG.getIntPtrConstant(0)));
2697 void SelectionDAGBuilder::visitFPExt(const User &I){
2698 // FPExt is never a no-op cast, no need to check
2699 SDValue N = getValue(I.getOperand(0));
2700 EVT DestVT = TLI.getValueType(I.getType());
2701 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2704 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2705 // FPToUI is never a no-op cast, no need to check
2706 SDValue N = getValue(I.getOperand(0));
2707 EVT DestVT = TLI.getValueType(I.getType());
2708 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2711 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2712 // FPToSI is never a no-op cast, no need to check
2713 SDValue N = getValue(I.getOperand(0));
2714 EVT DestVT = TLI.getValueType(I.getType());
2715 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2718 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2719 // UIToFP is never a no-op cast, no need to check
2720 SDValue N = getValue(I.getOperand(0));
2721 EVT DestVT = TLI.getValueType(I.getType());
2722 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2725 void SelectionDAGBuilder::visitSIToFP(const User &I){
2726 // SIToFP is never a no-op cast, no need to check
2727 SDValue N = getValue(I.getOperand(0));
2728 EVT DestVT = TLI.getValueType(I.getType());
2729 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2732 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2733 // What to do depends on the size of the integer and the size of the pointer.
2734 // We can either truncate, zero extend, or no-op, accordingly.
2735 SDValue N = getValue(I.getOperand(0));
2736 EVT DestVT = TLI.getValueType(I.getType());
2737 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2740 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2741 // What to do depends on the size of the integer and the size of the pointer.
2742 // We can either truncate, zero extend, or no-op, accordingly.
2743 SDValue N = getValue(I.getOperand(0));
2744 EVT DestVT = TLI.getValueType(I.getType());
2745 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2748 void SelectionDAGBuilder::visitBitCast(const User &I) {
2749 SDValue N = getValue(I.getOperand(0));
2750 EVT DestVT = TLI.getValueType(I.getType());
2752 // BitCast assures us that source and destination are the same size so this is
2753 // either a BITCAST or a no-op.
2754 if (DestVT != N.getValueType())
2755 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2756 DestVT, N)); // convert types.
2758 setValue(&I, N); // noop cast.
2761 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2762 SDValue InVec = getValue(I.getOperand(0));
2763 SDValue InVal = getValue(I.getOperand(1));
2764 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2766 getValue(I.getOperand(2)));
2767 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2768 TLI.getValueType(I.getType()),
2769 InVec, InVal, InIdx));
2772 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2773 SDValue InVec = getValue(I.getOperand(0));
2774 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2776 getValue(I.getOperand(1)));
2777 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2778 TLI.getValueType(I.getType()), InVec, InIdx));
2781 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2782 // from SIndx and increasing to the element length (undefs are allowed).
2783 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2784 unsigned MaskNumElts = Mask.size();
2785 for (unsigned i = 0; i != MaskNumElts; ++i)
2786 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2791 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2792 SmallVector<int, 8> Mask;
2793 SDValue Src1 = getValue(I.getOperand(0));
2794 SDValue Src2 = getValue(I.getOperand(1));
2796 // Convert the ConstantVector mask operand into an array of ints, with -1
2797 // representing undef values.
2798 SmallVector<Constant*, 8> MaskElts;
2799 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2800 unsigned MaskNumElts = MaskElts.size();
2801 for (unsigned i = 0; i != MaskNumElts; ++i) {
2802 if (isa<UndefValue>(MaskElts[i]))
2805 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2808 EVT VT = TLI.getValueType(I.getType());
2809 EVT SrcVT = Src1.getValueType();
2810 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2812 if (SrcNumElts == MaskNumElts) {
2813 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2818 // Normalize the shuffle vector since mask and vector length don't match.
2819 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2820 // Mask is longer than the source vectors and is a multiple of the source
2821 // vectors. We can use concatenate vector to make the mask and vectors
2823 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2824 // The shuffle is concatenating two vectors together.
2825 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2830 // Pad both vectors with undefs to make them the same length as the mask.
2831 unsigned NumConcat = MaskNumElts / SrcNumElts;
2832 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2833 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2834 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2836 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2837 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2841 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2842 getCurDebugLoc(), VT,
2843 &MOps1[0], NumConcat);
2844 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2845 getCurDebugLoc(), VT,
2846 &MOps2[0], NumConcat);
2848 // Readjust mask for new input vector length.
2849 SmallVector<int, 8> MappedOps;
2850 for (unsigned i = 0; i != MaskNumElts; ++i) {
2852 if (Idx < (int)SrcNumElts)
2853 MappedOps.push_back(Idx);
2855 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2858 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2863 if (SrcNumElts > MaskNumElts) {
2864 // Analyze the access pattern of the vector to see if we can extract
2865 // two subvectors and do the shuffle. The analysis is done by calculating
2866 // the range of elements the mask access on both vectors.
2867 int MinRange[2] = { static_cast<int>(SrcNumElts+1),
2868 static_cast<int>(SrcNumElts+1)};
2869 int MaxRange[2] = {-1, -1};
2871 for (unsigned i = 0; i != MaskNumElts; ++i) {
2877 if (Idx >= (int)SrcNumElts) {
2881 if (Idx > MaxRange[Input])
2882 MaxRange[Input] = Idx;
2883 if (Idx < MinRange[Input])
2884 MinRange[Input] = Idx;
2887 // Check if the access is smaller than the vector size and can we find
2888 // a reasonable extract index.
2889 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2891 int StartIdx[2]; // StartIdx to extract from
2892 for (int Input=0; Input < 2; ++Input) {
2893 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2894 RangeUse[Input] = 0; // Unused
2895 StartIdx[Input] = 0;
2896 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2897 // Fits within range but we should see if we can find a good
2898 // start index that is a multiple of the mask length.
2899 if (MaxRange[Input] < (int)MaskNumElts) {
2900 RangeUse[Input] = 1; // Extract from beginning of the vector
2901 StartIdx[Input] = 0;
2903 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2904 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2905 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2906 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2911 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2912 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2915 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2916 // Extract appropriate subvector and generate a vector shuffle
2917 for (int Input=0; Input < 2; ++Input) {
2918 SDValue &Src = Input == 0 ? Src1 : Src2;
2919 if (RangeUse[Input] == 0)
2920 Src = DAG.getUNDEF(VT);
2922 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2923 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2926 // Calculate new mask.
2927 SmallVector<int, 8> MappedOps;
2928 for (unsigned i = 0; i != MaskNumElts; ++i) {
2931 MappedOps.push_back(Idx);
2932 else if (Idx < (int)SrcNumElts)
2933 MappedOps.push_back(Idx - StartIdx[0]);
2935 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2938 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2944 // We can't use either concat vectors or extract subvectors so fall back to
2945 // replacing the shuffle with extract and build vector.
2946 // to insert and build vector.
2947 EVT EltVT = VT.getVectorElementType();
2948 EVT PtrVT = TLI.getPointerTy();
2949 SmallVector<SDValue,8> Ops;
2950 for (unsigned i = 0; i != MaskNumElts; ++i) {
2952 Ops.push_back(DAG.getUNDEF(EltVT));
2957 if (Idx < (int)SrcNumElts)
2958 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2959 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2961 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2963 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2969 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2970 VT, &Ops[0], Ops.size()));
2973 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2974 const Value *Op0 = I.getOperand(0);
2975 const Value *Op1 = I.getOperand(1);
2976 Type *AggTy = I.getType();
2977 Type *ValTy = Op1->getType();
2978 bool IntoUndef = isa<UndefValue>(Op0);
2979 bool FromUndef = isa<UndefValue>(Op1);
2981 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2983 SmallVector<EVT, 4> AggValueVTs;
2984 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2985 SmallVector<EVT, 4> ValValueVTs;
2986 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2988 unsigned NumAggValues = AggValueVTs.size();
2989 unsigned NumValValues = ValValueVTs.size();
2990 SmallVector<SDValue, 4> Values(NumAggValues);
2992 SDValue Agg = getValue(Op0);
2994 // Copy the beginning value(s) from the original aggregate.
2995 for (; i != LinearIndex; ++i)
2996 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2997 SDValue(Agg.getNode(), Agg.getResNo() + i);
2998 // Copy values from the inserted value(s).
3000 SDValue Val = getValue(Op1);
3001 for (; i != LinearIndex + NumValValues; ++i)
3002 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3003 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3005 // Copy remaining value(s) from the original aggregate.
3006 for (; i != NumAggValues; ++i)
3007 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3008 SDValue(Agg.getNode(), Agg.getResNo() + i);
3010 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3011 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3012 &Values[0], NumAggValues));
3015 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3016 const Value *Op0 = I.getOperand(0);
3017 Type *AggTy = Op0->getType();
3018 Type *ValTy = I.getType();
3019 bool OutOfUndef = isa<UndefValue>(Op0);
3021 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3023 SmallVector<EVT, 4> ValValueVTs;
3024 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3026 unsigned NumValValues = ValValueVTs.size();
3028 // Ignore a extractvalue that produces an empty object
3029 if (!NumValValues) {
3030 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3034 SmallVector<SDValue, 4> Values(NumValValues);
3036 SDValue Agg = getValue(Op0);
3037 // Copy out the selected value(s).
3038 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3039 Values[i - LinearIndex] =
3041 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3042 SDValue(Agg.getNode(), Agg.getResNo() + i);
3044 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3045 DAG.getVTList(&ValValueVTs[0], NumValValues),
3046 &Values[0], NumValValues));
3049 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3050 SDValue N = getValue(I.getOperand(0));
3051 Type *Ty = I.getOperand(0)->getType();
3053 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3055 const Value *Idx = *OI;
3056 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3057 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3060 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3061 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3062 DAG.getIntPtrConstant(Offset));
3065 Ty = StTy->getElementType(Field);
3067 Ty = cast<SequentialType>(Ty)->getElementType();
3069 // If this is a constant subscript, handle it quickly.
3070 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3071 if (CI->isZero()) continue;
3073 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3075 EVT PTy = TLI.getPointerTy();
3076 unsigned PtrBits = PTy.getSizeInBits();
3078 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3080 DAG.getConstant(Offs, MVT::i64));
3082 OffsVal = DAG.getIntPtrConstant(Offs);
3084 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3089 // N = N + Idx * ElementSize;
3090 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3091 TD->getTypeAllocSize(Ty));
3092 SDValue IdxN = getValue(Idx);
3094 // If the index is smaller or larger than intptr_t, truncate or extend
3096 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3098 // If this is a multiply by a power of two, turn it into a shl
3099 // immediately. This is a very common case.
3100 if (ElementSize != 1) {
3101 if (ElementSize.isPowerOf2()) {
3102 unsigned Amt = ElementSize.logBase2();
3103 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3104 N.getValueType(), IdxN,
3105 DAG.getConstant(Amt, IdxN.getValueType()));
3107 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3108 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3109 N.getValueType(), IdxN, Scale);
3113 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3114 N.getValueType(), N, IdxN);
3121 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3122 // If this is a fixed sized alloca in the entry block of the function,
3123 // allocate it statically on the stack.
3124 if (FuncInfo.StaticAllocaMap.count(&I))
3125 return; // getValue will auto-populate this.
3127 Type *Ty = I.getAllocatedType();
3128 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3130 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3133 SDValue AllocSize = getValue(I.getArraySize());
3135 EVT IntPtr = TLI.getPointerTy();
3136 if (AllocSize.getValueType() != IntPtr)
3137 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3139 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3141 DAG.getConstant(TySize, IntPtr));
3143 // Handle alignment. If the requested alignment is less than or equal to
3144 // the stack alignment, ignore it. If the size is greater than or equal to
3145 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3146 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3147 if (Align <= StackAlign)
3150 // Round the size of the allocation up to the stack alignment size
3151 // by add SA-1 to the size.
3152 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3153 AllocSize.getValueType(), AllocSize,
3154 DAG.getIntPtrConstant(StackAlign-1));
3156 // Mask out the low bits for alignment purposes.
3157 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3158 AllocSize.getValueType(), AllocSize,
3159 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3161 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3162 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3163 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3166 DAG.setRoot(DSA.getValue(1));
3168 // Inform the Frame Information that we have just allocated a variable-sized
3170 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3173 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3175 return visitAtomicLoad(I);
3177 const Value *SV = I.getOperand(0);
3178 SDValue Ptr = getValue(SV);
3180 Type *Ty = I.getType();
3182 bool isVolatile = I.isVolatile();
3183 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3184 bool isInvariant = I.getMetadata("invariant.load") != 0;
3185 unsigned Alignment = I.getAlignment();
3186 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3188 SmallVector<EVT, 4> ValueVTs;
3189 SmallVector<uint64_t, 4> Offsets;
3190 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3191 unsigned NumValues = ValueVTs.size();
3196 bool ConstantMemory = false;
3197 if (I.isVolatile() || NumValues > MaxParallelChains)
3198 // Serialize volatile loads with other side effects.
3200 else if (AA->pointsToConstantMemory(
3201 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3202 // Do not serialize (non-volatile) loads of constant memory with anything.
3203 Root = DAG.getEntryNode();
3204 ConstantMemory = true;
3206 // Do not serialize non-volatile loads against each other.
3207 Root = DAG.getRoot();
3210 SmallVector<SDValue, 4> Values(NumValues);
3211 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3213 EVT PtrVT = Ptr.getValueType();
3214 unsigned ChainI = 0;
3215 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3216 // Serializing loads here may result in excessive register pressure, and
3217 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3218 // could recover a bit by hoisting nodes upward in the chain by recognizing
3219 // they are side-effect free or do not alias. The optimizer should really
3220 // avoid this case by converting large object/array copies to llvm.memcpy
3221 // (MaxParallelChains should always remain as failsafe).
3222 if (ChainI == MaxParallelChains) {
3223 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3224 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3225 MVT::Other, &Chains[0], ChainI);
3229 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3231 DAG.getConstant(Offsets[i], PtrVT));
3232 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3233 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3234 isNonTemporal, isInvariant, Alignment, TBAAInfo);
3237 Chains[ChainI] = L.getValue(1);
3240 if (!ConstantMemory) {
3241 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3242 MVT::Other, &Chains[0], ChainI);
3246 PendingLoads.push_back(Chain);
3249 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3250 DAG.getVTList(&ValueVTs[0], NumValues),
3251 &Values[0], NumValues));
3254 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3256 return visitAtomicStore(I);
3258 const Value *SrcV = I.getOperand(0);
3259 const Value *PtrV = I.getOperand(1);
3261 SmallVector<EVT, 4> ValueVTs;
3262 SmallVector<uint64_t, 4> Offsets;
3263 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3264 unsigned NumValues = ValueVTs.size();
3268 // Get the lowered operands. Note that we do this after
3269 // checking if NumResults is zero, because with zero results
3270 // the operands won't have values in the map.
3271 SDValue Src = getValue(SrcV);
3272 SDValue Ptr = getValue(PtrV);
3274 SDValue Root = getRoot();
3275 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3277 EVT PtrVT = Ptr.getValueType();
3278 bool isVolatile = I.isVolatile();
3279 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3280 unsigned Alignment = I.getAlignment();
3281 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3283 unsigned ChainI = 0;
3284 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3285 // See visitLoad comments.
3286 if (ChainI == MaxParallelChains) {
3287 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3288 MVT::Other, &Chains[0], ChainI);
3292 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3293 DAG.getConstant(Offsets[i], PtrVT));
3294 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3295 SDValue(Src.getNode(), Src.getResNo() + i),
3296 Add, MachinePointerInfo(PtrV, Offsets[i]),
3297 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3298 Chains[ChainI] = St;
3301 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3302 MVT::Other, &Chains[0], ChainI);
3304 AssignOrderingToNode(StoreNode.getNode());
3305 DAG.setRoot(StoreNode);
3308 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3309 SynchronizationScope Scope,
3310 bool Before, DebugLoc dl,
3312 const TargetLowering &TLI) {
3313 // Fence, if necessary
3315 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3317 else if (Order == Acquire || Order == Monotonic)
3320 if (Order == AcquireRelease)
3322 else if (Order == Release || Order == Monotonic)
3327 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3328 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3329 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3332 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3333 DebugLoc dl = getCurDebugLoc();
3334 AtomicOrdering Order = I.getOrdering();
3335 SynchronizationScope Scope = I.getSynchScope();
3337 SDValue InChain = getRoot();
3339 if (TLI.getInsertFencesForAtomic())
3340 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3344 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3345 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3347 getValue(I.getPointerOperand()),
3348 getValue(I.getCompareOperand()),
3349 getValue(I.getNewValOperand()),
3350 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3351 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3354 SDValue OutChain = L.getValue(1);
3356 if (TLI.getInsertFencesForAtomic())
3357 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3361 DAG.setRoot(OutChain);
3364 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3365 DebugLoc dl = getCurDebugLoc();
3367 switch (I.getOperation()) {
3368 default: llvm_unreachable("Unknown atomicrmw operation"); return;
3369 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3370 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3371 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3372 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3373 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3374 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3375 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3376 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3377 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3378 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3379 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3381 AtomicOrdering Order = I.getOrdering();
3382 SynchronizationScope Scope = I.getSynchScope();
3384 SDValue InChain = getRoot();
3386 if (TLI.getInsertFencesForAtomic())
3387 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3391 DAG.getAtomic(NT, dl,
3392 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3394 getValue(I.getPointerOperand()),
3395 getValue(I.getValOperand()),
3396 I.getPointerOperand(), 0 /* Alignment */,
3397 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3400 SDValue OutChain = L.getValue(1);
3402 if (TLI.getInsertFencesForAtomic())
3403 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3407 DAG.setRoot(OutChain);
3410 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3411 DebugLoc dl = getCurDebugLoc();
3414 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3415 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3416 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3419 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3420 DebugLoc dl = getCurDebugLoc();
3421 AtomicOrdering Order = I.getOrdering();
3422 SynchronizationScope Scope = I.getSynchScope();
3424 SDValue InChain = getRoot();
3426 EVT VT = EVT::getEVT(I.getType());
3428 if (I.getAlignment() * 8 < VT.getSizeInBits())
3429 report_fatal_error("Cannot generate unaligned atomic load");
3432 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3433 getValue(I.getPointerOperand()),
3434 I.getPointerOperand(), I.getAlignment(),
3435 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3438 SDValue OutChain = L.getValue(1);
3440 if (TLI.getInsertFencesForAtomic())
3441 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3445 DAG.setRoot(OutChain);
3448 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3449 DebugLoc dl = getCurDebugLoc();
3451 AtomicOrdering Order = I.getOrdering();
3452 SynchronizationScope Scope = I.getSynchScope();
3454 SDValue InChain = getRoot();
3456 EVT VT = EVT::getEVT(I.getValueOperand()->getType());
3458 if (I.getAlignment() * 8 < VT.getSizeInBits())
3459 report_fatal_error("Cannot generate unaligned atomic store");
3461 if (TLI.getInsertFencesForAtomic())
3462 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3466 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3468 getValue(I.getPointerOperand()),
3469 getValue(I.getValueOperand()),
3470 I.getPointerOperand(), I.getAlignment(),
3471 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3474 if (TLI.getInsertFencesForAtomic())
3475 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3478 DAG.setRoot(OutChain);
3481 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3483 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3484 unsigned Intrinsic) {
3485 bool HasChain = !I.doesNotAccessMemory();
3486 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3488 // Build the operand list.
3489 SmallVector<SDValue, 8> Ops;
3490 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3492 // We don't need to serialize loads against other loads.
3493 Ops.push_back(DAG.getRoot());
3495 Ops.push_back(getRoot());
3499 // Info is set by getTgtMemInstrinsic
3500 TargetLowering::IntrinsicInfo Info;
3501 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3503 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3504 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3505 Info.opc == ISD::INTRINSIC_W_CHAIN)
3506 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3508 // Add all operands of the call to the operand list.
3509 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3510 SDValue Op = getValue(I.getArgOperand(i));
3511 assert(TLI.isTypeLegal(Op.getValueType()) &&
3512 "Intrinsic uses a non-legal type?");
3516 SmallVector<EVT, 4> ValueVTs;
3517 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3519 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3520 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3521 "Intrinsic uses a non-legal type?");
3526 ValueVTs.push_back(MVT::Other);
3528 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3532 if (IsTgtIntrinsic) {
3533 // This is target intrinsic that touches memory
3534 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3535 VTs, &Ops[0], Ops.size(),
3537 MachinePointerInfo(Info.ptrVal, Info.offset),
3538 Info.align, Info.vol,
3539 Info.readMem, Info.writeMem);
3540 } else if (!HasChain) {
3541 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3542 VTs, &Ops[0], Ops.size());
3543 } else if (!I.getType()->isVoidTy()) {
3544 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3545 VTs, &Ops[0], Ops.size());
3547 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3548 VTs, &Ops[0], Ops.size());
3552 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3554 PendingLoads.push_back(Chain);
3559 if (!I.getType()->isVoidTy()) {
3560 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3561 EVT VT = TLI.getValueType(PTy);
3562 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3565 setValue(&I, Result);
3569 /// GetSignificand - Get the significand and build it into a floating-point
3570 /// number with exponent of 1:
3572 /// Op = (Op & 0x007fffff) | 0x3f800000;
3574 /// where Op is the hexidecimal representation of floating point value.
3576 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3577 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3578 DAG.getConstant(0x007fffff, MVT::i32));
3579 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3580 DAG.getConstant(0x3f800000, MVT::i32));
3581 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3584 /// GetExponent - Get the exponent:
3586 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3588 /// where Op is the hexidecimal representation of floating point value.
3590 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3592 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3593 DAG.getConstant(0x7f800000, MVT::i32));
3594 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3595 DAG.getConstant(23, TLI.getPointerTy()));
3596 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3597 DAG.getConstant(127, MVT::i32));
3598 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3601 /// getF32Constant - Get 32-bit floating point constant.
3603 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3604 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3607 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3609 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3610 SDValue Op1 = getValue(I.getArgOperand(0));
3611 SDValue Op2 = getValue(I.getArgOperand(1));
3613 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3614 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3618 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3619 /// limited-precision mode.
3621 SelectionDAGBuilder::visitExp(const CallInst &I) {
3623 DebugLoc dl = getCurDebugLoc();
3625 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3626 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3627 SDValue Op = getValue(I.getArgOperand(0));
3629 // Put the exponent in the right bit position for later addition to the
3632 // #define LOG2OFe 1.4426950f
3633 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3634 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3635 getF32Constant(DAG, 0x3fb8aa3b));
3636 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3638 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3639 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3640 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3642 // IntegerPartOfX <<= 23;
3643 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3644 DAG.getConstant(23, TLI.getPointerTy()));
3646 if (LimitFloatPrecision <= 6) {
3647 // For floating-point precision of 6:
3649 // TwoToFractionalPartOfX =
3651 // (0.735607626f + 0.252464424f * x) * x;
3653 // error 0.0144103317, which is 6 bits
3654 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3655 getF32Constant(DAG, 0x3e814304));
3656 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3657 getF32Constant(DAG, 0x3f3c50c8));
3658 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3659 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3660 getF32Constant(DAG, 0x3f7f5e7e));
3661 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3663 // Add the exponent into the result in integer domain.
3664 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3665 TwoToFracPartOfX, IntegerPartOfX);
3667 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3668 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3669 // For floating-point precision of 12:
3671 // TwoToFractionalPartOfX =
3674 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3676 // 0.000107046256 error, which is 13 to 14 bits
3677 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3678 getF32Constant(DAG, 0x3da235e3));
3679 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3680 getF32Constant(DAG, 0x3e65b8f3));
3681 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3682 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3683 getF32Constant(DAG, 0x3f324b07));
3684 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3685 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3686 getF32Constant(DAG, 0x3f7ff8fd));
3687 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3689 // Add the exponent into the result in integer domain.
3690 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3691 TwoToFracPartOfX, IntegerPartOfX);
3693 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3694 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3695 // For floating-point precision of 18:
3697 // TwoToFractionalPartOfX =
3701 // (0.554906021e-1f +
3702 // (0.961591928e-2f +
3703 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3705 // error 2.47208000*10^(-7), which is better than 18 bits
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3707 getF32Constant(DAG, 0x3924b03e));
3708 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3709 getF32Constant(DAG, 0x3ab24b87));
3710 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3711 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3712 getF32Constant(DAG, 0x3c1d8c17));
3713 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3714 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3715 getF32Constant(DAG, 0x3d634a1d));
3716 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3717 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3718 getF32Constant(DAG, 0x3e75fe14));
3719 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3720 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3721 getF32Constant(DAG, 0x3f317234));
3722 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3723 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3724 getF32Constant(DAG, 0x3f800000));
3725 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3728 // Add the exponent into the result in integer domain.
3729 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3730 TwoToFracPartOfX, IntegerPartOfX);
3732 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3735 // No special expansion.
3736 result = DAG.getNode(ISD::FEXP, dl,
3737 getValue(I.getArgOperand(0)).getValueType(),
3738 getValue(I.getArgOperand(0)));
3741 setValue(&I, result);
3744 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3745 /// limited-precision mode.
3747 SelectionDAGBuilder::visitLog(const CallInst &I) {
3749 DebugLoc dl = getCurDebugLoc();
3751 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3752 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3753 SDValue Op = getValue(I.getArgOperand(0));
3754 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3756 // Scale the exponent by log(2) [0.69314718f].
3757 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3758 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3759 getF32Constant(DAG, 0x3f317218));
3761 // Get the significand and build it into a floating-point number with
3763 SDValue X = GetSignificand(DAG, Op1, dl);
3765 if (LimitFloatPrecision <= 6) {
3766 // For floating-point precision of 6:
3770 // (1.4034025f - 0.23903021f * x) * x;
3772 // error 0.0034276066, which is better than 8 bits
3773 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3774 getF32Constant(DAG, 0xbe74c456));
3775 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3776 getF32Constant(DAG, 0x3fb3a2b1));
3777 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3778 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3779 getF32Constant(DAG, 0x3f949a29));
3781 result = DAG.getNode(ISD::FADD, dl,
3782 MVT::f32, LogOfExponent, LogOfMantissa);
3783 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3784 // For floating-point precision of 12:
3790 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3792 // error 0.000061011436, which is 14 bits
3793 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3794 getF32Constant(DAG, 0xbd67b6d6));
3795 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3796 getF32Constant(DAG, 0x3ee4f4b8));
3797 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3798 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3799 getF32Constant(DAG, 0x3fbc278b));
3800 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3801 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3802 getF32Constant(DAG, 0x40348e95));
3803 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3804 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3805 getF32Constant(DAG, 0x3fdef31a));
3807 result = DAG.getNode(ISD::FADD, dl,
3808 MVT::f32, LogOfExponent, LogOfMantissa);
3809 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3810 // For floating-point precision of 18:
3818 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3820 // error 0.0000023660568, which is better than 18 bits
3821 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3822 getF32Constant(DAG, 0xbc91e5ac));
3823 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3824 getF32Constant(DAG, 0x3e4350aa));
3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3826 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3827 getF32Constant(DAG, 0x3f60d3e3));
3828 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3829 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3830 getF32Constant(DAG, 0x4011cdf0));
3831 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3832 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3833 getF32Constant(DAG, 0x406cfd1c));
3834 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3835 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3836 getF32Constant(DAG, 0x408797cb));
3837 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3838 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3839 getF32Constant(DAG, 0x4006dcab));
3841 result = DAG.getNode(ISD::FADD, dl,
3842 MVT::f32, LogOfExponent, LogOfMantissa);
3845 // No special expansion.
3846 result = DAG.getNode(ISD::FLOG, dl,
3847 getValue(I.getArgOperand(0)).getValueType(),
3848 getValue(I.getArgOperand(0)));
3851 setValue(&I, result);
3854 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3855 /// limited-precision mode.
3857 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3859 DebugLoc dl = getCurDebugLoc();
3861 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3862 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3863 SDValue Op = getValue(I.getArgOperand(0));
3864 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3866 // Get the exponent.
3867 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3869 // Get the significand and build it into a floating-point number with
3871 SDValue X = GetSignificand(DAG, Op1, dl);
3873 // Different possible minimax approximations of significand in
3874 // floating-point for various degrees of accuracy over [1,2].
3875 if (LimitFloatPrecision <= 6) {
3876 // For floating-point precision of 6:
3878 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3880 // error 0.0049451742, which is more than 7 bits
3881 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3882 getF32Constant(DAG, 0xbeb08fe0));
3883 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3884 getF32Constant(DAG, 0x40019463));
3885 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3886 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3887 getF32Constant(DAG, 0x3fd6633d));
3889 result = DAG.getNode(ISD::FADD, dl,
3890 MVT::f32, LogOfExponent, Log2ofMantissa);
3891 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3892 // For floating-point precision of 12:
3898 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3900 // error 0.0000876136000, which is better than 13 bits
3901 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3902 getF32Constant(DAG, 0xbda7262e));
3903 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3904 getF32Constant(DAG, 0x3f25280b));
3905 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3906 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3907 getF32Constant(DAG, 0x4007b923));
3908 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3909 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3910 getF32Constant(DAG, 0x40823e2f));
3911 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3912 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3913 getF32Constant(DAG, 0x4020d29c));
3915 result = DAG.getNode(ISD::FADD, dl,
3916 MVT::f32, LogOfExponent, Log2ofMantissa);
3917 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3918 // For floating-point precision of 18:
3927 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3929 // error 0.0000018516, which is better than 18 bits
3930 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3931 getF32Constant(DAG, 0xbcd2769e));
3932 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3933 getF32Constant(DAG, 0x3e8ce0b9));
3934 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3935 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3936 getF32Constant(DAG, 0x3fa22ae7));
3937 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3938 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3939 getF32Constant(DAG, 0x40525723));
3940 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3941 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3942 getF32Constant(DAG, 0x40aaf200));
3943 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3944 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3945 getF32Constant(DAG, 0x40c39dad));
3946 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3947 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3948 getF32Constant(DAG, 0x4042902c));
3950 result = DAG.getNode(ISD::FADD, dl,
3951 MVT::f32, LogOfExponent, Log2ofMantissa);
3954 // No special expansion.
3955 result = DAG.getNode(ISD::FLOG2, dl,
3956 getValue(I.getArgOperand(0)).getValueType(),
3957 getValue(I.getArgOperand(0)));
3960 setValue(&I, result);
3963 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3964 /// limited-precision mode.
3966 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3968 DebugLoc dl = getCurDebugLoc();
3970 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3971 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3972 SDValue Op = getValue(I.getArgOperand(0));
3973 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3975 // Scale the exponent by log10(2) [0.30102999f].
3976 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3977 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3978 getF32Constant(DAG, 0x3e9a209a));
3980 // Get the significand and build it into a floating-point number with
3982 SDValue X = GetSignificand(DAG, Op1, dl);
3984 if (LimitFloatPrecision <= 6) {
3985 // For floating-point precision of 6:
3987 // Log10ofMantissa =
3989 // (0.60948995f - 0.10380950f * x) * x;
3991 // error 0.0014886165, which is 6 bits
3992 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3993 getF32Constant(DAG, 0xbdd49a13));
3994 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3995 getF32Constant(DAG, 0x3f1c0789));
3996 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3997 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3998 getF32Constant(DAG, 0x3f011300));
4000 result = DAG.getNode(ISD::FADD, dl,
4001 MVT::f32, LogOfExponent, Log10ofMantissa);
4002 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4003 // For floating-point precision of 12:
4005 // Log10ofMantissa =
4008 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4010 // error 0.00019228036, which is better than 12 bits
4011 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4012 getF32Constant(DAG, 0x3d431f31));
4013 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4014 getF32Constant(DAG, 0x3ea21fb2));
4015 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4016 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4017 getF32Constant(DAG, 0x3f6ae232));
4018 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4019 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4020 getF32Constant(DAG, 0x3f25f7c3));
4022 result = DAG.getNode(ISD::FADD, dl,
4023 MVT::f32, LogOfExponent, Log10ofMantissa);
4024 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4025 // For floating-point precision of 18:
4027 // Log10ofMantissa =
4032 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4034 // error 0.0000037995730, which is better than 18 bits
4035 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4036 getF32Constant(DAG, 0x3c5d51ce));
4037 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4038 getF32Constant(DAG, 0x3e00685a));
4039 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4040 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4041 getF32Constant(DAG, 0x3efb6798));
4042 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4043 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4044 getF32Constant(DAG, 0x3f88d192));
4045 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4046 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4047 getF32Constant(DAG, 0x3fc4316c));
4048 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4049 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4050 getF32Constant(DAG, 0x3f57ce70));
4052 result = DAG.getNode(ISD::FADD, dl,
4053 MVT::f32, LogOfExponent, Log10ofMantissa);
4056 // No special expansion.
4057 result = DAG.getNode(ISD::FLOG10, dl,
4058 getValue(I.getArgOperand(0)).getValueType(),
4059 getValue(I.getArgOperand(0)));
4062 setValue(&I, result);
4065 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4066 /// limited-precision mode.
4068 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4070 DebugLoc dl = getCurDebugLoc();
4072 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4073 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4074 SDValue Op = getValue(I.getArgOperand(0));
4076 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4078 // FractionalPartOfX = x - (float)IntegerPartOfX;
4079 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4080 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4082 // IntegerPartOfX <<= 23;
4083 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4084 DAG.getConstant(23, TLI.getPointerTy()));
4086 if (LimitFloatPrecision <= 6) {
4087 // For floating-point precision of 6:
4089 // TwoToFractionalPartOfX =
4091 // (0.735607626f + 0.252464424f * x) * x;
4093 // error 0.0144103317, which is 6 bits
4094 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4095 getF32Constant(DAG, 0x3e814304));
4096 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4097 getF32Constant(DAG, 0x3f3c50c8));
4098 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4099 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4100 getF32Constant(DAG, 0x3f7f5e7e));
4101 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4102 SDValue TwoToFractionalPartOfX =
4103 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4105 result = DAG.getNode(ISD::BITCAST, dl,
4106 MVT::f32, TwoToFractionalPartOfX);
4107 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4108 // For floating-point precision of 12:
4110 // TwoToFractionalPartOfX =
4113 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4115 // error 0.000107046256, which is 13 to 14 bits
4116 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4117 getF32Constant(DAG, 0x3da235e3));
4118 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4119 getF32Constant(DAG, 0x3e65b8f3));
4120 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4121 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4122 getF32Constant(DAG, 0x3f324b07));
4123 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4124 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4125 getF32Constant(DAG, 0x3f7ff8fd));
4126 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4127 SDValue TwoToFractionalPartOfX =
4128 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4130 result = DAG.getNode(ISD::BITCAST, dl,
4131 MVT::f32, TwoToFractionalPartOfX);
4132 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4133 // For floating-point precision of 18:
4135 // TwoToFractionalPartOfX =
4139 // (0.554906021e-1f +
4140 // (0.961591928e-2f +
4141 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4142 // error 2.47208000*10^(-7), which is better than 18 bits
4143 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4144 getF32Constant(DAG, 0x3924b03e));
4145 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4146 getF32Constant(DAG, 0x3ab24b87));
4147 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4148 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4149 getF32Constant(DAG, 0x3c1d8c17));
4150 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4151 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4152 getF32Constant(DAG, 0x3d634a1d));
4153 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4154 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4155 getF32Constant(DAG, 0x3e75fe14));
4156 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4157 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4158 getF32Constant(DAG, 0x3f317234));
4159 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4160 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4161 getF32Constant(DAG, 0x3f800000));
4162 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4163 SDValue TwoToFractionalPartOfX =
4164 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4166 result = DAG.getNode(ISD::BITCAST, dl,
4167 MVT::f32, TwoToFractionalPartOfX);
4170 // No special expansion.
4171 result = DAG.getNode(ISD::FEXP2, dl,
4172 getValue(I.getArgOperand(0)).getValueType(),
4173 getValue(I.getArgOperand(0)));
4176 setValue(&I, result);
4179 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4180 /// limited-precision mode with x == 10.0f.
4182 SelectionDAGBuilder::visitPow(const CallInst &I) {
4184 const Value *Val = I.getArgOperand(0);
4185 DebugLoc dl = getCurDebugLoc();
4186 bool IsExp10 = false;
4188 if (getValue(Val).getValueType() == MVT::f32 &&
4189 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4190 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4191 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4192 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4194 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4199 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4200 SDValue Op = getValue(I.getArgOperand(1));
4202 // Put the exponent in the right bit position for later addition to the
4205 // #define LOG2OF10 3.3219281f
4206 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4207 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4208 getF32Constant(DAG, 0x40549a78));
4209 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4211 // FractionalPartOfX = x - (float)IntegerPartOfX;
4212 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4213 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4215 // IntegerPartOfX <<= 23;
4216 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4217 DAG.getConstant(23, TLI.getPointerTy()));
4219 if (LimitFloatPrecision <= 6) {
4220 // For floating-point precision of 6:
4222 // twoToFractionalPartOfX =
4224 // (0.735607626f + 0.252464424f * x) * x;
4226 // error 0.0144103317, which is 6 bits
4227 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4228 getF32Constant(DAG, 0x3e814304));
4229 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4230 getF32Constant(DAG, 0x3f3c50c8));
4231 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4232 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4233 getF32Constant(DAG, 0x3f7f5e7e));
4234 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4235 SDValue TwoToFractionalPartOfX =
4236 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4238 result = DAG.getNode(ISD::BITCAST, dl,
4239 MVT::f32, TwoToFractionalPartOfX);
4240 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4241 // For floating-point precision of 12:
4243 // TwoToFractionalPartOfX =
4246 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4248 // error 0.000107046256, which is 13 to 14 bits
4249 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4250 getF32Constant(DAG, 0x3da235e3));
4251 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4252 getF32Constant(DAG, 0x3e65b8f3));
4253 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4254 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4255 getF32Constant(DAG, 0x3f324b07));
4256 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4257 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4258 getF32Constant(DAG, 0x3f7ff8fd));
4259 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4260 SDValue TwoToFractionalPartOfX =
4261 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4263 result = DAG.getNode(ISD::BITCAST, dl,
4264 MVT::f32, TwoToFractionalPartOfX);
4265 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4266 // For floating-point precision of 18:
4268 // TwoToFractionalPartOfX =
4272 // (0.554906021e-1f +
4273 // (0.961591928e-2f +
4274 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4275 // error 2.47208000*10^(-7), which is better than 18 bits
4276 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4277 getF32Constant(DAG, 0x3924b03e));
4278 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4279 getF32Constant(DAG, 0x3ab24b87));
4280 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4281 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4282 getF32Constant(DAG, 0x3c1d8c17));
4283 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4284 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4285 getF32Constant(DAG, 0x3d634a1d));
4286 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4287 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4288 getF32Constant(DAG, 0x3e75fe14));
4289 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4290 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4291 getF32Constant(DAG, 0x3f317234));
4292 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4293 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4294 getF32Constant(DAG, 0x3f800000));
4295 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4296 SDValue TwoToFractionalPartOfX =
4297 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4299 result = DAG.getNode(ISD::BITCAST, dl,
4300 MVT::f32, TwoToFractionalPartOfX);
4303 // No special expansion.
4304 result = DAG.getNode(ISD::FPOW, dl,
4305 getValue(I.getArgOperand(0)).getValueType(),
4306 getValue(I.getArgOperand(0)),
4307 getValue(I.getArgOperand(1)));
4310 setValue(&I, result);
4314 /// ExpandPowI - Expand a llvm.powi intrinsic.
4315 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4316 SelectionDAG &DAG) {
4317 // If RHS is a constant, we can expand this out to a multiplication tree,
4318 // otherwise we end up lowering to a call to __powidf2 (for example). When
4319 // optimizing for size, we only want to do this if the expansion would produce
4320 // a small number of multiplies, otherwise we do the full expansion.
4321 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4322 // Get the exponent as a positive value.
4323 unsigned Val = RHSC->getSExtValue();
4324 if ((int)Val < 0) Val = -Val;
4326 // powi(x, 0) -> 1.0
4328 return DAG.getConstantFP(1.0, LHS.getValueType());
4330 const Function *F = DAG.getMachineFunction().getFunction();
4331 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4332 // If optimizing for size, don't insert too many multiplies. This
4333 // inserts up to 5 multiplies.
4334 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4335 // We use the simple binary decomposition method to generate the multiply
4336 // sequence. There are more optimal ways to do this (for example,
4337 // powi(x,15) generates one more multiply than it should), but this has
4338 // the benefit of being both really simple and much better than a libcall.
4339 SDValue Res; // Logically starts equal to 1.0
4340 SDValue CurSquare = LHS;
4344 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4346 Res = CurSquare; // 1.0*CurSquare.
4349 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4350 CurSquare, CurSquare);
4354 // If the original was negative, invert the result, producing 1/(x*x*x).
4355 if (RHSC->getSExtValue() < 0)
4356 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4357 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4362 // Otherwise, expand to a libcall.
4363 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4366 // getTruncatedArgReg - Find underlying register used for an truncated
4368 static unsigned getTruncatedArgReg(const SDValue &N) {
4369 if (N.getOpcode() != ISD::TRUNCATE)
4372 const SDValue &Ext = N.getOperand(0);
4373 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4374 const SDValue &CFR = Ext.getOperand(0);
4375 if (CFR.getOpcode() == ISD::CopyFromReg)
4376 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4378 if (CFR.getOpcode() == ISD::TRUNCATE)
4379 return getTruncatedArgReg(CFR);
4384 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4385 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4386 /// At the end of instruction selection, they will be inserted to the entry BB.
4388 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4391 const Argument *Arg = dyn_cast<Argument>(V);
4395 MachineFunction &MF = DAG.getMachineFunction();
4396 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4397 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4399 // Ignore inlined function arguments here.
4400 DIVariable DV(Variable);
4401 if (DV.isInlinedFnArgument(MF.getFunction()))
4405 // Some arguments' frame index is recorded during argument lowering.
4406 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4408 Reg = TRI->getFrameRegister(MF);
4410 if (!Reg && N.getNode()) {
4411 if (N.getOpcode() == ISD::CopyFromReg)
4412 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4414 Reg = getTruncatedArgReg(N);
4415 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4416 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4417 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4424 // Check if ValueMap has reg number.
4425 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4426 if (VMI != FuncInfo.ValueMap.end())
4430 if (!Reg && N.getNode()) {
4431 // Check if frame index is available.
4432 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4433 if (FrameIndexSDNode *FINode =
4434 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4435 Reg = TRI->getFrameRegister(MF);
4436 Offset = FINode->getIndex();
4443 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4444 TII->get(TargetOpcode::DBG_VALUE))
4445 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4446 FuncInfo.ArgDbgValues.push_back(&*MIB);
4450 // VisualStudio defines setjmp as _setjmp
4451 #if defined(_MSC_VER) && defined(setjmp) && \
4452 !defined(setjmp_undefined_for_msvc)
4453 # pragma push_macro("setjmp")
4455 # define setjmp_undefined_for_msvc
4458 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4459 /// we want to emit this as a call to a named external function, return the name
4460 /// otherwise lower it and return null.
4462 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4463 DebugLoc dl = getCurDebugLoc();
4466 switch (Intrinsic) {
4468 // By default, turn this into a target intrinsic node.
4469 visitTargetIntrinsic(I, Intrinsic);
4471 case Intrinsic::vastart: visitVAStart(I); return 0;
4472 case Intrinsic::vaend: visitVAEnd(I); return 0;
4473 case Intrinsic::vacopy: visitVACopy(I); return 0;
4474 case Intrinsic::returnaddress:
4475 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4476 getValue(I.getArgOperand(0))));
4478 case Intrinsic::frameaddress:
4479 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4480 getValue(I.getArgOperand(0))));
4482 case Intrinsic::setjmp:
4483 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4484 case Intrinsic::longjmp:
4485 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4486 case Intrinsic::memcpy: {
4487 // Assert for address < 256 since we support only user defined address
4489 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4491 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4493 "Unknown address space");
4494 SDValue Op1 = getValue(I.getArgOperand(0));
4495 SDValue Op2 = getValue(I.getArgOperand(1));
4496 SDValue Op3 = getValue(I.getArgOperand(2));
4497 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4498 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4499 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4500 MachinePointerInfo(I.getArgOperand(0)),
4501 MachinePointerInfo(I.getArgOperand(1))));
4504 case Intrinsic::memset: {
4505 // Assert for address < 256 since we support only user defined address
4507 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4509 "Unknown address space");
4510 SDValue Op1 = getValue(I.getArgOperand(0));
4511 SDValue Op2 = getValue(I.getArgOperand(1));
4512 SDValue Op3 = getValue(I.getArgOperand(2));
4513 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4514 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4515 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4516 MachinePointerInfo(I.getArgOperand(0))));
4519 case Intrinsic::memmove: {
4520 // Assert for address < 256 since we support only user defined address
4522 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4524 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4526 "Unknown address space");
4527 SDValue Op1 = getValue(I.getArgOperand(0));
4528 SDValue Op2 = getValue(I.getArgOperand(1));
4529 SDValue Op3 = getValue(I.getArgOperand(2));
4530 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4531 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4532 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4533 MachinePointerInfo(I.getArgOperand(0)),
4534 MachinePointerInfo(I.getArgOperand(1))));
4537 case Intrinsic::dbg_declare: {
4538 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4539 MDNode *Variable = DI.getVariable();
4540 const Value *Address = DI.getAddress();
4541 if (!Address || !DIVariable(Variable).Verify())
4544 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4545 // but do not always have a corresponding SDNode built. The SDNodeOrder
4546 // absolute, but not relative, values are different depending on whether
4547 // debug info exists.
4550 // Check if address has undef value.
4551 if (isa<UndefValue>(Address) ||
4552 (Address->use_empty() && !isa<Argument>(Address))) {
4553 DEBUG(dbgs() << "Dropping debug info for " << DI);
4557 SDValue &N = NodeMap[Address];
4558 if (!N.getNode() && isa<Argument>(Address))
4559 // Check unused arguments map.
4560 N = UnusedArgNodeMap[Address];
4563 // Parameters are handled specially.
4565 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4566 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4567 Address = BCI->getOperand(0);
4568 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4570 if (isParameter && !AI) {
4571 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4573 // Byval parameter. We have a frame index at this point.
4574 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4575 0, dl, SDNodeOrder);
4577 // Address is an argument, so try to emit its dbg value using
4578 // virtual register info from the FuncInfo.ValueMap.
4579 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4583 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4584 0, dl, SDNodeOrder);
4586 // Can't do anything with other non-AI cases yet.
4587 DEBUG(dbgs() << "Dropping debug info for " << DI);
4590 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4592 // If Address is an argument then try to emit its dbg value using
4593 // virtual register info from the FuncInfo.ValueMap.
4594 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4595 // If variable is pinned by a alloca in dominating bb then
4596 // use StaticAllocaMap.
4597 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4598 if (AI->getParent() != DI.getParent()) {
4599 DenseMap<const AllocaInst*, int>::iterator SI =
4600 FuncInfo.StaticAllocaMap.find(AI);
4601 if (SI != FuncInfo.StaticAllocaMap.end()) {
4602 SDV = DAG.getDbgValue(Variable, SI->second,
4603 0, dl, SDNodeOrder);
4604 DAG.AddDbgValue(SDV, 0, false);
4609 DEBUG(dbgs() << "Dropping debug info for " << DI);
4614 case Intrinsic::dbg_value: {
4615 const DbgValueInst &DI = cast<DbgValueInst>(I);
4616 if (!DIVariable(DI.getVariable()).Verify())
4619 MDNode *Variable = DI.getVariable();
4620 uint64_t Offset = DI.getOffset();
4621 const Value *V = DI.getValue();
4625 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4626 // but do not always have a corresponding SDNode built. The SDNodeOrder
4627 // absolute, but not relative, values are different depending on whether
4628 // debug info exists.
4631 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4632 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4633 DAG.AddDbgValue(SDV, 0, false);
4635 // Do not use getValue() in here; we don't want to generate code at
4636 // this point if it hasn't been done yet.
4637 SDValue N = NodeMap[V];
4638 if (!N.getNode() && isa<Argument>(V))
4639 // Check unused arguments map.
4640 N = UnusedArgNodeMap[V];
4642 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4643 SDV = DAG.getDbgValue(Variable, N.getNode(),
4644 N.getResNo(), Offset, dl, SDNodeOrder);
4645 DAG.AddDbgValue(SDV, N.getNode(), false);
4647 } else if (!V->use_empty() ) {
4648 // Do not call getValue(V) yet, as we don't want to generate code.
4649 // Remember it for later.
4650 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4651 DanglingDebugInfoMap[V] = DDI;
4653 // We may expand this to cover more cases. One case where we have no
4654 // data available is an unreferenced parameter.
4655 DEBUG(dbgs() << "Dropping debug info for " << DI);
4659 // Build a debug info table entry.
4660 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4661 V = BCI->getOperand(0);
4662 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4663 // Don't handle byval struct arguments or VLAs, for example.
4666 DenseMap<const AllocaInst*, int>::iterator SI =
4667 FuncInfo.StaticAllocaMap.find(AI);
4668 if (SI == FuncInfo.StaticAllocaMap.end())
4670 int FI = SI->second;
4672 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4673 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4674 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4677 case Intrinsic::eh_exception: {
4678 // Insert the EXCEPTIONADDR instruction.
4679 assert(FuncInfo.MBB->isLandingPad() &&
4680 "Call to eh.exception not in landing pad!");
4681 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4683 Ops[0] = DAG.getRoot();
4684 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4686 DAG.setRoot(Op.getValue(1));
4690 case Intrinsic::eh_selector: {
4691 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4692 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4693 if (CallMBB->isLandingPad())
4694 AddCatchInfo(I, &MMI, CallMBB);
4697 FuncInfo.CatchInfoLost.insert(&I);
4699 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4700 unsigned Reg = TLI.getExceptionSelectorRegister();
4701 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4704 // Insert the EHSELECTION instruction.
4705 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4707 Ops[0] = getValue(I.getArgOperand(0));
4709 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4710 DAG.setRoot(Op.getValue(1));
4711 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4715 case Intrinsic::eh_typeid_for: {
4716 // Find the type id for the given typeinfo.
4717 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4718 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4719 Res = DAG.getConstant(TypeID, MVT::i32);
4724 case Intrinsic::eh_return_i32:
4725 case Intrinsic::eh_return_i64:
4726 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4727 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4730 getValue(I.getArgOperand(0)),
4731 getValue(I.getArgOperand(1))));
4733 case Intrinsic::eh_unwind_init:
4734 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4736 case Intrinsic::eh_dwarf_cfa: {
4737 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4738 TLI.getPointerTy());
4739 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4741 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4742 TLI.getPointerTy()),
4744 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4746 DAG.getConstant(0, TLI.getPointerTy()));
4747 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4751 case Intrinsic::eh_sjlj_callsite: {
4752 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4753 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4754 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4755 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4757 MMI.setCurrentCallSite(CI->getZExtValue());
4760 case Intrinsic::eh_sjlj_functioncontext: {
4761 // Get and store the index of the function context.
4762 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4764 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4765 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4766 MFI->setFunctionContextIndex(FI);
4769 case Intrinsic::eh_sjlj_setjmp: {
4772 Ops[1] = getValue(I.getArgOperand(0));
4773 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4774 DAG.getVTList(MVT::i32, MVT::Other),
4776 setValue(&I, Op.getValue(0));
4777 DAG.setRoot(Op.getValue(1));
4780 case Intrinsic::eh_sjlj_longjmp: {
4781 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4782 getRoot(), getValue(I.getArgOperand(0))));
4786 case Intrinsic::x86_mmx_pslli_w:
4787 case Intrinsic::x86_mmx_pslli_d:
4788 case Intrinsic::x86_mmx_pslli_q:
4789 case Intrinsic::x86_mmx_psrli_w:
4790 case Intrinsic::x86_mmx_psrli_d:
4791 case Intrinsic::x86_mmx_psrli_q:
4792 case Intrinsic::x86_mmx_psrai_w:
4793 case Intrinsic::x86_mmx_psrai_d: {
4794 SDValue ShAmt = getValue(I.getArgOperand(1));
4795 if (isa<ConstantSDNode>(ShAmt)) {
4796 visitTargetIntrinsic(I, Intrinsic);
4799 unsigned NewIntrinsic = 0;
4800 EVT ShAmtVT = MVT::v2i32;
4801 switch (Intrinsic) {
4802 case Intrinsic::x86_mmx_pslli_w:
4803 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4805 case Intrinsic::x86_mmx_pslli_d:
4806 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4808 case Intrinsic::x86_mmx_pslli_q:
4809 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4811 case Intrinsic::x86_mmx_psrli_w:
4812 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4814 case Intrinsic::x86_mmx_psrli_d:
4815 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4817 case Intrinsic::x86_mmx_psrli_q:
4818 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4820 case Intrinsic::x86_mmx_psrai_w:
4821 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4823 case Intrinsic::x86_mmx_psrai_d:
4824 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4826 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4829 // The vector shift intrinsics with scalars uses 32b shift amounts but
4830 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4832 // We must do this early because v2i32 is not a legal type.
4833 DebugLoc dl = getCurDebugLoc();
4836 ShOps[1] = DAG.getConstant(0, MVT::i32);
4837 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4838 EVT DestVT = TLI.getValueType(I.getType());
4839 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4840 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4841 DAG.getConstant(NewIntrinsic, MVT::i32),
4842 getValue(I.getArgOperand(0)), ShAmt);
4846 case Intrinsic::convertff:
4847 case Intrinsic::convertfsi:
4848 case Intrinsic::convertfui:
4849 case Intrinsic::convertsif:
4850 case Intrinsic::convertuif:
4851 case Intrinsic::convertss:
4852 case Intrinsic::convertsu:
4853 case Intrinsic::convertus:
4854 case Intrinsic::convertuu: {
4855 ISD::CvtCode Code = ISD::CVT_INVALID;
4856 switch (Intrinsic) {
4857 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4858 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4859 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4860 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4861 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4862 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4863 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4864 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4865 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4867 EVT DestVT = TLI.getValueType(I.getType());
4868 const Value *Op1 = I.getArgOperand(0);
4869 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4870 DAG.getValueType(DestVT),
4871 DAG.getValueType(getValue(Op1).getValueType()),
4872 getValue(I.getArgOperand(1)),
4873 getValue(I.getArgOperand(2)),
4878 case Intrinsic::sqrt:
4879 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4880 getValue(I.getArgOperand(0)).getValueType(),
4881 getValue(I.getArgOperand(0))));
4883 case Intrinsic::powi:
4884 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4885 getValue(I.getArgOperand(1)), DAG));
4887 case Intrinsic::sin:
4888 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4889 getValue(I.getArgOperand(0)).getValueType(),
4890 getValue(I.getArgOperand(0))));
4892 case Intrinsic::cos:
4893 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4894 getValue(I.getArgOperand(0)).getValueType(),
4895 getValue(I.getArgOperand(0))));
4897 case Intrinsic::log:
4900 case Intrinsic::log2:
4903 case Intrinsic::log10:
4906 case Intrinsic::exp:
4909 case Intrinsic::exp2:
4912 case Intrinsic::pow:
4915 case Intrinsic::fma:
4916 setValue(&I, DAG.getNode(ISD::FMA, dl,
4917 getValue(I.getArgOperand(0)).getValueType(),
4918 getValue(I.getArgOperand(0)),
4919 getValue(I.getArgOperand(1)),
4920 getValue(I.getArgOperand(2))));
4922 case Intrinsic::convert_to_fp16:
4923 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4924 MVT::i16, getValue(I.getArgOperand(0))));
4926 case Intrinsic::convert_from_fp16:
4927 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4928 MVT::f32, getValue(I.getArgOperand(0))));
4930 case Intrinsic::pcmarker: {
4931 SDValue Tmp = getValue(I.getArgOperand(0));
4932 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4935 case Intrinsic::readcyclecounter: {
4936 SDValue Op = getRoot();
4937 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4938 DAG.getVTList(MVT::i64, MVT::Other),
4941 DAG.setRoot(Res.getValue(1));
4944 case Intrinsic::bswap:
4945 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4946 getValue(I.getArgOperand(0)).getValueType(),
4947 getValue(I.getArgOperand(0))));
4949 case Intrinsic::cttz: {
4950 SDValue Arg = getValue(I.getArgOperand(0));
4951 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4952 EVT Ty = Arg.getValueType();
4953 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4957 case Intrinsic::ctlz: {
4958 SDValue Arg = getValue(I.getArgOperand(0));
4959 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4960 EVT Ty = Arg.getValueType();
4961 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4965 case Intrinsic::ctpop: {
4966 SDValue Arg = getValue(I.getArgOperand(0));
4967 EVT Ty = Arg.getValueType();
4968 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4971 case Intrinsic::stacksave: {
4972 SDValue Op = getRoot();
4973 Res = DAG.getNode(ISD::STACKSAVE, dl,
4974 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4976 DAG.setRoot(Res.getValue(1));
4979 case Intrinsic::stackrestore: {
4980 Res = getValue(I.getArgOperand(0));
4981 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4984 case Intrinsic::stackprotector: {
4985 // Emit code into the DAG to store the stack guard onto the stack.
4986 MachineFunction &MF = DAG.getMachineFunction();
4987 MachineFrameInfo *MFI = MF.getFrameInfo();
4988 EVT PtrTy = TLI.getPointerTy();
4990 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4991 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4993 int FI = FuncInfo.StaticAllocaMap[Slot];
4994 MFI->setStackProtectorIndex(FI);
4996 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4998 // Store the stack protector onto the stack.
4999 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
5000 MachinePointerInfo::getFixedStack(FI),
5006 case Intrinsic::objectsize: {
5007 // If we don't know by now, we're never going to know.
5008 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5010 assert(CI && "Non-constant type in __builtin_object_size?");
5012 SDValue Arg = getValue(I.getCalledValue());
5013 EVT Ty = Arg.getValueType();
5016 Res = DAG.getConstant(-1ULL, Ty);
5018 Res = DAG.getConstant(0, Ty);
5023 case Intrinsic::var_annotation:
5024 // Discard annotate attributes
5027 case Intrinsic::init_trampoline: {
5028 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5032 Ops[1] = getValue(I.getArgOperand(0));
5033 Ops[2] = getValue(I.getArgOperand(1));
5034 Ops[3] = getValue(I.getArgOperand(2));
5035 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5036 Ops[5] = DAG.getSrcValue(F);
5038 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5043 case Intrinsic::adjust_trampoline: {
5044 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5046 getValue(I.getArgOperand(0))));
5049 case Intrinsic::gcroot:
5051 const Value *Alloca = I.getArgOperand(0);
5052 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5054 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5055 GFI->addStackRoot(FI->getIndex(), TypeMap);
5058 case Intrinsic::gcread:
5059 case Intrinsic::gcwrite:
5060 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5062 case Intrinsic::flt_rounds:
5063 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5066 case Intrinsic::expect: {
5067 // Just replace __builtin_expect(exp, c) with EXP.
5068 setValue(&I, getValue(I.getArgOperand(0)));
5072 case Intrinsic::trap: {
5073 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5074 if (TrapFuncName.empty()) {
5075 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5078 TargetLowering::ArgListTy Args;
5079 std::pair<SDValue, SDValue> Result =
5080 TLI.LowerCallTo(getRoot(), I.getType(),
5081 false, false, false, false, 0, CallingConv::C,
5082 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
5083 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5084 Args, DAG, getCurDebugLoc());
5085 DAG.setRoot(Result.second);
5088 case Intrinsic::uadd_with_overflow:
5089 return implVisitAluOverflow(I, ISD::UADDO);
5090 case Intrinsic::sadd_with_overflow:
5091 return implVisitAluOverflow(I, ISD::SADDO);
5092 case Intrinsic::usub_with_overflow:
5093 return implVisitAluOverflow(I, ISD::USUBO);
5094 case Intrinsic::ssub_with_overflow:
5095 return implVisitAluOverflow(I, ISD::SSUBO);
5096 case Intrinsic::umul_with_overflow:
5097 return implVisitAluOverflow(I, ISD::UMULO);
5098 case Intrinsic::smul_with_overflow:
5099 return implVisitAluOverflow(I, ISD::SMULO);
5101 case Intrinsic::prefetch: {
5103 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5105 Ops[1] = getValue(I.getArgOperand(0));
5106 Ops[2] = getValue(I.getArgOperand(1));
5107 Ops[3] = getValue(I.getArgOperand(2));
5108 Ops[4] = getValue(I.getArgOperand(3));
5109 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5110 DAG.getVTList(MVT::Other),
5112 EVT::getIntegerVT(*Context, 8),
5113 MachinePointerInfo(I.getArgOperand(0)),
5115 false, /* volatile */
5117 rw==1)); /* write */
5121 case Intrinsic::invariant_start:
5122 case Intrinsic::lifetime_start:
5123 // Discard region information.
5124 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5126 case Intrinsic::invariant_end:
5127 case Intrinsic::lifetime_end:
5128 // Discard region information.
5133 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5135 MachineBasicBlock *LandingPad) {
5136 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5137 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5138 Type *RetTy = FTy->getReturnType();
5139 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5140 MCSymbol *BeginLabel = 0;
5142 TargetLowering::ArgListTy Args;
5143 TargetLowering::ArgListEntry Entry;
5144 Args.reserve(CS.arg_size());
5146 // Check whether the function can return without sret-demotion.
5147 SmallVector<ISD::OutputArg, 4> Outs;
5148 SmallVector<uint64_t, 4> Offsets;
5149 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5150 Outs, TLI, &Offsets);
5152 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5153 DAG.getMachineFunction(),
5154 FTy->isVarArg(), Outs,
5157 SDValue DemoteStackSlot;
5158 int DemoteStackIdx = -100;
5160 if (!CanLowerReturn) {
5161 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5162 FTy->getReturnType());
5163 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5164 FTy->getReturnType());
5165 MachineFunction &MF = DAG.getMachineFunction();
5166 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5167 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5169 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5170 Entry.Node = DemoteStackSlot;
5171 Entry.Ty = StackSlotPtrType;
5172 Entry.isSExt = false;
5173 Entry.isZExt = false;
5174 Entry.isInReg = false;
5175 Entry.isSRet = true;
5176 Entry.isNest = false;
5177 Entry.isByVal = false;
5178 Entry.Alignment = Align;
5179 Args.push_back(Entry);
5180 RetTy = Type::getVoidTy(FTy->getContext());
5183 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5185 const Value *V = *i;
5188 if (V->getType()->isEmptyTy())
5191 SDValue ArgNode = getValue(V);
5192 Entry.Node = ArgNode; Entry.Ty = V->getType();
5194 unsigned attrInd = i - CS.arg_begin() + 1;
5195 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5196 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5197 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5198 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5199 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5200 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5201 Entry.Alignment = CS.getParamAlignment(attrInd);
5202 Args.push_back(Entry);
5206 // Insert a label before the invoke call to mark the try range. This can be
5207 // used to detect deletion of the invoke via the MachineModuleInfo.
5208 BeginLabel = MMI.getContext().CreateTempSymbol();
5210 // For SjLj, keep track of which landing pads go with which invokes
5211 // so as to maintain the ordering of pads in the LSDA.
5212 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5213 if (CallSiteIndex) {
5214 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5215 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5217 // Now that the call site is handled, stop tracking it.
5218 MMI.setCurrentCallSite(0);
5221 // Both PendingLoads and PendingExports must be flushed here;
5222 // this call might not return.
5224 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5227 // Check if target-independent constraints permit a tail call here.
5228 // Target-dependent constraints are checked within TLI.LowerCallTo.
5230 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5233 // If there's a possibility that fast-isel has already selected some amount
5234 // of the current basic block, don't emit a tail call.
5235 if (isTailCall && TM.Options.EnableFastISel)
5238 std::pair<SDValue,SDValue> Result =
5239 TLI.LowerCallTo(getRoot(), RetTy,
5240 CS.paramHasAttr(0, Attribute::SExt),
5241 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5242 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5243 CS.getCallingConv(),
5245 !CS.getInstruction()->use_empty(),
5246 Callee, Args, DAG, getCurDebugLoc());
5247 assert((isTailCall || Result.second.getNode()) &&
5248 "Non-null chain expected with non-tail call!");
5249 assert((Result.second.getNode() || !Result.first.getNode()) &&
5250 "Null value expected with tail call!");
5251 if (Result.first.getNode()) {
5252 setValue(CS.getInstruction(), Result.first);
5253 } else if (!CanLowerReturn && Result.second.getNode()) {
5254 // The instruction result is the result of loading from the
5255 // hidden sret parameter.
5256 SmallVector<EVT, 1> PVTs;
5257 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5259 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5260 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5261 EVT PtrVT = PVTs[0];
5262 unsigned NumValues = Outs.size();
5263 SmallVector<SDValue, 4> Values(NumValues);
5264 SmallVector<SDValue, 4> Chains(NumValues);
5266 for (unsigned i = 0; i < NumValues; ++i) {
5267 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5269 DAG.getConstant(Offsets[i], PtrVT));
5270 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5272 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5273 false, false, false, 1);
5275 Chains[i] = L.getValue(1);
5278 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5279 MVT::Other, &Chains[0], NumValues);
5280 PendingLoads.push_back(Chain);
5282 // Collect the legal value parts into potentially illegal values
5283 // that correspond to the original function's return values.
5284 SmallVector<EVT, 4> RetTys;
5285 RetTy = FTy->getReturnType();
5286 ComputeValueVTs(TLI, RetTy, RetTys);
5287 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5288 SmallVector<SDValue, 4> ReturnValues;
5289 unsigned CurReg = 0;
5290 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5292 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5293 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5295 SDValue ReturnValue =
5296 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5297 RegisterVT, VT, AssertOp);
5298 ReturnValues.push_back(ReturnValue);
5302 setValue(CS.getInstruction(),
5303 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5304 DAG.getVTList(&RetTys[0], RetTys.size()),
5305 &ReturnValues[0], ReturnValues.size()));
5308 // Assign order to nodes here. If the call does not produce a result, it won't
5309 // be mapped to a SDNode and visit() will not assign it an order number.
5310 if (!Result.second.getNode()) {
5311 // As a special case, a null chain means that a tail call has been emitted and
5312 // the DAG root is already updated.
5315 AssignOrderingToNode(DAG.getRoot().getNode());
5317 DAG.setRoot(Result.second);
5319 AssignOrderingToNode(Result.second.getNode());
5323 // Insert a label at the end of the invoke call to mark the try range. This
5324 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5325 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5326 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5328 // Inform MachineModuleInfo of range.
5329 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5333 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5334 /// value is equal or not-equal to zero.
5335 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5336 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5338 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5339 if (IC->isEquality())
5340 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5341 if (C->isNullValue())
5343 // Unknown instruction.
5349 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5351 SelectionDAGBuilder &Builder) {
5353 // Check to see if this load can be trivially constant folded, e.g. if the
5354 // input is from a string literal.
5355 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5356 // Cast pointer to the type we really want to load.
5357 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5358 PointerType::getUnqual(LoadTy));
5360 if (const Constant *LoadCst =
5361 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5363 return Builder.getValue(LoadCst);
5366 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5367 // still constant memory, the input chain can be the entry node.
5369 bool ConstantMemory = false;
5371 // Do not serialize (non-volatile) loads of constant memory with anything.
5372 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5373 Root = Builder.DAG.getEntryNode();
5374 ConstantMemory = true;
5376 // Do not serialize non-volatile loads against each other.
5377 Root = Builder.DAG.getRoot();
5380 SDValue Ptr = Builder.getValue(PtrVal);
5381 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5382 Ptr, MachinePointerInfo(PtrVal),
5384 false /*nontemporal*/,
5385 false /*isinvariant*/, 1 /* align=1 */);
5387 if (!ConstantMemory)
5388 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5393 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5394 /// If so, return true and lower it, otherwise return false and it will be
5395 /// lowered like a normal call.
5396 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5397 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5398 if (I.getNumArgOperands() != 3)
5401 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5402 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5403 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5404 !I.getType()->isIntegerTy())
5407 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5409 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5410 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5411 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5412 bool ActuallyDoIt = true;
5415 switch (Size->getZExtValue()) {
5417 LoadVT = MVT::Other;
5419 ActuallyDoIt = false;
5423 LoadTy = Type::getInt16Ty(Size->getContext());
5427 LoadTy = Type::getInt32Ty(Size->getContext());
5431 LoadTy = Type::getInt64Ty(Size->getContext());
5435 LoadVT = MVT::v4i32;
5436 LoadTy = Type::getInt32Ty(Size->getContext());
5437 LoadTy = VectorType::get(LoadTy, 4);
5442 // This turns into unaligned loads. We only do this if the target natively
5443 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5444 // we'll only produce a small number of byte loads.
5446 // Require that we can find a legal MVT, and only do this if the target
5447 // supports unaligned loads of that type. Expanding into byte loads would
5449 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5450 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5451 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5452 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5453 ActuallyDoIt = false;
5457 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5458 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5460 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5462 EVT CallVT = TLI.getValueType(I.getType(), true);
5463 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5473 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5474 // Handle inline assembly differently.
5475 if (isa<InlineAsm>(I.getCalledValue())) {
5480 // See if any floating point values are being passed to this function. This is
5481 // used to emit an undefined reference to fltused on Windows.
5483 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5484 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5485 if (FT->isVarArg() &&
5486 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5487 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5488 Type* T = I.getArgOperand(i)->getType();
5489 for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
5491 if (!i->isFloatingPointTy()) continue;
5492 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5498 const char *RenameFn = 0;
5499 if (Function *F = I.getCalledFunction()) {
5500 if (F->isDeclaration()) {
5501 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5502 if (unsigned IID = II->getIntrinsicID(F)) {
5503 RenameFn = visitIntrinsicCall(I, IID);
5508 if (unsigned IID = F->getIntrinsicID()) {
5509 RenameFn = visitIntrinsicCall(I, IID);
5515 // Check for well-known libc/libm calls. If the function is internal, it
5516 // can't be a library call.
5517 if (!F->hasLocalLinkage() && F->hasName()) {
5518 StringRef Name = F->getName();
5519 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") ||
5520 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") ||
5521 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) {
5522 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5523 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5524 I.getType() == I.getArgOperand(0)->getType() &&
5525 I.getType() == I.getArgOperand(1)->getType()) {
5526 SDValue LHS = getValue(I.getArgOperand(0));
5527 SDValue RHS = getValue(I.getArgOperand(1));
5528 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5529 LHS.getValueType(), LHS, RHS));
5532 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") ||
5533 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") ||
5534 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) {
5535 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5536 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5537 I.getType() == I.getArgOperand(0)->getType()) {
5538 SDValue Tmp = getValue(I.getArgOperand(0));
5539 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5540 Tmp.getValueType(), Tmp));
5543 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") ||
5544 (LibInfo->has(LibFunc::sinf) && Name == "sinf") ||
5545 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) {
5546 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5547 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5548 I.getType() == I.getArgOperand(0)->getType() &&
5549 I.onlyReadsMemory()) {
5550 SDValue Tmp = getValue(I.getArgOperand(0));
5551 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5552 Tmp.getValueType(), Tmp));
5555 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") ||
5556 (LibInfo->has(LibFunc::cosf) && Name == "cosf") ||
5557 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) {
5558 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5559 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5560 I.getType() == I.getArgOperand(0)->getType() &&
5561 I.onlyReadsMemory()) {
5562 SDValue Tmp = getValue(I.getArgOperand(0));
5563 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5564 Tmp.getValueType(), Tmp));
5567 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") ||
5568 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") ||
5569 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) {
5570 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5571 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5572 I.getType() == I.getArgOperand(0)->getType() &&
5573 I.onlyReadsMemory()) {
5574 SDValue Tmp = getValue(I.getArgOperand(0));
5575 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5576 Tmp.getValueType(), Tmp));
5579 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") ||
5580 (LibInfo->has(LibFunc::floorf) && Name == "floorf") ||
5581 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) {
5582 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5583 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5584 I.getType() == I.getArgOperand(0)->getType()) {
5585 SDValue Tmp = getValue(I.getArgOperand(0));
5586 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(),
5587 Tmp.getValueType(), Tmp));
5590 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") ||
5591 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") ||
5592 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) {
5593 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5594 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5595 I.getType() == I.getArgOperand(0)->getType()) {
5596 SDValue Tmp = getValue(I.getArgOperand(0));
5597 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(),
5598 Tmp.getValueType(), Tmp));
5601 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") ||
5602 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") ||
5603 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) {
5604 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5605 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5606 I.getType() == I.getArgOperand(0)->getType()) {
5607 SDValue Tmp = getValue(I.getArgOperand(0));
5608 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(),
5609 Tmp.getValueType(), Tmp));
5612 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") ||
5613 (LibInfo->has(LibFunc::rintf) && Name == "rintf") ||
5614 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) {
5615 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5616 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5617 I.getType() == I.getArgOperand(0)->getType()) {
5618 SDValue Tmp = getValue(I.getArgOperand(0));
5619 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(),
5620 Tmp.getValueType(), Tmp));
5623 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") ||
5624 (LibInfo->has(LibFunc::truncf) && Name == "truncf") ||
5625 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) {
5626 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5627 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5628 I.getType() == I.getArgOperand(0)->getType()) {
5629 SDValue Tmp = getValue(I.getArgOperand(0));
5630 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(),
5631 Tmp.getValueType(), Tmp));
5634 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") ||
5635 (LibInfo->has(LibFunc::log2f) && Name == "log2f") ||
5636 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) {
5637 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5638 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5639 I.getType() == I.getArgOperand(0)->getType()) {
5640 SDValue Tmp = getValue(I.getArgOperand(0));
5641 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(),
5642 Tmp.getValueType(), Tmp));
5645 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") ||
5646 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") ||
5647 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) {
5648 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5649 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5650 I.getType() == I.getArgOperand(0)->getType()) {
5651 SDValue Tmp = getValue(I.getArgOperand(0));
5652 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(),
5653 Tmp.getValueType(), Tmp));
5656 } else if (Name == "memcmp") {
5657 if (visitMemCmpCall(I))
5665 Callee = getValue(I.getCalledValue());
5667 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5669 // Check if we can potentially perform a tail call. More detailed checking is
5670 // be done within LowerCallTo, after more information about the call is known.
5671 LowerCallTo(&I, Callee, I.isTailCall());
5676 /// AsmOperandInfo - This contains information for each constraint that we are
5678 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5680 /// CallOperand - If this is the result output operand or a clobber
5681 /// this is null, otherwise it is the incoming operand to the CallInst.
5682 /// This gets modified as the asm is processed.
5683 SDValue CallOperand;
5685 /// AssignedRegs - If this is a register or register class operand, this
5686 /// contains the set of register corresponding to the operand.
5687 RegsForValue AssignedRegs;
5689 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5690 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5693 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5694 /// busy in OutputRegs/InputRegs.
5695 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5696 std::set<unsigned> &OutputRegs,
5697 std::set<unsigned> &InputRegs,
5698 const TargetRegisterInfo &TRI) const {
5700 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5701 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5704 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5705 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5709 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5710 /// corresponds to. If there is no Value* for this operand, it returns
5712 EVT getCallOperandValEVT(LLVMContext &Context,
5713 const TargetLowering &TLI,
5714 const TargetData *TD) const {
5715 if (CallOperandVal == 0) return MVT::Other;
5717 if (isa<BasicBlock>(CallOperandVal))
5718 return TLI.getPointerTy();
5720 llvm::Type *OpTy = CallOperandVal->getType();
5722 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5723 // If this is an indirect operand, the operand is a pointer to the
5726 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5728 report_fatal_error("Indirect operand for inline asm not a pointer!");
5729 OpTy = PtrTy->getElementType();
5732 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5733 if (StructType *STy = dyn_cast<StructType>(OpTy))
5734 if (STy->getNumElements() == 1)
5735 OpTy = STy->getElementType(0);
5737 // If OpTy is not a single value, it may be a struct/union that we
5738 // can tile with integers.
5739 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5740 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5749 OpTy = IntegerType::get(Context, BitSize);
5754 return TLI.getValueType(OpTy, true);
5758 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5760 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5761 const TargetRegisterInfo &TRI) {
5762 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5764 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5765 for (; *Aliases; ++Aliases)
5766 Regs.insert(*Aliases);
5770 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5772 } // end anonymous namespace
5774 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5775 /// specified operand. We prefer to assign virtual registers, to allow the
5776 /// register allocator to handle the assignment process. However, if the asm
5777 /// uses features that we can't model on machineinstrs, we have SDISel do the
5778 /// allocation. This produces generally horrible, but correct, code.
5780 /// OpInfo describes the operand.
5781 /// Input and OutputRegs are the set of already allocated physical registers.
5783 static void GetRegistersForValue(SelectionDAG &DAG,
5784 const TargetLowering &TLI,
5786 SDISelAsmOperandInfo &OpInfo,
5787 std::set<unsigned> &OutputRegs,
5788 std::set<unsigned> &InputRegs) {
5789 LLVMContext &Context = *DAG.getContext();
5791 // Compute whether this value requires an input register, an output register,
5793 bool isOutReg = false;
5794 bool isInReg = false;
5795 switch (OpInfo.Type) {
5796 case InlineAsm::isOutput:
5799 // If there is an input constraint that matches this, we need to reserve
5800 // the input register so no other inputs allocate to it.
5801 isInReg = OpInfo.hasMatchingInput();
5803 case InlineAsm::isInput:
5807 case InlineAsm::isClobber:
5814 MachineFunction &MF = DAG.getMachineFunction();
5815 SmallVector<unsigned, 4> Regs;
5817 // If this is a constraint for a single physreg, or a constraint for a
5818 // register class, find it.
5819 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5820 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5821 OpInfo.ConstraintVT);
5823 unsigned NumRegs = 1;
5824 if (OpInfo.ConstraintVT != MVT::Other) {
5825 // If this is a FP input in an integer register (or visa versa) insert a bit
5826 // cast of the input value. More generally, handle any case where the input
5827 // value disagrees with the register class we plan to stick this in.
5828 if (OpInfo.Type == InlineAsm::isInput &&
5829 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5830 // Try to convert to the first EVT that the reg class contains. If the
5831 // types are identical size, use a bitcast to convert (e.g. two differing
5833 EVT RegVT = *PhysReg.second->vt_begin();
5834 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5835 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5836 RegVT, OpInfo.CallOperand);
5837 OpInfo.ConstraintVT = RegVT;
5838 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5839 // If the input is a FP value and we want it in FP registers, do a
5840 // bitcast to the corresponding integer type. This turns an f64 value
5841 // into i64, which can be passed with two i32 values on a 32-bit
5843 RegVT = EVT::getIntegerVT(Context,
5844 OpInfo.ConstraintVT.getSizeInBits());
5845 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5846 RegVT, OpInfo.CallOperand);
5847 OpInfo.ConstraintVT = RegVT;
5851 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5855 EVT ValueVT = OpInfo.ConstraintVT;
5857 // If this is a constraint for a specific physical register, like {r17},
5859 if (unsigned AssignedReg = PhysReg.first) {
5860 const TargetRegisterClass *RC = PhysReg.second;
5861 if (OpInfo.ConstraintVT == MVT::Other)
5862 ValueVT = *RC->vt_begin();
5864 // Get the actual register value type. This is important, because the user
5865 // may have asked for (e.g.) the AX register in i32 type. We need to
5866 // remember that AX is actually i16 to get the right extension.
5867 RegVT = *RC->vt_begin();
5869 // This is a explicit reference to a physical register.
5870 Regs.push_back(AssignedReg);
5872 // If this is an expanded reference, add the rest of the regs to Regs.
5874 TargetRegisterClass::iterator I = RC->begin();
5875 for (; *I != AssignedReg; ++I)
5876 assert(I != RC->end() && "Didn't find reg!");
5878 // Already added the first reg.
5880 for (; NumRegs; --NumRegs, ++I) {
5881 assert(I != RC->end() && "Ran out of registers to allocate!");
5886 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5887 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5888 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5892 // Otherwise, if this was a reference to an LLVM register class, create vregs
5893 // for this reference.
5894 if (const TargetRegisterClass *RC = PhysReg.second) {
5895 RegVT = *RC->vt_begin();
5896 if (OpInfo.ConstraintVT == MVT::Other)
5899 // Create the appropriate number of virtual registers.
5900 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5901 for (; NumRegs; --NumRegs)
5902 Regs.push_back(RegInfo.createVirtualRegister(RC));
5904 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5908 // Otherwise, we couldn't allocate enough registers for this.
5911 /// visitInlineAsm - Handle a call to an InlineAsm object.
5913 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5914 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5916 /// ConstraintOperands - Information about all of the constraints.
5917 SDISelAsmOperandInfoVector ConstraintOperands;
5919 std::set<unsigned> OutputRegs, InputRegs;
5921 TargetLowering::AsmOperandInfoVector
5922 TargetConstraints = TLI.ParseConstraints(CS);
5924 bool hasMemory = false;
5926 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5927 unsigned ResNo = 0; // ResNo - The result number of the next output.
5928 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5929 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5930 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5932 EVT OpVT = MVT::Other;
5934 // Compute the value type for each operand.
5935 switch (OpInfo.Type) {
5936 case InlineAsm::isOutput:
5937 // Indirect outputs just consume an argument.
5938 if (OpInfo.isIndirect) {
5939 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5943 // The return value of the call is this value. As such, there is no
5944 // corresponding argument.
5945 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5946 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5947 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5949 assert(ResNo == 0 && "Asm only has one result!");
5950 OpVT = TLI.getValueType(CS.getType());
5954 case InlineAsm::isInput:
5955 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5957 case InlineAsm::isClobber:
5962 // If this is an input or an indirect output, process the call argument.
5963 // BasicBlocks are labels, currently appearing only in asm's.
5964 if (OpInfo.CallOperandVal) {
5965 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5966 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5968 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5971 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5974 OpInfo.ConstraintVT = OpVT;
5976 // Indirect operand accesses access memory.
5977 if (OpInfo.isIndirect)
5980 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5981 TargetLowering::ConstraintType
5982 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5983 if (CType == TargetLowering::C_Memory) {
5991 SDValue Chain, Flag;
5993 // We won't need to flush pending loads if this asm doesn't touch
5994 // memory and is nonvolatile.
5995 if (hasMemory || IA->hasSideEffects())
5998 Chain = DAG.getRoot();
6000 // Second pass over the constraints: compute which constraint option to use
6001 // and assign registers to constraints that want a specific physreg.
6002 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6003 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6005 // If this is an output operand with a matching input operand, look up the
6006 // matching input. If their types mismatch, e.g. one is an integer, the
6007 // other is floating point, or their sizes are different, flag it as an
6009 if (OpInfo.hasMatchingInput()) {
6010 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6012 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6013 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6014 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6015 OpInfo.ConstraintVT);
6016 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6017 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6018 Input.ConstraintVT);
6019 if ((OpInfo.ConstraintVT.isInteger() !=
6020 Input.ConstraintVT.isInteger()) ||
6021 (MatchRC.second != InputRC.second)) {
6022 report_fatal_error("Unsupported asm: input constraint"
6023 " with a matching output constraint of"
6024 " incompatible type!");
6026 Input.ConstraintVT = OpInfo.ConstraintVT;
6030 // Compute the constraint code and ConstraintType to use.
6031 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6033 // If this is a memory input, and if the operand is not indirect, do what we
6034 // need to to provide an address for the memory input.
6035 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6036 !OpInfo.isIndirect) {
6037 assert((OpInfo.isMultipleAlternative ||
6038 (OpInfo.Type == InlineAsm::isInput)) &&
6039 "Can only indirectify direct input operands!");
6041 // Memory operands really want the address of the value. If we don't have
6042 // an indirect input, put it in the constpool if we can, otherwise spill
6043 // it to a stack slot.
6044 // TODO: This isn't quite right. We need to handle these according to
6045 // the addressing mode that the constraint wants. Also, this may take
6046 // an additional register for the computation and we don't want that
6049 // If the operand is a float, integer, or vector constant, spill to a
6050 // constant pool entry to get its address.
6051 const Value *OpVal = OpInfo.CallOperandVal;
6052 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6053 isa<ConstantVector>(OpVal)) {
6054 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6055 TLI.getPointerTy());
6057 // Otherwise, create a stack slot and emit a store to it before the
6059 Type *Ty = OpVal->getType();
6060 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
6061 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
6062 MachineFunction &MF = DAG.getMachineFunction();
6063 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6064 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6065 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6066 OpInfo.CallOperand, StackSlot,
6067 MachinePointerInfo::getFixedStack(SSFI),
6069 OpInfo.CallOperand = StackSlot;
6072 // There is no longer a Value* corresponding to this operand.
6073 OpInfo.CallOperandVal = 0;
6075 // It is now an indirect operand.
6076 OpInfo.isIndirect = true;
6079 // If this constraint is for a specific register, allocate it before
6081 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6082 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
6086 // Second pass - Loop over all of the operands, assigning virtual or physregs
6087 // to register class operands.
6088 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6089 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6091 // C_Register operands have already been allocated, Other/Memory don't need
6093 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6094 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
6098 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6099 std::vector<SDValue> AsmNodeOperands;
6100 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6101 AsmNodeOperands.push_back(
6102 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6103 TLI.getPointerTy()));
6105 // If we have a !srcloc metadata node associated with it, we want to attach
6106 // this to the ultimately generated inline asm machineinstr. To do this, we
6107 // pass in the third operand as this (potentially null) inline asm MDNode.
6108 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6109 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6111 // Remember the HasSideEffect and AlignStack bits as operand 3.
6112 unsigned ExtraInfo = 0;
6113 if (IA->hasSideEffects())
6114 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6115 if (IA->isAlignStack())
6116 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6117 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6118 TLI.getPointerTy()));
6120 // Loop over all of the inputs, copying the operand values into the
6121 // appropriate registers and processing the output regs.
6122 RegsForValue RetValRegs;
6124 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6125 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6127 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6128 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6130 switch (OpInfo.Type) {
6131 case InlineAsm::isOutput: {
6132 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6133 OpInfo.ConstraintType != TargetLowering::C_Register) {
6134 // Memory output, or 'other' output (e.g. 'X' constraint).
6135 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6137 // Add information to the INLINEASM node to know about this output.
6138 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6139 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6140 TLI.getPointerTy()));
6141 AsmNodeOperands.push_back(OpInfo.CallOperand);
6145 // Otherwise, this is a register or register class output.
6147 // Copy the output from the appropriate register. Find a register that
6149 if (OpInfo.AssignedRegs.Regs.empty())
6150 report_fatal_error("Couldn't allocate output reg for constraint '" +
6151 Twine(OpInfo.ConstraintCode) + "'!");
6153 // If this is an indirect operand, store through the pointer after the
6155 if (OpInfo.isIndirect) {
6156 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6157 OpInfo.CallOperandVal));
6159 // This is the result value of the call.
6160 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6161 // Concatenate this output onto the outputs list.
6162 RetValRegs.append(OpInfo.AssignedRegs);
6165 // Add information to the INLINEASM node to know that this register is
6167 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6168 InlineAsm::Kind_RegDefEarlyClobber :
6169 InlineAsm::Kind_RegDef,
6176 case InlineAsm::isInput: {
6177 SDValue InOperandVal = OpInfo.CallOperand;
6179 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6180 // If this is required to match an output register we have already set,
6181 // just use its register.
6182 unsigned OperandNo = OpInfo.getMatchedOperand();
6184 // Scan until we find the definition we already emitted of this operand.
6185 // When we find it, create a RegsForValue operand.
6186 unsigned CurOp = InlineAsm::Op_FirstOperand;
6187 for (; OperandNo; --OperandNo) {
6188 // Advance to the next operand.
6190 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6191 assert((InlineAsm::isRegDefKind(OpFlag) ||
6192 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6193 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6194 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6198 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6199 if (InlineAsm::isRegDefKind(OpFlag) ||
6200 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6201 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6202 if (OpInfo.isIndirect) {
6203 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6204 LLVMContext &Ctx = *DAG.getContext();
6205 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6206 " don't know how to handle tied "
6207 "indirect register inputs");
6210 RegsForValue MatchedRegs;
6211 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6212 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6213 MatchedRegs.RegVTs.push_back(RegVT);
6214 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6215 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6217 MatchedRegs.Regs.push_back
6218 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6220 // Use the produced MatchedRegs object to
6221 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6223 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6224 true, OpInfo.getMatchedOperand(),
6225 DAG, AsmNodeOperands);
6229 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6230 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6231 "Unexpected number of operands");
6232 // Add information to the INLINEASM node to know about this input.
6233 // See InlineAsm.h isUseOperandTiedToDef.
6234 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6235 OpInfo.getMatchedOperand());
6236 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6237 TLI.getPointerTy()));
6238 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6242 // Treat indirect 'X' constraint as memory.
6243 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6245 OpInfo.ConstraintType = TargetLowering::C_Memory;
6247 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6248 std::vector<SDValue> Ops;
6249 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6252 report_fatal_error("Invalid operand for inline asm constraint '" +
6253 Twine(OpInfo.ConstraintCode) + "'!");
6255 // Add information to the INLINEASM node to know about this input.
6256 unsigned ResOpType =
6257 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6258 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6259 TLI.getPointerTy()));
6260 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6264 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6265 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6266 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6267 "Memory operands expect pointer values");
6269 // Add information to the INLINEASM node to know about this input.
6270 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6271 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6272 TLI.getPointerTy()));
6273 AsmNodeOperands.push_back(InOperandVal);
6277 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6278 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6279 "Unknown constraint type!");
6280 assert(!OpInfo.isIndirect &&
6281 "Don't know how to handle indirect register inputs yet!");
6283 // Copy the input into the appropriate registers.
6284 if (OpInfo.AssignedRegs.Regs.empty())
6285 report_fatal_error("Couldn't allocate input reg for constraint '" +
6286 Twine(OpInfo.ConstraintCode) + "'!");
6288 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6291 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6292 DAG, AsmNodeOperands);
6295 case InlineAsm::isClobber: {
6296 // Add the clobbered value to the operand list, so that the register
6297 // allocator is aware that the physreg got clobbered.
6298 if (!OpInfo.AssignedRegs.Regs.empty())
6299 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6307 // Finish up input operands. Set the input chain and add the flag last.
6308 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6309 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6311 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6312 DAG.getVTList(MVT::Other, MVT::Glue),
6313 &AsmNodeOperands[0], AsmNodeOperands.size());
6314 Flag = Chain.getValue(1);
6316 // If this asm returns a register value, copy the result from that register
6317 // and set it as the value of the call.
6318 if (!RetValRegs.Regs.empty()) {
6319 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6322 // FIXME: Why don't we do this for inline asms with MRVs?
6323 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6324 EVT ResultType = TLI.getValueType(CS.getType());
6326 // If any of the results of the inline asm is a vector, it may have the
6327 // wrong width/num elts. This can happen for register classes that can
6328 // contain multiple different value types. The preg or vreg allocated may
6329 // not have the same VT as was expected. Convert it to the right type
6330 // with bit_convert.
6331 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6332 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6335 } else if (ResultType != Val.getValueType() &&
6336 ResultType.isInteger() && Val.getValueType().isInteger()) {
6337 // If a result value was tied to an input value, the computed result may
6338 // have a wider width than the expected result. Extract the relevant
6340 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6343 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6346 setValue(CS.getInstruction(), Val);
6347 // Don't need to use this as a chain in this case.
6348 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6352 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6354 // Process indirect outputs, first output all of the flagged copies out of
6356 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6357 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6358 const Value *Ptr = IndirectStoresToEmit[i].second;
6359 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6361 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6364 // Emit the non-flagged stores from the physregs.
6365 SmallVector<SDValue, 8> OutChains;
6366 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6367 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6368 StoresToEmit[i].first,
6369 getValue(StoresToEmit[i].second),
6370 MachinePointerInfo(StoresToEmit[i].second),
6372 OutChains.push_back(Val);
6375 if (!OutChains.empty())
6376 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6377 &OutChains[0], OutChains.size());
6382 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6383 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6384 MVT::Other, getRoot(),
6385 getValue(I.getArgOperand(0)),
6386 DAG.getSrcValue(I.getArgOperand(0))));
6389 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6390 const TargetData &TD = *TLI.getTargetData();
6391 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6392 getRoot(), getValue(I.getOperand(0)),
6393 DAG.getSrcValue(I.getOperand(0)),
6394 TD.getABITypeAlignment(I.getType()));
6396 DAG.setRoot(V.getValue(1));
6399 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6400 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6401 MVT::Other, getRoot(),
6402 getValue(I.getArgOperand(0)),
6403 DAG.getSrcValue(I.getArgOperand(0))));
6406 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6407 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6408 MVT::Other, getRoot(),
6409 getValue(I.getArgOperand(0)),
6410 getValue(I.getArgOperand(1)),
6411 DAG.getSrcValue(I.getArgOperand(0)),
6412 DAG.getSrcValue(I.getArgOperand(1))));
6415 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6416 /// implementation, which just calls LowerCall.
6417 /// FIXME: When all targets are
6418 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6419 std::pair<SDValue, SDValue>
6420 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6421 bool RetSExt, bool RetZExt, bool isVarArg,
6422 bool isInreg, unsigned NumFixedArgs,
6423 CallingConv::ID CallConv, bool isTailCall,
6424 bool isReturnValueUsed,
6426 ArgListTy &Args, SelectionDAG &DAG,
6427 DebugLoc dl) const {
6428 // Handle all of the outgoing arguments.
6429 SmallVector<ISD::OutputArg, 32> Outs;
6430 SmallVector<SDValue, 32> OutVals;
6431 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6432 SmallVector<EVT, 4> ValueVTs;
6433 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6434 for (unsigned Value = 0, NumValues = ValueVTs.size();
6435 Value != NumValues; ++Value) {
6436 EVT VT = ValueVTs[Value];
6437 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6438 SDValue Op = SDValue(Args[i].Node.getNode(),
6439 Args[i].Node.getResNo() + Value);
6440 ISD::ArgFlagsTy Flags;
6441 unsigned OriginalAlignment =
6442 getTargetData()->getABITypeAlignment(ArgTy);
6448 if (Args[i].isInReg)
6452 if (Args[i].isByVal) {
6454 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6455 Type *ElementTy = Ty->getElementType();
6456 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6457 // For ByVal, alignment should come from FE. BE will guess if this
6458 // info is not there but there are cases it cannot get right.
6459 unsigned FrameAlign;
6460 if (Args[i].Alignment)
6461 FrameAlign = Args[i].Alignment;
6463 FrameAlign = getByValTypeAlignment(ElementTy);
6464 Flags.setByValAlign(FrameAlign);
6468 Flags.setOrigAlign(OriginalAlignment);
6470 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6471 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6472 SmallVector<SDValue, 4> Parts(NumParts);
6473 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6476 ExtendKind = ISD::SIGN_EXTEND;
6477 else if (Args[i].isZExt)
6478 ExtendKind = ISD::ZERO_EXTEND;
6480 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6481 PartVT, ExtendKind);
6483 for (unsigned j = 0; j != NumParts; ++j) {
6484 // if it isn't first piece, alignment must be 1
6485 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6487 if (NumParts > 1 && j == 0)
6488 MyFlags.Flags.setSplit();
6490 MyFlags.Flags.setOrigAlign(1);
6492 Outs.push_back(MyFlags);
6493 OutVals.push_back(Parts[j]);
6498 // Handle the incoming return values from the call.
6499 SmallVector<ISD::InputArg, 32> Ins;
6500 SmallVector<EVT, 4> RetTys;
6501 ComputeValueVTs(*this, RetTy, RetTys);
6502 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6504 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6505 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6506 for (unsigned i = 0; i != NumRegs; ++i) {
6507 ISD::InputArg MyFlags;
6508 MyFlags.VT = RegisterVT.getSimpleVT();
6509 MyFlags.Used = isReturnValueUsed;
6511 MyFlags.Flags.setSExt();
6513 MyFlags.Flags.setZExt();
6515 MyFlags.Flags.setInReg();
6516 Ins.push_back(MyFlags);
6520 SmallVector<SDValue, 4> InVals;
6521 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6522 Outs, OutVals, Ins, dl, DAG, InVals);
6524 // Verify that the target's LowerCall behaved as expected.
6525 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6526 "LowerCall didn't return a valid chain!");
6527 assert((!isTailCall || InVals.empty()) &&
6528 "LowerCall emitted a return value for a tail call!");
6529 assert((isTailCall || InVals.size() == Ins.size()) &&
6530 "LowerCall didn't emit the correct number of values!");
6532 // For a tail call, the return value is merely live-out and there aren't
6533 // any nodes in the DAG representing it. Return a special value to
6534 // indicate that a tail call has been emitted and no more Instructions
6535 // should be processed in the current block.
6538 return std::make_pair(SDValue(), SDValue());
6541 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6542 assert(InVals[i].getNode() &&
6543 "LowerCall emitted a null value!");
6544 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6545 "LowerCall emitted a value with the wrong type!");
6548 // Collect the legal value parts into potentially illegal values
6549 // that correspond to the original function's return values.
6550 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6552 AssertOp = ISD::AssertSext;
6554 AssertOp = ISD::AssertZext;
6555 SmallVector<SDValue, 4> ReturnValues;
6556 unsigned CurReg = 0;
6557 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6559 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6560 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6562 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6563 NumRegs, RegisterVT, VT,
6568 // For a function returning void, there is no return value. We can't create
6569 // such a node, so we just return a null return value in that case. In
6570 // that case, nothing will actually look at the value.
6571 if (ReturnValues.empty())
6572 return std::make_pair(SDValue(), Chain);
6574 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6575 DAG.getVTList(&RetTys[0], RetTys.size()),
6576 &ReturnValues[0], ReturnValues.size());
6577 return std::make_pair(Res, Chain);
6580 void TargetLowering::LowerOperationWrapper(SDNode *N,
6581 SmallVectorImpl<SDValue> &Results,
6582 SelectionDAG &DAG) const {
6583 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6585 Results.push_back(Res);
6588 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6589 llvm_unreachable("LowerOperation not implemented for this target!");
6594 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6595 SDValue Op = getNonRegisterValue(V);
6596 assert((Op.getOpcode() != ISD::CopyFromReg ||
6597 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6598 "Copy from a reg to the same reg!");
6599 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6601 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6602 SDValue Chain = DAG.getEntryNode();
6603 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6604 PendingExports.push_back(Chain);
6607 #include "llvm/CodeGen/SelectionDAGISel.h"
6609 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6610 /// entry block, return true. This includes arguments used by switches, since
6611 /// the switch may expand into multiple basic blocks.
6612 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6613 // With FastISel active, we may be splitting blocks, so force creation
6614 // of virtual registers for all non-dead arguments.
6616 return A->use_empty();
6618 const BasicBlock *Entry = A->getParent()->begin();
6619 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6621 const User *U = *UI;
6622 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6623 return false; // Use not in entry block.
6628 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6629 // If this is the entry block, emit arguments.
6630 const Function &F = *LLVMBB->getParent();
6631 SelectionDAG &DAG = SDB->DAG;
6632 DebugLoc dl = SDB->getCurDebugLoc();
6633 const TargetData *TD = TLI.getTargetData();
6634 SmallVector<ISD::InputArg, 16> Ins;
6636 // Check whether the function can return without sret-demotion.
6637 SmallVector<ISD::OutputArg, 4> Outs;
6638 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6641 if (!FuncInfo->CanLowerReturn) {
6642 // Put in an sret pointer parameter before all the other parameters.
6643 SmallVector<EVT, 1> ValueVTs;
6644 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6646 // NOTE: Assuming that a pointer will never break down to more than one VT
6648 ISD::ArgFlagsTy Flags;
6650 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6651 ISD::InputArg RetArg(Flags, RegisterVT, true);
6652 Ins.push_back(RetArg);
6655 // Set up the incoming argument description vector.
6657 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6658 I != E; ++I, ++Idx) {
6659 SmallVector<EVT, 4> ValueVTs;
6660 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6661 bool isArgValueUsed = !I->use_empty();
6662 for (unsigned Value = 0, NumValues = ValueVTs.size();
6663 Value != NumValues; ++Value) {
6664 EVT VT = ValueVTs[Value];
6665 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6666 ISD::ArgFlagsTy Flags;
6667 unsigned OriginalAlignment =
6668 TD->getABITypeAlignment(ArgTy);
6670 if (F.paramHasAttr(Idx, Attribute::ZExt))
6672 if (F.paramHasAttr(Idx, Attribute::SExt))
6674 if (F.paramHasAttr(Idx, Attribute::InReg))
6676 if (F.paramHasAttr(Idx, Attribute::StructRet))
6678 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6680 PointerType *Ty = cast<PointerType>(I->getType());
6681 Type *ElementTy = Ty->getElementType();
6682 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6683 // For ByVal, alignment should be passed from FE. BE will guess if
6684 // this info is not there but there are cases it cannot get right.
6685 unsigned FrameAlign;
6686 if (F.getParamAlignment(Idx))
6687 FrameAlign = F.getParamAlignment(Idx);
6689 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6690 Flags.setByValAlign(FrameAlign);
6692 if (F.paramHasAttr(Idx, Attribute::Nest))
6694 Flags.setOrigAlign(OriginalAlignment);
6696 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6697 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6698 for (unsigned i = 0; i != NumRegs; ++i) {
6699 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6700 if (NumRegs > 1 && i == 0)
6701 MyFlags.Flags.setSplit();
6702 // if it isn't first piece, alignment must be 1
6704 MyFlags.Flags.setOrigAlign(1);
6705 Ins.push_back(MyFlags);
6710 // Call the target to set up the argument values.
6711 SmallVector<SDValue, 8> InVals;
6712 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6716 // Verify that the target's LowerFormalArguments behaved as expected.
6717 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6718 "LowerFormalArguments didn't return a valid chain!");
6719 assert(InVals.size() == Ins.size() &&
6720 "LowerFormalArguments didn't emit the correct number of values!");
6722 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6723 assert(InVals[i].getNode() &&
6724 "LowerFormalArguments emitted a null value!");
6725 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6726 "LowerFormalArguments emitted a value with the wrong type!");
6730 // Update the DAG with the new chain value resulting from argument lowering.
6731 DAG.setRoot(NewRoot);
6733 // Set up the argument values.
6736 if (!FuncInfo->CanLowerReturn) {
6737 // Create a virtual register for the sret pointer, and put in a copy
6738 // from the sret argument into it.
6739 SmallVector<EVT, 1> ValueVTs;
6740 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6741 EVT VT = ValueVTs[0];
6742 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6743 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6744 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6745 RegVT, VT, AssertOp);
6747 MachineFunction& MF = SDB->DAG.getMachineFunction();
6748 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6749 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6750 FuncInfo->DemoteRegister = SRetReg;
6751 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6753 DAG.setRoot(NewRoot);
6755 // i indexes lowered arguments. Bump it past the hidden sret argument.
6756 // Idx indexes LLVM arguments. Don't touch it.
6760 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6762 SmallVector<SDValue, 4> ArgValues;
6763 SmallVector<EVT, 4> ValueVTs;
6764 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6765 unsigned NumValues = ValueVTs.size();
6767 // If this argument is unused then remember its value. It is used to generate
6768 // debugging information.
6769 if (I->use_empty() && NumValues)
6770 SDB->setUnusedArgValue(I, InVals[i]);
6772 for (unsigned Val = 0; Val != NumValues; ++Val) {
6773 EVT VT = ValueVTs[Val];
6774 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6775 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6777 if (!I->use_empty()) {
6778 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6779 if (F.paramHasAttr(Idx, Attribute::SExt))
6780 AssertOp = ISD::AssertSext;
6781 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6782 AssertOp = ISD::AssertZext;
6784 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6785 NumParts, PartVT, VT,
6792 // We don't need to do anything else for unused arguments.
6793 if (ArgValues.empty())
6796 // Note down frame index.
6797 if (FrameIndexSDNode *FI =
6798 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6799 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6801 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6802 SDB->getCurDebugLoc());
6804 SDB->setValue(I, Res);
6805 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6806 if (LoadSDNode *LNode =
6807 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6808 if (FrameIndexSDNode *FI =
6809 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6810 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6813 // If this argument is live outside of the entry block, insert a copy from
6814 // wherever we got it to the vreg that other BB's will reference it as.
6815 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6816 // If we can, though, try to skip creating an unnecessary vreg.
6817 // FIXME: This isn't very clean... it would be nice to make this more
6818 // general. It's also subtly incompatible with the hacks FastISel
6820 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6821 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6822 FuncInfo->ValueMap[I] = Reg;
6826 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6827 FuncInfo->InitializeRegForValue(I);
6828 SDB->CopyToExportRegsIfNeeded(I);
6832 assert(i == InVals.size() && "Argument register count mismatch!");
6834 // Finally, if the target has anything special to do, allow it to do so.
6835 // FIXME: this should insert code into the DAG!
6836 EmitFunctionEntryCode();
6839 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6840 /// ensure constants are generated when needed. Remember the virtual registers
6841 /// that need to be added to the Machine PHI nodes as input. We cannot just
6842 /// directly add them, because expansion might result in multiple MBB's for one
6843 /// BB. As such, the start of the BB might correspond to a different MBB than
6847 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6848 const TerminatorInst *TI = LLVMBB->getTerminator();
6850 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6852 // Check successor nodes' PHI nodes that expect a constant to be available
6854 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6855 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6856 if (!isa<PHINode>(SuccBB->begin())) continue;
6857 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6859 // If this terminator has multiple identical successors (common for
6860 // switches), only handle each succ once.
6861 if (!SuccsHandled.insert(SuccMBB)) continue;
6863 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6865 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6866 // nodes and Machine PHI nodes, but the incoming operands have not been
6868 for (BasicBlock::const_iterator I = SuccBB->begin();
6869 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6870 // Ignore dead phi's.
6871 if (PN->use_empty()) continue;
6874 if (PN->getType()->isEmptyTy())
6878 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6880 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6881 unsigned &RegOut = ConstantsOut[C];
6883 RegOut = FuncInfo.CreateRegs(C->getType());
6884 CopyValueToVirtualRegister(C, RegOut);
6888 DenseMap<const Value *, unsigned>::iterator I =
6889 FuncInfo.ValueMap.find(PHIOp);
6890 if (I != FuncInfo.ValueMap.end())
6893 assert(isa<AllocaInst>(PHIOp) &&
6894 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6895 "Didn't codegen value into a register!??");
6896 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6897 CopyValueToVirtualRegister(PHIOp, Reg);
6901 // Remember that this register needs to added to the machine PHI node as
6902 // the input for this MBB.
6903 SmallVector<EVT, 4> ValueVTs;
6904 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6905 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6906 EVT VT = ValueVTs[vti];
6907 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6908 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6909 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6910 Reg += NumRegisters;
6914 ConstantsOut.clear();