1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 // Trivial bitcast if the types are the same size and the destination
287 // vector type is legal.
288 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
289 TLI.isTypeLegal(ValueVT))
290 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
292 assert(ValueVT.getVectorElementType() == PartVT &&
293 ValueVT.getVectorNumElements() == 1 &&
294 "Only trivial scalar-to-vector conversions should get here!");
295 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
301 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
302 SDValue Val, SDValue *Parts, unsigned NumParts,
305 /// getCopyToParts - Create a series of nodes that contain the specified value
306 /// split into legal parts. If the parts contain more bits than Val, then, for
307 /// integers, ExtendKind can be used to specify how to generate the extra bits.
308 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
309 SDValue Val, SDValue *Parts, unsigned NumParts,
311 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
312 EVT ValueVT = Val.getValueType();
314 // Handle the vector case separately.
315 if (ValueVT.isVector())
316 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
318 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
319 unsigned PartBits = PartVT.getSizeInBits();
320 unsigned OrigNumParts = NumParts;
321 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
326 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
327 if (PartVT == ValueVT) {
328 assert(NumParts == 1 && "No-op copy with multiple parts!");
333 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
334 // If the parts cover more bits than the value has, promote the value.
335 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
336 assert(NumParts == 1 && "Do not know what to promote to!");
337 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
339 assert(PartVT.isInteger() && ValueVT.isInteger() &&
340 "Unknown mismatch!");
341 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
342 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
344 } else if (PartBits == ValueVT.getSizeInBits()) {
345 // Different types of the same size.
346 assert(NumParts == 1 && PartVT != ValueVT);
347 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
348 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
349 // If the parts cover less bits than value has, truncate the value.
350 assert(PartVT.isInteger() && ValueVT.isInteger() &&
351 "Unknown mismatch!");
352 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
353 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
356 // The value may have changed - recompute ValueVT.
357 ValueVT = Val.getValueType();
358 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
359 "Failed to tile the value with PartVT!");
362 assert(PartVT == ValueVT && "Type conversion failed!");
367 // Expand the value into multiple parts.
368 if (NumParts & (NumParts - 1)) {
369 // The number of parts is not a power of 2. Split off and copy the tail.
370 assert(PartVT.isInteger() && ValueVT.isInteger() &&
371 "Do not know what to expand to!");
372 unsigned RoundParts = 1 << Log2_32(NumParts);
373 unsigned RoundBits = RoundParts * PartBits;
374 unsigned OddParts = NumParts - RoundParts;
375 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
376 DAG.getIntPtrConstant(RoundBits));
377 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
379 if (TLI.isBigEndian())
380 // The odd parts were reversed by getCopyToParts - unreverse them.
381 std::reverse(Parts + RoundParts, Parts + NumParts);
383 NumParts = RoundParts;
384 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
385 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
388 // The number of parts is a power of 2. Repeatedly bisect the value using
390 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
391 EVT::getIntegerVT(*DAG.getContext(),
392 ValueVT.getSizeInBits()),
395 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
396 for (unsigned i = 0; i < NumParts; i += StepSize) {
397 unsigned ThisBits = StepSize * PartBits / 2;
398 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
399 SDValue &Part0 = Parts[i];
400 SDValue &Part1 = Parts[i+StepSize/2];
402 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
403 ThisVT, Part0, DAG.getIntPtrConstant(1));
404 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
405 ThisVT, Part0, DAG.getIntPtrConstant(0));
407 if (ThisBits == PartBits && ThisVT != PartVT) {
408 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
409 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
414 if (TLI.isBigEndian())
415 std::reverse(Parts, Parts + OrigNumParts);
419 /// getCopyToPartsVector - Create a series of nodes that contain the specified
420 /// value split into legal parts.
421 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
422 SDValue Val, SDValue *Parts, unsigned NumParts,
424 EVT ValueVT = Val.getValueType();
425 assert(ValueVT.isVector() && "Not a vector");
426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
429 if (PartVT == ValueVT) {
431 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
432 // Bitconvert vector->vector case.
433 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
434 } else if (PartVT.isVector() &&
435 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
436 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
437 EVT ElementVT = PartVT.getVectorElementType();
438 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
440 SmallVector<SDValue, 16> Ops;
441 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
442 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
443 ElementVT, Val, DAG.getIntPtrConstant(i)));
445 for (unsigned i = ValueVT.getVectorNumElements(),
446 e = PartVT.getVectorNumElements(); i != e; ++i)
447 Ops.push_back(DAG.getUNDEF(ElementVT));
449 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
451 // FIXME: Use CONCAT for 2x -> 4x.
453 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
454 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
456 // Vector -> scalar conversion.
457 assert(ValueVT.getVectorElementType() == PartVT &&
458 ValueVT.getVectorNumElements() == 1 &&
459 "Only trivial vector-to-scalar conversions should get here!");
460 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
461 PartVT, Val, DAG.getIntPtrConstant(0));
468 // Handle a multi-element vector.
469 EVT IntermediateVT, RegisterVT;
470 unsigned NumIntermediates;
471 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
473 NumIntermediates, RegisterVT);
474 unsigned NumElements = ValueVT.getVectorNumElements();
476 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
477 NumParts = NumRegs; // Silence a compiler warning.
478 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
480 // Split the vector into intermediate operands.
481 SmallVector<SDValue, 8> Ops(NumIntermediates);
482 for (unsigned i = 0; i != NumIntermediates; ++i) {
483 if (IntermediateVT.isVector())
484 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
486 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
488 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
489 IntermediateVT, Val, DAG.getIntPtrConstant(i));
492 // Split the intermediate operands into legal parts.
493 if (NumParts == NumIntermediates) {
494 // If the register was not expanded, promote or copy the value,
496 for (unsigned i = 0; i != NumParts; ++i)
497 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
498 } else if (NumParts > 0) {
499 // If the intermediate type was expanded, split each the value into
501 assert(NumParts % NumIntermediates == 0 &&
502 "Must expand into a divisible number of parts!");
503 unsigned Factor = NumParts / NumIntermediates;
504 for (unsigned i = 0; i != NumIntermediates; ++i)
505 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
513 /// RegsForValue - This struct represents the registers (physical or virtual)
514 /// that a particular set of values is assigned, and the type information
515 /// about the value. The most common situation is to represent one value at a
516 /// time, but struct or array values are handled element-wise as multiple
517 /// values. The splitting of aggregates is performed recursively, so that we
518 /// never have aggregate-typed registers. The values at this point do not
519 /// necessarily have legal types, so each value may require one or more
520 /// registers of some legal type.
522 struct RegsForValue {
523 /// ValueVTs - The value types of the values, which may not be legal, and
524 /// may need be promoted or synthesized from one or more registers.
526 SmallVector<EVT, 4> ValueVTs;
528 /// RegVTs - The value types of the registers. This is the same size as
529 /// ValueVTs and it records, for each value, what the type of the assigned
530 /// register or registers are. (Individual values are never synthesized
531 /// from more than one type of register.)
533 /// With virtual registers, the contents of RegVTs is redundant with TLI's
534 /// getRegisterType member function, however when with physical registers
535 /// it is necessary to have a separate record of the types.
537 SmallVector<EVT, 4> RegVTs;
539 /// Regs - This list holds the registers assigned to the values.
540 /// Each legal or promoted value requires one register, and each
541 /// expanded value requires multiple registers.
543 SmallVector<unsigned, 4> Regs;
547 RegsForValue(const SmallVector<unsigned, 4> ®s,
548 EVT regvt, EVT valuevt)
549 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
551 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
552 unsigned Reg, const Type *Ty) {
553 ComputeValueVTs(tli, Ty, ValueVTs);
555 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
556 EVT ValueVT = ValueVTs[Value];
557 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
558 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
559 for (unsigned i = 0; i != NumRegs; ++i)
560 Regs.push_back(Reg + i);
561 RegVTs.push_back(RegisterVT);
566 /// areValueTypesLegal - Return true if types of all the values are legal.
567 bool areValueTypesLegal(const TargetLowering &TLI) {
568 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
569 EVT RegisterVT = RegVTs[Value];
570 if (!TLI.isTypeLegal(RegisterVT))
576 /// append - Add the specified values to this one.
577 void append(const RegsForValue &RHS) {
578 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
579 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
580 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
583 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
584 /// this value and returns the result as a ValueVTs value. This uses
585 /// Chain/Flag as the input and updates them for the output Chain/Flag.
586 /// If the Flag pointer is NULL, no flag is used.
587 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
589 SDValue &Chain, SDValue *Flag) const;
591 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
592 /// specified value into the registers specified by this object. This uses
593 /// Chain/Flag as the input and updates them for the output Chain/Flag.
594 /// If the Flag pointer is NULL, no flag is used.
595 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
596 SDValue &Chain, SDValue *Flag) const;
598 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
599 /// operand list. This adds the code marker, matching input operand index
600 /// (if applicable), and includes the number of values added into it.
601 void AddInlineAsmOperands(unsigned Kind,
602 bool HasMatching, unsigned MatchingIdx,
604 std::vector<SDValue> &Ops) const;
608 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
609 /// this value and returns the result as a ValueVT value. This uses
610 /// Chain/Flag as the input and updates them for the output Chain/Flag.
611 /// If the Flag pointer is NULL, no flag is used.
612 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
613 FunctionLoweringInfo &FuncInfo,
615 SDValue &Chain, SDValue *Flag) const {
616 // A Value with type {} or [0 x %t] needs no registers.
617 if (ValueVTs.empty())
620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
622 // Assemble the legal parts into the final values.
623 SmallVector<SDValue, 4> Values(ValueVTs.size());
624 SmallVector<SDValue, 8> Parts;
625 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
626 // Copy the legal parts from the registers.
627 EVT ValueVT = ValueVTs[Value];
628 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
629 EVT RegisterVT = RegVTs[Value];
631 Parts.resize(NumRegs);
632 for (unsigned i = 0; i != NumRegs; ++i) {
635 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
637 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
638 *Flag = P.getValue(2);
641 Chain = P.getValue(1);
644 // If the source register was virtual and if we know something about it,
645 // add an assert node.
646 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
647 !RegisterVT.isInteger() || RegisterVT.isVector())
650 const FunctionLoweringInfo::LiveOutInfo *LOI =
651 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
655 unsigned RegSize = RegisterVT.getSizeInBits();
656 unsigned NumSignBits = LOI->NumSignBits;
657 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
659 // FIXME: We capture more information than the dag can represent. For
660 // now, just use the tightest assertzext/assertsext possible.
662 EVT FromVT(MVT::Other);
663 if (NumSignBits == RegSize)
664 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
665 else if (NumZeroBits >= RegSize-1)
666 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
667 else if (NumSignBits > RegSize-8)
668 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
669 else if (NumZeroBits >= RegSize-8)
670 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
671 else if (NumSignBits > RegSize-16)
672 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
673 else if (NumZeroBits >= RegSize-16)
674 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
675 else if (NumSignBits > RegSize-32)
676 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
677 else if (NumZeroBits >= RegSize-32)
678 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
682 // Add an assertion node.
683 assert(FromVT != MVT::Other);
684 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
685 RegisterVT, P, DAG.getValueType(FromVT));
688 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
689 NumRegs, RegisterVT, ValueVT);
694 return DAG.getNode(ISD::MERGE_VALUES, dl,
695 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
696 &Values[0], ValueVTs.size());
699 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
700 /// specified value into the registers specified by this object. This uses
701 /// Chain/Flag as the input and updates them for the output Chain/Flag.
702 /// If the Flag pointer is NULL, no flag is used.
703 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
704 SDValue &Chain, SDValue *Flag) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
707 // Get the list of the values's legal parts.
708 unsigned NumRegs = Regs.size();
709 SmallVector<SDValue, 8> Parts(NumRegs);
710 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
711 EVT ValueVT = ValueVTs[Value];
712 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
713 EVT RegisterVT = RegVTs[Value];
715 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
716 &Parts[Part], NumParts, RegisterVT);
720 // Copy the parts into the registers.
721 SmallVector<SDValue, 8> Chains(NumRegs);
722 for (unsigned i = 0; i != NumRegs; ++i) {
725 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
727 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
728 *Flag = Part.getValue(1);
731 Chains[i] = Part.getValue(0);
734 if (NumRegs == 1 || Flag)
735 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
736 // flagged to it. That is the CopyToReg nodes and the user are considered
737 // a single scheduling unit. If we create a TokenFactor and return it as
738 // chain, then the TokenFactor is both a predecessor (operand) of the
739 // user as well as a successor (the TF operands are flagged to the user).
740 // c1, f1 = CopyToReg
741 // c2, f2 = CopyToReg
742 // c3 = TokenFactor c1, c2
745 Chain = Chains[NumRegs-1];
747 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
750 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
751 /// operand list. This adds the code marker and includes the number of
752 /// values added into it.
753 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
754 unsigned MatchingIdx,
756 std::vector<SDValue> &Ops) const {
757 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
759 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
761 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
762 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
765 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
766 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
767 EVT RegisterVT = RegVTs[Value];
768 for (unsigned i = 0; i != NumRegs; ++i) {
769 assert(Reg < Regs.size() && "Mismatch in # registers expected");
770 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
775 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
778 TD = DAG.getTarget().getTargetData();
781 /// clear - Clear out the current SelectionDAG and the associated
782 /// state and prepare this SelectionDAGBuilder object to be used
783 /// for a new block. This doesn't clear out information about
784 /// additional blocks that are needed to complete switch lowering
785 /// or PHI node updating; that information is cleared out as it is
787 void SelectionDAGBuilder::clear() {
789 UnusedArgNodeMap.clear();
790 PendingLoads.clear();
791 PendingExports.clear();
792 CurDebugLoc = DebugLoc();
796 /// clearDanglingDebugInfo - Clear the dangling debug information
797 /// map. This function is seperated from the clear so that debug
798 /// information that is dangling in a basic block can be properly
799 /// resolved in a different basic block. This allows the
800 /// SelectionDAG to resolve dangling debug information attached
802 void SelectionDAGBuilder::clearDanglingDebugInfo() {
803 DanglingDebugInfoMap.clear();
806 /// getRoot - Return the current virtual root of the Selection DAG,
807 /// flushing any PendingLoad items. This must be done before emitting
808 /// a store or any other node that may need to be ordered after any
809 /// prior load instructions.
811 SDValue SelectionDAGBuilder::getRoot() {
812 if (PendingLoads.empty())
813 return DAG.getRoot();
815 if (PendingLoads.size() == 1) {
816 SDValue Root = PendingLoads[0];
818 PendingLoads.clear();
822 // Otherwise, we have to make a token factor node.
823 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
824 &PendingLoads[0], PendingLoads.size());
825 PendingLoads.clear();
830 /// getControlRoot - Similar to getRoot, but instead of flushing all the
831 /// PendingLoad items, flush all the PendingExports items. It is necessary
832 /// to do this before emitting a terminator instruction.
834 SDValue SelectionDAGBuilder::getControlRoot() {
835 SDValue Root = DAG.getRoot();
837 if (PendingExports.empty())
840 // Turn all of the CopyToReg chains into one factored node.
841 if (Root.getOpcode() != ISD::EntryToken) {
842 unsigned i = 0, e = PendingExports.size();
843 for (; i != e; ++i) {
844 assert(PendingExports[i].getNode()->getNumOperands() > 1);
845 if (PendingExports[i].getNode()->getOperand(0) == Root)
846 break; // Don't add the root if we already indirectly depend on it.
850 PendingExports.push_back(Root);
853 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
855 PendingExports.size());
856 PendingExports.clear();
861 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
862 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
863 DAG.AssignOrdering(Node, SDNodeOrder);
865 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
866 AssignOrderingToNode(Node->getOperand(I).getNode());
869 void SelectionDAGBuilder::visit(const Instruction &I) {
870 // Set up outgoing PHI node register values before emitting the terminator.
871 if (isa<TerminatorInst>(&I))
872 HandlePHINodesInSuccessorBlocks(I.getParent());
874 CurDebugLoc = I.getDebugLoc();
876 visit(I.getOpcode(), I);
878 if (!isa<TerminatorInst>(&I) && !HasTailCall)
879 CopyToExportRegsIfNeeded(&I);
881 CurDebugLoc = DebugLoc();
884 void SelectionDAGBuilder::visitPHI(const PHINode &) {
885 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
888 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
889 // Note: this doesn't use InstVisitor, because it has to work with
890 // ConstantExpr's in addition to instructions.
892 default: llvm_unreachable("Unknown instruction type encountered!");
893 // Build the switch statement using the Instruction.def file.
894 #define HANDLE_INST(NUM, OPCODE, CLASS) \
895 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
896 #include "llvm/Instruction.def"
899 // Assign the ordering to the freshly created DAG nodes.
900 if (NodeMap.count(&I)) {
902 AssignOrderingToNode(getValue(&I).getNode());
906 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
907 // generate the debug data structures now that we've seen its definition.
908 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
910 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
912 const DbgValueInst *DI = DDI.getDI();
913 DebugLoc dl = DDI.getdl();
914 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
915 MDNode *Variable = DI->getVariable();
916 uint64_t Offset = DI->getOffset();
919 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
920 SDV = DAG.getDbgValue(Variable, Val.getNode(),
921 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
922 DAG.AddDbgValue(SDV, Val.getNode(), false);
925 DEBUG(dbgs() << "Dropping debug info for " << DI);
926 DanglingDebugInfoMap[V] = DanglingDebugInfo();
930 // getValue - Return an SDValue for the given Value.
931 SDValue SelectionDAGBuilder::getValue(const Value *V) {
932 // If we already have an SDValue for this value, use it. It's important
933 // to do this first, so that we don't create a CopyFromReg if we already
934 // have a regular SDValue.
935 SDValue &N = NodeMap[V];
936 if (N.getNode()) return N;
938 // If there's a virtual register allocated and initialized for this
940 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
941 if (It != FuncInfo.ValueMap.end()) {
942 unsigned InReg = It->second;
943 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
944 SDValue Chain = DAG.getEntryNode();
945 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
946 resolveDanglingDebugInfo(V, N);
950 // Otherwise create a new SDValue and remember it.
951 SDValue Val = getValueImpl(V);
953 resolveDanglingDebugInfo(V, Val);
957 /// getNonRegisterValue - Return an SDValue for the given Value, but
958 /// don't look in FuncInfo.ValueMap for a virtual register.
959 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
960 // If we already have an SDValue for this value, use it.
961 SDValue &N = NodeMap[V];
962 if (N.getNode()) return N;
964 // Otherwise create a new SDValue and remember it.
965 SDValue Val = getValueImpl(V);
967 resolveDanglingDebugInfo(V, Val);
971 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
972 /// Create an SDValue for the given value.
973 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
974 if (const Constant *C = dyn_cast<Constant>(V)) {
975 EVT VT = TLI.getValueType(V->getType(), true);
977 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
978 return DAG.getConstant(*CI, VT);
980 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
981 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
983 if (isa<ConstantPointerNull>(C))
984 return DAG.getConstant(0, TLI.getPointerTy());
986 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
987 return DAG.getConstantFP(*CFP, VT);
989 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
990 return DAG.getUNDEF(VT);
992 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
993 visit(CE->getOpcode(), *CE);
994 SDValue N1 = NodeMap[V];
995 assert(N1.getNode() && "visit didn't populate the NodeMap!");
999 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1000 SmallVector<SDValue, 4> Constants;
1001 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1003 SDNode *Val = getValue(*OI).getNode();
1004 // If the operand is an empty aggregate, there are no values.
1006 // Add each leaf value from the operand to the Constants list
1007 // to form a flattened list of all the values.
1008 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1009 Constants.push_back(SDValue(Val, i));
1012 return DAG.getMergeValues(&Constants[0], Constants.size(),
1016 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1017 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1018 "Unknown struct or array constant!");
1020 SmallVector<EVT, 4> ValueVTs;
1021 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1022 unsigned NumElts = ValueVTs.size();
1024 return SDValue(); // empty struct
1025 SmallVector<SDValue, 4> Constants(NumElts);
1026 for (unsigned i = 0; i != NumElts; ++i) {
1027 EVT EltVT = ValueVTs[i];
1028 if (isa<UndefValue>(C))
1029 Constants[i] = DAG.getUNDEF(EltVT);
1030 else if (EltVT.isFloatingPoint())
1031 Constants[i] = DAG.getConstantFP(0, EltVT);
1033 Constants[i] = DAG.getConstant(0, EltVT);
1036 return DAG.getMergeValues(&Constants[0], NumElts,
1040 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1041 return DAG.getBlockAddress(BA, VT);
1043 const VectorType *VecTy = cast<VectorType>(V->getType());
1044 unsigned NumElements = VecTy->getNumElements();
1046 // Now that we know the number and type of the elements, get that number of
1047 // elements into the Ops array based on what kind of constant it is.
1048 SmallVector<SDValue, 16> Ops;
1049 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1050 for (unsigned i = 0; i != NumElements; ++i)
1051 Ops.push_back(getValue(CP->getOperand(i)));
1053 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1054 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1057 if (EltVT.isFloatingPoint())
1058 Op = DAG.getConstantFP(0, EltVT);
1060 Op = DAG.getConstant(0, EltVT);
1061 Ops.assign(NumElements, Op);
1064 // Create a BUILD_VECTOR node.
1065 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1066 VT, &Ops[0], Ops.size());
1069 // If this is a static alloca, generate it as the frameindex instead of
1071 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1072 DenseMap<const AllocaInst*, int>::iterator SI =
1073 FuncInfo.StaticAllocaMap.find(AI);
1074 if (SI != FuncInfo.StaticAllocaMap.end())
1075 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1078 // If this is an instruction which fast-isel has deferred, select it now.
1079 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1080 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1081 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1082 SDValue Chain = DAG.getEntryNode();
1083 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1086 llvm_unreachable("Can't get register for value!");
1090 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1091 SDValue Chain = getControlRoot();
1092 SmallVector<ISD::OutputArg, 8> Outs;
1093 SmallVector<SDValue, 8> OutVals;
1095 if (!FuncInfo.CanLowerReturn) {
1096 unsigned DemoteReg = FuncInfo.DemoteRegister;
1097 const Function *F = I.getParent()->getParent();
1099 // Emit a store of the return value through the virtual register.
1100 // Leave Outs empty so that LowerReturn won't try to load return
1101 // registers the usual way.
1102 SmallVector<EVT, 1> PtrValueVTs;
1103 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1106 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1107 SDValue RetOp = getValue(I.getOperand(0));
1109 SmallVector<EVT, 4> ValueVTs;
1110 SmallVector<uint64_t, 4> Offsets;
1111 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1112 unsigned NumValues = ValueVTs.size();
1114 SmallVector<SDValue, 4> Chains(NumValues);
1115 for (unsigned i = 0; i != NumValues; ++i) {
1116 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1117 RetPtr.getValueType(), RetPtr,
1118 DAG.getIntPtrConstant(Offsets[i]));
1120 DAG.getStore(Chain, getCurDebugLoc(),
1121 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1122 // FIXME: better loc info would be nice.
1123 Add, MachinePointerInfo(), false, false, 0);
1126 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1127 MVT::Other, &Chains[0], NumValues);
1128 } else if (I.getNumOperands() != 0) {
1129 SmallVector<EVT, 4> ValueVTs;
1130 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1131 unsigned NumValues = ValueVTs.size();
1133 SDValue RetOp = getValue(I.getOperand(0));
1134 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1135 EVT VT = ValueVTs[j];
1137 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1139 const Function *F = I.getParent()->getParent();
1140 if (F->paramHasAttr(0, Attribute::SExt))
1141 ExtendKind = ISD::SIGN_EXTEND;
1142 else if (F->paramHasAttr(0, Attribute::ZExt))
1143 ExtendKind = ISD::ZERO_EXTEND;
1145 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1146 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1148 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1149 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1150 SmallVector<SDValue, 4> Parts(NumParts);
1151 getCopyToParts(DAG, getCurDebugLoc(),
1152 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1153 &Parts[0], NumParts, PartVT, ExtendKind);
1155 // 'inreg' on function refers to return value
1156 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1157 if (F->paramHasAttr(0, Attribute::InReg))
1160 // Propagate extension type if any
1161 if (ExtendKind == ISD::SIGN_EXTEND)
1163 else if (ExtendKind == ISD::ZERO_EXTEND)
1166 for (unsigned i = 0; i < NumParts; ++i) {
1167 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1169 OutVals.push_back(Parts[i]);
1175 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1176 CallingConv::ID CallConv =
1177 DAG.getMachineFunction().getFunction()->getCallingConv();
1178 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1179 Outs, OutVals, getCurDebugLoc(), DAG);
1181 // Verify that the target's LowerReturn behaved as expected.
1182 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1183 "LowerReturn didn't return a valid chain!");
1185 // Update the DAG with the new chain value resulting from return lowering.
1189 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1190 /// created for it, emit nodes to copy the value into the virtual
1192 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1194 if (V->getType()->isEmptyTy())
1197 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1198 if (VMI != FuncInfo.ValueMap.end()) {
1199 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1200 CopyValueToVirtualRegister(V, VMI->second);
1204 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1205 /// the current basic block, add it to ValueMap now so that we'll get a
1207 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1208 // No need to export constants.
1209 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1211 // Already exported?
1212 if (FuncInfo.isExportedInst(V)) return;
1214 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1215 CopyValueToVirtualRegister(V, Reg);
1218 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1219 const BasicBlock *FromBB) {
1220 // The operands of the setcc have to be in this block. We don't know
1221 // how to export them from some other block.
1222 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1223 // Can export from current BB.
1224 if (VI->getParent() == FromBB)
1227 // Is already exported, noop.
1228 return FuncInfo.isExportedInst(V);
1231 // If this is an argument, we can export it if the BB is the entry block or
1232 // if it is already exported.
1233 if (isa<Argument>(V)) {
1234 if (FromBB == &FromBB->getParent()->getEntryBlock())
1237 // Otherwise, can only export this if it is already exported.
1238 return FuncInfo.isExportedInst(V);
1241 // Otherwise, constants can always be exported.
1245 static bool InBlock(const Value *V, const BasicBlock *BB) {
1246 if (const Instruction *I = dyn_cast<Instruction>(V))
1247 return I->getParent() == BB;
1251 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1252 /// This function emits a branch and is used at the leaves of an OR or an
1253 /// AND operator tree.
1256 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1257 MachineBasicBlock *TBB,
1258 MachineBasicBlock *FBB,
1259 MachineBasicBlock *CurBB,
1260 MachineBasicBlock *SwitchBB) {
1261 const BasicBlock *BB = CurBB->getBasicBlock();
1263 // If the leaf of the tree is a comparison, merge the condition into
1265 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1266 // The operands of the cmp have to be in this block. We don't know
1267 // how to export them from some other block. If this is the first block
1268 // of the sequence, no exporting is needed.
1269 if (CurBB == SwitchBB ||
1270 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1271 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1272 ISD::CondCode Condition;
1273 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1274 Condition = getICmpCondCode(IC->getPredicate());
1275 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1276 Condition = getFCmpCondCode(FC->getPredicate());
1278 Condition = ISD::SETEQ; // silence warning.
1279 llvm_unreachable("Unknown compare instruction");
1282 CaseBlock CB(Condition, BOp->getOperand(0),
1283 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1284 SwitchCases.push_back(CB);
1289 // Create a CaseBlock record representing this branch.
1290 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1291 NULL, TBB, FBB, CurBB);
1292 SwitchCases.push_back(CB);
1295 /// FindMergedConditions - If Cond is an expression like
1296 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1297 MachineBasicBlock *TBB,
1298 MachineBasicBlock *FBB,
1299 MachineBasicBlock *CurBB,
1300 MachineBasicBlock *SwitchBB,
1302 // If this node is not part of the or/and tree, emit it as a branch.
1303 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1304 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1305 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1306 BOp->getParent() != CurBB->getBasicBlock() ||
1307 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1308 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1309 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1313 // Create TmpBB after CurBB.
1314 MachineFunction::iterator BBI = CurBB;
1315 MachineFunction &MF = DAG.getMachineFunction();
1316 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1317 CurBB->getParent()->insert(++BBI, TmpBB);
1319 if (Opc == Instruction::Or) {
1320 // Codegen X | Y as:
1328 // Emit the LHS condition.
1329 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1331 // Emit the RHS condition into TmpBB.
1332 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1334 assert(Opc == Instruction::And && "Unknown merge op!");
1335 // Codegen X & Y as:
1342 // This requires creation of TmpBB after CurBB.
1344 // Emit the LHS condition.
1345 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1347 // Emit the RHS condition into TmpBB.
1348 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1352 /// If the set of cases should be emitted as a series of branches, return true.
1353 /// If we should emit this as a bunch of and/or'd together conditions, return
1356 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1357 if (Cases.size() != 2) return true;
1359 // If this is two comparisons of the same values or'd or and'd together, they
1360 // will get folded into a single comparison, so don't emit two blocks.
1361 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1362 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1363 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1364 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1368 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1369 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1370 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1371 Cases[0].CC == Cases[1].CC &&
1372 isa<Constant>(Cases[0].CmpRHS) &&
1373 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1374 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1376 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1383 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1384 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1386 // Update machine-CFG edges.
1387 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1389 // Figure out which block is immediately after the current one.
1390 MachineBasicBlock *NextBlock = 0;
1391 MachineFunction::iterator BBI = BrMBB;
1392 if (++BBI != FuncInfo.MF->end())
1395 if (I.isUnconditional()) {
1396 // Update machine-CFG edges.
1397 BrMBB->addSuccessor(Succ0MBB);
1399 // If this is not a fall-through branch, emit the branch.
1400 if (Succ0MBB != NextBlock)
1401 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1402 MVT::Other, getControlRoot(),
1403 DAG.getBasicBlock(Succ0MBB)));
1408 // If this condition is one of the special cases we handle, do special stuff
1410 const Value *CondVal = I.getCondition();
1411 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1413 // If this is a series of conditions that are or'd or and'd together, emit
1414 // this as a sequence of branches instead of setcc's with and/or operations.
1415 // As long as jumps are not expensive, this should improve performance.
1416 // For example, instead of something like:
1429 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1430 if (!TLI.isJumpExpensive() &&
1432 (BOp->getOpcode() == Instruction::And ||
1433 BOp->getOpcode() == Instruction::Or)) {
1434 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1436 // If the compares in later blocks need to use values not currently
1437 // exported from this block, export them now. This block should always
1438 // be the first entry.
1439 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1441 // Allow some cases to be rejected.
1442 if (ShouldEmitAsBranches(SwitchCases)) {
1443 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1444 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1445 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1448 // Emit the branch for this block.
1449 visitSwitchCase(SwitchCases[0], BrMBB);
1450 SwitchCases.erase(SwitchCases.begin());
1454 // Okay, we decided not to do this, remove any inserted MBB's and clear
1456 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1457 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1459 SwitchCases.clear();
1463 // Create a CaseBlock record representing this branch.
1464 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1465 NULL, Succ0MBB, Succ1MBB, BrMBB);
1467 // Use visitSwitchCase to actually insert the fast branch sequence for this
1469 visitSwitchCase(CB, BrMBB);
1472 /// visitSwitchCase - Emits the necessary code to represent a single node in
1473 /// the binary search tree resulting from lowering a switch instruction.
1474 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1475 MachineBasicBlock *SwitchBB) {
1477 SDValue CondLHS = getValue(CB.CmpLHS);
1478 DebugLoc dl = getCurDebugLoc();
1480 // Build the setcc now.
1481 if (CB.CmpMHS == NULL) {
1482 // Fold "(X == true)" to X and "(X == false)" to !X to
1483 // handle common cases produced by branch lowering.
1484 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1485 CB.CC == ISD::SETEQ)
1487 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1488 CB.CC == ISD::SETEQ) {
1489 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1490 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1492 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1494 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1496 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1497 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1499 SDValue CmpOp = getValue(CB.CmpMHS);
1500 EVT VT = CmpOp.getValueType();
1502 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1503 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1506 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1507 VT, CmpOp, DAG.getConstant(Low, VT));
1508 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1509 DAG.getConstant(High-Low, VT), ISD::SETULE);
1513 // Update successor info
1514 SwitchBB->addSuccessor(CB.TrueBB);
1515 SwitchBB->addSuccessor(CB.FalseBB);
1517 // Set NextBlock to be the MBB immediately after the current one, if any.
1518 // This is used to avoid emitting unnecessary branches to the next block.
1519 MachineBasicBlock *NextBlock = 0;
1520 MachineFunction::iterator BBI = SwitchBB;
1521 if (++BBI != FuncInfo.MF->end())
1524 // If the lhs block is the next block, invert the condition so that we can
1525 // fall through to the lhs instead of the rhs block.
1526 if (CB.TrueBB == NextBlock) {
1527 std::swap(CB.TrueBB, CB.FalseBB);
1528 SDValue True = DAG.getConstant(1, Cond.getValueType());
1529 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1532 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1533 MVT::Other, getControlRoot(), Cond,
1534 DAG.getBasicBlock(CB.TrueBB));
1536 // Insert the false branch. Do this even if it's a fall through branch,
1537 // this makes it easier to do DAG optimizations which require inverting
1538 // the branch condition.
1539 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1540 DAG.getBasicBlock(CB.FalseBB));
1542 DAG.setRoot(BrCond);
1545 /// visitJumpTable - Emit JumpTable node in the current MBB
1546 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1547 // Emit the code for the jump table
1548 assert(JT.Reg != -1U && "Should lower JT Header first!");
1549 EVT PTy = TLI.getPointerTy();
1550 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1552 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1553 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1554 MVT::Other, Index.getValue(1),
1556 DAG.setRoot(BrJumpTable);
1559 /// visitJumpTableHeader - This function emits necessary code to produce index
1560 /// in the JumpTable from switch case.
1561 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1562 JumpTableHeader &JTH,
1563 MachineBasicBlock *SwitchBB) {
1564 // Subtract the lowest switch case value from the value being switched on and
1565 // conditional branch to default mbb if the result is greater than the
1566 // difference between smallest and largest cases.
1567 SDValue SwitchOp = getValue(JTH.SValue);
1568 EVT VT = SwitchOp.getValueType();
1569 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1570 DAG.getConstant(JTH.First, VT));
1572 // The SDNode we just created, which holds the value being switched on minus
1573 // the smallest case value, needs to be copied to a virtual register so it
1574 // can be used as an index into the jump table in a subsequent basic block.
1575 // This value may be smaller or larger than the target's pointer type, and
1576 // therefore require extension or truncating.
1577 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1579 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1580 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1581 JumpTableReg, SwitchOp);
1582 JT.Reg = JumpTableReg;
1584 // Emit the range check for the jump table, and branch to the default block
1585 // for the switch statement if the value being switched on exceeds the largest
1586 // case in the switch.
1587 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1588 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1589 DAG.getConstant(JTH.Last-JTH.First,VT),
1592 // Set NextBlock to be the MBB immediately after the current one, if any.
1593 // This is used to avoid emitting unnecessary branches to the next block.
1594 MachineBasicBlock *NextBlock = 0;
1595 MachineFunction::iterator BBI = SwitchBB;
1597 if (++BBI != FuncInfo.MF->end())
1600 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1601 MVT::Other, CopyTo, CMP,
1602 DAG.getBasicBlock(JT.Default));
1604 if (JT.MBB != NextBlock)
1605 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1606 DAG.getBasicBlock(JT.MBB));
1608 DAG.setRoot(BrCond);
1611 /// visitBitTestHeader - This function emits necessary code to produce value
1612 /// suitable for "bit tests"
1613 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1614 MachineBasicBlock *SwitchBB) {
1615 // Subtract the minimum value
1616 SDValue SwitchOp = getValue(B.SValue);
1617 EVT VT = SwitchOp.getValueType();
1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1619 DAG.getConstant(B.First, VT));
1622 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1623 TLI.getSetCCResultType(Sub.getValueType()),
1624 Sub, DAG.getConstant(B.Range, VT),
1627 // Determine the type of the test operands.
1628 bool UsePtrType = false;
1629 if (!TLI.isTypeLegal(VT))
1632 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1633 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1634 // Switch table case range are encoded into series of masks.
1635 // Just use pointer type, it's guaranteed to fit.
1641 VT = TLI.getPointerTy();
1642 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1646 B.Reg = FuncInfo.CreateReg(VT);
1647 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1650 // Set NextBlock to be the MBB immediately after the current one, if any.
1651 // This is used to avoid emitting unnecessary branches to the next block.
1652 MachineBasicBlock *NextBlock = 0;
1653 MachineFunction::iterator BBI = SwitchBB;
1654 if (++BBI != FuncInfo.MF->end())
1657 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1659 SwitchBB->addSuccessor(B.Default);
1660 SwitchBB->addSuccessor(MBB);
1662 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1663 MVT::Other, CopyTo, RangeCmp,
1664 DAG.getBasicBlock(B.Default));
1666 if (MBB != NextBlock)
1667 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1668 DAG.getBasicBlock(MBB));
1670 DAG.setRoot(BrRange);
1673 /// visitBitTestCase - this function produces one "bit test"
1674 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1675 MachineBasicBlock* NextMBB,
1678 MachineBasicBlock *SwitchBB) {
1680 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1683 if (CountPopulation_64(B.Mask) == 1) {
1684 // Testing for a single bit; just compare the shift count with what it
1685 // would need to be to shift a 1 bit in that position.
1686 Cmp = DAG.getSetCC(getCurDebugLoc(),
1687 TLI.getSetCCResultType(VT),
1689 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1692 // Make desired shift
1693 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1694 DAG.getConstant(1, VT), ShiftOp);
1696 // Emit bit tests and jumps
1697 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1698 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1699 Cmp = DAG.getSetCC(getCurDebugLoc(),
1700 TLI.getSetCCResultType(VT),
1701 AndOp, DAG.getConstant(0, VT),
1705 SwitchBB->addSuccessor(B.TargetBB);
1706 SwitchBB->addSuccessor(NextMBB);
1708 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1709 MVT::Other, getControlRoot(),
1710 Cmp, DAG.getBasicBlock(B.TargetBB));
1712 // Set NextBlock to be the MBB immediately after the current one, if any.
1713 // This is used to avoid emitting unnecessary branches to the next block.
1714 MachineBasicBlock *NextBlock = 0;
1715 MachineFunction::iterator BBI = SwitchBB;
1716 if (++BBI != FuncInfo.MF->end())
1719 if (NextMBB != NextBlock)
1720 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1721 DAG.getBasicBlock(NextMBB));
1726 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1727 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1729 // Retrieve successors.
1730 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1731 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1733 const Value *Callee(I.getCalledValue());
1734 if (isa<InlineAsm>(Callee))
1737 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1739 // If the value of the invoke is used outside of its defining block, make it
1740 // available as a virtual register.
1741 CopyToExportRegsIfNeeded(&I);
1743 // Update successor info
1744 InvokeMBB->addSuccessor(Return);
1745 InvokeMBB->addSuccessor(LandingPad);
1747 // Drop into normal successor.
1748 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1749 MVT::Other, getControlRoot(),
1750 DAG.getBasicBlock(Return)));
1753 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1756 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1757 /// small case ranges).
1758 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1759 CaseRecVector& WorkList,
1761 MachineBasicBlock *Default,
1762 MachineBasicBlock *SwitchBB) {
1763 Case& BackCase = *(CR.Range.second-1);
1765 // Size is the number of Cases represented by this range.
1766 size_t Size = CR.Range.second - CR.Range.first;
1770 // Get the MachineFunction which holds the current MBB. This is used when
1771 // inserting any additional MBBs necessary to represent the switch.
1772 MachineFunction *CurMF = FuncInfo.MF;
1774 // Figure out which block is immediately after the current one.
1775 MachineBasicBlock *NextBlock = 0;
1776 MachineFunction::iterator BBI = CR.CaseBB;
1778 if (++BBI != FuncInfo.MF->end())
1781 // If any two of the cases has the same destination, and if one value
1782 // is the same as the other, but has one bit unset that the other has set,
1783 // use bit manipulation to do two compares at once. For example:
1784 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1785 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1786 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1787 if (Size == 2 && CR.CaseBB == SwitchBB) {
1788 Case &Small = *CR.Range.first;
1789 Case &Big = *(CR.Range.second-1);
1791 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1792 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1793 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1795 // Check that there is only one bit different.
1796 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1797 (SmallValue | BigValue) == BigValue) {
1798 // Isolate the common bit.
1799 APInt CommonBit = BigValue & ~SmallValue;
1800 assert((SmallValue | CommonBit) == BigValue &&
1801 CommonBit.countPopulation() == 1 && "Not a common bit?");
1803 SDValue CondLHS = getValue(SV);
1804 EVT VT = CondLHS.getValueType();
1805 DebugLoc DL = getCurDebugLoc();
1807 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1808 DAG.getConstant(CommonBit, VT));
1809 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1810 Or, DAG.getConstant(BigValue, VT),
1813 // Update successor info.
1814 SwitchBB->addSuccessor(Small.BB);
1815 SwitchBB->addSuccessor(Default);
1817 // Insert the true branch.
1818 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1819 getControlRoot(), Cond,
1820 DAG.getBasicBlock(Small.BB));
1822 // Insert the false branch.
1823 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1824 DAG.getBasicBlock(Default));
1826 DAG.setRoot(BrCond);
1832 // Rearrange the case blocks so that the last one falls through if possible.
1833 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1834 // The last case block won't fall through into 'NextBlock' if we emit the
1835 // branches in this order. See if rearranging a case value would help.
1836 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1837 if (I->BB == NextBlock) {
1838 std::swap(*I, BackCase);
1844 // Create a CaseBlock record representing a conditional branch to
1845 // the Case's target mbb if the value being switched on SV is equal
1847 MachineBasicBlock *CurBlock = CR.CaseBB;
1848 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1849 MachineBasicBlock *FallThrough;
1851 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1852 CurMF->insert(BBI, FallThrough);
1854 // Put SV in a virtual register to make it available from the new blocks.
1855 ExportFromCurrentBlock(SV);
1857 // If the last case doesn't match, go to the default block.
1858 FallThrough = Default;
1861 const Value *RHS, *LHS, *MHS;
1863 if (I->High == I->Low) {
1864 // This is just small small case range :) containing exactly 1 case
1866 LHS = SV; RHS = I->High; MHS = NULL;
1869 LHS = I->Low; MHS = SV; RHS = I->High;
1871 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1873 // If emitting the first comparison, just call visitSwitchCase to emit the
1874 // code into the current block. Otherwise, push the CaseBlock onto the
1875 // vector to be later processed by SDISel, and insert the node's MBB
1876 // before the next MBB.
1877 if (CurBlock == SwitchBB)
1878 visitSwitchCase(CB, SwitchBB);
1880 SwitchCases.push_back(CB);
1882 CurBlock = FallThrough;
1888 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1889 return !DisableJumpTables &&
1890 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1891 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1894 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1895 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1896 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1897 return (LastExt - FirstExt + 1ULL);
1900 /// handleJTSwitchCase - Emit jumptable for current switch case range
1901 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1902 CaseRecVector& WorkList,
1904 MachineBasicBlock* Default,
1905 MachineBasicBlock *SwitchBB) {
1906 Case& FrontCase = *CR.Range.first;
1907 Case& BackCase = *(CR.Range.second-1);
1909 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1910 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1912 APInt TSize(First.getBitWidth(), 0);
1913 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1917 if (!areJTsAllowed(TLI) || TSize.ult(4))
1920 APInt Range = ComputeRange(First, Last);
1921 double Density = TSize.roundToDouble() / Range.roundToDouble();
1925 DEBUG(dbgs() << "Lowering jump table\n"
1926 << "First entry: " << First << ". Last entry: " << Last << '\n'
1927 << "Range: " << Range
1928 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1930 // Get the MachineFunction which holds the current MBB. This is used when
1931 // inserting any additional MBBs necessary to represent the switch.
1932 MachineFunction *CurMF = FuncInfo.MF;
1934 // Figure out which block is immediately after the current one.
1935 MachineFunction::iterator BBI = CR.CaseBB;
1938 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1940 // Create a new basic block to hold the code for loading the address
1941 // of the jump table, and jumping to it. Update successor information;
1942 // we will either branch to the default case for the switch, or the jump
1944 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1945 CurMF->insert(BBI, JumpTableBB);
1946 CR.CaseBB->addSuccessor(Default);
1947 CR.CaseBB->addSuccessor(JumpTableBB);
1949 // Build a vector of destination BBs, corresponding to each target
1950 // of the jump table. If the value of the jump table slot corresponds to
1951 // a case statement, push the case's BB onto the vector, otherwise, push
1953 std::vector<MachineBasicBlock*> DestBBs;
1955 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1956 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1957 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1959 if (Low.sle(TEI) && TEI.sle(High)) {
1960 DestBBs.push_back(I->BB);
1964 DestBBs.push_back(Default);
1968 // Update successor info. Add one edge to each unique successor.
1969 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1970 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1971 E = DestBBs.end(); I != E; ++I) {
1972 if (!SuccsHandled[(*I)->getNumber()]) {
1973 SuccsHandled[(*I)->getNumber()] = true;
1974 JumpTableBB->addSuccessor(*I);
1978 // Create a jump table index for this jump table.
1979 unsigned JTEncoding = TLI.getJumpTableEncoding();
1980 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1981 ->createJumpTableIndex(DestBBs);
1983 // Set the jump table information so that we can codegen it as a second
1984 // MachineBasicBlock
1985 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1986 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1987 if (CR.CaseBB == SwitchBB)
1988 visitJumpTableHeader(JT, JTH, SwitchBB);
1990 JTCases.push_back(JumpTableBlock(JTH, JT));
1995 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1997 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1998 CaseRecVector& WorkList,
2000 MachineBasicBlock *Default,
2001 MachineBasicBlock *SwitchBB) {
2002 // Get the MachineFunction which holds the current MBB. This is used when
2003 // inserting any additional MBBs necessary to represent the switch.
2004 MachineFunction *CurMF = FuncInfo.MF;
2006 // Figure out which block is immediately after the current one.
2007 MachineFunction::iterator BBI = CR.CaseBB;
2010 Case& FrontCase = *CR.Range.first;
2011 Case& BackCase = *(CR.Range.second-1);
2012 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2014 // Size is the number of Cases represented by this range.
2015 unsigned Size = CR.Range.second - CR.Range.first;
2017 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2018 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2020 CaseItr Pivot = CR.Range.first + Size/2;
2022 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2023 // (heuristically) allow us to emit JumpTable's later.
2024 APInt TSize(First.getBitWidth(), 0);
2025 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2029 APInt LSize = FrontCase.size();
2030 APInt RSize = TSize-LSize;
2031 DEBUG(dbgs() << "Selecting best pivot: \n"
2032 << "First: " << First << ", Last: " << Last <<'\n'
2033 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2034 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2036 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2037 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2038 APInt Range = ComputeRange(LEnd, RBegin);
2039 assert((Range - 2ULL).isNonNegative() &&
2040 "Invalid case distance");
2041 // Use volatile double here to avoid excess precision issues on some hosts,
2042 // e.g. that use 80-bit X87 registers.
2043 volatile double LDensity =
2044 (double)LSize.roundToDouble() /
2045 (LEnd - First + 1ULL).roundToDouble();
2046 volatile double RDensity =
2047 (double)RSize.roundToDouble() /
2048 (Last - RBegin + 1ULL).roundToDouble();
2049 double Metric = Range.logBase2()*(LDensity+RDensity);
2050 // Should always split in some non-trivial place
2051 DEBUG(dbgs() <<"=>Step\n"
2052 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2053 << "LDensity: " << LDensity
2054 << ", RDensity: " << RDensity << '\n'
2055 << "Metric: " << Metric << '\n');
2056 if (FMetric < Metric) {
2059 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2065 if (areJTsAllowed(TLI)) {
2066 // If our case is dense we *really* should handle it earlier!
2067 assert((FMetric > 0) && "Should handle dense range earlier!");
2069 Pivot = CR.Range.first + Size/2;
2072 CaseRange LHSR(CR.Range.first, Pivot);
2073 CaseRange RHSR(Pivot, CR.Range.second);
2074 Constant *C = Pivot->Low;
2075 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2077 // We know that we branch to the LHS if the Value being switched on is
2078 // less than the Pivot value, C. We use this to optimize our binary
2079 // tree a bit, by recognizing that if SV is greater than or equal to the
2080 // LHS's Case Value, and that Case Value is exactly one less than the
2081 // Pivot's Value, then we can branch directly to the LHS's Target,
2082 // rather than creating a leaf node for it.
2083 if ((LHSR.second - LHSR.first) == 1 &&
2084 LHSR.first->High == CR.GE &&
2085 cast<ConstantInt>(C)->getValue() ==
2086 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2087 TrueBB = LHSR.first->BB;
2089 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2090 CurMF->insert(BBI, TrueBB);
2091 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2093 // Put SV in a virtual register to make it available from the new blocks.
2094 ExportFromCurrentBlock(SV);
2097 // Similar to the optimization above, if the Value being switched on is
2098 // known to be less than the Constant CR.LT, and the current Case Value
2099 // is CR.LT - 1, then we can branch directly to the target block for
2100 // the current Case Value, rather than emitting a RHS leaf node for it.
2101 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2102 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2103 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2104 FalseBB = RHSR.first->BB;
2106 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2107 CurMF->insert(BBI, FalseBB);
2108 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2110 // Put SV in a virtual register to make it available from the new blocks.
2111 ExportFromCurrentBlock(SV);
2114 // Create a CaseBlock record representing a conditional branch to
2115 // the LHS node if the value being switched on SV is less than C.
2116 // Otherwise, branch to LHS.
2117 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2119 if (CR.CaseBB == SwitchBB)
2120 visitSwitchCase(CB, SwitchBB);
2122 SwitchCases.push_back(CB);
2127 /// handleBitTestsSwitchCase - if current case range has few destination and
2128 /// range span less, than machine word bitwidth, encode case range into series
2129 /// of masks and emit bit tests with these masks.
2130 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2131 CaseRecVector& WorkList,
2133 MachineBasicBlock* Default,
2134 MachineBasicBlock *SwitchBB){
2135 EVT PTy = TLI.getPointerTy();
2136 unsigned IntPtrBits = PTy.getSizeInBits();
2138 Case& FrontCase = *CR.Range.first;
2139 Case& BackCase = *(CR.Range.second-1);
2141 // Get the MachineFunction which holds the current MBB. This is used when
2142 // inserting any additional MBBs necessary to represent the switch.
2143 MachineFunction *CurMF = FuncInfo.MF;
2145 // If target does not have legal shift left, do not emit bit tests at all.
2146 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2150 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2152 // Single case counts one, case range - two.
2153 numCmps += (I->Low == I->High ? 1 : 2);
2156 // Count unique destinations
2157 SmallSet<MachineBasicBlock*, 4> Dests;
2158 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2159 Dests.insert(I->BB);
2160 if (Dests.size() > 3)
2161 // Don't bother the code below, if there are too much unique destinations
2164 DEBUG(dbgs() << "Total number of unique destinations: "
2165 << Dests.size() << '\n'
2166 << "Total number of comparisons: " << numCmps << '\n');
2168 // Compute span of values.
2169 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2170 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2171 APInt cmpRange = maxValue - minValue;
2173 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2174 << "Low bound: " << minValue << '\n'
2175 << "High bound: " << maxValue << '\n');
2177 if (cmpRange.uge(IntPtrBits) ||
2178 (!(Dests.size() == 1 && numCmps >= 3) &&
2179 !(Dests.size() == 2 && numCmps >= 5) &&
2180 !(Dests.size() >= 3 && numCmps >= 6)))
2183 DEBUG(dbgs() << "Emitting bit tests\n");
2184 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2186 // Optimize the case where all the case values fit in a
2187 // word without having to subtract minValue. In this case,
2188 // we can optimize away the subtraction.
2189 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2190 cmpRange = maxValue;
2192 lowBound = minValue;
2195 CaseBitsVector CasesBits;
2196 unsigned i, count = 0;
2198 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2199 MachineBasicBlock* Dest = I->BB;
2200 for (i = 0; i < count; ++i)
2201 if (Dest == CasesBits[i].BB)
2205 assert((count < 3) && "Too much destinations to test!");
2206 CasesBits.push_back(CaseBits(0, Dest, 0));
2210 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2211 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2213 uint64_t lo = (lowValue - lowBound).getZExtValue();
2214 uint64_t hi = (highValue - lowBound).getZExtValue();
2216 for (uint64_t j = lo; j <= hi; j++) {
2217 CasesBits[i].Mask |= 1ULL << j;
2218 CasesBits[i].Bits++;
2222 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2226 // Figure out which block is immediately after the current one.
2227 MachineFunction::iterator BBI = CR.CaseBB;
2230 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2232 DEBUG(dbgs() << "Cases:\n");
2233 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2234 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2235 << ", Bits: " << CasesBits[i].Bits
2236 << ", BB: " << CasesBits[i].BB << '\n');
2238 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2239 CurMF->insert(BBI, CaseBB);
2240 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2244 // Put SV in a virtual register to make it available from the new blocks.
2245 ExportFromCurrentBlock(SV);
2248 BitTestBlock BTB(lowBound, cmpRange, SV,
2249 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2250 CR.CaseBB, Default, BTC);
2252 if (CR.CaseBB == SwitchBB)
2253 visitBitTestHeader(BTB, SwitchBB);
2255 BitTestCases.push_back(BTB);
2260 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2261 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2262 const SwitchInst& SI) {
2265 // Start with "simple" cases
2266 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2267 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2268 Cases.push_back(Case(SI.getSuccessorValue(i),
2269 SI.getSuccessorValue(i),
2272 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2274 // Merge case into clusters
2275 if (Cases.size() >= 2)
2276 // Must recompute end() each iteration because it may be
2277 // invalidated by erase if we hold on to it
2278 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2279 J != Cases.end(); ) {
2280 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2281 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2282 MachineBasicBlock* nextBB = J->BB;
2283 MachineBasicBlock* currentBB = I->BB;
2285 // If the two neighboring cases go to the same destination, merge them
2286 // into a single case.
2287 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2295 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2296 if (I->Low != I->High)
2297 // A range counts double, since it requires two compares.
2304 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2305 MachineBasicBlock *Last) {
2307 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2308 if (JTCases[i].first.HeaderBB == First)
2309 JTCases[i].first.HeaderBB = Last;
2311 // Update BitTestCases.
2312 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2313 if (BitTestCases[i].Parent == First)
2314 BitTestCases[i].Parent = Last;
2317 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2318 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2320 // Figure out which block is immediately after the current one.
2321 MachineBasicBlock *NextBlock = 0;
2322 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2324 // If there is only the default destination, branch to it if it is not the
2325 // next basic block. Otherwise, just fall through.
2326 if (SI.getNumOperands() == 2) {
2327 // Update machine-CFG edges.
2329 // If this is not a fall-through branch, emit the branch.
2330 SwitchMBB->addSuccessor(Default);
2331 if (Default != NextBlock)
2332 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2333 MVT::Other, getControlRoot(),
2334 DAG.getBasicBlock(Default)));
2339 // If there are any non-default case statements, create a vector of Cases
2340 // representing each one, and sort the vector so that we can efficiently
2341 // create a binary search tree from them.
2343 size_t numCmps = Clusterify(Cases, SI);
2344 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2345 << ". Total compares: " << numCmps << '\n');
2348 // Get the Value to be switched on and default basic blocks, which will be
2349 // inserted into CaseBlock records, representing basic blocks in the binary
2351 const Value *SV = SI.getOperand(0);
2353 // Push the initial CaseRec onto the worklist
2354 CaseRecVector WorkList;
2355 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2356 CaseRange(Cases.begin(),Cases.end())));
2358 while (!WorkList.empty()) {
2359 // Grab a record representing a case range to process off the worklist
2360 CaseRec CR = WorkList.back();
2361 WorkList.pop_back();
2363 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2366 // If the range has few cases (two or less) emit a series of specific
2368 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2371 // If the switch has more than 5 blocks, and at least 40% dense, and the
2372 // target supports indirect branches, then emit a jump table rather than
2373 // lowering the switch to a binary tree of conditional branches.
2374 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2377 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2378 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2379 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2383 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2384 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2386 // Update machine-CFG edges with unique successors.
2387 SmallVector<BasicBlock*, 32> succs;
2388 succs.reserve(I.getNumSuccessors());
2389 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2390 succs.push_back(I.getSuccessor(i));
2391 array_pod_sort(succs.begin(), succs.end());
2392 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2393 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2394 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2396 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2397 MVT::Other, getControlRoot(),
2398 getValue(I.getAddress())));
2401 void SelectionDAGBuilder::visitFSub(const User &I) {
2402 // -0.0 - X --> fneg
2403 const Type *Ty = I.getType();
2404 if (isa<Constant>(I.getOperand(0)) &&
2405 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2406 SDValue Op2 = getValue(I.getOperand(1));
2407 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2408 Op2.getValueType(), Op2));
2412 visitBinary(I, ISD::FSUB);
2415 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2416 SDValue Op1 = getValue(I.getOperand(0));
2417 SDValue Op2 = getValue(I.getOperand(1));
2418 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2419 Op1.getValueType(), Op1, Op2));
2422 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2423 SDValue Op1 = getValue(I.getOperand(0));
2424 SDValue Op2 = getValue(I.getOperand(1));
2426 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2428 // Coerce the shift amount to the right type if we can.
2429 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2430 unsigned ShiftSize = ShiftTy.getSizeInBits();
2431 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2432 DebugLoc DL = getCurDebugLoc();
2434 // If the operand is smaller than the shift count type, promote it.
2435 if (ShiftSize > Op2Size)
2436 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2438 // If the operand is larger than the shift count type but the shift
2439 // count type has enough bits to represent any shift value, truncate
2440 // it now. This is a common case and it exposes the truncate to
2441 // optimization early.
2442 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2443 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2444 // Otherwise we'll need to temporarily settle for some other convenient
2445 // type. Type legalization will make adjustments once the shiftee is split.
2447 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2450 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2451 Op1.getValueType(), Op1, Op2));
2454 void SelectionDAGBuilder::visitICmp(const User &I) {
2455 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2456 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2457 predicate = IC->getPredicate();
2458 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2459 predicate = ICmpInst::Predicate(IC->getPredicate());
2460 SDValue Op1 = getValue(I.getOperand(0));
2461 SDValue Op2 = getValue(I.getOperand(1));
2462 ISD::CondCode Opcode = getICmpCondCode(predicate);
2464 EVT DestVT = TLI.getValueType(I.getType());
2465 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2468 void SelectionDAGBuilder::visitFCmp(const User &I) {
2469 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2470 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2471 predicate = FC->getPredicate();
2472 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2473 predicate = FCmpInst::Predicate(FC->getPredicate());
2474 SDValue Op1 = getValue(I.getOperand(0));
2475 SDValue Op2 = getValue(I.getOperand(1));
2476 ISD::CondCode Condition = getFCmpCondCode(predicate);
2477 EVT DestVT = TLI.getValueType(I.getType());
2478 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2481 void SelectionDAGBuilder::visitSelect(const User &I) {
2482 SmallVector<EVT, 4> ValueVTs;
2483 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2484 unsigned NumValues = ValueVTs.size();
2485 if (NumValues == 0) return;
2487 SmallVector<SDValue, 4> Values(NumValues);
2488 SDValue Cond = getValue(I.getOperand(0));
2489 SDValue TrueVal = getValue(I.getOperand(1));
2490 SDValue FalseVal = getValue(I.getOperand(2));
2492 for (unsigned i = 0; i != NumValues; ++i)
2493 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2494 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2496 SDValue(TrueVal.getNode(),
2497 TrueVal.getResNo() + i),
2498 SDValue(FalseVal.getNode(),
2499 FalseVal.getResNo() + i));
2501 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2502 DAG.getVTList(&ValueVTs[0], NumValues),
2503 &Values[0], NumValues));
2506 void SelectionDAGBuilder::visitTrunc(const User &I) {
2507 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2508 SDValue N = getValue(I.getOperand(0));
2509 EVT DestVT = TLI.getValueType(I.getType());
2510 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2513 void SelectionDAGBuilder::visitZExt(const User &I) {
2514 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2515 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2516 SDValue N = getValue(I.getOperand(0));
2517 EVT DestVT = TLI.getValueType(I.getType());
2518 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2521 void SelectionDAGBuilder::visitSExt(const User &I) {
2522 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2523 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2524 SDValue N = getValue(I.getOperand(0));
2525 EVT DestVT = TLI.getValueType(I.getType());
2526 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2529 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2530 // FPTrunc is never a no-op cast, no need to check
2531 SDValue N = getValue(I.getOperand(0));
2532 EVT DestVT = TLI.getValueType(I.getType());
2533 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2534 DestVT, N, DAG.getIntPtrConstant(0)));
2537 void SelectionDAGBuilder::visitFPExt(const User &I){
2538 // FPTrunc is never a no-op cast, no need to check
2539 SDValue N = getValue(I.getOperand(0));
2540 EVT DestVT = TLI.getValueType(I.getType());
2541 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2544 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2545 // FPToUI is never a no-op cast, no need to check
2546 SDValue N = getValue(I.getOperand(0));
2547 EVT DestVT = TLI.getValueType(I.getType());
2548 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2551 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2552 // FPToSI is never a no-op cast, no need to check
2553 SDValue N = getValue(I.getOperand(0));
2554 EVT DestVT = TLI.getValueType(I.getType());
2555 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2558 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2559 // UIToFP is never a no-op cast, no need to check
2560 SDValue N = getValue(I.getOperand(0));
2561 EVT DestVT = TLI.getValueType(I.getType());
2562 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2565 void SelectionDAGBuilder::visitSIToFP(const User &I){
2566 // SIToFP is never a no-op cast, no need to check
2567 SDValue N = getValue(I.getOperand(0));
2568 EVT DestVT = TLI.getValueType(I.getType());
2569 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2572 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2573 // What to do depends on the size of the integer and the size of the pointer.
2574 // We can either truncate, zero extend, or no-op, accordingly.
2575 SDValue N = getValue(I.getOperand(0));
2576 EVT DestVT = TLI.getValueType(I.getType());
2577 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2580 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2581 // What to do depends on the size of the integer and the size of the pointer.
2582 // We can either truncate, zero extend, or no-op, accordingly.
2583 SDValue N = getValue(I.getOperand(0));
2584 EVT DestVT = TLI.getValueType(I.getType());
2585 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2588 void SelectionDAGBuilder::visitBitCast(const User &I) {
2589 SDValue N = getValue(I.getOperand(0));
2590 EVT DestVT = TLI.getValueType(I.getType());
2592 // BitCast assures us that source and destination are the same size so this is
2593 // either a BITCAST or a no-op.
2594 if (DestVT != N.getValueType())
2595 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2596 DestVT, N)); // convert types.
2598 setValue(&I, N); // noop cast.
2601 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2602 SDValue InVec = getValue(I.getOperand(0));
2603 SDValue InVal = getValue(I.getOperand(1));
2604 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2606 getValue(I.getOperand(2)));
2607 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2608 TLI.getValueType(I.getType()),
2609 InVec, InVal, InIdx));
2612 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2613 SDValue InVec = getValue(I.getOperand(0));
2614 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2616 getValue(I.getOperand(1)));
2617 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2618 TLI.getValueType(I.getType()), InVec, InIdx));
2621 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2622 // from SIndx and increasing to the element length (undefs are allowed).
2623 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2624 unsigned MaskNumElts = Mask.size();
2625 for (unsigned i = 0; i != MaskNumElts; ++i)
2626 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2631 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2632 SmallVector<int, 8> Mask;
2633 SDValue Src1 = getValue(I.getOperand(0));
2634 SDValue Src2 = getValue(I.getOperand(1));
2636 // Convert the ConstantVector mask operand into an array of ints, with -1
2637 // representing undef values.
2638 SmallVector<Constant*, 8> MaskElts;
2639 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2640 unsigned MaskNumElts = MaskElts.size();
2641 for (unsigned i = 0; i != MaskNumElts; ++i) {
2642 if (isa<UndefValue>(MaskElts[i]))
2645 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2648 EVT VT = TLI.getValueType(I.getType());
2649 EVT SrcVT = Src1.getValueType();
2650 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2652 if (SrcNumElts == MaskNumElts) {
2653 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2658 // Normalize the shuffle vector since mask and vector length don't match.
2659 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2660 // Mask is longer than the source vectors and is a multiple of the source
2661 // vectors. We can use concatenate vector to make the mask and vectors
2663 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2664 // The shuffle is concatenating two vectors together.
2665 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2670 // Pad both vectors with undefs to make them the same length as the mask.
2671 unsigned NumConcat = MaskNumElts / SrcNumElts;
2672 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2673 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2674 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2676 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2677 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2681 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2682 getCurDebugLoc(), VT,
2683 &MOps1[0], NumConcat);
2684 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2685 getCurDebugLoc(), VT,
2686 &MOps2[0], NumConcat);
2688 // Readjust mask for new input vector length.
2689 SmallVector<int, 8> MappedOps;
2690 for (unsigned i = 0; i != MaskNumElts; ++i) {
2692 if (Idx < (int)SrcNumElts)
2693 MappedOps.push_back(Idx);
2695 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2698 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2703 if (SrcNumElts > MaskNumElts) {
2704 // Analyze the access pattern of the vector to see if we can extract
2705 // two subvectors and do the shuffle. The analysis is done by calculating
2706 // the range of elements the mask access on both vectors.
2707 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2708 int MaxRange[2] = {-1, -1};
2710 for (unsigned i = 0; i != MaskNumElts; ++i) {
2716 if (Idx >= (int)SrcNumElts) {
2720 if (Idx > MaxRange[Input])
2721 MaxRange[Input] = Idx;
2722 if (Idx < MinRange[Input])
2723 MinRange[Input] = Idx;
2726 // Check if the access is smaller than the vector size and can we find
2727 // a reasonable extract index.
2728 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2730 int StartIdx[2]; // StartIdx to extract from
2731 for (int Input=0; Input < 2; ++Input) {
2732 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2733 RangeUse[Input] = 0; // Unused
2734 StartIdx[Input] = 0;
2735 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2736 // Fits within range but we should see if we can find a good
2737 // start index that is a multiple of the mask length.
2738 if (MaxRange[Input] < (int)MaskNumElts) {
2739 RangeUse[Input] = 1; // Extract from beginning of the vector
2740 StartIdx[Input] = 0;
2742 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2743 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2744 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2745 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2750 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2751 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2754 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2755 // Extract appropriate subvector and generate a vector shuffle
2756 for (int Input=0; Input < 2; ++Input) {
2757 SDValue &Src = Input == 0 ? Src1 : Src2;
2758 if (RangeUse[Input] == 0)
2759 Src = DAG.getUNDEF(VT);
2761 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2762 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2765 // Calculate new mask.
2766 SmallVector<int, 8> MappedOps;
2767 for (unsigned i = 0; i != MaskNumElts; ++i) {
2770 MappedOps.push_back(Idx);
2771 else if (Idx < (int)SrcNumElts)
2772 MappedOps.push_back(Idx - StartIdx[0]);
2774 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2777 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2783 // We can't use either concat vectors or extract subvectors so fall back to
2784 // replacing the shuffle with extract and build vector.
2785 // to insert and build vector.
2786 EVT EltVT = VT.getVectorElementType();
2787 EVT PtrVT = TLI.getPointerTy();
2788 SmallVector<SDValue,8> Ops;
2789 for (unsigned i = 0; i != MaskNumElts; ++i) {
2791 Ops.push_back(DAG.getUNDEF(EltVT));
2796 if (Idx < (int)SrcNumElts)
2797 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2798 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2800 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2802 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2808 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2809 VT, &Ops[0], Ops.size()));
2812 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2813 const Value *Op0 = I.getOperand(0);
2814 const Value *Op1 = I.getOperand(1);
2815 const Type *AggTy = I.getType();
2816 const Type *ValTy = Op1->getType();
2817 bool IntoUndef = isa<UndefValue>(Op0);
2818 bool FromUndef = isa<UndefValue>(Op1);
2820 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2822 SmallVector<EVT, 4> AggValueVTs;
2823 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2824 SmallVector<EVT, 4> ValValueVTs;
2825 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2827 unsigned NumAggValues = AggValueVTs.size();
2828 unsigned NumValValues = ValValueVTs.size();
2829 SmallVector<SDValue, 4> Values(NumAggValues);
2831 SDValue Agg = getValue(Op0);
2833 // Copy the beginning value(s) from the original aggregate.
2834 for (; i != LinearIndex; ++i)
2835 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2836 SDValue(Agg.getNode(), Agg.getResNo() + i);
2837 // Copy values from the inserted value(s).
2839 SDValue Val = getValue(Op1);
2840 for (; i != LinearIndex + NumValValues; ++i)
2841 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2842 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2844 // Copy remaining value(s) from the original aggregate.
2845 for (; i != NumAggValues; ++i)
2846 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2847 SDValue(Agg.getNode(), Agg.getResNo() + i);
2849 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2850 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2851 &Values[0], NumAggValues));
2854 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2855 const Value *Op0 = I.getOperand(0);
2856 const Type *AggTy = Op0->getType();
2857 const Type *ValTy = I.getType();
2858 bool OutOfUndef = isa<UndefValue>(Op0);
2860 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2862 SmallVector<EVT, 4> ValValueVTs;
2863 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2865 unsigned NumValValues = ValValueVTs.size();
2867 // Ignore a extractvalue that produces an empty object
2868 if (!NumValValues) {
2869 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2873 SmallVector<SDValue, 4> Values(NumValValues);
2875 SDValue Agg = getValue(Op0);
2876 // Copy out the selected value(s).
2877 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2878 Values[i - LinearIndex] =
2880 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2881 SDValue(Agg.getNode(), Agg.getResNo() + i);
2883 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2884 DAG.getVTList(&ValValueVTs[0], NumValValues),
2885 &Values[0], NumValValues));
2888 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2889 SDValue N = getValue(I.getOperand(0));
2890 const Type *Ty = I.getOperand(0)->getType();
2892 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2894 const Value *Idx = *OI;
2895 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2896 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2899 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2900 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2901 DAG.getIntPtrConstant(Offset));
2904 Ty = StTy->getElementType(Field);
2906 Ty = cast<SequentialType>(Ty)->getElementType();
2908 // If this is a constant subscript, handle it quickly.
2909 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2910 if (CI->isZero()) continue;
2912 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2914 EVT PTy = TLI.getPointerTy();
2915 unsigned PtrBits = PTy.getSizeInBits();
2917 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2919 DAG.getConstant(Offs, MVT::i64));
2921 OffsVal = DAG.getIntPtrConstant(Offs);
2923 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2928 // N = N + Idx * ElementSize;
2929 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2930 TD->getTypeAllocSize(Ty));
2931 SDValue IdxN = getValue(Idx);
2933 // If the index is smaller or larger than intptr_t, truncate or extend
2935 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2937 // If this is a multiply by a power of two, turn it into a shl
2938 // immediately. This is a very common case.
2939 if (ElementSize != 1) {
2940 if (ElementSize.isPowerOf2()) {
2941 unsigned Amt = ElementSize.logBase2();
2942 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2943 N.getValueType(), IdxN,
2944 DAG.getConstant(Amt, TLI.getPointerTy()));
2946 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2947 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2948 N.getValueType(), IdxN, Scale);
2952 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2953 N.getValueType(), N, IdxN);
2960 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2961 // If this is a fixed sized alloca in the entry block of the function,
2962 // allocate it statically on the stack.
2963 if (FuncInfo.StaticAllocaMap.count(&I))
2964 return; // getValue will auto-populate this.
2966 const Type *Ty = I.getAllocatedType();
2967 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2969 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2972 SDValue AllocSize = getValue(I.getArraySize());
2974 EVT IntPtr = TLI.getPointerTy();
2975 if (AllocSize.getValueType() != IntPtr)
2976 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2978 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2980 DAG.getConstant(TySize, IntPtr));
2982 // Handle alignment. If the requested alignment is less than or equal to
2983 // the stack alignment, ignore it. If the size is greater than or equal to
2984 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2985 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2986 if (Align <= StackAlign)
2989 // Round the size of the allocation up to the stack alignment size
2990 // by add SA-1 to the size.
2991 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2992 AllocSize.getValueType(), AllocSize,
2993 DAG.getIntPtrConstant(StackAlign-1));
2995 // Mask out the low bits for alignment purposes.
2996 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2997 AllocSize.getValueType(), AllocSize,
2998 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3000 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3001 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3002 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3005 DAG.setRoot(DSA.getValue(1));
3007 // Inform the Frame Information that we have just allocated a variable-sized
3009 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3012 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3013 const Value *SV = I.getOperand(0);
3014 SDValue Ptr = getValue(SV);
3016 const Type *Ty = I.getType();
3018 bool isVolatile = I.isVolatile();
3019 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3020 unsigned Alignment = I.getAlignment();
3021 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3023 SmallVector<EVT, 4> ValueVTs;
3024 SmallVector<uint64_t, 4> Offsets;
3025 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3026 unsigned NumValues = ValueVTs.size();
3031 bool ConstantMemory = false;
3032 if (I.isVolatile() || NumValues > MaxParallelChains)
3033 // Serialize volatile loads with other side effects.
3035 else if (AA->pointsToConstantMemory(
3036 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3037 // Do not serialize (non-volatile) loads of constant memory with anything.
3038 Root = DAG.getEntryNode();
3039 ConstantMemory = true;
3041 // Do not serialize non-volatile loads against each other.
3042 Root = DAG.getRoot();
3045 SmallVector<SDValue, 4> Values(NumValues);
3046 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3048 EVT PtrVT = Ptr.getValueType();
3049 unsigned ChainI = 0;
3050 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3051 // Serializing loads here may result in excessive register pressure, and
3052 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3053 // could recover a bit by hoisting nodes upward in the chain by recognizing
3054 // they are side-effect free or do not alias. The optimizer should really
3055 // avoid this case by converting large object/array copies to llvm.memcpy
3056 // (MaxParallelChains should always remain as failsafe).
3057 if (ChainI == MaxParallelChains) {
3058 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3059 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3060 MVT::Other, &Chains[0], ChainI);
3064 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3066 DAG.getConstant(Offsets[i], PtrVT));
3067 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3068 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3069 isNonTemporal, Alignment, TBAAInfo);
3072 Chains[ChainI] = L.getValue(1);
3075 if (!ConstantMemory) {
3076 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3077 MVT::Other, &Chains[0], ChainI);
3081 PendingLoads.push_back(Chain);
3084 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3085 DAG.getVTList(&ValueVTs[0], NumValues),
3086 &Values[0], NumValues));
3089 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3090 const Value *SrcV = I.getOperand(0);
3091 const Value *PtrV = I.getOperand(1);
3093 SmallVector<EVT, 4> ValueVTs;
3094 SmallVector<uint64_t, 4> Offsets;
3095 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3096 unsigned NumValues = ValueVTs.size();
3100 // Get the lowered operands. Note that we do this after
3101 // checking if NumResults is zero, because with zero results
3102 // the operands won't have values in the map.
3103 SDValue Src = getValue(SrcV);
3104 SDValue Ptr = getValue(PtrV);
3106 SDValue Root = getRoot();
3107 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3109 EVT PtrVT = Ptr.getValueType();
3110 bool isVolatile = I.isVolatile();
3111 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3112 unsigned Alignment = I.getAlignment();
3113 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3115 unsigned ChainI = 0;
3116 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3117 // See visitLoad comments.
3118 if (ChainI == MaxParallelChains) {
3119 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3120 MVT::Other, &Chains[0], ChainI);
3124 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3125 DAG.getConstant(Offsets[i], PtrVT));
3126 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3127 SDValue(Src.getNode(), Src.getResNo() + i),
3128 Add, MachinePointerInfo(PtrV, Offsets[i]),
3129 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3130 Chains[ChainI] = St;
3133 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3134 MVT::Other, &Chains[0], ChainI);
3136 AssignOrderingToNode(StoreNode.getNode());
3137 DAG.setRoot(StoreNode);
3140 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3142 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3143 unsigned Intrinsic) {
3144 bool HasChain = !I.doesNotAccessMemory();
3145 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3147 // Build the operand list.
3148 SmallVector<SDValue, 8> Ops;
3149 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3151 // We don't need to serialize loads against other loads.
3152 Ops.push_back(DAG.getRoot());
3154 Ops.push_back(getRoot());
3158 // Info is set by getTgtMemInstrinsic
3159 TargetLowering::IntrinsicInfo Info;
3160 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3162 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3163 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3164 Info.opc == ISD::INTRINSIC_W_CHAIN)
3165 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3167 // Add all operands of the call to the operand list.
3168 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3169 SDValue Op = getValue(I.getArgOperand(i));
3170 assert(TLI.isTypeLegal(Op.getValueType()) &&
3171 "Intrinsic uses a non-legal type?");
3175 SmallVector<EVT, 4> ValueVTs;
3176 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3178 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3179 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3180 "Intrinsic uses a non-legal type?");
3185 ValueVTs.push_back(MVT::Other);
3187 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3191 if (IsTgtIntrinsic) {
3192 // This is target intrinsic that touches memory
3193 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3194 VTs, &Ops[0], Ops.size(),
3196 MachinePointerInfo(Info.ptrVal, Info.offset),
3197 Info.align, Info.vol,
3198 Info.readMem, Info.writeMem);
3199 } else if (!HasChain) {
3200 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3201 VTs, &Ops[0], Ops.size());
3202 } else if (!I.getType()->isVoidTy()) {
3203 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3204 VTs, &Ops[0], Ops.size());
3206 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3207 VTs, &Ops[0], Ops.size());
3211 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3213 PendingLoads.push_back(Chain);
3218 if (!I.getType()->isVoidTy()) {
3219 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3220 EVT VT = TLI.getValueType(PTy);
3221 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3224 setValue(&I, Result);
3228 /// GetSignificand - Get the significand and build it into a floating-point
3229 /// number with exponent of 1:
3231 /// Op = (Op & 0x007fffff) | 0x3f800000;
3233 /// where Op is the hexidecimal representation of floating point value.
3235 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3236 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3237 DAG.getConstant(0x007fffff, MVT::i32));
3238 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3239 DAG.getConstant(0x3f800000, MVT::i32));
3240 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3243 /// GetExponent - Get the exponent:
3245 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3247 /// where Op is the hexidecimal representation of floating point value.
3249 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3251 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3252 DAG.getConstant(0x7f800000, MVT::i32));
3253 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3254 DAG.getConstant(23, TLI.getPointerTy()));
3255 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3256 DAG.getConstant(127, MVT::i32));
3257 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3260 /// getF32Constant - Get 32-bit floating point constant.
3262 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3263 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3266 /// Inlined utility function to implement binary input atomic intrinsics for
3267 /// visitIntrinsicCall: I is a call instruction
3268 /// Op is the associated NodeType for I
3270 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3272 SDValue Root = getRoot();
3274 DAG.getAtomic(Op, getCurDebugLoc(),
3275 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3277 getValue(I.getArgOperand(0)),
3278 getValue(I.getArgOperand(1)),
3279 I.getArgOperand(0));
3281 DAG.setRoot(L.getValue(1));
3285 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3287 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3288 SDValue Op1 = getValue(I.getArgOperand(0));
3289 SDValue Op2 = getValue(I.getArgOperand(1));
3291 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3292 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3296 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3297 /// limited-precision mode.
3299 SelectionDAGBuilder::visitExp(const CallInst &I) {
3301 DebugLoc dl = getCurDebugLoc();
3303 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3304 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3305 SDValue Op = getValue(I.getArgOperand(0));
3307 // Put the exponent in the right bit position for later addition to the
3310 // #define LOG2OFe 1.4426950f
3311 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3312 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3313 getF32Constant(DAG, 0x3fb8aa3b));
3314 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3316 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3317 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3318 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3320 // IntegerPartOfX <<= 23;
3321 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3322 DAG.getConstant(23, TLI.getPointerTy()));
3324 if (LimitFloatPrecision <= 6) {
3325 // For floating-point precision of 6:
3327 // TwoToFractionalPartOfX =
3329 // (0.735607626f + 0.252464424f * x) * x;
3331 // error 0.0144103317, which is 6 bits
3332 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3333 getF32Constant(DAG, 0x3e814304));
3334 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3335 getF32Constant(DAG, 0x3f3c50c8));
3336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3337 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3338 getF32Constant(DAG, 0x3f7f5e7e));
3339 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3341 // Add the exponent into the result in integer domain.
3342 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3343 TwoToFracPartOfX, IntegerPartOfX);
3345 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3346 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3347 // For floating-point precision of 12:
3349 // TwoToFractionalPartOfX =
3352 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3354 // 0.000107046256 error, which is 13 to 14 bits
3355 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3356 getF32Constant(DAG, 0x3da235e3));
3357 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3358 getF32Constant(DAG, 0x3e65b8f3));
3359 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3360 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3361 getF32Constant(DAG, 0x3f324b07));
3362 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3363 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3364 getF32Constant(DAG, 0x3f7ff8fd));
3365 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3367 // Add the exponent into the result in integer domain.
3368 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3369 TwoToFracPartOfX, IntegerPartOfX);
3371 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3372 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3373 // For floating-point precision of 18:
3375 // TwoToFractionalPartOfX =
3379 // (0.554906021e-1f +
3380 // (0.961591928e-2f +
3381 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3383 // error 2.47208000*10^(-7), which is better than 18 bits
3384 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3385 getF32Constant(DAG, 0x3924b03e));
3386 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3387 getF32Constant(DAG, 0x3ab24b87));
3388 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3389 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3390 getF32Constant(DAG, 0x3c1d8c17));
3391 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3392 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3393 getF32Constant(DAG, 0x3d634a1d));
3394 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3395 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3396 getF32Constant(DAG, 0x3e75fe14));
3397 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3398 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3399 getF32Constant(DAG, 0x3f317234));
3400 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3401 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3402 getF32Constant(DAG, 0x3f800000));
3403 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3406 // Add the exponent into the result in integer domain.
3407 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3408 TwoToFracPartOfX, IntegerPartOfX);
3410 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3413 // No special expansion.
3414 result = DAG.getNode(ISD::FEXP, dl,
3415 getValue(I.getArgOperand(0)).getValueType(),
3416 getValue(I.getArgOperand(0)));
3419 setValue(&I, result);
3422 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3423 /// limited-precision mode.
3425 SelectionDAGBuilder::visitLog(const CallInst &I) {
3427 DebugLoc dl = getCurDebugLoc();
3429 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3430 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3431 SDValue Op = getValue(I.getArgOperand(0));
3432 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3434 // Scale the exponent by log(2) [0.69314718f].
3435 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3436 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3437 getF32Constant(DAG, 0x3f317218));
3439 // Get the significand and build it into a floating-point number with
3441 SDValue X = GetSignificand(DAG, Op1, dl);
3443 if (LimitFloatPrecision <= 6) {
3444 // For floating-point precision of 6:
3448 // (1.4034025f - 0.23903021f * x) * x;
3450 // error 0.0034276066, which is better than 8 bits
3451 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3452 getF32Constant(DAG, 0xbe74c456));
3453 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3454 getF32Constant(DAG, 0x3fb3a2b1));
3455 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3456 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3457 getF32Constant(DAG, 0x3f949a29));
3459 result = DAG.getNode(ISD::FADD, dl,
3460 MVT::f32, LogOfExponent, LogOfMantissa);
3461 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3462 // For floating-point precision of 12:
3468 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3470 // error 0.000061011436, which is 14 bits
3471 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3472 getF32Constant(DAG, 0xbd67b6d6));
3473 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3474 getF32Constant(DAG, 0x3ee4f4b8));
3475 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3476 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3477 getF32Constant(DAG, 0x3fbc278b));
3478 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3479 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3480 getF32Constant(DAG, 0x40348e95));
3481 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3482 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3483 getF32Constant(DAG, 0x3fdef31a));
3485 result = DAG.getNode(ISD::FADD, dl,
3486 MVT::f32, LogOfExponent, LogOfMantissa);
3487 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3488 // For floating-point precision of 18:
3496 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3498 // error 0.0000023660568, which is better than 18 bits
3499 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3500 getF32Constant(DAG, 0xbc91e5ac));
3501 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3502 getF32Constant(DAG, 0x3e4350aa));
3503 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3504 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3505 getF32Constant(DAG, 0x3f60d3e3));
3506 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3507 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3508 getF32Constant(DAG, 0x4011cdf0));
3509 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3510 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3511 getF32Constant(DAG, 0x406cfd1c));
3512 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3513 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3514 getF32Constant(DAG, 0x408797cb));
3515 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3516 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3517 getF32Constant(DAG, 0x4006dcab));
3519 result = DAG.getNode(ISD::FADD, dl,
3520 MVT::f32, LogOfExponent, LogOfMantissa);
3523 // No special expansion.
3524 result = DAG.getNode(ISD::FLOG, dl,
3525 getValue(I.getArgOperand(0)).getValueType(),
3526 getValue(I.getArgOperand(0)));
3529 setValue(&I, result);
3532 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3533 /// limited-precision mode.
3535 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3537 DebugLoc dl = getCurDebugLoc();
3539 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3540 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3541 SDValue Op = getValue(I.getArgOperand(0));
3542 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3544 // Get the exponent.
3545 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3547 // Get the significand and build it into a floating-point number with
3549 SDValue X = GetSignificand(DAG, Op1, dl);
3551 // Different possible minimax approximations of significand in
3552 // floating-point for various degrees of accuracy over [1,2].
3553 if (LimitFloatPrecision <= 6) {
3554 // For floating-point precision of 6:
3556 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3558 // error 0.0049451742, which is more than 7 bits
3559 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3560 getF32Constant(DAG, 0xbeb08fe0));
3561 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3562 getF32Constant(DAG, 0x40019463));
3563 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3564 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3565 getF32Constant(DAG, 0x3fd6633d));
3567 result = DAG.getNode(ISD::FADD, dl,
3568 MVT::f32, LogOfExponent, Log2ofMantissa);
3569 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3570 // For floating-point precision of 12:
3576 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3578 // error 0.0000876136000, which is better than 13 bits
3579 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3580 getF32Constant(DAG, 0xbda7262e));
3581 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3582 getF32Constant(DAG, 0x3f25280b));
3583 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3584 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3585 getF32Constant(DAG, 0x4007b923));
3586 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3587 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3588 getF32Constant(DAG, 0x40823e2f));
3589 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3590 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3591 getF32Constant(DAG, 0x4020d29c));
3593 result = DAG.getNode(ISD::FADD, dl,
3594 MVT::f32, LogOfExponent, Log2ofMantissa);
3595 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3596 // For floating-point precision of 18:
3605 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3607 // error 0.0000018516, which is better than 18 bits
3608 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3609 getF32Constant(DAG, 0xbcd2769e));
3610 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3611 getF32Constant(DAG, 0x3e8ce0b9));
3612 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3613 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3614 getF32Constant(DAG, 0x3fa22ae7));
3615 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3616 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3617 getF32Constant(DAG, 0x40525723));
3618 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3619 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3620 getF32Constant(DAG, 0x40aaf200));
3621 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3622 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3623 getF32Constant(DAG, 0x40c39dad));
3624 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3625 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3626 getF32Constant(DAG, 0x4042902c));
3628 result = DAG.getNode(ISD::FADD, dl,
3629 MVT::f32, LogOfExponent, Log2ofMantissa);
3632 // No special expansion.
3633 result = DAG.getNode(ISD::FLOG2, dl,
3634 getValue(I.getArgOperand(0)).getValueType(),
3635 getValue(I.getArgOperand(0)));
3638 setValue(&I, result);
3641 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3642 /// limited-precision mode.
3644 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3646 DebugLoc dl = getCurDebugLoc();
3648 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3649 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3650 SDValue Op = getValue(I.getArgOperand(0));
3651 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3653 // Scale the exponent by log10(2) [0.30102999f].
3654 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3655 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3656 getF32Constant(DAG, 0x3e9a209a));
3658 // Get the significand and build it into a floating-point number with
3660 SDValue X = GetSignificand(DAG, Op1, dl);
3662 if (LimitFloatPrecision <= 6) {
3663 // For floating-point precision of 6:
3665 // Log10ofMantissa =
3667 // (0.60948995f - 0.10380950f * x) * x;
3669 // error 0.0014886165, which is 6 bits
3670 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3671 getF32Constant(DAG, 0xbdd49a13));
3672 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3673 getF32Constant(DAG, 0x3f1c0789));
3674 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3675 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3676 getF32Constant(DAG, 0x3f011300));
3678 result = DAG.getNode(ISD::FADD, dl,
3679 MVT::f32, LogOfExponent, Log10ofMantissa);
3680 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3681 // For floating-point precision of 12:
3683 // Log10ofMantissa =
3686 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3688 // error 0.00019228036, which is better than 12 bits
3689 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3690 getF32Constant(DAG, 0x3d431f31));
3691 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3692 getF32Constant(DAG, 0x3ea21fb2));
3693 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3694 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3695 getF32Constant(DAG, 0x3f6ae232));
3696 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3697 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3698 getF32Constant(DAG, 0x3f25f7c3));
3700 result = DAG.getNode(ISD::FADD, dl,
3701 MVT::f32, LogOfExponent, Log10ofMantissa);
3702 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3703 // For floating-point precision of 18:
3705 // Log10ofMantissa =
3710 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3712 // error 0.0000037995730, which is better than 18 bits
3713 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3714 getF32Constant(DAG, 0x3c5d51ce));
3715 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3716 getF32Constant(DAG, 0x3e00685a));
3717 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3718 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3719 getF32Constant(DAG, 0x3efb6798));
3720 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3721 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3722 getF32Constant(DAG, 0x3f88d192));
3723 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3724 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3725 getF32Constant(DAG, 0x3fc4316c));
3726 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3727 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3728 getF32Constant(DAG, 0x3f57ce70));
3730 result = DAG.getNode(ISD::FADD, dl,
3731 MVT::f32, LogOfExponent, Log10ofMantissa);
3734 // No special expansion.
3735 result = DAG.getNode(ISD::FLOG10, dl,
3736 getValue(I.getArgOperand(0)).getValueType(),
3737 getValue(I.getArgOperand(0)));
3740 setValue(&I, result);
3743 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3744 /// limited-precision mode.
3746 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3748 DebugLoc dl = getCurDebugLoc();
3750 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3751 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3752 SDValue Op = getValue(I.getArgOperand(0));
3754 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3756 // FractionalPartOfX = x - (float)IntegerPartOfX;
3757 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3758 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3760 // IntegerPartOfX <<= 23;
3761 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3762 DAG.getConstant(23, TLI.getPointerTy()));
3764 if (LimitFloatPrecision <= 6) {
3765 // For floating-point precision of 6:
3767 // TwoToFractionalPartOfX =
3769 // (0.735607626f + 0.252464424f * x) * x;
3771 // error 0.0144103317, which is 6 bits
3772 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3773 getF32Constant(DAG, 0x3e814304));
3774 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3775 getF32Constant(DAG, 0x3f3c50c8));
3776 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3777 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3778 getF32Constant(DAG, 0x3f7f5e7e));
3779 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3780 SDValue TwoToFractionalPartOfX =
3781 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3783 result = DAG.getNode(ISD::BITCAST, dl,
3784 MVT::f32, TwoToFractionalPartOfX);
3785 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3786 // For floating-point precision of 12:
3788 // TwoToFractionalPartOfX =
3791 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3793 // error 0.000107046256, which is 13 to 14 bits
3794 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3795 getF32Constant(DAG, 0x3da235e3));
3796 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3797 getF32Constant(DAG, 0x3e65b8f3));
3798 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3799 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3800 getF32Constant(DAG, 0x3f324b07));
3801 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3802 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3803 getF32Constant(DAG, 0x3f7ff8fd));
3804 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3805 SDValue TwoToFractionalPartOfX =
3806 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3808 result = DAG.getNode(ISD::BITCAST, dl,
3809 MVT::f32, TwoToFractionalPartOfX);
3810 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3811 // For floating-point precision of 18:
3813 // TwoToFractionalPartOfX =
3817 // (0.554906021e-1f +
3818 // (0.961591928e-2f +
3819 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3820 // error 2.47208000*10^(-7), which is better than 18 bits
3821 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3822 getF32Constant(DAG, 0x3924b03e));
3823 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3824 getF32Constant(DAG, 0x3ab24b87));
3825 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3826 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3827 getF32Constant(DAG, 0x3c1d8c17));
3828 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3829 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3830 getF32Constant(DAG, 0x3d634a1d));
3831 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3832 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3833 getF32Constant(DAG, 0x3e75fe14));
3834 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3835 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3836 getF32Constant(DAG, 0x3f317234));
3837 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3838 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3839 getF32Constant(DAG, 0x3f800000));
3840 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3841 SDValue TwoToFractionalPartOfX =
3842 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3844 result = DAG.getNode(ISD::BITCAST, dl,
3845 MVT::f32, TwoToFractionalPartOfX);
3848 // No special expansion.
3849 result = DAG.getNode(ISD::FEXP2, dl,
3850 getValue(I.getArgOperand(0)).getValueType(),
3851 getValue(I.getArgOperand(0)));
3854 setValue(&I, result);
3857 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3858 /// limited-precision mode with x == 10.0f.
3860 SelectionDAGBuilder::visitPow(const CallInst &I) {
3862 const Value *Val = I.getArgOperand(0);
3863 DebugLoc dl = getCurDebugLoc();
3864 bool IsExp10 = false;
3866 if (getValue(Val).getValueType() == MVT::f32 &&
3867 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3868 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3869 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3870 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3872 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3877 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3878 SDValue Op = getValue(I.getArgOperand(1));
3880 // Put the exponent in the right bit position for later addition to the
3883 // #define LOG2OF10 3.3219281f
3884 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3885 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3886 getF32Constant(DAG, 0x40549a78));
3887 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3889 // FractionalPartOfX = x - (float)IntegerPartOfX;
3890 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3891 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3893 // IntegerPartOfX <<= 23;
3894 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3895 DAG.getConstant(23, TLI.getPointerTy()));
3897 if (LimitFloatPrecision <= 6) {
3898 // For floating-point precision of 6:
3900 // twoToFractionalPartOfX =
3902 // (0.735607626f + 0.252464424f * x) * x;
3904 // error 0.0144103317, which is 6 bits
3905 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3906 getF32Constant(DAG, 0x3e814304));
3907 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3908 getF32Constant(DAG, 0x3f3c50c8));
3909 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3910 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3911 getF32Constant(DAG, 0x3f7f5e7e));
3912 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3913 SDValue TwoToFractionalPartOfX =
3914 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3916 result = DAG.getNode(ISD::BITCAST, dl,
3917 MVT::f32, TwoToFractionalPartOfX);
3918 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3919 // For floating-point precision of 12:
3921 // TwoToFractionalPartOfX =
3924 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3926 // error 0.000107046256, which is 13 to 14 bits
3927 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3928 getF32Constant(DAG, 0x3da235e3));
3929 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3930 getF32Constant(DAG, 0x3e65b8f3));
3931 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3932 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3933 getF32Constant(DAG, 0x3f324b07));
3934 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3935 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3936 getF32Constant(DAG, 0x3f7ff8fd));
3937 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3938 SDValue TwoToFractionalPartOfX =
3939 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3941 result = DAG.getNode(ISD::BITCAST, dl,
3942 MVT::f32, TwoToFractionalPartOfX);
3943 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3944 // For floating-point precision of 18:
3946 // TwoToFractionalPartOfX =
3950 // (0.554906021e-1f +
3951 // (0.961591928e-2f +
3952 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3953 // error 2.47208000*10^(-7), which is better than 18 bits
3954 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3955 getF32Constant(DAG, 0x3924b03e));
3956 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3957 getF32Constant(DAG, 0x3ab24b87));
3958 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3959 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3960 getF32Constant(DAG, 0x3c1d8c17));
3961 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3962 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3963 getF32Constant(DAG, 0x3d634a1d));
3964 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3965 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3966 getF32Constant(DAG, 0x3e75fe14));
3967 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3968 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3969 getF32Constant(DAG, 0x3f317234));
3970 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3971 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3972 getF32Constant(DAG, 0x3f800000));
3973 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3974 SDValue TwoToFractionalPartOfX =
3975 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3977 result = DAG.getNode(ISD::BITCAST, dl,
3978 MVT::f32, TwoToFractionalPartOfX);
3981 // No special expansion.
3982 result = DAG.getNode(ISD::FPOW, dl,
3983 getValue(I.getArgOperand(0)).getValueType(),
3984 getValue(I.getArgOperand(0)),
3985 getValue(I.getArgOperand(1)));
3988 setValue(&I, result);
3992 /// ExpandPowI - Expand a llvm.powi intrinsic.
3993 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3994 SelectionDAG &DAG) {
3995 // If RHS is a constant, we can expand this out to a multiplication tree,
3996 // otherwise we end up lowering to a call to __powidf2 (for example). When
3997 // optimizing for size, we only want to do this if the expansion would produce
3998 // a small number of multiplies, otherwise we do the full expansion.
3999 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4000 // Get the exponent as a positive value.
4001 unsigned Val = RHSC->getSExtValue();
4002 if ((int)Val < 0) Val = -Val;
4004 // powi(x, 0) -> 1.0
4006 return DAG.getConstantFP(1.0, LHS.getValueType());
4008 const Function *F = DAG.getMachineFunction().getFunction();
4009 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4010 // If optimizing for size, don't insert too many multiplies. This
4011 // inserts up to 5 multiplies.
4012 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4013 // We use the simple binary decomposition method to generate the multiply
4014 // sequence. There are more optimal ways to do this (for example,
4015 // powi(x,15) generates one more multiply than it should), but this has
4016 // the benefit of being both really simple and much better than a libcall.
4017 SDValue Res; // Logically starts equal to 1.0
4018 SDValue CurSquare = LHS;
4022 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4024 Res = CurSquare; // 1.0*CurSquare.
4027 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4028 CurSquare, CurSquare);
4032 // If the original was negative, invert the result, producing 1/(x*x*x).
4033 if (RHSC->getSExtValue() < 0)
4034 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4035 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4040 // Otherwise, expand to a libcall.
4041 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4044 // getTruncatedArgReg - Find underlying register used for an truncated
4046 static unsigned getTruncatedArgReg(const SDValue &N) {
4047 if (N.getOpcode() != ISD::TRUNCATE)
4050 const SDValue &Ext = N.getOperand(0);
4051 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4052 const SDValue &CFR = Ext.getOperand(0);
4053 if (CFR.getOpcode() == ISD::CopyFromReg)
4054 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4056 if (CFR.getOpcode() == ISD::TRUNCATE)
4057 return getTruncatedArgReg(CFR);
4062 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4063 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4064 /// At the end of instruction selection, they will be inserted to the entry BB.
4066 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4069 const Argument *Arg = dyn_cast<Argument>(V);
4073 MachineFunction &MF = DAG.getMachineFunction();
4074 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4075 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4077 // Ignore inlined function arguments here.
4078 DIVariable DV(Variable);
4079 if (DV.isInlinedFnArgument(MF.getFunction()))
4083 if (Arg->hasByValAttr()) {
4084 // Byval arguments' frame index is recorded during argument lowering.
4085 // Use this info directly.
4086 Reg = TRI->getFrameRegister(MF);
4087 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4088 // If byval argument ofset is not recorded then ignore this.
4094 if (N.getOpcode() == ISD::CopyFromReg)
4095 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4097 Reg = getTruncatedArgReg(N);
4098 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4099 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4100 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4107 // Check if ValueMap has reg number.
4108 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4109 if (VMI != FuncInfo.ValueMap.end())
4113 if (!Reg && N.getNode()) {
4114 // Check if frame index is available.
4115 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4116 if (FrameIndexSDNode *FINode =
4117 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4118 Reg = TRI->getFrameRegister(MF);
4119 Offset = FINode->getIndex();
4126 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4127 TII->get(TargetOpcode::DBG_VALUE))
4128 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4129 FuncInfo.ArgDbgValues.push_back(&*MIB);
4133 // VisualStudio defines setjmp as _setjmp
4134 #if defined(_MSC_VER) && defined(setjmp) && \
4135 !defined(setjmp_undefined_for_msvc)
4136 # pragma push_macro("setjmp")
4138 # define setjmp_undefined_for_msvc
4141 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4142 /// we want to emit this as a call to a named external function, return the name
4143 /// otherwise lower it and return null.
4145 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4146 DebugLoc dl = getCurDebugLoc();
4149 switch (Intrinsic) {
4151 // By default, turn this into a target intrinsic node.
4152 visitTargetIntrinsic(I, Intrinsic);
4154 case Intrinsic::vastart: visitVAStart(I); return 0;
4155 case Intrinsic::vaend: visitVAEnd(I); return 0;
4156 case Intrinsic::vacopy: visitVACopy(I); return 0;
4157 case Intrinsic::returnaddress:
4158 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4159 getValue(I.getArgOperand(0))));
4161 case Intrinsic::frameaddress:
4162 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4163 getValue(I.getArgOperand(0))));
4165 case Intrinsic::setjmp:
4166 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4167 case Intrinsic::longjmp:
4168 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4169 case Intrinsic::memcpy: {
4170 // Assert for address < 256 since we support only user defined address
4172 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4174 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4176 "Unknown address space");
4177 SDValue Op1 = getValue(I.getArgOperand(0));
4178 SDValue Op2 = getValue(I.getArgOperand(1));
4179 SDValue Op3 = getValue(I.getArgOperand(2));
4180 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4181 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4182 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4183 MachinePointerInfo(I.getArgOperand(0)),
4184 MachinePointerInfo(I.getArgOperand(1))));
4187 case Intrinsic::memset: {
4188 // Assert for address < 256 since we support only user defined address
4190 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4192 "Unknown address space");
4193 SDValue Op1 = getValue(I.getArgOperand(0));
4194 SDValue Op2 = getValue(I.getArgOperand(1));
4195 SDValue Op3 = getValue(I.getArgOperand(2));
4196 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4197 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4198 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4199 MachinePointerInfo(I.getArgOperand(0))));
4202 case Intrinsic::memmove: {
4203 // Assert for address < 256 since we support only user defined address
4205 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4207 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4209 "Unknown address space");
4210 SDValue Op1 = getValue(I.getArgOperand(0));
4211 SDValue Op2 = getValue(I.getArgOperand(1));
4212 SDValue Op3 = getValue(I.getArgOperand(2));
4213 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4214 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4215 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4216 MachinePointerInfo(I.getArgOperand(0)),
4217 MachinePointerInfo(I.getArgOperand(1))));
4220 case Intrinsic::dbg_declare: {
4221 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4222 MDNode *Variable = DI.getVariable();
4223 const Value *Address = DI.getAddress();
4224 if (!Address || !DIVariable(DI.getVariable()).Verify())
4227 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4228 // but do not always have a corresponding SDNode built. The SDNodeOrder
4229 // absolute, but not relative, values are different depending on whether
4230 // debug info exists.
4233 // Check if address has undef value.
4234 if (isa<UndefValue>(Address) ||
4235 (Address->use_empty() && !isa<Argument>(Address))) {
4236 DEBUG(dbgs() << "Dropping debug info for " << DI);
4240 SDValue &N = NodeMap[Address];
4241 if (!N.getNode() && isa<Argument>(Address))
4242 // Check unused arguments map.
4243 N = UnusedArgNodeMap[Address];
4246 // Parameters are handled specially.
4248 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4249 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4250 Address = BCI->getOperand(0);
4251 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4253 if (isParameter && !AI) {
4254 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4256 // Byval parameter. We have a frame index at this point.
4257 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4258 0, dl, SDNodeOrder);
4260 // Address is an argument, so try to emit its dbg value using
4261 // virtual register info from the FuncInfo.ValueMap.
4262 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4266 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4267 0, dl, SDNodeOrder);
4269 // Can't do anything with other non-AI cases yet.
4270 DEBUG(dbgs() << "Dropping debug info for " << DI);
4273 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4275 // If Address is an argument then try to emit its dbg value using
4276 // virtual register info from the FuncInfo.ValueMap.
4277 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4278 // If variable is pinned by a alloca in dominating bb then
4279 // use StaticAllocaMap.
4280 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4281 if (AI->getParent() != DI.getParent()) {
4282 DenseMap<const AllocaInst*, int>::iterator SI =
4283 FuncInfo.StaticAllocaMap.find(AI);
4284 if (SI != FuncInfo.StaticAllocaMap.end()) {
4285 SDV = DAG.getDbgValue(Variable, SI->second,
4286 0, dl, SDNodeOrder);
4287 DAG.AddDbgValue(SDV, 0, false);
4292 DEBUG(dbgs() << "Dropping debug info for " << DI);
4297 case Intrinsic::dbg_value: {
4298 const DbgValueInst &DI = cast<DbgValueInst>(I);
4299 if (!DIVariable(DI.getVariable()).Verify())
4302 MDNode *Variable = DI.getVariable();
4303 uint64_t Offset = DI.getOffset();
4304 const Value *V = DI.getValue();
4308 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4309 // but do not always have a corresponding SDNode built. The SDNodeOrder
4310 // absolute, but not relative, values are different depending on whether
4311 // debug info exists.
4314 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4315 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4316 DAG.AddDbgValue(SDV, 0, false);
4318 // Do not use getValue() in here; we don't want to generate code at
4319 // this point if it hasn't been done yet.
4320 SDValue N = NodeMap[V];
4321 if (!N.getNode() && isa<Argument>(V))
4322 // Check unused arguments map.
4323 N = UnusedArgNodeMap[V];
4325 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4326 SDV = DAG.getDbgValue(Variable, N.getNode(),
4327 N.getResNo(), Offset, dl, SDNodeOrder);
4328 DAG.AddDbgValue(SDV, N.getNode(), false);
4330 } else if (!V->use_empty() ) {
4331 // Do not call getValue(V) yet, as we don't want to generate code.
4332 // Remember it for later.
4333 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4334 DanglingDebugInfoMap[V] = DDI;
4336 // We may expand this to cover more cases. One case where we have no
4337 // data available is an unreferenced parameter.
4338 DEBUG(dbgs() << "Dropping debug info for " << DI);
4342 // Build a debug info table entry.
4343 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4344 V = BCI->getOperand(0);
4345 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4346 // Don't handle byval struct arguments or VLAs, for example.
4349 DenseMap<const AllocaInst*, int>::iterator SI =
4350 FuncInfo.StaticAllocaMap.find(AI);
4351 if (SI == FuncInfo.StaticAllocaMap.end())
4353 int FI = SI->second;
4355 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4356 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4357 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4360 case Intrinsic::eh_exception: {
4361 // Insert the EXCEPTIONADDR instruction.
4362 assert(FuncInfo.MBB->isLandingPad() &&
4363 "Call to eh.exception not in landing pad!");
4364 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4366 Ops[0] = DAG.getRoot();
4367 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4369 DAG.setRoot(Op.getValue(1));
4373 case Intrinsic::eh_selector: {
4374 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4375 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4376 if (CallMBB->isLandingPad())
4377 AddCatchInfo(I, &MMI, CallMBB);
4380 FuncInfo.CatchInfoLost.insert(&I);
4382 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4383 unsigned Reg = TLI.getExceptionSelectorRegister();
4384 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4387 // Insert the EHSELECTION instruction.
4388 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4390 Ops[0] = getValue(I.getArgOperand(0));
4392 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4393 DAG.setRoot(Op.getValue(1));
4394 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4398 case Intrinsic::eh_typeid_for: {
4399 // Find the type id for the given typeinfo.
4400 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4401 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4402 Res = DAG.getConstant(TypeID, MVT::i32);
4407 case Intrinsic::eh_return_i32:
4408 case Intrinsic::eh_return_i64:
4409 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4410 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4413 getValue(I.getArgOperand(0)),
4414 getValue(I.getArgOperand(1))));
4416 case Intrinsic::eh_unwind_init:
4417 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4419 case Intrinsic::eh_dwarf_cfa: {
4420 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4421 TLI.getPointerTy());
4422 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4424 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4425 TLI.getPointerTy()),
4427 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4429 DAG.getConstant(0, TLI.getPointerTy()));
4430 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4434 case Intrinsic::eh_sjlj_callsite: {
4435 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4436 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4437 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4438 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4440 MMI.setCurrentCallSite(CI->getZExtValue());
4443 case Intrinsic::eh_sjlj_setjmp: {
4444 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4445 getValue(I.getArgOperand(0))));
4448 case Intrinsic::eh_sjlj_longjmp: {
4449 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4450 getRoot(), getValue(I.getArgOperand(0))));
4453 case Intrinsic::eh_sjlj_dispatch_setup: {
4454 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4455 getRoot(), getValue(I.getArgOperand(0))));
4459 case Intrinsic::x86_mmx_pslli_w:
4460 case Intrinsic::x86_mmx_pslli_d:
4461 case Intrinsic::x86_mmx_pslli_q:
4462 case Intrinsic::x86_mmx_psrli_w:
4463 case Intrinsic::x86_mmx_psrli_d:
4464 case Intrinsic::x86_mmx_psrli_q:
4465 case Intrinsic::x86_mmx_psrai_w:
4466 case Intrinsic::x86_mmx_psrai_d: {
4467 SDValue ShAmt = getValue(I.getArgOperand(1));
4468 if (isa<ConstantSDNode>(ShAmt)) {
4469 visitTargetIntrinsic(I, Intrinsic);
4472 unsigned NewIntrinsic = 0;
4473 EVT ShAmtVT = MVT::v2i32;
4474 switch (Intrinsic) {
4475 case Intrinsic::x86_mmx_pslli_w:
4476 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4478 case Intrinsic::x86_mmx_pslli_d:
4479 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4481 case Intrinsic::x86_mmx_pslli_q:
4482 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4484 case Intrinsic::x86_mmx_psrli_w:
4485 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4487 case Intrinsic::x86_mmx_psrli_d:
4488 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4490 case Intrinsic::x86_mmx_psrli_q:
4491 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4493 case Intrinsic::x86_mmx_psrai_w:
4494 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4496 case Intrinsic::x86_mmx_psrai_d:
4497 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4499 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4502 // The vector shift intrinsics with scalars uses 32b shift amounts but
4503 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4505 // We must do this early because v2i32 is not a legal type.
4506 DebugLoc dl = getCurDebugLoc();
4509 ShOps[1] = DAG.getConstant(0, MVT::i32);
4510 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4511 EVT DestVT = TLI.getValueType(I.getType());
4512 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4513 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4514 DAG.getConstant(NewIntrinsic, MVT::i32),
4515 getValue(I.getArgOperand(0)), ShAmt);
4519 case Intrinsic::convertff:
4520 case Intrinsic::convertfsi:
4521 case Intrinsic::convertfui:
4522 case Intrinsic::convertsif:
4523 case Intrinsic::convertuif:
4524 case Intrinsic::convertss:
4525 case Intrinsic::convertsu:
4526 case Intrinsic::convertus:
4527 case Intrinsic::convertuu: {
4528 ISD::CvtCode Code = ISD::CVT_INVALID;
4529 switch (Intrinsic) {
4530 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4531 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4532 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4533 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4534 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4535 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4536 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4537 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4538 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4540 EVT DestVT = TLI.getValueType(I.getType());
4541 const Value *Op1 = I.getArgOperand(0);
4542 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4543 DAG.getValueType(DestVT),
4544 DAG.getValueType(getValue(Op1).getValueType()),
4545 getValue(I.getArgOperand(1)),
4546 getValue(I.getArgOperand(2)),
4551 case Intrinsic::sqrt:
4552 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4553 getValue(I.getArgOperand(0)).getValueType(),
4554 getValue(I.getArgOperand(0))));
4556 case Intrinsic::powi:
4557 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4558 getValue(I.getArgOperand(1)), DAG));
4560 case Intrinsic::sin:
4561 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4562 getValue(I.getArgOperand(0)).getValueType(),
4563 getValue(I.getArgOperand(0))));
4565 case Intrinsic::cos:
4566 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4567 getValue(I.getArgOperand(0)).getValueType(),
4568 getValue(I.getArgOperand(0))));
4570 case Intrinsic::log:
4573 case Intrinsic::log2:
4576 case Intrinsic::log10:
4579 case Intrinsic::exp:
4582 case Intrinsic::exp2:
4585 case Intrinsic::pow:
4588 case Intrinsic::convert_to_fp16:
4589 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4590 MVT::i16, getValue(I.getArgOperand(0))));
4592 case Intrinsic::convert_from_fp16:
4593 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4594 MVT::f32, getValue(I.getArgOperand(0))));
4596 case Intrinsic::pcmarker: {
4597 SDValue Tmp = getValue(I.getArgOperand(0));
4598 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4601 case Intrinsic::readcyclecounter: {
4602 SDValue Op = getRoot();
4603 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4604 DAG.getVTList(MVT::i64, MVT::Other),
4607 DAG.setRoot(Res.getValue(1));
4610 case Intrinsic::bswap:
4611 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4612 getValue(I.getArgOperand(0)).getValueType(),
4613 getValue(I.getArgOperand(0))));
4615 case Intrinsic::cttz: {
4616 SDValue Arg = getValue(I.getArgOperand(0));
4617 EVT Ty = Arg.getValueType();
4618 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4621 case Intrinsic::ctlz: {
4622 SDValue Arg = getValue(I.getArgOperand(0));
4623 EVT Ty = Arg.getValueType();
4624 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4627 case Intrinsic::ctpop: {
4628 SDValue Arg = getValue(I.getArgOperand(0));
4629 EVT Ty = Arg.getValueType();
4630 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4633 case Intrinsic::stacksave: {
4634 SDValue Op = getRoot();
4635 Res = DAG.getNode(ISD::STACKSAVE, dl,
4636 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4638 DAG.setRoot(Res.getValue(1));
4641 case Intrinsic::stackrestore: {
4642 Res = getValue(I.getArgOperand(0));
4643 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4646 case Intrinsic::stackprotector: {
4647 // Emit code into the DAG to store the stack guard onto the stack.
4648 MachineFunction &MF = DAG.getMachineFunction();
4649 MachineFrameInfo *MFI = MF.getFrameInfo();
4650 EVT PtrTy = TLI.getPointerTy();
4652 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4653 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4655 int FI = FuncInfo.StaticAllocaMap[Slot];
4656 MFI->setStackProtectorIndex(FI);
4658 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4660 // Store the stack protector onto the stack.
4661 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4662 MachinePointerInfo::getFixedStack(FI),
4668 case Intrinsic::objectsize: {
4669 // If we don't know by now, we're never going to know.
4670 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4672 assert(CI && "Non-constant type in __builtin_object_size?");
4674 SDValue Arg = getValue(I.getCalledValue());
4675 EVT Ty = Arg.getValueType();
4678 Res = DAG.getConstant(-1ULL, Ty);
4680 Res = DAG.getConstant(0, Ty);
4685 case Intrinsic::var_annotation:
4686 // Discard annotate attributes
4689 case Intrinsic::init_trampoline: {
4690 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4694 Ops[1] = getValue(I.getArgOperand(0));
4695 Ops[2] = getValue(I.getArgOperand(1));
4696 Ops[3] = getValue(I.getArgOperand(2));
4697 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4698 Ops[5] = DAG.getSrcValue(F);
4700 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4701 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4705 DAG.setRoot(Res.getValue(1));
4708 case Intrinsic::gcroot:
4710 const Value *Alloca = I.getArgOperand(0);
4711 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4713 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4714 GFI->addStackRoot(FI->getIndex(), TypeMap);
4717 case Intrinsic::gcread:
4718 case Intrinsic::gcwrite:
4719 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4721 case Intrinsic::flt_rounds:
4722 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4724 case Intrinsic::trap: {
4725 StringRef TrapFuncName = getTrapFunctionName();
4726 if (TrapFuncName.empty()) {
4727 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4730 TargetLowering::ArgListTy Args;
4731 std::pair<SDValue, SDValue> Result =
4732 TLI.LowerCallTo(getRoot(), I.getType(),
4733 false, false, false, false, 0, CallingConv::C,
4734 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
4735 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4736 Args, DAG, getCurDebugLoc());
4737 DAG.setRoot(Result.second);
4740 case Intrinsic::uadd_with_overflow:
4741 return implVisitAluOverflow(I, ISD::UADDO);
4742 case Intrinsic::sadd_with_overflow:
4743 return implVisitAluOverflow(I, ISD::SADDO);
4744 case Intrinsic::usub_with_overflow:
4745 return implVisitAluOverflow(I, ISD::USUBO);
4746 case Intrinsic::ssub_with_overflow:
4747 return implVisitAluOverflow(I, ISD::SSUBO);
4748 case Intrinsic::umul_with_overflow:
4749 return implVisitAluOverflow(I, ISD::UMULO);
4750 case Intrinsic::smul_with_overflow:
4751 return implVisitAluOverflow(I, ISD::SMULO);
4753 case Intrinsic::prefetch: {
4755 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4757 Ops[1] = getValue(I.getArgOperand(0));
4758 Ops[2] = getValue(I.getArgOperand(1));
4759 Ops[3] = getValue(I.getArgOperand(2));
4760 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4761 DAG.getVTList(MVT::Other),
4763 EVT::getIntegerVT(*Context, 8),
4764 MachinePointerInfo(I.getArgOperand(0)),
4766 false, /* volatile */
4768 rw==1)); /* write */
4771 case Intrinsic::memory_barrier: {
4774 for (int x = 1; x < 6; ++x)
4775 Ops[x] = getValue(I.getArgOperand(x - 1));
4777 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4780 case Intrinsic::atomic_cmp_swap: {
4781 SDValue Root = getRoot();
4783 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4784 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4786 getValue(I.getArgOperand(0)),
4787 getValue(I.getArgOperand(1)),
4788 getValue(I.getArgOperand(2)),
4789 MachinePointerInfo(I.getArgOperand(0)));
4791 DAG.setRoot(L.getValue(1));
4794 case Intrinsic::atomic_load_add:
4795 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4796 case Intrinsic::atomic_load_sub:
4797 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4798 case Intrinsic::atomic_load_or:
4799 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4800 case Intrinsic::atomic_load_xor:
4801 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4802 case Intrinsic::atomic_load_and:
4803 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4804 case Intrinsic::atomic_load_nand:
4805 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4806 case Intrinsic::atomic_load_max:
4807 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4808 case Intrinsic::atomic_load_min:
4809 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4810 case Intrinsic::atomic_load_umin:
4811 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4812 case Intrinsic::atomic_load_umax:
4813 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4814 case Intrinsic::atomic_swap:
4815 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4817 case Intrinsic::invariant_start:
4818 case Intrinsic::lifetime_start:
4819 // Discard region information.
4820 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4822 case Intrinsic::invariant_end:
4823 case Intrinsic::lifetime_end:
4824 // Discard region information.
4829 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4831 MachineBasicBlock *LandingPad) {
4832 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4833 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4834 const Type *RetTy = FTy->getReturnType();
4835 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4836 MCSymbol *BeginLabel = 0;
4838 TargetLowering::ArgListTy Args;
4839 TargetLowering::ArgListEntry Entry;
4840 Args.reserve(CS.arg_size());
4842 // Check whether the function can return without sret-demotion.
4843 SmallVector<ISD::OutputArg, 4> Outs;
4844 SmallVector<uint64_t, 4> Offsets;
4845 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4846 Outs, TLI, &Offsets);
4848 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4849 FTy->isVarArg(), Outs, FTy->getContext());
4851 SDValue DemoteStackSlot;
4852 int DemoteStackIdx = -100;
4854 if (!CanLowerReturn) {
4855 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4856 FTy->getReturnType());
4857 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4858 FTy->getReturnType());
4859 MachineFunction &MF = DAG.getMachineFunction();
4860 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4861 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4863 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4864 Entry.Node = DemoteStackSlot;
4865 Entry.Ty = StackSlotPtrType;
4866 Entry.isSExt = false;
4867 Entry.isZExt = false;
4868 Entry.isInReg = false;
4869 Entry.isSRet = true;
4870 Entry.isNest = false;
4871 Entry.isByVal = false;
4872 Entry.Alignment = Align;
4873 Args.push_back(Entry);
4874 RetTy = Type::getVoidTy(FTy->getContext());
4877 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4879 const Value *V = *i;
4882 if (V->getType()->isEmptyTy())
4885 SDValue ArgNode = getValue(V);
4886 Entry.Node = ArgNode; Entry.Ty = V->getType();
4888 unsigned attrInd = i - CS.arg_begin() + 1;
4889 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4890 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4891 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4892 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4893 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4894 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4895 Entry.Alignment = CS.getParamAlignment(attrInd);
4896 Args.push_back(Entry);
4900 // Insert a label before the invoke call to mark the try range. This can be
4901 // used to detect deletion of the invoke via the MachineModuleInfo.
4902 BeginLabel = MMI.getContext().CreateTempSymbol();
4904 // For SjLj, keep track of which landing pads go with which invokes
4905 // so as to maintain the ordering of pads in the LSDA.
4906 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4907 if (CallSiteIndex) {
4908 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4909 // Now that the call site is handled, stop tracking it.
4910 MMI.setCurrentCallSite(0);
4913 // Both PendingLoads and PendingExports must be flushed here;
4914 // this call might not return.
4916 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4919 // Check if target-independent constraints permit a tail call here.
4920 // Target-dependent constraints are checked within TLI.LowerCallTo.
4922 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4925 // If there's a possibility that fast-isel has already selected some amount
4926 // of the current basic block, don't emit a tail call.
4927 if (isTailCall && EnableFastISel)
4930 std::pair<SDValue,SDValue> Result =
4931 TLI.LowerCallTo(getRoot(), RetTy,
4932 CS.paramHasAttr(0, Attribute::SExt),
4933 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4934 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4935 CS.getCallingConv(),
4937 !CS.getInstruction()->use_empty(),
4938 Callee, Args, DAG, getCurDebugLoc());
4939 assert((isTailCall || Result.second.getNode()) &&
4940 "Non-null chain expected with non-tail call!");
4941 assert((Result.second.getNode() || !Result.first.getNode()) &&
4942 "Null value expected with tail call!");
4943 if (Result.first.getNode()) {
4944 setValue(CS.getInstruction(), Result.first);
4945 } else if (!CanLowerReturn && Result.second.getNode()) {
4946 // The instruction result is the result of loading from the
4947 // hidden sret parameter.
4948 SmallVector<EVT, 1> PVTs;
4949 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4951 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4952 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4953 EVT PtrVT = PVTs[0];
4954 unsigned NumValues = Outs.size();
4955 SmallVector<SDValue, 4> Values(NumValues);
4956 SmallVector<SDValue, 4> Chains(NumValues);
4958 for (unsigned i = 0; i < NumValues; ++i) {
4959 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4961 DAG.getConstant(Offsets[i], PtrVT));
4962 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4964 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4967 Chains[i] = L.getValue(1);
4970 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4971 MVT::Other, &Chains[0], NumValues);
4972 PendingLoads.push_back(Chain);
4974 // Collect the legal value parts into potentially illegal values
4975 // that correspond to the original function's return values.
4976 SmallVector<EVT, 4> RetTys;
4977 RetTy = FTy->getReturnType();
4978 ComputeValueVTs(TLI, RetTy, RetTys);
4979 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4980 SmallVector<SDValue, 4> ReturnValues;
4981 unsigned CurReg = 0;
4982 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4984 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4985 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4987 SDValue ReturnValue =
4988 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4989 RegisterVT, VT, AssertOp);
4990 ReturnValues.push_back(ReturnValue);
4994 setValue(CS.getInstruction(),
4995 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4996 DAG.getVTList(&RetTys[0], RetTys.size()),
4997 &ReturnValues[0], ReturnValues.size()));
5000 // Assign order to nodes here. If the call does not produce a result, it won't
5001 // be mapped to a SDNode and visit() will not assign it an order number.
5002 if (!Result.second.getNode()) {
5003 // As a special case, a null chain means that a tail call has been emitted and
5004 // the DAG root is already updated.
5007 AssignOrderingToNode(DAG.getRoot().getNode());
5009 DAG.setRoot(Result.second);
5011 AssignOrderingToNode(Result.second.getNode());
5015 // Insert a label at the end of the invoke call to mark the try range. This
5016 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5017 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5018 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5020 // Inform MachineModuleInfo of range.
5021 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5025 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5026 /// value is equal or not-equal to zero.
5027 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5028 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5030 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5031 if (IC->isEquality())
5032 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5033 if (C->isNullValue())
5035 // Unknown instruction.
5041 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5043 SelectionDAGBuilder &Builder) {
5045 // Check to see if this load can be trivially constant folded, e.g. if the
5046 // input is from a string literal.
5047 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5048 // Cast pointer to the type we really want to load.
5049 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5050 PointerType::getUnqual(LoadTy));
5052 if (const Constant *LoadCst =
5053 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5055 return Builder.getValue(LoadCst);
5058 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5059 // still constant memory, the input chain can be the entry node.
5061 bool ConstantMemory = false;
5063 // Do not serialize (non-volatile) loads of constant memory with anything.
5064 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5065 Root = Builder.DAG.getEntryNode();
5066 ConstantMemory = true;
5068 // Do not serialize non-volatile loads against each other.
5069 Root = Builder.DAG.getRoot();
5072 SDValue Ptr = Builder.getValue(PtrVal);
5073 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5074 Ptr, MachinePointerInfo(PtrVal),
5076 false /*nontemporal*/, 1 /* align=1 */);
5078 if (!ConstantMemory)
5079 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5084 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5085 /// If so, return true and lower it, otherwise return false and it will be
5086 /// lowered like a normal call.
5087 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5088 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5089 if (I.getNumArgOperands() != 3)
5092 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5093 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5094 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5095 !I.getType()->isIntegerTy())
5098 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5100 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5101 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5102 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5103 bool ActuallyDoIt = true;
5106 switch (Size->getZExtValue()) {
5108 LoadVT = MVT::Other;
5110 ActuallyDoIt = false;
5114 LoadTy = Type::getInt16Ty(Size->getContext());
5118 LoadTy = Type::getInt32Ty(Size->getContext());
5122 LoadTy = Type::getInt64Ty(Size->getContext());
5126 LoadVT = MVT::v4i32;
5127 LoadTy = Type::getInt32Ty(Size->getContext());
5128 LoadTy = VectorType::get(LoadTy, 4);
5133 // This turns into unaligned loads. We only do this if the target natively
5134 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5135 // we'll only produce a small number of byte loads.
5137 // Require that we can find a legal MVT, and only do this if the target
5138 // supports unaligned loads of that type. Expanding into byte loads would
5140 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5141 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5142 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5143 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5144 ActuallyDoIt = false;
5148 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5149 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5151 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5153 EVT CallVT = TLI.getValueType(I.getType(), true);
5154 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5164 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5165 // Handle inline assembly differently.
5166 if (isa<InlineAsm>(I.getCalledValue())) {
5171 // See if any floating point values are being passed to this function. This is
5172 // used to emit an undefined reference to fltused on Windows.
5173 const FunctionType *FT =
5174 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5175 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5176 if (FT->isVarArg() &&
5177 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5178 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5179 const Type* T = I.getArgOperand(i)->getType();
5180 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5182 if (!i->isFloatingPointTy()) continue;
5183 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5189 const char *RenameFn = 0;
5190 if (Function *F = I.getCalledFunction()) {
5191 if (F->isDeclaration()) {
5192 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5193 if (unsigned IID = II->getIntrinsicID(F)) {
5194 RenameFn = visitIntrinsicCall(I, IID);
5199 if (unsigned IID = F->getIntrinsicID()) {
5200 RenameFn = visitIntrinsicCall(I, IID);
5206 // Check for well-known libc/libm calls. If the function is internal, it
5207 // can't be a library call.
5208 if (!F->hasLocalLinkage() && F->hasName()) {
5209 StringRef Name = F->getName();
5210 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5211 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5212 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5213 I.getType() == I.getArgOperand(0)->getType() &&
5214 I.getType() == I.getArgOperand(1)->getType()) {
5215 SDValue LHS = getValue(I.getArgOperand(0));
5216 SDValue RHS = getValue(I.getArgOperand(1));
5217 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5218 LHS.getValueType(), LHS, RHS));
5221 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5222 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5223 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5224 I.getType() == I.getArgOperand(0)->getType()) {
5225 SDValue Tmp = getValue(I.getArgOperand(0));
5226 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5227 Tmp.getValueType(), Tmp));
5230 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5231 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5232 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5233 I.getType() == I.getArgOperand(0)->getType() &&
5234 I.onlyReadsMemory()) {
5235 SDValue Tmp = getValue(I.getArgOperand(0));
5236 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5237 Tmp.getValueType(), Tmp));
5240 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5241 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5242 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5243 I.getType() == I.getArgOperand(0)->getType() &&
5244 I.onlyReadsMemory()) {
5245 SDValue Tmp = getValue(I.getArgOperand(0));
5246 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5247 Tmp.getValueType(), Tmp));
5250 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5251 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5252 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5253 I.getType() == I.getArgOperand(0)->getType() &&
5254 I.onlyReadsMemory()) {
5255 SDValue Tmp = getValue(I.getArgOperand(0));
5256 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5257 Tmp.getValueType(), Tmp));
5260 } else if (Name == "memcmp") {
5261 if (visitMemCmpCall(I))
5269 Callee = getValue(I.getCalledValue());
5271 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5273 // Check if we can potentially perform a tail call. More detailed checking is
5274 // be done within LowerCallTo, after more information about the call is known.
5275 LowerCallTo(&I, Callee, I.isTailCall());
5280 /// AsmOperandInfo - This contains information for each constraint that we are
5282 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5284 /// CallOperand - If this is the result output operand or a clobber
5285 /// this is null, otherwise it is the incoming operand to the CallInst.
5286 /// This gets modified as the asm is processed.
5287 SDValue CallOperand;
5289 /// AssignedRegs - If this is a register or register class operand, this
5290 /// contains the set of register corresponding to the operand.
5291 RegsForValue AssignedRegs;
5293 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5294 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5297 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5298 /// busy in OutputRegs/InputRegs.
5299 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5300 std::set<unsigned> &OutputRegs,
5301 std::set<unsigned> &InputRegs,
5302 const TargetRegisterInfo &TRI) const {
5304 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5305 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5308 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5309 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5313 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5314 /// corresponds to. If there is no Value* for this operand, it returns
5316 EVT getCallOperandValEVT(LLVMContext &Context,
5317 const TargetLowering &TLI,
5318 const TargetData *TD) const {
5319 if (CallOperandVal == 0) return MVT::Other;
5321 if (isa<BasicBlock>(CallOperandVal))
5322 return TLI.getPointerTy();
5324 const llvm::Type *OpTy = CallOperandVal->getType();
5326 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5327 // If this is an indirect operand, the operand is a pointer to the
5330 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5332 report_fatal_error("Indirect operand for inline asm not a pointer!");
5333 OpTy = PtrTy->getElementType();
5336 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5337 if (const StructType *STy = dyn_cast<StructType>(OpTy))
5338 if (STy->getNumElements() == 1)
5339 OpTy = STy->getElementType(0);
5341 // If OpTy is not a single value, it may be a struct/union that we
5342 // can tile with integers.
5343 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5344 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5353 OpTy = IntegerType::get(Context, BitSize);
5358 return TLI.getValueType(OpTy, true);
5362 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5364 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5365 const TargetRegisterInfo &TRI) {
5366 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5368 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5369 for (; *Aliases; ++Aliases)
5370 Regs.insert(*Aliases);
5374 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5376 } // end anonymous namespace
5378 /// isAllocatableRegister - If the specified register is safe to allocate,
5379 /// i.e. it isn't a stack pointer or some other special register, return the
5380 /// register class for the register. Otherwise, return null.
5381 static const TargetRegisterClass *
5382 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5383 const TargetLowering &TLI,
5384 const TargetRegisterInfo *TRI) {
5385 EVT FoundVT = MVT::Other;
5386 const TargetRegisterClass *FoundRC = 0;
5387 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5388 E = TRI->regclass_end(); RCI != E; ++RCI) {
5389 EVT ThisVT = MVT::Other;
5391 const TargetRegisterClass *RC = *RCI;
5392 // If none of the value types for this register class are valid, we
5393 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5394 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5396 if (TLI.isTypeLegal(*I)) {
5397 // If we have already found this register in a different register class,
5398 // choose the one with the largest VT specified. For example, on
5399 // PowerPC, we favor f64 register classes over f32.
5400 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5407 if (ThisVT == MVT::Other) continue;
5409 // NOTE: This isn't ideal. In particular, this might allocate the
5410 // frame pointer in functions that need it (due to them not being taken
5411 // out of allocation, because a variable sized allocation hasn't been seen
5412 // yet). This is a slight code pessimization, but should still work.
5413 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5414 E = RC->allocation_order_end(MF); I != E; ++I)
5416 // We found a matching register class. Keep looking at others in case
5417 // we find one with larger registers that this physreg is also in.
5426 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5427 /// specified operand. We prefer to assign virtual registers, to allow the
5428 /// register allocator to handle the assignment process. However, if the asm
5429 /// uses features that we can't model on machineinstrs, we have SDISel do the
5430 /// allocation. This produces generally horrible, but correct, code.
5432 /// OpInfo describes the operand.
5433 /// Input and OutputRegs are the set of already allocated physical registers.
5435 static void GetRegistersForValue(SelectionDAG &DAG,
5436 const TargetLowering &TLI,
5438 SDISelAsmOperandInfo &OpInfo,
5439 std::set<unsigned> &OutputRegs,
5440 std::set<unsigned> &InputRegs) {
5441 LLVMContext &Context = *DAG.getContext();
5443 // Compute whether this value requires an input register, an output register,
5445 bool isOutReg = false;
5446 bool isInReg = false;
5447 switch (OpInfo.Type) {
5448 case InlineAsm::isOutput:
5451 // If there is an input constraint that matches this, we need to reserve
5452 // the input register so no other inputs allocate to it.
5453 isInReg = OpInfo.hasMatchingInput();
5455 case InlineAsm::isInput:
5459 case InlineAsm::isClobber:
5466 MachineFunction &MF = DAG.getMachineFunction();
5467 SmallVector<unsigned, 4> Regs;
5469 // If this is a constraint for a single physreg, or a constraint for a
5470 // register class, find it.
5471 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5472 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5473 OpInfo.ConstraintVT);
5475 unsigned NumRegs = 1;
5476 if (OpInfo.ConstraintVT != MVT::Other) {
5477 // If this is a FP input in an integer register (or visa versa) insert a bit
5478 // cast of the input value. More generally, handle any case where the input
5479 // value disagrees with the register class we plan to stick this in.
5480 if (OpInfo.Type == InlineAsm::isInput &&
5481 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5482 // Try to convert to the first EVT that the reg class contains. If the
5483 // types are identical size, use a bitcast to convert (e.g. two differing
5485 EVT RegVT = *PhysReg.second->vt_begin();
5486 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5487 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5488 RegVT, OpInfo.CallOperand);
5489 OpInfo.ConstraintVT = RegVT;
5490 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5491 // If the input is a FP value and we want it in FP registers, do a
5492 // bitcast to the corresponding integer type. This turns an f64 value
5493 // into i64, which can be passed with two i32 values on a 32-bit
5495 RegVT = EVT::getIntegerVT(Context,
5496 OpInfo.ConstraintVT.getSizeInBits());
5497 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5498 RegVT, OpInfo.CallOperand);
5499 OpInfo.ConstraintVT = RegVT;
5503 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5507 EVT ValueVT = OpInfo.ConstraintVT;
5509 // If this is a constraint for a specific physical register, like {r17},
5511 if (unsigned AssignedReg = PhysReg.first) {
5512 const TargetRegisterClass *RC = PhysReg.second;
5513 if (OpInfo.ConstraintVT == MVT::Other)
5514 ValueVT = *RC->vt_begin();
5516 // Get the actual register value type. This is important, because the user
5517 // may have asked for (e.g.) the AX register in i32 type. We need to
5518 // remember that AX is actually i16 to get the right extension.
5519 RegVT = *RC->vt_begin();
5521 // This is a explicit reference to a physical register.
5522 Regs.push_back(AssignedReg);
5524 // If this is an expanded reference, add the rest of the regs to Regs.
5526 TargetRegisterClass::iterator I = RC->begin();
5527 for (; *I != AssignedReg; ++I)
5528 assert(I != RC->end() && "Didn't find reg!");
5530 // Already added the first reg.
5532 for (; NumRegs; --NumRegs, ++I) {
5533 assert(I != RC->end() && "Ran out of registers to allocate!");
5538 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5539 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5540 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5544 // Otherwise, if this was a reference to an LLVM register class, create vregs
5545 // for this reference.
5546 if (const TargetRegisterClass *RC = PhysReg.second) {
5547 RegVT = *RC->vt_begin();
5548 if (OpInfo.ConstraintVT == MVT::Other)
5551 // Create the appropriate number of virtual registers.
5552 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5553 for (; NumRegs; --NumRegs)
5554 Regs.push_back(RegInfo.createVirtualRegister(RC));
5556 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5560 // This is a reference to a register class that doesn't directly correspond
5561 // to an LLVM register class. Allocate NumRegs consecutive, available,
5562 // registers from the class.
5563 std::vector<unsigned> RegClassRegs
5564 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5565 OpInfo.ConstraintVT);
5567 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5568 unsigned NumAllocated = 0;
5569 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5570 unsigned Reg = RegClassRegs[i];
5571 // See if this register is available.
5572 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5573 (isInReg && InputRegs.count(Reg))) { // Already used.
5574 // Make sure we find consecutive registers.
5579 // Check to see if this register is allocatable (i.e. don't give out the
5581 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5582 if (!RC) { // Couldn't allocate this register.
5583 // Reset NumAllocated to make sure we return consecutive registers.
5588 // Okay, this register is good, we can use it.
5591 // If we allocated enough consecutive registers, succeed.
5592 if (NumAllocated == NumRegs) {
5593 unsigned RegStart = (i-NumAllocated)+1;
5594 unsigned RegEnd = i+1;
5595 // Mark all of the allocated registers used.
5596 for (unsigned i = RegStart; i != RegEnd; ++i)
5597 Regs.push_back(RegClassRegs[i]);
5599 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5600 OpInfo.ConstraintVT);
5601 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5606 // Otherwise, we couldn't allocate enough registers for this.
5609 /// visitInlineAsm - Handle a call to an InlineAsm object.
5611 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5612 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5614 /// ConstraintOperands - Information about all of the constraints.
5615 SDISelAsmOperandInfoVector ConstraintOperands;
5617 std::set<unsigned> OutputRegs, InputRegs;
5619 TargetLowering::AsmOperandInfoVector
5620 TargetConstraints = TLI.ParseConstraints(CS);
5622 bool hasMemory = false;
5624 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5625 unsigned ResNo = 0; // ResNo - The result number of the next output.
5626 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5627 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5628 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5630 EVT OpVT = MVT::Other;
5632 // Compute the value type for each operand.
5633 switch (OpInfo.Type) {
5634 case InlineAsm::isOutput:
5635 // Indirect outputs just consume an argument.
5636 if (OpInfo.isIndirect) {
5637 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5641 // The return value of the call is this value. As such, there is no
5642 // corresponding argument.
5643 assert(!CS.getType()->isVoidTy() &&
5645 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5646 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5648 assert(ResNo == 0 && "Asm only has one result!");
5649 OpVT = TLI.getValueType(CS.getType());
5653 case InlineAsm::isInput:
5654 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5656 case InlineAsm::isClobber:
5661 // If this is an input or an indirect output, process the call argument.
5662 // BasicBlocks are labels, currently appearing only in asm's.
5663 if (OpInfo.CallOperandVal) {
5664 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5665 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5667 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5670 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5673 OpInfo.ConstraintVT = OpVT;
5675 // Indirect operand accesses access memory.
5676 if (OpInfo.isIndirect)
5679 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5680 TargetLowering::ConstraintType
5681 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5682 if (CType == TargetLowering::C_Memory) {
5690 SDValue Chain, Flag;
5692 // We won't need to flush pending loads if this asm doesn't touch
5693 // memory and is nonvolatile.
5694 if (hasMemory || IA->hasSideEffects())
5697 Chain = DAG.getRoot();
5699 // Second pass over the constraints: compute which constraint option to use
5700 // and assign registers to constraints that want a specific physreg.
5701 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5702 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5704 // If this is an output operand with a matching input operand, look up the
5705 // matching input. If their types mismatch, e.g. one is an integer, the
5706 // other is floating point, or their sizes are different, flag it as an
5708 if (OpInfo.hasMatchingInput()) {
5709 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5711 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5712 if ((OpInfo.ConstraintVT.isInteger() !=
5713 Input.ConstraintVT.isInteger()) ||
5714 (OpInfo.ConstraintVT.getSizeInBits() !=
5715 Input.ConstraintVT.getSizeInBits())) {
5716 report_fatal_error("Unsupported asm: input constraint"
5717 " with a matching output constraint of"
5718 " incompatible type!");
5720 Input.ConstraintVT = OpInfo.ConstraintVT;
5724 // Compute the constraint code and ConstraintType to use.
5725 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5727 // If this is a memory input, and if the operand is not indirect, do what we
5728 // need to to provide an address for the memory input.
5729 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5730 !OpInfo.isIndirect) {
5731 assert((OpInfo.isMultipleAlternative ||
5732 (OpInfo.Type == InlineAsm::isInput)) &&
5733 "Can only indirectify direct input operands!");
5735 // Memory operands really want the address of the value. If we don't have
5736 // an indirect input, put it in the constpool if we can, otherwise spill
5737 // it to a stack slot.
5739 // If the operand is a float, integer, or vector constant, spill to a
5740 // constant pool entry to get its address.
5741 const Value *OpVal = OpInfo.CallOperandVal;
5742 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5743 isa<ConstantVector>(OpVal)) {
5744 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5745 TLI.getPointerTy());
5747 // Otherwise, create a stack slot and emit a store to it before the
5749 const Type *Ty = OpVal->getType();
5750 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5751 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5752 MachineFunction &MF = DAG.getMachineFunction();
5753 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5754 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5755 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5756 OpInfo.CallOperand, StackSlot,
5757 MachinePointerInfo::getFixedStack(SSFI),
5759 OpInfo.CallOperand = StackSlot;
5762 // There is no longer a Value* corresponding to this operand.
5763 OpInfo.CallOperandVal = 0;
5765 // It is now an indirect operand.
5766 OpInfo.isIndirect = true;
5769 // If this constraint is for a specific register, allocate it before
5771 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5772 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5776 // Second pass - Loop over all of the operands, assigning virtual or physregs
5777 // to register class operands.
5778 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5779 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5781 // C_Register operands have already been allocated, Other/Memory don't need
5783 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5784 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5788 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5789 std::vector<SDValue> AsmNodeOperands;
5790 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5791 AsmNodeOperands.push_back(
5792 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5793 TLI.getPointerTy()));
5795 // If we have a !srcloc metadata node associated with it, we want to attach
5796 // this to the ultimately generated inline asm machineinstr. To do this, we
5797 // pass in the third operand as this (potentially null) inline asm MDNode.
5798 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5799 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5801 // Remember the HasSideEffect and AlignStack bits as operand 3.
5802 unsigned ExtraInfo = 0;
5803 if (IA->hasSideEffects())
5804 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5805 if (IA->isAlignStack())
5806 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5807 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5808 TLI.getPointerTy()));
5810 // Loop over all of the inputs, copying the operand values into the
5811 // appropriate registers and processing the output regs.
5812 RegsForValue RetValRegs;
5814 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5815 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5817 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5818 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5820 switch (OpInfo.Type) {
5821 case InlineAsm::isOutput: {
5822 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5823 OpInfo.ConstraintType != TargetLowering::C_Register) {
5824 // Memory output, or 'other' output (e.g. 'X' constraint).
5825 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5827 // Add information to the INLINEASM node to know about this output.
5828 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5829 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5830 TLI.getPointerTy()));
5831 AsmNodeOperands.push_back(OpInfo.CallOperand);
5835 // Otherwise, this is a register or register class output.
5837 // Copy the output from the appropriate register. Find a register that
5839 if (OpInfo.AssignedRegs.Regs.empty())
5840 report_fatal_error("Couldn't allocate output reg for constraint '" +
5841 Twine(OpInfo.ConstraintCode) + "'!");
5843 // If this is an indirect operand, store through the pointer after the
5845 if (OpInfo.isIndirect) {
5846 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5847 OpInfo.CallOperandVal));
5849 // This is the result value of the call.
5850 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5851 // Concatenate this output onto the outputs list.
5852 RetValRegs.append(OpInfo.AssignedRegs);
5855 // Add information to the INLINEASM node to know that this register is
5857 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5858 InlineAsm::Kind_RegDefEarlyClobber :
5859 InlineAsm::Kind_RegDef,
5866 case InlineAsm::isInput: {
5867 SDValue InOperandVal = OpInfo.CallOperand;
5869 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5870 // If this is required to match an output register we have already set,
5871 // just use its register.
5872 unsigned OperandNo = OpInfo.getMatchedOperand();
5874 // Scan until we find the definition we already emitted of this operand.
5875 // When we find it, create a RegsForValue operand.
5876 unsigned CurOp = InlineAsm::Op_FirstOperand;
5877 for (; OperandNo; --OperandNo) {
5878 // Advance to the next operand.
5880 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5881 assert((InlineAsm::isRegDefKind(OpFlag) ||
5882 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5883 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5884 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5888 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5889 if (InlineAsm::isRegDefKind(OpFlag) ||
5890 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5891 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5892 if (OpInfo.isIndirect) {
5893 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5894 LLVMContext &Ctx = *DAG.getContext();
5895 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5896 " don't know how to handle tied "
5897 "indirect register inputs");
5900 RegsForValue MatchedRegs;
5901 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5902 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5903 MatchedRegs.RegVTs.push_back(RegVT);
5904 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5905 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5907 MatchedRegs.Regs.push_back
5908 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5910 // Use the produced MatchedRegs object to
5911 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5913 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5914 true, OpInfo.getMatchedOperand(),
5915 DAG, AsmNodeOperands);
5919 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5920 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5921 "Unexpected number of operands");
5922 // Add information to the INLINEASM node to know about this input.
5923 // See InlineAsm.h isUseOperandTiedToDef.
5924 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5925 OpInfo.getMatchedOperand());
5926 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5927 TLI.getPointerTy()));
5928 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5932 // Treat indirect 'X' constraint as memory.
5933 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5935 OpInfo.ConstraintType = TargetLowering::C_Memory;
5937 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5938 std::vector<SDValue> Ops;
5939 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
5942 report_fatal_error("Invalid operand for inline asm constraint '" +
5943 Twine(OpInfo.ConstraintCode) + "'!");
5945 // Add information to the INLINEASM node to know about this input.
5946 unsigned ResOpType =
5947 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5948 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5949 TLI.getPointerTy()));
5950 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5954 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5955 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5956 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5957 "Memory operands expect pointer values");
5959 // Add information to the INLINEASM node to know about this input.
5960 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5961 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5962 TLI.getPointerTy()));
5963 AsmNodeOperands.push_back(InOperandVal);
5967 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5968 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5969 "Unknown constraint type!");
5970 assert(!OpInfo.isIndirect &&
5971 "Don't know how to handle indirect register inputs yet!");
5973 // Copy the input into the appropriate registers.
5974 if (OpInfo.AssignedRegs.Regs.empty() ||
5975 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5976 report_fatal_error("Couldn't allocate input reg for constraint '" +
5977 Twine(OpInfo.ConstraintCode) + "'!");
5979 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5982 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5983 DAG, AsmNodeOperands);
5986 case InlineAsm::isClobber: {
5987 // Add the clobbered value to the operand list, so that the register
5988 // allocator is aware that the physreg got clobbered.
5989 if (!OpInfo.AssignedRegs.Regs.empty())
5990 OpInfo.AssignedRegs.AddInlineAsmOperands(
5991 InlineAsm::Kind_RegDefEarlyClobber,
5999 // Finish up input operands. Set the input chain and add the flag last.
6000 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6001 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6003 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6004 DAG.getVTList(MVT::Other, MVT::Glue),
6005 &AsmNodeOperands[0], AsmNodeOperands.size());
6006 Flag = Chain.getValue(1);
6008 // If this asm returns a register value, copy the result from that register
6009 // and set it as the value of the call.
6010 if (!RetValRegs.Regs.empty()) {
6011 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6014 // FIXME: Why don't we do this for inline asms with MRVs?
6015 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6016 EVT ResultType = TLI.getValueType(CS.getType());
6018 // If any of the results of the inline asm is a vector, it may have the
6019 // wrong width/num elts. This can happen for register classes that can
6020 // contain multiple different value types. The preg or vreg allocated may
6021 // not have the same VT as was expected. Convert it to the right type
6022 // with bit_convert.
6023 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6024 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6027 } else if (ResultType != Val.getValueType() &&
6028 ResultType.isInteger() && Val.getValueType().isInteger()) {
6029 // If a result value was tied to an input value, the computed result may
6030 // have a wider width than the expected result. Extract the relevant
6032 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6035 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6038 setValue(CS.getInstruction(), Val);
6039 // Don't need to use this as a chain in this case.
6040 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6044 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6046 // Process indirect outputs, first output all of the flagged copies out of
6048 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6049 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6050 const Value *Ptr = IndirectStoresToEmit[i].second;
6051 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6053 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6056 // Emit the non-flagged stores from the physregs.
6057 SmallVector<SDValue, 8> OutChains;
6058 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6059 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6060 StoresToEmit[i].first,
6061 getValue(StoresToEmit[i].second),
6062 MachinePointerInfo(StoresToEmit[i].second),
6064 OutChains.push_back(Val);
6067 if (!OutChains.empty())
6068 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6069 &OutChains[0], OutChains.size());
6074 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6075 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6076 MVT::Other, getRoot(),
6077 getValue(I.getArgOperand(0)),
6078 DAG.getSrcValue(I.getArgOperand(0))));
6081 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6082 const TargetData &TD = *TLI.getTargetData();
6083 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6084 getRoot(), getValue(I.getOperand(0)),
6085 DAG.getSrcValue(I.getOperand(0)),
6086 TD.getABITypeAlignment(I.getType()));
6088 DAG.setRoot(V.getValue(1));
6091 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6092 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6093 MVT::Other, getRoot(),
6094 getValue(I.getArgOperand(0)),
6095 DAG.getSrcValue(I.getArgOperand(0))));
6098 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6099 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6100 MVT::Other, getRoot(),
6101 getValue(I.getArgOperand(0)),
6102 getValue(I.getArgOperand(1)),
6103 DAG.getSrcValue(I.getArgOperand(0)),
6104 DAG.getSrcValue(I.getArgOperand(1))));
6107 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6108 /// implementation, which just calls LowerCall.
6109 /// FIXME: When all targets are
6110 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6111 std::pair<SDValue, SDValue>
6112 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6113 bool RetSExt, bool RetZExt, bool isVarArg,
6114 bool isInreg, unsigned NumFixedArgs,
6115 CallingConv::ID CallConv, bool isTailCall,
6116 bool isReturnValueUsed,
6118 ArgListTy &Args, SelectionDAG &DAG,
6119 DebugLoc dl) const {
6120 // Handle all of the outgoing arguments.
6121 SmallVector<ISD::OutputArg, 32> Outs;
6122 SmallVector<SDValue, 32> OutVals;
6123 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6124 SmallVector<EVT, 4> ValueVTs;
6125 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6126 for (unsigned Value = 0, NumValues = ValueVTs.size();
6127 Value != NumValues; ++Value) {
6128 EVT VT = ValueVTs[Value];
6129 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6130 SDValue Op = SDValue(Args[i].Node.getNode(),
6131 Args[i].Node.getResNo() + Value);
6132 ISD::ArgFlagsTy Flags;
6133 unsigned OriginalAlignment =
6134 getTargetData()->getABITypeAlignment(ArgTy);
6140 if (Args[i].isInReg)
6144 if (Args[i].isByVal) {
6146 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6147 const Type *ElementTy = Ty->getElementType();
6148 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6149 // For ByVal, alignment should come from FE. BE will guess if this
6150 // info is not there but there are cases it cannot get right.
6151 unsigned FrameAlign;
6152 if (Args[i].Alignment)
6153 FrameAlign = Args[i].Alignment;
6155 FrameAlign = getByValTypeAlignment(ElementTy);
6156 Flags.setByValAlign(FrameAlign);
6160 Flags.setOrigAlign(OriginalAlignment);
6162 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6163 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6164 SmallVector<SDValue, 4> Parts(NumParts);
6165 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6168 ExtendKind = ISD::SIGN_EXTEND;
6169 else if (Args[i].isZExt)
6170 ExtendKind = ISD::ZERO_EXTEND;
6172 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6173 PartVT, ExtendKind);
6175 for (unsigned j = 0; j != NumParts; ++j) {
6176 // if it isn't first piece, alignment must be 1
6177 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6179 if (NumParts > 1 && j == 0)
6180 MyFlags.Flags.setSplit();
6182 MyFlags.Flags.setOrigAlign(1);
6184 Outs.push_back(MyFlags);
6185 OutVals.push_back(Parts[j]);
6190 // Handle the incoming return values from the call.
6191 SmallVector<ISD::InputArg, 32> Ins;
6192 SmallVector<EVT, 4> RetTys;
6193 ComputeValueVTs(*this, RetTy, RetTys);
6194 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6196 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6197 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6198 for (unsigned i = 0; i != NumRegs; ++i) {
6199 ISD::InputArg MyFlags;
6200 MyFlags.VT = RegisterVT.getSimpleVT();
6201 MyFlags.Used = isReturnValueUsed;
6203 MyFlags.Flags.setSExt();
6205 MyFlags.Flags.setZExt();
6207 MyFlags.Flags.setInReg();
6208 Ins.push_back(MyFlags);
6212 SmallVector<SDValue, 4> InVals;
6213 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6214 Outs, OutVals, Ins, dl, DAG, InVals);
6216 // Verify that the target's LowerCall behaved as expected.
6217 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6218 "LowerCall didn't return a valid chain!");
6219 assert((!isTailCall || InVals.empty()) &&
6220 "LowerCall emitted a return value for a tail call!");
6221 assert((isTailCall || InVals.size() == Ins.size()) &&
6222 "LowerCall didn't emit the correct number of values!");
6224 // For a tail call, the return value is merely live-out and there aren't
6225 // any nodes in the DAG representing it. Return a special value to
6226 // indicate that a tail call has been emitted and no more Instructions
6227 // should be processed in the current block.
6230 return std::make_pair(SDValue(), SDValue());
6233 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6234 assert(InVals[i].getNode() &&
6235 "LowerCall emitted a null value!");
6236 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6237 "LowerCall emitted a value with the wrong type!");
6240 // Collect the legal value parts into potentially illegal values
6241 // that correspond to the original function's return values.
6242 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6244 AssertOp = ISD::AssertSext;
6246 AssertOp = ISD::AssertZext;
6247 SmallVector<SDValue, 4> ReturnValues;
6248 unsigned CurReg = 0;
6249 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6251 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6252 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6254 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6255 NumRegs, RegisterVT, VT,
6260 // For a function returning void, there is no return value. We can't create
6261 // such a node, so we just return a null return value in that case. In
6262 // that case, nothing will actually look at the value.
6263 if (ReturnValues.empty())
6264 return std::make_pair(SDValue(), Chain);
6266 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6267 DAG.getVTList(&RetTys[0], RetTys.size()),
6268 &ReturnValues[0], ReturnValues.size());
6269 return std::make_pair(Res, Chain);
6272 void TargetLowering::LowerOperationWrapper(SDNode *N,
6273 SmallVectorImpl<SDValue> &Results,
6274 SelectionDAG &DAG) const {
6275 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6277 Results.push_back(Res);
6280 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6281 llvm_unreachable("LowerOperation not implemented for this target!");
6286 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6287 SDValue Op = getNonRegisterValue(V);
6288 assert((Op.getOpcode() != ISD::CopyFromReg ||
6289 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6290 "Copy from a reg to the same reg!");
6291 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6293 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6294 SDValue Chain = DAG.getEntryNode();
6295 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6296 PendingExports.push_back(Chain);
6299 #include "llvm/CodeGen/SelectionDAGISel.h"
6301 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6302 /// entry block, return true. This includes arguments used by switches, since
6303 /// the switch may expand into multiple basic blocks.
6304 static bool isOnlyUsedInEntryBlock(const Argument *A) {
6305 // With FastISel active, we may be splitting blocks, so force creation
6306 // of virtual registers for all non-dead arguments.
6308 return A->use_empty();
6310 const BasicBlock *Entry = A->getParent()->begin();
6311 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6313 const User *U = *UI;
6314 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6315 return false; // Use not in entry block.
6320 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6321 // If this is the entry block, emit arguments.
6322 const Function &F = *LLVMBB->getParent();
6323 SelectionDAG &DAG = SDB->DAG;
6324 DebugLoc dl = SDB->getCurDebugLoc();
6325 const TargetData *TD = TLI.getTargetData();
6326 SmallVector<ISD::InputArg, 16> Ins;
6328 // Check whether the function can return without sret-demotion.
6329 SmallVector<ISD::OutputArg, 4> Outs;
6330 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6333 if (!FuncInfo->CanLowerReturn) {
6334 // Put in an sret pointer parameter before all the other parameters.
6335 SmallVector<EVT, 1> ValueVTs;
6336 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6338 // NOTE: Assuming that a pointer will never break down to more than one VT
6340 ISD::ArgFlagsTy Flags;
6342 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6343 ISD::InputArg RetArg(Flags, RegisterVT, true);
6344 Ins.push_back(RetArg);
6347 // Set up the incoming argument description vector.
6349 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6350 I != E; ++I, ++Idx) {
6351 SmallVector<EVT, 4> ValueVTs;
6352 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6353 bool isArgValueUsed = !I->use_empty();
6354 for (unsigned Value = 0, NumValues = ValueVTs.size();
6355 Value != NumValues; ++Value) {
6356 EVT VT = ValueVTs[Value];
6357 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6358 ISD::ArgFlagsTy Flags;
6359 unsigned OriginalAlignment =
6360 TD->getABITypeAlignment(ArgTy);
6362 if (F.paramHasAttr(Idx, Attribute::ZExt))
6364 if (F.paramHasAttr(Idx, Attribute::SExt))
6366 if (F.paramHasAttr(Idx, Attribute::InReg))
6368 if (F.paramHasAttr(Idx, Attribute::StructRet))
6370 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6372 const PointerType *Ty = cast<PointerType>(I->getType());
6373 const Type *ElementTy = Ty->getElementType();
6374 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6375 // For ByVal, alignment should be passed from FE. BE will guess if
6376 // this info is not there but there are cases it cannot get right.
6377 unsigned FrameAlign;
6378 if (F.getParamAlignment(Idx))
6379 FrameAlign = F.getParamAlignment(Idx);
6381 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6382 Flags.setByValAlign(FrameAlign);
6384 if (F.paramHasAttr(Idx, Attribute::Nest))
6386 Flags.setOrigAlign(OriginalAlignment);
6388 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6389 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6390 for (unsigned i = 0; i != NumRegs; ++i) {
6391 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6392 if (NumRegs > 1 && i == 0)
6393 MyFlags.Flags.setSplit();
6394 // if it isn't first piece, alignment must be 1
6396 MyFlags.Flags.setOrigAlign(1);
6397 Ins.push_back(MyFlags);
6402 // Call the target to set up the argument values.
6403 SmallVector<SDValue, 8> InVals;
6404 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6408 // Verify that the target's LowerFormalArguments behaved as expected.
6409 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6410 "LowerFormalArguments didn't return a valid chain!");
6411 assert(InVals.size() == Ins.size() &&
6412 "LowerFormalArguments didn't emit the correct number of values!");
6414 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6415 assert(InVals[i].getNode() &&
6416 "LowerFormalArguments emitted a null value!");
6417 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6418 "LowerFormalArguments emitted a value with the wrong type!");
6422 // Update the DAG with the new chain value resulting from argument lowering.
6423 DAG.setRoot(NewRoot);
6425 // Set up the argument values.
6428 if (!FuncInfo->CanLowerReturn) {
6429 // Create a virtual register for the sret pointer, and put in a copy
6430 // from the sret argument into it.
6431 SmallVector<EVT, 1> ValueVTs;
6432 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6433 EVT VT = ValueVTs[0];
6434 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6435 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6436 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6437 RegVT, VT, AssertOp);
6439 MachineFunction& MF = SDB->DAG.getMachineFunction();
6440 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6441 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6442 FuncInfo->DemoteRegister = SRetReg;
6443 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6445 DAG.setRoot(NewRoot);
6447 // i indexes lowered arguments. Bump it past the hidden sret argument.
6448 // Idx indexes LLVM arguments. Don't touch it.
6452 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6454 SmallVector<SDValue, 4> ArgValues;
6455 SmallVector<EVT, 4> ValueVTs;
6456 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6457 unsigned NumValues = ValueVTs.size();
6459 // If this argument is unused then remember its value. It is used to generate
6460 // debugging information.
6461 if (I->use_empty() && NumValues)
6462 SDB->setUnusedArgValue(I, InVals[i]);
6464 for (unsigned Val = 0; Val != NumValues; ++Val) {
6465 EVT VT = ValueVTs[Val];
6466 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6467 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6469 if (!I->use_empty()) {
6470 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6471 if (F.paramHasAttr(Idx, Attribute::SExt))
6472 AssertOp = ISD::AssertSext;
6473 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6474 AssertOp = ISD::AssertZext;
6476 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6477 NumParts, PartVT, VT,
6484 // We don't need to do anything else for unused arguments.
6485 if (ArgValues.empty())
6488 // Note down frame index for byval arguments.
6489 if (I->hasByValAttr())
6490 if (FrameIndexSDNode *FI =
6491 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6492 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6494 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6495 SDB->getCurDebugLoc());
6496 SDB->setValue(I, Res);
6498 // If this argument is live outside of the entry block, insert a copy from
6499 // wherever we got it to the vreg that other BB's will reference it as.
6500 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6501 // If we can, though, try to skip creating an unnecessary vreg.
6502 // FIXME: This isn't very clean... it would be nice to make this more
6503 // general. It's also subtly incompatible with the hacks FastISel
6505 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6506 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6507 FuncInfo->ValueMap[I] = Reg;
6511 if (!isOnlyUsedInEntryBlock(I)) {
6512 FuncInfo->InitializeRegForValue(I);
6513 SDB->CopyToExportRegsIfNeeded(I);
6517 assert(i == InVals.size() && "Argument register count mismatch!");
6519 // Finally, if the target has anything special to do, allow it to do so.
6520 // FIXME: this should insert code into the DAG!
6521 EmitFunctionEntryCode();
6524 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6525 /// ensure constants are generated when needed. Remember the virtual registers
6526 /// that need to be added to the Machine PHI nodes as input. We cannot just
6527 /// directly add them, because expansion might result in multiple MBB's for one
6528 /// BB. As such, the start of the BB might correspond to a different MBB than
6532 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6533 const TerminatorInst *TI = LLVMBB->getTerminator();
6535 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6537 // Check successor nodes' PHI nodes that expect a constant to be available
6539 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6540 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6541 if (!isa<PHINode>(SuccBB->begin())) continue;
6542 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6544 // If this terminator has multiple identical successors (common for
6545 // switches), only handle each succ once.
6546 if (!SuccsHandled.insert(SuccMBB)) continue;
6548 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6550 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6551 // nodes and Machine PHI nodes, but the incoming operands have not been
6553 for (BasicBlock::const_iterator I = SuccBB->begin();
6554 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6555 // Ignore dead phi's.
6556 if (PN->use_empty()) continue;
6559 if (PN->getType()->isEmptyTy())
6563 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6565 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6566 unsigned &RegOut = ConstantsOut[C];
6568 RegOut = FuncInfo.CreateRegs(C->getType());
6569 CopyValueToVirtualRegister(C, RegOut);
6573 DenseMap<const Value *, unsigned>::iterator I =
6574 FuncInfo.ValueMap.find(PHIOp);
6575 if (I != FuncInfo.ValueMap.end())
6578 assert(isa<AllocaInst>(PHIOp) &&
6579 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6580 "Didn't codegen value into a register!??");
6581 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6582 CopyValueToVirtualRegister(PHIOp, Reg);
6586 // Remember that this register needs to added to the machine PHI node as
6587 // the input for this MBB.
6588 SmallVector<EVT, 4> ValueVTs;
6589 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6590 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6591 EVT VT = ValueVTs[vti];
6592 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6593 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6594 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6595 Reg += NumRegisters;
6599 ConstantsOut.clear();