1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 llvm_unreachable("should never codegen catchpads");
1166 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1167 // Update machine-CFG edge.
1168 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1169 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1170 PadMBB->addSuccessor(TargetMBB);
1172 // Create the terminator node.
1173 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1174 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1178 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1179 llvm_unreachable("should never codegen catchendpads");
1182 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1183 report_fatal_error("visitCleanupPad not yet implemented!");
1186 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1187 report_fatal_error("visitCleanupRet not yet implemented!");
1190 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1191 report_fatal_error("visitCleanupEndPad not yet implemented!");
1194 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1195 report_fatal_error("visitTerminatePad not yet implemented!");
1198 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1200 auto &DL = DAG.getDataLayout();
1201 SDValue Chain = getControlRoot();
1202 SmallVector<ISD::OutputArg, 8> Outs;
1203 SmallVector<SDValue, 8> OutVals;
1205 if (!FuncInfo.CanLowerReturn) {
1206 unsigned DemoteReg = FuncInfo.DemoteRegister;
1207 const Function *F = I.getParent()->getParent();
1209 // Emit a store of the return value through the virtual register.
1210 // Leave Outs empty so that LowerReturn won't try to load return
1211 // registers the usual way.
1212 SmallVector<EVT, 1> PtrValueVTs;
1213 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1216 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1217 SDValue RetOp = getValue(I.getOperand(0));
1219 SmallVector<EVT, 4> ValueVTs;
1220 SmallVector<uint64_t, 4> Offsets;
1221 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1222 unsigned NumValues = ValueVTs.size();
1224 SmallVector<SDValue, 4> Chains(NumValues);
1225 for (unsigned i = 0; i != NumValues; ++i) {
1226 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1227 RetPtr.getValueType(), RetPtr,
1228 DAG.getIntPtrConstant(Offsets[i],
1231 DAG.getStore(Chain, getCurSDLoc(),
1232 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1233 // FIXME: better loc info would be nice.
1234 Add, MachinePointerInfo(), false, false, 0);
1237 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1238 MVT::Other, Chains);
1239 } else if (I.getNumOperands() != 0) {
1240 SmallVector<EVT, 4> ValueVTs;
1241 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1242 unsigned NumValues = ValueVTs.size();
1244 SDValue RetOp = getValue(I.getOperand(0));
1246 const Function *F = I.getParent()->getParent();
1248 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1249 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1251 ExtendKind = ISD::SIGN_EXTEND;
1252 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1254 ExtendKind = ISD::ZERO_EXTEND;
1256 LLVMContext &Context = F->getContext();
1257 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 for (unsigned j = 0; j != NumValues; ++j) {
1261 EVT VT = ValueVTs[j];
1263 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1264 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1266 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1267 MVT PartVT = TLI.getRegisterType(Context, VT);
1268 SmallVector<SDValue, 4> Parts(NumParts);
1269 getCopyToParts(DAG, getCurSDLoc(),
1270 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1271 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1273 // 'inreg' on function refers to return value
1274 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1278 // Propagate extension type if any
1279 if (ExtendKind == ISD::SIGN_EXTEND)
1281 else if (ExtendKind == ISD::ZERO_EXTEND)
1284 for (unsigned i = 0; i < NumParts; ++i) {
1285 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1286 VT, /*isfixed=*/true, 0, 0));
1287 OutVals.push_back(Parts[i]);
1293 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1294 CallingConv::ID CallConv =
1295 DAG.getMachineFunction().getFunction()->getCallingConv();
1296 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1297 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1299 // Verify that the target's LowerReturn behaved as expected.
1300 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1301 "LowerReturn didn't return a valid chain!");
1303 // Update the DAG with the new chain value resulting from return lowering.
1307 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1308 /// created for it, emit nodes to copy the value into the virtual
1310 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1312 if (V->getType()->isEmptyTy())
1315 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1316 if (VMI != FuncInfo.ValueMap.end()) {
1317 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1318 CopyValueToVirtualRegister(V, VMI->second);
1322 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1323 /// the current basic block, add it to ValueMap now so that we'll get a
1325 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1326 // No need to export constants.
1327 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1329 // Already exported?
1330 if (FuncInfo.isExportedInst(V)) return;
1332 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1333 CopyValueToVirtualRegister(V, Reg);
1336 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1337 const BasicBlock *FromBB) {
1338 // The operands of the setcc have to be in this block. We don't know
1339 // how to export them from some other block.
1340 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1341 // Can export from current BB.
1342 if (VI->getParent() == FromBB)
1345 // Is already exported, noop.
1346 return FuncInfo.isExportedInst(V);
1349 // If this is an argument, we can export it if the BB is the entry block or
1350 // if it is already exported.
1351 if (isa<Argument>(V)) {
1352 if (FromBB == &FromBB->getParent()->getEntryBlock())
1355 // Otherwise, can only export this if it is already exported.
1356 return FuncInfo.isExportedInst(V);
1359 // Otherwise, constants can always be exported.
1363 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1364 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1365 const MachineBasicBlock *Dst) const {
1366 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1369 const BasicBlock *SrcBB = Src->getBasicBlock();
1370 const BasicBlock *DstBB = Dst->getBasicBlock();
1371 return BPI->getEdgeWeight(SrcBB, DstBB);
1374 void SelectionDAGBuilder::
1375 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1376 uint32_t Weight /* = 0 */) {
1378 Weight = getEdgeWeight(Src, Dst);
1379 Src->addSuccessor(Dst, Weight);
1383 static bool InBlock(const Value *V, const BasicBlock *BB) {
1384 if (const Instruction *I = dyn_cast<Instruction>(V))
1385 return I->getParent() == BB;
1389 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1390 /// This function emits a branch and is used at the leaves of an OR or an
1391 /// AND operator tree.
1394 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1395 MachineBasicBlock *TBB,
1396 MachineBasicBlock *FBB,
1397 MachineBasicBlock *CurBB,
1398 MachineBasicBlock *SwitchBB,
1401 const BasicBlock *BB = CurBB->getBasicBlock();
1403 // If the leaf of the tree is a comparison, merge the condition into
1405 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1406 // The operands of the cmp have to be in this block. We don't know
1407 // how to export them from some other block. If this is the first block
1408 // of the sequence, no exporting is needed.
1409 if (CurBB == SwitchBB ||
1410 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1411 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1412 ISD::CondCode Condition;
1413 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1414 Condition = getICmpCondCode(IC->getPredicate());
1416 const FCmpInst *FC = cast<FCmpInst>(Cond);
1417 Condition = getFCmpCondCode(FC->getPredicate());
1418 if (TM.Options.NoNaNsFPMath)
1419 Condition = getFCmpCodeWithoutNaN(Condition);
1422 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1423 TBB, FBB, CurBB, TWeight, FWeight);
1424 SwitchCases.push_back(CB);
1429 // Create a CaseBlock record representing this branch.
1430 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1431 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1432 SwitchCases.push_back(CB);
1435 /// Scale down both weights to fit into uint32_t.
1436 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1437 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1438 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1439 NewTrue = NewTrue / Scale;
1440 NewFalse = NewFalse / Scale;
1443 /// FindMergedConditions - If Cond is an expression like
1444 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1445 MachineBasicBlock *TBB,
1446 MachineBasicBlock *FBB,
1447 MachineBasicBlock *CurBB,
1448 MachineBasicBlock *SwitchBB,
1449 Instruction::BinaryOps Opc,
1452 // If this node is not part of the or/and tree, emit it as a branch.
1453 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1454 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1455 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1456 BOp->getParent() != CurBB->getBasicBlock() ||
1457 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1458 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1459 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1464 // Create TmpBB after CurBB.
1465 MachineFunction::iterator BBI = CurBB;
1466 MachineFunction &MF = DAG.getMachineFunction();
1467 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1468 CurBB->getParent()->insert(++BBI, TmpBB);
1470 if (Opc == Instruction::Or) {
1471 // Codegen X | Y as:
1480 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1481 // The requirement is that
1482 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1483 // = TrueProb for original BB.
1484 // Assuming the original weights are A and B, one choice is to set BB1's
1485 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1487 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1488 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1489 // TmpBB, but the math is more complicated.
1491 uint64_t NewTrueWeight = TWeight;
1492 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1493 ScaleWeights(NewTrueWeight, NewFalseWeight);
1494 // Emit the LHS condition.
1495 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1496 NewTrueWeight, NewFalseWeight);
1498 NewTrueWeight = TWeight;
1499 NewFalseWeight = 2 * (uint64_t)FWeight;
1500 ScaleWeights(NewTrueWeight, NewFalseWeight);
1501 // Emit the RHS condition into TmpBB.
1502 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1503 NewTrueWeight, NewFalseWeight);
1505 assert(Opc == Instruction::And && "Unknown merge op!");
1506 // Codegen X & Y as:
1514 // This requires creation of TmpBB after CurBB.
1516 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1517 // The requirement is that
1518 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1519 // = FalseProb for original BB.
1520 // Assuming the original weights are A and B, one choice is to set BB1's
1521 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1523 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1525 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1526 uint64_t NewFalseWeight = FWeight;
1527 ScaleWeights(NewTrueWeight, NewFalseWeight);
1528 // Emit the LHS condition.
1529 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1530 NewTrueWeight, NewFalseWeight);
1532 NewTrueWeight = 2 * (uint64_t)TWeight;
1533 NewFalseWeight = FWeight;
1534 ScaleWeights(NewTrueWeight, NewFalseWeight);
1535 // Emit the RHS condition into TmpBB.
1536 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1537 NewTrueWeight, NewFalseWeight);
1541 /// If the set of cases should be emitted as a series of branches, return true.
1542 /// If we should emit this as a bunch of and/or'd together conditions, return
1545 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1546 if (Cases.size() != 2) return true;
1548 // If this is two comparisons of the same values or'd or and'd together, they
1549 // will get folded into a single comparison, so don't emit two blocks.
1550 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1551 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1552 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1553 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1557 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1558 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1559 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1560 Cases[0].CC == Cases[1].CC &&
1561 isa<Constant>(Cases[0].CmpRHS) &&
1562 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1563 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1565 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1572 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1573 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1575 // Update machine-CFG edges.
1576 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1578 if (I.isUnconditional()) {
1579 // Update machine-CFG edges.
1580 BrMBB->addSuccessor(Succ0MBB);
1582 // If this is not a fall-through branch or optimizations are switched off,
1584 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1585 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1586 MVT::Other, getControlRoot(),
1587 DAG.getBasicBlock(Succ0MBB)));
1592 // If this condition is one of the special cases we handle, do special stuff
1594 const Value *CondVal = I.getCondition();
1595 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1597 // If this is a series of conditions that are or'd or and'd together, emit
1598 // this as a sequence of branches instead of setcc's with and/or operations.
1599 // As long as jumps are not expensive, this should improve performance.
1600 // For example, instead of something like:
1613 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1614 Instruction::BinaryOps Opcode = BOp->getOpcode();
1615 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1616 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1617 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1618 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1619 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1620 getEdgeWeight(BrMBB, Succ1MBB));
1621 // If the compares in later blocks need to use values not currently
1622 // exported from this block, export them now. This block should always
1623 // be the first entry.
1624 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1626 // Allow some cases to be rejected.
1627 if (ShouldEmitAsBranches(SwitchCases)) {
1628 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1629 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1630 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1633 // Emit the branch for this block.
1634 visitSwitchCase(SwitchCases[0], BrMBB);
1635 SwitchCases.erase(SwitchCases.begin());
1639 // Okay, we decided not to do this, remove any inserted MBB's and clear
1641 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1642 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1644 SwitchCases.clear();
1648 // Create a CaseBlock record representing this branch.
1649 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1650 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1652 // Use visitSwitchCase to actually insert the fast branch sequence for this
1654 visitSwitchCase(CB, BrMBB);
1657 /// visitSwitchCase - Emits the necessary code to represent a single node in
1658 /// the binary search tree resulting from lowering a switch instruction.
1659 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1660 MachineBasicBlock *SwitchBB) {
1662 SDValue CondLHS = getValue(CB.CmpLHS);
1663 SDLoc dl = getCurSDLoc();
1665 // Build the setcc now.
1667 // Fold "(X == true)" to X and "(X == false)" to !X to
1668 // handle common cases produced by branch lowering.
1669 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1670 CB.CC == ISD::SETEQ)
1672 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1673 CB.CC == ISD::SETEQ) {
1674 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1675 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1677 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1679 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1681 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1682 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1684 SDValue CmpOp = getValue(CB.CmpMHS);
1685 EVT VT = CmpOp.getValueType();
1687 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1688 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1691 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1692 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1693 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1694 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1698 // Update successor info
1699 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1700 // TrueBB and FalseBB are always different unless the incoming IR is
1701 // degenerate. This only happens when running llc on weird IR.
1702 if (CB.TrueBB != CB.FalseBB)
1703 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1705 // If the lhs block is the next block, invert the condition so that we can
1706 // fall through to the lhs instead of the rhs block.
1707 if (CB.TrueBB == NextBlock(SwitchBB)) {
1708 std::swap(CB.TrueBB, CB.FalseBB);
1709 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1710 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1713 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1714 MVT::Other, getControlRoot(), Cond,
1715 DAG.getBasicBlock(CB.TrueBB));
1717 // Insert the false branch. Do this even if it's a fall through branch,
1718 // this makes it easier to do DAG optimizations which require inverting
1719 // the branch condition.
1720 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1721 DAG.getBasicBlock(CB.FalseBB));
1723 DAG.setRoot(BrCond);
1726 /// visitJumpTable - Emit JumpTable node in the current MBB
1727 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1728 // Emit the code for the jump table
1729 assert(JT.Reg != -1U && "Should lower JT Header first!");
1730 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1731 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1733 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1734 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1735 MVT::Other, Index.getValue(1),
1737 DAG.setRoot(BrJumpTable);
1740 /// visitJumpTableHeader - This function emits necessary code to produce index
1741 /// in the JumpTable from switch case.
1742 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1743 JumpTableHeader &JTH,
1744 MachineBasicBlock *SwitchBB) {
1745 SDLoc dl = getCurSDLoc();
1747 // Subtract the lowest switch case value from the value being switched on and
1748 // conditional branch to default mbb if the result is greater than the
1749 // difference between smallest and largest cases.
1750 SDValue SwitchOp = getValue(JTH.SValue);
1751 EVT VT = SwitchOp.getValueType();
1752 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1753 DAG.getConstant(JTH.First, dl, VT));
1755 // The SDNode we just created, which holds the value being switched on minus
1756 // the smallest case value, needs to be copied to a virtual register so it
1757 // can be used as an index into the jump table in a subsequent basic block.
1758 // This value may be smaller or larger than the target's pointer type, and
1759 // therefore require extension or truncating.
1760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1761 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1763 unsigned JumpTableReg =
1764 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1765 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1766 JumpTableReg, SwitchOp);
1767 JT.Reg = JumpTableReg;
1769 // Emit the range check for the jump table, and branch to the default block
1770 // for the switch statement if the value being switched on exceeds the largest
1771 // case in the switch.
1772 SDValue CMP = DAG.getSetCC(
1773 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1774 Sub.getValueType()),
1775 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1777 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1778 MVT::Other, CopyTo, CMP,
1779 DAG.getBasicBlock(JT.Default));
1781 // Avoid emitting unnecessary branches to the next block.
1782 if (JT.MBB != NextBlock(SwitchBB))
1783 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1784 DAG.getBasicBlock(JT.MBB));
1786 DAG.setRoot(BrCond);
1789 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1790 /// tail spliced into a stack protector check success bb.
1792 /// For a high level explanation of how this fits into the stack protector
1793 /// generation see the comment on the declaration of class
1794 /// StackProtectorDescriptor.
1795 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1796 MachineBasicBlock *ParentBB) {
1798 // First create the loads to the guard/stack slot for the comparison.
1799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1800 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1802 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1803 int FI = MFI->getStackProtectorIndex();
1805 const Value *IRGuard = SPD.getGuard();
1806 SDValue GuardPtr = getValue(IRGuard);
1807 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1809 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1812 SDLoc dl = getCurSDLoc();
1814 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1815 // guard value from the virtual register holding the value. Otherwise, emit a
1816 // volatile load to retrieve the stack guard value.
1817 unsigned GuardReg = SPD.getGuardReg();
1819 if (GuardReg && TLI.useLoadStackGuardNode())
1820 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1823 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1824 GuardPtr, MachinePointerInfo(IRGuard, 0),
1825 true, false, false, Align);
1827 SDValue StackSlot = DAG.getLoad(
1828 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1829 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1830 false, false, Align);
1832 // Perform the comparison via a subtract/getsetcc.
1833 EVT VT = Guard.getValueType();
1834 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1836 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1838 Sub.getValueType()),
1839 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1841 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1842 // branch to failure MBB.
1843 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1844 MVT::Other, StackSlot.getOperand(0),
1845 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1846 // Otherwise branch to success MBB.
1847 SDValue Br = DAG.getNode(ISD::BR, dl,
1849 DAG.getBasicBlock(SPD.getSuccessMBB()));
1854 /// Codegen the failure basic block for a stack protector check.
1856 /// A failure stack protector machine basic block consists simply of a call to
1857 /// __stack_chk_fail().
1859 /// For a high level explanation of how this fits into the stack protector
1860 /// generation see the comment on the declaration of class
1861 /// StackProtectorDescriptor.
1863 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1866 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1867 nullptr, 0, false, getCurSDLoc(), false, false).second;
1871 /// visitBitTestHeader - This function emits necessary code to produce value
1872 /// suitable for "bit tests"
1873 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1874 MachineBasicBlock *SwitchBB) {
1875 SDLoc dl = getCurSDLoc();
1877 // Subtract the minimum value
1878 SDValue SwitchOp = getValue(B.SValue);
1879 EVT VT = SwitchOp.getValueType();
1880 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1881 DAG.getConstant(B.First, dl, VT));
1884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1885 SDValue RangeCmp = DAG.getSetCC(
1886 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1887 Sub.getValueType()),
1888 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1890 // Determine the type of the test operands.
1891 bool UsePtrType = false;
1892 if (!TLI.isTypeLegal(VT))
1895 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1896 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1897 // Switch table case range are encoded into series of masks.
1898 // Just use pointer type, it's guaranteed to fit.
1904 VT = TLI.getPointerTy(DAG.getDataLayout());
1905 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1908 B.RegVT = VT.getSimpleVT();
1909 B.Reg = FuncInfo.CreateReg(B.RegVT);
1910 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1912 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1914 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1915 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1917 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1918 MVT::Other, CopyTo, RangeCmp,
1919 DAG.getBasicBlock(B.Default));
1921 // Avoid emitting unnecessary branches to the next block.
1922 if (MBB != NextBlock(SwitchBB))
1923 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1924 DAG.getBasicBlock(MBB));
1926 DAG.setRoot(BrRange);
1929 /// visitBitTestCase - this function produces one "bit test"
1930 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1931 MachineBasicBlock* NextMBB,
1932 uint32_t BranchWeightToNext,
1935 MachineBasicBlock *SwitchBB) {
1936 SDLoc dl = getCurSDLoc();
1938 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1940 unsigned PopCount = countPopulation(B.Mask);
1941 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1942 if (PopCount == 1) {
1943 // Testing for a single bit; just compare the shift count with what it
1944 // would need to be to shift a 1 bit in that position.
1946 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1947 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1949 } else if (PopCount == BB.Range) {
1950 // There is only one zero bit in the range, test for it directly.
1952 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1953 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1956 // Make desired shift
1957 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1958 DAG.getConstant(1, dl, VT), ShiftOp);
1960 // Emit bit tests and jumps
1961 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1962 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1964 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1965 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1968 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1969 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1970 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1971 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1973 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1974 MVT::Other, getControlRoot(),
1975 Cmp, DAG.getBasicBlock(B.TargetBB));
1977 // Avoid emitting unnecessary branches to the next block.
1978 if (NextMBB != NextBlock(SwitchBB))
1979 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1980 DAG.getBasicBlock(NextMBB));
1985 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1986 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1988 // Retrieve successors. Look through artificial IR level blocks like catchpads
1989 // and catchendpads for successors.
1990 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1991 const BasicBlock *EHPadBB = I.getSuccessor(1);
1993 const Value *Callee(I.getCalledValue());
1994 const Function *Fn = dyn_cast<Function>(Callee);
1995 if (isa<InlineAsm>(Callee))
1997 else if (Fn && Fn->isIntrinsic()) {
1998 switch (Fn->getIntrinsicID()) {
2000 llvm_unreachable("Cannot invoke this intrinsic");
2001 case Intrinsic::donothing:
2002 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2004 case Intrinsic::experimental_patchpoint_void:
2005 case Intrinsic::experimental_patchpoint_i64:
2006 visitPatchpoint(&I, EHPadBB);
2008 case Intrinsic::experimental_gc_statepoint:
2009 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2013 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2015 // If the value of the invoke is used outside of its defining block, make it
2016 // available as a virtual register.
2017 // We already took care of the exported value for the statepoint instruction
2018 // during call to the LowerStatepoint.
2019 if (!isStatepoint(I)) {
2020 CopyToExportRegsIfNeeded(&I);
2023 // Stop when we hit a pad that generates real code or we unwind to caller.
2024 // Catchpads are conditional branches that add real MBB destinations and
2025 // continue the loop. EH "end" pads are not real BBs and simply continue.
2026 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2027 bool IsMSVCCXX = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()) ==
2028 EHPersonality::MSVC_CXX;
2030 const Instruction *Pad = EHPadBB->getFirstNonPHI();
2031 if (isa<LandingPadInst>(Pad)) {
2032 // Stop on landingpads. They are not funclets.
2033 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
2035 } else if (isa<CleanupPadInst>(Pad) || isa<LandingPadInst>(Pad)) {
2036 // Stop on cleanup pads. Cleanups are always funclet entries for all known
2038 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
2039 UnwindDests.back()->setIsEHFuncletEntry();
2041 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
2042 // Add the catchpad handler to the possible destinations.
2043 UnwindDests.push_back(FuncInfo.MBBMap[CPI->getNormalDest()]);
2044 // In MSVC C++, catchblocks are funclets and need prologues.
2046 UnwindDests.back()->setIsEHFuncletEntry();
2047 EHPadBB = CPI->getUnwindDest();
2048 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
2049 EHPadBB = CEPI->getUnwindDest();
2050 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
2051 EHPadBB = CEPI->getUnwindDest();
2055 // Update successor info.
2056 // FIXME: The weights for catchpads will be wrong.
2057 addSuccessorWithWeight(InvokeMBB, Return);
2058 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2059 UnwindDest->setIsEHPad();
2060 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2063 // Drop into normal successor.
2064 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2065 MVT::Other, getControlRoot(),
2066 DAG.getBasicBlock(Return)));
2069 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2070 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2073 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2074 assert(FuncInfo.MBB->isEHPad() &&
2075 "Call to landingpad not in landing pad!");
2077 MachineBasicBlock *MBB = FuncInfo.MBB;
2078 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2079 AddLandingPadInfo(LP, MMI, MBB);
2081 // If there aren't registers to copy the values into (e.g., during SjLj
2082 // exceptions), then don't bother to create these DAG nodes.
2083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2084 if (TLI.getExceptionPointerRegister() == 0 &&
2085 TLI.getExceptionSelectorRegister() == 0)
2088 SmallVector<EVT, 2> ValueVTs;
2089 SDLoc dl = getCurSDLoc();
2090 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2091 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2093 // Get the two live-in registers as SDValues. The physregs have already been
2094 // copied into virtual registers.
2096 if (FuncInfo.ExceptionPointerVirtReg) {
2097 Ops[0] = DAG.getZExtOrTrunc(
2098 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2099 FuncInfo.ExceptionPointerVirtReg,
2100 TLI.getPointerTy(DAG.getDataLayout())),
2103 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2105 Ops[1] = DAG.getZExtOrTrunc(
2106 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2107 FuncInfo.ExceptionSelectorVirtReg,
2108 TLI.getPointerTy(DAG.getDataLayout())),
2112 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2113 DAG.getVTList(ValueVTs), Ops);
2117 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2119 for (const CaseCluster &CC : Clusters)
2120 assert(CC.Low == CC.High && "Input clusters must be single-case");
2123 std::sort(Clusters.begin(), Clusters.end(),
2124 [](const CaseCluster &a, const CaseCluster &b) {
2125 return a.Low->getValue().slt(b.Low->getValue());
2128 // Merge adjacent clusters with the same destination.
2129 const unsigned N = Clusters.size();
2130 unsigned DstIndex = 0;
2131 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2132 CaseCluster &CC = Clusters[SrcIndex];
2133 const ConstantInt *CaseVal = CC.Low;
2134 MachineBasicBlock *Succ = CC.MBB;
2136 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2137 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2138 // If this case has the same successor and is a neighbour, merge it into
2139 // the previous cluster.
2140 Clusters[DstIndex - 1].High = CaseVal;
2141 Clusters[DstIndex - 1].Weight += CC.Weight;
2142 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2144 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2145 sizeof(Clusters[SrcIndex]));
2148 Clusters.resize(DstIndex);
2151 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2152 MachineBasicBlock *Last) {
2154 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2155 if (JTCases[i].first.HeaderBB == First)
2156 JTCases[i].first.HeaderBB = Last;
2158 // Update BitTestCases.
2159 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2160 if (BitTestCases[i].Parent == First)
2161 BitTestCases[i].Parent = Last;
2164 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2165 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2167 // Update machine-CFG edges with unique successors.
2168 SmallSet<BasicBlock*, 32> Done;
2169 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2170 BasicBlock *BB = I.getSuccessor(i);
2171 bool Inserted = Done.insert(BB).second;
2175 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2176 addSuccessorWithWeight(IndirectBrMBB, Succ);
2179 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2180 MVT::Other, getControlRoot(),
2181 getValue(I.getAddress())));
2184 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2185 if (DAG.getTarget().Options.TrapUnreachable)
2186 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2189 void SelectionDAGBuilder::visitFSub(const User &I) {
2190 // -0.0 - X --> fneg
2191 Type *Ty = I.getType();
2192 if (isa<Constant>(I.getOperand(0)) &&
2193 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2194 SDValue Op2 = getValue(I.getOperand(1));
2195 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2196 Op2.getValueType(), Op2));
2200 visitBinary(I, ISD::FSUB);
2203 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2204 SDValue Op1 = getValue(I.getOperand(0));
2205 SDValue Op2 = getValue(I.getOperand(1));
2212 if (const OverflowingBinaryOperator *OFBinOp =
2213 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2214 nuw = OFBinOp->hasNoUnsignedWrap();
2215 nsw = OFBinOp->hasNoSignedWrap();
2217 if (const PossiblyExactOperator *ExactOp =
2218 dyn_cast<const PossiblyExactOperator>(&I))
2219 exact = ExactOp->isExact();
2220 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2221 FMF = FPOp->getFastMathFlags();
2224 Flags.setExact(exact);
2225 Flags.setNoSignedWrap(nsw);
2226 Flags.setNoUnsignedWrap(nuw);
2227 if (EnableFMFInDAG) {
2228 Flags.setAllowReciprocal(FMF.allowReciprocal());
2229 Flags.setNoInfs(FMF.noInfs());
2230 Flags.setNoNaNs(FMF.noNaNs());
2231 Flags.setNoSignedZeros(FMF.noSignedZeros());
2232 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2234 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2236 setValue(&I, BinNodeValue);
2239 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2240 SDValue Op1 = getValue(I.getOperand(0));
2241 SDValue Op2 = getValue(I.getOperand(1));
2243 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2244 Op2.getValueType(), DAG.getDataLayout());
2246 // Coerce the shift amount to the right type if we can.
2247 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2248 unsigned ShiftSize = ShiftTy.getSizeInBits();
2249 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2250 SDLoc DL = getCurSDLoc();
2252 // If the operand is smaller than the shift count type, promote it.
2253 if (ShiftSize > Op2Size)
2254 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2256 // If the operand is larger than the shift count type but the shift
2257 // count type has enough bits to represent any shift value, truncate
2258 // it now. This is a common case and it exposes the truncate to
2259 // optimization early.
2260 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2261 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2262 // Otherwise we'll need to temporarily settle for some other convenient
2263 // type. Type legalization will make adjustments once the shiftee is split.
2265 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2272 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2274 if (const OverflowingBinaryOperator *OFBinOp =
2275 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2276 nuw = OFBinOp->hasNoUnsignedWrap();
2277 nsw = OFBinOp->hasNoSignedWrap();
2279 if (const PossiblyExactOperator *ExactOp =
2280 dyn_cast<const PossiblyExactOperator>(&I))
2281 exact = ExactOp->isExact();
2284 Flags.setExact(exact);
2285 Flags.setNoSignedWrap(nsw);
2286 Flags.setNoUnsignedWrap(nuw);
2287 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2292 void SelectionDAGBuilder::visitSDiv(const User &I) {
2293 SDValue Op1 = getValue(I.getOperand(0));
2294 SDValue Op2 = getValue(I.getOperand(1));
2297 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2298 cast<PossiblyExactOperator>(&I)->isExact());
2299 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2303 void SelectionDAGBuilder::visitICmp(const User &I) {
2304 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2305 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2306 predicate = IC->getPredicate();
2307 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2308 predicate = ICmpInst::Predicate(IC->getPredicate());
2309 SDValue Op1 = getValue(I.getOperand(0));
2310 SDValue Op2 = getValue(I.getOperand(1));
2311 ISD::CondCode Opcode = getICmpCondCode(predicate);
2313 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2315 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2318 void SelectionDAGBuilder::visitFCmp(const User &I) {
2319 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2320 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2321 predicate = FC->getPredicate();
2322 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2323 predicate = FCmpInst::Predicate(FC->getPredicate());
2324 SDValue Op1 = getValue(I.getOperand(0));
2325 SDValue Op2 = getValue(I.getOperand(1));
2326 ISD::CondCode Condition = getFCmpCondCode(predicate);
2327 if (TM.Options.NoNaNsFPMath)
2328 Condition = getFCmpCodeWithoutNaN(Condition);
2329 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2331 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2334 void SelectionDAGBuilder::visitSelect(const User &I) {
2335 SmallVector<EVT, 4> ValueVTs;
2336 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2338 unsigned NumValues = ValueVTs.size();
2339 if (NumValues == 0) return;
2341 SmallVector<SDValue, 4> Values(NumValues);
2342 SDValue Cond = getValue(I.getOperand(0));
2343 SDValue LHSVal = getValue(I.getOperand(1));
2344 SDValue RHSVal = getValue(I.getOperand(2));
2345 auto BaseOps = {Cond};
2346 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2347 ISD::VSELECT : ISD::SELECT;
2349 // Min/max matching is only viable if all output VTs are the same.
2350 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2351 EVT VT = ValueVTs[0];
2352 LLVMContext &Ctx = *DAG.getContext();
2353 auto &TLI = DAG.getTargetLoweringInfo();
2354 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2355 VT = TLI.getTypeToTransformTo(Ctx, VT);
2358 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2359 ISD::NodeType Opc = ISD::DELETED_NODE;
2360 switch (SPR.Flavor) {
2361 case SPF_UMAX: Opc = ISD::UMAX; break;
2362 case SPF_UMIN: Opc = ISD::UMIN; break;
2363 case SPF_SMAX: Opc = ISD::SMAX; break;
2364 case SPF_SMIN: Opc = ISD::SMIN; break;
2366 switch (SPR.NaNBehavior) {
2367 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2368 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2369 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2370 case SPNB_RETURNS_ANY:
2371 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2377 switch (SPR.NaNBehavior) {
2378 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2379 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2380 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2381 case SPNB_RETURNS_ANY:
2382 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2390 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2391 // If the underlying comparison instruction is used by any other instruction,
2392 // the consumed instructions won't be destroyed, so it is not profitable
2393 // to convert to a min/max.
2394 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2396 LHSVal = getValue(LHS);
2397 RHSVal = getValue(RHS);
2402 for (unsigned i = 0; i != NumValues; ++i) {
2403 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2404 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2405 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2406 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2407 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2411 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2412 DAG.getVTList(ValueVTs), Values));
2415 void SelectionDAGBuilder::visitTrunc(const User &I) {
2416 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2417 SDValue N = getValue(I.getOperand(0));
2418 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2420 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2423 void SelectionDAGBuilder::visitZExt(const User &I) {
2424 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2425 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2426 SDValue N = getValue(I.getOperand(0));
2427 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2429 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2432 void SelectionDAGBuilder::visitSExt(const User &I) {
2433 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2434 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2435 SDValue N = getValue(I.getOperand(0));
2436 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2438 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2441 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2442 // FPTrunc is never a no-op cast, no need to check
2443 SDValue N = getValue(I.getOperand(0));
2444 SDLoc dl = getCurSDLoc();
2445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2446 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2447 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2448 DAG.getTargetConstant(
2449 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2452 void SelectionDAGBuilder::visitFPExt(const User &I) {
2453 // FPExt is never a no-op cast, no need to check
2454 SDValue N = getValue(I.getOperand(0));
2455 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2457 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2460 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2461 // FPToUI is never a no-op cast, no need to check
2462 SDValue N = getValue(I.getOperand(0));
2463 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2465 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2468 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2469 // FPToSI is never a no-op cast, no need to check
2470 SDValue N = getValue(I.getOperand(0));
2471 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2473 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2476 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2477 // UIToFP is never a no-op cast, no need to check
2478 SDValue N = getValue(I.getOperand(0));
2479 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2481 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2484 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2485 // SIToFP is never a no-op cast, no need to check
2486 SDValue N = getValue(I.getOperand(0));
2487 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2489 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2492 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2493 // What to do depends on the size of the integer and the size of the pointer.
2494 // We can either truncate, zero extend, or no-op, accordingly.
2495 SDValue N = getValue(I.getOperand(0));
2496 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2498 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2501 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2502 // What to do depends on the size of the integer and the size of the pointer.
2503 // We can either truncate, zero extend, or no-op, accordingly.
2504 SDValue N = getValue(I.getOperand(0));
2505 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2507 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2510 void SelectionDAGBuilder::visitBitCast(const User &I) {
2511 SDValue N = getValue(I.getOperand(0));
2512 SDLoc dl = getCurSDLoc();
2513 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2516 // BitCast assures us that source and destination are the same size so this is
2517 // either a BITCAST or a no-op.
2518 if (DestVT != N.getValueType())
2519 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2520 DestVT, N)); // convert types.
2521 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2522 // might fold any kind of constant expression to an integer constant and that
2523 // is not what we are looking for. Only regcognize a bitcast of a genuine
2524 // constant integer as an opaque constant.
2525 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2526 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2529 setValue(&I, N); // noop cast.
2532 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2533 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2534 const Value *SV = I.getOperand(0);
2535 SDValue N = getValue(SV);
2536 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2538 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2539 unsigned DestAS = I.getType()->getPointerAddressSpace();
2541 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2542 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2547 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2548 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2549 SDValue InVec = getValue(I.getOperand(0));
2550 SDValue InVal = getValue(I.getOperand(1));
2551 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2552 TLI.getVectorIdxTy(DAG.getDataLayout()));
2553 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2554 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2555 InVec, InVal, InIdx));
2558 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2560 SDValue InVec = getValue(I.getOperand(0));
2561 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2562 TLI.getVectorIdxTy(DAG.getDataLayout()));
2563 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2564 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2568 // Utility for visitShuffleVector - Return true if every element in Mask,
2569 // beginning from position Pos and ending in Pos+Size, falls within the
2570 // specified sequential range [L, L+Pos). or is undef.
2571 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2572 unsigned Pos, unsigned Size, int Low) {
2573 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2574 if (Mask[i] >= 0 && Mask[i] != Low)
2579 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2580 SDValue Src1 = getValue(I.getOperand(0));
2581 SDValue Src2 = getValue(I.getOperand(1));
2583 SmallVector<int, 8> Mask;
2584 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2585 unsigned MaskNumElts = Mask.size();
2587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2588 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2589 EVT SrcVT = Src1.getValueType();
2590 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2592 if (SrcNumElts == MaskNumElts) {
2593 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2598 // Normalize the shuffle vector since mask and vector length don't match.
2599 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2600 // Mask is longer than the source vectors and is a multiple of the source
2601 // vectors. We can use concatenate vector to make the mask and vectors
2603 if (SrcNumElts*2 == MaskNumElts) {
2604 // First check for Src1 in low and Src2 in high
2605 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2606 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2607 // The shuffle is concatenating two vectors together.
2608 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2612 // Then check for Src2 in low and Src1 in high
2613 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2614 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2615 // The shuffle is concatenating two vectors together.
2616 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2622 // Pad both vectors with undefs to make them the same length as the mask.
2623 unsigned NumConcat = MaskNumElts / SrcNumElts;
2624 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2625 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2626 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2628 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2629 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2633 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2634 getCurSDLoc(), VT, MOps1);
2635 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2636 getCurSDLoc(), VT, MOps2);
2638 // Readjust mask for new input vector length.
2639 SmallVector<int, 8> MappedOps;
2640 for (unsigned i = 0; i != MaskNumElts; ++i) {
2642 if (Idx >= (int)SrcNumElts)
2643 Idx -= SrcNumElts - MaskNumElts;
2644 MappedOps.push_back(Idx);
2647 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2652 if (SrcNumElts > MaskNumElts) {
2653 // Analyze the access pattern of the vector to see if we can extract
2654 // two subvectors and do the shuffle. The analysis is done by calculating
2655 // the range of elements the mask access on both vectors.
2656 int MinRange[2] = { static_cast<int>(SrcNumElts),
2657 static_cast<int>(SrcNumElts)};
2658 int MaxRange[2] = {-1, -1};
2660 for (unsigned i = 0; i != MaskNumElts; ++i) {
2666 if (Idx >= (int)SrcNumElts) {
2670 if (Idx > MaxRange[Input])
2671 MaxRange[Input] = Idx;
2672 if (Idx < MinRange[Input])
2673 MinRange[Input] = Idx;
2676 // Check if the access is smaller than the vector size and can we find
2677 // a reasonable extract index.
2678 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2680 int StartIdx[2]; // StartIdx to extract from
2681 for (unsigned Input = 0; Input < 2; ++Input) {
2682 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2683 RangeUse[Input] = 0; // Unused
2684 StartIdx[Input] = 0;
2688 // Find a good start index that is a multiple of the mask length. Then
2689 // see if the rest of the elements are in range.
2690 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2691 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2692 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2693 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2696 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2697 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2700 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2701 // Extract appropriate subvector and generate a vector shuffle
2702 for (unsigned Input = 0; Input < 2; ++Input) {
2703 SDValue &Src = Input == 0 ? Src1 : Src2;
2704 if (RangeUse[Input] == 0)
2705 Src = DAG.getUNDEF(VT);
2707 SDLoc dl = getCurSDLoc();
2709 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2710 DAG.getConstant(StartIdx[Input], dl,
2711 TLI.getVectorIdxTy(DAG.getDataLayout())));
2715 // Calculate new mask.
2716 SmallVector<int, 8> MappedOps;
2717 for (unsigned i = 0; i != MaskNumElts; ++i) {
2720 if (Idx < (int)SrcNumElts)
2723 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2725 MappedOps.push_back(Idx);
2728 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2734 // We can't use either concat vectors or extract subvectors so fall back to
2735 // replacing the shuffle with extract and build vector.
2736 // to insert and build vector.
2737 EVT EltVT = VT.getVectorElementType();
2738 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2739 SDLoc dl = getCurSDLoc();
2740 SmallVector<SDValue,8> Ops;
2741 for (unsigned i = 0; i != MaskNumElts; ++i) {
2746 Res = DAG.getUNDEF(EltVT);
2748 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2749 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2751 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2752 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2758 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2761 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2762 const Value *Op0 = I.getOperand(0);
2763 const Value *Op1 = I.getOperand(1);
2764 Type *AggTy = I.getType();
2765 Type *ValTy = Op1->getType();
2766 bool IntoUndef = isa<UndefValue>(Op0);
2767 bool FromUndef = isa<UndefValue>(Op1);
2769 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2771 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2772 SmallVector<EVT, 4> AggValueVTs;
2773 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2774 SmallVector<EVT, 4> ValValueVTs;
2775 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2777 unsigned NumAggValues = AggValueVTs.size();
2778 unsigned NumValValues = ValValueVTs.size();
2779 SmallVector<SDValue, 4> Values(NumAggValues);
2781 // Ignore an insertvalue that produces an empty object
2782 if (!NumAggValues) {
2783 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2787 SDValue Agg = getValue(Op0);
2789 // Copy the beginning value(s) from the original aggregate.
2790 for (; i != LinearIndex; ++i)
2791 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2792 SDValue(Agg.getNode(), Agg.getResNo() + i);
2793 // Copy values from the inserted value(s).
2795 SDValue Val = getValue(Op1);
2796 for (; i != LinearIndex + NumValValues; ++i)
2797 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2798 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2800 // Copy remaining value(s) from the original aggregate.
2801 for (; i != NumAggValues; ++i)
2802 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2803 SDValue(Agg.getNode(), Agg.getResNo() + i);
2805 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2806 DAG.getVTList(AggValueVTs), Values));
2809 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2810 const Value *Op0 = I.getOperand(0);
2811 Type *AggTy = Op0->getType();
2812 Type *ValTy = I.getType();
2813 bool OutOfUndef = isa<UndefValue>(Op0);
2815 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2818 SmallVector<EVT, 4> ValValueVTs;
2819 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2821 unsigned NumValValues = ValValueVTs.size();
2823 // Ignore a extractvalue that produces an empty object
2824 if (!NumValValues) {
2825 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2829 SmallVector<SDValue, 4> Values(NumValValues);
2831 SDValue Agg = getValue(Op0);
2832 // Copy out the selected value(s).
2833 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2834 Values[i - LinearIndex] =
2836 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2837 SDValue(Agg.getNode(), Agg.getResNo() + i);
2839 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2840 DAG.getVTList(ValValueVTs), Values));
2843 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2844 Value *Op0 = I.getOperand(0);
2845 // Note that the pointer operand may be a vector of pointers. Take the scalar
2846 // element which holds a pointer.
2847 Type *Ty = Op0->getType()->getScalarType();
2848 unsigned AS = Ty->getPointerAddressSpace();
2849 SDValue N = getValue(Op0);
2850 SDLoc dl = getCurSDLoc();
2852 // Normalize Vector GEP - all scalar operands should be converted to the
2854 unsigned VectorWidth = I.getType()->isVectorTy() ?
2855 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2857 if (VectorWidth && !N.getValueType().isVector()) {
2858 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2859 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2860 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2862 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2864 const Value *Idx = *OI;
2865 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2866 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2869 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2870 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2871 DAG.getConstant(Offset, dl, N.getValueType()));
2874 Ty = StTy->getElementType(Field);
2876 Ty = cast<SequentialType>(Ty)->getElementType();
2878 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2879 unsigned PtrSize = PtrTy.getSizeInBits();
2880 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2882 // If this is a scalar constant or a splat vector of constants,
2883 // handle it quickly.
2884 const auto *CI = dyn_cast<ConstantInt>(Idx);
2885 if (!CI && isa<ConstantDataVector>(Idx) &&
2886 cast<ConstantDataVector>(Idx)->getSplatValue())
2887 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2892 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2893 SDValue OffsVal = VectorWidth ?
2894 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2895 DAG.getConstant(Offs, dl, PtrTy);
2896 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2900 // N = N + Idx * ElementSize;
2901 SDValue IdxN = getValue(Idx);
2903 if (!IdxN.getValueType().isVector() && VectorWidth) {
2904 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2905 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2906 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2908 // If the index is smaller or larger than intptr_t, truncate or extend
2910 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2912 // If this is a multiply by a power of two, turn it into a shl
2913 // immediately. This is a very common case.
2914 if (ElementSize != 1) {
2915 if (ElementSize.isPowerOf2()) {
2916 unsigned Amt = ElementSize.logBase2();
2917 IdxN = DAG.getNode(ISD::SHL, dl,
2918 N.getValueType(), IdxN,
2919 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2921 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2922 IdxN = DAG.getNode(ISD::MUL, dl,
2923 N.getValueType(), IdxN, Scale);
2927 N = DAG.getNode(ISD::ADD, dl,
2928 N.getValueType(), N, IdxN);
2935 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2936 // If this is a fixed sized alloca in the entry block of the function,
2937 // allocate it statically on the stack.
2938 if (FuncInfo.StaticAllocaMap.count(&I))
2939 return; // getValue will auto-populate this.
2941 SDLoc dl = getCurSDLoc();
2942 Type *Ty = I.getAllocatedType();
2943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2944 auto &DL = DAG.getDataLayout();
2945 uint64_t TySize = DL.getTypeAllocSize(Ty);
2947 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2949 SDValue AllocSize = getValue(I.getArraySize());
2951 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2952 if (AllocSize.getValueType() != IntPtr)
2953 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2955 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2957 DAG.getConstant(TySize, dl, IntPtr));
2959 // Handle alignment. If the requested alignment is less than or equal to
2960 // the stack alignment, ignore it. If the size is greater than or equal to
2961 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2962 unsigned StackAlign =
2963 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2964 if (Align <= StackAlign)
2967 // Round the size of the allocation up to the stack alignment size
2968 // by add SA-1 to the size.
2969 AllocSize = DAG.getNode(ISD::ADD, dl,
2970 AllocSize.getValueType(), AllocSize,
2971 DAG.getIntPtrConstant(StackAlign - 1, dl));
2973 // Mask out the low bits for alignment purposes.
2974 AllocSize = DAG.getNode(ISD::AND, dl,
2975 AllocSize.getValueType(), AllocSize,
2976 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2979 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2980 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2981 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2983 DAG.setRoot(DSA.getValue(1));
2985 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2988 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2990 return visitAtomicLoad(I);
2992 const Value *SV = I.getOperand(0);
2993 SDValue Ptr = getValue(SV);
2995 Type *Ty = I.getType();
2997 bool isVolatile = I.isVolatile();
2998 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3000 // The IR notion of invariant_load only guarantees that all *non-faulting*
3001 // invariant loads result in the same value. The MI notion of invariant load
3002 // guarantees that the load can be legally moved to any location within its
3003 // containing function. The MI notion of invariant_load is stronger than the
3004 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3005 // with a guarantee that the location being loaded from is dereferenceable
3006 // throughout the function's lifetime.
3008 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3009 isDereferenceablePointer(SV, DAG.getDataLayout());
3010 unsigned Alignment = I.getAlignment();
3013 I.getAAMetadata(AAInfo);
3014 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3016 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3017 SmallVector<EVT, 4> ValueVTs;
3018 SmallVector<uint64_t, 4> Offsets;
3019 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3020 unsigned NumValues = ValueVTs.size();
3025 bool ConstantMemory = false;
3026 if (isVolatile || NumValues > MaxParallelChains)
3027 // Serialize volatile loads with other side effects.
3029 else if (AA->pointsToConstantMemory(MemoryLocation(
3030 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3031 // Do not serialize (non-volatile) loads of constant memory with anything.
3032 Root = DAG.getEntryNode();
3033 ConstantMemory = true;
3035 // Do not serialize non-volatile loads against each other.
3036 Root = DAG.getRoot();
3039 SDLoc dl = getCurSDLoc();
3042 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3044 SmallVector<SDValue, 4> Values(NumValues);
3045 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3046 EVT PtrVT = Ptr.getValueType();
3047 unsigned ChainI = 0;
3048 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3049 // Serializing loads here may result in excessive register pressure, and
3050 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3051 // could recover a bit by hoisting nodes upward in the chain by recognizing
3052 // they are side-effect free or do not alias. The optimizer should really
3053 // avoid this case by converting large object/array copies to llvm.memcpy
3054 // (MaxParallelChains should always remain as failsafe).
3055 if (ChainI == MaxParallelChains) {
3056 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3057 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3058 makeArrayRef(Chains.data(), ChainI));
3062 SDValue A = DAG.getNode(ISD::ADD, dl,
3064 DAG.getConstant(Offsets[i], dl, PtrVT));
3065 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3066 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3067 isNonTemporal, isInvariant, Alignment, AAInfo,
3071 Chains[ChainI] = L.getValue(1);
3074 if (!ConstantMemory) {
3075 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3076 makeArrayRef(Chains.data(), ChainI));
3080 PendingLoads.push_back(Chain);
3083 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3084 DAG.getVTList(ValueVTs), Values));
3087 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3089 return visitAtomicStore(I);
3091 const Value *SrcV = I.getOperand(0);
3092 const Value *PtrV = I.getOperand(1);
3094 SmallVector<EVT, 4> ValueVTs;
3095 SmallVector<uint64_t, 4> Offsets;
3096 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3097 SrcV->getType(), ValueVTs, &Offsets);
3098 unsigned NumValues = ValueVTs.size();
3102 // Get the lowered operands. Note that we do this after
3103 // checking if NumResults is zero, because with zero results
3104 // the operands won't have values in the map.
3105 SDValue Src = getValue(SrcV);
3106 SDValue Ptr = getValue(PtrV);
3108 SDValue Root = getRoot();
3109 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3110 EVT PtrVT = Ptr.getValueType();
3111 bool isVolatile = I.isVolatile();
3112 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3113 unsigned Alignment = I.getAlignment();
3114 SDLoc dl = getCurSDLoc();
3117 I.getAAMetadata(AAInfo);
3119 unsigned ChainI = 0;
3120 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3121 // See visitLoad comments.
3122 if (ChainI == MaxParallelChains) {
3123 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3124 makeArrayRef(Chains.data(), ChainI));
3128 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3129 DAG.getConstant(Offsets[i], dl, PtrVT));
3130 SDValue St = DAG.getStore(Root, dl,
3131 SDValue(Src.getNode(), Src.getResNo() + i),
3132 Add, MachinePointerInfo(PtrV, Offsets[i]),
3133 isVolatile, isNonTemporal, Alignment, AAInfo);
3134 Chains[ChainI] = St;
3137 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3138 makeArrayRef(Chains.data(), ChainI));
3139 DAG.setRoot(StoreNode);
3142 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3143 SDLoc sdl = getCurSDLoc();
3145 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3146 Value *PtrOperand = I.getArgOperand(1);
3147 SDValue Ptr = getValue(PtrOperand);
3148 SDValue Src0 = getValue(I.getArgOperand(0));
3149 SDValue Mask = getValue(I.getArgOperand(3));
3150 EVT VT = Src0.getValueType();
3151 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3153 Alignment = DAG.getEVTAlignment(VT);
3156 I.getAAMetadata(AAInfo);
3158 MachineMemOperand *MMO =
3159 DAG.getMachineFunction().
3160 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3161 MachineMemOperand::MOStore, VT.getStoreSize(),
3163 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3165 DAG.setRoot(StoreNode);
3166 setValue(&I, StoreNode);
3169 // Get a uniform base for the Gather/Scatter intrinsic.
3170 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3171 // We try to represent it as a base pointer + vector of indices.
3172 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3173 // The first operand of the GEP may be a single pointer or a vector of pointers
3175 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3177 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3178 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3180 // When the first GEP operand is a single pointer - it is the uniform base we
3181 // are looking for. If first operand of the GEP is a splat vector - we
3182 // extract the spalt value and use it as a uniform base.
3183 // In all other cases the function returns 'false'.
3185 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3186 SelectionDAGBuilder* SDB) {
3188 SelectionDAG& DAG = SDB->DAG;
3189 LLVMContext &Context = *DAG.getContext();
3191 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3192 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3193 if (!GEP || GEP->getNumOperands() > 2)
3196 Value *GEPPtr = GEP->getPointerOperand();
3197 if (!GEPPtr->getType()->isVectorTy())
3199 else if (!(Ptr = getSplatValue(GEPPtr)))
3202 Value *IndexVal = GEP->getOperand(1);
3204 // The operands of the GEP may be defined in another basic block.
3205 // In this case we'll not find nodes for the operands.
3206 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3209 Base = SDB->getValue(Ptr);
3210 Index = SDB->getValue(IndexVal);
3212 // Suppress sign extension.
3213 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3214 if (SDB->findValue(Sext->getOperand(0))) {
3215 IndexVal = Sext->getOperand(0);
3216 Index = SDB->getValue(IndexVal);
3219 if (!Index.getValueType().isVector()) {
3220 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3221 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3222 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3223 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3228 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3229 SDLoc sdl = getCurSDLoc();
3231 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3232 Value *Ptr = I.getArgOperand(1);
3233 SDValue Src0 = getValue(I.getArgOperand(0));
3234 SDValue Mask = getValue(I.getArgOperand(3));
3235 EVT VT = Src0.getValueType();
3236 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3238 Alignment = DAG.getEVTAlignment(VT);
3239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3242 I.getAAMetadata(AAInfo);
3246 Value *BasePtr = Ptr;
3247 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3249 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3250 MachineMemOperand *MMO = DAG.getMachineFunction().
3251 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3252 MachineMemOperand::MOStore, VT.getStoreSize(),
3255 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3256 Index = getValue(Ptr);
3258 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3259 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3261 DAG.setRoot(Scatter);
3262 setValue(&I, Scatter);
3265 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3266 SDLoc sdl = getCurSDLoc();
3268 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3269 Value *PtrOperand = I.getArgOperand(0);
3270 SDValue Ptr = getValue(PtrOperand);
3271 SDValue Src0 = getValue(I.getArgOperand(3));
3272 SDValue Mask = getValue(I.getArgOperand(2));
3274 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3275 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3276 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3278 Alignment = DAG.getEVTAlignment(VT);
3281 I.getAAMetadata(AAInfo);
3282 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3284 SDValue InChain = DAG.getRoot();
3285 if (AA->pointsToConstantMemory(MemoryLocation(
3286 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3288 // Do not serialize (non-volatile) loads of constant memory with anything.
3289 InChain = DAG.getEntryNode();
3292 MachineMemOperand *MMO =
3293 DAG.getMachineFunction().
3294 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3295 MachineMemOperand::MOLoad, VT.getStoreSize(),
3296 Alignment, AAInfo, Ranges);
3298 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3300 SDValue OutChain = Load.getValue(1);
3301 DAG.setRoot(OutChain);
3305 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3306 SDLoc sdl = getCurSDLoc();
3308 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3309 Value *Ptr = I.getArgOperand(0);
3310 SDValue Src0 = getValue(I.getArgOperand(3));
3311 SDValue Mask = getValue(I.getArgOperand(2));
3313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3314 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3315 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3317 Alignment = DAG.getEVTAlignment(VT);
3320 I.getAAMetadata(AAInfo);
3321 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3323 SDValue Root = DAG.getRoot();
3326 Value *BasePtr = Ptr;
3327 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3328 bool ConstantMemory = false;
3330 AA->pointsToConstantMemory(MemoryLocation(
3331 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3333 // Do not serialize (non-volatile) loads of constant memory with anything.
3334 Root = DAG.getEntryNode();
3335 ConstantMemory = true;
3338 MachineMemOperand *MMO =
3339 DAG.getMachineFunction().
3340 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3341 MachineMemOperand::MOLoad, VT.getStoreSize(),
3342 Alignment, AAInfo, Ranges);
3345 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3346 Index = getValue(Ptr);
3348 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3349 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3352 SDValue OutChain = Gather.getValue(1);
3353 if (!ConstantMemory)
3354 PendingLoads.push_back(OutChain);
3355 setValue(&I, Gather);
3358 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3359 SDLoc dl = getCurSDLoc();
3360 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3361 AtomicOrdering FailureOrder = I.getFailureOrdering();
3362 SynchronizationScope Scope = I.getSynchScope();
3364 SDValue InChain = getRoot();
3366 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3367 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3368 SDValue L = DAG.getAtomicCmpSwap(
3369 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3370 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3371 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3372 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3374 SDValue OutChain = L.getValue(2);
3377 DAG.setRoot(OutChain);
3380 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3381 SDLoc dl = getCurSDLoc();
3383 switch (I.getOperation()) {
3384 default: llvm_unreachable("Unknown atomicrmw operation");
3385 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3386 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3387 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3388 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3389 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3390 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3391 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3392 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3393 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3394 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3395 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3397 AtomicOrdering Order = I.getOrdering();
3398 SynchronizationScope Scope = I.getSynchScope();
3400 SDValue InChain = getRoot();
3403 DAG.getAtomic(NT, dl,
3404 getValue(I.getValOperand()).getSimpleValueType(),
3406 getValue(I.getPointerOperand()),
3407 getValue(I.getValOperand()),
3408 I.getPointerOperand(),
3409 /* Alignment=*/ 0, Order, Scope);
3411 SDValue OutChain = L.getValue(1);
3414 DAG.setRoot(OutChain);
3417 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3418 SDLoc dl = getCurSDLoc();
3419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3422 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3423 TLI.getPointerTy(DAG.getDataLayout()));
3424 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3425 TLI.getPointerTy(DAG.getDataLayout()));
3426 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3429 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3430 SDLoc dl = getCurSDLoc();
3431 AtomicOrdering Order = I.getOrdering();
3432 SynchronizationScope Scope = I.getSynchScope();
3434 SDValue InChain = getRoot();
3436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3437 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3439 if (I.getAlignment() < VT.getSizeInBits() / 8)
3440 report_fatal_error("Cannot generate unaligned atomic load");
3442 MachineMemOperand *MMO =
3443 DAG.getMachineFunction().
3444 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3445 MachineMemOperand::MOVolatile |
3446 MachineMemOperand::MOLoad,
3448 I.getAlignment() ? I.getAlignment() :
3449 DAG.getEVTAlignment(VT));
3451 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3453 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3454 getValue(I.getPointerOperand()), MMO,
3457 SDValue OutChain = L.getValue(1);
3460 DAG.setRoot(OutChain);
3463 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3464 SDLoc dl = getCurSDLoc();
3466 AtomicOrdering Order = I.getOrdering();
3467 SynchronizationScope Scope = I.getSynchScope();
3469 SDValue InChain = getRoot();
3471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3473 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3475 if (I.getAlignment() < VT.getSizeInBits() / 8)
3476 report_fatal_error("Cannot generate unaligned atomic store");
3479 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3481 getValue(I.getPointerOperand()),
3482 getValue(I.getValueOperand()),
3483 I.getPointerOperand(), I.getAlignment(),
3486 DAG.setRoot(OutChain);
3489 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3491 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3492 unsigned Intrinsic) {
3493 bool HasChain = !I.doesNotAccessMemory();
3494 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3496 // Build the operand list.
3497 SmallVector<SDValue, 8> Ops;
3498 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3500 // We don't need to serialize loads against other loads.
3501 Ops.push_back(DAG.getRoot());
3503 Ops.push_back(getRoot());
3507 // Info is set by getTgtMemInstrinsic
3508 TargetLowering::IntrinsicInfo Info;
3509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3510 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3512 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3513 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3514 Info.opc == ISD::INTRINSIC_W_CHAIN)
3515 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3516 TLI.getPointerTy(DAG.getDataLayout())));
3518 // Add all operands of the call to the operand list.
3519 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3520 SDValue Op = getValue(I.getArgOperand(i));
3524 SmallVector<EVT, 4> ValueVTs;
3525 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3528 ValueVTs.push_back(MVT::Other);
3530 SDVTList VTs = DAG.getVTList(ValueVTs);
3534 if (IsTgtIntrinsic) {
3535 // This is target intrinsic that touches memory
3536 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3537 VTs, Ops, Info.memVT,
3538 MachinePointerInfo(Info.ptrVal, Info.offset),
3539 Info.align, Info.vol,
3540 Info.readMem, Info.writeMem, Info.size);
3541 } else if (!HasChain) {
3542 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3543 } else if (!I.getType()->isVoidTy()) {
3544 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3546 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3550 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3552 PendingLoads.push_back(Chain);
3557 if (!I.getType()->isVoidTy()) {
3558 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3559 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3560 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3563 setValue(&I, Result);
3567 /// GetSignificand - Get the significand and build it into a floating-point
3568 /// number with exponent of 1:
3570 /// Op = (Op & 0x007fffff) | 0x3f800000;
3572 /// where Op is the hexadecimal representation of floating point value.
3574 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3575 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3576 DAG.getConstant(0x007fffff, dl, MVT::i32));
3577 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3578 DAG.getConstant(0x3f800000, dl, MVT::i32));
3579 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3582 /// GetExponent - Get the exponent:
3584 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3586 /// where Op is the hexadecimal representation of floating point value.
3588 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3590 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3591 DAG.getConstant(0x7f800000, dl, MVT::i32));
3592 SDValue t1 = DAG.getNode(
3593 ISD::SRL, dl, MVT::i32, t0,
3594 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3595 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3596 DAG.getConstant(127, dl, MVT::i32));
3597 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3600 /// getF32Constant - Get 32-bit floating point constant.
3602 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3603 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3607 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3608 SelectionDAG &DAG) {
3609 // IntegerPartOfX = ((int32_t)(t0);
3610 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3612 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3613 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3614 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3616 // IntegerPartOfX <<= 23;
3617 IntegerPartOfX = DAG.getNode(
3618 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3619 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3620 DAG.getDataLayout())));
3622 SDValue TwoToFractionalPartOfX;
3623 if (LimitFloatPrecision <= 6) {
3624 // For floating-point precision of 6:
3626 // TwoToFractionalPartOfX =
3628 // (0.735607626f + 0.252464424f * x) * x;
3630 // error 0.0144103317, which is 6 bits
3631 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3632 getF32Constant(DAG, 0x3e814304, dl));
3633 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3634 getF32Constant(DAG, 0x3f3c50c8, dl));
3635 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3636 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3637 getF32Constant(DAG, 0x3f7f5e7e, dl));
3638 } else if (LimitFloatPrecision <= 12) {
3639 // For floating-point precision of 12:
3641 // TwoToFractionalPartOfX =
3644 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3646 // error 0.000107046256, which is 13 to 14 bits
3647 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3648 getF32Constant(DAG, 0x3da235e3, dl));
3649 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3650 getF32Constant(DAG, 0x3e65b8f3, dl));
3651 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3652 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3653 getF32Constant(DAG, 0x3f324b07, dl));
3654 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3655 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3656 getF32Constant(DAG, 0x3f7ff8fd, dl));
3657 } else { // LimitFloatPrecision <= 18
3658 // For floating-point precision of 18:
3660 // TwoToFractionalPartOfX =
3664 // (0.554906021e-1f +
3665 // (0.961591928e-2f +
3666 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3667 // error 2.47208000*10^(-7), which is better than 18 bits
3668 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3669 getF32Constant(DAG, 0x3924b03e, dl));
3670 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3671 getF32Constant(DAG, 0x3ab24b87, dl));
3672 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3673 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3674 getF32Constant(DAG, 0x3c1d8c17, dl));
3675 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3676 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3677 getF32Constant(DAG, 0x3d634a1d, dl));
3678 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3679 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3680 getF32Constant(DAG, 0x3e75fe14, dl));
3681 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3682 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3683 getF32Constant(DAG, 0x3f317234, dl));
3684 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3685 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3686 getF32Constant(DAG, 0x3f800000, dl));
3689 // Add the exponent into the result in integer domain.
3690 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3691 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3692 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3695 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3696 /// limited-precision mode.
3697 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3698 const TargetLowering &TLI) {
3699 if (Op.getValueType() == MVT::f32 &&
3700 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3702 // Put the exponent in the right bit position for later addition to the
3705 // #define LOG2OFe 1.4426950f
3706 // t0 = Op * LOG2OFe
3707 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3708 getF32Constant(DAG, 0x3fb8aa3b, dl));
3709 return getLimitedPrecisionExp2(t0, dl, DAG);
3712 // No special expansion.
3713 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3716 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3717 /// limited-precision mode.
3718 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3719 const TargetLowering &TLI) {
3720 if (Op.getValueType() == MVT::f32 &&
3721 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3722 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3724 // Scale the exponent by log(2) [0.69314718f].
3725 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3726 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3727 getF32Constant(DAG, 0x3f317218, dl));
3729 // Get the significand and build it into a floating-point number with
3731 SDValue X = GetSignificand(DAG, Op1, dl);
3733 SDValue LogOfMantissa;
3734 if (LimitFloatPrecision <= 6) {
3735 // For floating-point precision of 6:
3739 // (1.4034025f - 0.23903021f * x) * x;
3741 // error 0.0034276066, which is better than 8 bits
3742 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3743 getF32Constant(DAG, 0xbe74c456, dl));
3744 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3745 getF32Constant(DAG, 0x3fb3a2b1, dl));
3746 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3747 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3748 getF32Constant(DAG, 0x3f949a29, dl));
3749 } else if (LimitFloatPrecision <= 12) {
3750 // For floating-point precision of 12:
3756 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3758 // error 0.000061011436, which is 14 bits
3759 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3760 getF32Constant(DAG, 0xbd67b6d6, dl));
3761 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3762 getF32Constant(DAG, 0x3ee4f4b8, dl));
3763 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3764 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3765 getF32Constant(DAG, 0x3fbc278b, dl));
3766 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3767 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3768 getF32Constant(DAG, 0x40348e95, dl));
3769 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3770 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3771 getF32Constant(DAG, 0x3fdef31a, dl));
3772 } else { // LimitFloatPrecision <= 18
3773 // For floating-point precision of 18:
3781 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3783 // error 0.0000023660568, which is better than 18 bits
3784 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3785 getF32Constant(DAG, 0xbc91e5ac, dl));
3786 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3787 getF32Constant(DAG, 0x3e4350aa, dl));
3788 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3789 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3790 getF32Constant(DAG, 0x3f60d3e3, dl));
3791 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3792 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3793 getF32Constant(DAG, 0x4011cdf0, dl));
3794 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3795 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3796 getF32Constant(DAG, 0x406cfd1c, dl));
3797 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3798 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3799 getF32Constant(DAG, 0x408797cb, dl));
3800 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3801 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3802 getF32Constant(DAG, 0x4006dcab, dl));
3805 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3808 // No special expansion.
3809 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3812 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3813 /// limited-precision mode.
3814 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3815 const TargetLowering &TLI) {
3816 if (Op.getValueType() == MVT::f32 &&
3817 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3818 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3820 // Get the exponent.
3821 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3823 // Get the significand and build it into a floating-point number with
3825 SDValue X = GetSignificand(DAG, Op1, dl);
3827 // Different possible minimax approximations of significand in
3828 // floating-point for various degrees of accuracy over [1,2].
3829 SDValue Log2ofMantissa;
3830 if (LimitFloatPrecision <= 6) {
3831 // For floating-point precision of 6:
3833 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3835 // error 0.0049451742, which is more than 7 bits
3836 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3837 getF32Constant(DAG, 0xbeb08fe0, dl));
3838 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3839 getF32Constant(DAG, 0x40019463, dl));
3840 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3841 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3842 getF32Constant(DAG, 0x3fd6633d, dl));
3843 } else if (LimitFloatPrecision <= 12) {
3844 // For floating-point precision of 12:
3850 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3852 // error 0.0000876136000, which is better than 13 bits
3853 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3854 getF32Constant(DAG, 0xbda7262e, dl));
3855 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3856 getF32Constant(DAG, 0x3f25280b, dl));
3857 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3858 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3859 getF32Constant(DAG, 0x4007b923, dl));
3860 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3861 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3862 getF32Constant(DAG, 0x40823e2f, dl));
3863 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3864 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3865 getF32Constant(DAG, 0x4020d29c, dl));
3866 } else { // LimitFloatPrecision <= 18
3867 // For floating-point precision of 18:
3876 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3878 // error 0.0000018516, which is better than 18 bits
3879 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3880 getF32Constant(DAG, 0xbcd2769e, dl));
3881 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3882 getF32Constant(DAG, 0x3e8ce0b9, dl));
3883 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3884 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3885 getF32Constant(DAG, 0x3fa22ae7, dl));
3886 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3887 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3888 getF32Constant(DAG, 0x40525723, dl));
3889 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3890 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3891 getF32Constant(DAG, 0x40aaf200, dl));
3892 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3893 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3894 getF32Constant(DAG, 0x40c39dad, dl));
3895 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3896 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3897 getF32Constant(DAG, 0x4042902c, dl));
3900 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3903 // No special expansion.
3904 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3907 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3908 /// limited-precision mode.
3909 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3910 const TargetLowering &TLI) {
3911 if (Op.getValueType() == MVT::f32 &&
3912 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3913 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3915 // Scale the exponent by log10(2) [0.30102999f].
3916 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3917 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3918 getF32Constant(DAG, 0x3e9a209a, dl));
3920 // Get the significand and build it into a floating-point number with
3922 SDValue X = GetSignificand(DAG, Op1, dl);
3924 SDValue Log10ofMantissa;
3925 if (LimitFloatPrecision <= 6) {
3926 // For floating-point precision of 6:
3928 // Log10ofMantissa =
3930 // (0.60948995f - 0.10380950f * x) * x;
3932 // error 0.0014886165, which is 6 bits
3933 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3934 getF32Constant(DAG, 0xbdd49a13, dl));
3935 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3936 getF32Constant(DAG, 0x3f1c0789, dl));
3937 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3938 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3939 getF32Constant(DAG, 0x3f011300, dl));
3940 } else if (LimitFloatPrecision <= 12) {
3941 // For floating-point precision of 12:
3943 // Log10ofMantissa =
3946 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3948 // error 0.00019228036, which is better than 12 bits
3949 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3950 getF32Constant(DAG, 0x3d431f31, dl));
3951 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3952 getF32Constant(DAG, 0x3ea21fb2, dl));
3953 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3954 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3955 getF32Constant(DAG, 0x3f6ae232, dl));
3956 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3957 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3958 getF32Constant(DAG, 0x3f25f7c3, dl));
3959 } else { // LimitFloatPrecision <= 18
3960 // For floating-point precision of 18:
3962 // Log10ofMantissa =
3967 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3969 // error 0.0000037995730, which is better than 18 bits
3970 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3971 getF32Constant(DAG, 0x3c5d51ce, dl));
3972 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3973 getF32Constant(DAG, 0x3e00685a, dl));
3974 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3975 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3976 getF32Constant(DAG, 0x3efb6798, dl));
3977 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3978 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3979 getF32Constant(DAG, 0x3f88d192, dl));
3980 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3981 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3982 getF32Constant(DAG, 0x3fc4316c, dl));
3983 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3984 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3985 getF32Constant(DAG, 0x3f57ce70, dl));
3988 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3991 // No special expansion.
3992 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3995 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3996 /// limited-precision mode.
3997 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3998 const TargetLowering &TLI) {
3999 if (Op.getValueType() == MVT::f32 &&
4000 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4001 return getLimitedPrecisionExp2(Op, dl, DAG);
4003 // No special expansion.
4004 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4007 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4008 /// limited-precision mode with x == 10.0f.
4009 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4010 SelectionDAG &DAG, const TargetLowering &TLI) {
4011 bool IsExp10 = false;
4012 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4013 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4014 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4016 IsExp10 = LHSC->isExactlyValue(Ten);
4021 // Put the exponent in the right bit position for later addition to the
4024 // #define LOG2OF10 3.3219281f
4025 // t0 = Op * LOG2OF10;
4026 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4027 getF32Constant(DAG, 0x40549a78, dl));
4028 return getLimitedPrecisionExp2(t0, dl, DAG);
4031 // No special expansion.
4032 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4036 /// ExpandPowI - Expand a llvm.powi intrinsic.
4037 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4038 SelectionDAG &DAG) {
4039 // If RHS is a constant, we can expand this out to a multiplication tree,
4040 // otherwise we end up lowering to a call to __powidf2 (for example). When
4041 // optimizing for size, we only want to do this if the expansion would produce
4042 // a small number of multiplies, otherwise we do the full expansion.
4043 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4044 // Get the exponent as a positive value.
4045 unsigned Val = RHSC->getSExtValue();
4046 if ((int)Val < 0) Val = -Val;
4048 // powi(x, 0) -> 1.0
4050 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4052 const Function *F = DAG.getMachineFunction().getFunction();
4053 if (!F->optForSize() ||
4054 // If optimizing for size, don't insert too many multiplies.
4055 // This inserts up to 5 multiplies.
4056 countPopulation(Val) + Log2_32(Val) < 7) {
4057 // We use the simple binary decomposition method to generate the multiply
4058 // sequence. There are more optimal ways to do this (for example,
4059 // powi(x,15) generates one more multiply than it should), but this has
4060 // the benefit of being both really simple and much better than a libcall.
4061 SDValue Res; // Logically starts equal to 1.0
4062 SDValue CurSquare = LHS;
4066 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4068 Res = CurSquare; // 1.0*CurSquare.
4071 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4072 CurSquare, CurSquare);
4076 // If the original was negative, invert the result, producing 1/(x*x*x).
4077 if (RHSC->getSExtValue() < 0)
4078 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4079 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4084 // Otherwise, expand to a libcall.
4085 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4088 // getTruncatedArgReg - Find underlying register used for an truncated
4090 static unsigned getTruncatedArgReg(const SDValue &N) {
4091 if (N.getOpcode() != ISD::TRUNCATE)
4094 const SDValue &Ext = N.getOperand(0);
4095 if (Ext.getOpcode() == ISD::AssertZext ||
4096 Ext.getOpcode() == ISD::AssertSext) {
4097 const SDValue &CFR = Ext.getOperand(0);
4098 if (CFR.getOpcode() == ISD::CopyFromReg)
4099 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4100 if (CFR.getOpcode() == ISD::TRUNCATE)
4101 return getTruncatedArgReg(CFR);
4106 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4107 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4108 /// At the end of instruction selection, they will be inserted to the entry BB.
4109 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4110 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4111 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4112 const Argument *Arg = dyn_cast<Argument>(V);
4116 MachineFunction &MF = DAG.getMachineFunction();
4117 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4119 // Ignore inlined function arguments here.
4121 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4122 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4125 Optional<MachineOperand> Op;
4126 // Some arguments' frame index is recorded during argument lowering.
4127 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4128 Op = MachineOperand::CreateFI(FI);
4130 if (!Op && N.getNode()) {
4132 if (N.getOpcode() == ISD::CopyFromReg)
4133 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4135 Reg = getTruncatedArgReg(N);
4136 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4137 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4138 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4143 Op = MachineOperand::CreateReg(Reg, false);
4147 // Check if ValueMap has reg number.
4148 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4149 if (VMI != FuncInfo.ValueMap.end())
4150 Op = MachineOperand::CreateReg(VMI->second, false);
4153 if (!Op && N.getNode())
4154 // Check if frame index is available.
4155 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4156 if (FrameIndexSDNode *FINode =
4157 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4158 Op = MachineOperand::CreateFI(FINode->getIndex());
4163 assert(Variable->isValidLocationForIntrinsic(DL) &&
4164 "Expected inlined-at fields to agree");
4166 FuncInfo.ArgDbgValues.push_back(
4167 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4168 Op->getReg(), Offset, Variable, Expr));
4170 FuncInfo.ArgDbgValues.push_back(
4171 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4174 .addMetadata(Variable)
4175 .addMetadata(Expr));
4180 // VisualStudio defines setjmp as _setjmp
4181 #if defined(_MSC_VER) && defined(setjmp) && \
4182 !defined(setjmp_undefined_for_msvc)
4183 # pragma push_macro("setjmp")
4185 # define setjmp_undefined_for_msvc
4188 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4189 /// we want to emit this as a call to a named external function, return the name
4190 /// otherwise lower it and return null.
4192 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4194 SDLoc sdl = getCurSDLoc();
4195 DebugLoc dl = getCurDebugLoc();
4198 switch (Intrinsic) {
4200 // By default, turn this into a target intrinsic node.
4201 visitTargetIntrinsic(I, Intrinsic);
4203 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4204 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4205 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4206 case Intrinsic::returnaddress:
4207 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4208 TLI.getPointerTy(DAG.getDataLayout()),
4209 getValue(I.getArgOperand(0))));
4211 case Intrinsic::frameaddress:
4212 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4213 TLI.getPointerTy(DAG.getDataLayout()),
4214 getValue(I.getArgOperand(0))));
4216 case Intrinsic::read_register: {
4217 Value *Reg = I.getArgOperand(0);
4218 SDValue Chain = getRoot();
4220 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4221 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4222 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4223 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4225 DAG.setRoot(Res.getValue(1));
4228 case Intrinsic::write_register: {
4229 Value *Reg = I.getArgOperand(0);
4230 Value *RegValue = I.getArgOperand(1);
4231 SDValue Chain = getRoot();
4233 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4234 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4235 RegName, getValue(RegValue)));
4238 case Intrinsic::setjmp:
4239 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4240 case Intrinsic::longjmp:
4241 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4242 case Intrinsic::memcpy: {
4243 // FIXME: this definition of "user defined address space" is x86-specific
4244 // Assert for address < 256 since we support only user defined address
4246 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4248 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4250 "Unknown address space");
4251 SDValue Op1 = getValue(I.getArgOperand(0));
4252 SDValue Op2 = getValue(I.getArgOperand(1));
4253 SDValue Op3 = getValue(I.getArgOperand(2));
4254 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4256 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4257 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4258 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4259 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4261 MachinePointerInfo(I.getArgOperand(0)),
4262 MachinePointerInfo(I.getArgOperand(1)));
4263 updateDAGForMaybeTailCall(MC);
4266 case Intrinsic::memset: {
4267 // FIXME: this definition of "user defined address space" is x86-specific
4268 // Assert for address < 256 since we support only user defined address
4270 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4272 "Unknown address space");
4273 SDValue Op1 = getValue(I.getArgOperand(0));
4274 SDValue Op2 = getValue(I.getArgOperand(1));
4275 SDValue Op3 = getValue(I.getArgOperand(2));
4276 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4278 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4279 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4280 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4281 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4282 isTC, MachinePointerInfo(I.getArgOperand(0)));
4283 updateDAGForMaybeTailCall(MS);
4286 case Intrinsic::memmove: {
4287 // FIXME: this definition of "user defined address space" is x86-specific
4288 // Assert for address < 256 since we support only user defined address
4290 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4292 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4294 "Unknown address space");
4295 SDValue Op1 = getValue(I.getArgOperand(0));
4296 SDValue Op2 = getValue(I.getArgOperand(1));
4297 SDValue Op3 = getValue(I.getArgOperand(2));
4298 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4300 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4301 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4302 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4303 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4304 isTC, MachinePointerInfo(I.getArgOperand(0)),
4305 MachinePointerInfo(I.getArgOperand(1)));
4306 updateDAGForMaybeTailCall(MM);
4309 case Intrinsic::dbg_declare: {
4310 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4311 DILocalVariable *Variable = DI.getVariable();
4312 DIExpression *Expression = DI.getExpression();
4313 const Value *Address = DI.getAddress();
4314 assert(Variable && "Missing variable");
4316 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4320 // Check if address has undef value.
4321 if (isa<UndefValue>(Address) ||
4322 (Address->use_empty() && !isa<Argument>(Address))) {
4323 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4327 SDValue &N = NodeMap[Address];
4328 if (!N.getNode() && isa<Argument>(Address))
4329 // Check unused arguments map.
4330 N = UnusedArgNodeMap[Address];
4333 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4334 Address = BCI->getOperand(0);
4335 // Parameters are handled specially.
4336 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4338 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4340 if (isParameter && !AI) {
4341 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4343 // Byval parameter. We have a frame index at this point.
4344 SDV = DAG.getFrameIndexDbgValue(
4345 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4347 // Address is an argument, so try to emit its dbg value using
4348 // virtual register info from the FuncInfo.ValueMap.
4349 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4354 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4355 true, 0, dl, SDNodeOrder);
4357 // Can't do anything with other non-AI cases yet.
4358 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4359 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4360 DEBUG(Address->dump());
4363 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4365 // If Address is an argument then try to emit its dbg value using
4366 // virtual register info from the FuncInfo.ValueMap.
4367 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4369 // If variable is pinned by a alloca in dominating bb then
4370 // use StaticAllocaMap.
4371 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4372 if (AI->getParent() != DI.getParent()) {
4373 DenseMap<const AllocaInst*, int>::iterator SI =
4374 FuncInfo.StaticAllocaMap.find(AI);
4375 if (SI != FuncInfo.StaticAllocaMap.end()) {
4376 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4377 0, dl, SDNodeOrder);
4378 DAG.AddDbgValue(SDV, nullptr, false);
4383 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4388 case Intrinsic::dbg_value: {
4389 const DbgValueInst &DI = cast<DbgValueInst>(I);
4390 assert(DI.getVariable() && "Missing variable");
4392 DILocalVariable *Variable = DI.getVariable();
4393 DIExpression *Expression = DI.getExpression();
4394 uint64_t Offset = DI.getOffset();
4395 const Value *V = DI.getValue();
4400 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4401 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4403 DAG.AddDbgValue(SDV, nullptr, false);
4405 // Do not use getValue() in here; we don't want to generate code at
4406 // this point if it hasn't been done yet.
4407 SDValue N = NodeMap[V];
4408 if (!N.getNode() && isa<Argument>(V))
4409 // Check unused arguments map.
4410 N = UnusedArgNodeMap[V];
4412 // A dbg.value for an alloca is always indirect.
4413 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4414 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4416 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4417 IsIndirect, Offset, dl, SDNodeOrder);
4418 DAG.AddDbgValue(SDV, N.getNode(), false);
4420 } else if (!V->use_empty() ) {
4421 // Do not call getValue(V) yet, as we don't want to generate code.
4422 // Remember it for later.
4423 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4424 DanglingDebugInfoMap[V] = DDI;
4426 // We may expand this to cover more cases. One case where we have no
4427 // data available is an unreferenced parameter.
4428 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4432 // Build a debug info table entry.
4433 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4434 V = BCI->getOperand(0);
4435 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4436 // Don't handle byval struct arguments or VLAs, for example.
4438 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4439 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4442 DenseMap<const AllocaInst*, int>::iterator SI =
4443 FuncInfo.StaticAllocaMap.find(AI);
4444 if (SI == FuncInfo.StaticAllocaMap.end())
4445 return nullptr; // VLAs.
4449 case Intrinsic::eh_typeid_for: {
4450 // Find the type id for the given typeinfo.
4451 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4452 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4453 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4458 case Intrinsic::eh_return_i32:
4459 case Intrinsic::eh_return_i64:
4460 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4461 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4464 getValue(I.getArgOperand(0)),
4465 getValue(I.getArgOperand(1))));
4467 case Intrinsic::eh_unwind_init:
4468 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4470 case Intrinsic::eh_dwarf_cfa: {
4471 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4472 TLI.getPointerTy(DAG.getDataLayout()));
4473 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4474 CfaArg.getValueType(),
4475 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4476 CfaArg.getValueType()),
4478 SDValue FA = DAG.getNode(
4479 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4480 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4481 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4485 case Intrinsic::eh_sjlj_callsite: {
4486 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4487 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4488 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4489 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4491 MMI.setCurrentCallSite(CI->getZExtValue());
4494 case Intrinsic::eh_sjlj_functioncontext: {
4495 // Get and store the index of the function context.
4496 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4498 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4499 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4500 MFI->setFunctionContextIndex(FI);
4503 case Intrinsic::eh_sjlj_setjmp: {
4506 Ops[1] = getValue(I.getArgOperand(0));
4507 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4508 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4509 setValue(&I, Op.getValue(0));
4510 DAG.setRoot(Op.getValue(1));
4513 case Intrinsic::eh_sjlj_longjmp: {
4514 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4515 getRoot(), getValue(I.getArgOperand(0))));
4518 case Intrinsic::eh_sjlj_setup_dispatch: {
4519 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4524 case Intrinsic::masked_gather:
4525 visitMaskedGather(I);
4527 case Intrinsic::masked_load:
4530 case Intrinsic::masked_scatter:
4531 visitMaskedScatter(I);
4533 case Intrinsic::masked_store:
4534 visitMaskedStore(I);
4536 case Intrinsic::x86_mmx_pslli_w:
4537 case Intrinsic::x86_mmx_pslli_d:
4538 case Intrinsic::x86_mmx_pslli_q:
4539 case Intrinsic::x86_mmx_psrli_w:
4540 case Intrinsic::x86_mmx_psrli_d:
4541 case Intrinsic::x86_mmx_psrli_q:
4542 case Intrinsic::x86_mmx_psrai_w:
4543 case Intrinsic::x86_mmx_psrai_d: {
4544 SDValue ShAmt = getValue(I.getArgOperand(1));
4545 if (isa<ConstantSDNode>(ShAmt)) {
4546 visitTargetIntrinsic(I, Intrinsic);
4549 unsigned NewIntrinsic = 0;
4550 EVT ShAmtVT = MVT::v2i32;
4551 switch (Intrinsic) {
4552 case Intrinsic::x86_mmx_pslli_w:
4553 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4555 case Intrinsic::x86_mmx_pslli_d:
4556 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4558 case Intrinsic::x86_mmx_pslli_q:
4559 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4561 case Intrinsic::x86_mmx_psrli_w:
4562 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4564 case Intrinsic::x86_mmx_psrli_d:
4565 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4567 case Intrinsic::x86_mmx_psrli_q:
4568 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4570 case Intrinsic::x86_mmx_psrai_w:
4571 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4573 case Intrinsic::x86_mmx_psrai_d:
4574 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4576 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4579 // The vector shift intrinsics with scalars uses 32b shift amounts but
4580 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4582 // We must do this early because v2i32 is not a legal type.
4585 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4586 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4587 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4588 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4589 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4590 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4591 getValue(I.getArgOperand(0)), ShAmt);
4595 case Intrinsic::convertff:
4596 case Intrinsic::convertfsi:
4597 case Intrinsic::convertfui:
4598 case Intrinsic::convertsif:
4599 case Intrinsic::convertuif:
4600 case Intrinsic::convertss:
4601 case Intrinsic::convertsu:
4602 case Intrinsic::convertus:
4603 case Intrinsic::convertuu: {
4604 ISD::CvtCode Code = ISD::CVT_INVALID;
4605 switch (Intrinsic) {
4606 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4607 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4608 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4609 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4610 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4611 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4612 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4613 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4614 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4615 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4617 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4618 const Value *Op1 = I.getArgOperand(0);
4619 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4620 DAG.getValueType(DestVT),
4621 DAG.getValueType(getValue(Op1).getValueType()),
4622 getValue(I.getArgOperand(1)),
4623 getValue(I.getArgOperand(2)),
4628 case Intrinsic::powi:
4629 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4630 getValue(I.getArgOperand(1)), DAG));
4632 case Intrinsic::log:
4633 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4635 case Intrinsic::log2:
4636 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4638 case Intrinsic::log10:
4639 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4641 case Intrinsic::exp:
4642 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4644 case Intrinsic::exp2:
4645 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4647 case Intrinsic::pow:
4648 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4649 getValue(I.getArgOperand(1)), DAG, TLI));
4651 case Intrinsic::sqrt:
4652 case Intrinsic::fabs:
4653 case Intrinsic::sin:
4654 case Intrinsic::cos:
4655 case Intrinsic::floor:
4656 case Intrinsic::ceil:
4657 case Intrinsic::trunc:
4658 case Intrinsic::rint:
4659 case Intrinsic::nearbyint:
4660 case Intrinsic::round: {
4662 switch (Intrinsic) {
4663 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4664 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4665 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4666 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4667 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4668 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4669 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4670 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4671 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4672 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4673 case Intrinsic::round: Opcode = ISD::FROUND; break;
4676 setValue(&I, DAG.getNode(Opcode, sdl,
4677 getValue(I.getArgOperand(0)).getValueType(),
4678 getValue(I.getArgOperand(0))));
4681 case Intrinsic::minnum:
4682 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4683 getValue(I.getArgOperand(0)).getValueType(),
4684 getValue(I.getArgOperand(0)),
4685 getValue(I.getArgOperand(1))));
4687 case Intrinsic::maxnum:
4688 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4689 getValue(I.getArgOperand(0)).getValueType(),
4690 getValue(I.getArgOperand(0)),
4691 getValue(I.getArgOperand(1))));
4693 case Intrinsic::copysign:
4694 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4695 getValue(I.getArgOperand(0)).getValueType(),
4696 getValue(I.getArgOperand(0)),
4697 getValue(I.getArgOperand(1))));
4699 case Intrinsic::fma:
4700 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4701 getValue(I.getArgOperand(0)).getValueType(),
4702 getValue(I.getArgOperand(0)),
4703 getValue(I.getArgOperand(1)),
4704 getValue(I.getArgOperand(2))));
4706 case Intrinsic::fmuladd: {
4707 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4708 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4709 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4710 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4711 getValue(I.getArgOperand(0)).getValueType(),
4712 getValue(I.getArgOperand(0)),
4713 getValue(I.getArgOperand(1)),
4714 getValue(I.getArgOperand(2))));
4716 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4717 getValue(I.getArgOperand(0)).getValueType(),
4718 getValue(I.getArgOperand(0)),
4719 getValue(I.getArgOperand(1)));
4720 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4721 getValue(I.getArgOperand(0)).getValueType(),
4723 getValue(I.getArgOperand(2)));
4728 case Intrinsic::convert_to_fp16:
4729 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4730 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4731 getValue(I.getArgOperand(0)),
4732 DAG.getTargetConstant(0, sdl,
4735 case Intrinsic::convert_from_fp16:
4736 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4737 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4738 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4739 getValue(I.getArgOperand(0)))));
4741 case Intrinsic::pcmarker: {
4742 SDValue Tmp = getValue(I.getArgOperand(0));
4743 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4746 case Intrinsic::readcyclecounter: {
4747 SDValue Op = getRoot();
4748 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4749 DAG.getVTList(MVT::i64, MVT::Other), Op);
4751 DAG.setRoot(Res.getValue(1));
4754 case Intrinsic::bswap:
4755 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4756 getValue(I.getArgOperand(0)).getValueType(),
4757 getValue(I.getArgOperand(0))));
4759 case Intrinsic::uabsdiff:
4760 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4761 getValue(I.getArgOperand(0)).getValueType(),
4762 getValue(I.getArgOperand(0)),
4763 getValue(I.getArgOperand(1))));
4765 case Intrinsic::sabsdiff:
4766 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4767 getValue(I.getArgOperand(0)).getValueType(),
4768 getValue(I.getArgOperand(0)),
4769 getValue(I.getArgOperand(1))));
4771 case Intrinsic::cttz: {
4772 SDValue Arg = getValue(I.getArgOperand(0));
4773 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4774 EVT Ty = Arg.getValueType();
4775 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4779 case Intrinsic::ctlz: {
4780 SDValue Arg = getValue(I.getArgOperand(0));
4781 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4782 EVT Ty = Arg.getValueType();
4783 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4787 case Intrinsic::ctpop: {
4788 SDValue Arg = getValue(I.getArgOperand(0));
4789 EVT Ty = Arg.getValueType();
4790 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4793 case Intrinsic::stacksave: {
4794 SDValue Op = getRoot();
4796 ISD::STACKSAVE, sdl,
4797 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4799 DAG.setRoot(Res.getValue(1));
4802 case Intrinsic::stackrestore: {
4803 Res = getValue(I.getArgOperand(0));
4804 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4807 case Intrinsic::stackprotector: {
4808 // Emit code into the DAG to store the stack guard onto the stack.
4809 MachineFunction &MF = DAG.getMachineFunction();
4810 MachineFrameInfo *MFI = MF.getFrameInfo();
4811 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4812 SDValue Src, Chain = getRoot();
4813 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4814 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4816 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4817 // global variable __stack_chk_guard.
4819 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4820 if (BC->getOpcode() == Instruction::BitCast)
4821 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4823 if (GV && TLI.useLoadStackGuardNode()) {
4824 // Emit a LOAD_STACK_GUARD node.
4825 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4827 MachinePointerInfo MPInfo(GV);
4828 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4829 unsigned Flags = MachineMemOperand::MOLoad |
4830 MachineMemOperand::MOInvariant;
4831 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4832 PtrTy.getSizeInBits() / 8,
4833 DAG.getEVTAlignment(PtrTy));
4834 Node->setMemRefs(MemRefs, MemRefs + 1);
4836 // Copy the guard value to a virtual register so that it can be
4837 // retrieved in the epilogue.
4838 Src = SDValue(Node, 0);
4839 const TargetRegisterClass *RC =
4840 TLI.getRegClassFor(Src.getSimpleValueType());
4841 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4843 SPDescriptor.setGuardReg(Reg);
4844 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4846 Src = getValue(I.getArgOperand(0)); // The guard's value.
4849 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4851 int FI = FuncInfo.StaticAllocaMap[Slot];
4852 MFI->setStackProtectorIndex(FI);
4854 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4856 // Store the stack protector onto the stack.
4857 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4858 DAG.getMachineFunction(), FI),
4864 case Intrinsic::objectsize: {
4865 // If we don't know by now, we're never going to know.
4866 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4868 assert(CI && "Non-constant type in __builtin_object_size?");
4870 SDValue Arg = getValue(I.getCalledValue());
4871 EVT Ty = Arg.getValueType();
4874 Res = DAG.getConstant(-1ULL, sdl, Ty);
4876 Res = DAG.getConstant(0, sdl, Ty);
4881 case Intrinsic::annotation:
4882 case Intrinsic::ptr_annotation:
4883 // Drop the intrinsic, but forward the value
4884 setValue(&I, getValue(I.getOperand(0)));
4886 case Intrinsic::assume:
4887 case Intrinsic::var_annotation:
4888 // Discard annotate attributes and assumptions
4891 case Intrinsic::init_trampoline: {
4892 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4896 Ops[1] = getValue(I.getArgOperand(0));
4897 Ops[2] = getValue(I.getArgOperand(1));
4898 Ops[3] = getValue(I.getArgOperand(2));
4899 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4900 Ops[5] = DAG.getSrcValue(F);
4902 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4907 case Intrinsic::adjust_trampoline: {
4908 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4909 TLI.getPointerTy(DAG.getDataLayout()),
4910 getValue(I.getArgOperand(0))));
4913 case Intrinsic::gcroot:
4915 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4916 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4918 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4919 GFI->addStackRoot(FI->getIndex(), TypeMap);
4922 case Intrinsic::gcread:
4923 case Intrinsic::gcwrite:
4924 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4925 case Intrinsic::flt_rounds:
4926 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4929 case Intrinsic::expect: {
4930 // Just replace __builtin_expect(exp, c) with EXP.
4931 setValue(&I, getValue(I.getArgOperand(0)));
4935 case Intrinsic::debugtrap:
4936 case Intrinsic::trap: {
4937 StringRef TrapFuncName =
4939 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4940 .getValueAsString();
4941 if (TrapFuncName.empty()) {
4942 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4943 ISD::TRAP : ISD::DEBUGTRAP;
4944 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4947 TargetLowering::ArgListTy Args;
4949 TargetLowering::CallLoweringInfo CLI(DAG);
4950 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4951 CallingConv::C, I.getType(),
4952 DAG.getExternalSymbol(TrapFuncName.data(),
4953 TLI.getPointerTy(DAG.getDataLayout())),
4954 std::move(Args), 0);
4956 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4957 DAG.setRoot(Result.second);
4961 case Intrinsic::uadd_with_overflow:
4962 case Intrinsic::sadd_with_overflow:
4963 case Intrinsic::usub_with_overflow:
4964 case Intrinsic::ssub_with_overflow:
4965 case Intrinsic::umul_with_overflow:
4966 case Intrinsic::smul_with_overflow: {
4968 switch (Intrinsic) {
4969 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4970 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4971 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4972 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4973 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4974 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4975 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4977 SDValue Op1 = getValue(I.getArgOperand(0));
4978 SDValue Op2 = getValue(I.getArgOperand(1));
4980 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4981 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4984 case Intrinsic::prefetch: {
4986 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4988 Ops[1] = getValue(I.getArgOperand(0));
4989 Ops[2] = getValue(I.getArgOperand(1));
4990 Ops[3] = getValue(I.getArgOperand(2));
4991 Ops[4] = getValue(I.getArgOperand(3));
4992 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4993 DAG.getVTList(MVT::Other), Ops,
4994 EVT::getIntegerVT(*Context, 8),
4995 MachinePointerInfo(I.getArgOperand(0)),
4997 false, /* volatile */
4999 rw==1)); /* write */
5002 case Intrinsic::lifetime_start:
5003 case Intrinsic::lifetime_end: {
5004 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5005 // Stack coloring is not enabled in O0, discard region information.
5006 if (TM.getOptLevel() == CodeGenOpt::None)
5009 SmallVector<Value *, 4> Allocas;
5010 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5012 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5013 E = Allocas.end(); Object != E; ++Object) {
5014 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5016 // Could not find an Alloca.
5017 if (!LifetimeObject)
5020 // First check that the Alloca is static, otherwise it won't have a
5021 // valid frame index.
5022 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5023 if (SI == FuncInfo.StaticAllocaMap.end())
5026 int FI = SI->second;
5031 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5032 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5034 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5039 case Intrinsic::invariant_start:
5040 // Discard region information.
5041 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5043 case Intrinsic::invariant_end:
5044 // Discard region information.
5046 case Intrinsic::stackprotectorcheck: {
5047 // Do not actually emit anything for this basic block. Instead we initialize
5048 // the stack protector descriptor and export the guard variable so we can
5049 // access it in FinishBasicBlock.
5050 const BasicBlock *BB = I.getParent();
5051 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5052 ExportFromCurrentBlock(SPDescriptor.getGuard());
5054 // Flush our exports since we are going to process a terminator.
5055 (void)getControlRoot();
5058 case Intrinsic::clear_cache:
5059 return TLI.getClearCacheBuiltinName();
5060 case Intrinsic::eh_actions:
5061 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5063 case Intrinsic::donothing:
5066 case Intrinsic::experimental_stackmap: {
5070 case Intrinsic::experimental_patchpoint_void:
5071 case Intrinsic::experimental_patchpoint_i64: {
5072 visitPatchpoint(&I);
5075 case Intrinsic::experimental_gc_statepoint: {
5079 case Intrinsic::experimental_gc_result_int:
5080 case Intrinsic::experimental_gc_result_float:
5081 case Intrinsic::experimental_gc_result_ptr:
5082 case Intrinsic::experimental_gc_result: {
5086 case Intrinsic::experimental_gc_relocate: {
5090 case Intrinsic::instrprof_increment:
5091 llvm_unreachable("instrprof failed to lower an increment");
5093 case Intrinsic::localescape: {
5094 MachineFunction &MF = DAG.getMachineFunction();
5095 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5097 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5098 // is the same on all targets.
5099 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5100 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5101 if (isa<ConstantPointerNull>(Arg))
5102 continue; // Skip null pointers. They represent a hole in index space.
5103 AllocaInst *Slot = cast<AllocaInst>(Arg);
5104 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5105 "can only escape static allocas");
5106 int FI = FuncInfo.StaticAllocaMap[Slot];
5107 MCSymbol *FrameAllocSym =
5108 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5109 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5110 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5111 TII->get(TargetOpcode::LOCAL_ESCAPE))
5112 .addSym(FrameAllocSym)
5119 case Intrinsic::localrecover: {
5120 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5121 MachineFunction &MF = DAG.getMachineFunction();
5122 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5124 // Get the symbol that defines the frame offset.
5125 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5126 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5127 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5128 MCSymbol *FrameAllocSym =
5129 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5130 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5132 // Create a MCSymbol for the label to avoid any target lowering
5133 // that would make this PC relative.
5134 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5136 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5138 // Add the offset to the FP.
5139 Value *FP = I.getArgOperand(1);
5140 SDValue FPVal = getValue(FP);
5141 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5146 case Intrinsic::eh_begincatch:
5147 case Intrinsic::eh_endcatch:
5148 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5149 case Intrinsic::eh_exceptioncode: {
5150 unsigned Reg = TLI.getExceptionPointerRegister();
5151 assert(Reg && "cannot get exception code on this platform");
5152 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5153 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5154 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5155 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5157 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5158 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5165 std::pair<SDValue, SDValue>
5166 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5167 const BasicBlock *EHPadBB) {
5168 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5169 MCSymbol *BeginLabel = nullptr;
5172 // Insert a label before the invoke call to mark the try range. This can be
5173 // used to detect deletion of the invoke via the MachineModuleInfo.
5174 BeginLabel = MMI.getContext().createTempSymbol();
5176 // For SjLj, keep track of which landing pads go with which invokes
5177 // so as to maintain the ordering of pads in the LSDA.
5178 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5179 if (CallSiteIndex) {
5180 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5181 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5183 // Now that the call site is handled, stop tracking it.
5184 MMI.setCurrentCallSite(0);
5187 // Both PendingLoads and PendingExports must be flushed here;
5188 // this call might not return.
5190 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5192 CLI.setChain(getRoot());
5194 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5195 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5197 assert((CLI.IsTailCall || Result.second.getNode()) &&
5198 "Non-null chain expected with non-tail call!");
5199 assert((Result.second.getNode() || !Result.first.getNode()) &&
5200 "Null value expected with tail call!");
5202 if (!Result.second.getNode()) {
5203 // As a special case, a null chain means that a tail call has been emitted
5204 // and the DAG root is already updated.
5207 // Since there's no actual continuation from this block, nothing can be
5208 // relying on us setting vregs for them.
5209 PendingExports.clear();
5211 DAG.setRoot(Result.second);
5215 // Insert a label at the end of the invoke call to mark the try range. This
5216 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5217 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5218 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5220 // Inform MachineModuleInfo of range.
5221 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5227 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5229 const BasicBlock *EHPadBB) {
5230 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5231 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5232 Type *RetTy = FTy->getReturnType();
5234 TargetLowering::ArgListTy Args;
5235 TargetLowering::ArgListEntry Entry;
5236 Args.reserve(CS.arg_size());
5238 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5240 const Value *V = *i;
5243 if (V->getType()->isEmptyTy())
5246 SDValue ArgNode = getValue(V);
5247 Entry.Node = ArgNode; Entry.Ty = V->getType();
5249 // Skip the first return-type Attribute to get to params.
5250 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5251 Args.push_back(Entry);
5253 // If we have an explicit sret argument that is an Instruction, (i.e., it
5254 // might point to function-local memory), we can't meaningfully tail-call.
5255 if (Entry.isSRet && isa<Instruction>(V))
5259 // Check if target-independent constraints permit a tail call here.
5260 // Target-dependent constraints are checked within TLI->LowerCallTo.
5261 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5264 TargetLowering::CallLoweringInfo CLI(DAG);
5265 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5266 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5267 .setTailCall(isTailCall);
5268 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5270 if (Result.first.getNode())
5271 setValue(CS.getInstruction(), Result.first);
5274 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5275 /// value is equal or not-equal to zero.
5276 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5277 for (const User *U : V->users()) {
5278 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5279 if (IC->isEquality())
5280 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5281 if (C->isNullValue())
5283 // Unknown instruction.
5289 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5291 SelectionDAGBuilder &Builder) {
5293 // Check to see if this load can be trivially constant folded, e.g. if the
5294 // input is from a string literal.
5295 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5296 // Cast pointer to the type we really want to load.
5297 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5298 PointerType::getUnqual(LoadTy));
5300 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5301 const_cast<Constant *>(LoadInput), *Builder.DL))
5302 return Builder.getValue(LoadCst);
5305 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5306 // still constant memory, the input chain can be the entry node.
5308 bool ConstantMemory = false;
5310 // Do not serialize (non-volatile) loads of constant memory with anything.
5311 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5312 Root = Builder.DAG.getEntryNode();
5313 ConstantMemory = true;
5315 // Do not serialize non-volatile loads against each other.
5316 Root = Builder.DAG.getRoot();
5319 SDValue Ptr = Builder.getValue(PtrVal);
5320 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5321 Ptr, MachinePointerInfo(PtrVal),
5323 false /*nontemporal*/,
5324 false /*isinvariant*/, 1 /* align=1 */);
5326 if (!ConstantMemory)
5327 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5331 /// processIntegerCallValue - Record the value for an instruction that
5332 /// produces an integer result, converting the type where necessary.
5333 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5336 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5339 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5341 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5342 setValue(&I, Value);
5345 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5346 /// If so, return true and lower it, otherwise return false and it will be
5347 /// lowered like a normal call.
5348 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5349 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5350 if (I.getNumArgOperands() != 3)
5353 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5354 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5355 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5356 !I.getType()->isIntegerTy())
5359 const Value *Size = I.getArgOperand(2);
5360 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5361 if (CSize && CSize->getZExtValue() == 0) {
5362 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5364 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5368 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5369 std::pair<SDValue, SDValue> Res =
5370 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5371 getValue(LHS), getValue(RHS), getValue(Size),
5372 MachinePointerInfo(LHS),
5373 MachinePointerInfo(RHS));
5374 if (Res.first.getNode()) {
5375 processIntegerCallValue(I, Res.first, true);
5376 PendingLoads.push_back(Res.second);
5380 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5381 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5382 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5383 bool ActuallyDoIt = true;
5386 switch (CSize->getZExtValue()) {
5388 LoadVT = MVT::Other;
5390 ActuallyDoIt = false;
5394 LoadTy = Type::getInt16Ty(CSize->getContext());
5398 LoadTy = Type::getInt32Ty(CSize->getContext());
5402 LoadTy = Type::getInt64Ty(CSize->getContext());
5406 LoadVT = MVT::v4i32;
5407 LoadTy = Type::getInt32Ty(CSize->getContext());
5408 LoadTy = VectorType::get(LoadTy, 4);
5413 // This turns into unaligned loads. We only do this if the target natively
5414 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5415 // we'll only produce a small number of byte loads.
5417 // Require that we can find a legal MVT, and only do this if the target
5418 // supports unaligned loads of that type. Expanding into byte loads would
5420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5421 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5422 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5423 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5424 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5425 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5426 // TODO: Check alignment of src and dest ptrs.
5427 if (!TLI.isTypeLegal(LoadVT) ||
5428 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5429 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5430 ActuallyDoIt = false;
5434 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5435 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5437 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5439 processIntegerCallValue(I, Res, false);
5448 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5449 /// form. If so, return true and lower it, otherwise return false and it
5450 /// will be lowered like a normal call.
5451 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5452 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5453 if (I.getNumArgOperands() != 3)
5456 const Value *Src = I.getArgOperand(0);
5457 const Value *Char = I.getArgOperand(1);
5458 const Value *Length = I.getArgOperand(2);
5459 if (!Src->getType()->isPointerTy() ||
5460 !Char->getType()->isIntegerTy() ||
5461 !Length->getType()->isIntegerTy() ||
5462 !I.getType()->isPointerTy())
5465 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5466 std::pair<SDValue, SDValue> Res =
5467 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5468 getValue(Src), getValue(Char), getValue(Length),
5469 MachinePointerInfo(Src));
5470 if (Res.first.getNode()) {
5471 setValue(&I, Res.first);
5472 PendingLoads.push_back(Res.second);
5479 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5480 /// optimized form. If so, return true and lower it, otherwise return false
5481 /// and it will be lowered like a normal call.
5482 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5483 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5484 if (I.getNumArgOperands() != 2)
5487 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5488 if (!Arg0->getType()->isPointerTy() ||
5489 !Arg1->getType()->isPointerTy() ||
5490 !I.getType()->isPointerTy())
5493 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5494 std::pair<SDValue, SDValue> Res =
5495 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5496 getValue(Arg0), getValue(Arg1),
5497 MachinePointerInfo(Arg0),
5498 MachinePointerInfo(Arg1), isStpcpy);
5499 if (Res.first.getNode()) {
5500 setValue(&I, Res.first);
5501 DAG.setRoot(Res.second);
5508 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5509 /// If so, return true and lower it, otherwise return false and it will be
5510 /// lowered like a normal call.
5511 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5512 // Verify that the prototype makes sense. int strcmp(void*,void*)
5513 if (I.getNumArgOperands() != 2)
5516 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5517 if (!Arg0->getType()->isPointerTy() ||
5518 !Arg1->getType()->isPointerTy() ||
5519 !I.getType()->isIntegerTy())
5522 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5523 std::pair<SDValue, SDValue> Res =
5524 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5525 getValue(Arg0), getValue(Arg1),
5526 MachinePointerInfo(Arg0),
5527 MachinePointerInfo(Arg1));
5528 if (Res.first.getNode()) {
5529 processIntegerCallValue(I, Res.first, true);
5530 PendingLoads.push_back(Res.second);
5537 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5538 /// form. If so, return true and lower it, otherwise return false and it
5539 /// will be lowered like a normal call.
5540 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5541 // Verify that the prototype makes sense. size_t strlen(char *)
5542 if (I.getNumArgOperands() != 1)
5545 const Value *Arg0 = I.getArgOperand(0);
5546 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5549 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5550 std::pair<SDValue, SDValue> Res =
5551 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5552 getValue(Arg0), MachinePointerInfo(Arg0));
5553 if (Res.first.getNode()) {
5554 processIntegerCallValue(I, Res.first, false);
5555 PendingLoads.push_back(Res.second);
5562 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5563 /// form. If so, return true and lower it, otherwise return false and it
5564 /// will be lowered like a normal call.
5565 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5566 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5567 if (I.getNumArgOperands() != 2)
5570 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5571 if (!Arg0->getType()->isPointerTy() ||
5572 !Arg1->getType()->isIntegerTy() ||
5573 !I.getType()->isIntegerTy())
5576 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5577 std::pair<SDValue, SDValue> Res =
5578 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5579 getValue(Arg0), getValue(Arg1),
5580 MachinePointerInfo(Arg0));
5581 if (Res.first.getNode()) {
5582 processIntegerCallValue(I, Res.first, false);
5583 PendingLoads.push_back(Res.second);
5590 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5591 /// operation (as expected), translate it to an SDNode with the specified opcode
5592 /// and return true.
5593 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5595 // Sanity check that it really is a unary floating-point call.
5596 if (I.getNumArgOperands() != 1 ||
5597 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5598 I.getType() != I.getArgOperand(0)->getType() ||
5599 !I.onlyReadsMemory())
5602 SDValue Tmp = getValue(I.getArgOperand(0));
5603 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5607 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5608 /// operation (as expected), translate it to an SDNode with the specified opcode
5609 /// and return true.
5610 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5612 // Sanity check that it really is a binary floating-point call.
5613 if (I.getNumArgOperands() != 2 ||
5614 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5615 I.getType() != I.getArgOperand(0)->getType() ||
5616 I.getType() != I.getArgOperand(1)->getType() ||
5617 !I.onlyReadsMemory())
5620 SDValue Tmp0 = getValue(I.getArgOperand(0));
5621 SDValue Tmp1 = getValue(I.getArgOperand(1));
5622 EVT VT = Tmp0.getValueType();
5623 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5627 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5628 // Handle inline assembly differently.
5629 if (isa<InlineAsm>(I.getCalledValue())) {
5634 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5635 ComputeUsesVAFloatArgument(I, &MMI);
5637 const char *RenameFn = nullptr;
5638 if (Function *F = I.getCalledFunction()) {
5639 if (F->isDeclaration()) {
5640 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5641 if (unsigned IID = II->getIntrinsicID(F)) {
5642 RenameFn = visitIntrinsicCall(I, IID);
5647 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5648 RenameFn = visitIntrinsicCall(I, IID);
5654 // Check for well-known libc/libm calls. If the function is internal, it
5655 // can't be a library call.
5657 if (!F->hasLocalLinkage() && F->hasName() &&
5658 LibInfo->getLibFunc(F->getName(), Func) &&
5659 LibInfo->hasOptimizedCodeGen(Func)) {
5662 case LibFunc::copysign:
5663 case LibFunc::copysignf:
5664 case LibFunc::copysignl:
5665 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5666 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5667 I.getType() == I.getArgOperand(0)->getType() &&
5668 I.getType() == I.getArgOperand(1)->getType() &&
5669 I.onlyReadsMemory()) {
5670 SDValue LHS = getValue(I.getArgOperand(0));
5671 SDValue RHS = getValue(I.getArgOperand(1));
5672 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5673 LHS.getValueType(), LHS, RHS));
5678 case LibFunc::fabsf:
5679 case LibFunc::fabsl:
5680 if (visitUnaryFloatCall(I, ISD::FABS))
5684 case LibFunc::fminf:
5685 case LibFunc::fminl:
5686 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5690 case LibFunc::fmaxf:
5691 case LibFunc::fmaxl:
5692 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5698 if (visitUnaryFloatCall(I, ISD::FSIN))
5704 if (visitUnaryFloatCall(I, ISD::FCOS))
5708 case LibFunc::sqrtf:
5709 case LibFunc::sqrtl:
5710 case LibFunc::sqrt_finite:
5711 case LibFunc::sqrtf_finite:
5712 case LibFunc::sqrtl_finite:
5713 if (visitUnaryFloatCall(I, ISD::FSQRT))
5716 case LibFunc::floor:
5717 case LibFunc::floorf:
5718 case LibFunc::floorl:
5719 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5722 case LibFunc::nearbyint:
5723 case LibFunc::nearbyintf:
5724 case LibFunc::nearbyintl:
5725 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5729 case LibFunc::ceilf:
5730 case LibFunc::ceill:
5731 if (visitUnaryFloatCall(I, ISD::FCEIL))
5735 case LibFunc::rintf:
5736 case LibFunc::rintl:
5737 if (visitUnaryFloatCall(I, ISD::FRINT))
5740 case LibFunc::round:
5741 case LibFunc::roundf:
5742 case LibFunc::roundl:
5743 if (visitUnaryFloatCall(I, ISD::FROUND))
5746 case LibFunc::trunc:
5747 case LibFunc::truncf:
5748 case LibFunc::truncl:
5749 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5753 case LibFunc::log2f:
5754 case LibFunc::log2l:
5755 if (visitUnaryFloatCall(I, ISD::FLOG2))
5759 case LibFunc::exp2f:
5760 case LibFunc::exp2l:
5761 if (visitUnaryFloatCall(I, ISD::FEXP2))
5764 case LibFunc::memcmp:
5765 if (visitMemCmpCall(I))
5768 case LibFunc::memchr:
5769 if (visitMemChrCall(I))
5772 case LibFunc::strcpy:
5773 if (visitStrCpyCall(I, false))
5776 case LibFunc::stpcpy:
5777 if (visitStrCpyCall(I, true))
5780 case LibFunc::strcmp:
5781 if (visitStrCmpCall(I))
5784 case LibFunc::strlen:
5785 if (visitStrLenCall(I))
5788 case LibFunc::strnlen:
5789 if (visitStrNLenCall(I))
5798 Callee = getValue(I.getCalledValue());
5800 Callee = DAG.getExternalSymbol(
5802 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5804 // Check if we can potentially perform a tail call. More detailed checking is
5805 // be done within LowerCallTo, after more information about the call is known.
5806 LowerCallTo(&I, Callee, I.isTailCall());
5811 /// AsmOperandInfo - This contains information for each constraint that we are
5813 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5815 /// CallOperand - If this is the result output operand or a clobber
5816 /// this is null, otherwise it is the incoming operand to the CallInst.
5817 /// This gets modified as the asm is processed.
5818 SDValue CallOperand;
5820 /// AssignedRegs - If this is a register or register class operand, this
5821 /// contains the set of register corresponding to the operand.
5822 RegsForValue AssignedRegs;
5824 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5825 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5828 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5829 /// corresponds to. If there is no Value* for this operand, it returns
5831 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5832 const DataLayout &DL) const {
5833 if (!CallOperandVal) return MVT::Other;
5835 if (isa<BasicBlock>(CallOperandVal))
5836 return TLI.getPointerTy(DL);
5838 llvm::Type *OpTy = CallOperandVal->getType();
5840 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5841 // If this is an indirect operand, the operand is a pointer to the
5844 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5846 report_fatal_error("Indirect operand for inline asm not a pointer!");
5847 OpTy = PtrTy->getElementType();
5850 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5851 if (StructType *STy = dyn_cast<StructType>(OpTy))
5852 if (STy->getNumElements() == 1)
5853 OpTy = STy->getElementType(0);
5855 // If OpTy is not a single value, it may be a struct/union that we
5856 // can tile with integers.
5857 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5858 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5867 OpTy = IntegerType::get(Context, BitSize);
5872 return TLI.getValueType(DL, OpTy, true);
5876 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5878 } // end anonymous namespace
5880 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5881 /// specified operand. We prefer to assign virtual registers, to allow the
5882 /// register allocator to handle the assignment process. However, if the asm
5883 /// uses features that we can't model on machineinstrs, we have SDISel do the
5884 /// allocation. This produces generally horrible, but correct, code.
5886 /// OpInfo describes the operand.
5888 static void GetRegistersForValue(SelectionDAG &DAG,
5889 const TargetLowering &TLI,
5891 SDISelAsmOperandInfo &OpInfo) {
5892 LLVMContext &Context = *DAG.getContext();
5894 MachineFunction &MF = DAG.getMachineFunction();
5895 SmallVector<unsigned, 4> Regs;
5897 // If this is a constraint for a single physreg, or a constraint for a
5898 // register class, find it.
5899 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5900 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5901 OpInfo.ConstraintCode,
5902 OpInfo.ConstraintVT);
5904 unsigned NumRegs = 1;
5905 if (OpInfo.ConstraintVT != MVT::Other) {
5906 // If this is a FP input in an integer register (or visa versa) insert a bit
5907 // cast of the input value. More generally, handle any case where the input
5908 // value disagrees with the register class we plan to stick this in.
5909 if (OpInfo.Type == InlineAsm::isInput &&
5910 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5911 // Try to convert to the first EVT that the reg class contains. If the
5912 // types are identical size, use a bitcast to convert (e.g. two differing
5914 MVT RegVT = *PhysReg.second->vt_begin();
5915 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5916 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5917 RegVT, OpInfo.CallOperand);
5918 OpInfo.ConstraintVT = RegVT;
5919 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5920 // If the input is a FP value and we want it in FP registers, do a
5921 // bitcast to the corresponding integer type. This turns an f64 value
5922 // into i64, which can be passed with two i32 values on a 32-bit
5924 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5925 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5926 RegVT, OpInfo.CallOperand);
5927 OpInfo.ConstraintVT = RegVT;
5931 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5935 EVT ValueVT = OpInfo.ConstraintVT;
5937 // If this is a constraint for a specific physical register, like {r17},
5939 if (unsigned AssignedReg = PhysReg.first) {
5940 const TargetRegisterClass *RC = PhysReg.second;
5941 if (OpInfo.ConstraintVT == MVT::Other)
5942 ValueVT = *RC->vt_begin();
5944 // Get the actual register value type. This is important, because the user
5945 // may have asked for (e.g.) the AX register in i32 type. We need to
5946 // remember that AX is actually i16 to get the right extension.
5947 RegVT = *RC->vt_begin();
5949 // This is a explicit reference to a physical register.
5950 Regs.push_back(AssignedReg);
5952 // If this is an expanded reference, add the rest of the regs to Regs.
5954 TargetRegisterClass::iterator I = RC->begin();
5955 for (; *I != AssignedReg; ++I)
5956 assert(I != RC->end() && "Didn't find reg!");
5958 // Already added the first reg.
5960 for (; NumRegs; --NumRegs, ++I) {
5961 assert(I != RC->end() && "Ran out of registers to allocate!");
5966 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5970 // Otherwise, if this was a reference to an LLVM register class, create vregs
5971 // for this reference.
5972 if (const TargetRegisterClass *RC = PhysReg.second) {
5973 RegVT = *RC->vt_begin();
5974 if (OpInfo.ConstraintVT == MVT::Other)
5977 // Create the appropriate number of virtual registers.
5978 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5979 for (; NumRegs; --NumRegs)
5980 Regs.push_back(RegInfo.createVirtualRegister(RC));
5982 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5986 // Otherwise, we couldn't allocate enough registers for this.
5989 /// visitInlineAsm - Handle a call to an InlineAsm object.
5991 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5992 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5994 /// ConstraintOperands - Information about all of the constraints.
5995 SDISelAsmOperandInfoVector ConstraintOperands;
5997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5998 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5999 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6001 bool hasMemory = false;
6003 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6004 unsigned ResNo = 0; // ResNo - The result number of the next output.
6005 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6006 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6007 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6009 MVT OpVT = MVT::Other;
6011 // Compute the value type for each operand.
6012 switch (OpInfo.Type) {
6013 case InlineAsm::isOutput:
6014 // Indirect outputs just consume an argument.
6015 if (OpInfo.isIndirect) {
6016 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6020 // The return value of the call is this value. As such, there is no
6021 // corresponding argument.
6022 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6023 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6024 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6025 STy->getElementType(ResNo));
6027 assert(ResNo == 0 && "Asm only has one result!");
6028 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6032 case InlineAsm::isInput:
6033 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6035 case InlineAsm::isClobber:
6040 // If this is an input or an indirect output, process the call argument.
6041 // BasicBlocks are labels, currently appearing only in asm's.
6042 if (OpInfo.CallOperandVal) {
6043 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6044 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6046 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6049 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6050 DAG.getDataLayout()).getSimpleVT();
6053 OpInfo.ConstraintVT = OpVT;
6055 // Indirect operand accesses access memory.
6056 if (OpInfo.isIndirect)
6059 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6060 TargetLowering::ConstraintType
6061 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6062 if (CType == TargetLowering::C_Memory) {
6070 SDValue Chain, Flag;
6072 // We won't need to flush pending loads if this asm doesn't touch
6073 // memory and is nonvolatile.
6074 if (hasMemory || IA->hasSideEffects())
6077 Chain = DAG.getRoot();
6079 // Second pass over the constraints: compute which constraint option to use
6080 // and assign registers to constraints that want a specific physreg.
6081 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6082 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6084 // If this is an output operand with a matching input operand, look up the
6085 // matching input. If their types mismatch, e.g. one is an integer, the
6086 // other is floating point, or their sizes are different, flag it as an
6088 if (OpInfo.hasMatchingInput()) {
6089 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6091 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6092 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6093 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6094 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6095 OpInfo.ConstraintVT);
6096 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6097 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6098 Input.ConstraintVT);
6099 if ((OpInfo.ConstraintVT.isInteger() !=
6100 Input.ConstraintVT.isInteger()) ||
6101 (MatchRC.second != InputRC.second)) {
6102 report_fatal_error("Unsupported asm: input constraint"
6103 " with a matching output constraint of"
6104 " incompatible type!");
6106 Input.ConstraintVT = OpInfo.ConstraintVT;
6110 // Compute the constraint code and ConstraintType to use.
6111 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6113 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6114 OpInfo.Type == InlineAsm::isClobber)
6117 // If this is a memory input, and if the operand is not indirect, do what we
6118 // need to to provide an address for the memory input.
6119 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6120 !OpInfo.isIndirect) {
6121 assert((OpInfo.isMultipleAlternative ||
6122 (OpInfo.Type == InlineAsm::isInput)) &&
6123 "Can only indirectify direct input operands!");
6125 // Memory operands really want the address of the value. If we don't have
6126 // an indirect input, put it in the constpool if we can, otherwise spill
6127 // it to a stack slot.
6128 // TODO: This isn't quite right. We need to handle these according to
6129 // the addressing mode that the constraint wants. Also, this may take
6130 // an additional register for the computation and we don't want that
6133 // If the operand is a float, integer, or vector constant, spill to a
6134 // constant pool entry to get its address.
6135 const Value *OpVal = OpInfo.CallOperandVal;
6136 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6137 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6138 OpInfo.CallOperand = DAG.getConstantPool(
6139 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6141 // Otherwise, create a stack slot and emit a store to it before the
6143 Type *Ty = OpVal->getType();
6144 auto &DL = DAG.getDataLayout();
6145 uint64_t TySize = DL.getTypeAllocSize(Ty);
6146 unsigned Align = DL.getPrefTypeAlignment(Ty);
6147 MachineFunction &MF = DAG.getMachineFunction();
6148 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6150 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6151 Chain = DAG.getStore(
6152 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6153 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6155 OpInfo.CallOperand = StackSlot;
6158 // There is no longer a Value* corresponding to this operand.
6159 OpInfo.CallOperandVal = nullptr;
6161 // It is now an indirect operand.
6162 OpInfo.isIndirect = true;
6165 // If this constraint is for a specific register, allocate it before
6167 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6168 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6171 // Second pass - Loop over all of the operands, assigning virtual or physregs
6172 // to register class operands.
6173 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6174 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6176 // C_Register operands have already been allocated, Other/Memory don't need
6178 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6179 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6182 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6183 std::vector<SDValue> AsmNodeOperands;
6184 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6185 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6186 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6188 // If we have a !srcloc metadata node associated with it, we want to attach
6189 // this to the ultimately generated inline asm machineinstr. To do this, we
6190 // pass in the third operand as this (potentially null) inline asm MDNode.
6191 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6192 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6194 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6195 // bits as operand 3.
6196 unsigned ExtraInfo = 0;
6197 if (IA->hasSideEffects())
6198 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6199 if (IA->isAlignStack())
6200 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6201 // Set the asm dialect.
6202 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6204 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6205 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6206 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6208 // Compute the constraint code and ConstraintType to use.
6209 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6211 // Ideally, we would only check against memory constraints. However, the
6212 // meaning of an other constraint can be target-specific and we can't easily
6213 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6214 // for other constriants as well.
6215 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6216 OpInfo.ConstraintType == TargetLowering::C_Other) {
6217 if (OpInfo.Type == InlineAsm::isInput)
6218 ExtraInfo |= InlineAsm::Extra_MayLoad;
6219 else if (OpInfo.Type == InlineAsm::isOutput)
6220 ExtraInfo |= InlineAsm::Extra_MayStore;
6221 else if (OpInfo.Type == InlineAsm::isClobber)
6222 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6226 AsmNodeOperands.push_back(DAG.getTargetConstant(
6227 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6229 // Loop over all of the inputs, copying the operand values into the
6230 // appropriate registers and processing the output regs.
6231 RegsForValue RetValRegs;
6233 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6234 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6236 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6237 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6239 switch (OpInfo.Type) {
6240 case InlineAsm::isOutput: {
6241 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6242 OpInfo.ConstraintType != TargetLowering::C_Register) {
6243 // Memory output, or 'other' output (e.g. 'X' constraint).
6244 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6246 unsigned ConstraintID =
6247 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6248 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6249 "Failed to convert memory constraint code to constraint id.");
6251 // Add information to the INLINEASM node to know about this output.
6252 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6253 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6254 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6256 AsmNodeOperands.push_back(OpInfo.CallOperand);
6260 // Otherwise, this is a register or register class output.
6262 // Copy the output from the appropriate register. Find a register that
6264 if (OpInfo.AssignedRegs.Regs.empty()) {
6265 LLVMContext &Ctx = *DAG.getContext();
6266 Ctx.emitError(CS.getInstruction(),
6267 "couldn't allocate output register for constraint '" +
6268 Twine(OpInfo.ConstraintCode) + "'");
6272 // If this is an indirect operand, store through the pointer after the
6274 if (OpInfo.isIndirect) {
6275 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6276 OpInfo.CallOperandVal));
6278 // This is the result value of the call.
6279 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6280 // Concatenate this output onto the outputs list.
6281 RetValRegs.append(OpInfo.AssignedRegs);
6284 // Add information to the INLINEASM node to know that this register is
6287 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6288 ? InlineAsm::Kind_RegDefEarlyClobber
6289 : InlineAsm::Kind_RegDef,
6290 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6293 case InlineAsm::isInput: {
6294 SDValue InOperandVal = OpInfo.CallOperand;
6296 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6297 // If this is required to match an output register we have already set,
6298 // just use its register.
6299 unsigned OperandNo = OpInfo.getMatchedOperand();
6301 // Scan until we find the definition we already emitted of this operand.
6302 // When we find it, create a RegsForValue operand.
6303 unsigned CurOp = InlineAsm::Op_FirstOperand;
6304 for (; OperandNo; --OperandNo) {
6305 // Advance to the next operand.
6307 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6308 assert((InlineAsm::isRegDefKind(OpFlag) ||
6309 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6310 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6311 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6315 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6316 if (InlineAsm::isRegDefKind(OpFlag) ||
6317 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6318 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6319 if (OpInfo.isIndirect) {
6320 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6321 LLVMContext &Ctx = *DAG.getContext();
6322 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6323 " don't know how to handle tied "
6324 "indirect register inputs");
6328 RegsForValue MatchedRegs;
6329 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6330 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6331 MatchedRegs.RegVTs.push_back(RegVT);
6332 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6333 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6335 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6336 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6338 LLVMContext &Ctx = *DAG.getContext();
6339 Ctx.emitError(CS.getInstruction(),
6340 "inline asm error: This value"
6341 " type register class is not natively supported!");
6345 SDLoc dl = getCurSDLoc();
6346 // Use the produced MatchedRegs object to
6347 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6348 Chain, &Flag, CS.getInstruction());
6349 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6350 true, OpInfo.getMatchedOperand(), dl,
6351 DAG, AsmNodeOperands);
6355 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6356 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6357 "Unexpected number of operands");
6358 // Add information to the INLINEASM node to know about this input.
6359 // See InlineAsm.h isUseOperandTiedToDef.
6360 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6361 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6362 OpInfo.getMatchedOperand());
6363 AsmNodeOperands.push_back(DAG.getTargetConstant(
6364 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6365 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6369 // Treat indirect 'X' constraint as memory.
6370 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6372 OpInfo.ConstraintType = TargetLowering::C_Memory;
6374 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6375 std::vector<SDValue> Ops;
6376 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6379 LLVMContext &Ctx = *DAG.getContext();
6380 Ctx.emitError(CS.getInstruction(),
6381 "invalid operand for inline asm constraint '" +
6382 Twine(OpInfo.ConstraintCode) + "'");
6386 // Add information to the INLINEASM node to know about this input.
6387 unsigned ResOpType =
6388 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6389 AsmNodeOperands.push_back(DAG.getTargetConstant(
6390 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6391 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6395 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6396 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6397 assert(InOperandVal.getValueType() ==
6398 TLI.getPointerTy(DAG.getDataLayout()) &&
6399 "Memory operands expect pointer values");
6401 unsigned ConstraintID =
6402 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6403 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6404 "Failed to convert memory constraint code to constraint id.");
6406 // Add information to the INLINEASM node to know about this input.
6407 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6408 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6409 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6412 AsmNodeOperands.push_back(InOperandVal);
6416 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6417 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6418 "Unknown constraint type!");
6420 // TODO: Support this.
6421 if (OpInfo.isIndirect) {
6422 LLVMContext &Ctx = *DAG.getContext();
6423 Ctx.emitError(CS.getInstruction(),
6424 "Don't know how to handle indirect register inputs yet "
6425 "for constraint '" +
6426 Twine(OpInfo.ConstraintCode) + "'");
6430 // Copy the input into the appropriate registers.
6431 if (OpInfo.AssignedRegs.Regs.empty()) {
6432 LLVMContext &Ctx = *DAG.getContext();
6433 Ctx.emitError(CS.getInstruction(),
6434 "couldn't allocate input reg for constraint '" +
6435 Twine(OpInfo.ConstraintCode) + "'");
6439 SDLoc dl = getCurSDLoc();
6441 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6442 Chain, &Flag, CS.getInstruction());
6444 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6445 dl, DAG, AsmNodeOperands);
6448 case InlineAsm::isClobber: {
6449 // Add the clobbered value to the operand list, so that the register
6450 // allocator is aware that the physreg got clobbered.
6451 if (!OpInfo.AssignedRegs.Regs.empty())
6452 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6453 false, 0, getCurSDLoc(), DAG,
6460 // Finish up input operands. Set the input chain and add the flag last.
6461 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6462 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6464 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6465 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6466 Flag = Chain.getValue(1);
6468 // If this asm returns a register value, copy the result from that register
6469 // and set it as the value of the call.
6470 if (!RetValRegs.Regs.empty()) {
6471 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6472 Chain, &Flag, CS.getInstruction());
6474 // FIXME: Why don't we do this for inline asms with MRVs?
6475 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6476 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6478 // If any of the results of the inline asm is a vector, it may have the
6479 // wrong width/num elts. This can happen for register classes that can
6480 // contain multiple different value types. The preg or vreg allocated may
6481 // not have the same VT as was expected. Convert it to the right type
6482 // with bit_convert.
6483 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6484 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6487 } else if (ResultType != Val.getValueType() &&
6488 ResultType.isInteger() && Val.getValueType().isInteger()) {
6489 // If a result value was tied to an input value, the computed result may
6490 // have a wider width than the expected result. Extract the relevant
6492 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6495 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6498 setValue(CS.getInstruction(), Val);
6499 // Don't need to use this as a chain in this case.
6500 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6504 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6506 // Process indirect outputs, first output all of the flagged copies out of
6508 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6509 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6510 const Value *Ptr = IndirectStoresToEmit[i].second;
6511 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6513 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6516 // Emit the non-flagged stores from the physregs.
6517 SmallVector<SDValue, 8> OutChains;
6518 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6519 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6520 StoresToEmit[i].first,
6521 getValue(StoresToEmit[i].second),
6522 MachinePointerInfo(StoresToEmit[i].second),
6524 OutChains.push_back(Val);
6527 if (!OutChains.empty())
6528 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6533 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6534 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6535 MVT::Other, getRoot(),
6536 getValue(I.getArgOperand(0)),
6537 DAG.getSrcValue(I.getArgOperand(0))));
6540 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6542 const DataLayout &DL = DAG.getDataLayout();
6543 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6544 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6545 DAG.getSrcValue(I.getOperand(0)),
6546 DL.getABITypeAlignment(I.getType()));
6548 DAG.setRoot(V.getValue(1));
6551 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6552 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6553 MVT::Other, getRoot(),
6554 getValue(I.getArgOperand(0)),
6555 DAG.getSrcValue(I.getArgOperand(0))));
6558 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6559 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6560 MVT::Other, getRoot(),
6561 getValue(I.getArgOperand(0)),
6562 getValue(I.getArgOperand(1)),
6563 DAG.getSrcValue(I.getArgOperand(0)),
6564 DAG.getSrcValue(I.getArgOperand(1))));
6567 /// \brief Lower an argument list according to the target calling convention.
6569 /// \return A tuple of <return-value, token-chain>
6571 /// This is a helper for lowering intrinsics that follow a target calling
6572 /// convention or require stack pointer adjustment. Only a subset of the
6573 /// intrinsic's operands need to participate in the calling convention.
6574 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6575 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6576 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6577 TargetLowering::ArgListTy Args;
6578 Args.reserve(NumArgs);
6580 // Populate the argument list.
6581 // Attributes for args start at offset 1, after the return attribute.
6582 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6583 ArgI != ArgE; ++ArgI) {
6584 const Value *V = CS->getOperand(ArgI);
6586 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6588 TargetLowering::ArgListEntry Entry;
6589 Entry.Node = getValue(V);
6590 Entry.Ty = V->getType();
6591 Entry.setAttributes(&CS, AttrI);
6592 Args.push_back(Entry);
6595 TargetLowering::CallLoweringInfo CLI(DAG);
6596 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6597 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6598 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6600 return lowerInvokable(CLI, EHPadBB);
6603 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6604 /// or patchpoint target node's operand list.
6606 /// Constants are converted to TargetConstants purely as an optimization to
6607 /// avoid constant materialization and register allocation.
6609 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6610 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6611 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6612 /// address materialization and register allocation, but may also be required
6613 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6614 /// alloca in the entry block, then the runtime may assume that the alloca's
6615 /// StackMap location can be read immediately after compilation and that the
6616 /// location is valid at any point during execution (this is similar to the
6617 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6618 /// only available in a register, then the runtime would need to trap when
6619 /// execution reaches the StackMap in order to read the alloca's location.
6620 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6621 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6622 SelectionDAGBuilder &Builder) {
6623 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6624 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6627 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6629 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6630 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6631 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6632 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6633 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6635 Ops.push_back(OpVal);
6639 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6640 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6641 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6642 // [live variables...])
6644 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6646 SDValue Chain, InFlag, Callee, NullPtr;
6647 SmallVector<SDValue, 32> Ops;
6649 SDLoc DL = getCurSDLoc();
6650 Callee = getValue(CI.getCalledValue());
6651 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6653 // The stackmap intrinsic only records the live variables (the arguemnts
6654 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6655 // intrinsic, this won't be lowered to a function call. This means we don't
6656 // have to worry about calling conventions and target specific lowering code.
6657 // Instead we perform the call lowering right here.
6659 // chain, flag = CALLSEQ_START(chain, 0)
6660 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6661 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6663 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6664 InFlag = Chain.getValue(1);
6666 // Add the <id> and <numBytes> constants.
6667 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6668 Ops.push_back(DAG.getTargetConstant(
6669 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6670 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6671 Ops.push_back(DAG.getTargetConstant(
6672 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6675 // Push live variables for the stack map.
6676 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6678 // We are not pushing any register mask info here on the operands list,
6679 // because the stackmap doesn't clobber anything.
6681 // Push the chain and the glue flag.
6682 Ops.push_back(Chain);
6683 Ops.push_back(InFlag);
6685 // Create the STACKMAP node.
6686 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6687 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6688 Chain = SDValue(SM, 0);
6689 InFlag = Chain.getValue(1);
6691 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6693 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6695 // Set the root to the target-lowered call chain.
6698 // Inform the Frame Information that we have a stackmap in this function.
6699 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6702 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6703 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6704 const BasicBlock *EHPadBB) {
6705 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6710 // [live variables...])
6712 CallingConv::ID CC = CS.getCallingConv();
6713 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6714 bool HasDef = !CS->getType()->isVoidTy();
6715 SDLoc dl = getCurSDLoc();
6716 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6718 // Handle immediate and symbolic callees.
6719 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6720 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6722 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6723 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6724 SDLoc(SymbolicCallee),
6725 SymbolicCallee->getValueType(0));
6727 // Get the real number of arguments participating in the call <numArgs>
6728 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6729 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6731 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6732 // Intrinsics include all meta-operands up to but not including CC.
6733 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6734 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6735 "Not enough arguments provided to the patchpoint intrinsic");
6737 // For AnyRegCC the arguments are lowered later on manually.
6738 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6740 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6741 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6742 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6744 SDNode *CallEnd = Result.second.getNode();
6745 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6746 CallEnd = CallEnd->getOperand(0).getNode();
6748 /// Get a call instruction from the call sequence chain.
6749 /// Tail calls are not allowed.
6750 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6751 "Expected a callseq node.");
6752 SDNode *Call = CallEnd->getOperand(0).getNode();
6753 bool HasGlue = Call->getGluedNode();
6755 // Replace the target specific call node with the patchable intrinsic.
6756 SmallVector<SDValue, 8> Ops;
6758 // Add the <id> and <numBytes> constants.
6759 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6760 Ops.push_back(DAG.getTargetConstant(
6761 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6762 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6763 Ops.push_back(DAG.getTargetConstant(
6764 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6768 Ops.push_back(Callee);
6770 // Adjust <numArgs> to account for any arguments that have been passed on the
6772 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6773 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6774 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6775 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6777 // Add the calling convention
6778 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6780 // Add the arguments we omitted previously. The register allocator should
6781 // place these in any free register.
6783 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6784 Ops.push_back(getValue(CS.getArgument(i)));
6786 // Push the arguments from the call instruction up to the register mask.
6787 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6788 Ops.append(Call->op_begin() + 2, e);
6790 // Push live variables for the stack map.
6791 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6793 // Push the register mask info.
6795 Ops.push_back(*(Call->op_end()-2));
6797 Ops.push_back(*(Call->op_end()-1));
6799 // Push the chain (this is originally the first operand of the call, but
6800 // becomes now the last or second to last operand).
6801 Ops.push_back(*(Call->op_begin()));
6803 // Push the glue flag (last operand).
6805 Ops.push_back(*(Call->op_end()-1));
6808 if (IsAnyRegCC && HasDef) {
6809 // Create the return types based on the intrinsic definition
6810 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6811 SmallVector<EVT, 3> ValueVTs;
6812 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6813 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6815 // There is always a chain and a glue type at the end
6816 ValueVTs.push_back(MVT::Other);
6817 ValueVTs.push_back(MVT::Glue);
6818 NodeTys = DAG.getVTList(ValueVTs);
6820 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6822 // Replace the target specific call node with a PATCHPOINT node.
6823 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6826 // Update the NodeMap.
6829 setValue(CS.getInstruction(), SDValue(MN, 0));
6831 setValue(CS.getInstruction(), Result.first);
6834 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6835 // call sequence. Furthermore the location of the chain and glue can change
6836 // when the AnyReg calling convention is used and the intrinsic returns a
6838 if (IsAnyRegCC && HasDef) {
6839 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6840 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6841 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6843 DAG.ReplaceAllUsesWith(Call, MN);
6844 DAG.DeleteNode(Call);
6846 // Inform the Frame Information that we have a patchpoint in this function.
6847 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6850 /// Returns an AttributeSet representing the attributes applied to the return
6851 /// value of the given call.
6852 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6853 SmallVector<Attribute::AttrKind, 2> Attrs;
6855 Attrs.push_back(Attribute::SExt);
6857 Attrs.push_back(Attribute::ZExt);
6859 Attrs.push_back(Attribute::InReg);
6861 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6865 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6866 /// implementation, which just calls LowerCall.
6867 /// FIXME: When all targets are
6868 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6869 std::pair<SDValue, SDValue>
6870 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6871 // Handle the incoming return values from the call.
6873 Type *OrigRetTy = CLI.RetTy;
6874 SmallVector<EVT, 4> RetTys;
6875 SmallVector<uint64_t, 4> Offsets;
6876 auto &DL = CLI.DAG.getDataLayout();
6877 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6879 SmallVector<ISD::OutputArg, 4> Outs;
6880 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6882 bool CanLowerReturn =
6883 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6884 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6886 SDValue DemoteStackSlot;
6887 int DemoteStackIdx = -100;
6888 if (!CanLowerReturn) {
6889 // FIXME: equivalent assert?
6890 // assert(!CS.hasInAllocaArgument() &&
6891 // "sret demotion is incompatible with inalloca");
6892 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6893 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6894 MachineFunction &MF = CLI.DAG.getMachineFunction();
6895 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6896 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6898 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6900 Entry.Node = DemoteStackSlot;
6901 Entry.Ty = StackSlotPtrType;
6902 Entry.isSExt = false;
6903 Entry.isZExt = false;
6904 Entry.isInReg = false;
6905 Entry.isSRet = true;
6906 Entry.isNest = false;
6907 Entry.isByVal = false;
6908 Entry.isReturned = false;
6909 Entry.Alignment = Align;
6910 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6911 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6913 // sret demotion isn't compatible with tail-calls, since the sret argument
6914 // points into the callers stack frame.
6915 CLI.IsTailCall = false;
6917 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6919 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6920 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6921 for (unsigned i = 0; i != NumRegs; ++i) {
6922 ISD::InputArg MyFlags;
6923 MyFlags.VT = RegisterVT;
6925 MyFlags.Used = CLI.IsReturnValueUsed;
6927 MyFlags.Flags.setSExt();
6929 MyFlags.Flags.setZExt();
6931 MyFlags.Flags.setInReg();
6932 CLI.Ins.push_back(MyFlags);
6937 // Handle all of the outgoing arguments.
6939 CLI.OutVals.clear();
6940 ArgListTy &Args = CLI.getArgs();
6941 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6942 SmallVector<EVT, 4> ValueVTs;
6943 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6944 Type *FinalType = Args[i].Ty;
6945 if (Args[i].isByVal)
6946 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6947 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6948 FinalType, CLI.CallConv, CLI.IsVarArg);
6949 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6951 EVT VT = ValueVTs[Value];
6952 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6953 SDValue Op = SDValue(Args[i].Node.getNode(),
6954 Args[i].Node.getResNo() + Value);
6955 ISD::ArgFlagsTy Flags;
6956 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6962 if (Args[i].isInReg)
6966 if (Args[i].isByVal)
6968 if (Args[i].isInAlloca) {
6969 Flags.setInAlloca();
6970 // Set the byval flag for CCAssignFn callbacks that don't know about
6971 // inalloca. This way we can know how many bytes we should've allocated
6972 // and how many bytes a callee cleanup function will pop. If we port
6973 // inalloca to more targets, we'll have to add custom inalloca handling
6974 // in the various CC lowering callbacks.
6977 if (Args[i].isByVal || Args[i].isInAlloca) {
6978 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6979 Type *ElementTy = Ty->getElementType();
6980 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6981 // For ByVal, alignment should come from FE. BE will guess if this
6982 // info is not there but there are cases it cannot get right.
6983 unsigned FrameAlign;
6984 if (Args[i].Alignment)
6985 FrameAlign = Args[i].Alignment;
6987 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6988 Flags.setByValAlign(FrameAlign);
6993 Flags.setInConsecutiveRegs();
6994 Flags.setOrigAlign(OriginalAlignment);
6996 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6997 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6998 SmallVector<SDValue, 4> Parts(NumParts);
6999 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7002 ExtendKind = ISD::SIGN_EXTEND;
7003 else if (Args[i].isZExt)
7004 ExtendKind = ISD::ZERO_EXTEND;
7006 // Conservatively only handle 'returned' on non-vectors for now
7007 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7008 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7009 "unexpected use of 'returned'");
7010 // Before passing 'returned' to the target lowering code, ensure that
7011 // either the register MVT and the actual EVT are the same size or that
7012 // the return value and argument are extended in the same way; in these
7013 // cases it's safe to pass the argument register value unchanged as the
7014 // return register value (although it's at the target's option whether
7016 // TODO: allow code generation to take advantage of partially preserved
7017 // registers rather than clobbering the entire register when the
7018 // parameter extension method is not compatible with the return
7020 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7021 (ExtendKind != ISD::ANY_EXTEND &&
7022 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7023 Flags.setReturned();
7026 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7027 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7029 for (unsigned j = 0; j != NumParts; ++j) {
7030 // if it isn't first piece, alignment must be 1
7031 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7032 i < CLI.NumFixedArgs,
7033 i, j*Parts[j].getValueType().getStoreSize());
7034 if (NumParts > 1 && j == 0)
7035 MyFlags.Flags.setSplit();
7037 MyFlags.Flags.setOrigAlign(1);
7039 CLI.Outs.push_back(MyFlags);
7040 CLI.OutVals.push_back(Parts[j]);
7043 if (NeedsRegBlock && Value == NumValues - 1)
7044 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7048 SmallVector<SDValue, 4> InVals;
7049 CLI.Chain = LowerCall(CLI, InVals);
7051 // Verify that the target's LowerCall behaved as expected.
7052 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7053 "LowerCall didn't return a valid chain!");
7054 assert((!CLI.IsTailCall || InVals.empty()) &&
7055 "LowerCall emitted a return value for a tail call!");
7056 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7057 "LowerCall didn't emit the correct number of values!");
7059 // For a tail call, the return value is merely live-out and there aren't
7060 // any nodes in the DAG representing it. Return a special value to
7061 // indicate that a tail call has been emitted and no more Instructions
7062 // should be processed in the current block.
7063 if (CLI.IsTailCall) {
7064 CLI.DAG.setRoot(CLI.Chain);
7065 return std::make_pair(SDValue(), SDValue());
7068 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7069 assert(InVals[i].getNode() &&
7070 "LowerCall emitted a null value!");
7071 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7072 "LowerCall emitted a value with the wrong type!");
7075 SmallVector<SDValue, 4> ReturnValues;
7076 if (!CanLowerReturn) {
7077 // The instruction result is the result of loading from the
7078 // hidden sret parameter.
7079 SmallVector<EVT, 1> PVTs;
7080 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7082 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7083 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7084 EVT PtrVT = PVTs[0];
7086 unsigned NumValues = RetTys.size();
7087 ReturnValues.resize(NumValues);
7088 SmallVector<SDValue, 4> Chains(NumValues);
7090 for (unsigned i = 0; i < NumValues; ++i) {
7091 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7092 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7094 SDValue L = CLI.DAG.getLoad(
7095 RetTys[i], CLI.DL, CLI.Chain, Add,
7096 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7097 DemoteStackIdx, Offsets[i]),
7098 false, false, false, 1);
7099 ReturnValues[i] = L;
7100 Chains[i] = L.getValue(1);
7103 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7105 // Collect the legal value parts into potentially illegal values
7106 // that correspond to the original function's return values.
7107 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7109 AssertOp = ISD::AssertSext;
7110 else if (CLI.RetZExt)
7111 AssertOp = ISD::AssertZext;
7112 unsigned CurReg = 0;
7113 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7115 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7116 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7119 NumRegs, RegisterVT, VT, nullptr,
7124 // For a function returning void, there is no return value. We can't create
7125 // such a node, so we just return a null return value in that case. In
7126 // that case, nothing will actually look at the value.
7127 if (ReturnValues.empty())
7128 return std::make_pair(SDValue(), CLI.Chain);
7131 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7132 CLI.DAG.getVTList(RetTys), ReturnValues);
7133 return std::make_pair(Res, CLI.Chain);
7136 void TargetLowering::LowerOperationWrapper(SDNode *N,
7137 SmallVectorImpl<SDValue> &Results,
7138 SelectionDAG &DAG) const {
7139 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7141 Results.push_back(Res);
7144 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7145 llvm_unreachable("LowerOperation not implemented for this target!");
7149 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7150 SDValue Op = getNonRegisterValue(V);
7151 assert((Op.getOpcode() != ISD::CopyFromReg ||
7152 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7153 "Copy from a reg to the same reg!");
7154 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7157 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7159 SDValue Chain = DAG.getEntryNode();
7161 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7162 FuncInfo.PreferredExtendType.end())
7164 : FuncInfo.PreferredExtendType[V];
7165 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7166 PendingExports.push_back(Chain);
7169 #include "llvm/CodeGen/SelectionDAGISel.h"
7171 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7172 /// entry block, return true. This includes arguments used by switches, since
7173 /// the switch may expand into multiple basic blocks.
7174 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7175 // With FastISel active, we may be splitting blocks, so force creation
7176 // of virtual registers for all non-dead arguments.
7178 return A->use_empty();
7180 const BasicBlock *Entry = A->getParent()->begin();
7181 for (const User *U : A->users())
7182 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7183 return false; // Use not in entry block.
7188 void SelectionDAGISel::LowerArguments(const Function &F) {
7189 SelectionDAG &DAG = SDB->DAG;
7190 SDLoc dl = SDB->getCurSDLoc();
7191 const DataLayout &DL = DAG.getDataLayout();
7192 SmallVector<ISD::InputArg, 16> Ins;
7194 if (!FuncInfo->CanLowerReturn) {
7195 // Put in an sret pointer parameter before all the other parameters.
7196 SmallVector<EVT, 1> ValueVTs;
7197 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7198 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7200 // NOTE: Assuming that a pointer will never break down to more than one VT
7202 ISD::ArgFlagsTy Flags;
7204 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7205 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7206 ISD::InputArg::NoArgIndex, 0);
7207 Ins.push_back(RetArg);
7210 // Set up the incoming argument description vector.
7212 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7213 I != E; ++I, ++Idx) {
7214 SmallVector<EVT, 4> ValueVTs;
7215 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7216 bool isArgValueUsed = !I->use_empty();
7217 unsigned PartBase = 0;
7218 Type *FinalType = I->getType();
7219 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7220 FinalType = cast<PointerType>(FinalType)->getElementType();
7221 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7222 FinalType, F.getCallingConv(), F.isVarArg());
7223 for (unsigned Value = 0, NumValues = ValueVTs.size();
7224 Value != NumValues; ++Value) {
7225 EVT VT = ValueVTs[Value];
7226 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7227 ISD::ArgFlagsTy Flags;
7228 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7230 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7232 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7234 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7236 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7238 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7240 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7241 Flags.setInAlloca();
7242 // Set the byval flag for CCAssignFn callbacks that don't know about
7243 // inalloca. This way we can know how many bytes we should've allocated
7244 // and how many bytes a callee cleanup function will pop. If we port
7245 // inalloca to more targets, we'll have to add custom inalloca handling
7246 // in the various CC lowering callbacks.
7249 if (Flags.isByVal() || Flags.isInAlloca()) {
7250 PointerType *Ty = cast<PointerType>(I->getType());
7251 Type *ElementTy = Ty->getElementType();
7252 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7253 // For ByVal, alignment should be passed from FE. BE will guess if
7254 // this info is not there but there are cases it cannot get right.
7255 unsigned FrameAlign;
7256 if (F.getParamAlignment(Idx))
7257 FrameAlign = F.getParamAlignment(Idx);
7259 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7260 Flags.setByValAlign(FrameAlign);
7262 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7265 Flags.setInConsecutiveRegs();
7266 Flags.setOrigAlign(OriginalAlignment);
7268 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7269 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7270 for (unsigned i = 0; i != NumRegs; ++i) {
7271 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7272 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7273 if (NumRegs > 1 && i == 0)
7274 MyFlags.Flags.setSplit();
7275 // if it isn't first piece, alignment must be 1
7277 MyFlags.Flags.setOrigAlign(1);
7278 Ins.push_back(MyFlags);
7280 if (NeedsRegBlock && Value == NumValues - 1)
7281 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7282 PartBase += VT.getStoreSize();
7286 // Call the target to set up the argument values.
7287 SmallVector<SDValue, 8> InVals;
7288 SDValue NewRoot = TLI->LowerFormalArguments(
7289 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7291 // Verify that the target's LowerFormalArguments behaved as expected.
7292 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7293 "LowerFormalArguments didn't return a valid chain!");
7294 assert(InVals.size() == Ins.size() &&
7295 "LowerFormalArguments didn't emit the correct number of values!");
7297 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7298 assert(InVals[i].getNode() &&
7299 "LowerFormalArguments emitted a null value!");
7300 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7301 "LowerFormalArguments emitted a value with the wrong type!");
7305 // Update the DAG with the new chain value resulting from argument lowering.
7306 DAG.setRoot(NewRoot);
7308 // Set up the argument values.
7311 if (!FuncInfo->CanLowerReturn) {
7312 // Create a virtual register for the sret pointer, and put in a copy
7313 // from the sret argument into it.
7314 SmallVector<EVT, 1> ValueVTs;
7315 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7316 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7317 MVT VT = ValueVTs[0].getSimpleVT();
7318 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7319 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7320 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7321 RegVT, VT, nullptr, AssertOp);
7323 MachineFunction& MF = SDB->DAG.getMachineFunction();
7324 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7325 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7326 FuncInfo->DemoteRegister = SRetReg;
7328 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7329 DAG.setRoot(NewRoot);
7331 // i indexes lowered arguments. Bump it past the hidden sret argument.
7332 // Idx indexes LLVM arguments. Don't touch it.
7336 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7338 SmallVector<SDValue, 4> ArgValues;
7339 SmallVector<EVT, 4> ValueVTs;
7340 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7341 unsigned NumValues = ValueVTs.size();
7343 // If this argument is unused then remember its value. It is used to generate
7344 // debugging information.
7345 if (I->use_empty() && NumValues) {
7346 SDB->setUnusedArgValue(I, InVals[i]);
7348 // Also remember any frame index for use in FastISel.
7349 if (FrameIndexSDNode *FI =
7350 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7351 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7354 for (unsigned Val = 0; Val != NumValues; ++Val) {
7355 EVT VT = ValueVTs[Val];
7356 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7357 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7359 if (!I->use_empty()) {
7360 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7361 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7362 AssertOp = ISD::AssertSext;
7363 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7364 AssertOp = ISD::AssertZext;
7366 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7367 NumParts, PartVT, VT,
7368 nullptr, AssertOp));
7374 // We don't need to do anything else for unused arguments.
7375 if (ArgValues.empty())
7378 // Note down frame index.
7379 if (FrameIndexSDNode *FI =
7380 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7381 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7383 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7384 SDB->getCurSDLoc());
7386 SDB->setValue(I, Res);
7387 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7388 if (LoadSDNode *LNode =
7389 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7390 if (FrameIndexSDNode *FI =
7391 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7392 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7395 // If this argument is live outside of the entry block, insert a copy from
7396 // wherever we got it to the vreg that other BB's will reference it as.
7397 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7398 // If we can, though, try to skip creating an unnecessary vreg.
7399 // FIXME: This isn't very clean... it would be nice to make this more
7400 // general. It's also subtly incompatible with the hacks FastISel
7402 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7403 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7404 FuncInfo->ValueMap[I] = Reg;
7408 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7409 FuncInfo->InitializeRegForValue(I);
7410 SDB->CopyToExportRegsIfNeeded(I);
7414 assert(i == InVals.size() && "Argument register count mismatch!");
7416 // Finally, if the target has anything special to do, allow it to do so.
7417 EmitFunctionEntryCode();
7420 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7421 /// ensure constants are generated when needed. Remember the virtual registers
7422 /// that need to be added to the Machine PHI nodes as input. We cannot just
7423 /// directly add them, because expansion might result in multiple MBB's for one
7424 /// BB. As such, the start of the BB might correspond to a different MBB than
7428 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7429 const TerminatorInst *TI = LLVMBB->getTerminator();
7431 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7433 // Check PHI nodes in successors that expect a value to be available from this
7435 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7436 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7437 if (!isa<PHINode>(SuccBB->begin())) continue;
7438 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7440 // If this terminator has multiple identical successors (common for
7441 // switches), only handle each succ once.
7442 if (!SuccsHandled.insert(SuccMBB).second)
7445 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7447 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7448 // nodes and Machine PHI nodes, but the incoming operands have not been
7450 for (BasicBlock::const_iterator I = SuccBB->begin();
7451 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7452 // Ignore dead phi's.
7453 if (PN->use_empty()) continue;
7456 if (PN->getType()->isEmptyTy())
7460 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7462 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7463 unsigned &RegOut = ConstantsOut[C];
7465 RegOut = FuncInfo.CreateRegs(C->getType());
7466 CopyValueToVirtualRegister(C, RegOut);
7470 DenseMap<const Value *, unsigned>::iterator I =
7471 FuncInfo.ValueMap.find(PHIOp);
7472 if (I != FuncInfo.ValueMap.end())
7475 assert(isa<AllocaInst>(PHIOp) &&
7476 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7477 "Didn't codegen value into a register!??");
7478 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7479 CopyValueToVirtualRegister(PHIOp, Reg);
7483 // Remember that this register needs to added to the machine PHI node as
7484 // the input for this MBB.
7485 SmallVector<EVT, 4> ValueVTs;
7486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7487 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7488 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7489 EVT VT = ValueVTs[vti];
7490 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7491 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7492 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7493 Reg += NumRegisters;
7498 ConstantsOut.clear();
7501 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7504 SelectionDAGBuilder::StackProtectorDescriptor::
7505 AddSuccessorMBB(const BasicBlock *BB,
7506 MachineBasicBlock *ParentMBB,
7508 MachineBasicBlock *SuccMBB) {
7509 // If SuccBB has not been created yet, create it.
7511 MachineFunction *MF = ParentMBB->getParent();
7512 MachineFunction::iterator BBI = ParentMBB;
7513 SuccMBB = MF->CreateMachineBasicBlock(BB);
7514 MF->insert(++BBI, SuccMBB);
7516 // Add it as a successor of ParentMBB.
7517 ParentMBB->addSuccessor(
7518 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7522 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7523 MachineFunction::iterator I = MBB;
7524 if (++I == FuncInfo.MF->end())
7529 /// During lowering new call nodes can be created (such as memset, etc.).
7530 /// Those will become new roots of the current DAG, but complications arise
7531 /// when they are tail calls. In such cases, the call lowering will update
7532 /// the root, but the builder still needs to know that a tail call has been
7533 /// lowered in order to avoid generating an additional return.
7534 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7535 // If the node is null, we do have a tail call.
7536 if (MaybeTC.getNode() != nullptr)
7537 DAG.setRoot(MaybeTC);
7542 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7543 unsigned *TotalCases, unsigned First,
7545 assert(Last >= First);
7546 assert(TotalCases[Last] >= TotalCases[First]);
7548 APInt LowCase = Clusters[First].Low->getValue();
7549 APInt HighCase = Clusters[Last].High->getValue();
7550 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7552 // FIXME: A range of consecutive cases has 100% density, but only requires one
7553 // comparison to lower. We should discriminate against such consecutive ranges
7556 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7557 uint64_t Range = Diff + 1;
7560 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7562 assert(NumCases < UINT64_MAX / 100);
7563 assert(Range >= NumCases);
7565 return NumCases * 100 >= Range * MinJumpTableDensity;
7568 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7569 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7570 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7573 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7574 unsigned First, unsigned Last,
7575 const SwitchInst *SI,
7576 MachineBasicBlock *DefaultMBB,
7577 CaseCluster &JTCluster) {
7578 assert(First <= Last);
7580 uint32_t Weight = 0;
7581 unsigned NumCmps = 0;
7582 std::vector<MachineBasicBlock*> Table;
7583 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7584 for (unsigned I = First; I <= Last; ++I) {
7585 assert(Clusters[I].Kind == CC_Range);
7586 Weight += Clusters[I].Weight;
7587 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7588 APInt Low = Clusters[I].Low->getValue();
7589 APInt High = Clusters[I].High->getValue();
7590 NumCmps += (Low == High) ? 1 : 2;
7592 // Fill the gap between this and the previous cluster.
7593 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7594 assert(PreviousHigh.slt(Low));
7595 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7596 for (uint64_t J = 0; J < Gap; J++)
7597 Table.push_back(DefaultMBB);
7599 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7600 for (uint64_t J = 0; J < ClusterSize; ++J)
7601 Table.push_back(Clusters[I].MBB);
7602 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7605 unsigned NumDests = JTWeights.size();
7606 if (isSuitableForBitTests(NumDests, NumCmps,
7607 Clusters[First].Low->getValue(),
7608 Clusters[Last].High->getValue())) {
7609 // Clusters[First..Last] should be lowered as bit tests instead.
7613 // Create the MBB that will load from and jump through the table.
7614 // Note: We create it here, but it's not inserted into the function yet.
7615 MachineFunction *CurMF = FuncInfo.MF;
7616 MachineBasicBlock *JumpTableMBB =
7617 CurMF->CreateMachineBasicBlock(SI->getParent());
7619 // Add successors. Note: use table order for determinism.
7620 SmallPtrSet<MachineBasicBlock *, 8> Done;
7621 for (MachineBasicBlock *Succ : Table) {
7622 if (Done.count(Succ))
7624 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7629 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7630 ->createJumpTableIndex(Table);
7632 // Set up the jump table info.
7633 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7634 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7635 Clusters[Last].High->getValue(), SI->getCondition(),
7637 JTCases.emplace_back(std::move(JTH), std::move(JT));
7639 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7640 JTCases.size() - 1, Weight);
7644 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7645 const SwitchInst *SI,
7646 MachineBasicBlock *DefaultMBB) {
7648 // Clusters must be non-empty, sorted, and only contain Range clusters.
7649 assert(!Clusters.empty());
7650 for (CaseCluster &C : Clusters)
7651 assert(C.Kind == CC_Range);
7652 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7653 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7656 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7657 if (!areJTsAllowed(TLI))
7660 const int64_t N = Clusters.size();
7661 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7663 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7664 SmallVector<unsigned, 8> TotalCases(N);
7666 for (unsigned i = 0; i < N; ++i) {
7667 APInt Hi = Clusters[i].High->getValue();
7668 APInt Lo = Clusters[i].Low->getValue();
7669 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7671 TotalCases[i] += TotalCases[i - 1];
7674 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7675 // Cheap case: the whole range might be suitable for jump table.
7676 CaseCluster JTCluster;
7677 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7678 Clusters[0] = JTCluster;
7684 // The algorithm below is not suitable for -O0.
7685 if (TM.getOptLevel() == CodeGenOpt::None)
7688 // Split Clusters into minimum number of dense partitions. The algorithm uses
7689 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7690 // for the Case Statement'" (1994), but builds the MinPartitions array in
7691 // reverse order to make it easier to reconstruct the partitions in ascending
7692 // order. In the choice between two optimal partitionings, it picks the one
7693 // which yields more jump tables.
7695 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7696 SmallVector<unsigned, 8> MinPartitions(N);
7697 // LastElement[i] is the last element of the partition starting at i.
7698 SmallVector<unsigned, 8> LastElement(N);
7699 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7700 SmallVector<unsigned, 8> NumTables(N);
7702 // Base case: There is only one way to partition Clusters[N-1].
7703 MinPartitions[N - 1] = 1;
7704 LastElement[N - 1] = N - 1;
7705 assert(MinJumpTableSize > 1);
7706 NumTables[N - 1] = 0;
7708 // Note: loop indexes are signed to avoid underflow.
7709 for (int64_t i = N - 2; i >= 0; i--) {
7710 // Find optimal partitioning of Clusters[i..N-1].
7711 // Baseline: Put Clusters[i] into a partition on its own.
7712 MinPartitions[i] = MinPartitions[i + 1] + 1;
7714 NumTables[i] = NumTables[i + 1];
7716 // Search for a solution that results in fewer partitions.
7717 for (int64_t j = N - 1; j > i; j--) {
7718 // Try building a partition from Clusters[i..j].
7719 if (isDense(Clusters, &TotalCases[0], i, j)) {
7720 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7721 bool IsTable = j - i + 1 >= MinJumpTableSize;
7722 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7724 // If this j leads to fewer partitions, or same number of partitions
7725 // with more lookup tables, it is a better partitioning.
7726 if (NumPartitions < MinPartitions[i] ||
7727 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7728 MinPartitions[i] = NumPartitions;
7730 NumTables[i] = Tables;
7736 // Iterate over the partitions, replacing some with jump tables in-place.
7737 unsigned DstIndex = 0;
7738 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7739 Last = LastElement[First];
7740 assert(Last >= First);
7741 assert(DstIndex <= First);
7742 unsigned NumClusters = Last - First + 1;
7744 CaseCluster JTCluster;
7745 if (NumClusters >= MinJumpTableSize &&
7746 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7747 Clusters[DstIndex++] = JTCluster;
7749 for (unsigned I = First; I <= Last; ++I)
7750 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7753 Clusters.resize(DstIndex);
7756 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7757 // FIXME: Using the pointer type doesn't seem ideal.
7758 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7759 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7763 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7766 const APInt &High) {
7767 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7768 // range of cases both require only one branch to lower. Just looking at the
7769 // number of clusters and destinations should be enough to decide whether to
7772 // To lower a range with bit tests, the range must fit the bitwidth of a
7774 if (!rangeFitsInWord(Low, High))
7777 // Decide whether it's profitable to lower this range with bit tests. Each
7778 // destination requires a bit test and branch, and there is an overall range
7779 // check branch. For a small number of clusters, separate comparisons might be
7780 // cheaper, and for many destinations, splitting the range might be better.
7781 return (NumDests == 1 && NumCmps >= 3) ||
7782 (NumDests == 2 && NumCmps >= 5) ||
7783 (NumDests == 3 && NumCmps >= 6);
7786 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7787 unsigned First, unsigned Last,
7788 const SwitchInst *SI,
7789 CaseCluster &BTCluster) {
7790 assert(First <= Last);
7794 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7795 unsigned NumCmps = 0;
7796 for (int64_t I = First; I <= Last; ++I) {
7797 assert(Clusters[I].Kind == CC_Range);
7798 Dests.set(Clusters[I].MBB->getNumber());
7799 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7801 unsigned NumDests = Dests.count();
7803 APInt Low = Clusters[First].Low->getValue();
7804 APInt High = Clusters[Last].High->getValue();
7805 assert(Low.slt(High));
7807 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7813 const int BitWidth = DAG.getTargetLoweringInfo()
7814 .getPointerTy(DAG.getDataLayout())
7816 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7818 // Check if the clusters cover a contiguous range such that no value in the
7819 // range will jump to the default statement.
7820 bool ContiguousRange = true;
7821 for (int64_t I = First + 1; I <= Last; ++I) {
7822 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7823 ContiguousRange = false;
7828 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7829 // Optimize the case where all the case values fit in a word without having
7830 // to subtract minValue. In this case, we can optimize away the subtraction.
7831 LowBound = APInt::getNullValue(Low.getBitWidth());
7833 ContiguousRange = false;
7836 CmpRange = High - Low;
7840 uint32_t TotalWeight = 0;
7841 for (unsigned i = First; i <= Last; ++i) {
7842 // Find the CaseBits for this destination.
7844 for (j = 0; j < CBV.size(); ++j)
7845 if (CBV[j].BB == Clusters[i].MBB)
7847 if (j == CBV.size())
7848 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7849 CaseBits *CB = &CBV[j];
7851 // Update Mask, Bits and ExtraWeight.
7852 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7853 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7854 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7855 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7856 CB->Bits += Hi - Lo + 1;
7857 CB->ExtraWeight += Clusters[i].Weight;
7858 TotalWeight += Clusters[i].Weight;
7859 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7863 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7864 // Sort by weight first, number of bits second.
7865 if (a.ExtraWeight != b.ExtraWeight)
7866 return a.ExtraWeight > b.ExtraWeight;
7867 return a.Bits > b.Bits;
7870 for (auto &CB : CBV) {
7871 MachineBasicBlock *BitTestBB =
7872 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7873 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7875 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7876 SI->getCondition(), -1U, MVT::Other, false,
7877 ContiguousRange, nullptr, nullptr, std::move(BTI),
7880 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7881 BitTestCases.size() - 1, TotalWeight);
7885 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7886 const SwitchInst *SI) {
7887 // Partition Clusters into as few subsets as possible, where each subset has a
7888 // range that fits in a machine word and has <= 3 unique destinations.
7891 // Clusters must be sorted and contain Range or JumpTable clusters.
7892 assert(!Clusters.empty());
7893 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7894 for (const CaseCluster &C : Clusters)
7895 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7896 for (unsigned i = 1; i < Clusters.size(); ++i)
7897 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7900 // The algorithm below is not suitable for -O0.
7901 if (TM.getOptLevel() == CodeGenOpt::None)
7904 // If target does not have legal shift left, do not emit bit tests at all.
7905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7906 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7907 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7910 int BitWidth = PTy.getSizeInBits();
7911 const int64_t N = Clusters.size();
7913 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7914 SmallVector<unsigned, 8> MinPartitions(N);
7915 // LastElement[i] is the last element of the partition starting at i.
7916 SmallVector<unsigned, 8> LastElement(N);
7918 // FIXME: This might not be the best algorithm for finding bit test clusters.
7920 // Base case: There is only one way to partition Clusters[N-1].
7921 MinPartitions[N - 1] = 1;
7922 LastElement[N - 1] = N - 1;
7924 // Note: loop indexes are signed to avoid underflow.
7925 for (int64_t i = N - 2; i >= 0; --i) {
7926 // Find optimal partitioning of Clusters[i..N-1].
7927 // Baseline: Put Clusters[i] into a partition on its own.
7928 MinPartitions[i] = MinPartitions[i + 1] + 1;
7931 // Search for a solution that results in fewer partitions.
7932 // Note: the search is limited by BitWidth, reducing time complexity.
7933 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7934 // Try building a partition from Clusters[i..j].
7937 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7938 Clusters[j].High->getValue()))
7941 // Check nbr of destinations and cluster types.
7942 // FIXME: This works, but doesn't seem very efficient.
7943 bool RangesOnly = true;
7944 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7945 for (int64_t k = i; k <= j; k++) {
7946 if (Clusters[k].Kind != CC_Range) {
7950 Dests.set(Clusters[k].MBB->getNumber());
7952 if (!RangesOnly || Dests.count() > 3)
7955 // Check if it's a better partition.
7956 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7957 if (NumPartitions < MinPartitions[i]) {
7958 // Found a better partition.
7959 MinPartitions[i] = NumPartitions;
7965 // Iterate over the partitions, replacing with bit-test clusters in-place.
7966 unsigned DstIndex = 0;
7967 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7968 Last = LastElement[First];
7969 assert(First <= Last);
7970 assert(DstIndex <= First);
7972 CaseCluster BitTestCluster;
7973 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7974 Clusters[DstIndex++] = BitTestCluster;
7976 size_t NumClusters = Last - First + 1;
7977 std::memmove(&Clusters[DstIndex], &Clusters[First],
7978 sizeof(Clusters[0]) * NumClusters);
7979 DstIndex += NumClusters;
7982 Clusters.resize(DstIndex);
7985 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7986 MachineBasicBlock *SwitchMBB,
7987 MachineBasicBlock *DefaultMBB) {
7988 MachineFunction *CurMF = FuncInfo.MF;
7989 MachineBasicBlock *NextMBB = nullptr;
7990 MachineFunction::iterator BBI = W.MBB;
7991 if (++BBI != FuncInfo.MF->end())
7994 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7996 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7998 if (Size == 2 && W.MBB == SwitchMBB) {
7999 // If any two of the cases has the same destination, and if one value
8000 // is the same as the other, but has one bit unset that the other has set,
8001 // use bit manipulation to do two compares at once. For example:
8002 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8003 // TODO: This could be extended to merge any 2 cases in switches with 3
8005 // TODO: Handle cases where W.CaseBB != SwitchBB.
8006 CaseCluster &Small = *W.FirstCluster;
8007 CaseCluster &Big = *W.LastCluster;
8009 if (Small.Low == Small.High && Big.Low == Big.High &&
8010 Small.MBB == Big.MBB) {
8011 const APInt &SmallValue = Small.Low->getValue();
8012 const APInt &BigValue = Big.Low->getValue();
8014 // Check that there is only one bit different.
8015 APInt CommonBit = BigValue ^ SmallValue;
8016 if (CommonBit.isPowerOf2()) {
8017 SDValue CondLHS = getValue(Cond);
8018 EVT VT = CondLHS.getValueType();
8019 SDLoc DL = getCurSDLoc();
8021 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8022 DAG.getConstant(CommonBit, DL, VT));
8023 SDValue Cond = DAG.getSetCC(
8024 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8027 // Update successor info.
8028 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8029 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8030 addSuccessorWithWeight(
8031 SwitchMBB, DefaultMBB,
8032 // The default destination is the first successor in IR.
8033 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8036 // Insert the true branch.
8038 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8039 DAG.getBasicBlock(Small.MBB));
8040 // Insert the false branch.
8041 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8042 DAG.getBasicBlock(DefaultMBB));
8044 DAG.setRoot(BrCond);
8050 if (TM.getOptLevel() != CodeGenOpt::None) {
8051 // Order cases by weight so the most likely case will be checked first.
8052 std::sort(W.FirstCluster, W.LastCluster + 1,
8053 [](const CaseCluster &a, const CaseCluster &b) {
8054 return a.Weight > b.Weight;
8057 // Rearrange the case blocks so that the last one falls through if possible
8058 // without without changing the order of weights.
8059 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8061 if (I->Weight > W.LastCluster->Weight)
8063 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8064 std::swap(*I, *W.LastCluster);
8070 // Compute total weight.
8071 uint32_t DefaultWeight = W.DefaultWeight;
8072 uint32_t UnhandledWeights = DefaultWeight;
8073 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8074 UnhandledWeights += I->Weight;
8075 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8078 MachineBasicBlock *CurMBB = W.MBB;
8079 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8080 MachineBasicBlock *Fallthrough;
8081 if (I == W.LastCluster) {
8082 // For the last cluster, fall through to the default destination.
8083 Fallthrough = DefaultMBB;
8085 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8086 CurMF->insert(BBI, Fallthrough);
8087 // Put Cond in a virtual register to make it available from the new blocks.
8088 ExportFromCurrentBlock(Cond);
8090 UnhandledWeights -= I->Weight;
8093 case CC_JumpTable: {
8094 // FIXME: Optimize away range check based on pivot comparisons.
8095 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8096 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8098 // The jump block hasn't been inserted yet; insert it here.
8099 MachineBasicBlock *JumpMBB = JT->MBB;
8100 CurMF->insert(BBI, JumpMBB);
8102 uint32_t JumpWeight = I->Weight;
8103 uint32_t FallthroughWeight = UnhandledWeights;
8105 // If Fallthrough is a target of the jump table, we evenly distribute
8106 // the weight on the edge to Fallthrough to successors of CurMBB.
8107 // Also update the weight on the edge from JumpMBB to Fallthrough.
8108 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8109 SE = JumpMBB->succ_end();
8111 if (*SI == Fallthrough) {
8112 JumpWeight += DefaultWeight / 2;
8113 FallthroughWeight -= DefaultWeight / 2;
8114 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8119 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8120 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8122 // The jump table header will be inserted in our current block, do the
8123 // range check, and fall through to our fallthrough block.
8124 JTH->HeaderBB = CurMBB;
8125 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8127 // If we're in the right place, emit the jump table header right now.
8128 if (CurMBB == SwitchMBB) {
8129 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8130 JTH->Emitted = true;
8135 // FIXME: Optimize away range check based on pivot comparisons.
8136 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8138 // The bit test blocks haven't been inserted yet; insert them here.
8139 for (BitTestCase &BTC : BTB->Cases)
8140 CurMF->insert(BBI, BTC.ThisBB);
8142 // Fill in fields of the BitTestBlock.
8143 BTB->Parent = CurMBB;
8144 BTB->Default = Fallthrough;
8146 BTB->DefaultWeight = UnhandledWeights;
8147 // If the cases in bit test don't form a contiguous range, we evenly
8148 // distribute the weight on the edge to Fallthrough to two successors
8150 if (!BTB->ContiguousRange) {
8151 BTB->Weight += DefaultWeight / 2;
8152 BTB->DefaultWeight -= DefaultWeight / 2;
8155 // If we're in the right place, emit the bit test header right now.
8156 if (CurMBB == SwitchMBB) {
8157 visitBitTestHeader(*BTB, SwitchMBB);
8158 BTB->Emitted = true;
8163 const Value *RHS, *LHS, *MHS;
8165 if (I->Low == I->High) {
8166 // Check Cond == I->Low.
8172 // Check I->Low <= Cond <= I->High.
8179 // The false weight is the sum of all unhandled cases.
8180 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8183 if (CurMBB == SwitchMBB)
8184 visitSwitchCase(CB, SwitchMBB);
8186 SwitchCases.push_back(CB);
8191 CurMBB = Fallthrough;
8195 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8196 CaseClusterIt First,
8197 CaseClusterIt Last) {
8198 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8199 if (X.Weight != CC.Weight)
8200 return X.Weight > CC.Weight;
8202 // Ties are broken by comparing the case value.
8203 return X.Low->getValue().slt(CC.Low->getValue());
8207 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8208 const SwitchWorkListItem &W,
8210 MachineBasicBlock *SwitchMBB) {
8211 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8212 "Clusters not sorted?");
8214 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8216 // Balance the tree based on branch weights to create a near-optimal (in terms
8217 // of search time given key frequency) binary search tree. See e.g. Kurt
8218 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8219 CaseClusterIt LastLeft = W.FirstCluster;
8220 CaseClusterIt FirstRight = W.LastCluster;
8221 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8222 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8224 // Move LastLeft and FirstRight towards each other from opposite directions to
8225 // find a partitioning of the clusters which balances the weight on both
8226 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8227 // taken to ensure 0-weight nodes are distributed evenly.
8229 while (LastLeft + 1 < FirstRight) {
8230 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8231 LeftWeight += (++LastLeft)->Weight;
8233 RightWeight += (--FirstRight)->Weight;
8238 // Our binary search tree differs from a typical BST in that ours can have up
8239 // to three values in each leaf. The pivot selection above doesn't take that
8240 // into account, which means the tree might require more nodes and be less
8241 // efficient. We compensate for this here.
8243 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8244 unsigned NumRight = W.LastCluster - FirstRight + 1;
8246 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8247 // If one side has less than 3 clusters, and the other has more than 3,
8248 // consider taking a cluster from the other side.
8250 if (NumLeft < NumRight) {
8251 // Consider moving the first cluster on the right to the left side.
8252 CaseCluster &CC = *FirstRight;
8253 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8254 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8255 if (LeftSideRank <= RightSideRank) {
8256 // Moving the cluster to the left does not demote it.
8262 assert(NumRight < NumLeft);
8263 // Consider moving the last element on the left to the right side.
8264 CaseCluster &CC = *LastLeft;
8265 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8266 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8267 if (RightSideRank <= LeftSideRank) {
8268 // Moving the cluster to the right does not demot it.
8278 assert(LastLeft + 1 == FirstRight);
8279 assert(LastLeft >= W.FirstCluster);
8280 assert(FirstRight <= W.LastCluster);
8282 // Use the first element on the right as pivot since we will make less-than
8283 // comparisons against it.
8284 CaseClusterIt PivotCluster = FirstRight;
8285 assert(PivotCluster > W.FirstCluster);
8286 assert(PivotCluster <= W.LastCluster);
8288 CaseClusterIt FirstLeft = W.FirstCluster;
8289 CaseClusterIt LastRight = W.LastCluster;
8291 const ConstantInt *Pivot = PivotCluster->Low;
8293 // New blocks will be inserted immediately after the current one.
8294 MachineFunction::iterator BBI = W.MBB;
8297 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8298 // we can branch to its destination directly if it's squeezed exactly in
8299 // between the known lower bound and Pivot - 1.
8300 MachineBasicBlock *LeftMBB;
8301 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8302 FirstLeft->Low == W.GE &&
8303 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8304 LeftMBB = FirstLeft->MBB;
8306 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8307 FuncInfo.MF->insert(BBI, LeftMBB);
8309 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8310 // Put Cond in a virtual register to make it available from the new blocks.
8311 ExportFromCurrentBlock(Cond);
8314 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8315 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8316 // directly if RHS.High equals the current upper bound.
8317 MachineBasicBlock *RightMBB;
8318 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8319 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8320 RightMBB = FirstRight->MBB;
8322 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8323 FuncInfo.MF->insert(BBI, RightMBB);
8325 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8326 // Put Cond in a virtual register to make it available from the new blocks.
8327 ExportFromCurrentBlock(Cond);
8330 // Create the CaseBlock record that will be used to lower the branch.
8331 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8332 LeftWeight, RightWeight);
8334 if (W.MBB == SwitchMBB)
8335 visitSwitchCase(CB, SwitchMBB);
8337 SwitchCases.push_back(CB);
8340 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8341 // Extract cases from the switch.
8342 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8343 CaseClusterVector Clusters;
8344 Clusters.reserve(SI.getNumCases());
8345 for (auto I : SI.cases()) {
8346 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8347 const ConstantInt *CaseVal = I.getCaseValue();
8349 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8350 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8353 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8355 // Cluster adjacent cases with the same destination. We do this at all
8356 // optimization levels because it's cheap to do and will make codegen faster
8357 // if there are many clusters.
8358 sortAndRangeify(Clusters);
8360 if (TM.getOptLevel() != CodeGenOpt::None) {
8361 // Replace an unreachable default with the most popular destination.
8362 // FIXME: Exploit unreachable default more aggressively.
8363 bool UnreachableDefault =
8364 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8365 if (UnreachableDefault && !Clusters.empty()) {
8366 DenseMap<const BasicBlock *, unsigned> Popularity;
8367 unsigned MaxPop = 0;
8368 const BasicBlock *MaxBB = nullptr;
8369 for (auto I : SI.cases()) {
8370 const BasicBlock *BB = I.getCaseSuccessor();
8371 if (++Popularity[BB] > MaxPop) {
8372 MaxPop = Popularity[BB];
8377 assert(MaxPop > 0 && MaxBB);
8378 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8380 // Remove cases that were pointing to the destination that is now the
8382 CaseClusterVector New;
8383 New.reserve(Clusters.size());
8384 for (CaseCluster &CC : Clusters) {
8385 if (CC.MBB != DefaultMBB)
8388 Clusters = std::move(New);
8392 // If there is only the default destination, jump there directly.
8393 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8394 if (Clusters.empty()) {
8395 SwitchMBB->addSuccessor(DefaultMBB);
8396 if (DefaultMBB != NextBlock(SwitchMBB)) {
8397 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8398 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8403 findJumpTables(Clusters, &SI, DefaultMBB);
8404 findBitTestClusters(Clusters, &SI);
8407 dbgs() << "Case clusters: ";
8408 for (const CaseCluster &C : Clusters) {
8409 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8410 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8412 C.Low->getValue().print(dbgs(), true);
8413 if (C.Low != C.High) {
8415 C.High->getValue().print(dbgs(), true);
8422 assert(!Clusters.empty());
8423 SwitchWorkList WorkList;
8424 CaseClusterIt First = Clusters.begin();
8425 CaseClusterIt Last = Clusters.end() - 1;
8426 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8427 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8429 while (!WorkList.empty()) {
8430 SwitchWorkListItem W = WorkList.back();
8431 WorkList.pop_back();
8432 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8434 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8435 // For optimized builds, lower large range as a balanced binary tree.
8436 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8440 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);