1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/FastISel.h"
34 #include "llvm/CodeGen/GCStrategy.h"
35 #include "llvm/CodeGen/GCMetadata.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineModuleInfo.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/Analysis/DebugInfo.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
73 /// RegsForValue - This struct represents the registers (physical or virtual)
74 /// that a particular set of values is assigned, and the type information
75 /// about the value. The most common situation is to represent one value at a
76 /// time, but struct or array values are handled element-wise as multiple
77 /// values. The splitting of aggregates is performed recursively, so that we
78 /// never have aggregate-typed registers. The values at this point do not
79 /// necessarily have legal types, so each value may require one or more
80 /// registers of some legal type.
83 /// TLI - The TargetLowering object.
85 const TargetLowering *TLI;
87 /// ValueVTs - The value types of the values, which may not be legal, and
88 /// may need be promoted or synthesized from one or more registers.
90 SmallVector<EVT, 4> ValueVTs;
92 /// RegVTs - The value types of the registers. This is the same size as
93 /// ValueVTs and it records, for each value, what the type of the assigned
94 /// register or registers are. (Individual values are never synthesized
95 /// from more than one type of register.)
97 /// With virtual registers, the contents of RegVTs is redundant with TLI's
98 /// getRegisterType member function, however when with physical registers
99 /// it is necessary to have a separate record of the types.
101 SmallVector<EVT, 4> RegVTs;
103 /// Regs - This list holds the registers assigned to the values.
104 /// Each legal or promoted value requires one register, and each
105 /// expanded value requires multiple registers.
107 SmallVector<unsigned, 4> Regs;
109 RegsForValue() : TLI(0) {}
111 RegsForValue(const TargetLowering &tli,
112 const SmallVector<unsigned, 4> ®s,
113 EVT regvt, EVT valuevt)
114 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
115 RegsForValue(const TargetLowering &tli,
116 const SmallVector<unsigned, 4> ®s,
117 const SmallVector<EVT, 4> ®vts,
118 const SmallVector<EVT, 4> &valuevts)
119 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
120 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
121 unsigned Reg, const Type *Ty) : TLI(&tli) {
122 ComputeValueVTs(tli, Ty, ValueVTs);
124 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
125 EVT ValueVT = ValueVTs[Value];
126 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
127 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
128 for (unsigned i = 0; i != NumRegs; ++i)
129 Regs.push_back(Reg + i);
130 RegVTs.push_back(RegisterVT);
135 /// areValueTypesLegal - Return true if types of all the values are legal.
136 bool areValueTypesLegal() {
137 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
138 EVT RegisterVT = RegVTs[Value];
139 if (!TLI->isTypeLegal(RegisterVT))
146 /// append - Add the specified values to this one.
147 void append(const RegsForValue &RHS) {
149 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
150 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
151 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
155 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
156 /// this value and returns the result as a ValueVTs value. This uses
157 /// Chain/Flag as the input and updates them for the output Chain/Flag.
158 /// If the Flag pointer is NULL, no flag is used.
159 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
160 SDValue &Chain, SDValue *Flag) const;
162 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
163 /// specified value into the registers specified by this object. This uses
164 /// Chain/Flag as the input and updates them for the output Chain/Flag.
165 /// If the Flag pointer is NULL, no flag is used.
166 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
167 SDValue &Chain, SDValue *Flag) const;
169 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
170 /// operand list. This adds the code marker, matching input operand index
171 /// (if applicable), and includes the number of values added into it.
172 void AddInlineAsmOperands(unsigned Kind,
173 bool HasMatching, unsigned MatchingIdx,
175 std::vector<SDValue> &Ops) const;
179 /// getCopyFromParts - Create a value that contains the specified legal parts
180 /// combined into the value they represent. If the parts combine to a type
181 /// larger then ValueVT then AssertOp can be used to specify whether the extra
182 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
183 /// (ISD::AssertSext).
184 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
185 const SDValue *Parts,
186 unsigned NumParts, EVT PartVT, EVT ValueVT,
187 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
188 assert(NumParts > 0 && "No parts to assemble!");
189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
190 SDValue Val = Parts[0];
193 // Assemble the value from multiple parts.
194 if (!ValueVT.isVector() && ValueVT.isInteger()) {
195 unsigned PartBits = PartVT.getSizeInBits();
196 unsigned ValueBits = ValueVT.getSizeInBits();
198 // Assemble the power of 2 part.
199 unsigned RoundParts = NumParts & (NumParts - 1) ?
200 1 << Log2_32(NumParts) : NumParts;
201 unsigned RoundBits = PartBits * RoundParts;
202 EVT RoundVT = RoundBits == ValueBits ?
203 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
206 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
208 if (RoundParts > 2) {
209 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
211 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
212 RoundParts / 2, PartVT, HalfVT);
214 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
215 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
218 if (TLI.isBigEndian())
221 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
223 if (RoundParts < NumParts) {
224 // Assemble the trailing non-power-of-2 part.
225 unsigned OddParts = NumParts - RoundParts;
226 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
227 Hi = getCopyFromParts(DAG, dl,
228 Parts + RoundParts, OddParts, PartVT, OddVT);
230 // Combine the round and odd parts.
232 if (TLI.isBigEndian())
234 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
235 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
236 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
237 DAG.getConstant(Lo.getValueType().getSizeInBits(),
238 TLI.getPointerTy()));
239 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
240 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
242 } else if (ValueVT.isVector()) {
243 // Handle a multi-element vector.
244 EVT IntermediateVT, RegisterVT;
245 unsigned NumIntermediates;
247 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
248 NumIntermediates, RegisterVT);
249 assert(NumRegs == NumParts
250 && "Part count doesn't match vector breakdown!");
251 NumParts = NumRegs; // Silence a compiler warning.
252 assert(RegisterVT == PartVT
253 && "Part type doesn't match vector breakdown!");
254 assert(RegisterVT == Parts[0].getValueType() &&
255 "Part type doesn't match part!");
257 // Assemble the parts into intermediate operands.
258 SmallVector<SDValue, 8> Ops(NumIntermediates);
259 if (NumIntermediates == NumParts) {
260 // If the register was not expanded, truncate or copy the value,
262 for (unsigned i = 0; i != NumParts; ++i)
263 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
264 PartVT, IntermediateVT);
265 } else if (NumParts > 0) {
266 // If the intermediate type was expanded, build the intermediate
267 // operands from the parts.
268 assert(NumParts % NumIntermediates == 0 &&
269 "Must expand into a divisible number of parts!");
270 unsigned Factor = NumParts / NumIntermediates;
271 for (unsigned i = 0; i != NumIntermediates; ++i)
272 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
273 PartVT, IntermediateVT);
276 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
277 // intermediate operands.
278 Val = DAG.getNode(IntermediateVT.isVector() ?
279 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
280 ValueVT, &Ops[0], NumIntermediates);
281 } else if (PartVT.isFloatingPoint()) {
282 // FP split into multiple FP parts (for ppcf128)
283 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
286 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
287 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
288 if (TLI.isBigEndian())
290 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
292 // FP split into integer parts (soft fp)
293 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
294 !PartVT.isVector() && "Unexpected split");
295 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
296 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
300 // There is now one part, held in Val. Correct it to match ValueVT.
301 PartVT = Val.getValueType();
303 if (PartVT == ValueVT)
306 if (PartVT.isVector()) {
307 assert(ValueVT.isVector() && "Unknown vector conversion!");
308 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
311 if (ValueVT.isVector()) {
312 assert(ValueVT.getVectorElementType() == PartVT &&
313 ValueVT.getVectorNumElements() == 1 &&
314 "Only trivial scalar-to-vector conversions should get here!");
315 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
318 if (PartVT.isInteger() &&
319 ValueVT.isInteger()) {
320 if (ValueVT.bitsLT(PartVT)) {
321 // For a truncate, see if we have any information to
322 // indicate whether the truncated bits will always be
323 // zero or sign-extension.
324 if (AssertOp != ISD::DELETED_NODE)
325 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
326 DAG.getValueType(ValueVT));
327 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
329 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
333 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
334 if (ValueVT.bitsLT(Val.getValueType())) {
335 // FP_ROUND's are always exact here.
336 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
337 DAG.getIntPtrConstant(1));
340 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
343 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
344 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
346 llvm_unreachable("Unknown mismatch!");
350 /// getCopyToParts - Create a series of nodes that contain the specified value
351 /// split into legal parts. If the parts contain more bits than Val, then, for
352 /// integers, ExtendKind can be used to specify how to generate the extra bits.
353 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl,
354 SDValue Val, SDValue *Parts, unsigned NumParts,
356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 EVT PtrVT = TLI.getPointerTy();
359 EVT ValueVT = Val.getValueType();
360 unsigned PartBits = PartVT.getSizeInBits();
361 unsigned OrigNumParts = NumParts;
362 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
367 if (!ValueVT.isVector()) {
368 if (PartVT == ValueVT) {
369 assert(NumParts == 1 && "No-op copy with multiple parts!");
374 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
375 // If the parts cover more bits than the value has, promote the value.
376 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
377 assert(NumParts == 1 && "Do not know what to promote to!");
378 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
379 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
380 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
381 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
383 llvm_unreachable("Unknown mismatch!");
385 } else if (PartBits == ValueVT.getSizeInBits()) {
386 // Different types of the same size.
387 assert(NumParts == 1 && PartVT != ValueVT);
388 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
389 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
390 // If the parts cover less bits than value has, truncate the value.
391 if (PartVT.isInteger() && ValueVT.isInteger()) {
392 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
393 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
395 llvm_unreachable("Unknown mismatch!");
399 // The value may have changed - recompute ValueVT.
400 ValueVT = Val.getValueType();
401 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
402 "Failed to tile the value with PartVT!");
405 assert(PartVT == ValueVT && "Type conversion failed!");
410 // Expand the value into multiple parts.
411 if (NumParts & (NumParts - 1)) {
412 // The number of parts is not a power of 2. Split off and copy the tail.
413 assert(PartVT.isInteger() && ValueVT.isInteger() &&
414 "Do not know what to expand to!");
415 unsigned RoundParts = 1 << Log2_32(NumParts);
416 unsigned RoundBits = RoundParts * PartBits;
417 unsigned OddParts = NumParts - RoundParts;
418 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
419 DAG.getConstant(RoundBits,
420 TLI.getPointerTy()));
421 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts,
424 if (TLI.isBigEndian())
425 // The odd parts were reversed by getCopyToParts - unreverse them.
426 std::reverse(Parts + RoundParts, Parts + NumParts);
428 NumParts = RoundParts;
429 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
430 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
433 // The number of parts is a power of 2. Repeatedly bisect the value using
435 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
436 EVT::getIntegerVT(*DAG.getContext(),
437 ValueVT.getSizeInBits()),
440 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
441 for (unsigned i = 0; i < NumParts; i += StepSize) {
442 unsigned ThisBits = StepSize * PartBits / 2;
443 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
444 SDValue &Part0 = Parts[i];
445 SDValue &Part1 = Parts[i+StepSize/2];
447 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
449 DAG.getConstant(1, PtrVT));
450 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
452 DAG.getConstant(0, PtrVT));
454 if (ThisBits == PartBits && ThisVT != PartVT) {
455 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
457 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
471 if (PartVT != ValueVT) {
472 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
473 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
475 assert(ValueVT.getVectorElementType() == PartVT &&
476 ValueVT.getVectorNumElements() == 1 &&
477 "Only trivial vector-to-scalar conversions should get here!");
478 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
480 DAG.getConstant(0, PtrVT));
488 // Handle a multi-element vector.
489 EVT IntermediateVT, RegisterVT;
490 unsigned NumIntermediates;
491 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
492 IntermediateVT, NumIntermediates, RegisterVT);
493 unsigned NumElements = ValueVT.getVectorNumElements();
495 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
496 NumParts = NumRegs; // Silence a compiler warning.
497 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
499 // Split the vector into intermediate operands.
500 SmallVector<SDValue, 8> Ops(NumIntermediates);
501 for (unsigned i = 0; i != NumIntermediates; ++i) {
502 if (IntermediateVT.isVector())
503 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
505 DAG.getConstant(i * (NumElements / NumIntermediates),
508 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
510 DAG.getConstant(i, PtrVT));
513 // Split the intermediate operands into legal parts.
514 if (NumParts == NumIntermediates) {
515 // If the register was not expanded, promote or copy the value,
517 for (unsigned i = 0; i != NumParts; ++i)
518 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
519 } else if (NumParts > 0) {
520 // If the intermediate type was expanded, split each the value into
522 assert(NumParts % NumIntermediates == 0 &&
523 "Must expand into a divisible number of parts!");
524 unsigned Factor = NumParts / NumIntermediates;
525 for (unsigned i = 0; i != NumIntermediates; ++i)
526 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT);
531 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
534 TD = DAG.getTarget().getTargetData();
537 /// clear - Clear out the current SelectionDAG and the associated
538 /// state and prepare this SelectionDAGBuilder object to be used
539 /// for a new block. This doesn't clear out information about
540 /// additional blocks that are needed to complete switch lowering
541 /// or PHI node updating; that information is cleared out as it is
543 void SelectionDAGBuilder::clear() {
545 PendingLoads.clear();
546 PendingExports.clear();
549 CurDebugLoc = DebugLoc();
553 /// getRoot - Return the current virtual root of the Selection DAG,
554 /// flushing any PendingLoad items. This must be done before emitting
555 /// a store or any other node that may need to be ordered after any
556 /// prior load instructions.
558 SDValue SelectionDAGBuilder::getRoot() {
559 if (PendingLoads.empty())
560 return DAG.getRoot();
562 if (PendingLoads.size() == 1) {
563 SDValue Root = PendingLoads[0];
565 PendingLoads.clear();
569 // Otherwise, we have to make a token factor node.
570 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
571 &PendingLoads[0], PendingLoads.size());
572 PendingLoads.clear();
577 /// getControlRoot - Similar to getRoot, but instead of flushing all the
578 /// PendingLoad items, flush all the PendingExports items. It is necessary
579 /// to do this before emitting a terminator instruction.
581 SDValue SelectionDAGBuilder::getControlRoot() {
582 SDValue Root = DAG.getRoot();
584 if (PendingExports.empty())
587 // Turn all of the CopyToReg chains into one factored node.
588 if (Root.getOpcode() != ISD::EntryToken) {
589 unsigned i = 0, e = PendingExports.size();
590 for (; i != e; ++i) {
591 assert(PendingExports[i].getNode()->getNumOperands() > 1);
592 if (PendingExports[i].getNode()->getOperand(0) == Root)
593 break; // Don't add the root if we already indirectly depend on it.
597 PendingExports.push_back(Root);
600 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
602 PendingExports.size());
603 PendingExports.clear();
608 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
609 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
610 DAG.AssignOrdering(Node, SDNodeOrder);
612 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
613 AssignOrderingToNode(Node->getOperand(I).getNode());
616 void SelectionDAGBuilder::visit(const Instruction &I) {
617 visit(I.getOpcode(), I);
620 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
621 // Note: this doesn't use InstVisitor, because it has to work with
622 // ConstantExpr's in addition to instructions.
624 default: llvm_unreachable("Unknown instruction type encountered!");
625 // Build the switch statement using the Instruction.def file.
626 #define HANDLE_INST(NUM, OPCODE, CLASS) \
627 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
628 #include "llvm/Instruction.def"
631 // Assign the ordering to the freshly created DAG nodes.
632 if (NodeMap.count(&I)) {
634 AssignOrderingToNode(getValue(&I).getNode());
638 SDValue SelectionDAGBuilder::getValue(const Value *V) {
639 SDValue &N = NodeMap[V];
640 if (N.getNode()) return N;
642 if (const Constant *C = dyn_cast<Constant>(V)) {
643 EVT VT = TLI.getValueType(V->getType(), true);
645 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
646 return N = DAG.getConstant(*CI, VT);
648 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
649 return N = DAG.getGlobalAddress(GV, VT);
651 if (isa<ConstantPointerNull>(C))
652 return N = DAG.getConstant(0, TLI.getPointerTy());
654 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
655 return N = DAG.getConstantFP(*CFP, VT);
657 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
658 return N = DAG.getUNDEF(VT);
660 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
661 visit(CE->getOpcode(), *CE);
662 SDValue N1 = NodeMap[V];
663 assert(N1.getNode() && "visit didn't populate the NodeMap!");
667 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
668 SmallVector<SDValue, 4> Constants;
669 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
671 SDNode *Val = getValue(*OI).getNode();
672 // If the operand is an empty aggregate, there are no values.
674 // Add each leaf value from the operand to the Constants list
675 // to form a flattened list of all the values.
676 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
677 Constants.push_back(SDValue(Val, i));
680 return DAG.getMergeValues(&Constants[0], Constants.size(),
684 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
685 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
686 "Unknown struct or array constant!");
688 SmallVector<EVT, 4> ValueVTs;
689 ComputeValueVTs(TLI, C->getType(), ValueVTs);
690 unsigned NumElts = ValueVTs.size();
692 return SDValue(); // empty struct
693 SmallVector<SDValue, 4> Constants(NumElts);
694 for (unsigned i = 0; i != NumElts; ++i) {
695 EVT EltVT = ValueVTs[i];
696 if (isa<UndefValue>(C))
697 Constants[i] = DAG.getUNDEF(EltVT);
698 else if (EltVT.isFloatingPoint())
699 Constants[i] = DAG.getConstantFP(0, EltVT);
701 Constants[i] = DAG.getConstant(0, EltVT);
704 return DAG.getMergeValues(&Constants[0], NumElts,
708 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
709 return DAG.getBlockAddress(BA, VT);
711 const VectorType *VecTy = cast<VectorType>(V->getType());
712 unsigned NumElements = VecTy->getNumElements();
714 // Now that we know the number and type of the elements, get that number of
715 // elements into the Ops array based on what kind of constant it is.
716 SmallVector<SDValue, 16> Ops;
717 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
718 for (unsigned i = 0; i != NumElements; ++i)
719 Ops.push_back(getValue(CP->getOperand(i)));
721 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
722 EVT EltVT = TLI.getValueType(VecTy->getElementType());
725 if (EltVT.isFloatingPoint())
726 Op = DAG.getConstantFP(0, EltVT);
728 Op = DAG.getConstant(0, EltVT);
729 Ops.assign(NumElements, Op);
732 // Create a BUILD_VECTOR node.
733 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
734 VT, &Ops[0], Ops.size());
737 // If this is a static alloca, generate it as the frameindex instead of
739 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
740 DenseMap<const AllocaInst*, int>::iterator SI =
741 FuncInfo.StaticAllocaMap.find(AI);
742 if (SI != FuncInfo.StaticAllocaMap.end())
743 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
746 unsigned InReg = FuncInfo.ValueMap[V];
747 assert(InReg && "Value not in map!");
749 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
750 SDValue Chain = DAG.getEntryNode();
751 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
754 /// Get the EVTs and ArgFlags collections that represent the legalized return
755 /// type of the given function. This does not require a DAG or a return value,
756 /// and is suitable for use before any DAGs for the function are constructed.
757 static void getReturnInfo(const Type* ReturnType,
758 Attributes attr, SmallVectorImpl<EVT> &OutVTs,
759 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
760 const TargetLowering &TLI,
761 SmallVectorImpl<uint64_t> *Offsets = 0) {
762 SmallVector<EVT, 4> ValueVTs;
763 ComputeValueVTs(TLI, ReturnType, ValueVTs);
764 unsigned NumValues = ValueVTs.size();
765 if (NumValues == 0) return;
768 for (unsigned j = 0, f = NumValues; j != f; ++j) {
769 EVT VT = ValueVTs[j];
770 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
772 if (attr & Attribute::SExt)
773 ExtendKind = ISD::SIGN_EXTEND;
774 else if (attr & Attribute::ZExt)
775 ExtendKind = ISD::ZERO_EXTEND;
777 // FIXME: C calling convention requires the return type to be promoted to
778 // at least 32-bit. But this is not necessary for non-C calling
779 // conventions. The frontend should mark functions whose return values
780 // require promoting with signext or zeroext attributes.
781 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
782 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
783 if (VT.bitsLT(MinVT))
787 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
788 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
789 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
790 PartVT.getTypeForEVT(ReturnType->getContext()));
792 // 'inreg' on function refers to return value
793 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
794 if (attr & Attribute::InReg)
797 // Propagate extension type if any
798 if (attr & Attribute::SExt)
800 else if (attr & Attribute::ZExt)
803 for (unsigned i = 0; i < NumParts; ++i) {
804 OutVTs.push_back(PartVT);
805 OutFlags.push_back(Flags);
808 Offsets->push_back(Offset);
815 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
816 SDValue Chain = getControlRoot();
817 SmallVector<ISD::OutputArg, 8> Outs;
818 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
820 if (!FLI.CanLowerReturn) {
821 unsigned DemoteReg = FLI.DemoteRegister;
822 const Function *F = I.getParent()->getParent();
824 // Emit a store of the return value through the virtual register.
825 // Leave Outs empty so that LowerReturn won't try to load return
826 // registers the usual way.
827 SmallVector<EVT, 1> PtrValueVTs;
828 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
831 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
832 SDValue RetOp = getValue(I.getOperand(0));
834 SmallVector<EVT, 4> ValueVTs;
835 SmallVector<uint64_t, 4> Offsets;
836 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
837 unsigned NumValues = ValueVTs.size();
839 SmallVector<SDValue, 4> Chains(NumValues);
840 EVT PtrVT = PtrValueVTs[0];
841 for (unsigned i = 0; i != NumValues; ++i) {
842 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
843 DAG.getConstant(Offsets[i], PtrVT));
845 DAG.getStore(Chain, getCurDebugLoc(),
846 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
847 Add, NULL, Offsets[i], false, false, 0);
850 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
851 MVT::Other, &Chains[0], NumValues);
852 } else if (I.getNumOperands() != 0) {
853 SmallVector<EVT, 4> ValueVTs;
854 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
855 unsigned NumValues = ValueVTs.size();
857 SDValue RetOp = getValue(I.getOperand(0));
858 for (unsigned j = 0, f = NumValues; j != f; ++j) {
859 EVT VT = ValueVTs[j];
861 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
863 const Function *F = I.getParent()->getParent();
864 if (F->paramHasAttr(0, Attribute::SExt))
865 ExtendKind = ISD::SIGN_EXTEND;
866 else if (F->paramHasAttr(0, Attribute::ZExt))
867 ExtendKind = ISD::ZERO_EXTEND;
869 // FIXME: C calling convention requires the return type to be promoted
870 // to at least 32-bit. But this is not necessary for non-C calling
871 // conventions. The frontend should mark functions whose return values
872 // require promoting with signext or zeroext attributes.
873 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
874 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
875 if (VT.bitsLT(MinVT))
879 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
880 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
881 SmallVector<SDValue, 4> Parts(NumParts);
882 getCopyToParts(DAG, getCurDebugLoc(),
883 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
884 &Parts[0], NumParts, PartVT, ExtendKind);
886 // 'inreg' on function refers to return value
887 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
888 if (F->paramHasAttr(0, Attribute::InReg))
891 // Propagate extension type if any
892 if (F->paramHasAttr(0, Attribute::SExt))
894 else if (F->paramHasAttr(0, Attribute::ZExt))
897 for (unsigned i = 0; i < NumParts; ++i)
898 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
903 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
904 CallingConv::ID CallConv =
905 DAG.getMachineFunction().getFunction()->getCallingConv();
906 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
907 Outs, getCurDebugLoc(), DAG);
909 // Verify that the target's LowerReturn behaved as expected.
910 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
911 "LowerReturn didn't return a valid chain!");
913 // Update the DAG with the new chain value resulting from return lowering.
917 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
918 /// created for it, emit nodes to copy the value into the virtual
920 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
921 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
922 if (VMI != FuncInfo.ValueMap.end()) {
923 assert(!V->use_empty() && "Unused value assigned virtual registers!");
924 CopyValueToVirtualRegister(V, VMI->second);
928 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
929 /// the current basic block, add it to ValueMap now so that we'll get a
931 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
932 // No need to export constants.
933 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
936 if (FuncInfo.isExportedInst(V)) return;
938 unsigned Reg = FuncInfo.InitializeRegForValue(V);
939 CopyValueToVirtualRegister(V, Reg);
942 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
943 const BasicBlock *FromBB) {
944 // The operands of the setcc have to be in this block. We don't know
945 // how to export them from some other block.
946 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
947 // Can export from current BB.
948 if (VI->getParent() == FromBB)
951 // Is already exported, noop.
952 return FuncInfo.isExportedInst(V);
955 // If this is an argument, we can export it if the BB is the entry block or
956 // if it is already exported.
957 if (isa<Argument>(V)) {
958 if (FromBB == &FromBB->getParent()->getEntryBlock())
961 // Otherwise, can only export this if it is already exported.
962 return FuncInfo.isExportedInst(V);
965 // Otherwise, constants can always be exported.
969 static bool InBlock(const Value *V, const BasicBlock *BB) {
970 if (const Instruction *I = dyn_cast<Instruction>(V))
971 return I->getParent() == BB;
975 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
976 /// This function emits a branch and is used at the leaves of an OR or an
977 /// AND operator tree.
980 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
981 MachineBasicBlock *TBB,
982 MachineBasicBlock *FBB,
983 MachineBasicBlock *CurBB) {
984 const BasicBlock *BB = CurBB->getBasicBlock();
986 // If the leaf of the tree is a comparison, merge the condition into
988 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
989 // The operands of the cmp have to be in this block. We don't know
990 // how to export them from some other block. If this is the first block
991 // of the sequence, no exporting is needed.
992 if (CurBB == CurMBB ||
993 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
994 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
995 ISD::CondCode Condition;
996 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
997 Condition = getICmpCondCode(IC->getPredicate());
998 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
999 Condition = getFCmpCondCode(FC->getPredicate());
1001 Condition = ISD::SETEQ; // silence warning.
1002 llvm_unreachable("Unknown compare instruction");
1005 CaseBlock CB(Condition, BOp->getOperand(0),
1006 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1007 SwitchCases.push_back(CB);
1012 // Create a CaseBlock record representing this branch.
1013 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1014 NULL, TBB, FBB, CurBB);
1015 SwitchCases.push_back(CB);
1018 /// FindMergedConditions - If Cond is an expression like
1019 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1020 MachineBasicBlock *TBB,
1021 MachineBasicBlock *FBB,
1022 MachineBasicBlock *CurBB,
1024 // If this node is not part of the or/and tree, emit it as a branch.
1025 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1026 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1027 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1028 BOp->getParent() != CurBB->getBasicBlock() ||
1029 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1030 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1031 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1035 // Create TmpBB after CurBB.
1036 MachineFunction::iterator BBI = CurBB;
1037 MachineFunction &MF = DAG.getMachineFunction();
1038 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1039 CurBB->getParent()->insert(++BBI, TmpBB);
1041 if (Opc == Instruction::Or) {
1042 // Codegen X | Y as:
1050 // Emit the LHS condition.
1051 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1053 // Emit the RHS condition into TmpBB.
1054 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1056 assert(Opc == Instruction::And && "Unknown merge op!");
1057 // Codegen X & Y as:
1064 // This requires creation of TmpBB after CurBB.
1066 // Emit the LHS condition.
1067 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1069 // Emit the RHS condition into TmpBB.
1070 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1074 /// If the set of cases should be emitted as a series of branches, return true.
1075 /// If we should emit this as a bunch of and/or'd together conditions, return
1078 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1079 if (Cases.size() != 2) return true;
1081 // If this is two comparisons of the same values or'd or and'd together, they
1082 // will get folded into a single comparison, so don't emit two blocks.
1083 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1084 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1085 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1086 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1090 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1091 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1092 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1093 Cases[0].CC == Cases[1].CC &&
1094 isa<Constant>(Cases[0].CmpRHS) &&
1095 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1096 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1098 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1105 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1106 // Update machine-CFG edges.
1107 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1109 // Figure out which block is immediately after the current one.
1110 MachineBasicBlock *NextBlock = 0;
1111 MachineFunction::iterator BBI = CurMBB;
1112 if (++BBI != FuncInfo.MF->end())
1115 if (I.isUnconditional()) {
1116 // Update machine-CFG edges.
1117 CurMBB->addSuccessor(Succ0MBB);
1119 // If this is not a fall-through branch, emit the branch.
1120 if (Succ0MBB != NextBlock)
1121 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1122 MVT::Other, getControlRoot(),
1123 DAG.getBasicBlock(Succ0MBB)));
1128 // If this condition is one of the special cases we handle, do special stuff
1130 const Value *CondVal = I.getCondition();
1131 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1133 // If this is a series of conditions that are or'd or and'd together, emit
1134 // this as a sequence of branches instead of setcc's with and/or operations.
1135 // For example, instead of something like:
1148 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1149 if (BOp->hasOneUse() &&
1150 (BOp->getOpcode() == Instruction::And ||
1151 BOp->getOpcode() == Instruction::Or)) {
1152 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1153 // If the compares in later blocks need to use values not currently
1154 // exported from this block, export them now. This block should always
1155 // be the first entry.
1156 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1158 // Allow some cases to be rejected.
1159 if (ShouldEmitAsBranches(SwitchCases)) {
1160 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1161 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1162 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1165 // Emit the branch for this block.
1166 visitSwitchCase(SwitchCases[0]);
1167 SwitchCases.erase(SwitchCases.begin());
1171 // Okay, we decided not to do this, remove any inserted MBB's and clear
1173 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1174 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1176 SwitchCases.clear();
1180 // Create a CaseBlock record representing this branch.
1181 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1182 NULL, Succ0MBB, Succ1MBB, CurMBB);
1184 // Use visitSwitchCase to actually insert the fast branch sequence for this
1186 visitSwitchCase(CB);
1189 /// visitSwitchCase - Emits the necessary code to represent a single node in
1190 /// the binary search tree resulting from lowering a switch instruction.
1191 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
1193 SDValue CondLHS = getValue(CB.CmpLHS);
1194 DebugLoc dl = getCurDebugLoc();
1196 // Build the setcc now.
1197 if (CB.CmpMHS == NULL) {
1198 // Fold "(X == true)" to X and "(X == false)" to !X to
1199 // handle common cases produced by branch lowering.
1200 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1201 CB.CC == ISD::SETEQ)
1203 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1204 CB.CC == ISD::SETEQ) {
1205 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1206 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1208 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1210 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1212 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1213 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1215 SDValue CmpOp = getValue(CB.CmpMHS);
1216 EVT VT = CmpOp.getValueType();
1218 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1219 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1222 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1223 VT, CmpOp, DAG.getConstant(Low, VT));
1224 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1225 DAG.getConstant(High-Low, VT), ISD::SETULE);
1229 // Update successor info
1230 CurMBB->addSuccessor(CB.TrueBB);
1231 CurMBB->addSuccessor(CB.FalseBB);
1233 // Set NextBlock to be the MBB immediately after the current one, if any.
1234 // This is used to avoid emitting unnecessary branches to the next block.
1235 MachineBasicBlock *NextBlock = 0;
1236 MachineFunction::iterator BBI = CurMBB;
1237 if (++BBI != FuncInfo.MF->end())
1240 // If the lhs block is the next block, invert the condition so that we can
1241 // fall through to the lhs instead of the rhs block.
1242 if (CB.TrueBB == NextBlock) {
1243 std::swap(CB.TrueBB, CB.FalseBB);
1244 SDValue True = DAG.getConstant(1, Cond.getValueType());
1245 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1248 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1249 MVT::Other, getControlRoot(), Cond,
1250 DAG.getBasicBlock(CB.TrueBB));
1252 // If the branch was constant folded, fix up the CFG.
1253 if (BrCond.getOpcode() == ISD::BR) {
1254 CurMBB->removeSuccessor(CB.FalseBB);
1256 // Otherwise, go ahead and insert the false branch.
1257 if (BrCond == getControlRoot())
1258 CurMBB->removeSuccessor(CB.TrueBB);
1260 if (CB.FalseBB != NextBlock)
1261 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1262 DAG.getBasicBlock(CB.FalseBB));
1265 DAG.setRoot(BrCond);
1268 /// visitJumpTable - Emit JumpTable node in the current MBB
1269 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1270 // Emit the code for the jump table
1271 assert(JT.Reg != -1U && "Should lower JT Header first!");
1272 EVT PTy = TLI.getPointerTy();
1273 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1275 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1276 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1277 MVT::Other, Index.getValue(1),
1279 DAG.setRoot(BrJumpTable);
1282 /// visitJumpTableHeader - This function emits necessary code to produce index
1283 /// in the JumpTable from switch case.
1284 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1285 JumpTableHeader &JTH) {
1286 // Subtract the lowest switch case value from the value being switched on and
1287 // conditional branch to default mbb if the result is greater than the
1288 // difference between smallest and largest cases.
1289 SDValue SwitchOp = getValue(JTH.SValue);
1290 EVT VT = SwitchOp.getValueType();
1291 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1292 DAG.getConstant(JTH.First, VT));
1294 // The SDNode we just created, which holds the value being switched on minus
1295 // the smallest case value, needs to be copied to a virtual register so it
1296 // can be used as an index into the jump table in a subsequent basic block.
1297 // This value may be smaller or larger than the target's pointer type, and
1298 // therefore require extension or truncating.
1299 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1301 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1302 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1303 JumpTableReg, SwitchOp);
1304 JT.Reg = JumpTableReg;
1306 // Emit the range check for the jump table, and branch to the default block
1307 // for the switch statement if the value being switched on exceeds the largest
1308 // case in the switch.
1309 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1310 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1311 DAG.getConstant(JTH.Last-JTH.First,VT),
1314 // Set NextBlock to be the MBB immediately after the current one, if any.
1315 // This is used to avoid emitting unnecessary branches to the next block.
1316 MachineBasicBlock *NextBlock = 0;
1317 MachineFunction::iterator BBI = CurMBB;
1319 if (++BBI != FuncInfo.MF->end())
1322 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1323 MVT::Other, CopyTo, CMP,
1324 DAG.getBasicBlock(JT.Default));
1326 if (JT.MBB != NextBlock)
1327 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1328 DAG.getBasicBlock(JT.MBB));
1330 DAG.setRoot(BrCond);
1333 /// visitBitTestHeader - This function emits necessary code to produce value
1334 /// suitable for "bit tests"
1335 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
1336 // Subtract the minimum value
1337 SDValue SwitchOp = getValue(B.SValue);
1338 EVT VT = SwitchOp.getValueType();
1339 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1340 DAG.getConstant(B.First, VT));
1343 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1344 TLI.getSetCCResultType(Sub.getValueType()),
1345 Sub, DAG.getConstant(B.Range, VT),
1348 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1349 TLI.getPointerTy());
1351 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1352 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1355 // Set NextBlock to be the MBB immediately after the current one, if any.
1356 // This is used to avoid emitting unnecessary branches to the next block.
1357 MachineBasicBlock *NextBlock = 0;
1358 MachineFunction::iterator BBI = CurMBB;
1359 if (++BBI != FuncInfo.MF->end())
1362 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1364 CurMBB->addSuccessor(B.Default);
1365 CurMBB->addSuccessor(MBB);
1367 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1368 MVT::Other, CopyTo, RangeCmp,
1369 DAG.getBasicBlock(B.Default));
1371 if (MBB != NextBlock)
1372 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1373 DAG.getBasicBlock(MBB));
1375 DAG.setRoot(BrRange);
1378 /// visitBitTestCase - this function produces one "bit test"
1379 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1382 // Make desired shift
1383 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1384 TLI.getPointerTy());
1385 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1387 DAG.getConstant(1, TLI.getPointerTy()),
1390 // Emit bit tests and jumps
1391 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1392 TLI.getPointerTy(), SwitchVal,
1393 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1394 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1395 TLI.getSetCCResultType(AndOp.getValueType()),
1396 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1399 CurMBB->addSuccessor(B.TargetBB);
1400 CurMBB->addSuccessor(NextMBB);
1402 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1403 MVT::Other, getControlRoot(),
1404 AndCmp, DAG.getBasicBlock(B.TargetBB));
1406 // Set NextBlock to be the MBB immediately after the current one, if any.
1407 // This is used to avoid emitting unnecessary branches to the next block.
1408 MachineBasicBlock *NextBlock = 0;
1409 MachineFunction::iterator BBI = CurMBB;
1410 if (++BBI != FuncInfo.MF->end())
1413 if (NextMBB != NextBlock)
1414 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1415 DAG.getBasicBlock(NextMBB));
1420 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1421 // Retrieve successors.
1422 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1423 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1425 const Value *Callee(I.getCalledValue());
1426 if (isa<InlineAsm>(Callee))
1429 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1431 // If the value of the invoke is used outside of its defining block, make it
1432 // available as a virtual register.
1433 CopyToExportRegsIfNeeded(&I);
1435 // Update successor info
1436 CurMBB->addSuccessor(Return);
1437 CurMBB->addSuccessor(LandingPad);
1439 // Drop into normal successor.
1440 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1441 MVT::Other, getControlRoot(),
1442 DAG.getBasicBlock(Return)));
1445 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1448 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1449 /// small case ranges).
1450 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1451 CaseRecVector& WorkList,
1453 MachineBasicBlock* Default) {
1454 Case& BackCase = *(CR.Range.second-1);
1456 // Size is the number of Cases represented by this range.
1457 size_t Size = CR.Range.second - CR.Range.first;
1461 // Get the MachineFunction which holds the current MBB. This is used when
1462 // inserting any additional MBBs necessary to represent the switch.
1463 MachineFunction *CurMF = FuncInfo.MF;
1465 // Figure out which block is immediately after the current one.
1466 MachineBasicBlock *NextBlock = 0;
1467 MachineFunction::iterator BBI = CR.CaseBB;
1469 if (++BBI != FuncInfo.MF->end())
1472 // TODO: If any two of the cases has the same destination, and if one value
1473 // is the same as the other, but has one bit unset that the other has set,
1474 // use bit manipulation to do two compares at once. For example:
1475 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1477 // Rearrange the case blocks so that the last one falls through if possible.
1478 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1479 // The last case block won't fall through into 'NextBlock' if we emit the
1480 // branches in this order. See if rearranging a case value would help.
1481 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1482 if (I->BB == NextBlock) {
1483 std::swap(*I, BackCase);
1489 // Create a CaseBlock record representing a conditional branch to
1490 // the Case's target mbb if the value being switched on SV is equal
1492 MachineBasicBlock *CurBlock = CR.CaseBB;
1493 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1494 MachineBasicBlock *FallThrough;
1496 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1497 CurMF->insert(BBI, FallThrough);
1499 // Put SV in a virtual register to make it available from the new blocks.
1500 ExportFromCurrentBlock(SV);
1502 // If the last case doesn't match, go to the default block.
1503 FallThrough = Default;
1506 const Value *RHS, *LHS, *MHS;
1508 if (I->High == I->Low) {
1509 // This is just small small case range :) containing exactly 1 case
1511 LHS = SV; RHS = I->High; MHS = NULL;
1514 LHS = I->Low; MHS = SV; RHS = I->High;
1516 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1518 // If emitting the first comparison, just call visitSwitchCase to emit the
1519 // code into the current block. Otherwise, push the CaseBlock onto the
1520 // vector to be later processed by SDISel, and insert the node's MBB
1521 // before the next MBB.
1522 if (CurBlock == CurMBB)
1523 visitSwitchCase(CB);
1525 SwitchCases.push_back(CB);
1527 CurBlock = FallThrough;
1533 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1534 return !DisableJumpTables &&
1535 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1536 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1539 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1540 APInt LastExt(Last), FirstExt(First);
1541 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1542 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1543 return (LastExt - FirstExt + 1ULL);
1546 /// handleJTSwitchCase - Emit jumptable for current switch case range
1547 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1548 CaseRecVector& WorkList,
1550 MachineBasicBlock* Default) {
1551 Case& FrontCase = *CR.Range.first;
1552 Case& BackCase = *(CR.Range.second-1);
1554 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1555 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1557 APInt TSize(First.getBitWidth(), 0);
1558 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1562 if (!areJTsAllowed(TLI) || TSize.ult(4))
1565 APInt Range = ComputeRange(First, Last);
1566 double Density = TSize.roundToDouble() / Range.roundToDouble();
1570 DEBUG(dbgs() << "Lowering jump table\n"
1571 << "First entry: " << First << ". Last entry: " << Last << '\n'
1572 << "Range: " << Range
1573 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1575 // Get the MachineFunction which holds the current MBB. This is used when
1576 // inserting any additional MBBs necessary to represent the switch.
1577 MachineFunction *CurMF = FuncInfo.MF;
1579 // Figure out which block is immediately after the current one.
1580 MachineFunction::iterator BBI = CR.CaseBB;
1583 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1585 // Create a new basic block to hold the code for loading the address
1586 // of the jump table, and jumping to it. Update successor information;
1587 // we will either branch to the default case for the switch, or the jump
1589 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1590 CurMF->insert(BBI, JumpTableBB);
1591 CR.CaseBB->addSuccessor(Default);
1592 CR.CaseBB->addSuccessor(JumpTableBB);
1594 // Build a vector of destination BBs, corresponding to each target
1595 // of the jump table. If the value of the jump table slot corresponds to
1596 // a case statement, push the case's BB onto the vector, otherwise, push
1598 std::vector<MachineBasicBlock*> DestBBs;
1600 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1601 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1602 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1604 if (Low.sle(TEI) && TEI.sle(High)) {
1605 DestBBs.push_back(I->BB);
1609 DestBBs.push_back(Default);
1613 // Update successor info. Add one edge to each unique successor.
1614 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1615 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1616 E = DestBBs.end(); I != E; ++I) {
1617 if (!SuccsHandled[(*I)->getNumber()]) {
1618 SuccsHandled[(*I)->getNumber()] = true;
1619 JumpTableBB->addSuccessor(*I);
1623 // Create a jump table index for this jump table.
1624 unsigned JTEncoding = TLI.getJumpTableEncoding();
1625 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1626 ->createJumpTableIndex(DestBBs);
1628 // Set the jump table information so that we can codegen it as a second
1629 // MachineBasicBlock
1630 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1631 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1632 if (CR.CaseBB == CurMBB)
1633 visitJumpTableHeader(JT, JTH);
1635 JTCases.push_back(JumpTableBlock(JTH, JT));
1640 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1642 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1643 CaseRecVector& WorkList,
1645 MachineBasicBlock* Default) {
1646 // Get the MachineFunction which holds the current MBB. This is used when
1647 // inserting any additional MBBs necessary to represent the switch.
1648 MachineFunction *CurMF = FuncInfo.MF;
1650 // Figure out which block is immediately after the current one.
1651 MachineFunction::iterator BBI = CR.CaseBB;
1654 Case& FrontCase = *CR.Range.first;
1655 Case& BackCase = *(CR.Range.second-1);
1656 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1658 // Size is the number of Cases represented by this range.
1659 unsigned Size = CR.Range.second - CR.Range.first;
1661 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1662 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1664 CaseItr Pivot = CR.Range.first + Size/2;
1666 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1667 // (heuristically) allow us to emit JumpTable's later.
1668 APInt TSize(First.getBitWidth(), 0);
1669 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1673 APInt LSize = FrontCase.size();
1674 APInt RSize = TSize-LSize;
1675 DEBUG(dbgs() << "Selecting best pivot: \n"
1676 << "First: " << First << ", Last: " << Last <<'\n'
1677 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1678 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1680 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1681 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1682 APInt Range = ComputeRange(LEnd, RBegin);
1683 assert((Range - 2ULL).isNonNegative() &&
1684 "Invalid case distance");
1685 double LDensity = (double)LSize.roundToDouble() /
1686 (LEnd - First + 1ULL).roundToDouble();
1687 double RDensity = (double)RSize.roundToDouble() /
1688 (Last - RBegin + 1ULL).roundToDouble();
1689 double Metric = Range.logBase2()*(LDensity+RDensity);
1690 // Should always split in some non-trivial place
1691 DEBUG(dbgs() <<"=>Step\n"
1692 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1693 << "LDensity: " << LDensity
1694 << ", RDensity: " << RDensity << '\n'
1695 << "Metric: " << Metric << '\n');
1696 if (FMetric < Metric) {
1699 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1705 if (areJTsAllowed(TLI)) {
1706 // If our case is dense we *really* should handle it earlier!
1707 assert((FMetric > 0) && "Should handle dense range earlier!");
1709 Pivot = CR.Range.first + Size/2;
1712 CaseRange LHSR(CR.Range.first, Pivot);
1713 CaseRange RHSR(Pivot, CR.Range.second);
1714 Constant *C = Pivot->Low;
1715 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1717 // We know that we branch to the LHS if the Value being switched on is
1718 // less than the Pivot value, C. We use this to optimize our binary
1719 // tree a bit, by recognizing that if SV is greater than or equal to the
1720 // LHS's Case Value, and that Case Value is exactly one less than the
1721 // Pivot's Value, then we can branch directly to the LHS's Target,
1722 // rather than creating a leaf node for it.
1723 if ((LHSR.second - LHSR.first) == 1 &&
1724 LHSR.first->High == CR.GE &&
1725 cast<ConstantInt>(C)->getValue() ==
1726 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1727 TrueBB = LHSR.first->BB;
1729 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1730 CurMF->insert(BBI, TrueBB);
1731 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1733 // Put SV in a virtual register to make it available from the new blocks.
1734 ExportFromCurrentBlock(SV);
1737 // Similar to the optimization above, if the Value being switched on is
1738 // known to be less than the Constant CR.LT, and the current Case Value
1739 // is CR.LT - 1, then we can branch directly to the target block for
1740 // the current Case Value, rather than emitting a RHS leaf node for it.
1741 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1742 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1743 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1744 FalseBB = RHSR.first->BB;
1746 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1747 CurMF->insert(BBI, FalseBB);
1748 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1750 // Put SV in a virtual register to make it available from the new blocks.
1751 ExportFromCurrentBlock(SV);
1754 // Create a CaseBlock record representing a conditional branch to
1755 // the LHS node if the value being switched on SV is less than C.
1756 // Otherwise, branch to LHS.
1757 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1759 if (CR.CaseBB == CurMBB)
1760 visitSwitchCase(CB);
1762 SwitchCases.push_back(CB);
1767 /// handleBitTestsSwitchCase - if current case range has few destination and
1768 /// range span less, than machine word bitwidth, encode case range into series
1769 /// of masks and emit bit tests with these masks.
1770 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1771 CaseRecVector& WorkList,
1773 MachineBasicBlock* Default){
1774 EVT PTy = TLI.getPointerTy();
1775 unsigned IntPtrBits = PTy.getSizeInBits();
1777 Case& FrontCase = *CR.Range.first;
1778 Case& BackCase = *(CR.Range.second-1);
1780 // Get the MachineFunction which holds the current MBB. This is used when
1781 // inserting any additional MBBs necessary to represent the switch.
1782 MachineFunction *CurMF = FuncInfo.MF;
1784 // If target does not have legal shift left, do not emit bit tests at all.
1785 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1789 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1791 // Single case counts one, case range - two.
1792 numCmps += (I->Low == I->High ? 1 : 2);
1795 // Count unique destinations
1796 SmallSet<MachineBasicBlock*, 4> Dests;
1797 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1798 Dests.insert(I->BB);
1799 if (Dests.size() > 3)
1800 // Don't bother the code below, if there are too much unique destinations
1803 DEBUG(dbgs() << "Total number of unique destinations: "
1804 << Dests.size() << '\n'
1805 << "Total number of comparisons: " << numCmps << '\n');
1807 // Compute span of values.
1808 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1809 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1810 APInt cmpRange = maxValue - minValue;
1812 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
1813 << "Low bound: " << minValue << '\n'
1814 << "High bound: " << maxValue << '\n');
1816 if (cmpRange.uge(IntPtrBits) ||
1817 (!(Dests.size() == 1 && numCmps >= 3) &&
1818 !(Dests.size() == 2 && numCmps >= 5) &&
1819 !(Dests.size() >= 3 && numCmps >= 6)))
1822 DEBUG(dbgs() << "Emitting bit tests\n");
1823 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1825 // Optimize the case where all the case values fit in a
1826 // word without having to subtract minValue. In this case,
1827 // we can optimize away the subtraction.
1828 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
1829 cmpRange = maxValue;
1831 lowBound = minValue;
1834 CaseBitsVector CasesBits;
1835 unsigned i, count = 0;
1837 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1838 MachineBasicBlock* Dest = I->BB;
1839 for (i = 0; i < count; ++i)
1840 if (Dest == CasesBits[i].BB)
1844 assert((count < 3) && "Too much destinations to test!");
1845 CasesBits.push_back(CaseBits(0, Dest, 0));
1849 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1850 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1852 uint64_t lo = (lowValue - lowBound).getZExtValue();
1853 uint64_t hi = (highValue - lowBound).getZExtValue();
1855 for (uint64_t j = lo; j <= hi; j++) {
1856 CasesBits[i].Mask |= 1ULL << j;
1857 CasesBits[i].Bits++;
1861 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1865 // Figure out which block is immediately after the current one.
1866 MachineFunction::iterator BBI = CR.CaseBB;
1869 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1871 DEBUG(dbgs() << "Cases:\n");
1872 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1873 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
1874 << ", Bits: " << CasesBits[i].Bits
1875 << ", BB: " << CasesBits[i].BB << '\n');
1877 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1878 CurMF->insert(BBI, CaseBB);
1879 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1883 // Put SV in a virtual register to make it available from the new blocks.
1884 ExportFromCurrentBlock(SV);
1887 BitTestBlock BTB(lowBound, cmpRange, SV,
1888 -1U, (CR.CaseBB == CurMBB),
1889 CR.CaseBB, Default, BTC);
1891 if (CR.CaseBB == CurMBB)
1892 visitBitTestHeader(BTB);
1894 BitTestCases.push_back(BTB);
1899 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1900 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
1901 const SwitchInst& SI) {
1904 // Start with "simple" cases
1905 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1906 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1907 Cases.push_back(Case(SI.getSuccessorValue(i),
1908 SI.getSuccessorValue(i),
1911 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1913 // Merge case into clusters
1914 if (Cases.size() >= 2)
1915 // Must recompute end() each iteration because it may be
1916 // invalidated by erase if we hold on to it
1917 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1918 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1919 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1920 MachineBasicBlock* nextBB = J->BB;
1921 MachineBasicBlock* currentBB = I->BB;
1923 // If the two neighboring cases go to the same destination, merge them
1924 // into a single case.
1925 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
1933 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1934 if (I->Low != I->High)
1935 // A range counts double, since it requires two compares.
1942 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
1943 // Figure out which block is immediately after the current one.
1944 MachineBasicBlock *NextBlock = 0;
1945 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1947 // If there is only the default destination, branch to it if it is not the
1948 // next basic block. Otherwise, just fall through.
1949 if (SI.getNumOperands() == 2) {
1950 // Update machine-CFG edges.
1952 // If this is not a fall-through branch, emit the branch.
1953 CurMBB->addSuccessor(Default);
1954 if (Default != NextBlock)
1955 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1956 MVT::Other, getControlRoot(),
1957 DAG.getBasicBlock(Default)));
1962 // If there are any non-default case statements, create a vector of Cases
1963 // representing each one, and sort the vector so that we can efficiently
1964 // create a binary search tree from them.
1966 size_t numCmps = Clusterify(Cases, SI);
1967 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
1968 << ". Total compares: " << numCmps << '\n');
1971 // Get the Value to be switched on and default basic blocks, which will be
1972 // inserted into CaseBlock records, representing basic blocks in the binary
1974 const Value *SV = SI.getOperand(0);
1976 // Push the initial CaseRec onto the worklist
1977 CaseRecVector WorkList;
1978 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1980 while (!WorkList.empty()) {
1981 // Grab a record representing a case range to process off the worklist
1982 CaseRec CR = WorkList.back();
1983 WorkList.pop_back();
1985 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1988 // If the range has few cases (two or less) emit a series of specific
1990 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1993 // If the switch has more than 5 blocks, and at least 40% dense, and the
1994 // target supports indirect branches, then emit a jump table rather than
1995 // lowering the switch to a binary tree of conditional branches.
1996 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1999 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2000 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2001 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2005 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2006 // Update machine-CFG edges with unique successors.
2007 SmallVector<BasicBlock*, 32> succs;
2008 succs.reserve(I.getNumSuccessors());
2009 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2010 succs.push_back(I.getSuccessor(i));
2011 array_pod_sort(succs.begin(), succs.end());
2012 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2013 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2014 CurMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2016 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2017 MVT::Other, getControlRoot(),
2018 getValue(I.getAddress())));
2021 void SelectionDAGBuilder::visitFSub(const User &I) {
2022 // -0.0 - X --> fneg
2023 const Type *Ty = I.getType();
2024 if (Ty->isVectorTy()) {
2025 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2026 const VectorType *DestTy = cast<VectorType>(I.getType());
2027 const Type *ElTy = DestTy->getElementType();
2028 unsigned VL = DestTy->getNumElements();
2029 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2030 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2032 SDValue Op2 = getValue(I.getOperand(1));
2033 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2034 Op2.getValueType(), Op2));
2040 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2041 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2042 SDValue Op2 = getValue(I.getOperand(1));
2043 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2044 Op2.getValueType(), Op2));
2048 visitBinary(I, ISD::FSUB);
2051 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2052 SDValue Op1 = getValue(I.getOperand(0));
2053 SDValue Op2 = getValue(I.getOperand(1));
2054 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2055 Op1.getValueType(), Op1, Op2));
2058 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2059 SDValue Op1 = getValue(I.getOperand(0));
2060 SDValue Op2 = getValue(I.getOperand(1));
2061 if (!I.getType()->isVectorTy() &&
2062 Op2.getValueType() != TLI.getShiftAmountTy()) {
2063 // If the operand is smaller than the shift count type, promote it.
2064 EVT PTy = TLI.getPointerTy();
2065 EVT STy = TLI.getShiftAmountTy();
2066 if (STy.bitsGT(Op2.getValueType()))
2067 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2068 TLI.getShiftAmountTy(), Op2);
2069 // If the operand is larger than the shift count type but the shift
2070 // count type has enough bits to represent any shift value, truncate
2071 // it now. This is a common case and it exposes the truncate to
2072 // optimization early.
2073 else if (STy.getSizeInBits() >=
2074 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2075 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2076 TLI.getShiftAmountTy(), Op2);
2077 // Otherwise we'll need to temporarily settle for some other
2078 // convenient type; type legalization will make adjustments as
2080 else if (PTy.bitsLT(Op2.getValueType()))
2081 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2082 TLI.getPointerTy(), Op2);
2083 else if (PTy.bitsGT(Op2.getValueType()))
2084 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2085 TLI.getPointerTy(), Op2);
2088 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2089 Op1.getValueType(), Op1, Op2));
2092 void SelectionDAGBuilder::visitICmp(const User &I) {
2093 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2094 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2095 predicate = IC->getPredicate();
2096 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2097 predicate = ICmpInst::Predicate(IC->getPredicate());
2098 SDValue Op1 = getValue(I.getOperand(0));
2099 SDValue Op2 = getValue(I.getOperand(1));
2100 ISD::CondCode Opcode = getICmpCondCode(predicate);
2102 EVT DestVT = TLI.getValueType(I.getType());
2103 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2106 void SelectionDAGBuilder::visitFCmp(const User &I) {
2107 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2108 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2109 predicate = FC->getPredicate();
2110 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2111 predicate = FCmpInst::Predicate(FC->getPredicate());
2112 SDValue Op1 = getValue(I.getOperand(0));
2113 SDValue Op2 = getValue(I.getOperand(1));
2114 ISD::CondCode Condition = getFCmpCondCode(predicate);
2115 EVT DestVT = TLI.getValueType(I.getType());
2116 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2119 void SelectionDAGBuilder::visitSelect(const User &I) {
2120 SmallVector<EVT, 4> ValueVTs;
2121 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2122 unsigned NumValues = ValueVTs.size();
2123 if (NumValues == 0) return;
2125 SmallVector<SDValue, 4> Values(NumValues);
2126 SDValue Cond = getValue(I.getOperand(0));
2127 SDValue TrueVal = getValue(I.getOperand(1));
2128 SDValue FalseVal = getValue(I.getOperand(2));
2130 for (unsigned i = 0; i != NumValues; ++i)
2131 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2132 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2134 SDValue(TrueVal.getNode(),
2135 TrueVal.getResNo() + i),
2136 SDValue(FalseVal.getNode(),
2137 FalseVal.getResNo() + i));
2139 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2140 DAG.getVTList(&ValueVTs[0], NumValues),
2141 &Values[0], NumValues));
2144 void SelectionDAGBuilder::visitTrunc(const User &I) {
2145 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2146 SDValue N = getValue(I.getOperand(0));
2147 EVT DestVT = TLI.getValueType(I.getType());
2148 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2151 void SelectionDAGBuilder::visitZExt(const User &I) {
2152 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2153 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2154 SDValue N = getValue(I.getOperand(0));
2155 EVT DestVT = TLI.getValueType(I.getType());
2156 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2159 void SelectionDAGBuilder::visitSExt(const User &I) {
2160 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2161 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2162 SDValue N = getValue(I.getOperand(0));
2163 EVT DestVT = TLI.getValueType(I.getType());
2164 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2167 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2168 // FPTrunc is never a no-op cast, no need to check
2169 SDValue N = getValue(I.getOperand(0));
2170 EVT DestVT = TLI.getValueType(I.getType());
2171 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2172 DestVT, N, DAG.getIntPtrConstant(0)));
2175 void SelectionDAGBuilder::visitFPExt(const User &I){
2176 // FPTrunc is never a no-op cast, no need to check
2177 SDValue N = getValue(I.getOperand(0));
2178 EVT DestVT = TLI.getValueType(I.getType());
2179 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2182 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2183 // FPToUI is never a no-op cast, no need to check
2184 SDValue N = getValue(I.getOperand(0));
2185 EVT DestVT = TLI.getValueType(I.getType());
2186 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2189 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2190 // FPToSI is never a no-op cast, no need to check
2191 SDValue N = getValue(I.getOperand(0));
2192 EVT DestVT = TLI.getValueType(I.getType());
2193 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2196 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2197 // UIToFP is never a no-op cast, no need to check
2198 SDValue N = getValue(I.getOperand(0));
2199 EVT DestVT = TLI.getValueType(I.getType());
2200 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2203 void SelectionDAGBuilder::visitSIToFP(const User &I){
2204 // SIToFP is never a no-op cast, no need to check
2205 SDValue N = getValue(I.getOperand(0));
2206 EVT DestVT = TLI.getValueType(I.getType());
2207 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2210 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2211 // What to do depends on the size of the integer and the size of the pointer.
2212 // We can either truncate, zero extend, or no-op, accordingly.
2213 SDValue N = getValue(I.getOperand(0));
2214 EVT SrcVT = N.getValueType();
2215 EVT DestVT = TLI.getValueType(I.getType());
2216 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2219 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2220 // What to do depends on the size of the integer and the size of the pointer.
2221 // We can either truncate, zero extend, or no-op, accordingly.
2222 SDValue N = getValue(I.getOperand(0));
2223 EVT SrcVT = N.getValueType();
2224 EVT DestVT = TLI.getValueType(I.getType());
2225 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2228 void SelectionDAGBuilder::visitBitCast(const User &I) {
2229 SDValue N = getValue(I.getOperand(0));
2230 EVT DestVT = TLI.getValueType(I.getType());
2232 // BitCast assures us that source and destination are the same size so this is
2233 // either a BIT_CONVERT or a no-op.
2234 if (DestVT != N.getValueType())
2235 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2236 DestVT, N)); // convert types.
2238 setValue(&I, N); // noop cast.
2241 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2242 SDValue InVec = getValue(I.getOperand(0));
2243 SDValue InVal = getValue(I.getOperand(1));
2244 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2246 getValue(I.getOperand(2)));
2247 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2248 TLI.getValueType(I.getType()),
2249 InVec, InVal, InIdx));
2252 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2253 SDValue InVec = getValue(I.getOperand(0));
2254 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2256 getValue(I.getOperand(1)));
2257 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2258 TLI.getValueType(I.getType()), InVec, InIdx));
2261 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2262 // from SIndx and increasing to the element length (undefs are allowed).
2263 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2264 unsigned MaskNumElts = Mask.size();
2265 for (unsigned i = 0; i != MaskNumElts; ++i)
2266 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2271 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2272 SmallVector<int, 8> Mask;
2273 SDValue Src1 = getValue(I.getOperand(0));
2274 SDValue Src2 = getValue(I.getOperand(1));
2276 // Convert the ConstantVector mask operand into an array of ints, with -1
2277 // representing undef values.
2278 SmallVector<Constant*, 8> MaskElts;
2279 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2280 unsigned MaskNumElts = MaskElts.size();
2281 for (unsigned i = 0; i != MaskNumElts; ++i) {
2282 if (isa<UndefValue>(MaskElts[i]))
2285 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2288 EVT VT = TLI.getValueType(I.getType());
2289 EVT SrcVT = Src1.getValueType();
2290 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2292 if (SrcNumElts == MaskNumElts) {
2293 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2298 // Normalize the shuffle vector since mask and vector length don't match.
2299 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2300 // Mask is longer than the source vectors and is a multiple of the source
2301 // vectors. We can use concatenate vector to make the mask and vectors
2303 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2304 // The shuffle is concatenating two vectors together.
2305 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2310 // Pad both vectors with undefs to make them the same length as the mask.
2311 unsigned NumConcat = MaskNumElts / SrcNumElts;
2312 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2313 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2314 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2316 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2317 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2321 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2322 getCurDebugLoc(), VT,
2323 &MOps1[0], NumConcat);
2324 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2325 getCurDebugLoc(), VT,
2326 &MOps2[0], NumConcat);
2328 // Readjust mask for new input vector length.
2329 SmallVector<int, 8> MappedOps;
2330 for (unsigned i = 0; i != MaskNumElts; ++i) {
2332 if (Idx < (int)SrcNumElts)
2333 MappedOps.push_back(Idx);
2335 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2338 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2343 if (SrcNumElts > MaskNumElts) {
2344 // Analyze the access pattern of the vector to see if we can extract
2345 // two subvectors and do the shuffle. The analysis is done by calculating
2346 // the range of elements the mask access on both vectors.
2347 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2348 int MaxRange[2] = {-1, -1};
2350 for (unsigned i = 0; i != MaskNumElts; ++i) {
2356 if (Idx >= (int)SrcNumElts) {
2360 if (Idx > MaxRange[Input])
2361 MaxRange[Input] = Idx;
2362 if (Idx < MinRange[Input])
2363 MinRange[Input] = Idx;
2366 // Check if the access is smaller than the vector size and can we find
2367 // a reasonable extract index.
2368 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2370 int StartIdx[2]; // StartIdx to extract from
2371 for (int Input=0; Input < 2; ++Input) {
2372 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2373 RangeUse[Input] = 0; // Unused
2374 StartIdx[Input] = 0;
2375 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2376 // Fits within range but we should see if we can find a good
2377 // start index that is a multiple of the mask length.
2378 if (MaxRange[Input] < (int)MaskNumElts) {
2379 RangeUse[Input] = 1; // Extract from beginning of the vector
2380 StartIdx[Input] = 0;
2382 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2383 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2384 StartIdx[Input] + MaskNumElts < SrcNumElts)
2385 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2390 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2391 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2394 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2395 // Extract appropriate subvector and generate a vector shuffle
2396 for (int Input=0; Input < 2; ++Input) {
2397 SDValue &Src = Input == 0 ? Src1 : Src2;
2398 if (RangeUse[Input] == 0)
2399 Src = DAG.getUNDEF(VT);
2401 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2402 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2405 // Calculate new mask.
2406 SmallVector<int, 8> MappedOps;
2407 for (unsigned i = 0; i != MaskNumElts; ++i) {
2410 MappedOps.push_back(Idx);
2411 else if (Idx < (int)SrcNumElts)
2412 MappedOps.push_back(Idx - StartIdx[0]);
2414 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2417 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2423 // We can't use either concat vectors or extract subvectors so fall back to
2424 // replacing the shuffle with extract and build vector.
2425 // to insert and build vector.
2426 EVT EltVT = VT.getVectorElementType();
2427 EVT PtrVT = TLI.getPointerTy();
2428 SmallVector<SDValue,8> Ops;
2429 for (unsigned i = 0; i != MaskNumElts; ++i) {
2431 Ops.push_back(DAG.getUNDEF(EltVT));
2436 if (Idx < (int)SrcNumElts)
2437 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2438 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2440 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2442 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2448 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2449 VT, &Ops[0], Ops.size()));
2452 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2453 const Value *Op0 = I.getOperand(0);
2454 const Value *Op1 = I.getOperand(1);
2455 const Type *AggTy = I.getType();
2456 const Type *ValTy = Op1->getType();
2457 bool IntoUndef = isa<UndefValue>(Op0);
2458 bool FromUndef = isa<UndefValue>(Op1);
2460 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2461 I.idx_begin(), I.idx_end());
2463 SmallVector<EVT, 4> AggValueVTs;
2464 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2465 SmallVector<EVT, 4> ValValueVTs;
2466 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2468 unsigned NumAggValues = AggValueVTs.size();
2469 unsigned NumValValues = ValValueVTs.size();
2470 SmallVector<SDValue, 4> Values(NumAggValues);
2472 SDValue Agg = getValue(Op0);
2473 SDValue Val = getValue(Op1);
2475 // Copy the beginning value(s) from the original aggregate.
2476 for (; i != LinearIndex; ++i)
2477 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2478 SDValue(Agg.getNode(), Agg.getResNo() + i);
2479 // Copy values from the inserted value(s).
2480 for (; i != LinearIndex + NumValValues; ++i)
2481 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2482 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2483 // Copy remaining value(s) from the original aggregate.
2484 for (; i != NumAggValues; ++i)
2485 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2486 SDValue(Agg.getNode(), Agg.getResNo() + i);
2488 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2489 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2490 &Values[0], NumAggValues));
2493 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2494 const Value *Op0 = I.getOperand(0);
2495 const Type *AggTy = Op0->getType();
2496 const Type *ValTy = I.getType();
2497 bool OutOfUndef = isa<UndefValue>(Op0);
2499 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2500 I.idx_begin(), I.idx_end());
2502 SmallVector<EVT, 4> ValValueVTs;
2503 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2505 unsigned NumValValues = ValValueVTs.size();
2506 SmallVector<SDValue, 4> Values(NumValValues);
2508 SDValue Agg = getValue(Op0);
2509 // Copy out the selected value(s).
2510 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2511 Values[i - LinearIndex] =
2513 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2514 SDValue(Agg.getNode(), Agg.getResNo() + i);
2516 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2517 DAG.getVTList(&ValValueVTs[0], NumValValues),
2518 &Values[0], NumValValues));
2521 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2522 SDValue N = getValue(I.getOperand(0));
2523 const Type *Ty = I.getOperand(0)->getType();
2525 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2527 const Value *Idx = *OI;
2528 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2529 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2532 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2533 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2534 DAG.getIntPtrConstant(Offset));
2537 Ty = StTy->getElementType(Field);
2538 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) {
2539 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2541 // Offset canonically 0 for unions, but type changes
2542 Ty = UnTy->getElementType(Field);
2544 Ty = cast<SequentialType>(Ty)->getElementType();
2546 // If this is a constant subscript, handle it quickly.
2547 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2548 if (CI->getZExtValue() == 0) continue;
2550 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2552 EVT PTy = TLI.getPointerTy();
2553 unsigned PtrBits = PTy.getSizeInBits();
2555 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2557 DAG.getConstant(Offs, MVT::i64));
2559 OffsVal = DAG.getIntPtrConstant(Offs);
2561 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2566 // N = N + Idx * ElementSize;
2567 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2568 TD->getTypeAllocSize(Ty));
2569 SDValue IdxN = getValue(Idx);
2571 // If the index is smaller or larger than intptr_t, truncate or extend
2573 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2575 // If this is a multiply by a power of two, turn it into a shl
2576 // immediately. This is a very common case.
2577 if (ElementSize != 1) {
2578 if (ElementSize.isPowerOf2()) {
2579 unsigned Amt = ElementSize.logBase2();
2580 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2581 N.getValueType(), IdxN,
2582 DAG.getConstant(Amt, TLI.getPointerTy()));
2584 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2585 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2586 N.getValueType(), IdxN, Scale);
2590 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2591 N.getValueType(), N, IdxN);
2598 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2599 // If this is a fixed sized alloca in the entry block of the function,
2600 // allocate it statically on the stack.
2601 if (FuncInfo.StaticAllocaMap.count(&I))
2602 return; // getValue will auto-populate this.
2604 const Type *Ty = I.getAllocatedType();
2605 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2607 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2610 SDValue AllocSize = getValue(I.getArraySize());
2612 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2614 DAG.getConstant(TySize, AllocSize.getValueType()));
2616 EVT IntPtr = TLI.getPointerTy();
2617 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2619 // Handle alignment. If the requested alignment is less than or equal to
2620 // the stack alignment, ignore it. If the size is greater than or equal to
2621 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2622 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2623 if (Align <= StackAlign)
2626 // Round the size of the allocation up to the stack alignment size
2627 // by add SA-1 to the size.
2628 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2629 AllocSize.getValueType(), AllocSize,
2630 DAG.getIntPtrConstant(StackAlign-1));
2632 // Mask out the low bits for alignment purposes.
2633 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2634 AllocSize.getValueType(), AllocSize,
2635 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2637 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2638 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2639 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2642 DAG.setRoot(DSA.getValue(1));
2644 // Inform the Frame Information that we have just allocated a variable-sized
2646 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2649 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2650 const Value *SV = I.getOperand(0);
2651 SDValue Ptr = getValue(SV);
2653 const Type *Ty = I.getType();
2655 bool isVolatile = I.isVolatile();
2656 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2657 unsigned Alignment = I.getAlignment();
2659 SmallVector<EVT, 4> ValueVTs;
2660 SmallVector<uint64_t, 4> Offsets;
2661 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2662 unsigned NumValues = ValueVTs.size();
2667 bool ConstantMemory = false;
2669 // Serialize volatile loads with other side effects.
2671 else if (AA->pointsToConstantMemory(SV)) {
2672 // Do not serialize (non-volatile) loads of constant memory with anything.
2673 Root = DAG.getEntryNode();
2674 ConstantMemory = true;
2676 // Do not serialize non-volatile loads against each other.
2677 Root = DAG.getRoot();
2680 SmallVector<SDValue, 4> Values(NumValues);
2681 SmallVector<SDValue, 4> Chains(NumValues);
2682 EVT PtrVT = Ptr.getValueType();
2683 for (unsigned i = 0; i != NumValues; ++i) {
2684 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2686 DAG.getConstant(Offsets[i], PtrVT));
2687 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2688 A, SV, Offsets[i], isVolatile,
2689 isNonTemporal, Alignment);
2692 Chains[i] = L.getValue(1);
2695 if (!ConstantMemory) {
2696 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2697 MVT::Other, &Chains[0], NumValues);
2701 PendingLoads.push_back(Chain);
2704 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2705 DAG.getVTList(&ValueVTs[0], NumValues),
2706 &Values[0], NumValues));
2709 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2710 const Value *SrcV = I.getOperand(0);
2711 const Value *PtrV = I.getOperand(1);
2713 SmallVector<EVT, 4> ValueVTs;
2714 SmallVector<uint64_t, 4> Offsets;
2715 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2716 unsigned NumValues = ValueVTs.size();
2720 // Get the lowered operands. Note that we do this after
2721 // checking if NumResults is zero, because with zero results
2722 // the operands won't have values in the map.
2723 SDValue Src = getValue(SrcV);
2724 SDValue Ptr = getValue(PtrV);
2726 SDValue Root = getRoot();
2727 SmallVector<SDValue, 4> Chains(NumValues);
2728 EVT PtrVT = Ptr.getValueType();
2729 bool isVolatile = I.isVolatile();
2730 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2731 unsigned Alignment = I.getAlignment();
2733 for (unsigned i = 0; i != NumValues; ++i) {
2734 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
2735 DAG.getConstant(Offsets[i], PtrVT));
2736 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2737 SDValue(Src.getNode(), Src.getResNo() + i),
2738 Add, PtrV, Offsets[i], isVolatile,
2739 isNonTemporal, Alignment);
2742 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2743 MVT::Other, &Chains[0], NumValues));
2746 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2748 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
2749 unsigned Intrinsic) {
2750 bool HasChain = !I.doesNotAccessMemory();
2751 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2753 // Build the operand list.
2754 SmallVector<SDValue, 8> Ops;
2755 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2757 // We don't need to serialize loads against other loads.
2758 Ops.push_back(DAG.getRoot());
2760 Ops.push_back(getRoot());
2764 // Info is set by getTgtMemInstrinsic
2765 TargetLowering::IntrinsicInfo Info;
2766 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2768 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2769 if (!IsTgtIntrinsic)
2770 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2772 // Add all operands of the call to the operand list.
2773 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2774 SDValue Op = getValue(I.getOperand(i));
2775 assert(TLI.isTypeLegal(Op.getValueType()) &&
2776 "Intrinsic uses a non-legal type?");
2780 SmallVector<EVT, 4> ValueVTs;
2781 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2783 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2784 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2785 "Intrinsic uses a non-legal type?");
2790 ValueVTs.push_back(MVT::Other);
2792 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2796 if (IsTgtIntrinsic) {
2797 // This is target intrinsic that touches memory
2798 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2799 VTs, &Ops[0], Ops.size(),
2800 Info.memVT, Info.ptrVal, Info.offset,
2801 Info.align, Info.vol,
2802 Info.readMem, Info.writeMem);
2803 } else if (!HasChain) {
2804 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2805 VTs, &Ops[0], Ops.size());
2806 } else if (!I.getType()->isVoidTy()) {
2807 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2808 VTs, &Ops[0], Ops.size());
2810 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2811 VTs, &Ops[0], Ops.size());
2815 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2817 PendingLoads.push_back(Chain);
2822 if (!I.getType()->isVoidTy()) {
2823 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2824 EVT VT = TLI.getValueType(PTy);
2825 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2828 setValue(&I, Result);
2832 /// GetSignificand - Get the significand and build it into a floating-point
2833 /// number with exponent of 1:
2835 /// Op = (Op & 0x007fffff) | 0x3f800000;
2837 /// where Op is the hexidecimal representation of floating point value.
2839 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
2840 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2841 DAG.getConstant(0x007fffff, MVT::i32));
2842 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
2843 DAG.getConstant(0x3f800000, MVT::i32));
2844 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
2847 /// GetExponent - Get the exponent:
2849 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
2851 /// where Op is the hexidecimal representation of floating point value.
2853 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
2855 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2856 DAG.getConstant(0x7f800000, MVT::i32));
2857 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
2858 DAG.getConstant(23, TLI.getPointerTy()));
2859 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
2860 DAG.getConstant(127, MVT::i32));
2861 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
2864 /// getF32Constant - Get 32-bit floating point constant.
2866 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2867 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2870 /// Inlined utility function to implement binary input atomic intrinsics for
2871 /// visitIntrinsicCall: I is a call instruction
2872 /// Op is the associated NodeType for I
2874 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
2876 SDValue Root = getRoot();
2878 DAG.getAtomic(Op, getCurDebugLoc(),
2879 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
2881 getValue(I.getOperand(1)),
2882 getValue(I.getOperand(2)),
2885 DAG.setRoot(L.getValue(1));
2889 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
2891 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
2892 SDValue Op1 = getValue(I.getOperand(1));
2893 SDValue Op2 = getValue(I.getOperand(2));
2895 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
2896 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
2900 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2901 /// limited-precision mode.
2903 SelectionDAGBuilder::visitExp(const CallInst &I) {
2905 DebugLoc dl = getCurDebugLoc();
2907 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2908 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2909 SDValue Op = getValue(I.getOperand(1));
2911 // Put the exponent in the right bit position for later addition to the
2914 // #define LOG2OFe 1.4426950f
2915 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2916 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
2917 getF32Constant(DAG, 0x3fb8aa3b));
2918 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
2920 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2921 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
2922 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
2924 // IntegerPartOfX <<= 23;
2925 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
2926 DAG.getConstant(23, TLI.getPointerTy()));
2928 if (LimitFloatPrecision <= 6) {
2929 // For floating-point precision of 6:
2931 // TwoToFractionalPartOfX =
2933 // (0.735607626f + 0.252464424f * x) * x;
2935 // error 0.0144103317, which is 6 bits
2936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2937 getF32Constant(DAG, 0x3e814304));
2938 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2939 getF32Constant(DAG, 0x3f3c50c8));
2940 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2941 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2942 getF32Constant(DAG, 0x3f7f5e7e));
2943 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
2945 // Add the exponent into the result in integer domain.
2946 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2947 TwoToFracPartOfX, IntegerPartOfX);
2949 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
2950 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2951 // For floating-point precision of 12:
2953 // TwoToFractionalPartOfX =
2956 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2958 // 0.000107046256 error, which is 13 to 14 bits
2959 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2960 getF32Constant(DAG, 0x3da235e3));
2961 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2962 getF32Constant(DAG, 0x3e65b8f3));
2963 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2964 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2965 getF32Constant(DAG, 0x3f324b07));
2966 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
2967 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
2968 getF32Constant(DAG, 0x3f7ff8fd));
2969 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
2971 // Add the exponent into the result in integer domain.
2972 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2973 TwoToFracPartOfX, IntegerPartOfX);
2975 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
2976 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
2977 // For floating-point precision of 18:
2979 // TwoToFractionalPartOfX =
2983 // (0.554906021e-1f +
2984 // (0.961591928e-2f +
2985 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
2987 // error 2.47208000*10^(-7), which is better than 18 bits
2988 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2989 getF32Constant(DAG, 0x3924b03e));
2990 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2991 getF32Constant(DAG, 0x3ab24b87));
2992 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2993 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2994 getF32Constant(DAG, 0x3c1d8c17));
2995 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
2996 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
2997 getF32Constant(DAG, 0x3d634a1d));
2998 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
2999 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3000 getF32Constant(DAG, 0x3e75fe14));
3001 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3002 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3003 getF32Constant(DAG, 0x3f317234));
3004 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3005 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3006 getF32Constant(DAG, 0x3f800000));
3007 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3010 // Add the exponent into the result in integer domain.
3011 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3012 TwoToFracPartOfX, IntegerPartOfX);
3014 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3017 // No special expansion.
3018 result = DAG.getNode(ISD::FEXP, dl,
3019 getValue(I.getOperand(1)).getValueType(),
3020 getValue(I.getOperand(1)));
3023 setValue(&I, result);
3026 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3027 /// limited-precision mode.
3029 SelectionDAGBuilder::visitLog(const CallInst &I) {
3031 DebugLoc dl = getCurDebugLoc();
3033 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3034 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3035 SDValue Op = getValue(I.getOperand(1));
3036 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3038 // Scale the exponent by log(2) [0.69314718f].
3039 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3040 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3041 getF32Constant(DAG, 0x3f317218));
3043 // Get the significand and build it into a floating-point number with
3045 SDValue X = GetSignificand(DAG, Op1, dl);
3047 if (LimitFloatPrecision <= 6) {
3048 // For floating-point precision of 6:
3052 // (1.4034025f - 0.23903021f * x) * x;
3054 // error 0.0034276066, which is better than 8 bits
3055 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3056 getF32Constant(DAG, 0xbe74c456));
3057 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3058 getF32Constant(DAG, 0x3fb3a2b1));
3059 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3060 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3061 getF32Constant(DAG, 0x3f949a29));
3063 result = DAG.getNode(ISD::FADD, dl,
3064 MVT::f32, LogOfExponent, LogOfMantissa);
3065 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3066 // For floating-point precision of 12:
3072 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3074 // error 0.000061011436, which is 14 bits
3075 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3076 getF32Constant(DAG, 0xbd67b6d6));
3077 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3078 getF32Constant(DAG, 0x3ee4f4b8));
3079 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3080 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3081 getF32Constant(DAG, 0x3fbc278b));
3082 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3083 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3084 getF32Constant(DAG, 0x40348e95));
3085 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3086 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3087 getF32Constant(DAG, 0x3fdef31a));
3089 result = DAG.getNode(ISD::FADD, dl,
3090 MVT::f32, LogOfExponent, LogOfMantissa);
3091 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3092 // For floating-point precision of 18:
3100 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3102 // error 0.0000023660568, which is better than 18 bits
3103 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3104 getF32Constant(DAG, 0xbc91e5ac));
3105 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3106 getF32Constant(DAG, 0x3e4350aa));
3107 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3108 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3109 getF32Constant(DAG, 0x3f60d3e3));
3110 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3111 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3112 getF32Constant(DAG, 0x4011cdf0));
3113 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3114 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3115 getF32Constant(DAG, 0x406cfd1c));
3116 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3117 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3118 getF32Constant(DAG, 0x408797cb));
3119 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3120 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3121 getF32Constant(DAG, 0x4006dcab));
3123 result = DAG.getNode(ISD::FADD, dl,
3124 MVT::f32, LogOfExponent, LogOfMantissa);
3127 // No special expansion.
3128 result = DAG.getNode(ISD::FLOG, dl,
3129 getValue(I.getOperand(1)).getValueType(),
3130 getValue(I.getOperand(1)));
3133 setValue(&I, result);
3136 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3137 /// limited-precision mode.
3139 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3141 DebugLoc dl = getCurDebugLoc();
3143 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3144 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3145 SDValue Op = getValue(I.getOperand(1));
3146 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3148 // Get the exponent.
3149 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3151 // Get the significand and build it into a floating-point number with
3153 SDValue X = GetSignificand(DAG, Op1, dl);
3155 // Different possible minimax approximations of significand in
3156 // floating-point for various degrees of accuracy over [1,2].
3157 if (LimitFloatPrecision <= 6) {
3158 // For floating-point precision of 6:
3160 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3162 // error 0.0049451742, which is more than 7 bits
3163 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3164 getF32Constant(DAG, 0xbeb08fe0));
3165 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3166 getF32Constant(DAG, 0x40019463));
3167 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3168 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3169 getF32Constant(DAG, 0x3fd6633d));
3171 result = DAG.getNode(ISD::FADD, dl,
3172 MVT::f32, LogOfExponent, Log2ofMantissa);
3173 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3174 // For floating-point precision of 12:
3180 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3182 // error 0.0000876136000, which is better than 13 bits
3183 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3184 getF32Constant(DAG, 0xbda7262e));
3185 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3186 getF32Constant(DAG, 0x3f25280b));
3187 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3188 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3189 getF32Constant(DAG, 0x4007b923));
3190 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3191 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3192 getF32Constant(DAG, 0x40823e2f));
3193 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3194 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3195 getF32Constant(DAG, 0x4020d29c));
3197 result = DAG.getNode(ISD::FADD, dl,
3198 MVT::f32, LogOfExponent, Log2ofMantissa);
3199 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3200 // For floating-point precision of 18:
3209 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3211 // error 0.0000018516, which is better than 18 bits
3212 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3213 getF32Constant(DAG, 0xbcd2769e));
3214 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3215 getF32Constant(DAG, 0x3e8ce0b9));
3216 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3217 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3218 getF32Constant(DAG, 0x3fa22ae7));
3219 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3220 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3221 getF32Constant(DAG, 0x40525723));
3222 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3223 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3224 getF32Constant(DAG, 0x40aaf200));
3225 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3226 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3227 getF32Constant(DAG, 0x40c39dad));
3228 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3229 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3230 getF32Constant(DAG, 0x4042902c));
3232 result = DAG.getNode(ISD::FADD, dl,
3233 MVT::f32, LogOfExponent, Log2ofMantissa);
3236 // No special expansion.
3237 result = DAG.getNode(ISD::FLOG2, dl,
3238 getValue(I.getOperand(1)).getValueType(),
3239 getValue(I.getOperand(1)));
3242 setValue(&I, result);
3245 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3246 /// limited-precision mode.
3248 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3250 DebugLoc dl = getCurDebugLoc();
3252 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3253 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3254 SDValue Op = getValue(I.getOperand(1));
3255 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3257 // Scale the exponent by log10(2) [0.30102999f].
3258 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3259 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3260 getF32Constant(DAG, 0x3e9a209a));
3262 // Get the significand and build it into a floating-point number with
3264 SDValue X = GetSignificand(DAG, Op1, dl);
3266 if (LimitFloatPrecision <= 6) {
3267 // For floating-point precision of 6:
3269 // Log10ofMantissa =
3271 // (0.60948995f - 0.10380950f * x) * x;
3273 // error 0.0014886165, which is 6 bits
3274 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3275 getF32Constant(DAG, 0xbdd49a13));
3276 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3277 getF32Constant(DAG, 0x3f1c0789));
3278 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3279 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3280 getF32Constant(DAG, 0x3f011300));
3282 result = DAG.getNode(ISD::FADD, dl,
3283 MVT::f32, LogOfExponent, Log10ofMantissa);
3284 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3285 // For floating-point precision of 12:
3287 // Log10ofMantissa =
3290 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3292 // error 0.00019228036, which is better than 12 bits
3293 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3294 getF32Constant(DAG, 0x3d431f31));
3295 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3296 getF32Constant(DAG, 0x3ea21fb2));
3297 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3298 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3299 getF32Constant(DAG, 0x3f6ae232));
3300 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3301 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3302 getF32Constant(DAG, 0x3f25f7c3));
3304 result = DAG.getNode(ISD::FADD, dl,
3305 MVT::f32, LogOfExponent, Log10ofMantissa);
3306 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3307 // For floating-point precision of 18:
3309 // Log10ofMantissa =
3314 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3316 // error 0.0000037995730, which is better than 18 bits
3317 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3318 getF32Constant(DAG, 0x3c5d51ce));
3319 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3320 getF32Constant(DAG, 0x3e00685a));
3321 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3322 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3323 getF32Constant(DAG, 0x3efb6798));
3324 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3325 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3326 getF32Constant(DAG, 0x3f88d192));
3327 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3328 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3329 getF32Constant(DAG, 0x3fc4316c));
3330 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3331 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3332 getF32Constant(DAG, 0x3f57ce70));
3334 result = DAG.getNode(ISD::FADD, dl,
3335 MVT::f32, LogOfExponent, Log10ofMantissa);
3338 // No special expansion.
3339 result = DAG.getNode(ISD::FLOG10, dl,
3340 getValue(I.getOperand(1)).getValueType(),
3341 getValue(I.getOperand(1)));
3344 setValue(&I, result);
3347 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3348 /// limited-precision mode.
3350 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3352 DebugLoc dl = getCurDebugLoc();
3354 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3355 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3356 SDValue Op = getValue(I.getOperand(1));
3358 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3360 // FractionalPartOfX = x - (float)IntegerPartOfX;
3361 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3362 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3364 // IntegerPartOfX <<= 23;
3365 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3366 DAG.getConstant(23, TLI.getPointerTy()));
3368 if (LimitFloatPrecision <= 6) {
3369 // For floating-point precision of 6:
3371 // TwoToFractionalPartOfX =
3373 // (0.735607626f + 0.252464424f * x) * x;
3375 // error 0.0144103317, which is 6 bits
3376 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3377 getF32Constant(DAG, 0x3e814304));
3378 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3379 getF32Constant(DAG, 0x3f3c50c8));
3380 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3381 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3382 getF32Constant(DAG, 0x3f7f5e7e));
3383 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3384 SDValue TwoToFractionalPartOfX =
3385 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3387 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3388 MVT::f32, TwoToFractionalPartOfX);
3389 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3390 // For floating-point precision of 12:
3392 // TwoToFractionalPartOfX =
3395 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3397 // error 0.000107046256, which is 13 to 14 bits
3398 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3399 getF32Constant(DAG, 0x3da235e3));
3400 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3401 getF32Constant(DAG, 0x3e65b8f3));
3402 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3403 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3404 getF32Constant(DAG, 0x3f324b07));
3405 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3406 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3407 getF32Constant(DAG, 0x3f7ff8fd));
3408 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3409 SDValue TwoToFractionalPartOfX =
3410 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3412 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3413 MVT::f32, TwoToFractionalPartOfX);
3414 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3415 // For floating-point precision of 18:
3417 // TwoToFractionalPartOfX =
3421 // (0.554906021e-1f +
3422 // (0.961591928e-2f +
3423 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3424 // error 2.47208000*10^(-7), which is better than 18 bits
3425 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3426 getF32Constant(DAG, 0x3924b03e));
3427 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3428 getF32Constant(DAG, 0x3ab24b87));
3429 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3430 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3431 getF32Constant(DAG, 0x3c1d8c17));
3432 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3433 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3434 getF32Constant(DAG, 0x3d634a1d));
3435 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3436 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3437 getF32Constant(DAG, 0x3e75fe14));
3438 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3439 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3440 getF32Constant(DAG, 0x3f317234));
3441 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3442 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3443 getF32Constant(DAG, 0x3f800000));
3444 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3445 SDValue TwoToFractionalPartOfX =
3446 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3448 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3449 MVT::f32, TwoToFractionalPartOfX);
3452 // No special expansion.
3453 result = DAG.getNode(ISD::FEXP2, dl,
3454 getValue(I.getOperand(1)).getValueType(),
3455 getValue(I.getOperand(1)));
3458 setValue(&I, result);
3461 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3462 /// limited-precision mode with x == 10.0f.
3464 SelectionDAGBuilder::visitPow(const CallInst &I) {
3466 const Value *Val = I.getOperand(1);
3467 DebugLoc dl = getCurDebugLoc();
3468 bool IsExp10 = false;
3470 if (getValue(Val).getValueType() == MVT::f32 &&
3471 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3472 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3473 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3474 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3476 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3481 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3482 SDValue Op = getValue(I.getOperand(2));
3484 // Put the exponent in the right bit position for later addition to the
3487 // #define LOG2OF10 3.3219281f
3488 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3489 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3490 getF32Constant(DAG, 0x40549a78));
3491 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3493 // FractionalPartOfX = x - (float)IntegerPartOfX;
3494 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3495 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3497 // IntegerPartOfX <<= 23;
3498 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3499 DAG.getConstant(23, TLI.getPointerTy()));
3501 if (LimitFloatPrecision <= 6) {
3502 // For floating-point precision of 6:
3504 // twoToFractionalPartOfX =
3506 // (0.735607626f + 0.252464424f * x) * x;
3508 // error 0.0144103317, which is 6 bits
3509 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3510 getF32Constant(DAG, 0x3e814304));
3511 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3512 getF32Constant(DAG, 0x3f3c50c8));
3513 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3514 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3515 getF32Constant(DAG, 0x3f7f5e7e));
3516 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3517 SDValue TwoToFractionalPartOfX =
3518 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3520 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3521 MVT::f32, TwoToFractionalPartOfX);
3522 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3523 // For floating-point precision of 12:
3525 // TwoToFractionalPartOfX =
3528 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3530 // error 0.000107046256, which is 13 to 14 bits
3531 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3532 getF32Constant(DAG, 0x3da235e3));
3533 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3534 getF32Constant(DAG, 0x3e65b8f3));
3535 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3536 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3537 getF32Constant(DAG, 0x3f324b07));
3538 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3539 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3540 getF32Constant(DAG, 0x3f7ff8fd));
3541 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3542 SDValue TwoToFractionalPartOfX =
3543 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3545 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3546 MVT::f32, TwoToFractionalPartOfX);
3547 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3548 // For floating-point precision of 18:
3550 // TwoToFractionalPartOfX =
3554 // (0.554906021e-1f +
3555 // (0.961591928e-2f +
3556 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3557 // error 2.47208000*10^(-7), which is better than 18 bits
3558 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3559 getF32Constant(DAG, 0x3924b03e));
3560 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3561 getF32Constant(DAG, 0x3ab24b87));
3562 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3563 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3564 getF32Constant(DAG, 0x3c1d8c17));
3565 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3566 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3567 getF32Constant(DAG, 0x3d634a1d));
3568 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3569 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3570 getF32Constant(DAG, 0x3e75fe14));
3571 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3572 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3573 getF32Constant(DAG, 0x3f317234));
3574 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3575 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3576 getF32Constant(DAG, 0x3f800000));
3577 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3578 SDValue TwoToFractionalPartOfX =
3579 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3581 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3582 MVT::f32, TwoToFractionalPartOfX);
3585 // No special expansion.
3586 result = DAG.getNode(ISD::FPOW, dl,
3587 getValue(I.getOperand(1)).getValueType(),
3588 getValue(I.getOperand(1)),
3589 getValue(I.getOperand(2)));
3592 setValue(&I, result);
3596 /// ExpandPowI - Expand a llvm.powi intrinsic.
3597 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3598 SelectionDAG &DAG) {
3599 // If RHS is a constant, we can expand this out to a multiplication tree,
3600 // otherwise we end up lowering to a call to __powidf2 (for example). When
3601 // optimizing for size, we only want to do this if the expansion would produce
3602 // a small number of multiplies, otherwise we do the full expansion.
3603 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3604 // Get the exponent as a positive value.
3605 unsigned Val = RHSC->getSExtValue();
3606 if ((int)Val < 0) Val = -Val;
3608 // powi(x, 0) -> 1.0
3610 return DAG.getConstantFP(1.0, LHS.getValueType());
3612 const Function *F = DAG.getMachineFunction().getFunction();
3613 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3614 // If optimizing for size, don't insert too many multiplies. This
3615 // inserts up to 5 multiplies.
3616 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3617 // We use the simple binary decomposition method to generate the multiply
3618 // sequence. There are more optimal ways to do this (for example,
3619 // powi(x,15) generates one more multiply than it should), but this has
3620 // the benefit of being both really simple and much better than a libcall.
3621 SDValue Res; // Logically starts equal to 1.0
3622 SDValue CurSquare = LHS;
3626 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3628 Res = CurSquare; // 1.0*CurSquare.
3631 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3632 CurSquare, CurSquare);
3636 // If the original was negative, invert the result, producing 1/(x*x*x).
3637 if (RHSC->getSExtValue() < 0)
3638 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3639 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3644 // Otherwise, expand to a libcall.
3645 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3649 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3650 /// we want to emit this as a call to a named external function, return the name
3651 /// otherwise lower it and return null.
3653 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3654 DebugLoc dl = getCurDebugLoc();
3657 switch (Intrinsic) {
3659 // By default, turn this into a target intrinsic node.
3660 visitTargetIntrinsic(I, Intrinsic);
3662 case Intrinsic::vastart: visitVAStart(I); return 0;
3663 case Intrinsic::vaend: visitVAEnd(I); return 0;
3664 case Intrinsic::vacopy: visitVACopy(I); return 0;
3665 case Intrinsic::returnaddress:
3666 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3667 getValue(I.getOperand(1))));
3669 case Intrinsic::frameaddress:
3670 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3671 getValue(I.getOperand(1))));
3673 case Intrinsic::setjmp:
3674 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3675 case Intrinsic::longjmp:
3676 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3677 case Intrinsic::memcpy: {
3678 // Assert for address < 256 since we support only user defined address
3680 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3682 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3684 "Unknown address space");
3685 SDValue Op1 = getValue(I.getOperand(1));
3686 SDValue Op2 = getValue(I.getOperand(2));
3687 SDValue Op3 = getValue(I.getOperand(3));
3688 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3689 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3690 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
3691 I.getOperand(1), 0, I.getOperand(2), 0));
3694 case Intrinsic::memset: {
3695 // Assert for address < 256 since we support only user defined address
3697 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3699 "Unknown address space");
3700 SDValue Op1 = getValue(I.getOperand(1));
3701 SDValue Op2 = getValue(I.getOperand(2));
3702 SDValue Op3 = getValue(I.getOperand(3));
3703 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3704 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3705 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3706 I.getOperand(1), 0));
3709 case Intrinsic::memmove: {
3710 // Assert for address < 256 since we support only user defined address
3712 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3714 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3716 "Unknown address space");
3717 SDValue Op1 = getValue(I.getOperand(1));
3718 SDValue Op2 = getValue(I.getOperand(2));
3719 SDValue Op3 = getValue(I.getOperand(3));
3720 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3721 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3723 // If the source and destination are known to not be aliases, we can
3724 // lower memmove as memcpy.
3725 uint64_t Size = -1ULL;
3726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3727 Size = C->getZExtValue();
3728 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3729 AliasAnalysis::NoAlias) {
3730 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3731 false, I.getOperand(1), 0, I.getOperand(2), 0));
3735 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3736 I.getOperand(1), 0, I.getOperand(2), 0));
3739 case Intrinsic::dbg_declare: {
3740 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None.
3741 // The real handling of this intrinsic is in FastISel.
3742 if (OptLevel != CodeGenOpt::None)
3743 // FIXME: Variable debug info is not supported here.
3745 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3746 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3749 MDNode *Variable = DI.getVariable();
3750 const Value *Address = DI.getAddress();
3753 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3754 Address = BCI->getOperand(0);
3755 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3756 // Don't handle byval struct arguments or VLAs, for example.
3759 DenseMap<const AllocaInst*, int>::iterator SI =
3760 FuncInfo.StaticAllocaMap.find(AI);
3761 if (SI == FuncInfo.StaticAllocaMap.end())
3763 int FI = SI->second;
3765 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3766 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3767 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3770 case Intrinsic::dbg_value: {
3771 const DbgValueInst &DI = cast<DbgValueInst>(I);
3772 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3775 MDNode *Variable = DI.getVariable();
3776 uint64_t Offset = DI.getOffset();
3777 const Value *V = DI.getValue();
3781 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
3782 // but do not always have a corresponding SDNode built. The SDNodeOrder
3783 // absolute, but not relative, values are different depending on whether
3784 // debug info exists.
3786 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
3787 DAG.AddDbgValue(DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder));
3789 SDValue &N = NodeMap[V];
3791 DAG.AddDbgValue(DAG.getDbgValue(Variable, N.getNode(),
3792 N.getResNo(), Offset, dl, SDNodeOrder),
3795 // We may expand this to cover more cases. One case where we have no
3796 // data available is an unreferenced parameter; we need this fallback.
3797 DAG.AddDbgValue(DAG.getDbgValue(Variable,
3798 UndefValue::get(V->getType()),
3799 Offset, dl, SDNodeOrder));
3802 // Build a debug info table entry.
3803 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
3804 V = BCI->getOperand(0);
3805 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
3806 // Don't handle byval struct arguments or VLAs, for example.
3809 DenseMap<const AllocaInst*, int>::iterator SI =
3810 FuncInfo.StaticAllocaMap.find(AI);
3811 if (SI == FuncInfo.StaticAllocaMap.end())
3813 int FI = SI->second;
3815 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3816 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3817 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3820 case Intrinsic::eh_exception: {
3821 // Insert the EXCEPTIONADDR instruction.
3822 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3823 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3825 Ops[0] = DAG.getRoot();
3826 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3828 DAG.setRoot(Op.getValue(1));
3832 case Intrinsic::eh_selector: {
3833 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3834 if (CurMBB->isLandingPad())
3835 AddCatchInfo(I, &MMI, CurMBB);
3838 FuncInfo.CatchInfoLost.insert(&I);
3840 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3841 unsigned Reg = TLI.getExceptionSelectorRegister();
3842 if (Reg) CurMBB->addLiveIn(Reg);
3845 // Insert the EHSELECTION instruction.
3846 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3848 Ops[0] = getValue(I.getOperand(1));
3850 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3851 DAG.setRoot(Op.getValue(1));
3852 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
3856 case Intrinsic::eh_typeid_for: {
3857 // Find the type id for the given typeinfo.
3858 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3859 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
3860 Res = DAG.getConstant(TypeID, MVT::i32);
3865 case Intrinsic::eh_return_i32:
3866 case Intrinsic::eh_return_i64:
3867 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
3868 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3871 getValue(I.getOperand(1)),
3872 getValue(I.getOperand(2))));
3874 case Intrinsic::eh_unwind_init:
3875 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
3877 case Intrinsic::eh_dwarf_cfa: {
3878 EVT VT = getValue(I.getOperand(1)).getValueType();
3879 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
3880 TLI.getPointerTy());
3881 SDValue Offset = DAG.getNode(ISD::ADD, dl,
3883 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
3884 TLI.getPointerTy()),
3886 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
3888 DAG.getConstant(0, TLI.getPointerTy()));
3889 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
3893 case Intrinsic::eh_sjlj_callsite: {
3894 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3895 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
3896 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
3897 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
3899 MMI.setCurrentCallSite(CI->getZExtValue());
3903 case Intrinsic::convertff:
3904 case Intrinsic::convertfsi:
3905 case Intrinsic::convertfui:
3906 case Intrinsic::convertsif:
3907 case Intrinsic::convertuif:
3908 case Intrinsic::convertss:
3909 case Intrinsic::convertsu:
3910 case Intrinsic::convertus:
3911 case Intrinsic::convertuu: {
3912 ISD::CvtCode Code = ISD::CVT_INVALID;
3913 switch (Intrinsic) {
3914 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
3915 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
3916 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
3917 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
3918 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
3919 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
3920 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
3921 case Intrinsic::convertus: Code = ISD::CVT_US; break;
3922 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
3924 EVT DestVT = TLI.getValueType(I.getType());
3925 const Value *Op1 = I.getOperand(1);
3926 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
3927 DAG.getValueType(DestVT),
3928 DAG.getValueType(getValue(Op1).getValueType()),
3929 getValue(I.getOperand(2)),
3930 getValue(I.getOperand(3)),
3935 case Intrinsic::sqrt:
3936 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
3937 getValue(I.getOperand(1)).getValueType(),
3938 getValue(I.getOperand(1))));
3940 case Intrinsic::powi:
3941 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)),
3942 getValue(I.getOperand(2)), DAG));
3944 case Intrinsic::sin:
3945 setValue(&I, DAG.getNode(ISD::FSIN, dl,
3946 getValue(I.getOperand(1)).getValueType(),
3947 getValue(I.getOperand(1))));
3949 case Intrinsic::cos:
3950 setValue(&I, DAG.getNode(ISD::FCOS, dl,
3951 getValue(I.getOperand(1)).getValueType(),
3952 getValue(I.getOperand(1))));
3954 case Intrinsic::log:
3957 case Intrinsic::log2:
3960 case Intrinsic::log10:
3963 case Intrinsic::exp:
3966 case Intrinsic::exp2:
3969 case Intrinsic::pow:
3972 case Intrinsic::convert_to_fp16:
3973 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
3974 MVT::i16, getValue(I.getOperand(1))));
3976 case Intrinsic::convert_from_fp16:
3977 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
3978 MVT::f32, getValue(I.getOperand(1))));
3980 case Intrinsic::pcmarker: {
3981 SDValue Tmp = getValue(I.getOperand(1));
3982 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
3985 case Intrinsic::readcyclecounter: {
3986 SDValue Op = getRoot();
3987 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
3988 DAG.getVTList(MVT::i64, MVT::Other),
3991 DAG.setRoot(Res.getValue(1));
3994 case Intrinsic::bswap:
3995 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
3996 getValue(I.getOperand(1)).getValueType(),
3997 getValue(I.getOperand(1))));
3999 case Intrinsic::cttz: {
4000 SDValue Arg = getValue(I.getOperand(1));
4001 EVT Ty = Arg.getValueType();
4002 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4005 case Intrinsic::ctlz: {
4006 SDValue Arg = getValue(I.getOperand(1));
4007 EVT Ty = Arg.getValueType();
4008 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4011 case Intrinsic::ctpop: {
4012 SDValue Arg = getValue(I.getOperand(1));
4013 EVT Ty = Arg.getValueType();
4014 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4017 case Intrinsic::stacksave: {
4018 SDValue Op = getRoot();
4019 Res = DAG.getNode(ISD::STACKSAVE, dl,
4020 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4022 DAG.setRoot(Res.getValue(1));
4025 case Intrinsic::stackrestore: {
4026 Res = getValue(I.getOperand(1));
4027 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4030 case Intrinsic::stackprotector: {
4031 // Emit code into the DAG to store the stack guard onto the stack.
4032 MachineFunction &MF = DAG.getMachineFunction();
4033 MachineFrameInfo *MFI = MF.getFrameInfo();
4034 EVT PtrTy = TLI.getPointerTy();
4036 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4037 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4039 int FI = FuncInfo.StaticAllocaMap[Slot];
4040 MFI->setStackProtectorIndex(FI);
4042 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4044 // Store the stack protector onto the stack.
4045 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4046 PseudoSourceValue::getFixedStack(FI),
4052 case Intrinsic::objectsize: {
4053 // If we don't know by now, we're never going to know.
4054 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4056 assert(CI && "Non-constant type in __builtin_object_size?");
4058 SDValue Arg = getValue(I.getOperand(0));
4059 EVT Ty = Arg.getValueType();
4061 if (CI->getZExtValue() == 0)
4062 Res = DAG.getConstant(-1ULL, Ty);
4064 Res = DAG.getConstant(0, Ty);
4069 case Intrinsic::var_annotation:
4070 // Discard annotate attributes
4073 case Intrinsic::init_trampoline: {
4074 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4078 Ops[1] = getValue(I.getOperand(1));
4079 Ops[2] = getValue(I.getOperand(2));
4080 Ops[3] = getValue(I.getOperand(3));
4081 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4082 Ops[5] = DAG.getSrcValue(F);
4084 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4085 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4089 DAG.setRoot(Res.getValue(1));
4092 case Intrinsic::gcroot:
4094 const Value *Alloca = I.getOperand(1);
4095 const Constant *TypeMap = cast<Constant>(I.getOperand(2));
4097 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4098 GFI->addStackRoot(FI->getIndex(), TypeMap);
4101 case Intrinsic::gcread:
4102 case Intrinsic::gcwrite:
4103 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4105 case Intrinsic::flt_rounds:
4106 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4108 case Intrinsic::trap:
4109 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4111 case Intrinsic::uadd_with_overflow:
4112 return implVisitAluOverflow(I, ISD::UADDO);
4113 case Intrinsic::sadd_with_overflow:
4114 return implVisitAluOverflow(I, ISD::SADDO);
4115 case Intrinsic::usub_with_overflow:
4116 return implVisitAluOverflow(I, ISD::USUBO);
4117 case Intrinsic::ssub_with_overflow:
4118 return implVisitAluOverflow(I, ISD::SSUBO);
4119 case Intrinsic::umul_with_overflow:
4120 return implVisitAluOverflow(I, ISD::UMULO);
4121 case Intrinsic::smul_with_overflow:
4122 return implVisitAluOverflow(I, ISD::SMULO);
4124 case Intrinsic::prefetch: {
4127 Ops[1] = getValue(I.getOperand(1));
4128 Ops[2] = getValue(I.getOperand(2));
4129 Ops[3] = getValue(I.getOperand(3));
4130 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4134 case Intrinsic::memory_barrier: {
4137 for (int x = 1; x < 6; ++x)
4138 Ops[x] = getValue(I.getOperand(x));
4140 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4143 case Intrinsic::atomic_cmp_swap: {
4144 SDValue Root = getRoot();
4146 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4147 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4149 getValue(I.getOperand(1)),
4150 getValue(I.getOperand(2)),
4151 getValue(I.getOperand(3)),
4154 DAG.setRoot(L.getValue(1));
4157 case Intrinsic::atomic_load_add:
4158 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4159 case Intrinsic::atomic_load_sub:
4160 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4161 case Intrinsic::atomic_load_or:
4162 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4163 case Intrinsic::atomic_load_xor:
4164 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4165 case Intrinsic::atomic_load_and:
4166 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4167 case Intrinsic::atomic_load_nand:
4168 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4169 case Intrinsic::atomic_load_max:
4170 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4171 case Intrinsic::atomic_load_min:
4172 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4173 case Intrinsic::atomic_load_umin:
4174 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4175 case Intrinsic::atomic_load_umax:
4176 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4177 case Intrinsic::atomic_swap:
4178 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4180 case Intrinsic::invariant_start:
4181 case Intrinsic::lifetime_start:
4182 // Discard region information.
4183 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4185 case Intrinsic::invariant_end:
4186 case Intrinsic::lifetime_end:
4187 // Discard region information.
4192 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4194 MachineBasicBlock *LandingPad) {
4195 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4196 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4197 const Type *RetTy = FTy->getReturnType();
4198 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4199 MCSymbol *BeginLabel = 0;
4201 TargetLowering::ArgListTy Args;
4202 TargetLowering::ArgListEntry Entry;
4203 Args.reserve(CS.arg_size());
4205 // Check whether the function can return without sret-demotion.
4206 SmallVector<EVT, 4> OutVTs;
4207 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4208 SmallVector<uint64_t, 4> Offsets;
4209 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4210 OutVTs, OutsFlags, TLI, &Offsets);
4212 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4213 FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4215 SDValue DemoteStackSlot;
4217 if (!CanLowerReturn) {
4218 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4219 FTy->getReturnType());
4220 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4221 FTy->getReturnType());
4222 MachineFunction &MF = DAG.getMachineFunction();
4223 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4224 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4226 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4227 Entry.Node = DemoteStackSlot;
4228 Entry.Ty = StackSlotPtrType;
4229 Entry.isSExt = false;
4230 Entry.isZExt = false;
4231 Entry.isInReg = false;
4232 Entry.isSRet = true;
4233 Entry.isNest = false;
4234 Entry.isByVal = false;
4235 Entry.Alignment = Align;
4236 Args.push_back(Entry);
4237 RetTy = Type::getVoidTy(FTy->getContext());
4240 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4242 SDValue ArgNode = getValue(*i);
4243 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4245 unsigned attrInd = i - CS.arg_begin() + 1;
4246 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4247 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4248 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4249 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4250 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4251 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4252 Entry.Alignment = CS.getParamAlignment(attrInd);
4253 Args.push_back(Entry);
4257 // Insert a label before the invoke call to mark the try range. This can be
4258 // used to detect deletion of the invoke via the MachineModuleInfo.
4259 BeginLabel = MMI.getContext().CreateTempSymbol();
4261 // For SjLj, keep track of which landing pads go with which invokes
4262 // so as to maintain the ordering of pads in the LSDA.
4263 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4264 if (CallSiteIndex) {
4265 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4266 // Now that the call site is handled, stop tracking it.
4267 MMI.setCurrentCallSite(0);
4270 // Both PendingLoads and PendingExports must be flushed here;
4271 // this call might not return.
4273 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4276 // Check if target-independent constraints permit a tail call here.
4277 // Target-dependent constraints are checked within TLI.LowerCallTo.
4279 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4282 std::pair<SDValue,SDValue> Result =
4283 TLI.LowerCallTo(getRoot(), RetTy,
4284 CS.paramHasAttr(0, Attribute::SExt),
4285 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4286 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4287 CS.getCallingConv(),
4289 !CS.getInstruction()->use_empty(),
4290 Callee, Args, DAG, getCurDebugLoc());
4291 assert((isTailCall || Result.second.getNode()) &&
4292 "Non-null chain expected with non-tail call!");
4293 assert((Result.second.getNode() || !Result.first.getNode()) &&
4294 "Null value expected with tail call!");
4295 if (Result.first.getNode()) {
4296 setValue(CS.getInstruction(), Result.first);
4297 } else if (!CanLowerReturn && Result.second.getNode()) {
4298 // The instruction result is the result of loading from the
4299 // hidden sret parameter.
4300 SmallVector<EVT, 1> PVTs;
4301 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4303 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4304 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4305 EVT PtrVT = PVTs[0];
4306 unsigned NumValues = OutVTs.size();
4307 SmallVector<SDValue, 4> Values(NumValues);
4308 SmallVector<SDValue, 4> Chains(NumValues);
4310 for (unsigned i = 0; i < NumValues; ++i) {
4311 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4313 DAG.getConstant(Offsets[i], PtrVT));
4314 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4315 Add, NULL, Offsets[i], false, false, 1);
4317 Chains[i] = L.getValue(1);
4320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4321 MVT::Other, &Chains[0], NumValues);
4322 PendingLoads.push_back(Chain);
4324 // Collect the legal value parts into potentially illegal values
4325 // that correspond to the original function's return values.
4326 SmallVector<EVT, 4> RetTys;
4327 RetTy = FTy->getReturnType();
4328 ComputeValueVTs(TLI, RetTy, RetTys);
4329 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4330 SmallVector<SDValue, 4> ReturnValues;
4331 unsigned CurReg = 0;
4332 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4334 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4335 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4337 SDValue ReturnValue =
4338 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4339 RegisterVT, VT, AssertOp);
4340 ReturnValues.push_back(ReturnValue);
4344 setValue(CS.getInstruction(),
4345 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4346 DAG.getVTList(&RetTys[0], RetTys.size()),
4347 &ReturnValues[0], ReturnValues.size()));
4351 // As a special case, a null chain means that a tail call has been emitted and
4352 // the DAG root is already updated.
4353 if (Result.second.getNode())
4354 DAG.setRoot(Result.second);
4359 // Insert a label at the end of the invoke call to mark the try range. This
4360 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4361 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4362 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4364 // Inform MachineModuleInfo of range.
4365 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4369 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4370 /// value is equal or not-equal to zero.
4371 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4372 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4374 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4375 if (IC->isEquality())
4376 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4377 if (C->isNullValue())
4379 // Unknown instruction.
4385 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4387 SelectionDAGBuilder &Builder) {
4389 // Check to see if this load can be trivially constant folded, e.g. if the
4390 // input is from a string literal.
4391 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4392 // Cast pointer to the type we really want to load.
4393 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4394 PointerType::getUnqual(LoadTy));
4396 if (const Constant *LoadCst =
4397 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4399 return Builder.getValue(LoadCst);
4402 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4403 // still constant memory, the input chain can be the entry node.
4405 bool ConstantMemory = false;
4407 // Do not serialize (non-volatile) loads of constant memory with anything.
4408 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4409 Root = Builder.DAG.getEntryNode();
4410 ConstantMemory = true;
4412 // Do not serialize non-volatile loads against each other.
4413 Root = Builder.DAG.getRoot();
4416 SDValue Ptr = Builder.getValue(PtrVal);
4417 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4418 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4420 false /*nontemporal*/, 1 /* align=1 */);
4422 if (!ConstantMemory)
4423 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4428 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4429 /// If so, return true and lower it, otherwise return false and it will be
4430 /// lowered like a normal call.
4431 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4432 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4433 if (I.getNumOperands() != 4)
4436 const Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
4437 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4438 !I.getOperand(3)->getType()->isIntegerTy() ||
4439 !I.getType()->isIntegerTy())
4442 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
4444 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4445 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4446 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4447 bool ActuallyDoIt = true;
4450 switch (Size->getZExtValue()) {
4452 LoadVT = MVT::Other;
4454 ActuallyDoIt = false;
4458 LoadTy = Type::getInt16Ty(Size->getContext());
4462 LoadTy = Type::getInt32Ty(Size->getContext());
4466 LoadTy = Type::getInt64Ty(Size->getContext());
4470 LoadVT = MVT::v4i32;
4471 LoadTy = Type::getInt32Ty(Size->getContext());
4472 LoadTy = VectorType::get(LoadTy, 4);
4477 // This turns into unaligned loads. We only do this if the target natively
4478 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4479 // we'll only produce a small number of byte loads.
4481 // Require that we can find a legal MVT, and only do this if the target
4482 // supports unaligned loads of that type. Expanding into byte loads would
4484 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4485 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4486 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4487 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4488 ActuallyDoIt = false;
4492 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4493 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4495 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4497 EVT CallVT = TLI.getValueType(I.getType(), true);
4498 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4508 void SelectionDAGBuilder::visitCall(const CallInst &I) {
4509 const char *RenameFn = 0;
4510 if (Function *F = I.getCalledFunction()) {
4511 if (F->isDeclaration()) {
4512 const TargetIntrinsicInfo *II = TM.getIntrinsicInfo();
4514 if (unsigned IID = II->getIntrinsicID(F)) {
4515 RenameFn = visitIntrinsicCall(I, IID);
4520 if (unsigned IID = F->getIntrinsicID()) {
4521 RenameFn = visitIntrinsicCall(I, IID);
4527 // Check for well-known libc/libm calls. If the function is internal, it
4528 // can't be a library call.
4529 if (!F->hasLocalLinkage() && F->hasName()) {
4530 StringRef Name = F->getName();
4531 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
4532 if (I.getNumOperands() == 3 && // Basic sanity checks.
4533 I.getOperand(1)->getType()->isFloatingPointTy() &&
4534 I.getType() == I.getOperand(1)->getType() &&
4535 I.getType() == I.getOperand(2)->getType()) {
4536 SDValue LHS = getValue(I.getOperand(1));
4537 SDValue RHS = getValue(I.getOperand(2));
4538 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4539 LHS.getValueType(), LHS, RHS));
4542 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4543 if (I.getNumOperands() == 2 && // Basic sanity checks.
4544 I.getOperand(1)->getType()->isFloatingPointTy() &&
4545 I.getType() == I.getOperand(1)->getType()) {
4546 SDValue Tmp = getValue(I.getOperand(1));
4547 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4548 Tmp.getValueType(), Tmp));
4551 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4552 if (I.getNumOperands() == 2 && // Basic sanity checks.
4553 I.getOperand(1)->getType()->isFloatingPointTy() &&
4554 I.getType() == I.getOperand(1)->getType() &&
4555 I.onlyReadsMemory()) {
4556 SDValue Tmp = getValue(I.getOperand(1));
4557 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4558 Tmp.getValueType(), Tmp));
4561 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4562 if (I.getNumOperands() == 2 && // Basic sanity checks.
4563 I.getOperand(1)->getType()->isFloatingPointTy() &&
4564 I.getType() == I.getOperand(1)->getType() &&
4565 I.onlyReadsMemory()) {
4566 SDValue Tmp = getValue(I.getOperand(1));
4567 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4568 Tmp.getValueType(), Tmp));
4571 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4572 if (I.getNumOperands() == 2 && // Basic sanity checks.
4573 I.getOperand(1)->getType()->isFloatingPointTy() &&
4574 I.getType() == I.getOperand(1)->getType() &&
4575 I.onlyReadsMemory()) {
4576 SDValue Tmp = getValue(I.getOperand(1));
4577 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4578 Tmp.getValueType(), Tmp));
4581 } else if (Name == "memcmp") {
4582 if (visitMemCmpCall(I))
4586 } else if (isa<InlineAsm>(I.getOperand(0))) {
4593 Callee = getValue(I.getOperand(0));
4595 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4597 // Check if we can potentially perform a tail call. More detailed checking is
4598 // be done within LowerCallTo, after more information about the call is known.
4599 LowerCallTo(&I, Callee, I.isTailCall());
4602 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4603 /// this value and returns the result as a ValueVT value. This uses
4604 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4605 /// If the Flag pointer is NULL, no flag is used.
4606 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4607 SDValue &Chain, SDValue *Flag) const {
4608 // Assemble the legal parts into the final values.
4609 SmallVector<SDValue, 4> Values(ValueVTs.size());
4610 SmallVector<SDValue, 8> Parts;
4611 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4612 // Copy the legal parts from the registers.
4613 EVT ValueVT = ValueVTs[Value];
4614 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4615 EVT RegisterVT = RegVTs[Value];
4617 Parts.resize(NumRegs);
4618 for (unsigned i = 0; i != NumRegs; ++i) {
4621 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4623 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4624 *Flag = P.getValue(2);
4627 Chain = P.getValue(1);
4629 // If the source register was virtual and if we know something about it,
4630 // add an assert node.
4631 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4632 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4633 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4634 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4635 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4636 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4638 unsigned RegSize = RegisterVT.getSizeInBits();
4639 unsigned NumSignBits = LOI.NumSignBits;
4640 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4642 // FIXME: We capture more information than the dag can represent. For
4643 // now, just use the tightest assertzext/assertsext possible.
4645 EVT FromVT(MVT::Other);
4646 if (NumSignBits == RegSize)
4647 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4648 else if (NumZeroBits >= RegSize-1)
4649 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4650 else if (NumSignBits > RegSize-8)
4651 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4652 else if (NumZeroBits >= RegSize-8)
4653 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4654 else if (NumSignBits > RegSize-16)
4655 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4656 else if (NumZeroBits >= RegSize-16)
4657 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4658 else if (NumSignBits > RegSize-32)
4659 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4660 else if (NumZeroBits >= RegSize-32)
4661 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4663 if (FromVT != MVT::Other)
4664 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4665 RegisterVT, P, DAG.getValueType(FromVT));
4672 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4673 NumRegs, RegisterVT, ValueVT);
4678 return DAG.getNode(ISD::MERGE_VALUES, dl,
4679 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4680 &Values[0], ValueVTs.size());
4683 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4684 /// specified value into the registers specified by this object. This uses
4685 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4686 /// If the Flag pointer is NULL, no flag is used.
4687 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4688 SDValue &Chain, SDValue *Flag) const {
4689 // Get the list of the values's legal parts.
4690 unsigned NumRegs = Regs.size();
4691 SmallVector<SDValue, 8> Parts(NumRegs);
4692 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4693 EVT ValueVT = ValueVTs[Value];
4694 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4695 EVT RegisterVT = RegVTs[Value];
4697 getCopyToParts(DAG, dl,
4698 Val.getValue(Val.getResNo() + Value),
4699 &Parts[Part], NumParts, RegisterVT);
4703 // Copy the parts into the registers.
4704 SmallVector<SDValue, 8> Chains(NumRegs);
4705 for (unsigned i = 0; i != NumRegs; ++i) {
4708 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4710 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4711 *Flag = Part.getValue(1);
4714 Chains[i] = Part.getValue(0);
4717 if (NumRegs == 1 || Flag)
4718 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4719 // flagged to it. That is the CopyToReg nodes and the user are considered
4720 // a single scheduling unit. If we create a TokenFactor and return it as
4721 // chain, then the TokenFactor is both a predecessor (operand) of the
4722 // user as well as a successor (the TF operands are flagged to the user).
4723 // c1, f1 = CopyToReg
4724 // c2, f2 = CopyToReg
4725 // c3 = TokenFactor c1, c2
4728 Chain = Chains[NumRegs-1];
4730 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4733 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4734 /// operand list. This adds the code marker and includes the number of
4735 /// values added into it.
4736 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
4737 unsigned MatchingIdx,
4739 std::vector<SDValue> &Ops) const {
4740 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
4742 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
4743 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
4746 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4747 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4748 EVT RegisterVT = RegVTs[Value];
4749 for (unsigned i = 0; i != NumRegs; ++i) {
4750 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4751 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4756 /// isAllocatableRegister - If the specified register is safe to allocate,
4757 /// i.e. it isn't a stack pointer or some other special register, return the
4758 /// register class for the register. Otherwise, return null.
4759 static const TargetRegisterClass *
4760 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4761 const TargetLowering &TLI,
4762 const TargetRegisterInfo *TRI) {
4763 EVT FoundVT = MVT::Other;
4764 const TargetRegisterClass *FoundRC = 0;
4765 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4766 E = TRI->regclass_end(); RCI != E; ++RCI) {
4767 EVT ThisVT = MVT::Other;
4769 const TargetRegisterClass *RC = *RCI;
4770 // If none of the value types for this register class are valid, we
4771 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4772 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4774 if (TLI.isTypeLegal(*I)) {
4775 // If we have already found this register in a different register class,
4776 // choose the one with the largest VT specified. For example, on
4777 // PowerPC, we favor f64 register classes over f32.
4778 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4785 if (ThisVT == MVT::Other) continue;
4787 // NOTE: This isn't ideal. In particular, this might allocate the
4788 // frame pointer in functions that need it (due to them not being taken
4789 // out of allocation, because a variable sized allocation hasn't been seen
4790 // yet). This is a slight code pessimization, but should still work.
4791 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4792 E = RC->allocation_order_end(MF); I != E; ++I)
4794 // We found a matching register class. Keep looking at others in case
4795 // we find one with larger registers that this physreg is also in.
4806 /// AsmOperandInfo - This contains information for each constraint that we are
4808 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4809 public TargetLowering::AsmOperandInfo {
4811 /// CallOperand - If this is the result output operand or a clobber
4812 /// this is null, otherwise it is the incoming operand to the CallInst.
4813 /// This gets modified as the asm is processed.
4814 SDValue CallOperand;
4816 /// AssignedRegs - If this is a register or register class operand, this
4817 /// contains the set of register corresponding to the operand.
4818 RegsForValue AssignedRegs;
4820 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4821 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4824 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4825 /// busy in OutputRegs/InputRegs.
4826 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4827 std::set<unsigned> &OutputRegs,
4828 std::set<unsigned> &InputRegs,
4829 const TargetRegisterInfo &TRI) const {
4831 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4832 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4835 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4836 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4840 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4841 /// corresponds to. If there is no Value* for this operand, it returns
4843 EVT getCallOperandValEVT(LLVMContext &Context,
4844 const TargetLowering &TLI,
4845 const TargetData *TD) const {
4846 if (CallOperandVal == 0) return MVT::Other;
4848 if (isa<BasicBlock>(CallOperandVal))
4849 return TLI.getPointerTy();
4851 const llvm::Type *OpTy = CallOperandVal->getType();
4853 // If this is an indirect operand, the operand is a pointer to the
4856 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4858 report_fatal_error("Indirect operand for inline asm not a pointer!");
4859 OpTy = PtrTy->getElementType();
4862 // If OpTy is not a single value, it may be a struct/union that we
4863 // can tile with integers.
4864 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4865 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4874 OpTy = IntegerType::get(Context, BitSize);
4879 return TLI.getValueType(OpTy, true);
4883 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4885 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4886 const TargetRegisterInfo &TRI) {
4887 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4889 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4890 for (; *Aliases; ++Aliases)
4891 Regs.insert(*Aliases);
4894 } // end llvm namespace.
4897 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4898 /// specified operand. We prefer to assign virtual registers, to allow the
4899 /// register allocator to handle the assignment process. However, if the asm
4900 /// uses features that we can't model on machineinstrs, we have SDISel do the
4901 /// allocation. This produces generally horrible, but correct, code.
4903 /// OpInfo describes the operand.
4904 /// Input and OutputRegs are the set of already allocated physical registers.
4906 void SelectionDAGBuilder::
4907 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4908 std::set<unsigned> &OutputRegs,
4909 std::set<unsigned> &InputRegs) {
4910 LLVMContext &Context = FuncInfo.Fn->getContext();
4912 // Compute whether this value requires an input register, an output register,
4914 bool isOutReg = false;
4915 bool isInReg = false;
4916 switch (OpInfo.Type) {
4917 case InlineAsm::isOutput:
4920 // If there is an input constraint that matches this, we need to reserve
4921 // the input register so no other inputs allocate to it.
4922 isInReg = OpInfo.hasMatchingInput();
4924 case InlineAsm::isInput:
4928 case InlineAsm::isClobber:
4935 MachineFunction &MF = DAG.getMachineFunction();
4936 SmallVector<unsigned, 4> Regs;
4938 // If this is a constraint for a single physreg, or a constraint for a
4939 // register class, find it.
4940 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4941 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4942 OpInfo.ConstraintVT);
4944 unsigned NumRegs = 1;
4945 if (OpInfo.ConstraintVT != MVT::Other) {
4946 // If this is a FP input in an integer register (or visa versa) insert a bit
4947 // cast of the input value. More generally, handle any case where the input
4948 // value disagrees with the register class we plan to stick this in.
4949 if (OpInfo.Type == InlineAsm::isInput &&
4950 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4951 // Try to convert to the first EVT that the reg class contains. If the
4952 // types are identical size, use a bitcast to convert (e.g. two differing
4954 EVT RegVT = *PhysReg.second->vt_begin();
4955 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4956 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4957 RegVT, OpInfo.CallOperand);
4958 OpInfo.ConstraintVT = RegVT;
4959 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4960 // If the input is a FP value and we want it in FP registers, do a
4961 // bitcast to the corresponding integer type. This turns an f64 value
4962 // into i64, which can be passed with two i32 values on a 32-bit
4964 RegVT = EVT::getIntegerVT(Context,
4965 OpInfo.ConstraintVT.getSizeInBits());
4966 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4967 RegVT, OpInfo.CallOperand);
4968 OpInfo.ConstraintVT = RegVT;
4972 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
4976 EVT ValueVT = OpInfo.ConstraintVT;
4978 // If this is a constraint for a specific physical register, like {r17},
4980 if (unsigned AssignedReg = PhysReg.first) {
4981 const TargetRegisterClass *RC = PhysReg.second;
4982 if (OpInfo.ConstraintVT == MVT::Other)
4983 ValueVT = *RC->vt_begin();
4985 // Get the actual register value type. This is important, because the user
4986 // may have asked for (e.g.) the AX register in i32 type. We need to
4987 // remember that AX is actually i16 to get the right extension.
4988 RegVT = *RC->vt_begin();
4990 // This is a explicit reference to a physical register.
4991 Regs.push_back(AssignedReg);
4993 // If this is an expanded reference, add the rest of the regs to Regs.
4995 TargetRegisterClass::iterator I = RC->begin();
4996 for (; *I != AssignedReg; ++I)
4997 assert(I != RC->end() && "Didn't find reg!");
4999 // Already added the first reg.
5001 for (; NumRegs; --NumRegs, ++I) {
5002 assert(I != RC->end() && "Ran out of registers to allocate!");
5007 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5008 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5009 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5013 // Otherwise, if this was a reference to an LLVM register class, create vregs
5014 // for this reference.
5015 if (const TargetRegisterClass *RC = PhysReg.second) {
5016 RegVT = *RC->vt_begin();
5017 if (OpInfo.ConstraintVT == MVT::Other)
5020 // Create the appropriate number of virtual registers.
5021 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5022 for (; NumRegs; --NumRegs)
5023 Regs.push_back(RegInfo.createVirtualRegister(RC));
5025 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5029 // This is a reference to a register class that doesn't directly correspond
5030 // to an LLVM register class. Allocate NumRegs consecutive, available,
5031 // registers from the class.
5032 std::vector<unsigned> RegClassRegs
5033 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5034 OpInfo.ConstraintVT);
5036 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5037 unsigned NumAllocated = 0;
5038 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5039 unsigned Reg = RegClassRegs[i];
5040 // See if this register is available.
5041 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5042 (isInReg && InputRegs.count(Reg))) { // Already used.
5043 // Make sure we find consecutive registers.
5048 // Check to see if this register is allocatable (i.e. don't give out the
5050 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5051 if (!RC) { // Couldn't allocate this register.
5052 // Reset NumAllocated to make sure we return consecutive registers.
5057 // Okay, this register is good, we can use it.
5060 // If we allocated enough consecutive registers, succeed.
5061 if (NumAllocated == NumRegs) {
5062 unsigned RegStart = (i-NumAllocated)+1;
5063 unsigned RegEnd = i+1;
5064 // Mark all of the allocated registers used.
5065 for (unsigned i = RegStart; i != RegEnd; ++i)
5066 Regs.push_back(RegClassRegs[i]);
5068 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5069 OpInfo.ConstraintVT);
5070 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5075 // Otherwise, we couldn't allocate enough registers for this.
5078 /// visitInlineAsm - Handle a call to an InlineAsm object.
5080 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5081 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5083 /// ConstraintOperands - Information about all of the constraints.
5084 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5086 std::set<unsigned> OutputRegs, InputRegs;
5088 // Do a prepass over the constraints, canonicalizing them, and building up the
5089 // ConstraintOperands list.
5090 std::vector<InlineAsm::ConstraintInfo>
5091 ConstraintInfos = IA->ParseConstraints();
5093 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5095 SDValue Chain, Flag;
5097 // We won't need to flush pending loads if this asm doesn't touch
5098 // memory and is nonvolatile.
5099 if (hasMemory || IA->hasSideEffects())
5102 Chain = DAG.getRoot();
5104 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5105 unsigned ResNo = 0; // ResNo - The result number of the next output.
5106 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5107 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5108 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5110 EVT OpVT = MVT::Other;
5112 // Compute the value type for each operand.
5113 switch (OpInfo.Type) {
5114 case InlineAsm::isOutput:
5115 // Indirect outputs just consume an argument.
5116 if (OpInfo.isIndirect) {
5117 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5121 // The return value of the call is this value. As such, there is no
5122 // corresponding argument.
5123 assert(!CS.getType()->isVoidTy() &&
5125 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5126 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5128 assert(ResNo == 0 && "Asm only has one result!");
5129 OpVT = TLI.getValueType(CS.getType());
5133 case InlineAsm::isInput:
5134 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5136 case InlineAsm::isClobber:
5141 // If this is an input or an indirect output, process the call argument.
5142 // BasicBlocks are labels, currently appearing only in asm's.
5143 if (OpInfo.CallOperandVal) {
5144 // Strip bitcasts, if any. This mostly comes up for functions.
5145 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5147 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5148 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5150 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5153 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5156 OpInfo.ConstraintVT = OpVT;
5159 // Second pass over the constraints: compute which constraint option to use
5160 // and assign registers to constraints that want a specific physreg.
5161 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5162 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5164 // If this is an output operand with a matching input operand, look up the
5165 // matching input. If their types mismatch, e.g. one is an integer, the
5166 // other is floating point, or their sizes are different, flag it as an
5168 if (OpInfo.hasMatchingInput()) {
5169 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5171 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5172 if ((OpInfo.ConstraintVT.isInteger() !=
5173 Input.ConstraintVT.isInteger()) ||
5174 (OpInfo.ConstraintVT.getSizeInBits() !=
5175 Input.ConstraintVT.getSizeInBits())) {
5176 report_fatal_error("Unsupported asm: input constraint"
5177 " with a matching output constraint of"
5178 " incompatible type!");
5180 Input.ConstraintVT = OpInfo.ConstraintVT;
5184 // Compute the constraint code and ConstraintType to use.
5185 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5187 // If this is a memory input, and if the operand is not indirect, do what we
5188 // need to to provide an address for the memory input.
5189 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5190 !OpInfo.isIndirect) {
5191 assert(OpInfo.Type == InlineAsm::isInput &&
5192 "Can only indirectify direct input operands!");
5194 // Memory operands really want the address of the value. If we don't have
5195 // an indirect input, put it in the constpool if we can, otherwise spill
5196 // it to a stack slot.
5198 // If the operand is a float, integer, or vector constant, spill to a
5199 // constant pool entry to get its address.
5200 const Value *OpVal = OpInfo.CallOperandVal;
5201 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5202 isa<ConstantVector>(OpVal)) {
5203 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5204 TLI.getPointerTy());
5206 // Otherwise, create a stack slot and emit a store to it before the
5208 const Type *Ty = OpVal->getType();
5209 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5210 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5211 MachineFunction &MF = DAG.getMachineFunction();
5212 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5213 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5214 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5215 OpInfo.CallOperand, StackSlot, NULL, 0,
5217 OpInfo.CallOperand = StackSlot;
5220 // There is no longer a Value* corresponding to this operand.
5221 OpInfo.CallOperandVal = 0;
5223 // It is now an indirect operand.
5224 OpInfo.isIndirect = true;
5227 // If this constraint is for a specific register, allocate it before
5229 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5230 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5233 ConstraintInfos.clear();
5235 // Second pass - Loop over all of the operands, assigning virtual or physregs
5236 // to register class operands.
5237 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5238 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5240 // C_Register operands have already been allocated, Other/Memory don't need
5242 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5243 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5246 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5247 std::vector<SDValue> AsmNodeOperands;
5248 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5249 AsmNodeOperands.push_back(
5250 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5251 TLI.getPointerTy()));
5253 // If we have a !srcloc metadata node associated with it, we want to attach
5254 // this to the ultimately generated inline asm machineinstr. To do this, we
5255 // pass in the third operand as this (potentially null) inline asm MDNode.
5256 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5257 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5259 // Loop over all of the inputs, copying the operand values into the
5260 // appropriate registers and processing the output regs.
5261 RegsForValue RetValRegs;
5263 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5264 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5266 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5267 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5269 switch (OpInfo.Type) {
5270 case InlineAsm::isOutput: {
5271 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5272 OpInfo.ConstraintType != TargetLowering::C_Register) {
5273 // Memory output, or 'other' output (e.g. 'X' constraint).
5274 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5276 // Add information to the INLINEASM node to know about this output.
5277 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5278 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5279 TLI.getPointerTy()));
5280 AsmNodeOperands.push_back(OpInfo.CallOperand);
5284 // Otherwise, this is a register or register class output.
5286 // Copy the output from the appropriate register. Find a register that
5288 if (OpInfo.AssignedRegs.Regs.empty())
5289 report_fatal_error("Couldn't allocate output reg for constraint '" +
5290 Twine(OpInfo.ConstraintCode) + "'!");
5292 // If this is an indirect operand, store through the pointer after the
5294 if (OpInfo.isIndirect) {
5295 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5296 OpInfo.CallOperandVal));
5298 // This is the result value of the call.
5299 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5300 // Concatenate this output onto the outputs list.
5301 RetValRegs.append(OpInfo.AssignedRegs);
5304 // Add information to the INLINEASM node to know that this register is
5306 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5307 InlineAsm::Kind_RegDefEarlyClobber :
5308 InlineAsm::Kind_RegDef,
5315 case InlineAsm::isInput: {
5316 SDValue InOperandVal = OpInfo.CallOperand;
5318 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5319 // If this is required to match an output register we have already set,
5320 // just use its register.
5321 unsigned OperandNo = OpInfo.getMatchedOperand();
5323 // Scan until we find the definition we already emitted of this operand.
5324 // When we find it, create a RegsForValue operand.
5325 unsigned CurOp = InlineAsm::Op_FirstOperand;
5326 for (; OperandNo; --OperandNo) {
5327 // Advance to the next operand.
5329 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5330 assert((InlineAsm::isRegDefKind(OpFlag) ||
5331 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5332 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5333 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5337 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5338 if (InlineAsm::isRegDefKind(OpFlag) ||
5339 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5340 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5341 if (OpInfo.isIndirect) {
5342 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5343 LLVMContext &Ctx = CurMBB->getParent()->getFunction()->getContext();
5344 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5345 " don't know how to handle tied "
5346 "indirect register inputs");
5349 RegsForValue MatchedRegs;
5350 MatchedRegs.TLI = &TLI;
5351 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5352 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5353 MatchedRegs.RegVTs.push_back(RegVT);
5354 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5355 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5357 MatchedRegs.Regs.push_back
5358 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5360 // Use the produced MatchedRegs object to
5361 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5363 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5364 true, OpInfo.getMatchedOperand(),
5365 DAG, AsmNodeOperands);
5369 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5370 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5371 "Unexpected number of operands");
5372 // Add information to the INLINEASM node to know about this input.
5373 // See InlineAsm.h isUseOperandTiedToDef.
5374 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5375 OpInfo.getMatchedOperand());
5376 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5377 TLI.getPointerTy()));
5378 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5382 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5383 assert(!OpInfo.isIndirect &&
5384 "Don't know how to handle indirect other inputs yet!");
5386 std::vector<SDValue> Ops;
5387 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5388 hasMemory, Ops, DAG);
5390 report_fatal_error("Invalid operand for inline asm constraint '" +
5391 Twine(OpInfo.ConstraintCode) + "'!");
5393 // Add information to the INLINEASM node to know about this input.
5394 unsigned ResOpType =
5395 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5396 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5397 TLI.getPointerTy()));
5398 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5402 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5403 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5404 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5405 "Memory operands expect pointer values");
5407 // Add information to the INLINEASM node to know about this input.
5408 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5409 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5410 TLI.getPointerTy()));
5411 AsmNodeOperands.push_back(InOperandVal);
5415 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5416 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5417 "Unknown constraint type!");
5418 assert(!OpInfo.isIndirect &&
5419 "Don't know how to handle indirect register inputs yet!");
5421 // Copy the input into the appropriate registers.
5422 if (OpInfo.AssignedRegs.Regs.empty() ||
5423 !OpInfo.AssignedRegs.areValueTypesLegal())
5424 report_fatal_error("Couldn't allocate input reg for constraint '" +
5425 Twine(OpInfo.ConstraintCode) + "'!");
5427 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5430 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5431 DAG, AsmNodeOperands);
5434 case InlineAsm::isClobber: {
5435 // Add the clobbered value to the operand list, so that the register
5436 // allocator is aware that the physreg got clobbered.
5437 if (!OpInfo.AssignedRegs.Regs.empty())
5438 OpInfo.AssignedRegs.AddInlineAsmOperands(
5439 InlineAsm::Kind_RegDefEarlyClobber,
5447 // Finish up input operands. Set the input chain and add the flag last.
5448 AsmNodeOperands[0] = Chain;
5449 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5451 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5452 DAG.getVTList(MVT::Other, MVT::Flag),
5453 &AsmNodeOperands[0], AsmNodeOperands.size());
5454 Flag = Chain.getValue(1);
5456 // If this asm returns a register value, copy the result from that register
5457 // and set it as the value of the call.
5458 if (!RetValRegs.Regs.empty()) {
5459 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5462 // FIXME: Why don't we do this for inline asms with MRVs?
5463 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5464 EVT ResultType = TLI.getValueType(CS.getType());
5466 // If any of the results of the inline asm is a vector, it may have the
5467 // wrong width/num elts. This can happen for register classes that can
5468 // contain multiple different value types. The preg or vreg allocated may
5469 // not have the same VT as was expected. Convert it to the right type
5470 // with bit_convert.
5471 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5472 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5475 } else if (ResultType != Val.getValueType() &&
5476 ResultType.isInteger() && Val.getValueType().isInteger()) {
5477 // If a result value was tied to an input value, the computed result may
5478 // have a wider width than the expected result. Extract the relevant
5480 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5483 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5486 setValue(CS.getInstruction(), Val);
5487 // Don't need to use this as a chain in this case.
5488 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5492 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5494 // Process indirect outputs, first output all of the flagged copies out of
5496 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5497 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5498 const Value *Ptr = IndirectStoresToEmit[i].second;
5499 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5501 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5504 // Emit the non-flagged stores from the physregs.
5505 SmallVector<SDValue, 8> OutChains;
5506 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5507 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5508 StoresToEmit[i].first,
5509 getValue(StoresToEmit[i].second),
5510 StoresToEmit[i].second, 0,
5512 OutChains.push_back(Val);
5515 if (!OutChains.empty())
5516 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5517 &OutChains[0], OutChains.size());
5522 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5523 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5524 MVT::Other, getRoot(),
5525 getValue(I.getOperand(1)),
5526 DAG.getSrcValue(I.getOperand(1))));
5529 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5530 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5531 getRoot(), getValue(I.getOperand(0)),
5532 DAG.getSrcValue(I.getOperand(0)));
5534 DAG.setRoot(V.getValue(1));
5537 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5538 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5539 MVT::Other, getRoot(),
5540 getValue(I.getOperand(1)),
5541 DAG.getSrcValue(I.getOperand(1))));
5544 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5545 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5546 MVT::Other, getRoot(),
5547 getValue(I.getOperand(1)),
5548 getValue(I.getOperand(2)),
5549 DAG.getSrcValue(I.getOperand(1)),
5550 DAG.getSrcValue(I.getOperand(2))));
5553 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5554 /// implementation, which just calls LowerCall.
5555 /// FIXME: When all targets are
5556 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5557 std::pair<SDValue, SDValue>
5558 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5559 bool RetSExt, bool RetZExt, bool isVarArg,
5560 bool isInreg, unsigned NumFixedArgs,
5561 CallingConv::ID CallConv, bool isTailCall,
5562 bool isReturnValueUsed,
5564 ArgListTy &Args, SelectionDAG &DAG,
5565 DebugLoc dl) const {
5566 // Handle all of the outgoing arguments.
5567 SmallVector<ISD::OutputArg, 32> Outs;
5568 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5569 SmallVector<EVT, 4> ValueVTs;
5570 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5571 for (unsigned Value = 0, NumValues = ValueVTs.size();
5572 Value != NumValues; ++Value) {
5573 EVT VT = ValueVTs[Value];
5574 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5575 SDValue Op = SDValue(Args[i].Node.getNode(),
5576 Args[i].Node.getResNo() + Value);
5577 ISD::ArgFlagsTy Flags;
5578 unsigned OriginalAlignment =
5579 getTargetData()->getABITypeAlignment(ArgTy);
5585 if (Args[i].isInReg)
5589 if (Args[i].isByVal) {
5591 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5592 const Type *ElementTy = Ty->getElementType();
5593 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5594 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5595 // For ByVal, alignment should come from FE. BE will guess if this
5596 // info is not there but there are cases it cannot get right.
5597 if (Args[i].Alignment)
5598 FrameAlign = Args[i].Alignment;
5599 Flags.setByValAlign(FrameAlign);
5600 Flags.setByValSize(FrameSize);
5604 Flags.setOrigAlign(OriginalAlignment);
5606 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5607 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5608 SmallVector<SDValue, 4> Parts(NumParts);
5609 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5612 ExtendKind = ISD::SIGN_EXTEND;
5613 else if (Args[i].isZExt)
5614 ExtendKind = ISD::ZERO_EXTEND;
5616 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5617 PartVT, ExtendKind);
5619 for (unsigned j = 0; j != NumParts; ++j) {
5620 // if it isn't first piece, alignment must be 1
5621 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5622 if (NumParts > 1 && j == 0)
5623 MyFlags.Flags.setSplit();
5625 MyFlags.Flags.setOrigAlign(1);
5627 Outs.push_back(MyFlags);
5632 // Handle the incoming return values from the call.
5633 SmallVector<ISD::InputArg, 32> Ins;
5634 SmallVector<EVT, 4> RetTys;
5635 ComputeValueVTs(*this, RetTy, RetTys);
5636 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5638 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5639 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5640 for (unsigned i = 0; i != NumRegs; ++i) {
5641 ISD::InputArg MyFlags;
5642 MyFlags.VT = RegisterVT;
5643 MyFlags.Used = isReturnValueUsed;
5645 MyFlags.Flags.setSExt();
5647 MyFlags.Flags.setZExt();
5649 MyFlags.Flags.setInReg();
5650 Ins.push_back(MyFlags);
5654 SmallVector<SDValue, 4> InVals;
5655 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5656 Outs, Ins, dl, DAG, InVals);
5658 // Verify that the target's LowerCall behaved as expected.
5659 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5660 "LowerCall didn't return a valid chain!");
5661 assert((!isTailCall || InVals.empty()) &&
5662 "LowerCall emitted a return value for a tail call!");
5663 assert((isTailCall || InVals.size() == Ins.size()) &&
5664 "LowerCall didn't emit the correct number of values!");
5666 // For a tail call, the return value is merely live-out and there aren't
5667 // any nodes in the DAG representing it. Return a special value to
5668 // indicate that a tail call has been emitted and no more Instructions
5669 // should be processed in the current block.
5672 return std::make_pair(SDValue(), SDValue());
5675 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5676 assert(InVals[i].getNode() &&
5677 "LowerCall emitted a null value!");
5678 assert(Ins[i].VT == InVals[i].getValueType() &&
5679 "LowerCall emitted a value with the wrong type!");
5682 // Collect the legal value parts into potentially illegal values
5683 // that correspond to the original function's return values.
5684 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5686 AssertOp = ISD::AssertSext;
5688 AssertOp = ISD::AssertZext;
5689 SmallVector<SDValue, 4> ReturnValues;
5690 unsigned CurReg = 0;
5691 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5693 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5694 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5696 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5697 NumRegs, RegisterVT, VT,
5702 // For a function returning void, there is no return value. We can't create
5703 // such a node, so we just return a null return value in that case. In
5704 // that case, nothing will actualy look at the value.
5705 if (ReturnValues.empty())
5706 return std::make_pair(SDValue(), Chain);
5708 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5709 DAG.getVTList(&RetTys[0], RetTys.size()),
5710 &ReturnValues[0], ReturnValues.size());
5711 return std::make_pair(Res, Chain);
5714 void TargetLowering::LowerOperationWrapper(SDNode *N,
5715 SmallVectorImpl<SDValue> &Results,
5716 SelectionDAG &DAG) const {
5717 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5719 Results.push_back(Res);
5722 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5723 llvm_unreachable("LowerOperation not implemented for this target!");
5728 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
5729 SDValue Op = getValue(V);
5730 assert((Op.getOpcode() != ISD::CopyFromReg ||
5731 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5732 "Copy from a reg to the same reg!");
5733 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5735 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5736 SDValue Chain = DAG.getEntryNode();
5737 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5738 PendingExports.push_back(Chain);
5741 #include "llvm/CodeGen/SelectionDAGISel.h"
5743 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
5744 // If this is the entry block, emit arguments.
5745 const Function &F = *LLVMBB->getParent();
5746 SelectionDAG &DAG = SDB->DAG;
5747 SDValue OldRoot = DAG.getRoot();
5748 DebugLoc dl = SDB->getCurDebugLoc();
5749 const TargetData *TD = TLI.getTargetData();
5750 SmallVector<ISD::InputArg, 16> Ins;
5752 // Check whether the function can return without sret-demotion.
5753 SmallVector<EVT, 4> OutVTs;
5754 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
5755 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5756 OutVTs, OutsFlags, TLI);
5757 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5759 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
5760 OutVTs, OutsFlags, DAG);
5761 if (!FLI.CanLowerReturn) {
5762 // Put in an sret pointer parameter before all the other parameters.
5763 SmallVector<EVT, 1> ValueVTs;
5764 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5766 // NOTE: Assuming that a pointer will never break down to more than one VT
5768 ISD::ArgFlagsTy Flags;
5770 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]);
5771 ISD::InputArg RetArg(Flags, RegisterVT, true);
5772 Ins.push_back(RetArg);
5775 // Set up the incoming argument description vector.
5777 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
5778 I != E; ++I, ++Idx) {
5779 SmallVector<EVT, 4> ValueVTs;
5780 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5781 bool isArgValueUsed = !I->use_empty();
5782 for (unsigned Value = 0, NumValues = ValueVTs.size();
5783 Value != NumValues; ++Value) {
5784 EVT VT = ValueVTs[Value];
5785 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5786 ISD::ArgFlagsTy Flags;
5787 unsigned OriginalAlignment =
5788 TD->getABITypeAlignment(ArgTy);
5790 if (F.paramHasAttr(Idx, Attribute::ZExt))
5792 if (F.paramHasAttr(Idx, Attribute::SExt))
5794 if (F.paramHasAttr(Idx, Attribute::InReg))
5796 if (F.paramHasAttr(Idx, Attribute::StructRet))
5798 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5800 const PointerType *Ty = cast<PointerType>(I->getType());
5801 const Type *ElementTy = Ty->getElementType();
5802 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5803 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5804 // For ByVal, alignment should be passed from FE. BE will guess if
5805 // this info is not there but there are cases it cannot get right.
5806 if (F.getParamAlignment(Idx))
5807 FrameAlign = F.getParamAlignment(Idx);
5808 Flags.setByValAlign(FrameAlign);
5809 Flags.setByValSize(FrameSize);
5811 if (F.paramHasAttr(Idx, Attribute::Nest))
5813 Flags.setOrigAlign(OriginalAlignment);
5815 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5816 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5817 for (unsigned i = 0; i != NumRegs; ++i) {
5818 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5819 if (NumRegs > 1 && i == 0)
5820 MyFlags.Flags.setSplit();
5821 // if it isn't first piece, alignment must be 1
5823 MyFlags.Flags.setOrigAlign(1);
5824 Ins.push_back(MyFlags);
5829 // Call the target to set up the argument values.
5830 SmallVector<SDValue, 8> InVals;
5831 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5835 // Verify that the target's LowerFormalArguments behaved as expected.
5836 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5837 "LowerFormalArguments didn't return a valid chain!");
5838 assert(InVals.size() == Ins.size() &&
5839 "LowerFormalArguments didn't emit the correct number of values!");
5841 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5842 assert(InVals[i].getNode() &&
5843 "LowerFormalArguments emitted a null value!");
5844 assert(Ins[i].VT == InVals[i].getValueType() &&
5845 "LowerFormalArguments emitted a value with the wrong type!");
5849 // Update the DAG with the new chain value resulting from argument lowering.
5850 DAG.setRoot(NewRoot);
5852 // Set up the argument values.
5855 if (!FLI.CanLowerReturn) {
5856 // Create a virtual register for the sret pointer, and put in a copy
5857 // from the sret argument into it.
5858 SmallVector<EVT, 1> ValueVTs;
5859 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5860 EVT VT = ValueVTs[0];
5861 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5862 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5863 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
5864 RegVT, VT, AssertOp);
5866 MachineFunction& MF = SDB->DAG.getMachineFunction();
5867 MachineRegisterInfo& RegInfo = MF.getRegInfo();
5868 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
5869 FLI.DemoteRegister = SRetReg;
5870 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
5872 DAG.setRoot(NewRoot);
5874 // i indexes lowered arguments. Bump it past the hidden sret argument.
5875 // Idx indexes LLVM arguments. Don't touch it.
5879 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5881 SmallVector<SDValue, 4> ArgValues;
5882 SmallVector<EVT, 4> ValueVTs;
5883 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5884 unsigned NumValues = ValueVTs.size();
5885 for (unsigned Value = 0; Value != NumValues; ++Value) {
5886 EVT VT = ValueVTs[Value];
5887 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5888 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5890 if (!I->use_empty()) {
5891 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5892 if (F.paramHasAttr(Idx, Attribute::SExt))
5893 AssertOp = ISD::AssertSext;
5894 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5895 AssertOp = ISD::AssertZext;
5897 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
5898 NumParts, PartVT, VT,
5905 if (!I->use_empty()) {
5907 if (!ArgValues.empty())
5908 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
5909 SDB->getCurDebugLoc());
5910 SDB->setValue(I, Res);
5912 // If this argument is live outside of the entry block, insert a copy from
5913 // whereever we got it to the vreg that other BB's will reference it as.
5914 SDB->CopyToExportRegsIfNeeded(I);
5918 assert(i == InVals.size() && "Argument register count mismatch!");
5920 // Finally, if the target has anything special to do, allow it to do so.
5921 // FIXME: this should insert code into the DAG!
5922 EmitFunctionEntryCode();
5925 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5926 /// ensure constants are generated when needed. Remember the virtual registers
5927 /// that need to be added to the Machine PHI nodes as input. We cannot just
5928 /// directly add them, because expansion might result in multiple MBB's for one
5929 /// BB. As such, the start of the BB might correspond to a different MBB than
5933 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
5934 const TerminatorInst *TI = LLVMBB->getTerminator();
5936 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5938 // Check successor nodes' PHI nodes that expect a constant to be available
5940 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5941 const BasicBlock *SuccBB = TI->getSuccessor(succ);
5942 if (!isa<PHINode>(SuccBB->begin())) continue;
5943 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5945 // If this terminator has multiple identical successors (common for
5946 // switches), only handle each succ once.
5947 if (!SuccsHandled.insert(SuccMBB)) continue;
5949 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5951 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5952 // nodes and Machine PHI nodes, but the incoming operands have not been
5954 for (BasicBlock::const_iterator I = SuccBB->begin();
5955 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
5956 // Ignore dead phi's.
5957 if (PN->use_empty()) continue;
5960 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5962 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
5963 unsigned &RegOut = SDB->ConstantsOut[C];
5965 RegOut = FuncInfo->CreateRegForValue(C);
5966 SDB->CopyValueToVirtualRegister(C, RegOut);
5970 Reg = FuncInfo->ValueMap[PHIOp];
5972 assert(isa<AllocaInst>(PHIOp) &&
5973 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5974 "Didn't codegen value into a register!??");
5975 Reg = FuncInfo->CreateRegForValue(PHIOp);
5976 SDB->CopyValueToVirtualRegister(PHIOp, Reg);
5980 // Remember that this register needs to added to the machine PHI node as
5981 // the input for this MBB.
5982 SmallVector<EVT, 4> ValueVTs;
5983 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5984 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5985 EVT VT = ValueVTs[vti];
5986 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5987 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5988 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5989 Reg += NumRegisters;
5993 SDB->ConstantsOut.clear();
5996 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5997 /// supports legal types, and it emits MachineInstrs directly instead of
5998 /// creating SelectionDAG nodes.
6001 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(const BasicBlock *LLVMBB,
6003 const TerminatorInst *TI = LLVMBB->getTerminator();
6005 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6006 unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
6008 // Check successor nodes' PHI nodes that expect a constant to be available
6010 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6011 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6012 if (!isa<PHINode>(SuccBB->begin())) continue;
6013 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6015 // If this terminator has multiple identical successors (common for
6016 // switches), only handle each succ once.
6017 if (!SuccsHandled.insert(SuccMBB)) continue;
6019 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6021 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6022 // nodes and Machine PHI nodes, but the incoming operands have not been
6024 for (BasicBlock::const_iterator I = SuccBB->begin();
6025 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6026 // Ignore dead phi's.
6027 if (PN->use_empty()) continue;
6029 // Only handle legal types. Two interesting things to note here. First,
6030 // by bailing out early, we may leave behind some dead instructions,
6031 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6032 // own moves. Second, this check is necessary becuase FastISel doesn't
6033 // use CreateRegForValue to create registers, so it always creates
6034 // exactly one register for each non-void instruction.
6035 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6036 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6039 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6041 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6046 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6048 unsigned Reg = F->getRegForValue(PHIOp);
6050 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6053 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));