1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
65 #define DEBUG_TYPE "isel"
67 /// LimitFloatPrecision - Generate low-precision inline sequences for
68 /// some float libcalls (6, 8 or 12 bits).
69 static unsigned LimitFloatPrecision;
71 static cl::opt<unsigned, true>
72 LimitFPPrecision("limit-float-precision",
73 cl::desc("Generate low-precision inline sequences "
74 "for some float libcalls"),
75 cl::location(LimitFloatPrecision),
78 // Limit the width of DAG chains. This is important in general to prevent
79 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // load clustering may not complete in reasonable time. It is difficult to
81 // recognize and avoid this situation within each individual analysis, and
82 // future analyses are likely to have the same behavior. Limiting DAG width is
83 // the safe approach, and will be especially important with global DAGs.
85 // MaxParallelChains default is arbitrarily high to avoid affecting
86 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
87 // sequence over this should have been converted to llvm.memcpy by the
88 // frontend. It easy to induce this behavior with .ll code such as:
89 // %buffer = alloca [4096 x i8]
90 // %data = load [4096 x i8]* %argPtr
91 // store [4096 x i8] %data, [4096 x i8]* %buffer
92 static const unsigned MaxParallelChains = 64;
94 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
95 const SDValue *Parts, unsigned NumParts,
96 MVT PartVT, EVT ValueVT, const Value *V);
98 /// getCopyFromParts - Create a value that contains the specified legal parts
99 /// combined into the value they represent. If the parts combine to a type
100 /// larger then ValueVT then AssertOp can be used to specify whether the extra
101 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 /// (ISD::AssertSext).
103 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts,
105 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
108 if (ValueVT.isVector())
109 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
112 assert(NumParts > 0 && "No parts to assemble!");
113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
114 SDValue Val = Parts[0];
117 // Assemble the value from multiple parts.
118 if (ValueVT.isInteger()) {
119 unsigned PartBits = PartVT.getSizeInBits();
120 unsigned ValueBits = ValueVT.getSizeInBits();
122 // Assemble the power of 2 part.
123 unsigned RoundParts = NumParts & (NumParts - 1) ?
124 1 << Log2_32(NumParts) : NumParts;
125 unsigned RoundBits = PartBits * RoundParts;
126 EVT RoundVT = RoundBits == ValueBits ?
127 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
130 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
132 if (RoundParts > 2) {
133 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
135 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
136 RoundParts / 2, PartVT, HalfVT, V);
138 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 if (TLI.isBigEndian())
145 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
147 if (RoundParts < NumParts) {
148 // Assemble the trailing non-power-of-2 part.
149 unsigned OddParts = NumParts - RoundParts;
150 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
151 Hi = getCopyFromParts(DAG, DL,
152 Parts + RoundParts, OddParts, PartVT, OddVT, V);
154 // Combine the round and odd parts.
156 if (TLI.isBigEndian())
158 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
159 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
160 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
161 DAG.getConstant(Lo.getValueType().getSizeInBits(),
162 TLI.getPointerTy()));
163 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
164 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
166 } else if (PartVT.isFloatingPoint()) {
167 // FP split into multiple FP parts (for ppcf128)
168 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
171 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
172 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
173 if (TLI.hasBigEndianPartOrdering(ValueVT))
175 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
177 // FP split into integer parts (soft fp)
178 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
179 !PartVT.isVector() && "Unexpected split");
180 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
181 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 // There is now one part, held in Val. Correct it to match ValueVT.
186 EVT PartEVT = Val.getValueType();
188 if (PartEVT == ValueVT)
191 if (PartEVT.isInteger() && ValueVT.isInteger()) {
192 if (ValueVT.bitsLT(PartEVT)) {
193 // For a truncate, see if we have any information to
194 // indicate whether the truncated bits will always be
195 // zero or sign-extension.
196 if (AssertOp != ISD::DELETED_NODE)
197 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
198 DAG.getValueType(ValueVT));
199 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
201 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
204 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
205 // FP_ROUND's are always exact here.
206 if (ValueVT.bitsLT(Val.getValueType()))
207 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
208 DAG.getTargetConstant(1, TLI.getPointerTy()));
210 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
214 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
216 llvm_unreachable("Unknown mismatch!");
219 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
220 const Twine &ErrMsg) {
221 const Instruction *I = dyn_cast_or_null<Instruction>(V);
223 return Ctx.emitError(ErrMsg);
225 const char *AsmError = ", possible invalid constraint for vector type";
226 if (const CallInst *CI = dyn_cast<CallInst>(I))
227 if (isa<InlineAsm>(CI->getCalledValue()))
228 return Ctx.emitError(I, ErrMsg + AsmError);
230 return Ctx.emitError(I, ErrMsg);
233 /// getCopyFromPartsVector - Create a value that contains the specified legal
234 /// parts combined into the value they represent. If the parts combine to a
235 /// type larger then ValueVT then AssertOp can be used to specify whether the
236 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
237 /// ValueVT (ISD::AssertSext).
238 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
239 const SDValue *Parts, unsigned NumParts,
240 MVT PartVT, EVT ValueVT, const Value *V) {
241 assert(ValueVT.isVector() && "Not a vector value");
242 assert(NumParts > 0 && "No parts to assemble!");
243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
244 SDValue Val = Parts[0];
246 // Handle a multi-element vector.
250 unsigned NumIntermediates;
252 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
253 NumIntermediates, RegisterVT);
254 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
255 NumParts = NumRegs; // Silence a compiler warning.
256 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
257 assert(RegisterVT == Parts[0].getSimpleValueType() &&
258 "Part type doesn't match part!");
260 // Assemble the parts into intermediate operands.
261 SmallVector<SDValue, 8> Ops(NumIntermediates);
262 if (NumIntermediates == NumParts) {
263 // If the register was not expanded, truncate or copy the value,
265 for (unsigned i = 0; i != NumParts; ++i)
266 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
267 PartVT, IntermediateVT, V);
268 } else if (NumParts > 0) {
269 // If the intermediate type was expanded, build the intermediate
270 // operands from the parts.
271 assert(NumParts % NumIntermediates == 0 &&
272 "Must expand into a divisible number of parts!");
273 unsigned Factor = NumParts / NumIntermediates;
274 for (unsigned i = 0; i != NumIntermediates; ++i)
275 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
276 PartVT, IntermediateVT, V);
279 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 // intermediate operands.
281 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
286 // There is now one part, held in Val. Correct it to match ValueVT.
287 EVT PartEVT = Val.getValueType();
289 if (PartEVT == ValueVT)
292 if (PartEVT.isVector()) {
293 // If the element type of the source/dest vectors are the same, but the
294 // parts vector has more elements than the value vector, then we have a
295 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
297 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
298 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
299 "Cannot narrow, it would be a lossy transformation");
300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
301 DAG.getConstant(0, TLI.getVectorIdxTy()));
304 // Vector/Vector bitcast.
305 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
306 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
308 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
309 "Cannot handle this kind of promotion");
310 // Promoted vector extract
311 bool Smaller = ValueVT.bitsLE(PartEVT);
312 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
317 // Trivial bitcast if the types are the same size and the destination
318 // vector type is legal.
319 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
320 TLI.isTypeLegal(ValueVT))
321 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
323 // Handle cases such as i8 -> <1 x i1>
324 if (ValueVT.getVectorNumElements() != 1) {
325 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
326 "non-trivial scalar-to-vector conversion");
327 return DAG.getUNDEF(ValueVT);
330 if (ValueVT.getVectorNumElements() == 1 &&
331 ValueVT.getVectorElementType() != PartEVT) {
332 bool Smaller = ValueVT.bitsLE(PartEVT);
333 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
334 DL, ValueVT.getScalarType(), Val);
337 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
340 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
341 SDValue Val, SDValue *Parts, unsigned NumParts,
342 MVT PartVT, const Value *V);
344 /// getCopyToParts - Create a series of nodes that contain the specified value
345 /// split into legal parts. If the parts contain more bits than Val, then, for
346 /// integers, ExtendKind can be used to specify how to generate the extra bits.
347 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V,
350 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
351 EVT ValueVT = Val.getValueType();
353 // Handle the vector case separately.
354 if (ValueVT.isVector())
355 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 unsigned PartBits = PartVT.getSizeInBits();
359 unsigned OrigNumParts = NumParts;
360 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
366 EVT PartEVT = PartVT;
367 if (PartEVT == ValueVT) {
368 assert(NumParts == 1 && "No-op copy with multiple parts!");
373 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
374 // If the parts cover more bits than the value has, promote the value.
375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
376 assert(NumParts == 1 && "Do not know what to promote to!");
377 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
379 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
380 ValueVT.isInteger() &&
381 "Unknown mismatch!");
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
384 if (PartVT == MVT::x86mmx)
385 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
387 } else if (PartBits == ValueVT.getSizeInBits()) {
388 // Different types of the same size.
389 assert(NumParts == 1 && PartEVT != ValueVT);
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
392 // If the parts cover less bits than value has, truncate the value.
393 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
394 ValueVT.isInteger() &&
395 "Unknown mismatch!");
396 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
397 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
398 if (PartVT == MVT::x86mmx)
399 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
402 // The value may have changed - recompute ValueVT.
403 ValueVT = Val.getValueType();
404 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
405 "Failed to tile the value with PartVT!");
408 if (PartEVT != ValueVT)
409 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
410 "scalar-to-vector conversion failed");
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getConstant(i,
494 TLI.getVectorIdxTy())));
496 for (unsigned i = ValueVT.getVectorNumElements(),
497 e = PartVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getUNDEF(ElementVT));
500 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
502 // FIXME: Use CONCAT for 2x -> 4x.
504 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
505 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType().bitsGE(
508 ValueVT.getVectorElementType()) &&
509 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
511 // Promoted vector extract
512 bool Smaller = PartEVT.bitsLE(ValueVT);
513 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
516 // Vector -> scalar conversion.
517 assert(ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
520 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
522 bool Smaller = ValueVT.bitsLE(PartVT);
523 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
531 // Handle a multi-element vector.
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
537 NumIntermediates, RegisterVT);
538 unsigned NumElements = ValueVT.getVectorNumElements();
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
542 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
544 // Split the vector into intermediate operands.
545 SmallVector<SDValue, 8> Ops(NumIntermediates);
546 for (unsigned i = 0; i != NumIntermediates; ++i) {
547 if (IntermediateVT.isVector())
548 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
550 DAG.getConstant(i * (NumElements / NumIntermediates),
551 TLI.getVectorIdxTy()));
553 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
555 DAG.getConstant(i, TLI.getVectorIdxTy()));
558 // Split the intermediate operands into legal parts.
559 if (NumParts == NumIntermediates) {
560 // If the register was not expanded, promote or copy the value,
562 for (unsigned i = 0; i != NumParts; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
564 } else if (NumParts > 0) {
565 // If the intermediate type was expanded, split each the value into
567 assert(NumParts % NumIntermediates == 0 &&
568 "Must expand into a divisible number of parts!");
569 unsigned Factor = NumParts / NumIntermediates;
570 for (unsigned i = 0; i != NumIntermediates; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 /// RegsForValue - This struct represents the registers (physical or virtual)
577 /// that a particular set of values is assigned, and the type information
578 /// about the value. The most common situation is to represent one value at a
579 /// time, but struct or array values are handled element-wise as multiple
580 /// values. The splitting of aggregates is performed recursively, so that we
581 /// never have aggregate-typed registers. The values at this point do not
582 /// necessarily have legal types, so each value may require one or more
583 /// registers of some legal type.
585 struct RegsForValue {
586 /// ValueVTs - The value types of the values, which may not be legal, and
587 /// may need be promoted or synthesized from one or more registers.
589 SmallVector<EVT, 4> ValueVTs;
591 /// RegVTs - The value types of the registers. This is the same size as
592 /// ValueVTs and it records, for each value, what the type of the assigned
593 /// register or registers are. (Individual values are never synthesized
594 /// from more than one type of register.)
596 /// With virtual registers, the contents of RegVTs is redundant with TLI's
597 /// getRegisterType member function, however when with physical registers
598 /// it is necessary to have a separate record of the types.
600 SmallVector<MVT, 4> RegVTs;
602 /// Regs - This list holds the registers assigned to the values.
603 /// Each legal or promoted value requires one register, and each
604 /// expanded value requires multiple registers.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
614 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
615 unsigned Reg, Type *Ty) {
616 ComputeValueVTs(tli, Ty, ValueVTs);
618 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
623 Regs.push_back(Reg + i);
624 RegVTs.push_back(RegisterVT);
629 /// append - Add the specified values to this one.
630 void append(const RegsForValue &RHS) {
631 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
632 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
633 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVTs value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
642 SDValue &Chain, SDValue *Flag,
643 const Value *V = nullptr) const;
645 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
646 /// specified value into the registers specified by this object. This uses
647 /// Chain/Flag as the input and updates them for the output Chain/Flag.
648 /// If the Flag pointer is NULL, no flag is used.
650 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
651 SDValue *Flag, const Value *V,
652 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
654 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
655 /// operand list. This adds the code marker, matching input operand index
656 /// (if applicable), and includes the number of values added into it.
657 void AddInlineAsmOperands(unsigned Kind,
658 bool HasMatching, unsigned MatchingIdx,
660 std::vector<SDValue> &Ops) const;
664 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
665 /// this value and returns the result as a ValueVT value. This uses
666 /// Chain/Flag as the input and updates them for the output Chain/Flag.
667 /// If the Flag pointer is NULL, no flag is used.
668 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
669 FunctionLoweringInfo &FuncInfo,
671 SDValue &Chain, SDValue *Flag,
672 const Value *V) const {
673 // A Value with type {} or [0 x %t] needs no registers.
674 if (ValueVTs.empty())
677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 // Assemble the legal parts into the final values.
680 SmallVector<SDValue, 4> Values(ValueVTs.size());
681 SmallVector<SDValue, 8> Parts;
682 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
683 // Copy the legal parts from the registers.
684 EVT ValueVT = ValueVTs[Value];
685 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
686 MVT RegisterVT = RegVTs[Value];
688 Parts.resize(NumRegs);
689 for (unsigned i = 0; i != NumRegs; ++i) {
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
694 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
695 *Flag = P.getValue(2);
698 Chain = P.getValue(1);
701 // If the source register was virtual and if we know something about it,
702 // add an assert node.
703 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
704 !RegisterVT.isInteger() || RegisterVT.isVector())
707 const FunctionLoweringInfo::LiveOutInfo *LOI =
708 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
712 unsigned RegSize = RegisterVT.getSizeInBits();
713 unsigned NumSignBits = LOI->NumSignBits;
714 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
716 if (NumZeroBits == RegSize) {
717 // The current value is a zero.
718 // Explicitly express that as it would be easier for
719 // optimizations to kick in.
720 Parts[i] = DAG.getConstant(0, RegisterVT);
724 // FIXME: We capture more information than the dag can represent. For
725 // now, just use the tightest assertzext/assertsext possible.
727 EVT FromVT(MVT::Other);
728 if (NumSignBits == RegSize)
729 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
730 else if (NumZeroBits >= RegSize-1)
731 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
732 else if (NumSignBits > RegSize-8)
733 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
734 else if (NumZeroBits >= RegSize-8)
735 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
736 else if (NumSignBits > RegSize-16)
737 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
738 else if (NumZeroBits >= RegSize-16)
739 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
740 else if (NumSignBits > RegSize-32)
741 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
742 else if (NumZeroBits >= RegSize-32)
743 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
747 // Add an assertion node.
748 assert(FromVT != MVT::Other);
749 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
750 RegisterVT, P, DAG.getValueType(FromVT));
753 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
754 NumRegs, RegisterVT, ValueVT, V);
759 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
762 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
763 /// specified value into the registers specified by this object. This uses
764 /// Chain/Flag as the input and updates them for the output Chain/Flag.
765 /// If the Flag pointer is NULL, no flag is used.
766 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
767 SDValue &Chain, SDValue *Flag, const Value *V,
768 ISD::NodeType PreferredExtendType) const {
769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
770 ISD::NodeType ExtendKind = PreferredExtendType;
772 // Get the list of the values's legal parts.
773 unsigned NumRegs = Regs.size();
774 SmallVector<SDValue, 8> Parts(NumRegs);
775 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
776 EVT ValueVT = ValueVTs[Value];
777 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
778 MVT RegisterVT = RegVTs[Value];
780 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
781 ExtendKind = ISD::ZERO_EXTEND;
783 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
784 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
788 // Copy the parts into the registers.
789 SmallVector<SDValue, 8> Chains(NumRegs);
790 for (unsigned i = 0; i != NumRegs; ++i) {
793 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
795 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
796 *Flag = Part.getValue(1);
799 Chains[i] = Part.getValue(0);
802 if (NumRegs == 1 || Flag)
803 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
804 // flagged to it. That is the CopyToReg nodes and the user are considered
805 // a single scheduling unit. If we create a TokenFactor and return it as
806 // chain, then the TokenFactor is both a predecessor (operand) of the
807 // user as well as a successor (the TF operands are flagged to the user).
808 // c1, f1 = CopyToReg
809 // c2, f2 = CopyToReg
810 // c3 = TokenFactor c1, c2
813 Chain = Chains[NumRegs-1];
815 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
818 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
819 /// operand list. This adds the code marker and includes the number of
820 /// values added into it.
821 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
822 unsigned MatchingIdx,
824 std::vector<SDValue> &Ops) const {
825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
827 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
829 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
830 else if (!Regs.empty() &&
831 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
832 // Put the register class of the virtual registers in the flag word. That
833 // way, later passes can recompute register class constraints for inline
834 // assembly as well as normal instructions.
835 // Don't do this for tied operands that can use the regclass information
837 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
838 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
839 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
842 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
845 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
846 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
847 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
848 MVT RegisterVT = RegVTs[Value];
849 for (unsigned i = 0; i != NumRegs; ++i) {
850 assert(Reg < Regs.size() && "Mismatch in # registers expected");
851 unsigned TheReg = Regs[Reg++];
852 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
854 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
855 // If we clobbered the stack pointer, MFI should know about it.
856 assert(DAG.getMachineFunction().getFrameInfo()->
857 hasInlineAsmWithSPAdjust());
863 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
864 const TargetLibraryInfo *li) {
868 DL = DAG.getSubtarget().getDataLayout();
869 Context = DAG.getContext();
870 LPadToCallSiteMap.clear();
873 /// clear - Clear out the current SelectionDAG and the associated
874 /// state and prepare this SelectionDAGBuilder object to be used
875 /// for a new block. This doesn't clear out information about
876 /// additional blocks that are needed to complete switch lowering
877 /// or PHI node updating; that information is cleared out as it is
879 void SelectionDAGBuilder::clear() {
881 UnusedArgNodeMap.clear();
882 PendingLoads.clear();
883 PendingExports.clear();
886 SDNodeOrder = LowestSDNodeOrder;
889 /// clearDanglingDebugInfo - Clear the dangling debug information
890 /// map. This function is separated from the clear so that debug
891 /// information that is dangling in a basic block can be properly
892 /// resolved in a different basic block. This allows the
893 /// SelectionDAG to resolve dangling debug information attached
895 void SelectionDAGBuilder::clearDanglingDebugInfo() {
896 DanglingDebugInfoMap.clear();
899 /// getRoot - Return the current virtual root of the Selection DAG,
900 /// flushing any PendingLoad items. This must be done before emitting
901 /// a store or any other node that may need to be ordered after any
902 /// prior load instructions.
904 SDValue SelectionDAGBuilder::getRoot() {
905 if (PendingLoads.empty())
906 return DAG.getRoot();
908 if (PendingLoads.size() == 1) {
909 SDValue Root = PendingLoads[0];
911 PendingLoads.clear();
915 // Otherwise, we have to make a token factor node.
916 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
918 PendingLoads.clear();
923 /// getControlRoot - Similar to getRoot, but instead of flushing all the
924 /// PendingLoad items, flush all the PendingExports items. It is necessary
925 /// to do this before emitting a terminator instruction.
927 SDValue SelectionDAGBuilder::getControlRoot() {
928 SDValue Root = DAG.getRoot();
930 if (PendingExports.empty())
933 // Turn all of the CopyToReg chains into one factored node.
934 if (Root.getOpcode() != ISD::EntryToken) {
935 unsigned i = 0, e = PendingExports.size();
936 for (; i != e; ++i) {
937 assert(PendingExports[i].getNode()->getNumOperands() > 1);
938 if (PendingExports[i].getNode()->getOperand(0) == Root)
939 break; // Don't add the root if we already indirectly depend on it.
943 PendingExports.push_back(Root);
946 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
948 PendingExports.clear();
953 void SelectionDAGBuilder::visit(const Instruction &I) {
954 // Set up outgoing PHI node register values before emitting the terminator.
955 if (isa<TerminatorInst>(&I))
956 HandlePHINodesInSuccessorBlocks(I.getParent());
962 visit(I.getOpcode(), I);
964 if (!isa<TerminatorInst>(&I) && !HasTailCall)
965 CopyToExportRegsIfNeeded(&I);
970 void SelectionDAGBuilder::visitPHI(const PHINode &) {
971 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
974 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
975 // Note: this doesn't use InstVisitor, because it has to work with
976 // ConstantExpr's in addition to instructions.
978 default: llvm_unreachable("Unknown instruction type encountered!");
979 // Build the switch statement using the Instruction.def file.
980 #define HANDLE_INST(NUM, OPCODE, CLASS) \
981 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
982 #include "llvm/IR/Instruction.def"
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 MDNode *Expr = DI->getExpression();
997 uint64_t Offset = DI->getOffset();
998 // A dbg.value for an alloca is always indirect.
999 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1001 if (Val.getNode()) {
1002 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1004 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1005 IsIndirect, Offset, dl, DbgSDNodeOrder);
1006 DAG.AddDbgValue(SDV, Val.getNode(), false);
1009 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1010 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1014 /// getValue - Return an SDValue for the given Value.
1015 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it. It's important
1017 // to do this first, so that we don't create a CopyFromReg if we already
1018 // have a regular SDValue.
1019 SDValue &N = NodeMap[V];
1020 if (N.getNode()) return N;
1022 // If there's a virtual register allocated and initialized for this
1024 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(),
1028 *TM.getSubtargetImpl()->getTargetLowering(), InReg,
1030 SDValue Chain = DAG.getEntryNode();
1031 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1032 resolveDanglingDebugInfo(V, N);
1036 // Otherwise create a new SDValue and remember it.
1037 SDValue Val = getValueImpl(V);
1039 resolveDanglingDebugInfo(V, Val);
1043 /// getNonRegisterValue - Return an SDValue for the given Value, but
1044 /// don't look in FuncInfo.ValueMap for a virtual register.
1045 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1046 // If we already have an SDValue for this value, use it.
1047 SDValue &N = NodeMap[V];
1048 if (N.getNode()) return N;
1050 // Otherwise create a new SDValue and remember it.
1051 SDValue Val = getValueImpl(V);
1053 resolveDanglingDebugInfo(V, Val);
1057 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1058 /// Create an SDValue for the given value.
1059 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1060 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1062 if (const Constant *C = dyn_cast<Constant>(V)) {
1063 EVT VT = TLI->getValueType(V->getType(), true);
1065 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1066 return DAG.getConstant(*CI, VT);
1068 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1069 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1071 if (isa<ConstantPointerNull>(C)) {
1072 unsigned AS = V->getType()->getPointerAddressSpace();
1073 return DAG.getConstant(0, TLI->getPointerTy(AS));
1076 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1077 return DAG.getConstantFP(*CFP, VT);
1079 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1080 return DAG.getUNDEF(VT);
1082 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1083 visit(CE->getOpcode(), *CE);
1084 SDValue N1 = NodeMap[V];
1085 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1089 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1090 SmallVector<SDValue, 4> Constants;
1091 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1093 SDNode *Val = getValue(*OI).getNode();
1094 // If the operand is an empty aggregate, there are no values.
1096 // Add each leaf value from the operand to the Constants list
1097 // to form a flattened list of all the values.
1098 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1099 Constants.push_back(SDValue(Val, i));
1102 return DAG.getMergeValues(Constants, getCurSDLoc());
1105 if (const ConstantDataSequential *CDS =
1106 dyn_cast<ConstantDataSequential>(C)) {
1107 SmallVector<SDValue, 4> Ops;
1108 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1109 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1110 // Add each leaf value from the operand to the Constants list
1111 // to form a flattened list of all the values.
1112 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1113 Ops.push_back(SDValue(Val, i));
1116 if (isa<ArrayType>(CDS->getType()))
1117 return DAG.getMergeValues(Ops, getCurSDLoc());
1118 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1122 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1123 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1124 "Unknown struct or array constant!");
1126 SmallVector<EVT, 4> ValueVTs;
1127 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1128 unsigned NumElts = ValueVTs.size();
1130 return SDValue(); // empty struct
1131 SmallVector<SDValue, 4> Constants(NumElts);
1132 for (unsigned i = 0; i != NumElts; ++i) {
1133 EVT EltVT = ValueVTs[i];
1134 if (isa<UndefValue>(C))
1135 Constants[i] = DAG.getUNDEF(EltVT);
1136 else if (EltVT.isFloatingPoint())
1137 Constants[i] = DAG.getConstantFP(0, EltVT);
1139 Constants[i] = DAG.getConstant(0, EltVT);
1142 return DAG.getMergeValues(Constants, getCurSDLoc());
1145 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1146 return DAG.getBlockAddress(BA, VT);
1148 VectorType *VecTy = cast<VectorType>(V->getType());
1149 unsigned NumElements = VecTy->getNumElements();
1151 // Now that we know the number and type of the elements, get that number of
1152 // elements into the Ops array based on what kind of constant it is.
1153 SmallVector<SDValue, 16> Ops;
1154 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1155 for (unsigned i = 0; i != NumElements; ++i)
1156 Ops.push_back(getValue(CV->getOperand(i)));
1158 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1159 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1162 if (EltVT.isFloatingPoint())
1163 Op = DAG.getConstantFP(0, EltVT);
1165 Op = DAG.getConstant(0, EltVT);
1166 Ops.assign(NumElements, Op);
1169 // Create a BUILD_VECTOR node.
1170 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1173 // If this is a static alloca, generate it as the frameindex instead of
1175 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1176 DenseMap<const AllocaInst*, int>::iterator SI =
1177 FuncInfo.StaticAllocaMap.find(AI);
1178 if (SI != FuncInfo.StaticAllocaMap.end())
1179 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1182 // If this is an instruction which fast-isel has deferred, select it now.
1183 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1184 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1185 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1186 SDValue Chain = DAG.getEntryNode();
1187 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1190 llvm_unreachable("Can't get register for value!");
1193 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1194 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1195 SDValue Chain = getControlRoot();
1196 SmallVector<ISD::OutputArg, 8> Outs;
1197 SmallVector<SDValue, 8> OutVals;
1199 if (!FuncInfo.CanLowerReturn) {
1200 unsigned DemoteReg = FuncInfo.DemoteRegister;
1201 const Function *F = I.getParent()->getParent();
1203 // Emit a store of the return value through the virtual register.
1204 // Leave Outs empty so that LowerReturn won't try to load return
1205 // registers the usual way.
1206 SmallVector<EVT, 1> PtrValueVTs;
1207 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1210 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1211 SDValue RetOp = getValue(I.getOperand(0));
1213 SmallVector<EVT, 4> ValueVTs;
1214 SmallVector<uint64_t, 4> Offsets;
1215 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1216 unsigned NumValues = ValueVTs.size();
1218 SmallVector<SDValue, 4> Chains(NumValues);
1219 for (unsigned i = 0; i != NumValues; ++i) {
1220 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1221 RetPtr.getValueType(), RetPtr,
1222 DAG.getIntPtrConstant(Offsets[i]));
1224 DAG.getStore(Chain, getCurSDLoc(),
1225 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1226 // FIXME: better loc info would be nice.
1227 Add, MachinePointerInfo(), false, false, 0);
1230 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1231 MVT::Other, Chains);
1232 } else if (I.getNumOperands() != 0) {
1233 SmallVector<EVT, 4> ValueVTs;
1234 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1235 unsigned NumValues = ValueVTs.size();
1237 SDValue RetOp = getValue(I.getOperand(0));
1238 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1239 EVT VT = ValueVTs[j];
1241 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1243 const Function *F = I.getParent()->getParent();
1244 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1246 ExtendKind = ISD::SIGN_EXTEND;
1247 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1249 ExtendKind = ISD::ZERO_EXTEND;
1251 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1252 VT = TLI->getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1254 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1255 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1256 SmallVector<SDValue, 4> Parts(NumParts);
1257 getCopyToParts(DAG, getCurSDLoc(),
1258 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1259 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1261 // 'inreg' on function refers to return value
1262 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1263 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1267 // Propagate extension type if any
1268 if (ExtendKind == ISD::SIGN_EXTEND)
1270 else if (ExtendKind == ISD::ZERO_EXTEND)
1273 for (unsigned i = 0; i < NumParts; ++i) {
1274 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1275 VT, /*isfixed=*/true, 0, 0));
1276 OutVals.push_back(Parts[i]);
1282 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1283 CallingConv::ID CallConv =
1284 DAG.getMachineFunction().getFunction()->getCallingConv();
1285 Chain = TM.getSubtargetImpl()->getTargetLowering()->LowerReturn(
1286 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1288 // Verify that the target's LowerReturn behaved as expected.
1289 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1290 "LowerReturn didn't return a valid chain!");
1292 // Update the DAG with the new chain value resulting from return lowering.
1296 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1297 /// created for it, emit nodes to copy the value into the virtual
1299 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1301 if (V->getType()->isEmptyTy())
1304 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1305 if (VMI != FuncInfo.ValueMap.end()) {
1306 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1307 CopyValueToVirtualRegister(V, VMI->second);
1311 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1312 /// the current basic block, add it to ValueMap now so that we'll get a
1314 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1315 // No need to export constants.
1316 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1318 // Already exported?
1319 if (FuncInfo.isExportedInst(V)) return;
1321 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1322 CopyValueToVirtualRegister(V, Reg);
1325 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1326 const BasicBlock *FromBB) {
1327 // The operands of the setcc have to be in this block. We don't know
1328 // how to export them from some other block.
1329 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1330 // Can export from current BB.
1331 if (VI->getParent() == FromBB)
1334 // Is already exported, noop.
1335 return FuncInfo.isExportedInst(V);
1338 // If this is an argument, we can export it if the BB is the entry block or
1339 // if it is already exported.
1340 if (isa<Argument>(V)) {
1341 if (FromBB == &FromBB->getParent()->getEntryBlock())
1344 // Otherwise, can only export this if it is already exported.
1345 return FuncInfo.isExportedInst(V);
1348 // Otherwise, constants can always be exported.
1352 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1353 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1354 const MachineBasicBlock *Dst) const {
1355 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1358 const BasicBlock *SrcBB = Src->getBasicBlock();
1359 const BasicBlock *DstBB = Dst->getBasicBlock();
1360 return BPI->getEdgeWeight(SrcBB, DstBB);
1363 void SelectionDAGBuilder::
1364 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1365 uint32_t Weight /* = 0 */) {
1367 Weight = getEdgeWeight(Src, Dst);
1368 Src->addSuccessor(Dst, Weight);
1372 static bool InBlock(const Value *V, const BasicBlock *BB) {
1373 if (const Instruction *I = dyn_cast<Instruction>(V))
1374 return I->getParent() == BB;
1378 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1379 /// This function emits a branch and is used at the leaves of an OR or an
1380 /// AND operator tree.
1383 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1384 MachineBasicBlock *TBB,
1385 MachineBasicBlock *FBB,
1386 MachineBasicBlock *CurBB,
1387 MachineBasicBlock *SwitchBB,
1390 const BasicBlock *BB = CurBB->getBasicBlock();
1392 // If the leaf of the tree is a comparison, merge the condition into
1394 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1395 // The operands of the cmp have to be in this block. We don't know
1396 // how to export them from some other block. If this is the first block
1397 // of the sequence, no exporting is needed.
1398 if (CurBB == SwitchBB ||
1399 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1400 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1401 ISD::CondCode Condition;
1402 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1403 Condition = getICmpCondCode(IC->getPredicate());
1404 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1405 Condition = getFCmpCondCode(FC->getPredicate());
1406 if (TM.Options.NoNaNsFPMath)
1407 Condition = getFCmpCodeWithoutNaN(Condition);
1409 Condition = ISD::SETEQ; // silence warning.
1410 llvm_unreachable("Unknown compare instruction");
1413 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1414 TBB, FBB, CurBB, TWeight, FWeight);
1415 SwitchCases.push_back(CB);
1420 // Create a CaseBlock record representing this branch.
1421 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1422 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1423 SwitchCases.push_back(CB);
1426 /// Scale down both weights to fit into uint32_t.
1427 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1428 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1429 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1430 NewTrue = NewTrue / Scale;
1431 NewFalse = NewFalse / Scale;
1434 /// FindMergedConditions - If Cond is an expression like
1435 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1436 MachineBasicBlock *TBB,
1437 MachineBasicBlock *FBB,
1438 MachineBasicBlock *CurBB,
1439 MachineBasicBlock *SwitchBB,
1440 unsigned Opc, uint32_t TWeight,
1442 // If this node is not part of the or/and tree, emit it as a branch.
1443 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1444 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1445 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1446 BOp->getParent() != CurBB->getBasicBlock() ||
1447 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1448 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1449 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1454 // Create TmpBB after CurBB.
1455 MachineFunction::iterator BBI = CurBB;
1456 MachineFunction &MF = DAG.getMachineFunction();
1457 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1458 CurBB->getParent()->insert(++BBI, TmpBB);
1460 if (Opc == Instruction::Or) {
1461 // Codegen X | Y as:
1470 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1471 // The requirement is that
1472 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1473 // = TrueProb for orignal BB.
1474 // Assuming the orignal weights are A and B, one choice is to set BB1's
1475 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1477 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1478 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1479 // TmpBB, but the math is more complicated.
1481 uint64_t NewTrueWeight = TWeight;
1482 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1483 ScaleWeights(NewTrueWeight, NewFalseWeight);
1484 // Emit the LHS condition.
1485 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1486 NewTrueWeight, NewFalseWeight);
1488 NewTrueWeight = TWeight;
1489 NewFalseWeight = 2 * (uint64_t)FWeight;
1490 ScaleWeights(NewTrueWeight, NewFalseWeight);
1491 // Emit the RHS condition into TmpBB.
1492 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1493 NewTrueWeight, NewFalseWeight);
1495 assert(Opc == Instruction::And && "Unknown merge op!");
1496 // Codegen X & Y as:
1504 // This requires creation of TmpBB after CurBB.
1506 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1507 // The requirement is that
1508 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1509 // = FalseProb for orignal BB.
1510 // Assuming the orignal weights are A and B, one choice is to set BB1's
1511 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1513 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1515 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1516 uint64_t NewFalseWeight = FWeight;
1517 ScaleWeights(NewTrueWeight, NewFalseWeight);
1518 // Emit the LHS condition.
1519 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1520 NewTrueWeight, NewFalseWeight);
1522 NewTrueWeight = 2 * (uint64_t)TWeight;
1523 NewFalseWeight = FWeight;
1524 ScaleWeights(NewTrueWeight, NewFalseWeight);
1525 // Emit the RHS condition into TmpBB.
1526 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1527 NewTrueWeight, NewFalseWeight);
1531 /// If the set of cases should be emitted as a series of branches, return true.
1532 /// If we should emit this as a bunch of and/or'd together conditions, return
1535 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1536 if (Cases.size() != 2) return true;
1538 // If this is two comparisons of the same values or'd or and'd together, they
1539 // will get folded into a single comparison, so don't emit two blocks.
1540 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1541 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1542 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1543 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1547 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1548 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1549 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1550 Cases[0].CC == Cases[1].CC &&
1551 isa<Constant>(Cases[0].CmpRHS) &&
1552 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1553 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1555 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1562 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1563 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1565 // Update machine-CFG edges.
1566 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1568 // Figure out which block is immediately after the current one.
1569 MachineBasicBlock *NextBlock = nullptr;
1570 MachineFunction::iterator BBI = BrMBB;
1571 if (++BBI != FuncInfo.MF->end())
1574 if (I.isUnconditional()) {
1575 // Update machine-CFG edges.
1576 BrMBB->addSuccessor(Succ0MBB);
1578 // If this is not a fall-through branch or optimizations are switched off,
1580 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1581 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1582 MVT::Other, getControlRoot(),
1583 DAG.getBasicBlock(Succ0MBB)));
1588 // If this condition is one of the special cases we handle, do special stuff
1590 const Value *CondVal = I.getCondition();
1591 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1593 // If this is a series of conditions that are or'd or and'd together, emit
1594 // this as a sequence of branches instead of setcc's with and/or operations.
1595 // As long as jumps are not expensive, this should improve performance.
1596 // For example, instead of something like:
1609 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1610 if (!TM.getSubtargetImpl()->getTargetLowering()->isJumpExpensive() &&
1611 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1612 BOp->getOpcode() == Instruction::Or)) {
1613 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1614 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1615 getEdgeWeight(BrMBB, Succ1MBB));
1616 // If the compares in later blocks need to use values not currently
1617 // exported from this block, export them now. This block should always
1618 // be the first entry.
1619 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1621 // Allow some cases to be rejected.
1622 if (ShouldEmitAsBranches(SwitchCases)) {
1623 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1624 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1625 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1628 // Emit the branch for this block.
1629 visitSwitchCase(SwitchCases[0], BrMBB);
1630 SwitchCases.erase(SwitchCases.begin());
1634 // Okay, we decided not to do this, remove any inserted MBB's and clear
1636 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1637 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1639 SwitchCases.clear();
1643 // Create a CaseBlock record representing this branch.
1644 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1645 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1647 // Use visitSwitchCase to actually insert the fast branch sequence for this
1649 visitSwitchCase(CB, BrMBB);
1652 /// visitSwitchCase - Emits the necessary code to represent a single node in
1653 /// the binary search tree resulting from lowering a switch instruction.
1654 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1655 MachineBasicBlock *SwitchBB) {
1657 SDValue CondLHS = getValue(CB.CmpLHS);
1658 SDLoc dl = getCurSDLoc();
1660 // Build the setcc now.
1662 // Fold "(X == true)" to X and "(X == false)" to !X to
1663 // handle common cases produced by branch lowering.
1664 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1665 CB.CC == ISD::SETEQ)
1667 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1668 CB.CC == ISD::SETEQ) {
1669 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1670 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1672 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1674 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1676 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1677 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1679 SDValue CmpOp = getValue(CB.CmpMHS);
1680 EVT VT = CmpOp.getValueType();
1682 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1683 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1686 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1687 VT, CmpOp, DAG.getConstant(Low, VT));
1688 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1689 DAG.getConstant(High-Low, VT), ISD::SETULE);
1693 // Update successor info
1694 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1695 // TrueBB and FalseBB are always different unless the incoming IR is
1696 // degenerate. This only happens when running llc on weird IR.
1697 if (CB.TrueBB != CB.FalseBB)
1698 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1700 // Set NextBlock to be the MBB immediately after the current one, if any.
1701 // This is used to avoid emitting unnecessary branches to the next block.
1702 MachineBasicBlock *NextBlock = nullptr;
1703 MachineFunction::iterator BBI = SwitchBB;
1704 if (++BBI != FuncInfo.MF->end())
1707 // If the lhs block is the next block, invert the condition so that we can
1708 // fall through to the lhs instead of the rhs block.
1709 if (CB.TrueBB == NextBlock) {
1710 std::swap(CB.TrueBB, CB.FalseBB);
1711 SDValue True = DAG.getConstant(1, Cond.getValueType());
1712 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1715 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1716 MVT::Other, getControlRoot(), Cond,
1717 DAG.getBasicBlock(CB.TrueBB));
1719 // Insert the false branch. Do this even if it's a fall through branch,
1720 // this makes it easier to do DAG optimizations which require inverting
1721 // the branch condition.
1722 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1723 DAG.getBasicBlock(CB.FalseBB));
1725 DAG.setRoot(BrCond);
1728 /// visitJumpTable - Emit JumpTable node in the current MBB
1729 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1730 // Emit the code for the jump table
1731 assert(JT.Reg != -1U && "Should lower JT Header first!");
1732 EVT PTy = TM.getSubtargetImpl()->getTargetLowering()->getPointerTy();
1733 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1735 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1736 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1737 MVT::Other, Index.getValue(1),
1739 DAG.setRoot(BrJumpTable);
1742 /// visitJumpTableHeader - This function emits necessary code to produce index
1743 /// in the JumpTable from switch case.
1744 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1745 JumpTableHeader &JTH,
1746 MachineBasicBlock *SwitchBB) {
1747 // Subtract the lowest switch case value from the value being switched on and
1748 // conditional branch to default mbb if the result is greater than the
1749 // difference between smallest and largest cases.
1750 SDValue SwitchOp = getValue(JTH.SValue);
1751 EVT VT = SwitchOp.getValueType();
1752 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1753 DAG.getConstant(JTH.First, VT));
1755 // The SDNode we just created, which holds the value being switched on minus
1756 // the smallest case value, needs to be copied to a virtual register so it
1757 // can be used as an index into the jump table in a subsequent basic block.
1758 // This value may be smaller or larger than the target's pointer type, and
1759 // therefore require extension or truncating.
1760 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1761 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1763 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1764 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1765 JumpTableReg, SwitchOp);
1766 JT.Reg = JumpTableReg;
1768 // Emit the range check for the jump table, and branch to the default block
1769 // for the switch statement if the value being switched on exceeds the largest
1770 // case in the switch.
1771 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1772 TLI->getSetCCResultType(*DAG.getContext(),
1773 Sub.getValueType()),
1775 DAG.getConstant(JTH.Last - JTH.First,VT),
1778 // Set NextBlock to be the MBB immediately after the current one, if any.
1779 // This is used to avoid emitting unnecessary branches to the next block.
1780 MachineBasicBlock *NextBlock = nullptr;
1781 MachineFunction::iterator BBI = SwitchBB;
1783 if (++BBI != FuncInfo.MF->end())
1786 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1787 MVT::Other, CopyTo, CMP,
1788 DAG.getBasicBlock(JT.Default));
1790 if (JT.MBB != NextBlock)
1791 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1792 DAG.getBasicBlock(JT.MBB));
1794 DAG.setRoot(BrCond);
1797 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1798 /// tail spliced into a stack protector check success bb.
1800 /// For a high level explanation of how this fits into the stack protector
1801 /// generation see the comment on the declaration of class
1802 /// StackProtectorDescriptor.
1803 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1804 MachineBasicBlock *ParentBB) {
1806 // First create the loads to the guard/stack slot for the comparison.
1807 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1808 EVT PtrTy = TLI->getPointerTy();
1810 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1811 int FI = MFI->getStackProtectorIndex();
1813 const Value *IRGuard = SPD.getGuard();
1814 SDValue GuardPtr = getValue(IRGuard);
1815 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1818 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1822 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1823 // guard value from the virtual register holding the value. Otherwise, emit a
1824 // volatile load to retrieve the stack guard value.
1825 unsigned GuardReg = SPD.getGuardReg();
1827 if (GuardReg && TLI->useLoadStackGuardNode())
1828 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1831 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1832 GuardPtr, MachinePointerInfo(IRGuard, 0),
1833 true, false, false, Align);
1835 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1837 MachinePointerInfo::getFixedStack(FI),
1838 true, false, false, Align);
1840 // Perform the comparison via a subtract/getsetcc.
1841 EVT VT = Guard.getValueType();
1842 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1844 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1845 TLI->getSetCCResultType(*DAG.getContext(),
1846 Sub.getValueType()),
1847 Sub, DAG.getConstant(0, VT),
1850 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1851 // branch to failure MBB.
1852 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1853 MVT::Other, StackSlot.getOperand(0),
1854 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1855 // Otherwise branch to success MBB.
1856 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1858 DAG.getBasicBlock(SPD.getSuccessMBB()));
1863 /// Codegen the failure basic block for a stack protector check.
1865 /// A failure stack protector machine basic block consists simply of a call to
1866 /// __stack_chk_fail().
1868 /// For a high level explanation of how this fits into the stack protector
1869 /// generation see the comment on the declaration of class
1870 /// StackProtectorDescriptor.
1872 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1873 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1874 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1875 MVT::isVoid, nullptr, 0, false,
1876 getCurSDLoc(), false, false).second;
1880 /// visitBitTestHeader - This function emits necessary code to produce value
1881 /// suitable for "bit tests"
1882 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1883 MachineBasicBlock *SwitchBB) {
1884 // Subtract the minimum value
1885 SDValue SwitchOp = getValue(B.SValue);
1886 EVT VT = SwitchOp.getValueType();
1887 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1888 DAG.getConstant(B.First, VT));
1891 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1892 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1893 TLI->getSetCCResultType(*DAG.getContext(),
1894 Sub.getValueType()),
1895 Sub, DAG.getConstant(B.Range, VT),
1898 // Determine the type of the test operands.
1899 bool UsePtrType = false;
1900 if (!TLI->isTypeLegal(VT))
1903 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1904 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1905 // Switch table case range are encoded into series of masks.
1906 // Just use pointer type, it's guaranteed to fit.
1912 VT = TLI->getPointerTy();
1913 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1916 B.RegVT = VT.getSimpleVT();
1917 B.Reg = FuncInfo.CreateReg(B.RegVT);
1918 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1921 // Set NextBlock to be the MBB immediately after the current one, if any.
1922 // This is used to avoid emitting unnecessary branches to the next block.
1923 MachineBasicBlock *NextBlock = nullptr;
1924 MachineFunction::iterator BBI = SwitchBB;
1925 if (++BBI != FuncInfo.MF->end())
1928 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1930 addSuccessorWithWeight(SwitchBB, B.Default);
1931 addSuccessorWithWeight(SwitchBB, MBB);
1933 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1934 MVT::Other, CopyTo, RangeCmp,
1935 DAG.getBasicBlock(B.Default));
1937 if (MBB != NextBlock)
1938 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1939 DAG.getBasicBlock(MBB));
1941 DAG.setRoot(BrRange);
1944 /// visitBitTestCase - this function produces one "bit test"
1945 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1946 MachineBasicBlock* NextMBB,
1947 uint32_t BranchWeightToNext,
1950 MachineBasicBlock *SwitchBB) {
1952 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1955 unsigned PopCount = CountPopulation_64(B.Mask);
1956 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1957 if (PopCount == 1) {
1958 // Testing for a single bit; just compare the shift count with what it
1959 // would need to be to shift a 1 bit in that position.
1960 Cmp = DAG.getSetCC(getCurSDLoc(),
1961 TLI->getSetCCResultType(*DAG.getContext(), VT),
1963 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1965 } else if (PopCount == BB.Range) {
1966 // There is only one zero bit in the range, test for it directly.
1967 Cmp = DAG.getSetCC(getCurSDLoc(),
1968 TLI->getSetCCResultType(*DAG.getContext(), VT),
1970 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1973 // Make desired shift
1974 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1975 DAG.getConstant(1, VT), ShiftOp);
1977 // Emit bit tests and jumps
1978 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1979 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1980 Cmp = DAG.getSetCC(getCurSDLoc(),
1981 TLI->getSetCCResultType(*DAG.getContext(), VT),
1982 AndOp, DAG.getConstant(0, VT),
1986 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1987 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1988 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1989 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1991 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1992 MVT::Other, getControlRoot(),
1993 Cmp, DAG.getBasicBlock(B.TargetBB));
1995 // Set NextBlock to be the MBB immediately after the current one, if any.
1996 // This is used to avoid emitting unnecessary branches to the next block.
1997 MachineBasicBlock *NextBlock = nullptr;
1998 MachineFunction::iterator BBI = SwitchBB;
1999 if (++BBI != FuncInfo.MF->end())
2002 if (NextMBB != NextBlock)
2003 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2004 DAG.getBasicBlock(NextMBB));
2009 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2010 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2012 // Retrieve successors.
2013 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2014 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2016 const Value *Callee(I.getCalledValue());
2017 const Function *Fn = dyn_cast<Function>(Callee);
2018 if (isa<InlineAsm>(Callee))
2020 else if (Fn && Fn->isIntrinsic()) {
2021 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2022 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2024 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2026 // If the value of the invoke is used outside of its defining block, make it
2027 // available as a virtual register.
2028 CopyToExportRegsIfNeeded(&I);
2030 // Update successor info
2031 addSuccessorWithWeight(InvokeMBB, Return);
2032 addSuccessorWithWeight(InvokeMBB, LandingPad);
2034 // Drop into normal successor.
2035 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2036 MVT::Other, getControlRoot(),
2037 DAG.getBasicBlock(Return)));
2040 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2041 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2044 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2045 assert(FuncInfo.MBB->isLandingPad() &&
2046 "Call to landingpad not in landing pad!");
2048 MachineBasicBlock *MBB = FuncInfo.MBB;
2049 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2050 AddLandingPadInfo(LP, MMI, MBB);
2052 // If there aren't registers to copy the values into (e.g., during SjLj
2053 // exceptions), then don't bother to create these DAG nodes.
2054 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2055 if (TLI->getExceptionPointerRegister() == 0 &&
2056 TLI->getExceptionSelectorRegister() == 0)
2059 SmallVector<EVT, 2> ValueVTs;
2060 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2061 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2063 // Get the two live-in registers as SDValues. The physregs have already been
2064 // copied into virtual registers.
2066 Ops[0] = DAG.getZExtOrTrunc(
2067 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2068 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2069 getCurSDLoc(), ValueVTs[0]);
2070 Ops[1] = DAG.getZExtOrTrunc(
2071 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2072 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2073 getCurSDLoc(), ValueVTs[1]);
2076 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2077 DAG.getVTList(ValueVTs), Ops);
2081 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2082 /// small case ranges).
2083 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2084 CaseRecVector& WorkList,
2086 MachineBasicBlock *Default,
2087 MachineBasicBlock *SwitchBB) {
2088 // Size is the number of Cases represented by this range.
2089 size_t Size = CR.Range.second - CR.Range.first;
2093 // Get the MachineFunction which holds the current MBB. This is used when
2094 // inserting any additional MBBs necessary to represent the switch.
2095 MachineFunction *CurMF = FuncInfo.MF;
2097 // Figure out which block is immediately after the current one.
2098 MachineBasicBlock *NextBlock = nullptr;
2099 MachineFunction::iterator BBI = CR.CaseBB;
2101 if (++BBI != FuncInfo.MF->end())
2104 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2105 // If any two of the cases has the same destination, and if one value
2106 // is the same as the other, but has one bit unset that the other has set,
2107 // use bit manipulation to do two compares at once. For example:
2108 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2109 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2110 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2111 if (Size == 2 && CR.CaseBB == SwitchBB) {
2112 Case &Small = *CR.Range.first;
2113 Case &Big = *(CR.Range.second-1);
2115 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2116 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2117 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2119 // Check that there is only one bit different.
2120 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2121 (SmallValue | BigValue) == BigValue) {
2122 // Isolate the common bit.
2123 APInt CommonBit = BigValue & ~SmallValue;
2124 assert((SmallValue | CommonBit) == BigValue &&
2125 CommonBit.countPopulation() == 1 && "Not a common bit?");
2127 SDValue CondLHS = getValue(SV);
2128 EVT VT = CondLHS.getValueType();
2129 SDLoc DL = getCurSDLoc();
2131 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2132 DAG.getConstant(CommonBit, VT));
2133 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2134 Or, DAG.getConstant(BigValue, VT),
2137 // Update successor info.
2138 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2139 addSuccessorWithWeight(SwitchBB, Small.BB,
2140 Small.ExtraWeight + Big.ExtraWeight);
2141 addSuccessorWithWeight(SwitchBB, Default,
2142 // The default destination is the first successor in IR.
2143 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2145 // Insert the true branch.
2146 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2147 getControlRoot(), Cond,
2148 DAG.getBasicBlock(Small.BB));
2150 // Insert the false branch.
2151 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2152 DAG.getBasicBlock(Default));
2154 DAG.setRoot(BrCond);
2160 // Order cases by weight so the most likely case will be checked first.
2161 uint32_t UnhandledWeights = 0;
2163 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2164 uint32_t IWeight = I->ExtraWeight;
2165 UnhandledWeights += IWeight;
2166 for (CaseItr J = CR.Range.first; J < I; ++J) {
2167 uint32_t JWeight = J->ExtraWeight;
2168 if (IWeight > JWeight)
2173 // Rearrange the case blocks so that the last one falls through if possible.
2174 Case &BackCase = *(CR.Range.second-1);
2176 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2177 // The last case block won't fall through into 'NextBlock' if we emit the
2178 // branches in this order. See if rearranging a case value would help.
2179 // We start at the bottom as it's the case with the least weight.
2180 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2181 if (I->BB == NextBlock) {
2182 std::swap(*I, BackCase);
2187 // Create a CaseBlock record representing a conditional branch to
2188 // the Case's target mbb if the value being switched on SV is equal
2190 MachineBasicBlock *CurBlock = CR.CaseBB;
2191 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2192 MachineBasicBlock *FallThrough;
2194 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2195 CurMF->insert(BBI, FallThrough);
2197 // Put SV in a virtual register to make it available from the new blocks.
2198 ExportFromCurrentBlock(SV);
2200 // If the last case doesn't match, go to the default block.
2201 FallThrough = Default;
2204 const Value *RHS, *LHS, *MHS;
2206 if (I->High == I->Low) {
2207 // This is just small small case range :) containing exactly 1 case
2209 LHS = SV; RHS = I->High; MHS = nullptr;
2212 LHS = I->Low; MHS = SV; RHS = I->High;
2215 // The false weight should be sum of all un-handled cases.
2216 UnhandledWeights -= I->ExtraWeight;
2217 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2219 /* trueweight */ I->ExtraWeight,
2220 /* falseweight */ UnhandledWeights);
2222 // If emitting the first comparison, just call visitSwitchCase to emit the
2223 // code into the current block. Otherwise, push the CaseBlock onto the
2224 // vector to be later processed by SDISel, and insert the node's MBB
2225 // before the next MBB.
2226 if (CurBlock == SwitchBB)
2227 visitSwitchCase(CB, SwitchBB);
2229 SwitchCases.push_back(CB);
2231 CurBlock = FallThrough;
2237 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2238 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2239 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2242 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2243 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2244 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2245 return (LastExt - FirstExt + 1ULL);
2248 /// handleJTSwitchCase - Emit jumptable for current switch case range
2249 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2250 CaseRecVector &WorkList,
2252 MachineBasicBlock *Default,
2253 MachineBasicBlock *SwitchBB) {
2254 Case& FrontCase = *CR.Range.first;
2255 Case& BackCase = *(CR.Range.second-1);
2257 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2258 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2260 APInt TSize(First.getBitWidth(), 0);
2261 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2264 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2265 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2268 APInt Range = ComputeRange(First, Last);
2269 // The density is TSize / Range. Require at least 40%.
2270 // It should not be possible for IntTSize to saturate for sane code, but make
2271 // sure we handle Range saturation correctly.
2272 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2273 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2274 if (IntTSize * 10 < IntRange * 4)
2277 DEBUG(dbgs() << "Lowering jump table\n"
2278 << "First entry: " << First << ". Last entry: " << Last << '\n'
2279 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2281 // Get the MachineFunction which holds the current MBB. This is used when
2282 // inserting any additional MBBs necessary to represent the switch.
2283 MachineFunction *CurMF = FuncInfo.MF;
2285 // Figure out which block is immediately after the current one.
2286 MachineFunction::iterator BBI = CR.CaseBB;
2289 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2291 // Create a new basic block to hold the code for loading the address
2292 // of the jump table, and jumping to it. Update successor information;
2293 // we will either branch to the default case for the switch, or the jump
2295 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2296 CurMF->insert(BBI, JumpTableBB);
2298 addSuccessorWithWeight(CR.CaseBB, Default);
2299 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2301 // Build a vector of destination BBs, corresponding to each target
2302 // of the jump table. If the value of the jump table slot corresponds to
2303 // a case statement, push the case's BB onto the vector, otherwise, push
2305 std::vector<MachineBasicBlock*> DestBBs;
2307 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2308 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2309 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2311 if (Low.sle(TEI) && TEI.sle(High)) {
2312 DestBBs.push_back(I->BB);
2316 DestBBs.push_back(Default);
2320 // Calculate weight for each unique destination in CR.
2321 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2323 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2324 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2325 DestWeights.find(I->BB);
2326 if (Itr != DestWeights.end())
2327 Itr->second += I->ExtraWeight;
2329 DestWeights[I->BB] = I->ExtraWeight;
2332 // Update successor info. Add one edge to each unique successor.
2333 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2334 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2335 E = DestBBs.end(); I != E; ++I) {
2336 if (!SuccsHandled[(*I)->getNumber()]) {
2337 SuccsHandled[(*I)->getNumber()] = true;
2338 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2339 DestWeights.find(*I);
2340 addSuccessorWithWeight(JumpTableBB, *I,
2341 Itr != DestWeights.end() ? Itr->second : 0);
2345 // Create a jump table index for this jump table.
2346 unsigned JTEncoding = TLI->getJumpTableEncoding();
2347 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2348 ->createJumpTableIndex(DestBBs);
2350 // Set the jump table information so that we can codegen it as a second
2351 // MachineBasicBlock
2352 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2353 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2354 if (CR.CaseBB == SwitchBB)
2355 visitJumpTableHeader(JT, JTH, SwitchBB);
2357 JTCases.push_back(JumpTableBlock(JTH, JT));
2361 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2363 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2364 CaseRecVector& WorkList,
2366 MachineBasicBlock* Default,
2367 MachineBasicBlock* SwitchBB) {
2368 // Get the MachineFunction which holds the current MBB. This is used when
2369 // inserting any additional MBBs necessary to represent the switch.
2370 MachineFunction *CurMF = FuncInfo.MF;
2372 // Figure out which block is immediately after the current one.
2373 MachineFunction::iterator BBI = CR.CaseBB;
2376 Case& FrontCase = *CR.Range.first;
2377 Case& BackCase = *(CR.Range.second-1);
2378 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2380 // Size is the number of Cases represented by this range.
2381 unsigned Size = CR.Range.second - CR.Range.first;
2383 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2384 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2386 CaseItr Pivot = CR.Range.first + Size/2;
2388 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2389 // (heuristically) allow us to emit JumpTable's later.
2390 APInt TSize(First.getBitWidth(), 0);
2391 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2395 APInt LSize = FrontCase.size();
2396 APInt RSize = TSize-LSize;
2397 DEBUG(dbgs() << "Selecting best pivot: \n"
2398 << "First: " << First << ", Last: " << Last <<'\n'
2399 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2400 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2402 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2403 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2404 APInt Range = ComputeRange(LEnd, RBegin);
2405 assert((Range - 2ULL).isNonNegative() &&
2406 "Invalid case distance");
2407 // Use volatile double here to avoid excess precision issues on some hosts,
2408 // e.g. that use 80-bit X87 registers.
2409 volatile double LDensity =
2410 (double)LSize.roundToDouble() /
2411 (LEnd - First + 1ULL).roundToDouble();
2412 volatile double RDensity =
2413 (double)RSize.roundToDouble() /
2414 (Last - RBegin + 1ULL).roundToDouble();
2415 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2416 // Should always split in some non-trivial place
2417 DEBUG(dbgs() <<"=>Step\n"
2418 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2419 << "LDensity: " << LDensity
2420 << ", RDensity: " << RDensity << '\n'
2421 << "Metric: " << Metric << '\n');
2422 if (FMetric < Metric) {
2425 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2432 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2433 if (areJTsAllowed(*TLI)) {
2434 // If our case is dense we *really* should handle it earlier!
2435 assert((FMetric > 0) && "Should handle dense range earlier!");
2437 Pivot = CR.Range.first + Size/2;
2440 CaseRange LHSR(CR.Range.first, Pivot);
2441 CaseRange RHSR(Pivot, CR.Range.second);
2442 const Constant *C = Pivot->Low;
2443 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2445 // We know that we branch to the LHS if the Value being switched on is
2446 // less than the Pivot value, C. We use this to optimize our binary
2447 // tree a bit, by recognizing that if SV is greater than or equal to the
2448 // LHS's Case Value, and that Case Value is exactly one less than the
2449 // Pivot's Value, then we can branch directly to the LHS's Target,
2450 // rather than creating a leaf node for it.
2451 if ((LHSR.second - LHSR.first) == 1 &&
2452 LHSR.first->High == CR.GE &&
2453 cast<ConstantInt>(C)->getValue() ==
2454 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2455 TrueBB = LHSR.first->BB;
2457 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2458 CurMF->insert(BBI, TrueBB);
2459 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2461 // Put SV in a virtual register to make it available from the new blocks.
2462 ExportFromCurrentBlock(SV);
2465 // Similar to the optimization above, if the Value being switched on is
2466 // known to be less than the Constant CR.LT, and the current Case Value
2467 // is CR.LT - 1, then we can branch directly to the target block for
2468 // the current Case Value, rather than emitting a RHS leaf node for it.
2469 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2470 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2471 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2472 FalseBB = RHSR.first->BB;
2474 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2475 CurMF->insert(BBI, FalseBB);
2476 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2478 // Put SV in a virtual register to make it available from the new blocks.
2479 ExportFromCurrentBlock(SV);
2482 // Create a CaseBlock record representing a conditional branch to
2483 // the LHS node if the value being switched on SV is less than C.
2484 // Otherwise, branch to LHS.
2485 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2487 if (CR.CaseBB == SwitchBB)
2488 visitSwitchCase(CB, SwitchBB);
2490 SwitchCases.push_back(CB);
2495 /// handleBitTestsSwitchCase - if current case range has few destination and
2496 /// range span less, than machine word bitwidth, encode case range into series
2497 /// of masks and emit bit tests with these masks.
2498 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2499 CaseRecVector& WorkList,
2501 MachineBasicBlock* Default,
2502 MachineBasicBlock* SwitchBB) {
2503 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2504 EVT PTy = TLI->getPointerTy();
2505 unsigned IntPtrBits = PTy.getSizeInBits();
2507 Case& FrontCase = *CR.Range.first;
2508 Case& BackCase = *(CR.Range.second-1);
2510 // Get the MachineFunction which holds the current MBB. This is used when
2511 // inserting any additional MBBs necessary to represent the switch.
2512 MachineFunction *CurMF = FuncInfo.MF;
2514 // If target does not have legal shift left, do not emit bit tests at all.
2515 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2519 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2521 // Single case counts one, case range - two.
2522 numCmps += (I->Low == I->High ? 1 : 2);
2525 // Count unique destinations
2526 SmallSet<MachineBasicBlock*, 4> Dests;
2527 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2528 Dests.insert(I->BB);
2529 if (Dests.size() > 3)
2530 // Don't bother the code below, if there are too much unique destinations
2533 DEBUG(dbgs() << "Total number of unique destinations: "
2534 << Dests.size() << '\n'
2535 << "Total number of comparisons: " << numCmps << '\n');
2537 // Compute span of values.
2538 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2539 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2540 APInt cmpRange = maxValue - minValue;
2542 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2543 << "Low bound: " << minValue << '\n'
2544 << "High bound: " << maxValue << '\n');
2546 if (cmpRange.uge(IntPtrBits) ||
2547 (!(Dests.size() == 1 && numCmps >= 3) &&
2548 !(Dests.size() == 2 && numCmps >= 5) &&
2549 !(Dests.size() >= 3 && numCmps >= 6)))
2552 DEBUG(dbgs() << "Emitting bit tests\n");
2553 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2555 // Optimize the case where all the case values fit in a
2556 // word without having to subtract minValue. In this case,
2557 // we can optimize away the subtraction.
2558 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2559 cmpRange = maxValue;
2561 lowBound = minValue;
2564 CaseBitsVector CasesBits;
2565 unsigned i, count = 0;
2567 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2568 MachineBasicBlock* Dest = I->BB;
2569 for (i = 0; i < count; ++i)
2570 if (Dest == CasesBits[i].BB)
2574 assert((count < 3) && "Too much destinations to test!");
2575 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2579 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2580 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2582 uint64_t lo = (lowValue - lowBound).getZExtValue();
2583 uint64_t hi = (highValue - lowBound).getZExtValue();
2584 CasesBits[i].ExtraWeight += I->ExtraWeight;
2586 for (uint64_t j = lo; j <= hi; j++) {
2587 CasesBits[i].Mask |= 1ULL << j;
2588 CasesBits[i].Bits++;
2592 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2596 // Figure out which block is immediately after the current one.
2597 MachineFunction::iterator BBI = CR.CaseBB;
2600 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2602 DEBUG(dbgs() << "Cases:\n");
2603 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2604 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2605 << ", Bits: " << CasesBits[i].Bits
2606 << ", BB: " << CasesBits[i].BB << '\n');
2608 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2609 CurMF->insert(BBI, CaseBB);
2610 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2612 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2614 // Put SV in a virtual register to make it available from the new blocks.
2615 ExportFromCurrentBlock(SV);
2618 BitTestBlock BTB(lowBound, cmpRange, SV,
2619 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2620 CR.CaseBB, Default, std::move(BTC));
2622 if (CR.CaseBB == SwitchBB)
2623 visitBitTestHeader(BTB, SwitchBB);
2625 BitTestCases.push_back(std::move(BTB));
2630 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2631 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2632 const SwitchInst& SI) {
2635 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2636 // Start with "simple" cases
2637 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2639 const BasicBlock *SuccBB = i.getCaseSuccessor();
2640 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2642 uint32_t ExtraWeight =
2643 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2645 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2646 SMBB, ExtraWeight));
2648 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2650 // Merge case into clusters
2651 if (Cases.size() >= 2)
2652 // Must recompute end() each iteration because it may be
2653 // invalidated by erase if we hold on to it
2654 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2655 J != Cases.end(); ) {
2656 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2657 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2658 MachineBasicBlock* nextBB = J->BB;
2659 MachineBasicBlock* currentBB = I->BB;
2661 // If the two neighboring cases go to the same destination, merge them
2662 // into a single case.
2663 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2665 I->ExtraWeight += J->ExtraWeight;
2672 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2673 if (I->Low != I->High)
2674 // A range counts double, since it requires two compares.
2681 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2682 MachineBasicBlock *Last) {
2684 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2685 if (JTCases[i].first.HeaderBB == First)
2686 JTCases[i].first.HeaderBB = Last;
2688 // Update BitTestCases.
2689 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2690 if (BitTestCases[i].Parent == First)
2691 BitTestCases[i].Parent = Last;
2694 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2695 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2697 // Figure out which block is immediately after the current one.
2698 MachineBasicBlock *NextBlock = nullptr;
2699 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2701 // If there is only the default destination, branch to it if it is not the
2702 // next basic block. Otherwise, just fall through.
2703 if (!SI.getNumCases()) {
2704 // Update machine-CFG edges.
2706 // If this is not a fall-through branch, emit the branch.
2707 SwitchMBB->addSuccessor(Default);
2708 if (Default != NextBlock)
2709 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2710 MVT::Other, getControlRoot(),
2711 DAG.getBasicBlock(Default)));
2716 // If there are any non-default case statements, create a vector of Cases
2717 // representing each one, and sort the vector so that we can efficiently
2718 // create a binary search tree from them.
2720 size_t numCmps = Clusterify(Cases, SI);
2721 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2722 << ". Total compares: " << numCmps << '\n');
2725 // Get the Value to be switched on and default basic blocks, which will be
2726 // inserted into CaseBlock records, representing basic blocks in the binary
2728 const Value *SV = SI.getCondition();
2730 // Push the initial CaseRec onto the worklist
2731 CaseRecVector WorkList;
2732 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2733 CaseRange(Cases.begin(),Cases.end())));
2735 while (!WorkList.empty()) {
2736 // Grab a record representing a case range to process off the worklist
2737 CaseRec CR = WorkList.back();
2738 WorkList.pop_back();
2740 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2743 // If the range has few cases (two or less) emit a series of specific
2745 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2748 // If the switch has more than N blocks, and is at least 40% dense, and the
2749 // target supports indirect branches, then emit a jump table rather than
2750 // lowering the switch to a binary tree of conditional branches.
2751 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2752 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2755 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2756 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2757 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2761 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2762 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2764 // Update machine-CFG edges with unique successors.
2765 SmallSet<BasicBlock*, 32> Done;
2766 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2767 BasicBlock *BB = I.getSuccessor(i);
2768 bool Inserted = Done.insert(BB);
2772 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2773 addSuccessorWithWeight(IndirectBrMBB, Succ);
2776 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2777 MVT::Other, getControlRoot(),
2778 getValue(I.getAddress())));
2781 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2782 if (DAG.getTarget().Options.TrapUnreachable)
2783 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2786 void SelectionDAGBuilder::visitFSub(const User &I) {
2787 // -0.0 - X --> fneg
2788 Type *Ty = I.getType();
2789 if (isa<Constant>(I.getOperand(0)) &&
2790 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2791 SDValue Op2 = getValue(I.getOperand(1));
2792 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2793 Op2.getValueType(), Op2));
2797 visitBinary(I, ISD::FSUB);
2800 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2801 SDValue Op1 = getValue(I.getOperand(0));
2802 SDValue Op2 = getValue(I.getOperand(1));
2807 if (const OverflowingBinaryOperator *OFBinOp =
2808 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2809 nuw = OFBinOp->hasNoUnsignedWrap();
2810 nsw = OFBinOp->hasNoSignedWrap();
2812 if (const PossiblyExactOperator *ExactOp =
2813 dyn_cast<const PossiblyExactOperator>(&I))
2814 exact = ExactOp->isExact();
2816 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2817 Op1, Op2, nuw, nsw, exact);
2818 setValue(&I, BinNodeValue);
2821 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2822 SDValue Op1 = getValue(I.getOperand(0));
2823 SDValue Op2 = getValue(I.getOperand(1));
2825 EVT ShiftTy = TM.getSubtargetImpl()->getTargetLowering()->getShiftAmountTy(
2826 Op2.getValueType());
2828 // Coerce the shift amount to the right type if we can.
2829 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2830 unsigned ShiftSize = ShiftTy.getSizeInBits();
2831 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2832 SDLoc DL = getCurSDLoc();
2834 // If the operand is smaller than the shift count type, promote it.
2835 if (ShiftSize > Op2Size)
2836 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2838 // If the operand is larger than the shift count type but the shift
2839 // count type has enough bits to represent any shift value, truncate
2840 // it now. This is a common case and it exposes the truncate to
2841 // optimization early.
2842 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2843 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2844 // Otherwise we'll need to temporarily settle for some other convenient
2845 // type. Type legalization will make adjustments once the shiftee is split.
2847 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2854 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2856 if (const OverflowingBinaryOperator *OFBinOp =
2857 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2858 nuw = OFBinOp->hasNoUnsignedWrap();
2859 nsw = OFBinOp->hasNoSignedWrap();
2861 if (const PossiblyExactOperator *ExactOp =
2862 dyn_cast<const PossiblyExactOperator>(&I))
2863 exact = ExactOp->isExact();
2866 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2871 void SelectionDAGBuilder::visitSDiv(const User &I) {
2872 SDValue Op1 = getValue(I.getOperand(0));
2873 SDValue Op2 = getValue(I.getOperand(1));
2875 // Turn exact SDivs into multiplications.
2876 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2878 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2879 !isa<ConstantSDNode>(Op1) &&
2880 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2881 setValue(&I, TM.getSubtargetImpl()->getTargetLowering()->BuildExactSDIV(
2882 Op1, Op2, getCurSDLoc(), DAG));
2884 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2888 void SelectionDAGBuilder::visitICmp(const User &I) {
2889 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2890 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2891 predicate = IC->getPredicate();
2892 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2893 predicate = ICmpInst::Predicate(IC->getPredicate());
2894 SDValue Op1 = getValue(I.getOperand(0));
2895 SDValue Op2 = getValue(I.getOperand(1));
2896 ISD::CondCode Opcode = getICmpCondCode(predicate);
2899 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2900 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2903 void SelectionDAGBuilder::visitFCmp(const User &I) {
2904 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2905 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2906 predicate = FC->getPredicate();
2907 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2908 predicate = FCmpInst::Predicate(FC->getPredicate());
2909 SDValue Op1 = getValue(I.getOperand(0));
2910 SDValue Op2 = getValue(I.getOperand(1));
2911 ISD::CondCode Condition = getFCmpCondCode(predicate);
2912 if (TM.Options.NoNaNsFPMath)
2913 Condition = getFCmpCodeWithoutNaN(Condition);
2915 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2916 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2919 void SelectionDAGBuilder::visitSelect(const User &I) {
2920 SmallVector<EVT, 4> ValueVTs;
2921 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), I.getType(),
2923 unsigned NumValues = ValueVTs.size();
2924 if (NumValues == 0) return;
2926 SmallVector<SDValue, 4> Values(NumValues);
2927 SDValue Cond = getValue(I.getOperand(0));
2928 SDValue TrueVal = getValue(I.getOperand(1));
2929 SDValue FalseVal = getValue(I.getOperand(2));
2930 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2931 ISD::VSELECT : ISD::SELECT;
2933 for (unsigned i = 0; i != NumValues; ++i)
2934 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2935 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2937 SDValue(TrueVal.getNode(),
2938 TrueVal.getResNo() + i),
2939 SDValue(FalseVal.getNode(),
2940 FalseVal.getResNo() + i));
2942 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2943 DAG.getVTList(ValueVTs), Values));
2946 void SelectionDAGBuilder::visitTrunc(const User &I) {
2947 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2948 SDValue N = getValue(I.getOperand(0));
2950 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2951 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2954 void SelectionDAGBuilder::visitZExt(const User &I) {
2955 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2956 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2957 SDValue N = getValue(I.getOperand(0));
2959 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2960 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2963 void SelectionDAGBuilder::visitSExt(const User &I) {
2964 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2965 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2966 SDValue N = getValue(I.getOperand(0));
2968 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2969 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2972 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2973 // FPTrunc is never a no-op cast, no need to check
2974 SDValue N = getValue(I.getOperand(0));
2975 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2976 EVT DestVT = TLI->getValueType(I.getType());
2977 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2979 DAG.getTargetConstant(0, TLI->getPointerTy())));
2982 void SelectionDAGBuilder::visitFPExt(const User &I) {
2983 // FPExt is never a no-op cast, no need to check
2984 SDValue N = getValue(I.getOperand(0));
2986 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2987 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2990 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2991 // FPToUI is never a no-op cast, no need to check
2992 SDValue N = getValue(I.getOperand(0));
2994 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2995 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2998 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2999 // FPToSI is never a no-op cast, no need to check
3000 SDValue N = getValue(I.getOperand(0));
3002 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3003 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3006 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3007 // UIToFP is never a no-op cast, no need to check
3008 SDValue N = getValue(I.getOperand(0));
3010 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3011 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3014 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3015 // SIToFP is never a no-op cast, no need to check
3016 SDValue N = getValue(I.getOperand(0));
3018 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3019 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3022 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3023 // What to do depends on the size of the integer and the size of the pointer.
3024 // We can either truncate, zero extend, or no-op, accordingly.
3025 SDValue N = getValue(I.getOperand(0));
3027 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3028 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3031 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3032 // What to do depends on the size of the integer and the size of the pointer.
3033 // We can either truncate, zero extend, or no-op, accordingly.
3034 SDValue N = getValue(I.getOperand(0));
3036 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3037 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3040 void SelectionDAGBuilder::visitBitCast(const User &I) {
3041 SDValue N = getValue(I.getOperand(0));
3043 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3045 // BitCast assures us that source and destination are the same size so this is
3046 // either a BITCAST or a no-op.
3047 if (DestVT != N.getValueType())
3048 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3049 DestVT, N)); // convert types.
3050 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3051 // might fold any kind of constant expression to an integer constant and that
3052 // is not what we are looking for. Only regcognize a bitcast of a genuine
3053 // constant integer as an opaque constant.
3054 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3055 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3058 setValue(&I, N); // noop cast.
3061 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3063 const Value *SV = I.getOperand(0);
3064 SDValue N = getValue(SV);
3066 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3068 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3069 unsigned DestAS = I.getType()->getPointerAddressSpace();
3071 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3072 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3077 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3079 SDValue InVec = getValue(I.getOperand(0));
3080 SDValue InVal = getValue(I.getOperand(1));
3081 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3082 getCurSDLoc(), TLI.getVectorIdxTy());
3084 DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3085 TM.getSubtargetImpl()->getTargetLowering()->getValueType(
3087 InVec, InVal, InIdx));
3090 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3091 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3092 SDValue InVec = getValue(I.getOperand(0));
3093 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3094 getCurSDLoc(), TLI.getVectorIdxTy());
3096 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3097 TM.getSubtargetImpl()->getTargetLowering()->getValueType(
3102 // Utility for visitShuffleVector - Return true if every element in Mask,
3103 // beginning from position Pos and ending in Pos+Size, falls within the
3104 // specified sequential range [L, L+Pos). or is undef.
3105 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3106 unsigned Pos, unsigned Size, int Low) {
3107 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3108 if (Mask[i] >= 0 && Mask[i] != Low)
3113 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3114 SDValue Src1 = getValue(I.getOperand(0));
3115 SDValue Src2 = getValue(I.getOperand(1));
3117 SmallVector<int, 8> Mask;
3118 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3119 unsigned MaskNumElts = Mask.size();
3121 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3122 EVT VT = TLI->getValueType(I.getType());
3123 EVT SrcVT = Src1.getValueType();
3124 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3126 if (SrcNumElts == MaskNumElts) {
3127 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3132 // Normalize the shuffle vector since mask and vector length don't match.
3133 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3134 // Mask is longer than the source vectors and is a multiple of the source
3135 // vectors. We can use concatenate vector to make the mask and vectors
3137 if (SrcNumElts*2 == MaskNumElts) {
3138 // First check for Src1 in low and Src2 in high
3139 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3140 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3141 // The shuffle is concatenating two vectors together.
3142 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3146 // Then check for Src2 in low and Src1 in high
3147 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3148 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3149 // The shuffle is concatenating two vectors together.
3150 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3156 // Pad both vectors with undefs to make them the same length as the mask.
3157 unsigned NumConcat = MaskNumElts / SrcNumElts;
3158 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3159 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3160 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3162 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3163 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3167 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3168 getCurSDLoc(), VT, MOps1);
3169 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3170 getCurSDLoc(), VT, MOps2);
3172 // Readjust mask for new input vector length.
3173 SmallVector<int, 8> MappedOps;
3174 for (unsigned i = 0; i != MaskNumElts; ++i) {
3176 if (Idx >= (int)SrcNumElts)
3177 Idx -= SrcNumElts - MaskNumElts;
3178 MappedOps.push_back(Idx);
3181 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3186 if (SrcNumElts > MaskNumElts) {
3187 // Analyze the access pattern of the vector to see if we can extract
3188 // two subvectors and do the shuffle. The analysis is done by calculating
3189 // the range of elements the mask access on both vectors.
3190 int MinRange[2] = { static_cast<int>(SrcNumElts),
3191 static_cast<int>(SrcNumElts)};
3192 int MaxRange[2] = {-1, -1};
3194 for (unsigned i = 0; i != MaskNumElts; ++i) {
3200 if (Idx >= (int)SrcNumElts) {
3204 if (Idx > MaxRange[Input])
3205 MaxRange[Input] = Idx;
3206 if (Idx < MinRange[Input])
3207 MinRange[Input] = Idx;
3210 // Check if the access is smaller than the vector size and can we find
3211 // a reasonable extract index.
3212 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3214 int StartIdx[2]; // StartIdx to extract from
3215 for (unsigned Input = 0; Input < 2; ++Input) {
3216 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3217 RangeUse[Input] = 0; // Unused
3218 StartIdx[Input] = 0;
3222 // Find a good start index that is a multiple of the mask length. Then
3223 // see if the rest of the elements are in range.
3224 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3225 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3226 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3227 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3230 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3231 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3234 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3235 // Extract appropriate subvector and generate a vector shuffle
3236 for (unsigned Input = 0; Input < 2; ++Input) {
3237 SDValue &Src = Input == 0 ? Src1 : Src2;
3238 if (RangeUse[Input] == 0)
3239 Src = DAG.getUNDEF(VT);
3241 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3242 Src, DAG.getConstant(StartIdx[Input],
3243 TLI->getVectorIdxTy()));
3246 // Calculate new mask.
3247 SmallVector<int, 8> MappedOps;
3248 for (unsigned i = 0; i != MaskNumElts; ++i) {
3251 if (Idx < (int)SrcNumElts)
3254 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3256 MappedOps.push_back(Idx);
3259 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3265 // We can't use either concat vectors or extract subvectors so fall back to
3266 // replacing the shuffle with extract and build vector.
3267 // to insert and build vector.
3268 EVT EltVT = VT.getVectorElementType();
3269 EVT IdxVT = TLI->getVectorIdxTy();
3270 SmallVector<SDValue,8> Ops;
3271 for (unsigned i = 0; i != MaskNumElts; ++i) {
3276 Res = DAG.getUNDEF(EltVT);
3278 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3279 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3281 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3282 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3288 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3291 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3292 const Value *Op0 = I.getOperand(0);
3293 const Value *Op1 = I.getOperand(1);
3294 Type *AggTy = I.getType();
3295 Type *ValTy = Op1->getType();
3296 bool IntoUndef = isa<UndefValue>(Op0);
3297 bool FromUndef = isa<UndefValue>(Op1);
3299 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3301 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3302 SmallVector<EVT, 4> AggValueVTs;
3303 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3304 SmallVector<EVT, 4> ValValueVTs;
3305 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3307 unsigned NumAggValues = AggValueVTs.size();
3308 unsigned NumValValues = ValValueVTs.size();
3309 SmallVector<SDValue, 4> Values(NumAggValues);
3311 // Ignore an insertvalue that produces an empty object
3312 if (!NumAggValues) {
3313 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3317 SDValue Agg = getValue(Op0);
3319 // Copy the beginning value(s) from the original aggregate.
3320 for (; i != LinearIndex; ++i)
3321 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3322 SDValue(Agg.getNode(), Agg.getResNo() + i);
3323 // Copy values from the inserted value(s).
3325 SDValue Val = getValue(Op1);
3326 for (; i != LinearIndex + NumValValues; ++i)
3327 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3328 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3330 // Copy remaining value(s) from the original aggregate.
3331 for (; i != NumAggValues; ++i)
3332 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3333 SDValue(Agg.getNode(), Agg.getResNo() + i);
3335 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3336 DAG.getVTList(AggValueVTs), Values));
3339 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3340 const Value *Op0 = I.getOperand(0);
3341 Type *AggTy = Op0->getType();
3342 Type *ValTy = I.getType();
3343 bool OutOfUndef = isa<UndefValue>(Op0);
3345 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3347 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3348 SmallVector<EVT, 4> ValValueVTs;
3349 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3351 unsigned NumValValues = ValValueVTs.size();
3353 // Ignore a extractvalue that produces an empty object
3354 if (!NumValValues) {
3355 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3359 SmallVector<SDValue, 4> Values(NumValValues);
3361 SDValue Agg = getValue(Op0);
3362 // Copy out the selected value(s).
3363 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3364 Values[i - LinearIndex] =
3366 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3367 SDValue(Agg.getNode(), Agg.getResNo() + i);
3369 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3370 DAG.getVTList(ValValueVTs), Values));
3373 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3374 Value *Op0 = I.getOperand(0);
3375 // Note that the pointer operand may be a vector of pointers. Take the scalar
3376 // element which holds a pointer.
3377 Type *Ty = Op0->getType()->getScalarType();
3378 unsigned AS = Ty->getPointerAddressSpace();
3379 SDValue N = getValue(Op0);
3381 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3383 const Value *Idx = *OI;
3384 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3385 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3388 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3389 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3390 DAG.getConstant(Offset, N.getValueType()));
3393 Ty = StTy->getElementType(Field);
3395 Ty = cast<SequentialType>(Ty)->getElementType();
3397 // If this is a constant subscript, handle it quickly.
3398 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3399 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3400 if (CI->isZero()) continue;
3402 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3404 EVT PTy = TLI->getPointerTy(AS);
3405 unsigned PtrBits = PTy.getSizeInBits();
3407 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3408 DAG.getConstant(Offs, MVT::i64));
3410 OffsVal = DAG.getConstant(Offs, PTy);
3412 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3417 // N = N + Idx * ElementSize;
3418 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3419 DL->getTypeAllocSize(Ty));
3420 SDValue IdxN = getValue(Idx);
3422 // If the index is smaller or larger than intptr_t, truncate or extend
3424 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3426 // If this is a multiply by a power of two, turn it into a shl
3427 // immediately. This is a very common case.
3428 if (ElementSize != 1) {
3429 if (ElementSize.isPowerOf2()) {
3430 unsigned Amt = ElementSize.logBase2();
3431 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3432 N.getValueType(), IdxN,
3433 DAG.getConstant(Amt, IdxN.getValueType()));
3435 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3436 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3437 N.getValueType(), IdxN, Scale);
3441 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3442 N.getValueType(), N, IdxN);
3449 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3450 // If this is a fixed sized alloca in the entry block of the function,
3451 // allocate it statically on the stack.
3452 if (FuncInfo.StaticAllocaMap.count(&I))
3453 return; // getValue will auto-populate this.
3455 Type *Ty = I.getAllocatedType();
3456 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3457 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3459 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3462 SDValue AllocSize = getValue(I.getArraySize());
3464 EVT IntPtr = TLI->getPointerTy();
3465 if (AllocSize.getValueType() != IntPtr)
3466 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3468 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3470 DAG.getConstant(TySize, IntPtr));
3472 // Handle alignment. If the requested alignment is less than or equal to
3473 // the stack alignment, ignore it. If the size is greater than or equal to
3474 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3475 unsigned StackAlign =
3476 TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
3477 if (Align <= StackAlign)
3480 // Round the size of the allocation up to the stack alignment size
3481 // by add SA-1 to the size.
3482 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3483 AllocSize.getValueType(), AllocSize,
3484 DAG.getIntPtrConstant(StackAlign-1));
3486 // Mask out the low bits for alignment purposes.
3487 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3488 AllocSize.getValueType(), AllocSize,
3489 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3491 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3492 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3493 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3495 DAG.setRoot(DSA.getValue(1));
3497 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3500 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3502 return visitAtomicLoad(I);
3504 const Value *SV = I.getOperand(0);
3505 SDValue Ptr = getValue(SV);
3507 Type *Ty = I.getType();
3509 bool isVolatile = I.isVolatile();
3510 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3511 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3512 unsigned Alignment = I.getAlignment();
3515 I.getAAMetadata(AAInfo);
3516 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3518 SmallVector<EVT, 4> ValueVTs;
3519 SmallVector<uint64_t, 4> Offsets;
3520 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), Ty, ValueVTs,
3522 unsigned NumValues = ValueVTs.size();
3527 bool ConstantMemory = false;
3528 if (isVolatile || NumValues > MaxParallelChains)
3529 // Serialize volatile loads with other side effects.
3531 else if (AA->pointsToConstantMemory(
3532 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3533 // Do not serialize (non-volatile) loads of constant memory with anything.
3534 Root = DAG.getEntryNode();
3535 ConstantMemory = true;
3537 // Do not serialize non-volatile loads against each other.
3538 Root = DAG.getRoot();
3541 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3543 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3545 SmallVector<SDValue, 4> Values(NumValues);
3546 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3548 EVT PtrVT = Ptr.getValueType();
3549 unsigned ChainI = 0;
3550 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3551 // Serializing loads here may result in excessive register pressure, and
3552 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3553 // could recover a bit by hoisting nodes upward in the chain by recognizing
3554 // they are side-effect free or do not alias. The optimizer should really
3555 // avoid this case by converting large object/array copies to llvm.memcpy
3556 // (MaxParallelChains should always remain as failsafe).
3557 if (ChainI == MaxParallelChains) {
3558 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3559 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3560 makeArrayRef(Chains.data(), ChainI));
3564 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3566 DAG.getConstant(Offsets[i], PtrVT));
3567 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3568 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3569 isNonTemporal, isInvariant, Alignment, AAInfo,
3573 Chains[ChainI] = L.getValue(1);
3576 if (!ConstantMemory) {
3577 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3578 makeArrayRef(Chains.data(), ChainI));
3582 PendingLoads.push_back(Chain);
3585 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3586 DAG.getVTList(ValueVTs), Values));
3589 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3591 return visitAtomicStore(I);
3593 const Value *SrcV = I.getOperand(0);
3594 const Value *PtrV = I.getOperand(1);
3596 SmallVector<EVT, 4> ValueVTs;
3597 SmallVector<uint64_t, 4> Offsets;
3598 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), SrcV->getType(),
3599 ValueVTs, &Offsets);
3600 unsigned NumValues = ValueVTs.size();
3604 // Get the lowered operands. Note that we do this after
3605 // checking if NumResults is zero, because with zero results
3606 // the operands won't have values in the map.
3607 SDValue Src = getValue(SrcV);
3608 SDValue Ptr = getValue(PtrV);
3610 SDValue Root = getRoot();
3611 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3613 EVT PtrVT = Ptr.getValueType();
3614 bool isVolatile = I.isVolatile();
3615 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3616 unsigned Alignment = I.getAlignment();
3619 I.getAAMetadata(AAInfo);
3621 unsigned ChainI = 0;
3622 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3623 // See visitLoad comments.
3624 if (ChainI == MaxParallelChains) {
3625 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3626 makeArrayRef(Chains.data(), ChainI));
3630 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3631 DAG.getConstant(Offsets[i], PtrVT));
3632 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3633 SDValue(Src.getNode(), Src.getResNo() + i),
3634 Add, MachinePointerInfo(PtrV, Offsets[i]),
3635 isVolatile, isNonTemporal, Alignment, AAInfo);
3636 Chains[ChainI] = St;
3639 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3640 makeArrayRef(Chains.data(), ChainI));
3641 DAG.setRoot(StoreNode);
3644 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3645 SynchronizationScope Scope,
3646 bool Before, SDLoc dl,
3648 const TargetLowering &TLI) {
3649 // Fence, if necessary
3651 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3653 else if (Order == Acquire || Order == Monotonic || Order == Unordered)
3656 if (Order == AcquireRelease)
3658 else if (Order == Release || Order == Monotonic || Order == Unordered)
3663 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3664 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3665 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
3668 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3669 SDLoc dl = getCurSDLoc();
3670 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3671 AtomicOrdering FailureOrder = I.getFailureOrdering();
3672 SynchronizationScope Scope = I.getSynchScope();
3674 SDValue InChain = getRoot();
3676 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3677 if (TLI->getInsertFencesForAtomic())
3678 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3681 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3682 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3683 SDValue L = DAG.getAtomicCmpSwap(
3684 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3685 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3686 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3688 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3689 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder, Scope);
3691 SDValue OutChain = L.getValue(2);
3693 if (TLI->getInsertFencesForAtomic())
3694 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3698 DAG.setRoot(OutChain);
3701 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3702 SDLoc dl = getCurSDLoc();
3704 switch (I.getOperation()) {
3705 default: llvm_unreachable("Unknown atomicrmw operation");
3706 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3707 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3708 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3709 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3710 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3711 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3712 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3713 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3714 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3715 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3716 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3718 AtomicOrdering Order = I.getOrdering();
3719 SynchronizationScope Scope = I.getSynchScope();
3721 SDValue InChain = getRoot();
3723 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3724 if (TLI->getInsertFencesForAtomic())
3725 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3729 DAG.getAtomic(NT, dl,
3730 getValue(I.getValOperand()).getSimpleValueType(),
3732 getValue(I.getPointerOperand()),
3733 getValue(I.getValOperand()),
3734 I.getPointerOperand(), 0 /* Alignment */,
3735 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3738 SDValue OutChain = L.getValue(1);
3740 if (TLI->getInsertFencesForAtomic())
3741 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3745 DAG.setRoot(OutChain);
3748 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3749 SDLoc dl = getCurSDLoc();
3750 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3753 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3754 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3755 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3758 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3759 SDLoc dl = getCurSDLoc();
3760 AtomicOrdering Order = I.getOrdering();
3761 SynchronizationScope Scope = I.getSynchScope();
3763 SDValue InChain = getRoot();
3765 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3766 EVT VT = TLI->getValueType(I.getType());
3768 if (I.getAlignment() < VT.getSizeInBits() / 8)
3769 report_fatal_error("Cannot generate unaligned atomic load");
3771 MachineMemOperand *MMO =
3772 DAG.getMachineFunction().
3773 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3774 MachineMemOperand::MOVolatile |
3775 MachineMemOperand::MOLoad,
3777 I.getAlignment() ? I.getAlignment() :
3778 DAG.getEVTAlignment(VT));
3780 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3782 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3783 getValue(I.getPointerOperand()), MMO,
3784 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3787 SDValue OutChain = L.getValue(1);
3789 if (TLI->getInsertFencesForAtomic())
3790 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3794 DAG.setRoot(OutChain);
3797 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3798 SDLoc dl = getCurSDLoc();
3800 AtomicOrdering Order = I.getOrdering();
3801 SynchronizationScope Scope = I.getSynchScope();
3803 SDValue InChain = getRoot();
3805 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3806 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3808 if (I.getAlignment() < VT.getSizeInBits() / 8)
3809 report_fatal_error("Cannot generate unaligned atomic store");
3811 if (TLI->getInsertFencesForAtomic())
3812 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3816 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3818 getValue(I.getPointerOperand()),
3819 getValue(I.getValueOperand()),
3820 I.getPointerOperand(), I.getAlignment(),
3821 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3824 if (TLI->getInsertFencesForAtomic())
3825 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3828 DAG.setRoot(OutChain);
3831 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3833 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3834 unsigned Intrinsic) {
3835 bool HasChain = !I.doesNotAccessMemory();
3836 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3838 // Build the operand list.
3839 SmallVector<SDValue, 8> Ops;
3840 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3842 // We don't need to serialize loads against other loads.
3843 Ops.push_back(DAG.getRoot());
3845 Ops.push_back(getRoot());
3849 // Info is set by getTgtMemInstrinsic
3850 TargetLowering::IntrinsicInfo Info;
3851 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3852 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3854 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3855 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3856 Info.opc == ISD::INTRINSIC_W_CHAIN)
3857 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3859 // Add all operands of the call to the operand list.
3860 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3861 SDValue Op = getValue(I.getArgOperand(i));
3865 SmallVector<EVT, 4> ValueVTs;
3866 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3869 ValueVTs.push_back(MVT::Other);
3871 SDVTList VTs = DAG.getVTList(ValueVTs);
3875 if (IsTgtIntrinsic) {
3876 // This is target intrinsic that touches memory
3877 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3878 VTs, Ops, Info.memVT,
3879 MachinePointerInfo(Info.ptrVal, Info.offset),
3880 Info.align, Info.vol,
3881 Info.readMem, Info.writeMem, Info.size);
3882 } else if (!HasChain) {
3883 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3884 } else if (!I.getType()->isVoidTy()) {
3885 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3887 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3891 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3893 PendingLoads.push_back(Chain);
3898 if (!I.getType()->isVoidTy()) {
3899 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3900 EVT VT = TLI->getValueType(PTy);
3901 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3904 setValue(&I, Result);
3908 /// GetSignificand - Get the significand and build it into a floating-point
3909 /// number with exponent of 1:
3911 /// Op = (Op & 0x007fffff) | 0x3f800000;
3913 /// where Op is the hexadecimal representation of floating point value.
3915 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3916 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3917 DAG.getConstant(0x007fffff, MVT::i32));
3918 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3919 DAG.getConstant(0x3f800000, MVT::i32));
3920 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3923 /// GetExponent - Get the exponent:
3925 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3927 /// where Op is the hexadecimal representation of floating point value.
3929 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3931 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3932 DAG.getConstant(0x7f800000, MVT::i32));
3933 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3934 DAG.getConstant(23, TLI.getPointerTy()));
3935 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3936 DAG.getConstant(127, MVT::i32));
3937 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3940 /// getF32Constant - Get 32-bit floating point constant.
3942 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3943 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3947 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3948 /// limited-precision mode.
3949 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3950 const TargetLowering &TLI) {
3951 if (Op.getValueType() == MVT::f32 &&
3952 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3954 // Put the exponent in the right bit position for later addition to the
3957 // #define LOG2OFe 1.4426950f
3958 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3959 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3960 getF32Constant(DAG, 0x3fb8aa3b));
3961 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3963 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3964 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3965 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3967 // IntegerPartOfX <<= 23;
3968 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3969 DAG.getConstant(23, TLI.getPointerTy()));
3971 SDValue TwoToFracPartOfX;
3972 if (LimitFloatPrecision <= 6) {
3973 // For floating-point precision of 6:
3975 // TwoToFractionalPartOfX =
3977 // (0.735607626f + 0.252464424f * x) * x;
3979 // error 0.0144103317, which is 6 bits
3980 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3981 getF32Constant(DAG, 0x3e814304));
3982 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3983 getF32Constant(DAG, 0x3f3c50c8));
3984 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3985 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3986 getF32Constant(DAG, 0x3f7f5e7e));
3987 } else if (LimitFloatPrecision <= 12) {
3988 // For floating-point precision of 12:
3990 // TwoToFractionalPartOfX =
3993 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3995 // 0.000107046256 error, which is 13 to 14 bits
3996 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3997 getF32Constant(DAG, 0x3da235e3));
3998 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3999 getF32Constant(DAG, 0x3e65b8f3));
4000 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4001 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4002 getF32Constant(DAG, 0x3f324b07));
4003 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4004 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4005 getF32Constant(DAG, 0x3f7ff8fd));
4006 } else { // LimitFloatPrecision <= 18
4007 // For floating-point precision of 18:
4009 // TwoToFractionalPartOfX =
4013 // (0.554906021e-1f +
4014 // (0.961591928e-2f +
4015 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4017 // error 2.47208000*10^(-7), which is better than 18 bits
4018 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4019 getF32Constant(DAG, 0x3924b03e));
4020 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4021 getF32Constant(DAG, 0x3ab24b87));
4022 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4023 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4024 getF32Constant(DAG, 0x3c1d8c17));
4025 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4026 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4027 getF32Constant(DAG, 0x3d634a1d));
4028 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4029 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4030 getF32Constant(DAG, 0x3e75fe14));
4031 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4032 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4033 getF32Constant(DAG, 0x3f317234));
4034 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4035 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4036 getF32Constant(DAG, 0x3f800000));
4039 // Add the exponent into the result in integer domain.
4040 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4041 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4042 DAG.getNode(ISD::ADD, dl, MVT::i32,
4043 t13, IntegerPartOfX));
4046 // No special expansion.
4047 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4050 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4051 /// limited-precision mode.
4052 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4053 const TargetLowering &TLI) {
4054 if (Op.getValueType() == MVT::f32 &&
4055 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4056 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4058 // Scale the exponent by log(2) [0.69314718f].
4059 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4060 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4061 getF32Constant(DAG, 0x3f317218));
4063 // Get the significand and build it into a floating-point number with
4065 SDValue X = GetSignificand(DAG, Op1, dl);
4067 SDValue LogOfMantissa;
4068 if (LimitFloatPrecision <= 6) {
4069 // For floating-point precision of 6:
4073 // (1.4034025f - 0.23903021f * x) * x;
4075 // error 0.0034276066, which is better than 8 bits
4076 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4077 getF32Constant(DAG, 0xbe74c456));
4078 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4079 getF32Constant(DAG, 0x3fb3a2b1));
4080 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4081 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4082 getF32Constant(DAG, 0x3f949a29));
4083 } else if (LimitFloatPrecision <= 12) {
4084 // For floating-point precision of 12:
4090 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4092 // error 0.000061011436, which is 14 bits
4093 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4094 getF32Constant(DAG, 0xbd67b6d6));
4095 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4096 getF32Constant(DAG, 0x3ee4f4b8));
4097 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4098 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4099 getF32Constant(DAG, 0x3fbc278b));
4100 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4101 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4102 getF32Constant(DAG, 0x40348e95));
4103 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4104 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4105 getF32Constant(DAG, 0x3fdef31a));
4106 } else { // LimitFloatPrecision <= 18
4107 // For floating-point precision of 18:
4115 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4117 // error 0.0000023660568, which is better than 18 bits
4118 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4119 getF32Constant(DAG, 0xbc91e5ac));
4120 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4121 getF32Constant(DAG, 0x3e4350aa));
4122 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4123 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4124 getF32Constant(DAG, 0x3f60d3e3));
4125 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4126 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4127 getF32Constant(DAG, 0x4011cdf0));
4128 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4129 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4130 getF32Constant(DAG, 0x406cfd1c));
4131 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4132 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4133 getF32Constant(DAG, 0x408797cb));
4134 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4135 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4136 getF32Constant(DAG, 0x4006dcab));
4139 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4142 // No special expansion.
4143 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4146 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4147 /// limited-precision mode.
4148 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4149 const TargetLowering &TLI) {
4150 if (Op.getValueType() == MVT::f32 &&
4151 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4152 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4154 // Get the exponent.
4155 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4157 // Get the significand and build it into a floating-point number with
4159 SDValue X = GetSignificand(DAG, Op1, dl);
4161 // Different possible minimax approximations of significand in
4162 // floating-point for various degrees of accuracy over [1,2].
4163 SDValue Log2ofMantissa;
4164 if (LimitFloatPrecision <= 6) {
4165 // For floating-point precision of 6:
4167 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4169 // error 0.0049451742, which is more than 7 bits
4170 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4171 getF32Constant(DAG, 0xbeb08fe0));
4172 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4173 getF32Constant(DAG, 0x40019463));
4174 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4175 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4176 getF32Constant(DAG, 0x3fd6633d));
4177 } else if (LimitFloatPrecision <= 12) {
4178 // For floating-point precision of 12:
4184 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4186 // error 0.0000876136000, which is better than 13 bits
4187 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4188 getF32Constant(DAG, 0xbda7262e));
4189 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4190 getF32Constant(DAG, 0x3f25280b));
4191 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4192 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4193 getF32Constant(DAG, 0x4007b923));
4194 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4195 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4196 getF32Constant(DAG, 0x40823e2f));
4197 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4198 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4199 getF32Constant(DAG, 0x4020d29c));
4200 } else { // LimitFloatPrecision <= 18
4201 // For floating-point precision of 18:
4210 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4212 // error 0.0000018516, which is better than 18 bits
4213 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4214 getF32Constant(DAG, 0xbcd2769e));
4215 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4216 getF32Constant(DAG, 0x3e8ce0b9));
4217 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4218 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4219 getF32Constant(DAG, 0x3fa22ae7));
4220 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4221 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4222 getF32Constant(DAG, 0x40525723));
4223 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4224 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4225 getF32Constant(DAG, 0x40aaf200));
4226 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4227 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4228 getF32Constant(DAG, 0x40c39dad));
4229 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4230 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4231 getF32Constant(DAG, 0x4042902c));
4234 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4237 // No special expansion.
4238 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4241 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4242 /// limited-precision mode.
4243 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4244 const TargetLowering &TLI) {
4245 if (Op.getValueType() == MVT::f32 &&
4246 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4247 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4249 // Scale the exponent by log10(2) [0.30102999f].
4250 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4251 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4252 getF32Constant(DAG, 0x3e9a209a));
4254 // Get the significand and build it into a floating-point number with
4256 SDValue X = GetSignificand(DAG, Op1, dl);
4258 SDValue Log10ofMantissa;
4259 if (LimitFloatPrecision <= 6) {
4260 // For floating-point precision of 6:
4262 // Log10ofMantissa =
4264 // (0.60948995f - 0.10380950f * x) * x;
4266 // error 0.0014886165, which is 6 bits
4267 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4268 getF32Constant(DAG, 0xbdd49a13));
4269 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4270 getF32Constant(DAG, 0x3f1c0789));
4271 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4272 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4273 getF32Constant(DAG, 0x3f011300));
4274 } else if (LimitFloatPrecision <= 12) {
4275 // For floating-point precision of 12:
4277 // Log10ofMantissa =
4280 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4282 // error 0.00019228036, which is better than 12 bits
4283 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4284 getF32Constant(DAG, 0x3d431f31));
4285 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4286 getF32Constant(DAG, 0x3ea21fb2));
4287 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4288 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4289 getF32Constant(DAG, 0x3f6ae232));
4290 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4291 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4292 getF32Constant(DAG, 0x3f25f7c3));
4293 } else { // LimitFloatPrecision <= 18
4294 // For floating-point precision of 18:
4296 // Log10ofMantissa =
4301 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4303 // error 0.0000037995730, which is better than 18 bits
4304 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4305 getF32Constant(DAG, 0x3c5d51ce));
4306 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4307 getF32Constant(DAG, 0x3e00685a));
4308 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4309 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4310 getF32Constant(DAG, 0x3efb6798));
4311 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4312 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4313 getF32Constant(DAG, 0x3f88d192));
4314 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4315 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4316 getF32Constant(DAG, 0x3fc4316c));
4317 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4318 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4319 getF32Constant(DAG, 0x3f57ce70));
4322 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4325 // No special expansion.
4326 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4329 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4330 /// limited-precision mode.
4331 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4332 const TargetLowering &TLI) {
4333 if (Op.getValueType() == MVT::f32 &&
4334 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4335 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4337 // FractionalPartOfX = x - (float)IntegerPartOfX;
4338 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4339 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4341 // IntegerPartOfX <<= 23;
4342 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4343 DAG.getConstant(23, TLI.getPointerTy()));
4345 SDValue TwoToFractionalPartOfX;
4346 if (LimitFloatPrecision <= 6) {
4347 // For floating-point precision of 6:
4349 // TwoToFractionalPartOfX =
4351 // (0.735607626f + 0.252464424f * x) * x;
4353 // error 0.0144103317, which is 6 bits
4354 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4355 getF32Constant(DAG, 0x3e814304));
4356 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4357 getF32Constant(DAG, 0x3f3c50c8));
4358 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4359 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4360 getF32Constant(DAG, 0x3f7f5e7e));
4361 } else if (LimitFloatPrecision <= 12) {
4362 // For floating-point precision of 12:
4364 // TwoToFractionalPartOfX =
4367 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4369 // error 0.000107046256, which is 13 to 14 bits
4370 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4371 getF32Constant(DAG, 0x3da235e3));
4372 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4373 getF32Constant(DAG, 0x3e65b8f3));
4374 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4375 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4376 getF32Constant(DAG, 0x3f324b07));
4377 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4378 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4379 getF32Constant(DAG, 0x3f7ff8fd));
4380 } else { // LimitFloatPrecision <= 18
4381 // For floating-point precision of 18:
4383 // TwoToFractionalPartOfX =
4387 // (0.554906021e-1f +
4388 // (0.961591928e-2f +
4389 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4390 // error 2.47208000*10^(-7), which is better than 18 bits
4391 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4392 getF32Constant(DAG, 0x3924b03e));
4393 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4394 getF32Constant(DAG, 0x3ab24b87));
4395 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4396 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4397 getF32Constant(DAG, 0x3c1d8c17));
4398 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4399 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4400 getF32Constant(DAG, 0x3d634a1d));
4401 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4402 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4403 getF32Constant(DAG, 0x3e75fe14));
4404 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4405 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4406 getF32Constant(DAG, 0x3f317234));
4407 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4408 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4409 getF32Constant(DAG, 0x3f800000));
4412 // Add the exponent into the result in integer domain.
4413 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4414 TwoToFractionalPartOfX);
4415 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4416 DAG.getNode(ISD::ADD, dl, MVT::i32,
4417 t13, IntegerPartOfX));
4420 // No special expansion.
4421 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4424 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4425 /// limited-precision mode with x == 10.0f.
4426 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4427 SelectionDAG &DAG, const TargetLowering &TLI) {
4428 bool IsExp10 = false;
4429 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4430 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4431 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4433 IsExp10 = LHSC->isExactlyValue(Ten);
4438 // Put the exponent in the right bit position for later addition to the
4441 // #define LOG2OF10 3.3219281f
4442 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4443 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4444 getF32Constant(DAG, 0x40549a78));
4445 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4447 // FractionalPartOfX = x - (float)IntegerPartOfX;
4448 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4449 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4451 // IntegerPartOfX <<= 23;
4452 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4453 DAG.getConstant(23, TLI.getPointerTy()));
4455 SDValue TwoToFractionalPartOfX;
4456 if (LimitFloatPrecision <= 6) {
4457 // For floating-point precision of 6:
4459 // twoToFractionalPartOfX =
4461 // (0.735607626f + 0.252464424f * x) * x;
4463 // error 0.0144103317, which is 6 bits
4464 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4465 getF32Constant(DAG, 0x3e814304));
4466 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4467 getF32Constant(DAG, 0x3f3c50c8));
4468 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4469 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4470 getF32Constant(DAG, 0x3f7f5e7e));
4471 } else if (LimitFloatPrecision <= 12) {
4472 // For floating-point precision of 12:
4474 // TwoToFractionalPartOfX =
4477 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4479 // error 0.000107046256, which is 13 to 14 bits
4480 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4481 getF32Constant(DAG, 0x3da235e3));
4482 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4483 getF32Constant(DAG, 0x3e65b8f3));
4484 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4485 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4486 getF32Constant(DAG, 0x3f324b07));
4487 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4488 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4489 getF32Constant(DAG, 0x3f7ff8fd));
4490 } else { // LimitFloatPrecision <= 18
4491 // For floating-point precision of 18:
4493 // TwoToFractionalPartOfX =
4497 // (0.554906021e-1f +
4498 // (0.961591928e-2f +
4499 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4500 // error 2.47208000*10^(-7), which is better than 18 bits
4501 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4502 getF32Constant(DAG, 0x3924b03e));
4503 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4504 getF32Constant(DAG, 0x3ab24b87));
4505 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4506 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4507 getF32Constant(DAG, 0x3c1d8c17));
4508 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4509 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4510 getF32Constant(DAG, 0x3d634a1d));
4511 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4512 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4513 getF32Constant(DAG, 0x3e75fe14));
4514 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4515 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4516 getF32Constant(DAG, 0x3f317234));
4517 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4518 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4519 getF32Constant(DAG, 0x3f800000));
4522 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4523 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4524 DAG.getNode(ISD::ADD, dl, MVT::i32,
4525 t13, IntegerPartOfX));
4528 // No special expansion.
4529 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4533 /// ExpandPowI - Expand a llvm.powi intrinsic.
4534 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4535 SelectionDAG &DAG) {
4536 // If RHS is a constant, we can expand this out to a multiplication tree,
4537 // otherwise we end up lowering to a call to __powidf2 (for example). When
4538 // optimizing for size, we only want to do this if the expansion would produce
4539 // a small number of multiplies, otherwise we do the full expansion.
4540 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4541 // Get the exponent as a positive value.
4542 unsigned Val = RHSC->getSExtValue();
4543 if ((int)Val < 0) Val = -Val;
4545 // powi(x, 0) -> 1.0
4547 return DAG.getConstantFP(1.0, LHS.getValueType());
4549 const Function *F = DAG.getMachineFunction().getFunction();
4550 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4551 Attribute::OptimizeForSize) ||
4552 // If optimizing for size, don't insert too many multiplies. This
4553 // inserts up to 5 multiplies.
4554 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4555 // We use the simple binary decomposition method to generate the multiply
4556 // sequence. There are more optimal ways to do this (for example,
4557 // powi(x,15) generates one more multiply than it should), but this has
4558 // the benefit of being both really simple and much better than a libcall.
4559 SDValue Res; // Logically starts equal to 1.0
4560 SDValue CurSquare = LHS;
4564 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4566 Res = CurSquare; // 1.0*CurSquare.
4569 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4570 CurSquare, CurSquare);
4574 // If the original was negative, invert the result, producing 1/(x*x*x).
4575 if (RHSC->getSExtValue() < 0)
4576 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4577 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4582 // Otherwise, expand to a libcall.
4583 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4586 // getTruncatedArgReg - Find underlying register used for an truncated
4588 static unsigned getTruncatedArgReg(const SDValue &N) {
4589 if (N.getOpcode() != ISD::TRUNCATE)
4592 const SDValue &Ext = N.getOperand(0);
4593 if (Ext.getOpcode() == ISD::AssertZext ||
4594 Ext.getOpcode() == ISD::AssertSext) {
4595 const SDValue &CFR = Ext.getOperand(0);
4596 if (CFR.getOpcode() == ISD::CopyFromReg)
4597 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4598 if (CFR.getOpcode() == ISD::TRUNCATE)
4599 return getTruncatedArgReg(CFR);
4604 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4605 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4606 /// At the end of instruction selection, they will be inserted to the entry BB.
4607 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4609 MDNode *Expr, int64_t Offset,
4612 const Argument *Arg = dyn_cast<Argument>(V);
4616 MachineFunction &MF = DAG.getMachineFunction();
4617 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4619 // Ignore inlined function arguments here.
4620 DIVariable DV(Variable);
4621 if (DV.isInlinedFnArgument(MF.getFunction()))
4624 Optional<MachineOperand> Op;
4625 // Some arguments' frame index is recorded during argument lowering.
4626 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4627 Op = MachineOperand::CreateFI(FI);
4629 if (!Op && N.getNode()) {
4631 if (N.getOpcode() == ISD::CopyFromReg)
4632 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4634 Reg = getTruncatedArgReg(N);
4635 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4636 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4637 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4642 Op = MachineOperand::CreateReg(Reg, false);
4646 // Check if ValueMap has reg number.
4647 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4648 if (VMI != FuncInfo.ValueMap.end())
4649 Op = MachineOperand::CreateReg(VMI->second, false);
4652 if (!Op && N.getNode())
4653 // Check if frame index is available.
4654 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4655 if (FrameIndexSDNode *FINode =
4656 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4657 Op = MachineOperand::CreateFI(FINode->getIndex());
4663 FuncInfo.ArgDbgValues.push_back(
4664 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4665 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4667 FuncInfo.ArgDbgValues.push_back(
4668 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4671 .addMetadata(Variable)
4672 .addMetadata(Expr));
4677 // VisualStudio defines setjmp as _setjmp
4678 #if defined(_MSC_VER) && defined(setjmp) && \
4679 !defined(setjmp_undefined_for_msvc)
4680 # pragma push_macro("setjmp")
4682 # define setjmp_undefined_for_msvc
4685 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4686 /// we want to emit this as a call to a named external function, return the name
4687 /// otherwise lower it and return null.
4689 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4690 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
4691 SDLoc sdl = getCurSDLoc();
4692 DebugLoc dl = getCurDebugLoc();
4695 switch (Intrinsic) {
4697 // By default, turn this into a target intrinsic node.
4698 visitTargetIntrinsic(I, Intrinsic);
4700 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4701 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4702 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4703 case Intrinsic::returnaddress:
4704 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4705 getValue(I.getArgOperand(0))));
4707 case Intrinsic::frameaddress:
4708 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4709 getValue(I.getArgOperand(0))));
4711 case Intrinsic::read_register: {
4712 Value *Reg = I.getArgOperand(0);
4713 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4715 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
4716 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4719 case Intrinsic::write_register: {
4720 Value *Reg = I.getArgOperand(0);
4721 Value *RegValue = I.getArgOperand(1);
4722 SDValue Chain = getValue(RegValue).getOperand(0);
4723 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4724 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4725 RegName, getValue(RegValue)));
4728 case Intrinsic::setjmp:
4729 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4730 case Intrinsic::longjmp:
4731 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4732 case Intrinsic::memcpy: {
4733 // Assert for address < 256 since we support only user defined address
4735 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4737 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4739 "Unknown address space");
4740 SDValue Op1 = getValue(I.getArgOperand(0));
4741 SDValue Op2 = getValue(I.getArgOperand(1));
4742 SDValue Op3 = getValue(I.getArgOperand(2));
4743 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4745 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4746 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4747 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4748 MachinePointerInfo(I.getArgOperand(0)),
4749 MachinePointerInfo(I.getArgOperand(1))));
4752 case Intrinsic::memset: {
4753 // Assert for address < 256 since we support only user defined address
4755 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4757 "Unknown address space");
4758 SDValue Op1 = getValue(I.getArgOperand(0));
4759 SDValue Op2 = getValue(I.getArgOperand(1));
4760 SDValue Op3 = getValue(I.getArgOperand(2));
4761 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4763 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4764 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4765 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4766 MachinePointerInfo(I.getArgOperand(0))));
4769 case Intrinsic::memmove: {
4770 // Assert for address < 256 since we support only user defined address
4772 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4774 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4776 "Unknown address space");
4777 SDValue Op1 = getValue(I.getArgOperand(0));
4778 SDValue Op2 = getValue(I.getArgOperand(1));
4779 SDValue Op3 = getValue(I.getArgOperand(2));
4780 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4782 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4783 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4784 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4785 MachinePointerInfo(I.getArgOperand(0)),
4786 MachinePointerInfo(I.getArgOperand(1))));
4789 case Intrinsic::dbg_declare: {
4790 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4791 MDNode *Variable = DI.getVariable();
4792 MDNode *Expression = DI.getExpression();
4793 const Value *Address = DI.getAddress();
4794 DIVariable DIVar(Variable);
4795 assert((!DIVar || DIVar.isVariable()) &&
4796 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4797 if (!Address || !DIVar) {
4798 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4802 // Check if address has undef value.
4803 if (isa<UndefValue>(Address) ||
4804 (Address->use_empty() && !isa<Argument>(Address))) {
4805 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4809 SDValue &N = NodeMap[Address];
4810 if (!N.getNode() && isa<Argument>(Address))
4811 // Check unused arguments map.
4812 N = UnusedArgNodeMap[Address];
4815 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4816 Address = BCI->getOperand(0);
4817 // Parameters are handled specially.
4819 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4820 isa<Argument>(Address));
4822 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4824 if (isParameter && !AI) {
4825 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4827 // Byval parameter. We have a frame index at this point.
4828 SDV = DAG.getFrameIndexDbgValue(
4829 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4831 // Address is an argument, so try to emit its dbg value using
4832 // virtual register info from the FuncInfo.ValueMap.
4833 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4837 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4838 true, 0, dl, SDNodeOrder);
4840 // Can't do anything with other non-AI cases yet.
4841 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4842 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4843 DEBUG(Address->dump());
4846 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4848 // If Address is an argument then try to emit its dbg value using
4849 // virtual register info from the FuncInfo.ValueMap.
4850 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4852 // If variable is pinned by a alloca in dominating bb then
4853 // use StaticAllocaMap.
4854 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4855 if (AI->getParent() != DI.getParent()) {
4856 DenseMap<const AllocaInst*, int>::iterator SI =
4857 FuncInfo.StaticAllocaMap.find(AI);
4858 if (SI != FuncInfo.StaticAllocaMap.end()) {
4859 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4860 0, dl, SDNodeOrder);
4861 DAG.AddDbgValue(SDV, nullptr, false);
4866 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4871 case Intrinsic::dbg_value: {
4872 const DbgValueInst &DI = cast<DbgValueInst>(I);
4873 DIVariable DIVar(DI.getVariable());
4874 assert((!DIVar || DIVar.isVariable()) &&
4875 "Variable in DbgValueInst should be either null or a DIVariable.");
4879 MDNode *Variable = DI.getVariable();
4880 MDNode *Expression = DI.getExpression();
4881 uint64_t Offset = DI.getOffset();
4882 const Value *V = DI.getValue();
4887 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4888 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4890 DAG.AddDbgValue(SDV, nullptr, false);
4892 // Do not use getValue() in here; we don't want to generate code at
4893 // this point if it hasn't been done yet.
4894 SDValue N = NodeMap[V];
4895 if (!N.getNode() && isa<Argument>(V))
4896 // Check unused arguments map.
4897 N = UnusedArgNodeMap[V];
4899 // A dbg.value for an alloca is always indirect.
4900 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4901 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4903 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4904 IsIndirect, Offset, dl, SDNodeOrder);
4905 DAG.AddDbgValue(SDV, N.getNode(), false);
4907 } else if (!V->use_empty() ) {
4908 // Do not call getValue(V) yet, as we don't want to generate code.
4909 // Remember it for later.
4910 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4911 DanglingDebugInfoMap[V] = DDI;
4913 // We may expand this to cover more cases. One case where we have no
4914 // data available is an unreferenced parameter.
4915 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4919 // Build a debug info table entry.
4920 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4921 V = BCI->getOperand(0);
4922 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4923 // Don't handle byval struct arguments or VLAs, for example.
4925 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4926 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4929 DenseMap<const AllocaInst*, int>::iterator SI =
4930 FuncInfo.StaticAllocaMap.find(AI);
4931 if (SI == FuncInfo.StaticAllocaMap.end())
4932 return nullptr; // VLAs.
4936 case Intrinsic::eh_typeid_for: {
4937 // Find the type id for the given typeinfo.
4938 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4939 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4940 Res = DAG.getConstant(TypeID, MVT::i32);
4945 case Intrinsic::eh_return_i32:
4946 case Intrinsic::eh_return_i64:
4947 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4948 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4951 getValue(I.getArgOperand(0)),
4952 getValue(I.getArgOperand(1))));
4954 case Intrinsic::eh_unwind_init:
4955 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4957 case Intrinsic::eh_dwarf_cfa: {
4958 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4959 TLI->getPointerTy());
4960 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4961 CfaArg.getValueType(),
4962 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4963 CfaArg.getValueType()),
4965 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4966 TLI->getPointerTy(),
4967 DAG.getConstant(0, TLI->getPointerTy()));
4968 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4972 case Intrinsic::eh_sjlj_callsite: {
4973 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4974 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4975 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4976 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4978 MMI.setCurrentCallSite(CI->getZExtValue());
4981 case Intrinsic::eh_sjlj_functioncontext: {
4982 // Get and store the index of the function context.
4983 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4985 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4986 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4987 MFI->setFunctionContextIndex(FI);
4990 case Intrinsic::eh_sjlj_setjmp: {
4993 Ops[1] = getValue(I.getArgOperand(0));
4994 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4995 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4996 setValue(&I, Op.getValue(0));
4997 DAG.setRoot(Op.getValue(1));
5000 case Intrinsic::eh_sjlj_longjmp: {
5001 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5002 getRoot(), getValue(I.getArgOperand(0))));
5006 case Intrinsic::x86_mmx_pslli_w:
5007 case Intrinsic::x86_mmx_pslli_d:
5008 case Intrinsic::x86_mmx_pslli_q:
5009 case Intrinsic::x86_mmx_psrli_w:
5010 case Intrinsic::x86_mmx_psrli_d:
5011 case Intrinsic::x86_mmx_psrli_q:
5012 case Intrinsic::x86_mmx_psrai_w:
5013 case Intrinsic::x86_mmx_psrai_d: {
5014 SDValue ShAmt = getValue(I.getArgOperand(1));
5015 if (isa<ConstantSDNode>(ShAmt)) {
5016 visitTargetIntrinsic(I, Intrinsic);
5019 unsigned NewIntrinsic = 0;
5020 EVT ShAmtVT = MVT::v2i32;
5021 switch (Intrinsic) {
5022 case Intrinsic::x86_mmx_pslli_w:
5023 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5025 case Intrinsic::x86_mmx_pslli_d:
5026 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5028 case Intrinsic::x86_mmx_pslli_q:
5029 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5031 case Intrinsic::x86_mmx_psrli_w:
5032 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5034 case Intrinsic::x86_mmx_psrli_d:
5035 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5037 case Intrinsic::x86_mmx_psrli_q:
5038 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5040 case Intrinsic::x86_mmx_psrai_w:
5041 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5043 case Intrinsic::x86_mmx_psrai_d:
5044 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5046 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5049 // The vector shift intrinsics with scalars uses 32b shift amounts but
5050 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5052 // We must do this early because v2i32 is not a legal type.
5055 ShOps[1] = DAG.getConstant(0, MVT::i32);
5056 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5057 EVT DestVT = TLI->getValueType(I.getType());
5058 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5059 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5060 DAG.getConstant(NewIntrinsic, MVT::i32),
5061 getValue(I.getArgOperand(0)), ShAmt);
5065 case Intrinsic::x86_avx_vinsertf128_pd_256:
5066 case Intrinsic::x86_avx_vinsertf128_ps_256:
5067 case Intrinsic::x86_avx_vinsertf128_si_256:
5068 case Intrinsic::x86_avx2_vinserti128: {
5069 EVT DestVT = TLI->getValueType(I.getType());
5070 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
5071 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5072 ElVT.getVectorNumElements();
5073 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5074 getValue(I.getArgOperand(0)),
5075 getValue(I.getArgOperand(1)),
5076 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5080 case Intrinsic::x86_avx_vextractf128_pd_256:
5081 case Intrinsic::x86_avx_vextractf128_ps_256:
5082 case Intrinsic::x86_avx_vextractf128_si_256:
5083 case Intrinsic::x86_avx2_vextracti128: {
5084 EVT DestVT = TLI->getValueType(I.getType());
5085 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5086 DestVT.getVectorNumElements();
5087 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5088 getValue(I.getArgOperand(0)),
5089 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5093 case Intrinsic::convertff:
5094 case Intrinsic::convertfsi:
5095 case Intrinsic::convertfui:
5096 case Intrinsic::convertsif:
5097 case Intrinsic::convertuif:
5098 case Intrinsic::convertss:
5099 case Intrinsic::convertsu:
5100 case Intrinsic::convertus:
5101 case Intrinsic::convertuu: {
5102 ISD::CvtCode Code = ISD::CVT_INVALID;
5103 switch (Intrinsic) {
5104 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5105 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5106 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5107 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5108 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5109 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5110 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5111 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5112 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5113 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5115 EVT DestVT = TLI->getValueType(I.getType());
5116 const Value *Op1 = I.getArgOperand(0);
5117 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5118 DAG.getValueType(DestVT),
5119 DAG.getValueType(getValue(Op1).getValueType()),
5120 getValue(I.getArgOperand(1)),
5121 getValue(I.getArgOperand(2)),
5126 case Intrinsic::powi:
5127 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5128 getValue(I.getArgOperand(1)), DAG));
5130 case Intrinsic::log:
5131 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5133 case Intrinsic::log2:
5134 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5136 case Intrinsic::log10:
5137 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5139 case Intrinsic::exp:
5140 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5142 case Intrinsic::exp2:
5143 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5145 case Intrinsic::pow:
5146 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5147 getValue(I.getArgOperand(1)), DAG, *TLI));
5149 case Intrinsic::sqrt:
5150 case Intrinsic::fabs:
5151 case Intrinsic::sin:
5152 case Intrinsic::cos:
5153 case Intrinsic::floor:
5154 case Intrinsic::ceil:
5155 case Intrinsic::trunc:
5156 case Intrinsic::rint:
5157 case Intrinsic::nearbyint:
5158 case Intrinsic::round: {
5160 switch (Intrinsic) {
5161 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5162 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5163 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5164 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5165 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5166 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5167 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5168 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5169 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5170 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5171 case Intrinsic::round: Opcode = ISD::FROUND; break;
5174 setValue(&I, DAG.getNode(Opcode, sdl,
5175 getValue(I.getArgOperand(0)).getValueType(),
5176 getValue(I.getArgOperand(0))));
5179 case Intrinsic::copysign:
5180 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5181 getValue(I.getArgOperand(0)).getValueType(),
5182 getValue(I.getArgOperand(0)),
5183 getValue(I.getArgOperand(1))));
5185 case Intrinsic::fma:
5186 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5187 getValue(I.getArgOperand(0)).getValueType(),
5188 getValue(I.getArgOperand(0)),
5189 getValue(I.getArgOperand(1)),
5190 getValue(I.getArgOperand(2))));
5192 case Intrinsic::fmuladd: {
5193 EVT VT = TLI->getValueType(I.getType());
5194 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5195 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5196 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5197 getValue(I.getArgOperand(0)).getValueType(),
5198 getValue(I.getArgOperand(0)),
5199 getValue(I.getArgOperand(1)),
5200 getValue(I.getArgOperand(2))));
5202 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5203 getValue(I.getArgOperand(0)).getValueType(),
5204 getValue(I.getArgOperand(0)),
5205 getValue(I.getArgOperand(1)));
5206 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5207 getValue(I.getArgOperand(0)).getValueType(),
5209 getValue(I.getArgOperand(2)));
5214 case Intrinsic::convert_to_fp16:
5215 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5216 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5217 getValue(I.getArgOperand(0)),
5218 DAG.getTargetConstant(0, MVT::i32))));
5220 case Intrinsic::convert_from_fp16:
5222 DAG.getNode(ISD::FP_EXTEND, sdl, TLI->getValueType(I.getType()),
5223 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5224 getValue(I.getArgOperand(0)))));
5226 case Intrinsic::pcmarker: {
5227 SDValue Tmp = getValue(I.getArgOperand(0));
5228 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5231 case Intrinsic::readcyclecounter: {
5232 SDValue Op = getRoot();
5233 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5234 DAG.getVTList(MVT::i64, MVT::Other), Op);
5236 DAG.setRoot(Res.getValue(1));
5239 case Intrinsic::bswap:
5240 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5241 getValue(I.getArgOperand(0)).getValueType(),
5242 getValue(I.getArgOperand(0))));
5244 case Intrinsic::cttz: {
5245 SDValue Arg = getValue(I.getArgOperand(0));
5246 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5247 EVT Ty = Arg.getValueType();
5248 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5252 case Intrinsic::ctlz: {
5253 SDValue Arg = getValue(I.getArgOperand(0));
5254 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5255 EVT Ty = Arg.getValueType();
5256 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5260 case Intrinsic::ctpop: {
5261 SDValue Arg = getValue(I.getArgOperand(0));
5262 EVT Ty = Arg.getValueType();
5263 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5266 case Intrinsic::stacksave: {
5267 SDValue Op = getRoot();
5268 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5269 DAG.getVTList(TLI->getPointerTy(), MVT::Other), Op);
5271 DAG.setRoot(Res.getValue(1));
5274 case Intrinsic::stackrestore: {
5275 Res = getValue(I.getArgOperand(0));
5276 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5279 case Intrinsic::stackprotector: {
5280 // Emit code into the DAG to store the stack guard onto the stack.
5281 MachineFunction &MF = DAG.getMachineFunction();
5282 MachineFrameInfo *MFI = MF.getFrameInfo();
5283 EVT PtrTy = TLI->getPointerTy();
5284 SDValue Src, Chain = getRoot();
5285 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5286 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5288 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5289 // global variable __stack_chk_guard.
5291 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5292 if (BC->getOpcode() == Instruction::BitCast)
5293 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5295 if (GV && TLI->useLoadStackGuardNode()) {
5296 // Emit a LOAD_STACK_GUARD node.
5297 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5299 MachinePointerInfo MPInfo(GV);
5300 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5301 unsigned Flags = MachineMemOperand::MOLoad |
5302 MachineMemOperand::MOInvariant;
5303 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5304 PtrTy.getSizeInBits() / 8,
5305 DAG.getEVTAlignment(PtrTy));
5306 Node->setMemRefs(MemRefs, MemRefs + 1);
5308 // Copy the guard value to a virtual register so that it can be
5309 // retrieved in the epilogue.
5310 Src = SDValue(Node, 0);
5311 const TargetRegisterClass *RC =
5312 TLI->getRegClassFor(Src.getSimpleValueType());
5313 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5315 SPDescriptor.setGuardReg(Reg);
5316 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5318 Src = getValue(I.getArgOperand(0)); // The guard's value.
5321 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5323 int FI = FuncInfo.StaticAllocaMap[Slot];
5324 MFI->setStackProtectorIndex(FI);
5326 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5328 // Store the stack protector onto the stack.
5329 Res = DAG.getStore(Chain, sdl, Src, FIN,
5330 MachinePointerInfo::getFixedStack(FI),
5336 case Intrinsic::objectsize: {
5337 // If we don't know by now, we're never going to know.
5338 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5340 assert(CI && "Non-constant type in __builtin_object_size?");
5342 SDValue Arg = getValue(I.getCalledValue());
5343 EVT Ty = Arg.getValueType();
5346 Res = DAG.getConstant(-1ULL, Ty);
5348 Res = DAG.getConstant(0, Ty);
5353 case Intrinsic::annotation:
5354 case Intrinsic::ptr_annotation:
5355 // Drop the intrinsic, but forward the value
5356 setValue(&I, getValue(I.getOperand(0)));
5358 case Intrinsic::assume:
5359 case Intrinsic::var_annotation:
5360 // Discard annotate attributes and assumptions
5363 case Intrinsic::init_trampoline: {
5364 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5368 Ops[1] = getValue(I.getArgOperand(0));
5369 Ops[2] = getValue(I.getArgOperand(1));
5370 Ops[3] = getValue(I.getArgOperand(2));
5371 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5372 Ops[5] = DAG.getSrcValue(F);
5374 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5379 case Intrinsic::adjust_trampoline: {
5380 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5381 TLI->getPointerTy(),
5382 getValue(I.getArgOperand(0))));
5385 case Intrinsic::gcroot:
5387 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5388 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5390 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5391 GFI->addStackRoot(FI->getIndex(), TypeMap);
5394 case Intrinsic::gcread:
5395 case Intrinsic::gcwrite:
5396 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5397 case Intrinsic::flt_rounds:
5398 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5401 case Intrinsic::expect: {
5402 // Just replace __builtin_expect(exp, c) with EXP.
5403 setValue(&I, getValue(I.getArgOperand(0)));
5407 case Intrinsic::debugtrap:
5408 case Intrinsic::trap: {
5409 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5410 if (TrapFuncName.empty()) {
5411 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5412 ISD::TRAP : ISD::DEBUGTRAP;
5413 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5416 TargetLowering::ArgListTy Args;
5418 TargetLowering::CallLoweringInfo CLI(DAG);
5419 CLI.setDebugLoc(sdl).setChain(getRoot())
5420 .setCallee(CallingConv::C, I.getType(),
5421 DAG.getExternalSymbol(TrapFuncName.data(), TLI->getPointerTy()),
5422 std::move(Args), 0);
5424 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5425 DAG.setRoot(Result.second);
5429 case Intrinsic::uadd_with_overflow:
5430 case Intrinsic::sadd_with_overflow:
5431 case Intrinsic::usub_with_overflow:
5432 case Intrinsic::ssub_with_overflow:
5433 case Intrinsic::umul_with_overflow:
5434 case Intrinsic::smul_with_overflow: {
5436 switch (Intrinsic) {
5437 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5438 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5439 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5440 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5441 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5442 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5443 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5445 SDValue Op1 = getValue(I.getArgOperand(0));
5446 SDValue Op2 = getValue(I.getArgOperand(1));
5448 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5449 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5452 case Intrinsic::prefetch: {
5454 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5456 Ops[1] = getValue(I.getArgOperand(0));
5457 Ops[2] = getValue(I.getArgOperand(1));
5458 Ops[3] = getValue(I.getArgOperand(2));
5459 Ops[4] = getValue(I.getArgOperand(3));
5460 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5461 DAG.getVTList(MVT::Other), Ops,
5462 EVT::getIntegerVT(*Context, 8),
5463 MachinePointerInfo(I.getArgOperand(0)),
5465 false, /* volatile */
5467 rw==1)); /* write */
5470 case Intrinsic::lifetime_start:
5471 case Intrinsic::lifetime_end: {
5472 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5473 // Stack coloring is not enabled in O0, discard region information.
5474 if (TM.getOptLevel() == CodeGenOpt::None)
5477 SmallVector<Value *, 4> Allocas;
5478 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5480 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5481 E = Allocas.end(); Object != E; ++Object) {
5482 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5484 // Could not find an Alloca.
5485 if (!LifetimeObject)
5488 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5492 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5493 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5495 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5500 case Intrinsic::invariant_start:
5501 // Discard region information.
5502 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5504 case Intrinsic::invariant_end:
5505 // Discard region information.
5507 case Intrinsic::stackprotectorcheck: {
5508 // Do not actually emit anything for this basic block. Instead we initialize
5509 // the stack protector descriptor and export the guard variable so we can
5510 // access it in FinishBasicBlock.
5511 const BasicBlock *BB = I.getParent();
5512 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5513 ExportFromCurrentBlock(SPDescriptor.getGuard());
5515 // Flush our exports since we are going to process a terminator.
5516 (void)getControlRoot();
5519 case Intrinsic::clear_cache:
5520 return TLI->getClearCacheBuiltinName();
5521 case Intrinsic::donothing:
5524 case Intrinsic::experimental_stackmap: {
5528 case Intrinsic::experimental_patchpoint_void:
5529 case Intrinsic::experimental_patchpoint_i64: {
5536 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5538 MachineBasicBlock *LandingPad) {
5539 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5540 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5541 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5542 Type *RetTy = FTy->getReturnType();
5543 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5544 MCSymbol *BeginLabel = nullptr;
5546 TargetLowering::ArgListTy Args;
5547 TargetLowering::ArgListEntry Entry;
5548 Args.reserve(CS.arg_size());
5550 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5552 const Value *V = *i;
5555 if (V->getType()->isEmptyTy())
5558 SDValue ArgNode = getValue(V);
5559 Entry.Node = ArgNode; Entry.Ty = V->getType();
5561 // Skip the first return-type Attribute to get to params.
5562 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5563 Args.push_back(Entry);
5567 // Insert a label before the invoke call to mark the try range. This can be
5568 // used to detect deletion of the invoke via the MachineModuleInfo.
5569 BeginLabel = MMI.getContext().CreateTempSymbol();
5571 // For SjLj, keep track of which landing pads go with which invokes
5572 // so as to maintain the ordering of pads in the LSDA.
5573 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5574 if (CallSiteIndex) {
5575 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5576 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5578 // Now that the call site is handled, stop tracking it.
5579 MMI.setCurrentCallSite(0);
5582 // Both PendingLoads and PendingExports must be flushed here;
5583 // this call might not return.
5585 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5588 // Check if target-independent constraints permit a tail call here.
5589 // Target-dependent constraints are checked within TLI->LowerCallTo.
5590 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5593 TargetLowering::CallLoweringInfo CLI(DAG);
5594 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5595 .setCallee(RetTy, FTy, Callee, std::move(Args), CS).setTailCall(isTailCall);
5597 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5598 assert((isTailCall || Result.second.getNode()) &&
5599 "Non-null chain expected with non-tail call!");
5600 assert((Result.second.getNode() || !Result.first.getNode()) &&
5601 "Null value expected with tail call!");
5602 if (Result.first.getNode())
5603 setValue(CS.getInstruction(), Result.first);
5605 if (!Result.second.getNode()) {
5606 // As a special case, a null chain means that a tail call has been emitted
5607 // and the DAG root is already updated.
5610 // Since there's no actual continuation from this block, nothing can be
5611 // relying on us setting vregs for them.
5612 PendingExports.clear();
5614 DAG.setRoot(Result.second);
5618 // Insert a label at the end of the invoke call to mark the try range. This
5619 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5620 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5621 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5623 // Inform MachineModuleInfo of range.
5624 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5628 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5629 /// value is equal or not-equal to zero.
5630 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5631 for (const User *U : V->users()) {
5632 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5633 if (IC->isEquality())
5634 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5635 if (C->isNullValue())
5637 // Unknown instruction.
5643 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5645 SelectionDAGBuilder &Builder) {
5647 // Check to see if this load can be trivially constant folded, e.g. if the
5648 // input is from a string literal.
5649 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5650 // Cast pointer to the type we really want to load.
5651 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5652 PointerType::getUnqual(LoadTy));
5654 if (const Constant *LoadCst =
5655 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5657 return Builder.getValue(LoadCst);
5660 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5661 // still constant memory, the input chain can be the entry node.
5663 bool ConstantMemory = false;
5665 // Do not serialize (non-volatile) loads of constant memory with anything.
5666 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5667 Root = Builder.DAG.getEntryNode();
5668 ConstantMemory = true;
5670 // Do not serialize non-volatile loads against each other.
5671 Root = Builder.DAG.getRoot();
5674 SDValue Ptr = Builder.getValue(PtrVal);
5675 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5676 Ptr, MachinePointerInfo(PtrVal),
5678 false /*nontemporal*/,
5679 false /*isinvariant*/, 1 /* align=1 */);
5681 if (!ConstantMemory)
5682 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5686 /// processIntegerCallValue - Record the value for an instruction that
5687 /// produces an integer result, converting the type where necessary.
5688 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5691 EVT VT = TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType(),
5694 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5696 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5697 setValue(&I, Value);
5700 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5701 /// If so, return true and lower it, otherwise return false and it will be
5702 /// lowered like a normal call.
5703 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5704 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5705 if (I.getNumArgOperands() != 3)
5708 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5709 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5710 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5711 !I.getType()->isIntegerTy())
5714 const Value *Size = I.getArgOperand(2);
5715 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5716 if (CSize && CSize->getZExtValue() == 0) {
5717 EVT CallVT = TM.getSubtargetImpl()->getTargetLowering()->getValueType(
5719 setValue(&I, DAG.getConstant(0, CallVT));
5723 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5724 std::pair<SDValue, SDValue> Res =
5725 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5726 getValue(LHS), getValue(RHS), getValue(Size),
5727 MachinePointerInfo(LHS),
5728 MachinePointerInfo(RHS));
5729 if (Res.first.getNode()) {
5730 processIntegerCallValue(I, Res.first, true);
5731 PendingLoads.push_back(Res.second);
5735 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5736 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5737 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5738 bool ActuallyDoIt = true;
5741 switch (CSize->getZExtValue()) {
5743 LoadVT = MVT::Other;
5745 ActuallyDoIt = false;
5749 LoadTy = Type::getInt16Ty(CSize->getContext());
5753 LoadTy = Type::getInt32Ty(CSize->getContext());
5757 LoadTy = Type::getInt64Ty(CSize->getContext());
5761 LoadVT = MVT::v4i32;
5762 LoadTy = Type::getInt32Ty(CSize->getContext());
5763 LoadTy = VectorType::get(LoadTy, 4);
5768 // This turns into unaligned loads. We only do this if the target natively
5769 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5770 // we'll only produce a small number of byte loads.
5772 // Require that we can find a legal MVT, and only do this if the target
5773 // supports unaligned loads of that type. Expanding into byte loads would
5775 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5776 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5777 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5778 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5779 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5780 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5781 // TODO: Check alignment of src and dest ptrs.
5782 if (!TLI->isTypeLegal(LoadVT) ||
5783 !TLI->allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5784 !TLI->allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5785 ActuallyDoIt = false;
5789 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5790 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5792 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5794 processIntegerCallValue(I, Res, false);
5803 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5804 /// form. If so, return true and lower it, otherwise return false and it
5805 /// will be lowered like a normal call.
5806 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5807 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5808 if (I.getNumArgOperands() != 3)
5811 const Value *Src = I.getArgOperand(0);
5812 const Value *Char = I.getArgOperand(1);
5813 const Value *Length = I.getArgOperand(2);
5814 if (!Src->getType()->isPointerTy() ||
5815 !Char->getType()->isIntegerTy() ||
5816 !Length->getType()->isIntegerTy() ||
5817 !I.getType()->isPointerTy())
5820 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5821 std::pair<SDValue, SDValue> Res =
5822 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5823 getValue(Src), getValue(Char), getValue(Length),
5824 MachinePointerInfo(Src));
5825 if (Res.first.getNode()) {
5826 setValue(&I, Res.first);
5827 PendingLoads.push_back(Res.second);
5834 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5835 /// optimized form. If so, return true and lower it, otherwise return false
5836 /// and it will be lowered like a normal call.
5837 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5838 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5839 if (I.getNumArgOperands() != 2)
5842 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5843 if (!Arg0->getType()->isPointerTy() ||
5844 !Arg1->getType()->isPointerTy() ||
5845 !I.getType()->isPointerTy())
5848 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5849 std::pair<SDValue, SDValue> Res =
5850 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5851 getValue(Arg0), getValue(Arg1),
5852 MachinePointerInfo(Arg0),
5853 MachinePointerInfo(Arg1), isStpcpy);
5854 if (Res.first.getNode()) {
5855 setValue(&I, Res.first);
5856 DAG.setRoot(Res.second);
5863 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5864 /// If so, return true and lower it, otherwise return false and it will be
5865 /// lowered like a normal call.
5866 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5867 // Verify that the prototype makes sense. int strcmp(void*,void*)
5868 if (I.getNumArgOperands() != 2)
5871 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5872 if (!Arg0->getType()->isPointerTy() ||
5873 !Arg1->getType()->isPointerTy() ||
5874 !I.getType()->isIntegerTy())
5877 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5878 std::pair<SDValue, SDValue> Res =
5879 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5880 getValue(Arg0), getValue(Arg1),
5881 MachinePointerInfo(Arg0),
5882 MachinePointerInfo(Arg1));
5883 if (Res.first.getNode()) {
5884 processIntegerCallValue(I, Res.first, true);
5885 PendingLoads.push_back(Res.second);
5892 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5893 /// form. If so, return true and lower it, otherwise return false and it
5894 /// will be lowered like a normal call.
5895 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5896 // Verify that the prototype makes sense. size_t strlen(char *)
5897 if (I.getNumArgOperands() != 1)
5900 const Value *Arg0 = I.getArgOperand(0);
5901 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5904 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5905 std::pair<SDValue, SDValue> Res =
5906 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5907 getValue(Arg0), MachinePointerInfo(Arg0));
5908 if (Res.first.getNode()) {
5909 processIntegerCallValue(I, Res.first, false);
5910 PendingLoads.push_back(Res.second);
5917 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5918 /// form. If so, return true and lower it, otherwise return false and it
5919 /// will be lowered like a normal call.
5920 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5921 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5922 if (I.getNumArgOperands() != 2)
5925 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5926 if (!Arg0->getType()->isPointerTy() ||
5927 !Arg1->getType()->isIntegerTy() ||
5928 !I.getType()->isIntegerTy())
5931 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5932 std::pair<SDValue, SDValue> Res =
5933 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5934 getValue(Arg0), getValue(Arg1),
5935 MachinePointerInfo(Arg0));
5936 if (Res.first.getNode()) {
5937 processIntegerCallValue(I, Res.first, false);
5938 PendingLoads.push_back(Res.second);
5945 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5946 /// operation (as expected), translate it to an SDNode with the specified opcode
5947 /// and return true.
5948 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5950 // Sanity check that it really is a unary floating-point call.
5951 if (I.getNumArgOperands() != 1 ||
5952 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5953 I.getType() != I.getArgOperand(0)->getType() ||
5954 !I.onlyReadsMemory())
5957 SDValue Tmp = getValue(I.getArgOperand(0));
5958 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5962 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5963 // Handle inline assembly differently.
5964 if (isa<InlineAsm>(I.getCalledValue())) {
5969 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5970 ComputeUsesVAFloatArgument(I, &MMI);
5972 const char *RenameFn = nullptr;
5973 if (Function *F = I.getCalledFunction()) {
5974 if (F->isDeclaration()) {
5975 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5976 if (unsigned IID = II->getIntrinsicID(F)) {
5977 RenameFn = visitIntrinsicCall(I, IID);
5982 if (unsigned IID = F->getIntrinsicID()) {
5983 RenameFn = visitIntrinsicCall(I, IID);
5989 // Check for well-known libc/libm calls. If the function is internal, it
5990 // can't be a library call.
5992 if (!F->hasLocalLinkage() && F->hasName() &&
5993 LibInfo->getLibFunc(F->getName(), Func) &&
5994 LibInfo->hasOptimizedCodeGen(Func)) {
5997 case LibFunc::copysign:
5998 case LibFunc::copysignf:
5999 case LibFunc::copysignl:
6000 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6001 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6002 I.getType() == I.getArgOperand(0)->getType() &&
6003 I.getType() == I.getArgOperand(1)->getType() &&
6004 I.onlyReadsMemory()) {
6005 SDValue LHS = getValue(I.getArgOperand(0));
6006 SDValue RHS = getValue(I.getArgOperand(1));
6007 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6008 LHS.getValueType(), LHS, RHS));
6013 case LibFunc::fabsf:
6014 case LibFunc::fabsl:
6015 if (visitUnaryFloatCall(I, ISD::FABS))
6021 if (visitUnaryFloatCall(I, ISD::FSIN))
6027 if (visitUnaryFloatCall(I, ISD::FCOS))
6031 case LibFunc::sqrtf:
6032 case LibFunc::sqrtl:
6033 case LibFunc::sqrt_finite:
6034 case LibFunc::sqrtf_finite:
6035 case LibFunc::sqrtl_finite:
6036 if (visitUnaryFloatCall(I, ISD::FSQRT))
6039 case LibFunc::floor:
6040 case LibFunc::floorf:
6041 case LibFunc::floorl:
6042 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6045 case LibFunc::nearbyint:
6046 case LibFunc::nearbyintf:
6047 case LibFunc::nearbyintl:
6048 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6052 case LibFunc::ceilf:
6053 case LibFunc::ceill:
6054 if (visitUnaryFloatCall(I, ISD::FCEIL))
6058 case LibFunc::rintf:
6059 case LibFunc::rintl:
6060 if (visitUnaryFloatCall(I, ISD::FRINT))
6063 case LibFunc::round:
6064 case LibFunc::roundf:
6065 case LibFunc::roundl:
6066 if (visitUnaryFloatCall(I, ISD::FROUND))
6069 case LibFunc::trunc:
6070 case LibFunc::truncf:
6071 case LibFunc::truncl:
6072 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6076 case LibFunc::log2f:
6077 case LibFunc::log2l:
6078 if (visitUnaryFloatCall(I, ISD::FLOG2))
6082 case LibFunc::exp2f:
6083 case LibFunc::exp2l:
6084 if (visitUnaryFloatCall(I, ISD::FEXP2))
6087 case LibFunc::memcmp:
6088 if (visitMemCmpCall(I))
6091 case LibFunc::memchr:
6092 if (visitMemChrCall(I))
6095 case LibFunc::strcpy:
6096 if (visitStrCpyCall(I, false))
6099 case LibFunc::stpcpy:
6100 if (visitStrCpyCall(I, true))
6103 case LibFunc::strcmp:
6104 if (visitStrCmpCall(I))
6107 case LibFunc::strlen:
6108 if (visitStrLenCall(I))
6111 case LibFunc::strnlen:
6112 if (visitStrNLenCall(I))
6121 Callee = getValue(I.getCalledValue());
6123 Callee = DAG.getExternalSymbol(
6124 RenameFn, TM.getSubtargetImpl()->getTargetLowering()->getPointerTy());
6126 // Check if we can potentially perform a tail call. More detailed checking is
6127 // be done within LowerCallTo, after more information about the call is known.
6128 LowerCallTo(&I, Callee, I.isTailCall());
6133 /// AsmOperandInfo - This contains information for each constraint that we are
6135 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6137 /// CallOperand - If this is the result output operand or a clobber
6138 /// this is null, otherwise it is the incoming operand to the CallInst.
6139 /// This gets modified as the asm is processed.
6140 SDValue CallOperand;
6142 /// AssignedRegs - If this is a register or register class operand, this
6143 /// contains the set of register corresponding to the operand.
6144 RegsForValue AssignedRegs;
6146 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6147 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6150 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6151 /// corresponds to. If there is no Value* for this operand, it returns
6153 EVT getCallOperandValEVT(LLVMContext &Context,
6154 const TargetLowering &TLI,
6155 const DataLayout *DL) const {
6156 if (!CallOperandVal) return MVT::Other;
6158 if (isa<BasicBlock>(CallOperandVal))
6159 return TLI.getPointerTy();
6161 llvm::Type *OpTy = CallOperandVal->getType();
6163 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6164 // If this is an indirect operand, the operand is a pointer to the
6167 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6169 report_fatal_error("Indirect operand for inline asm not a pointer!");
6170 OpTy = PtrTy->getElementType();
6173 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6174 if (StructType *STy = dyn_cast<StructType>(OpTy))
6175 if (STy->getNumElements() == 1)
6176 OpTy = STy->getElementType(0);
6178 // If OpTy is not a single value, it may be a struct/union that we
6179 // can tile with integers.
6180 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6181 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6190 OpTy = IntegerType::get(Context, BitSize);
6195 return TLI.getValueType(OpTy, true);
6199 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6201 } // end anonymous namespace
6203 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6204 /// specified operand. We prefer to assign virtual registers, to allow the
6205 /// register allocator to handle the assignment process. However, if the asm
6206 /// uses features that we can't model on machineinstrs, we have SDISel do the
6207 /// allocation. This produces generally horrible, but correct, code.
6209 /// OpInfo describes the operand.
6211 static void GetRegistersForValue(SelectionDAG &DAG,
6212 const TargetLowering &TLI,
6214 SDISelAsmOperandInfo &OpInfo) {
6215 LLVMContext &Context = *DAG.getContext();
6217 MachineFunction &MF = DAG.getMachineFunction();
6218 SmallVector<unsigned, 4> Regs;
6220 // If this is a constraint for a single physreg, or a constraint for a
6221 // register class, find it.
6222 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6223 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6224 OpInfo.ConstraintVT);
6226 unsigned NumRegs = 1;
6227 if (OpInfo.ConstraintVT != MVT::Other) {
6228 // If this is a FP input in an integer register (or visa versa) insert a bit
6229 // cast of the input value. More generally, handle any case where the input
6230 // value disagrees with the register class we plan to stick this in.
6231 if (OpInfo.Type == InlineAsm::isInput &&
6232 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6233 // Try to convert to the first EVT that the reg class contains. If the
6234 // types are identical size, use a bitcast to convert (e.g. two differing
6236 MVT RegVT = *PhysReg.second->vt_begin();
6237 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6238 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6239 RegVT, OpInfo.CallOperand);
6240 OpInfo.ConstraintVT = RegVT;
6241 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6242 // If the input is a FP value and we want it in FP registers, do a
6243 // bitcast to the corresponding integer type. This turns an f64 value
6244 // into i64, which can be passed with two i32 values on a 32-bit
6246 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6247 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6248 RegVT, OpInfo.CallOperand);
6249 OpInfo.ConstraintVT = RegVT;
6253 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6257 EVT ValueVT = OpInfo.ConstraintVT;
6259 // If this is a constraint for a specific physical register, like {r17},
6261 if (unsigned AssignedReg = PhysReg.first) {
6262 const TargetRegisterClass *RC = PhysReg.second;
6263 if (OpInfo.ConstraintVT == MVT::Other)
6264 ValueVT = *RC->vt_begin();
6266 // Get the actual register value type. This is important, because the user
6267 // may have asked for (e.g.) the AX register in i32 type. We need to
6268 // remember that AX is actually i16 to get the right extension.
6269 RegVT = *RC->vt_begin();
6271 // This is a explicit reference to a physical register.
6272 Regs.push_back(AssignedReg);
6274 // If this is an expanded reference, add the rest of the regs to Regs.
6276 TargetRegisterClass::iterator I = RC->begin();
6277 for (; *I != AssignedReg; ++I)
6278 assert(I != RC->end() && "Didn't find reg!");
6280 // Already added the first reg.
6282 for (; NumRegs; --NumRegs, ++I) {
6283 assert(I != RC->end() && "Ran out of registers to allocate!");
6288 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6292 // Otherwise, if this was a reference to an LLVM register class, create vregs
6293 // for this reference.
6294 if (const TargetRegisterClass *RC = PhysReg.second) {
6295 RegVT = *RC->vt_begin();
6296 if (OpInfo.ConstraintVT == MVT::Other)
6299 // Create the appropriate number of virtual registers.
6300 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6301 for (; NumRegs; --NumRegs)
6302 Regs.push_back(RegInfo.createVirtualRegister(RC));
6304 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6308 // Otherwise, we couldn't allocate enough registers for this.
6311 /// visitInlineAsm - Handle a call to an InlineAsm object.
6313 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6314 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6316 /// ConstraintOperands - Information about all of the constraints.
6317 SDISelAsmOperandInfoVector ConstraintOperands;
6319 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6320 TargetLowering::AsmOperandInfoVector
6321 TargetConstraints = TLI->ParseConstraints(CS);
6323 bool hasMemory = false;
6325 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6326 unsigned ResNo = 0; // ResNo - The result number of the next output.
6327 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6328 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6329 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6331 MVT OpVT = MVT::Other;
6333 // Compute the value type for each operand.
6334 switch (OpInfo.Type) {
6335 case InlineAsm::isOutput:
6336 // Indirect outputs just consume an argument.
6337 if (OpInfo.isIndirect) {
6338 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6342 // The return value of the call is this value. As such, there is no
6343 // corresponding argument.
6344 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6345 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6346 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6348 assert(ResNo == 0 && "Asm only has one result!");
6349 OpVT = TLI->getSimpleValueType(CS.getType());
6353 case InlineAsm::isInput:
6354 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6356 case InlineAsm::isClobber:
6361 // If this is an input or an indirect output, process the call argument.
6362 // BasicBlocks are labels, currently appearing only in asm's.
6363 if (OpInfo.CallOperandVal) {
6364 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6365 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6367 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6370 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6374 OpInfo.ConstraintVT = OpVT;
6376 // Indirect operand accesses access memory.
6377 if (OpInfo.isIndirect)
6380 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6381 TargetLowering::ConstraintType
6382 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6383 if (CType == TargetLowering::C_Memory) {
6391 SDValue Chain, Flag;
6393 // We won't need to flush pending loads if this asm doesn't touch
6394 // memory and is nonvolatile.
6395 if (hasMemory || IA->hasSideEffects())
6398 Chain = DAG.getRoot();
6400 // Second pass over the constraints: compute which constraint option to use
6401 // and assign registers to constraints that want a specific physreg.
6402 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6403 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6405 // If this is an output operand with a matching input operand, look up the
6406 // matching input. If their types mismatch, e.g. one is an integer, the
6407 // other is floating point, or their sizes are different, flag it as an
6409 if (OpInfo.hasMatchingInput()) {
6410 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6412 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6413 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6414 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6415 OpInfo.ConstraintVT);
6416 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6417 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6418 Input.ConstraintVT);
6419 if ((OpInfo.ConstraintVT.isInteger() !=
6420 Input.ConstraintVT.isInteger()) ||
6421 (MatchRC.second != InputRC.second)) {
6422 report_fatal_error("Unsupported asm: input constraint"
6423 " with a matching output constraint of"
6424 " incompatible type!");
6426 Input.ConstraintVT = OpInfo.ConstraintVT;
6430 // Compute the constraint code and ConstraintType to use.
6431 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6433 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6434 OpInfo.Type == InlineAsm::isClobber)
6437 // If this is a memory input, and if the operand is not indirect, do what we
6438 // need to to provide an address for the memory input.
6439 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6440 !OpInfo.isIndirect) {
6441 assert((OpInfo.isMultipleAlternative ||
6442 (OpInfo.Type == InlineAsm::isInput)) &&
6443 "Can only indirectify direct input operands!");
6445 // Memory operands really want the address of the value. If we don't have
6446 // an indirect input, put it in the constpool if we can, otherwise spill
6447 // it to a stack slot.
6448 // TODO: This isn't quite right. We need to handle these according to
6449 // the addressing mode that the constraint wants. Also, this may take
6450 // an additional register for the computation and we don't want that
6453 // If the operand is a float, integer, or vector constant, spill to a
6454 // constant pool entry to get its address.
6455 const Value *OpVal = OpInfo.CallOperandVal;
6456 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6457 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6458 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6459 TLI->getPointerTy());
6461 // Otherwise, create a stack slot and emit a store to it before the
6463 Type *Ty = OpVal->getType();
6464 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6465 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6466 MachineFunction &MF = DAG.getMachineFunction();
6467 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6468 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6469 Chain = DAG.getStore(Chain, getCurSDLoc(),
6470 OpInfo.CallOperand, StackSlot,
6471 MachinePointerInfo::getFixedStack(SSFI),
6473 OpInfo.CallOperand = StackSlot;
6476 // There is no longer a Value* corresponding to this operand.
6477 OpInfo.CallOperandVal = nullptr;
6479 // It is now an indirect operand.
6480 OpInfo.isIndirect = true;
6483 // If this constraint is for a specific register, allocate it before
6485 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6486 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6489 // Second pass - Loop over all of the operands, assigning virtual or physregs
6490 // to register class operands.
6491 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6492 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6494 // C_Register operands have already been allocated, Other/Memory don't need
6496 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6497 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6500 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6501 std::vector<SDValue> AsmNodeOperands;
6502 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6503 AsmNodeOperands.push_back(
6504 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6505 TLI->getPointerTy()));
6507 // If we have a !srcloc metadata node associated with it, we want to attach
6508 // this to the ultimately generated inline asm machineinstr. To do this, we
6509 // pass in the third operand as this (potentially null) inline asm MDNode.
6510 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6511 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6513 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6514 // bits as operand 3.
6515 unsigned ExtraInfo = 0;
6516 if (IA->hasSideEffects())
6517 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6518 if (IA->isAlignStack())
6519 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6520 // Set the asm dialect.
6521 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6523 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6524 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6525 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6527 // Compute the constraint code and ConstraintType to use.
6528 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6530 // Ideally, we would only check against memory constraints. However, the
6531 // meaning of an other constraint can be target-specific and we can't easily
6532 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6533 // for other constriants as well.
6534 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6535 OpInfo.ConstraintType == TargetLowering::C_Other) {
6536 if (OpInfo.Type == InlineAsm::isInput)
6537 ExtraInfo |= InlineAsm::Extra_MayLoad;
6538 else if (OpInfo.Type == InlineAsm::isOutput)
6539 ExtraInfo |= InlineAsm::Extra_MayStore;
6540 else if (OpInfo.Type == InlineAsm::isClobber)
6541 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6545 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6546 TLI->getPointerTy()));
6548 // Loop over all of the inputs, copying the operand values into the
6549 // appropriate registers and processing the output regs.
6550 RegsForValue RetValRegs;
6552 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6553 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6555 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6556 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6558 switch (OpInfo.Type) {
6559 case InlineAsm::isOutput: {
6560 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6561 OpInfo.ConstraintType != TargetLowering::C_Register) {
6562 // Memory output, or 'other' output (e.g. 'X' constraint).
6563 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6565 // Add information to the INLINEASM node to know about this output.
6566 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6567 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6568 TLI->getPointerTy()));
6569 AsmNodeOperands.push_back(OpInfo.CallOperand);
6573 // Otherwise, this is a register or register class output.
6575 // Copy the output from the appropriate register. Find a register that
6577 if (OpInfo.AssignedRegs.Regs.empty()) {
6578 LLVMContext &Ctx = *DAG.getContext();
6579 Ctx.emitError(CS.getInstruction(),
6580 "couldn't allocate output register for constraint '" +
6581 Twine(OpInfo.ConstraintCode) + "'");
6585 // If this is an indirect operand, store through the pointer after the
6587 if (OpInfo.isIndirect) {
6588 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6589 OpInfo.CallOperandVal));
6591 // This is the result value of the call.
6592 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6593 // Concatenate this output onto the outputs list.
6594 RetValRegs.append(OpInfo.AssignedRegs);
6597 // Add information to the INLINEASM node to know that this register is
6600 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6601 ? InlineAsm::Kind_RegDefEarlyClobber
6602 : InlineAsm::Kind_RegDef,
6603 false, 0, DAG, AsmNodeOperands);
6606 case InlineAsm::isInput: {
6607 SDValue InOperandVal = OpInfo.CallOperand;
6609 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6610 // If this is required to match an output register we have already set,
6611 // just use its register.
6612 unsigned OperandNo = OpInfo.getMatchedOperand();
6614 // Scan until we find the definition we already emitted of this operand.
6615 // When we find it, create a RegsForValue operand.
6616 unsigned CurOp = InlineAsm::Op_FirstOperand;
6617 for (; OperandNo; --OperandNo) {
6618 // Advance to the next operand.
6620 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6621 assert((InlineAsm::isRegDefKind(OpFlag) ||
6622 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6623 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6624 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6628 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6629 if (InlineAsm::isRegDefKind(OpFlag) ||
6630 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6631 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6632 if (OpInfo.isIndirect) {
6633 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6634 LLVMContext &Ctx = *DAG.getContext();
6635 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6636 " don't know how to handle tied "
6637 "indirect register inputs");
6641 RegsForValue MatchedRegs;
6642 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6643 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6644 MatchedRegs.RegVTs.push_back(RegVT);
6645 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6646 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6648 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6649 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6651 LLVMContext &Ctx = *DAG.getContext();
6652 Ctx.emitError(CS.getInstruction(),
6653 "inline asm error: This value"
6654 " type register class is not natively supported!");
6658 // Use the produced MatchedRegs object to
6659 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6660 Chain, &Flag, CS.getInstruction());
6661 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6662 true, OpInfo.getMatchedOperand(),
6663 DAG, AsmNodeOperands);
6667 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6668 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6669 "Unexpected number of operands");
6670 // Add information to the INLINEASM node to know about this input.
6671 // See InlineAsm.h isUseOperandTiedToDef.
6672 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6673 OpInfo.getMatchedOperand());
6674 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6675 TLI->getPointerTy()));
6676 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6680 // Treat indirect 'X' constraint as memory.
6681 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6683 OpInfo.ConstraintType = TargetLowering::C_Memory;
6685 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6686 std::vector<SDValue> Ops;
6687 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6690 LLVMContext &Ctx = *DAG.getContext();
6691 Ctx.emitError(CS.getInstruction(),
6692 "invalid operand for inline asm constraint '" +
6693 Twine(OpInfo.ConstraintCode) + "'");
6697 // Add information to the INLINEASM node to know about this input.
6698 unsigned ResOpType =
6699 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6700 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6701 TLI->getPointerTy()));
6702 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6706 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6707 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6708 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6709 "Memory operands expect pointer values");
6711 // Add information to the INLINEASM node to know about this input.
6712 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6713 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6714 TLI->getPointerTy()));
6715 AsmNodeOperands.push_back(InOperandVal);
6719 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6720 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6721 "Unknown constraint type!");
6723 // TODO: Support this.
6724 if (OpInfo.isIndirect) {
6725 LLVMContext &Ctx = *DAG.getContext();
6726 Ctx.emitError(CS.getInstruction(),
6727 "Don't know how to handle indirect register inputs yet "
6728 "for constraint '" +
6729 Twine(OpInfo.ConstraintCode) + "'");
6733 // Copy the input into the appropriate registers.
6734 if (OpInfo.AssignedRegs.Regs.empty()) {
6735 LLVMContext &Ctx = *DAG.getContext();
6736 Ctx.emitError(CS.getInstruction(),
6737 "couldn't allocate input reg for constraint '" +
6738 Twine(OpInfo.ConstraintCode) + "'");
6742 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6743 Chain, &Flag, CS.getInstruction());
6745 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6746 DAG, AsmNodeOperands);
6749 case InlineAsm::isClobber: {
6750 // Add the clobbered value to the operand list, so that the register
6751 // allocator is aware that the physreg got clobbered.
6752 if (!OpInfo.AssignedRegs.Regs.empty())
6753 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6761 // Finish up input operands. Set the input chain and add the flag last.
6762 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6763 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6765 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6766 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6767 Flag = Chain.getValue(1);
6769 // If this asm returns a register value, copy the result from that register
6770 // and set it as the value of the call.
6771 if (!RetValRegs.Regs.empty()) {
6772 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6773 Chain, &Flag, CS.getInstruction());
6775 // FIXME: Why don't we do this for inline asms with MRVs?
6776 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6777 EVT ResultType = TLI->getValueType(CS.getType());
6779 // If any of the results of the inline asm is a vector, it may have the
6780 // wrong width/num elts. This can happen for register classes that can
6781 // contain multiple different value types. The preg or vreg allocated may
6782 // not have the same VT as was expected. Convert it to the right type
6783 // with bit_convert.
6784 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6785 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6788 } else if (ResultType != Val.getValueType() &&
6789 ResultType.isInteger() && Val.getValueType().isInteger()) {
6790 // If a result value was tied to an input value, the computed result may
6791 // have a wider width than the expected result. Extract the relevant
6793 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6796 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6799 setValue(CS.getInstruction(), Val);
6800 // Don't need to use this as a chain in this case.
6801 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6805 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6807 // Process indirect outputs, first output all of the flagged copies out of
6809 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6810 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6811 const Value *Ptr = IndirectStoresToEmit[i].second;
6812 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6814 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6817 // Emit the non-flagged stores from the physregs.
6818 SmallVector<SDValue, 8> OutChains;
6819 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6820 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6821 StoresToEmit[i].first,
6822 getValue(StoresToEmit[i].second),
6823 MachinePointerInfo(StoresToEmit[i].second),
6825 OutChains.push_back(Val);
6828 if (!OutChains.empty())
6829 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6834 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6835 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6836 MVT::Other, getRoot(),
6837 getValue(I.getArgOperand(0)),
6838 DAG.getSrcValue(I.getArgOperand(0))));
6841 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6842 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6843 const DataLayout &DL = *TLI->getDataLayout();
6844 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6845 getRoot(), getValue(I.getOperand(0)),
6846 DAG.getSrcValue(I.getOperand(0)),
6847 DL.getABITypeAlignment(I.getType()));
6849 DAG.setRoot(V.getValue(1));
6852 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6853 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6854 MVT::Other, getRoot(),
6855 getValue(I.getArgOperand(0)),
6856 DAG.getSrcValue(I.getArgOperand(0))));
6859 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6860 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6861 MVT::Other, getRoot(),
6862 getValue(I.getArgOperand(0)),
6863 getValue(I.getArgOperand(1)),
6864 DAG.getSrcValue(I.getArgOperand(0)),
6865 DAG.getSrcValue(I.getArgOperand(1))));
6868 /// \brief Lower an argument list according to the target calling convention.
6870 /// \return A tuple of <return-value, token-chain>
6872 /// This is a helper for lowering intrinsics that follow a target calling
6873 /// convention or require stack pointer adjustment. Only a subset of the
6874 /// intrinsic's operands need to participate in the calling convention.
6875 std::pair<SDValue, SDValue>
6876 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6877 unsigned NumArgs, SDValue Callee,
6879 TargetLowering::ArgListTy Args;
6880 Args.reserve(NumArgs);
6882 // Populate the argument list.
6883 // Attributes for args start at offset 1, after the return attribute.
6884 ImmutableCallSite CS(&CI);
6885 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6886 ArgI != ArgE; ++ArgI) {
6887 const Value *V = CI.getOperand(ArgI);
6889 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6891 TargetLowering::ArgListEntry Entry;
6892 Entry.Node = getValue(V);
6893 Entry.Ty = V->getType();
6894 Entry.setAttributes(&CS, AttrI);
6895 Args.push_back(Entry);
6898 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6899 TargetLowering::CallLoweringInfo CLI(DAG);
6900 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6901 .setCallee(CI.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6902 .setDiscardResult(!CI.use_empty());
6904 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6905 return TLI->LowerCallTo(CLI);
6908 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6909 /// or patchpoint target node's operand list.
6911 /// Constants are converted to TargetConstants purely as an optimization to
6912 /// avoid constant materialization and register allocation.
6914 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6915 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6916 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6917 /// address materialization and register allocation, but may also be required
6918 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6919 /// alloca in the entry block, then the runtime may assume that the alloca's
6920 /// StackMap location can be read immediately after compilation and that the
6921 /// location is valid at any point during execution (this is similar to the
6922 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6923 /// only available in a register, then the runtime would need to trap when
6924 /// execution reaches the StackMap in order to read the alloca's location.
6925 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6926 SmallVectorImpl<SDValue> &Ops,
6927 SelectionDAGBuilder &Builder) {
6928 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6929 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6930 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6932 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6934 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6935 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6936 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6938 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6940 Ops.push_back(OpVal);
6944 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6945 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6946 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6947 // [live variables...])
6949 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6951 SDValue Chain, InFlag, Callee, NullPtr;
6952 SmallVector<SDValue, 32> Ops;
6954 SDLoc DL = getCurSDLoc();
6955 Callee = getValue(CI.getCalledValue());
6956 NullPtr = DAG.getIntPtrConstant(0, true);
6958 // The stackmap intrinsic only records the live variables (the arguemnts
6959 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6960 // intrinsic, this won't be lowered to a function call. This means we don't
6961 // have to worry about calling conventions and target specific lowering code.
6962 // Instead we perform the call lowering right here.
6964 // chain, flag = CALLSEQ_START(chain, 0)
6965 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6966 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6968 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6969 InFlag = Chain.getValue(1);
6971 // Add the <id> and <numBytes> constants.
6972 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6973 Ops.push_back(DAG.getTargetConstant(
6974 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6975 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6976 Ops.push_back(DAG.getTargetConstant(
6977 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6979 // Push live variables for the stack map.
6980 addStackMapLiveVars(CI, 2, Ops, *this);
6982 // We are not pushing any register mask info here on the operands list,
6983 // because the stackmap doesn't clobber anything.
6985 // Push the chain and the glue flag.
6986 Ops.push_back(Chain);
6987 Ops.push_back(InFlag);
6989 // Create the STACKMAP node.
6990 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6991 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6992 Chain = SDValue(SM, 0);
6993 InFlag = Chain.getValue(1);
6995 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6997 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6999 // Set the root to the target-lowered call chain.
7002 // Inform the Frame Information that we have a stackmap in this function.
7003 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7006 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7007 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
7008 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7013 // [live variables...])
7015 CallingConv::ID CC = CI.getCallingConv();
7016 bool isAnyRegCC = CC == CallingConv::AnyReg;
7017 bool hasDef = !CI.getType()->isVoidTy();
7018 SDValue Callee = getValue(CI.getOperand(2)); // <target>
7020 // Get the real number of arguments participating in the call <numArgs>
7021 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
7022 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7024 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7025 // Intrinsics include all meta-operands up to but not including CC.
7026 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7027 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
7028 "Not enough arguments provided to the patchpoint intrinsic");
7030 // For AnyRegCC the arguments are lowered later on manually.
7031 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
7032 std::pair<SDValue, SDValue> Result =
7033 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
7035 // Set the root to the target-lowered call chain.
7036 SDValue Chain = Result.second;
7039 SDNode *CallEnd = Chain.getNode();
7040 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7041 CallEnd = CallEnd->getOperand(0).getNode();
7043 /// Get a call instruction from the call sequence chain.
7044 /// Tail calls are not allowed.
7045 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7046 "Expected a callseq node.");
7047 SDNode *Call = CallEnd->getOperand(0).getNode();
7048 bool hasGlue = Call->getGluedNode();
7050 // Replace the target specific call node with the patchable intrinsic.
7051 SmallVector<SDValue, 8> Ops;
7053 // Add the <id> and <numBytes> constants.
7054 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7055 Ops.push_back(DAG.getTargetConstant(
7056 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7057 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7058 Ops.push_back(DAG.getTargetConstant(
7059 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7061 // Assume that the Callee is a constant address.
7062 // FIXME: handle function symbols in the future.
7064 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7065 /*isTarget=*/true));
7067 // Adjust <numArgs> to account for any arguments that have been passed on the
7069 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7070 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7071 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7072 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7074 // Add the calling convention
7075 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7077 // Add the arguments we omitted previously. The register allocator should
7078 // place these in any free register.
7080 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7081 Ops.push_back(getValue(CI.getArgOperand(i)));
7083 // Push the arguments from the call instruction up to the register mask.
7084 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7085 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7088 // Push live variables for the stack map.
7089 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7091 // Push the register mask info.
7093 Ops.push_back(*(Call->op_end()-2));
7095 Ops.push_back(*(Call->op_end()-1));
7097 // Push the chain (this is originally the first operand of the call, but
7098 // becomes now the last or second to last operand).
7099 Ops.push_back(*(Call->op_begin()));
7101 // Push the glue flag (last operand).
7103 Ops.push_back(*(Call->op_end()-1));
7106 if (isAnyRegCC && hasDef) {
7107 // Create the return types based on the intrinsic definition
7108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7109 SmallVector<EVT, 3> ValueVTs;
7110 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7111 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7113 // There is always a chain and a glue type at the end
7114 ValueVTs.push_back(MVT::Other);
7115 ValueVTs.push_back(MVT::Glue);
7116 NodeTys = DAG.getVTList(ValueVTs);
7118 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7120 // Replace the target specific call node with a PATCHPOINT node.
7121 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7122 getCurSDLoc(), NodeTys, Ops);
7124 // Update the NodeMap.
7127 setValue(&CI, SDValue(MN, 0));
7129 setValue(&CI, Result.first);
7132 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7133 // call sequence. Furthermore the location of the chain and glue can change
7134 // when the AnyReg calling convention is used and the intrinsic returns a
7136 if (isAnyRegCC && hasDef) {
7137 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7138 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7139 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7141 DAG.ReplaceAllUsesWith(Call, MN);
7142 DAG.DeleteNode(Call);
7144 // Inform the Frame Information that we have a patchpoint in this function.
7145 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7148 /// Returns an AttributeSet representing the attributes applied to the return
7149 /// value of the given call.
7150 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7151 SmallVector<Attribute::AttrKind, 2> Attrs;
7153 Attrs.push_back(Attribute::SExt);
7155 Attrs.push_back(Attribute::ZExt);
7157 Attrs.push_back(Attribute::InReg);
7159 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7163 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7164 /// implementation, which just calls LowerCall.
7165 /// FIXME: When all targets are
7166 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7167 std::pair<SDValue, SDValue>
7168 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7169 // Handle the incoming return values from the call.
7171 Type *OrigRetTy = CLI.RetTy;
7172 SmallVector<EVT, 4> RetTys;
7173 SmallVector<uint64_t, 4> Offsets;
7174 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7176 SmallVector<ISD::OutputArg, 4> Outs;
7177 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7179 bool CanLowerReturn =
7180 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7181 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7183 SDValue DemoteStackSlot;
7184 int DemoteStackIdx = -100;
7185 if (!CanLowerReturn) {
7186 // FIXME: equivalent assert?
7187 // assert(!CS.hasInAllocaArgument() &&
7188 // "sret demotion is incompatible with inalloca");
7189 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7190 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7191 MachineFunction &MF = CLI.DAG.getMachineFunction();
7192 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7193 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7195 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7197 Entry.Node = DemoteStackSlot;
7198 Entry.Ty = StackSlotPtrType;
7199 Entry.isSExt = false;
7200 Entry.isZExt = false;
7201 Entry.isInReg = false;
7202 Entry.isSRet = true;
7203 Entry.isNest = false;
7204 Entry.isByVal = false;
7205 Entry.isReturned = false;
7206 Entry.Alignment = Align;
7207 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7208 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7210 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7212 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7213 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7214 for (unsigned i = 0; i != NumRegs; ++i) {
7215 ISD::InputArg MyFlags;
7216 MyFlags.VT = RegisterVT;
7218 MyFlags.Used = CLI.IsReturnValueUsed;
7220 MyFlags.Flags.setSExt();
7222 MyFlags.Flags.setZExt();
7224 MyFlags.Flags.setInReg();
7225 CLI.Ins.push_back(MyFlags);
7230 // Handle all of the outgoing arguments.
7232 CLI.OutVals.clear();
7233 ArgListTy &Args = CLI.getArgs();
7234 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7235 SmallVector<EVT, 4> ValueVTs;
7236 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7237 Type *FinalType = Args[i].Ty;
7238 if (Args[i].isByVal)
7239 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7240 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7241 FinalType, CLI.CallConv, CLI.IsVarArg);
7242 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7244 EVT VT = ValueVTs[Value];
7245 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7246 SDValue Op = SDValue(Args[i].Node.getNode(),
7247 Args[i].Node.getResNo() + Value);
7248 ISD::ArgFlagsTy Flags;
7249 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7255 if (Args[i].isInReg)
7259 if (Args[i].isByVal)
7261 if (Args[i].isInAlloca) {
7262 Flags.setInAlloca();
7263 // Set the byval flag for CCAssignFn callbacks that don't know about
7264 // inalloca. This way we can know how many bytes we should've allocated
7265 // and how many bytes a callee cleanup function will pop. If we port
7266 // inalloca to more targets, we'll have to add custom inalloca handling
7267 // in the various CC lowering callbacks.
7270 if (Args[i].isByVal || Args[i].isInAlloca) {
7271 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7272 Type *ElementTy = Ty->getElementType();
7273 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7274 // For ByVal, alignment should come from FE. BE will guess if this
7275 // info is not there but there are cases it cannot get right.
7276 unsigned FrameAlign;
7277 if (Args[i].Alignment)
7278 FrameAlign = Args[i].Alignment;
7280 FrameAlign = getByValTypeAlignment(ElementTy);
7281 Flags.setByValAlign(FrameAlign);
7285 if (NeedsRegBlock) {
7286 Flags.setInConsecutiveRegs();
7287 if (Value == NumValues - 1)
7288 Flags.setInConsecutiveRegsLast();
7290 Flags.setOrigAlign(OriginalAlignment);
7292 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7293 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7294 SmallVector<SDValue, 4> Parts(NumParts);
7295 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7298 ExtendKind = ISD::SIGN_EXTEND;
7299 else if (Args[i].isZExt)
7300 ExtendKind = ISD::ZERO_EXTEND;
7302 // Conservatively only handle 'returned' on non-vectors for now
7303 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7304 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7305 "unexpected use of 'returned'");
7306 // Before passing 'returned' to the target lowering code, ensure that
7307 // either the register MVT and the actual EVT are the same size or that
7308 // the return value and argument are extended in the same way; in these
7309 // cases it's safe to pass the argument register value unchanged as the
7310 // return register value (although it's at the target's option whether
7312 // TODO: allow code generation to take advantage of partially preserved
7313 // registers rather than clobbering the entire register when the
7314 // parameter extension method is not compatible with the return
7316 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7317 (ExtendKind != ISD::ANY_EXTEND &&
7318 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7319 Flags.setReturned();
7322 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7323 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7325 for (unsigned j = 0; j != NumParts; ++j) {
7326 // if it isn't first piece, alignment must be 1
7327 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7328 i < CLI.NumFixedArgs,
7329 i, j*Parts[j].getValueType().getStoreSize());
7330 if (NumParts > 1 && j == 0)
7331 MyFlags.Flags.setSplit();
7333 MyFlags.Flags.setOrigAlign(1);
7335 CLI.Outs.push_back(MyFlags);
7336 CLI.OutVals.push_back(Parts[j]);
7341 SmallVector<SDValue, 4> InVals;
7342 CLI.Chain = LowerCall(CLI, InVals);
7344 // Verify that the target's LowerCall behaved as expected.
7345 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7346 "LowerCall didn't return a valid chain!");
7347 assert((!CLI.IsTailCall || InVals.empty()) &&
7348 "LowerCall emitted a return value for a tail call!");
7349 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7350 "LowerCall didn't emit the correct number of values!");
7352 // For a tail call, the return value is merely live-out and there aren't
7353 // any nodes in the DAG representing it. Return a special value to
7354 // indicate that a tail call has been emitted and no more Instructions
7355 // should be processed in the current block.
7356 if (CLI.IsTailCall) {
7357 CLI.DAG.setRoot(CLI.Chain);
7358 return std::make_pair(SDValue(), SDValue());
7361 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7362 assert(InVals[i].getNode() &&
7363 "LowerCall emitted a null value!");
7364 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7365 "LowerCall emitted a value with the wrong type!");
7368 SmallVector<SDValue, 4> ReturnValues;
7369 if (!CanLowerReturn) {
7370 // The instruction result is the result of loading from the
7371 // hidden sret parameter.
7372 SmallVector<EVT, 1> PVTs;
7373 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7375 ComputeValueVTs(*this, PtrRetTy, PVTs);
7376 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7377 EVT PtrVT = PVTs[0];
7379 unsigned NumValues = RetTys.size();
7380 ReturnValues.resize(NumValues);
7381 SmallVector<SDValue, 4> Chains(NumValues);
7383 for (unsigned i = 0; i < NumValues; ++i) {
7384 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7385 CLI.DAG.getConstant(Offsets[i], PtrVT));
7386 SDValue L = CLI.DAG.getLoad(
7387 RetTys[i], CLI.DL, CLI.Chain, Add,
7388 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7390 ReturnValues[i] = L;
7391 Chains[i] = L.getValue(1);
7394 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7396 // Collect the legal value parts into potentially illegal values
7397 // that correspond to the original function's return values.
7398 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7400 AssertOp = ISD::AssertSext;
7401 else if (CLI.RetZExt)
7402 AssertOp = ISD::AssertZext;
7403 unsigned CurReg = 0;
7404 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7406 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7407 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7409 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7410 NumRegs, RegisterVT, VT, nullptr,
7415 // For a function returning void, there is no return value. We can't create
7416 // such a node, so we just return a null return value in that case. In
7417 // that case, nothing will actually look at the value.
7418 if (ReturnValues.empty())
7419 return std::make_pair(SDValue(), CLI.Chain);
7422 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7423 CLI.DAG.getVTList(RetTys), ReturnValues);
7424 return std::make_pair(Res, CLI.Chain);
7427 void TargetLowering::LowerOperationWrapper(SDNode *N,
7428 SmallVectorImpl<SDValue> &Results,
7429 SelectionDAG &DAG) const {
7430 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7432 Results.push_back(Res);
7435 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7436 llvm_unreachable("LowerOperation not implemented for this target!");
7440 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7441 SDValue Op = getNonRegisterValue(V);
7442 assert((Op.getOpcode() != ISD::CopyFromReg ||
7443 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7444 "Copy from a reg to the same reg!");
7445 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7447 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
7448 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7449 SDValue Chain = DAG.getEntryNode();
7451 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7452 FuncInfo.PreferredExtendType.end())
7454 : FuncInfo.PreferredExtendType[V];
7455 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7456 PendingExports.push_back(Chain);
7459 #include "llvm/CodeGen/SelectionDAGISel.h"
7461 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7462 /// entry block, return true. This includes arguments used by switches, since
7463 /// the switch may expand into multiple basic blocks.
7464 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7465 // With FastISel active, we may be splitting blocks, so force creation
7466 // of virtual registers for all non-dead arguments.
7468 return A->use_empty();
7470 const BasicBlock *Entry = A->getParent()->begin();
7471 for (const User *U : A->users())
7472 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7473 return false; // Use not in entry block.
7478 void SelectionDAGISel::LowerArguments(const Function &F) {
7479 SelectionDAG &DAG = SDB->DAG;
7480 SDLoc dl = SDB->getCurSDLoc();
7481 const TargetLowering *TLI = getTargetLowering();
7482 const DataLayout *DL = TLI->getDataLayout();
7483 SmallVector<ISD::InputArg, 16> Ins;
7485 if (!FuncInfo->CanLowerReturn) {
7486 // Put in an sret pointer parameter before all the other parameters.
7487 SmallVector<EVT, 1> ValueVTs;
7488 ComputeValueVTs(*getTargetLowering(),
7489 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7491 // NOTE: Assuming that a pointer will never break down to more than one VT
7493 ISD::ArgFlagsTy Flags;
7495 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7496 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7497 Ins.push_back(RetArg);
7500 // Set up the incoming argument description vector.
7502 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7503 I != E; ++I, ++Idx) {
7504 SmallVector<EVT, 4> ValueVTs;
7505 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7506 bool isArgValueUsed = !I->use_empty();
7507 unsigned PartBase = 0;
7508 Type *FinalType = I->getType();
7509 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7510 FinalType = cast<PointerType>(FinalType)->getElementType();
7511 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7512 FinalType, F.getCallingConv(), F.isVarArg());
7513 for (unsigned Value = 0, NumValues = ValueVTs.size();
7514 Value != NumValues; ++Value) {
7515 EVT VT = ValueVTs[Value];
7516 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7517 ISD::ArgFlagsTy Flags;
7518 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7520 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7522 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7524 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7526 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7528 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7530 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7531 Flags.setInAlloca();
7532 // Set the byval flag for CCAssignFn callbacks that don't know about
7533 // inalloca. This way we can know how many bytes we should've allocated
7534 // and how many bytes a callee cleanup function will pop. If we port
7535 // inalloca to more targets, we'll have to add custom inalloca handling
7536 // in the various CC lowering callbacks.
7539 if (Flags.isByVal() || Flags.isInAlloca()) {
7540 PointerType *Ty = cast<PointerType>(I->getType());
7541 Type *ElementTy = Ty->getElementType();
7542 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7543 // For ByVal, alignment should be passed from FE. BE will guess if
7544 // this info is not there but there are cases it cannot get right.
7545 unsigned FrameAlign;
7546 if (F.getParamAlignment(Idx))
7547 FrameAlign = F.getParamAlignment(Idx);
7549 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7550 Flags.setByValAlign(FrameAlign);
7552 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7554 if (NeedsRegBlock) {
7555 Flags.setInConsecutiveRegs();
7556 if (Value == NumValues - 1)
7557 Flags.setInConsecutiveRegsLast();
7559 Flags.setOrigAlign(OriginalAlignment);
7561 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7562 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7563 for (unsigned i = 0; i != NumRegs; ++i) {
7564 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7565 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7566 if (NumRegs > 1 && i == 0)
7567 MyFlags.Flags.setSplit();
7568 // if it isn't first piece, alignment must be 1
7570 MyFlags.Flags.setOrigAlign(1);
7571 Ins.push_back(MyFlags);
7573 PartBase += VT.getStoreSize();
7577 // Call the target to set up the argument values.
7578 SmallVector<SDValue, 8> InVals;
7579 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7583 // Verify that the target's LowerFormalArguments behaved as expected.
7584 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7585 "LowerFormalArguments didn't return a valid chain!");
7586 assert(InVals.size() == Ins.size() &&
7587 "LowerFormalArguments didn't emit the correct number of values!");
7589 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7590 assert(InVals[i].getNode() &&
7591 "LowerFormalArguments emitted a null value!");
7592 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7593 "LowerFormalArguments emitted a value with the wrong type!");
7597 // Update the DAG with the new chain value resulting from argument lowering.
7598 DAG.setRoot(NewRoot);
7600 // Set up the argument values.
7603 if (!FuncInfo->CanLowerReturn) {
7604 // Create a virtual register for the sret pointer, and put in a copy
7605 // from the sret argument into it.
7606 SmallVector<EVT, 1> ValueVTs;
7607 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7608 MVT VT = ValueVTs[0].getSimpleVT();
7609 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7610 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7611 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7612 RegVT, VT, nullptr, AssertOp);
7614 MachineFunction& MF = SDB->DAG.getMachineFunction();
7615 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7616 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7617 FuncInfo->DemoteRegister = SRetReg;
7618 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7620 DAG.setRoot(NewRoot);
7622 // i indexes lowered arguments. Bump it past the hidden sret argument.
7623 // Idx indexes LLVM arguments. Don't touch it.
7627 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7629 SmallVector<SDValue, 4> ArgValues;
7630 SmallVector<EVT, 4> ValueVTs;
7631 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7632 unsigned NumValues = ValueVTs.size();
7634 // If this argument is unused then remember its value. It is used to generate
7635 // debugging information.
7636 if (I->use_empty() && NumValues) {
7637 SDB->setUnusedArgValue(I, InVals[i]);
7639 // Also remember any frame index for use in FastISel.
7640 if (FrameIndexSDNode *FI =
7641 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7642 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7645 for (unsigned Val = 0; Val != NumValues; ++Val) {
7646 EVT VT = ValueVTs[Val];
7647 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7648 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7650 if (!I->use_empty()) {
7651 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7652 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7653 AssertOp = ISD::AssertSext;
7654 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7655 AssertOp = ISD::AssertZext;
7657 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7658 NumParts, PartVT, VT,
7659 nullptr, AssertOp));
7665 // We don't need to do anything else for unused arguments.
7666 if (ArgValues.empty())
7669 // Note down frame index.
7670 if (FrameIndexSDNode *FI =
7671 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7672 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7674 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7675 SDB->getCurSDLoc());
7677 SDB->setValue(I, Res);
7678 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7679 if (LoadSDNode *LNode =
7680 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7681 if (FrameIndexSDNode *FI =
7682 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7683 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7686 // If this argument is live outside of the entry block, insert a copy from
7687 // wherever we got it to the vreg that other BB's will reference it as.
7688 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7689 // If we can, though, try to skip creating an unnecessary vreg.
7690 // FIXME: This isn't very clean... it would be nice to make this more
7691 // general. It's also subtly incompatible with the hacks FastISel
7693 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7694 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7695 FuncInfo->ValueMap[I] = Reg;
7699 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7700 FuncInfo->InitializeRegForValue(I);
7701 SDB->CopyToExportRegsIfNeeded(I);
7705 assert(i == InVals.size() && "Argument register count mismatch!");
7707 // Finally, if the target has anything special to do, allow it to do so.
7708 // FIXME: this should insert code into the DAG!
7709 EmitFunctionEntryCode();
7712 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7713 /// ensure constants are generated when needed. Remember the virtual registers
7714 /// that need to be added to the Machine PHI nodes as input. We cannot just
7715 /// directly add them, because expansion might result in multiple MBB's for one
7716 /// BB. As such, the start of the BB might correspond to a different MBB than
7720 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7721 const TerminatorInst *TI = LLVMBB->getTerminator();
7723 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7725 // Check successor nodes' PHI nodes that expect a constant to be available
7727 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7728 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7729 if (!isa<PHINode>(SuccBB->begin())) continue;
7730 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7732 // If this terminator has multiple identical successors (common for
7733 // switches), only handle each succ once.
7734 if (!SuccsHandled.insert(SuccMBB)) continue;
7736 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7738 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7739 // nodes and Machine PHI nodes, but the incoming operands have not been
7741 for (BasicBlock::const_iterator I = SuccBB->begin();
7742 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7743 // Ignore dead phi's.
7744 if (PN->use_empty()) continue;
7747 if (PN->getType()->isEmptyTy())
7751 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7753 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7754 unsigned &RegOut = ConstantsOut[C];
7756 RegOut = FuncInfo.CreateRegs(C->getType());
7757 CopyValueToVirtualRegister(C, RegOut);
7761 DenseMap<const Value *, unsigned>::iterator I =
7762 FuncInfo.ValueMap.find(PHIOp);
7763 if (I != FuncInfo.ValueMap.end())
7766 assert(isa<AllocaInst>(PHIOp) &&
7767 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7768 "Didn't codegen value into a register!??");
7769 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7770 CopyValueToVirtualRegister(PHIOp, Reg);
7774 // Remember that this register needs to added to the machine PHI node as
7775 // the input for this MBB.
7776 SmallVector<EVT, 4> ValueVTs;
7777 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
7778 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7779 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7780 EVT VT = ValueVTs[vti];
7781 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7782 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7783 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7784 Reg += NumRegisters;
7789 ConstantsOut.clear();
7792 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7795 SelectionDAGBuilder::StackProtectorDescriptor::
7796 AddSuccessorMBB(const BasicBlock *BB,
7797 MachineBasicBlock *ParentMBB,
7798 MachineBasicBlock *SuccMBB) {
7799 // If SuccBB has not been created yet, create it.
7801 MachineFunction *MF = ParentMBB->getParent();
7802 MachineFunction::iterator BBI = ParentMBB;
7803 SuccMBB = MF->CreateMachineBasicBlock(BB);
7804 MF->insert(++BBI, SuccMBB);
7806 // Add it as a successor of ParentMBB.
7807 ParentMBB->addSuccessor(SuccMBB);