1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Constants.h"
37 #include "llvm/DataLayout.h"
38 #include "llvm/DebugInfo.h"
39 #include "llvm/DerivedTypes.h"
40 #include "llvm/Function.h"
41 #include "llvm/GlobalVariable.h"
42 #include "llvm/InlineAsm.h"
43 #include "llvm/Instructions.h"
44 #include "llvm/IntrinsicInst.h"
45 #include "llvm/Intrinsics.h"
46 #include "llvm/LLVMContext.h"
47 #include "llvm/Module.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/IntegersSubsetMapping.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static const unsigned MaxParallelChains = 64;
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
91 const SDValue *Parts, unsigned NumParts,
92 EVT PartVT, EVT ValueVT, const Value *V);
94 /// getCopyFromParts - Create a value that contains the specified legal parts
95 /// combined into the value they represent. If the parts combine to a type
96 /// larger then ValueVT then AssertOp can be used to specify whether the extra
97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
98 /// (ISD::AssertSext).
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 const SDValue *Parts,
101 unsigned NumParts, EVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT, V);
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT, V);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 PartVT = Val.getValueType();
184 if (PartVT == ValueVT)
187 if (PartVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getTargetConstant(1, TLI.getPointerTy()));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromPartsVector - Create a value that contains the specified legal
216 /// parts combined into the value they represent. If the parts combine to a
217 /// type larger then ValueVT then AssertOp can be used to specify whether the
218 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
219 /// ValueVT (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 EVT PartVT, EVT ValueVT, const Value *V) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
230 EVT IntermediateVT, RegisterVT;
231 unsigned NumIntermediates;
233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
234 NumIntermediates, RegisterVT);
235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
236 NumParts = NumRegs; // Silence a compiler warning.
237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
238 assert(RegisterVT == Parts[0].getValueType() &&
239 "Part type doesn't match part!");
241 // Assemble the parts into intermediate operands.
242 SmallVector<SDValue, 8> Ops(NumIntermediates);
243 if (NumIntermediates == NumParts) {
244 // If the register was not expanded, truncate or copy the value,
246 for (unsigned i = 0; i != NumParts; ++i)
247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
248 PartVT, IntermediateVT, V);
249 } else if (NumParts > 0) {
250 // If the intermediate type was expanded, build the intermediate
251 // operands from the parts.
252 assert(NumParts % NumIntermediates == 0 &&
253 "Must expand into a divisible number of parts!");
254 unsigned Factor = NumParts / NumIntermediates;
255 for (unsigned i = 0; i != NumIntermediates; ++i)
256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
257 PartVT, IntermediateVT, V);
260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
261 // intermediate operands.
262 Val = DAG.getNode(IntermediateVT.isVector() ?
263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
264 ValueVT, &Ops[0], NumIntermediates);
267 // There is now one part, held in Val. Correct it to match ValueVT.
268 PartVT = Val.getValueType();
270 if (PartVT == ValueVT)
273 if (PartVT.isVector()) {
274 // If the element type of the source/dest vectors are the same, but the
275 // parts vector has more elements than the value vector, then we have a
276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
280 "Cannot narrow, it would be a lossy transformation");
281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
282 DAG.getIntPtrConstant(0));
285 // Vector/Vector bitcast.
286 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
287 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
289 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
290 "Cannot handle this kind of promotion");
291 // Promoted vector extract
292 bool Smaller = ValueVT.bitsLE(PartVT);
293 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
298 // Trivial bitcast if the types are the same size and the destination
299 // vector type is legal.
300 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
301 TLI.isTypeLegal(ValueVT))
302 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
304 // Handle cases such as i8 -> <1 x i1>
305 if (ValueVT.getVectorNumElements() != 1) {
306 LLVMContext &Ctx = *DAG.getContext();
307 Twine ErrMsg("non-trivial scalar-to-vector conversion");
308 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
309 if (const CallInst *CI = dyn_cast<CallInst>(I))
310 if (isa<InlineAsm>(CI->getCalledValue()))
311 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
312 Ctx.emitError(I, ErrMsg);
314 Ctx.emitError(ErrMsg);
316 report_fatal_error("Cannot handle scalar-to-vector conversion!");
319 if (ValueVT.getVectorNumElements() == 1 &&
320 ValueVT.getVectorElementType() != PartVT) {
321 bool Smaller = ValueVT.bitsLE(PartVT);
322 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
323 DL, ValueVT.getScalarType(), Val);
326 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
329 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
330 SDValue Val, SDValue *Parts, unsigned NumParts,
331 EVT PartVT, const Value *V);
333 /// getCopyToParts - Create a series of nodes that contain the specified value
334 /// split into legal parts. If the parts contain more bits than Val, then, for
335 /// integers, ExtendKind can be used to specify how to generate the extra bits.
336 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
337 SDValue Val, SDValue *Parts, unsigned NumParts,
338 EVT PartVT, const Value *V,
339 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
340 EVT ValueVT = Val.getValueType();
342 // Handle the vector case separately.
343 if (ValueVT.isVector())
344 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
347 unsigned PartBits = PartVT.getSizeInBits();
348 unsigned OrigNumParts = NumParts;
349 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
354 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
355 if (PartVT == ValueVT) {
356 assert(NumParts == 1 && "No-op copy with multiple parts!");
361 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
362 // If the parts cover more bits than the value has, promote the value.
363 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
364 assert(NumParts == 1 && "Do not know what to promote to!");
365 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
367 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
368 ValueVT.isInteger() &&
369 "Unknown mismatch!");
370 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
371 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
372 if (PartVT == MVT::x86mmx)
373 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
375 } else if (PartBits == ValueVT.getSizeInBits()) {
376 // Different types of the same size.
377 assert(NumParts == 1 && PartVT != ValueVT);
378 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
380 // If the parts cover less bits than value has, truncate the value.
381 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
382 ValueVT.isInteger() &&
383 "Unknown mismatch!");
384 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
385 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
386 if (PartVT == MVT::x86mmx)
387 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 // The value may have changed - recompute ValueVT.
391 ValueVT = Val.getValueType();
392 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
393 "Failed to tile the value with PartVT!");
396 if (PartVT != ValueVT) {
397 LLVMContext &Ctx = *DAG.getContext();
398 Twine ErrMsg("scalar-to-vector conversion failed");
399 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
400 if (const CallInst *CI = dyn_cast<CallInst>(I))
401 if (isa<InlineAsm>(CI->getCalledValue()))
402 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
403 Ctx.emitError(I, ErrMsg);
405 Ctx.emitError(ErrMsg);
413 // Expand the value into multiple parts.
414 if (NumParts & (NumParts - 1)) {
415 // The number of parts is not a power of 2. Split off and copy the tail.
416 assert(PartVT.isInteger() && ValueVT.isInteger() &&
417 "Do not know what to expand to!");
418 unsigned RoundParts = 1 << Log2_32(NumParts);
419 unsigned RoundBits = RoundParts * PartBits;
420 unsigned OddParts = NumParts - RoundParts;
421 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
422 DAG.getIntPtrConstant(RoundBits));
423 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
425 if (TLI.isBigEndian())
426 // The odd parts were reversed by getCopyToParts - unreverse them.
427 std::reverse(Parts + RoundParts, Parts + NumParts);
429 NumParts = RoundParts;
430 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
431 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
434 // The number of parts is a power of 2. Repeatedly bisect the value using
436 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
437 EVT::getIntegerVT(*DAG.getContext(),
438 ValueVT.getSizeInBits()),
441 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
442 for (unsigned i = 0; i < NumParts; i += StepSize) {
443 unsigned ThisBits = StepSize * PartBits / 2;
444 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
445 SDValue &Part0 = Parts[i];
446 SDValue &Part1 = Parts[i+StepSize/2];
448 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
449 ThisVT, Part0, DAG.getIntPtrConstant(1));
450 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(0));
453 if (ThisBits == PartBits && ThisVT != PartVT) {
454 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
455 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
460 if (TLI.isBigEndian())
461 std::reverse(Parts, Parts + OrigNumParts);
465 /// getCopyToPartsVector - Create a series of nodes that contain the specified
466 /// value split into legal parts.
467 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
468 SDValue Val, SDValue *Parts, unsigned NumParts,
469 EVT PartVT, const Value *V) {
470 EVT ValueVT = Val.getValueType();
471 assert(ValueVT.isVector() && "Not a vector");
472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
475 if (PartVT == ValueVT) {
477 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
478 // Bitconvert vector->vector case.
479 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
480 } else if (PartVT.isVector() &&
481 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
482 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
483 EVT ElementVT = PartVT.getVectorElementType();
484 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
486 SmallVector<SDValue, 16> Ops;
487 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
488 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
489 ElementVT, Val, DAG.getIntPtrConstant(i)));
491 for (unsigned i = ValueVT.getVectorNumElements(),
492 e = PartVT.getVectorNumElements(); i != e; ++i)
493 Ops.push_back(DAG.getUNDEF(ElementVT));
495 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
497 // FIXME: Use CONCAT for 2x -> 4x.
499 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
500 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
501 } else if (PartVT.isVector() &&
502 PartVT.getVectorElementType().bitsGE(
503 ValueVT.getVectorElementType()) &&
504 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
506 // Promoted vector extract
507 bool Smaller = PartVT.bitsLE(ValueVT);
508 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
511 // Vector -> scalar conversion.
512 assert(ValueVT.getVectorNumElements() == 1 &&
513 "Only trivial vector-to-scalar conversions should get here!");
514 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
515 PartVT, Val, DAG.getIntPtrConstant(0));
517 bool Smaller = ValueVT.bitsLE(PartVT);
518 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
526 // Handle a multi-element vector.
527 EVT IntermediateVT, RegisterVT;
528 unsigned NumIntermediates;
529 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
531 NumIntermediates, RegisterVT);
532 unsigned NumElements = ValueVT.getVectorNumElements();
534 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
535 NumParts = NumRegs; // Silence a compiler warning.
536 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
538 // Split the vector into intermediate operands.
539 SmallVector<SDValue, 8> Ops(NumIntermediates);
540 for (unsigned i = 0; i != NumIntermediates; ++i) {
541 if (IntermediateVT.isVector())
542 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
544 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
546 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
547 IntermediateVT, Val, DAG.getIntPtrConstant(i));
550 // Split the intermediate operands into legal parts.
551 if (NumParts == NumIntermediates) {
552 // If the register was not expanded, promote or copy the value,
554 for (unsigned i = 0; i != NumParts; ++i)
555 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
556 } else if (NumParts > 0) {
557 // If the intermediate type was expanded, split each the value into
559 assert(NumParts % NumIntermediates == 0 &&
560 "Must expand into a divisible number of parts!");
561 unsigned Factor = NumParts / NumIntermediates;
562 for (unsigned i = 0; i != NumIntermediates; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
568 /// RegsForValue - This struct represents the registers (physical or virtual)
569 /// that a particular set of values is assigned, and the type information
570 /// about the value. The most common situation is to represent one value at a
571 /// time, but struct or array values are handled element-wise as multiple
572 /// values. The splitting of aggregates is performed recursively, so that we
573 /// never have aggregate-typed registers. The values at this point do not
574 /// necessarily have legal types, so each value may require one or more
575 /// registers of some legal type.
577 struct RegsForValue {
578 /// ValueVTs - The value types of the values, which may not be legal, and
579 /// may need be promoted or synthesized from one or more registers.
581 SmallVector<EVT, 4> ValueVTs;
583 /// RegVTs - The value types of the registers. This is the same size as
584 /// ValueVTs and it records, for each value, what the type of the assigned
585 /// register or registers are. (Individual values are never synthesized
586 /// from more than one type of register.)
588 /// With virtual registers, the contents of RegVTs is redundant with TLI's
589 /// getRegisterType member function, however when with physical registers
590 /// it is necessary to have a separate record of the types.
592 SmallVector<EVT, 4> RegVTs;
594 /// Regs - This list holds the registers assigned to the values.
595 /// Each legal or promoted value requires one register, and each
596 /// expanded value requires multiple registers.
598 SmallVector<unsigned, 4> Regs;
602 RegsForValue(const SmallVector<unsigned, 4> ®s,
603 EVT regvt, EVT valuevt)
604 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
606 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
607 unsigned Reg, Type *Ty) {
608 ComputeValueVTs(tli, Ty, ValueVTs);
610 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
611 EVT ValueVT = ValueVTs[Value];
612 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
613 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
614 for (unsigned i = 0; i != NumRegs; ++i)
615 Regs.push_back(Reg + i);
616 RegVTs.push_back(RegisterVT);
621 /// areValueTypesLegal - Return true if types of all the values are legal.
622 bool areValueTypesLegal(const TargetLowering &TLI) {
623 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 EVT RegisterVT = RegVTs[Value];
625 if (!TLI.isTypeLegal(RegisterVT))
631 /// append - Add the specified values to this one.
632 void append(const RegsForValue &RHS) {
633 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
634 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
635 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
638 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
639 /// this value and returns the result as a ValueVTs value. This uses
640 /// Chain/Flag as the input and updates them for the output Chain/Flag.
641 /// If the Flag pointer is NULL, no flag is used.
642 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
644 SDValue &Chain, SDValue *Flag,
645 const Value *V = 0) const;
647 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
648 /// specified value into the registers specified by this object. This uses
649 /// Chain/Flag as the input and updates them for the output Chain/Flag.
650 /// If the Flag pointer is NULL, no flag is used.
651 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
652 SDValue &Chain, SDValue *Flag, const Value *V) const;
654 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
655 /// operand list. This adds the code marker, matching input operand index
656 /// (if applicable), and includes the number of values added into it.
657 void AddInlineAsmOperands(unsigned Kind,
658 bool HasMatching, unsigned MatchingIdx,
660 std::vector<SDValue> &Ops) const;
664 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
665 /// this value and returns the result as a ValueVT value. This uses
666 /// Chain/Flag as the input and updates them for the output Chain/Flag.
667 /// If the Flag pointer is NULL, no flag is used.
668 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
669 FunctionLoweringInfo &FuncInfo,
671 SDValue &Chain, SDValue *Flag,
672 const Value *V) const {
673 // A Value with type {} or [0 x %t] needs no registers.
674 if (ValueVTs.empty())
677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 // Assemble the legal parts into the final values.
680 SmallVector<SDValue, 4> Values(ValueVTs.size());
681 SmallVector<SDValue, 8> Parts;
682 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
683 // Copy the legal parts from the registers.
684 EVT ValueVT = ValueVTs[Value];
685 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
686 EVT RegisterVT = RegVTs[Value];
688 Parts.resize(NumRegs);
689 for (unsigned i = 0; i != NumRegs; ++i) {
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
694 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
695 *Flag = P.getValue(2);
698 Chain = P.getValue(1);
701 // If the source register was virtual and if we know something about it,
702 // add an assert node.
703 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
704 !RegisterVT.isInteger() || RegisterVT.isVector())
707 const FunctionLoweringInfo::LiveOutInfo *LOI =
708 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
712 unsigned RegSize = RegisterVT.getSizeInBits();
713 unsigned NumSignBits = LOI->NumSignBits;
714 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
716 // FIXME: We capture more information than the dag can represent. For
717 // now, just use the tightest assertzext/assertsext possible.
719 EVT FromVT(MVT::Other);
720 if (NumSignBits == RegSize)
721 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
722 else if (NumZeroBits >= RegSize-1)
723 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
724 else if (NumSignBits > RegSize-8)
725 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
726 else if (NumZeroBits >= RegSize-8)
727 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
728 else if (NumSignBits > RegSize-16)
729 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
730 else if (NumZeroBits >= RegSize-16)
731 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
732 else if (NumSignBits > RegSize-32)
733 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
734 else if (NumZeroBits >= RegSize-32)
735 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
739 // Add an assertion node.
740 assert(FromVT != MVT::Other);
741 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
742 RegisterVT, P, DAG.getValueType(FromVT));
745 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
746 NumRegs, RegisterVT, ValueVT, V);
751 return DAG.getNode(ISD::MERGE_VALUES, dl,
752 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
753 &Values[0], ValueVTs.size());
756 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
757 /// specified value into the registers specified by this object. This uses
758 /// Chain/Flag as the input and updates them for the output Chain/Flag.
759 /// If the Flag pointer is NULL, no flag is used.
760 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
761 SDValue &Chain, SDValue *Flag,
762 const Value *V) const {
763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
765 // Get the list of the values's legal parts.
766 unsigned NumRegs = Regs.size();
767 SmallVector<SDValue, 8> Parts(NumRegs);
768 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
769 EVT ValueVT = ValueVTs[Value];
770 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
771 EVT RegisterVT = RegVTs[Value];
772 ISD::NodeType ExtendKind =
773 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
775 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
776 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
780 // Copy the parts into the registers.
781 SmallVector<SDValue, 8> Chains(NumRegs);
782 for (unsigned i = 0; i != NumRegs; ++i) {
785 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
787 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
788 *Flag = Part.getValue(1);
791 Chains[i] = Part.getValue(0);
794 if (NumRegs == 1 || Flag)
795 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
796 // flagged to it. That is the CopyToReg nodes and the user are considered
797 // a single scheduling unit. If we create a TokenFactor and return it as
798 // chain, then the TokenFactor is both a predecessor (operand) of the
799 // user as well as a successor (the TF operands are flagged to the user).
800 // c1, f1 = CopyToReg
801 // c2, f2 = CopyToReg
802 // c3 = TokenFactor c1, c2
805 Chain = Chains[NumRegs-1];
807 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
810 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
811 /// operand list. This adds the code marker and includes the number of
812 /// values added into it.
813 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
814 unsigned MatchingIdx,
816 std::vector<SDValue> &Ops) const {
817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
819 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
821 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
822 else if (!Regs.empty() &&
823 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
824 // Put the register class of the virtual registers in the flag word. That
825 // way, later passes can recompute register class constraints for inline
826 // assembly as well as normal instructions.
827 // Don't do this for tied operands that can use the regclass information
829 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
830 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
831 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
834 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
837 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
838 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
839 EVT RegisterVT = RegVTs[Value];
840 for (unsigned i = 0; i != NumRegs; ++i) {
841 assert(Reg < Regs.size() && "Mismatch in # registers expected");
842 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
847 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
848 const TargetLibraryInfo *li) {
852 TD = DAG.getTarget().getDataLayout();
853 Context = DAG.getContext();
854 LPadToCallSiteMap.clear();
857 /// clear - Clear out the current SelectionDAG and the associated
858 /// state and prepare this SelectionDAGBuilder object to be used
859 /// for a new block. This doesn't clear out information about
860 /// additional blocks that are needed to complete switch lowering
861 /// or PHI node updating; that information is cleared out as it is
863 void SelectionDAGBuilder::clear() {
865 UnusedArgNodeMap.clear();
866 PendingLoads.clear();
867 PendingExports.clear();
868 CurDebugLoc = DebugLoc();
872 /// clearDanglingDebugInfo - Clear the dangling debug information
873 /// map. This function is separated from the clear so that debug
874 /// information that is dangling in a basic block can be properly
875 /// resolved in a different basic block. This allows the
876 /// SelectionDAG to resolve dangling debug information attached
878 void SelectionDAGBuilder::clearDanglingDebugInfo() {
879 DanglingDebugInfoMap.clear();
882 /// getRoot - Return the current virtual root of the Selection DAG,
883 /// flushing any PendingLoad items. This must be done before emitting
884 /// a store or any other node that may need to be ordered after any
885 /// prior load instructions.
887 SDValue SelectionDAGBuilder::getRoot() {
888 if (PendingLoads.empty())
889 return DAG.getRoot();
891 if (PendingLoads.size() == 1) {
892 SDValue Root = PendingLoads[0];
894 PendingLoads.clear();
898 // Otherwise, we have to make a token factor node.
899 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
900 &PendingLoads[0], PendingLoads.size());
901 PendingLoads.clear();
906 /// getControlRoot - Similar to getRoot, but instead of flushing all the
907 /// PendingLoad items, flush all the PendingExports items. It is necessary
908 /// to do this before emitting a terminator instruction.
910 SDValue SelectionDAGBuilder::getControlRoot() {
911 SDValue Root = DAG.getRoot();
913 if (PendingExports.empty())
916 // Turn all of the CopyToReg chains into one factored node.
917 if (Root.getOpcode() != ISD::EntryToken) {
918 unsigned i = 0, e = PendingExports.size();
919 for (; i != e; ++i) {
920 assert(PendingExports[i].getNode()->getNumOperands() > 1);
921 if (PendingExports[i].getNode()->getOperand(0) == Root)
922 break; // Don't add the root if we already indirectly depend on it.
926 PendingExports.push_back(Root);
929 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
931 PendingExports.size());
932 PendingExports.clear();
937 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
938 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
939 DAG.AssignOrdering(Node, SDNodeOrder);
941 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
942 AssignOrderingToNode(Node->getOperand(I).getNode());
945 void SelectionDAGBuilder::visit(const Instruction &I) {
946 // Set up outgoing PHI node register values before emitting the terminator.
947 if (isa<TerminatorInst>(&I))
948 HandlePHINodesInSuccessorBlocks(I.getParent());
950 CurDebugLoc = I.getDebugLoc();
952 visit(I.getOpcode(), I);
954 if (!isa<TerminatorInst>(&I) && !HasTailCall)
955 CopyToExportRegsIfNeeded(&I);
957 CurDebugLoc = DebugLoc();
960 void SelectionDAGBuilder::visitPHI(const PHINode &) {
961 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
964 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
965 // Note: this doesn't use InstVisitor, because it has to work with
966 // ConstantExpr's in addition to instructions.
968 default: llvm_unreachable("Unknown instruction type encountered!");
969 // Build the switch statement using the Instruction.def file.
970 #define HANDLE_INST(NUM, OPCODE, CLASS) \
971 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
972 #include "llvm/Instruction.def"
975 // Assign the ordering to the freshly created DAG nodes.
976 if (NodeMap.count(&I)) {
978 AssignOrderingToNode(getValue(&I).getNode());
982 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
983 // generate the debug data structures now that we've seen its definition.
984 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
986 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
988 const DbgValueInst *DI = DDI.getDI();
989 DebugLoc dl = DDI.getdl();
990 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
991 MDNode *Variable = DI->getVariable();
992 uint64_t Offset = DI->getOffset();
995 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
996 SDV = DAG.getDbgValue(Variable, Val.getNode(),
997 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
998 DAG.AddDbgValue(SDV, Val.getNode(), false);
1001 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
1002 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1006 /// getValue - Return an SDValue for the given Value.
1007 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1008 // If we already have an SDValue for this value, use it. It's important
1009 // to do this first, so that we don't create a CopyFromReg if we already
1010 // have a regular SDValue.
1011 SDValue &N = NodeMap[V];
1012 if (N.getNode()) return N;
1014 // If there's a virtual register allocated and initialized for this
1016 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1017 if (It != FuncInfo.ValueMap.end()) {
1018 unsigned InReg = It->second;
1019 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
1020 SDValue Chain = DAG.getEntryNode();
1021 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1022 resolveDanglingDebugInfo(V, N);
1026 // Otherwise create a new SDValue and remember it.
1027 SDValue Val = getValueImpl(V);
1029 resolveDanglingDebugInfo(V, Val);
1033 /// getNonRegisterValue - Return an SDValue for the given Value, but
1034 /// don't look in FuncInfo.ValueMap for a virtual register.
1035 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1036 // If we already have an SDValue for this value, use it.
1037 SDValue &N = NodeMap[V];
1038 if (N.getNode()) return N;
1040 // Otherwise create a new SDValue and remember it.
1041 SDValue Val = getValueImpl(V);
1043 resolveDanglingDebugInfo(V, Val);
1047 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1048 /// Create an SDValue for the given value.
1049 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1050 if (const Constant *C = dyn_cast<Constant>(V)) {
1051 EVT VT = TLI.getValueType(V->getType(), true);
1053 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1054 return DAG.getConstant(*CI, VT);
1056 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1057 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1059 if (isa<ConstantPointerNull>(C))
1060 return DAG.getConstant(0, TLI.getPointerTy());
1062 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1063 return DAG.getConstantFP(*CFP, VT);
1065 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1066 return DAG.getUNDEF(VT);
1068 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1069 visit(CE->getOpcode(), *CE);
1070 SDValue N1 = NodeMap[V];
1071 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1075 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1076 SmallVector<SDValue, 4> Constants;
1077 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1079 SDNode *Val = getValue(*OI).getNode();
1080 // If the operand is an empty aggregate, there are no values.
1082 // Add each leaf value from the operand to the Constants list
1083 // to form a flattened list of all the values.
1084 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1085 Constants.push_back(SDValue(Val, i));
1088 return DAG.getMergeValues(&Constants[0], Constants.size(),
1092 if (const ConstantDataSequential *CDS =
1093 dyn_cast<ConstantDataSequential>(C)) {
1094 SmallVector<SDValue, 4> Ops;
1095 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1096 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1097 // Add each leaf value from the operand to the Constants list
1098 // to form a flattened list of all the values.
1099 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1100 Ops.push_back(SDValue(Val, i));
1103 if (isa<ArrayType>(CDS->getType()))
1104 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1105 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1106 VT, &Ops[0], Ops.size());
1109 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1110 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1111 "Unknown struct or array constant!");
1113 SmallVector<EVT, 4> ValueVTs;
1114 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1115 unsigned NumElts = ValueVTs.size();
1117 return SDValue(); // empty struct
1118 SmallVector<SDValue, 4> Constants(NumElts);
1119 for (unsigned i = 0; i != NumElts; ++i) {
1120 EVT EltVT = ValueVTs[i];
1121 if (isa<UndefValue>(C))
1122 Constants[i] = DAG.getUNDEF(EltVT);
1123 else if (EltVT.isFloatingPoint())
1124 Constants[i] = DAG.getConstantFP(0, EltVT);
1126 Constants[i] = DAG.getConstant(0, EltVT);
1129 return DAG.getMergeValues(&Constants[0], NumElts,
1133 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1134 return DAG.getBlockAddress(BA, VT);
1136 VectorType *VecTy = cast<VectorType>(V->getType());
1137 unsigned NumElements = VecTy->getNumElements();
1139 // Now that we know the number and type of the elements, get that number of
1140 // elements into the Ops array based on what kind of constant it is.
1141 SmallVector<SDValue, 16> Ops;
1142 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1143 for (unsigned i = 0; i != NumElements; ++i)
1144 Ops.push_back(getValue(CV->getOperand(i)));
1146 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1147 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1150 if (EltVT.isFloatingPoint())
1151 Op = DAG.getConstantFP(0, EltVT);
1153 Op = DAG.getConstant(0, EltVT);
1154 Ops.assign(NumElements, Op);
1157 // Create a BUILD_VECTOR node.
1158 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1159 VT, &Ops[0], Ops.size());
1162 // If this is a static alloca, generate it as the frameindex instead of
1164 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1165 DenseMap<const AllocaInst*, int>::iterator SI =
1166 FuncInfo.StaticAllocaMap.find(AI);
1167 if (SI != FuncInfo.StaticAllocaMap.end())
1168 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1171 // If this is an instruction which fast-isel has deferred, select it now.
1172 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1173 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1174 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1175 SDValue Chain = DAG.getEntryNode();
1176 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1179 llvm_unreachable("Can't get register for value!");
1182 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1183 SDValue Chain = getControlRoot();
1184 SmallVector<ISD::OutputArg, 8> Outs;
1185 SmallVector<SDValue, 8> OutVals;
1187 if (!FuncInfo.CanLowerReturn) {
1188 unsigned DemoteReg = FuncInfo.DemoteRegister;
1189 const Function *F = I.getParent()->getParent();
1191 // Emit a store of the return value through the virtual register.
1192 // Leave Outs empty so that LowerReturn won't try to load return
1193 // registers the usual way.
1194 SmallVector<EVT, 1> PtrValueVTs;
1195 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1198 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1199 SDValue RetOp = getValue(I.getOperand(0));
1201 SmallVector<EVT, 4> ValueVTs;
1202 SmallVector<uint64_t, 4> Offsets;
1203 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1204 unsigned NumValues = ValueVTs.size();
1206 SmallVector<SDValue, 4> Chains(NumValues);
1207 for (unsigned i = 0; i != NumValues; ++i) {
1208 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1209 RetPtr.getValueType(), RetPtr,
1210 DAG.getIntPtrConstant(Offsets[i]));
1212 DAG.getStore(Chain, getCurDebugLoc(),
1213 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1214 // FIXME: better loc info would be nice.
1215 Add, MachinePointerInfo(), false, false, 0);
1218 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1219 MVT::Other, &Chains[0], NumValues);
1220 } else if (I.getNumOperands() != 0) {
1221 SmallVector<EVT, 4> ValueVTs;
1222 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1223 unsigned NumValues = ValueVTs.size();
1225 SDValue RetOp = getValue(I.getOperand(0));
1226 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1227 EVT VT = ValueVTs[j];
1229 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1231 const Function *F = I.getParent()->getParent();
1232 if (F->getRetAttributes().hasAttribute(Attributes::SExt))
1233 ExtendKind = ISD::SIGN_EXTEND;
1234 else if (F->getRetAttributes().hasAttribute(Attributes::ZExt))
1235 ExtendKind = ISD::ZERO_EXTEND;
1237 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1238 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1240 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1241 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1242 SmallVector<SDValue, 4> Parts(NumParts);
1243 getCopyToParts(DAG, getCurDebugLoc(),
1244 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1245 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1247 // 'inreg' on function refers to return value
1248 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1249 if (F->getRetAttributes().hasAttribute(Attributes::InReg))
1252 // Propagate extension type if any
1253 if (ExtendKind == ISD::SIGN_EXTEND)
1255 else if (ExtendKind == ISD::ZERO_EXTEND)
1258 for (unsigned i = 0; i < NumParts; ++i) {
1259 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1260 /*isfixed=*/true, 0, 0));
1261 OutVals.push_back(Parts[i]);
1267 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1268 CallingConv::ID CallConv =
1269 DAG.getMachineFunction().getFunction()->getCallingConv();
1270 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1271 Outs, OutVals, getCurDebugLoc(), DAG);
1273 // Verify that the target's LowerReturn behaved as expected.
1274 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1275 "LowerReturn didn't return a valid chain!");
1277 // Update the DAG with the new chain value resulting from return lowering.
1281 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1282 /// created for it, emit nodes to copy the value into the virtual
1284 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1286 if (V->getType()->isEmptyTy())
1289 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1290 if (VMI != FuncInfo.ValueMap.end()) {
1291 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1292 CopyValueToVirtualRegister(V, VMI->second);
1296 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1297 /// the current basic block, add it to ValueMap now so that we'll get a
1299 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1300 // No need to export constants.
1301 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1303 // Already exported?
1304 if (FuncInfo.isExportedInst(V)) return;
1306 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1307 CopyValueToVirtualRegister(V, Reg);
1310 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1311 const BasicBlock *FromBB) {
1312 // The operands of the setcc have to be in this block. We don't know
1313 // how to export them from some other block.
1314 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1315 // Can export from current BB.
1316 if (VI->getParent() == FromBB)
1319 // Is already exported, noop.
1320 return FuncInfo.isExportedInst(V);
1323 // If this is an argument, we can export it if the BB is the entry block or
1324 // if it is already exported.
1325 if (isa<Argument>(V)) {
1326 if (FromBB == &FromBB->getParent()->getEntryBlock())
1329 // Otherwise, can only export this if it is already exported.
1330 return FuncInfo.isExportedInst(V);
1333 // Otherwise, constants can always be exported.
1337 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1338 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1339 const MachineBasicBlock *Dst) const {
1340 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1343 const BasicBlock *SrcBB = Src->getBasicBlock();
1344 const BasicBlock *DstBB = Dst->getBasicBlock();
1345 return BPI->getEdgeWeight(SrcBB, DstBB);
1348 void SelectionDAGBuilder::
1349 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1350 uint32_t Weight /* = 0 */) {
1352 Weight = getEdgeWeight(Src, Dst);
1353 Src->addSuccessor(Dst, Weight);
1357 static bool InBlock(const Value *V, const BasicBlock *BB) {
1358 if (const Instruction *I = dyn_cast<Instruction>(V))
1359 return I->getParent() == BB;
1363 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1364 /// This function emits a branch and is used at the leaves of an OR or an
1365 /// AND operator tree.
1368 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1369 MachineBasicBlock *TBB,
1370 MachineBasicBlock *FBB,
1371 MachineBasicBlock *CurBB,
1372 MachineBasicBlock *SwitchBB) {
1373 const BasicBlock *BB = CurBB->getBasicBlock();
1375 // If the leaf of the tree is a comparison, merge the condition into
1377 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1378 // The operands of the cmp have to be in this block. We don't know
1379 // how to export them from some other block. If this is the first block
1380 // of the sequence, no exporting is needed.
1381 if (CurBB == SwitchBB ||
1382 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1383 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1384 ISD::CondCode Condition;
1385 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1386 Condition = getICmpCondCode(IC->getPredicate());
1387 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1388 Condition = getFCmpCondCode(FC->getPredicate());
1389 if (TM.Options.NoNaNsFPMath)
1390 Condition = getFCmpCodeWithoutNaN(Condition);
1392 Condition = ISD::SETEQ; // silence warning.
1393 llvm_unreachable("Unknown compare instruction");
1396 CaseBlock CB(Condition, BOp->getOperand(0),
1397 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1398 SwitchCases.push_back(CB);
1403 // Create a CaseBlock record representing this branch.
1404 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1405 NULL, TBB, FBB, CurBB);
1406 SwitchCases.push_back(CB);
1409 /// FindMergedConditions - If Cond is an expression like
1410 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1411 MachineBasicBlock *TBB,
1412 MachineBasicBlock *FBB,
1413 MachineBasicBlock *CurBB,
1414 MachineBasicBlock *SwitchBB,
1416 // If this node is not part of the or/and tree, emit it as a branch.
1417 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1418 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1419 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1420 BOp->getParent() != CurBB->getBasicBlock() ||
1421 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1422 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1423 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1427 // Create TmpBB after CurBB.
1428 MachineFunction::iterator BBI = CurBB;
1429 MachineFunction &MF = DAG.getMachineFunction();
1430 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1431 CurBB->getParent()->insert(++BBI, TmpBB);
1433 if (Opc == Instruction::Or) {
1434 // Codegen X | Y as:
1442 // Emit the LHS condition.
1443 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1445 // Emit the RHS condition into TmpBB.
1446 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1448 assert(Opc == Instruction::And && "Unknown merge op!");
1449 // Codegen X & Y as:
1456 // This requires creation of TmpBB after CurBB.
1458 // Emit the LHS condition.
1459 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1461 // Emit the RHS condition into TmpBB.
1462 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1466 /// If the set of cases should be emitted as a series of branches, return true.
1467 /// If we should emit this as a bunch of and/or'd together conditions, return
1470 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1471 if (Cases.size() != 2) return true;
1473 // If this is two comparisons of the same values or'd or and'd together, they
1474 // will get folded into a single comparison, so don't emit two blocks.
1475 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1476 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1477 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1478 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1482 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1483 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1484 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1485 Cases[0].CC == Cases[1].CC &&
1486 isa<Constant>(Cases[0].CmpRHS) &&
1487 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1488 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1490 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1497 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1498 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1500 // Update machine-CFG edges.
1501 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1503 // Figure out which block is immediately after the current one.
1504 MachineBasicBlock *NextBlock = 0;
1505 MachineFunction::iterator BBI = BrMBB;
1506 if (++BBI != FuncInfo.MF->end())
1509 if (I.isUnconditional()) {
1510 // Update machine-CFG edges.
1511 BrMBB->addSuccessor(Succ0MBB);
1513 // If this is not a fall-through branch, emit the branch.
1514 if (Succ0MBB != NextBlock)
1515 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1516 MVT::Other, getControlRoot(),
1517 DAG.getBasicBlock(Succ0MBB)));
1522 // If this condition is one of the special cases we handle, do special stuff
1524 const Value *CondVal = I.getCondition();
1525 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1527 // If this is a series of conditions that are or'd or and'd together, emit
1528 // this as a sequence of branches instead of setcc's with and/or operations.
1529 // As long as jumps are not expensive, this should improve performance.
1530 // For example, instead of something like:
1543 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1544 if (!TLI.isJumpExpensive() &&
1546 (BOp->getOpcode() == Instruction::And ||
1547 BOp->getOpcode() == Instruction::Or)) {
1548 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1550 // If the compares in later blocks need to use values not currently
1551 // exported from this block, export them now. This block should always
1552 // be the first entry.
1553 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1555 // Allow some cases to be rejected.
1556 if (ShouldEmitAsBranches(SwitchCases)) {
1557 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1558 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1559 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1562 // Emit the branch for this block.
1563 visitSwitchCase(SwitchCases[0], BrMBB);
1564 SwitchCases.erase(SwitchCases.begin());
1568 // Okay, we decided not to do this, remove any inserted MBB's and clear
1570 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1571 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1573 SwitchCases.clear();
1577 // Create a CaseBlock record representing this branch.
1578 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1579 NULL, Succ0MBB, Succ1MBB, BrMBB);
1581 // Use visitSwitchCase to actually insert the fast branch sequence for this
1583 visitSwitchCase(CB, BrMBB);
1586 /// visitSwitchCase - Emits the necessary code to represent a single node in
1587 /// the binary search tree resulting from lowering a switch instruction.
1588 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1589 MachineBasicBlock *SwitchBB) {
1591 SDValue CondLHS = getValue(CB.CmpLHS);
1592 DebugLoc dl = getCurDebugLoc();
1594 // Build the setcc now.
1595 if (CB.CmpMHS == NULL) {
1596 // Fold "(X == true)" to X and "(X == false)" to !X to
1597 // handle common cases produced by branch lowering.
1598 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1599 CB.CC == ISD::SETEQ)
1601 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1602 CB.CC == ISD::SETEQ) {
1603 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1604 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1606 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1608 assert(CB.CC == ISD::SETCC_INVALID &&
1609 "Condition is undefined for to-the-range belonging check.");
1611 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1612 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1614 SDValue CmpOp = getValue(CB.CmpMHS);
1615 EVT VT = CmpOp.getValueType();
1617 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1618 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1621 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1622 VT, CmpOp, DAG.getConstant(Low, VT));
1623 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1624 DAG.getConstant(High-Low, VT), ISD::SETULE);
1628 // Update successor info
1629 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1630 // TrueBB and FalseBB are always different unless the incoming IR is
1631 // degenerate. This only happens when running llc on weird IR.
1632 if (CB.TrueBB != CB.FalseBB)
1633 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1635 // Set NextBlock to be the MBB immediately after the current one, if any.
1636 // This is used to avoid emitting unnecessary branches to the next block.
1637 MachineBasicBlock *NextBlock = 0;
1638 MachineFunction::iterator BBI = SwitchBB;
1639 if (++BBI != FuncInfo.MF->end())
1642 // If the lhs block is the next block, invert the condition so that we can
1643 // fall through to the lhs instead of the rhs block.
1644 if (CB.TrueBB == NextBlock) {
1645 std::swap(CB.TrueBB, CB.FalseBB);
1646 SDValue True = DAG.getConstant(1, Cond.getValueType());
1647 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1650 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1651 MVT::Other, getControlRoot(), Cond,
1652 DAG.getBasicBlock(CB.TrueBB));
1654 // Insert the false branch. Do this even if it's a fall through branch,
1655 // this makes it easier to do DAG optimizations which require inverting
1656 // the branch condition.
1657 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1658 DAG.getBasicBlock(CB.FalseBB));
1660 DAG.setRoot(BrCond);
1663 /// visitJumpTable - Emit JumpTable node in the current MBB
1664 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1665 // Emit the code for the jump table
1666 assert(JT.Reg != -1U && "Should lower JT Header first!");
1667 EVT PTy = TLI.getPointerTy();
1668 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1670 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1671 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1672 MVT::Other, Index.getValue(1),
1674 DAG.setRoot(BrJumpTable);
1677 /// visitJumpTableHeader - This function emits necessary code to produce index
1678 /// in the JumpTable from switch case.
1679 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1680 JumpTableHeader &JTH,
1681 MachineBasicBlock *SwitchBB) {
1682 // Subtract the lowest switch case value from the value being switched on and
1683 // conditional branch to default mbb if the result is greater than the
1684 // difference between smallest and largest cases.
1685 SDValue SwitchOp = getValue(JTH.SValue);
1686 EVT VT = SwitchOp.getValueType();
1687 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1688 DAG.getConstant(JTH.First, VT));
1690 // The SDNode we just created, which holds the value being switched on minus
1691 // the smallest case value, needs to be copied to a virtual register so it
1692 // can be used as an index into the jump table in a subsequent basic block.
1693 // This value may be smaller or larger than the target's pointer type, and
1694 // therefore require extension or truncating.
1695 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1697 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1698 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1699 JumpTableReg, SwitchOp);
1700 JT.Reg = JumpTableReg;
1702 // Emit the range check for the jump table, and branch to the default block
1703 // for the switch statement if the value being switched on exceeds the largest
1704 // case in the switch.
1705 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1706 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1707 DAG.getConstant(JTH.Last-JTH.First,VT),
1710 // Set NextBlock to be the MBB immediately after the current one, if any.
1711 // This is used to avoid emitting unnecessary branches to the next block.
1712 MachineBasicBlock *NextBlock = 0;
1713 MachineFunction::iterator BBI = SwitchBB;
1715 if (++BBI != FuncInfo.MF->end())
1718 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1719 MVT::Other, CopyTo, CMP,
1720 DAG.getBasicBlock(JT.Default));
1722 if (JT.MBB != NextBlock)
1723 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1724 DAG.getBasicBlock(JT.MBB));
1726 DAG.setRoot(BrCond);
1729 /// visitBitTestHeader - This function emits necessary code to produce value
1730 /// suitable for "bit tests"
1731 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1732 MachineBasicBlock *SwitchBB) {
1733 // Subtract the minimum value
1734 SDValue SwitchOp = getValue(B.SValue);
1735 MVT VT = SwitchOp.getSimpleValueType();
1736 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1737 DAG.getConstant(B.First, VT));
1740 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1741 TLI.getSetCCResultType(Sub.getValueType()),
1742 Sub, DAG.getConstant(B.Range, VT),
1745 // Determine the type of the test operands.
1746 bool UsePtrType = false;
1747 if (!TLI.isTypeLegal(VT))
1750 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1751 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1752 // Switch table case range are encoded into series of masks.
1753 // Just use pointer type, it's guaranteed to fit.
1759 VT = TLI.getPointerTy();
1760 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1764 B.Reg = FuncInfo.CreateReg(VT);
1765 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1768 // Set NextBlock to be the MBB immediately after the current one, if any.
1769 // This is used to avoid emitting unnecessary branches to the next block.
1770 MachineBasicBlock *NextBlock = 0;
1771 MachineFunction::iterator BBI = SwitchBB;
1772 if (++BBI != FuncInfo.MF->end())
1775 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1777 addSuccessorWithWeight(SwitchBB, B.Default);
1778 addSuccessorWithWeight(SwitchBB, MBB);
1780 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1781 MVT::Other, CopyTo, RangeCmp,
1782 DAG.getBasicBlock(B.Default));
1784 if (MBB != NextBlock)
1785 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1786 DAG.getBasicBlock(MBB));
1788 DAG.setRoot(BrRange);
1791 /// visitBitTestCase - this function produces one "bit test"
1792 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1793 MachineBasicBlock* NextMBB,
1794 uint32_t BranchWeightToNext,
1797 MachineBasicBlock *SwitchBB) {
1799 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1802 unsigned PopCount = CountPopulation_64(B.Mask);
1803 if (PopCount == 1) {
1804 // Testing for a single bit; just compare the shift count with what it
1805 // would need to be to shift a 1 bit in that position.
1806 Cmp = DAG.getSetCC(getCurDebugLoc(),
1807 TLI.getSetCCResultType(VT),
1809 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1811 } else if (PopCount == BB.Range) {
1812 // There is only one zero bit in the range, test for it directly.
1813 Cmp = DAG.getSetCC(getCurDebugLoc(),
1814 TLI.getSetCCResultType(VT),
1816 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1819 // Make desired shift
1820 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1821 DAG.getConstant(1, VT), ShiftOp);
1823 // Emit bit tests and jumps
1824 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1825 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1826 Cmp = DAG.getSetCC(getCurDebugLoc(),
1827 TLI.getSetCCResultType(VT),
1828 AndOp, DAG.getConstant(0, VT),
1832 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1833 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1834 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1835 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1837 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1838 MVT::Other, getControlRoot(),
1839 Cmp, DAG.getBasicBlock(B.TargetBB));
1841 // Set NextBlock to be the MBB immediately after the current one, if any.
1842 // This is used to avoid emitting unnecessary branches to the next block.
1843 MachineBasicBlock *NextBlock = 0;
1844 MachineFunction::iterator BBI = SwitchBB;
1845 if (++BBI != FuncInfo.MF->end())
1848 if (NextMBB != NextBlock)
1849 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1850 DAG.getBasicBlock(NextMBB));
1855 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1856 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1858 // Retrieve successors.
1859 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1860 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1862 const Value *Callee(I.getCalledValue());
1863 const Function *Fn = dyn_cast<Function>(Callee);
1864 if (isa<InlineAsm>(Callee))
1866 else if (Fn && Fn->isIntrinsic()) {
1867 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1868 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1870 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1872 // If the value of the invoke is used outside of its defining block, make it
1873 // available as a virtual register.
1874 CopyToExportRegsIfNeeded(&I);
1876 // Update successor info
1877 addSuccessorWithWeight(InvokeMBB, Return);
1878 addSuccessorWithWeight(InvokeMBB, LandingPad);
1880 // Drop into normal successor.
1881 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1882 MVT::Other, getControlRoot(),
1883 DAG.getBasicBlock(Return)));
1886 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1887 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1890 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1891 assert(FuncInfo.MBB->isLandingPad() &&
1892 "Call to landingpad not in landing pad!");
1894 MachineBasicBlock *MBB = FuncInfo.MBB;
1895 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1896 AddLandingPadInfo(LP, MMI, MBB);
1898 // If there aren't registers to copy the values into (e.g., during SjLj
1899 // exceptions), then don't bother to create these DAG nodes.
1900 if (TLI.getExceptionPointerRegister() == 0 &&
1901 TLI.getExceptionSelectorRegister() == 0)
1904 SmallVector<EVT, 2> ValueVTs;
1905 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1907 // Insert the EXCEPTIONADDR instruction.
1908 assert(FuncInfo.MBB->isLandingPad() &&
1909 "Call to eh.exception not in landing pad!");
1910 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1912 Ops[0] = DAG.getRoot();
1913 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1914 SDValue Chain = Op1.getValue(1);
1916 // Insert the EHSELECTION instruction.
1917 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1920 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1921 Chain = Op2.getValue(1);
1922 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1926 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1927 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1930 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1931 setValue(&LP, RetPair.first);
1932 DAG.setRoot(RetPair.second);
1935 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1936 /// small case ranges).
1937 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1938 CaseRecVector& WorkList,
1940 MachineBasicBlock *Default,
1941 MachineBasicBlock *SwitchBB) {
1942 // Size is the number of Cases represented by this range.
1943 size_t Size = CR.Range.second - CR.Range.first;
1947 // Get the MachineFunction which holds the current MBB. This is used when
1948 // inserting any additional MBBs necessary to represent the switch.
1949 MachineFunction *CurMF = FuncInfo.MF;
1951 // Figure out which block is immediately after the current one.
1952 MachineBasicBlock *NextBlock = 0;
1953 MachineFunction::iterator BBI = CR.CaseBB;
1955 if (++BBI != FuncInfo.MF->end())
1958 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1959 // If any two of the cases has the same destination, and if one value
1960 // is the same as the other, but has one bit unset that the other has set,
1961 // use bit manipulation to do two compares at once. For example:
1962 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1963 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1964 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1965 if (Size == 2 && CR.CaseBB == SwitchBB) {
1966 Case &Small = *CR.Range.first;
1967 Case &Big = *(CR.Range.second-1);
1969 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1970 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1971 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1973 // Check that there is only one bit different.
1974 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1975 (SmallValue | BigValue) == BigValue) {
1976 // Isolate the common bit.
1977 APInt CommonBit = BigValue & ~SmallValue;
1978 assert((SmallValue | CommonBit) == BigValue &&
1979 CommonBit.countPopulation() == 1 && "Not a common bit?");
1981 SDValue CondLHS = getValue(SV);
1982 EVT VT = CondLHS.getValueType();
1983 DebugLoc DL = getCurDebugLoc();
1985 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1986 DAG.getConstant(CommonBit, VT));
1987 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1988 Or, DAG.getConstant(BigValue, VT),
1991 // Update successor info.
1992 // Both Small and Big will jump to Small.BB, so we sum up the weights.
1993 addSuccessorWithWeight(SwitchBB, Small.BB,
1994 Small.ExtraWeight + Big.ExtraWeight);
1995 addSuccessorWithWeight(SwitchBB, Default,
1996 // The default destination is the first successor in IR.
1997 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
1999 // Insert the true branch.
2000 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2001 getControlRoot(), Cond,
2002 DAG.getBasicBlock(Small.BB));
2004 // Insert the false branch.
2005 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2006 DAG.getBasicBlock(Default));
2008 DAG.setRoot(BrCond);
2014 // Order cases by weight so the most likely case will be checked first.
2015 uint32_t UnhandledWeights = 0;
2017 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2018 uint32_t IWeight = I->ExtraWeight;
2019 UnhandledWeights += IWeight;
2020 for (CaseItr J = CR.Range.first; J < I; ++J) {
2021 uint32_t JWeight = J->ExtraWeight;
2022 if (IWeight > JWeight)
2027 // Rearrange the case blocks so that the last one falls through if possible.
2028 Case &BackCase = *(CR.Range.second-1);
2030 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2031 // The last case block won't fall through into 'NextBlock' if we emit the
2032 // branches in this order. See if rearranging a case value would help.
2033 // We start at the bottom as it's the case with the least weight.
2034 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2035 if (I->BB == NextBlock) {
2036 std::swap(*I, BackCase);
2042 // Create a CaseBlock record representing a conditional branch to
2043 // the Case's target mbb if the value being switched on SV is equal
2045 MachineBasicBlock *CurBlock = CR.CaseBB;
2046 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2047 MachineBasicBlock *FallThrough;
2049 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2050 CurMF->insert(BBI, FallThrough);
2052 // Put SV in a virtual register to make it available from the new blocks.
2053 ExportFromCurrentBlock(SV);
2055 // If the last case doesn't match, go to the default block.
2056 FallThrough = Default;
2059 const Value *RHS, *LHS, *MHS;
2061 if (I->High == I->Low) {
2062 // This is just small small case range :) containing exactly 1 case
2064 LHS = SV; RHS = I->High; MHS = NULL;
2066 CC = ISD::SETCC_INVALID;
2067 LHS = I->Low; MHS = SV; RHS = I->High;
2070 // The false weight should be sum of all un-handled cases.
2071 UnhandledWeights -= I->ExtraWeight;
2072 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2074 /* trueweight */ I->ExtraWeight,
2075 /* falseweight */ UnhandledWeights);
2077 // If emitting the first comparison, just call visitSwitchCase to emit the
2078 // code into the current block. Otherwise, push the CaseBlock onto the
2079 // vector to be later processed by SDISel, and insert the node's MBB
2080 // before the next MBB.
2081 if (CurBlock == SwitchBB)
2082 visitSwitchCase(CB, SwitchBB);
2084 SwitchCases.push_back(CB);
2086 CurBlock = FallThrough;
2092 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2093 return TLI.supportJumpTables() &&
2094 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2095 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2098 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2099 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2100 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2101 return (LastExt - FirstExt + 1ULL);
2104 /// handleJTSwitchCase - Emit jumptable for current switch case range
2105 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2106 CaseRecVector &WorkList,
2108 MachineBasicBlock *Default,
2109 MachineBasicBlock *SwitchBB) {
2110 Case& FrontCase = *CR.Range.first;
2111 Case& BackCase = *(CR.Range.second-1);
2113 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2114 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2116 APInt TSize(First.getBitWidth(), 0);
2117 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2120 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2123 APInt Range = ComputeRange(First, Last);
2124 // The density is TSize / Range. Require at least 40%.
2125 // It should not be possible for IntTSize to saturate for sane code, but make
2126 // sure we handle Range saturation correctly.
2127 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2128 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2129 if (IntTSize * 10 < IntRange * 4)
2132 DEBUG(dbgs() << "Lowering jump table\n"
2133 << "First entry: " << First << ". Last entry: " << Last << '\n'
2134 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2136 // Get the MachineFunction which holds the current MBB. This is used when
2137 // inserting any additional MBBs necessary to represent the switch.
2138 MachineFunction *CurMF = FuncInfo.MF;
2140 // Figure out which block is immediately after the current one.
2141 MachineFunction::iterator BBI = CR.CaseBB;
2144 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2146 // Create a new basic block to hold the code for loading the address
2147 // of the jump table, and jumping to it. Update successor information;
2148 // we will either branch to the default case for the switch, or the jump
2150 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2151 CurMF->insert(BBI, JumpTableBB);
2153 addSuccessorWithWeight(CR.CaseBB, Default);
2154 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2156 // Build a vector of destination BBs, corresponding to each target
2157 // of the jump table. If the value of the jump table slot corresponds to
2158 // a case statement, push the case's BB onto the vector, otherwise, push
2160 std::vector<MachineBasicBlock*> DestBBs;
2162 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2163 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2164 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2166 if (Low.ule(TEI) && TEI.ule(High)) {
2167 DestBBs.push_back(I->BB);
2171 DestBBs.push_back(Default);
2175 // Calculate weight for each unique destination in CR.
2176 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2178 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2179 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2180 DestWeights.find(I->BB);
2181 if (Itr != DestWeights.end())
2182 Itr->second += I->ExtraWeight;
2184 DestWeights[I->BB] = I->ExtraWeight;
2187 // Update successor info. Add one edge to each unique successor.
2188 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2189 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2190 E = DestBBs.end(); I != E; ++I) {
2191 if (!SuccsHandled[(*I)->getNumber()]) {
2192 SuccsHandled[(*I)->getNumber()] = true;
2193 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2194 DestWeights.find(*I);
2195 addSuccessorWithWeight(JumpTableBB, *I,
2196 Itr != DestWeights.end() ? Itr->second : 0);
2200 // Create a jump table index for this jump table.
2201 unsigned JTEncoding = TLI.getJumpTableEncoding();
2202 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2203 ->createJumpTableIndex(DestBBs);
2205 // Set the jump table information so that we can codegen it as a second
2206 // MachineBasicBlock
2207 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2208 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2209 if (CR.CaseBB == SwitchBB)
2210 visitJumpTableHeader(JT, JTH, SwitchBB);
2212 JTCases.push_back(JumpTableBlock(JTH, JT));
2216 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2218 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2219 CaseRecVector& WorkList,
2221 MachineBasicBlock *Default,
2222 MachineBasicBlock *SwitchBB) {
2223 // Get the MachineFunction which holds the current MBB. This is used when
2224 // inserting any additional MBBs necessary to represent the switch.
2225 MachineFunction *CurMF = FuncInfo.MF;
2227 // Figure out which block is immediately after the current one.
2228 MachineFunction::iterator BBI = CR.CaseBB;
2231 Case& FrontCase = *CR.Range.first;
2232 Case& BackCase = *(CR.Range.second-1);
2233 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2235 // Size is the number of Cases represented by this range.
2236 unsigned Size = CR.Range.second - CR.Range.first;
2238 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2239 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2241 CaseItr Pivot = CR.Range.first + Size/2;
2243 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2244 // (heuristically) allow us to emit JumpTable's later.
2245 APInt TSize(First.getBitWidth(), 0);
2246 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2250 APInt LSize = FrontCase.size();
2251 APInt RSize = TSize-LSize;
2252 DEBUG(dbgs() << "Selecting best pivot: \n"
2253 << "First: " << First << ", Last: " << Last <<'\n'
2254 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2255 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2257 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2258 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2259 APInt Range = ComputeRange(LEnd, RBegin);
2260 assert((Range - 2ULL).isNonNegative() &&
2261 "Invalid case distance");
2262 // Use volatile double here to avoid excess precision issues on some hosts,
2263 // e.g. that use 80-bit X87 registers.
2264 volatile double LDensity =
2265 (double)LSize.roundToDouble() /
2266 (LEnd - First + 1ULL).roundToDouble();
2267 volatile double RDensity =
2268 (double)RSize.roundToDouble() /
2269 (Last - RBegin + 1ULL).roundToDouble();
2270 double Metric = Range.logBase2()*(LDensity+RDensity);
2271 // Should always split in some non-trivial place
2272 DEBUG(dbgs() <<"=>Step\n"
2273 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2274 << "LDensity: " << LDensity
2275 << ", RDensity: " << RDensity << '\n'
2276 << "Metric: " << Metric << '\n');
2277 if (FMetric < Metric) {
2280 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2286 if (areJTsAllowed(TLI)) {
2287 // If our case is dense we *really* should handle it earlier!
2288 assert((FMetric > 0) && "Should handle dense range earlier!");
2290 Pivot = CR.Range.first + Size/2;
2293 CaseRange LHSR(CR.Range.first, Pivot);
2294 CaseRange RHSR(Pivot, CR.Range.second);
2295 const Constant *C = Pivot->Low;
2296 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2298 // We know that we branch to the LHS if the Value being switched on is
2299 // less than the Pivot value, C. We use this to optimize our binary
2300 // tree a bit, by recognizing that if SV is greater than or equal to the
2301 // LHS's Case Value, and that Case Value is exactly one less than the
2302 // Pivot's Value, then we can branch directly to the LHS's Target,
2303 // rather than creating a leaf node for it.
2304 if ((LHSR.second - LHSR.first) == 1 &&
2305 LHSR.first->High == CR.GE &&
2306 cast<ConstantInt>(C)->getValue() ==
2307 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2308 TrueBB = LHSR.first->BB;
2310 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2311 CurMF->insert(BBI, TrueBB);
2312 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2314 // Put SV in a virtual register to make it available from the new blocks.
2315 ExportFromCurrentBlock(SV);
2318 // Similar to the optimization above, if the Value being switched on is
2319 // known to be less than the Constant CR.LT, and the current Case Value
2320 // is CR.LT - 1, then we can branch directly to the target block for
2321 // the current Case Value, rather than emitting a RHS leaf node for it.
2322 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2323 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2324 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2325 FalseBB = RHSR.first->BB;
2327 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2328 CurMF->insert(BBI, FalseBB);
2329 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2331 // Put SV in a virtual register to make it available from the new blocks.
2332 ExportFromCurrentBlock(SV);
2335 // Create a CaseBlock record representing a conditional branch to
2336 // the LHS node if the value being switched on SV is less than C.
2337 // Otherwise, branch to LHS.
2338 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2340 if (CR.CaseBB == SwitchBB)
2341 visitSwitchCase(CB, SwitchBB);
2343 SwitchCases.push_back(CB);
2348 /// handleBitTestsSwitchCase - if current case range has few destination and
2349 /// range span less, than machine word bitwidth, encode case range into series
2350 /// of masks and emit bit tests with these masks.
2351 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2352 CaseRecVector& WorkList,
2354 MachineBasicBlock* Default,
2355 MachineBasicBlock *SwitchBB){
2356 EVT PTy = TLI.getPointerTy();
2357 unsigned IntPtrBits = PTy.getSizeInBits();
2359 Case& FrontCase = *CR.Range.first;
2360 Case& BackCase = *(CR.Range.second-1);
2362 // Get the MachineFunction which holds the current MBB. This is used when
2363 // inserting any additional MBBs necessary to represent the switch.
2364 MachineFunction *CurMF = FuncInfo.MF;
2366 // If target does not have legal shift left, do not emit bit tests at all.
2367 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2371 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2373 // Single case counts one, case range - two.
2374 numCmps += (I->Low == I->High ? 1 : 2);
2377 // Count unique destinations
2378 SmallSet<MachineBasicBlock*, 4> Dests;
2379 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2380 Dests.insert(I->BB);
2381 if (Dests.size() > 3)
2382 // Don't bother the code below, if there are too much unique destinations
2385 DEBUG(dbgs() << "Total number of unique destinations: "
2386 << Dests.size() << '\n'
2387 << "Total number of comparisons: " << numCmps << '\n');
2389 // Compute span of values.
2390 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2391 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2392 APInt cmpRange = maxValue - minValue;
2394 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2395 << "Low bound: " << minValue << '\n'
2396 << "High bound: " << maxValue << '\n');
2398 if (cmpRange.uge(IntPtrBits) ||
2399 (!(Dests.size() == 1 && numCmps >= 3) &&
2400 !(Dests.size() == 2 && numCmps >= 5) &&
2401 !(Dests.size() >= 3 && numCmps >= 6)))
2404 DEBUG(dbgs() << "Emitting bit tests\n");
2405 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2407 // Optimize the case where all the case values fit in a
2408 // word without having to subtract minValue. In this case,
2409 // we can optimize away the subtraction.
2410 if (maxValue.ult(IntPtrBits)) {
2411 cmpRange = maxValue;
2413 lowBound = minValue;
2416 CaseBitsVector CasesBits;
2417 unsigned i, count = 0;
2419 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2420 MachineBasicBlock* Dest = I->BB;
2421 for (i = 0; i < count; ++i)
2422 if (Dest == CasesBits[i].BB)
2426 assert((count < 3) && "Too much destinations to test!");
2427 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2431 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2432 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2434 uint64_t lo = (lowValue - lowBound).getZExtValue();
2435 uint64_t hi = (highValue - lowBound).getZExtValue();
2436 CasesBits[i].ExtraWeight += I->ExtraWeight;
2438 for (uint64_t j = lo; j <= hi; j++) {
2439 CasesBits[i].Mask |= 1ULL << j;
2440 CasesBits[i].Bits++;
2444 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2448 // Figure out which block is immediately after the current one.
2449 MachineFunction::iterator BBI = CR.CaseBB;
2452 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2454 DEBUG(dbgs() << "Cases:\n");
2455 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2456 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2457 << ", Bits: " << CasesBits[i].Bits
2458 << ", BB: " << CasesBits[i].BB << '\n');
2460 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2461 CurMF->insert(BBI, CaseBB);
2462 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2464 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2466 // Put SV in a virtual register to make it available from the new blocks.
2467 ExportFromCurrentBlock(SV);
2470 BitTestBlock BTB(lowBound, cmpRange, SV,
2471 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2472 CR.CaseBB, Default, BTC);
2474 if (CR.CaseBB == SwitchBB)
2475 visitBitTestHeader(BTB, SwitchBB);
2477 BitTestCases.push_back(BTB);
2482 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2483 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2484 const SwitchInst& SI) {
2486 /// Use a shorter form of declaration, and also
2487 /// show the we want to use CRSBuilder as Clusterifier.
2488 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2490 Clusterifier TheClusterifier;
2492 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2493 // Start with "simple" cases
2494 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2496 const BasicBlock *SuccBB = i.getCaseSuccessor();
2497 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2499 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2500 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2503 TheClusterifier.optimize();
2506 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2507 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2508 Clusterifier::Cluster &C = *i;
2509 // Update edge weight for the cluster.
2510 unsigned W = C.first.Weight;
2512 // FIXME: Currently work with ConstantInt based numbers.
2513 // Changing it to APInt based is a pretty heavy for this commit.
2514 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2515 C.first.getHigh().toConstantInt(), C.second, W));
2517 if (C.first.getLow() != C.first.getHigh())
2518 // A range counts double, since it requires two compares.
2525 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2526 MachineBasicBlock *Last) {
2528 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2529 if (JTCases[i].first.HeaderBB == First)
2530 JTCases[i].first.HeaderBB = Last;
2532 // Update BitTestCases.
2533 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2534 if (BitTestCases[i].Parent == First)
2535 BitTestCases[i].Parent = Last;
2538 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2539 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2541 // Figure out which block is immediately after the current one.
2542 MachineBasicBlock *NextBlock = 0;
2543 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2545 // If there is only the default destination, branch to it if it is not the
2546 // next basic block. Otherwise, just fall through.
2547 if (!SI.getNumCases()) {
2548 // Update machine-CFG edges.
2550 // If this is not a fall-through branch, emit the branch.
2551 SwitchMBB->addSuccessor(Default);
2552 if (Default != NextBlock)
2553 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2554 MVT::Other, getControlRoot(),
2555 DAG.getBasicBlock(Default)));
2560 // If there are any non-default case statements, create a vector of Cases
2561 // representing each one, and sort the vector so that we can efficiently
2562 // create a binary search tree from them.
2564 size_t numCmps = Clusterify(Cases, SI);
2565 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2566 << ". Total compares: " << numCmps << '\n');
2569 // Get the Value to be switched on and default basic blocks, which will be
2570 // inserted into CaseBlock records, representing basic blocks in the binary
2572 const Value *SV = SI.getCondition();
2574 // Push the initial CaseRec onto the worklist
2575 CaseRecVector WorkList;
2576 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2577 CaseRange(Cases.begin(),Cases.end())));
2579 while (!WorkList.empty()) {
2580 // Grab a record representing a case range to process off the worklist
2581 CaseRec CR = WorkList.back();
2582 WorkList.pop_back();
2584 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2587 // If the range has few cases (two or less) emit a series of specific
2589 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2592 // If the switch has more than N blocks, and is at least 40% dense, and the
2593 // target supports indirect branches, then emit a jump table rather than
2594 // lowering the switch to a binary tree of conditional branches.
2595 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2596 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2599 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2600 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2601 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2605 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2606 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2608 // Update machine-CFG edges with unique successors.
2609 SmallSet<BasicBlock*, 32> Done;
2610 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2611 BasicBlock *BB = I.getSuccessor(i);
2612 bool Inserted = Done.insert(BB);
2616 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2617 addSuccessorWithWeight(IndirectBrMBB, Succ);
2620 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2621 MVT::Other, getControlRoot(),
2622 getValue(I.getAddress())));
2625 void SelectionDAGBuilder::visitFSub(const User &I) {
2626 // -0.0 - X --> fneg
2627 Type *Ty = I.getType();
2628 if (isa<Constant>(I.getOperand(0)) &&
2629 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2630 SDValue Op2 = getValue(I.getOperand(1));
2631 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2632 Op2.getValueType(), Op2));
2636 visitBinary(I, ISD::FSUB);
2639 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2640 SDValue Op1 = getValue(I.getOperand(0));
2641 SDValue Op2 = getValue(I.getOperand(1));
2642 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2643 Op1.getValueType(), Op1, Op2));
2646 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2647 SDValue Op1 = getValue(I.getOperand(0));
2648 SDValue Op2 = getValue(I.getOperand(1));
2650 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2652 // Coerce the shift amount to the right type if we can.
2653 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2654 unsigned ShiftSize = ShiftTy.getSizeInBits();
2655 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2656 DebugLoc DL = getCurDebugLoc();
2658 // If the operand is smaller than the shift count type, promote it.
2659 if (ShiftSize > Op2Size)
2660 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2662 // If the operand is larger than the shift count type but the shift
2663 // count type has enough bits to represent any shift value, truncate
2664 // it now. This is a common case and it exposes the truncate to
2665 // optimization early.
2666 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2667 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2668 // Otherwise we'll need to temporarily settle for some other convenient
2669 // type. Type legalization will make adjustments once the shiftee is split.
2671 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2674 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2675 Op1.getValueType(), Op1, Op2));
2678 void SelectionDAGBuilder::visitSDiv(const User &I) {
2679 SDValue Op1 = getValue(I.getOperand(0));
2680 SDValue Op2 = getValue(I.getOperand(1));
2682 // Turn exact SDivs into multiplications.
2683 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2685 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2686 !isa<ConstantSDNode>(Op1) &&
2687 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2688 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2690 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2694 void SelectionDAGBuilder::visitICmp(const User &I) {
2695 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2696 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2697 predicate = IC->getPredicate();
2698 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2699 predicate = ICmpInst::Predicate(IC->getPredicate());
2700 SDValue Op1 = getValue(I.getOperand(0));
2701 SDValue Op2 = getValue(I.getOperand(1));
2702 ISD::CondCode Opcode = getICmpCondCode(predicate);
2704 EVT DestVT = TLI.getValueType(I.getType());
2705 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2708 void SelectionDAGBuilder::visitFCmp(const User &I) {
2709 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2710 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2711 predicate = FC->getPredicate();
2712 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2713 predicate = FCmpInst::Predicate(FC->getPredicate());
2714 SDValue Op1 = getValue(I.getOperand(0));
2715 SDValue Op2 = getValue(I.getOperand(1));
2716 ISD::CondCode Condition = getFCmpCondCode(predicate);
2717 if (TM.Options.NoNaNsFPMath)
2718 Condition = getFCmpCodeWithoutNaN(Condition);
2719 EVT DestVT = TLI.getValueType(I.getType());
2720 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2723 void SelectionDAGBuilder::visitSelect(const User &I) {
2724 SmallVector<EVT, 4> ValueVTs;
2725 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2726 unsigned NumValues = ValueVTs.size();
2727 if (NumValues == 0) return;
2729 SmallVector<SDValue, 4> Values(NumValues);
2730 SDValue Cond = getValue(I.getOperand(0));
2731 SDValue TrueVal = getValue(I.getOperand(1));
2732 SDValue FalseVal = getValue(I.getOperand(2));
2733 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2734 ISD::VSELECT : ISD::SELECT;
2736 for (unsigned i = 0; i != NumValues; ++i)
2737 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2738 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2740 SDValue(TrueVal.getNode(),
2741 TrueVal.getResNo() + i),
2742 SDValue(FalseVal.getNode(),
2743 FalseVal.getResNo() + i));
2745 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2746 DAG.getVTList(&ValueVTs[0], NumValues),
2747 &Values[0], NumValues));
2750 void SelectionDAGBuilder::visitTrunc(const User &I) {
2751 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2752 SDValue N = getValue(I.getOperand(0));
2753 EVT DestVT = TLI.getValueType(I.getType());
2754 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2757 void SelectionDAGBuilder::visitZExt(const User &I) {
2758 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2759 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2760 SDValue N = getValue(I.getOperand(0));
2761 EVT DestVT = TLI.getValueType(I.getType());
2762 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2765 void SelectionDAGBuilder::visitSExt(const User &I) {
2766 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2767 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2768 SDValue N = getValue(I.getOperand(0));
2769 EVT DestVT = TLI.getValueType(I.getType());
2770 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2773 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2774 // FPTrunc is never a no-op cast, no need to check
2775 SDValue N = getValue(I.getOperand(0));
2776 EVT DestVT = TLI.getValueType(I.getType());
2777 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2779 DAG.getTargetConstant(0, TLI.getPointerTy())));
2782 void SelectionDAGBuilder::visitFPExt(const User &I){
2783 // FPExt is never a no-op cast, no need to check
2784 SDValue N = getValue(I.getOperand(0));
2785 EVT DestVT = TLI.getValueType(I.getType());
2786 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2789 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2790 // FPToUI is never a no-op cast, no need to check
2791 SDValue N = getValue(I.getOperand(0));
2792 EVT DestVT = TLI.getValueType(I.getType());
2793 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2796 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2797 // FPToSI is never a no-op cast, no need to check
2798 SDValue N = getValue(I.getOperand(0));
2799 EVT DestVT = TLI.getValueType(I.getType());
2800 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2803 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2804 // UIToFP is never a no-op cast, no need to check
2805 SDValue N = getValue(I.getOperand(0));
2806 EVT DestVT = TLI.getValueType(I.getType());
2807 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2810 void SelectionDAGBuilder::visitSIToFP(const User &I){
2811 // SIToFP is never a no-op cast, no need to check
2812 SDValue N = getValue(I.getOperand(0));
2813 EVT DestVT = TLI.getValueType(I.getType());
2814 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2817 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2818 // What to do depends on the size of the integer and the size of the pointer.
2819 // We can either truncate, zero extend, or no-op, accordingly.
2820 SDValue N = getValue(I.getOperand(0));
2821 EVT DestVT = TLI.getValueType(I.getType());
2822 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2825 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2826 // What to do depends on the size of the integer and the size of the pointer.
2827 // We can either truncate, zero extend, or no-op, accordingly.
2828 SDValue N = getValue(I.getOperand(0));
2829 EVT DestVT = TLI.getValueType(I.getType());
2830 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2833 void SelectionDAGBuilder::visitBitCast(const User &I) {
2834 SDValue N = getValue(I.getOperand(0));
2835 EVT DestVT = TLI.getValueType(I.getType());
2837 // BitCast assures us that source and destination are the same size so this is
2838 // either a BITCAST or a no-op.
2839 if (DestVT != N.getValueType())
2840 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2841 DestVT, N)); // convert types.
2843 setValue(&I, N); // noop cast.
2846 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2847 SDValue InVec = getValue(I.getOperand(0));
2848 SDValue InVal = getValue(I.getOperand(1));
2849 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2851 getValue(I.getOperand(2)));
2852 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2853 TLI.getValueType(I.getType()),
2854 InVec, InVal, InIdx));
2857 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2858 SDValue InVec = getValue(I.getOperand(0));
2859 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2861 getValue(I.getOperand(1)));
2862 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2863 TLI.getValueType(I.getType()), InVec, InIdx));
2866 // Utility for visitShuffleVector - Return true if every element in Mask,
2867 // beginning from position Pos and ending in Pos+Size, falls within the
2868 // specified sequential range [L, L+Pos). or is undef.
2869 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2870 unsigned Pos, unsigned Size, int Low) {
2871 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2872 if (Mask[i] >= 0 && Mask[i] != Low)
2877 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2878 SDValue Src1 = getValue(I.getOperand(0));
2879 SDValue Src2 = getValue(I.getOperand(1));
2881 SmallVector<int, 8> Mask;
2882 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2883 unsigned MaskNumElts = Mask.size();
2885 EVT VT = TLI.getValueType(I.getType());
2886 EVT SrcVT = Src1.getValueType();
2887 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2889 if (SrcNumElts == MaskNumElts) {
2890 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2895 // Normalize the shuffle vector since mask and vector length don't match.
2896 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2897 // Mask is longer than the source vectors and is a multiple of the source
2898 // vectors. We can use concatenate vector to make the mask and vectors
2900 if (SrcNumElts*2 == MaskNumElts) {
2901 // First check for Src1 in low and Src2 in high
2902 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2903 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2904 // The shuffle is concatenating two vectors together.
2905 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2909 // Then check for Src2 in low and Src1 in high
2910 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2911 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2912 // The shuffle is concatenating two vectors together.
2913 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2919 // Pad both vectors with undefs to make them the same length as the mask.
2920 unsigned NumConcat = MaskNumElts / SrcNumElts;
2921 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2922 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2923 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2925 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2926 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2930 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2931 getCurDebugLoc(), VT,
2932 &MOps1[0], NumConcat);
2933 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2934 getCurDebugLoc(), VT,
2935 &MOps2[0], NumConcat);
2937 // Readjust mask for new input vector length.
2938 SmallVector<int, 8> MappedOps;
2939 for (unsigned i = 0; i != MaskNumElts; ++i) {
2941 if (Idx >= (int)SrcNumElts)
2942 Idx -= SrcNumElts - MaskNumElts;
2943 MappedOps.push_back(Idx);
2946 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2951 if (SrcNumElts > MaskNumElts) {
2952 // Analyze the access pattern of the vector to see if we can extract
2953 // two subvectors and do the shuffle. The analysis is done by calculating
2954 // the range of elements the mask access on both vectors.
2955 int MinRange[2] = { static_cast<int>(SrcNumElts),
2956 static_cast<int>(SrcNumElts)};
2957 int MaxRange[2] = {-1, -1};
2959 for (unsigned i = 0; i != MaskNumElts; ++i) {
2965 if (Idx >= (int)SrcNumElts) {
2969 if (Idx > MaxRange[Input])
2970 MaxRange[Input] = Idx;
2971 if (Idx < MinRange[Input])
2972 MinRange[Input] = Idx;
2975 // Check if the access is smaller than the vector size and can we find
2976 // a reasonable extract index.
2977 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2979 int StartIdx[2]; // StartIdx to extract from
2980 for (unsigned Input = 0; Input < 2; ++Input) {
2981 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2982 RangeUse[Input] = 0; // Unused
2983 StartIdx[Input] = 0;
2987 // Find a good start index that is a multiple of the mask length. Then
2988 // see if the rest of the elements are in range.
2989 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2990 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2991 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2992 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2995 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2996 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2999 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3000 // Extract appropriate subvector and generate a vector shuffle
3001 for (unsigned Input = 0; Input < 2; ++Input) {
3002 SDValue &Src = Input == 0 ? Src1 : Src2;
3003 if (RangeUse[Input] == 0)
3004 Src = DAG.getUNDEF(VT);
3006 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
3007 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3010 // Calculate new mask.
3011 SmallVector<int, 8> MappedOps;
3012 for (unsigned i = 0; i != MaskNumElts; ++i) {
3015 if (Idx < (int)SrcNumElts)
3018 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3020 MappedOps.push_back(Idx);
3023 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
3029 // We can't use either concat vectors or extract subvectors so fall back to
3030 // replacing the shuffle with extract and build vector.
3031 // to insert and build vector.
3032 EVT EltVT = VT.getVectorElementType();
3033 EVT PtrVT = TLI.getPointerTy();
3034 SmallVector<SDValue,8> Ops;
3035 for (unsigned i = 0; i != MaskNumElts; ++i) {
3040 Res = DAG.getUNDEF(EltVT);
3042 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3043 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3045 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
3046 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3052 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
3053 VT, &Ops[0], Ops.size()));
3056 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3057 const Value *Op0 = I.getOperand(0);
3058 const Value *Op1 = I.getOperand(1);
3059 Type *AggTy = I.getType();
3060 Type *ValTy = Op1->getType();
3061 bool IntoUndef = isa<UndefValue>(Op0);
3062 bool FromUndef = isa<UndefValue>(Op1);
3064 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3066 SmallVector<EVT, 4> AggValueVTs;
3067 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3068 SmallVector<EVT, 4> ValValueVTs;
3069 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3071 unsigned NumAggValues = AggValueVTs.size();
3072 unsigned NumValValues = ValValueVTs.size();
3073 SmallVector<SDValue, 4> Values(NumAggValues);
3075 SDValue Agg = getValue(Op0);
3077 // Copy the beginning value(s) from the original aggregate.
3078 for (; i != LinearIndex; ++i)
3079 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3080 SDValue(Agg.getNode(), Agg.getResNo() + i);
3081 // Copy values from the inserted value(s).
3083 SDValue Val = getValue(Op1);
3084 for (; i != LinearIndex + NumValValues; ++i)
3085 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3086 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3088 // Copy remaining value(s) from the original aggregate.
3089 for (; i != NumAggValues; ++i)
3090 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3091 SDValue(Agg.getNode(), Agg.getResNo() + i);
3093 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3094 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3095 &Values[0], NumAggValues));
3098 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3099 const Value *Op0 = I.getOperand(0);
3100 Type *AggTy = Op0->getType();
3101 Type *ValTy = I.getType();
3102 bool OutOfUndef = isa<UndefValue>(Op0);
3104 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3106 SmallVector<EVT, 4> ValValueVTs;
3107 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3109 unsigned NumValValues = ValValueVTs.size();
3111 // Ignore a extractvalue that produces an empty object
3112 if (!NumValValues) {
3113 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3117 SmallVector<SDValue, 4> Values(NumValValues);
3119 SDValue Agg = getValue(Op0);
3120 // Copy out the selected value(s).
3121 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3122 Values[i - LinearIndex] =
3124 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3125 SDValue(Agg.getNode(), Agg.getResNo() + i);
3127 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3128 DAG.getVTList(&ValValueVTs[0], NumValValues),
3129 &Values[0], NumValValues));
3132 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3133 SDValue N = getValue(I.getOperand(0));
3134 // Note that the pointer operand may be a vector of pointers. Take the scalar
3135 // element which holds a pointer.
3136 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3138 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3140 const Value *Idx = *OI;
3141 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3142 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3145 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3146 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3147 DAG.getConstant(Offset, N.getValueType()));
3150 Ty = StTy->getElementType(Field);
3152 Ty = cast<SequentialType>(Ty)->getElementType();
3154 // If this is a constant subscript, handle it quickly.
3155 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3156 if (CI->isZero()) continue;
3158 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3160 EVT PTy = TLI.getPointerTy();
3161 unsigned PtrBits = PTy.getSizeInBits();
3163 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3165 DAG.getConstant(Offs, MVT::i64));
3167 OffsVal = DAG.getIntPtrConstant(Offs);
3169 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3174 // N = N + Idx * ElementSize;
3175 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3176 TD->getTypeAllocSize(Ty));
3177 SDValue IdxN = getValue(Idx);
3179 // If the index is smaller or larger than intptr_t, truncate or extend
3181 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3183 // If this is a multiply by a power of two, turn it into a shl
3184 // immediately. This is a very common case.
3185 if (ElementSize != 1) {
3186 if (ElementSize.isPowerOf2()) {
3187 unsigned Amt = ElementSize.logBase2();
3188 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3189 N.getValueType(), IdxN,
3190 DAG.getConstant(Amt, IdxN.getValueType()));
3192 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3193 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3194 N.getValueType(), IdxN, Scale);
3198 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3199 N.getValueType(), N, IdxN);
3206 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3207 // If this is a fixed sized alloca in the entry block of the function,
3208 // allocate it statically on the stack.
3209 if (FuncInfo.StaticAllocaMap.count(&I))
3210 return; // getValue will auto-populate this.
3212 Type *Ty = I.getAllocatedType();
3213 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3215 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3218 SDValue AllocSize = getValue(I.getArraySize());
3220 EVT IntPtr = TLI.getPointerTy();
3221 if (AllocSize.getValueType() != IntPtr)
3222 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3224 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3226 DAG.getConstant(TySize, IntPtr));
3228 // Handle alignment. If the requested alignment is less than or equal to
3229 // the stack alignment, ignore it. If the size is greater than or equal to
3230 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3231 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3232 if (Align <= StackAlign)
3235 // Round the size of the allocation up to the stack alignment size
3236 // by add SA-1 to the size.
3237 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3238 AllocSize.getValueType(), AllocSize,
3239 DAG.getIntPtrConstant(StackAlign-1));
3241 // Mask out the low bits for alignment purposes.
3242 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3243 AllocSize.getValueType(), AllocSize,
3244 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3246 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3247 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3248 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3251 DAG.setRoot(DSA.getValue(1));
3253 // Inform the Frame Information that we have just allocated a variable-sized
3255 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3258 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3260 return visitAtomicLoad(I);
3262 const Value *SV = I.getOperand(0);
3263 SDValue Ptr = getValue(SV);
3265 Type *Ty = I.getType();
3267 bool isVolatile = I.isVolatile();
3268 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3269 bool isInvariant = I.getMetadata("invariant.load") != 0;
3270 unsigned Alignment = I.getAlignment();
3271 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3272 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3274 SmallVector<EVT, 4> ValueVTs;
3275 SmallVector<uint64_t, 4> Offsets;
3276 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3277 unsigned NumValues = ValueVTs.size();
3282 bool ConstantMemory = false;
3283 if (I.isVolatile() || NumValues > MaxParallelChains)
3284 // Serialize volatile loads with other side effects.
3286 else if (AA->pointsToConstantMemory(
3287 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3288 // Do not serialize (non-volatile) loads of constant memory with anything.
3289 Root = DAG.getEntryNode();
3290 ConstantMemory = true;
3292 // Do not serialize non-volatile loads against each other.
3293 Root = DAG.getRoot();
3296 SmallVector<SDValue, 4> Values(NumValues);
3297 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3299 EVT PtrVT = Ptr.getValueType();
3300 unsigned ChainI = 0;
3301 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3302 // Serializing loads here may result in excessive register pressure, and
3303 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3304 // could recover a bit by hoisting nodes upward in the chain by recognizing
3305 // they are side-effect free or do not alias. The optimizer should really
3306 // avoid this case by converting large object/array copies to llvm.memcpy
3307 // (MaxParallelChains should always remain as failsafe).
3308 if (ChainI == MaxParallelChains) {
3309 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3310 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3311 MVT::Other, &Chains[0], ChainI);
3315 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3317 DAG.getConstant(Offsets[i], PtrVT));
3318 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3319 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3320 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3324 Chains[ChainI] = L.getValue(1);
3327 if (!ConstantMemory) {
3328 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3329 MVT::Other, &Chains[0], ChainI);
3333 PendingLoads.push_back(Chain);
3336 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3337 DAG.getVTList(&ValueVTs[0], NumValues),
3338 &Values[0], NumValues));
3341 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3343 return visitAtomicStore(I);
3345 const Value *SrcV = I.getOperand(0);
3346 const Value *PtrV = I.getOperand(1);
3348 SmallVector<EVT, 4> ValueVTs;
3349 SmallVector<uint64_t, 4> Offsets;
3350 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3351 unsigned NumValues = ValueVTs.size();
3355 // Get the lowered operands. Note that we do this after
3356 // checking if NumResults is zero, because with zero results
3357 // the operands won't have values in the map.
3358 SDValue Src = getValue(SrcV);
3359 SDValue Ptr = getValue(PtrV);
3361 SDValue Root = getRoot();
3362 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3364 EVT PtrVT = Ptr.getValueType();
3365 bool isVolatile = I.isVolatile();
3366 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3367 unsigned Alignment = I.getAlignment();
3368 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3370 unsigned ChainI = 0;
3371 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3372 // See visitLoad comments.
3373 if (ChainI == MaxParallelChains) {
3374 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3375 MVT::Other, &Chains[0], ChainI);
3379 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3380 DAG.getConstant(Offsets[i], PtrVT));
3381 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3382 SDValue(Src.getNode(), Src.getResNo() + i),
3383 Add, MachinePointerInfo(PtrV, Offsets[i]),
3384 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3385 Chains[ChainI] = St;
3388 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3389 MVT::Other, &Chains[0], ChainI);
3391 AssignOrderingToNode(StoreNode.getNode());
3392 DAG.setRoot(StoreNode);
3395 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3396 SynchronizationScope Scope,
3397 bool Before, DebugLoc dl,
3399 const TargetLowering &TLI) {
3400 // Fence, if necessary
3402 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3404 else if (Order == Acquire || Order == Monotonic)
3407 if (Order == AcquireRelease)
3409 else if (Order == Release || Order == Monotonic)
3414 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3415 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3416 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3419 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3420 DebugLoc dl = getCurDebugLoc();
3421 AtomicOrdering Order = I.getOrdering();
3422 SynchronizationScope Scope = I.getSynchScope();
3424 SDValue InChain = getRoot();
3426 if (TLI.getInsertFencesForAtomic())
3427 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3431 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3432 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3434 getValue(I.getPointerOperand()),
3435 getValue(I.getCompareOperand()),
3436 getValue(I.getNewValOperand()),
3437 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3438 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3441 SDValue OutChain = L.getValue(1);
3443 if (TLI.getInsertFencesForAtomic())
3444 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3448 DAG.setRoot(OutChain);
3451 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3452 DebugLoc dl = getCurDebugLoc();
3454 switch (I.getOperation()) {
3455 default: llvm_unreachable("Unknown atomicrmw operation");
3456 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3457 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3458 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3459 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3460 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3461 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3462 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3463 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3464 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3465 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3466 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3468 AtomicOrdering Order = I.getOrdering();
3469 SynchronizationScope Scope = I.getSynchScope();
3471 SDValue InChain = getRoot();
3473 if (TLI.getInsertFencesForAtomic())
3474 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3478 DAG.getAtomic(NT, dl,
3479 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3481 getValue(I.getPointerOperand()),
3482 getValue(I.getValOperand()),
3483 I.getPointerOperand(), 0 /* Alignment */,
3484 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3487 SDValue OutChain = L.getValue(1);
3489 if (TLI.getInsertFencesForAtomic())
3490 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3494 DAG.setRoot(OutChain);
3497 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3498 DebugLoc dl = getCurDebugLoc();
3501 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3502 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3503 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3506 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3507 DebugLoc dl = getCurDebugLoc();
3508 AtomicOrdering Order = I.getOrdering();
3509 SynchronizationScope Scope = I.getSynchScope();
3511 SDValue InChain = getRoot();
3513 EVT VT = TLI.getValueType(I.getType());
3515 if (I.getAlignment() * 8 < VT.getSizeInBits())
3516 report_fatal_error("Cannot generate unaligned atomic load");
3519 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3520 getValue(I.getPointerOperand()),
3521 I.getPointerOperand(), I.getAlignment(),
3522 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3525 SDValue OutChain = L.getValue(1);
3527 if (TLI.getInsertFencesForAtomic())
3528 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3532 DAG.setRoot(OutChain);
3535 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3536 DebugLoc dl = getCurDebugLoc();
3538 AtomicOrdering Order = I.getOrdering();
3539 SynchronizationScope Scope = I.getSynchScope();
3541 SDValue InChain = getRoot();
3543 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3545 if (I.getAlignment() * 8 < VT.getSizeInBits())
3546 report_fatal_error("Cannot generate unaligned atomic store");
3548 if (TLI.getInsertFencesForAtomic())
3549 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3553 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3555 getValue(I.getPointerOperand()),
3556 getValue(I.getValueOperand()),
3557 I.getPointerOperand(), I.getAlignment(),
3558 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3561 if (TLI.getInsertFencesForAtomic())
3562 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3565 DAG.setRoot(OutChain);
3568 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3570 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3571 unsigned Intrinsic) {
3572 bool HasChain = !I.doesNotAccessMemory();
3573 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3575 // Build the operand list.
3576 SmallVector<SDValue, 8> Ops;
3577 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3579 // We don't need to serialize loads against other loads.
3580 Ops.push_back(DAG.getRoot());
3582 Ops.push_back(getRoot());
3586 // Info is set by getTgtMemInstrinsic
3587 TargetLowering::IntrinsicInfo Info;
3588 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3590 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3591 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3592 Info.opc == ISD::INTRINSIC_W_CHAIN)
3593 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3595 // Add all operands of the call to the operand list.
3596 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3597 SDValue Op = getValue(I.getArgOperand(i));
3601 SmallVector<EVT, 4> ValueVTs;
3602 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3605 ValueVTs.push_back(MVT::Other);
3607 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3611 if (IsTgtIntrinsic) {
3612 // This is target intrinsic that touches memory
3613 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3614 VTs, &Ops[0], Ops.size(),
3616 MachinePointerInfo(Info.ptrVal, Info.offset),
3617 Info.align, Info.vol,
3618 Info.readMem, Info.writeMem);
3619 } else if (!HasChain) {
3620 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3621 VTs, &Ops[0], Ops.size());
3622 } else if (!I.getType()->isVoidTy()) {
3623 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3624 VTs, &Ops[0], Ops.size());
3626 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3627 VTs, &Ops[0], Ops.size());
3631 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3633 PendingLoads.push_back(Chain);
3638 if (!I.getType()->isVoidTy()) {
3639 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3640 EVT VT = TLI.getValueType(PTy);
3641 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3644 setValue(&I, Result);
3646 // Assign order to result here. If the intrinsic does not produce a result,
3647 // it won't be mapped to a SDNode and visit() will not assign it an order
3650 AssignOrderingToNode(Result.getNode());
3654 /// GetSignificand - Get the significand and build it into a floating-point
3655 /// number with exponent of 1:
3657 /// Op = (Op & 0x007fffff) | 0x3f800000;
3659 /// where Op is the hexidecimal representation of floating point value.
3661 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3662 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3663 DAG.getConstant(0x007fffff, MVT::i32));
3664 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3665 DAG.getConstant(0x3f800000, MVT::i32));
3666 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3669 /// GetExponent - Get the exponent:
3671 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3673 /// where Op is the hexidecimal representation of floating point value.
3675 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3677 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3678 DAG.getConstant(0x7f800000, MVT::i32));
3679 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3680 DAG.getConstant(23, TLI.getPointerTy()));
3681 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3682 DAG.getConstant(127, MVT::i32));
3683 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3686 /// getF32Constant - Get 32-bit floating point constant.
3688 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3689 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3692 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3693 /// limited-precision mode.
3694 static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3695 const TargetLowering &TLI) {
3696 if (Op.getValueType() == MVT::f32 &&
3697 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3699 // Put the exponent in the right bit position for later addition to the
3702 // #define LOG2OFe 1.4426950f
3703 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3704 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3705 getF32Constant(DAG, 0x3fb8aa3b));
3706 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3708 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3709 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3710 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3712 // IntegerPartOfX <<= 23;
3713 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3714 DAG.getConstant(23, TLI.getPointerTy()));
3716 SDValue TwoToFracPartOfX;
3717 if (LimitFloatPrecision <= 6) {
3718 // For floating-point precision of 6:
3720 // TwoToFractionalPartOfX =
3722 // (0.735607626f + 0.252464424f * x) * x;
3724 // error 0.0144103317, which is 6 bits
3725 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3726 getF32Constant(DAG, 0x3e814304));
3727 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3728 getF32Constant(DAG, 0x3f3c50c8));
3729 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3730 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3731 getF32Constant(DAG, 0x3f7f5e7e));
3732 } else if (LimitFloatPrecision <= 12) {
3733 // For floating-point precision of 12:
3735 // TwoToFractionalPartOfX =
3738 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3740 // 0.000107046256 error, which is 13 to 14 bits
3741 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3742 getF32Constant(DAG, 0x3da235e3));
3743 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3744 getF32Constant(DAG, 0x3e65b8f3));
3745 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3746 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3747 getF32Constant(DAG, 0x3f324b07));
3748 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3749 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3750 getF32Constant(DAG, 0x3f7ff8fd));
3751 } else { // LimitFloatPrecision <= 18
3752 // For floating-point precision of 18:
3754 // TwoToFractionalPartOfX =
3758 // (0.554906021e-1f +
3759 // (0.961591928e-2f +
3760 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3762 // error 2.47208000*10^(-7), which is better than 18 bits
3763 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3764 getF32Constant(DAG, 0x3924b03e));
3765 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3766 getF32Constant(DAG, 0x3ab24b87));
3767 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3768 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3769 getF32Constant(DAG, 0x3c1d8c17));
3770 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3771 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3772 getF32Constant(DAG, 0x3d634a1d));
3773 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3774 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3775 getF32Constant(DAG, 0x3e75fe14));
3776 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3777 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3778 getF32Constant(DAG, 0x3f317234));
3779 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3780 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3781 getF32Constant(DAG, 0x3f800000));
3784 // Add the exponent into the result in integer domain.
3785 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3786 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3787 DAG.getNode(ISD::ADD, dl, MVT::i32,
3788 t13, IntegerPartOfX));
3791 // No special expansion.
3792 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3795 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3796 /// limited-precision mode.
3797 static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3798 const TargetLowering &TLI) {
3799 if (Op.getValueType() == MVT::f32 &&
3800 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3801 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3803 // Scale the exponent by log(2) [0.69314718f].
3804 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3805 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3806 getF32Constant(DAG, 0x3f317218));
3808 // Get the significand and build it into a floating-point number with
3810 SDValue X = GetSignificand(DAG, Op1, dl);
3812 SDValue LogOfMantissa;
3813 if (LimitFloatPrecision <= 6) {
3814 // For floating-point precision of 6:
3818 // (1.4034025f - 0.23903021f * x) * x;
3820 // error 0.0034276066, which is better than 8 bits
3821 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3822 getF32Constant(DAG, 0xbe74c456));
3823 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3824 getF32Constant(DAG, 0x3fb3a2b1));
3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3826 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3827 getF32Constant(DAG, 0x3f949a29));
3828 } else if (LimitFloatPrecision <= 12) {
3829 // For floating-point precision of 12:
3835 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3837 // error 0.000061011436, which is 14 bits
3838 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3839 getF32Constant(DAG, 0xbd67b6d6));
3840 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3841 getF32Constant(DAG, 0x3ee4f4b8));
3842 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3843 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3844 getF32Constant(DAG, 0x3fbc278b));
3845 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3846 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3847 getF32Constant(DAG, 0x40348e95));
3848 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3849 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3850 getF32Constant(DAG, 0x3fdef31a));
3851 } else { // LimitFloatPrecision <= 18
3852 // For floating-point precision of 18:
3860 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3862 // error 0.0000023660568, which is better than 18 bits
3863 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3864 getF32Constant(DAG, 0xbc91e5ac));
3865 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3866 getF32Constant(DAG, 0x3e4350aa));
3867 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3868 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3869 getF32Constant(DAG, 0x3f60d3e3));
3870 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3871 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3872 getF32Constant(DAG, 0x4011cdf0));
3873 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3874 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3875 getF32Constant(DAG, 0x406cfd1c));
3876 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3877 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3878 getF32Constant(DAG, 0x408797cb));
3879 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3880 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3881 getF32Constant(DAG, 0x4006dcab));
3884 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3887 // No special expansion.
3888 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3891 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3892 /// limited-precision mode.
3893 static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3894 const TargetLowering &TLI) {
3895 if (Op.getValueType() == MVT::f32 &&
3896 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3897 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3899 // Get the exponent.
3900 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3902 // Get the significand and build it into a floating-point number with
3904 SDValue X = GetSignificand(DAG, Op1, dl);
3906 // Different possible minimax approximations of significand in
3907 // floating-point for various degrees of accuracy over [1,2].
3908 SDValue Log2ofMantissa;
3909 if (LimitFloatPrecision <= 6) {
3910 // For floating-point precision of 6:
3912 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3914 // error 0.0049451742, which is more than 7 bits
3915 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3916 getF32Constant(DAG, 0xbeb08fe0));
3917 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3918 getF32Constant(DAG, 0x40019463));
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3920 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3921 getF32Constant(DAG, 0x3fd6633d));
3922 } else if (LimitFloatPrecision <= 12) {
3923 // For floating-point precision of 12:
3929 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3931 // error 0.0000876136000, which is better than 13 bits
3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0xbda7262e));
3934 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3935 getF32Constant(DAG, 0x3f25280b));
3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3937 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x4007b923));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x40823e2f));
3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3943 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3944 getF32Constant(DAG, 0x4020d29c));
3945 } else { // LimitFloatPrecision <= 18
3946 // For floating-point precision of 18:
3955 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3957 // error 0.0000018516, which is better than 18 bits
3958 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3959 getF32Constant(DAG, 0xbcd2769e));
3960 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3961 getF32Constant(DAG, 0x3e8ce0b9));
3962 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3963 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3964 getF32Constant(DAG, 0x3fa22ae7));
3965 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3966 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3967 getF32Constant(DAG, 0x40525723));
3968 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3969 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3970 getF32Constant(DAG, 0x40aaf200));
3971 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3972 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3973 getF32Constant(DAG, 0x40c39dad));
3974 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3975 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3976 getF32Constant(DAG, 0x4042902c));
3979 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3982 // No special expansion.
3983 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3986 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3987 /// limited-precision mode.
3988 static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3989 const TargetLowering &TLI) {
3990 if (Op.getValueType() == MVT::f32 &&
3991 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3992 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3994 // Scale the exponent by log10(2) [0.30102999f].
3995 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3996 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3997 getF32Constant(DAG, 0x3e9a209a));
3999 // Get the significand and build it into a floating-point number with
4001 SDValue X = GetSignificand(DAG, Op1, dl);
4003 SDValue Log10ofMantissa;
4004 if (LimitFloatPrecision <= 6) {
4005 // For floating-point precision of 6:
4007 // Log10ofMantissa =
4009 // (0.60948995f - 0.10380950f * x) * x;
4011 // error 0.0014886165, which is 6 bits
4012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4013 getF32Constant(DAG, 0xbdd49a13));
4014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4015 getF32Constant(DAG, 0x3f1c0789));
4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4017 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4018 getF32Constant(DAG, 0x3f011300));
4019 } else if (LimitFloatPrecision <= 12) {
4020 // For floating-point precision of 12:
4022 // Log10ofMantissa =
4025 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4027 // error 0.00019228036, which is better than 12 bits
4028 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4029 getF32Constant(DAG, 0x3d431f31));
4030 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4031 getF32Constant(DAG, 0x3ea21fb2));
4032 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4033 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4034 getF32Constant(DAG, 0x3f6ae232));
4035 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4036 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4037 getF32Constant(DAG, 0x3f25f7c3));
4038 } else { // LimitFloatPrecision <= 18
4039 // For floating-point precision of 18:
4041 // Log10ofMantissa =
4046 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4048 // error 0.0000037995730, which is better than 18 bits
4049 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4050 getF32Constant(DAG, 0x3c5d51ce));
4051 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4052 getF32Constant(DAG, 0x3e00685a));
4053 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4054 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4055 getF32Constant(DAG, 0x3efb6798));
4056 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4057 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4058 getF32Constant(DAG, 0x3f88d192));
4059 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4060 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4061 getF32Constant(DAG, 0x3fc4316c));
4062 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4063 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4064 getF32Constant(DAG, 0x3f57ce70));
4067 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4070 // No special expansion.
4071 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4074 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4075 /// limited-precision mode.
4076 static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
4077 const TargetLowering &TLI) {
4078 if (Op.getValueType() == MVT::f32 &&
4079 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4080 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4082 // FractionalPartOfX = x - (float)IntegerPartOfX;
4083 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4084 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4086 // IntegerPartOfX <<= 23;
4087 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4088 DAG.getConstant(23, TLI.getPointerTy()));
4090 SDValue TwoToFractionalPartOfX;
4091 if (LimitFloatPrecision <= 6) {
4092 // For floating-point precision of 6:
4094 // TwoToFractionalPartOfX =
4096 // (0.735607626f + 0.252464424f * x) * x;
4098 // error 0.0144103317, which is 6 bits
4099 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4100 getF32Constant(DAG, 0x3e814304));
4101 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4102 getF32Constant(DAG, 0x3f3c50c8));
4103 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4104 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4105 getF32Constant(DAG, 0x3f7f5e7e));
4106 } else if (LimitFloatPrecision <= 12) {
4107 // For floating-point precision of 12:
4109 // TwoToFractionalPartOfX =
4112 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4114 // error 0.000107046256, which is 13 to 14 bits
4115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4116 getF32Constant(DAG, 0x3da235e3));
4117 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4118 getF32Constant(DAG, 0x3e65b8f3));
4119 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4120 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4121 getF32Constant(DAG, 0x3f324b07));
4122 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4123 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4124 getF32Constant(DAG, 0x3f7ff8fd));
4125 } else { // LimitFloatPrecision <= 18
4126 // For floating-point precision of 18:
4128 // TwoToFractionalPartOfX =
4132 // (0.554906021e-1f +
4133 // (0.961591928e-2f +
4134 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4135 // error 2.47208000*10^(-7), which is better than 18 bits
4136 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4137 getF32Constant(DAG, 0x3924b03e));
4138 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4139 getF32Constant(DAG, 0x3ab24b87));
4140 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4141 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4142 getF32Constant(DAG, 0x3c1d8c17));
4143 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4144 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4145 getF32Constant(DAG, 0x3d634a1d));
4146 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4147 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4148 getF32Constant(DAG, 0x3e75fe14));
4149 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4150 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4151 getF32Constant(DAG, 0x3f317234));
4152 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4153 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4154 getF32Constant(DAG, 0x3f800000));
4157 // Add the exponent into the result in integer domain.
4158 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4159 TwoToFractionalPartOfX);
4160 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4161 DAG.getNode(ISD::ADD, dl, MVT::i32,
4162 t13, IntegerPartOfX));
4165 // No special expansion.
4166 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4169 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4170 /// limited-precision mode with x == 10.0f.
4171 static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS,
4172 SelectionDAG &DAG, const TargetLowering &TLI) {
4173 bool IsExp10 = false;
4174 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4175 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4176 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4178 IsExp10 = LHSC->isExactlyValue(Ten);
4183 // Put the exponent in the right bit position for later addition to the
4186 // #define LOG2OF10 3.3219281f
4187 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4188 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4189 getF32Constant(DAG, 0x40549a78));
4190 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4192 // FractionalPartOfX = x - (float)IntegerPartOfX;
4193 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4194 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4196 // IntegerPartOfX <<= 23;
4197 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4198 DAG.getConstant(23, TLI.getPointerTy()));
4200 SDValue TwoToFractionalPartOfX;
4201 if (LimitFloatPrecision <= 6) {
4202 // For floating-point precision of 6:
4204 // twoToFractionalPartOfX =
4206 // (0.735607626f + 0.252464424f * x) * x;
4208 // error 0.0144103317, which is 6 bits
4209 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4210 getF32Constant(DAG, 0x3e814304));
4211 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4212 getF32Constant(DAG, 0x3f3c50c8));
4213 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4214 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4215 getF32Constant(DAG, 0x3f7f5e7e));
4216 } else if (LimitFloatPrecision <= 12) {
4217 // For floating-point precision of 12:
4219 // TwoToFractionalPartOfX =
4222 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4224 // error 0.000107046256, which is 13 to 14 bits
4225 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4226 getF32Constant(DAG, 0x3da235e3));
4227 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4228 getF32Constant(DAG, 0x3e65b8f3));
4229 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4230 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4231 getF32Constant(DAG, 0x3f324b07));
4232 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4233 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4234 getF32Constant(DAG, 0x3f7ff8fd));
4235 } else { // LimitFloatPrecision <= 18
4236 // For floating-point precision of 18:
4238 // TwoToFractionalPartOfX =
4242 // (0.554906021e-1f +
4243 // (0.961591928e-2f +
4244 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4245 // error 2.47208000*10^(-7), which is better than 18 bits
4246 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4247 getF32Constant(DAG, 0x3924b03e));
4248 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4249 getF32Constant(DAG, 0x3ab24b87));
4250 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4251 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4252 getF32Constant(DAG, 0x3c1d8c17));
4253 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4254 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4255 getF32Constant(DAG, 0x3d634a1d));
4256 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4257 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4258 getF32Constant(DAG, 0x3e75fe14));
4259 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4260 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4261 getF32Constant(DAG, 0x3f317234));
4262 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4263 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4264 getF32Constant(DAG, 0x3f800000));
4267 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4268 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4269 DAG.getNode(ISD::ADD, dl, MVT::i32,
4270 t13, IntegerPartOfX));
4273 // No special expansion.
4274 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4278 /// ExpandPowI - Expand a llvm.powi intrinsic.
4279 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4280 SelectionDAG &DAG) {
4281 // If RHS is a constant, we can expand this out to a multiplication tree,
4282 // otherwise we end up lowering to a call to __powidf2 (for example). When
4283 // optimizing for size, we only want to do this if the expansion would produce
4284 // a small number of multiplies, otherwise we do the full expansion.
4285 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4286 // Get the exponent as a positive value.
4287 unsigned Val = RHSC->getSExtValue();
4288 if ((int)Val < 0) Val = -Val;
4290 // powi(x, 0) -> 1.0
4292 return DAG.getConstantFP(1.0, LHS.getValueType());
4294 const Function *F = DAG.getMachineFunction().getFunction();
4295 if (!F->getFnAttributes().hasAttribute(Attributes::OptimizeForSize) ||
4296 // If optimizing for size, don't insert too many multiplies. This
4297 // inserts up to 5 multiplies.
4298 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4299 // We use the simple binary decomposition method to generate the multiply
4300 // sequence. There are more optimal ways to do this (for example,
4301 // powi(x,15) generates one more multiply than it should), but this has
4302 // the benefit of being both really simple and much better than a libcall.
4303 SDValue Res; // Logically starts equal to 1.0
4304 SDValue CurSquare = LHS;
4308 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4310 Res = CurSquare; // 1.0*CurSquare.
4313 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4314 CurSquare, CurSquare);
4318 // If the original was negative, invert the result, producing 1/(x*x*x).
4319 if (RHSC->getSExtValue() < 0)
4320 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4321 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4326 // Otherwise, expand to a libcall.
4327 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4330 // getTruncatedArgReg - Find underlying register used for an truncated
4332 static unsigned getTruncatedArgReg(const SDValue &N) {
4333 if (N.getOpcode() != ISD::TRUNCATE)
4336 const SDValue &Ext = N.getOperand(0);
4337 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4338 const SDValue &CFR = Ext.getOperand(0);
4339 if (CFR.getOpcode() == ISD::CopyFromReg)
4340 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4341 if (CFR.getOpcode() == ISD::TRUNCATE)
4342 return getTruncatedArgReg(CFR);
4347 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4348 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4349 /// At the end of instruction selection, they will be inserted to the entry BB.
4351 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4354 const Argument *Arg = dyn_cast<Argument>(V);
4358 MachineFunction &MF = DAG.getMachineFunction();
4359 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4360 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4362 // Ignore inlined function arguments here.
4363 DIVariable DV(Variable);
4364 if (DV.isInlinedFnArgument(MF.getFunction()))
4368 // Some arguments' frame index is recorded during argument lowering.
4369 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4371 Reg = TRI->getFrameRegister(MF);
4373 if (!Reg && N.getNode()) {
4374 if (N.getOpcode() == ISD::CopyFromReg)
4375 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4377 Reg = getTruncatedArgReg(N);
4378 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4379 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4380 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4387 // Check if ValueMap has reg number.
4388 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4389 if (VMI != FuncInfo.ValueMap.end())
4393 if (!Reg && N.getNode()) {
4394 // Check if frame index is available.
4395 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4396 if (FrameIndexSDNode *FINode =
4397 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4398 Reg = TRI->getFrameRegister(MF);
4399 Offset = FINode->getIndex();
4406 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4407 TII->get(TargetOpcode::DBG_VALUE))
4408 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4409 FuncInfo.ArgDbgValues.push_back(&*MIB);
4413 // VisualStudio defines setjmp as _setjmp
4414 #if defined(_MSC_VER) && defined(setjmp) && \
4415 !defined(setjmp_undefined_for_msvc)
4416 # pragma push_macro("setjmp")
4418 # define setjmp_undefined_for_msvc
4421 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4422 /// we want to emit this as a call to a named external function, return the name
4423 /// otherwise lower it and return null.
4425 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4426 DebugLoc dl = getCurDebugLoc();
4429 switch (Intrinsic) {
4431 // By default, turn this into a target intrinsic node.
4432 visitTargetIntrinsic(I, Intrinsic);
4434 case Intrinsic::vastart: visitVAStart(I); return 0;
4435 case Intrinsic::vaend: visitVAEnd(I); return 0;
4436 case Intrinsic::vacopy: visitVACopy(I); return 0;
4437 case Intrinsic::returnaddress:
4438 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4439 getValue(I.getArgOperand(0))));
4441 case Intrinsic::frameaddress:
4442 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4443 getValue(I.getArgOperand(0))));
4445 case Intrinsic::setjmp:
4446 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4447 case Intrinsic::longjmp:
4448 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4449 case Intrinsic::memcpy: {
4450 // Assert for address < 256 since we support only user defined address
4452 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4454 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4456 "Unknown address space");
4457 SDValue Op1 = getValue(I.getArgOperand(0));
4458 SDValue Op2 = getValue(I.getArgOperand(1));
4459 SDValue Op3 = getValue(I.getArgOperand(2));
4460 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4461 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4462 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4463 MachinePointerInfo(I.getArgOperand(0)),
4464 MachinePointerInfo(I.getArgOperand(1))));
4467 case Intrinsic::memset: {
4468 // Assert for address < 256 since we support only user defined address
4470 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4472 "Unknown address space");
4473 SDValue Op1 = getValue(I.getArgOperand(0));
4474 SDValue Op2 = getValue(I.getArgOperand(1));
4475 SDValue Op3 = getValue(I.getArgOperand(2));
4476 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4477 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4478 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4479 MachinePointerInfo(I.getArgOperand(0))));
4482 case Intrinsic::memmove: {
4483 // Assert for address < 256 since we support only user defined address
4485 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4487 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4489 "Unknown address space");
4490 SDValue Op1 = getValue(I.getArgOperand(0));
4491 SDValue Op2 = getValue(I.getArgOperand(1));
4492 SDValue Op3 = getValue(I.getArgOperand(2));
4493 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4494 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4495 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4496 MachinePointerInfo(I.getArgOperand(0)),
4497 MachinePointerInfo(I.getArgOperand(1))));
4500 case Intrinsic::dbg_declare: {
4501 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4502 MDNode *Variable = DI.getVariable();
4503 const Value *Address = DI.getAddress();
4504 if (!Address || !DIVariable(Variable).Verify()) {
4505 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4509 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4510 // but do not always have a corresponding SDNode built. The SDNodeOrder
4511 // absolute, but not relative, values are different depending on whether
4512 // debug info exists.
4515 // Check if address has undef value.
4516 if (isa<UndefValue>(Address) ||
4517 (Address->use_empty() && !isa<Argument>(Address))) {
4518 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4522 SDValue &N = NodeMap[Address];
4523 if (!N.getNode() && isa<Argument>(Address))
4524 // Check unused arguments map.
4525 N = UnusedArgNodeMap[Address];
4528 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4529 Address = BCI->getOperand(0);
4530 // Parameters are handled specially.
4532 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4533 isa<Argument>(Address));
4535 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4537 if (isParameter && !AI) {
4538 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4540 // Byval parameter. We have a frame index at this point.
4541 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4542 0, dl, SDNodeOrder);
4544 // Address is an argument, so try to emit its dbg value using
4545 // virtual register info from the FuncInfo.ValueMap.
4546 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4550 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4551 0, dl, SDNodeOrder);
4553 // Can't do anything with other non-AI cases yet.
4554 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4555 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4556 DEBUG(Address->dump());
4559 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4561 // If Address is an argument then try to emit its dbg value using
4562 // virtual register info from the FuncInfo.ValueMap.
4563 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4564 // If variable is pinned by a alloca in dominating bb then
4565 // use StaticAllocaMap.
4566 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4567 if (AI->getParent() != DI.getParent()) {
4568 DenseMap<const AllocaInst*, int>::iterator SI =
4569 FuncInfo.StaticAllocaMap.find(AI);
4570 if (SI != FuncInfo.StaticAllocaMap.end()) {
4571 SDV = DAG.getDbgValue(Variable, SI->second,
4572 0, dl, SDNodeOrder);
4573 DAG.AddDbgValue(SDV, 0, false);
4578 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4583 case Intrinsic::dbg_value: {
4584 const DbgValueInst &DI = cast<DbgValueInst>(I);
4585 if (!DIVariable(DI.getVariable()).Verify())
4588 MDNode *Variable = DI.getVariable();
4589 uint64_t Offset = DI.getOffset();
4590 const Value *V = DI.getValue();
4594 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4595 // but do not always have a corresponding SDNode built. The SDNodeOrder
4596 // absolute, but not relative, values are different depending on whether
4597 // debug info exists.
4600 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4601 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4602 DAG.AddDbgValue(SDV, 0, false);
4604 // Do not use getValue() in here; we don't want to generate code at
4605 // this point if it hasn't been done yet.
4606 SDValue N = NodeMap[V];
4607 if (!N.getNode() && isa<Argument>(V))
4608 // Check unused arguments map.
4609 N = UnusedArgNodeMap[V];
4611 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4612 SDV = DAG.getDbgValue(Variable, N.getNode(),
4613 N.getResNo(), Offset, dl, SDNodeOrder);
4614 DAG.AddDbgValue(SDV, N.getNode(), false);
4616 } else if (!V->use_empty() ) {
4617 // Do not call getValue(V) yet, as we don't want to generate code.
4618 // Remember it for later.
4619 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4620 DanglingDebugInfoMap[V] = DDI;
4622 // We may expand this to cover more cases. One case where we have no
4623 // data available is an unreferenced parameter.
4624 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4628 // Build a debug info table entry.
4629 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4630 V = BCI->getOperand(0);
4631 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4632 // Don't handle byval struct arguments or VLAs, for example.
4634 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4635 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4638 DenseMap<const AllocaInst*, int>::iterator SI =
4639 FuncInfo.StaticAllocaMap.find(AI);
4640 if (SI == FuncInfo.StaticAllocaMap.end())
4642 int FI = SI->second;
4644 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4645 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4646 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4650 case Intrinsic::eh_typeid_for: {
4651 // Find the type id for the given typeinfo.
4652 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4653 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4654 Res = DAG.getConstant(TypeID, MVT::i32);
4659 case Intrinsic::eh_return_i32:
4660 case Intrinsic::eh_return_i64:
4661 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4662 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4665 getValue(I.getArgOperand(0)),
4666 getValue(I.getArgOperand(1))));
4668 case Intrinsic::eh_unwind_init:
4669 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4671 case Intrinsic::eh_dwarf_cfa: {
4672 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4673 TLI.getPointerTy());
4674 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4676 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4677 TLI.getPointerTy()),
4679 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4681 DAG.getConstant(0, TLI.getPointerTy()));
4682 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4686 case Intrinsic::eh_sjlj_callsite: {
4687 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4688 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4689 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4690 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4692 MMI.setCurrentCallSite(CI->getZExtValue());
4695 case Intrinsic::eh_sjlj_functioncontext: {
4696 // Get and store the index of the function context.
4697 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4699 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4700 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4701 MFI->setFunctionContextIndex(FI);
4704 case Intrinsic::eh_sjlj_setjmp: {
4707 Ops[1] = getValue(I.getArgOperand(0));
4708 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4709 DAG.getVTList(MVT::i32, MVT::Other),
4711 setValue(&I, Op.getValue(0));
4712 DAG.setRoot(Op.getValue(1));
4715 case Intrinsic::eh_sjlj_longjmp: {
4716 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4717 getRoot(), getValue(I.getArgOperand(0))));
4721 case Intrinsic::x86_mmx_pslli_w:
4722 case Intrinsic::x86_mmx_pslli_d:
4723 case Intrinsic::x86_mmx_pslli_q:
4724 case Intrinsic::x86_mmx_psrli_w:
4725 case Intrinsic::x86_mmx_psrli_d:
4726 case Intrinsic::x86_mmx_psrli_q:
4727 case Intrinsic::x86_mmx_psrai_w:
4728 case Intrinsic::x86_mmx_psrai_d: {
4729 SDValue ShAmt = getValue(I.getArgOperand(1));
4730 if (isa<ConstantSDNode>(ShAmt)) {
4731 visitTargetIntrinsic(I, Intrinsic);
4734 unsigned NewIntrinsic = 0;
4735 EVT ShAmtVT = MVT::v2i32;
4736 switch (Intrinsic) {
4737 case Intrinsic::x86_mmx_pslli_w:
4738 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4740 case Intrinsic::x86_mmx_pslli_d:
4741 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4743 case Intrinsic::x86_mmx_pslli_q:
4744 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4746 case Intrinsic::x86_mmx_psrli_w:
4747 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4749 case Intrinsic::x86_mmx_psrli_d:
4750 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4752 case Intrinsic::x86_mmx_psrli_q:
4753 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4755 case Intrinsic::x86_mmx_psrai_w:
4756 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4758 case Intrinsic::x86_mmx_psrai_d:
4759 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4761 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4764 // The vector shift intrinsics with scalars uses 32b shift amounts but
4765 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4767 // We must do this early because v2i32 is not a legal type.
4770 ShOps[1] = DAG.getConstant(0, MVT::i32);
4771 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4772 EVT DestVT = TLI.getValueType(I.getType());
4773 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4774 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4775 DAG.getConstant(NewIntrinsic, MVT::i32),
4776 getValue(I.getArgOperand(0)), ShAmt);
4780 case Intrinsic::x86_avx_vinsertf128_pd_256:
4781 case Intrinsic::x86_avx_vinsertf128_ps_256:
4782 case Intrinsic::x86_avx_vinsertf128_si_256:
4783 case Intrinsic::x86_avx2_vinserti128: {
4784 EVT DestVT = TLI.getValueType(I.getType());
4785 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4786 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4787 ElVT.getVectorNumElements();
4788 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4789 getValue(I.getArgOperand(0)),
4790 getValue(I.getArgOperand(1)),
4791 DAG.getIntPtrConstant(Idx));
4795 case Intrinsic::x86_avx_vextractf128_pd_256:
4796 case Intrinsic::x86_avx_vextractf128_ps_256:
4797 case Intrinsic::x86_avx_vextractf128_si_256:
4798 case Intrinsic::x86_avx2_vextracti128: {
4799 EVT DestVT = TLI.getValueType(I.getType());
4800 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4801 DestVT.getVectorNumElements();
4802 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4803 getValue(I.getArgOperand(0)),
4804 DAG.getIntPtrConstant(Idx));
4808 case Intrinsic::convertff:
4809 case Intrinsic::convertfsi:
4810 case Intrinsic::convertfui:
4811 case Intrinsic::convertsif:
4812 case Intrinsic::convertuif:
4813 case Intrinsic::convertss:
4814 case Intrinsic::convertsu:
4815 case Intrinsic::convertus:
4816 case Intrinsic::convertuu: {
4817 ISD::CvtCode Code = ISD::CVT_INVALID;
4818 switch (Intrinsic) {
4819 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4820 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4821 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4822 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4823 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4824 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4825 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4826 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4827 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4828 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4830 EVT DestVT = TLI.getValueType(I.getType());
4831 const Value *Op1 = I.getArgOperand(0);
4832 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1),
4833 DAG.getValueType(DestVT),
4834 DAG.getValueType(getValue(Op1).getValueType()),
4835 getValue(I.getArgOperand(1)),
4836 getValue(I.getArgOperand(2)),
4841 case Intrinsic::powi:
4842 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4843 getValue(I.getArgOperand(1)), DAG));
4845 case Intrinsic::log:
4846 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4848 case Intrinsic::log2:
4849 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4851 case Intrinsic::log10:
4852 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4854 case Intrinsic::exp:
4855 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4857 case Intrinsic::exp2:
4858 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4860 case Intrinsic::pow:
4861 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)),
4862 getValue(I.getArgOperand(1)), DAG, TLI));
4864 case Intrinsic::sqrt:
4865 case Intrinsic::fabs:
4866 case Intrinsic::sin:
4867 case Intrinsic::cos:
4868 case Intrinsic::floor:
4869 case Intrinsic::ceil:
4870 case Intrinsic::trunc:
4871 case Intrinsic::rint:
4872 case Intrinsic::nearbyint: {
4874 switch (Intrinsic) {
4875 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4876 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4877 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4878 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4879 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4880 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4881 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4882 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4883 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4884 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4887 setValue(&I, DAG.getNode(Opcode, dl,
4888 getValue(I.getArgOperand(0)).getValueType(),
4889 getValue(I.getArgOperand(0))));
4892 case Intrinsic::fma:
4893 setValue(&I, DAG.getNode(ISD::FMA, dl,
4894 getValue(I.getArgOperand(0)).getValueType(),
4895 getValue(I.getArgOperand(0)),
4896 getValue(I.getArgOperand(1)),
4897 getValue(I.getArgOperand(2))));
4899 case Intrinsic::fmuladd: {
4900 EVT VT = TLI.getValueType(I.getType());
4901 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4902 TLI.isOperationLegalOrCustom(ISD::FMA, VT) &&
4903 TLI.isFMAFasterThanMulAndAdd(VT)){
4904 setValue(&I, DAG.getNode(ISD::FMA, dl,
4905 getValue(I.getArgOperand(0)).getValueType(),
4906 getValue(I.getArgOperand(0)),
4907 getValue(I.getArgOperand(1)),
4908 getValue(I.getArgOperand(2))));
4910 SDValue Mul = DAG.getNode(ISD::FMUL, dl,
4911 getValue(I.getArgOperand(0)).getValueType(),
4912 getValue(I.getArgOperand(0)),
4913 getValue(I.getArgOperand(1)));
4914 SDValue Add = DAG.getNode(ISD::FADD, dl,
4915 getValue(I.getArgOperand(0)).getValueType(),
4917 getValue(I.getArgOperand(2)));
4922 case Intrinsic::convert_to_fp16:
4923 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4924 MVT::i16, getValue(I.getArgOperand(0))));
4926 case Intrinsic::convert_from_fp16:
4927 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4928 MVT::f32, getValue(I.getArgOperand(0))));
4930 case Intrinsic::pcmarker: {
4931 SDValue Tmp = getValue(I.getArgOperand(0));
4932 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4935 case Intrinsic::readcyclecounter: {
4936 SDValue Op = getRoot();
4937 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4938 DAG.getVTList(MVT::i64, MVT::Other),
4941 DAG.setRoot(Res.getValue(1));
4944 case Intrinsic::bswap:
4945 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4946 getValue(I.getArgOperand(0)).getValueType(),
4947 getValue(I.getArgOperand(0))));
4949 case Intrinsic::cttz: {
4950 SDValue Arg = getValue(I.getArgOperand(0));
4951 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4952 EVT Ty = Arg.getValueType();
4953 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4957 case Intrinsic::ctlz: {
4958 SDValue Arg = getValue(I.getArgOperand(0));
4959 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4960 EVT Ty = Arg.getValueType();
4961 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4965 case Intrinsic::ctpop: {
4966 SDValue Arg = getValue(I.getArgOperand(0));
4967 EVT Ty = Arg.getValueType();
4968 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4971 case Intrinsic::stacksave: {
4972 SDValue Op = getRoot();
4973 Res = DAG.getNode(ISD::STACKSAVE, dl,
4974 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4976 DAG.setRoot(Res.getValue(1));
4979 case Intrinsic::stackrestore: {
4980 Res = getValue(I.getArgOperand(0));
4981 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4984 case Intrinsic::stackprotector: {
4985 // Emit code into the DAG to store the stack guard onto the stack.
4986 MachineFunction &MF = DAG.getMachineFunction();
4987 MachineFrameInfo *MFI = MF.getFrameInfo();
4988 EVT PtrTy = TLI.getPointerTy();
4990 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4991 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4993 int FI = FuncInfo.StaticAllocaMap[Slot];
4994 MFI->setStackProtectorIndex(FI);
4996 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4998 // Store the stack protector onto the stack.
4999 Res = DAG.getStore(getRoot(), dl, Src, FIN,
5000 MachinePointerInfo::getFixedStack(FI),
5006 case Intrinsic::objectsize: {
5007 // If we don't know by now, we're never going to know.
5008 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5010 assert(CI && "Non-constant type in __builtin_object_size?");
5012 SDValue Arg = getValue(I.getCalledValue());
5013 EVT Ty = Arg.getValueType();
5016 Res = DAG.getConstant(-1ULL, Ty);
5018 Res = DAG.getConstant(0, Ty);
5023 case Intrinsic::var_annotation:
5024 // Discard annotate attributes
5027 case Intrinsic::init_trampoline: {
5028 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5032 Ops[1] = getValue(I.getArgOperand(0));
5033 Ops[2] = getValue(I.getArgOperand(1));
5034 Ops[3] = getValue(I.getArgOperand(2));
5035 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5036 Ops[5] = DAG.getSrcValue(F);
5038 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5043 case Intrinsic::adjust_trampoline: {
5044 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5046 getValue(I.getArgOperand(0))));
5049 case Intrinsic::gcroot:
5051 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5052 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5054 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5055 GFI->addStackRoot(FI->getIndex(), TypeMap);
5058 case Intrinsic::gcread:
5059 case Intrinsic::gcwrite:
5060 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5061 case Intrinsic::flt_rounds:
5062 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5065 case Intrinsic::expect: {
5066 // Just replace __builtin_expect(exp, c) with EXP.
5067 setValue(&I, getValue(I.getArgOperand(0)));
5071 case Intrinsic::debugtrap:
5072 case Intrinsic::trap: {
5073 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5074 if (TrapFuncName.empty()) {
5075 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5076 ISD::TRAP : ISD::DEBUGTRAP;
5077 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot()));
5080 TargetLowering::ArgListTy Args;
5082 CallLoweringInfo CLI(getRoot(), I.getType(),
5083 false, false, false, false, 0, CallingConv::C,
5084 /*isTailCall=*/false,
5085 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5086 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5088 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5089 DAG.setRoot(Result.second);
5093 case Intrinsic::uadd_with_overflow:
5094 case Intrinsic::sadd_with_overflow:
5095 case Intrinsic::usub_with_overflow:
5096 case Intrinsic::ssub_with_overflow:
5097 case Intrinsic::umul_with_overflow:
5098 case Intrinsic::smul_with_overflow: {
5100 switch (Intrinsic) {
5101 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5102 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5103 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5104 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5105 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5106 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5107 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5109 SDValue Op1 = getValue(I.getArgOperand(0));
5110 SDValue Op2 = getValue(I.getArgOperand(1));
5112 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5113 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2));
5116 case Intrinsic::prefetch: {
5118 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5120 Ops[1] = getValue(I.getArgOperand(0));
5121 Ops[2] = getValue(I.getArgOperand(1));
5122 Ops[3] = getValue(I.getArgOperand(2));
5123 Ops[4] = getValue(I.getArgOperand(3));
5124 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5125 DAG.getVTList(MVT::Other),
5127 EVT::getIntegerVT(*Context, 8),
5128 MachinePointerInfo(I.getArgOperand(0)),
5130 false, /* volatile */
5132 rw==1)); /* write */
5135 case Intrinsic::lifetime_start:
5136 case Intrinsic::lifetime_end: {
5137 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5138 // Stack coloring is not enabled in O0, discard region information.
5139 if (TM.getOptLevel() == CodeGenOpt::None)
5142 SmallVector<Value *, 4> Allocas;
5143 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5145 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(),
5146 E = Allocas.end(); Object != E; ++Object) {
5147 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5149 // Could not find an Alloca.
5150 if (!LifetimeObject)
5153 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5157 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5158 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5160 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2);
5164 case Intrinsic::invariant_start:
5165 // Discard region information.
5166 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5168 case Intrinsic::invariant_end:
5169 // Discard region information.
5171 case Intrinsic::donothing:
5177 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5179 MachineBasicBlock *LandingPad) {
5180 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5181 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5182 Type *RetTy = FTy->getReturnType();
5183 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5184 MCSymbol *BeginLabel = 0;
5186 TargetLowering::ArgListTy Args;
5187 TargetLowering::ArgListEntry Entry;
5188 Args.reserve(CS.arg_size());
5190 // Check whether the function can return without sret-demotion.
5191 SmallVector<ISD::OutputArg, 4> Outs;
5192 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5195 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5196 DAG.getMachineFunction(),
5197 FTy->isVarArg(), Outs,
5200 SDValue DemoteStackSlot;
5201 int DemoteStackIdx = -100;
5203 if (!CanLowerReturn) {
5204 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(
5205 FTy->getReturnType());
5206 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(
5207 FTy->getReturnType());
5208 MachineFunction &MF = DAG.getMachineFunction();
5209 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5210 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5212 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5213 Entry.Node = DemoteStackSlot;
5214 Entry.Ty = StackSlotPtrType;
5215 Entry.isSExt = false;
5216 Entry.isZExt = false;
5217 Entry.isInReg = false;
5218 Entry.isSRet = true;
5219 Entry.isNest = false;
5220 Entry.isByVal = false;
5221 Entry.Alignment = Align;
5222 Args.push_back(Entry);
5223 RetTy = Type::getVoidTy(FTy->getContext());
5226 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5228 const Value *V = *i;
5231 if (V->getType()->isEmptyTy())
5234 SDValue ArgNode = getValue(V);
5235 Entry.Node = ArgNode; Entry.Ty = V->getType();
5237 unsigned attrInd = i - CS.arg_begin() + 1;
5238 Entry.isSExt = CS.paramHasAttr(attrInd, Attributes::SExt);
5239 Entry.isZExt = CS.paramHasAttr(attrInd, Attributes::ZExt);
5240 Entry.isInReg = CS.paramHasAttr(attrInd, Attributes::InReg);
5241 Entry.isSRet = CS.paramHasAttr(attrInd, Attributes::StructRet);
5242 Entry.isNest = CS.paramHasAttr(attrInd, Attributes::Nest);
5243 Entry.isByVal = CS.paramHasAttr(attrInd, Attributes::ByVal);
5244 Entry.Alignment = CS.getParamAlignment(attrInd);
5245 Args.push_back(Entry);
5249 // Insert a label before the invoke call to mark the try range. This can be
5250 // used to detect deletion of the invoke via the MachineModuleInfo.
5251 BeginLabel = MMI.getContext().CreateTempSymbol();
5253 // For SjLj, keep track of which landing pads go with which invokes
5254 // so as to maintain the ordering of pads in the LSDA.
5255 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5256 if (CallSiteIndex) {
5257 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5258 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5260 // Now that the call site is handled, stop tracking it.
5261 MMI.setCurrentCallSite(0);
5264 // Both PendingLoads and PendingExports must be flushed here;
5265 // this call might not return.
5267 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5270 // Check if target-independent constraints permit a tail call here.
5271 // Target-dependent constraints are checked within TLI.LowerCallTo.
5273 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5277 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5278 getCurDebugLoc(), CS);
5279 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5280 assert((isTailCall || Result.second.getNode()) &&
5281 "Non-null chain expected with non-tail call!");
5282 assert((Result.second.getNode() || !Result.first.getNode()) &&
5283 "Null value expected with tail call!");
5284 if (Result.first.getNode()) {
5285 setValue(CS.getInstruction(), Result.first);
5286 } else if (!CanLowerReturn && Result.second.getNode()) {
5287 // The instruction result is the result of loading from the
5288 // hidden sret parameter.
5289 SmallVector<EVT, 1> PVTs;
5290 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5292 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5293 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5294 EVT PtrVT = PVTs[0];
5296 SmallVector<EVT, 4> RetTys;
5297 SmallVector<uint64_t, 4> Offsets;
5298 RetTy = FTy->getReturnType();
5299 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5301 unsigned NumValues = RetTys.size();
5302 SmallVector<SDValue, 4> Values(NumValues);
5303 SmallVector<SDValue, 4> Chains(NumValues);
5305 for (unsigned i = 0; i < NumValues; ++i) {
5306 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5308 DAG.getConstant(Offsets[i], PtrVT));
5309 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5310 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5311 false, false, false, 1);
5313 Chains[i] = L.getValue(1);
5316 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5317 MVT::Other, &Chains[0], NumValues);
5318 PendingLoads.push_back(Chain);
5320 setValue(CS.getInstruction(),
5321 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5322 DAG.getVTList(&RetTys[0], RetTys.size()),
5323 &Values[0], Values.size()));
5326 // Assign order to nodes here. If the call does not produce a result, it won't
5327 // be mapped to a SDNode and visit() will not assign it an order number.
5328 if (!Result.second.getNode()) {
5329 // As a special case, a null chain means that a tail call has been emitted and
5330 // the DAG root is already updated.
5333 AssignOrderingToNode(DAG.getRoot().getNode());
5335 DAG.setRoot(Result.second);
5337 AssignOrderingToNode(Result.second.getNode());
5341 // Insert a label at the end of the invoke call to mark the try range. This
5342 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5343 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5344 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5346 // Inform MachineModuleInfo of range.
5347 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5351 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5352 /// value is equal or not-equal to zero.
5353 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5354 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5356 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5357 if (IC->isEquality())
5358 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5359 if (C->isNullValue())
5361 // Unknown instruction.
5367 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5369 SelectionDAGBuilder &Builder) {
5371 // Check to see if this load can be trivially constant folded, e.g. if the
5372 // input is from a string literal.
5373 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5374 // Cast pointer to the type we really want to load.
5375 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5376 PointerType::getUnqual(LoadTy));
5378 if (const Constant *LoadCst =
5379 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5381 return Builder.getValue(LoadCst);
5384 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5385 // still constant memory, the input chain can be the entry node.
5387 bool ConstantMemory = false;
5389 // Do not serialize (non-volatile) loads of constant memory with anything.
5390 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5391 Root = Builder.DAG.getEntryNode();
5392 ConstantMemory = true;
5394 // Do not serialize non-volatile loads against each other.
5395 Root = Builder.DAG.getRoot();
5398 SDValue Ptr = Builder.getValue(PtrVal);
5399 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5400 Ptr, MachinePointerInfo(PtrVal),
5402 false /*nontemporal*/,
5403 false /*isinvariant*/, 1 /* align=1 */);
5405 if (!ConstantMemory)
5406 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5411 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5412 /// If so, return true and lower it, otherwise return false and it will be
5413 /// lowered like a normal call.
5414 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5415 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5416 if (I.getNumArgOperands() != 3)
5419 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5420 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5421 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5422 !I.getType()->isIntegerTy())
5425 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5427 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5428 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5429 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5430 bool ActuallyDoIt = true;
5433 switch (Size->getZExtValue()) {
5435 LoadVT = MVT::Other;
5437 ActuallyDoIt = false;
5441 LoadTy = Type::getInt16Ty(Size->getContext());
5445 LoadTy = Type::getInt32Ty(Size->getContext());
5449 LoadTy = Type::getInt64Ty(Size->getContext());
5453 LoadVT = MVT::v4i32;
5454 LoadTy = Type::getInt32Ty(Size->getContext());
5455 LoadTy = VectorType::get(LoadTy, 4);
5460 // This turns into unaligned loads. We only do this if the target natively
5461 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5462 // we'll only produce a small number of byte loads.
5464 // Require that we can find a legal MVT, and only do this if the target
5465 // supports unaligned loads of that type. Expanding into byte loads would
5467 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5468 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5469 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5470 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5471 ActuallyDoIt = false;
5475 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5476 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5478 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5480 EVT CallVT = TLI.getValueType(I.getType(), true);
5481 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5490 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5491 /// operation (as expected), translate it to an SDNode with the specified opcode
5492 /// and return true.
5493 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5495 // Sanity check that it really is a unary floating-point call.
5496 if (I.getNumArgOperands() != 1 ||
5497 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5498 I.getType() != I.getArgOperand(0)->getType() ||
5499 !I.onlyReadsMemory())
5502 SDValue Tmp = getValue(I.getArgOperand(0));
5503 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
5507 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5508 // Handle inline assembly differently.
5509 if (isa<InlineAsm>(I.getCalledValue())) {
5514 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5515 ComputeUsesVAFloatArgument(I, &MMI);
5517 const char *RenameFn = 0;
5518 if (Function *F = I.getCalledFunction()) {
5519 if (F->isDeclaration()) {
5520 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5521 if (unsigned IID = II->getIntrinsicID(F)) {
5522 RenameFn = visitIntrinsicCall(I, IID);
5527 if (unsigned IID = F->getIntrinsicID()) {
5528 RenameFn = visitIntrinsicCall(I, IID);
5534 // Check for well-known libc/libm calls. If the function is internal, it
5535 // can't be a library call.
5537 if (!F->hasLocalLinkage() && F->hasName() &&
5538 LibInfo->getLibFunc(F->getName(), Func) &&
5539 LibInfo->hasOptimizedCodeGen(Func)) {
5542 case LibFunc::copysign:
5543 case LibFunc::copysignf:
5544 case LibFunc::copysignl:
5545 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5546 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5547 I.getType() == I.getArgOperand(0)->getType() &&
5548 I.getType() == I.getArgOperand(1)->getType() &&
5549 I.onlyReadsMemory()) {
5550 SDValue LHS = getValue(I.getArgOperand(0));
5551 SDValue RHS = getValue(I.getArgOperand(1));
5552 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5553 LHS.getValueType(), LHS, RHS));
5558 case LibFunc::fabsf:
5559 case LibFunc::fabsl:
5560 if (visitUnaryFloatCall(I, ISD::FABS))
5566 if (visitUnaryFloatCall(I, ISD::FSIN))
5572 if (visitUnaryFloatCall(I, ISD::FCOS))
5576 case LibFunc::sqrtf:
5577 case LibFunc::sqrtl:
5578 if (visitUnaryFloatCall(I, ISD::FSQRT))
5581 case LibFunc::floor:
5582 case LibFunc::floorf:
5583 case LibFunc::floorl:
5584 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5587 case LibFunc::nearbyint:
5588 case LibFunc::nearbyintf:
5589 case LibFunc::nearbyintl:
5590 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5594 case LibFunc::ceilf:
5595 case LibFunc::ceill:
5596 if (visitUnaryFloatCall(I, ISD::FCEIL))
5600 case LibFunc::rintf:
5601 case LibFunc::rintl:
5602 if (visitUnaryFloatCall(I, ISD::FRINT))
5605 case LibFunc::trunc:
5606 case LibFunc::truncf:
5607 case LibFunc::truncl:
5608 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5612 case LibFunc::log2f:
5613 case LibFunc::log2l:
5614 if (visitUnaryFloatCall(I, ISD::FLOG2))
5618 case LibFunc::exp2f:
5619 case LibFunc::exp2l:
5620 if (visitUnaryFloatCall(I, ISD::FEXP2))
5623 case LibFunc::memcmp:
5624 if (visitMemCmpCall(I))
5633 Callee = getValue(I.getCalledValue());
5635 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5637 // Check if we can potentially perform a tail call. More detailed checking is
5638 // be done within LowerCallTo, after more information about the call is known.
5639 LowerCallTo(&I, Callee, I.isTailCall());
5644 /// AsmOperandInfo - This contains information for each constraint that we are
5646 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5648 /// CallOperand - If this is the result output operand or a clobber
5649 /// this is null, otherwise it is the incoming operand to the CallInst.
5650 /// This gets modified as the asm is processed.
5651 SDValue CallOperand;
5653 /// AssignedRegs - If this is a register or register class operand, this
5654 /// contains the set of register corresponding to the operand.
5655 RegsForValue AssignedRegs;
5657 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5658 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5661 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5662 /// corresponds to. If there is no Value* for this operand, it returns
5664 EVT getCallOperandValEVT(LLVMContext &Context,
5665 const TargetLowering &TLI,
5666 const DataLayout *TD) const {
5667 if (CallOperandVal == 0) return MVT::Other;
5669 if (isa<BasicBlock>(CallOperandVal))
5670 return TLI.getPointerTy();
5672 llvm::Type *OpTy = CallOperandVal->getType();
5674 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5675 // If this is an indirect operand, the operand is a pointer to the
5678 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5680 report_fatal_error("Indirect operand for inline asm not a pointer!");
5681 OpTy = PtrTy->getElementType();
5684 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5685 if (StructType *STy = dyn_cast<StructType>(OpTy))
5686 if (STy->getNumElements() == 1)
5687 OpTy = STy->getElementType(0);
5689 // If OpTy is not a single value, it may be a struct/union that we
5690 // can tile with integers.
5691 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5692 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5701 OpTy = IntegerType::get(Context, BitSize);
5706 return TLI.getValueType(OpTy, true);
5710 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5712 } // end anonymous namespace
5714 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5715 /// specified operand. We prefer to assign virtual registers, to allow the
5716 /// register allocator to handle the assignment process. However, if the asm
5717 /// uses features that we can't model on machineinstrs, we have SDISel do the
5718 /// allocation. This produces generally horrible, but correct, code.
5720 /// OpInfo describes the operand.
5722 static void GetRegistersForValue(SelectionDAG &DAG,
5723 const TargetLowering &TLI,
5725 SDISelAsmOperandInfo &OpInfo) {
5726 LLVMContext &Context = *DAG.getContext();
5728 MachineFunction &MF = DAG.getMachineFunction();
5729 SmallVector<unsigned, 4> Regs;
5731 // If this is a constraint for a single physreg, or a constraint for a
5732 // register class, find it.
5733 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5734 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5735 OpInfo.ConstraintVT);
5737 unsigned NumRegs = 1;
5738 if (OpInfo.ConstraintVT != MVT::Other) {
5739 // If this is a FP input in an integer register (or visa versa) insert a bit
5740 // cast of the input value. More generally, handle any case where the input
5741 // value disagrees with the register class we plan to stick this in.
5742 if (OpInfo.Type == InlineAsm::isInput &&
5743 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5744 // Try to convert to the first EVT that the reg class contains. If the
5745 // types are identical size, use a bitcast to convert (e.g. two differing
5747 EVT RegVT = *PhysReg.second->vt_begin();
5748 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5749 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5750 RegVT, OpInfo.CallOperand);
5751 OpInfo.ConstraintVT = RegVT;
5752 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5753 // If the input is a FP value and we want it in FP registers, do a
5754 // bitcast to the corresponding integer type. This turns an f64 value
5755 // into i64, which can be passed with two i32 values on a 32-bit
5757 RegVT = EVT::getIntegerVT(Context,
5758 OpInfo.ConstraintVT.getSizeInBits());
5759 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5760 RegVT, OpInfo.CallOperand);
5761 OpInfo.ConstraintVT = RegVT;
5765 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5769 EVT ValueVT = OpInfo.ConstraintVT;
5771 // If this is a constraint for a specific physical register, like {r17},
5773 if (unsigned AssignedReg = PhysReg.first) {
5774 const TargetRegisterClass *RC = PhysReg.second;
5775 if (OpInfo.ConstraintVT == MVT::Other)
5776 ValueVT = *RC->vt_begin();
5778 // Get the actual register value type. This is important, because the user
5779 // may have asked for (e.g.) the AX register in i32 type. We need to
5780 // remember that AX is actually i16 to get the right extension.
5781 RegVT = *RC->vt_begin();
5783 // This is a explicit reference to a physical register.
5784 Regs.push_back(AssignedReg);
5786 // If this is an expanded reference, add the rest of the regs to Regs.
5788 TargetRegisterClass::iterator I = RC->begin();
5789 for (; *I != AssignedReg; ++I)
5790 assert(I != RC->end() && "Didn't find reg!");
5792 // Already added the first reg.
5794 for (; NumRegs; --NumRegs, ++I) {
5795 assert(I != RC->end() && "Ran out of registers to allocate!");
5800 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5804 // Otherwise, if this was a reference to an LLVM register class, create vregs
5805 // for this reference.
5806 if (const TargetRegisterClass *RC = PhysReg.second) {
5807 RegVT = *RC->vt_begin();
5808 if (OpInfo.ConstraintVT == MVT::Other)
5811 // Create the appropriate number of virtual registers.
5812 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5813 for (; NumRegs; --NumRegs)
5814 Regs.push_back(RegInfo.createVirtualRegister(RC));
5816 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5820 // Otherwise, we couldn't allocate enough registers for this.
5823 /// visitInlineAsm - Handle a call to an InlineAsm object.
5825 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5826 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5828 /// ConstraintOperands - Information about all of the constraints.
5829 SDISelAsmOperandInfoVector ConstraintOperands;
5831 TargetLowering::AsmOperandInfoVector
5832 TargetConstraints = TLI.ParseConstraints(CS);
5834 bool hasMemory = false;
5836 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5837 unsigned ResNo = 0; // ResNo - The result number of the next output.
5838 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5839 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5840 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5842 EVT OpVT = MVT::Other;
5844 // Compute the value type for each operand.
5845 switch (OpInfo.Type) {
5846 case InlineAsm::isOutput:
5847 // Indirect outputs just consume an argument.
5848 if (OpInfo.isIndirect) {
5849 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5853 // The return value of the call is this value. As such, there is no
5854 // corresponding argument.
5855 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5856 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5857 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5859 assert(ResNo == 0 && "Asm only has one result!");
5860 OpVT = TLI.getValueType(CS.getType());
5864 case InlineAsm::isInput:
5865 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5867 case InlineAsm::isClobber:
5872 // If this is an input or an indirect output, process the call argument.
5873 // BasicBlocks are labels, currently appearing only in asm's.
5874 if (OpInfo.CallOperandVal) {
5875 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5876 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5878 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5881 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5884 OpInfo.ConstraintVT = OpVT;
5886 // Indirect operand accesses access memory.
5887 if (OpInfo.isIndirect)
5890 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5891 TargetLowering::ConstraintType
5892 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5893 if (CType == TargetLowering::C_Memory) {
5901 SDValue Chain, Flag;
5903 // We won't need to flush pending loads if this asm doesn't touch
5904 // memory and is nonvolatile.
5905 if (hasMemory || IA->hasSideEffects())
5908 Chain = DAG.getRoot();
5910 // Second pass over the constraints: compute which constraint option to use
5911 // and assign registers to constraints that want a specific physreg.
5912 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5913 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5915 // If this is an output operand with a matching input operand, look up the
5916 // matching input. If their types mismatch, e.g. one is an integer, the
5917 // other is floating point, or their sizes are different, flag it as an
5919 if (OpInfo.hasMatchingInput()) {
5920 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5922 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5923 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5924 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5925 OpInfo.ConstraintVT);
5926 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5927 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5928 Input.ConstraintVT);
5929 if ((OpInfo.ConstraintVT.isInteger() !=
5930 Input.ConstraintVT.isInteger()) ||
5931 (MatchRC.second != InputRC.second)) {
5932 report_fatal_error("Unsupported asm: input constraint"
5933 " with a matching output constraint of"
5934 " incompatible type!");
5936 Input.ConstraintVT = OpInfo.ConstraintVT;
5940 // Compute the constraint code and ConstraintType to use.
5941 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5943 // If this is a memory input, and if the operand is not indirect, do what we
5944 // need to to provide an address for the memory input.
5945 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5946 !OpInfo.isIndirect) {
5947 assert((OpInfo.isMultipleAlternative ||
5948 (OpInfo.Type == InlineAsm::isInput)) &&
5949 "Can only indirectify direct input operands!");
5951 // Memory operands really want the address of the value. If we don't have
5952 // an indirect input, put it in the constpool if we can, otherwise spill
5953 // it to a stack slot.
5954 // TODO: This isn't quite right. We need to handle these according to
5955 // the addressing mode that the constraint wants. Also, this may take
5956 // an additional register for the computation and we don't want that
5959 // If the operand is a float, integer, or vector constant, spill to a
5960 // constant pool entry to get its address.
5961 const Value *OpVal = OpInfo.CallOperandVal;
5962 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5963 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5964 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5965 TLI.getPointerTy());
5967 // Otherwise, create a stack slot and emit a store to it before the
5969 Type *Ty = OpVal->getType();
5970 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5971 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5972 MachineFunction &MF = DAG.getMachineFunction();
5973 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5974 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5975 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5976 OpInfo.CallOperand, StackSlot,
5977 MachinePointerInfo::getFixedStack(SSFI),
5979 OpInfo.CallOperand = StackSlot;
5982 // There is no longer a Value* corresponding to this operand.
5983 OpInfo.CallOperandVal = 0;
5985 // It is now an indirect operand.
5986 OpInfo.isIndirect = true;
5989 // If this constraint is for a specific register, allocate it before
5991 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5992 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
5995 // Second pass - Loop over all of the operands, assigning virtual or physregs
5996 // to register class operands.
5997 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5998 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6000 // C_Register operands have already been allocated, Other/Memory don't need
6002 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6003 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6006 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6007 std::vector<SDValue> AsmNodeOperands;
6008 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6009 AsmNodeOperands.push_back(
6010 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6011 TLI.getPointerTy()));
6013 // If we have a !srcloc metadata node associated with it, we want to attach
6014 // this to the ultimately generated inline asm machineinstr. To do this, we
6015 // pass in the third operand as this (potentially null) inline asm MDNode.
6016 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6017 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6019 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6020 // bits as operand 3.
6021 unsigned ExtraInfo = 0;
6022 if (IA->hasSideEffects())
6023 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6024 if (IA->isAlignStack())
6025 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6026 // Set the asm dialect.
6027 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6029 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6030 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6031 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6033 // Compute the constraint code and ConstraintType to use.
6034 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6036 // Ideally, we would only check against memory constraints. However, the
6037 // meaning of an other constraint can be target-specific and we can't easily
6038 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6039 // for other constriants as well.
6040 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6041 OpInfo.ConstraintType == TargetLowering::C_Other) {
6042 if (OpInfo.Type == InlineAsm::isInput)
6043 ExtraInfo |= InlineAsm::Extra_MayLoad;
6044 else if (OpInfo.Type == InlineAsm::isOutput)
6045 ExtraInfo |= InlineAsm::Extra_MayStore;
6049 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6050 TLI.getPointerTy()));
6052 // Loop over all of the inputs, copying the operand values into the
6053 // appropriate registers and processing the output regs.
6054 RegsForValue RetValRegs;
6056 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6057 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6059 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6060 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6062 switch (OpInfo.Type) {
6063 case InlineAsm::isOutput: {
6064 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6065 OpInfo.ConstraintType != TargetLowering::C_Register) {
6066 // Memory output, or 'other' output (e.g. 'X' constraint).
6067 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6069 // Add information to the INLINEASM node to know about this output.
6070 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6071 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6072 TLI.getPointerTy()));
6073 AsmNodeOperands.push_back(OpInfo.CallOperand);
6077 // Otherwise, this is a register or register class output.
6079 // Copy the output from the appropriate register. Find a register that
6081 if (OpInfo.AssignedRegs.Regs.empty()) {
6082 LLVMContext &Ctx = *DAG.getContext();
6083 Ctx.emitError(CS.getInstruction(),
6084 "couldn't allocate output register for constraint '" +
6085 Twine(OpInfo.ConstraintCode) + "'");
6089 // If this is an indirect operand, store through the pointer after the
6091 if (OpInfo.isIndirect) {
6092 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6093 OpInfo.CallOperandVal));
6095 // This is the result value of the call.
6096 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6097 // Concatenate this output onto the outputs list.
6098 RetValRegs.append(OpInfo.AssignedRegs);
6101 // Add information to the INLINEASM node to know that this register is
6103 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6104 InlineAsm::Kind_RegDefEarlyClobber :
6105 InlineAsm::Kind_RegDef,
6112 case InlineAsm::isInput: {
6113 SDValue InOperandVal = OpInfo.CallOperand;
6115 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6116 // If this is required to match an output register we have already set,
6117 // just use its register.
6118 unsigned OperandNo = OpInfo.getMatchedOperand();
6120 // Scan until we find the definition we already emitted of this operand.
6121 // When we find it, create a RegsForValue operand.
6122 unsigned CurOp = InlineAsm::Op_FirstOperand;
6123 for (; OperandNo; --OperandNo) {
6124 // Advance to the next operand.
6126 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6127 assert((InlineAsm::isRegDefKind(OpFlag) ||
6128 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6129 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6130 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6134 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6135 if (InlineAsm::isRegDefKind(OpFlag) ||
6136 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6137 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6138 if (OpInfo.isIndirect) {
6139 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6140 LLVMContext &Ctx = *DAG.getContext();
6141 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6142 " don't know how to handle tied "
6143 "indirect register inputs");
6146 RegsForValue MatchedRegs;
6147 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6148 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6149 MatchedRegs.RegVTs.push_back(RegVT);
6150 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6151 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6153 MatchedRegs.Regs.push_back
6154 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6156 // Use the produced MatchedRegs object to
6157 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6158 Chain, &Flag, CS.getInstruction());
6159 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6160 true, OpInfo.getMatchedOperand(),
6161 DAG, AsmNodeOperands);
6165 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6166 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6167 "Unexpected number of operands");
6168 // Add information to the INLINEASM node to know about this input.
6169 // See InlineAsm.h isUseOperandTiedToDef.
6170 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6171 OpInfo.getMatchedOperand());
6172 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6173 TLI.getPointerTy()));
6174 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6178 // Treat indirect 'X' constraint as memory.
6179 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6181 OpInfo.ConstraintType = TargetLowering::C_Memory;
6183 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6184 std::vector<SDValue> Ops;
6185 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6188 LLVMContext &Ctx = *DAG.getContext();
6189 Ctx.emitError(CS.getInstruction(),
6190 "invalid operand for inline asm constraint '" +
6191 Twine(OpInfo.ConstraintCode) + "'");
6195 // Add information to the INLINEASM node to know about this input.
6196 unsigned ResOpType =
6197 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6198 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6199 TLI.getPointerTy()));
6200 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6204 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6205 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6206 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6207 "Memory operands expect pointer values");
6209 // Add information to the INLINEASM node to know about this input.
6210 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6211 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6212 TLI.getPointerTy()));
6213 AsmNodeOperands.push_back(InOperandVal);
6217 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6218 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6219 "Unknown constraint type!");
6221 // TODO: Support this.
6222 if (OpInfo.isIndirect) {
6223 LLVMContext &Ctx = *DAG.getContext();
6224 Ctx.emitError(CS.getInstruction(),
6225 "Don't know how to handle indirect register inputs yet "
6226 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6230 // Copy the input into the appropriate registers.
6231 if (OpInfo.AssignedRegs.Regs.empty()) {
6232 LLVMContext &Ctx = *DAG.getContext();
6233 Ctx.emitError(CS.getInstruction(),
6234 "couldn't allocate input reg for constraint '" +
6235 Twine(OpInfo.ConstraintCode) + "'");
6239 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6240 Chain, &Flag, CS.getInstruction());
6242 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6243 DAG, AsmNodeOperands);
6246 case InlineAsm::isClobber: {
6247 // Add the clobbered value to the operand list, so that the register
6248 // allocator is aware that the physreg got clobbered.
6249 if (!OpInfo.AssignedRegs.Regs.empty())
6250 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6258 // Finish up input operands. Set the input chain and add the flag last.
6259 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6260 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6262 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6263 DAG.getVTList(MVT::Other, MVT::Glue),
6264 &AsmNodeOperands[0], AsmNodeOperands.size());
6265 Flag = Chain.getValue(1);
6267 // If this asm returns a register value, copy the result from that register
6268 // and set it as the value of the call.
6269 if (!RetValRegs.Regs.empty()) {
6270 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6271 Chain, &Flag, CS.getInstruction());
6273 // FIXME: Why don't we do this for inline asms with MRVs?
6274 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6275 EVT ResultType = TLI.getValueType(CS.getType());
6277 // If any of the results of the inline asm is a vector, it may have the
6278 // wrong width/num elts. This can happen for register classes that can
6279 // contain multiple different value types. The preg or vreg allocated may
6280 // not have the same VT as was expected. Convert it to the right type
6281 // with bit_convert.
6282 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6283 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6286 } else if (ResultType != Val.getValueType() &&
6287 ResultType.isInteger() && Val.getValueType().isInteger()) {
6288 // If a result value was tied to an input value, the computed result may
6289 // have a wider width than the expected result. Extract the relevant
6291 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6294 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6297 setValue(CS.getInstruction(), Val);
6298 // Don't need to use this as a chain in this case.
6299 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6303 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6305 // Process indirect outputs, first output all of the flagged copies out of
6307 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6308 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6309 const Value *Ptr = IndirectStoresToEmit[i].second;
6310 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6312 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6315 // Emit the non-flagged stores from the physregs.
6316 SmallVector<SDValue, 8> OutChains;
6317 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6318 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6319 StoresToEmit[i].first,
6320 getValue(StoresToEmit[i].second),
6321 MachinePointerInfo(StoresToEmit[i].second),
6323 OutChains.push_back(Val);
6326 if (!OutChains.empty())
6327 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6328 &OutChains[0], OutChains.size());
6333 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6334 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6335 MVT::Other, getRoot(),
6336 getValue(I.getArgOperand(0)),
6337 DAG.getSrcValue(I.getArgOperand(0))));
6340 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6341 const DataLayout &TD = *TLI.getDataLayout();
6342 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6343 getRoot(), getValue(I.getOperand(0)),
6344 DAG.getSrcValue(I.getOperand(0)),
6345 TD.getABITypeAlignment(I.getType()));
6347 DAG.setRoot(V.getValue(1));
6350 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6351 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6352 MVT::Other, getRoot(),
6353 getValue(I.getArgOperand(0)),
6354 DAG.getSrcValue(I.getArgOperand(0))));
6357 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6358 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6359 MVT::Other, getRoot(),
6360 getValue(I.getArgOperand(0)),
6361 getValue(I.getArgOperand(1)),
6362 DAG.getSrcValue(I.getArgOperand(0)),
6363 DAG.getSrcValue(I.getArgOperand(1))));
6366 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6367 /// implementation, which just calls LowerCall.
6368 /// FIXME: When all targets are
6369 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6370 std::pair<SDValue, SDValue>
6371 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6372 // Handle all of the outgoing arguments.
6374 CLI.OutVals.clear();
6375 ArgListTy &Args = CLI.Args;
6376 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6377 SmallVector<EVT, 4> ValueVTs;
6378 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6379 for (unsigned Value = 0, NumValues = ValueVTs.size();
6380 Value != NumValues; ++Value) {
6381 EVT VT = ValueVTs[Value];
6382 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6383 SDValue Op = SDValue(Args[i].Node.getNode(),
6384 Args[i].Node.getResNo() + Value);
6385 ISD::ArgFlagsTy Flags;
6386 unsigned OriginalAlignment =
6387 getDataLayout()->getABITypeAlignment(ArgTy);
6393 if (Args[i].isInReg)
6397 if (Args[i].isByVal) {
6399 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6400 Type *ElementTy = Ty->getElementType();
6401 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6402 // For ByVal, alignment should come from FE. BE will guess if this
6403 // info is not there but there are cases it cannot get right.
6404 unsigned FrameAlign;
6405 if (Args[i].Alignment)
6406 FrameAlign = Args[i].Alignment;
6408 FrameAlign = getByValTypeAlignment(ElementTy);
6409 Flags.setByValAlign(FrameAlign);
6413 Flags.setOrigAlign(OriginalAlignment);
6415 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6416 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6417 SmallVector<SDValue, 4> Parts(NumParts);
6418 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6421 ExtendKind = ISD::SIGN_EXTEND;
6422 else if (Args[i].isZExt)
6423 ExtendKind = ISD::ZERO_EXTEND;
6425 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6426 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6428 for (unsigned j = 0; j != NumParts; ++j) {
6429 // if it isn't first piece, alignment must be 1
6430 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6431 i < CLI.NumFixedArgs,
6432 i, j*Parts[j].getValueType().getStoreSize());
6433 if (NumParts > 1 && j == 0)
6434 MyFlags.Flags.setSplit();
6436 MyFlags.Flags.setOrigAlign(1);
6438 CLI.Outs.push_back(MyFlags);
6439 CLI.OutVals.push_back(Parts[j]);
6444 // Handle the incoming return values from the call.
6446 SmallVector<EVT, 4> RetTys;
6447 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6448 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6450 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6451 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6452 for (unsigned i = 0; i != NumRegs; ++i) {
6453 ISD::InputArg MyFlags;
6454 MyFlags.VT = RegisterVT.getSimpleVT();
6455 MyFlags.Used = CLI.IsReturnValueUsed;
6457 MyFlags.Flags.setSExt();
6459 MyFlags.Flags.setZExt();
6461 MyFlags.Flags.setInReg();
6462 CLI.Ins.push_back(MyFlags);
6466 SmallVector<SDValue, 4> InVals;
6467 CLI.Chain = LowerCall(CLI, InVals);
6469 // Verify that the target's LowerCall behaved as expected.
6470 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6471 "LowerCall didn't return a valid chain!");
6472 assert((!CLI.IsTailCall || InVals.empty()) &&
6473 "LowerCall emitted a return value for a tail call!");
6474 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6475 "LowerCall didn't emit the correct number of values!");
6477 // For a tail call, the return value is merely live-out and there aren't
6478 // any nodes in the DAG representing it. Return a special value to
6479 // indicate that a tail call has been emitted and no more Instructions
6480 // should be processed in the current block.
6481 if (CLI.IsTailCall) {
6482 CLI.DAG.setRoot(CLI.Chain);
6483 return std::make_pair(SDValue(), SDValue());
6486 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6487 assert(InVals[i].getNode() &&
6488 "LowerCall emitted a null value!");
6489 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6490 "LowerCall emitted a value with the wrong type!");
6493 // Collect the legal value parts into potentially illegal values
6494 // that correspond to the original function's return values.
6495 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6497 AssertOp = ISD::AssertSext;
6498 else if (CLI.RetZExt)
6499 AssertOp = ISD::AssertZext;
6500 SmallVector<SDValue, 4> ReturnValues;
6501 unsigned CurReg = 0;
6502 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6504 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6505 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6507 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6508 NumRegs, RegisterVT, VT, NULL,
6513 // For a function returning void, there is no return value. We can't create
6514 // such a node, so we just return a null return value in that case. In
6515 // that case, nothing will actually look at the value.
6516 if (ReturnValues.empty())
6517 return std::make_pair(SDValue(), CLI.Chain);
6519 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6520 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6521 &ReturnValues[0], ReturnValues.size());
6522 return std::make_pair(Res, CLI.Chain);
6525 void TargetLowering::LowerOperationWrapper(SDNode *N,
6526 SmallVectorImpl<SDValue> &Results,
6527 SelectionDAG &DAG) const {
6528 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6530 Results.push_back(Res);
6533 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6534 llvm_unreachable("LowerOperation not implemented for this target!");
6538 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6539 SDValue Op = getNonRegisterValue(V);
6540 assert((Op.getOpcode() != ISD::CopyFromReg ||
6541 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6542 "Copy from a reg to the same reg!");
6543 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6545 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6546 SDValue Chain = DAG.getEntryNode();
6547 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V);
6548 PendingExports.push_back(Chain);
6551 #include "llvm/CodeGen/SelectionDAGISel.h"
6553 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6554 /// entry block, return true. This includes arguments used by switches, since
6555 /// the switch may expand into multiple basic blocks.
6556 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6557 // With FastISel active, we may be splitting blocks, so force creation
6558 // of virtual registers for all non-dead arguments.
6560 return A->use_empty();
6562 const BasicBlock *Entry = A->getParent()->begin();
6563 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6565 const User *U = *UI;
6566 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6567 return false; // Use not in entry block.
6572 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6573 // If this is the entry block, emit arguments.
6574 const Function &F = *LLVMBB->getParent();
6575 SelectionDAG &DAG = SDB->DAG;
6576 DebugLoc dl = SDB->getCurDebugLoc();
6577 const DataLayout *TD = TLI.getDataLayout();
6578 SmallVector<ISD::InputArg, 16> Ins;
6580 // Check whether the function can return without sret-demotion.
6581 SmallVector<ISD::OutputArg, 4> Outs;
6582 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6585 if (!FuncInfo->CanLowerReturn) {
6586 // Put in an sret pointer parameter before all the other parameters.
6587 SmallVector<EVT, 1> ValueVTs;
6588 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6590 // NOTE: Assuming that a pointer will never break down to more than one VT
6592 ISD::ArgFlagsTy Flags;
6594 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6595 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6596 Ins.push_back(RetArg);
6599 // Set up the incoming argument description vector.
6601 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6602 I != E; ++I, ++Idx) {
6603 SmallVector<EVT, 4> ValueVTs;
6604 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6605 bool isArgValueUsed = !I->use_empty();
6606 for (unsigned Value = 0, NumValues = ValueVTs.size();
6607 Value != NumValues; ++Value) {
6608 EVT VT = ValueVTs[Value];
6609 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6610 ISD::ArgFlagsTy Flags;
6611 unsigned OriginalAlignment =
6612 TD->getABITypeAlignment(ArgTy);
6614 if (F.getParamAttributes(Idx).hasAttribute(Attributes::ZExt))
6616 if (F.getParamAttributes(Idx).hasAttribute(Attributes::SExt))
6618 if (F.getParamAttributes(Idx).hasAttribute(Attributes::InReg))
6620 if (F.getParamAttributes(Idx).hasAttribute(Attributes::StructRet))
6622 if (F.getParamAttributes(Idx).hasAttribute(Attributes::ByVal)) {
6624 PointerType *Ty = cast<PointerType>(I->getType());
6625 Type *ElementTy = Ty->getElementType();
6626 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6627 // For ByVal, alignment should be passed from FE. BE will guess if
6628 // this info is not there but there are cases it cannot get right.
6629 unsigned FrameAlign;
6630 if (F.getParamAlignment(Idx))
6631 FrameAlign = F.getParamAlignment(Idx);
6633 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6634 Flags.setByValAlign(FrameAlign);
6636 if (F.getParamAttributes(Idx).hasAttribute(Attributes::Nest))
6638 Flags.setOrigAlign(OriginalAlignment);
6640 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6641 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6642 for (unsigned i = 0; i != NumRegs; ++i) {
6643 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6644 Idx-1, i*RegisterVT.getStoreSize());
6645 if (NumRegs > 1 && i == 0)
6646 MyFlags.Flags.setSplit();
6647 // if it isn't first piece, alignment must be 1
6649 MyFlags.Flags.setOrigAlign(1);
6650 Ins.push_back(MyFlags);
6655 // Call the target to set up the argument values.
6656 SmallVector<SDValue, 8> InVals;
6657 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6661 // Verify that the target's LowerFormalArguments behaved as expected.
6662 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6663 "LowerFormalArguments didn't return a valid chain!");
6664 assert(InVals.size() == Ins.size() &&
6665 "LowerFormalArguments didn't emit the correct number of values!");
6667 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6668 assert(InVals[i].getNode() &&
6669 "LowerFormalArguments emitted a null value!");
6670 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6671 "LowerFormalArguments emitted a value with the wrong type!");
6675 // Update the DAG with the new chain value resulting from argument lowering.
6676 DAG.setRoot(NewRoot);
6678 // Set up the argument values.
6681 if (!FuncInfo->CanLowerReturn) {
6682 // Create a virtual register for the sret pointer, and put in a copy
6683 // from the sret argument into it.
6684 SmallVector<EVT, 1> ValueVTs;
6685 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6686 MVT VT = ValueVTs[0].getSimpleVT();
6687 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT).getSimpleVT();
6688 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6689 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6690 RegVT, VT, NULL, AssertOp);
6692 MachineFunction& MF = SDB->DAG.getMachineFunction();
6693 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6694 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6695 FuncInfo->DemoteRegister = SRetReg;
6696 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6698 DAG.setRoot(NewRoot);
6700 // i indexes lowered arguments. Bump it past the hidden sret argument.
6701 // Idx indexes LLVM arguments. Don't touch it.
6705 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6707 SmallVector<SDValue, 4> ArgValues;
6708 SmallVector<EVT, 4> ValueVTs;
6709 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6710 unsigned NumValues = ValueVTs.size();
6712 // If this argument is unused then remember its value. It is used to generate
6713 // debugging information.
6714 if (I->use_empty() && NumValues)
6715 SDB->setUnusedArgValue(I, InVals[i]);
6717 for (unsigned Val = 0; Val != NumValues; ++Val) {
6718 EVT VT = ValueVTs[Val];
6719 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6720 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6722 if (!I->use_empty()) {
6723 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6724 if (F.getParamAttributes(Idx).hasAttribute(Attributes::SExt))
6725 AssertOp = ISD::AssertSext;
6726 else if (F.getParamAttributes(Idx).hasAttribute(Attributes::ZExt))
6727 AssertOp = ISD::AssertZext;
6729 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6730 NumParts, PartVT, VT,
6737 // We don't need to do anything else for unused arguments.
6738 if (ArgValues.empty())
6741 // Note down frame index.
6742 if (FrameIndexSDNode *FI =
6743 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6744 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6746 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6747 SDB->getCurDebugLoc());
6749 SDB->setValue(I, Res);
6750 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6751 if (LoadSDNode *LNode =
6752 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6753 if (FrameIndexSDNode *FI =
6754 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6755 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6758 // If this argument is live outside of the entry block, insert a copy from
6759 // wherever we got it to the vreg that other BB's will reference it as.
6760 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6761 // If we can, though, try to skip creating an unnecessary vreg.
6762 // FIXME: This isn't very clean... it would be nice to make this more
6763 // general. It's also subtly incompatible with the hacks FastISel
6765 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6766 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6767 FuncInfo->ValueMap[I] = Reg;
6771 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6772 FuncInfo->InitializeRegForValue(I);
6773 SDB->CopyToExportRegsIfNeeded(I);
6777 assert(i == InVals.size() && "Argument register count mismatch!");
6779 // Finally, if the target has anything special to do, allow it to do so.
6780 // FIXME: this should insert code into the DAG!
6781 EmitFunctionEntryCode();
6784 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6785 /// ensure constants are generated when needed. Remember the virtual registers
6786 /// that need to be added to the Machine PHI nodes as input. We cannot just
6787 /// directly add them, because expansion might result in multiple MBB's for one
6788 /// BB. As such, the start of the BB might correspond to a different MBB than
6792 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6793 const TerminatorInst *TI = LLVMBB->getTerminator();
6795 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6797 // Check successor nodes' PHI nodes that expect a constant to be available
6799 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6800 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6801 if (!isa<PHINode>(SuccBB->begin())) continue;
6802 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6804 // If this terminator has multiple identical successors (common for
6805 // switches), only handle each succ once.
6806 if (!SuccsHandled.insert(SuccMBB)) continue;
6808 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6810 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6811 // nodes and Machine PHI nodes, but the incoming operands have not been
6813 for (BasicBlock::const_iterator I = SuccBB->begin();
6814 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6815 // Ignore dead phi's.
6816 if (PN->use_empty()) continue;
6819 if (PN->getType()->isEmptyTy())
6823 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6825 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6826 unsigned &RegOut = ConstantsOut[C];
6828 RegOut = FuncInfo.CreateRegs(C->getType());
6829 CopyValueToVirtualRegister(C, RegOut);
6833 DenseMap<const Value *, unsigned>::iterator I =
6834 FuncInfo.ValueMap.find(PHIOp);
6835 if (I != FuncInfo.ValueMap.end())
6838 assert(isa<AllocaInst>(PHIOp) &&
6839 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6840 "Didn't codegen value into a register!??");
6841 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6842 CopyValueToVirtualRegister(PHIOp, Reg);
6846 // Remember that this register needs to added to the machine PHI node as
6847 // the input for this MBB.
6848 SmallVector<EVT, 4> ValueVTs;
6849 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6850 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6851 EVT VT = ValueVTs[vti];
6852 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6853 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6854 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6855 Reg += NumRegisters;
6859 ConstantsOut.clear();