1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
593 SmallVector<EVT, 4> ValueVTs;
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
604 SmallVector<MVT, 4> RegVTs;
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
610 SmallVector<unsigned, 4> Regs;
614 RegsForValue(const SmallVector<unsigned, 4> ®s,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
751 // Add an assertion node.
752 assert(FromVT != MVT::Other);
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
766 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767 /// specified value into the registers specified by this object. This uses
768 /// Chain/Flag as the input and updates them for the output Chain/Flag.
769 /// If the Flag pointer is NULL, no flag is used.
770 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
803 Chains[i] = Part.getValue(0);
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
817 Chain = Chains[NumRegs-1];
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
822 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
823 /// operand list. This adds the code marker and includes the number of
824 /// values added into it.
825 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->
861 hasInlineAsmWithSPAdjust());
867 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
872 DL = DAG.getTarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
877 /// clear - Clear out the current SelectionDAG and the associated
878 /// state and prepare this SelectionDAGBuilder object to be used
879 /// for a new block. This doesn't clear out information about
880 /// additional blocks that are needed to complete switch lowering
881 /// or PHI node updating; that information is cleared out as it is
883 void SelectionDAGBuilder::clear() {
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
894 /// clearDanglingDebugInfo - Clear the dangling debug information
895 /// map. This function is separated from the clear so that debug
896 /// information that is dangling in a basic block can be properly
897 /// resolved in a different basic block. This allows the
898 /// SelectionDAG to resolve dangling debug information attached
900 void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
904 /// getRoot - Return the current virtual root of the Selection DAG,
905 /// flushing any PendingLoad items. This must be done before emitting
906 /// a store or any other node that may need to be ordered after any
907 /// prior load instructions.
909 SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
916 PendingLoads.clear();
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
923 PendingLoads.clear();
928 /// getControlRoot - Similar to getRoot, but instead of flushing all the
929 /// PendingLoad items, flush all the PendingExports items. It is necessary
930 /// to do this before emitting a terminator instruction.
932 SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
935 if (PendingExports.empty())
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1);
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
948 PendingExports.push_back(Root);
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
953 PendingExports.clear();
958 void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
967 visit(I.getOpcode(), I);
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
975 void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
979 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
983 default: llvm_unreachable("Unknown instruction type encountered!");
984 // Build the switch statement using the Instruction.def file.
985 #define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987 #include "llvm/IR/Instruction.def"
991 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992 // generate the debug data structures now that we've seen its definition.
993 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1019 /// getCopyFromRegs - If there was virtual register allocated for the value V
1020 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1021 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1022 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, res);
1037 /// getValue - Return an SDValue for the given Value.
1038 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1039 // If we already have an SDValue for this value, use it. It's important
1040 // to do this first, so that we don't create a CopyFromReg if we already
1041 // have a regular SDValue.
1042 SDValue &N = NodeMap[V];
1043 if (N.getNode()) return N;
1045 // If there's a virtual register allocated and initialized for this
1047 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1048 if (copyFromReg.getNode()) {
1052 // Otherwise create a new SDValue and remember it.
1053 SDValue Val = getValueImpl(V);
1055 resolveDanglingDebugInfo(V, Val);
1059 /// getNonRegisterValue - Return an SDValue for the given Value, but
1060 /// don't look in FuncInfo.ValueMap for a virtual register.
1061 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1062 // If we already have an SDValue for this value, use it.
1063 SDValue &N = NodeMap[V];
1064 if (N.getNode()) return N;
1066 // Otherwise create a new SDValue and remember it.
1067 SDValue Val = getValueImpl(V);
1069 resolveDanglingDebugInfo(V, Val);
1073 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1074 /// Create an SDValue for the given value.
1075 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1078 if (const Constant *C = dyn_cast<Constant>(V)) {
1079 EVT VT = TLI.getValueType(V->getType(), true);
1081 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1082 return DAG.getConstant(*CI, VT);
1084 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1085 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1087 if (isa<ConstantPointerNull>(C)) {
1088 unsigned AS = V->getType()->getPointerAddressSpace();
1089 return DAG.getConstant(0, TLI.getPointerTy(AS));
1092 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1093 return DAG.getConstantFP(*CFP, VT);
1095 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1096 return DAG.getUNDEF(VT);
1098 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1099 visit(CE->getOpcode(), *CE);
1100 SDValue N1 = NodeMap[V];
1101 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1105 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1106 SmallVector<SDValue, 4> Constants;
1107 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1109 SDNode *Val = getValue(*OI).getNode();
1110 // If the operand is an empty aggregate, there are no values.
1112 // Add each leaf value from the operand to the Constants list
1113 // to form a flattened list of all the values.
1114 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1115 Constants.push_back(SDValue(Val, i));
1118 return DAG.getMergeValues(Constants, getCurSDLoc());
1121 if (const ConstantDataSequential *CDS =
1122 dyn_cast<ConstantDataSequential>(C)) {
1123 SmallVector<SDValue, 4> Ops;
1124 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1125 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1126 // Add each leaf value from the operand to the Constants list
1127 // to form a flattened list of all the values.
1128 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1129 Ops.push_back(SDValue(Val, i));
1132 if (isa<ArrayType>(CDS->getType()))
1133 return DAG.getMergeValues(Ops, getCurSDLoc());
1134 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1138 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1139 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1140 "Unknown struct or array constant!");
1142 SmallVector<EVT, 4> ValueVTs;
1143 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1144 unsigned NumElts = ValueVTs.size();
1146 return SDValue(); // empty struct
1147 SmallVector<SDValue, 4> Constants(NumElts);
1148 for (unsigned i = 0; i != NumElts; ++i) {
1149 EVT EltVT = ValueVTs[i];
1150 if (isa<UndefValue>(C))
1151 Constants[i] = DAG.getUNDEF(EltVT);
1152 else if (EltVT.isFloatingPoint())
1153 Constants[i] = DAG.getConstantFP(0, EltVT);
1155 Constants[i] = DAG.getConstant(0, EltVT);
1158 return DAG.getMergeValues(Constants, getCurSDLoc());
1161 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1162 return DAG.getBlockAddress(BA, VT);
1164 VectorType *VecTy = cast<VectorType>(V->getType());
1165 unsigned NumElements = VecTy->getNumElements();
1167 // Now that we know the number and type of the elements, get that number of
1168 // elements into the Ops array based on what kind of constant it is.
1169 SmallVector<SDValue, 16> Ops;
1170 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1171 for (unsigned i = 0; i != NumElements; ++i)
1172 Ops.push_back(getValue(CV->getOperand(i)));
1174 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1175 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1178 if (EltVT.isFloatingPoint())
1179 Op = DAG.getConstantFP(0, EltVT);
1181 Op = DAG.getConstant(0, EltVT);
1182 Ops.assign(NumElements, Op);
1185 // Create a BUILD_VECTOR node.
1186 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1189 // If this is a static alloca, generate it as the frameindex instead of
1191 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1192 DenseMap<const AllocaInst*, int>::iterator SI =
1193 FuncInfo.StaticAllocaMap.find(AI);
1194 if (SI != FuncInfo.StaticAllocaMap.end())
1195 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1198 // If this is an instruction which fast-isel has deferred, select it now.
1199 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1200 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1201 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1202 SDValue Chain = DAG.getEntryNode();
1203 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1206 llvm_unreachable("Can't get register for value!");
1209 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1211 SDValue Chain = getControlRoot();
1212 SmallVector<ISD::OutputArg, 8> Outs;
1213 SmallVector<SDValue, 8> OutVals;
1215 if (!FuncInfo.CanLowerReturn) {
1216 unsigned DemoteReg = FuncInfo.DemoteRegister;
1217 const Function *F = I.getParent()->getParent();
1219 // Emit a store of the return value through the virtual register.
1220 // Leave Outs empty so that LowerReturn won't try to load return
1221 // registers the usual way.
1222 SmallVector<EVT, 1> PtrValueVTs;
1223 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1226 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1227 SDValue RetOp = getValue(I.getOperand(0));
1229 SmallVector<EVT, 4> ValueVTs;
1230 SmallVector<uint64_t, 4> Offsets;
1231 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1232 unsigned NumValues = ValueVTs.size();
1234 SmallVector<SDValue, 4> Chains(NumValues);
1235 for (unsigned i = 0; i != NumValues; ++i) {
1236 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1237 RetPtr.getValueType(), RetPtr,
1238 DAG.getIntPtrConstant(Offsets[i]));
1240 DAG.getStore(Chain, getCurSDLoc(),
1241 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1242 // FIXME: better loc info would be nice.
1243 Add, MachinePointerInfo(), false, false, 0);
1246 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1247 MVT::Other, Chains);
1248 } else if (I.getNumOperands() != 0) {
1249 SmallVector<EVT, 4> ValueVTs;
1250 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1251 unsigned NumValues = ValueVTs.size();
1253 SDValue RetOp = getValue(I.getOperand(0));
1255 const Function *F = I.getParent()->getParent();
1257 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 ExtendKind = ISD::SIGN_EXTEND;
1261 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 ExtendKind = ISD::ZERO_EXTEND;
1265 LLVMContext &Context = F->getContext();
1266 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1269 for (unsigned j = 0; j != NumValues; ++j) {
1270 EVT VT = ValueVTs[j];
1272 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1273 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1275 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1276 MVT PartVT = TLI.getRegisterType(Context, VT);
1277 SmallVector<SDValue, 4> Parts(NumParts);
1278 getCopyToParts(DAG, getCurSDLoc(),
1279 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1280 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1282 // 'inreg' on function refers to return value
1283 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1287 // Propagate extension type if any
1288 if (ExtendKind == ISD::SIGN_EXTEND)
1290 else if (ExtendKind == ISD::ZERO_EXTEND)
1293 for (unsigned i = 0; i < NumParts; ++i) {
1294 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1295 VT, /*isfixed=*/true, 0, 0));
1296 OutVals.push_back(Parts[i]);
1302 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1303 CallingConv::ID CallConv =
1304 DAG.getMachineFunction().getFunction()->getCallingConv();
1305 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1306 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1308 // Verify that the target's LowerReturn behaved as expected.
1309 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1310 "LowerReturn didn't return a valid chain!");
1312 // Update the DAG with the new chain value resulting from return lowering.
1316 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1317 /// created for it, emit nodes to copy the value into the virtual
1319 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1321 if (V->getType()->isEmptyTy())
1324 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1325 if (VMI != FuncInfo.ValueMap.end()) {
1326 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1327 CopyValueToVirtualRegister(V, VMI->second);
1331 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1332 /// the current basic block, add it to ValueMap now so that we'll get a
1334 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1335 // No need to export constants.
1336 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1338 // Already exported?
1339 if (FuncInfo.isExportedInst(V)) return;
1341 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1342 CopyValueToVirtualRegister(V, Reg);
1345 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1346 const BasicBlock *FromBB) {
1347 // The operands of the setcc have to be in this block. We don't know
1348 // how to export them from some other block.
1349 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1350 // Can export from current BB.
1351 if (VI->getParent() == FromBB)
1354 // Is already exported, noop.
1355 return FuncInfo.isExportedInst(V);
1358 // If this is an argument, we can export it if the BB is the entry block or
1359 // if it is already exported.
1360 if (isa<Argument>(V)) {
1361 if (FromBB == &FromBB->getParent()->getEntryBlock())
1364 // Otherwise, can only export this if it is already exported.
1365 return FuncInfo.isExportedInst(V);
1368 // Otherwise, constants can always be exported.
1372 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1373 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1374 const MachineBasicBlock *Dst) const {
1375 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1378 const BasicBlock *SrcBB = Src->getBasicBlock();
1379 const BasicBlock *DstBB = Dst->getBasicBlock();
1380 return BPI->getEdgeWeight(SrcBB, DstBB);
1383 void SelectionDAGBuilder::
1384 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1385 uint32_t Weight /* = 0 */) {
1387 Weight = getEdgeWeight(Src, Dst);
1388 Src->addSuccessor(Dst, Weight);
1392 static bool InBlock(const Value *V, const BasicBlock *BB) {
1393 if (const Instruction *I = dyn_cast<Instruction>(V))
1394 return I->getParent() == BB;
1398 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1399 /// This function emits a branch and is used at the leaves of an OR or an
1400 /// AND operator tree.
1403 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1404 MachineBasicBlock *TBB,
1405 MachineBasicBlock *FBB,
1406 MachineBasicBlock *CurBB,
1407 MachineBasicBlock *SwitchBB,
1410 const BasicBlock *BB = CurBB->getBasicBlock();
1412 // If the leaf of the tree is a comparison, merge the condition into
1414 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1415 // The operands of the cmp have to be in this block. We don't know
1416 // how to export them from some other block. If this is the first block
1417 // of the sequence, no exporting is needed.
1418 if (CurBB == SwitchBB ||
1419 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1420 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1421 ISD::CondCode Condition;
1422 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1423 Condition = getICmpCondCode(IC->getPredicate());
1424 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1425 Condition = getFCmpCondCode(FC->getPredicate());
1426 if (TM.Options.NoNaNsFPMath)
1427 Condition = getFCmpCodeWithoutNaN(Condition);
1429 (void)Condition; // silence warning.
1430 llvm_unreachable("Unknown compare instruction");
1433 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1434 TBB, FBB, CurBB, TWeight, FWeight);
1435 SwitchCases.push_back(CB);
1440 // Create a CaseBlock record representing this branch.
1441 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1442 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1443 SwitchCases.push_back(CB);
1446 /// Scale down both weights to fit into uint32_t.
1447 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1448 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1449 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1450 NewTrue = NewTrue / Scale;
1451 NewFalse = NewFalse / Scale;
1454 /// FindMergedConditions - If Cond is an expression like
1455 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1456 MachineBasicBlock *TBB,
1457 MachineBasicBlock *FBB,
1458 MachineBasicBlock *CurBB,
1459 MachineBasicBlock *SwitchBB,
1460 unsigned Opc, uint32_t TWeight,
1462 // If this node is not part of the or/and tree, emit it as a branch.
1463 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1464 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1465 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1466 BOp->getParent() != CurBB->getBasicBlock() ||
1467 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1468 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1469 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1474 // Create TmpBB after CurBB.
1475 MachineFunction::iterator BBI = CurBB;
1476 MachineFunction &MF = DAG.getMachineFunction();
1477 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1478 CurBB->getParent()->insert(++BBI, TmpBB);
1480 if (Opc == Instruction::Or) {
1481 // Codegen X | Y as:
1490 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1491 // The requirement is that
1492 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1493 // = TrueProb for orignal BB.
1494 // Assuming the orignal weights are A and B, one choice is to set BB1's
1495 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1497 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1498 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1499 // TmpBB, but the math is more complicated.
1501 uint64_t NewTrueWeight = TWeight;
1502 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1503 ScaleWeights(NewTrueWeight, NewFalseWeight);
1504 // Emit the LHS condition.
1505 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1506 NewTrueWeight, NewFalseWeight);
1508 NewTrueWeight = TWeight;
1509 NewFalseWeight = 2 * (uint64_t)FWeight;
1510 ScaleWeights(NewTrueWeight, NewFalseWeight);
1511 // Emit the RHS condition into TmpBB.
1512 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1513 NewTrueWeight, NewFalseWeight);
1515 assert(Opc == Instruction::And && "Unknown merge op!");
1516 // Codegen X & Y as:
1524 // This requires creation of TmpBB after CurBB.
1526 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1527 // The requirement is that
1528 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1529 // = FalseProb for orignal BB.
1530 // Assuming the orignal weights are A and B, one choice is to set BB1's
1531 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1533 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1535 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1536 uint64_t NewFalseWeight = FWeight;
1537 ScaleWeights(NewTrueWeight, NewFalseWeight);
1538 // Emit the LHS condition.
1539 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1540 NewTrueWeight, NewFalseWeight);
1542 NewTrueWeight = 2 * (uint64_t)TWeight;
1543 NewFalseWeight = FWeight;
1544 ScaleWeights(NewTrueWeight, NewFalseWeight);
1545 // Emit the RHS condition into TmpBB.
1546 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1547 NewTrueWeight, NewFalseWeight);
1551 /// If the set of cases should be emitted as a series of branches, return true.
1552 /// If we should emit this as a bunch of and/or'd together conditions, return
1555 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1556 if (Cases.size() != 2) return true;
1558 // If this is two comparisons of the same values or'd or and'd together, they
1559 // will get folded into a single comparison, so don't emit two blocks.
1560 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1561 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1562 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1563 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1567 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1568 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1569 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1570 Cases[0].CC == Cases[1].CC &&
1571 isa<Constant>(Cases[0].CmpRHS) &&
1572 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1573 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1575 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1582 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1583 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1585 // Update machine-CFG edges.
1586 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1588 // Figure out which block is immediately after the current one.
1589 MachineBasicBlock *NextBlock = nullptr;
1590 MachineFunction::iterator BBI = BrMBB;
1591 if (++BBI != FuncInfo.MF->end())
1594 if (I.isUnconditional()) {
1595 // Update machine-CFG edges.
1596 BrMBB->addSuccessor(Succ0MBB);
1598 // If this is not a fall-through branch or optimizations are switched off,
1600 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1601 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1602 MVT::Other, getControlRoot(),
1603 DAG.getBasicBlock(Succ0MBB)));
1608 // If this condition is one of the special cases we handle, do special stuff
1610 const Value *CondVal = I.getCondition();
1611 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1613 // If this is a series of conditions that are or'd or and'd together, emit
1614 // this as a sequence of branches instead of setcc's with and/or operations.
1615 // As long as jumps are not expensive, this should improve performance.
1616 // For example, instead of something like:
1629 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1630 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1631 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1632 BOp->getOpcode() == Instruction::Or)) {
1633 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1634 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1635 getEdgeWeight(BrMBB, Succ1MBB));
1636 // If the compares in later blocks need to use values not currently
1637 // exported from this block, export them now. This block should always
1638 // be the first entry.
1639 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1641 // Allow some cases to be rejected.
1642 if (ShouldEmitAsBranches(SwitchCases)) {
1643 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1644 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1645 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1648 // Emit the branch for this block.
1649 visitSwitchCase(SwitchCases[0], BrMBB);
1650 SwitchCases.erase(SwitchCases.begin());
1654 // Okay, we decided not to do this, remove any inserted MBB's and clear
1656 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1657 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1659 SwitchCases.clear();
1663 // Create a CaseBlock record representing this branch.
1664 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1665 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1667 // Use visitSwitchCase to actually insert the fast branch sequence for this
1669 visitSwitchCase(CB, BrMBB);
1672 /// visitSwitchCase - Emits the necessary code to represent a single node in
1673 /// the binary search tree resulting from lowering a switch instruction.
1674 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1675 MachineBasicBlock *SwitchBB) {
1677 SDValue CondLHS = getValue(CB.CmpLHS);
1678 SDLoc dl = getCurSDLoc();
1680 // Build the setcc now.
1682 // Fold "(X == true)" to X and "(X == false)" to !X to
1683 // handle common cases produced by branch lowering.
1684 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1685 CB.CC == ISD::SETEQ)
1687 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1688 CB.CC == ISD::SETEQ) {
1689 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1690 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1692 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1694 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1696 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1697 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1699 SDValue CmpOp = getValue(CB.CmpMHS);
1700 EVT VT = CmpOp.getValueType();
1702 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1703 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1706 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1707 VT, CmpOp, DAG.getConstant(Low, VT));
1708 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1709 DAG.getConstant(High-Low, VT), ISD::SETULE);
1713 // Update successor info
1714 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1715 // TrueBB and FalseBB are always different unless the incoming IR is
1716 // degenerate. This only happens when running llc on weird IR.
1717 if (CB.TrueBB != CB.FalseBB)
1718 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1720 // Set NextBlock to be the MBB immediately after the current one, if any.
1721 // This is used to avoid emitting unnecessary branches to the next block.
1722 MachineBasicBlock *NextBlock = nullptr;
1723 MachineFunction::iterator BBI = SwitchBB;
1724 if (++BBI != FuncInfo.MF->end())
1727 // If the lhs block is the next block, invert the condition so that we can
1728 // fall through to the lhs instead of the rhs block.
1729 if (CB.TrueBB == NextBlock) {
1730 std::swap(CB.TrueBB, CB.FalseBB);
1731 SDValue True = DAG.getConstant(1, Cond.getValueType());
1732 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1735 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1736 MVT::Other, getControlRoot(), Cond,
1737 DAG.getBasicBlock(CB.TrueBB));
1739 // Insert the false branch. Do this even if it's a fall through branch,
1740 // this makes it easier to do DAG optimizations which require inverting
1741 // the branch condition.
1742 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1743 DAG.getBasicBlock(CB.FalseBB));
1745 DAG.setRoot(BrCond);
1748 /// visitJumpTable - Emit JumpTable node in the current MBB
1749 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1750 // Emit the code for the jump table
1751 assert(JT.Reg != -1U && "Should lower JT Header first!");
1752 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1753 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1755 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1756 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1757 MVT::Other, Index.getValue(1),
1759 DAG.setRoot(BrJumpTable);
1762 /// visitJumpTableHeader - This function emits necessary code to produce index
1763 /// in the JumpTable from switch case.
1764 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1765 JumpTableHeader &JTH,
1766 MachineBasicBlock *SwitchBB) {
1767 // Subtract the lowest switch case value from the value being switched on and
1768 // conditional branch to default mbb if the result is greater than the
1769 // difference between smallest and largest cases.
1770 SDValue SwitchOp = getValue(JTH.SValue);
1771 EVT VT = SwitchOp.getValueType();
1772 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1773 DAG.getConstant(JTH.First, VT));
1775 // The SDNode we just created, which holds the value being switched on minus
1776 // the smallest case value, needs to be copied to a virtual register so it
1777 // can be used as an index into the jump table in a subsequent basic block.
1778 // This value may be smaller or larger than the target's pointer type, and
1779 // therefore require extension or truncating.
1780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1781 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1783 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1784 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1785 JumpTableReg, SwitchOp);
1786 JT.Reg = JumpTableReg;
1788 // Emit the range check for the jump table, and branch to the default block
1789 // for the switch statement if the value being switched on exceeds the largest
1790 // case in the switch.
1792 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1793 Sub.getValueType()),
1794 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1796 // Set NextBlock to be the MBB immediately after the current one, if any.
1797 // This is used to avoid emitting unnecessary branches to the next block.
1798 MachineBasicBlock *NextBlock = nullptr;
1799 MachineFunction::iterator BBI = SwitchBB;
1801 if (++BBI != FuncInfo.MF->end())
1804 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1805 MVT::Other, CopyTo, CMP,
1806 DAG.getBasicBlock(JT.Default));
1808 if (JT.MBB != NextBlock)
1809 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1810 DAG.getBasicBlock(JT.MBB));
1812 DAG.setRoot(BrCond);
1815 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1816 /// tail spliced into a stack protector check success bb.
1818 /// For a high level explanation of how this fits into the stack protector
1819 /// generation see the comment on the declaration of class
1820 /// StackProtectorDescriptor.
1821 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1822 MachineBasicBlock *ParentBB) {
1824 // First create the loads to the guard/stack slot for the comparison.
1825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1826 EVT PtrTy = TLI.getPointerTy();
1828 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1829 int FI = MFI->getStackProtectorIndex();
1831 const Value *IRGuard = SPD.getGuard();
1832 SDValue GuardPtr = getValue(IRGuard);
1833 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1836 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1840 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1841 // guard value from the virtual register holding the value. Otherwise, emit a
1842 // volatile load to retrieve the stack guard value.
1843 unsigned GuardReg = SPD.getGuardReg();
1845 if (GuardReg && TLI.useLoadStackGuardNode())
1846 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1849 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1850 GuardPtr, MachinePointerInfo(IRGuard, 0),
1851 true, false, false, Align);
1853 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1855 MachinePointerInfo::getFixedStack(FI),
1856 true, false, false, Align);
1858 // Perform the comparison via a subtract/getsetcc.
1859 EVT VT = Guard.getValueType();
1860 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1863 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1864 Sub.getValueType()),
1865 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1867 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1868 // branch to failure MBB.
1869 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1870 MVT::Other, StackSlot.getOperand(0),
1871 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1872 // Otherwise branch to success MBB.
1873 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1875 DAG.getBasicBlock(SPD.getSuccessMBB()));
1880 /// Codegen the failure basic block for a stack protector check.
1882 /// A failure stack protector machine basic block consists simply of a call to
1883 /// __stack_chk_fail().
1885 /// For a high level explanation of how this fits into the stack protector
1886 /// generation see the comment on the declaration of class
1887 /// StackProtectorDescriptor.
1889 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1892 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1893 nullptr, 0, false, getCurSDLoc(), false, false).second;
1897 /// visitBitTestHeader - This function emits necessary code to produce value
1898 /// suitable for "bit tests"
1899 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1900 MachineBasicBlock *SwitchBB) {
1901 // Subtract the minimum value
1902 SDValue SwitchOp = getValue(B.SValue);
1903 EVT VT = SwitchOp.getValueType();
1904 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1905 DAG.getConstant(B.First, VT));
1908 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1910 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1911 Sub.getValueType()),
1912 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1914 // Determine the type of the test operands.
1915 bool UsePtrType = false;
1916 if (!TLI.isTypeLegal(VT))
1919 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1920 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1921 // Switch table case range are encoded into series of masks.
1922 // Just use pointer type, it's guaranteed to fit.
1928 VT = TLI.getPointerTy();
1929 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1932 B.RegVT = VT.getSimpleVT();
1933 B.Reg = FuncInfo.CreateReg(B.RegVT);
1934 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1937 // Set NextBlock to be the MBB immediately after the current one, if any.
1938 // This is used to avoid emitting unnecessary branches to the next block.
1939 MachineBasicBlock *NextBlock = nullptr;
1940 MachineFunction::iterator BBI = SwitchBB;
1941 if (++BBI != FuncInfo.MF->end())
1944 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1946 addSuccessorWithWeight(SwitchBB, B.Default);
1947 addSuccessorWithWeight(SwitchBB, MBB);
1949 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1950 MVT::Other, CopyTo, RangeCmp,
1951 DAG.getBasicBlock(B.Default));
1953 if (MBB != NextBlock)
1954 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1955 DAG.getBasicBlock(MBB));
1957 DAG.setRoot(BrRange);
1960 /// visitBitTestCase - this function produces one "bit test"
1961 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1962 MachineBasicBlock* NextMBB,
1963 uint32_t BranchWeightToNext,
1966 MachineBasicBlock *SwitchBB) {
1968 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1971 unsigned PopCount = countPopulation(B.Mask);
1972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1973 if (PopCount == 1) {
1974 // Testing for a single bit; just compare the shift count with what it
1975 // would need to be to shift a 1 bit in that position.
1977 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1978 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1979 } else if (PopCount == BB.Range) {
1980 // There is only one zero bit in the range, test for it directly.
1982 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1983 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1985 // Make desired shift
1986 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1987 DAG.getConstant(1, VT), ShiftOp);
1989 // Emit bit tests and jumps
1990 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1991 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1992 Cmp = DAG.getSetCC(getCurSDLoc(),
1993 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1994 DAG.getConstant(0, VT), ISD::SETNE);
1997 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1998 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1999 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2000 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2002 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
2003 MVT::Other, getControlRoot(),
2004 Cmp, DAG.getBasicBlock(B.TargetBB));
2006 // Set NextBlock to be the MBB immediately after the current one, if any.
2007 // This is used to avoid emitting unnecessary branches to the next block.
2008 MachineBasicBlock *NextBlock = nullptr;
2009 MachineFunction::iterator BBI = SwitchBB;
2010 if (++BBI != FuncInfo.MF->end())
2013 if (NextMBB != NextBlock)
2014 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2015 DAG.getBasicBlock(NextMBB));
2020 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2021 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2023 // Retrieve successors.
2024 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2025 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2027 const Value *Callee(I.getCalledValue());
2028 const Function *Fn = dyn_cast<Function>(Callee);
2029 if (isa<InlineAsm>(Callee))
2031 else if (Fn && Fn->isIntrinsic()) {
2032 switch (Fn->getIntrinsicID()) {
2034 llvm_unreachable("Cannot invoke this intrinsic");
2035 case Intrinsic::donothing:
2036 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2038 case Intrinsic::experimental_patchpoint_void:
2039 case Intrinsic::experimental_patchpoint_i64:
2040 visitPatchpoint(&I, LandingPad);
2042 case Intrinsic::experimental_gc_statepoint:
2043 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2047 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2049 // If the value of the invoke is used outside of its defining block, make it
2050 // available as a virtual register.
2051 // We already took care of the exported value for the statepoint instruction
2052 // during call to the LowerStatepoint.
2053 if (!isStatepoint(I)) {
2054 CopyToExportRegsIfNeeded(&I);
2057 // Update successor info
2058 addSuccessorWithWeight(InvokeMBB, Return);
2059 addSuccessorWithWeight(InvokeMBB, LandingPad);
2061 // Drop into normal successor.
2062 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2063 MVT::Other, getControlRoot(),
2064 DAG.getBasicBlock(Return)));
2067 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2068 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2071 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2072 assert(FuncInfo.MBB->isLandingPad() &&
2073 "Call to landingpad not in landing pad!");
2075 MachineBasicBlock *MBB = FuncInfo.MBB;
2076 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2077 AddLandingPadInfo(LP, MMI, MBB);
2079 // If there aren't registers to copy the values into (e.g., during SjLj
2080 // exceptions), then don't bother to create these DAG nodes.
2081 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2082 if (TLI.getExceptionPointerRegister() == 0 &&
2083 TLI.getExceptionSelectorRegister() == 0)
2086 SmallVector<EVT, 2> ValueVTs;
2087 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2088 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2090 // Get the two live-in registers as SDValues. The physregs have already been
2091 // copied into virtual registers.
2093 if (FuncInfo.ExceptionPointerVirtReg) {
2094 Ops[0] = DAG.getZExtOrTrunc(
2095 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2096 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2097 getCurSDLoc(), ValueVTs[0]);
2099 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2101 Ops[1] = DAG.getZExtOrTrunc(
2102 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2103 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2104 getCurSDLoc(), ValueVTs[1]);
2107 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2108 DAG.getVTList(ValueVTs), Ops);
2113 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2114 MachineBasicBlock *LPadBB) {
2115 SDValue Chain = getControlRoot();
2117 // Get the typeid that we will dispatch on later.
2118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2119 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2120 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2121 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2122 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2123 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2125 // Branch to the main landing pad block.
2126 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2127 ClauseMBB->addSuccessor(LPadBB);
2128 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2129 DAG.getBasicBlock(LPadBB)));
2133 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2134 /// small case ranges).
2135 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2136 CaseRecVector& WorkList,
2138 MachineBasicBlock *Default,
2139 MachineBasicBlock *SwitchBB) {
2140 // Size is the number of Cases represented by this range.
2141 size_t Size = CR.Range.second - CR.Range.first;
2145 // Get the MachineFunction which holds the current MBB. This is used when
2146 // inserting any additional MBBs necessary to represent the switch.
2147 MachineFunction *CurMF = FuncInfo.MF;
2149 // Figure out which block is immediately after the current one.
2150 MachineBasicBlock *NextBlock = nullptr;
2151 MachineFunction::iterator BBI = CR.CaseBB;
2153 if (++BBI != FuncInfo.MF->end())
2156 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2157 // If any two of the cases has the same destination, and if one value
2158 // is the same as the other, but has one bit unset that the other has set,
2159 // use bit manipulation to do two compares at once. For example:
2160 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2161 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2162 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2163 if (Size == 2 && CR.CaseBB == SwitchBB) {
2164 Case &Small = *CR.Range.first;
2165 Case &Big = *(CR.Range.second-1);
2167 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2168 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2169 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2171 // Check that there is only one bit different.
2172 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2173 (SmallValue | BigValue) == BigValue) {
2174 // Isolate the common bit.
2175 APInt CommonBit = BigValue & ~SmallValue;
2176 assert((SmallValue | CommonBit) == BigValue &&
2177 CommonBit.countPopulation() == 1 && "Not a common bit?");
2179 SDValue CondLHS = getValue(SV);
2180 EVT VT = CondLHS.getValueType();
2181 SDLoc DL = getCurSDLoc();
2183 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2184 DAG.getConstant(CommonBit, VT));
2185 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2186 Or, DAG.getConstant(BigValue, VT),
2189 // Update successor info.
2190 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2191 addSuccessorWithWeight(SwitchBB, Small.BB,
2192 Small.ExtraWeight + Big.ExtraWeight);
2193 addSuccessorWithWeight(SwitchBB, Default,
2194 // The default destination is the first successor in IR.
2195 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2197 // Insert the true branch.
2198 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2199 getControlRoot(), Cond,
2200 DAG.getBasicBlock(Small.BB));
2202 // Insert the false branch.
2203 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2204 DAG.getBasicBlock(Default));
2206 DAG.setRoot(BrCond);
2212 // Order cases by weight so the most likely case will be checked first.
2213 uint32_t UnhandledWeights = 0;
2215 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2216 uint32_t IWeight = I->ExtraWeight;
2217 UnhandledWeights += IWeight;
2218 for (CaseItr J = CR.Range.first; J < I; ++J) {
2219 uint32_t JWeight = J->ExtraWeight;
2220 if (IWeight > JWeight)
2225 // Rearrange the case blocks so that the last one falls through if possible.
2226 Case &BackCase = *(CR.Range.second-1);
2228 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2229 // The last case block won't fall through into 'NextBlock' if we emit the
2230 // branches in this order. See if rearranging a case value would help.
2231 // We start at the bottom as it's the case with the least weight.
2232 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2233 if (I->BB == NextBlock) {
2234 std::swap(*I, BackCase);
2239 // Create a CaseBlock record representing a conditional branch to
2240 // the Case's target mbb if the value being switched on SV is equal
2242 MachineBasicBlock *CurBlock = CR.CaseBB;
2243 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2244 MachineBasicBlock *FallThrough;
2246 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2247 CurMF->insert(BBI, FallThrough);
2249 // Put SV in a virtual register to make it available from the new blocks.
2250 ExportFromCurrentBlock(SV);
2252 // If the last case doesn't match, go to the default block.
2253 FallThrough = Default;
2256 const Value *RHS, *LHS, *MHS;
2258 if (I->High == I->Low) {
2259 // This is just small small case range :) containing exactly 1 case
2261 LHS = SV; RHS = I->High; MHS = nullptr;
2264 LHS = I->Low; MHS = SV; RHS = I->High;
2267 // The false weight should be sum of all un-handled cases.
2268 UnhandledWeights -= I->ExtraWeight;
2269 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2271 /* trueweight */ I->ExtraWeight,
2272 /* falseweight */ UnhandledWeights);
2274 // If emitting the first comparison, just call visitSwitchCase to emit the
2275 // code into the current block. Otherwise, push the CaseBlock onto the
2276 // vector to be later processed by SDISel, and insert the node's MBB
2277 // before the next MBB.
2278 if (CurBlock == SwitchBB)
2279 visitSwitchCase(CB, SwitchBB);
2281 SwitchCases.push_back(CB);
2283 CurBlock = FallThrough;
2289 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2290 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2291 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2294 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2295 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2296 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2297 return (LastExt - FirstExt + 1ULL);
2300 /// handleJTSwitchCase - Emit jumptable for current switch case range
2301 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2302 CaseRecVector &WorkList,
2304 MachineBasicBlock *Default,
2305 MachineBasicBlock *SwitchBB) {
2306 Case& FrontCase = *CR.Range.first;
2307 Case& BackCase = *(CR.Range.second-1);
2309 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2310 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2312 APInt TSize(First.getBitWidth(), 0);
2313 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2317 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2320 APInt Range = ComputeRange(First, Last);
2321 // The density is TSize / Range. Require at least 40%.
2322 // It should not be possible for IntTSize to saturate for sane code, but make
2323 // sure we handle Range saturation correctly.
2324 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2325 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2326 if (IntTSize * 10 < IntRange * 4)
2329 DEBUG(dbgs() << "Lowering jump table\n"
2330 << "First entry: " << First << ". Last entry: " << Last << '\n'
2331 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2333 // Get the MachineFunction which holds the current MBB. This is used when
2334 // inserting any additional MBBs necessary to represent the switch.
2335 MachineFunction *CurMF = FuncInfo.MF;
2337 // Figure out which block is immediately after the current one.
2338 MachineFunction::iterator BBI = CR.CaseBB;
2341 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2343 // Create a new basic block to hold the code for loading the address
2344 // of the jump table, and jumping to it. Update successor information;
2345 // we will either branch to the default case for the switch, or the jump
2347 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2348 CurMF->insert(BBI, JumpTableBB);
2350 addSuccessorWithWeight(CR.CaseBB, Default);
2351 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2353 // Build a vector of destination BBs, corresponding to each target
2354 // of the jump table. If the value of the jump table slot corresponds to
2355 // a case statement, push the case's BB onto the vector, otherwise, push
2357 std::vector<MachineBasicBlock*> DestBBs;
2359 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2360 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2361 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2363 if (Low.sle(TEI) && TEI.sle(High)) {
2364 DestBBs.push_back(I->BB);
2368 DestBBs.push_back(Default);
2372 // Calculate weight for each unique destination in CR.
2373 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2375 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2376 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2377 DestWeights.find(I->BB);
2378 if (Itr != DestWeights.end())
2379 Itr->second += I->ExtraWeight;
2381 DestWeights[I->BB] = I->ExtraWeight;
2384 // Update successor info. Add one edge to each unique successor.
2385 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2386 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2387 E = DestBBs.end(); I != E; ++I) {
2388 if (!SuccsHandled[(*I)->getNumber()]) {
2389 SuccsHandled[(*I)->getNumber()] = true;
2390 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2391 DestWeights.find(*I);
2392 addSuccessorWithWeight(JumpTableBB, *I,
2393 Itr != DestWeights.end() ? Itr->second : 0);
2397 // Create a jump table index for this jump table.
2398 unsigned JTEncoding = TLI.getJumpTableEncoding();
2399 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2400 ->createJumpTableIndex(DestBBs);
2402 // Set the jump table information so that we can codegen it as a second
2403 // MachineBasicBlock
2404 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2405 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2406 if (CR.CaseBB == SwitchBB)
2407 visitJumpTableHeader(JT, JTH, SwitchBB);
2409 JTCases.push_back(JumpTableBlock(JTH, JT));
2413 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2415 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2416 CaseRecVector& WorkList,
2418 MachineBasicBlock* SwitchBB) {
2419 Case& FrontCase = *CR.Range.first;
2420 Case& BackCase = *(CR.Range.second-1);
2422 // Size is the number of Cases represented by this range.
2423 unsigned Size = CR.Range.second - CR.Range.first;
2425 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2426 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2428 CaseItr Pivot = CR.Range.first + Size/2;
2430 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2431 // (heuristically) allow us to emit JumpTable's later.
2432 APInt TSize(First.getBitWidth(), 0);
2433 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2437 APInt LSize = FrontCase.size();
2438 APInt RSize = TSize-LSize;
2439 DEBUG(dbgs() << "Selecting best pivot: \n"
2440 << "First: " << First << ", Last: " << Last <<'\n'
2441 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2443 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2445 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2446 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2447 APInt Range = ComputeRange(LEnd, RBegin);
2448 assert((Range - 2ULL).isNonNegative() &&
2449 "Invalid case distance");
2450 // Use volatile double here to avoid excess precision issues on some hosts,
2451 // e.g. that use 80-bit X87 registers.
2452 // Only consider the density of sub-ranges that actually have sufficient
2453 // entries to be lowered as a jump table.
2454 volatile double LDensity =
2455 LSize.ult(TLI.getMinimumJumpTableEntries())
2457 : LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2458 volatile double RDensity =
2459 RSize.ult(TLI.getMinimumJumpTableEntries())
2461 : RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2462 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2463 // Should always split in some non-trivial place
2464 DEBUG(dbgs() <<"=>Step\n"
2465 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2466 << "LDensity: " << LDensity
2467 << ", RDensity: " << RDensity << '\n'
2468 << "Metric: " << Metric << '\n');
2469 if (FMetric < Metric) {
2472 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2479 if (FMetric == 0 || !areJTsAllowed(TLI))
2480 Pivot = CR.Range.first + Size/2;
2481 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2485 void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2486 CaseRecVector &WorkList,
2488 MachineBasicBlock *SwitchBB) {
2489 // Get the MachineFunction which holds the current MBB. This is used when
2490 // inserting any additional MBBs necessary to represent the switch.
2491 MachineFunction *CurMF = FuncInfo.MF;
2493 // Figure out which block is immediately after the current one.
2494 MachineFunction::iterator BBI = CR.CaseBB;
2497 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2499 CaseRange LHSR(CR.Range.first, Pivot);
2500 CaseRange RHSR(Pivot, CR.Range.second);
2501 const Constant *C = Pivot->Low;
2502 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2504 // We know that we branch to the LHS if the Value being switched on is
2505 // less than the Pivot value, C. We use this to optimize our binary
2506 // tree a bit, by recognizing that if SV is greater than or equal to the
2507 // LHS's Case Value, and that Case Value is exactly one less than the
2508 // Pivot's Value, then we can branch directly to the LHS's Target,
2509 // rather than creating a leaf node for it.
2510 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2511 cast<ConstantInt>(C)->getValue() ==
2512 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2513 TrueBB = LHSR.first->BB;
2515 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2516 CurMF->insert(BBI, TrueBB);
2517 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2519 // Put SV in a virtual register to make it available from the new blocks.
2520 ExportFromCurrentBlock(SV);
2523 // Similar to the optimization above, if the Value being switched on is
2524 // known to be less than the Constant CR.LT, and the current Case Value
2525 // is CR.LT - 1, then we can branch directly to the target block for
2526 // the current Case Value, rather than emitting a RHS leaf node for it.
2527 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2528 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2529 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2530 FalseBB = RHSR.first->BB;
2532 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2533 CurMF->insert(BBI, FalseBB);
2534 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2536 // Put SV in a virtual register to make it available from the new blocks.
2537 ExportFromCurrentBlock(SV);
2540 // Create a CaseBlock record representing a conditional branch to
2541 // the LHS node if the value being switched on SV is less than C.
2542 // Otherwise, branch to LHS.
2543 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2545 if (CR.CaseBB == SwitchBB)
2546 visitSwitchCase(CB, SwitchBB);
2548 SwitchCases.push_back(CB);
2551 /// handleBitTestsSwitchCase - if current case range has few destination and
2552 /// range span less, than machine word bitwidth, encode case range into series
2553 /// of masks and emit bit tests with these masks.
2554 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2555 CaseRecVector& WorkList,
2557 MachineBasicBlock* Default,
2558 MachineBasicBlock* SwitchBB) {
2559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2560 EVT PTy = TLI.getPointerTy();
2561 unsigned IntPtrBits = PTy.getSizeInBits();
2563 Case& FrontCase = *CR.Range.first;
2564 Case& BackCase = *(CR.Range.second-1);
2566 // Get the MachineFunction which holds the current MBB. This is used when
2567 // inserting any additional MBBs necessary to represent the switch.
2568 MachineFunction *CurMF = FuncInfo.MF;
2570 // If target does not have legal shift left, do not emit bit tests at all.
2571 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2575 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2576 // Single case counts one, case range - two.
2577 numCmps += (I->Low == I->High ? 1 : 2);
2580 // Count unique destinations
2581 SmallSet<MachineBasicBlock*, 4> Dests;
2582 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2583 Dests.insert(I->BB);
2584 if (Dests.size() > 3)
2585 // Don't bother the code below, if there are too much unique destinations
2588 DEBUG(dbgs() << "Total number of unique destinations: "
2589 << Dests.size() << '\n'
2590 << "Total number of comparisons: " << numCmps << '\n');
2592 // Compute span of values.
2593 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2594 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2595 APInt cmpRange = maxValue - minValue;
2597 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2598 << "Low bound: " << minValue << '\n'
2599 << "High bound: " << maxValue << '\n');
2601 if (cmpRange.uge(IntPtrBits) ||
2602 (!(Dests.size() == 1 && numCmps >= 3) &&
2603 !(Dests.size() == 2 && numCmps >= 5) &&
2604 !(Dests.size() >= 3 && numCmps >= 6)))
2607 DEBUG(dbgs() << "Emitting bit tests\n");
2608 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2610 // Optimize the case where all the case values fit in a
2611 // word without having to subtract minValue. In this case,
2612 // we can optimize away the subtraction.
2613 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2614 cmpRange = maxValue;
2616 lowBound = minValue;
2619 CaseBitsVector CasesBits;
2620 unsigned i, count = 0;
2622 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2623 MachineBasicBlock* Dest = I->BB;
2624 for (i = 0; i < count; ++i)
2625 if (Dest == CasesBits[i].BB)
2629 assert((count < 3) && "Too much destinations to test!");
2630 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2634 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2635 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2637 uint64_t lo = (lowValue - lowBound).getZExtValue();
2638 uint64_t hi = (highValue - lowBound).getZExtValue();
2639 CasesBits[i].ExtraWeight += I->ExtraWeight;
2641 for (uint64_t j = lo; j <= hi; j++) {
2642 CasesBits[i].Mask |= 1ULL << j;
2643 CasesBits[i].Bits++;
2647 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2651 // Figure out which block is immediately after the current one.
2652 MachineFunction::iterator BBI = CR.CaseBB;
2655 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2657 DEBUG(dbgs() << "Cases:\n");
2658 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2659 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2660 << ", Bits: " << CasesBits[i].Bits
2661 << ", BB: " << CasesBits[i].BB << '\n');
2663 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2664 CurMF->insert(BBI, CaseBB);
2665 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2667 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2669 // Put SV in a virtual register to make it available from the new blocks.
2670 ExportFromCurrentBlock(SV);
2673 BitTestBlock BTB(lowBound, cmpRange, SV,
2674 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2675 CR.CaseBB, Default, std::move(BTC));
2677 if (CR.CaseBB == SwitchBB)
2678 visitBitTestHeader(BTB, SwitchBB);
2680 BitTestCases.push_back(std::move(BTB));
2685 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2686 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2687 const SwitchInst& SI) {
2688 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2689 // Start with "simple" cases.
2690 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2691 const BasicBlock *SuccBB = i.getCaseSuccessor();
2692 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2694 uint32_t ExtraWeight =
2695 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2697 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2698 SMBB, ExtraWeight));
2700 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2702 // Merge case into clusters
2703 if (Cases.size() >= 2)
2704 // Must recompute end() each iteration because it may be
2705 // invalidated by erase if we hold on to it
2706 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2707 J != Cases.end(); ) {
2708 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2709 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2710 MachineBasicBlock* nextBB = J->BB;
2711 MachineBasicBlock* currentBB = I->BB;
2713 // If the two neighboring cases go to the same destination, merge them
2714 // into a single case.
2715 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2717 I->ExtraWeight += J->ExtraWeight;
2726 for (auto &I : Cases)
2727 // A range counts double, since it requires two compares.
2728 numCmps += I.Low != I.High ? 2 : 1;
2730 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2731 << ". Total compares: " << numCmps << '\n';
2735 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2736 MachineBasicBlock *Last) {
2738 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2739 if (JTCases[i].first.HeaderBB == First)
2740 JTCases[i].first.HeaderBB = Last;
2742 // Update BitTestCases.
2743 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2744 if (BitTestCases[i].Parent == First)
2745 BitTestCases[i].Parent = Last;
2748 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2749 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2751 // Figure out which block is immediately after the current one.
2752 MachineBasicBlock *NextBlock = nullptr;
2753 if (SwitchMBB + 1 != FuncInfo.MF->end())
2754 NextBlock = SwitchMBB + 1;
2757 // Create a vector of Cases, sorted so that we can efficiently create a binary
2758 // search tree from them.
2760 Clusterify(Cases, SI);
2762 // Get the default destination MBB.
2763 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2765 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2767 // Replace an unreachable default destination with the most popular case
2769 DenseMap<const BasicBlock *, unsigned> Popularity;
2770 unsigned MaxPop = 0;
2771 const BasicBlock *MaxBB = nullptr;
2772 for (auto I : SI.cases()) {
2773 const BasicBlock *BB = I.getCaseSuccessor();
2774 if (++Popularity[BB] > MaxPop) {
2775 MaxPop = Popularity[BB];
2783 Default = FuncInfo.MBBMap[MaxBB];
2785 // Remove cases that were pointing to the destination that is now the default.
2786 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2787 [&](const Case &C) { return C.BB == Default; }),
2791 // If there is only the default destination, go there directly.
2792 if (Cases.empty()) {
2793 // Update machine-CFG edges.
2794 SwitchMBB->addSuccessor(Default);
2796 // If this is not a fall-through branch, emit the branch.
2797 if (Default != NextBlock) {
2798 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2799 getControlRoot(), DAG.getBasicBlock(Default)));
2804 // Get the Value to be switched on.
2805 const Value *SV = SI.getCondition();
2807 // Push the initial CaseRec onto the worklist
2808 CaseRecVector WorkList;
2809 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2810 CaseRange(Cases.begin(),Cases.end())));
2812 while (!WorkList.empty()) {
2813 // Grab a record representing a case range to process off the worklist
2814 CaseRec CR = WorkList.back();
2815 WorkList.pop_back();
2817 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2820 // If the range has few cases (two or less) emit a series of specific
2822 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2825 // If the switch has more than N blocks, and is at least 40% dense, and the
2826 // target supports indirect branches, then emit a jump table rather than
2827 // lowering the switch to a binary tree of conditional branches.
2828 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2829 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2832 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2833 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2834 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2838 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2839 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2841 // Update machine-CFG edges with unique successors.
2842 SmallSet<BasicBlock*, 32> Done;
2843 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2844 BasicBlock *BB = I.getSuccessor(i);
2845 bool Inserted = Done.insert(BB).second;
2849 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2850 addSuccessorWithWeight(IndirectBrMBB, Succ);
2853 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2854 MVT::Other, getControlRoot(),
2855 getValue(I.getAddress())));
2858 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2859 if (DAG.getTarget().Options.TrapUnreachable)
2860 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2863 void SelectionDAGBuilder::visitFSub(const User &I) {
2864 // -0.0 - X --> fneg
2865 Type *Ty = I.getType();
2866 if (isa<Constant>(I.getOperand(0)) &&
2867 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2868 SDValue Op2 = getValue(I.getOperand(1));
2869 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2870 Op2.getValueType(), Op2));
2874 visitBinary(I, ISD::FSUB);
2877 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2878 SDValue Op1 = getValue(I.getOperand(0));
2879 SDValue Op2 = getValue(I.getOperand(1));
2884 if (const OverflowingBinaryOperator *OFBinOp =
2885 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2886 nuw = OFBinOp->hasNoUnsignedWrap();
2887 nsw = OFBinOp->hasNoSignedWrap();
2889 if (const PossiblyExactOperator *ExactOp =
2890 dyn_cast<const PossiblyExactOperator>(&I))
2891 exact = ExactOp->isExact();
2893 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2894 Op1, Op2, nuw, nsw, exact);
2895 setValue(&I, BinNodeValue);
2898 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2899 SDValue Op1 = getValue(I.getOperand(0));
2900 SDValue Op2 = getValue(I.getOperand(1));
2903 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2905 // Coerce the shift amount to the right type if we can.
2906 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2907 unsigned ShiftSize = ShiftTy.getSizeInBits();
2908 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2909 SDLoc DL = getCurSDLoc();
2911 // If the operand is smaller than the shift count type, promote it.
2912 if (ShiftSize > Op2Size)
2913 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2915 // If the operand is larger than the shift count type but the shift
2916 // count type has enough bits to represent any shift value, truncate
2917 // it now. This is a common case and it exposes the truncate to
2918 // optimization early.
2919 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2920 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2921 // Otherwise we'll need to temporarily settle for some other convenient
2922 // type. Type legalization will make adjustments once the shiftee is split.
2924 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2931 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2933 if (const OverflowingBinaryOperator *OFBinOp =
2934 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2935 nuw = OFBinOp->hasNoUnsignedWrap();
2936 nsw = OFBinOp->hasNoSignedWrap();
2938 if (const PossiblyExactOperator *ExactOp =
2939 dyn_cast<const PossiblyExactOperator>(&I))
2940 exact = ExactOp->isExact();
2943 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2948 void SelectionDAGBuilder::visitSDiv(const User &I) {
2949 SDValue Op1 = getValue(I.getOperand(0));
2950 SDValue Op2 = getValue(I.getOperand(1));
2952 // Turn exact SDivs into multiplications.
2953 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2955 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2956 !isa<ConstantSDNode>(Op1) &&
2957 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2958 setValue(&I, DAG.getTargetLoweringInfo()
2959 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2961 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2965 void SelectionDAGBuilder::visitICmp(const User &I) {
2966 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2967 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2968 predicate = IC->getPredicate();
2969 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2970 predicate = ICmpInst::Predicate(IC->getPredicate());
2971 SDValue Op1 = getValue(I.getOperand(0));
2972 SDValue Op2 = getValue(I.getOperand(1));
2973 ISD::CondCode Opcode = getICmpCondCode(predicate);
2975 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2976 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2979 void SelectionDAGBuilder::visitFCmp(const User &I) {
2980 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2981 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2982 predicate = FC->getPredicate();
2983 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2984 predicate = FCmpInst::Predicate(FC->getPredicate());
2985 SDValue Op1 = getValue(I.getOperand(0));
2986 SDValue Op2 = getValue(I.getOperand(1));
2987 ISD::CondCode Condition = getFCmpCondCode(predicate);
2988 if (TM.Options.NoNaNsFPMath)
2989 Condition = getFCmpCodeWithoutNaN(Condition);
2990 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2991 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2994 void SelectionDAGBuilder::visitSelect(const User &I) {
2995 SmallVector<EVT, 4> ValueVTs;
2996 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2997 unsigned NumValues = ValueVTs.size();
2998 if (NumValues == 0) return;
3000 SmallVector<SDValue, 4> Values(NumValues);
3001 SDValue Cond = getValue(I.getOperand(0));
3002 SDValue TrueVal = getValue(I.getOperand(1));
3003 SDValue FalseVal = getValue(I.getOperand(2));
3004 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
3005 ISD::VSELECT : ISD::SELECT;
3007 for (unsigned i = 0; i != NumValues; ++i)
3008 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
3009 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
3011 SDValue(TrueVal.getNode(),
3012 TrueVal.getResNo() + i),
3013 SDValue(FalseVal.getNode(),
3014 FalseVal.getResNo() + i));
3016 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3017 DAG.getVTList(ValueVTs), Values));
3020 void SelectionDAGBuilder::visitTrunc(const User &I) {
3021 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3022 SDValue N = getValue(I.getOperand(0));
3023 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3024 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3027 void SelectionDAGBuilder::visitZExt(const User &I) {
3028 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3029 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3030 SDValue N = getValue(I.getOperand(0));
3031 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3032 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3035 void SelectionDAGBuilder::visitSExt(const User &I) {
3036 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3037 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3038 SDValue N = getValue(I.getOperand(0));
3039 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3040 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3043 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3044 // FPTrunc is never a no-op cast, no need to check
3045 SDValue N = getValue(I.getOperand(0));
3046 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3047 EVT DestVT = TLI.getValueType(I.getType());
3048 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3049 DAG.getTargetConstant(0, TLI.getPointerTy())));
3052 void SelectionDAGBuilder::visitFPExt(const User &I) {
3053 // FPExt is never a no-op cast, no need to check
3054 SDValue N = getValue(I.getOperand(0));
3055 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3056 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3059 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3060 // FPToUI is never a no-op cast, no need to check
3061 SDValue N = getValue(I.getOperand(0));
3062 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3063 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3066 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3067 // FPToSI is never a no-op cast, no need to check
3068 SDValue N = getValue(I.getOperand(0));
3069 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3070 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3073 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3074 // UIToFP is never a no-op cast, no need to check
3075 SDValue N = getValue(I.getOperand(0));
3076 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3077 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3080 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3081 // SIToFP is never a no-op cast, no need to check
3082 SDValue N = getValue(I.getOperand(0));
3083 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3084 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3087 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3088 // What to do depends on the size of the integer and the size of the pointer.
3089 // We can either truncate, zero extend, or no-op, accordingly.
3090 SDValue N = getValue(I.getOperand(0));
3091 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3092 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3095 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3096 // What to do depends on the size of the integer and the size of the pointer.
3097 // We can either truncate, zero extend, or no-op, accordingly.
3098 SDValue N = getValue(I.getOperand(0));
3099 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3100 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3103 void SelectionDAGBuilder::visitBitCast(const User &I) {
3104 SDValue N = getValue(I.getOperand(0));
3105 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3107 // BitCast assures us that source and destination are the same size so this is
3108 // either a BITCAST or a no-op.
3109 if (DestVT != N.getValueType())
3110 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3111 DestVT, N)); // convert types.
3112 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3113 // might fold any kind of constant expression to an integer constant and that
3114 // is not what we are looking for. Only regcognize a bitcast of a genuine
3115 // constant integer as an opaque constant.
3116 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3117 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3120 setValue(&I, N); // noop cast.
3123 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3124 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3125 const Value *SV = I.getOperand(0);
3126 SDValue N = getValue(SV);
3127 EVT DestVT = TLI.getValueType(I.getType());
3129 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3130 unsigned DestAS = I.getType()->getPointerAddressSpace();
3132 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3133 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3138 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3140 SDValue InVec = getValue(I.getOperand(0));
3141 SDValue InVal = getValue(I.getOperand(1));
3142 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3143 getCurSDLoc(), TLI.getVectorIdxTy());
3144 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3145 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3148 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3149 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3150 SDValue InVec = getValue(I.getOperand(0));
3151 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3152 getCurSDLoc(), TLI.getVectorIdxTy());
3153 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3154 TLI.getValueType(I.getType()), InVec, InIdx));
3157 // Utility for visitShuffleVector - Return true if every element in Mask,
3158 // beginning from position Pos and ending in Pos+Size, falls within the
3159 // specified sequential range [L, L+Pos). or is undef.
3160 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3161 unsigned Pos, unsigned Size, int Low) {
3162 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3163 if (Mask[i] >= 0 && Mask[i] != Low)
3168 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3169 SDValue Src1 = getValue(I.getOperand(0));
3170 SDValue Src2 = getValue(I.getOperand(1));
3172 SmallVector<int, 8> Mask;
3173 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3174 unsigned MaskNumElts = Mask.size();
3176 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3177 EVT VT = TLI.getValueType(I.getType());
3178 EVT SrcVT = Src1.getValueType();
3179 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3181 if (SrcNumElts == MaskNumElts) {
3182 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3187 // Normalize the shuffle vector since mask and vector length don't match.
3188 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3189 // Mask is longer than the source vectors and is a multiple of the source
3190 // vectors. We can use concatenate vector to make the mask and vectors
3192 if (SrcNumElts*2 == MaskNumElts) {
3193 // First check for Src1 in low and Src2 in high
3194 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3195 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3196 // The shuffle is concatenating two vectors together.
3197 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3201 // Then check for Src2 in low and Src1 in high
3202 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3203 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3204 // The shuffle is concatenating two vectors together.
3205 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3211 // Pad both vectors with undefs to make them the same length as the mask.
3212 unsigned NumConcat = MaskNumElts / SrcNumElts;
3213 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3214 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3215 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3217 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3218 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3222 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3223 getCurSDLoc(), VT, MOps1);
3224 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3225 getCurSDLoc(), VT, MOps2);
3227 // Readjust mask for new input vector length.
3228 SmallVector<int, 8> MappedOps;
3229 for (unsigned i = 0; i != MaskNumElts; ++i) {
3231 if (Idx >= (int)SrcNumElts)
3232 Idx -= SrcNumElts - MaskNumElts;
3233 MappedOps.push_back(Idx);
3236 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3241 if (SrcNumElts > MaskNumElts) {
3242 // Analyze the access pattern of the vector to see if we can extract
3243 // two subvectors and do the shuffle. The analysis is done by calculating
3244 // the range of elements the mask access on both vectors.
3245 int MinRange[2] = { static_cast<int>(SrcNumElts),
3246 static_cast<int>(SrcNumElts)};
3247 int MaxRange[2] = {-1, -1};
3249 for (unsigned i = 0; i != MaskNumElts; ++i) {
3255 if (Idx >= (int)SrcNumElts) {
3259 if (Idx > MaxRange[Input])
3260 MaxRange[Input] = Idx;
3261 if (Idx < MinRange[Input])
3262 MinRange[Input] = Idx;
3265 // Check if the access is smaller than the vector size and can we find
3266 // a reasonable extract index.
3267 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3269 int StartIdx[2]; // StartIdx to extract from
3270 for (unsigned Input = 0; Input < 2; ++Input) {
3271 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3272 RangeUse[Input] = 0; // Unused
3273 StartIdx[Input] = 0;
3277 // Find a good start index that is a multiple of the mask length. Then
3278 // see if the rest of the elements are in range.
3279 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3280 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3281 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3282 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3285 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3286 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3289 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3290 // Extract appropriate subvector and generate a vector shuffle
3291 for (unsigned Input = 0; Input < 2; ++Input) {
3292 SDValue &Src = Input == 0 ? Src1 : Src2;
3293 if (RangeUse[Input] == 0)
3294 Src = DAG.getUNDEF(VT);
3297 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3298 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3301 // Calculate new mask.
3302 SmallVector<int, 8> MappedOps;
3303 for (unsigned i = 0; i != MaskNumElts; ++i) {
3306 if (Idx < (int)SrcNumElts)
3309 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3311 MappedOps.push_back(Idx);
3314 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3320 // We can't use either concat vectors or extract subvectors so fall back to
3321 // replacing the shuffle with extract and build vector.
3322 // to insert and build vector.
3323 EVT EltVT = VT.getVectorElementType();
3324 EVT IdxVT = TLI.getVectorIdxTy();
3325 SmallVector<SDValue,8> Ops;
3326 for (unsigned i = 0; i != MaskNumElts; ++i) {
3331 Res = DAG.getUNDEF(EltVT);
3333 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3334 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3336 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3337 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3343 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3346 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3347 const Value *Op0 = I.getOperand(0);
3348 const Value *Op1 = I.getOperand(1);
3349 Type *AggTy = I.getType();
3350 Type *ValTy = Op1->getType();
3351 bool IntoUndef = isa<UndefValue>(Op0);
3352 bool FromUndef = isa<UndefValue>(Op1);
3354 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3357 SmallVector<EVT, 4> AggValueVTs;
3358 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3359 SmallVector<EVT, 4> ValValueVTs;
3360 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3362 unsigned NumAggValues = AggValueVTs.size();
3363 unsigned NumValValues = ValValueVTs.size();
3364 SmallVector<SDValue, 4> Values(NumAggValues);
3366 // Ignore an insertvalue that produces an empty object
3367 if (!NumAggValues) {
3368 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3372 SDValue Agg = getValue(Op0);
3374 // Copy the beginning value(s) from the original aggregate.
3375 for (; i != LinearIndex; ++i)
3376 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3377 SDValue(Agg.getNode(), Agg.getResNo() + i);
3378 // Copy values from the inserted value(s).
3380 SDValue Val = getValue(Op1);
3381 for (; i != LinearIndex + NumValValues; ++i)
3382 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3383 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3385 // Copy remaining value(s) from the original aggregate.
3386 for (; i != NumAggValues; ++i)
3387 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3388 SDValue(Agg.getNode(), Agg.getResNo() + i);
3390 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3391 DAG.getVTList(AggValueVTs), Values));
3394 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3395 const Value *Op0 = I.getOperand(0);
3396 Type *AggTy = Op0->getType();
3397 Type *ValTy = I.getType();
3398 bool OutOfUndef = isa<UndefValue>(Op0);
3400 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3403 SmallVector<EVT, 4> ValValueVTs;
3404 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3406 unsigned NumValValues = ValValueVTs.size();
3408 // Ignore a extractvalue that produces an empty object
3409 if (!NumValValues) {
3410 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3414 SmallVector<SDValue, 4> Values(NumValValues);
3416 SDValue Agg = getValue(Op0);
3417 // Copy out the selected value(s).
3418 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3419 Values[i - LinearIndex] =
3421 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3422 SDValue(Agg.getNode(), Agg.getResNo() + i);
3424 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3425 DAG.getVTList(ValValueVTs), Values));
3428 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3429 Value *Op0 = I.getOperand(0);
3430 // Note that the pointer operand may be a vector of pointers. Take the scalar
3431 // element which holds a pointer.
3432 Type *Ty = Op0->getType()->getScalarType();
3433 unsigned AS = Ty->getPointerAddressSpace();
3434 SDValue N = getValue(Op0);
3436 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3438 const Value *Idx = *OI;
3439 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3440 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3443 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3444 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3445 DAG.getConstant(Offset, N.getValueType()));
3448 Ty = StTy->getElementType(Field);
3450 Ty = cast<SequentialType>(Ty)->getElementType();
3451 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
3452 unsigned PtrSize = PtrTy.getSizeInBits();
3453 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3455 // If this is a constant subscript, handle it quickly.
3456 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
3459 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3460 SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
3461 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
3465 // N = N + Idx * ElementSize;
3466 SDValue IdxN = getValue(Idx);
3468 // If the index is smaller or larger than intptr_t, truncate or extend
3470 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3472 // If this is a multiply by a power of two, turn it into a shl
3473 // immediately. This is a very common case.
3474 if (ElementSize != 1) {
3475 if (ElementSize.isPowerOf2()) {
3476 unsigned Amt = ElementSize.logBase2();
3477 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3478 N.getValueType(), IdxN,
3479 DAG.getConstant(Amt, IdxN.getValueType()));
3481 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3482 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3483 N.getValueType(), IdxN, Scale);
3487 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3488 N.getValueType(), N, IdxN);
3495 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3496 // If this is a fixed sized alloca in the entry block of the function,
3497 // allocate it statically on the stack.
3498 if (FuncInfo.StaticAllocaMap.count(&I))
3499 return; // getValue will auto-populate this.
3501 Type *Ty = I.getAllocatedType();
3502 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3503 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3505 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3508 SDValue AllocSize = getValue(I.getArraySize());
3510 EVT IntPtr = TLI.getPointerTy();
3511 if (AllocSize.getValueType() != IntPtr)
3512 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3514 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3516 DAG.getConstant(TySize, IntPtr));
3518 // Handle alignment. If the requested alignment is less than or equal to
3519 // the stack alignment, ignore it. If the size is greater than or equal to
3520 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3521 unsigned StackAlign =
3522 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3523 if (Align <= StackAlign)
3526 // Round the size of the allocation up to the stack alignment size
3527 // by add SA-1 to the size.
3528 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3529 AllocSize.getValueType(), AllocSize,
3530 DAG.getIntPtrConstant(StackAlign-1));
3532 // Mask out the low bits for alignment purposes.
3533 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3534 AllocSize.getValueType(), AllocSize,
3535 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3537 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3538 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3539 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3541 DAG.setRoot(DSA.getValue(1));
3543 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3546 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3548 return visitAtomicLoad(I);
3550 const Value *SV = I.getOperand(0);
3551 SDValue Ptr = getValue(SV);
3553 Type *Ty = I.getType();
3555 bool isVolatile = I.isVolatile();
3556 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3557 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3558 unsigned Alignment = I.getAlignment();
3561 I.getAAMetadata(AAInfo);
3562 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3565 SmallVector<EVT, 4> ValueVTs;
3566 SmallVector<uint64_t, 4> Offsets;
3567 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3568 unsigned NumValues = ValueVTs.size();
3573 bool ConstantMemory = false;
3574 if (isVolatile || NumValues > MaxParallelChains)
3575 // Serialize volatile loads with other side effects.
3577 else if (AA->pointsToConstantMemory(
3578 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3579 // Do not serialize (non-volatile) loads of constant memory with anything.
3580 Root = DAG.getEntryNode();
3581 ConstantMemory = true;
3583 // Do not serialize non-volatile loads against each other.
3584 Root = DAG.getRoot();
3588 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3590 SmallVector<SDValue, 4> Values(NumValues);
3591 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3593 EVT PtrVT = Ptr.getValueType();
3594 unsigned ChainI = 0;
3595 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3596 // Serializing loads here may result in excessive register pressure, and
3597 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3598 // could recover a bit by hoisting nodes upward in the chain by recognizing
3599 // they are side-effect free or do not alias. The optimizer should really
3600 // avoid this case by converting large object/array copies to llvm.memcpy
3601 // (MaxParallelChains should always remain as failsafe).
3602 if (ChainI == MaxParallelChains) {
3603 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3604 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3605 makeArrayRef(Chains.data(), ChainI));
3609 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3611 DAG.getConstant(Offsets[i], PtrVT));
3612 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3613 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3614 isNonTemporal, isInvariant, Alignment, AAInfo,
3618 Chains[ChainI] = L.getValue(1);
3621 if (!ConstantMemory) {
3622 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3623 makeArrayRef(Chains.data(), ChainI));
3627 PendingLoads.push_back(Chain);
3630 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3631 DAG.getVTList(ValueVTs), Values));
3634 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3636 return visitAtomicStore(I);
3638 const Value *SrcV = I.getOperand(0);
3639 const Value *PtrV = I.getOperand(1);
3641 SmallVector<EVT, 4> ValueVTs;
3642 SmallVector<uint64_t, 4> Offsets;
3643 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3644 ValueVTs, &Offsets);
3645 unsigned NumValues = ValueVTs.size();
3649 // Get the lowered operands. Note that we do this after
3650 // checking if NumResults is zero, because with zero results
3651 // the operands won't have values in the map.
3652 SDValue Src = getValue(SrcV);
3653 SDValue Ptr = getValue(PtrV);
3655 SDValue Root = getRoot();
3656 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3658 EVT PtrVT = Ptr.getValueType();
3659 bool isVolatile = I.isVolatile();
3660 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3661 unsigned Alignment = I.getAlignment();
3664 I.getAAMetadata(AAInfo);
3666 unsigned ChainI = 0;
3667 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3668 // See visitLoad comments.
3669 if (ChainI == MaxParallelChains) {
3670 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3671 makeArrayRef(Chains.data(), ChainI));
3675 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3676 DAG.getConstant(Offsets[i], PtrVT));
3677 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3678 SDValue(Src.getNode(), Src.getResNo() + i),
3679 Add, MachinePointerInfo(PtrV, Offsets[i]),
3680 isVolatile, isNonTemporal, Alignment, AAInfo);
3681 Chains[ChainI] = St;
3684 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3685 makeArrayRef(Chains.data(), ChainI));
3686 DAG.setRoot(StoreNode);
3689 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3690 SDLoc sdl = getCurSDLoc();
3692 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3693 Value *PtrOperand = I.getArgOperand(1);
3694 SDValue Ptr = getValue(PtrOperand);
3695 SDValue Src0 = getValue(I.getArgOperand(0));
3696 SDValue Mask = getValue(I.getArgOperand(3));
3697 EVT VT = Src0.getValueType();
3698 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3700 Alignment = DAG.getEVTAlignment(VT);
3703 I.getAAMetadata(AAInfo);
3705 MachineMemOperand *MMO =
3706 DAG.getMachineFunction().
3707 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3708 MachineMemOperand::MOStore, VT.getStoreSize(),
3710 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3712 DAG.setRoot(StoreNode);
3713 setValue(&I, StoreNode);
3716 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3717 SDLoc sdl = getCurSDLoc();
3719 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3720 Value *PtrOperand = I.getArgOperand(0);
3721 SDValue Ptr = getValue(PtrOperand);
3722 SDValue Src0 = getValue(I.getArgOperand(3));
3723 SDValue Mask = getValue(I.getArgOperand(2));
3725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3726 EVT VT = TLI.getValueType(I.getType());
3727 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3729 Alignment = DAG.getEVTAlignment(VT);
3732 I.getAAMetadata(AAInfo);
3733 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3735 SDValue InChain = DAG.getRoot();
3736 if (AA->pointsToConstantMemory(
3737 AliasAnalysis::Location(PtrOperand,
3738 AA->getTypeStoreSize(I.getType()),
3740 // Do not serialize (non-volatile) loads of constant memory with anything.
3741 InChain = DAG.getEntryNode();
3744 MachineMemOperand *MMO =
3745 DAG.getMachineFunction().
3746 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3747 MachineMemOperand::MOLoad, VT.getStoreSize(),
3748 Alignment, AAInfo, Ranges);
3750 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3752 SDValue OutChain = Load.getValue(1);
3753 DAG.setRoot(OutChain);
3757 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3758 SDLoc dl = getCurSDLoc();
3759 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3760 AtomicOrdering FailureOrder = I.getFailureOrdering();
3761 SynchronizationScope Scope = I.getSynchScope();
3763 SDValue InChain = getRoot();
3765 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3766 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3767 SDValue L = DAG.getAtomicCmpSwap(
3768 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3769 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3770 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3771 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3773 SDValue OutChain = L.getValue(2);
3776 DAG.setRoot(OutChain);
3779 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3780 SDLoc dl = getCurSDLoc();
3782 switch (I.getOperation()) {
3783 default: llvm_unreachable("Unknown atomicrmw operation");
3784 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3785 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3786 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3787 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3788 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3789 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3790 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3791 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3792 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3793 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3794 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3796 AtomicOrdering Order = I.getOrdering();
3797 SynchronizationScope Scope = I.getSynchScope();
3799 SDValue InChain = getRoot();
3802 DAG.getAtomic(NT, dl,
3803 getValue(I.getValOperand()).getSimpleValueType(),
3805 getValue(I.getPointerOperand()),
3806 getValue(I.getValOperand()),
3807 I.getPointerOperand(),
3808 /* Alignment=*/ 0, Order, Scope);
3810 SDValue OutChain = L.getValue(1);
3813 DAG.setRoot(OutChain);
3816 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3817 SDLoc dl = getCurSDLoc();
3818 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3821 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3822 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3823 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3826 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3827 SDLoc dl = getCurSDLoc();
3828 AtomicOrdering Order = I.getOrdering();
3829 SynchronizationScope Scope = I.getSynchScope();
3831 SDValue InChain = getRoot();
3833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3834 EVT VT = TLI.getValueType(I.getType());
3836 if (I.getAlignment() < VT.getSizeInBits() / 8)
3837 report_fatal_error("Cannot generate unaligned atomic load");
3839 MachineMemOperand *MMO =
3840 DAG.getMachineFunction().
3841 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3842 MachineMemOperand::MOVolatile |
3843 MachineMemOperand::MOLoad,
3845 I.getAlignment() ? I.getAlignment() :
3846 DAG.getEVTAlignment(VT));
3848 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3850 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3851 getValue(I.getPointerOperand()), MMO,
3854 SDValue OutChain = L.getValue(1);
3857 DAG.setRoot(OutChain);
3860 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3861 SDLoc dl = getCurSDLoc();
3863 AtomicOrdering Order = I.getOrdering();
3864 SynchronizationScope Scope = I.getSynchScope();
3866 SDValue InChain = getRoot();
3868 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3869 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3871 if (I.getAlignment() < VT.getSizeInBits() / 8)
3872 report_fatal_error("Cannot generate unaligned atomic store");
3875 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3877 getValue(I.getPointerOperand()),
3878 getValue(I.getValueOperand()),
3879 I.getPointerOperand(), I.getAlignment(),
3882 DAG.setRoot(OutChain);
3885 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3887 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3888 unsigned Intrinsic) {
3889 bool HasChain = !I.doesNotAccessMemory();
3890 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3892 // Build the operand list.
3893 SmallVector<SDValue, 8> Ops;
3894 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3896 // We don't need to serialize loads against other loads.
3897 Ops.push_back(DAG.getRoot());
3899 Ops.push_back(getRoot());
3903 // Info is set by getTgtMemInstrinsic
3904 TargetLowering::IntrinsicInfo Info;
3905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3906 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3908 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3909 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3910 Info.opc == ISD::INTRINSIC_W_CHAIN)
3911 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3913 // Add all operands of the call to the operand list.
3914 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3915 SDValue Op = getValue(I.getArgOperand(i));
3919 SmallVector<EVT, 4> ValueVTs;
3920 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3923 ValueVTs.push_back(MVT::Other);
3925 SDVTList VTs = DAG.getVTList(ValueVTs);
3929 if (IsTgtIntrinsic) {
3930 // This is target intrinsic that touches memory
3931 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3932 VTs, Ops, Info.memVT,
3933 MachinePointerInfo(Info.ptrVal, Info.offset),
3934 Info.align, Info.vol,
3935 Info.readMem, Info.writeMem, Info.size);
3936 } else if (!HasChain) {
3937 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3938 } else if (!I.getType()->isVoidTy()) {
3939 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3941 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3945 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3947 PendingLoads.push_back(Chain);
3952 if (!I.getType()->isVoidTy()) {
3953 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3954 EVT VT = TLI.getValueType(PTy);
3955 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3958 setValue(&I, Result);
3962 /// GetSignificand - Get the significand and build it into a floating-point
3963 /// number with exponent of 1:
3965 /// Op = (Op & 0x007fffff) | 0x3f800000;
3967 /// where Op is the hexadecimal representation of floating point value.
3969 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3970 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3971 DAG.getConstant(0x007fffff, MVT::i32));
3972 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3973 DAG.getConstant(0x3f800000, MVT::i32));
3974 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3977 /// GetExponent - Get the exponent:
3979 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3981 /// where Op is the hexadecimal representation of floating point value.
3983 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3985 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3986 DAG.getConstant(0x7f800000, MVT::i32));
3987 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3988 DAG.getConstant(23, TLI.getPointerTy()));
3989 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3990 DAG.getConstant(127, MVT::i32));
3991 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3994 /// getF32Constant - Get 32-bit floating point constant.
3996 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3997 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
4001 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
4002 SelectionDAG &DAG) {
4003 // IntegerPartOfX = ((int32_t)(t0);
4004 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4006 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4007 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4008 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4010 // IntegerPartOfX <<= 23;
4011 IntegerPartOfX = DAG.getNode(
4012 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4013 DAG.getConstant(23, DAG.getTargetLoweringInfo().getPointerTy()));
4015 SDValue TwoToFractionalPartOfX;
4016 if (LimitFloatPrecision <= 6) {
4017 // For floating-point precision of 6:
4019 // TwoToFractionalPartOfX =
4021 // (0.735607626f + 0.252464424f * x) * x;
4023 // error 0.0144103317, which is 6 bits
4024 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4025 getF32Constant(DAG, 0x3e814304));
4026 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4027 getF32Constant(DAG, 0x3f3c50c8));
4028 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4029 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4030 getF32Constant(DAG, 0x3f7f5e7e));
4031 } else if (LimitFloatPrecision <= 12) {
4032 // For floating-point precision of 12:
4034 // TwoToFractionalPartOfX =
4037 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4039 // error 0.000107046256, which is 13 to 14 bits
4040 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4041 getF32Constant(DAG, 0x3da235e3));
4042 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4043 getF32Constant(DAG, 0x3e65b8f3));
4044 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4045 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4046 getF32Constant(DAG, 0x3f324b07));
4047 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4048 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4049 getF32Constant(DAG, 0x3f7ff8fd));
4050 } else { // LimitFloatPrecision <= 18
4051 // For floating-point precision of 18:
4053 // TwoToFractionalPartOfX =
4057 // (0.554906021e-1f +
4058 // (0.961591928e-2f +
4059 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4060 // error 2.47208000*10^(-7), which is better than 18 bits
4061 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4062 getF32Constant(DAG, 0x3924b03e));
4063 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4064 getF32Constant(DAG, 0x3ab24b87));
4065 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4066 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4067 getF32Constant(DAG, 0x3c1d8c17));
4068 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4069 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4070 getF32Constant(DAG, 0x3d634a1d));
4071 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4072 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4073 getF32Constant(DAG, 0x3e75fe14));
4074 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4075 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4076 getF32Constant(DAG, 0x3f317234));
4077 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4078 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4079 getF32Constant(DAG, 0x3f800000));
4082 // Add the exponent into the result in integer domain.
4083 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4084 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4085 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4088 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4089 /// limited-precision mode.
4090 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4091 const TargetLowering &TLI) {
4092 if (Op.getValueType() == MVT::f32 &&
4093 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4095 // Put the exponent in the right bit position for later addition to the
4098 // #define LOG2OFe 1.4426950f
4099 // t0 = Op * LOG2OFe
4100 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4101 getF32Constant(DAG, 0x3fb8aa3b));
4102 return getLimitedPrecisionExp2(t0, dl, DAG);
4105 // No special expansion.
4106 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4109 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4110 /// limited-precision mode.
4111 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4112 const TargetLowering &TLI) {
4113 if (Op.getValueType() == MVT::f32 &&
4114 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4115 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4117 // Scale the exponent by log(2) [0.69314718f].
4118 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4119 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4120 getF32Constant(DAG, 0x3f317218));
4122 // Get the significand and build it into a floating-point number with
4124 SDValue X = GetSignificand(DAG, Op1, dl);
4126 SDValue LogOfMantissa;
4127 if (LimitFloatPrecision <= 6) {
4128 // For floating-point precision of 6:
4132 // (1.4034025f - 0.23903021f * x) * x;
4134 // error 0.0034276066, which is better than 8 bits
4135 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4136 getF32Constant(DAG, 0xbe74c456));
4137 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4138 getF32Constant(DAG, 0x3fb3a2b1));
4139 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4140 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4141 getF32Constant(DAG, 0x3f949a29));
4142 } else if (LimitFloatPrecision <= 12) {
4143 // For floating-point precision of 12:
4149 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4151 // error 0.000061011436, which is 14 bits
4152 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4153 getF32Constant(DAG, 0xbd67b6d6));
4154 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4155 getF32Constant(DAG, 0x3ee4f4b8));
4156 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4157 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4158 getF32Constant(DAG, 0x3fbc278b));
4159 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4160 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4161 getF32Constant(DAG, 0x40348e95));
4162 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4163 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4164 getF32Constant(DAG, 0x3fdef31a));
4165 } else { // LimitFloatPrecision <= 18
4166 // For floating-point precision of 18:
4174 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4176 // error 0.0000023660568, which is better than 18 bits
4177 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4178 getF32Constant(DAG, 0xbc91e5ac));
4179 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4180 getF32Constant(DAG, 0x3e4350aa));
4181 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4182 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4183 getF32Constant(DAG, 0x3f60d3e3));
4184 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4185 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4186 getF32Constant(DAG, 0x4011cdf0));
4187 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4188 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4189 getF32Constant(DAG, 0x406cfd1c));
4190 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4191 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4192 getF32Constant(DAG, 0x408797cb));
4193 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4194 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4195 getF32Constant(DAG, 0x4006dcab));
4198 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4201 // No special expansion.
4202 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4205 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4206 /// limited-precision mode.
4207 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4208 const TargetLowering &TLI) {
4209 if (Op.getValueType() == MVT::f32 &&
4210 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4211 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4213 // Get the exponent.
4214 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4216 // Get the significand and build it into a floating-point number with
4218 SDValue X = GetSignificand(DAG, Op1, dl);
4220 // Different possible minimax approximations of significand in
4221 // floating-point for various degrees of accuracy over [1,2].
4222 SDValue Log2ofMantissa;
4223 if (LimitFloatPrecision <= 6) {
4224 // For floating-point precision of 6:
4226 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4228 // error 0.0049451742, which is more than 7 bits
4229 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4230 getF32Constant(DAG, 0xbeb08fe0));
4231 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4232 getF32Constant(DAG, 0x40019463));
4233 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4234 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4235 getF32Constant(DAG, 0x3fd6633d));
4236 } else if (LimitFloatPrecision <= 12) {
4237 // For floating-point precision of 12:
4243 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4245 // error 0.0000876136000, which is better than 13 bits
4246 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4247 getF32Constant(DAG, 0xbda7262e));
4248 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4249 getF32Constant(DAG, 0x3f25280b));
4250 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4251 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4252 getF32Constant(DAG, 0x4007b923));
4253 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4254 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4255 getF32Constant(DAG, 0x40823e2f));
4256 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4257 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4258 getF32Constant(DAG, 0x4020d29c));
4259 } else { // LimitFloatPrecision <= 18
4260 // For floating-point precision of 18:
4269 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4271 // error 0.0000018516, which is better than 18 bits
4272 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4273 getF32Constant(DAG, 0xbcd2769e));
4274 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4275 getF32Constant(DAG, 0x3e8ce0b9));
4276 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4277 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4278 getF32Constant(DAG, 0x3fa22ae7));
4279 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4280 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4281 getF32Constant(DAG, 0x40525723));
4282 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4283 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4284 getF32Constant(DAG, 0x40aaf200));
4285 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4286 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4287 getF32Constant(DAG, 0x40c39dad));
4288 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4289 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4290 getF32Constant(DAG, 0x4042902c));
4293 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4296 // No special expansion.
4297 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4300 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4301 /// limited-precision mode.
4302 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4303 const TargetLowering &TLI) {
4304 if (Op.getValueType() == MVT::f32 &&
4305 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4306 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4308 // Scale the exponent by log10(2) [0.30102999f].
4309 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4310 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4311 getF32Constant(DAG, 0x3e9a209a));
4313 // Get the significand and build it into a floating-point number with
4315 SDValue X = GetSignificand(DAG, Op1, dl);
4317 SDValue Log10ofMantissa;
4318 if (LimitFloatPrecision <= 6) {
4319 // For floating-point precision of 6:
4321 // Log10ofMantissa =
4323 // (0.60948995f - 0.10380950f * x) * x;
4325 // error 0.0014886165, which is 6 bits
4326 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4327 getF32Constant(DAG, 0xbdd49a13));
4328 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4329 getF32Constant(DAG, 0x3f1c0789));
4330 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4331 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4332 getF32Constant(DAG, 0x3f011300));
4333 } else if (LimitFloatPrecision <= 12) {
4334 // For floating-point precision of 12:
4336 // Log10ofMantissa =
4339 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4341 // error 0.00019228036, which is better than 12 bits
4342 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4343 getF32Constant(DAG, 0x3d431f31));
4344 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4345 getF32Constant(DAG, 0x3ea21fb2));
4346 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4347 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4348 getF32Constant(DAG, 0x3f6ae232));
4349 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4350 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4351 getF32Constant(DAG, 0x3f25f7c3));
4352 } else { // LimitFloatPrecision <= 18
4353 // For floating-point precision of 18:
4355 // Log10ofMantissa =
4360 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4362 // error 0.0000037995730, which is better than 18 bits
4363 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4364 getF32Constant(DAG, 0x3c5d51ce));
4365 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4366 getF32Constant(DAG, 0x3e00685a));
4367 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4368 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4369 getF32Constant(DAG, 0x3efb6798));
4370 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4371 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4372 getF32Constant(DAG, 0x3f88d192));
4373 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4374 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4375 getF32Constant(DAG, 0x3fc4316c));
4376 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4377 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4378 getF32Constant(DAG, 0x3f57ce70));
4381 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4384 // No special expansion.
4385 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4388 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4389 /// limited-precision mode.
4390 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4391 const TargetLowering &TLI) {
4392 if (Op.getValueType() == MVT::f32 &&
4393 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4394 return getLimitedPrecisionExp2(Op, dl, DAG);
4396 // No special expansion.
4397 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4400 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4401 /// limited-precision mode with x == 10.0f.
4402 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4403 SelectionDAG &DAG, const TargetLowering &TLI) {
4404 bool IsExp10 = false;
4405 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4406 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4407 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4409 IsExp10 = LHSC->isExactlyValue(Ten);
4414 // Put the exponent in the right bit position for later addition to the
4417 // #define LOG2OF10 3.3219281f
4418 // t0 = Op * LOG2OF10;
4419 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4420 getF32Constant(DAG, 0x40549a78));
4421 return getLimitedPrecisionExp2(t0, dl, DAG);
4424 // No special expansion.
4425 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4429 /// ExpandPowI - Expand a llvm.powi intrinsic.
4430 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4431 SelectionDAG &DAG) {
4432 // If RHS is a constant, we can expand this out to a multiplication tree,
4433 // otherwise we end up lowering to a call to __powidf2 (for example). When
4434 // optimizing for size, we only want to do this if the expansion would produce
4435 // a small number of multiplies, otherwise we do the full expansion.
4436 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4437 // Get the exponent as a positive value.
4438 unsigned Val = RHSC->getSExtValue();
4439 if ((int)Val < 0) Val = -Val;
4441 // powi(x, 0) -> 1.0
4443 return DAG.getConstantFP(1.0, LHS.getValueType());
4445 const Function *F = DAG.getMachineFunction().getFunction();
4446 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
4447 // If optimizing for size, don't insert too many multiplies. This
4448 // inserts up to 5 multiplies.
4449 countPopulation(Val) + Log2_32(Val) < 7) {
4450 // We use the simple binary decomposition method to generate the multiply
4451 // sequence. There are more optimal ways to do this (for example,
4452 // powi(x,15) generates one more multiply than it should), but this has
4453 // the benefit of being both really simple and much better than a libcall.
4454 SDValue Res; // Logically starts equal to 1.0
4455 SDValue CurSquare = LHS;
4459 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4461 Res = CurSquare; // 1.0*CurSquare.
4464 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4465 CurSquare, CurSquare);
4469 // If the original was negative, invert the result, producing 1/(x*x*x).
4470 if (RHSC->getSExtValue() < 0)
4471 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4472 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4477 // Otherwise, expand to a libcall.
4478 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4481 // getTruncatedArgReg - Find underlying register used for an truncated
4483 static unsigned getTruncatedArgReg(const SDValue &N) {
4484 if (N.getOpcode() != ISD::TRUNCATE)
4487 const SDValue &Ext = N.getOperand(0);
4488 if (Ext.getOpcode() == ISD::AssertZext ||
4489 Ext.getOpcode() == ISD::AssertSext) {
4490 const SDValue &CFR = Ext.getOperand(0);
4491 if (CFR.getOpcode() == ISD::CopyFromReg)
4492 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4493 if (CFR.getOpcode() == ISD::TRUNCATE)
4494 return getTruncatedArgReg(CFR);
4499 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4500 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4501 /// At the end of instruction selection, they will be inserted to the entry BB.
4502 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4504 MDNode *Expr, int64_t Offset,
4507 const Argument *Arg = dyn_cast<Argument>(V);
4511 MachineFunction &MF = DAG.getMachineFunction();
4512 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4514 // Ignore inlined function arguments here.
4515 DIVariable DV(Variable);
4516 if (DV.isInlinedFnArgument(MF.getFunction()))
4519 Optional<MachineOperand> Op;
4520 // Some arguments' frame index is recorded during argument lowering.
4521 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4522 Op = MachineOperand::CreateFI(FI);
4524 if (!Op && N.getNode()) {
4526 if (N.getOpcode() == ISD::CopyFromReg)
4527 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4529 Reg = getTruncatedArgReg(N);
4530 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4531 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4532 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4537 Op = MachineOperand::CreateReg(Reg, false);
4541 // Check if ValueMap has reg number.
4542 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4543 if (VMI != FuncInfo.ValueMap.end())
4544 Op = MachineOperand::CreateReg(VMI->second, false);
4547 if (!Op && N.getNode())
4548 // Check if frame index is available.
4549 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4550 if (FrameIndexSDNode *FINode =
4551 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4552 Op = MachineOperand::CreateFI(FINode->getIndex());
4558 FuncInfo.ArgDbgValues.push_back(
4559 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4560 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4562 FuncInfo.ArgDbgValues.push_back(
4563 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4566 .addMetadata(Variable)
4567 .addMetadata(Expr));
4572 // VisualStudio defines setjmp as _setjmp
4573 #if defined(_MSC_VER) && defined(setjmp) && \
4574 !defined(setjmp_undefined_for_msvc)
4575 # pragma push_macro("setjmp")
4577 # define setjmp_undefined_for_msvc
4580 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4581 /// we want to emit this as a call to a named external function, return the name
4582 /// otherwise lower it and return null.
4584 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4586 SDLoc sdl = getCurSDLoc();
4587 DebugLoc dl = getCurDebugLoc();
4590 switch (Intrinsic) {
4592 // By default, turn this into a target intrinsic node.
4593 visitTargetIntrinsic(I, Intrinsic);
4595 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4596 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4597 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4598 case Intrinsic::returnaddress:
4599 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4600 getValue(I.getArgOperand(0))));
4602 case Intrinsic::frameaddress:
4603 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4604 getValue(I.getArgOperand(0))));
4606 case Intrinsic::read_register: {
4607 Value *Reg = I.getArgOperand(0);
4609 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4610 EVT VT = TLI.getValueType(I.getType());
4611 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4614 case Intrinsic::write_register: {
4615 Value *Reg = I.getArgOperand(0);
4616 Value *RegValue = I.getArgOperand(1);
4617 SDValue Chain = getValue(RegValue).getOperand(0);
4619 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4620 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4621 RegName, getValue(RegValue)));
4624 case Intrinsic::setjmp:
4625 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4626 case Intrinsic::longjmp:
4627 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4628 case Intrinsic::memcpy: {
4629 // FIXME: this definition of "user defined address space" is x86-specific
4630 // Assert for address < 256 since we support only user defined address
4632 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4634 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4636 "Unknown address space");
4637 SDValue Op1 = getValue(I.getArgOperand(0));
4638 SDValue Op2 = getValue(I.getArgOperand(1));
4639 SDValue Op3 = getValue(I.getArgOperand(2));
4640 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4642 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4643 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4644 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4645 MachinePointerInfo(I.getArgOperand(0)),
4646 MachinePointerInfo(I.getArgOperand(1))));
4649 case Intrinsic::memset: {
4650 // FIXME: this definition of "user defined address space" is x86-specific
4651 // Assert for address < 256 since we support only user defined address
4653 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4655 "Unknown address space");
4656 SDValue Op1 = getValue(I.getArgOperand(0));
4657 SDValue Op2 = getValue(I.getArgOperand(1));
4658 SDValue Op3 = getValue(I.getArgOperand(2));
4659 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4661 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4662 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4663 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4664 MachinePointerInfo(I.getArgOperand(0))));
4667 case Intrinsic::memmove: {
4668 // FIXME: this definition of "user defined address space" is x86-specific
4669 // Assert for address < 256 since we support only user defined address
4671 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4673 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4675 "Unknown address space");
4676 SDValue Op1 = getValue(I.getArgOperand(0));
4677 SDValue Op2 = getValue(I.getArgOperand(1));
4678 SDValue Op3 = getValue(I.getArgOperand(2));
4679 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4681 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4682 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4683 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4684 MachinePointerInfo(I.getArgOperand(0)),
4685 MachinePointerInfo(I.getArgOperand(1))));
4688 case Intrinsic::dbg_declare: {
4689 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4690 MDNode *Variable = DI.getVariable();
4691 MDNode *Expression = DI.getExpression();
4692 const Value *Address = DI.getAddress();
4693 DIVariable DIVar(Variable);
4694 assert((!DIVar || DIVar.isVariable()) &&
4695 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4696 if (!Address || !DIVar) {
4697 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4701 // Check if address has undef value.
4702 if (isa<UndefValue>(Address) ||
4703 (Address->use_empty() && !isa<Argument>(Address))) {
4704 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4708 SDValue &N = NodeMap[Address];
4709 if (!N.getNode() && isa<Argument>(Address))
4710 // Check unused arguments map.
4711 N = UnusedArgNodeMap[Address];
4714 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4715 Address = BCI->getOperand(0);
4716 // Parameters are handled specially.
4718 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4719 isa<Argument>(Address));
4721 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4723 if (isParameter && !AI) {
4724 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4726 // Byval parameter. We have a frame index at this point.
4727 SDV = DAG.getFrameIndexDbgValue(
4728 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4730 // Address is an argument, so try to emit its dbg value using
4731 // virtual register info from the FuncInfo.ValueMap.
4732 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4736 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4737 true, 0, dl, SDNodeOrder);
4739 // Can't do anything with other non-AI cases yet.
4740 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4741 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4742 DEBUG(Address->dump());
4745 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4747 // If Address is an argument then try to emit its dbg value using
4748 // virtual register info from the FuncInfo.ValueMap.
4749 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4751 // If variable is pinned by a alloca in dominating bb then
4752 // use StaticAllocaMap.
4753 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4754 if (AI->getParent() != DI.getParent()) {
4755 DenseMap<const AllocaInst*, int>::iterator SI =
4756 FuncInfo.StaticAllocaMap.find(AI);
4757 if (SI != FuncInfo.StaticAllocaMap.end()) {
4758 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4759 0, dl, SDNodeOrder);
4760 DAG.AddDbgValue(SDV, nullptr, false);
4765 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4770 case Intrinsic::dbg_value: {
4771 const DbgValueInst &DI = cast<DbgValueInst>(I);
4772 DIVariable DIVar(DI.getVariable());
4773 assert((!DIVar || DIVar.isVariable()) &&
4774 "Variable in DbgValueInst should be either null or a DIVariable.");
4778 MDNode *Variable = DI.getVariable();
4779 MDNode *Expression = DI.getExpression();
4780 uint64_t Offset = DI.getOffset();
4781 const Value *V = DI.getValue();
4786 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4787 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4789 DAG.AddDbgValue(SDV, nullptr, false);
4791 // Do not use getValue() in here; we don't want to generate code at
4792 // this point if it hasn't been done yet.
4793 SDValue N = NodeMap[V];
4794 if (!N.getNode() && isa<Argument>(V))
4795 // Check unused arguments map.
4796 N = UnusedArgNodeMap[V];
4798 // A dbg.value for an alloca is always indirect.
4799 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4800 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4802 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4803 IsIndirect, Offset, dl, SDNodeOrder);
4804 DAG.AddDbgValue(SDV, N.getNode(), false);
4806 } else if (!V->use_empty() ) {
4807 // Do not call getValue(V) yet, as we don't want to generate code.
4808 // Remember it for later.
4809 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4810 DanglingDebugInfoMap[V] = DDI;
4812 // We may expand this to cover more cases. One case where we have no
4813 // data available is an unreferenced parameter.
4814 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4818 // Build a debug info table entry.
4819 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4820 V = BCI->getOperand(0);
4821 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4822 // Don't handle byval struct arguments or VLAs, for example.
4824 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4825 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4828 DenseMap<const AllocaInst*, int>::iterator SI =
4829 FuncInfo.StaticAllocaMap.find(AI);
4830 if (SI == FuncInfo.StaticAllocaMap.end())
4831 return nullptr; // VLAs.
4835 case Intrinsic::eh_typeid_for: {
4836 // Find the type id for the given typeinfo.
4837 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4838 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4839 Res = DAG.getConstant(TypeID, MVT::i32);
4844 case Intrinsic::eh_return_i32:
4845 case Intrinsic::eh_return_i64:
4846 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4847 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4850 getValue(I.getArgOperand(0)),
4851 getValue(I.getArgOperand(1))));
4853 case Intrinsic::eh_unwind_init:
4854 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4856 case Intrinsic::eh_dwarf_cfa: {
4857 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4858 TLI.getPointerTy());
4859 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4860 CfaArg.getValueType(),
4861 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4862 CfaArg.getValueType()),
4864 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4865 DAG.getConstant(0, TLI.getPointerTy()));
4866 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4870 case Intrinsic::eh_sjlj_callsite: {
4871 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4872 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4873 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4874 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4876 MMI.setCurrentCallSite(CI->getZExtValue());
4879 case Intrinsic::eh_sjlj_functioncontext: {
4880 // Get and store the index of the function context.
4881 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4883 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4884 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4885 MFI->setFunctionContextIndex(FI);
4888 case Intrinsic::eh_sjlj_setjmp: {
4891 Ops[1] = getValue(I.getArgOperand(0));
4892 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4893 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4894 setValue(&I, Op.getValue(0));
4895 DAG.setRoot(Op.getValue(1));
4898 case Intrinsic::eh_sjlj_longjmp: {
4899 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4900 getRoot(), getValue(I.getArgOperand(0))));
4904 case Intrinsic::masked_load:
4907 case Intrinsic::masked_store:
4908 visitMaskedStore(I);
4910 case Intrinsic::x86_mmx_pslli_w:
4911 case Intrinsic::x86_mmx_pslli_d:
4912 case Intrinsic::x86_mmx_pslli_q:
4913 case Intrinsic::x86_mmx_psrli_w:
4914 case Intrinsic::x86_mmx_psrli_d:
4915 case Intrinsic::x86_mmx_psrli_q:
4916 case Intrinsic::x86_mmx_psrai_w:
4917 case Intrinsic::x86_mmx_psrai_d: {
4918 SDValue ShAmt = getValue(I.getArgOperand(1));
4919 if (isa<ConstantSDNode>(ShAmt)) {
4920 visitTargetIntrinsic(I, Intrinsic);
4923 unsigned NewIntrinsic = 0;
4924 EVT ShAmtVT = MVT::v2i32;
4925 switch (Intrinsic) {
4926 case Intrinsic::x86_mmx_pslli_w:
4927 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4929 case Intrinsic::x86_mmx_pslli_d:
4930 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4932 case Intrinsic::x86_mmx_pslli_q:
4933 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4935 case Intrinsic::x86_mmx_psrli_w:
4936 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4938 case Intrinsic::x86_mmx_psrli_d:
4939 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4941 case Intrinsic::x86_mmx_psrli_q:
4942 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4944 case Intrinsic::x86_mmx_psrai_w:
4945 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4947 case Intrinsic::x86_mmx_psrai_d:
4948 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4953 // The vector shift intrinsics with scalars uses 32b shift amounts but
4954 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4956 // We must do this early because v2i32 is not a legal type.
4959 ShOps[1] = DAG.getConstant(0, MVT::i32);
4960 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4961 EVT DestVT = TLI.getValueType(I.getType());
4962 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4963 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4964 DAG.getConstant(NewIntrinsic, MVT::i32),
4965 getValue(I.getArgOperand(0)), ShAmt);
4969 case Intrinsic::x86_avx2_vinserti128: {
4970 EVT DestVT = TLI.getValueType(I.getType());
4971 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4972 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4973 ElVT.getVectorNumElements();
4975 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4976 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
4977 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
4981 case Intrinsic::x86_avx_vextractf128_pd_256:
4982 case Intrinsic::x86_avx_vextractf128_ps_256:
4983 case Intrinsic::x86_avx_vextractf128_si_256:
4984 case Intrinsic::x86_avx2_vextracti128: {
4985 EVT DestVT = TLI.getValueType(I.getType());
4986 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4987 DestVT.getVectorNumElements();
4988 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
4989 getValue(I.getArgOperand(0)),
4990 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
4994 case Intrinsic::convertff:
4995 case Intrinsic::convertfsi:
4996 case Intrinsic::convertfui:
4997 case Intrinsic::convertsif:
4998 case Intrinsic::convertuif:
4999 case Intrinsic::convertss:
5000 case Intrinsic::convertsu:
5001 case Intrinsic::convertus:
5002 case Intrinsic::convertuu: {
5003 ISD::CvtCode Code = ISD::CVT_INVALID;
5004 switch (Intrinsic) {
5005 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5006 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5007 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5008 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5009 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5010 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5011 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5012 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5013 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5014 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5016 EVT DestVT = TLI.getValueType(I.getType());
5017 const Value *Op1 = I.getArgOperand(0);
5018 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5019 DAG.getValueType(DestVT),
5020 DAG.getValueType(getValue(Op1).getValueType()),
5021 getValue(I.getArgOperand(1)),
5022 getValue(I.getArgOperand(2)),
5027 case Intrinsic::powi:
5028 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5029 getValue(I.getArgOperand(1)), DAG));
5031 case Intrinsic::log:
5032 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5034 case Intrinsic::log2:
5035 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5037 case Intrinsic::log10:
5038 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5040 case Intrinsic::exp:
5041 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5043 case Intrinsic::exp2:
5044 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5046 case Intrinsic::pow:
5047 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5048 getValue(I.getArgOperand(1)), DAG, TLI));
5050 case Intrinsic::sqrt:
5051 case Intrinsic::fabs:
5052 case Intrinsic::sin:
5053 case Intrinsic::cos:
5054 case Intrinsic::floor:
5055 case Intrinsic::ceil:
5056 case Intrinsic::trunc:
5057 case Intrinsic::rint:
5058 case Intrinsic::nearbyint:
5059 case Intrinsic::round: {
5061 switch (Intrinsic) {
5062 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5063 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5064 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5065 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5066 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5067 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5068 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5069 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5070 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5071 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5072 case Intrinsic::round: Opcode = ISD::FROUND; break;
5075 setValue(&I, DAG.getNode(Opcode, sdl,
5076 getValue(I.getArgOperand(0)).getValueType(),
5077 getValue(I.getArgOperand(0))));
5080 case Intrinsic::minnum:
5081 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5082 getValue(I.getArgOperand(0)).getValueType(),
5083 getValue(I.getArgOperand(0)),
5084 getValue(I.getArgOperand(1))));
5086 case Intrinsic::maxnum:
5087 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5088 getValue(I.getArgOperand(0)).getValueType(),
5089 getValue(I.getArgOperand(0)),
5090 getValue(I.getArgOperand(1))));
5092 case Intrinsic::copysign:
5093 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5094 getValue(I.getArgOperand(0)).getValueType(),
5095 getValue(I.getArgOperand(0)),
5096 getValue(I.getArgOperand(1))));
5098 case Intrinsic::fma:
5099 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5100 getValue(I.getArgOperand(0)).getValueType(),
5101 getValue(I.getArgOperand(0)),
5102 getValue(I.getArgOperand(1)),
5103 getValue(I.getArgOperand(2))));
5105 case Intrinsic::fmuladd: {
5106 EVT VT = TLI.getValueType(I.getType());
5107 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5108 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5109 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5110 getValue(I.getArgOperand(0)).getValueType(),
5111 getValue(I.getArgOperand(0)),
5112 getValue(I.getArgOperand(1)),
5113 getValue(I.getArgOperand(2))));
5115 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5116 getValue(I.getArgOperand(0)).getValueType(),
5117 getValue(I.getArgOperand(0)),
5118 getValue(I.getArgOperand(1)));
5119 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5120 getValue(I.getArgOperand(0)).getValueType(),
5122 getValue(I.getArgOperand(2)));
5127 case Intrinsic::convert_to_fp16:
5128 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5129 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5130 getValue(I.getArgOperand(0)),
5131 DAG.getTargetConstant(0, MVT::i32))));
5133 case Intrinsic::convert_from_fp16:
5135 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5136 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5137 getValue(I.getArgOperand(0)))));
5139 case Intrinsic::pcmarker: {
5140 SDValue Tmp = getValue(I.getArgOperand(0));
5141 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5144 case Intrinsic::readcyclecounter: {
5145 SDValue Op = getRoot();
5146 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5147 DAG.getVTList(MVT::i64, MVT::Other), Op);
5149 DAG.setRoot(Res.getValue(1));
5152 case Intrinsic::bswap:
5153 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5154 getValue(I.getArgOperand(0)).getValueType(),
5155 getValue(I.getArgOperand(0))));
5157 case Intrinsic::cttz: {
5158 SDValue Arg = getValue(I.getArgOperand(0));
5159 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5160 EVT Ty = Arg.getValueType();
5161 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5165 case Intrinsic::ctlz: {
5166 SDValue Arg = getValue(I.getArgOperand(0));
5167 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5168 EVT Ty = Arg.getValueType();
5169 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5173 case Intrinsic::ctpop: {
5174 SDValue Arg = getValue(I.getArgOperand(0));
5175 EVT Ty = Arg.getValueType();
5176 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5179 case Intrinsic::stacksave: {
5180 SDValue Op = getRoot();
5181 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5182 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5184 DAG.setRoot(Res.getValue(1));
5187 case Intrinsic::stackrestore: {
5188 Res = getValue(I.getArgOperand(0));
5189 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5192 case Intrinsic::stackprotector: {
5193 // Emit code into the DAG to store the stack guard onto the stack.
5194 MachineFunction &MF = DAG.getMachineFunction();
5195 MachineFrameInfo *MFI = MF.getFrameInfo();
5196 EVT PtrTy = TLI.getPointerTy();
5197 SDValue Src, Chain = getRoot();
5198 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5199 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5201 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5202 // global variable __stack_chk_guard.
5204 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5205 if (BC->getOpcode() == Instruction::BitCast)
5206 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5208 if (GV && TLI.useLoadStackGuardNode()) {
5209 // Emit a LOAD_STACK_GUARD node.
5210 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5212 MachinePointerInfo MPInfo(GV);
5213 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5214 unsigned Flags = MachineMemOperand::MOLoad |
5215 MachineMemOperand::MOInvariant;
5216 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5217 PtrTy.getSizeInBits() / 8,
5218 DAG.getEVTAlignment(PtrTy));
5219 Node->setMemRefs(MemRefs, MemRefs + 1);
5221 // Copy the guard value to a virtual register so that it can be
5222 // retrieved in the epilogue.
5223 Src = SDValue(Node, 0);
5224 const TargetRegisterClass *RC =
5225 TLI.getRegClassFor(Src.getSimpleValueType());
5226 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5228 SPDescriptor.setGuardReg(Reg);
5229 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5231 Src = getValue(I.getArgOperand(0)); // The guard's value.
5234 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5236 int FI = FuncInfo.StaticAllocaMap[Slot];
5237 MFI->setStackProtectorIndex(FI);
5239 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5241 // Store the stack protector onto the stack.
5242 Res = DAG.getStore(Chain, sdl, Src, FIN,
5243 MachinePointerInfo::getFixedStack(FI),
5249 case Intrinsic::objectsize: {
5250 // If we don't know by now, we're never going to know.
5251 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5253 assert(CI && "Non-constant type in __builtin_object_size?");
5255 SDValue Arg = getValue(I.getCalledValue());
5256 EVT Ty = Arg.getValueType();
5259 Res = DAG.getConstant(-1ULL, Ty);
5261 Res = DAG.getConstant(0, Ty);
5266 case Intrinsic::annotation:
5267 case Intrinsic::ptr_annotation:
5268 // Drop the intrinsic, but forward the value
5269 setValue(&I, getValue(I.getOperand(0)));
5271 case Intrinsic::assume:
5272 case Intrinsic::var_annotation:
5273 // Discard annotate attributes and assumptions
5276 case Intrinsic::init_trampoline: {
5277 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5281 Ops[1] = getValue(I.getArgOperand(0));
5282 Ops[2] = getValue(I.getArgOperand(1));
5283 Ops[3] = getValue(I.getArgOperand(2));
5284 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5285 Ops[5] = DAG.getSrcValue(F);
5287 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5292 case Intrinsic::adjust_trampoline: {
5293 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5295 getValue(I.getArgOperand(0))));
5298 case Intrinsic::gcroot:
5300 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5301 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5303 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5304 GFI->addStackRoot(FI->getIndex(), TypeMap);
5307 case Intrinsic::gcread:
5308 case Intrinsic::gcwrite:
5309 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5310 case Intrinsic::flt_rounds:
5311 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5314 case Intrinsic::expect: {
5315 // Just replace __builtin_expect(exp, c) with EXP.
5316 setValue(&I, getValue(I.getArgOperand(0)));
5320 case Intrinsic::debugtrap:
5321 case Intrinsic::trap: {
5322 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5323 if (TrapFuncName.empty()) {
5324 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5325 ISD::TRAP : ISD::DEBUGTRAP;
5326 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5329 TargetLowering::ArgListTy Args;
5331 TargetLowering::CallLoweringInfo CLI(DAG);
5332 CLI.setDebugLoc(sdl).setChain(getRoot())
5333 .setCallee(CallingConv::C, I.getType(),
5334 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5335 std::move(Args), 0);
5337 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5338 DAG.setRoot(Result.second);
5342 case Intrinsic::uadd_with_overflow:
5343 case Intrinsic::sadd_with_overflow:
5344 case Intrinsic::usub_with_overflow:
5345 case Intrinsic::ssub_with_overflow:
5346 case Intrinsic::umul_with_overflow:
5347 case Intrinsic::smul_with_overflow: {
5349 switch (Intrinsic) {
5350 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5351 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5352 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5353 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5354 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5355 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5356 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5358 SDValue Op1 = getValue(I.getArgOperand(0));
5359 SDValue Op2 = getValue(I.getArgOperand(1));
5361 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5362 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5365 case Intrinsic::prefetch: {
5367 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5369 Ops[1] = getValue(I.getArgOperand(0));
5370 Ops[2] = getValue(I.getArgOperand(1));
5371 Ops[3] = getValue(I.getArgOperand(2));
5372 Ops[4] = getValue(I.getArgOperand(3));
5373 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5374 DAG.getVTList(MVT::Other), Ops,
5375 EVT::getIntegerVT(*Context, 8),
5376 MachinePointerInfo(I.getArgOperand(0)),
5378 false, /* volatile */
5380 rw==1)); /* write */
5383 case Intrinsic::lifetime_start:
5384 case Intrinsic::lifetime_end: {
5385 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5386 // Stack coloring is not enabled in O0, discard region information.
5387 if (TM.getOptLevel() == CodeGenOpt::None)
5390 SmallVector<Value *, 4> Allocas;
5391 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5393 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5394 E = Allocas.end(); Object != E; ++Object) {
5395 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5397 // Could not find an Alloca.
5398 if (!LifetimeObject)
5401 // First check that the Alloca is static, otherwise it won't have a
5402 // valid frame index.
5403 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5404 if (SI == FuncInfo.StaticAllocaMap.end())
5407 int FI = SI->second;
5411 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5412 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5414 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5419 case Intrinsic::invariant_start:
5420 // Discard region information.
5421 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5423 case Intrinsic::invariant_end:
5424 // Discard region information.
5426 case Intrinsic::stackprotectorcheck: {
5427 // Do not actually emit anything for this basic block. Instead we initialize
5428 // the stack protector descriptor and export the guard variable so we can
5429 // access it in FinishBasicBlock.
5430 const BasicBlock *BB = I.getParent();
5431 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5432 ExportFromCurrentBlock(SPDescriptor.getGuard());
5434 // Flush our exports since we are going to process a terminator.
5435 (void)getControlRoot();
5438 case Intrinsic::clear_cache:
5439 return TLI.getClearCacheBuiltinName();
5440 case Intrinsic::donothing:
5443 case Intrinsic::experimental_stackmap: {
5447 case Intrinsic::experimental_patchpoint_void:
5448 case Intrinsic::experimental_patchpoint_i64: {
5449 visitPatchpoint(&I);
5452 case Intrinsic::experimental_gc_statepoint: {
5456 case Intrinsic::experimental_gc_result_int:
5457 case Intrinsic::experimental_gc_result_float:
5458 case Intrinsic::experimental_gc_result_ptr:
5459 case Intrinsic::experimental_gc_result: {
5463 case Intrinsic::experimental_gc_relocate: {
5467 case Intrinsic::instrprof_increment:
5468 llvm_unreachable("instrprof failed to lower an increment");
5470 case Intrinsic::frameescape: {
5471 MachineFunction &MF = DAG.getMachineFunction();
5472 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5474 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
5475 // is the same on all targets.
5476 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5478 cast<AllocaInst>(I.getArgOperand(Idx)->stripPointerCasts());
5479 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5480 "can only escape static allocas");
5481 int FI = FuncInfo.StaticAllocaMap[Slot];
5482 MCSymbol *FrameAllocSym =
5483 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName(),
5485 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5486 TII->get(TargetOpcode::FRAME_ALLOC))
5487 .addSym(FrameAllocSym)
5494 case Intrinsic::framerecover: {
5495 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
5496 MachineFunction &MF = DAG.getMachineFunction();
5497 MVT PtrVT = TLI.getPointerTy(0);
5499 // Get the symbol that defines the frame offset.
5500 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5501 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5502 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5503 MCSymbol *FrameAllocSym =
5504 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName(),
5507 // Create a TargetExternalSymbol for the label to avoid any target lowering
5508 // that would make this PC relative.
5509 StringRef Name = FrameAllocSym->getName();
5510 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
5511 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5513 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5515 // Add the offset to the FP.
5516 Value *FP = I.getArgOperand(1);
5517 SDValue FPVal = getValue(FP);
5518 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5523 case Intrinsic::eh_begincatch:
5524 case Intrinsic::eh_endcatch:
5525 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5529 std::pair<SDValue, SDValue>
5530 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5531 MachineBasicBlock *LandingPad) {
5532 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5533 MCSymbol *BeginLabel = nullptr;
5536 // Insert a label before the invoke call to mark the try range. This can be
5537 // used to detect deletion of the invoke via the MachineModuleInfo.
5538 BeginLabel = MMI.getContext().CreateTempSymbol();
5540 // For SjLj, keep track of which landing pads go with which invokes
5541 // so as to maintain the ordering of pads in the LSDA.
5542 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5543 if (CallSiteIndex) {
5544 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5545 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5547 // Now that the call site is handled, stop tracking it.
5548 MMI.setCurrentCallSite(0);
5551 // Both PendingLoads and PendingExports must be flushed here;
5552 // this call might not return.
5554 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5556 CLI.setChain(getRoot());
5558 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5559 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5561 assert((CLI.IsTailCall || Result.second.getNode()) &&
5562 "Non-null chain expected with non-tail call!");
5563 assert((Result.second.getNode() || !Result.first.getNode()) &&
5564 "Null value expected with tail call!");
5566 if (!Result.second.getNode()) {
5567 // As a special case, a null chain means that a tail call has been emitted
5568 // and the DAG root is already updated.
5571 // Since there's no actual continuation from this block, nothing can be
5572 // relying on us setting vregs for them.
5573 PendingExports.clear();
5575 DAG.setRoot(Result.second);
5579 // Insert a label at the end of the invoke call to mark the try range. This
5580 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5581 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5582 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5584 // Inform MachineModuleInfo of range.
5585 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5591 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5593 MachineBasicBlock *LandingPad) {
5594 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5595 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5596 Type *RetTy = FTy->getReturnType();
5598 TargetLowering::ArgListTy Args;
5599 TargetLowering::ArgListEntry Entry;
5600 Args.reserve(CS.arg_size());
5602 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5604 const Value *V = *i;
5607 if (V->getType()->isEmptyTy())
5610 SDValue ArgNode = getValue(V);
5611 Entry.Node = ArgNode; Entry.Ty = V->getType();
5613 // Skip the first return-type Attribute to get to params.
5614 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5615 Args.push_back(Entry);
5618 // Check if target-independent constraints permit a tail call here.
5619 // Target-dependent constraints are checked within TLI->LowerCallTo.
5620 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5623 TargetLowering::CallLoweringInfo CLI(DAG);
5624 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5625 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5626 .setTailCall(isTailCall);
5627 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5629 if (Result.first.getNode())
5630 setValue(CS.getInstruction(), Result.first);
5633 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5634 /// value is equal or not-equal to zero.
5635 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5636 for (const User *U : V->users()) {
5637 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5638 if (IC->isEquality())
5639 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5640 if (C->isNullValue())
5642 // Unknown instruction.
5648 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5650 SelectionDAGBuilder &Builder) {
5652 // Check to see if this load can be trivially constant folded, e.g. if the
5653 // input is from a string literal.
5654 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5655 // Cast pointer to the type we really want to load.
5656 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5657 PointerType::getUnqual(LoadTy));
5659 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5660 const_cast<Constant *>(LoadInput), *Builder.DL))
5661 return Builder.getValue(LoadCst);
5664 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5665 // still constant memory, the input chain can be the entry node.
5667 bool ConstantMemory = false;
5669 // Do not serialize (non-volatile) loads of constant memory with anything.
5670 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5671 Root = Builder.DAG.getEntryNode();
5672 ConstantMemory = true;
5674 // Do not serialize non-volatile loads against each other.
5675 Root = Builder.DAG.getRoot();
5678 SDValue Ptr = Builder.getValue(PtrVal);
5679 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5680 Ptr, MachinePointerInfo(PtrVal),
5682 false /*nontemporal*/,
5683 false /*isinvariant*/, 1 /* align=1 */);
5685 if (!ConstantMemory)
5686 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5690 /// processIntegerCallValue - Record the value for an instruction that
5691 /// produces an integer result, converting the type where necessary.
5692 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5695 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5697 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5699 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5700 setValue(&I, Value);
5703 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5704 /// If so, return true and lower it, otherwise return false and it will be
5705 /// lowered like a normal call.
5706 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5707 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5708 if (I.getNumArgOperands() != 3)
5711 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5712 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5713 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5714 !I.getType()->isIntegerTy())
5717 const Value *Size = I.getArgOperand(2);
5718 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5719 if (CSize && CSize->getZExtValue() == 0) {
5720 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5721 setValue(&I, DAG.getConstant(0, CallVT));
5725 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5726 std::pair<SDValue, SDValue> Res =
5727 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5728 getValue(LHS), getValue(RHS), getValue(Size),
5729 MachinePointerInfo(LHS),
5730 MachinePointerInfo(RHS));
5731 if (Res.first.getNode()) {
5732 processIntegerCallValue(I, Res.first, true);
5733 PendingLoads.push_back(Res.second);
5737 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5738 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5739 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5740 bool ActuallyDoIt = true;
5743 switch (CSize->getZExtValue()) {
5745 LoadVT = MVT::Other;
5747 ActuallyDoIt = false;
5751 LoadTy = Type::getInt16Ty(CSize->getContext());
5755 LoadTy = Type::getInt32Ty(CSize->getContext());
5759 LoadTy = Type::getInt64Ty(CSize->getContext());
5763 LoadVT = MVT::v4i32;
5764 LoadTy = Type::getInt32Ty(CSize->getContext());
5765 LoadTy = VectorType::get(LoadTy, 4);
5770 // This turns into unaligned loads. We only do this if the target natively
5771 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5772 // we'll only produce a small number of byte loads.
5774 // Require that we can find a legal MVT, and only do this if the target
5775 // supports unaligned loads of that type. Expanding into byte loads would
5777 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5778 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5779 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5780 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5781 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5782 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5783 // TODO: Check alignment of src and dest ptrs.
5784 if (!TLI.isTypeLegal(LoadVT) ||
5785 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5786 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5787 ActuallyDoIt = false;
5791 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5792 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5794 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5796 processIntegerCallValue(I, Res, false);
5805 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5806 /// form. If so, return true and lower it, otherwise return false and it
5807 /// will be lowered like a normal call.
5808 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5809 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5810 if (I.getNumArgOperands() != 3)
5813 const Value *Src = I.getArgOperand(0);
5814 const Value *Char = I.getArgOperand(1);
5815 const Value *Length = I.getArgOperand(2);
5816 if (!Src->getType()->isPointerTy() ||
5817 !Char->getType()->isIntegerTy() ||
5818 !Length->getType()->isIntegerTy() ||
5819 !I.getType()->isPointerTy())
5822 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5823 std::pair<SDValue, SDValue> Res =
5824 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5825 getValue(Src), getValue(Char), getValue(Length),
5826 MachinePointerInfo(Src));
5827 if (Res.first.getNode()) {
5828 setValue(&I, Res.first);
5829 PendingLoads.push_back(Res.second);
5836 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5837 /// optimized form. If so, return true and lower it, otherwise return false
5838 /// and it will be lowered like a normal call.
5839 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5840 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5841 if (I.getNumArgOperands() != 2)
5844 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5845 if (!Arg0->getType()->isPointerTy() ||
5846 !Arg1->getType()->isPointerTy() ||
5847 !I.getType()->isPointerTy())
5850 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5851 std::pair<SDValue, SDValue> Res =
5852 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5853 getValue(Arg0), getValue(Arg1),
5854 MachinePointerInfo(Arg0),
5855 MachinePointerInfo(Arg1), isStpcpy);
5856 if (Res.first.getNode()) {
5857 setValue(&I, Res.first);
5858 DAG.setRoot(Res.second);
5865 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5866 /// If so, return true and lower it, otherwise return false and it will be
5867 /// lowered like a normal call.
5868 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5869 // Verify that the prototype makes sense. int strcmp(void*,void*)
5870 if (I.getNumArgOperands() != 2)
5873 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5874 if (!Arg0->getType()->isPointerTy() ||
5875 !Arg1->getType()->isPointerTy() ||
5876 !I.getType()->isIntegerTy())
5879 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5880 std::pair<SDValue, SDValue> Res =
5881 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5882 getValue(Arg0), getValue(Arg1),
5883 MachinePointerInfo(Arg0),
5884 MachinePointerInfo(Arg1));
5885 if (Res.first.getNode()) {
5886 processIntegerCallValue(I, Res.first, true);
5887 PendingLoads.push_back(Res.second);
5894 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5895 /// form. If so, return true and lower it, otherwise return false and it
5896 /// will be lowered like a normal call.
5897 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5898 // Verify that the prototype makes sense. size_t strlen(char *)
5899 if (I.getNumArgOperands() != 1)
5902 const Value *Arg0 = I.getArgOperand(0);
5903 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5906 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5907 std::pair<SDValue, SDValue> Res =
5908 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5909 getValue(Arg0), MachinePointerInfo(Arg0));
5910 if (Res.first.getNode()) {
5911 processIntegerCallValue(I, Res.first, false);
5912 PendingLoads.push_back(Res.second);
5919 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5920 /// form. If so, return true and lower it, otherwise return false and it
5921 /// will be lowered like a normal call.
5922 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5923 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5924 if (I.getNumArgOperands() != 2)
5927 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5928 if (!Arg0->getType()->isPointerTy() ||
5929 !Arg1->getType()->isIntegerTy() ||
5930 !I.getType()->isIntegerTy())
5933 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5934 std::pair<SDValue, SDValue> Res =
5935 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5936 getValue(Arg0), getValue(Arg1),
5937 MachinePointerInfo(Arg0));
5938 if (Res.first.getNode()) {
5939 processIntegerCallValue(I, Res.first, false);
5940 PendingLoads.push_back(Res.second);
5947 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5948 /// operation (as expected), translate it to an SDNode with the specified opcode
5949 /// and return true.
5950 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5952 // Sanity check that it really is a unary floating-point call.
5953 if (I.getNumArgOperands() != 1 ||
5954 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5955 I.getType() != I.getArgOperand(0)->getType() ||
5956 !I.onlyReadsMemory())
5959 SDValue Tmp = getValue(I.getArgOperand(0));
5960 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5964 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5965 /// operation (as expected), translate it to an SDNode with the specified opcode
5966 /// and return true.
5967 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5969 // Sanity check that it really is a binary floating-point call.
5970 if (I.getNumArgOperands() != 2 ||
5971 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5972 I.getType() != I.getArgOperand(0)->getType() ||
5973 I.getType() != I.getArgOperand(1)->getType() ||
5974 !I.onlyReadsMemory())
5977 SDValue Tmp0 = getValue(I.getArgOperand(0));
5978 SDValue Tmp1 = getValue(I.getArgOperand(1));
5979 EVT VT = Tmp0.getValueType();
5980 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5984 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5985 // Handle inline assembly differently.
5986 if (isa<InlineAsm>(I.getCalledValue())) {
5991 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5992 ComputeUsesVAFloatArgument(I, &MMI);
5994 const char *RenameFn = nullptr;
5995 if (Function *F = I.getCalledFunction()) {
5996 if (F->isDeclaration()) {
5997 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5998 if (unsigned IID = II->getIntrinsicID(F)) {
5999 RenameFn = visitIntrinsicCall(I, IID);
6004 if (unsigned IID = F->getIntrinsicID()) {
6005 RenameFn = visitIntrinsicCall(I, IID);
6011 // Check for well-known libc/libm calls. If the function is internal, it
6012 // can't be a library call.
6014 if (!F->hasLocalLinkage() && F->hasName() &&
6015 LibInfo->getLibFunc(F->getName(), Func) &&
6016 LibInfo->hasOptimizedCodeGen(Func)) {
6019 case LibFunc::copysign:
6020 case LibFunc::copysignf:
6021 case LibFunc::copysignl:
6022 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6023 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6024 I.getType() == I.getArgOperand(0)->getType() &&
6025 I.getType() == I.getArgOperand(1)->getType() &&
6026 I.onlyReadsMemory()) {
6027 SDValue LHS = getValue(I.getArgOperand(0));
6028 SDValue RHS = getValue(I.getArgOperand(1));
6029 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6030 LHS.getValueType(), LHS, RHS));
6035 case LibFunc::fabsf:
6036 case LibFunc::fabsl:
6037 if (visitUnaryFloatCall(I, ISD::FABS))
6041 case LibFunc::fminf:
6042 case LibFunc::fminl:
6043 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6047 case LibFunc::fmaxf:
6048 case LibFunc::fmaxl:
6049 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6055 if (visitUnaryFloatCall(I, ISD::FSIN))
6061 if (visitUnaryFloatCall(I, ISD::FCOS))
6065 case LibFunc::sqrtf:
6066 case LibFunc::sqrtl:
6067 case LibFunc::sqrt_finite:
6068 case LibFunc::sqrtf_finite:
6069 case LibFunc::sqrtl_finite:
6070 if (visitUnaryFloatCall(I, ISD::FSQRT))
6073 case LibFunc::floor:
6074 case LibFunc::floorf:
6075 case LibFunc::floorl:
6076 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6079 case LibFunc::nearbyint:
6080 case LibFunc::nearbyintf:
6081 case LibFunc::nearbyintl:
6082 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6086 case LibFunc::ceilf:
6087 case LibFunc::ceill:
6088 if (visitUnaryFloatCall(I, ISD::FCEIL))
6092 case LibFunc::rintf:
6093 case LibFunc::rintl:
6094 if (visitUnaryFloatCall(I, ISD::FRINT))
6097 case LibFunc::round:
6098 case LibFunc::roundf:
6099 case LibFunc::roundl:
6100 if (visitUnaryFloatCall(I, ISD::FROUND))
6103 case LibFunc::trunc:
6104 case LibFunc::truncf:
6105 case LibFunc::truncl:
6106 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6110 case LibFunc::log2f:
6111 case LibFunc::log2l:
6112 if (visitUnaryFloatCall(I, ISD::FLOG2))
6116 case LibFunc::exp2f:
6117 case LibFunc::exp2l:
6118 if (visitUnaryFloatCall(I, ISD::FEXP2))
6121 case LibFunc::memcmp:
6122 if (visitMemCmpCall(I))
6125 case LibFunc::memchr:
6126 if (visitMemChrCall(I))
6129 case LibFunc::strcpy:
6130 if (visitStrCpyCall(I, false))
6133 case LibFunc::stpcpy:
6134 if (visitStrCpyCall(I, true))
6137 case LibFunc::strcmp:
6138 if (visitStrCmpCall(I))
6141 case LibFunc::strlen:
6142 if (visitStrLenCall(I))
6145 case LibFunc::strnlen:
6146 if (visitStrNLenCall(I))
6155 Callee = getValue(I.getCalledValue());
6157 Callee = DAG.getExternalSymbol(RenameFn,
6158 DAG.getTargetLoweringInfo().getPointerTy());
6160 // Check if we can potentially perform a tail call. More detailed checking is
6161 // be done within LowerCallTo, after more information about the call is known.
6162 LowerCallTo(&I, Callee, I.isTailCall());
6167 /// AsmOperandInfo - This contains information for each constraint that we are
6169 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6171 /// CallOperand - If this is the result output operand or a clobber
6172 /// this is null, otherwise it is the incoming operand to the CallInst.
6173 /// This gets modified as the asm is processed.
6174 SDValue CallOperand;
6176 /// AssignedRegs - If this is a register or register class operand, this
6177 /// contains the set of register corresponding to the operand.
6178 RegsForValue AssignedRegs;
6180 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6181 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6184 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6185 /// corresponds to. If there is no Value* for this operand, it returns
6187 EVT getCallOperandValEVT(LLVMContext &Context,
6188 const TargetLowering &TLI,
6189 const DataLayout *DL) const {
6190 if (!CallOperandVal) return MVT::Other;
6192 if (isa<BasicBlock>(CallOperandVal))
6193 return TLI.getPointerTy();
6195 llvm::Type *OpTy = CallOperandVal->getType();
6197 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6198 // If this is an indirect operand, the operand is a pointer to the
6201 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6203 report_fatal_error("Indirect operand for inline asm not a pointer!");
6204 OpTy = PtrTy->getElementType();
6207 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6208 if (StructType *STy = dyn_cast<StructType>(OpTy))
6209 if (STy->getNumElements() == 1)
6210 OpTy = STy->getElementType(0);
6212 // If OpTy is not a single value, it may be a struct/union that we
6213 // can tile with integers.
6214 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6215 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6224 OpTy = IntegerType::get(Context, BitSize);
6229 return TLI.getValueType(OpTy, true);
6233 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6235 } // end anonymous namespace
6237 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6238 /// specified operand. We prefer to assign virtual registers, to allow the
6239 /// register allocator to handle the assignment process. However, if the asm
6240 /// uses features that we can't model on machineinstrs, we have SDISel do the
6241 /// allocation. This produces generally horrible, but correct, code.
6243 /// OpInfo describes the operand.
6245 static void GetRegistersForValue(SelectionDAG &DAG,
6246 const TargetLowering &TLI,
6248 SDISelAsmOperandInfo &OpInfo) {
6249 LLVMContext &Context = *DAG.getContext();
6251 MachineFunction &MF = DAG.getMachineFunction();
6252 SmallVector<unsigned, 4> Regs;
6254 // If this is a constraint for a single physreg, or a constraint for a
6255 // register class, find it.
6256 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6257 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6258 OpInfo.ConstraintCode,
6259 OpInfo.ConstraintVT);
6261 unsigned NumRegs = 1;
6262 if (OpInfo.ConstraintVT != MVT::Other) {
6263 // If this is a FP input in an integer register (or visa versa) insert a bit
6264 // cast of the input value. More generally, handle any case where the input
6265 // value disagrees with the register class we plan to stick this in.
6266 if (OpInfo.Type == InlineAsm::isInput &&
6267 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6268 // Try to convert to the first EVT that the reg class contains. If the
6269 // types are identical size, use a bitcast to convert (e.g. two differing
6271 MVT RegVT = *PhysReg.second->vt_begin();
6272 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6273 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6274 RegVT, OpInfo.CallOperand);
6275 OpInfo.ConstraintVT = RegVT;
6276 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6277 // If the input is a FP value and we want it in FP registers, do a
6278 // bitcast to the corresponding integer type. This turns an f64 value
6279 // into i64, which can be passed with two i32 values on a 32-bit
6281 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6282 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6283 RegVT, OpInfo.CallOperand);
6284 OpInfo.ConstraintVT = RegVT;
6288 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6292 EVT ValueVT = OpInfo.ConstraintVT;
6294 // If this is a constraint for a specific physical register, like {r17},
6296 if (unsigned AssignedReg = PhysReg.first) {
6297 const TargetRegisterClass *RC = PhysReg.second;
6298 if (OpInfo.ConstraintVT == MVT::Other)
6299 ValueVT = *RC->vt_begin();
6301 // Get the actual register value type. This is important, because the user
6302 // may have asked for (e.g.) the AX register in i32 type. We need to
6303 // remember that AX is actually i16 to get the right extension.
6304 RegVT = *RC->vt_begin();
6306 // This is a explicit reference to a physical register.
6307 Regs.push_back(AssignedReg);
6309 // If this is an expanded reference, add the rest of the regs to Regs.
6311 TargetRegisterClass::iterator I = RC->begin();
6312 for (; *I != AssignedReg; ++I)
6313 assert(I != RC->end() && "Didn't find reg!");
6315 // Already added the first reg.
6317 for (; NumRegs; --NumRegs, ++I) {
6318 assert(I != RC->end() && "Ran out of registers to allocate!");
6323 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6327 // Otherwise, if this was a reference to an LLVM register class, create vregs
6328 // for this reference.
6329 if (const TargetRegisterClass *RC = PhysReg.second) {
6330 RegVT = *RC->vt_begin();
6331 if (OpInfo.ConstraintVT == MVT::Other)
6334 // Create the appropriate number of virtual registers.
6335 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6336 for (; NumRegs; --NumRegs)
6337 Regs.push_back(RegInfo.createVirtualRegister(RC));
6339 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6343 // Otherwise, we couldn't allocate enough registers for this.
6346 /// visitInlineAsm - Handle a call to an InlineAsm object.
6348 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6349 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6351 /// ConstraintOperands - Information about all of the constraints.
6352 SDISelAsmOperandInfoVector ConstraintOperands;
6354 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6355 TargetLowering::AsmOperandInfoVector TargetConstraints =
6356 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
6358 bool hasMemory = false;
6360 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6361 unsigned ResNo = 0; // ResNo - The result number of the next output.
6362 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6363 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6364 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6366 MVT OpVT = MVT::Other;
6368 // Compute the value type for each operand.
6369 switch (OpInfo.Type) {
6370 case InlineAsm::isOutput:
6371 // Indirect outputs just consume an argument.
6372 if (OpInfo.isIndirect) {
6373 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6377 // The return value of the call is this value. As such, there is no
6378 // corresponding argument.
6379 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6380 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6381 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6383 assert(ResNo == 0 && "Asm only has one result!");
6384 OpVT = TLI.getSimpleValueType(CS.getType());
6388 case InlineAsm::isInput:
6389 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6391 case InlineAsm::isClobber:
6396 // If this is an input or an indirect output, process the call argument.
6397 // BasicBlocks are labels, currently appearing only in asm's.
6398 if (OpInfo.CallOperandVal) {
6399 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6400 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6402 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6406 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6409 OpInfo.ConstraintVT = OpVT;
6411 // Indirect operand accesses access memory.
6412 if (OpInfo.isIndirect)
6415 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6416 TargetLowering::ConstraintType
6417 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6418 if (CType == TargetLowering::C_Memory) {
6426 SDValue Chain, Flag;
6428 // We won't need to flush pending loads if this asm doesn't touch
6429 // memory and is nonvolatile.
6430 if (hasMemory || IA->hasSideEffects())
6433 Chain = DAG.getRoot();
6435 // Second pass over the constraints: compute which constraint option to use
6436 // and assign registers to constraints that want a specific physreg.
6437 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6438 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6440 // If this is an output operand with a matching input operand, look up the
6441 // matching input. If their types mismatch, e.g. one is an integer, the
6442 // other is floating point, or their sizes are different, flag it as an
6444 if (OpInfo.hasMatchingInput()) {
6445 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6447 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6448 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6449 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6450 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6451 OpInfo.ConstraintVT);
6452 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6453 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6454 Input.ConstraintVT);
6455 if ((OpInfo.ConstraintVT.isInteger() !=
6456 Input.ConstraintVT.isInteger()) ||
6457 (MatchRC.second != InputRC.second)) {
6458 report_fatal_error("Unsupported asm: input constraint"
6459 " with a matching output constraint of"
6460 " incompatible type!");
6462 Input.ConstraintVT = OpInfo.ConstraintVT;
6466 // Compute the constraint code and ConstraintType to use.
6467 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6469 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6470 OpInfo.Type == InlineAsm::isClobber)
6473 // If this is a memory input, and if the operand is not indirect, do what we
6474 // need to to provide an address for the memory input.
6475 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6476 !OpInfo.isIndirect) {
6477 assert((OpInfo.isMultipleAlternative ||
6478 (OpInfo.Type == InlineAsm::isInput)) &&
6479 "Can only indirectify direct input operands!");
6481 // Memory operands really want the address of the value. If we don't have
6482 // an indirect input, put it in the constpool if we can, otherwise spill
6483 // it to a stack slot.
6484 // TODO: This isn't quite right. We need to handle these according to
6485 // the addressing mode that the constraint wants. Also, this may take
6486 // an additional register for the computation and we don't want that
6489 // If the operand is a float, integer, or vector constant, spill to a
6490 // constant pool entry to get its address.
6491 const Value *OpVal = OpInfo.CallOperandVal;
6492 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6493 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6494 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6495 TLI.getPointerTy());
6497 // Otherwise, create a stack slot and emit a store to it before the
6499 Type *Ty = OpVal->getType();
6500 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6501 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6502 MachineFunction &MF = DAG.getMachineFunction();
6503 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6504 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6505 Chain = DAG.getStore(Chain, getCurSDLoc(),
6506 OpInfo.CallOperand, StackSlot,
6507 MachinePointerInfo::getFixedStack(SSFI),
6509 OpInfo.CallOperand = StackSlot;
6512 // There is no longer a Value* corresponding to this operand.
6513 OpInfo.CallOperandVal = nullptr;
6515 // It is now an indirect operand.
6516 OpInfo.isIndirect = true;
6519 // If this constraint is for a specific register, allocate it before
6521 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6522 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6525 // Second pass - Loop over all of the operands, assigning virtual or physregs
6526 // to register class operands.
6527 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6528 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6530 // C_Register operands have already been allocated, Other/Memory don't need
6532 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6533 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6536 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6537 std::vector<SDValue> AsmNodeOperands;
6538 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6539 AsmNodeOperands.push_back(
6540 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6541 TLI.getPointerTy()));
6543 // If we have a !srcloc metadata node associated with it, we want to attach
6544 // this to the ultimately generated inline asm machineinstr. To do this, we
6545 // pass in the third operand as this (potentially null) inline asm MDNode.
6546 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6547 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6549 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6550 // bits as operand 3.
6551 unsigned ExtraInfo = 0;
6552 if (IA->hasSideEffects())
6553 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6554 if (IA->isAlignStack())
6555 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6556 // Set the asm dialect.
6557 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6559 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6560 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6561 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6563 // Compute the constraint code and ConstraintType to use.
6564 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6566 // Ideally, we would only check against memory constraints. However, the
6567 // meaning of an other constraint can be target-specific and we can't easily
6568 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6569 // for other constriants as well.
6570 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6571 OpInfo.ConstraintType == TargetLowering::C_Other) {
6572 if (OpInfo.Type == InlineAsm::isInput)
6573 ExtraInfo |= InlineAsm::Extra_MayLoad;
6574 else if (OpInfo.Type == InlineAsm::isOutput)
6575 ExtraInfo |= InlineAsm::Extra_MayStore;
6576 else if (OpInfo.Type == InlineAsm::isClobber)
6577 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6581 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6582 TLI.getPointerTy()));
6584 // Loop over all of the inputs, copying the operand values into the
6585 // appropriate registers and processing the output regs.
6586 RegsForValue RetValRegs;
6588 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6589 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6591 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6592 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6594 switch (OpInfo.Type) {
6595 case InlineAsm::isOutput: {
6596 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6597 OpInfo.ConstraintType != TargetLowering::C_Register) {
6598 // Memory output, or 'other' output (e.g. 'X' constraint).
6599 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6601 unsigned ConstraintID =
6602 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6603 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6604 "Failed to convert memory constraint code to constraint id.");
6606 // Add information to the INLINEASM node to know about this output.
6607 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6608 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6609 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
6610 AsmNodeOperands.push_back(OpInfo.CallOperand);
6614 // Otherwise, this is a register or register class output.
6616 // Copy the output from the appropriate register. Find a register that
6618 if (OpInfo.AssignedRegs.Regs.empty()) {
6619 LLVMContext &Ctx = *DAG.getContext();
6620 Ctx.emitError(CS.getInstruction(),
6621 "couldn't allocate output register for constraint '" +
6622 Twine(OpInfo.ConstraintCode) + "'");
6626 // If this is an indirect operand, store through the pointer after the
6628 if (OpInfo.isIndirect) {
6629 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6630 OpInfo.CallOperandVal));
6632 // This is the result value of the call.
6633 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6634 // Concatenate this output onto the outputs list.
6635 RetValRegs.append(OpInfo.AssignedRegs);
6638 // Add information to the INLINEASM node to know that this register is
6641 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6642 ? InlineAsm::Kind_RegDefEarlyClobber
6643 : InlineAsm::Kind_RegDef,
6644 false, 0, DAG, AsmNodeOperands);
6647 case InlineAsm::isInput: {
6648 SDValue InOperandVal = OpInfo.CallOperand;
6650 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6651 // If this is required to match an output register we have already set,
6652 // just use its register.
6653 unsigned OperandNo = OpInfo.getMatchedOperand();
6655 // Scan until we find the definition we already emitted of this operand.
6656 // When we find it, create a RegsForValue operand.
6657 unsigned CurOp = InlineAsm::Op_FirstOperand;
6658 for (; OperandNo; --OperandNo) {
6659 // Advance to the next operand.
6661 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6662 assert((InlineAsm::isRegDefKind(OpFlag) ||
6663 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6664 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6665 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6669 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6670 if (InlineAsm::isRegDefKind(OpFlag) ||
6671 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6672 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6673 if (OpInfo.isIndirect) {
6674 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6675 LLVMContext &Ctx = *DAG.getContext();
6676 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6677 " don't know how to handle tied "
6678 "indirect register inputs");
6682 RegsForValue MatchedRegs;
6683 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6684 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6685 MatchedRegs.RegVTs.push_back(RegVT);
6686 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6687 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6689 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6690 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6692 LLVMContext &Ctx = *DAG.getContext();
6693 Ctx.emitError(CS.getInstruction(),
6694 "inline asm error: This value"
6695 " type register class is not natively supported!");
6699 // Use the produced MatchedRegs object to
6700 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6701 Chain, &Flag, CS.getInstruction());
6702 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6703 true, OpInfo.getMatchedOperand(),
6704 DAG, AsmNodeOperands);
6708 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6709 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6710 "Unexpected number of operands");
6711 // Add information to the INLINEASM node to know about this input.
6712 // See InlineAsm.h isUseOperandTiedToDef.
6713 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6714 OpInfo.getMatchedOperand());
6715 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6716 TLI.getPointerTy()));
6717 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6721 // Treat indirect 'X' constraint as memory.
6722 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6724 OpInfo.ConstraintType = TargetLowering::C_Memory;
6726 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6727 std::vector<SDValue> Ops;
6728 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6731 LLVMContext &Ctx = *DAG.getContext();
6732 Ctx.emitError(CS.getInstruction(),
6733 "invalid operand for inline asm constraint '" +
6734 Twine(OpInfo.ConstraintCode) + "'");
6738 // Add information to the INLINEASM node to know about this input.
6739 unsigned ResOpType =
6740 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6741 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6742 TLI.getPointerTy()));
6743 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6747 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6748 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6749 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6750 "Memory operands expect pointer values");
6752 unsigned ConstraintID =
6753 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6754 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6755 "Failed to convert memory constraint code to constraint id.");
6757 // Add information to the INLINEASM node to know about this input.
6758 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6759 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6760 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
6761 AsmNodeOperands.push_back(InOperandVal);
6765 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6766 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6767 "Unknown constraint type!");
6769 // TODO: Support this.
6770 if (OpInfo.isIndirect) {
6771 LLVMContext &Ctx = *DAG.getContext();
6772 Ctx.emitError(CS.getInstruction(),
6773 "Don't know how to handle indirect register inputs yet "
6774 "for constraint '" +
6775 Twine(OpInfo.ConstraintCode) + "'");
6779 // Copy the input into the appropriate registers.
6780 if (OpInfo.AssignedRegs.Regs.empty()) {
6781 LLVMContext &Ctx = *DAG.getContext();
6782 Ctx.emitError(CS.getInstruction(),
6783 "couldn't allocate input reg for constraint '" +
6784 Twine(OpInfo.ConstraintCode) + "'");
6788 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6789 Chain, &Flag, CS.getInstruction());
6791 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6792 DAG, AsmNodeOperands);
6795 case InlineAsm::isClobber: {
6796 // Add the clobbered value to the operand list, so that the register
6797 // allocator is aware that the physreg got clobbered.
6798 if (!OpInfo.AssignedRegs.Regs.empty())
6799 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6807 // Finish up input operands. Set the input chain and add the flag last.
6808 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6809 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6811 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6812 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6813 Flag = Chain.getValue(1);
6815 // If this asm returns a register value, copy the result from that register
6816 // and set it as the value of the call.
6817 if (!RetValRegs.Regs.empty()) {
6818 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6819 Chain, &Flag, CS.getInstruction());
6821 // FIXME: Why don't we do this for inline asms with MRVs?
6822 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6823 EVT ResultType = TLI.getValueType(CS.getType());
6825 // If any of the results of the inline asm is a vector, it may have the
6826 // wrong width/num elts. This can happen for register classes that can
6827 // contain multiple different value types. The preg or vreg allocated may
6828 // not have the same VT as was expected. Convert it to the right type
6829 // with bit_convert.
6830 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6831 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6834 } else if (ResultType != Val.getValueType() &&
6835 ResultType.isInteger() && Val.getValueType().isInteger()) {
6836 // If a result value was tied to an input value, the computed result may
6837 // have a wider width than the expected result. Extract the relevant
6839 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6842 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6845 setValue(CS.getInstruction(), Val);
6846 // Don't need to use this as a chain in this case.
6847 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6851 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6853 // Process indirect outputs, first output all of the flagged copies out of
6855 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6856 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6857 const Value *Ptr = IndirectStoresToEmit[i].second;
6858 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6860 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6863 // Emit the non-flagged stores from the physregs.
6864 SmallVector<SDValue, 8> OutChains;
6865 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6866 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6867 StoresToEmit[i].first,
6868 getValue(StoresToEmit[i].second),
6869 MachinePointerInfo(StoresToEmit[i].second),
6871 OutChains.push_back(Val);
6874 if (!OutChains.empty())
6875 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6880 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6881 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6882 MVT::Other, getRoot(),
6883 getValue(I.getArgOperand(0)),
6884 DAG.getSrcValue(I.getArgOperand(0))));
6887 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6888 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6889 const DataLayout &DL = *TLI.getDataLayout();
6890 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6891 getRoot(), getValue(I.getOperand(0)),
6892 DAG.getSrcValue(I.getOperand(0)),
6893 DL.getABITypeAlignment(I.getType()));
6895 DAG.setRoot(V.getValue(1));
6898 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6899 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6900 MVT::Other, getRoot(),
6901 getValue(I.getArgOperand(0)),
6902 DAG.getSrcValue(I.getArgOperand(0))));
6905 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6906 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6907 MVT::Other, getRoot(),
6908 getValue(I.getArgOperand(0)),
6909 getValue(I.getArgOperand(1)),
6910 DAG.getSrcValue(I.getArgOperand(0)),
6911 DAG.getSrcValue(I.getArgOperand(1))));
6914 /// \brief Lower an argument list according to the target calling convention.
6916 /// \return A tuple of <return-value, token-chain>
6918 /// This is a helper for lowering intrinsics that follow a target calling
6919 /// convention or require stack pointer adjustment. Only a subset of the
6920 /// intrinsic's operands need to participate in the calling convention.
6921 std::pair<SDValue, SDValue>
6922 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6923 unsigned NumArgs, SDValue Callee,
6925 MachineBasicBlock *LandingPad,
6926 bool IsPatchPoint) {
6927 TargetLowering::ArgListTy Args;
6928 Args.reserve(NumArgs);
6930 // Populate the argument list.
6931 // Attributes for args start at offset 1, after the return attribute.
6932 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6933 ArgI != ArgE; ++ArgI) {
6934 const Value *V = CS->getOperand(ArgI);
6936 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6938 TargetLowering::ArgListEntry Entry;
6939 Entry.Node = getValue(V);
6940 Entry.Ty = V->getType();
6941 Entry.setAttributes(&CS, AttrI);
6942 Args.push_back(Entry);
6945 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6946 TargetLowering::CallLoweringInfo CLI(DAG);
6947 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6948 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6949 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6951 return lowerInvokable(CLI, LandingPad);
6954 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6955 /// or patchpoint target node's operand list.
6957 /// Constants are converted to TargetConstants purely as an optimization to
6958 /// avoid constant materialization and register allocation.
6960 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6961 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6962 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6963 /// address materialization and register allocation, but may also be required
6964 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6965 /// alloca in the entry block, then the runtime may assume that the alloca's
6966 /// StackMap location can be read immediately after compilation and that the
6967 /// location is valid at any point during execution (this is similar to the
6968 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6969 /// only available in a register, then the runtime would need to trap when
6970 /// execution reaches the StackMap in order to read the alloca's location.
6971 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6972 SmallVectorImpl<SDValue> &Ops,
6973 SelectionDAGBuilder &Builder) {
6974 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6975 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6978 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6980 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6981 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6982 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6984 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6986 Ops.push_back(OpVal);
6990 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6991 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6992 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6993 // [live variables...])
6995 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6997 SDValue Chain, InFlag, Callee, NullPtr;
6998 SmallVector<SDValue, 32> Ops;
7000 SDLoc DL = getCurSDLoc();
7001 Callee = getValue(CI.getCalledValue());
7002 NullPtr = DAG.getIntPtrConstant(0, true);
7004 // The stackmap intrinsic only records the live variables (the arguemnts
7005 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7006 // intrinsic, this won't be lowered to a function call. This means we don't
7007 // have to worry about calling conventions and target specific lowering code.
7008 // Instead we perform the call lowering right here.
7010 // chain, flag = CALLSEQ_START(chain, 0)
7011 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7012 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7014 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7015 InFlag = Chain.getValue(1);
7017 // Add the <id> and <numBytes> constants.
7018 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7019 Ops.push_back(DAG.getTargetConstant(
7020 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7021 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7022 Ops.push_back(DAG.getTargetConstant(
7023 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7025 // Push live variables for the stack map.
7026 addStackMapLiveVars(&CI, 2, Ops, *this);
7028 // We are not pushing any register mask info here on the operands list,
7029 // because the stackmap doesn't clobber anything.
7031 // Push the chain and the glue flag.
7032 Ops.push_back(Chain);
7033 Ops.push_back(InFlag);
7035 // Create the STACKMAP node.
7036 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7037 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7038 Chain = SDValue(SM, 0);
7039 InFlag = Chain.getValue(1);
7041 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7043 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7045 // Set the root to the target-lowered call chain.
7048 // Inform the Frame Information that we have a stackmap in this function.
7049 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7052 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7053 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7054 MachineBasicBlock *LandingPad) {
7055 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7060 // [live variables...])
7062 CallingConv::ID CC = CS.getCallingConv();
7063 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7064 bool HasDef = !CS->getType()->isVoidTy();
7065 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7067 // Get the real number of arguments participating in the call <numArgs>
7068 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7069 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7071 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7072 // Intrinsics include all meta-operands up to but not including CC.
7073 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7074 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7075 "Not enough arguments provided to the patchpoint intrinsic");
7077 // For AnyRegCC the arguments are lowered later on manually.
7078 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7079 std::pair<SDValue, SDValue> Result =
7080 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7083 SDNode *CallEnd = Result.second.getNode();
7084 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7085 CallEnd = CallEnd->getOperand(0).getNode();
7087 /// Get a call instruction from the call sequence chain.
7088 /// Tail calls are not allowed.
7089 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7090 "Expected a callseq node.");
7091 SDNode *Call = CallEnd->getOperand(0).getNode();
7092 bool HasGlue = Call->getGluedNode();
7094 // Replace the target specific call node with the patchable intrinsic.
7095 SmallVector<SDValue, 8> Ops;
7097 // Add the <id> and <numBytes> constants.
7098 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7099 Ops.push_back(DAG.getTargetConstant(
7100 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7101 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7102 Ops.push_back(DAG.getTargetConstant(
7103 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7105 // Assume that the Callee is a constant address.
7106 // FIXME: handle function symbols in the future.
7108 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7109 /*isTarget=*/true));
7111 // Adjust <numArgs> to account for any arguments that have been passed on the
7113 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7114 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7115 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7116 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7118 // Add the calling convention
7119 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7121 // Add the arguments we omitted previously. The register allocator should
7122 // place these in any free register.
7124 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7125 Ops.push_back(getValue(CS.getArgument(i)));
7127 // Push the arguments from the call instruction up to the register mask.
7128 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7129 Ops.append(Call->op_begin() + 2, e);
7131 // Push live variables for the stack map.
7132 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7134 // Push the register mask info.
7136 Ops.push_back(*(Call->op_end()-2));
7138 Ops.push_back(*(Call->op_end()-1));
7140 // Push the chain (this is originally the first operand of the call, but
7141 // becomes now the last or second to last operand).
7142 Ops.push_back(*(Call->op_begin()));
7144 // Push the glue flag (last operand).
7146 Ops.push_back(*(Call->op_end()-1));
7149 if (IsAnyRegCC && HasDef) {
7150 // Create the return types based on the intrinsic definition
7151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7152 SmallVector<EVT, 3> ValueVTs;
7153 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7154 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7156 // There is always a chain and a glue type at the end
7157 ValueVTs.push_back(MVT::Other);
7158 ValueVTs.push_back(MVT::Glue);
7159 NodeTys = DAG.getVTList(ValueVTs);
7161 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7163 // Replace the target specific call node with a PATCHPOINT node.
7164 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7165 getCurSDLoc(), NodeTys, Ops);
7167 // Update the NodeMap.
7170 setValue(CS.getInstruction(), SDValue(MN, 0));
7172 setValue(CS.getInstruction(), Result.first);
7175 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7176 // call sequence. Furthermore the location of the chain and glue can change
7177 // when the AnyReg calling convention is used and the intrinsic returns a
7179 if (IsAnyRegCC && HasDef) {
7180 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7181 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7182 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7184 DAG.ReplaceAllUsesWith(Call, MN);
7185 DAG.DeleteNode(Call);
7187 // Inform the Frame Information that we have a patchpoint in this function.
7188 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7191 /// Returns an AttributeSet representing the attributes applied to the return
7192 /// value of the given call.
7193 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7194 SmallVector<Attribute::AttrKind, 2> Attrs;
7196 Attrs.push_back(Attribute::SExt);
7198 Attrs.push_back(Attribute::ZExt);
7200 Attrs.push_back(Attribute::InReg);
7202 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7206 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7207 /// implementation, which just calls LowerCall.
7208 /// FIXME: When all targets are
7209 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7210 std::pair<SDValue, SDValue>
7211 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7212 // Handle the incoming return values from the call.
7214 Type *OrigRetTy = CLI.RetTy;
7215 SmallVector<EVT, 4> RetTys;
7216 SmallVector<uint64_t, 4> Offsets;
7217 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7219 SmallVector<ISD::OutputArg, 4> Outs;
7220 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7222 bool CanLowerReturn =
7223 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7224 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7226 SDValue DemoteStackSlot;
7227 int DemoteStackIdx = -100;
7228 if (!CanLowerReturn) {
7229 // FIXME: equivalent assert?
7230 // assert(!CS.hasInAllocaArgument() &&
7231 // "sret demotion is incompatible with inalloca");
7232 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7233 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7234 MachineFunction &MF = CLI.DAG.getMachineFunction();
7235 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7236 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7238 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7240 Entry.Node = DemoteStackSlot;
7241 Entry.Ty = StackSlotPtrType;
7242 Entry.isSExt = false;
7243 Entry.isZExt = false;
7244 Entry.isInReg = false;
7245 Entry.isSRet = true;
7246 Entry.isNest = false;
7247 Entry.isByVal = false;
7248 Entry.isReturned = false;
7249 Entry.Alignment = Align;
7250 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7251 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7253 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7255 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7256 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7257 for (unsigned i = 0; i != NumRegs; ++i) {
7258 ISD::InputArg MyFlags;
7259 MyFlags.VT = RegisterVT;
7261 MyFlags.Used = CLI.IsReturnValueUsed;
7263 MyFlags.Flags.setSExt();
7265 MyFlags.Flags.setZExt();
7267 MyFlags.Flags.setInReg();
7268 CLI.Ins.push_back(MyFlags);
7273 // Handle all of the outgoing arguments.
7275 CLI.OutVals.clear();
7276 ArgListTy &Args = CLI.getArgs();
7277 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7278 SmallVector<EVT, 4> ValueVTs;
7279 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7280 Type *FinalType = Args[i].Ty;
7281 if (Args[i].isByVal)
7282 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7283 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7284 FinalType, CLI.CallConv, CLI.IsVarArg);
7285 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7287 EVT VT = ValueVTs[Value];
7288 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7289 SDValue Op = SDValue(Args[i].Node.getNode(),
7290 Args[i].Node.getResNo() + Value);
7291 ISD::ArgFlagsTy Flags;
7292 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7298 if (Args[i].isInReg)
7302 if (Args[i].isByVal)
7304 if (Args[i].isInAlloca) {
7305 Flags.setInAlloca();
7306 // Set the byval flag for CCAssignFn callbacks that don't know about
7307 // inalloca. This way we can know how many bytes we should've allocated
7308 // and how many bytes a callee cleanup function will pop. If we port
7309 // inalloca to more targets, we'll have to add custom inalloca handling
7310 // in the various CC lowering callbacks.
7313 if (Args[i].isByVal || Args[i].isInAlloca) {
7314 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7315 Type *ElementTy = Ty->getElementType();
7316 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7317 // For ByVal, alignment should come from FE. BE will guess if this
7318 // info is not there but there are cases it cannot get right.
7319 unsigned FrameAlign;
7320 if (Args[i].Alignment)
7321 FrameAlign = Args[i].Alignment;
7323 FrameAlign = getByValTypeAlignment(ElementTy);
7324 Flags.setByValAlign(FrameAlign);
7329 Flags.setInConsecutiveRegs();
7330 Flags.setOrigAlign(OriginalAlignment);
7332 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7333 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7334 SmallVector<SDValue, 4> Parts(NumParts);
7335 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7338 ExtendKind = ISD::SIGN_EXTEND;
7339 else if (Args[i].isZExt)
7340 ExtendKind = ISD::ZERO_EXTEND;
7342 // Conservatively only handle 'returned' on non-vectors for now
7343 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7344 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7345 "unexpected use of 'returned'");
7346 // Before passing 'returned' to the target lowering code, ensure that
7347 // either the register MVT and the actual EVT are the same size or that
7348 // the return value and argument are extended in the same way; in these
7349 // cases it's safe to pass the argument register value unchanged as the
7350 // return register value (although it's at the target's option whether
7352 // TODO: allow code generation to take advantage of partially preserved
7353 // registers rather than clobbering the entire register when the
7354 // parameter extension method is not compatible with the return
7356 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7357 (ExtendKind != ISD::ANY_EXTEND &&
7358 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7359 Flags.setReturned();
7362 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7363 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7365 for (unsigned j = 0; j != NumParts; ++j) {
7366 // if it isn't first piece, alignment must be 1
7367 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7368 i < CLI.NumFixedArgs,
7369 i, j*Parts[j].getValueType().getStoreSize());
7370 if (NumParts > 1 && j == 0)
7371 MyFlags.Flags.setSplit();
7373 MyFlags.Flags.setOrigAlign(1);
7375 CLI.Outs.push_back(MyFlags);
7376 CLI.OutVals.push_back(Parts[j]);
7379 if (NeedsRegBlock && Value == NumValues - 1)
7380 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7384 SmallVector<SDValue, 4> InVals;
7385 CLI.Chain = LowerCall(CLI, InVals);
7387 // Verify that the target's LowerCall behaved as expected.
7388 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7389 "LowerCall didn't return a valid chain!");
7390 assert((!CLI.IsTailCall || InVals.empty()) &&
7391 "LowerCall emitted a return value for a tail call!");
7392 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7393 "LowerCall didn't emit the correct number of values!");
7395 // For a tail call, the return value is merely live-out and there aren't
7396 // any nodes in the DAG representing it. Return a special value to
7397 // indicate that a tail call has been emitted and no more Instructions
7398 // should be processed in the current block.
7399 if (CLI.IsTailCall) {
7400 CLI.DAG.setRoot(CLI.Chain);
7401 return std::make_pair(SDValue(), SDValue());
7404 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7405 assert(InVals[i].getNode() &&
7406 "LowerCall emitted a null value!");
7407 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7408 "LowerCall emitted a value with the wrong type!");
7411 SmallVector<SDValue, 4> ReturnValues;
7412 if (!CanLowerReturn) {
7413 // The instruction result is the result of loading from the
7414 // hidden sret parameter.
7415 SmallVector<EVT, 1> PVTs;
7416 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7418 ComputeValueVTs(*this, PtrRetTy, PVTs);
7419 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7420 EVT PtrVT = PVTs[0];
7422 unsigned NumValues = RetTys.size();
7423 ReturnValues.resize(NumValues);
7424 SmallVector<SDValue, 4> Chains(NumValues);
7426 for (unsigned i = 0; i < NumValues; ++i) {
7427 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7428 CLI.DAG.getConstant(Offsets[i], PtrVT));
7429 SDValue L = CLI.DAG.getLoad(
7430 RetTys[i], CLI.DL, CLI.Chain, Add,
7431 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7433 ReturnValues[i] = L;
7434 Chains[i] = L.getValue(1);
7437 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7439 // Collect the legal value parts into potentially illegal values
7440 // that correspond to the original function's return values.
7441 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7443 AssertOp = ISD::AssertSext;
7444 else if (CLI.RetZExt)
7445 AssertOp = ISD::AssertZext;
7446 unsigned CurReg = 0;
7447 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7449 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7450 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7452 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7453 NumRegs, RegisterVT, VT, nullptr,
7458 // For a function returning void, there is no return value. We can't create
7459 // such a node, so we just return a null return value in that case. In
7460 // that case, nothing will actually look at the value.
7461 if (ReturnValues.empty())
7462 return std::make_pair(SDValue(), CLI.Chain);
7465 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7466 CLI.DAG.getVTList(RetTys), ReturnValues);
7467 return std::make_pair(Res, CLI.Chain);
7470 void TargetLowering::LowerOperationWrapper(SDNode *N,
7471 SmallVectorImpl<SDValue> &Results,
7472 SelectionDAG &DAG) const {
7473 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7475 Results.push_back(Res);
7478 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7479 llvm_unreachable("LowerOperation not implemented for this target!");
7483 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7484 SDValue Op = getNonRegisterValue(V);
7485 assert((Op.getOpcode() != ISD::CopyFromReg ||
7486 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7487 "Copy from a reg to the same reg!");
7488 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7491 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7492 SDValue Chain = DAG.getEntryNode();
7494 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7495 FuncInfo.PreferredExtendType.end())
7497 : FuncInfo.PreferredExtendType[V];
7498 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7499 PendingExports.push_back(Chain);
7502 #include "llvm/CodeGen/SelectionDAGISel.h"
7504 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7505 /// entry block, return true. This includes arguments used by switches, since
7506 /// the switch may expand into multiple basic blocks.
7507 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7508 // With FastISel active, we may be splitting blocks, so force creation
7509 // of virtual registers for all non-dead arguments.
7511 return A->use_empty();
7513 const BasicBlock *Entry = A->getParent()->begin();
7514 for (const User *U : A->users())
7515 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7516 return false; // Use not in entry block.
7521 void SelectionDAGISel::LowerArguments(const Function &F) {
7522 SelectionDAG &DAG = SDB->DAG;
7523 SDLoc dl = SDB->getCurSDLoc();
7524 const DataLayout *DL = TLI->getDataLayout();
7525 SmallVector<ISD::InputArg, 16> Ins;
7527 if (!FuncInfo->CanLowerReturn) {
7528 // Put in an sret pointer parameter before all the other parameters.
7529 SmallVector<EVT, 1> ValueVTs;
7530 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7532 // NOTE: Assuming that a pointer will never break down to more than one VT
7534 ISD::ArgFlagsTy Flags;
7536 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7537 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7538 ISD::InputArg::NoArgIndex, 0);
7539 Ins.push_back(RetArg);
7542 // Set up the incoming argument description vector.
7544 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7545 I != E; ++I, ++Idx) {
7546 SmallVector<EVT, 4> ValueVTs;
7547 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7548 bool isArgValueUsed = !I->use_empty();
7549 unsigned PartBase = 0;
7550 Type *FinalType = I->getType();
7551 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7552 FinalType = cast<PointerType>(FinalType)->getElementType();
7553 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7554 FinalType, F.getCallingConv(), F.isVarArg());
7555 for (unsigned Value = 0, NumValues = ValueVTs.size();
7556 Value != NumValues; ++Value) {
7557 EVT VT = ValueVTs[Value];
7558 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7559 ISD::ArgFlagsTy Flags;
7560 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7562 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7564 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7566 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7568 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7570 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7572 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7573 Flags.setInAlloca();
7574 // Set the byval flag for CCAssignFn callbacks that don't know about
7575 // inalloca. This way we can know how many bytes we should've allocated
7576 // and how many bytes a callee cleanup function will pop. If we port
7577 // inalloca to more targets, we'll have to add custom inalloca handling
7578 // in the various CC lowering callbacks.
7581 if (Flags.isByVal() || Flags.isInAlloca()) {
7582 PointerType *Ty = cast<PointerType>(I->getType());
7583 Type *ElementTy = Ty->getElementType();
7584 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7585 // For ByVal, alignment should be passed from FE. BE will guess if
7586 // this info is not there but there are cases it cannot get right.
7587 unsigned FrameAlign;
7588 if (F.getParamAlignment(Idx))
7589 FrameAlign = F.getParamAlignment(Idx);
7591 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7592 Flags.setByValAlign(FrameAlign);
7594 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7597 Flags.setInConsecutiveRegs();
7598 Flags.setOrigAlign(OriginalAlignment);
7600 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7601 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7602 for (unsigned i = 0; i != NumRegs; ++i) {
7603 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7604 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7605 if (NumRegs > 1 && i == 0)
7606 MyFlags.Flags.setSplit();
7607 // if it isn't first piece, alignment must be 1
7609 MyFlags.Flags.setOrigAlign(1);
7610 Ins.push_back(MyFlags);
7612 if (NeedsRegBlock && Value == NumValues - 1)
7613 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7614 PartBase += VT.getStoreSize();
7618 // Call the target to set up the argument values.
7619 SmallVector<SDValue, 8> InVals;
7620 SDValue NewRoot = TLI->LowerFormalArguments(
7621 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7623 // Verify that the target's LowerFormalArguments behaved as expected.
7624 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7625 "LowerFormalArguments didn't return a valid chain!");
7626 assert(InVals.size() == Ins.size() &&
7627 "LowerFormalArguments didn't emit the correct number of values!");
7629 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7630 assert(InVals[i].getNode() &&
7631 "LowerFormalArguments emitted a null value!");
7632 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7633 "LowerFormalArguments emitted a value with the wrong type!");
7637 // Update the DAG with the new chain value resulting from argument lowering.
7638 DAG.setRoot(NewRoot);
7640 // Set up the argument values.
7643 if (!FuncInfo->CanLowerReturn) {
7644 // Create a virtual register for the sret pointer, and put in a copy
7645 // from the sret argument into it.
7646 SmallVector<EVT, 1> ValueVTs;
7647 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7648 MVT VT = ValueVTs[0].getSimpleVT();
7649 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7650 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7651 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7652 RegVT, VT, nullptr, AssertOp);
7654 MachineFunction& MF = SDB->DAG.getMachineFunction();
7655 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7656 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7657 FuncInfo->DemoteRegister = SRetReg;
7659 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7660 DAG.setRoot(NewRoot);
7662 // i indexes lowered arguments. Bump it past the hidden sret argument.
7663 // Idx indexes LLVM arguments. Don't touch it.
7667 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7669 SmallVector<SDValue, 4> ArgValues;
7670 SmallVector<EVT, 4> ValueVTs;
7671 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7672 unsigned NumValues = ValueVTs.size();
7674 // If this argument is unused then remember its value. It is used to generate
7675 // debugging information.
7676 if (I->use_empty() && NumValues) {
7677 SDB->setUnusedArgValue(I, InVals[i]);
7679 // Also remember any frame index for use in FastISel.
7680 if (FrameIndexSDNode *FI =
7681 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7682 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7685 for (unsigned Val = 0; Val != NumValues; ++Val) {
7686 EVT VT = ValueVTs[Val];
7687 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7688 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7690 if (!I->use_empty()) {
7691 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7692 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7693 AssertOp = ISD::AssertSext;
7694 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7695 AssertOp = ISD::AssertZext;
7697 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7698 NumParts, PartVT, VT,
7699 nullptr, AssertOp));
7705 // We don't need to do anything else for unused arguments.
7706 if (ArgValues.empty())
7709 // Note down frame index.
7710 if (FrameIndexSDNode *FI =
7711 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7712 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7714 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7715 SDB->getCurSDLoc());
7717 SDB->setValue(I, Res);
7718 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7719 if (LoadSDNode *LNode =
7720 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7721 if (FrameIndexSDNode *FI =
7722 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7723 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7726 // If this argument is live outside of the entry block, insert a copy from
7727 // wherever we got it to the vreg that other BB's will reference it as.
7728 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7729 // If we can, though, try to skip creating an unnecessary vreg.
7730 // FIXME: This isn't very clean... it would be nice to make this more
7731 // general. It's also subtly incompatible with the hacks FastISel
7733 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7734 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7735 FuncInfo->ValueMap[I] = Reg;
7739 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7740 FuncInfo->InitializeRegForValue(I);
7741 SDB->CopyToExportRegsIfNeeded(I);
7745 assert(i == InVals.size() && "Argument register count mismatch!");
7747 // Finally, if the target has anything special to do, allow it to do so.
7748 EmitFunctionEntryCode();
7751 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7752 /// ensure constants are generated when needed. Remember the virtual registers
7753 /// that need to be added to the Machine PHI nodes as input. We cannot just
7754 /// directly add them, because expansion might result in multiple MBB's for one
7755 /// BB. As such, the start of the BB might correspond to a different MBB than
7759 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7760 const TerminatorInst *TI = LLVMBB->getTerminator();
7762 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7764 // Check successor nodes' PHI nodes that expect a constant to be available
7766 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7767 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7768 if (!isa<PHINode>(SuccBB->begin())) continue;
7769 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7771 // If this terminator has multiple identical successors (common for
7772 // switches), only handle each succ once.
7773 if (!SuccsHandled.insert(SuccMBB).second)
7776 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7778 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7779 // nodes and Machine PHI nodes, but the incoming operands have not been
7781 for (BasicBlock::const_iterator I = SuccBB->begin();
7782 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7783 // Ignore dead phi's.
7784 if (PN->use_empty()) continue;
7787 if (PN->getType()->isEmptyTy())
7791 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7793 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7794 unsigned &RegOut = ConstantsOut[C];
7796 RegOut = FuncInfo.CreateRegs(C->getType());
7797 CopyValueToVirtualRegister(C, RegOut);
7801 DenseMap<const Value *, unsigned>::iterator I =
7802 FuncInfo.ValueMap.find(PHIOp);
7803 if (I != FuncInfo.ValueMap.end())
7806 assert(isa<AllocaInst>(PHIOp) &&
7807 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7808 "Didn't codegen value into a register!??");
7809 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7810 CopyValueToVirtualRegister(PHIOp, Reg);
7814 // Remember that this register needs to added to the machine PHI node as
7815 // the input for this MBB.
7816 SmallVector<EVT, 4> ValueVTs;
7817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7818 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7819 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7820 EVT VT = ValueVTs[vti];
7821 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7822 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7823 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7824 Reg += NumRegisters;
7829 ConstantsOut.clear();
7832 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7835 SelectionDAGBuilder::StackProtectorDescriptor::
7836 AddSuccessorMBB(const BasicBlock *BB,
7837 MachineBasicBlock *ParentMBB,
7839 MachineBasicBlock *SuccMBB) {
7840 // If SuccBB has not been created yet, create it.
7842 MachineFunction *MF = ParentMBB->getParent();
7843 MachineFunction::iterator BBI = ParentMBB;
7844 SuccMBB = MF->CreateMachineBasicBlock(BB);
7845 MF->insert(++BBI, SuccMBB);
7847 // Add it as a successor of ParentMBB.
7848 ParentMBB->addSuccessor(
7849 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));