1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 // Update machine-CFG edges.
1164 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1165 MachineBasicBlock *CatchingMBB = FuncInfo.MBBMap[I.getNormalDest()];
1166 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1167 PadMBB->addSuccessor(CatchingMBB);
1168 PadMBB->addSuccessor(UnwindMBB);
1170 CatchingMBB->setIsEHFuncletEntry();
1171 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1172 MMI.setHasEHFunclets(true);
1175 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1176 // Update machine-CFG edge.
1177 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1178 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1179 PadMBB->addSuccessor(TargetMBB);
1181 // Create the terminator node.
1182 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1183 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1187 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1188 // If this unwinds to caller, we don't need a DAG node hanging around.
1189 if (!I.hasUnwindDest())
1192 // Update machine-CFG edge.
1193 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1194 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1195 PadMBB->addSuccessor(UnwindMBB);
1198 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1199 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1200 MMI.setHasEHFunclets(true);
1201 report_fatal_error("visitCleanupPad not yet implemented!");
1204 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1205 report_fatal_error("visitCleanupRet not yet implemented!");
1208 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1209 report_fatal_error("visitTerminatePad not yet implemented!");
1212 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1214 auto &DL = DAG.getDataLayout();
1215 SDValue Chain = getControlRoot();
1216 SmallVector<ISD::OutputArg, 8> Outs;
1217 SmallVector<SDValue, 8> OutVals;
1219 if (!FuncInfo.CanLowerReturn) {
1220 unsigned DemoteReg = FuncInfo.DemoteRegister;
1221 const Function *F = I.getParent()->getParent();
1223 // Emit a store of the return value through the virtual register.
1224 // Leave Outs empty so that LowerReturn won't try to load return
1225 // registers the usual way.
1226 SmallVector<EVT, 1> PtrValueVTs;
1227 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1230 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1231 SDValue RetOp = getValue(I.getOperand(0));
1233 SmallVector<EVT, 4> ValueVTs;
1234 SmallVector<uint64_t, 4> Offsets;
1235 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1236 unsigned NumValues = ValueVTs.size();
1238 SmallVector<SDValue, 4> Chains(NumValues);
1239 for (unsigned i = 0; i != NumValues; ++i) {
1240 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1241 RetPtr.getValueType(), RetPtr,
1242 DAG.getIntPtrConstant(Offsets[i],
1245 DAG.getStore(Chain, getCurSDLoc(),
1246 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1247 // FIXME: better loc info would be nice.
1248 Add, MachinePointerInfo(), false, false, 0);
1251 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1252 MVT::Other, Chains);
1253 } else if (I.getNumOperands() != 0) {
1254 SmallVector<EVT, 4> ValueVTs;
1255 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1256 unsigned NumValues = ValueVTs.size();
1258 SDValue RetOp = getValue(I.getOperand(0));
1260 const Function *F = I.getParent()->getParent();
1262 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1263 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1265 ExtendKind = ISD::SIGN_EXTEND;
1266 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1268 ExtendKind = ISD::ZERO_EXTEND;
1270 LLVMContext &Context = F->getContext();
1271 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1274 for (unsigned j = 0; j != NumValues; ++j) {
1275 EVT VT = ValueVTs[j];
1277 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1278 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1280 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1281 MVT PartVT = TLI.getRegisterType(Context, VT);
1282 SmallVector<SDValue, 4> Parts(NumParts);
1283 getCopyToParts(DAG, getCurSDLoc(),
1284 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1285 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1287 // 'inreg' on function refers to return value
1288 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1292 // Propagate extension type if any
1293 if (ExtendKind == ISD::SIGN_EXTEND)
1295 else if (ExtendKind == ISD::ZERO_EXTEND)
1298 for (unsigned i = 0; i < NumParts; ++i) {
1299 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1300 VT, /*isfixed=*/true, 0, 0));
1301 OutVals.push_back(Parts[i]);
1307 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1308 CallingConv::ID CallConv =
1309 DAG.getMachineFunction().getFunction()->getCallingConv();
1310 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1311 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1313 // Verify that the target's LowerReturn behaved as expected.
1314 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1315 "LowerReturn didn't return a valid chain!");
1317 // Update the DAG with the new chain value resulting from return lowering.
1321 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1322 /// created for it, emit nodes to copy the value into the virtual
1324 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1326 if (V->getType()->isEmptyTy())
1329 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1330 if (VMI != FuncInfo.ValueMap.end()) {
1331 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1332 CopyValueToVirtualRegister(V, VMI->second);
1336 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1337 /// the current basic block, add it to ValueMap now so that we'll get a
1339 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1340 // No need to export constants.
1341 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1343 // Already exported?
1344 if (FuncInfo.isExportedInst(V)) return;
1346 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1347 CopyValueToVirtualRegister(V, Reg);
1350 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1351 const BasicBlock *FromBB) {
1352 // The operands of the setcc have to be in this block. We don't know
1353 // how to export them from some other block.
1354 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1355 // Can export from current BB.
1356 if (VI->getParent() == FromBB)
1359 // Is already exported, noop.
1360 return FuncInfo.isExportedInst(V);
1363 // If this is an argument, we can export it if the BB is the entry block or
1364 // if it is already exported.
1365 if (isa<Argument>(V)) {
1366 if (FromBB == &FromBB->getParent()->getEntryBlock())
1369 // Otherwise, can only export this if it is already exported.
1370 return FuncInfo.isExportedInst(V);
1373 // Otherwise, constants can always be exported.
1377 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1378 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1379 const MachineBasicBlock *Dst) const {
1380 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1383 const BasicBlock *SrcBB = Src->getBasicBlock();
1384 const BasicBlock *DstBB = Dst->getBasicBlock();
1385 return BPI->getEdgeWeight(SrcBB, DstBB);
1388 void SelectionDAGBuilder::
1389 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1390 uint32_t Weight /* = 0 */) {
1392 Weight = getEdgeWeight(Src, Dst);
1393 Src->addSuccessor(Dst, Weight);
1397 static bool InBlock(const Value *V, const BasicBlock *BB) {
1398 if (const Instruction *I = dyn_cast<Instruction>(V))
1399 return I->getParent() == BB;
1403 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1404 /// This function emits a branch and is used at the leaves of an OR or an
1405 /// AND operator tree.
1408 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1409 MachineBasicBlock *TBB,
1410 MachineBasicBlock *FBB,
1411 MachineBasicBlock *CurBB,
1412 MachineBasicBlock *SwitchBB,
1415 const BasicBlock *BB = CurBB->getBasicBlock();
1417 // If the leaf of the tree is a comparison, merge the condition into
1419 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1420 // The operands of the cmp have to be in this block. We don't know
1421 // how to export them from some other block. If this is the first block
1422 // of the sequence, no exporting is needed.
1423 if (CurBB == SwitchBB ||
1424 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1425 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1426 ISD::CondCode Condition;
1427 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1428 Condition = getICmpCondCode(IC->getPredicate());
1430 const FCmpInst *FC = cast<FCmpInst>(Cond);
1431 Condition = getFCmpCondCode(FC->getPredicate());
1432 if (TM.Options.NoNaNsFPMath)
1433 Condition = getFCmpCodeWithoutNaN(Condition);
1436 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1437 TBB, FBB, CurBB, TWeight, FWeight);
1438 SwitchCases.push_back(CB);
1443 // Create a CaseBlock record representing this branch.
1444 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1445 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1446 SwitchCases.push_back(CB);
1449 /// Scale down both weights to fit into uint32_t.
1450 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1451 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1452 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1453 NewTrue = NewTrue / Scale;
1454 NewFalse = NewFalse / Scale;
1457 /// FindMergedConditions - If Cond is an expression like
1458 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1459 MachineBasicBlock *TBB,
1460 MachineBasicBlock *FBB,
1461 MachineBasicBlock *CurBB,
1462 MachineBasicBlock *SwitchBB,
1463 Instruction::BinaryOps Opc,
1466 // If this node is not part of the or/and tree, emit it as a branch.
1467 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1468 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1469 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1470 BOp->getParent() != CurBB->getBasicBlock() ||
1471 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1472 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1473 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1478 // Create TmpBB after CurBB.
1479 MachineFunction::iterator BBI = CurBB;
1480 MachineFunction &MF = DAG.getMachineFunction();
1481 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1482 CurBB->getParent()->insert(++BBI, TmpBB);
1484 if (Opc == Instruction::Or) {
1485 // Codegen X | Y as:
1494 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1495 // The requirement is that
1496 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1497 // = TrueProb for original BB.
1498 // Assuming the original weights are A and B, one choice is to set BB1's
1499 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1501 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1502 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1503 // TmpBB, but the math is more complicated.
1505 uint64_t NewTrueWeight = TWeight;
1506 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1507 ScaleWeights(NewTrueWeight, NewFalseWeight);
1508 // Emit the LHS condition.
1509 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1510 NewTrueWeight, NewFalseWeight);
1512 NewTrueWeight = TWeight;
1513 NewFalseWeight = 2 * (uint64_t)FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the RHS condition into TmpBB.
1516 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 assert(Opc == Instruction::And && "Unknown merge op!");
1520 // Codegen X & Y as:
1528 // This requires creation of TmpBB after CurBB.
1530 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1531 // The requirement is that
1532 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1533 // = FalseProb for original BB.
1534 // Assuming the original weights are A and B, one choice is to set BB1's
1535 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1537 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1539 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1540 uint64_t NewFalseWeight = FWeight;
1541 ScaleWeights(NewTrueWeight, NewFalseWeight);
1542 // Emit the LHS condition.
1543 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1544 NewTrueWeight, NewFalseWeight);
1546 NewTrueWeight = 2 * (uint64_t)TWeight;
1547 NewFalseWeight = FWeight;
1548 ScaleWeights(NewTrueWeight, NewFalseWeight);
1549 // Emit the RHS condition into TmpBB.
1550 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1551 NewTrueWeight, NewFalseWeight);
1555 /// If the set of cases should be emitted as a series of branches, return true.
1556 /// If we should emit this as a bunch of and/or'd together conditions, return
1559 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1560 if (Cases.size() != 2) return true;
1562 // If this is two comparisons of the same values or'd or and'd together, they
1563 // will get folded into a single comparison, so don't emit two blocks.
1564 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1565 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1566 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1567 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1571 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1572 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1573 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1574 Cases[0].CC == Cases[1].CC &&
1575 isa<Constant>(Cases[0].CmpRHS) &&
1576 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1577 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1579 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1586 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1587 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1589 // Update machine-CFG edges.
1590 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1592 if (I.isUnconditional()) {
1593 // Update machine-CFG edges.
1594 BrMBB->addSuccessor(Succ0MBB);
1596 // If this is not a fall-through branch or optimizations are switched off,
1598 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1599 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1600 MVT::Other, getControlRoot(),
1601 DAG.getBasicBlock(Succ0MBB)));
1606 // If this condition is one of the special cases we handle, do special stuff
1608 const Value *CondVal = I.getCondition();
1609 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1611 // If this is a series of conditions that are or'd or and'd together, emit
1612 // this as a sequence of branches instead of setcc's with and/or operations.
1613 // As long as jumps are not expensive, this should improve performance.
1614 // For example, instead of something like:
1627 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1628 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1629 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1630 BOp->getOpcode() == Instruction::Or)) {
1631 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1632 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1633 getEdgeWeight(BrMBB, Succ1MBB));
1634 // If the compares in later blocks need to use values not currently
1635 // exported from this block, export them now. This block should always
1636 // be the first entry.
1637 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1639 // Allow some cases to be rejected.
1640 if (ShouldEmitAsBranches(SwitchCases)) {
1641 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1642 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1643 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1646 // Emit the branch for this block.
1647 visitSwitchCase(SwitchCases[0], BrMBB);
1648 SwitchCases.erase(SwitchCases.begin());
1652 // Okay, we decided not to do this, remove any inserted MBB's and clear
1654 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1655 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1657 SwitchCases.clear();
1661 // Create a CaseBlock record representing this branch.
1662 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1663 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1665 // Use visitSwitchCase to actually insert the fast branch sequence for this
1667 visitSwitchCase(CB, BrMBB);
1670 /// visitSwitchCase - Emits the necessary code to represent a single node in
1671 /// the binary search tree resulting from lowering a switch instruction.
1672 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1673 MachineBasicBlock *SwitchBB) {
1675 SDValue CondLHS = getValue(CB.CmpLHS);
1676 SDLoc dl = getCurSDLoc();
1678 // Build the setcc now.
1680 // Fold "(X == true)" to X and "(X == false)" to !X to
1681 // handle common cases produced by branch lowering.
1682 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1683 CB.CC == ISD::SETEQ)
1685 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1686 CB.CC == ISD::SETEQ) {
1687 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1688 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1690 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1692 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1694 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1695 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1697 SDValue CmpOp = getValue(CB.CmpMHS);
1698 EVT VT = CmpOp.getValueType();
1700 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1701 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1704 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1705 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1706 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1707 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1711 // Update successor info
1712 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1713 // TrueBB and FalseBB are always different unless the incoming IR is
1714 // degenerate. This only happens when running llc on weird IR.
1715 if (CB.TrueBB != CB.FalseBB)
1716 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1718 // If the lhs block is the next block, invert the condition so that we can
1719 // fall through to the lhs instead of the rhs block.
1720 if (CB.TrueBB == NextBlock(SwitchBB)) {
1721 std::swap(CB.TrueBB, CB.FalseBB);
1722 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1723 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1726 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1727 MVT::Other, getControlRoot(), Cond,
1728 DAG.getBasicBlock(CB.TrueBB));
1730 // Insert the false branch. Do this even if it's a fall through branch,
1731 // this makes it easier to do DAG optimizations which require inverting
1732 // the branch condition.
1733 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1734 DAG.getBasicBlock(CB.FalseBB));
1736 DAG.setRoot(BrCond);
1739 /// visitJumpTable - Emit JumpTable node in the current MBB
1740 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1741 // Emit the code for the jump table
1742 assert(JT.Reg != -1U && "Should lower JT Header first!");
1743 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1744 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1746 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1747 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1748 MVT::Other, Index.getValue(1),
1750 DAG.setRoot(BrJumpTable);
1753 /// visitJumpTableHeader - This function emits necessary code to produce index
1754 /// in the JumpTable from switch case.
1755 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1756 JumpTableHeader &JTH,
1757 MachineBasicBlock *SwitchBB) {
1758 SDLoc dl = getCurSDLoc();
1760 // Subtract the lowest switch case value from the value being switched on and
1761 // conditional branch to default mbb if the result is greater than the
1762 // difference between smallest and largest cases.
1763 SDValue SwitchOp = getValue(JTH.SValue);
1764 EVT VT = SwitchOp.getValueType();
1765 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1766 DAG.getConstant(JTH.First, dl, VT));
1768 // The SDNode we just created, which holds the value being switched on minus
1769 // the smallest case value, needs to be copied to a virtual register so it
1770 // can be used as an index into the jump table in a subsequent basic block.
1771 // This value may be smaller or larger than the target's pointer type, and
1772 // therefore require extension or truncating.
1773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1774 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1776 unsigned JumpTableReg =
1777 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1778 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1779 JumpTableReg, SwitchOp);
1780 JT.Reg = JumpTableReg;
1782 // Emit the range check for the jump table, and branch to the default block
1783 // for the switch statement if the value being switched on exceeds the largest
1784 // case in the switch.
1785 SDValue CMP = DAG.getSetCC(
1786 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1787 Sub.getValueType()),
1788 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1790 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1791 MVT::Other, CopyTo, CMP,
1792 DAG.getBasicBlock(JT.Default));
1794 // Avoid emitting unnecessary branches to the next block.
1795 if (JT.MBB != NextBlock(SwitchBB))
1796 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1797 DAG.getBasicBlock(JT.MBB));
1799 DAG.setRoot(BrCond);
1802 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1803 /// tail spliced into a stack protector check success bb.
1805 /// For a high level explanation of how this fits into the stack protector
1806 /// generation see the comment on the declaration of class
1807 /// StackProtectorDescriptor.
1808 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1809 MachineBasicBlock *ParentBB) {
1811 // First create the loads to the guard/stack slot for the comparison.
1812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1813 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1815 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1816 int FI = MFI->getStackProtectorIndex();
1818 const Value *IRGuard = SPD.getGuard();
1819 SDValue GuardPtr = getValue(IRGuard);
1820 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1822 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1825 SDLoc dl = getCurSDLoc();
1827 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1828 // guard value from the virtual register holding the value. Otherwise, emit a
1829 // volatile load to retrieve the stack guard value.
1830 unsigned GuardReg = SPD.getGuardReg();
1832 if (GuardReg && TLI.useLoadStackGuardNode())
1833 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1836 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1837 GuardPtr, MachinePointerInfo(IRGuard, 0),
1838 true, false, false, Align);
1840 SDValue StackSlot = DAG.getLoad(
1841 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1842 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1843 false, false, Align);
1845 // Perform the comparison via a subtract/getsetcc.
1846 EVT VT = Guard.getValueType();
1847 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1849 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1851 Sub.getValueType()),
1852 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1854 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1855 // branch to failure MBB.
1856 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1857 MVT::Other, StackSlot.getOperand(0),
1858 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1859 // Otherwise branch to success MBB.
1860 SDValue Br = DAG.getNode(ISD::BR, dl,
1862 DAG.getBasicBlock(SPD.getSuccessMBB()));
1867 /// Codegen the failure basic block for a stack protector check.
1869 /// A failure stack protector machine basic block consists simply of a call to
1870 /// __stack_chk_fail().
1872 /// For a high level explanation of how this fits into the stack protector
1873 /// generation see the comment on the declaration of class
1874 /// StackProtectorDescriptor.
1876 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1877 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1879 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1880 nullptr, 0, false, getCurSDLoc(), false, false).second;
1884 /// visitBitTestHeader - This function emits necessary code to produce value
1885 /// suitable for "bit tests"
1886 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1887 MachineBasicBlock *SwitchBB) {
1888 SDLoc dl = getCurSDLoc();
1890 // Subtract the minimum value
1891 SDValue SwitchOp = getValue(B.SValue);
1892 EVT VT = SwitchOp.getValueType();
1893 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1894 DAG.getConstant(B.First, dl, VT));
1897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1898 SDValue RangeCmp = DAG.getSetCC(
1899 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1900 Sub.getValueType()),
1901 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1903 // Determine the type of the test operands.
1904 bool UsePtrType = false;
1905 if (!TLI.isTypeLegal(VT))
1908 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1909 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1910 // Switch table case range are encoded into series of masks.
1911 // Just use pointer type, it's guaranteed to fit.
1917 VT = TLI.getPointerTy(DAG.getDataLayout());
1918 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1921 B.RegVT = VT.getSimpleVT();
1922 B.Reg = FuncInfo.CreateReg(B.RegVT);
1923 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1925 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1927 uint32_t DefaultWeight = getEdgeWeight(SwitchBB, B.Default);
1928 addSuccessorWithWeight(SwitchBB, B.Default, DefaultWeight);
1929 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1931 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1932 MVT::Other, CopyTo, RangeCmp,
1933 DAG.getBasicBlock(B.Default));
1935 // Avoid emitting unnecessary branches to the next block.
1936 if (MBB != NextBlock(SwitchBB))
1937 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1938 DAG.getBasicBlock(MBB));
1940 DAG.setRoot(BrRange);
1943 /// visitBitTestCase - this function produces one "bit test"
1944 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1945 MachineBasicBlock* NextMBB,
1946 uint32_t BranchWeightToNext,
1949 MachineBasicBlock *SwitchBB) {
1950 SDLoc dl = getCurSDLoc();
1952 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1954 unsigned PopCount = countPopulation(B.Mask);
1955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1956 if (PopCount == 1) {
1957 // Testing for a single bit; just compare the shift count with what it
1958 // would need to be to shift a 1 bit in that position.
1960 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1961 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1963 } else if (PopCount == BB.Range) {
1964 // There is only one zero bit in the range, test for it directly.
1966 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1967 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1970 // Make desired shift
1971 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1972 DAG.getConstant(1, dl, VT), ShiftOp);
1974 // Emit bit tests and jumps
1975 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1976 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1978 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1979 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1982 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1983 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1984 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1985 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1987 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1988 MVT::Other, getControlRoot(),
1989 Cmp, DAG.getBasicBlock(B.TargetBB));
1991 // Avoid emitting unnecessary branches to the next block.
1992 if (NextMBB != NextBlock(SwitchBB))
1993 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1994 DAG.getBasicBlock(NextMBB));
1999 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2000 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2002 // Retrieve successors.
2003 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2004 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2006 const Value *Callee(I.getCalledValue());
2007 const Function *Fn = dyn_cast<Function>(Callee);
2008 if (isa<InlineAsm>(Callee))
2010 else if (Fn && Fn->isIntrinsic()) {
2011 switch (Fn->getIntrinsicID()) {
2013 llvm_unreachable("Cannot invoke this intrinsic");
2014 case Intrinsic::donothing:
2015 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2017 case Intrinsic::experimental_patchpoint_void:
2018 case Intrinsic::experimental_patchpoint_i64:
2019 visitPatchpoint(&I, LandingPad);
2021 case Intrinsic::experimental_gc_statepoint:
2022 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2026 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2028 // If the value of the invoke is used outside of its defining block, make it
2029 // available as a virtual register.
2030 // We already took care of the exported value for the statepoint instruction
2031 // during call to the LowerStatepoint.
2032 if (!isStatepoint(I)) {
2033 CopyToExportRegsIfNeeded(&I);
2036 // Update successor info
2037 addSuccessorWithWeight(InvokeMBB, Return);
2038 addSuccessorWithWeight(InvokeMBB, LandingPad);
2040 // Drop into normal successor.
2041 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2042 MVT::Other, getControlRoot(),
2043 DAG.getBasicBlock(Return)));
2046 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2047 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2050 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2051 assert(FuncInfo.MBB->isEHPad() &&
2052 "Call to landingpad not in landing pad!");
2054 MachineBasicBlock *MBB = FuncInfo.MBB;
2055 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2056 AddLandingPadInfo(LP, MMI, MBB);
2058 // If there aren't registers to copy the values into (e.g., during SjLj
2059 // exceptions), then don't bother to create these DAG nodes.
2060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2061 if (TLI.getExceptionPointerRegister() == 0 &&
2062 TLI.getExceptionSelectorRegister() == 0)
2065 SmallVector<EVT, 2> ValueVTs;
2066 SDLoc dl = getCurSDLoc();
2067 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2068 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2070 // Get the two live-in registers as SDValues. The physregs have already been
2071 // copied into virtual registers.
2073 if (FuncInfo.ExceptionPointerVirtReg) {
2074 Ops[0] = DAG.getZExtOrTrunc(
2075 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2076 FuncInfo.ExceptionPointerVirtReg,
2077 TLI.getPointerTy(DAG.getDataLayout())),
2080 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2082 Ops[1] = DAG.getZExtOrTrunc(
2083 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2084 FuncInfo.ExceptionSelectorVirtReg,
2085 TLI.getPointerTy(DAG.getDataLayout())),
2089 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2090 DAG.getVTList(ValueVTs), Ops);
2094 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2096 for (const CaseCluster &CC : Clusters)
2097 assert(CC.Low == CC.High && "Input clusters must be single-case");
2100 std::sort(Clusters.begin(), Clusters.end(),
2101 [](const CaseCluster &a, const CaseCluster &b) {
2102 return a.Low->getValue().slt(b.Low->getValue());
2105 // Merge adjacent clusters with the same destination.
2106 const unsigned N = Clusters.size();
2107 unsigned DstIndex = 0;
2108 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2109 CaseCluster &CC = Clusters[SrcIndex];
2110 const ConstantInt *CaseVal = CC.Low;
2111 MachineBasicBlock *Succ = CC.MBB;
2113 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2114 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2115 // If this case has the same successor and is a neighbour, merge it into
2116 // the previous cluster.
2117 Clusters[DstIndex - 1].High = CaseVal;
2118 Clusters[DstIndex - 1].Weight += CC.Weight;
2119 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2121 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2122 sizeof(Clusters[SrcIndex]));
2125 Clusters.resize(DstIndex);
2128 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2129 MachineBasicBlock *Last) {
2131 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2132 if (JTCases[i].first.HeaderBB == First)
2133 JTCases[i].first.HeaderBB = Last;
2135 // Update BitTestCases.
2136 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2137 if (BitTestCases[i].Parent == First)
2138 BitTestCases[i].Parent = Last;
2141 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2142 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2144 // Update machine-CFG edges with unique successors.
2145 SmallSet<BasicBlock*, 32> Done;
2146 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2147 BasicBlock *BB = I.getSuccessor(i);
2148 bool Inserted = Done.insert(BB).second;
2152 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2153 addSuccessorWithWeight(IndirectBrMBB, Succ);
2156 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2157 MVT::Other, getControlRoot(),
2158 getValue(I.getAddress())));
2161 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2162 if (DAG.getTarget().Options.TrapUnreachable)
2163 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2166 void SelectionDAGBuilder::visitFSub(const User &I) {
2167 // -0.0 - X --> fneg
2168 Type *Ty = I.getType();
2169 if (isa<Constant>(I.getOperand(0)) &&
2170 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2171 SDValue Op2 = getValue(I.getOperand(1));
2172 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2173 Op2.getValueType(), Op2));
2177 visitBinary(I, ISD::FSUB);
2180 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2181 SDValue Op1 = getValue(I.getOperand(0));
2182 SDValue Op2 = getValue(I.getOperand(1));
2189 if (const OverflowingBinaryOperator *OFBinOp =
2190 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2191 nuw = OFBinOp->hasNoUnsignedWrap();
2192 nsw = OFBinOp->hasNoSignedWrap();
2194 if (const PossiblyExactOperator *ExactOp =
2195 dyn_cast<const PossiblyExactOperator>(&I))
2196 exact = ExactOp->isExact();
2197 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2198 FMF = FPOp->getFastMathFlags();
2201 Flags.setExact(exact);
2202 Flags.setNoSignedWrap(nsw);
2203 Flags.setNoUnsignedWrap(nuw);
2204 if (EnableFMFInDAG) {
2205 Flags.setAllowReciprocal(FMF.allowReciprocal());
2206 Flags.setNoInfs(FMF.noInfs());
2207 Flags.setNoNaNs(FMF.noNaNs());
2208 Flags.setNoSignedZeros(FMF.noSignedZeros());
2209 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2211 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2213 setValue(&I, BinNodeValue);
2216 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2217 SDValue Op1 = getValue(I.getOperand(0));
2218 SDValue Op2 = getValue(I.getOperand(1));
2220 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2221 Op2.getValueType(), DAG.getDataLayout());
2223 // Coerce the shift amount to the right type if we can.
2224 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2225 unsigned ShiftSize = ShiftTy.getSizeInBits();
2226 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2227 SDLoc DL = getCurSDLoc();
2229 // If the operand is smaller than the shift count type, promote it.
2230 if (ShiftSize > Op2Size)
2231 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2233 // If the operand is larger than the shift count type but the shift
2234 // count type has enough bits to represent any shift value, truncate
2235 // it now. This is a common case and it exposes the truncate to
2236 // optimization early.
2237 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2238 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2239 // Otherwise we'll need to temporarily settle for some other convenient
2240 // type. Type legalization will make adjustments once the shiftee is split.
2242 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2249 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2251 if (const OverflowingBinaryOperator *OFBinOp =
2252 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2253 nuw = OFBinOp->hasNoUnsignedWrap();
2254 nsw = OFBinOp->hasNoSignedWrap();
2256 if (const PossiblyExactOperator *ExactOp =
2257 dyn_cast<const PossiblyExactOperator>(&I))
2258 exact = ExactOp->isExact();
2261 Flags.setExact(exact);
2262 Flags.setNoSignedWrap(nsw);
2263 Flags.setNoUnsignedWrap(nuw);
2264 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2269 void SelectionDAGBuilder::visitSDiv(const User &I) {
2270 SDValue Op1 = getValue(I.getOperand(0));
2271 SDValue Op2 = getValue(I.getOperand(1));
2274 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2275 cast<PossiblyExactOperator>(&I)->isExact());
2276 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2280 void SelectionDAGBuilder::visitICmp(const User &I) {
2281 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2282 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2283 predicate = IC->getPredicate();
2284 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2285 predicate = ICmpInst::Predicate(IC->getPredicate());
2286 SDValue Op1 = getValue(I.getOperand(0));
2287 SDValue Op2 = getValue(I.getOperand(1));
2288 ISD::CondCode Opcode = getICmpCondCode(predicate);
2290 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2292 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2295 void SelectionDAGBuilder::visitFCmp(const User &I) {
2296 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2297 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2298 predicate = FC->getPredicate();
2299 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2300 predicate = FCmpInst::Predicate(FC->getPredicate());
2301 SDValue Op1 = getValue(I.getOperand(0));
2302 SDValue Op2 = getValue(I.getOperand(1));
2303 ISD::CondCode Condition = getFCmpCondCode(predicate);
2304 if (TM.Options.NoNaNsFPMath)
2305 Condition = getFCmpCodeWithoutNaN(Condition);
2306 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2308 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2311 void SelectionDAGBuilder::visitSelect(const User &I) {
2312 SmallVector<EVT, 4> ValueVTs;
2313 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2315 unsigned NumValues = ValueVTs.size();
2316 if (NumValues == 0) return;
2318 SmallVector<SDValue, 4> Values(NumValues);
2319 SDValue Cond = getValue(I.getOperand(0));
2320 SDValue LHSVal = getValue(I.getOperand(1));
2321 SDValue RHSVal = getValue(I.getOperand(2));
2322 auto BaseOps = {Cond};
2323 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2324 ISD::VSELECT : ISD::SELECT;
2326 // Min/max matching is only viable if all output VTs are the same.
2327 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2328 EVT VT = ValueVTs[0];
2329 LLVMContext &Ctx = *DAG.getContext();
2330 auto &TLI = DAG.getTargetLoweringInfo();
2331 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2332 VT = TLI.getTypeToTransformTo(Ctx, VT);
2335 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2336 ISD::NodeType Opc = ISD::DELETED_NODE;
2337 switch (SPR.Flavor) {
2338 case SPF_UMAX: Opc = ISD::UMAX; break;
2339 case SPF_UMIN: Opc = ISD::UMIN; break;
2340 case SPF_SMAX: Opc = ISD::SMAX; break;
2341 case SPF_SMIN: Opc = ISD::SMIN; break;
2343 switch (SPR.NaNBehavior) {
2344 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2345 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2346 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2347 case SPNB_RETURNS_ANY:
2348 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2354 switch (SPR.NaNBehavior) {
2355 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2356 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2357 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2358 case SPNB_RETURNS_ANY:
2359 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2367 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2368 // If the underlying comparison instruction is used by any other instruction,
2369 // the consumed instructions won't be destroyed, so it is not profitable
2370 // to convert to a min/max.
2371 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2373 LHSVal = getValue(LHS);
2374 RHSVal = getValue(RHS);
2379 for (unsigned i = 0; i != NumValues; ++i) {
2380 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2381 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2382 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2383 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2384 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2388 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2389 DAG.getVTList(ValueVTs), Values));
2392 void SelectionDAGBuilder::visitTrunc(const User &I) {
2393 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2394 SDValue N = getValue(I.getOperand(0));
2395 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2397 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2400 void SelectionDAGBuilder::visitZExt(const User &I) {
2401 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2402 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2403 SDValue N = getValue(I.getOperand(0));
2404 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2406 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2409 void SelectionDAGBuilder::visitSExt(const User &I) {
2410 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2411 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2412 SDValue N = getValue(I.getOperand(0));
2413 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2415 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2418 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2419 // FPTrunc is never a no-op cast, no need to check
2420 SDValue N = getValue(I.getOperand(0));
2421 SDLoc dl = getCurSDLoc();
2422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2423 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2424 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2425 DAG.getTargetConstant(
2426 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2429 void SelectionDAGBuilder::visitFPExt(const User &I) {
2430 // FPExt is never a no-op cast, no need to check
2431 SDValue N = getValue(I.getOperand(0));
2432 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2434 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2437 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2438 // FPToUI is never a no-op cast, no need to check
2439 SDValue N = getValue(I.getOperand(0));
2440 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2442 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2445 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2446 // FPToSI is never a no-op cast, no need to check
2447 SDValue N = getValue(I.getOperand(0));
2448 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2450 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2453 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2454 // UIToFP is never a no-op cast, no need to check
2455 SDValue N = getValue(I.getOperand(0));
2456 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2458 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2461 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2462 // SIToFP is never a no-op cast, no need to check
2463 SDValue N = getValue(I.getOperand(0));
2464 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2466 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2469 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2470 // What to do depends on the size of the integer and the size of the pointer.
2471 // We can either truncate, zero extend, or no-op, accordingly.
2472 SDValue N = getValue(I.getOperand(0));
2473 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2475 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2478 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2479 // What to do depends on the size of the integer and the size of the pointer.
2480 // We can either truncate, zero extend, or no-op, accordingly.
2481 SDValue N = getValue(I.getOperand(0));
2482 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2484 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2487 void SelectionDAGBuilder::visitBitCast(const User &I) {
2488 SDValue N = getValue(I.getOperand(0));
2489 SDLoc dl = getCurSDLoc();
2490 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2493 // BitCast assures us that source and destination are the same size so this is
2494 // either a BITCAST or a no-op.
2495 if (DestVT != N.getValueType())
2496 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2497 DestVT, N)); // convert types.
2498 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2499 // might fold any kind of constant expression to an integer constant and that
2500 // is not what we are looking for. Only regcognize a bitcast of a genuine
2501 // constant integer as an opaque constant.
2502 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2503 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2506 setValue(&I, N); // noop cast.
2509 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2511 const Value *SV = I.getOperand(0);
2512 SDValue N = getValue(SV);
2513 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2515 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2516 unsigned DestAS = I.getType()->getPointerAddressSpace();
2518 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2519 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2524 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2526 SDValue InVec = getValue(I.getOperand(0));
2527 SDValue InVal = getValue(I.getOperand(1));
2528 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2529 TLI.getVectorIdxTy(DAG.getDataLayout()));
2530 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2531 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2532 InVec, InVal, InIdx));
2535 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2537 SDValue InVec = getValue(I.getOperand(0));
2538 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2539 TLI.getVectorIdxTy(DAG.getDataLayout()));
2540 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2541 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2545 // Utility for visitShuffleVector - Return true if every element in Mask,
2546 // beginning from position Pos and ending in Pos+Size, falls within the
2547 // specified sequential range [L, L+Pos). or is undef.
2548 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2549 unsigned Pos, unsigned Size, int Low) {
2550 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2551 if (Mask[i] >= 0 && Mask[i] != Low)
2556 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2557 SDValue Src1 = getValue(I.getOperand(0));
2558 SDValue Src2 = getValue(I.getOperand(1));
2560 SmallVector<int, 8> Mask;
2561 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2562 unsigned MaskNumElts = Mask.size();
2564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2565 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2566 EVT SrcVT = Src1.getValueType();
2567 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2569 if (SrcNumElts == MaskNumElts) {
2570 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2575 // Normalize the shuffle vector since mask and vector length don't match.
2576 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2577 // Mask is longer than the source vectors and is a multiple of the source
2578 // vectors. We can use concatenate vector to make the mask and vectors
2580 if (SrcNumElts*2 == MaskNumElts) {
2581 // First check for Src1 in low and Src2 in high
2582 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2583 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2584 // The shuffle is concatenating two vectors together.
2585 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2589 // Then check for Src2 in low and Src1 in high
2590 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2591 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2592 // The shuffle is concatenating two vectors together.
2593 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2599 // Pad both vectors with undefs to make them the same length as the mask.
2600 unsigned NumConcat = MaskNumElts / SrcNumElts;
2601 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2602 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2603 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2605 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2606 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2610 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2611 getCurSDLoc(), VT, MOps1);
2612 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2613 getCurSDLoc(), VT, MOps2);
2615 // Readjust mask for new input vector length.
2616 SmallVector<int, 8> MappedOps;
2617 for (unsigned i = 0; i != MaskNumElts; ++i) {
2619 if (Idx >= (int)SrcNumElts)
2620 Idx -= SrcNumElts - MaskNumElts;
2621 MappedOps.push_back(Idx);
2624 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2629 if (SrcNumElts > MaskNumElts) {
2630 // Analyze the access pattern of the vector to see if we can extract
2631 // two subvectors and do the shuffle. The analysis is done by calculating
2632 // the range of elements the mask access on both vectors.
2633 int MinRange[2] = { static_cast<int>(SrcNumElts),
2634 static_cast<int>(SrcNumElts)};
2635 int MaxRange[2] = {-1, -1};
2637 for (unsigned i = 0; i != MaskNumElts; ++i) {
2643 if (Idx >= (int)SrcNumElts) {
2647 if (Idx > MaxRange[Input])
2648 MaxRange[Input] = Idx;
2649 if (Idx < MinRange[Input])
2650 MinRange[Input] = Idx;
2653 // Check if the access is smaller than the vector size and can we find
2654 // a reasonable extract index.
2655 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2657 int StartIdx[2]; // StartIdx to extract from
2658 for (unsigned Input = 0; Input < 2; ++Input) {
2659 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2660 RangeUse[Input] = 0; // Unused
2661 StartIdx[Input] = 0;
2665 // Find a good start index that is a multiple of the mask length. Then
2666 // see if the rest of the elements are in range.
2667 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2668 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2669 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2670 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2673 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2674 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2677 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2678 // Extract appropriate subvector and generate a vector shuffle
2679 for (unsigned Input = 0; Input < 2; ++Input) {
2680 SDValue &Src = Input == 0 ? Src1 : Src2;
2681 if (RangeUse[Input] == 0)
2682 Src = DAG.getUNDEF(VT);
2684 SDLoc dl = getCurSDLoc();
2686 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2687 DAG.getConstant(StartIdx[Input], dl,
2688 TLI.getVectorIdxTy(DAG.getDataLayout())));
2692 // Calculate new mask.
2693 SmallVector<int, 8> MappedOps;
2694 for (unsigned i = 0; i != MaskNumElts; ++i) {
2697 if (Idx < (int)SrcNumElts)
2700 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2702 MappedOps.push_back(Idx);
2705 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2711 // We can't use either concat vectors or extract subvectors so fall back to
2712 // replacing the shuffle with extract and build vector.
2713 // to insert and build vector.
2714 EVT EltVT = VT.getVectorElementType();
2715 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2716 SDLoc dl = getCurSDLoc();
2717 SmallVector<SDValue,8> Ops;
2718 for (unsigned i = 0; i != MaskNumElts; ++i) {
2723 Res = DAG.getUNDEF(EltVT);
2725 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2726 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2728 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2729 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2735 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2738 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2739 const Value *Op0 = I.getOperand(0);
2740 const Value *Op1 = I.getOperand(1);
2741 Type *AggTy = I.getType();
2742 Type *ValTy = Op1->getType();
2743 bool IntoUndef = isa<UndefValue>(Op0);
2744 bool FromUndef = isa<UndefValue>(Op1);
2746 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2749 SmallVector<EVT, 4> AggValueVTs;
2750 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2751 SmallVector<EVT, 4> ValValueVTs;
2752 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2754 unsigned NumAggValues = AggValueVTs.size();
2755 unsigned NumValValues = ValValueVTs.size();
2756 SmallVector<SDValue, 4> Values(NumAggValues);
2758 // Ignore an insertvalue that produces an empty object
2759 if (!NumAggValues) {
2760 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2764 SDValue Agg = getValue(Op0);
2766 // Copy the beginning value(s) from the original aggregate.
2767 for (; i != LinearIndex; ++i)
2768 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2769 SDValue(Agg.getNode(), Agg.getResNo() + i);
2770 // Copy values from the inserted value(s).
2772 SDValue Val = getValue(Op1);
2773 for (; i != LinearIndex + NumValValues; ++i)
2774 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2775 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2777 // Copy remaining value(s) from the original aggregate.
2778 for (; i != NumAggValues; ++i)
2779 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2780 SDValue(Agg.getNode(), Agg.getResNo() + i);
2782 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2783 DAG.getVTList(AggValueVTs), Values));
2786 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2787 const Value *Op0 = I.getOperand(0);
2788 Type *AggTy = Op0->getType();
2789 Type *ValTy = I.getType();
2790 bool OutOfUndef = isa<UndefValue>(Op0);
2792 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2794 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2795 SmallVector<EVT, 4> ValValueVTs;
2796 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2798 unsigned NumValValues = ValValueVTs.size();
2800 // Ignore a extractvalue that produces an empty object
2801 if (!NumValValues) {
2802 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2806 SmallVector<SDValue, 4> Values(NumValValues);
2808 SDValue Agg = getValue(Op0);
2809 // Copy out the selected value(s).
2810 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2811 Values[i - LinearIndex] =
2813 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2814 SDValue(Agg.getNode(), Agg.getResNo() + i);
2816 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2817 DAG.getVTList(ValValueVTs), Values));
2820 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2821 Value *Op0 = I.getOperand(0);
2822 // Note that the pointer operand may be a vector of pointers. Take the scalar
2823 // element which holds a pointer.
2824 Type *Ty = Op0->getType()->getScalarType();
2825 unsigned AS = Ty->getPointerAddressSpace();
2826 SDValue N = getValue(Op0);
2827 SDLoc dl = getCurSDLoc();
2829 // Normalize Vector GEP - all scalar operands should be converted to the
2831 unsigned VectorWidth = I.getType()->isVectorTy() ?
2832 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2834 if (VectorWidth && !N.getValueType().isVector()) {
2835 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2836 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2837 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2839 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2841 const Value *Idx = *OI;
2842 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2843 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2846 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2847 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2848 DAG.getConstant(Offset, dl, N.getValueType()));
2851 Ty = StTy->getElementType(Field);
2853 Ty = cast<SequentialType>(Ty)->getElementType();
2855 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2856 unsigned PtrSize = PtrTy.getSizeInBits();
2857 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2859 // If this is a scalar constant or a splat vector of constants,
2860 // handle it quickly.
2861 const auto *CI = dyn_cast<ConstantInt>(Idx);
2862 if (!CI && isa<ConstantDataVector>(Idx) &&
2863 cast<ConstantDataVector>(Idx)->getSplatValue())
2864 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2869 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2870 SDValue OffsVal = VectorWidth ?
2871 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2872 DAG.getConstant(Offs, dl, PtrTy);
2873 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2877 // N = N + Idx * ElementSize;
2878 SDValue IdxN = getValue(Idx);
2880 if (!IdxN.getValueType().isVector() && VectorWidth) {
2881 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2882 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2883 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2885 // If the index is smaller or larger than intptr_t, truncate or extend
2887 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2889 // If this is a multiply by a power of two, turn it into a shl
2890 // immediately. This is a very common case.
2891 if (ElementSize != 1) {
2892 if (ElementSize.isPowerOf2()) {
2893 unsigned Amt = ElementSize.logBase2();
2894 IdxN = DAG.getNode(ISD::SHL, dl,
2895 N.getValueType(), IdxN,
2896 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2898 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2899 IdxN = DAG.getNode(ISD::MUL, dl,
2900 N.getValueType(), IdxN, Scale);
2904 N = DAG.getNode(ISD::ADD, dl,
2905 N.getValueType(), N, IdxN);
2912 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2913 // If this is a fixed sized alloca in the entry block of the function,
2914 // allocate it statically on the stack.
2915 if (FuncInfo.StaticAllocaMap.count(&I))
2916 return; // getValue will auto-populate this.
2918 SDLoc dl = getCurSDLoc();
2919 Type *Ty = I.getAllocatedType();
2920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2921 auto &DL = DAG.getDataLayout();
2922 uint64_t TySize = DL.getTypeAllocSize(Ty);
2924 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2926 SDValue AllocSize = getValue(I.getArraySize());
2928 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2929 if (AllocSize.getValueType() != IntPtr)
2930 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2932 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2934 DAG.getConstant(TySize, dl, IntPtr));
2936 // Handle alignment. If the requested alignment is less than or equal to
2937 // the stack alignment, ignore it. If the size is greater than or equal to
2938 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2939 unsigned StackAlign =
2940 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2941 if (Align <= StackAlign)
2944 // Round the size of the allocation up to the stack alignment size
2945 // by add SA-1 to the size.
2946 AllocSize = DAG.getNode(ISD::ADD, dl,
2947 AllocSize.getValueType(), AllocSize,
2948 DAG.getIntPtrConstant(StackAlign - 1, dl));
2950 // Mask out the low bits for alignment purposes.
2951 AllocSize = DAG.getNode(ISD::AND, dl,
2952 AllocSize.getValueType(), AllocSize,
2953 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2956 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2957 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2958 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2960 DAG.setRoot(DSA.getValue(1));
2962 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2965 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2967 return visitAtomicLoad(I);
2969 const Value *SV = I.getOperand(0);
2970 SDValue Ptr = getValue(SV);
2972 Type *Ty = I.getType();
2974 bool isVolatile = I.isVolatile();
2975 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2977 // The IR notion of invariant_load only guarantees that all *non-faulting*
2978 // invariant loads result in the same value. The MI notion of invariant load
2979 // guarantees that the load can be legally moved to any location within its
2980 // containing function. The MI notion of invariant_load is stronger than the
2981 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2982 // with a guarantee that the location being loaded from is dereferenceable
2983 // throughout the function's lifetime.
2985 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2986 isDereferenceablePointer(SV, DAG.getDataLayout());
2987 unsigned Alignment = I.getAlignment();
2990 I.getAAMetadata(AAInfo);
2991 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2994 SmallVector<EVT, 4> ValueVTs;
2995 SmallVector<uint64_t, 4> Offsets;
2996 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2997 unsigned NumValues = ValueVTs.size();
3002 bool ConstantMemory = false;
3003 if (isVolatile || NumValues > MaxParallelChains)
3004 // Serialize volatile loads with other side effects.
3006 else if (AA->pointsToConstantMemory(MemoryLocation(
3007 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3008 // Do not serialize (non-volatile) loads of constant memory with anything.
3009 Root = DAG.getEntryNode();
3010 ConstantMemory = true;
3012 // Do not serialize non-volatile loads against each other.
3013 Root = DAG.getRoot();
3016 SDLoc dl = getCurSDLoc();
3019 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3021 SmallVector<SDValue, 4> Values(NumValues);
3022 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3023 EVT PtrVT = Ptr.getValueType();
3024 unsigned ChainI = 0;
3025 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3026 // Serializing loads here may result in excessive register pressure, and
3027 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3028 // could recover a bit by hoisting nodes upward in the chain by recognizing
3029 // they are side-effect free or do not alias. The optimizer should really
3030 // avoid this case by converting large object/array copies to llvm.memcpy
3031 // (MaxParallelChains should always remain as failsafe).
3032 if (ChainI == MaxParallelChains) {
3033 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3034 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3035 makeArrayRef(Chains.data(), ChainI));
3039 SDValue A = DAG.getNode(ISD::ADD, dl,
3041 DAG.getConstant(Offsets[i], dl, PtrVT));
3042 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3043 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3044 isNonTemporal, isInvariant, Alignment, AAInfo,
3048 Chains[ChainI] = L.getValue(1);
3051 if (!ConstantMemory) {
3052 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3053 makeArrayRef(Chains.data(), ChainI));
3057 PendingLoads.push_back(Chain);
3060 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3061 DAG.getVTList(ValueVTs), Values));
3064 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3066 return visitAtomicStore(I);
3068 const Value *SrcV = I.getOperand(0);
3069 const Value *PtrV = I.getOperand(1);
3071 SmallVector<EVT, 4> ValueVTs;
3072 SmallVector<uint64_t, 4> Offsets;
3073 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3074 SrcV->getType(), ValueVTs, &Offsets);
3075 unsigned NumValues = ValueVTs.size();
3079 // Get the lowered operands. Note that we do this after
3080 // checking if NumResults is zero, because with zero results
3081 // the operands won't have values in the map.
3082 SDValue Src = getValue(SrcV);
3083 SDValue Ptr = getValue(PtrV);
3085 SDValue Root = getRoot();
3086 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3087 EVT PtrVT = Ptr.getValueType();
3088 bool isVolatile = I.isVolatile();
3089 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3090 unsigned Alignment = I.getAlignment();
3091 SDLoc dl = getCurSDLoc();
3094 I.getAAMetadata(AAInfo);
3096 unsigned ChainI = 0;
3097 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3098 // See visitLoad comments.
3099 if (ChainI == MaxParallelChains) {
3100 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3101 makeArrayRef(Chains.data(), ChainI));
3105 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3106 DAG.getConstant(Offsets[i], dl, PtrVT));
3107 SDValue St = DAG.getStore(Root, dl,
3108 SDValue(Src.getNode(), Src.getResNo() + i),
3109 Add, MachinePointerInfo(PtrV, Offsets[i]),
3110 isVolatile, isNonTemporal, Alignment, AAInfo);
3111 Chains[ChainI] = St;
3114 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3115 makeArrayRef(Chains.data(), ChainI));
3116 DAG.setRoot(StoreNode);
3119 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3120 SDLoc sdl = getCurSDLoc();
3122 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3123 Value *PtrOperand = I.getArgOperand(1);
3124 SDValue Ptr = getValue(PtrOperand);
3125 SDValue Src0 = getValue(I.getArgOperand(0));
3126 SDValue Mask = getValue(I.getArgOperand(3));
3127 EVT VT = Src0.getValueType();
3128 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3130 Alignment = DAG.getEVTAlignment(VT);
3133 I.getAAMetadata(AAInfo);
3135 MachineMemOperand *MMO =
3136 DAG.getMachineFunction().
3137 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3138 MachineMemOperand::MOStore, VT.getStoreSize(),
3140 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3142 DAG.setRoot(StoreNode);
3143 setValue(&I, StoreNode);
3146 // Gather/scatter receive a vector of pointers.
3147 // This vector of pointers may be represented as a base pointer + vector of
3148 // indices, it depends on GEP and instruction preceding GEP
3149 // that calculates indices
3150 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3151 SelectionDAGBuilder* SDB) {
3153 assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
3154 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3155 if (!GEP || GEP->getNumOperands() > 2)
3157 Value *GEPPtrs = GEP->getPointerOperand();
3158 if (!(Ptr = getSplatValue(GEPPtrs)))
3161 SelectionDAG& DAG = SDB->DAG;
3162 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3163 // Check is the Ptr is inside current basic block
3164 // If not, look for the shuffle instruction
3165 if (SDB->findValue(Ptr))
3166 Base = SDB->getValue(Ptr);
3167 else if (SDB->findValue(GEPPtrs)) {
3168 SDValue GEPPtrsVal = SDB->getValue(GEPPtrs);
3169 SDLoc sdl = GEPPtrsVal;
3170 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3171 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3172 GEPPtrsVal.getValueType().getScalarType(), GEPPtrsVal,
3173 DAG.getConstant(0, sdl, IdxVT));
3174 SDB->setValue(Ptr, Base);
3179 Value *IndexVal = GEP->getOperand(1);
3180 if (SDB->findValue(IndexVal)) {
3181 Index = SDB->getValue(IndexVal);
3183 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3184 IndexVal = Sext->getOperand(0);
3185 if (SDB->findValue(IndexVal))
3186 Index = SDB->getValue(IndexVal);
3193 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3194 SDLoc sdl = getCurSDLoc();
3196 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3197 Value *Ptr = I.getArgOperand(1);
3198 SDValue Src0 = getValue(I.getArgOperand(0));
3199 SDValue Mask = getValue(I.getArgOperand(3));
3200 EVT VT = Src0.getValueType();
3201 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3203 Alignment = DAG.getEVTAlignment(VT);
3204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3207 I.getAAMetadata(AAInfo);
3211 Value *BasePtr = Ptr;
3212 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3214 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3215 MachineMemOperand *MMO = DAG.getMachineFunction().
3216 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3217 MachineMemOperand::MOStore, VT.getStoreSize(),
3220 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3221 Index = getValue(Ptr);
3223 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3224 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3226 DAG.setRoot(Scatter);
3227 setValue(&I, Scatter);
3230 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3231 SDLoc sdl = getCurSDLoc();
3233 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3234 Value *PtrOperand = I.getArgOperand(0);
3235 SDValue Ptr = getValue(PtrOperand);
3236 SDValue Src0 = getValue(I.getArgOperand(3));
3237 SDValue Mask = getValue(I.getArgOperand(2));
3239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3240 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3241 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3243 Alignment = DAG.getEVTAlignment(VT);
3246 I.getAAMetadata(AAInfo);
3247 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3249 SDValue InChain = DAG.getRoot();
3250 if (AA->pointsToConstantMemory(MemoryLocation(
3251 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3253 // Do not serialize (non-volatile) loads of constant memory with anything.
3254 InChain = DAG.getEntryNode();
3257 MachineMemOperand *MMO =
3258 DAG.getMachineFunction().
3259 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3260 MachineMemOperand::MOLoad, VT.getStoreSize(),
3261 Alignment, AAInfo, Ranges);
3263 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3265 SDValue OutChain = Load.getValue(1);
3266 DAG.setRoot(OutChain);
3270 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3271 SDLoc sdl = getCurSDLoc();
3273 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3274 Value *Ptr = I.getArgOperand(0);
3275 SDValue Src0 = getValue(I.getArgOperand(3));
3276 SDValue Mask = getValue(I.getArgOperand(2));
3278 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3279 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3280 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3282 Alignment = DAG.getEVTAlignment(VT);
3285 I.getAAMetadata(AAInfo);
3286 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3288 SDValue Root = DAG.getRoot();
3291 Value *BasePtr = Ptr;
3292 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3293 bool ConstantMemory = false;
3295 AA->pointsToConstantMemory(MemoryLocation(
3296 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3298 // Do not serialize (non-volatile) loads of constant memory with anything.
3299 Root = DAG.getEntryNode();
3300 ConstantMemory = true;
3303 MachineMemOperand *MMO =
3304 DAG.getMachineFunction().
3305 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3306 MachineMemOperand::MOLoad, VT.getStoreSize(),
3307 Alignment, AAInfo, Ranges);
3310 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3311 Index = getValue(Ptr);
3313 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3314 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3317 SDValue OutChain = Gather.getValue(1);
3318 if (!ConstantMemory)
3319 PendingLoads.push_back(OutChain);
3320 setValue(&I, Gather);
3323 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3324 SDLoc dl = getCurSDLoc();
3325 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3326 AtomicOrdering FailureOrder = I.getFailureOrdering();
3327 SynchronizationScope Scope = I.getSynchScope();
3329 SDValue InChain = getRoot();
3331 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3332 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3333 SDValue L = DAG.getAtomicCmpSwap(
3334 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3335 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3336 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3337 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3339 SDValue OutChain = L.getValue(2);
3342 DAG.setRoot(OutChain);
3345 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3346 SDLoc dl = getCurSDLoc();
3348 switch (I.getOperation()) {
3349 default: llvm_unreachable("Unknown atomicrmw operation");
3350 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3351 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3352 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3353 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3354 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3355 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3356 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3357 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3358 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3359 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3360 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3362 AtomicOrdering Order = I.getOrdering();
3363 SynchronizationScope Scope = I.getSynchScope();
3365 SDValue InChain = getRoot();
3368 DAG.getAtomic(NT, dl,
3369 getValue(I.getValOperand()).getSimpleValueType(),
3371 getValue(I.getPointerOperand()),
3372 getValue(I.getValOperand()),
3373 I.getPointerOperand(),
3374 /* Alignment=*/ 0, Order, Scope);
3376 SDValue OutChain = L.getValue(1);
3379 DAG.setRoot(OutChain);
3382 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3383 SDLoc dl = getCurSDLoc();
3384 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3387 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3388 TLI.getPointerTy(DAG.getDataLayout()));
3389 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3390 TLI.getPointerTy(DAG.getDataLayout()));
3391 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3394 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3395 SDLoc dl = getCurSDLoc();
3396 AtomicOrdering Order = I.getOrdering();
3397 SynchronizationScope Scope = I.getSynchScope();
3399 SDValue InChain = getRoot();
3401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3402 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3404 if (I.getAlignment() < VT.getSizeInBits() / 8)
3405 report_fatal_error("Cannot generate unaligned atomic load");
3407 MachineMemOperand *MMO =
3408 DAG.getMachineFunction().
3409 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3410 MachineMemOperand::MOVolatile |
3411 MachineMemOperand::MOLoad,
3413 I.getAlignment() ? I.getAlignment() :
3414 DAG.getEVTAlignment(VT));
3416 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3418 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3419 getValue(I.getPointerOperand()), MMO,
3422 SDValue OutChain = L.getValue(1);
3425 DAG.setRoot(OutChain);
3428 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3429 SDLoc dl = getCurSDLoc();
3431 AtomicOrdering Order = I.getOrdering();
3432 SynchronizationScope Scope = I.getSynchScope();
3434 SDValue InChain = getRoot();
3436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3438 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3440 if (I.getAlignment() < VT.getSizeInBits() / 8)
3441 report_fatal_error("Cannot generate unaligned atomic store");
3444 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3446 getValue(I.getPointerOperand()),
3447 getValue(I.getValueOperand()),
3448 I.getPointerOperand(), I.getAlignment(),
3451 DAG.setRoot(OutChain);
3454 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3456 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3457 unsigned Intrinsic) {
3458 bool HasChain = !I.doesNotAccessMemory();
3459 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3461 // Build the operand list.
3462 SmallVector<SDValue, 8> Ops;
3463 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3465 // We don't need to serialize loads against other loads.
3466 Ops.push_back(DAG.getRoot());
3468 Ops.push_back(getRoot());
3472 // Info is set by getTgtMemInstrinsic
3473 TargetLowering::IntrinsicInfo Info;
3474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3475 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3477 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3478 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3479 Info.opc == ISD::INTRINSIC_W_CHAIN)
3480 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3481 TLI.getPointerTy(DAG.getDataLayout())));
3483 // Add all operands of the call to the operand list.
3484 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3485 SDValue Op = getValue(I.getArgOperand(i));
3489 SmallVector<EVT, 4> ValueVTs;
3490 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3493 ValueVTs.push_back(MVT::Other);
3495 SDVTList VTs = DAG.getVTList(ValueVTs);
3499 if (IsTgtIntrinsic) {
3500 // This is target intrinsic that touches memory
3501 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3502 VTs, Ops, Info.memVT,
3503 MachinePointerInfo(Info.ptrVal, Info.offset),
3504 Info.align, Info.vol,
3505 Info.readMem, Info.writeMem, Info.size);
3506 } else if (!HasChain) {
3507 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3508 } else if (!I.getType()->isVoidTy()) {
3509 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3511 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3515 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3517 PendingLoads.push_back(Chain);
3522 if (!I.getType()->isVoidTy()) {
3523 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3524 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3525 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3528 setValue(&I, Result);
3532 /// GetSignificand - Get the significand and build it into a floating-point
3533 /// number with exponent of 1:
3535 /// Op = (Op & 0x007fffff) | 0x3f800000;
3537 /// where Op is the hexadecimal representation of floating point value.
3539 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3540 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3541 DAG.getConstant(0x007fffff, dl, MVT::i32));
3542 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3543 DAG.getConstant(0x3f800000, dl, MVT::i32));
3544 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3547 /// GetExponent - Get the exponent:
3549 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3551 /// where Op is the hexadecimal representation of floating point value.
3553 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3555 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3556 DAG.getConstant(0x7f800000, dl, MVT::i32));
3557 SDValue t1 = DAG.getNode(
3558 ISD::SRL, dl, MVT::i32, t0,
3559 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3560 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3561 DAG.getConstant(127, dl, MVT::i32));
3562 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3565 /// getF32Constant - Get 32-bit floating point constant.
3567 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3568 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3572 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3573 SelectionDAG &DAG) {
3574 // IntegerPartOfX = ((int32_t)(t0);
3575 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3577 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3578 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3579 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3581 // IntegerPartOfX <<= 23;
3582 IntegerPartOfX = DAG.getNode(
3583 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3584 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3585 DAG.getDataLayout())));
3587 SDValue TwoToFractionalPartOfX;
3588 if (LimitFloatPrecision <= 6) {
3589 // For floating-point precision of 6:
3591 // TwoToFractionalPartOfX =
3593 // (0.735607626f + 0.252464424f * x) * x;
3595 // error 0.0144103317, which is 6 bits
3596 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3597 getF32Constant(DAG, 0x3e814304, dl));
3598 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3599 getF32Constant(DAG, 0x3f3c50c8, dl));
3600 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3601 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3602 getF32Constant(DAG, 0x3f7f5e7e, dl));
3603 } else if (LimitFloatPrecision <= 12) {
3604 // For floating-point precision of 12:
3606 // TwoToFractionalPartOfX =
3609 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3611 // error 0.000107046256, which is 13 to 14 bits
3612 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3613 getF32Constant(DAG, 0x3da235e3, dl));
3614 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3615 getF32Constant(DAG, 0x3e65b8f3, dl));
3616 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3617 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3618 getF32Constant(DAG, 0x3f324b07, dl));
3619 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3620 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3621 getF32Constant(DAG, 0x3f7ff8fd, dl));
3622 } else { // LimitFloatPrecision <= 18
3623 // For floating-point precision of 18:
3625 // TwoToFractionalPartOfX =
3629 // (0.554906021e-1f +
3630 // (0.961591928e-2f +
3631 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3632 // error 2.47208000*10^(-7), which is better than 18 bits
3633 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3634 getF32Constant(DAG, 0x3924b03e, dl));
3635 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3636 getF32Constant(DAG, 0x3ab24b87, dl));
3637 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3638 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3639 getF32Constant(DAG, 0x3c1d8c17, dl));
3640 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3641 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3642 getF32Constant(DAG, 0x3d634a1d, dl));
3643 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3644 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3645 getF32Constant(DAG, 0x3e75fe14, dl));
3646 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3647 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3648 getF32Constant(DAG, 0x3f317234, dl));
3649 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3650 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3651 getF32Constant(DAG, 0x3f800000, dl));
3654 // Add the exponent into the result in integer domain.
3655 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3656 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3657 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3660 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3661 /// limited-precision mode.
3662 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3663 const TargetLowering &TLI) {
3664 if (Op.getValueType() == MVT::f32 &&
3665 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3667 // Put the exponent in the right bit position for later addition to the
3670 // #define LOG2OFe 1.4426950f
3671 // t0 = Op * LOG2OFe
3672 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3673 getF32Constant(DAG, 0x3fb8aa3b, dl));
3674 return getLimitedPrecisionExp2(t0, dl, DAG);
3677 // No special expansion.
3678 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3681 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3682 /// limited-precision mode.
3683 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3684 const TargetLowering &TLI) {
3685 if (Op.getValueType() == MVT::f32 &&
3686 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3687 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3689 // Scale the exponent by log(2) [0.69314718f].
3690 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3691 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3692 getF32Constant(DAG, 0x3f317218, dl));
3694 // Get the significand and build it into a floating-point number with
3696 SDValue X = GetSignificand(DAG, Op1, dl);
3698 SDValue LogOfMantissa;
3699 if (LimitFloatPrecision <= 6) {
3700 // For floating-point precision of 6:
3704 // (1.4034025f - 0.23903021f * x) * x;
3706 // error 0.0034276066, which is better than 8 bits
3707 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3708 getF32Constant(DAG, 0xbe74c456, dl));
3709 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3710 getF32Constant(DAG, 0x3fb3a2b1, dl));
3711 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3712 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3713 getF32Constant(DAG, 0x3f949a29, dl));
3714 } else if (LimitFloatPrecision <= 12) {
3715 // For floating-point precision of 12:
3721 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3723 // error 0.000061011436, which is 14 bits
3724 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3725 getF32Constant(DAG, 0xbd67b6d6, dl));
3726 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3727 getF32Constant(DAG, 0x3ee4f4b8, dl));
3728 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3729 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3730 getF32Constant(DAG, 0x3fbc278b, dl));
3731 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3732 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3733 getF32Constant(DAG, 0x40348e95, dl));
3734 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3735 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3736 getF32Constant(DAG, 0x3fdef31a, dl));
3737 } else { // LimitFloatPrecision <= 18
3738 // For floating-point precision of 18:
3746 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3748 // error 0.0000023660568, which is better than 18 bits
3749 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3750 getF32Constant(DAG, 0xbc91e5ac, dl));
3751 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3752 getF32Constant(DAG, 0x3e4350aa, dl));
3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3754 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3f60d3e3, dl));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x4011cdf0, dl));
3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3760 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3761 getF32Constant(DAG, 0x406cfd1c, dl));
3762 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3763 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3764 getF32Constant(DAG, 0x408797cb, dl));
3765 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3766 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3767 getF32Constant(DAG, 0x4006dcab, dl));
3770 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3773 // No special expansion.
3774 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3777 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3778 /// limited-precision mode.
3779 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3780 const TargetLowering &TLI) {
3781 if (Op.getValueType() == MVT::f32 &&
3782 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3783 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3785 // Get the exponent.
3786 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3788 // Get the significand and build it into a floating-point number with
3790 SDValue X = GetSignificand(DAG, Op1, dl);
3792 // Different possible minimax approximations of significand in
3793 // floating-point for various degrees of accuracy over [1,2].
3794 SDValue Log2ofMantissa;
3795 if (LimitFloatPrecision <= 6) {
3796 // For floating-point precision of 6:
3798 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3800 // error 0.0049451742, which is more than 7 bits
3801 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3802 getF32Constant(DAG, 0xbeb08fe0, dl));
3803 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3804 getF32Constant(DAG, 0x40019463, dl));
3805 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3806 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3807 getF32Constant(DAG, 0x3fd6633d, dl));
3808 } else if (LimitFloatPrecision <= 12) {
3809 // For floating-point precision of 12:
3815 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3817 // error 0.0000876136000, which is better than 13 bits
3818 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3819 getF32Constant(DAG, 0xbda7262e, dl));
3820 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3821 getF32Constant(DAG, 0x3f25280b, dl));
3822 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3823 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3824 getF32Constant(DAG, 0x4007b923, dl));
3825 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3826 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3827 getF32Constant(DAG, 0x40823e2f, dl));
3828 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3829 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3830 getF32Constant(DAG, 0x4020d29c, dl));
3831 } else { // LimitFloatPrecision <= 18
3832 // For floating-point precision of 18:
3841 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3843 // error 0.0000018516, which is better than 18 bits
3844 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3845 getF32Constant(DAG, 0xbcd2769e, dl));
3846 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3847 getF32Constant(DAG, 0x3e8ce0b9, dl));
3848 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3849 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3850 getF32Constant(DAG, 0x3fa22ae7, dl));
3851 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3852 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3853 getF32Constant(DAG, 0x40525723, dl));
3854 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3855 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3856 getF32Constant(DAG, 0x40aaf200, dl));
3857 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3858 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3859 getF32Constant(DAG, 0x40c39dad, dl));
3860 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3861 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3862 getF32Constant(DAG, 0x4042902c, dl));
3865 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3868 // No special expansion.
3869 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3872 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3873 /// limited-precision mode.
3874 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3875 const TargetLowering &TLI) {
3876 if (Op.getValueType() == MVT::f32 &&
3877 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3878 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3880 // Scale the exponent by log10(2) [0.30102999f].
3881 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3882 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3883 getF32Constant(DAG, 0x3e9a209a, dl));
3885 // Get the significand and build it into a floating-point number with
3887 SDValue X = GetSignificand(DAG, Op1, dl);
3889 SDValue Log10ofMantissa;
3890 if (LimitFloatPrecision <= 6) {
3891 // For floating-point precision of 6:
3893 // Log10ofMantissa =
3895 // (0.60948995f - 0.10380950f * x) * x;
3897 // error 0.0014886165, which is 6 bits
3898 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3899 getF32Constant(DAG, 0xbdd49a13, dl));
3900 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3901 getF32Constant(DAG, 0x3f1c0789, dl));
3902 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3903 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3904 getF32Constant(DAG, 0x3f011300, dl));
3905 } else if (LimitFloatPrecision <= 12) {
3906 // For floating-point precision of 12:
3908 // Log10ofMantissa =
3911 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3913 // error 0.00019228036, which is better than 12 bits
3914 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3915 getF32Constant(DAG, 0x3d431f31, dl));
3916 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3917 getF32Constant(DAG, 0x3ea21fb2, dl));
3918 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3919 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3920 getF32Constant(DAG, 0x3f6ae232, dl));
3921 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3922 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3923 getF32Constant(DAG, 0x3f25f7c3, dl));
3924 } else { // LimitFloatPrecision <= 18
3925 // For floating-point precision of 18:
3927 // Log10ofMantissa =
3932 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3934 // error 0.0000037995730, which is better than 18 bits
3935 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3936 getF32Constant(DAG, 0x3c5d51ce, dl));
3937 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3938 getF32Constant(DAG, 0x3e00685a, dl));
3939 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3940 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3941 getF32Constant(DAG, 0x3efb6798, dl));
3942 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3943 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3944 getF32Constant(DAG, 0x3f88d192, dl));
3945 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3946 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3947 getF32Constant(DAG, 0x3fc4316c, dl));
3948 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3949 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3950 getF32Constant(DAG, 0x3f57ce70, dl));
3953 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3956 // No special expansion.
3957 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3960 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3961 /// limited-precision mode.
3962 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3963 const TargetLowering &TLI) {
3964 if (Op.getValueType() == MVT::f32 &&
3965 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3966 return getLimitedPrecisionExp2(Op, dl, DAG);
3968 // No special expansion.
3969 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3972 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3973 /// limited-precision mode with x == 10.0f.
3974 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3975 SelectionDAG &DAG, const TargetLowering &TLI) {
3976 bool IsExp10 = false;
3977 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3978 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3979 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3981 IsExp10 = LHSC->isExactlyValue(Ten);
3986 // Put the exponent in the right bit position for later addition to the
3989 // #define LOG2OF10 3.3219281f
3990 // t0 = Op * LOG2OF10;
3991 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3992 getF32Constant(DAG, 0x40549a78, dl));
3993 return getLimitedPrecisionExp2(t0, dl, DAG);
3996 // No special expansion.
3997 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4001 /// ExpandPowI - Expand a llvm.powi intrinsic.
4002 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4003 SelectionDAG &DAG) {
4004 // If RHS is a constant, we can expand this out to a multiplication tree,
4005 // otherwise we end up lowering to a call to __powidf2 (for example). When
4006 // optimizing for size, we only want to do this if the expansion would produce
4007 // a small number of multiplies, otherwise we do the full expansion.
4008 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4009 // Get the exponent as a positive value.
4010 unsigned Val = RHSC->getSExtValue();
4011 if ((int)Val < 0) Val = -Val;
4013 // powi(x, 0) -> 1.0
4015 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4017 const Function *F = DAG.getMachineFunction().getFunction();
4018 if (!F->optForSize() ||
4019 // If optimizing for size, don't insert too many multiplies.
4020 // This inserts up to 5 multiplies.
4021 countPopulation(Val) + Log2_32(Val) < 7) {
4022 // We use the simple binary decomposition method to generate the multiply
4023 // sequence. There are more optimal ways to do this (for example,
4024 // powi(x,15) generates one more multiply than it should), but this has
4025 // the benefit of being both really simple and much better than a libcall.
4026 SDValue Res; // Logically starts equal to 1.0
4027 SDValue CurSquare = LHS;
4031 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4033 Res = CurSquare; // 1.0*CurSquare.
4036 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4037 CurSquare, CurSquare);
4041 // If the original was negative, invert the result, producing 1/(x*x*x).
4042 if (RHSC->getSExtValue() < 0)
4043 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4044 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4049 // Otherwise, expand to a libcall.
4050 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4053 // getTruncatedArgReg - Find underlying register used for an truncated
4055 static unsigned getTruncatedArgReg(const SDValue &N) {
4056 if (N.getOpcode() != ISD::TRUNCATE)
4059 const SDValue &Ext = N.getOperand(0);
4060 if (Ext.getOpcode() == ISD::AssertZext ||
4061 Ext.getOpcode() == ISD::AssertSext) {
4062 const SDValue &CFR = Ext.getOperand(0);
4063 if (CFR.getOpcode() == ISD::CopyFromReg)
4064 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4065 if (CFR.getOpcode() == ISD::TRUNCATE)
4066 return getTruncatedArgReg(CFR);
4071 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4072 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4073 /// At the end of instruction selection, they will be inserted to the entry BB.
4074 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4075 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4076 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4077 const Argument *Arg = dyn_cast<Argument>(V);
4081 MachineFunction &MF = DAG.getMachineFunction();
4082 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4084 // Ignore inlined function arguments here.
4086 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4087 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4090 Optional<MachineOperand> Op;
4091 // Some arguments' frame index is recorded during argument lowering.
4092 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4093 Op = MachineOperand::CreateFI(FI);
4095 if (!Op && N.getNode()) {
4097 if (N.getOpcode() == ISD::CopyFromReg)
4098 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4100 Reg = getTruncatedArgReg(N);
4101 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4102 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4103 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4108 Op = MachineOperand::CreateReg(Reg, false);
4112 // Check if ValueMap has reg number.
4113 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4114 if (VMI != FuncInfo.ValueMap.end())
4115 Op = MachineOperand::CreateReg(VMI->second, false);
4118 if (!Op && N.getNode())
4119 // Check if frame index is available.
4120 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4121 if (FrameIndexSDNode *FINode =
4122 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4123 Op = MachineOperand::CreateFI(FINode->getIndex());
4128 assert(Variable->isValidLocationForIntrinsic(DL) &&
4129 "Expected inlined-at fields to agree");
4131 FuncInfo.ArgDbgValues.push_back(
4132 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4133 Op->getReg(), Offset, Variable, Expr));
4135 FuncInfo.ArgDbgValues.push_back(
4136 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4139 .addMetadata(Variable)
4140 .addMetadata(Expr));
4145 // VisualStudio defines setjmp as _setjmp
4146 #if defined(_MSC_VER) && defined(setjmp) && \
4147 !defined(setjmp_undefined_for_msvc)
4148 # pragma push_macro("setjmp")
4150 # define setjmp_undefined_for_msvc
4153 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4154 /// we want to emit this as a call to a named external function, return the name
4155 /// otherwise lower it and return null.
4157 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4158 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4159 SDLoc sdl = getCurSDLoc();
4160 DebugLoc dl = getCurDebugLoc();
4163 switch (Intrinsic) {
4165 // By default, turn this into a target intrinsic node.
4166 visitTargetIntrinsic(I, Intrinsic);
4168 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4169 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4170 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4171 case Intrinsic::returnaddress:
4172 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4173 TLI.getPointerTy(DAG.getDataLayout()),
4174 getValue(I.getArgOperand(0))));
4176 case Intrinsic::frameaddress:
4177 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4178 TLI.getPointerTy(DAG.getDataLayout()),
4179 getValue(I.getArgOperand(0))));
4181 case Intrinsic::read_register: {
4182 Value *Reg = I.getArgOperand(0);
4183 SDValue Chain = getRoot();
4185 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4186 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4187 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4188 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4190 DAG.setRoot(Res.getValue(1));
4193 case Intrinsic::write_register: {
4194 Value *Reg = I.getArgOperand(0);
4195 Value *RegValue = I.getArgOperand(1);
4196 SDValue Chain = getRoot();
4198 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4199 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4200 RegName, getValue(RegValue)));
4203 case Intrinsic::setjmp:
4204 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4205 case Intrinsic::longjmp:
4206 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4207 case Intrinsic::memcpy: {
4208 // FIXME: this definition of "user defined address space" is x86-specific
4209 // Assert for address < 256 since we support only user defined address
4211 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4213 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4215 "Unknown address space");
4216 SDValue Op1 = getValue(I.getArgOperand(0));
4217 SDValue Op2 = getValue(I.getArgOperand(1));
4218 SDValue Op3 = getValue(I.getArgOperand(2));
4219 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4221 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4222 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4223 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4224 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4226 MachinePointerInfo(I.getArgOperand(0)),
4227 MachinePointerInfo(I.getArgOperand(1)));
4228 updateDAGForMaybeTailCall(MC);
4231 case Intrinsic::memset: {
4232 // FIXME: this definition of "user defined address space" is x86-specific
4233 // Assert for address < 256 since we support only user defined address
4235 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4237 "Unknown address space");
4238 SDValue Op1 = getValue(I.getArgOperand(0));
4239 SDValue Op2 = getValue(I.getArgOperand(1));
4240 SDValue Op3 = getValue(I.getArgOperand(2));
4241 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4243 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4244 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4245 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4246 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4247 isTC, MachinePointerInfo(I.getArgOperand(0)));
4248 updateDAGForMaybeTailCall(MS);
4251 case Intrinsic::memmove: {
4252 // FIXME: this definition of "user defined address space" is x86-specific
4253 // Assert for address < 256 since we support only user defined address
4255 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4257 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4259 "Unknown address space");
4260 SDValue Op1 = getValue(I.getArgOperand(0));
4261 SDValue Op2 = getValue(I.getArgOperand(1));
4262 SDValue Op3 = getValue(I.getArgOperand(2));
4263 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4265 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4266 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4267 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4268 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4269 isTC, MachinePointerInfo(I.getArgOperand(0)),
4270 MachinePointerInfo(I.getArgOperand(1)));
4271 updateDAGForMaybeTailCall(MM);
4274 case Intrinsic::dbg_declare: {
4275 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4276 DILocalVariable *Variable = DI.getVariable();
4277 DIExpression *Expression = DI.getExpression();
4278 const Value *Address = DI.getAddress();
4279 assert(Variable && "Missing variable");
4281 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4285 // Check if address has undef value.
4286 if (isa<UndefValue>(Address) ||
4287 (Address->use_empty() && !isa<Argument>(Address))) {
4288 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4292 SDValue &N = NodeMap[Address];
4293 if (!N.getNode() && isa<Argument>(Address))
4294 // Check unused arguments map.
4295 N = UnusedArgNodeMap[Address];
4298 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4299 Address = BCI->getOperand(0);
4300 // Parameters are handled specially.
4301 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4303 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4305 if (isParameter && !AI) {
4306 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4308 // Byval parameter. We have a frame index at this point.
4309 SDV = DAG.getFrameIndexDbgValue(
4310 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4312 // Address is an argument, so try to emit its dbg value using
4313 // virtual register info from the FuncInfo.ValueMap.
4314 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4319 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4320 true, 0, dl, SDNodeOrder);
4322 // Can't do anything with other non-AI cases yet.
4323 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4324 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4325 DEBUG(Address->dump());
4328 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4330 // If Address is an argument then try to emit its dbg value using
4331 // virtual register info from the FuncInfo.ValueMap.
4332 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4334 // If variable is pinned by a alloca in dominating bb then
4335 // use StaticAllocaMap.
4336 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4337 if (AI->getParent() != DI.getParent()) {
4338 DenseMap<const AllocaInst*, int>::iterator SI =
4339 FuncInfo.StaticAllocaMap.find(AI);
4340 if (SI != FuncInfo.StaticAllocaMap.end()) {
4341 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4342 0, dl, SDNodeOrder);
4343 DAG.AddDbgValue(SDV, nullptr, false);
4348 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4353 case Intrinsic::dbg_value: {
4354 const DbgValueInst &DI = cast<DbgValueInst>(I);
4355 assert(DI.getVariable() && "Missing variable");
4357 DILocalVariable *Variable = DI.getVariable();
4358 DIExpression *Expression = DI.getExpression();
4359 uint64_t Offset = DI.getOffset();
4360 const Value *V = DI.getValue();
4365 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4366 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4368 DAG.AddDbgValue(SDV, nullptr, false);
4370 // Do not use getValue() in here; we don't want to generate code at
4371 // this point if it hasn't been done yet.
4372 SDValue N = NodeMap[V];
4373 if (!N.getNode() && isa<Argument>(V))
4374 // Check unused arguments map.
4375 N = UnusedArgNodeMap[V];
4377 // A dbg.value for an alloca is always indirect.
4378 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4379 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4381 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4382 IsIndirect, Offset, dl, SDNodeOrder);
4383 DAG.AddDbgValue(SDV, N.getNode(), false);
4385 } else if (!V->use_empty() ) {
4386 // Do not call getValue(V) yet, as we don't want to generate code.
4387 // Remember it for later.
4388 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4389 DanglingDebugInfoMap[V] = DDI;
4391 // We may expand this to cover more cases. One case where we have no
4392 // data available is an unreferenced parameter.
4393 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4397 // Build a debug info table entry.
4398 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4399 V = BCI->getOperand(0);
4400 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4401 // Don't handle byval struct arguments or VLAs, for example.
4403 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4404 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4407 DenseMap<const AllocaInst*, int>::iterator SI =
4408 FuncInfo.StaticAllocaMap.find(AI);
4409 if (SI == FuncInfo.StaticAllocaMap.end())
4410 return nullptr; // VLAs.
4414 case Intrinsic::eh_typeid_for: {
4415 // Find the type id for the given typeinfo.
4416 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4417 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4418 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4423 case Intrinsic::eh_return_i32:
4424 case Intrinsic::eh_return_i64:
4425 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4426 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4429 getValue(I.getArgOperand(0)),
4430 getValue(I.getArgOperand(1))));
4432 case Intrinsic::eh_unwind_init:
4433 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4435 case Intrinsic::eh_dwarf_cfa: {
4436 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4437 TLI.getPointerTy(DAG.getDataLayout()));
4438 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4439 CfaArg.getValueType(),
4440 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4441 CfaArg.getValueType()),
4443 SDValue FA = DAG.getNode(
4444 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4445 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4446 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4450 case Intrinsic::eh_sjlj_callsite: {
4451 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4452 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4453 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4454 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4456 MMI.setCurrentCallSite(CI->getZExtValue());
4459 case Intrinsic::eh_sjlj_functioncontext: {
4460 // Get and store the index of the function context.
4461 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4463 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4464 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4465 MFI->setFunctionContextIndex(FI);
4468 case Intrinsic::eh_sjlj_setjmp: {
4471 Ops[1] = getValue(I.getArgOperand(0));
4472 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4473 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4474 setValue(&I, Op.getValue(0));
4475 DAG.setRoot(Op.getValue(1));
4478 case Intrinsic::eh_sjlj_longjmp: {
4479 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4480 getRoot(), getValue(I.getArgOperand(0))));
4483 case Intrinsic::eh_sjlj_setup_dispatch: {
4484 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4489 case Intrinsic::masked_gather:
4490 visitMaskedGather(I);
4492 case Intrinsic::masked_load:
4495 case Intrinsic::masked_scatter:
4496 visitMaskedScatter(I);
4498 case Intrinsic::masked_store:
4499 visitMaskedStore(I);
4501 case Intrinsic::x86_mmx_pslli_w:
4502 case Intrinsic::x86_mmx_pslli_d:
4503 case Intrinsic::x86_mmx_pslli_q:
4504 case Intrinsic::x86_mmx_psrli_w:
4505 case Intrinsic::x86_mmx_psrli_d:
4506 case Intrinsic::x86_mmx_psrli_q:
4507 case Intrinsic::x86_mmx_psrai_w:
4508 case Intrinsic::x86_mmx_psrai_d: {
4509 SDValue ShAmt = getValue(I.getArgOperand(1));
4510 if (isa<ConstantSDNode>(ShAmt)) {
4511 visitTargetIntrinsic(I, Intrinsic);
4514 unsigned NewIntrinsic = 0;
4515 EVT ShAmtVT = MVT::v2i32;
4516 switch (Intrinsic) {
4517 case Intrinsic::x86_mmx_pslli_w:
4518 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4520 case Intrinsic::x86_mmx_pslli_d:
4521 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4523 case Intrinsic::x86_mmx_pslli_q:
4524 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4526 case Intrinsic::x86_mmx_psrli_w:
4527 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4529 case Intrinsic::x86_mmx_psrli_d:
4530 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4532 case Intrinsic::x86_mmx_psrli_q:
4533 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4535 case Intrinsic::x86_mmx_psrai_w:
4536 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4538 case Intrinsic::x86_mmx_psrai_d:
4539 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4541 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4544 // The vector shift intrinsics with scalars uses 32b shift amounts but
4545 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4547 // We must do this early because v2i32 is not a legal type.
4550 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4551 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4552 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4553 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4554 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4555 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4556 getValue(I.getArgOperand(0)), ShAmt);
4560 case Intrinsic::convertff:
4561 case Intrinsic::convertfsi:
4562 case Intrinsic::convertfui:
4563 case Intrinsic::convertsif:
4564 case Intrinsic::convertuif:
4565 case Intrinsic::convertss:
4566 case Intrinsic::convertsu:
4567 case Intrinsic::convertus:
4568 case Intrinsic::convertuu: {
4569 ISD::CvtCode Code = ISD::CVT_INVALID;
4570 switch (Intrinsic) {
4571 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4572 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4573 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4574 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4575 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4576 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4577 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4578 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4579 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4580 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4582 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4583 const Value *Op1 = I.getArgOperand(0);
4584 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4585 DAG.getValueType(DestVT),
4586 DAG.getValueType(getValue(Op1).getValueType()),
4587 getValue(I.getArgOperand(1)),
4588 getValue(I.getArgOperand(2)),
4593 case Intrinsic::powi:
4594 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4595 getValue(I.getArgOperand(1)), DAG));
4597 case Intrinsic::log:
4598 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4600 case Intrinsic::log2:
4601 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4603 case Intrinsic::log10:
4604 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4606 case Intrinsic::exp:
4607 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4609 case Intrinsic::exp2:
4610 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4612 case Intrinsic::pow:
4613 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4614 getValue(I.getArgOperand(1)), DAG, TLI));
4616 case Intrinsic::sqrt:
4617 case Intrinsic::fabs:
4618 case Intrinsic::sin:
4619 case Intrinsic::cos:
4620 case Intrinsic::floor:
4621 case Intrinsic::ceil:
4622 case Intrinsic::trunc:
4623 case Intrinsic::rint:
4624 case Intrinsic::nearbyint:
4625 case Intrinsic::round: {
4627 switch (Intrinsic) {
4628 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4629 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4630 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4631 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4632 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4633 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4634 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4635 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4636 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4637 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4638 case Intrinsic::round: Opcode = ISD::FROUND; break;
4641 setValue(&I, DAG.getNode(Opcode, sdl,
4642 getValue(I.getArgOperand(0)).getValueType(),
4643 getValue(I.getArgOperand(0))));
4646 case Intrinsic::minnum:
4647 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4648 getValue(I.getArgOperand(0)).getValueType(),
4649 getValue(I.getArgOperand(0)),
4650 getValue(I.getArgOperand(1))));
4652 case Intrinsic::maxnum:
4653 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4654 getValue(I.getArgOperand(0)).getValueType(),
4655 getValue(I.getArgOperand(0)),
4656 getValue(I.getArgOperand(1))));
4658 case Intrinsic::copysign:
4659 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4660 getValue(I.getArgOperand(0)).getValueType(),
4661 getValue(I.getArgOperand(0)),
4662 getValue(I.getArgOperand(1))));
4664 case Intrinsic::fma:
4665 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4666 getValue(I.getArgOperand(0)).getValueType(),
4667 getValue(I.getArgOperand(0)),
4668 getValue(I.getArgOperand(1)),
4669 getValue(I.getArgOperand(2))));
4671 case Intrinsic::fmuladd: {
4672 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4673 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4674 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4675 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4676 getValue(I.getArgOperand(0)).getValueType(),
4677 getValue(I.getArgOperand(0)),
4678 getValue(I.getArgOperand(1)),
4679 getValue(I.getArgOperand(2))));
4681 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4682 getValue(I.getArgOperand(0)).getValueType(),
4683 getValue(I.getArgOperand(0)),
4684 getValue(I.getArgOperand(1)));
4685 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4686 getValue(I.getArgOperand(0)).getValueType(),
4688 getValue(I.getArgOperand(2)));
4693 case Intrinsic::convert_to_fp16:
4694 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4695 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4696 getValue(I.getArgOperand(0)),
4697 DAG.getTargetConstant(0, sdl,
4700 case Intrinsic::convert_from_fp16:
4701 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4702 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4703 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4704 getValue(I.getArgOperand(0)))));
4706 case Intrinsic::pcmarker: {
4707 SDValue Tmp = getValue(I.getArgOperand(0));
4708 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4711 case Intrinsic::readcyclecounter: {
4712 SDValue Op = getRoot();
4713 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4714 DAG.getVTList(MVT::i64, MVT::Other), Op);
4716 DAG.setRoot(Res.getValue(1));
4719 case Intrinsic::bswap:
4720 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4721 getValue(I.getArgOperand(0)).getValueType(),
4722 getValue(I.getArgOperand(0))));
4724 case Intrinsic::uabsdiff:
4725 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4726 getValue(I.getArgOperand(0)).getValueType(),
4727 getValue(I.getArgOperand(0)),
4728 getValue(I.getArgOperand(1))));
4730 case Intrinsic::sabsdiff:
4731 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4732 getValue(I.getArgOperand(0)).getValueType(),
4733 getValue(I.getArgOperand(0)),
4734 getValue(I.getArgOperand(1))));
4736 case Intrinsic::cttz: {
4737 SDValue Arg = getValue(I.getArgOperand(0));
4738 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4739 EVT Ty = Arg.getValueType();
4740 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4744 case Intrinsic::ctlz: {
4745 SDValue Arg = getValue(I.getArgOperand(0));
4746 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4747 EVT Ty = Arg.getValueType();
4748 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4752 case Intrinsic::ctpop: {
4753 SDValue Arg = getValue(I.getArgOperand(0));
4754 EVT Ty = Arg.getValueType();
4755 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4758 case Intrinsic::stacksave: {
4759 SDValue Op = getRoot();
4761 ISD::STACKSAVE, sdl,
4762 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4764 DAG.setRoot(Res.getValue(1));
4767 case Intrinsic::stackrestore: {
4768 Res = getValue(I.getArgOperand(0));
4769 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4772 case Intrinsic::stackprotector: {
4773 // Emit code into the DAG to store the stack guard onto the stack.
4774 MachineFunction &MF = DAG.getMachineFunction();
4775 MachineFrameInfo *MFI = MF.getFrameInfo();
4776 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4777 SDValue Src, Chain = getRoot();
4778 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4779 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4781 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4782 // global variable __stack_chk_guard.
4784 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4785 if (BC->getOpcode() == Instruction::BitCast)
4786 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4788 if (GV && TLI.useLoadStackGuardNode()) {
4789 // Emit a LOAD_STACK_GUARD node.
4790 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4792 MachinePointerInfo MPInfo(GV);
4793 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4794 unsigned Flags = MachineMemOperand::MOLoad |
4795 MachineMemOperand::MOInvariant;
4796 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4797 PtrTy.getSizeInBits() / 8,
4798 DAG.getEVTAlignment(PtrTy));
4799 Node->setMemRefs(MemRefs, MemRefs + 1);
4801 // Copy the guard value to a virtual register so that it can be
4802 // retrieved in the epilogue.
4803 Src = SDValue(Node, 0);
4804 const TargetRegisterClass *RC =
4805 TLI.getRegClassFor(Src.getSimpleValueType());
4806 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4808 SPDescriptor.setGuardReg(Reg);
4809 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4811 Src = getValue(I.getArgOperand(0)); // The guard's value.
4814 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4816 int FI = FuncInfo.StaticAllocaMap[Slot];
4817 MFI->setStackProtectorIndex(FI);
4819 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4821 // Store the stack protector onto the stack.
4822 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4823 DAG.getMachineFunction(), FI),
4829 case Intrinsic::objectsize: {
4830 // If we don't know by now, we're never going to know.
4831 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4833 assert(CI && "Non-constant type in __builtin_object_size?");
4835 SDValue Arg = getValue(I.getCalledValue());
4836 EVT Ty = Arg.getValueType();
4839 Res = DAG.getConstant(-1ULL, sdl, Ty);
4841 Res = DAG.getConstant(0, sdl, Ty);
4846 case Intrinsic::annotation:
4847 case Intrinsic::ptr_annotation:
4848 // Drop the intrinsic, but forward the value
4849 setValue(&I, getValue(I.getOperand(0)));
4851 case Intrinsic::assume:
4852 case Intrinsic::var_annotation:
4853 // Discard annotate attributes and assumptions
4856 case Intrinsic::init_trampoline: {
4857 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4861 Ops[1] = getValue(I.getArgOperand(0));
4862 Ops[2] = getValue(I.getArgOperand(1));
4863 Ops[3] = getValue(I.getArgOperand(2));
4864 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4865 Ops[5] = DAG.getSrcValue(F);
4867 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4872 case Intrinsic::adjust_trampoline: {
4873 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4874 TLI.getPointerTy(DAG.getDataLayout()),
4875 getValue(I.getArgOperand(0))));
4878 case Intrinsic::gcroot:
4880 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4881 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4883 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4884 GFI->addStackRoot(FI->getIndex(), TypeMap);
4887 case Intrinsic::gcread:
4888 case Intrinsic::gcwrite:
4889 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4890 case Intrinsic::flt_rounds:
4891 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4894 case Intrinsic::expect: {
4895 // Just replace __builtin_expect(exp, c) with EXP.
4896 setValue(&I, getValue(I.getArgOperand(0)));
4900 case Intrinsic::debugtrap:
4901 case Intrinsic::trap: {
4902 StringRef TrapFuncName =
4904 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4905 .getValueAsString();
4906 if (TrapFuncName.empty()) {
4907 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4908 ISD::TRAP : ISD::DEBUGTRAP;
4909 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4912 TargetLowering::ArgListTy Args;
4914 TargetLowering::CallLoweringInfo CLI(DAG);
4915 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4916 CallingConv::C, I.getType(),
4917 DAG.getExternalSymbol(TrapFuncName.data(),
4918 TLI.getPointerTy(DAG.getDataLayout())),
4919 std::move(Args), 0);
4921 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4922 DAG.setRoot(Result.second);
4926 case Intrinsic::uadd_with_overflow:
4927 case Intrinsic::sadd_with_overflow:
4928 case Intrinsic::usub_with_overflow:
4929 case Intrinsic::ssub_with_overflow:
4930 case Intrinsic::umul_with_overflow:
4931 case Intrinsic::smul_with_overflow: {
4933 switch (Intrinsic) {
4934 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4935 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4936 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4937 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4938 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4939 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4940 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4942 SDValue Op1 = getValue(I.getArgOperand(0));
4943 SDValue Op2 = getValue(I.getArgOperand(1));
4945 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4946 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4949 case Intrinsic::prefetch: {
4951 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4953 Ops[1] = getValue(I.getArgOperand(0));
4954 Ops[2] = getValue(I.getArgOperand(1));
4955 Ops[3] = getValue(I.getArgOperand(2));
4956 Ops[4] = getValue(I.getArgOperand(3));
4957 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4958 DAG.getVTList(MVT::Other), Ops,
4959 EVT::getIntegerVT(*Context, 8),
4960 MachinePointerInfo(I.getArgOperand(0)),
4962 false, /* volatile */
4964 rw==1)); /* write */
4967 case Intrinsic::lifetime_start:
4968 case Intrinsic::lifetime_end: {
4969 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4970 // Stack coloring is not enabled in O0, discard region information.
4971 if (TM.getOptLevel() == CodeGenOpt::None)
4974 SmallVector<Value *, 4> Allocas;
4975 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4977 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4978 E = Allocas.end(); Object != E; ++Object) {
4979 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4981 // Could not find an Alloca.
4982 if (!LifetimeObject)
4985 // First check that the Alloca is static, otherwise it won't have a
4986 // valid frame index.
4987 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4988 if (SI == FuncInfo.StaticAllocaMap.end())
4991 int FI = SI->second;
4996 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
4997 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4999 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5004 case Intrinsic::invariant_start:
5005 // Discard region information.
5006 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5008 case Intrinsic::invariant_end:
5009 // Discard region information.
5011 case Intrinsic::stackprotectorcheck: {
5012 // Do not actually emit anything for this basic block. Instead we initialize
5013 // the stack protector descriptor and export the guard variable so we can
5014 // access it in FinishBasicBlock.
5015 const BasicBlock *BB = I.getParent();
5016 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5017 ExportFromCurrentBlock(SPDescriptor.getGuard());
5019 // Flush our exports since we are going to process a terminator.
5020 (void)getControlRoot();
5023 case Intrinsic::clear_cache:
5024 return TLI.getClearCacheBuiltinName();
5025 case Intrinsic::eh_actions:
5026 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5028 case Intrinsic::donothing:
5031 case Intrinsic::experimental_stackmap: {
5035 case Intrinsic::experimental_patchpoint_void:
5036 case Intrinsic::experimental_patchpoint_i64: {
5037 visitPatchpoint(&I);
5040 case Intrinsic::experimental_gc_statepoint: {
5044 case Intrinsic::experimental_gc_result_int:
5045 case Intrinsic::experimental_gc_result_float:
5046 case Intrinsic::experimental_gc_result_ptr:
5047 case Intrinsic::experimental_gc_result: {
5051 case Intrinsic::experimental_gc_relocate: {
5055 case Intrinsic::instrprof_increment:
5056 llvm_unreachable("instrprof failed to lower an increment");
5058 case Intrinsic::localescape: {
5059 MachineFunction &MF = DAG.getMachineFunction();
5060 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5062 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5063 // is the same on all targets.
5064 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5065 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5066 if (isa<ConstantPointerNull>(Arg))
5067 continue; // Skip null pointers. They represent a hole in index space.
5068 AllocaInst *Slot = cast<AllocaInst>(Arg);
5069 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5070 "can only escape static allocas");
5071 int FI = FuncInfo.StaticAllocaMap[Slot];
5072 MCSymbol *FrameAllocSym =
5073 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5074 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5076 TII->get(TargetOpcode::LOCAL_ESCAPE))
5077 .addSym(FrameAllocSym)
5084 case Intrinsic::localrecover: {
5085 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5086 MachineFunction &MF = DAG.getMachineFunction();
5087 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5089 // Get the symbol that defines the frame offset.
5090 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5091 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5092 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5093 MCSymbol *FrameAllocSym =
5094 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5095 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5097 // Create a MCSymbol for the label to avoid any target lowering
5098 // that would make this PC relative.
5099 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5101 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5103 // Add the offset to the FP.
5104 Value *FP = I.getArgOperand(1);
5105 SDValue FPVal = getValue(FP);
5106 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5111 case Intrinsic::eh_begincatch:
5112 case Intrinsic::eh_endcatch:
5113 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5114 case Intrinsic::eh_exceptioncode: {
5115 unsigned Reg = TLI.getExceptionPointerRegister();
5116 assert(Reg && "cannot get exception code on this platform");
5117 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5118 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5119 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5120 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5122 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5123 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5130 std::pair<SDValue, SDValue>
5131 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5132 MachineBasicBlock *LandingPad) {
5133 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5134 MCSymbol *BeginLabel = nullptr;
5137 // Insert a label before the invoke call to mark the try range. This can be
5138 // used to detect deletion of the invoke via the MachineModuleInfo.
5139 BeginLabel = MMI.getContext().createTempSymbol();
5141 // For SjLj, keep track of which landing pads go with which invokes
5142 // so as to maintain the ordering of pads in the LSDA.
5143 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5144 if (CallSiteIndex) {
5145 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5146 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5148 // Now that the call site is handled, stop tracking it.
5149 MMI.setCurrentCallSite(0);
5152 // Both PendingLoads and PendingExports must be flushed here;
5153 // this call might not return.
5155 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5157 CLI.setChain(getRoot());
5159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5160 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5162 assert((CLI.IsTailCall || Result.second.getNode()) &&
5163 "Non-null chain expected with non-tail call!");
5164 assert((Result.second.getNode() || !Result.first.getNode()) &&
5165 "Null value expected with tail call!");
5167 if (!Result.second.getNode()) {
5168 // As a special case, a null chain means that a tail call has been emitted
5169 // and the DAG root is already updated.
5172 // Since there's no actual continuation from this block, nothing can be
5173 // relying on us setting vregs for them.
5174 PendingExports.clear();
5176 DAG.setRoot(Result.second);
5180 // Insert a label at the end of the invoke call to mark the try range. This
5181 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5182 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5183 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5185 // Inform MachineModuleInfo of range.
5186 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5192 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5194 MachineBasicBlock *LandingPad) {
5195 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5196 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5197 Type *RetTy = FTy->getReturnType();
5199 TargetLowering::ArgListTy Args;
5200 TargetLowering::ArgListEntry Entry;
5201 Args.reserve(CS.arg_size());
5203 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5205 const Value *V = *i;
5208 if (V->getType()->isEmptyTy())
5211 SDValue ArgNode = getValue(V);
5212 Entry.Node = ArgNode; Entry.Ty = V->getType();
5214 // Skip the first return-type Attribute to get to params.
5215 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5216 Args.push_back(Entry);
5218 // If we have an explicit sret argument that is an Instruction, (i.e., it
5219 // might point to function-local memory), we can't meaningfully tail-call.
5220 if (Entry.isSRet && isa<Instruction>(V))
5224 // Check if target-independent constraints permit a tail call here.
5225 // Target-dependent constraints are checked within TLI->LowerCallTo.
5226 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5229 TargetLowering::CallLoweringInfo CLI(DAG);
5230 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5231 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5232 .setTailCall(isTailCall);
5233 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5235 if (Result.first.getNode())
5236 setValue(CS.getInstruction(), Result.first);
5239 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5240 /// value is equal or not-equal to zero.
5241 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5242 for (const User *U : V->users()) {
5243 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5244 if (IC->isEquality())
5245 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5246 if (C->isNullValue())
5248 // Unknown instruction.
5254 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5256 SelectionDAGBuilder &Builder) {
5258 // Check to see if this load can be trivially constant folded, e.g. if the
5259 // input is from a string literal.
5260 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5261 // Cast pointer to the type we really want to load.
5262 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5263 PointerType::getUnqual(LoadTy));
5265 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5266 const_cast<Constant *>(LoadInput), *Builder.DL))
5267 return Builder.getValue(LoadCst);
5270 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5271 // still constant memory, the input chain can be the entry node.
5273 bool ConstantMemory = false;
5275 // Do not serialize (non-volatile) loads of constant memory with anything.
5276 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5277 Root = Builder.DAG.getEntryNode();
5278 ConstantMemory = true;
5280 // Do not serialize non-volatile loads against each other.
5281 Root = Builder.DAG.getRoot();
5284 SDValue Ptr = Builder.getValue(PtrVal);
5285 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5286 Ptr, MachinePointerInfo(PtrVal),
5288 false /*nontemporal*/,
5289 false /*isinvariant*/, 1 /* align=1 */);
5291 if (!ConstantMemory)
5292 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5296 /// processIntegerCallValue - Record the value for an instruction that
5297 /// produces an integer result, converting the type where necessary.
5298 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5301 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5304 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5306 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5307 setValue(&I, Value);
5310 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5311 /// If so, return true and lower it, otherwise return false and it will be
5312 /// lowered like a normal call.
5313 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5314 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5315 if (I.getNumArgOperands() != 3)
5318 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5319 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5320 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5321 !I.getType()->isIntegerTy())
5324 const Value *Size = I.getArgOperand(2);
5325 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5326 if (CSize && CSize->getZExtValue() == 0) {
5327 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5329 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5333 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5334 std::pair<SDValue, SDValue> Res =
5335 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5336 getValue(LHS), getValue(RHS), getValue(Size),
5337 MachinePointerInfo(LHS),
5338 MachinePointerInfo(RHS));
5339 if (Res.first.getNode()) {
5340 processIntegerCallValue(I, Res.first, true);
5341 PendingLoads.push_back(Res.second);
5345 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5346 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5347 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5348 bool ActuallyDoIt = true;
5351 switch (CSize->getZExtValue()) {
5353 LoadVT = MVT::Other;
5355 ActuallyDoIt = false;
5359 LoadTy = Type::getInt16Ty(CSize->getContext());
5363 LoadTy = Type::getInt32Ty(CSize->getContext());
5367 LoadTy = Type::getInt64Ty(CSize->getContext());
5371 LoadVT = MVT::v4i32;
5372 LoadTy = Type::getInt32Ty(CSize->getContext());
5373 LoadTy = VectorType::get(LoadTy, 4);
5378 // This turns into unaligned loads. We only do this if the target natively
5379 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5380 // we'll only produce a small number of byte loads.
5382 // Require that we can find a legal MVT, and only do this if the target
5383 // supports unaligned loads of that type. Expanding into byte loads would
5385 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5386 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5387 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5388 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5389 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5390 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5391 // TODO: Check alignment of src and dest ptrs.
5392 if (!TLI.isTypeLegal(LoadVT) ||
5393 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5394 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5395 ActuallyDoIt = false;
5399 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5400 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5402 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5404 processIntegerCallValue(I, Res, false);
5413 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5414 /// form. If so, return true and lower it, otherwise return false and it
5415 /// will be lowered like a normal call.
5416 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5417 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5418 if (I.getNumArgOperands() != 3)
5421 const Value *Src = I.getArgOperand(0);
5422 const Value *Char = I.getArgOperand(1);
5423 const Value *Length = I.getArgOperand(2);
5424 if (!Src->getType()->isPointerTy() ||
5425 !Char->getType()->isIntegerTy() ||
5426 !Length->getType()->isIntegerTy() ||
5427 !I.getType()->isPointerTy())
5430 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5431 std::pair<SDValue, SDValue> Res =
5432 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5433 getValue(Src), getValue(Char), getValue(Length),
5434 MachinePointerInfo(Src));
5435 if (Res.first.getNode()) {
5436 setValue(&I, Res.first);
5437 PendingLoads.push_back(Res.second);
5444 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5445 /// optimized form. If so, return true and lower it, otherwise return false
5446 /// and it will be lowered like a normal call.
5447 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5448 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5449 if (I.getNumArgOperands() != 2)
5452 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5453 if (!Arg0->getType()->isPointerTy() ||
5454 !Arg1->getType()->isPointerTy() ||
5455 !I.getType()->isPointerTy())
5458 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5459 std::pair<SDValue, SDValue> Res =
5460 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5461 getValue(Arg0), getValue(Arg1),
5462 MachinePointerInfo(Arg0),
5463 MachinePointerInfo(Arg1), isStpcpy);
5464 if (Res.first.getNode()) {
5465 setValue(&I, Res.first);
5466 DAG.setRoot(Res.second);
5473 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5474 /// If so, return true and lower it, otherwise return false and it will be
5475 /// lowered like a normal call.
5476 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5477 // Verify that the prototype makes sense. int strcmp(void*,void*)
5478 if (I.getNumArgOperands() != 2)
5481 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5482 if (!Arg0->getType()->isPointerTy() ||
5483 !Arg1->getType()->isPointerTy() ||
5484 !I.getType()->isIntegerTy())
5487 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5488 std::pair<SDValue, SDValue> Res =
5489 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5490 getValue(Arg0), getValue(Arg1),
5491 MachinePointerInfo(Arg0),
5492 MachinePointerInfo(Arg1));
5493 if (Res.first.getNode()) {
5494 processIntegerCallValue(I, Res.first, true);
5495 PendingLoads.push_back(Res.second);
5502 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5503 /// form. If so, return true and lower it, otherwise return false and it
5504 /// will be lowered like a normal call.
5505 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5506 // Verify that the prototype makes sense. size_t strlen(char *)
5507 if (I.getNumArgOperands() != 1)
5510 const Value *Arg0 = I.getArgOperand(0);
5511 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5514 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5515 std::pair<SDValue, SDValue> Res =
5516 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5517 getValue(Arg0), MachinePointerInfo(Arg0));
5518 if (Res.first.getNode()) {
5519 processIntegerCallValue(I, Res.first, false);
5520 PendingLoads.push_back(Res.second);
5527 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5528 /// form. If so, return true and lower it, otherwise return false and it
5529 /// will be lowered like a normal call.
5530 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5531 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5532 if (I.getNumArgOperands() != 2)
5535 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5536 if (!Arg0->getType()->isPointerTy() ||
5537 !Arg1->getType()->isIntegerTy() ||
5538 !I.getType()->isIntegerTy())
5541 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5542 std::pair<SDValue, SDValue> Res =
5543 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5544 getValue(Arg0), getValue(Arg1),
5545 MachinePointerInfo(Arg0));
5546 if (Res.first.getNode()) {
5547 processIntegerCallValue(I, Res.first, false);
5548 PendingLoads.push_back(Res.second);
5555 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5556 /// operation (as expected), translate it to an SDNode with the specified opcode
5557 /// and return true.
5558 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5560 // Sanity check that it really is a unary floating-point call.
5561 if (I.getNumArgOperands() != 1 ||
5562 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5563 I.getType() != I.getArgOperand(0)->getType() ||
5564 !I.onlyReadsMemory())
5567 SDValue Tmp = getValue(I.getArgOperand(0));
5568 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5572 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5573 /// operation (as expected), translate it to an SDNode with the specified opcode
5574 /// and return true.
5575 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5577 // Sanity check that it really is a binary floating-point call.
5578 if (I.getNumArgOperands() != 2 ||
5579 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5580 I.getType() != I.getArgOperand(0)->getType() ||
5581 I.getType() != I.getArgOperand(1)->getType() ||
5582 !I.onlyReadsMemory())
5585 SDValue Tmp0 = getValue(I.getArgOperand(0));
5586 SDValue Tmp1 = getValue(I.getArgOperand(1));
5587 EVT VT = Tmp0.getValueType();
5588 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5592 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5593 // Handle inline assembly differently.
5594 if (isa<InlineAsm>(I.getCalledValue())) {
5599 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5600 ComputeUsesVAFloatArgument(I, &MMI);
5602 const char *RenameFn = nullptr;
5603 if (Function *F = I.getCalledFunction()) {
5604 if (F->isDeclaration()) {
5605 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5606 if (unsigned IID = II->getIntrinsicID(F)) {
5607 RenameFn = visitIntrinsicCall(I, IID);
5612 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5613 RenameFn = visitIntrinsicCall(I, IID);
5619 // Check for well-known libc/libm calls. If the function is internal, it
5620 // can't be a library call.
5622 if (!F->hasLocalLinkage() && F->hasName() &&
5623 LibInfo->getLibFunc(F->getName(), Func) &&
5624 LibInfo->hasOptimizedCodeGen(Func)) {
5627 case LibFunc::copysign:
5628 case LibFunc::copysignf:
5629 case LibFunc::copysignl:
5630 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5631 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5632 I.getType() == I.getArgOperand(0)->getType() &&
5633 I.getType() == I.getArgOperand(1)->getType() &&
5634 I.onlyReadsMemory()) {
5635 SDValue LHS = getValue(I.getArgOperand(0));
5636 SDValue RHS = getValue(I.getArgOperand(1));
5637 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5638 LHS.getValueType(), LHS, RHS));
5643 case LibFunc::fabsf:
5644 case LibFunc::fabsl:
5645 if (visitUnaryFloatCall(I, ISD::FABS))
5649 case LibFunc::fminf:
5650 case LibFunc::fminl:
5651 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5655 case LibFunc::fmaxf:
5656 case LibFunc::fmaxl:
5657 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5663 if (visitUnaryFloatCall(I, ISD::FSIN))
5669 if (visitUnaryFloatCall(I, ISD::FCOS))
5673 case LibFunc::sqrtf:
5674 case LibFunc::sqrtl:
5675 case LibFunc::sqrt_finite:
5676 case LibFunc::sqrtf_finite:
5677 case LibFunc::sqrtl_finite:
5678 if (visitUnaryFloatCall(I, ISD::FSQRT))
5681 case LibFunc::floor:
5682 case LibFunc::floorf:
5683 case LibFunc::floorl:
5684 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5687 case LibFunc::nearbyint:
5688 case LibFunc::nearbyintf:
5689 case LibFunc::nearbyintl:
5690 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5694 case LibFunc::ceilf:
5695 case LibFunc::ceill:
5696 if (visitUnaryFloatCall(I, ISD::FCEIL))
5700 case LibFunc::rintf:
5701 case LibFunc::rintl:
5702 if (visitUnaryFloatCall(I, ISD::FRINT))
5705 case LibFunc::round:
5706 case LibFunc::roundf:
5707 case LibFunc::roundl:
5708 if (visitUnaryFloatCall(I, ISD::FROUND))
5711 case LibFunc::trunc:
5712 case LibFunc::truncf:
5713 case LibFunc::truncl:
5714 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5718 case LibFunc::log2f:
5719 case LibFunc::log2l:
5720 if (visitUnaryFloatCall(I, ISD::FLOG2))
5724 case LibFunc::exp2f:
5725 case LibFunc::exp2l:
5726 if (visitUnaryFloatCall(I, ISD::FEXP2))
5729 case LibFunc::memcmp:
5730 if (visitMemCmpCall(I))
5733 case LibFunc::memchr:
5734 if (visitMemChrCall(I))
5737 case LibFunc::strcpy:
5738 if (visitStrCpyCall(I, false))
5741 case LibFunc::stpcpy:
5742 if (visitStrCpyCall(I, true))
5745 case LibFunc::strcmp:
5746 if (visitStrCmpCall(I))
5749 case LibFunc::strlen:
5750 if (visitStrLenCall(I))
5753 case LibFunc::strnlen:
5754 if (visitStrNLenCall(I))
5763 Callee = getValue(I.getCalledValue());
5765 Callee = DAG.getExternalSymbol(
5767 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5769 // Check if we can potentially perform a tail call. More detailed checking is
5770 // be done within LowerCallTo, after more information about the call is known.
5771 LowerCallTo(&I, Callee, I.isTailCall());
5776 /// AsmOperandInfo - This contains information for each constraint that we are
5778 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5780 /// CallOperand - If this is the result output operand or a clobber
5781 /// this is null, otherwise it is the incoming operand to the CallInst.
5782 /// This gets modified as the asm is processed.
5783 SDValue CallOperand;
5785 /// AssignedRegs - If this is a register or register class operand, this
5786 /// contains the set of register corresponding to the operand.
5787 RegsForValue AssignedRegs;
5789 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5790 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5793 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5794 /// corresponds to. If there is no Value* for this operand, it returns
5796 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5797 const DataLayout &DL) const {
5798 if (!CallOperandVal) return MVT::Other;
5800 if (isa<BasicBlock>(CallOperandVal))
5801 return TLI.getPointerTy(DL);
5803 llvm::Type *OpTy = CallOperandVal->getType();
5805 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5806 // If this is an indirect operand, the operand is a pointer to the
5809 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5811 report_fatal_error("Indirect operand for inline asm not a pointer!");
5812 OpTy = PtrTy->getElementType();
5815 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5816 if (StructType *STy = dyn_cast<StructType>(OpTy))
5817 if (STy->getNumElements() == 1)
5818 OpTy = STy->getElementType(0);
5820 // If OpTy is not a single value, it may be a struct/union that we
5821 // can tile with integers.
5822 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5823 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5832 OpTy = IntegerType::get(Context, BitSize);
5837 return TLI.getValueType(DL, OpTy, true);
5841 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5843 } // end anonymous namespace
5845 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5846 /// specified operand. We prefer to assign virtual registers, to allow the
5847 /// register allocator to handle the assignment process. However, if the asm
5848 /// uses features that we can't model on machineinstrs, we have SDISel do the
5849 /// allocation. This produces generally horrible, but correct, code.
5851 /// OpInfo describes the operand.
5853 static void GetRegistersForValue(SelectionDAG &DAG,
5854 const TargetLowering &TLI,
5856 SDISelAsmOperandInfo &OpInfo) {
5857 LLVMContext &Context = *DAG.getContext();
5859 MachineFunction &MF = DAG.getMachineFunction();
5860 SmallVector<unsigned, 4> Regs;
5862 // If this is a constraint for a single physreg, or a constraint for a
5863 // register class, find it.
5864 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5865 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5866 OpInfo.ConstraintCode,
5867 OpInfo.ConstraintVT);
5869 unsigned NumRegs = 1;
5870 if (OpInfo.ConstraintVT != MVT::Other) {
5871 // If this is a FP input in an integer register (or visa versa) insert a bit
5872 // cast of the input value. More generally, handle any case where the input
5873 // value disagrees with the register class we plan to stick this in.
5874 if (OpInfo.Type == InlineAsm::isInput &&
5875 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5876 // Try to convert to the first EVT that the reg class contains. If the
5877 // types are identical size, use a bitcast to convert (e.g. two differing
5879 MVT RegVT = *PhysReg.second->vt_begin();
5880 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5881 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5882 RegVT, OpInfo.CallOperand);
5883 OpInfo.ConstraintVT = RegVT;
5884 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5885 // If the input is a FP value and we want it in FP registers, do a
5886 // bitcast to the corresponding integer type. This turns an f64 value
5887 // into i64, which can be passed with two i32 values on a 32-bit
5889 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5890 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5891 RegVT, OpInfo.CallOperand);
5892 OpInfo.ConstraintVT = RegVT;
5896 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5900 EVT ValueVT = OpInfo.ConstraintVT;
5902 // If this is a constraint for a specific physical register, like {r17},
5904 if (unsigned AssignedReg = PhysReg.first) {
5905 const TargetRegisterClass *RC = PhysReg.second;
5906 if (OpInfo.ConstraintVT == MVT::Other)
5907 ValueVT = *RC->vt_begin();
5909 // Get the actual register value type. This is important, because the user
5910 // may have asked for (e.g.) the AX register in i32 type. We need to
5911 // remember that AX is actually i16 to get the right extension.
5912 RegVT = *RC->vt_begin();
5914 // This is a explicit reference to a physical register.
5915 Regs.push_back(AssignedReg);
5917 // If this is an expanded reference, add the rest of the regs to Regs.
5919 TargetRegisterClass::iterator I = RC->begin();
5920 for (; *I != AssignedReg; ++I)
5921 assert(I != RC->end() && "Didn't find reg!");
5923 // Already added the first reg.
5925 for (; NumRegs; --NumRegs, ++I) {
5926 assert(I != RC->end() && "Ran out of registers to allocate!");
5931 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5935 // Otherwise, if this was a reference to an LLVM register class, create vregs
5936 // for this reference.
5937 if (const TargetRegisterClass *RC = PhysReg.second) {
5938 RegVT = *RC->vt_begin();
5939 if (OpInfo.ConstraintVT == MVT::Other)
5942 // Create the appropriate number of virtual registers.
5943 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5944 for (; NumRegs; --NumRegs)
5945 Regs.push_back(RegInfo.createVirtualRegister(RC));
5947 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5951 // Otherwise, we couldn't allocate enough registers for this.
5954 /// visitInlineAsm - Handle a call to an InlineAsm object.
5956 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5957 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5959 /// ConstraintOperands - Information about all of the constraints.
5960 SDISelAsmOperandInfoVector ConstraintOperands;
5962 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5963 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5964 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5966 bool hasMemory = false;
5968 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5969 unsigned ResNo = 0; // ResNo - The result number of the next output.
5970 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5971 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5972 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5974 MVT OpVT = MVT::Other;
5976 // Compute the value type for each operand.
5977 switch (OpInfo.Type) {
5978 case InlineAsm::isOutput:
5979 // Indirect outputs just consume an argument.
5980 if (OpInfo.isIndirect) {
5981 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5985 // The return value of the call is this value. As such, there is no
5986 // corresponding argument.
5987 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5988 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5989 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
5990 STy->getElementType(ResNo));
5992 assert(ResNo == 0 && "Asm only has one result!");
5993 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
5997 case InlineAsm::isInput:
5998 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6000 case InlineAsm::isClobber:
6005 // If this is an input or an indirect output, process the call argument.
6006 // BasicBlocks are labels, currently appearing only in asm's.
6007 if (OpInfo.CallOperandVal) {
6008 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6009 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6011 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6014 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6015 DAG.getDataLayout()).getSimpleVT();
6018 OpInfo.ConstraintVT = OpVT;
6020 // Indirect operand accesses access memory.
6021 if (OpInfo.isIndirect)
6024 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6025 TargetLowering::ConstraintType
6026 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6027 if (CType == TargetLowering::C_Memory) {
6035 SDValue Chain, Flag;
6037 // We won't need to flush pending loads if this asm doesn't touch
6038 // memory and is nonvolatile.
6039 if (hasMemory || IA->hasSideEffects())
6042 Chain = DAG.getRoot();
6044 // Second pass over the constraints: compute which constraint option to use
6045 // and assign registers to constraints that want a specific physreg.
6046 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6047 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6049 // If this is an output operand with a matching input operand, look up the
6050 // matching input. If their types mismatch, e.g. one is an integer, the
6051 // other is floating point, or their sizes are different, flag it as an
6053 if (OpInfo.hasMatchingInput()) {
6054 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6056 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6057 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6058 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6059 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6060 OpInfo.ConstraintVT);
6061 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6062 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6063 Input.ConstraintVT);
6064 if ((OpInfo.ConstraintVT.isInteger() !=
6065 Input.ConstraintVT.isInteger()) ||
6066 (MatchRC.second != InputRC.second)) {
6067 report_fatal_error("Unsupported asm: input constraint"
6068 " with a matching output constraint of"
6069 " incompatible type!");
6071 Input.ConstraintVT = OpInfo.ConstraintVT;
6075 // Compute the constraint code and ConstraintType to use.
6076 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6078 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6079 OpInfo.Type == InlineAsm::isClobber)
6082 // If this is a memory input, and if the operand is not indirect, do what we
6083 // need to to provide an address for the memory input.
6084 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6085 !OpInfo.isIndirect) {
6086 assert((OpInfo.isMultipleAlternative ||
6087 (OpInfo.Type == InlineAsm::isInput)) &&
6088 "Can only indirectify direct input operands!");
6090 // Memory operands really want the address of the value. If we don't have
6091 // an indirect input, put it in the constpool if we can, otherwise spill
6092 // it to a stack slot.
6093 // TODO: This isn't quite right. We need to handle these according to
6094 // the addressing mode that the constraint wants. Also, this may take
6095 // an additional register for the computation and we don't want that
6098 // If the operand is a float, integer, or vector constant, spill to a
6099 // constant pool entry to get its address.
6100 const Value *OpVal = OpInfo.CallOperandVal;
6101 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6102 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6103 OpInfo.CallOperand = DAG.getConstantPool(
6104 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6106 // Otherwise, create a stack slot and emit a store to it before the
6108 Type *Ty = OpVal->getType();
6109 auto &DL = DAG.getDataLayout();
6110 uint64_t TySize = DL.getTypeAllocSize(Ty);
6111 unsigned Align = DL.getPrefTypeAlignment(Ty);
6112 MachineFunction &MF = DAG.getMachineFunction();
6113 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6115 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6116 Chain = DAG.getStore(
6117 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6118 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6120 OpInfo.CallOperand = StackSlot;
6123 // There is no longer a Value* corresponding to this operand.
6124 OpInfo.CallOperandVal = nullptr;
6126 // It is now an indirect operand.
6127 OpInfo.isIndirect = true;
6130 // If this constraint is for a specific register, allocate it before
6132 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6133 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6136 // Second pass - Loop over all of the operands, assigning virtual or physregs
6137 // to register class operands.
6138 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6139 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6141 // C_Register operands have already been allocated, Other/Memory don't need
6143 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6144 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6147 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6148 std::vector<SDValue> AsmNodeOperands;
6149 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6150 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6151 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6153 // If we have a !srcloc metadata node associated with it, we want to attach
6154 // this to the ultimately generated inline asm machineinstr. To do this, we
6155 // pass in the third operand as this (potentially null) inline asm MDNode.
6156 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6157 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6159 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6160 // bits as operand 3.
6161 unsigned ExtraInfo = 0;
6162 if (IA->hasSideEffects())
6163 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6164 if (IA->isAlignStack())
6165 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6166 // Set the asm dialect.
6167 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6169 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6170 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6171 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6173 // Compute the constraint code and ConstraintType to use.
6174 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6176 // Ideally, we would only check against memory constraints. However, the
6177 // meaning of an other constraint can be target-specific and we can't easily
6178 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6179 // for other constriants as well.
6180 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6181 OpInfo.ConstraintType == TargetLowering::C_Other) {
6182 if (OpInfo.Type == InlineAsm::isInput)
6183 ExtraInfo |= InlineAsm::Extra_MayLoad;
6184 else if (OpInfo.Type == InlineAsm::isOutput)
6185 ExtraInfo |= InlineAsm::Extra_MayStore;
6186 else if (OpInfo.Type == InlineAsm::isClobber)
6187 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6191 AsmNodeOperands.push_back(DAG.getTargetConstant(
6192 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6194 // Loop over all of the inputs, copying the operand values into the
6195 // appropriate registers and processing the output regs.
6196 RegsForValue RetValRegs;
6198 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6199 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6201 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6202 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6204 switch (OpInfo.Type) {
6205 case InlineAsm::isOutput: {
6206 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6207 OpInfo.ConstraintType != TargetLowering::C_Register) {
6208 // Memory output, or 'other' output (e.g. 'X' constraint).
6209 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6211 unsigned ConstraintID =
6212 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6213 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6214 "Failed to convert memory constraint code to constraint id.");
6216 // Add information to the INLINEASM node to know about this output.
6217 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6218 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6219 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6221 AsmNodeOperands.push_back(OpInfo.CallOperand);
6225 // Otherwise, this is a register or register class output.
6227 // Copy the output from the appropriate register. Find a register that
6229 if (OpInfo.AssignedRegs.Regs.empty()) {
6230 LLVMContext &Ctx = *DAG.getContext();
6231 Ctx.emitError(CS.getInstruction(),
6232 "couldn't allocate output register for constraint '" +
6233 Twine(OpInfo.ConstraintCode) + "'");
6237 // If this is an indirect operand, store through the pointer after the
6239 if (OpInfo.isIndirect) {
6240 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6241 OpInfo.CallOperandVal));
6243 // This is the result value of the call.
6244 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6245 // Concatenate this output onto the outputs list.
6246 RetValRegs.append(OpInfo.AssignedRegs);
6249 // Add information to the INLINEASM node to know that this register is
6252 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6253 ? InlineAsm::Kind_RegDefEarlyClobber
6254 : InlineAsm::Kind_RegDef,
6255 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6258 case InlineAsm::isInput: {
6259 SDValue InOperandVal = OpInfo.CallOperand;
6261 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6262 // If this is required to match an output register we have already set,
6263 // just use its register.
6264 unsigned OperandNo = OpInfo.getMatchedOperand();
6266 // Scan until we find the definition we already emitted of this operand.
6267 // When we find it, create a RegsForValue operand.
6268 unsigned CurOp = InlineAsm::Op_FirstOperand;
6269 for (; OperandNo; --OperandNo) {
6270 // Advance to the next operand.
6272 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6273 assert((InlineAsm::isRegDefKind(OpFlag) ||
6274 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6275 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6276 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6280 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6281 if (InlineAsm::isRegDefKind(OpFlag) ||
6282 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6283 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6284 if (OpInfo.isIndirect) {
6285 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6286 LLVMContext &Ctx = *DAG.getContext();
6287 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6288 " don't know how to handle tied "
6289 "indirect register inputs");
6293 RegsForValue MatchedRegs;
6294 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6295 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6296 MatchedRegs.RegVTs.push_back(RegVT);
6297 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6298 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6300 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6301 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6303 LLVMContext &Ctx = *DAG.getContext();
6304 Ctx.emitError(CS.getInstruction(),
6305 "inline asm error: This value"
6306 " type register class is not natively supported!");
6310 SDLoc dl = getCurSDLoc();
6311 // Use the produced MatchedRegs object to
6312 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6313 Chain, &Flag, CS.getInstruction());
6314 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6315 true, OpInfo.getMatchedOperand(), dl,
6316 DAG, AsmNodeOperands);
6320 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6321 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6322 "Unexpected number of operands");
6323 // Add information to the INLINEASM node to know about this input.
6324 // See InlineAsm.h isUseOperandTiedToDef.
6325 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6326 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6327 OpInfo.getMatchedOperand());
6328 AsmNodeOperands.push_back(DAG.getTargetConstant(
6329 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6330 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6334 // Treat indirect 'X' constraint as memory.
6335 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6337 OpInfo.ConstraintType = TargetLowering::C_Memory;
6339 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6340 std::vector<SDValue> Ops;
6341 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6344 LLVMContext &Ctx = *DAG.getContext();
6345 Ctx.emitError(CS.getInstruction(),
6346 "invalid operand for inline asm constraint '" +
6347 Twine(OpInfo.ConstraintCode) + "'");
6351 // Add information to the INLINEASM node to know about this input.
6352 unsigned ResOpType =
6353 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6354 AsmNodeOperands.push_back(DAG.getTargetConstant(
6355 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6356 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6360 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6361 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6362 assert(InOperandVal.getValueType() ==
6363 TLI.getPointerTy(DAG.getDataLayout()) &&
6364 "Memory operands expect pointer values");
6366 unsigned ConstraintID =
6367 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6368 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6369 "Failed to convert memory constraint code to constraint id.");
6371 // Add information to the INLINEASM node to know about this input.
6372 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6373 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6374 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6377 AsmNodeOperands.push_back(InOperandVal);
6381 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6382 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6383 "Unknown constraint type!");
6385 // TODO: Support this.
6386 if (OpInfo.isIndirect) {
6387 LLVMContext &Ctx = *DAG.getContext();
6388 Ctx.emitError(CS.getInstruction(),
6389 "Don't know how to handle indirect register inputs yet "
6390 "for constraint '" +
6391 Twine(OpInfo.ConstraintCode) + "'");
6395 // Copy the input into the appropriate registers.
6396 if (OpInfo.AssignedRegs.Regs.empty()) {
6397 LLVMContext &Ctx = *DAG.getContext();
6398 Ctx.emitError(CS.getInstruction(),
6399 "couldn't allocate input reg for constraint '" +
6400 Twine(OpInfo.ConstraintCode) + "'");
6404 SDLoc dl = getCurSDLoc();
6406 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6407 Chain, &Flag, CS.getInstruction());
6409 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6410 dl, DAG, AsmNodeOperands);
6413 case InlineAsm::isClobber: {
6414 // Add the clobbered value to the operand list, so that the register
6415 // allocator is aware that the physreg got clobbered.
6416 if (!OpInfo.AssignedRegs.Regs.empty())
6417 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6418 false, 0, getCurSDLoc(), DAG,
6425 // Finish up input operands. Set the input chain and add the flag last.
6426 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6427 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6429 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6430 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6431 Flag = Chain.getValue(1);
6433 // If this asm returns a register value, copy the result from that register
6434 // and set it as the value of the call.
6435 if (!RetValRegs.Regs.empty()) {
6436 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6437 Chain, &Flag, CS.getInstruction());
6439 // FIXME: Why don't we do this for inline asms with MRVs?
6440 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6441 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6443 // If any of the results of the inline asm is a vector, it may have the
6444 // wrong width/num elts. This can happen for register classes that can
6445 // contain multiple different value types. The preg or vreg allocated may
6446 // not have the same VT as was expected. Convert it to the right type
6447 // with bit_convert.
6448 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6449 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6452 } else if (ResultType != Val.getValueType() &&
6453 ResultType.isInteger() && Val.getValueType().isInteger()) {
6454 // If a result value was tied to an input value, the computed result may
6455 // have a wider width than the expected result. Extract the relevant
6457 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6460 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6463 setValue(CS.getInstruction(), Val);
6464 // Don't need to use this as a chain in this case.
6465 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6469 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6471 // Process indirect outputs, first output all of the flagged copies out of
6473 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6474 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6475 const Value *Ptr = IndirectStoresToEmit[i].second;
6476 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6478 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6481 // Emit the non-flagged stores from the physregs.
6482 SmallVector<SDValue, 8> OutChains;
6483 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6484 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6485 StoresToEmit[i].first,
6486 getValue(StoresToEmit[i].second),
6487 MachinePointerInfo(StoresToEmit[i].second),
6489 OutChains.push_back(Val);
6492 if (!OutChains.empty())
6493 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6498 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6499 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6500 MVT::Other, getRoot(),
6501 getValue(I.getArgOperand(0)),
6502 DAG.getSrcValue(I.getArgOperand(0))));
6505 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6506 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6507 const DataLayout &DL = DAG.getDataLayout();
6508 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6509 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6510 DAG.getSrcValue(I.getOperand(0)),
6511 DL.getABITypeAlignment(I.getType()));
6513 DAG.setRoot(V.getValue(1));
6516 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6517 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6518 MVT::Other, getRoot(),
6519 getValue(I.getArgOperand(0)),
6520 DAG.getSrcValue(I.getArgOperand(0))));
6523 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6524 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6525 MVT::Other, getRoot(),
6526 getValue(I.getArgOperand(0)),
6527 getValue(I.getArgOperand(1)),
6528 DAG.getSrcValue(I.getArgOperand(0)),
6529 DAG.getSrcValue(I.getArgOperand(1))));
6532 /// \brief Lower an argument list according to the target calling convention.
6534 /// \return A tuple of <return-value, token-chain>
6536 /// This is a helper for lowering intrinsics that follow a target calling
6537 /// convention or require stack pointer adjustment. Only a subset of the
6538 /// intrinsic's operands need to participate in the calling convention.
6539 std::pair<SDValue, SDValue>
6540 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6541 unsigned NumArgs, SDValue Callee,
6543 MachineBasicBlock *LandingPad,
6544 bool IsPatchPoint) {
6545 TargetLowering::ArgListTy Args;
6546 Args.reserve(NumArgs);
6548 // Populate the argument list.
6549 // Attributes for args start at offset 1, after the return attribute.
6550 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6551 ArgI != ArgE; ++ArgI) {
6552 const Value *V = CS->getOperand(ArgI);
6554 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6556 TargetLowering::ArgListEntry Entry;
6557 Entry.Node = getValue(V);
6558 Entry.Ty = V->getType();
6559 Entry.setAttributes(&CS, AttrI);
6560 Args.push_back(Entry);
6563 TargetLowering::CallLoweringInfo CLI(DAG);
6564 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6565 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6566 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6568 return lowerInvokable(CLI, LandingPad);
6571 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6572 /// or patchpoint target node's operand list.
6574 /// Constants are converted to TargetConstants purely as an optimization to
6575 /// avoid constant materialization and register allocation.
6577 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6578 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6579 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6580 /// address materialization and register allocation, but may also be required
6581 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6582 /// alloca in the entry block, then the runtime may assume that the alloca's
6583 /// StackMap location can be read immediately after compilation and that the
6584 /// location is valid at any point during execution (this is similar to the
6585 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6586 /// only available in a register, then the runtime would need to trap when
6587 /// execution reaches the StackMap in order to read the alloca's location.
6588 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6589 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6590 SelectionDAGBuilder &Builder) {
6591 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6592 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6595 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6597 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6598 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6599 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6600 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6601 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6603 Ops.push_back(OpVal);
6607 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6608 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6609 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6610 // [live variables...])
6612 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6614 SDValue Chain, InFlag, Callee, NullPtr;
6615 SmallVector<SDValue, 32> Ops;
6617 SDLoc DL = getCurSDLoc();
6618 Callee = getValue(CI.getCalledValue());
6619 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6621 // The stackmap intrinsic only records the live variables (the arguemnts
6622 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6623 // intrinsic, this won't be lowered to a function call. This means we don't
6624 // have to worry about calling conventions and target specific lowering code.
6625 // Instead we perform the call lowering right here.
6627 // chain, flag = CALLSEQ_START(chain, 0)
6628 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6629 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6631 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6632 InFlag = Chain.getValue(1);
6634 // Add the <id> and <numBytes> constants.
6635 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6636 Ops.push_back(DAG.getTargetConstant(
6637 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6638 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6639 Ops.push_back(DAG.getTargetConstant(
6640 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6643 // Push live variables for the stack map.
6644 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6646 // We are not pushing any register mask info here on the operands list,
6647 // because the stackmap doesn't clobber anything.
6649 // Push the chain and the glue flag.
6650 Ops.push_back(Chain);
6651 Ops.push_back(InFlag);
6653 // Create the STACKMAP node.
6654 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6655 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6656 Chain = SDValue(SM, 0);
6657 InFlag = Chain.getValue(1);
6659 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6661 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6663 // Set the root to the target-lowered call chain.
6666 // Inform the Frame Information that we have a stackmap in this function.
6667 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6670 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6671 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6672 MachineBasicBlock *LandingPad) {
6673 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6678 // [live variables...])
6680 CallingConv::ID CC = CS.getCallingConv();
6681 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6682 bool HasDef = !CS->getType()->isVoidTy();
6683 SDLoc dl = getCurSDLoc();
6684 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6686 // Handle immediate and symbolic callees.
6687 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6688 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6690 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6691 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6692 SDLoc(SymbolicCallee),
6693 SymbolicCallee->getValueType(0));
6695 // Get the real number of arguments participating in the call <numArgs>
6696 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6697 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6699 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6700 // Intrinsics include all meta-operands up to but not including CC.
6701 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6702 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6703 "Not enough arguments provided to the patchpoint intrinsic");
6705 // For AnyRegCC the arguments are lowered later on manually.
6706 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6708 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6709 std::pair<SDValue, SDValue> Result =
6710 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6713 SDNode *CallEnd = Result.second.getNode();
6714 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6715 CallEnd = CallEnd->getOperand(0).getNode();
6717 /// Get a call instruction from the call sequence chain.
6718 /// Tail calls are not allowed.
6719 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6720 "Expected a callseq node.");
6721 SDNode *Call = CallEnd->getOperand(0).getNode();
6722 bool HasGlue = Call->getGluedNode();
6724 // Replace the target specific call node with the patchable intrinsic.
6725 SmallVector<SDValue, 8> Ops;
6727 // Add the <id> and <numBytes> constants.
6728 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6729 Ops.push_back(DAG.getTargetConstant(
6730 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6731 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6732 Ops.push_back(DAG.getTargetConstant(
6733 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6737 Ops.push_back(Callee);
6739 // Adjust <numArgs> to account for any arguments that have been passed on the
6741 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6742 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6743 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6744 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6746 // Add the calling convention
6747 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6749 // Add the arguments we omitted previously. The register allocator should
6750 // place these in any free register.
6752 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6753 Ops.push_back(getValue(CS.getArgument(i)));
6755 // Push the arguments from the call instruction up to the register mask.
6756 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6757 Ops.append(Call->op_begin() + 2, e);
6759 // Push live variables for the stack map.
6760 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6762 // Push the register mask info.
6764 Ops.push_back(*(Call->op_end()-2));
6766 Ops.push_back(*(Call->op_end()-1));
6768 // Push the chain (this is originally the first operand of the call, but
6769 // becomes now the last or second to last operand).
6770 Ops.push_back(*(Call->op_begin()));
6772 // Push the glue flag (last operand).
6774 Ops.push_back(*(Call->op_end()-1));
6777 if (IsAnyRegCC && HasDef) {
6778 // Create the return types based on the intrinsic definition
6779 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6780 SmallVector<EVT, 3> ValueVTs;
6781 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6782 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6784 // There is always a chain and a glue type at the end
6785 ValueVTs.push_back(MVT::Other);
6786 ValueVTs.push_back(MVT::Glue);
6787 NodeTys = DAG.getVTList(ValueVTs);
6789 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6791 // Replace the target specific call node with a PATCHPOINT node.
6792 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6795 // Update the NodeMap.
6798 setValue(CS.getInstruction(), SDValue(MN, 0));
6800 setValue(CS.getInstruction(), Result.first);
6803 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6804 // call sequence. Furthermore the location of the chain and glue can change
6805 // when the AnyReg calling convention is used and the intrinsic returns a
6807 if (IsAnyRegCC && HasDef) {
6808 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6809 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6810 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6812 DAG.ReplaceAllUsesWith(Call, MN);
6813 DAG.DeleteNode(Call);
6815 // Inform the Frame Information that we have a patchpoint in this function.
6816 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6819 /// Returns an AttributeSet representing the attributes applied to the return
6820 /// value of the given call.
6821 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6822 SmallVector<Attribute::AttrKind, 2> Attrs;
6824 Attrs.push_back(Attribute::SExt);
6826 Attrs.push_back(Attribute::ZExt);
6828 Attrs.push_back(Attribute::InReg);
6830 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6834 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6835 /// implementation, which just calls LowerCall.
6836 /// FIXME: When all targets are
6837 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6838 std::pair<SDValue, SDValue>
6839 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6840 // Handle the incoming return values from the call.
6842 Type *OrigRetTy = CLI.RetTy;
6843 SmallVector<EVT, 4> RetTys;
6844 SmallVector<uint64_t, 4> Offsets;
6845 auto &DL = CLI.DAG.getDataLayout();
6846 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6848 SmallVector<ISD::OutputArg, 4> Outs;
6849 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6851 bool CanLowerReturn =
6852 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6853 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6855 SDValue DemoteStackSlot;
6856 int DemoteStackIdx = -100;
6857 if (!CanLowerReturn) {
6858 // FIXME: equivalent assert?
6859 // assert(!CS.hasInAllocaArgument() &&
6860 // "sret demotion is incompatible with inalloca");
6861 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6862 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6863 MachineFunction &MF = CLI.DAG.getMachineFunction();
6864 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6865 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6867 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6869 Entry.Node = DemoteStackSlot;
6870 Entry.Ty = StackSlotPtrType;
6871 Entry.isSExt = false;
6872 Entry.isZExt = false;
6873 Entry.isInReg = false;
6874 Entry.isSRet = true;
6875 Entry.isNest = false;
6876 Entry.isByVal = false;
6877 Entry.isReturned = false;
6878 Entry.Alignment = Align;
6879 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6880 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6882 // sret demotion isn't compatible with tail-calls, since the sret argument
6883 // points into the callers stack frame.
6884 CLI.IsTailCall = false;
6886 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6888 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6889 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6890 for (unsigned i = 0; i != NumRegs; ++i) {
6891 ISD::InputArg MyFlags;
6892 MyFlags.VT = RegisterVT;
6894 MyFlags.Used = CLI.IsReturnValueUsed;
6896 MyFlags.Flags.setSExt();
6898 MyFlags.Flags.setZExt();
6900 MyFlags.Flags.setInReg();
6901 CLI.Ins.push_back(MyFlags);
6906 // Handle all of the outgoing arguments.
6908 CLI.OutVals.clear();
6909 ArgListTy &Args = CLI.getArgs();
6910 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6911 SmallVector<EVT, 4> ValueVTs;
6912 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6913 Type *FinalType = Args[i].Ty;
6914 if (Args[i].isByVal)
6915 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6916 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6917 FinalType, CLI.CallConv, CLI.IsVarArg);
6918 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6920 EVT VT = ValueVTs[Value];
6921 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6922 SDValue Op = SDValue(Args[i].Node.getNode(),
6923 Args[i].Node.getResNo() + Value);
6924 ISD::ArgFlagsTy Flags;
6925 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6931 if (Args[i].isInReg)
6935 if (Args[i].isByVal)
6937 if (Args[i].isInAlloca) {
6938 Flags.setInAlloca();
6939 // Set the byval flag for CCAssignFn callbacks that don't know about
6940 // inalloca. This way we can know how many bytes we should've allocated
6941 // and how many bytes a callee cleanup function will pop. If we port
6942 // inalloca to more targets, we'll have to add custom inalloca handling
6943 // in the various CC lowering callbacks.
6946 if (Args[i].isByVal || Args[i].isInAlloca) {
6947 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6948 Type *ElementTy = Ty->getElementType();
6949 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6950 // For ByVal, alignment should come from FE. BE will guess if this
6951 // info is not there but there are cases it cannot get right.
6952 unsigned FrameAlign;
6953 if (Args[i].Alignment)
6954 FrameAlign = Args[i].Alignment;
6956 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6957 Flags.setByValAlign(FrameAlign);
6962 Flags.setInConsecutiveRegs();
6963 Flags.setOrigAlign(OriginalAlignment);
6965 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6966 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6967 SmallVector<SDValue, 4> Parts(NumParts);
6968 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6971 ExtendKind = ISD::SIGN_EXTEND;
6972 else if (Args[i].isZExt)
6973 ExtendKind = ISD::ZERO_EXTEND;
6975 // Conservatively only handle 'returned' on non-vectors for now
6976 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6977 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6978 "unexpected use of 'returned'");
6979 // Before passing 'returned' to the target lowering code, ensure that
6980 // either the register MVT and the actual EVT are the same size or that
6981 // the return value and argument are extended in the same way; in these
6982 // cases it's safe to pass the argument register value unchanged as the
6983 // return register value (although it's at the target's option whether
6985 // TODO: allow code generation to take advantage of partially preserved
6986 // registers rather than clobbering the entire register when the
6987 // parameter extension method is not compatible with the return
6989 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6990 (ExtendKind != ISD::ANY_EXTEND &&
6991 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6992 Flags.setReturned();
6995 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6996 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6998 for (unsigned j = 0; j != NumParts; ++j) {
6999 // if it isn't first piece, alignment must be 1
7000 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7001 i < CLI.NumFixedArgs,
7002 i, j*Parts[j].getValueType().getStoreSize());
7003 if (NumParts > 1 && j == 0)
7004 MyFlags.Flags.setSplit();
7006 MyFlags.Flags.setOrigAlign(1);
7008 CLI.Outs.push_back(MyFlags);
7009 CLI.OutVals.push_back(Parts[j]);
7012 if (NeedsRegBlock && Value == NumValues - 1)
7013 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7017 SmallVector<SDValue, 4> InVals;
7018 CLI.Chain = LowerCall(CLI, InVals);
7020 // Verify that the target's LowerCall behaved as expected.
7021 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7022 "LowerCall didn't return a valid chain!");
7023 assert((!CLI.IsTailCall || InVals.empty()) &&
7024 "LowerCall emitted a return value for a tail call!");
7025 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7026 "LowerCall didn't emit the correct number of values!");
7028 // For a tail call, the return value is merely live-out and there aren't
7029 // any nodes in the DAG representing it. Return a special value to
7030 // indicate that a tail call has been emitted and no more Instructions
7031 // should be processed in the current block.
7032 if (CLI.IsTailCall) {
7033 CLI.DAG.setRoot(CLI.Chain);
7034 return std::make_pair(SDValue(), SDValue());
7037 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7038 assert(InVals[i].getNode() &&
7039 "LowerCall emitted a null value!");
7040 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7041 "LowerCall emitted a value with the wrong type!");
7044 SmallVector<SDValue, 4> ReturnValues;
7045 if (!CanLowerReturn) {
7046 // The instruction result is the result of loading from the
7047 // hidden sret parameter.
7048 SmallVector<EVT, 1> PVTs;
7049 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7051 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7052 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7053 EVT PtrVT = PVTs[0];
7055 unsigned NumValues = RetTys.size();
7056 ReturnValues.resize(NumValues);
7057 SmallVector<SDValue, 4> Chains(NumValues);
7059 for (unsigned i = 0; i < NumValues; ++i) {
7060 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7061 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7063 SDValue L = CLI.DAG.getLoad(
7064 RetTys[i], CLI.DL, CLI.Chain, Add,
7065 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7066 DemoteStackIdx, Offsets[i]),
7067 false, false, false, 1);
7068 ReturnValues[i] = L;
7069 Chains[i] = L.getValue(1);
7072 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7074 // Collect the legal value parts into potentially illegal values
7075 // that correspond to the original function's return values.
7076 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7078 AssertOp = ISD::AssertSext;
7079 else if (CLI.RetZExt)
7080 AssertOp = ISD::AssertZext;
7081 unsigned CurReg = 0;
7082 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7084 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7085 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7087 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7088 NumRegs, RegisterVT, VT, nullptr,
7093 // For a function returning void, there is no return value. We can't create
7094 // such a node, so we just return a null return value in that case. In
7095 // that case, nothing will actually look at the value.
7096 if (ReturnValues.empty())
7097 return std::make_pair(SDValue(), CLI.Chain);
7100 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7101 CLI.DAG.getVTList(RetTys), ReturnValues);
7102 return std::make_pair(Res, CLI.Chain);
7105 void TargetLowering::LowerOperationWrapper(SDNode *N,
7106 SmallVectorImpl<SDValue> &Results,
7107 SelectionDAG &DAG) const {
7108 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7110 Results.push_back(Res);
7113 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7114 llvm_unreachable("LowerOperation not implemented for this target!");
7118 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7119 SDValue Op = getNonRegisterValue(V);
7120 assert((Op.getOpcode() != ISD::CopyFromReg ||
7121 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7122 "Copy from a reg to the same reg!");
7123 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7126 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7128 SDValue Chain = DAG.getEntryNode();
7130 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7131 FuncInfo.PreferredExtendType.end())
7133 : FuncInfo.PreferredExtendType[V];
7134 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7135 PendingExports.push_back(Chain);
7138 #include "llvm/CodeGen/SelectionDAGISel.h"
7140 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7141 /// entry block, return true. This includes arguments used by switches, since
7142 /// the switch may expand into multiple basic blocks.
7143 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7144 // With FastISel active, we may be splitting blocks, so force creation
7145 // of virtual registers for all non-dead arguments.
7147 return A->use_empty();
7149 const BasicBlock *Entry = A->getParent()->begin();
7150 for (const User *U : A->users())
7151 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7152 return false; // Use not in entry block.
7157 void SelectionDAGISel::LowerArguments(const Function &F) {
7158 SelectionDAG &DAG = SDB->DAG;
7159 SDLoc dl = SDB->getCurSDLoc();
7160 const DataLayout &DL = DAG.getDataLayout();
7161 SmallVector<ISD::InputArg, 16> Ins;
7163 if (!FuncInfo->CanLowerReturn) {
7164 // Put in an sret pointer parameter before all the other parameters.
7165 SmallVector<EVT, 1> ValueVTs;
7166 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7167 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7169 // NOTE: Assuming that a pointer will never break down to more than one VT
7171 ISD::ArgFlagsTy Flags;
7173 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7174 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7175 ISD::InputArg::NoArgIndex, 0);
7176 Ins.push_back(RetArg);
7179 // Set up the incoming argument description vector.
7181 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7182 I != E; ++I, ++Idx) {
7183 SmallVector<EVT, 4> ValueVTs;
7184 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7185 bool isArgValueUsed = !I->use_empty();
7186 unsigned PartBase = 0;
7187 Type *FinalType = I->getType();
7188 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7189 FinalType = cast<PointerType>(FinalType)->getElementType();
7190 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7191 FinalType, F.getCallingConv(), F.isVarArg());
7192 for (unsigned Value = 0, NumValues = ValueVTs.size();
7193 Value != NumValues; ++Value) {
7194 EVT VT = ValueVTs[Value];
7195 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7196 ISD::ArgFlagsTy Flags;
7197 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7199 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7201 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7203 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7205 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7207 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7209 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7210 Flags.setInAlloca();
7211 // Set the byval flag for CCAssignFn callbacks that don't know about
7212 // inalloca. This way we can know how many bytes we should've allocated
7213 // and how many bytes a callee cleanup function will pop. If we port
7214 // inalloca to more targets, we'll have to add custom inalloca handling
7215 // in the various CC lowering callbacks.
7218 if (Flags.isByVal() || Flags.isInAlloca()) {
7219 PointerType *Ty = cast<PointerType>(I->getType());
7220 Type *ElementTy = Ty->getElementType();
7221 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7222 // For ByVal, alignment should be passed from FE. BE will guess if
7223 // this info is not there but there are cases it cannot get right.
7224 unsigned FrameAlign;
7225 if (F.getParamAlignment(Idx))
7226 FrameAlign = F.getParamAlignment(Idx);
7228 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7229 Flags.setByValAlign(FrameAlign);
7231 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7234 Flags.setInConsecutiveRegs();
7235 Flags.setOrigAlign(OriginalAlignment);
7237 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7238 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7239 for (unsigned i = 0; i != NumRegs; ++i) {
7240 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7241 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7242 if (NumRegs > 1 && i == 0)
7243 MyFlags.Flags.setSplit();
7244 // if it isn't first piece, alignment must be 1
7246 MyFlags.Flags.setOrigAlign(1);
7247 Ins.push_back(MyFlags);
7249 if (NeedsRegBlock && Value == NumValues - 1)
7250 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7251 PartBase += VT.getStoreSize();
7255 // Call the target to set up the argument values.
7256 SmallVector<SDValue, 8> InVals;
7257 SDValue NewRoot = TLI->LowerFormalArguments(
7258 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7260 // Verify that the target's LowerFormalArguments behaved as expected.
7261 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7262 "LowerFormalArguments didn't return a valid chain!");
7263 assert(InVals.size() == Ins.size() &&
7264 "LowerFormalArguments didn't emit the correct number of values!");
7266 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7267 assert(InVals[i].getNode() &&
7268 "LowerFormalArguments emitted a null value!");
7269 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7270 "LowerFormalArguments emitted a value with the wrong type!");
7274 // Update the DAG with the new chain value resulting from argument lowering.
7275 DAG.setRoot(NewRoot);
7277 // Set up the argument values.
7280 if (!FuncInfo->CanLowerReturn) {
7281 // Create a virtual register for the sret pointer, and put in a copy
7282 // from the sret argument into it.
7283 SmallVector<EVT, 1> ValueVTs;
7284 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7285 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7286 MVT VT = ValueVTs[0].getSimpleVT();
7287 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7288 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7289 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7290 RegVT, VT, nullptr, AssertOp);
7292 MachineFunction& MF = SDB->DAG.getMachineFunction();
7293 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7294 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7295 FuncInfo->DemoteRegister = SRetReg;
7297 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7298 DAG.setRoot(NewRoot);
7300 // i indexes lowered arguments. Bump it past the hidden sret argument.
7301 // Idx indexes LLVM arguments. Don't touch it.
7305 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7307 SmallVector<SDValue, 4> ArgValues;
7308 SmallVector<EVT, 4> ValueVTs;
7309 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7310 unsigned NumValues = ValueVTs.size();
7312 // If this argument is unused then remember its value. It is used to generate
7313 // debugging information.
7314 if (I->use_empty() && NumValues) {
7315 SDB->setUnusedArgValue(I, InVals[i]);
7317 // Also remember any frame index for use in FastISel.
7318 if (FrameIndexSDNode *FI =
7319 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7320 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7323 for (unsigned Val = 0; Val != NumValues; ++Val) {
7324 EVT VT = ValueVTs[Val];
7325 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7326 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7328 if (!I->use_empty()) {
7329 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7330 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7331 AssertOp = ISD::AssertSext;
7332 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7333 AssertOp = ISD::AssertZext;
7335 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7336 NumParts, PartVT, VT,
7337 nullptr, AssertOp));
7343 // We don't need to do anything else for unused arguments.
7344 if (ArgValues.empty())
7347 // Note down frame index.
7348 if (FrameIndexSDNode *FI =
7349 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7350 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7352 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7353 SDB->getCurSDLoc());
7355 SDB->setValue(I, Res);
7356 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7357 if (LoadSDNode *LNode =
7358 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7359 if (FrameIndexSDNode *FI =
7360 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7361 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7364 // If this argument is live outside of the entry block, insert a copy from
7365 // wherever we got it to the vreg that other BB's will reference it as.
7366 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7367 // If we can, though, try to skip creating an unnecessary vreg.
7368 // FIXME: This isn't very clean... it would be nice to make this more
7369 // general. It's also subtly incompatible with the hacks FastISel
7371 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7372 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7373 FuncInfo->ValueMap[I] = Reg;
7377 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7378 FuncInfo->InitializeRegForValue(I);
7379 SDB->CopyToExportRegsIfNeeded(I);
7383 assert(i == InVals.size() && "Argument register count mismatch!");
7385 // Finally, if the target has anything special to do, allow it to do so.
7386 EmitFunctionEntryCode();
7389 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7390 /// ensure constants are generated when needed. Remember the virtual registers
7391 /// that need to be added to the Machine PHI nodes as input. We cannot just
7392 /// directly add them, because expansion might result in multiple MBB's for one
7393 /// BB. As such, the start of the BB might correspond to a different MBB than
7397 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7398 const TerminatorInst *TI = LLVMBB->getTerminator();
7400 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7402 // Check PHI nodes in successors that expect a value to be available from this
7404 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7405 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7406 if (!isa<PHINode>(SuccBB->begin())) continue;
7407 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7409 // If this terminator has multiple identical successors (common for
7410 // switches), only handle each succ once.
7411 if (!SuccsHandled.insert(SuccMBB).second)
7414 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7416 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7417 // nodes and Machine PHI nodes, but the incoming operands have not been
7419 for (BasicBlock::const_iterator I = SuccBB->begin();
7420 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7421 // Ignore dead phi's.
7422 if (PN->use_empty()) continue;
7425 if (PN->getType()->isEmptyTy())
7429 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7431 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7432 unsigned &RegOut = ConstantsOut[C];
7434 RegOut = FuncInfo.CreateRegs(C->getType());
7435 CopyValueToVirtualRegister(C, RegOut);
7439 DenseMap<const Value *, unsigned>::iterator I =
7440 FuncInfo.ValueMap.find(PHIOp);
7441 if (I != FuncInfo.ValueMap.end())
7444 assert(isa<AllocaInst>(PHIOp) &&
7445 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7446 "Didn't codegen value into a register!??");
7447 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7448 CopyValueToVirtualRegister(PHIOp, Reg);
7452 // Remember that this register needs to added to the machine PHI node as
7453 // the input for this MBB.
7454 SmallVector<EVT, 4> ValueVTs;
7455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7456 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7457 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7458 EVT VT = ValueVTs[vti];
7459 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7460 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7461 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7462 Reg += NumRegisters;
7467 ConstantsOut.clear();
7470 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7473 SelectionDAGBuilder::StackProtectorDescriptor::
7474 AddSuccessorMBB(const BasicBlock *BB,
7475 MachineBasicBlock *ParentMBB,
7477 MachineBasicBlock *SuccMBB) {
7478 // If SuccBB has not been created yet, create it.
7480 MachineFunction *MF = ParentMBB->getParent();
7481 MachineFunction::iterator BBI = ParentMBB;
7482 SuccMBB = MF->CreateMachineBasicBlock(BB);
7483 MF->insert(++BBI, SuccMBB);
7485 // Add it as a successor of ParentMBB.
7486 ParentMBB->addSuccessor(
7487 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7491 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7492 MachineFunction::iterator I = MBB;
7493 if (++I == FuncInfo.MF->end())
7498 /// During lowering new call nodes can be created (such as memset, etc.).
7499 /// Those will become new roots of the current DAG, but complications arise
7500 /// when they are tail calls. In such cases, the call lowering will update
7501 /// the root, but the builder still needs to know that a tail call has been
7502 /// lowered in order to avoid generating an additional return.
7503 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7504 // If the node is null, we do have a tail call.
7505 if (MaybeTC.getNode() != nullptr)
7506 DAG.setRoot(MaybeTC);
7511 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7512 unsigned *TotalCases, unsigned First,
7514 assert(Last >= First);
7515 assert(TotalCases[Last] >= TotalCases[First]);
7517 APInt LowCase = Clusters[First].Low->getValue();
7518 APInt HighCase = Clusters[Last].High->getValue();
7519 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7521 // FIXME: A range of consecutive cases has 100% density, but only requires one
7522 // comparison to lower. We should discriminate against such consecutive ranges
7525 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7526 uint64_t Range = Diff + 1;
7529 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7531 assert(NumCases < UINT64_MAX / 100);
7532 assert(Range >= NumCases);
7534 return NumCases * 100 >= Range * MinJumpTableDensity;
7537 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7538 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7539 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7542 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7543 unsigned First, unsigned Last,
7544 const SwitchInst *SI,
7545 MachineBasicBlock *DefaultMBB,
7546 CaseCluster &JTCluster) {
7547 assert(First <= Last);
7549 uint32_t Weight = 0;
7550 unsigned NumCmps = 0;
7551 std::vector<MachineBasicBlock*> Table;
7552 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7553 for (unsigned I = First; I <= Last; ++I) {
7554 assert(Clusters[I].Kind == CC_Range);
7555 Weight += Clusters[I].Weight;
7556 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7557 APInt Low = Clusters[I].Low->getValue();
7558 APInt High = Clusters[I].High->getValue();
7559 NumCmps += (Low == High) ? 1 : 2;
7561 // Fill the gap between this and the previous cluster.
7562 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7563 assert(PreviousHigh.slt(Low));
7564 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7565 for (uint64_t J = 0; J < Gap; J++)
7566 Table.push_back(DefaultMBB);
7568 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7569 for (uint64_t J = 0; J < ClusterSize; ++J)
7570 Table.push_back(Clusters[I].MBB);
7571 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7574 unsigned NumDests = JTWeights.size();
7575 if (isSuitableForBitTests(NumDests, NumCmps,
7576 Clusters[First].Low->getValue(),
7577 Clusters[Last].High->getValue())) {
7578 // Clusters[First..Last] should be lowered as bit tests instead.
7582 // Create the MBB that will load from and jump through the table.
7583 // Note: We create it here, but it's not inserted into the function yet.
7584 MachineFunction *CurMF = FuncInfo.MF;
7585 MachineBasicBlock *JumpTableMBB =
7586 CurMF->CreateMachineBasicBlock(SI->getParent());
7588 // Add successors. Note: use table order for determinism.
7589 SmallPtrSet<MachineBasicBlock *, 8> Done;
7590 for (MachineBasicBlock *Succ : Table) {
7591 if (Done.count(Succ))
7593 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7598 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7599 ->createJumpTableIndex(Table);
7601 // Set up the jump table info.
7602 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7603 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7604 Clusters[Last].High->getValue(), SI->getCondition(),
7606 JTCases.emplace_back(std::move(JTH), std::move(JT));
7608 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7609 JTCases.size() - 1, Weight);
7613 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7614 const SwitchInst *SI,
7615 MachineBasicBlock *DefaultMBB) {
7617 // Clusters must be non-empty, sorted, and only contain Range clusters.
7618 assert(!Clusters.empty());
7619 for (CaseCluster &C : Clusters)
7620 assert(C.Kind == CC_Range);
7621 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7622 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7626 if (!areJTsAllowed(TLI))
7629 const int64_t N = Clusters.size();
7630 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7632 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7633 SmallVector<unsigned, 8> TotalCases(N);
7635 for (unsigned i = 0; i < N; ++i) {
7636 APInt Hi = Clusters[i].High->getValue();
7637 APInt Lo = Clusters[i].Low->getValue();
7638 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7640 TotalCases[i] += TotalCases[i - 1];
7643 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7644 // Cheap case: the whole range might be suitable for jump table.
7645 CaseCluster JTCluster;
7646 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7647 Clusters[0] = JTCluster;
7653 // The algorithm below is not suitable for -O0.
7654 if (TM.getOptLevel() == CodeGenOpt::None)
7657 // Split Clusters into minimum number of dense partitions. The algorithm uses
7658 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7659 // for the Case Statement'" (1994), but builds the MinPartitions array in
7660 // reverse order to make it easier to reconstruct the partitions in ascending
7661 // order. In the choice between two optimal partitionings, it picks the one
7662 // which yields more jump tables.
7664 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7665 SmallVector<unsigned, 8> MinPartitions(N);
7666 // LastElement[i] is the last element of the partition starting at i.
7667 SmallVector<unsigned, 8> LastElement(N);
7668 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7669 SmallVector<unsigned, 8> NumTables(N);
7671 // Base case: There is only one way to partition Clusters[N-1].
7672 MinPartitions[N - 1] = 1;
7673 LastElement[N - 1] = N - 1;
7674 assert(MinJumpTableSize > 1);
7675 NumTables[N - 1] = 0;
7677 // Note: loop indexes are signed to avoid underflow.
7678 for (int64_t i = N - 2; i >= 0; i--) {
7679 // Find optimal partitioning of Clusters[i..N-1].
7680 // Baseline: Put Clusters[i] into a partition on its own.
7681 MinPartitions[i] = MinPartitions[i + 1] + 1;
7683 NumTables[i] = NumTables[i + 1];
7685 // Search for a solution that results in fewer partitions.
7686 for (int64_t j = N - 1; j > i; j--) {
7687 // Try building a partition from Clusters[i..j].
7688 if (isDense(Clusters, &TotalCases[0], i, j)) {
7689 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7690 bool IsTable = j - i + 1 >= MinJumpTableSize;
7691 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7693 // If this j leads to fewer partitions, or same number of partitions
7694 // with more lookup tables, it is a better partitioning.
7695 if (NumPartitions < MinPartitions[i] ||
7696 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7697 MinPartitions[i] = NumPartitions;
7699 NumTables[i] = Tables;
7705 // Iterate over the partitions, replacing some with jump tables in-place.
7706 unsigned DstIndex = 0;
7707 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7708 Last = LastElement[First];
7709 assert(Last >= First);
7710 assert(DstIndex <= First);
7711 unsigned NumClusters = Last - First + 1;
7713 CaseCluster JTCluster;
7714 if (NumClusters >= MinJumpTableSize &&
7715 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7716 Clusters[DstIndex++] = JTCluster;
7718 for (unsigned I = First; I <= Last; ++I)
7719 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7722 Clusters.resize(DstIndex);
7725 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7726 // FIXME: Using the pointer type doesn't seem ideal.
7727 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7728 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7732 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7735 const APInt &High) {
7736 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7737 // range of cases both require only one branch to lower. Just looking at the
7738 // number of clusters and destinations should be enough to decide whether to
7741 // To lower a range with bit tests, the range must fit the bitwidth of a
7743 if (!rangeFitsInWord(Low, High))
7746 // Decide whether it's profitable to lower this range with bit tests. Each
7747 // destination requires a bit test and branch, and there is an overall range
7748 // check branch. For a small number of clusters, separate comparisons might be
7749 // cheaper, and for many destinations, splitting the range might be better.
7750 return (NumDests == 1 && NumCmps >= 3) ||
7751 (NumDests == 2 && NumCmps >= 5) ||
7752 (NumDests == 3 && NumCmps >= 6);
7755 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7756 unsigned First, unsigned Last,
7757 const SwitchInst *SI,
7758 CaseCluster &BTCluster) {
7759 assert(First <= Last);
7763 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7764 unsigned NumCmps = 0;
7765 for (int64_t I = First; I <= Last; ++I) {
7766 assert(Clusters[I].Kind == CC_Range);
7767 Dests.set(Clusters[I].MBB->getNumber());
7768 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7770 unsigned NumDests = Dests.count();
7772 APInt Low = Clusters[First].Low->getValue();
7773 APInt High = Clusters[Last].High->getValue();
7774 assert(Low.slt(High));
7776 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7782 const int BitWidth = DAG.getTargetLoweringInfo()
7783 .getPointerTy(DAG.getDataLayout())
7785 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7787 // Check if the clusters cover a contiguous range such that no value in the
7788 // range will jump to the default statement.
7789 bool ContiguousRange = true;
7790 for (int64_t I = First + 1; I <= Last; ++I) {
7791 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7792 ContiguousRange = false;
7797 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7798 // Optimize the case where all the case values fit in a word without having
7799 // to subtract minValue. In this case, we can optimize away the subtraction.
7800 LowBound = APInt::getNullValue(Low.getBitWidth());
7802 ContiguousRange = false;
7805 CmpRange = High - Low;
7809 uint32_t TotalWeight = 0;
7810 for (unsigned i = First; i <= Last; ++i) {
7811 // Find the CaseBits for this destination.
7813 for (j = 0; j < CBV.size(); ++j)
7814 if (CBV[j].BB == Clusters[i].MBB)
7816 if (j == CBV.size())
7817 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7818 CaseBits *CB = &CBV[j];
7820 // Update Mask, Bits and ExtraWeight.
7821 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7822 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7823 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7824 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7825 CB->Bits += Hi - Lo + 1;
7826 CB->ExtraWeight += Clusters[i].Weight;
7827 TotalWeight += Clusters[i].Weight;
7828 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7832 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7833 // Sort by weight first, number of bits second.
7834 if (a.ExtraWeight != b.ExtraWeight)
7835 return a.ExtraWeight > b.ExtraWeight;
7836 return a.Bits > b.Bits;
7839 for (auto &CB : CBV) {
7840 MachineBasicBlock *BitTestBB =
7841 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7842 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7844 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7845 SI->getCondition(), -1U, MVT::Other, false,
7846 ContiguousRange, nullptr, nullptr, std::move(BTI),
7849 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7850 BitTestCases.size() - 1, TotalWeight);
7854 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7855 const SwitchInst *SI) {
7856 // Partition Clusters into as few subsets as possible, where each subset has a
7857 // range that fits in a machine word and has <= 3 unique destinations.
7860 // Clusters must be sorted and contain Range or JumpTable clusters.
7861 assert(!Clusters.empty());
7862 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7863 for (const CaseCluster &C : Clusters)
7864 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7865 for (unsigned i = 1; i < Clusters.size(); ++i)
7866 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7869 // The algorithm below is not suitable for -O0.
7870 if (TM.getOptLevel() == CodeGenOpt::None)
7873 // If target does not have legal shift left, do not emit bit tests at all.
7874 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7875 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7876 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7879 int BitWidth = PTy.getSizeInBits();
7880 const int64_t N = Clusters.size();
7882 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7883 SmallVector<unsigned, 8> MinPartitions(N);
7884 // LastElement[i] is the last element of the partition starting at i.
7885 SmallVector<unsigned, 8> LastElement(N);
7887 // FIXME: This might not be the best algorithm for finding bit test clusters.
7889 // Base case: There is only one way to partition Clusters[N-1].
7890 MinPartitions[N - 1] = 1;
7891 LastElement[N - 1] = N - 1;
7893 // Note: loop indexes are signed to avoid underflow.
7894 for (int64_t i = N - 2; i >= 0; --i) {
7895 // Find optimal partitioning of Clusters[i..N-1].
7896 // Baseline: Put Clusters[i] into a partition on its own.
7897 MinPartitions[i] = MinPartitions[i + 1] + 1;
7900 // Search for a solution that results in fewer partitions.
7901 // Note: the search is limited by BitWidth, reducing time complexity.
7902 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7903 // Try building a partition from Clusters[i..j].
7906 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7907 Clusters[j].High->getValue()))
7910 // Check nbr of destinations and cluster types.
7911 // FIXME: This works, but doesn't seem very efficient.
7912 bool RangesOnly = true;
7913 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7914 for (int64_t k = i; k <= j; k++) {
7915 if (Clusters[k].Kind != CC_Range) {
7919 Dests.set(Clusters[k].MBB->getNumber());
7921 if (!RangesOnly || Dests.count() > 3)
7924 // Check if it's a better partition.
7925 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7926 if (NumPartitions < MinPartitions[i]) {
7927 // Found a better partition.
7928 MinPartitions[i] = NumPartitions;
7934 // Iterate over the partitions, replacing with bit-test clusters in-place.
7935 unsigned DstIndex = 0;
7936 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7937 Last = LastElement[First];
7938 assert(First <= Last);
7939 assert(DstIndex <= First);
7941 CaseCluster BitTestCluster;
7942 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7943 Clusters[DstIndex++] = BitTestCluster;
7945 size_t NumClusters = Last - First + 1;
7946 std::memmove(&Clusters[DstIndex], &Clusters[First],
7947 sizeof(Clusters[0]) * NumClusters);
7948 DstIndex += NumClusters;
7951 Clusters.resize(DstIndex);
7954 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7955 MachineBasicBlock *SwitchMBB,
7956 MachineBasicBlock *DefaultMBB) {
7957 MachineFunction *CurMF = FuncInfo.MF;
7958 MachineBasicBlock *NextMBB = nullptr;
7959 MachineFunction::iterator BBI = W.MBB;
7960 if (++BBI != FuncInfo.MF->end())
7963 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7965 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7967 if (Size == 2 && W.MBB == SwitchMBB) {
7968 // If any two of the cases has the same destination, and if one value
7969 // is the same as the other, but has one bit unset that the other has set,
7970 // use bit manipulation to do two compares at once. For example:
7971 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7972 // TODO: This could be extended to merge any 2 cases in switches with 3
7974 // TODO: Handle cases where W.CaseBB != SwitchBB.
7975 CaseCluster &Small = *W.FirstCluster;
7976 CaseCluster &Big = *W.LastCluster;
7978 if (Small.Low == Small.High && Big.Low == Big.High &&
7979 Small.MBB == Big.MBB) {
7980 const APInt &SmallValue = Small.Low->getValue();
7981 const APInt &BigValue = Big.Low->getValue();
7983 // Check that there is only one bit different.
7984 APInt CommonBit = BigValue ^ SmallValue;
7985 if (CommonBit.isPowerOf2()) {
7986 SDValue CondLHS = getValue(Cond);
7987 EVT VT = CondLHS.getValueType();
7988 SDLoc DL = getCurSDLoc();
7990 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7991 DAG.getConstant(CommonBit, DL, VT));
7992 SDValue Cond = DAG.getSetCC(
7993 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7996 // Update successor info.
7997 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7998 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7999 addSuccessorWithWeight(
8000 SwitchMBB, DefaultMBB,
8001 // The default destination is the first successor in IR.
8002 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8005 // Insert the true branch.
8007 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8008 DAG.getBasicBlock(Small.MBB));
8009 // Insert the false branch.
8010 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8011 DAG.getBasicBlock(DefaultMBB));
8013 DAG.setRoot(BrCond);
8019 if (TM.getOptLevel() != CodeGenOpt::None) {
8020 // Order cases by weight so the most likely case will be checked first.
8021 std::sort(W.FirstCluster, W.LastCluster + 1,
8022 [](const CaseCluster &a, const CaseCluster &b) {
8023 return a.Weight > b.Weight;
8026 // Rearrange the case blocks so that the last one falls through if possible
8027 // without without changing the order of weights.
8028 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8030 if (I->Weight > W.LastCluster->Weight)
8032 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8033 std::swap(*I, *W.LastCluster);
8039 // Compute total weight.
8040 uint32_t UnhandledWeights = 0;
8041 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8042 UnhandledWeights += I->Weight;
8043 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8046 MachineBasicBlock *CurMBB = W.MBB;
8047 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8048 MachineBasicBlock *Fallthrough;
8049 if (I == W.LastCluster) {
8050 // For the last cluster, fall through to the default destination.
8051 Fallthrough = DefaultMBB;
8053 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8054 CurMF->insert(BBI, Fallthrough);
8055 // Put Cond in a virtual register to make it available from the new blocks.
8056 ExportFromCurrentBlock(Cond);
8058 UnhandledWeights -= I->Weight;
8061 case CC_JumpTable: {
8062 // FIXME: Optimize away range check based on pivot comparisons.
8063 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8064 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8066 // The jump block hasn't been inserted yet; insert it here.
8067 MachineBasicBlock *JumpMBB = JT->MBB;
8068 CurMF->insert(BBI, JumpMBB);
8070 // Collect the sum of weights of outgoing edges from JumpMBB, which will
8071 // be the edge weight on CurMBB->JumpMBB.
8072 uint32_t JumpWeight = 0;
8073 for (auto Succ : JumpMBB->successors())
8074 JumpWeight += getEdgeWeight(JumpMBB, Succ);
8075 uint32_t FallthruWeight = getEdgeWeight(CurMBB, Fallthrough);
8077 addSuccessorWithWeight(CurMBB, Fallthrough, FallthruWeight);
8078 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8080 // The jump table header will be inserted in our current block, do the
8081 // range check, and fall through to our fallthrough block.
8082 JTH->HeaderBB = CurMBB;
8083 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8085 // If we're in the right place, emit the jump table header right now.
8086 if (CurMBB == SwitchMBB) {
8087 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8088 JTH->Emitted = true;
8093 // FIXME: Optimize away range check based on pivot comparisons.
8094 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8096 // The bit test blocks haven't been inserted yet; insert them here.
8097 for (BitTestCase &BTC : BTB->Cases)
8098 CurMF->insert(BBI, BTC.ThisBB);
8100 // Fill in fields of the BitTestBlock.
8101 BTB->Parent = CurMBB;
8102 BTB->Default = Fallthrough;
8104 // If we're in the right place, emit the bit test header header right now.
8105 if (CurMBB ==SwitchMBB) {
8106 visitBitTestHeader(*BTB, SwitchMBB);
8107 BTB->Emitted = true;
8112 const Value *RHS, *LHS, *MHS;
8114 if (I->Low == I->High) {
8115 // Check Cond == I->Low.
8121 // Check I->Low <= Cond <= I->High.
8128 // The false weight is the sum of all unhandled cases.
8129 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8132 if (CurMBB == SwitchMBB)
8133 visitSwitchCase(CB, SwitchMBB);
8135 SwitchCases.push_back(CB);
8140 CurMBB = Fallthrough;
8144 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8145 CaseClusterIt First,
8146 CaseClusterIt Last) {
8147 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8148 if (X.Weight != CC.Weight)
8149 return X.Weight > CC.Weight;
8151 // Ties are broken by comparing the case value.
8152 return X.Low->getValue().slt(CC.Low->getValue());
8156 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8157 const SwitchWorkListItem &W,
8159 MachineBasicBlock *SwitchMBB) {
8160 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8161 "Clusters not sorted?");
8163 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8165 // Balance the tree based on branch weights to create a near-optimal (in terms
8166 // of search time given key frequency) binary search tree. See e.g. Kurt
8167 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8168 CaseClusterIt LastLeft = W.FirstCluster;
8169 CaseClusterIt FirstRight = W.LastCluster;
8170 uint32_t LeftWeight = LastLeft->Weight;
8171 uint32_t RightWeight = FirstRight->Weight;
8173 // Move LastLeft and FirstRight towards each other from opposite directions to
8174 // find a partitioning of the clusters which balances the weight on both
8175 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8176 // taken to ensure 0-weight nodes are distributed evenly.
8178 while (LastLeft + 1 < FirstRight) {
8179 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8180 LeftWeight += (++LastLeft)->Weight;
8182 RightWeight += (--FirstRight)->Weight;
8187 // Our binary search tree differs from a typical BST in that ours can have up
8188 // to three values in each leaf. The pivot selection above doesn't take that
8189 // into account, which means the tree might require more nodes and be less
8190 // efficient. We compensate for this here.
8192 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8193 unsigned NumRight = W.LastCluster - FirstRight + 1;
8195 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8196 // If one side has less than 3 clusters, and the other has more than 3,
8197 // consider taking a cluster from the other side.
8199 if (NumLeft < NumRight) {
8200 // Consider moving the first cluster on the right to the left side.
8201 CaseCluster &CC = *FirstRight;
8202 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8203 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8204 if (LeftSideRank <= RightSideRank) {
8205 // Moving the cluster to the left does not demote it.
8211 assert(NumRight < NumLeft);
8212 // Consider moving the last element on the left to the right side.
8213 CaseCluster &CC = *LastLeft;
8214 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8215 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8216 if (RightSideRank <= LeftSideRank) {
8217 // Moving the cluster to the right does not demot it.
8227 assert(LastLeft + 1 == FirstRight);
8228 assert(LastLeft >= W.FirstCluster);
8229 assert(FirstRight <= W.LastCluster);
8231 // Use the first element on the right as pivot since we will make less-than
8232 // comparisons against it.
8233 CaseClusterIt PivotCluster = FirstRight;
8234 assert(PivotCluster > W.FirstCluster);
8235 assert(PivotCluster <= W.LastCluster);
8237 CaseClusterIt FirstLeft = W.FirstCluster;
8238 CaseClusterIt LastRight = W.LastCluster;
8240 const ConstantInt *Pivot = PivotCluster->Low;
8242 // New blocks will be inserted immediately after the current one.
8243 MachineFunction::iterator BBI = W.MBB;
8246 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8247 // we can branch to its destination directly if it's squeezed exactly in
8248 // between the known lower bound and Pivot - 1.
8249 MachineBasicBlock *LeftMBB;
8250 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8251 FirstLeft->Low == W.GE &&
8252 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8253 LeftMBB = FirstLeft->MBB;
8255 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8256 FuncInfo.MF->insert(BBI, LeftMBB);
8257 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8258 // Put Cond in a virtual register to make it available from the new blocks.
8259 ExportFromCurrentBlock(Cond);
8262 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8263 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8264 // directly if RHS.High equals the current upper bound.
8265 MachineBasicBlock *RightMBB;
8266 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8267 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8268 RightMBB = FirstRight->MBB;
8270 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8271 FuncInfo.MF->insert(BBI, RightMBB);
8272 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8273 // Put Cond in a virtual register to make it available from the new blocks.
8274 ExportFromCurrentBlock(Cond);
8277 // Create the CaseBlock record that will be used to lower the branch.
8278 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8279 LeftWeight, RightWeight);
8281 if (W.MBB == SwitchMBB)
8282 visitSwitchCase(CB, SwitchMBB);
8284 SwitchCases.push_back(CB);
8287 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8288 // Extract cases from the switch.
8289 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8290 CaseClusterVector Clusters;
8291 Clusters.reserve(SI.getNumCases());
8292 for (auto I : SI.cases()) {
8293 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8294 const ConstantInt *CaseVal = I.getCaseValue();
8296 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8297 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8300 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8302 // Cluster adjacent cases with the same destination. We do this at all
8303 // optimization levels because it's cheap to do and will make codegen faster
8304 // if there are many clusters.
8305 sortAndRangeify(Clusters);
8307 if (TM.getOptLevel() != CodeGenOpt::None) {
8308 // Replace an unreachable default with the most popular destination.
8309 // FIXME: Exploit unreachable default more aggressively.
8310 bool UnreachableDefault =
8311 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8312 if (UnreachableDefault && !Clusters.empty()) {
8313 DenseMap<const BasicBlock *, unsigned> Popularity;
8314 unsigned MaxPop = 0;
8315 const BasicBlock *MaxBB = nullptr;
8316 for (auto I : SI.cases()) {
8317 const BasicBlock *BB = I.getCaseSuccessor();
8318 if (++Popularity[BB] > MaxPop) {
8319 MaxPop = Popularity[BB];
8324 assert(MaxPop > 0 && MaxBB);
8325 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8327 // Remove cases that were pointing to the destination that is now the
8329 CaseClusterVector New;
8330 New.reserve(Clusters.size());
8331 for (CaseCluster &CC : Clusters) {
8332 if (CC.MBB != DefaultMBB)
8335 Clusters = std::move(New);
8339 // If there is only the default destination, jump there directly.
8340 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8341 if (Clusters.empty()) {
8342 SwitchMBB->addSuccessor(DefaultMBB);
8343 if (DefaultMBB != NextBlock(SwitchMBB)) {
8344 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8345 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8350 findJumpTables(Clusters, &SI, DefaultMBB);
8351 findBitTestClusters(Clusters, &SI);
8354 dbgs() << "Case clusters: ";
8355 for (const CaseCluster &C : Clusters) {
8356 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8357 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8359 C.Low->getValue().print(dbgs(), true);
8360 if (C.Low != C.High) {
8362 C.High->getValue().print(dbgs(), true);
8369 assert(!Clusters.empty());
8370 SwitchWorkList WorkList;
8371 CaseClusterIt First = Clusters.begin();
8372 CaseClusterIt Last = Clusters.end() - 1;
8373 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8375 while (!WorkList.empty()) {
8376 SwitchWorkListItem W = WorkList.back();
8377 WorkList.pop_back();
8378 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8380 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8381 // For optimized builds, lower large range as a balanced binary tree.
8382 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8386 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);