1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static cl::opt<unsigned>
88 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
89 cl::init(64), cl::Hidden);
91 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
92 const SDValue *Parts, unsigned NumParts,
93 EVT PartVT, EVT ValueVT);
95 /// getCopyFromParts - Create a value that contains the specified legal parts
96 /// combined into the value they represent. If the parts combine to a type
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
100 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
101 const SDValue *Parts,
102 unsigned NumParts, EVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
107 assert(NumParts > 0 && "No parts to assemble!");
108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
109 SDValue Val = Parts[0];
112 // Assemble the value from multiple parts.
113 if (ValueVT.isInteger()) {
114 unsigned PartBits = PartVT.getSizeInBits();
115 unsigned ValueBits = ValueVT.getSizeInBits();
117 // Assemble the power of 2 part.
118 unsigned RoundParts = NumParts & (NumParts - 1) ?
119 1 << Log2_32(NumParts) : NumParts;
120 unsigned RoundBits = PartBits * RoundParts;
121 EVT RoundVT = RoundBits == ValueBits ?
122 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
125 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
127 if (RoundParts > 2) {
128 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
130 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
131 RoundParts / 2, PartVT, HalfVT);
133 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
134 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
137 if (TLI.isBigEndian())
140 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
142 if (RoundParts < NumParts) {
143 // Assemble the trailing non-power-of-2 part.
144 unsigned OddParts = NumParts - RoundParts;
145 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
146 Hi = getCopyFromParts(DAG, DL,
147 Parts + RoundParts, OddParts, PartVT, OddVT);
149 // Combine the round and odd parts.
151 if (TLI.isBigEndian())
153 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
154 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
155 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
156 DAG.getConstant(Lo.getValueType().getSizeInBits(),
157 TLI.getPointerTy()));
158 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
159 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
161 } else if (PartVT.isFloatingPoint()) {
162 // FP split into multiple FP parts (for ppcf128)
163 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
166 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
167 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
168 if (TLI.isBigEndian())
170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
172 // FP split into integer parts (soft fp)
173 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
174 !PartVT.isVector() && "Unexpected split");
175 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
176 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
180 // There is now one part, held in Val. Correct it to match ValueVT.
181 PartVT = Val.getValueType();
183 if (PartVT == ValueVT)
186 if (PartVT.isInteger() && ValueVT.isInteger()) {
187 if (ValueVT.bitsLT(PartVT)) {
188 // For a truncate, see if we have any information to
189 // indicate whether the truncated bits will always be
190 // zero or sign-extension.
191 if (AssertOp != ISD::DELETED_NODE)
192 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
193 DAG.getValueType(ValueVT));
194 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
196 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
199 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
200 // FP_ROUND's are always exact here.
201 if (ValueVT.bitsLT(Val.getValueType()))
202 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
203 DAG.getIntPtrConstant(1));
205 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
208 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
209 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
211 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromParts - Create a value that contains the specified legal parts
216 /// combined into the value they represent. If the parts combine to a type
217 /// larger then ValueVT then AssertOp can be used to specify whether the extra
218 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
219 /// (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 EVT PartVT, EVT ValueVT) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
230 EVT IntermediateVT, RegisterVT;
231 unsigned NumIntermediates;
233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
234 NumIntermediates, RegisterVT);
235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
236 NumParts = NumRegs; // Silence a compiler warning.
237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
238 assert(RegisterVT == Parts[0].getValueType() &&
239 "Part type doesn't match part!");
241 // Assemble the parts into intermediate operands.
242 SmallVector<SDValue, 8> Ops(NumIntermediates);
243 if (NumIntermediates == NumParts) {
244 // If the register was not expanded, truncate or copy the value,
246 for (unsigned i = 0; i != NumParts; ++i)
247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
248 PartVT, IntermediateVT);
249 } else if (NumParts > 0) {
250 // If the intermediate type was expanded, build the intermediate
251 // operands from the parts.
252 assert(NumParts % NumIntermediates == 0 &&
253 "Must expand into a divisible number of parts!");
254 unsigned Factor = NumParts / NumIntermediates;
255 for (unsigned i = 0; i != NumIntermediates; ++i)
256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
257 PartVT, IntermediateVT);
260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
261 // intermediate operands.
262 Val = DAG.getNode(IntermediateVT.isVector() ?
263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
264 ValueVT, &Ops[0], NumIntermediates);
267 // There is now one part, held in Val. Correct it to match ValueVT.
268 PartVT = Val.getValueType();
270 if (PartVT == ValueVT)
273 if (PartVT.isVector()) {
274 // If the element type of the source/dest vectors are the same, but the
275 // parts vector has more elements than the value vector, then we have a
276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
280 "Cannot narrow, it would be a lossy transformation");
281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
282 DAG.getIntPtrConstant(0));
285 // Vector/Vector bitcast.
286 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
289 assert(ValueVT.getVectorElementType() == PartVT &&
290 ValueVT.getVectorNumElements() == 1 &&
291 "Only trivial scalar-to-vector conversions should get here!");
292 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
298 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
299 SDValue Val, SDValue *Parts, unsigned NumParts,
302 /// getCopyToParts - Create a series of nodes that contain the specified value
303 /// split into legal parts. If the parts contain more bits than Val, then, for
304 /// integers, ExtendKind can be used to specify how to generate the extra bits.
305 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
306 SDValue Val, SDValue *Parts, unsigned NumParts,
308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
309 EVT ValueVT = Val.getValueType();
311 // Handle the vector case separately.
312 if (ValueVT.isVector())
313 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
316 unsigned PartBits = PartVT.getSizeInBits();
317 unsigned OrigNumParts = NumParts;
318 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
323 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
324 if (PartVT == ValueVT) {
325 assert(NumParts == 1 && "No-op copy with multiple parts!");
330 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
331 // If the parts cover more bits than the value has, promote the value.
332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
333 assert(NumParts == 1 && "Do not know what to promote to!");
334 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
336 assert(PartVT.isInteger() && ValueVT.isInteger() &&
337 "Unknown mismatch!");
338 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
339 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
341 } else if (PartBits == ValueVT.getSizeInBits()) {
342 // Different types of the same size.
343 assert(NumParts == 1 && PartVT != ValueVT);
344 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
345 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
346 // If the parts cover less bits than value has, truncate the value.
347 assert(PartVT.isInteger() && ValueVT.isInteger() &&
348 "Unknown mismatch!");
349 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
353 // The value may have changed - recompute ValueVT.
354 ValueVT = Val.getValueType();
355 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
356 "Failed to tile the value with PartVT!");
359 assert(PartVT == ValueVT && "Type conversion failed!");
364 // Expand the value into multiple parts.
365 if (NumParts & (NumParts - 1)) {
366 // The number of parts is not a power of 2. Split off and copy the tail.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Do not know what to expand to!");
369 unsigned RoundParts = 1 << Log2_32(NumParts);
370 unsigned RoundBits = RoundParts * PartBits;
371 unsigned OddParts = NumParts - RoundParts;
372 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
373 DAG.getIntPtrConstant(RoundBits));
374 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
376 if (TLI.isBigEndian())
377 // The odd parts were reversed by getCopyToParts - unreverse them.
378 std::reverse(Parts + RoundParts, Parts + NumParts);
380 NumParts = RoundParts;
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
385 // The number of parts is a power of 2. Repeatedly bisect the value using
387 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
388 EVT::getIntegerVT(*DAG.getContext(),
389 ValueVT.getSizeInBits()),
392 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
393 for (unsigned i = 0; i < NumParts; i += StepSize) {
394 unsigned ThisBits = StepSize * PartBits / 2;
395 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
396 SDValue &Part0 = Parts[i];
397 SDValue &Part1 = Parts[i+StepSize/2];
399 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
400 ThisVT, Part0, DAG.getIntPtrConstant(1));
401 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
402 ThisVT, Part0, DAG.getIntPtrConstant(0));
404 if (ThisBits == PartBits && ThisVT != PartVT) {
405 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
406 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
411 if (TLI.isBigEndian())
412 std::reverse(Parts, Parts + OrigNumParts);
416 /// getCopyToPartsVector - Create a series of nodes that contain the specified
417 /// value split into legal parts.
418 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
419 SDValue Val, SDValue *Parts, unsigned NumParts,
421 EVT ValueVT = Val.getValueType();
422 assert(ValueVT.isVector() && "Not a vector");
423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
426 if (PartVT == ValueVT) {
428 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
429 // Bitconvert vector->vector case.
430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
431 } else if (PartVT.isVector() &&
432 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
433 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
434 EVT ElementVT = PartVT.getVectorElementType();
435 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
437 SmallVector<SDValue, 16> Ops;
438 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
439 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
440 ElementVT, Val, DAG.getIntPtrConstant(i)));
442 for (unsigned i = ValueVT.getVectorNumElements(),
443 e = PartVT.getVectorNumElements(); i != e; ++i)
444 Ops.push_back(DAG.getUNDEF(ElementVT));
446 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
448 // FIXME: Use CONCAT for 2x -> 4x.
450 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
451 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
453 // Vector -> scalar conversion.
454 assert(ValueVT.getVectorElementType() == PartVT &&
455 ValueVT.getVectorNumElements() == 1 &&
456 "Only trivial vector-to-scalar conversions should get here!");
457 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
458 PartVT, Val, DAG.getIntPtrConstant(0));
465 // Handle a multi-element vector.
466 EVT IntermediateVT, RegisterVT;
467 unsigned NumIntermediates;
468 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
470 NumIntermediates, RegisterVT);
471 unsigned NumElements = ValueVT.getVectorNumElements();
473 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
474 NumParts = NumRegs; // Silence a compiler warning.
475 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
477 // Split the vector into intermediate operands.
478 SmallVector<SDValue, 8> Ops(NumIntermediates);
479 for (unsigned i = 0; i != NumIntermediates; ++i) {
480 if (IntermediateVT.isVector())
481 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
483 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
485 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 IntermediateVT, Val, DAG.getIntPtrConstant(i));
489 // Split the intermediate operands into legal parts.
490 if (NumParts == NumIntermediates) {
491 // If the register was not expanded, promote or copy the value,
493 for (unsigned i = 0; i != NumParts; ++i)
494 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
495 } else if (NumParts > 0) {
496 // If the intermediate type was expanded, split each the value into
498 assert(NumParts % NumIntermediates == 0 &&
499 "Must expand into a divisible number of parts!");
500 unsigned Factor = NumParts / NumIntermediates;
501 for (unsigned i = 0; i != NumIntermediates; ++i)
502 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
510 /// RegsForValue - This struct represents the registers (physical or virtual)
511 /// that a particular set of values is assigned, and the type information
512 /// about the value. The most common situation is to represent one value at a
513 /// time, but struct or array values are handled element-wise as multiple
514 /// values. The splitting of aggregates is performed recursively, so that we
515 /// never have aggregate-typed registers. The values at this point do not
516 /// necessarily have legal types, so each value may require one or more
517 /// registers of some legal type.
519 struct RegsForValue {
520 /// ValueVTs - The value types of the values, which may not be legal, and
521 /// may need be promoted or synthesized from one or more registers.
523 SmallVector<EVT, 4> ValueVTs;
525 /// RegVTs - The value types of the registers. This is the same size as
526 /// ValueVTs and it records, for each value, what the type of the assigned
527 /// register or registers are. (Individual values are never synthesized
528 /// from more than one type of register.)
530 /// With virtual registers, the contents of RegVTs is redundant with TLI's
531 /// getRegisterType member function, however when with physical registers
532 /// it is necessary to have a separate record of the types.
534 SmallVector<EVT, 4> RegVTs;
536 /// Regs - This list holds the registers assigned to the values.
537 /// Each legal or promoted value requires one register, and each
538 /// expanded value requires multiple registers.
540 SmallVector<unsigned, 4> Regs;
544 RegsForValue(const SmallVector<unsigned, 4> ®s,
545 EVT regvt, EVT valuevt)
546 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
548 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
549 unsigned Reg, const Type *Ty) {
550 ComputeValueVTs(tli, Ty, ValueVTs);
552 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
553 EVT ValueVT = ValueVTs[Value];
554 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
555 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
556 for (unsigned i = 0; i != NumRegs; ++i)
557 Regs.push_back(Reg + i);
558 RegVTs.push_back(RegisterVT);
563 /// areValueTypesLegal - Return true if types of all the values are legal.
564 bool areValueTypesLegal(const TargetLowering &TLI) {
565 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
566 EVT RegisterVT = RegVTs[Value];
567 if (!TLI.isTypeLegal(RegisterVT))
573 /// append - Add the specified values to this one.
574 void append(const RegsForValue &RHS) {
575 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
576 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
577 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
580 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
581 /// this value and returns the result as a ValueVTs value. This uses
582 /// Chain/Flag as the input and updates them for the output Chain/Flag.
583 /// If the Flag pointer is NULL, no flag is used.
584 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
586 SDValue &Chain, SDValue *Flag) const;
588 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
589 /// specified value into the registers specified by this object. This uses
590 /// Chain/Flag as the input and updates them for the output Chain/Flag.
591 /// If the Flag pointer is NULL, no flag is used.
592 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
593 SDValue &Chain, SDValue *Flag) const;
595 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
596 /// operand list. This adds the code marker, matching input operand index
597 /// (if applicable), and includes the number of values added into it.
598 void AddInlineAsmOperands(unsigned Kind,
599 bool HasMatching, unsigned MatchingIdx,
601 std::vector<SDValue> &Ops) const;
605 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
606 /// this value and returns the result as a ValueVT value. This uses
607 /// Chain/Flag as the input and updates them for the output Chain/Flag.
608 /// If the Flag pointer is NULL, no flag is used.
609 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
610 FunctionLoweringInfo &FuncInfo,
612 SDValue &Chain, SDValue *Flag) const {
613 // A Value with type {} or [0 x %t] needs no registers.
614 if (ValueVTs.empty())
617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
619 // Assemble the legal parts into the final values.
620 SmallVector<SDValue, 4> Values(ValueVTs.size());
621 SmallVector<SDValue, 8> Parts;
622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 // Copy the legal parts from the registers.
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
626 EVT RegisterVT = RegVTs[Value];
628 Parts.resize(NumRegs);
629 for (unsigned i = 0; i != NumRegs; ++i) {
632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
635 *Flag = P.getValue(2);
638 Chain = P.getValue(1);
641 // If the source register was virtual and if we know something about it,
642 // add an assert node.
643 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
644 !RegisterVT.isInteger() || RegisterVT.isVector() ||
645 !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i]))
648 const FunctionLoweringInfo::LiveOutInfo &LOI =
649 FuncInfo.LiveOutRegInfo[Regs[Part+i]];
651 unsigned RegSize = RegisterVT.getSizeInBits();
652 unsigned NumSignBits = LOI.NumSignBits;
653 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
655 // FIXME: We capture more information than the dag can represent. For
656 // now, just use the tightest assertzext/assertsext possible.
658 EVT FromVT(MVT::Other);
659 if (NumSignBits == RegSize)
660 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
661 else if (NumZeroBits >= RegSize-1)
662 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
663 else if (NumSignBits > RegSize-8)
664 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
665 else if (NumZeroBits >= RegSize-8)
666 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
667 else if (NumSignBits > RegSize-16)
668 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
669 else if (NumZeroBits >= RegSize-16)
670 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
671 else if (NumSignBits > RegSize-32)
672 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
673 else if (NumZeroBits >= RegSize-32)
674 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
678 // Add an assertion node.
679 assert(FromVT != MVT::Other);
680 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
681 RegisterVT, P, DAG.getValueType(FromVT));
684 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
685 NumRegs, RegisterVT, ValueVT);
690 return DAG.getNode(ISD::MERGE_VALUES, dl,
691 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
692 &Values[0], ValueVTs.size());
695 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
696 /// specified value into the registers specified by this object. This uses
697 /// Chain/Flag as the input and updates them for the output Chain/Flag.
698 /// If the Flag pointer is NULL, no flag is used.
699 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
700 SDValue &Chain, SDValue *Flag) const {
701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
703 // Get the list of the values's legal parts.
704 unsigned NumRegs = Regs.size();
705 SmallVector<SDValue, 8> Parts(NumRegs);
706 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
707 EVT ValueVT = ValueVTs[Value];
708 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
709 EVT RegisterVT = RegVTs[Value];
711 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
712 &Parts[Part], NumParts, RegisterVT);
716 // Copy the parts into the registers.
717 SmallVector<SDValue, 8> Chains(NumRegs);
718 for (unsigned i = 0; i != NumRegs; ++i) {
721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
723 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
724 *Flag = Part.getValue(1);
727 Chains[i] = Part.getValue(0);
730 if (NumRegs == 1 || Flag)
731 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
732 // flagged to it. That is the CopyToReg nodes and the user are considered
733 // a single scheduling unit. If we create a TokenFactor and return it as
734 // chain, then the TokenFactor is both a predecessor (operand) of the
735 // user as well as a successor (the TF operands are flagged to the user).
736 // c1, f1 = CopyToReg
737 // c2, f2 = CopyToReg
738 // c3 = TokenFactor c1, c2
741 Chain = Chains[NumRegs-1];
743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
746 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
747 /// operand list. This adds the code marker and includes the number of
748 /// values added into it.
749 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
750 unsigned MatchingIdx,
752 std::vector<SDValue> &Ops) const {
753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
755 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
757 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
758 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
761 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
762 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
763 EVT RegisterVT = RegVTs[Value];
764 for (unsigned i = 0; i != NumRegs; ++i) {
765 assert(Reg < Regs.size() && "Mismatch in # registers expected");
766 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
771 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
774 TD = DAG.getTarget().getTargetData();
777 /// clear - Clear out the current SelectionDAG and the associated
778 /// state and prepare this SelectionDAGBuilder object to be used
779 /// for a new block. This doesn't clear out information about
780 /// additional blocks that are needed to complete switch lowering
781 /// or PHI node updating; that information is cleared out as it is
783 void SelectionDAGBuilder::clear() {
785 UnusedArgNodeMap.clear();
786 PendingLoads.clear();
787 PendingExports.clear();
788 DanglingDebugInfoMap.clear();
789 CurDebugLoc = DebugLoc();
793 /// getRoot - Return the current virtual root of the Selection DAG,
794 /// flushing any PendingLoad items. This must be done before emitting
795 /// a store or any other node that may need to be ordered after any
796 /// prior load instructions.
798 SDValue SelectionDAGBuilder::getRoot() {
799 if (PendingLoads.empty())
800 return DAG.getRoot();
802 if (PendingLoads.size() == 1) {
803 SDValue Root = PendingLoads[0];
805 PendingLoads.clear();
809 // Otherwise, we have to make a token factor node.
810 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
811 &PendingLoads[0], PendingLoads.size());
812 PendingLoads.clear();
817 /// getControlRoot - Similar to getRoot, but instead of flushing all the
818 /// PendingLoad items, flush all the PendingExports items. It is necessary
819 /// to do this before emitting a terminator instruction.
821 SDValue SelectionDAGBuilder::getControlRoot() {
822 SDValue Root = DAG.getRoot();
824 if (PendingExports.empty())
827 // Turn all of the CopyToReg chains into one factored node.
828 if (Root.getOpcode() != ISD::EntryToken) {
829 unsigned i = 0, e = PendingExports.size();
830 for (; i != e; ++i) {
831 assert(PendingExports[i].getNode()->getNumOperands() > 1);
832 if (PendingExports[i].getNode()->getOperand(0) == Root)
833 break; // Don't add the root if we already indirectly depend on it.
837 PendingExports.push_back(Root);
840 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
842 PendingExports.size());
843 PendingExports.clear();
848 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
849 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
850 DAG.AssignOrdering(Node, SDNodeOrder);
852 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
853 AssignOrderingToNode(Node->getOperand(I).getNode());
856 void SelectionDAGBuilder::visit(const Instruction &I) {
857 // Set up outgoing PHI node register values before emitting the terminator.
858 if (isa<TerminatorInst>(&I))
859 HandlePHINodesInSuccessorBlocks(I.getParent());
861 CurDebugLoc = I.getDebugLoc();
863 visit(I.getOpcode(), I);
865 if (!isa<TerminatorInst>(&I) && !HasTailCall)
866 CopyToExportRegsIfNeeded(&I);
868 CurDebugLoc = DebugLoc();
871 void SelectionDAGBuilder::visitPHI(const PHINode &) {
872 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
875 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
876 // Note: this doesn't use InstVisitor, because it has to work with
877 // ConstantExpr's in addition to instructions.
879 default: llvm_unreachable("Unknown instruction type encountered!");
880 // Build the switch statement using the Instruction.def file.
881 #define HANDLE_INST(NUM, OPCODE, CLASS) \
882 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
883 #include "llvm/Instruction.def"
886 // Assign the ordering to the freshly created DAG nodes.
887 if (NodeMap.count(&I)) {
889 AssignOrderingToNode(getValue(&I).getNode());
893 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
894 // generate the debug data structures now that we've seen its definition.
895 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
897 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
899 const DbgValueInst *DI = DDI.getDI();
900 DebugLoc dl = DDI.getdl();
901 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
902 MDNode *Variable = DI->getVariable();
903 uint64_t Offset = DI->getOffset();
906 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
907 SDV = DAG.getDbgValue(Variable, Val.getNode(),
908 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
909 DAG.AddDbgValue(SDV, Val.getNode(), false);
912 DEBUG(dbgs() << "Dropping debug info for " << DI);
913 DanglingDebugInfoMap[V] = DanglingDebugInfo();
917 // getValue - Return an SDValue for the given Value.
918 SDValue SelectionDAGBuilder::getValue(const Value *V) {
919 // If we already have an SDValue for this value, use it. It's important
920 // to do this first, so that we don't create a CopyFromReg if we already
921 // have a regular SDValue.
922 SDValue &N = NodeMap[V];
923 if (N.getNode()) return N;
925 // If there's a virtual register allocated and initialized for this
927 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
928 if (It != FuncInfo.ValueMap.end()) {
929 unsigned InReg = It->second;
930 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
931 SDValue Chain = DAG.getEntryNode();
932 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
933 resolveDanglingDebugInfo(V, N);
937 // Otherwise create a new SDValue and remember it.
938 SDValue Val = getValueImpl(V);
940 resolveDanglingDebugInfo(V, Val);
944 /// getNonRegisterValue - Return an SDValue for the given Value, but
945 /// don't look in FuncInfo.ValueMap for a virtual register.
946 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
947 // If we already have an SDValue for this value, use it.
948 SDValue &N = NodeMap[V];
949 if (N.getNode()) return N;
951 // Otherwise create a new SDValue and remember it.
952 SDValue Val = getValueImpl(V);
954 resolveDanglingDebugInfo(V, Val);
958 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
959 /// Create an SDValue for the given value.
960 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
961 if (const Constant *C = dyn_cast<Constant>(V)) {
962 EVT VT = TLI.getValueType(V->getType(), true);
964 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
965 return DAG.getConstant(*CI, VT);
967 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
968 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
970 if (isa<ConstantPointerNull>(C))
971 return DAG.getConstant(0, TLI.getPointerTy());
973 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
974 return DAG.getConstantFP(*CFP, VT);
976 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
977 return DAG.getUNDEF(VT);
979 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
980 visit(CE->getOpcode(), *CE);
981 SDValue N1 = NodeMap[V];
982 assert(N1.getNode() && "visit didn't populate the NodeMap!");
986 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
987 SmallVector<SDValue, 4> Constants;
988 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
990 SDNode *Val = getValue(*OI).getNode();
991 // If the operand is an empty aggregate, there are no values.
993 // Add each leaf value from the operand to the Constants list
994 // to form a flattened list of all the values.
995 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
996 Constants.push_back(SDValue(Val, i));
999 return DAG.getMergeValues(&Constants[0], Constants.size(),
1003 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1004 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1005 "Unknown struct or array constant!");
1007 SmallVector<EVT, 4> ValueVTs;
1008 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1009 unsigned NumElts = ValueVTs.size();
1011 return SDValue(); // empty struct
1012 SmallVector<SDValue, 4> Constants(NumElts);
1013 for (unsigned i = 0; i != NumElts; ++i) {
1014 EVT EltVT = ValueVTs[i];
1015 if (isa<UndefValue>(C))
1016 Constants[i] = DAG.getUNDEF(EltVT);
1017 else if (EltVT.isFloatingPoint())
1018 Constants[i] = DAG.getConstantFP(0, EltVT);
1020 Constants[i] = DAG.getConstant(0, EltVT);
1023 return DAG.getMergeValues(&Constants[0], NumElts,
1027 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1028 return DAG.getBlockAddress(BA, VT);
1030 const VectorType *VecTy = cast<VectorType>(V->getType());
1031 unsigned NumElements = VecTy->getNumElements();
1033 // Now that we know the number and type of the elements, get that number of
1034 // elements into the Ops array based on what kind of constant it is.
1035 SmallVector<SDValue, 16> Ops;
1036 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1037 for (unsigned i = 0; i != NumElements; ++i)
1038 Ops.push_back(getValue(CP->getOperand(i)));
1040 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1041 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1044 if (EltVT.isFloatingPoint())
1045 Op = DAG.getConstantFP(0, EltVT);
1047 Op = DAG.getConstant(0, EltVT);
1048 Ops.assign(NumElements, Op);
1051 // Create a BUILD_VECTOR node.
1052 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1053 VT, &Ops[0], Ops.size());
1056 // If this is a static alloca, generate it as the frameindex instead of
1058 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1059 DenseMap<const AllocaInst*, int>::iterator SI =
1060 FuncInfo.StaticAllocaMap.find(AI);
1061 if (SI != FuncInfo.StaticAllocaMap.end())
1062 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1065 // If this is an instruction which fast-isel has deferred, select it now.
1066 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1067 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1068 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1069 SDValue Chain = DAG.getEntryNode();
1070 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1073 llvm_unreachable("Can't get register for value!");
1077 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1078 SDValue Chain = getControlRoot();
1079 SmallVector<ISD::OutputArg, 8> Outs;
1080 SmallVector<SDValue, 8> OutVals;
1082 if (!FuncInfo.CanLowerReturn) {
1083 unsigned DemoteReg = FuncInfo.DemoteRegister;
1084 const Function *F = I.getParent()->getParent();
1086 // Emit a store of the return value through the virtual register.
1087 // Leave Outs empty so that LowerReturn won't try to load return
1088 // registers the usual way.
1089 SmallVector<EVT, 1> PtrValueVTs;
1090 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1093 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1094 SDValue RetOp = getValue(I.getOperand(0));
1096 SmallVector<EVT, 4> ValueVTs;
1097 SmallVector<uint64_t, 4> Offsets;
1098 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1099 unsigned NumValues = ValueVTs.size();
1101 SmallVector<SDValue, 4> Chains(NumValues);
1102 for (unsigned i = 0; i != NumValues; ++i) {
1103 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1104 RetPtr.getValueType(), RetPtr,
1105 DAG.getIntPtrConstant(Offsets[i]));
1107 DAG.getStore(Chain, getCurDebugLoc(),
1108 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1109 // FIXME: better loc info would be nice.
1110 Add, MachinePointerInfo(), false, false, 0);
1113 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1114 MVT::Other, &Chains[0], NumValues);
1115 } else if (I.getNumOperands() != 0) {
1116 SmallVector<EVT, 4> ValueVTs;
1117 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1118 unsigned NumValues = ValueVTs.size();
1120 SDValue RetOp = getValue(I.getOperand(0));
1121 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1122 EVT VT = ValueVTs[j];
1124 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1126 const Function *F = I.getParent()->getParent();
1127 if (F->paramHasAttr(0, Attribute::SExt))
1128 ExtendKind = ISD::SIGN_EXTEND;
1129 else if (F->paramHasAttr(0, Attribute::ZExt))
1130 ExtendKind = ISD::ZERO_EXTEND;
1132 // FIXME: C calling convention requires the return type to be promoted
1133 // to at least 32-bit. But this is not necessary for non-C calling
1134 // conventions. The frontend should mark functions whose return values
1135 // require promoting with signext or zeroext attributes.
1136 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1137 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1138 if (VT.bitsLT(MinVT))
1142 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1143 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1144 SmallVector<SDValue, 4> Parts(NumParts);
1145 getCopyToParts(DAG, getCurDebugLoc(),
1146 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1147 &Parts[0], NumParts, PartVT, ExtendKind);
1149 // 'inreg' on function refers to return value
1150 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1151 if (F->paramHasAttr(0, Attribute::InReg))
1154 // Propagate extension type if any
1155 if (F->paramHasAttr(0, Attribute::SExt))
1157 else if (F->paramHasAttr(0, Attribute::ZExt))
1160 for (unsigned i = 0; i < NumParts; ++i) {
1161 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1163 OutVals.push_back(Parts[i]);
1169 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1170 CallingConv::ID CallConv =
1171 DAG.getMachineFunction().getFunction()->getCallingConv();
1172 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1173 Outs, OutVals, getCurDebugLoc(), DAG);
1175 // Verify that the target's LowerReturn behaved as expected.
1176 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1177 "LowerReturn didn't return a valid chain!");
1179 // Update the DAG with the new chain value resulting from return lowering.
1183 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1184 /// created for it, emit nodes to copy the value into the virtual
1186 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1187 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1188 if (VMI != FuncInfo.ValueMap.end()) {
1189 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1190 CopyValueToVirtualRegister(V, VMI->second);
1194 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1195 /// the current basic block, add it to ValueMap now so that we'll get a
1197 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1198 // No need to export constants.
1199 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1201 // Already exported?
1202 if (FuncInfo.isExportedInst(V)) return;
1204 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1205 CopyValueToVirtualRegister(V, Reg);
1208 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1209 const BasicBlock *FromBB) {
1210 // The operands of the setcc have to be in this block. We don't know
1211 // how to export them from some other block.
1212 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1213 // Can export from current BB.
1214 if (VI->getParent() == FromBB)
1217 // Is already exported, noop.
1218 return FuncInfo.isExportedInst(V);
1221 // If this is an argument, we can export it if the BB is the entry block or
1222 // if it is already exported.
1223 if (isa<Argument>(V)) {
1224 if (FromBB == &FromBB->getParent()->getEntryBlock())
1227 // Otherwise, can only export this if it is already exported.
1228 return FuncInfo.isExportedInst(V);
1231 // Otherwise, constants can always be exported.
1235 static bool InBlock(const Value *V, const BasicBlock *BB) {
1236 if (const Instruction *I = dyn_cast<Instruction>(V))
1237 return I->getParent() == BB;
1241 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1242 /// This function emits a branch and is used at the leaves of an OR or an
1243 /// AND operator tree.
1246 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1247 MachineBasicBlock *TBB,
1248 MachineBasicBlock *FBB,
1249 MachineBasicBlock *CurBB,
1250 MachineBasicBlock *SwitchBB) {
1251 const BasicBlock *BB = CurBB->getBasicBlock();
1253 // If the leaf of the tree is a comparison, merge the condition into
1255 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1256 // The operands of the cmp have to be in this block. We don't know
1257 // how to export them from some other block. If this is the first block
1258 // of the sequence, no exporting is needed.
1259 if (CurBB == SwitchBB ||
1260 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1261 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1262 ISD::CondCode Condition;
1263 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1264 Condition = getICmpCondCode(IC->getPredicate());
1265 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1266 Condition = getFCmpCondCode(FC->getPredicate());
1268 Condition = ISD::SETEQ; // silence warning.
1269 llvm_unreachable("Unknown compare instruction");
1272 CaseBlock CB(Condition, BOp->getOperand(0),
1273 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1274 SwitchCases.push_back(CB);
1279 // Create a CaseBlock record representing this branch.
1280 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1281 NULL, TBB, FBB, CurBB);
1282 SwitchCases.push_back(CB);
1285 /// FindMergedConditions - If Cond is an expression like
1286 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1287 MachineBasicBlock *TBB,
1288 MachineBasicBlock *FBB,
1289 MachineBasicBlock *CurBB,
1290 MachineBasicBlock *SwitchBB,
1292 // If this node is not part of the or/and tree, emit it as a branch.
1293 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1294 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1295 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1296 BOp->getParent() != CurBB->getBasicBlock() ||
1297 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1298 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1299 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1303 // Create TmpBB after CurBB.
1304 MachineFunction::iterator BBI = CurBB;
1305 MachineFunction &MF = DAG.getMachineFunction();
1306 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1307 CurBB->getParent()->insert(++BBI, TmpBB);
1309 if (Opc == Instruction::Or) {
1310 // Codegen X | Y as:
1318 // Emit the LHS condition.
1319 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1321 // Emit the RHS condition into TmpBB.
1322 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1324 assert(Opc == Instruction::And && "Unknown merge op!");
1325 // Codegen X & Y as:
1332 // This requires creation of TmpBB after CurBB.
1334 // Emit the LHS condition.
1335 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1337 // Emit the RHS condition into TmpBB.
1338 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1342 /// If the set of cases should be emitted as a series of branches, return true.
1343 /// If we should emit this as a bunch of and/or'd together conditions, return
1346 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1347 if (Cases.size() != 2) return true;
1349 // If this is two comparisons of the same values or'd or and'd together, they
1350 // will get folded into a single comparison, so don't emit two blocks.
1351 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1352 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1353 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1354 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1358 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1359 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1360 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1361 Cases[0].CC == Cases[1].CC &&
1362 isa<Constant>(Cases[0].CmpRHS) &&
1363 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1364 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1366 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1373 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1374 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1376 // Update machine-CFG edges.
1377 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1379 // Figure out which block is immediately after the current one.
1380 MachineBasicBlock *NextBlock = 0;
1381 MachineFunction::iterator BBI = BrMBB;
1382 if (++BBI != FuncInfo.MF->end())
1385 if (I.isUnconditional()) {
1386 // Update machine-CFG edges.
1387 BrMBB->addSuccessor(Succ0MBB);
1389 // If this is not a fall-through branch, emit the branch.
1390 if (Succ0MBB != NextBlock)
1391 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1392 MVT::Other, getControlRoot(),
1393 DAG.getBasicBlock(Succ0MBB)));
1398 // If this condition is one of the special cases we handle, do special stuff
1400 const Value *CondVal = I.getCondition();
1401 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1403 // If this is a series of conditions that are or'd or and'd together, emit
1404 // this as a sequence of branches instead of setcc's with and/or operations.
1405 // As long as jumps are not expensive, this should improve performance.
1406 // For example, instead of something like:
1419 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1420 if (!TLI.isJumpExpensive() &&
1422 (BOp->getOpcode() == Instruction::And ||
1423 BOp->getOpcode() == Instruction::Or)) {
1424 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1426 // If the compares in later blocks need to use values not currently
1427 // exported from this block, export them now. This block should always
1428 // be the first entry.
1429 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1431 // Allow some cases to be rejected.
1432 if (ShouldEmitAsBranches(SwitchCases)) {
1433 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1434 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1435 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1438 // Emit the branch for this block.
1439 visitSwitchCase(SwitchCases[0], BrMBB);
1440 SwitchCases.erase(SwitchCases.begin());
1444 // Okay, we decided not to do this, remove any inserted MBB's and clear
1446 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1447 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1449 SwitchCases.clear();
1453 // Create a CaseBlock record representing this branch.
1454 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1455 NULL, Succ0MBB, Succ1MBB, BrMBB);
1457 // Use visitSwitchCase to actually insert the fast branch sequence for this
1459 visitSwitchCase(CB, BrMBB);
1462 /// visitSwitchCase - Emits the necessary code to represent a single node in
1463 /// the binary search tree resulting from lowering a switch instruction.
1464 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1465 MachineBasicBlock *SwitchBB) {
1467 SDValue CondLHS = getValue(CB.CmpLHS);
1468 DebugLoc dl = getCurDebugLoc();
1470 // Build the setcc now.
1471 if (CB.CmpMHS == NULL) {
1472 // Fold "(X == true)" to X and "(X == false)" to !X to
1473 // handle common cases produced by branch lowering.
1474 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1475 CB.CC == ISD::SETEQ)
1477 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1478 CB.CC == ISD::SETEQ) {
1479 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1480 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1482 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1484 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1486 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1487 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1489 SDValue CmpOp = getValue(CB.CmpMHS);
1490 EVT VT = CmpOp.getValueType();
1492 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1493 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1496 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1497 VT, CmpOp, DAG.getConstant(Low, VT));
1498 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1499 DAG.getConstant(High-Low, VT), ISD::SETULE);
1503 // Update successor info
1504 SwitchBB->addSuccessor(CB.TrueBB);
1505 SwitchBB->addSuccessor(CB.FalseBB);
1507 // Set NextBlock to be the MBB immediately after the current one, if any.
1508 // This is used to avoid emitting unnecessary branches to the next block.
1509 MachineBasicBlock *NextBlock = 0;
1510 MachineFunction::iterator BBI = SwitchBB;
1511 if (++BBI != FuncInfo.MF->end())
1514 // If the lhs block is the next block, invert the condition so that we can
1515 // fall through to the lhs instead of the rhs block.
1516 if (CB.TrueBB == NextBlock) {
1517 std::swap(CB.TrueBB, CB.FalseBB);
1518 SDValue True = DAG.getConstant(1, Cond.getValueType());
1519 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1522 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1523 MVT::Other, getControlRoot(), Cond,
1524 DAG.getBasicBlock(CB.TrueBB));
1526 // Insert the false branch. Do this even if it's a fall through branch,
1527 // this makes it easier to do DAG optimizations which require inverting
1528 // the branch condition.
1529 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1530 DAG.getBasicBlock(CB.FalseBB));
1532 DAG.setRoot(BrCond);
1535 /// visitJumpTable - Emit JumpTable node in the current MBB
1536 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1537 // Emit the code for the jump table
1538 assert(JT.Reg != -1U && "Should lower JT Header first!");
1539 EVT PTy = TLI.getPointerTy();
1540 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1542 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1543 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1544 MVT::Other, Index.getValue(1),
1546 DAG.setRoot(BrJumpTable);
1549 /// visitJumpTableHeader - This function emits necessary code to produce index
1550 /// in the JumpTable from switch case.
1551 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1552 JumpTableHeader &JTH,
1553 MachineBasicBlock *SwitchBB) {
1554 // Subtract the lowest switch case value from the value being switched on and
1555 // conditional branch to default mbb if the result is greater than the
1556 // difference between smallest and largest cases.
1557 SDValue SwitchOp = getValue(JTH.SValue);
1558 EVT VT = SwitchOp.getValueType();
1559 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1560 DAG.getConstant(JTH.First, VT));
1562 // The SDNode we just created, which holds the value being switched on minus
1563 // the smallest case value, needs to be copied to a virtual register so it
1564 // can be used as an index into the jump table in a subsequent basic block.
1565 // This value may be smaller or larger than the target's pointer type, and
1566 // therefore require extension or truncating.
1567 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1569 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1570 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1571 JumpTableReg, SwitchOp);
1572 JT.Reg = JumpTableReg;
1574 // Emit the range check for the jump table, and branch to the default block
1575 // for the switch statement if the value being switched on exceeds the largest
1576 // case in the switch.
1577 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1578 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1579 DAG.getConstant(JTH.Last-JTH.First,VT),
1582 // Set NextBlock to be the MBB immediately after the current one, if any.
1583 // This is used to avoid emitting unnecessary branches to the next block.
1584 MachineBasicBlock *NextBlock = 0;
1585 MachineFunction::iterator BBI = SwitchBB;
1587 if (++BBI != FuncInfo.MF->end())
1590 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1591 MVT::Other, CopyTo, CMP,
1592 DAG.getBasicBlock(JT.Default));
1594 if (JT.MBB != NextBlock)
1595 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1596 DAG.getBasicBlock(JT.MBB));
1598 DAG.setRoot(BrCond);
1601 /// visitBitTestHeader - This function emits necessary code to produce value
1602 /// suitable for "bit tests"
1603 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1604 MachineBasicBlock *SwitchBB) {
1605 // Subtract the minimum value
1606 SDValue SwitchOp = getValue(B.SValue);
1607 EVT VT = SwitchOp.getValueType();
1608 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1609 DAG.getConstant(B.First, VT));
1612 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1613 TLI.getSetCCResultType(Sub.getValueType()),
1614 Sub, DAG.getConstant(B.Range, VT),
1617 // Determine the type of the test operands.
1618 bool UsePtrType = false;
1619 if (!TLI.isTypeLegal(VT))
1622 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1623 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1624 // Switch table case range are encoded into series of masks.
1625 // Just use pointer type, it's guaranteed to fit.
1631 VT = TLI.getPointerTy();
1632 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1636 B.Reg = FuncInfo.CreateReg(VT);
1637 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1640 // Set NextBlock to be the MBB immediately after the current one, if any.
1641 // This is used to avoid emitting unnecessary branches to the next block.
1642 MachineBasicBlock *NextBlock = 0;
1643 MachineFunction::iterator BBI = SwitchBB;
1644 if (++BBI != FuncInfo.MF->end())
1647 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1649 SwitchBB->addSuccessor(B.Default);
1650 SwitchBB->addSuccessor(MBB);
1652 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1653 MVT::Other, CopyTo, RangeCmp,
1654 DAG.getBasicBlock(B.Default));
1656 if (MBB != NextBlock)
1657 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1658 DAG.getBasicBlock(MBB));
1660 DAG.setRoot(BrRange);
1663 /// visitBitTestCase - this function produces one "bit test"
1664 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1665 MachineBasicBlock* NextMBB,
1668 MachineBasicBlock *SwitchBB) {
1670 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1673 if (CountPopulation_64(B.Mask) == 1) {
1674 // Testing for a single bit; just compare the shift count with what it
1675 // would need to be to shift a 1 bit in that position.
1676 Cmp = DAG.getSetCC(getCurDebugLoc(),
1677 TLI.getSetCCResultType(VT),
1679 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1682 // Make desired shift
1683 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1684 DAG.getConstant(1, VT), ShiftOp);
1686 // Emit bit tests and jumps
1687 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1688 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1689 Cmp = DAG.getSetCC(getCurDebugLoc(),
1690 TLI.getSetCCResultType(VT),
1691 AndOp, DAG.getConstant(0, VT),
1695 SwitchBB->addSuccessor(B.TargetBB);
1696 SwitchBB->addSuccessor(NextMBB);
1698 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1699 MVT::Other, getControlRoot(),
1700 Cmp, DAG.getBasicBlock(B.TargetBB));
1702 // Set NextBlock to be the MBB immediately after the current one, if any.
1703 // This is used to avoid emitting unnecessary branches to the next block.
1704 MachineBasicBlock *NextBlock = 0;
1705 MachineFunction::iterator BBI = SwitchBB;
1706 if (++BBI != FuncInfo.MF->end())
1709 if (NextMBB != NextBlock)
1710 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1711 DAG.getBasicBlock(NextMBB));
1716 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1717 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1719 // Retrieve successors.
1720 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1721 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1723 const Value *Callee(I.getCalledValue());
1724 if (isa<InlineAsm>(Callee))
1727 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1729 // If the value of the invoke is used outside of its defining block, make it
1730 // available as a virtual register.
1731 CopyToExportRegsIfNeeded(&I);
1733 // Update successor info
1734 InvokeMBB->addSuccessor(Return);
1735 InvokeMBB->addSuccessor(LandingPad);
1737 // Drop into normal successor.
1738 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1739 MVT::Other, getControlRoot(),
1740 DAG.getBasicBlock(Return)));
1743 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1746 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1747 /// small case ranges).
1748 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1749 CaseRecVector& WorkList,
1751 MachineBasicBlock *Default,
1752 MachineBasicBlock *SwitchBB) {
1753 Case& BackCase = *(CR.Range.second-1);
1755 // Size is the number of Cases represented by this range.
1756 size_t Size = CR.Range.second - CR.Range.first;
1760 // Get the MachineFunction which holds the current MBB. This is used when
1761 // inserting any additional MBBs necessary to represent the switch.
1762 MachineFunction *CurMF = FuncInfo.MF;
1764 // Figure out which block is immediately after the current one.
1765 MachineBasicBlock *NextBlock = 0;
1766 MachineFunction::iterator BBI = CR.CaseBB;
1768 if (++BBI != FuncInfo.MF->end())
1771 // If any two of the cases has the same destination, and if one value
1772 // is the same as the other, but has one bit unset that the other has set,
1773 // use bit manipulation to do two compares at once. For example:
1774 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1775 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1776 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1777 if (Size == 2 && CR.CaseBB == SwitchBB) {
1778 Case &Small = *CR.Range.first;
1779 Case &Big = *(CR.Range.second-1);
1781 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1782 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1783 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1785 // Check that there is only one bit different.
1786 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1787 (SmallValue | BigValue) == BigValue) {
1788 // Isolate the common bit.
1789 APInt CommonBit = BigValue & ~SmallValue;
1790 assert((SmallValue | CommonBit) == BigValue &&
1791 CommonBit.countPopulation() == 1 && "Not a common bit?");
1793 SDValue CondLHS = getValue(SV);
1794 EVT VT = CondLHS.getValueType();
1795 DebugLoc DL = getCurDebugLoc();
1797 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1798 DAG.getConstant(CommonBit, VT));
1799 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1800 Or, DAG.getConstant(BigValue, VT),
1803 // Update successor info.
1804 SwitchBB->addSuccessor(Small.BB);
1805 SwitchBB->addSuccessor(Default);
1807 // Insert the true branch.
1808 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1809 getControlRoot(), Cond,
1810 DAG.getBasicBlock(Small.BB));
1812 // Insert the false branch.
1813 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1814 DAG.getBasicBlock(Default));
1816 DAG.setRoot(BrCond);
1822 // Rearrange the case blocks so that the last one falls through if possible.
1823 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1824 // The last case block won't fall through into 'NextBlock' if we emit the
1825 // branches in this order. See if rearranging a case value would help.
1826 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1827 if (I->BB == NextBlock) {
1828 std::swap(*I, BackCase);
1834 // Create a CaseBlock record representing a conditional branch to
1835 // the Case's target mbb if the value being switched on SV is equal
1837 MachineBasicBlock *CurBlock = CR.CaseBB;
1838 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1839 MachineBasicBlock *FallThrough;
1841 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1842 CurMF->insert(BBI, FallThrough);
1844 // Put SV in a virtual register to make it available from the new blocks.
1845 ExportFromCurrentBlock(SV);
1847 // If the last case doesn't match, go to the default block.
1848 FallThrough = Default;
1851 const Value *RHS, *LHS, *MHS;
1853 if (I->High == I->Low) {
1854 // This is just small small case range :) containing exactly 1 case
1856 LHS = SV; RHS = I->High; MHS = NULL;
1859 LHS = I->Low; MHS = SV; RHS = I->High;
1861 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1863 // If emitting the first comparison, just call visitSwitchCase to emit the
1864 // code into the current block. Otherwise, push the CaseBlock onto the
1865 // vector to be later processed by SDISel, and insert the node's MBB
1866 // before the next MBB.
1867 if (CurBlock == SwitchBB)
1868 visitSwitchCase(CB, SwitchBB);
1870 SwitchCases.push_back(CB);
1872 CurBlock = FallThrough;
1878 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1879 return !DisableJumpTables &&
1880 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1881 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1884 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1885 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1886 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1887 return (LastExt - FirstExt + 1ULL);
1890 /// handleJTSwitchCase - Emit jumptable for current switch case range
1891 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1892 CaseRecVector& WorkList,
1894 MachineBasicBlock* Default,
1895 MachineBasicBlock *SwitchBB) {
1896 Case& FrontCase = *CR.Range.first;
1897 Case& BackCase = *(CR.Range.second-1);
1899 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1900 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1902 APInt TSize(First.getBitWidth(), 0);
1903 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1907 if (!areJTsAllowed(TLI) || TSize.ult(4))
1910 APInt Range = ComputeRange(First, Last);
1911 double Density = TSize.roundToDouble() / Range.roundToDouble();
1915 DEBUG(dbgs() << "Lowering jump table\n"
1916 << "First entry: " << First << ". Last entry: " << Last << '\n'
1917 << "Range: " << Range
1918 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1920 // Get the MachineFunction which holds the current MBB. This is used when
1921 // inserting any additional MBBs necessary to represent the switch.
1922 MachineFunction *CurMF = FuncInfo.MF;
1924 // Figure out which block is immediately after the current one.
1925 MachineFunction::iterator BBI = CR.CaseBB;
1928 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1930 // Create a new basic block to hold the code for loading the address
1931 // of the jump table, and jumping to it. Update successor information;
1932 // we will either branch to the default case for the switch, or the jump
1934 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1935 CurMF->insert(BBI, JumpTableBB);
1936 CR.CaseBB->addSuccessor(Default);
1937 CR.CaseBB->addSuccessor(JumpTableBB);
1939 // Build a vector of destination BBs, corresponding to each target
1940 // of the jump table. If the value of the jump table slot corresponds to
1941 // a case statement, push the case's BB onto the vector, otherwise, push
1943 std::vector<MachineBasicBlock*> DestBBs;
1945 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1946 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1947 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1949 if (Low.sle(TEI) && TEI.sle(High)) {
1950 DestBBs.push_back(I->BB);
1954 DestBBs.push_back(Default);
1958 // Update successor info. Add one edge to each unique successor.
1959 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1960 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1961 E = DestBBs.end(); I != E; ++I) {
1962 if (!SuccsHandled[(*I)->getNumber()]) {
1963 SuccsHandled[(*I)->getNumber()] = true;
1964 JumpTableBB->addSuccessor(*I);
1968 // Create a jump table index for this jump table.
1969 unsigned JTEncoding = TLI.getJumpTableEncoding();
1970 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1971 ->createJumpTableIndex(DestBBs);
1973 // Set the jump table information so that we can codegen it as a second
1974 // MachineBasicBlock
1975 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1976 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1977 if (CR.CaseBB == SwitchBB)
1978 visitJumpTableHeader(JT, JTH, SwitchBB);
1980 JTCases.push_back(JumpTableBlock(JTH, JT));
1985 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1987 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1988 CaseRecVector& WorkList,
1990 MachineBasicBlock *Default,
1991 MachineBasicBlock *SwitchBB) {
1992 // Get the MachineFunction which holds the current MBB. This is used when
1993 // inserting any additional MBBs necessary to represent the switch.
1994 MachineFunction *CurMF = FuncInfo.MF;
1996 // Figure out which block is immediately after the current one.
1997 MachineFunction::iterator BBI = CR.CaseBB;
2000 Case& FrontCase = *CR.Range.first;
2001 Case& BackCase = *(CR.Range.second-1);
2002 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2004 // Size is the number of Cases represented by this range.
2005 unsigned Size = CR.Range.second - CR.Range.first;
2007 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2008 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2010 CaseItr Pivot = CR.Range.first + Size/2;
2012 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2013 // (heuristically) allow us to emit JumpTable's later.
2014 APInt TSize(First.getBitWidth(), 0);
2015 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2019 APInt LSize = FrontCase.size();
2020 APInt RSize = TSize-LSize;
2021 DEBUG(dbgs() << "Selecting best pivot: \n"
2022 << "First: " << First << ", Last: " << Last <<'\n'
2023 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2024 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2026 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2027 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2028 APInt Range = ComputeRange(LEnd, RBegin);
2029 assert((Range - 2ULL).isNonNegative() &&
2030 "Invalid case distance");
2031 double LDensity = (double)LSize.roundToDouble() /
2032 (LEnd - First + 1ULL).roundToDouble();
2033 double RDensity = (double)RSize.roundToDouble() /
2034 (Last - RBegin + 1ULL).roundToDouble();
2035 double Metric = Range.logBase2()*(LDensity+RDensity);
2036 // Should always split in some non-trivial place
2037 DEBUG(dbgs() <<"=>Step\n"
2038 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2039 << "LDensity: " << LDensity
2040 << ", RDensity: " << RDensity << '\n'
2041 << "Metric: " << Metric << '\n');
2042 if (FMetric < Metric) {
2045 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2051 if (areJTsAllowed(TLI)) {
2052 // If our case is dense we *really* should handle it earlier!
2053 assert((FMetric > 0) && "Should handle dense range earlier!");
2055 Pivot = CR.Range.first + Size/2;
2058 CaseRange LHSR(CR.Range.first, Pivot);
2059 CaseRange RHSR(Pivot, CR.Range.second);
2060 Constant *C = Pivot->Low;
2061 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2063 // We know that we branch to the LHS if the Value being switched on is
2064 // less than the Pivot value, C. We use this to optimize our binary
2065 // tree a bit, by recognizing that if SV is greater than or equal to the
2066 // LHS's Case Value, and that Case Value is exactly one less than the
2067 // Pivot's Value, then we can branch directly to the LHS's Target,
2068 // rather than creating a leaf node for it.
2069 if ((LHSR.second - LHSR.first) == 1 &&
2070 LHSR.first->High == CR.GE &&
2071 cast<ConstantInt>(C)->getValue() ==
2072 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2073 TrueBB = LHSR.first->BB;
2075 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2076 CurMF->insert(BBI, TrueBB);
2077 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2079 // Put SV in a virtual register to make it available from the new blocks.
2080 ExportFromCurrentBlock(SV);
2083 // Similar to the optimization above, if the Value being switched on is
2084 // known to be less than the Constant CR.LT, and the current Case Value
2085 // is CR.LT - 1, then we can branch directly to the target block for
2086 // the current Case Value, rather than emitting a RHS leaf node for it.
2087 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2088 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2089 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2090 FalseBB = RHSR.first->BB;
2092 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2093 CurMF->insert(BBI, FalseBB);
2094 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2096 // Put SV in a virtual register to make it available from the new blocks.
2097 ExportFromCurrentBlock(SV);
2100 // Create a CaseBlock record representing a conditional branch to
2101 // the LHS node if the value being switched on SV is less than C.
2102 // Otherwise, branch to LHS.
2103 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2105 if (CR.CaseBB == SwitchBB)
2106 visitSwitchCase(CB, SwitchBB);
2108 SwitchCases.push_back(CB);
2113 /// handleBitTestsSwitchCase - if current case range has few destination and
2114 /// range span less, than machine word bitwidth, encode case range into series
2115 /// of masks and emit bit tests with these masks.
2116 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2117 CaseRecVector& WorkList,
2119 MachineBasicBlock* Default,
2120 MachineBasicBlock *SwitchBB){
2121 EVT PTy = TLI.getPointerTy();
2122 unsigned IntPtrBits = PTy.getSizeInBits();
2124 Case& FrontCase = *CR.Range.first;
2125 Case& BackCase = *(CR.Range.second-1);
2127 // Get the MachineFunction which holds the current MBB. This is used when
2128 // inserting any additional MBBs necessary to represent the switch.
2129 MachineFunction *CurMF = FuncInfo.MF;
2131 // If target does not have legal shift left, do not emit bit tests at all.
2132 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2136 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2138 // Single case counts one, case range - two.
2139 numCmps += (I->Low == I->High ? 1 : 2);
2142 // Count unique destinations
2143 SmallSet<MachineBasicBlock*, 4> Dests;
2144 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2145 Dests.insert(I->BB);
2146 if (Dests.size() > 3)
2147 // Don't bother the code below, if there are too much unique destinations
2150 DEBUG(dbgs() << "Total number of unique destinations: "
2151 << Dests.size() << '\n'
2152 << "Total number of comparisons: " << numCmps << '\n');
2154 // Compute span of values.
2155 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2156 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2157 APInt cmpRange = maxValue - minValue;
2159 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2160 << "Low bound: " << minValue << '\n'
2161 << "High bound: " << maxValue << '\n');
2163 if (cmpRange.uge(IntPtrBits) ||
2164 (!(Dests.size() == 1 && numCmps >= 3) &&
2165 !(Dests.size() == 2 && numCmps >= 5) &&
2166 !(Dests.size() >= 3 && numCmps >= 6)))
2169 DEBUG(dbgs() << "Emitting bit tests\n");
2170 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2172 // Optimize the case where all the case values fit in a
2173 // word without having to subtract minValue. In this case,
2174 // we can optimize away the subtraction.
2175 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2176 cmpRange = maxValue;
2178 lowBound = minValue;
2181 CaseBitsVector CasesBits;
2182 unsigned i, count = 0;
2184 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2185 MachineBasicBlock* Dest = I->BB;
2186 for (i = 0; i < count; ++i)
2187 if (Dest == CasesBits[i].BB)
2191 assert((count < 3) && "Too much destinations to test!");
2192 CasesBits.push_back(CaseBits(0, Dest, 0));
2196 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2197 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2199 uint64_t lo = (lowValue - lowBound).getZExtValue();
2200 uint64_t hi = (highValue - lowBound).getZExtValue();
2202 for (uint64_t j = lo; j <= hi; j++) {
2203 CasesBits[i].Mask |= 1ULL << j;
2204 CasesBits[i].Bits++;
2208 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2212 // Figure out which block is immediately after the current one.
2213 MachineFunction::iterator BBI = CR.CaseBB;
2216 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2218 DEBUG(dbgs() << "Cases:\n");
2219 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2220 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2221 << ", Bits: " << CasesBits[i].Bits
2222 << ", BB: " << CasesBits[i].BB << '\n');
2224 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2225 CurMF->insert(BBI, CaseBB);
2226 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2230 // Put SV in a virtual register to make it available from the new blocks.
2231 ExportFromCurrentBlock(SV);
2234 BitTestBlock BTB(lowBound, cmpRange, SV,
2235 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2236 CR.CaseBB, Default, BTC);
2238 if (CR.CaseBB == SwitchBB)
2239 visitBitTestHeader(BTB, SwitchBB);
2241 BitTestCases.push_back(BTB);
2246 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2247 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2248 const SwitchInst& SI) {
2251 // Start with "simple" cases
2252 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2253 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2254 Cases.push_back(Case(SI.getSuccessorValue(i),
2255 SI.getSuccessorValue(i),
2258 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2260 // Merge case into clusters
2261 if (Cases.size() >= 2)
2262 // Must recompute end() each iteration because it may be
2263 // invalidated by erase if we hold on to it
2264 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2265 J != Cases.end(); ) {
2266 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2267 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2268 MachineBasicBlock* nextBB = J->BB;
2269 MachineBasicBlock* currentBB = I->BB;
2271 // If the two neighboring cases go to the same destination, merge them
2272 // into a single case.
2273 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2281 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2282 if (I->Low != I->High)
2283 // A range counts double, since it requires two compares.
2290 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2291 MachineBasicBlock *Last) {
2293 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2294 if (JTCases[i].first.HeaderBB == First)
2295 JTCases[i].first.HeaderBB = Last;
2297 // Update BitTestCases.
2298 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2299 if (BitTestCases[i].Parent == First)
2300 BitTestCases[i].Parent = Last;
2303 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2304 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2306 // Figure out which block is immediately after the current one.
2307 MachineBasicBlock *NextBlock = 0;
2308 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2310 // If there is only the default destination, branch to it if it is not the
2311 // next basic block. Otherwise, just fall through.
2312 if (SI.getNumOperands() == 2) {
2313 // Update machine-CFG edges.
2315 // If this is not a fall-through branch, emit the branch.
2316 SwitchMBB->addSuccessor(Default);
2317 if (Default != NextBlock)
2318 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2319 MVT::Other, getControlRoot(),
2320 DAG.getBasicBlock(Default)));
2325 // If there are any non-default case statements, create a vector of Cases
2326 // representing each one, and sort the vector so that we can efficiently
2327 // create a binary search tree from them.
2329 size_t numCmps = Clusterify(Cases, SI);
2330 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2331 << ". Total compares: " << numCmps << '\n');
2334 // Get the Value to be switched on and default basic blocks, which will be
2335 // inserted into CaseBlock records, representing basic blocks in the binary
2337 const Value *SV = SI.getOperand(0);
2339 // Push the initial CaseRec onto the worklist
2340 CaseRecVector WorkList;
2341 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2342 CaseRange(Cases.begin(),Cases.end())));
2344 while (!WorkList.empty()) {
2345 // Grab a record representing a case range to process off the worklist
2346 CaseRec CR = WorkList.back();
2347 WorkList.pop_back();
2349 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2352 // If the range has few cases (two or less) emit a series of specific
2354 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2357 // If the switch has more than 5 blocks, and at least 40% dense, and the
2358 // target supports indirect branches, then emit a jump table rather than
2359 // lowering the switch to a binary tree of conditional branches.
2360 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2363 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2364 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2365 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2369 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2370 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2372 // Update machine-CFG edges with unique successors.
2373 SmallVector<BasicBlock*, 32> succs;
2374 succs.reserve(I.getNumSuccessors());
2375 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2376 succs.push_back(I.getSuccessor(i));
2377 array_pod_sort(succs.begin(), succs.end());
2378 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2379 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2380 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2382 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2383 MVT::Other, getControlRoot(),
2384 getValue(I.getAddress())));
2387 void SelectionDAGBuilder::visitFSub(const User &I) {
2388 // -0.0 - X --> fneg
2389 const Type *Ty = I.getType();
2390 if (Ty->isVectorTy()) {
2391 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2392 const VectorType *DestTy = cast<VectorType>(I.getType());
2393 const Type *ElTy = DestTy->getElementType();
2394 unsigned VL = DestTy->getNumElements();
2395 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2396 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2398 SDValue Op2 = getValue(I.getOperand(1));
2399 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2400 Op2.getValueType(), Op2));
2406 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2407 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2408 SDValue Op2 = getValue(I.getOperand(1));
2409 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2410 Op2.getValueType(), Op2));
2414 visitBinary(I, ISD::FSUB);
2417 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2418 SDValue Op1 = getValue(I.getOperand(0));
2419 SDValue Op2 = getValue(I.getOperand(1));
2420 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2421 Op1.getValueType(), Op1, Op2));
2424 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2425 SDValue Op1 = getValue(I.getOperand(0));
2426 SDValue Op2 = getValue(I.getOperand(1));
2428 MVT ShiftTy = TLI.getShiftAmountTy();
2429 unsigned ShiftSize = ShiftTy.getSizeInBits();
2430 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2432 // Coerce the shift amount to the right type if we can.
2433 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2434 DebugLoc DL = getCurDebugLoc();
2436 // If the operand is smaller than the shift count type, promote it.
2437 MVT PtrTy = TLI.getPointerTy();
2438 if (ShiftSize > Op2Size)
2439 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2441 // If the operand is larger than the shift count type but the shift
2442 // count type has enough bits to represent any shift value, truncate
2443 // it now. This is a common case and it exposes the truncate to
2444 // optimization early.
2445 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2446 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2447 // Otherwise we'll need to temporarily settle for some other convenient
2448 // type. Type legalization will make adjustments as needed.
2450 Op2 = DAG.getZExtOrTrunc(Op2, DL, PtrTy);
2453 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2454 Op1.getValueType(), Op1, Op2));
2457 void SelectionDAGBuilder::visitICmp(const User &I) {
2458 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2459 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2460 predicate = IC->getPredicate();
2461 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2462 predicate = ICmpInst::Predicate(IC->getPredicate());
2463 SDValue Op1 = getValue(I.getOperand(0));
2464 SDValue Op2 = getValue(I.getOperand(1));
2465 ISD::CondCode Opcode = getICmpCondCode(predicate);
2467 EVT DestVT = TLI.getValueType(I.getType());
2468 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2471 void SelectionDAGBuilder::visitFCmp(const User &I) {
2472 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2473 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2474 predicate = FC->getPredicate();
2475 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2476 predicate = FCmpInst::Predicate(FC->getPredicate());
2477 SDValue Op1 = getValue(I.getOperand(0));
2478 SDValue Op2 = getValue(I.getOperand(1));
2479 ISD::CondCode Condition = getFCmpCondCode(predicate);
2480 EVT DestVT = TLI.getValueType(I.getType());
2481 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2484 void SelectionDAGBuilder::visitSelect(const User &I) {
2485 SmallVector<EVT, 4> ValueVTs;
2486 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2487 unsigned NumValues = ValueVTs.size();
2488 if (NumValues == 0) return;
2490 SmallVector<SDValue, 4> Values(NumValues);
2491 SDValue Cond = getValue(I.getOperand(0));
2492 SDValue TrueVal = getValue(I.getOperand(1));
2493 SDValue FalseVal = getValue(I.getOperand(2));
2495 for (unsigned i = 0; i != NumValues; ++i)
2496 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2497 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2499 SDValue(TrueVal.getNode(),
2500 TrueVal.getResNo() + i),
2501 SDValue(FalseVal.getNode(),
2502 FalseVal.getResNo() + i));
2504 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2505 DAG.getVTList(&ValueVTs[0], NumValues),
2506 &Values[0], NumValues));
2509 void SelectionDAGBuilder::visitTrunc(const User &I) {
2510 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2511 SDValue N = getValue(I.getOperand(0));
2512 EVT DestVT = TLI.getValueType(I.getType());
2513 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2516 void SelectionDAGBuilder::visitZExt(const User &I) {
2517 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2518 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2519 SDValue N = getValue(I.getOperand(0));
2520 EVT DestVT = TLI.getValueType(I.getType());
2521 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2524 void SelectionDAGBuilder::visitSExt(const User &I) {
2525 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2526 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2527 SDValue N = getValue(I.getOperand(0));
2528 EVT DestVT = TLI.getValueType(I.getType());
2529 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2532 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2533 // FPTrunc is never a no-op cast, no need to check
2534 SDValue N = getValue(I.getOperand(0));
2535 EVT DestVT = TLI.getValueType(I.getType());
2536 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2537 DestVT, N, DAG.getIntPtrConstant(0)));
2540 void SelectionDAGBuilder::visitFPExt(const User &I){
2541 // FPTrunc is never a no-op cast, no need to check
2542 SDValue N = getValue(I.getOperand(0));
2543 EVT DestVT = TLI.getValueType(I.getType());
2544 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2547 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2548 // FPToUI is never a no-op cast, no need to check
2549 SDValue N = getValue(I.getOperand(0));
2550 EVT DestVT = TLI.getValueType(I.getType());
2551 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2554 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2555 // FPToSI is never a no-op cast, no need to check
2556 SDValue N = getValue(I.getOperand(0));
2557 EVT DestVT = TLI.getValueType(I.getType());
2558 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2561 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2562 // UIToFP is never a no-op cast, no need to check
2563 SDValue N = getValue(I.getOperand(0));
2564 EVT DestVT = TLI.getValueType(I.getType());
2565 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2568 void SelectionDAGBuilder::visitSIToFP(const User &I){
2569 // SIToFP is never a no-op cast, no need to check
2570 SDValue N = getValue(I.getOperand(0));
2571 EVT DestVT = TLI.getValueType(I.getType());
2572 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2575 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2576 // What to do depends on the size of the integer and the size of the pointer.
2577 // We can either truncate, zero extend, or no-op, accordingly.
2578 SDValue N = getValue(I.getOperand(0));
2579 EVT DestVT = TLI.getValueType(I.getType());
2580 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2583 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2584 // What to do depends on the size of the integer and the size of the pointer.
2585 // We can either truncate, zero extend, or no-op, accordingly.
2586 SDValue N = getValue(I.getOperand(0));
2587 EVT DestVT = TLI.getValueType(I.getType());
2588 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2591 void SelectionDAGBuilder::visitBitCast(const User &I) {
2592 SDValue N = getValue(I.getOperand(0));
2593 EVT DestVT = TLI.getValueType(I.getType());
2595 // BitCast assures us that source and destination are the same size so this is
2596 // either a BITCAST or a no-op.
2597 if (DestVT != N.getValueType())
2598 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2599 DestVT, N)); // convert types.
2601 setValue(&I, N); // noop cast.
2604 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2605 SDValue InVec = getValue(I.getOperand(0));
2606 SDValue InVal = getValue(I.getOperand(1));
2607 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2609 getValue(I.getOperand(2)));
2610 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2611 TLI.getValueType(I.getType()),
2612 InVec, InVal, InIdx));
2615 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2616 SDValue InVec = getValue(I.getOperand(0));
2617 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2619 getValue(I.getOperand(1)));
2620 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2621 TLI.getValueType(I.getType()), InVec, InIdx));
2624 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2625 // from SIndx and increasing to the element length (undefs are allowed).
2626 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2627 unsigned MaskNumElts = Mask.size();
2628 for (unsigned i = 0; i != MaskNumElts; ++i)
2629 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2634 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2635 SmallVector<int, 8> Mask;
2636 SDValue Src1 = getValue(I.getOperand(0));
2637 SDValue Src2 = getValue(I.getOperand(1));
2639 // Convert the ConstantVector mask operand into an array of ints, with -1
2640 // representing undef values.
2641 SmallVector<Constant*, 8> MaskElts;
2642 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2643 unsigned MaskNumElts = MaskElts.size();
2644 for (unsigned i = 0; i != MaskNumElts; ++i) {
2645 if (isa<UndefValue>(MaskElts[i]))
2648 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2651 EVT VT = TLI.getValueType(I.getType());
2652 EVT SrcVT = Src1.getValueType();
2653 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2655 if (SrcNumElts == MaskNumElts) {
2656 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2661 // Normalize the shuffle vector since mask and vector length don't match.
2662 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2663 // Mask is longer than the source vectors and is a multiple of the source
2664 // vectors. We can use concatenate vector to make the mask and vectors
2666 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2667 // The shuffle is concatenating two vectors together.
2668 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2673 // Pad both vectors with undefs to make them the same length as the mask.
2674 unsigned NumConcat = MaskNumElts / SrcNumElts;
2675 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2676 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2677 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2679 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2680 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2684 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2685 getCurDebugLoc(), VT,
2686 &MOps1[0], NumConcat);
2687 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2688 getCurDebugLoc(), VT,
2689 &MOps2[0], NumConcat);
2691 // Readjust mask for new input vector length.
2692 SmallVector<int, 8> MappedOps;
2693 for (unsigned i = 0; i != MaskNumElts; ++i) {
2695 if (Idx < (int)SrcNumElts)
2696 MappedOps.push_back(Idx);
2698 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2701 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2706 if (SrcNumElts > MaskNumElts) {
2707 // Analyze the access pattern of the vector to see if we can extract
2708 // two subvectors and do the shuffle. The analysis is done by calculating
2709 // the range of elements the mask access on both vectors.
2710 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2711 int MaxRange[2] = {-1, -1};
2713 for (unsigned i = 0; i != MaskNumElts; ++i) {
2719 if (Idx >= (int)SrcNumElts) {
2723 if (Idx > MaxRange[Input])
2724 MaxRange[Input] = Idx;
2725 if (Idx < MinRange[Input])
2726 MinRange[Input] = Idx;
2729 // Check if the access is smaller than the vector size and can we find
2730 // a reasonable extract index.
2731 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2733 int StartIdx[2]; // StartIdx to extract from
2734 for (int Input=0; Input < 2; ++Input) {
2735 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2736 RangeUse[Input] = 0; // Unused
2737 StartIdx[Input] = 0;
2738 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2739 // Fits within range but we should see if we can find a good
2740 // start index that is a multiple of the mask length.
2741 if (MaxRange[Input] < (int)MaskNumElts) {
2742 RangeUse[Input] = 1; // Extract from beginning of the vector
2743 StartIdx[Input] = 0;
2745 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2746 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2747 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2748 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2753 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2754 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2757 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2758 // Extract appropriate subvector and generate a vector shuffle
2759 for (int Input=0; Input < 2; ++Input) {
2760 SDValue &Src = Input == 0 ? Src1 : Src2;
2761 if (RangeUse[Input] == 0)
2762 Src = DAG.getUNDEF(VT);
2764 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2765 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2768 // Calculate new mask.
2769 SmallVector<int, 8> MappedOps;
2770 for (unsigned i = 0; i != MaskNumElts; ++i) {
2773 MappedOps.push_back(Idx);
2774 else if (Idx < (int)SrcNumElts)
2775 MappedOps.push_back(Idx - StartIdx[0]);
2777 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2780 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2786 // We can't use either concat vectors or extract subvectors so fall back to
2787 // replacing the shuffle with extract and build vector.
2788 // to insert and build vector.
2789 EVT EltVT = VT.getVectorElementType();
2790 EVT PtrVT = TLI.getPointerTy();
2791 SmallVector<SDValue,8> Ops;
2792 for (unsigned i = 0; i != MaskNumElts; ++i) {
2794 Ops.push_back(DAG.getUNDEF(EltVT));
2799 if (Idx < (int)SrcNumElts)
2800 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2801 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2803 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2805 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2811 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2812 VT, &Ops[0], Ops.size()));
2815 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2816 const Value *Op0 = I.getOperand(0);
2817 const Value *Op1 = I.getOperand(1);
2818 const Type *AggTy = I.getType();
2819 const Type *ValTy = Op1->getType();
2820 bool IntoUndef = isa<UndefValue>(Op0);
2821 bool FromUndef = isa<UndefValue>(Op1);
2823 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2825 SmallVector<EVT, 4> AggValueVTs;
2826 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2827 SmallVector<EVT, 4> ValValueVTs;
2828 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2830 unsigned NumAggValues = AggValueVTs.size();
2831 unsigned NumValValues = ValValueVTs.size();
2832 SmallVector<SDValue, 4> Values(NumAggValues);
2834 SDValue Agg = getValue(Op0);
2835 SDValue Val = getValue(Op1);
2837 // Copy the beginning value(s) from the original aggregate.
2838 for (; i != LinearIndex; ++i)
2839 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2840 SDValue(Agg.getNode(), Agg.getResNo() + i);
2841 // Copy values from the inserted value(s).
2842 for (; i != LinearIndex + NumValValues; ++i)
2843 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2844 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2845 // Copy remaining value(s) from the original aggregate.
2846 for (; i != NumAggValues; ++i)
2847 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2848 SDValue(Agg.getNode(), Agg.getResNo() + i);
2850 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2851 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2852 &Values[0], NumAggValues));
2855 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2856 const Value *Op0 = I.getOperand(0);
2857 const Type *AggTy = Op0->getType();
2858 const Type *ValTy = I.getType();
2859 bool OutOfUndef = isa<UndefValue>(Op0);
2861 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2863 SmallVector<EVT, 4> ValValueVTs;
2864 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2866 unsigned NumValValues = ValValueVTs.size();
2867 SmallVector<SDValue, 4> Values(NumValValues);
2869 SDValue Agg = getValue(Op0);
2870 // Copy out the selected value(s).
2871 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2872 Values[i - LinearIndex] =
2874 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2875 SDValue(Agg.getNode(), Agg.getResNo() + i);
2877 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2878 DAG.getVTList(&ValValueVTs[0], NumValValues),
2879 &Values[0], NumValValues));
2882 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2883 SDValue N = getValue(I.getOperand(0));
2884 const Type *Ty = I.getOperand(0)->getType();
2886 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2888 const Value *Idx = *OI;
2889 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2890 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2893 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2894 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2895 DAG.getIntPtrConstant(Offset));
2898 Ty = StTy->getElementType(Field);
2900 Ty = cast<SequentialType>(Ty)->getElementType();
2902 // If this is a constant subscript, handle it quickly.
2903 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2904 if (CI->isZero()) continue;
2906 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2908 EVT PTy = TLI.getPointerTy();
2909 unsigned PtrBits = PTy.getSizeInBits();
2911 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2913 DAG.getConstant(Offs, MVT::i64));
2915 OffsVal = DAG.getIntPtrConstant(Offs);
2917 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2922 // N = N + Idx * ElementSize;
2923 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2924 TD->getTypeAllocSize(Ty));
2925 SDValue IdxN = getValue(Idx);
2927 // If the index is smaller or larger than intptr_t, truncate or extend
2929 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2931 // If this is a multiply by a power of two, turn it into a shl
2932 // immediately. This is a very common case.
2933 if (ElementSize != 1) {
2934 if (ElementSize.isPowerOf2()) {
2935 unsigned Amt = ElementSize.logBase2();
2936 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2937 N.getValueType(), IdxN,
2938 DAG.getConstant(Amt, TLI.getPointerTy()));
2940 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2941 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2942 N.getValueType(), IdxN, Scale);
2946 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2947 N.getValueType(), N, IdxN);
2954 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2955 // If this is a fixed sized alloca in the entry block of the function,
2956 // allocate it statically on the stack.
2957 if (FuncInfo.StaticAllocaMap.count(&I))
2958 return; // getValue will auto-populate this.
2960 const Type *Ty = I.getAllocatedType();
2961 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2963 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2966 SDValue AllocSize = getValue(I.getArraySize());
2968 EVT IntPtr = TLI.getPointerTy();
2969 if (AllocSize.getValueType() != IntPtr)
2970 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2972 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2974 DAG.getConstant(TySize, IntPtr));
2976 // Handle alignment. If the requested alignment is less than or equal to
2977 // the stack alignment, ignore it. If the size is greater than or equal to
2978 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2979 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2980 if (Align <= StackAlign)
2983 // Round the size of the allocation up to the stack alignment size
2984 // by add SA-1 to the size.
2985 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2986 AllocSize.getValueType(), AllocSize,
2987 DAG.getIntPtrConstant(StackAlign-1));
2989 // Mask out the low bits for alignment purposes.
2990 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2991 AllocSize.getValueType(), AllocSize,
2992 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2994 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2995 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2996 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2999 DAG.setRoot(DSA.getValue(1));
3001 // Inform the Frame Information that we have just allocated a variable-sized
3003 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3006 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3007 const Value *SV = I.getOperand(0);
3008 SDValue Ptr = getValue(SV);
3010 const Type *Ty = I.getType();
3012 bool isVolatile = I.isVolatile();
3013 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3014 unsigned Alignment = I.getAlignment();
3015 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3017 SmallVector<EVT, 4> ValueVTs;
3018 SmallVector<uint64_t, 4> Offsets;
3019 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3020 unsigned NumValues = ValueVTs.size();
3025 bool ConstantMemory = false;
3026 if (I.isVolatile() || NumValues > MaxParallelChains)
3027 // Serialize volatile loads with other side effects.
3029 else if (AA->pointsToConstantMemory(
3030 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3031 // Do not serialize (non-volatile) loads of constant memory with anything.
3032 Root = DAG.getEntryNode();
3033 ConstantMemory = true;
3035 // Do not serialize non-volatile loads against each other.
3036 Root = DAG.getRoot();
3039 SmallVector<SDValue, 4> Values(NumValues);
3040 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3042 EVT PtrVT = Ptr.getValueType();
3043 unsigned ChainI = 0;
3044 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3045 // Serializing loads here may result in excessive register pressure, and
3046 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3047 // could recover a bit by hoisting nodes upward in the chain by recognizing
3048 // they are side-effect free or do not alias. The optimizer should really
3049 // avoid this case by converting large object/array copies to llvm.memcpy
3050 // (MaxParallelChains should always remain as failsafe).
3051 if (ChainI == MaxParallelChains) {
3052 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3053 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3054 MVT::Other, &Chains[0], ChainI);
3058 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3060 DAG.getConstant(Offsets[i], PtrVT));
3061 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3062 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3063 isNonTemporal, Alignment, TBAAInfo);
3066 Chains[ChainI] = L.getValue(1);
3069 if (!ConstantMemory) {
3070 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3071 MVT::Other, &Chains[0], ChainI);
3075 PendingLoads.push_back(Chain);
3078 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3079 DAG.getVTList(&ValueVTs[0], NumValues),
3080 &Values[0], NumValues));
3083 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3084 const Value *SrcV = I.getOperand(0);
3085 const Value *PtrV = I.getOperand(1);
3087 SmallVector<EVT, 4> ValueVTs;
3088 SmallVector<uint64_t, 4> Offsets;
3089 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3090 unsigned NumValues = ValueVTs.size();
3094 // Get the lowered operands. Note that we do this after
3095 // checking if NumResults is zero, because with zero results
3096 // the operands won't have values in the map.
3097 SDValue Src = getValue(SrcV);
3098 SDValue Ptr = getValue(PtrV);
3100 SDValue Root = getRoot();
3101 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3103 EVT PtrVT = Ptr.getValueType();
3104 bool isVolatile = I.isVolatile();
3105 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3106 unsigned Alignment = I.getAlignment();
3107 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3109 unsigned ChainI = 0;
3110 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3111 // See visitLoad comments.
3112 if (ChainI == MaxParallelChains) {
3113 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3114 MVT::Other, &Chains[0], ChainI);
3118 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3119 DAG.getConstant(Offsets[i], PtrVT));
3120 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3121 SDValue(Src.getNode(), Src.getResNo() + i),
3122 Add, MachinePointerInfo(PtrV, Offsets[i]),
3123 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3124 Chains[ChainI] = St;
3127 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3128 MVT::Other, &Chains[0], ChainI);
3130 AssignOrderingToNode(StoreNode.getNode());
3131 DAG.setRoot(StoreNode);
3134 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3136 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3137 unsigned Intrinsic) {
3138 bool HasChain = !I.doesNotAccessMemory();
3139 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3141 // Build the operand list.
3142 SmallVector<SDValue, 8> Ops;
3143 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3145 // We don't need to serialize loads against other loads.
3146 Ops.push_back(DAG.getRoot());
3148 Ops.push_back(getRoot());
3152 // Info is set by getTgtMemInstrinsic
3153 TargetLowering::IntrinsicInfo Info;
3154 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3156 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3157 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3158 Info.opc == ISD::INTRINSIC_W_CHAIN)
3159 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3161 // Add all operands of the call to the operand list.
3162 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3163 SDValue Op = getValue(I.getArgOperand(i));
3164 assert(TLI.isTypeLegal(Op.getValueType()) &&
3165 "Intrinsic uses a non-legal type?");
3169 SmallVector<EVT, 4> ValueVTs;
3170 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3172 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3173 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3174 "Intrinsic uses a non-legal type?");
3179 ValueVTs.push_back(MVT::Other);
3181 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3185 if (IsTgtIntrinsic) {
3186 // This is target intrinsic that touches memory
3187 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3188 VTs, &Ops[0], Ops.size(),
3190 MachinePointerInfo(Info.ptrVal, Info.offset),
3191 Info.align, Info.vol,
3192 Info.readMem, Info.writeMem);
3193 } else if (!HasChain) {
3194 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3195 VTs, &Ops[0], Ops.size());
3196 } else if (!I.getType()->isVoidTy()) {
3197 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3198 VTs, &Ops[0], Ops.size());
3200 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3201 VTs, &Ops[0], Ops.size());
3205 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3207 PendingLoads.push_back(Chain);
3212 if (!I.getType()->isVoidTy()) {
3213 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3214 EVT VT = TLI.getValueType(PTy);
3215 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3218 setValue(&I, Result);
3222 /// GetSignificand - Get the significand and build it into a floating-point
3223 /// number with exponent of 1:
3225 /// Op = (Op & 0x007fffff) | 0x3f800000;
3227 /// where Op is the hexidecimal representation of floating point value.
3229 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3230 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3231 DAG.getConstant(0x007fffff, MVT::i32));
3232 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3233 DAG.getConstant(0x3f800000, MVT::i32));
3234 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3237 /// GetExponent - Get the exponent:
3239 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3241 /// where Op is the hexidecimal representation of floating point value.
3243 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3245 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3246 DAG.getConstant(0x7f800000, MVT::i32));
3247 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3248 DAG.getConstant(23, TLI.getPointerTy()));
3249 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3250 DAG.getConstant(127, MVT::i32));
3251 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3254 /// getF32Constant - Get 32-bit floating point constant.
3256 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3257 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3260 /// Inlined utility function to implement binary input atomic intrinsics for
3261 /// visitIntrinsicCall: I is a call instruction
3262 /// Op is the associated NodeType for I
3264 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3266 SDValue Root = getRoot();
3268 DAG.getAtomic(Op, getCurDebugLoc(),
3269 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3271 getValue(I.getArgOperand(0)),
3272 getValue(I.getArgOperand(1)),
3273 I.getArgOperand(0));
3275 DAG.setRoot(L.getValue(1));
3279 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3281 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3282 SDValue Op1 = getValue(I.getArgOperand(0));
3283 SDValue Op2 = getValue(I.getArgOperand(1));
3285 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3286 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3290 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3291 /// limited-precision mode.
3293 SelectionDAGBuilder::visitExp(const CallInst &I) {
3295 DebugLoc dl = getCurDebugLoc();
3297 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3298 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3299 SDValue Op = getValue(I.getArgOperand(0));
3301 // Put the exponent in the right bit position for later addition to the
3304 // #define LOG2OFe 1.4426950f
3305 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3306 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3307 getF32Constant(DAG, 0x3fb8aa3b));
3308 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3310 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3311 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3312 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3314 // IntegerPartOfX <<= 23;
3315 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3316 DAG.getConstant(23, TLI.getPointerTy()));
3318 if (LimitFloatPrecision <= 6) {
3319 // For floating-point precision of 6:
3321 // TwoToFractionalPartOfX =
3323 // (0.735607626f + 0.252464424f * x) * x;
3325 // error 0.0144103317, which is 6 bits
3326 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3327 getF32Constant(DAG, 0x3e814304));
3328 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3329 getF32Constant(DAG, 0x3f3c50c8));
3330 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3331 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3332 getF32Constant(DAG, 0x3f7f5e7e));
3333 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3335 // Add the exponent into the result in integer domain.
3336 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3337 TwoToFracPartOfX, IntegerPartOfX);
3339 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3340 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3341 // For floating-point precision of 12:
3343 // TwoToFractionalPartOfX =
3346 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3348 // 0.000107046256 error, which is 13 to 14 bits
3349 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3350 getF32Constant(DAG, 0x3da235e3));
3351 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3352 getF32Constant(DAG, 0x3e65b8f3));
3353 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3354 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3355 getF32Constant(DAG, 0x3f324b07));
3356 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3357 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3358 getF32Constant(DAG, 0x3f7ff8fd));
3359 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3361 // Add the exponent into the result in integer domain.
3362 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3363 TwoToFracPartOfX, IntegerPartOfX);
3365 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3366 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3367 // For floating-point precision of 18:
3369 // TwoToFractionalPartOfX =
3373 // (0.554906021e-1f +
3374 // (0.961591928e-2f +
3375 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3377 // error 2.47208000*10^(-7), which is better than 18 bits
3378 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3379 getF32Constant(DAG, 0x3924b03e));
3380 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3381 getF32Constant(DAG, 0x3ab24b87));
3382 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3383 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3384 getF32Constant(DAG, 0x3c1d8c17));
3385 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3386 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3387 getF32Constant(DAG, 0x3d634a1d));
3388 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3389 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3390 getF32Constant(DAG, 0x3e75fe14));
3391 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3392 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3393 getF32Constant(DAG, 0x3f317234));
3394 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3395 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3396 getF32Constant(DAG, 0x3f800000));
3397 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3400 // Add the exponent into the result in integer domain.
3401 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3402 TwoToFracPartOfX, IntegerPartOfX);
3404 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3407 // No special expansion.
3408 result = DAG.getNode(ISD::FEXP, dl,
3409 getValue(I.getArgOperand(0)).getValueType(),
3410 getValue(I.getArgOperand(0)));
3413 setValue(&I, result);
3416 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3417 /// limited-precision mode.
3419 SelectionDAGBuilder::visitLog(const CallInst &I) {
3421 DebugLoc dl = getCurDebugLoc();
3423 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3424 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3425 SDValue Op = getValue(I.getArgOperand(0));
3426 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3428 // Scale the exponent by log(2) [0.69314718f].
3429 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3430 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3431 getF32Constant(DAG, 0x3f317218));
3433 // Get the significand and build it into a floating-point number with
3435 SDValue X = GetSignificand(DAG, Op1, dl);
3437 if (LimitFloatPrecision <= 6) {
3438 // For floating-point precision of 6:
3442 // (1.4034025f - 0.23903021f * x) * x;
3444 // error 0.0034276066, which is better than 8 bits
3445 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3446 getF32Constant(DAG, 0xbe74c456));
3447 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3448 getF32Constant(DAG, 0x3fb3a2b1));
3449 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3450 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3451 getF32Constant(DAG, 0x3f949a29));
3453 result = DAG.getNode(ISD::FADD, dl,
3454 MVT::f32, LogOfExponent, LogOfMantissa);
3455 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3456 // For floating-point precision of 12:
3462 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3464 // error 0.000061011436, which is 14 bits
3465 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3466 getF32Constant(DAG, 0xbd67b6d6));
3467 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3468 getF32Constant(DAG, 0x3ee4f4b8));
3469 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3470 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3471 getF32Constant(DAG, 0x3fbc278b));
3472 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3473 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3474 getF32Constant(DAG, 0x40348e95));
3475 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3476 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3477 getF32Constant(DAG, 0x3fdef31a));
3479 result = DAG.getNode(ISD::FADD, dl,
3480 MVT::f32, LogOfExponent, LogOfMantissa);
3481 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3482 // For floating-point precision of 18:
3490 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3492 // error 0.0000023660568, which is better than 18 bits
3493 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3494 getF32Constant(DAG, 0xbc91e5ac));
3495 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3496 getF32Constant(DAG, 0x3e4350aa));
3497 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3498 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3499 getF32Constant(DAG, 0x3f60d3e3));
3500 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3501 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3502 getF32Constant(DAG, 0x4011cdf0));
3503 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3504 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3505 getF32Constant(DAG, 0x406cfd1c));
3506 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3507 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3508 getF32Constant(DAG, 0x408797cb));
3509 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3510 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3511 getF32Constant(DAG, 0x4006dcab));
3513 result = DAG.getNode(ISD::FADD, dl,
3514 MVT::f32, LogOfExponent, LogOfMantissa);
3517 // No special expansion.
3518 result = DAG.getNode(ISD::FLOG, dl,
3519 getValue(I.getArgOperand(0)).getValueType(),
3520 getValue(I.getArgOperand(0)));
3523 setValue(&I, result);
3526 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3527 /// limited-precision mode.
3529 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3531 DebugLoc dl = getCurDebugLoc();
3533 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3534 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3535 SDValue Op = getValue(I.getArgOperand(0));
3536 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3538 // Get the exponent.
3539 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3541 // Get the significand and build it into a floating-point number with
3543 SDValue X = GetSignificand(DAG, Op1, dl);
3545 // Different possible minimax approximations of significand in
3546 // floating-point for various degrees of accuracy over [1,2].
3547 if (LimitFloatPrecision <= 6) {
3548 // For floating-point precision of 6:
3550 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3552 // error 0.0049451742, which is more than 7 bits
3553 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3554 getF32Constant(DAG, 0xbeb08fe0));
3555 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3556 getF32Constant(DAG, 0x40019463));
3557 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3558 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3559 getF32Constant(DAG, 0x3fd6633d));
3561 result = DAG.getNode(ISD::FADD, dl,
3562 MVT::f32, LogOfExponent, Log2ofMantissa);
3563 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3564 // For floating-point precision of 12:
3570 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3572 // error 0.0000876136000, which is better than 13 bits
3573 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3574 getF32Constant(DAG, 0xbda7262e));
3575 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3576 getF32Constant(DAG, 0x3f25280b));
3577 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3578 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3579 getF32Constant(DAG, 0x4007b923));
3580 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3581 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3582 getF32Constant(DAG, 0x40823e2f));
3583 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3584 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3585 getF32Constant(DAG, 0x4020d29c));
3587 result = DAG.getNode(ISD::FADD, dl,
3588 MVT::f32, LogOfExponent, Log2ofMantissa);
3589 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3590 // For floating-point precision of 18:
3599 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3601 // error 0.0000018516, which is better than 18 bits
3602 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3603 getF32Constant(DAG, 0xbcd2769e));
3604 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3605 getF32Constant(DAG, 0x3e8ce0b9));
3606 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3607 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3608 getF32Constant(DAG, 0x3fa22ae7));
3609 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3610 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3611 getF32Constant(DAG, 0x40525723));
3612 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3613 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3614 getF32Constant(DAG, 0x40aaf200));
3615 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3616 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3617 getF32Constant(DAG, 0x40c39dad));
3618 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3619 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3620 getF32Constant(DAG, 0x4042902c));
3622 result = DAG.getNode(ISD::FADD, dl,
3623 MVT::f32, LogOfExponent, Log2ofMantissa);
3626 // No special expansion.
3627 result = DAG.getNode(ISD::FLOG2, dl,
3628 getValue(I.getArgOperand(0)).getValueType(),
3629 getValue(I.getArgOperand(0)));
3632 setValue(&I, result);
3635 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3636 /// limited-precision mode.
3638 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3640 DebugLoc dl = getCurDebugLoc();
3642 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3643 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3644 SDValue Op = getValue(I.getArgOperand(0));
3645 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3647 // Scale the exponent by log10(2) [0.30102999f].
3648 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3649 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3650 getF32Constant(DAG, 0x3e9a209a));
3652 // Get the significand and build it into a floating-point number with
3654 SDValue X = GetSignificand(DAG, Op1, dl);
3656 if (LimitFloatPrecision <= 6) {
3657 // For floating-point precision of 6:
3659 // Log10ofMantissa =
3661 // (0.60948995f - 0.10380950f * x) * x;
3663 // error 0.0014886165, which is 6 bits
3664 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3665 getF32Constant(DAG, 0xbdd49a13));
3666 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3667 getF32Constant(DAG, 0x3f1c0789));
3668 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3669 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3670 getF32Constant(DAG, 0x3f011300));
3672 result = DAG.getNode(ISD::FADD, dl,
3673 MVT::f32, LogOfExponent, Log10ofMantissa);
3674 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3675 // For floating-point precision of 12:
3677 // Log10ofMantissa =
3680 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3682 // error 0.00019228036, which is better than 12 bits
3683 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3684 getF32Constant(DAG, 0x3d431f31));
3685 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3686 getF32Constant(DAG, 0x3ea21fb2));
3687 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3688 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3689 getF32Constant(DAG, 0x3f6ae232));
3690 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3691 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3692 getF32Constant(DAG, 0x3f25f7c3));
3694 result = DAG.getNode(ISD::FADD, dl,
3695 MVT::f32, LogOfExponent, Log10ofMantissa);
3696 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3697 // For floating-point precision of 18:
3699 // Log10ofMantissa =
3704 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3706 // error 0.0000037995730, which is better than 18 bits
3707 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3708 getF32Constant(DAG, 0x3c5d51ce));
3709 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3710 getF32Constant(DAG, 0x3e00685a));
3711 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3712 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3713 getF32Constant(DAG, 0x3efb6798));
3714 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3715 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3716 getF32Constant(DAG, 0x3f88d192));
3717 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3718 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3719 getF32Constant(DAG, 0x3fc4316c));
3720 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3721 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3722 getF32Constant(DAG, 0x3f57ce70));
3724 result = DAG.getNode(ISD::FADD, dl,
3725 MVT::f32, LogOfExponent, Log10ofMantissa);
3728 // No special expansion.
3729 result = DAG.getNode(ISD::FLOG10, dl,
3730 getValue(I.getArgOperand(0)).getValueType(),
3731 getValue(I.getArgOperand(0)));
3734 setValue(&I, result);
3737 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3738 /// limited-precision mode.
3740 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3742 DebugLoc dl = getCurDebugLoc();
3744 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3745 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3746 SDValue Op = getValue(I.getArgOperand(0));
3748 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3750 // FractionalPartOfX = x - (float)IntegerPartOfX;
3751 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3752 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3754 // IntegerPartOfX <<= 23;
3755 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3756 DAG.getConstant(23, TLI.getPointerTy()));
3758 if (LimitFloatPrecision <= 6) {
3759 // For floating-point precision of 6:
3761 // TwoToFractionalPartOfX =
3763 // (0.735607626f + 0.252464424f * x) * x;
3765 // error 0.0144103317, which is 6 bits
3766 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3767 getF32Constant(DAG, 0x3e814304));
3768 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3769 getF32Constant(DAG, 0x3f3c50c8));
3770 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3771 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3772 getF32Constant(DAG, 0x3f7f5e7e));
3773 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3774 SDValue TwoToFractionalPartOfX =
3775 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3777 result = DAG.getNode(ISD::BITCAST, dl,
3778 MVT::f32, TwoToFractionalPartOfX);
3779 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3780 // For floating-point precision of 12:
3782 // TwoToFractionalPartOfX =
3785 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3787 // error 0.000107046256, which is 13 to 14 bits
3788 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3789 getF32Constant(DAG, 0x3da235e3));
3790 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3791 getF32Constant(DAG, 0x3e65b8f3));
3792 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3793 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3794 getF32Constant(DAG, 0x3f324b07));
3795 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3796 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3797 getF32Constant(DAG, 0x3f7ff8fd));
3798 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3799 SDValue TwoToFractionalPartOfX =
3800 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3802 result = DAG.getNode(ISD::BITCAST, dl,
3803 MVT::f32, TwoToFractionalPartOfX);
3804 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3805 // For floating-point precision of 18:
3807 // TwoToFractionalPartOfX =
3811 // (0.554906021e-1f +
3812 // (0.961591928e-2f +
3813 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3814 // error 2.47208000*10^(-7), which is better than 18 bits
3815 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3816 getF32Constant(DAG, 0x3924b03e));
3817 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3818 getF32Constant(DAG, 0x3ab24b87));
3819 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3820 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3821 getF32Constant(DAG, 0x3c1d8c17));
3822 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3823 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3824 getF32Constant(DAG, 0x3d634a1d));
3825 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3826 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3827 getF32Constant(DAG, 0x3e75fe14));
3828 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3829 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3830 getF32Constant(DAG, 0x3f317234));
3831 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3832 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3833 getF32Constant(DAG, 0x3f800000));
3834 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3835 SDValue TwoToFractionalPartOfX =
3836 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3838 result = DAG.getNode(ISD::BITCAST, dl,
3839 MVT::f32, TwoToFractionalPartOfX);
3842 // No special expansion.
3843 result = DAG.getNode(ISD::FEXP2, dl,
3844 getValue(I.getArgOperand(0)).getValueType(),
3845 getValue(I.getArgOperand(0)));
3848 setValue(&I, result);
3851 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3852 /// limited-precision mode with x == 10.0f.
3854 SelectionDAGBuilder::visitPow(const CallInst &I) {
3856 const Value *Val = I.getArgOperand(0);
3857 DebugLoc dl = getCurDebugLoc();
3858 bool IsExp10 = false;
3860 if (getValue(Val).getValueType() == MVT::f32 &&
3861 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3862 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3863 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3864 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3866 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3871 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3872 SDValue Op = getValue(I.getArgOperand(1));
3874 // Put the exponent in the right bit position for later addition to the
3877 // #define LOG2OF10 3.3219281f
3878 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3879 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3880 getF32Constant(DAG, 0x40549a78));
3881 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3883 // FractionalPartOfX = x - (float)IntegerPartOfX;
3884 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3885 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3887 // IntegerPartOfX <<= 23;
3888 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3889 DAG.getConstant(23, TLI.getPointerTy()));
3891 if (LimitFloatPrecision <= 6) {
3892 // For floating-point precision of 6:
3894 // twoToFractionalPartOfX =
3896 // (0.735607626f + 0.252464424f * x) * x;
3898 // error 0.0144103317, which is 6 bits
3899 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3900 getF32Constant(DAG, 0x3e814304));
3901 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3902 getF32Constant(DAG, 0x3f3c50c8));
3903 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3904 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3905 getF32Constant(DAG, 0x3f7f5e7e));
3906 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3907 SDValue TwoToFractionalPartOfX =
3908 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3910 result = DAG.getNode(ISD::BITCAST, dl,
3911 MVT::f32, TwoToFractionalPartOfX);
3912 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3913 // For floating-point precision of 12:
3915 // TwoToFractionalPartOfX =
3918 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3920 // error 0.000107046256, which is 13 to 14 bits
3921 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3922 getF32Constant(DAG, 0x3da235e3));
3923 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3924 getF32Constant(DAG, 0x3e65b8f3));
3925 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3926 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3927 getF32Constant(DAG, 0x3f324b07));
3928 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3929 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3930 getF32Constant(DAG, 0x3f7ff8fd));
3931 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3932 SDValue TwoToFractionalPartOfX =
3933 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3935 result = DAG.getNode(ISD::BITCAST, dl,
3936 MVT::f32, TwoToFractionalPartOfX);
3937 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3938 // For floating-point precision of 18:
3940 // TwoToFractionalPartOfX =
3944 // (0.554906021e-1f +
3945 // (0.961591928e-2f +
3946 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3947 // error 2.47208000*10^(-7), which is better than 18 bits
3948 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3949 getF32Constant(DAG, 0x3924b03e));
3950 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3951 getF32Constant(DAG, 0x3ab24b87));
3952 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3953 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3954 getF32Constant(DAG, 0x3c1d8c17));
3955 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3956 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3957 getF32Constant(DAG, 0x3d634a1d));
3958 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3959 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3960 getF32Constant(DAG, 0x3e75fe14));
3961 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3962 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3963 getF32Constant(DAG, 0x3f317234));
3964 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3965 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3966 getF32Constant(DAG, 0x3f800000));
3967 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3968 SDValue TwoToFractionalPartOfX =
3969 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3971 result = DAG.getNode(ISD::BITCAST, dl,
3972 MVT::f32, TwoToFractionalPartOfX);
3975 // No special expansion.
3976 result = DAG.getNode(ISD::FPOW, dl,
3977 getValue(I.getArgOperand(0)).getValueType(),
3978 getValue(I.getArgOperand(0)),
3979 getValue(I.getArgOperand(1)));
3982 setValue(&I, result);
3986 /// ExpandPowI - Expand a llvm.powi intrinsic.
3987 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3988 SelectionDAG &DAG) {
3989 // If RHS is a constant, we can expand this out to a multiplication tree,
3990 // otherwise we end up lowering to a call to __powidf2 (for example). When
3991 // optimizing for size, we only want to do this if the expansion would produce
3992 // a small number of multiplies, otherwise we do the full expansion.
3993 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3994 // Get the exponent as a positive value.
3995 unsigned Val = RHSC->getSExtValue();
3996 if ((int)Val < 0) Val = -Val;
3998 // powi(x, 0) -> 1.0
4000 return DAG.getConstantFP(1.0, LHS.getValueType());
4002 const Function *F = DAG.getMachineFunction().getFunction();
4003 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4004 // If optimizing for size, don't insert too many multiplies. This
4005 // inserts up to 5 multiplies.
4006 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4007 // We use the simple binary decomposition method to generate the multiply
4008 // sequence. There are more optimal ways to do this (for example,
4009 // powi(x,15) generates one more multiply than it should), but this has
4010 // the benefit of being both really simple and much better than a libcall.
4011 SDValue Res; // Logically starts equal to 1.0
4012 SDValue CurSquare = LHS;
4016 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4018 Res = CurSquare; // 1.0*CurSquare.
4021 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4022 CurSquare, CurSquare);
4026 // If the original was negative, invert the result, producing 1/(x*x*x).
4027 if (RHSC->getSExtValue() < 0)
4028 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4029 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4034 // Otherwise, expand to a libcall.
4035 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4038 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4039 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4040 /// At the end of instruction selection, they will be inserted to the entry BB.
4042 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4045 const Argument *Arg = dyn_cast<Argument>(V);
4049 MachineFunction &MF = DAG.getMachineFunction();
4050 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4051 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4053 // Ignore inlined function arguments here.
4054 DIVariable DV(Variable);
4055 if (DV.isInlinedFnArgument(MF.getFunction()))
4058 MachineBasicBlock *MBB = FuncInfo.MBB;
4059 if (MBB != &MF.front())
4063 if (Arg->hasByValAttr()) {
4064 // Byval arguments' frame index is recorded during argument lowering.
4065 // Use this info directly.
4066 Reg = TRI->getFrameRegister(MF);
4067 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4068 // If byval argument ofset is not recorded then ignore this.
4073 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4074 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4075 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4076 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4077 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4084 // Check if ValueMap has reg number.
4085 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4086 if (VMI != FuncInfo.ValueMap.end())
4090 if (!Reg && N.getNode()) {
4091 // Check if frame index is available.
4092 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4093 if (FrameIndexSDNode *FINode =
4094 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4095 Reg = TRI->getFrameRegister(MF);
4096 Offset = FINode->getIndex();
4103 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4104 TII->get(TargetOpcode::DBG_VALUE))
4105 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4106 FuncInfo.ArgDbgValues.push_back(&*MIB);
4110 // VisualStudio defines setjmp as _setjmp
4111 #if defined(_MSC_VER) && defined(setjmp) && \
4112 !defined(setjmp_undefined_for_msvc)
4113 # pragma push_macro("setjmp")
4115 # define setjmp_undefined_for_msvc
4118 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4119 /// we want to emit this as a call to a named external function, return the name
4120 /// otherwise lower it and return null.
4122 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4123 DebugLoc dl = getCurDebugLoc();
4126 switch (Intrinsic) {
4128 // By default, turn this into a target intrinsic node.
4129 visitTargetIntrinsic(I, Intrinsic);
4131 case Intrinsic::vastart: visitVAStart(I); return 0;
4132 case Intrinsic::vaend: visitVAEnd(I); return 0;
4133 case Intrinsic::vacopy: visitVACopy(I); return 0;
4134 case Intrinsic::returnaddress:
4135 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4136 getValue(I.getArgOperand(0))));
4138 case Intrinsic::frameaddress:
4139 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4140 getValue(I.getArgOperand(0))));
4142 case Intrinsic::setjmp:
4143 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4144 case Intrinsic::longjmp:
4145 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4146 case Intrinsic::memcpy: {
4147 // Assert for address < 256 since we support only user defined address
4149 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4151 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4153 "Unknown address space");
4154 SDValue Op1 = getValue(I.getArgOperand(0));
4155 SDValue Op2 = getValue(I.getArgOperand(1));
4156 SDValue Op3 = getValue(I.getArgOperand(2));
4157 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4158 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4159 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4160 MachinePointerInfo(I.getArgOperand(0)),
4161 MachinePointerInfo(I.getArgOperand(1))));
4164 case Intrinsic::memset: {
4165 // Assert for address < 256 since we support only user defined address
4167 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4169 "Unknown address space");
4170 SDValue Op1 = getValue(I.getArgOperand(0));
4171 SDValue Op2 = getValue(I.getArgOperand(1));
4172 SDValue Op3 = getValue(I.getArgOperand(2));
4173 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4174 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4175 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4176 MachinePointerInfo(I.getArgOperand(0))));
4179 case Intrinsic::memmove: {
4180 // Assert for address < 256 since we support only user defined address
4182 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4184 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4186 "Unknown address space");
4187 SDValue Op1 = getValue(I.getArgOperand(0));
4188 SDValue Op2 = getValue(I.getArgOperand(1));
4189 SDValue Op3 = getValue(I.getArgOperand(2));
4190 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4191 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4192 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4193 MachinePointerInfo(I.getArgOperand(0)),
4194 MachinePointerInfo(I.getArgOperand(1))));
4197 case Intrinsic::dbg_declare: {
4198 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4199 MDNode *Variable = DI.getVariable();
4200 const Value *Address = DI.getAddress();
4201 if (!Address || !DIVariable(DI.getVariable()).Verify())
4204 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4205 // but do not always have a corresponding SDNode built. The SDNodeOrder
4206 // absolute, but not relative, values are different depending on whether
4207 // debug info exists.
4210 // Check if address has undef value.
4211 if (isa<UndefValue>(Address) ||
4212 (Address->use_empty() && !isa<Argument>(Address))) {
4213 DEBUG(dbgs() << "Dropping debug info for " << DI);
4217 SDValue &N = NodeMap[Address];
4218 if (!N.getNode() && isa<Argument>(Address))
4219 // Check unused arguments map.
4220 N = UnusedArgNodeMap[Address];
4223 // Parameters are handled specially.
4225 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4226 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4227 Address = BCI->getOperand(0);
4228 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4230 if (isParameter && !AI) {
4231 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4233 // Byval parameter. We have a frame index at this point.
4234 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4235 0, dl, SDNodeOrder);
4237 // Can't do anything with other non-AI cases yet. This might be a
4238 // parameter of a callee function that got inlined, for example.
4239 DEBUG(dbgs() << "Dropping debug info for " << DI);
4243 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4244 0, dl, SDNodeOrder);
4246 // Can't do anything with other non-AI cases yet.
4247 DEBUG(dbgs() << "Dropping debug info for " << DI);
4250 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4252 // If Address is an argument then try to emit its dbg value using
4253 // virtual register info from the FuncInfo.ValueMap.
4254 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4255 // If variable is pinned by a alloca in dominating bb then
4256 // use StaticAllocaMap.
4257 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4258 if (AI->getParent() != DI.getParent()) {
4259 DenseMap<const AllocaInst*, int>::iterator SI =
4260 FuncInfo.StaticAllocaMap.find(AI);
4261 if (SI != FuncInfo.StaticAllocaMap.end()) {
4262 SDV = DAG.getDbgValue(Variable, SI->second,
4263 0, dl, SDNodeOrder);
4264 DAG.AddDbgValue(SDV, 0, false);
4269 DEBUG(dbgs() << "Dropping debug info for " << DI);
4274 case Intrinsic::dbg_value: {
4275 const DbgValueInst &DI = cast<DbgValueInst>(I);
4276 if (!DIVariable(DI.getVariable()).Verify())
4279 MDNode *Variable = DI.getVariable();
4280 uint64_t Offset = DI.getOffset();
4281 const Value *V = DI.getValue();
4285 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4286 // but do not always have a corresponding SDNode built. The SDNodeOrder
4287 // absolute, but not relative, values are different depending on whether
4288 // debug info exists.
4291 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4292 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4293 DAG.AddDbgValue(SDV, 0, false);
4295 // Do not use getValue() in here; we don't want to generate code at
4296 // this point if it hasn't been done yet.
4297 SDValue N = NodeMap[V];
4298 if (!N.getNode() && isa<Argument>(V))
4299 // Check unused arguments map.
4300 N = UnusedArgNodeMap[V];
4302 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4303 SDV = DAG.getDbgValue(Variable, N.getNode(),
4304 N.getResNo(), Offset, dl, SDNodeOrder);
4305 DAG.AddDbgValue(SDV, N.getNode(), false);
4307 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4308 // Do not call getValue(V) yet, as we don't want to generate code.
4309 // Remember it for later.
4310 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4311 DanglingDebugInfoMap[V] = DDI;
4313 // We may expand this to cover more cases. One case where we have no
4314 // data available is an unreferenced parameter.
4315 DEBUG(dbgs() << "Dropping debug info for " << DI);
4319 // Build a debug info table entry.
4320 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4321 V = BCI->getOperand(0);
4322 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4323 // Don't handle byval struct arguments or VLAs, for example.
4326 DenseMap<const AllocaInst*, int>::iterator SI =
4327 FuncInfo.StaticAllocaMap.find(AI);
4328 if (SI == FuncInfo.StaticAllocaMap.end())
4330 int FI = SI->second;
4332 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4333 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4334 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4337 case Intrinsic::eh_exception: {
4338 // Insert the EXCEPTIONADDR instruction.
4339 assert(FuncInfo.MBB->isLandingPad() &&
4340 "Call to eh.exception not in landing pad!");
4341 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4343 Ops[0] = DAG.getRoot();
4344 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4346 DAG.setRoot(Op.getValue(1));
4350 case Intrinsic::eh_selector: {
4351 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4352 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4353 if (CallMBB->isLandingPad())
4354 AddCatchInfo(I, &MMI, CallMBB);
4357 FuncInfo.CatchInfoLost.insert(&I);
4359 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4360 unsigned Reg = TLI.getExceptionSelectorRegister();
4361 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4364 // Insert the EHSELECTION instruction.
4365 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4367 Ops[0] = getValue(I.getArgOperand(0));
4369 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4370 DAG.setRoot(Op.getValue(1));
4371 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4375 case Intrinsic::eh_typeid_for: {
4376 // Find the type id for the given typeinfo.
4377 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4378 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4379 Res = DAG.getConstant(TypeID, MVT::i32);
4384 case Intrinsic::eh_return_i32:
4385 case Intrinsic::eh_return_i64:
4386 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4387 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4390 getValue(I.getArgOperand(0)),
4391 getValue(I.getArgOperand(1))));
4393 case Intrinsic::eh_unwind_init:
4394 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4396 case Intrinsic::eh_dwarf_cfa: {
4397 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4398 TLI.getPointerTy());
4399 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4401 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4402 TLI.getPointerTy()),
4404 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4406 DAG.getConstant(0, TLI.getPointerTy()));
4407 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4411 case Intrinsic::eh_sjlj_callsite: {
4412 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4413 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4414 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4415 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4417 MMI.setCurrentCallSite(CI->getZExtValue());
4420 case Intrinsic::eh_sjlj_setjmp: {
4421 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4422 getValue(I.getArgOperand(0))));
4425 case Intrinsic::eh_sjlj_longjmp: {
4426 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4427 getRoot(), getValue(I.getArgOperand(0))));
4430 case Intrinsic::eh_sjlj_dispatch_setup: {
4431 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4432 getRoot(), getValue(I.getArgOperand(0))));
4436 case Intrinsic::x86_mmx_pslli_w:
4437 case Intrinsic::x86_mmx_pslli_d:
4438 case Intrinsic::x86_mmx_pslli_q:
4439 case Intrinsic::x86_mmx_psrli_w:
4440 case Intrinsic::x86_mmx_psrli_d:
4441 case Intrinsic::x86_mmx_psrli_q:
4442 case Intrinsic::x86_mmx_psrai_w:
4443 case Intrinsic::x86_mmx_psrai_d: {
4444 SDValue ShAmt = getValue(I.getArgOperand(1));
4445 if (isa<ConstantSDNode>(ShAmt)) {
4446 visitTargetIntrinsic(I, Intrinsic);
4449 unsigned NewIntrinsic = 0;
4450 EVT ShAmtVT = MVT::v2i32;
4451 switch (Intrinsic) {
4452 case Intrinsic::x86_mmx_pslli_w:
4453 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4455 case Intrinsic::x86_mmx_pslli_d:
4456 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4458 case Intrinsic::x86_mmx_pslli_q:
4459 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4461 case Intrinsic::x86_mmx_psrli_w:
4462 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4464 case Intrinsic::x86_mmx_psrli_d:
4465 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4467 case Intrinsic::x86_mmx_psrli_q:
4468 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4470 case Intrinsic::x86_mmx_psrai_w:
4471 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4473 case Intrinsic::x86_mmx_psrai_d:
4474 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4476 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4479 // The vector shift intrinsics with scalars uses 32b shift amounts but
4480 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4482 // We must do this early because v2i32 is not a legal type.
4483 DebugLoc dl = getCurDebugLoc();
4486 ShOps[1] = DAG.getConstant(0, MVT::i32);
4487 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4488 EVT DestVT = TLI.getValueType(I.getType());
4489 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4490 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4491 DAG.getConstant(NewIntrinsic, MVT::i32),
4492 getValue(I.getArgOperand(0)), ShAmt);
4496 case Intrinsic::convertff:
4497 case Intrinsic::convertfsi:
4498 case Intrinsic::convertfui:
4499 case Intrinsic::convertsif:
4500 case Intrinsic::convertuif:
4501 case Intrinsic::convertss:
4502 case Intrinsic::convertsu:
4503 case Intrinsic::convertus:
4504 case Intrinsic::convertuu: {
4505 ISD::CvtCode Code = ISD::CVT_INVALID;
4506 switch (Intrinsic) {
4507 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4508 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4509 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4510 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4511 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4512 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4513 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4514 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4515 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4517 EVT DestVT = TLI.getValueType(I.getType());
4518 const Value *Op1 = I.getArgOperand(0);
4519 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4520 DAG.getValueType(DestVT),
4521 DAG.getValueType(getValue(Op1).getValueType()),
4522 getValue(I.getArgOperand(1)),
4523 getValue(I.getArgOperand(2)),
4528 case Intrinsic::sqrt:
4529 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4530 getValue(I.getArgOperand(0)).getValueType(),
4531 getValue(I.getArgOperand(0))));
4533 case Intrinsic::powi:
4534 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4535 getValue(I.getArgOperand(1)), DAG));
4537 case Intrinsic::sin:
4538 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4539 getValue(I.getArgOperand(0)).getValueType(),
4540 getValue(I.getArgOperand(0))));
4542 case Intrinsic::cos:
4543 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4544 getValue(I.getArgOperand(0)).getValueType(),
4545 getValue(I.getArgOperand(0))));
4547 case Intrinsic::log:
4550 case Intrinsic::log2:
4553 case Intrinsic::log10:
4556 case Intrinsic::exp:
4559 case Intrinsic::exp2:
4562 case Intrinsic::pow:
4565 case Intrinsic::convert_to_fp16:
4566 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4567 MVT::i16, getValue(I.getArgOperand(0))));
4569 case Intrinsic::convert_from_fp16:
4570 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4571 MVT::f32, getValue(I.getArgOperand(0))));
4573 case Intrinsic::pcmarker: {
4574 SDValue Tmp = getValue(I.getArgOperand(0));
4575 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4578 case Intrinsic::readcyclecounter: {
4579 SDValue Op = getRoot();
4580 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4581 DAG.getVTList(MVT::i64, MVT::Other),
4584 DAG.setRoot(Res.getValue(1));
4587 case Intrinsic::bswap:
4588 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4589 getValue(I.getArgOperand(0)).getValueType(),
4590 getValue(I.getArgOperand(0))));
4592 case Intrinsic::cttz: {
4593 SDValue Arg = getValue(I.getArgOperand(0));
4594 EVT Ty = Arg.getValueType();
4595 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4598 case Intrinsic::ctlz: {
4599 SDValue Arg = getValue(I.getArgOperand(0));
4600 EVT Ty = Arg.getValueType();
4601 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4604 case Intrinsic::ctpop: {
4605 SDValue Arg = getValue(I.getArgOperand(0));
4606 EVT Ty = Arg.getValueType();
4607 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4610 case Intrinsic::stacksave: {
4611 SDValue Op = getRoot();
4612 Res = DAG.getNode(ISD::STACKSAVE, dl,
4613 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4615 DAG.setRoot(Res.getValue(1));
4618 case Intrinsic::stackrestore: {
4619 Res = getValue(I.getArgOperand(0));
4620 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4623 case Intrinsic::stackprotector: {
4624 // Emit code into the DAG to store the stack guard onto the stack.
4625 MachineFunction &MF = DAG.getMachineFunction();
4626 MachineFrameInfo *MFI = MF.getFrameInfo();
4627 EVT PtrTy = TLI.getPointerTy();
4629 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4630 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4632 int FI = FuncInfo.StaticAllocaMap[Slot];
4633 MFI->setStackProtectorIndex(FI);
4635 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4637 // Store the stack protector onto the stack.
4638 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4639 MachinePointerInfo::getFixedStack(FI),
4645 case Intrinsic::objectsize: {
4646 // If we don't know by now, we're never going to know.
4647 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4649 assert(CI && "Non-constant type in __builtin_object_size?");
4651 SDValue Arg = getValue(I.getCalledValue());
4652 EVT Ty = Arg.getValueType();
4655 Res = DAG.getConstant(-1ULL, Ty);
4657 Res = DAG.getConstant(0, Ty);
4662 case Intrinsic::var_annotation:
4663 // Discard annotate attributes
4666 case Intrinsic::init_trampoline: {
4667 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4671 Ops[1] = getValue(I.getArgOperand(0));
4672 Ops[2] = getValue(I.getArgOperand(1));
4673 Ops[3] = getValue(I.getArgOperand(2));
4674 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4675 Ops[5] = DAG.getSrcValue(F);
4677 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4678 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4682 DAG.setRoot(Res.getValue(1));
4685 case Intrinsic::gcroot:
4687 const Value *Alloca = I.getArgOperand(0);
4688 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4690 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4691 GFI->addStackRoot(FI->getIndex(), TypeMap);
4694 case Intrinsic::gcread:
4695 case Intrinsic::gcwrite:
4696 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4698 case Intrinsic::flt_rounds:
4699 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4701 case Intrinsic::trap:
4702 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4704 case Intrinsic::uadd_with_overflow:
4705 return implVisitAluOverflow(I, ISD::UADDO);
4706 case Intrinsic::sadd_with_overflow:
4707 return implVisitAluOverflow(I, ISD::SADDO);
4708 case Intrinsic::usub_with_overflow:
4709 return implVisitAluOverflow(I, ISD::USUBO);
4710 case Intrinsic::ssub_with_overflow:
4711 return implVisitAluOverflow(I, ISD::SSUBO);
4712 case Intrinsic::umul_with_overflow:
4713 return implVisitAluOverflow(I, ISD::UMULO);
4714 case Intrinsic::smul_with_overflow:
4715 return implVisitAluOverflow(I, ISD::SMULO);
4717 case Intrinsic::prefetch: {
4719 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4721 Ops[1] = getValue(I.getArgOperand(0));
4722 Ops[2] = getValue(I.getArgOperand(1));
4723 Ops[3] = getValue(I.getArgOperand(2));
4724 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4725 DAG.getVTList(MVT::Other),
4727 EVT::getIntegerVT(*Context, 8),
4728 MachinePointerInfo(I.getArgOperand(0)),
4730 false, /* volatile */
4732 rw==1)); /* write */
4735 case Intrinsic::memory_barrier: {
4738 for (int x = 1; x < 6; ++x)
4739 Ops[x] = getValue(I.getArgOperand(x - 1));
4741 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4744 case Intrinsic::atomic_cmp_swap: {
4745 SDValue Root = getRoot();
4747 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4748 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4750 getValue(I.getArgOperand(0)),
4751 getValue(I.getArgOperand(1)),
4752 getValue(I.getArgOperand(2)),
4753 MachinePointerInfo(I.getArgOperand(0)));
4755 DAG.setRoot(L.getValue(1));
4758 case Intrinsic::atomic_load_add:
4759 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4760 case Intrinsic::atomic_load_sub:
4761 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4762 case Intrinsic::atomic_load_or:
4763 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4764 case Intrinsic::atomic_load_xor:
4765 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4766 case Intrinsic::atomic_load_and:
4767 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4768 case Intrinsic::atomic_load_nand:
4769 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4770 case Intrinsic::atomic_load_max:
4771 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4772 case Intrinsic::atomic_load_min:
4773 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4774 case Intrinsic::atomic_load_umin:
4775 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4776 case Intrinsic::atomic_load_umax:
4777 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4778 case Intrinsic::atomic_swap:
4779 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4781 case Intrinsic::invariant_start:
4782 case Intrinsic::lifetime_start:
4783 // Discard region information.
4784 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4786 case Intrinsic::invariant_end:
4787 case Intrinsic::lifetime_end:
4788 // Discard region information.
4793 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4795 MachineBasicBlock *LandingPad) {
4796 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4797 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4798 const Type *RetTy = FTy->getReturnType();
4799 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4800 MCSymbol *BeginLabel = 0;
4802 TargetLowering::ArgListTy Args;
4803 TargetLowering::ArgListEntry Entry;
4804 Args.reserve(CS.arg_size());
4806 // Check whether the function can return without sret-demotion.
4807 SmallVector<ISD::OutputArg, 4> Outs;
4808 SmallVector<uint64_t, 4> Offsets;
4809 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4810 Outs, TLI, &Offsets);
4812 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4813 FTy->isVarArg(), Outs, FTy->getContext());
4815 SDValue DemoteStackSlot;
4816 int DemoteStackIdx = -100;
4818 if (!CanLowerReturn) {
4819 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4820 FTy->getReturnType());
4821 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4822 FTy->getReturnType());
4823 MachineFunction &MF = DAG.getMachineFunction();
4824 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4825 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4827 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4828 Entry.Node = DemoteStackSlot;
4829 Entry.Ty = StackSlotPtrType;
4830 Entry.isSExt = false;
4831 Entry.isZExt = false;
4832 Entry.isInReg = false;
4833 Entry.isSRet = true;
4834 Entry.isNest = false;
4835 Entry.isByVal = false;
4836 Entry.Alignment = Align;
4837 Args.push_back(Entry);
4838 RetTy = Type::getVoidTy(FTy->getContext());
4841 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4843 SDValue ArgNode = getValue(*i);
4844 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4846 unsigned attrInd = i - CS.arg_begin() + 1;
4847 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4848 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4849 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4850 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4851 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4852 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4853 Entry.Alignment = CS.getParamAlignment(attrInd);
4854 Args.push_back(Entry);
4858 // Insert a label before the invoke call to mark the try range. This can be
4859 // used to detect deletion of the invoke via the MachineModuleInfo.
4860 BeginLabel = MMI.getContext().CreateTempSymbol();
4862 // For SjLj, keep track of which landing pads go with which invokes
4863 // so as to maintain the ordering of pads in the LSDA.
4864 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4865 if (CallSiteIndex) {
4866 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4867 // Now that the call site is handled, stop tracking it.
4868 MMI.setCurrentCallSite(0);
4871 // Both PendingLoads and PendingExports must be flushed here;
4872 // this call might not return.
4874 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4877 // Check if target-independent constraints permit a tail call here.
4878 // Target-dependent constraints are checked within TLI.LowerCallTo.
4880 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4883 // If there's a possibility that fast-isel has already selected some amount
4884 // of the current basic block, don't emit a tail call.
4885 if (isTailCall && EnableFastISel)
4888 std::pair<SDValue,SDValue> Result =
4889 TLI.LowerCallTo(getRoot(), RetTy,
4890 CS.paramHasAttr(0, Attribute::SExt),
4891 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4892 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4893 CS.getCallingConv(),
4895 !CS.getInstruction()->use_empty(),
4896 Callee, Args, DAG, getCurDebugLoc());
4897 assert((isTailCall || Result.second.getNode()) &&
4898 "Non-null chain expected with non-tail call!");
4899 assert((Result.second.getNode() || !Result.first.getNode()) &&
4900 "Null value expected with tail call!");
4901 if (Result.first.getNode()) {
4902 setValue(CS.getInstruction(), Result.first);
4903 } else if (!CanLowerReturn && Result.second.getNode()) {
4904 // The instruction result is the result of loading from the
4905 // hidden sret parameter.
4906 SmallVector<EVT, 1> PVTs;
4907 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4909 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4910 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4911 EVT PtrVT = PVTs[0];
4912 unsigned NumValues = Outs.size();
4913 SmallVector<SDValue, 4> Values(NumValues);
4914 SmallVector<SDValue, 4> Chains(NumValues);
4916 for (unsigned i = 0; i < NumValues; ++i) {
4917 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4919 DAG.getConstant(Offsets[i], PtrVT));
4920 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4922 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4925 Chains[i] = L.getValue(1);
4928 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4929 MVT::Other, &Chains[0], NumValues);
4930 PendingLoads.push_back(Chain);
4932 // Collect the legal value parts into potentially illegal values
4933 // that correspond to the original function's return values.
4934 SmallVector<EVT, 4> RetTys;
4935 RetTy = FTy->getReturnType();
4936 ComputeValueVTs(TLI, RetTy, RetTys);
4937 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4938 SmallVector<SDValue, 4> ReturnValues;
4939 unsigned CurReg = 0;
4940 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4942 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4943 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4945 SDValue ReturnValue =
4946 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4947 RegisterVT, VT, AssertOp);
4948 ReturnValues.push_back(ReturnValue);
4952 setValue(CS.getInstruction(),
4953 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4954 DAG.getVTList(&RetTys[0], RetTys.size()),
4955 &ReturnValues[0], ReturnValues.size()));
4959 // As a special case, a null chain means that a tail call has been emitted and
4960 // the DAG root is already updated.
4961 if (Result.second.getNode())
4962 DAG.setRoot(Result.second);
4967 // Insert a label at the end of the invoke call to mark the try range. This
4968 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4969 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4970 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4972 // Inform MachineModuleInfo of range.
4973 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4977 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4978 /// value is equal or not-equal to zero.
4979 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4980 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4982 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4983 if (IC->isEquality())
4984 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4985 if (C->isNullValue())
4987 // Unknown instruction.
4993 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4995 SelectionDAGBuilder &Builder) {
4997 // Check to see if this load can be trivially constant folded, e.g. if the
4998 // input is from a string literal.
4999 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5000 // Cast pointer to the type we really want to load.
5001 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5002 PointerType::getUnqual(LoadTy));
5004 if (const Constant *LoadCst =
5005 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5007 return Builder.getValue(LoadCst);
5010 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5011 // still constant memory, the input chain can be the entry node.
5013 bool ConstantMemory = false;
5015 // Do not serialize (non-volatile) loads of constant memory with anything.
5016 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5017 Root = Builder.DAG.getEntryNode();
5018 ConstantMemory = true;
5020 // Do not serialize non-volatile loads against each other.
5021 Root = Builder.DAG.getRoot();
5024 SDValue Ptr = Builder.getValue(PtrVal);
5025 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5026 Ptr, MachinePointerInfo(PtrVal),
5028 false /*nontemporal*/, 1 /* align=1 */);
5030 if (!ConstantMemory)
5031 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5036 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5037 /// If so, return true and lower it, otherwise return false and it will be
5038 /// lowered like a normal call.
5039 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5040 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5041 if (I.getNumArgOperands() != 3)
5044 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5045 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5046 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5047 !I.getType()->isIntegerTy())
5050 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5052 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5053 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5054 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5055 bool ActuallyDoIt = true;
5058 switch (Size->getZExtValue()) {
5060 LoadVT = MVT::Other;
5062 ActuallyDoIt = false;
5066 LoadTy = Type::getInt16Ty(Size->getContext());
5070 LoadTy = Type::getInt32Ty(Size->getContext());
5074 LoadTy = Type::getInt64Ty(Size->getContext());
5078 LoadVT = MVT::v4i32;
5079 LoadTy = Type::getInt32Ty(Size->getContext());
5080 LoadTy = VectorType::get(LoadTy, 4);
5085 // This turns into unaligned loads. We only do this if the target natively
5086 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5087 // we'll only produce a small number of byte loads.
5089 // Require that we can find a legal MVT, and only do this if the target
5090 // supports unaligned loads of that type. Expanding into byte loads would
5092 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5093 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5094 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5095 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5096 ActuallyDoIt = false;
5100 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5101 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5103 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5105 EVT CallVT = TLI.getValueType(I.getType(), true);
5106 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5116 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5117 // Handle inline assembly differently.
5118 if (isa<InlineAsm>(I.getCalledValue())) {
5123 // See if any floating point values are being passed to this function. This is
5124 // used to emit an undefined reference to fltused on Windows.
5125 const FunctionType *FT =
5126 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5127 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5128 if (FT->isVarArg() &&
5129 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5130 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5131 const Type* T = I.getArgOperand(i)->getType();
5132 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5134 if (!i->isFloatingPointTy()) continue;
5135 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5141 const char *RenameFn = 0;
5142 if (Function *F = I.getCalledFunction()) {
5143 if (F->isDeclaration()) {
5144 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5145 if (unsigned IID = II->getIntrinsicID(F)) {
5146 RenameFn = visitIntrinsicCall(I, IID);
5151 if (unsigned IID = F->getIntrinsicID()) {
5152 RenameFn = visitIntrinsicCall(I, IID);
5158 // Check for well-known libc/libm calls. If the function is internal, it
5159 // can't be a library call.
5160 if (!F->hasLocalLinkage() && F->hasName()) {
5161 StringRef Name = F->getName();
5162 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5163 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5164 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5165 I.getType() == I.getArgOperand(0)->getType() &&
5166 I.getType() == I.getArgOperand(1)->getType()) {
5167 SDValue LHS = getValue(I.getArgOperand(0));
5168 SDValue RHS = getValue(I.getArgOperand(1));
5169 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5170 LHS.getValueType(), LHS, RHS));
5173 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5174 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5175 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5176 I.getType() == I.getArgOperand(0)->getType()) {
5177 SDValue Tmp = getValue(I.getArgOperand(0));
5178 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5179 Tmp.getValueType(), Tmp));
5182 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5183 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5184 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5185 I.getType() == I.getArgOperand(0)->getType() &&
5186 I.onlyReadsMemory()) {
5187 SDValue Tmp = getValue(I.getArgOperand(0));
5188 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5189 Tmp.getValueType(), Tmp));
5192 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5193 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5194 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5195 I.getType() == I.getArgOperand(0)->getType() &&
5196 I.onlyReadsMemory()) {
5197 SDValue Tmp = getValue(I.getArgOperand(0));
5198 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5199 Tmp.getValueType(), Tmp));
5202 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5203 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5204 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5205 I.getType() == I.getArgOperand(0)->getType() &&
5206 I.onlyReadsMemory()) {
5207 SDValue Tmp = getValue(I.getArgOperand(0));
5208 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5209 Tmp.getValueType(), Tmp));
5212 } else if (Name == "memcmp") {
5213 if (visitMemCmpCall(I))
5221 Callee = getValue(I.getCalledValue());
5223 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5225 // Check if we can potentially perform a tail call. More detailed checking is
5226 // be done within LowerCallTo, after more information about the call is known.
5227 LowerCallTo(&I, Callee, I.isTailCall());
5232 /// AsmOperandInfo - This contains information for each constraint that we are
5234 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5235 public TargetLowering::AsmOperandInfo {
5237 /// CallOperand - If this is the result output operand or a clobber
5238 /// this is null, otherwise it is the incoming operand to the CallInst.
5239 /// This gets modified as the asm is processed.
5240 SDValue CallOperand;
5242 /// AssignedRegs - If this is a register or register class operand, this
5243 /// contains the set of register corresponding to the operand.
5244 RegsForValue AssignedRegs;
5246 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5247 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5250 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5251 /// busy in OutputRegs/InputRegs.
5252 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5253 std::set<unsigned> &OutputRegs,
5254 std::set<unsigned> &InputRegs,
5255 const TargetRegisterInfo &TRI) const {
5257 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5258 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5261 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5262 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5266 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5267 /// corresponds to. If there is no Value* for this operand, it returns
5269 EVT getCallOperandValEVT(LLVMContext &Context,
5270 const TargetLowering &TLI,
5271 const TargetData *TD) const {
5272 if (CallOperandVal == 0) return MVT::Other;
5274 if (isa<BasicBlock>(CallOperandVal))
5275 return TLI.getPointerTy();
5277 const llvm::Type *OpTy = CallOperandVal->getType();
5279 // If this is an indirect operand, the operand is a pointer to the
5282 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5284 report_fatal_error("Indirect operand for inline asm not a pointer!");
5285 OpTy = PtrTy->getElementType();
5288 // If OpTy is not a single value, it may be a struct/union that we
5289 // can tile with integers.
5290 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5291 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5300 OpTy = IntegerType::get(Context, BitSize);
5305 return TLI.getValueType(OpTy, true);
5309 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5311 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5312 const TargetRegisterInfo &TRI) {
5313 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5315 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5316 for (; *Aliases; ++Aliases)
5317 Regs.insert(*Aliases);
5321 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5323 } // end llvm namespace.
5325 /// isAllocatableRegister - If the specified register is safe to allocate,
5326 /// i.e. it isn't a stack pointer or some other special register, return the
5327 /// register class for the register. Otherwise, return null.
5328 static const TargetRegisterClass *
5329 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5330 const TargetLowering &TLI,
5331 const TargetRegisterInfo *TRI) {
5332 EVT FoundVT = MVT::Other;
5333 const TargetRegisterClass *FoundRC = 0;
5334 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5335 E = TRI->regclass_end(); RCI != E; ++RCI) {
5336 EVT ThisVT = MVT::Other;
5338 const TargetRegisterClass *RC = *RCI;
5339 // If none of the value types for this register class are valid, we
5340 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5341 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5343 if (TLI.isTypeLegal(*I)) {
5344 // If we have already found this register in a different register class,
5345 // choose the one with the largest VT specified. For example, on
5346 // PowerPC, we favor f64 register classes over f32.
5347 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5354 if (ThisVT == MVT::Other) continue;
5356 // NOTE: This isn't ideal. In particular, this might allocate the
5357 // frame pointer in functions that need it (due to them not being taken
5358 // out of allocation, because a variable sized allocation hasn't been seen
5359 // yet). This is a slight code pessimization, but should still work.
5360 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5361 E = RC->allocation_order_end(MF); I != E; ++I)
5363 // We found a matching register class. Keep looking at others in case
5364 // we find one with larger registers that this physreg is also in.
5373 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5374 /// specified operand. We prefer to assign virtual registers, to allow the
5375 /// register allocator to handle the assignment process. However, if the asm
5376 /// uses features that we can't model on machineinstrs, we have SDISel do the
5377 /// allocation. This produces generally horrible, but correct, code.
5379 /// OpInfo describes the operand.
5380 /// Input and OutputRegs are the set of already allocated physical registers.
5382 void SelectionDAGBuilder::
5383 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5384 std::set<unsigned> &OutputRegs,
5385 std::set<unsigned> &InputRegs) {
5386 LLVMContext &Context = FuncInfo.Fn->getContext();
5388 // Compute whether this value requires an input register, an output register,
5390 bool isOutReg = false;
5391 bool isInReg = false;
5392 switch (OpInfo.Type) {
5393 case InlineAsm::isOutput:
5396 // If there is an input constraint that matches this, we need to reserve
5397 // the input register so no other inputs allocate to it.
5398 isInReg = OpInfo.hasMatchingInput();
5400 case InlineAsm::isInput:
5404 case InlineAsm::isClobber:
5411 MachineFunction &MF = DAG.getMachineFunction();
5412 SmallVector<unsigned, 4> Regs;
5414 // If this is a constraint for a single physreg, or a constraint for a
5415 // register class, find it.
5416 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5417 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5418 OpInfo.ConstraintVT);
5420 unsigned NumRegs = 1;
5421 if (OpInfo.ConstraintVT != MVT::Other) {
5422 // If this is a FP input in an integer register (or visa versa) insert a bit
5423 // cast of the input value. More generally, handle any case where the input
5424 // value disagrees with the register class we plan to stick this in.
5425 if (OpInfo.Type == InlineAsm::isInput &&
5426 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5427 // Try to convert to the first EVT that the reg class contains. If the
5428 // types are identical size, use a bitcast to convert (e.g. two differing
5430 EVT RegVT = *PhysReg.second->vt_begin();
5431 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5432 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5433 RegVT, OpInfo.CallOperand);
5434 OpInfo.ConstraintVT = RegVT;
5435 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5436 // If the input is a FP value and we want it in FP registers, do a
5437 // bitcast to the corresponding integer type. This turns an f64 value
5438 // into i64, which can be passed with two i32 values on a 32-bit
5440 RegVT = EVT::getIntegerVT(Context,
5441 OpInfo.ConstraintVT.getSizeInBits());
5442 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5443 RegVT, OpInfo.CallOperand);
5444 OpInfo.ConstraintVT = RegVT;
5448 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5452 EVT ValueVT = OpInfo.ConstraintVT;
5454 // If this is a constraint for a specific physical register, like {r17},
5456 if (unsigned AssignedReg = PhysReg.first) {
5457 const TargetRegisterClass *RC = PhysReg.second;
5458 if (OpInfo.ConstraintVT == MVT::Other)
5459 ValueVT = *RC->vt_begin();
5461 // Get the actual register value type. This is important, because the user
5462 // may have asked for (e.g.) the AX register in i32 type. We need to
5463 // remember that AX is actually i16 to get the right extension.
5464 RegVT = *RC->vt_begin();
5466 // This is a explicit reference to a physical register.
5467 Regs.push_back(AssignedReg);
5469 // If this is an expanded reference, add the rest of the regs to Regs.
5471 TargetRegisterClass::iterator I = RC->begin();
5472 for (; *I != AssignedReg; ++I)
5473 assert(I != RC->end() && "Didn't find reg!");
5475 // Already added the first reg.
5477 for (; NumRegs; --NumRegs, ++I) {
5478 assert(I != RC->end() && "Ran out of registers to allocate!");
5483 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5484 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5485 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5489 // Otherwise, if this was a reference to an LLVM register class, create vregs
5490 // for this reference.
5491 if (const TargetRegisterClass *RC = PhysReg.second) {
5492 RegVT = *RC->vt_begin();
5493 if (OpInfo.ConstraintVT == MVT::Other)
5496 // Create the appropriate number of virtual registers.
5497 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5498 for (; NumRegs; --NumRegs)
5499 Regs.push_back(RegInfo.createVirtualRegister(RC));
5501 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5505 // This is a reference to a register class that doesn't directly correspond
5506 // to an LLVM register class. Allocate NumRegs consecutive, available,
5507 // registers from the class.
5508 std::vector<unsigned> RegClassRegs
5509 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5510 OpInfo.ConstraintVT);
5512 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5513 unsigned NumAllocated = 0;
5514 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5515 unsigned Reg = RegClassRegs[i];
5516 // See if this register is available.
5517 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5518 (isInReg && InputRegs.count(Reg))) { // Already used.
5519 // Make sure we find consecutive registers.
5524 // Check to see if this register is allocatable (i.e. don't give out the
5526 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5527 if (!RC) { // Couldn't allocate this register.
5528 // Reset NumAllocated to make sure we return consecutive registers.
5533 // Okay, this register is good, we can use it.
5536 // If we allocated enough consecutive registers, succeed.
5537 if (NumAllocated == NumRegs) {
5538 unsigned RegStart = (i-NumAllocated)+1;
5539 unsigned RegEnd = i+1;
5540 // Mark all of the allocated registers used.
5541 for (unsigned i = RegStart; i != RegEnd; ++i)
5542 Regs.push_back(RegClassRegs[i]);
5544 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5545 OpInfo.ConstraintVT);
5546 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5551 // Otherwise, we couldn't allocate enough registers for this.
5554 /// visitInlineAsm - Handle a call to an InlineAsm object.
5556 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5557 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5559 /// ConstraintOperands - Information about all of the constraints.
5560 SDISelAsmOperandInfoVector ConstraintOperands;
5562 std::set<unsigned> OutputRegs, InputRegs;
5564 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5565 bool hasMemory = false;
5567 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5568 unsigned ResNo = 0; // ResNo - The result number of the next output.
5569 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5570 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5571 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5573 EVT OpVT = MVT::Other;
5575 // Compute the value type for each operand.
5576 switch (OpInfo.Type) {
5577 case InlineAsm::isOutput:
5578 // Indirect outputs just consume an argument.
5579 if (OpInfo.isIndirect) {
5580 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5584 // The return value of the call is this value. As such, there is no
5585 // corresponding argument.
5586 assert(!CS.getType()->isVoidTy() &&
5588 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5589 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5591 assert(ResNo == 0 && "Asm only has one result!");
5592 OpVT = TLI.getValueType(CS.getType());
5596 case InlineAsm::isInput:
5597 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5599 case InlineAsm::isClobber:
5604 // If this is an input or an indirect output, process the call argument.
5605 // BasicBlocks are labels, currently appearing only in asm's.
5606 if (OpInfo.CallOperandVal) {
5607 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5608 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5610 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5613 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5616 OpInfo.ConstraintVT = OpVT;
5618 // Indirect operand accesses access memory.
5619 if (OpInfo.isIndirect)
5622 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5623 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5624 if (CType == TargetLowering::C_Memory) {
5632 SDValue Chain, Flag;
5634 // We won't need to flush pending loads if this asm doesn't touch
5635 // memory and is nonvolatile.
5636 if (hasMemory || IA->hasSideEffects())
5639 Chain = DAG.getRoot();
5641 // Second pass over the constraints: compute which constraint option to use
5642 // and assign registers to constraints that want a specific physreg.
5643 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5644 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5646 // If this is an output operand with a matching input operand, look up the
5647 // matching input. If their types mismatch, e.g. one is an integer, the
5648 // other is floating point, or their sizes are different, flag it as an
5650 if (OpInfo.hasMatchingInput()) {
5651 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5653 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5654 if ((OpInfo.ConstraintVT.isInteger() !=
5655 Input.ConstraintVT.isInteger()) ||
5656 (OpInfo.ConstraintVT.getSizeInBits() !=
5657 Input.ConstraintVT.getSizeInBits())) {
5658 report_fatal_error("Unsupported asm: input constraint"
5659 " with a matching output constraint of"
5660 " incompatible type!");
5662 Input.ConstraintVT = OpInfo.ConstraintVT;
5666 // Compute the constraint code and ConstraintType to use.
5667 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5669 // If this is a memory input, and if the operand is not indirect, do what we
5670 // need to to provide an address for the memory input.
5671 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5672 !OpInfo.isIndirect) {
5673 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5674 "Can only indirectify direct input operands!");
5676 // Memory operands really want the address of the value. If we don't have
5677 // an indirect input, put it in the constpool if we can, otherwise spill
5678 // it to a stack slot.
5680 // If the operand is a float, integer, or vector constant, spill to a
5681 // constant pool entry to get its address.
5682 const Value *OpVal = OpInfo.CallOperandVal;
5683 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5684 isa<ConstantVector>(OpVal)) {
5685 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5686 TLI.getPointerTy());
5688 // Otherwise, create a stack slot and emit a store to it before the
5690 const Type *Ty = OpVal->getType();
5691 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5692 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5693 MachineFunction &MF = DAG.getMachineFunction();
5694 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5695 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5696 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5697 OpInfo.CallOperand, StackSlot,
5698 MachinePointerInfo::getFixedStack(SSFI),
5700 OpInfo.CallOperand = StackSlot;
5703 // There is no longer a Value* corresponding to this operand.
5704 OpInfo.CallOperandVal = 0;
5706 // It is now an indirect operand.
5707 OpInfo.isIndirect = true;
5710 // If this constraint is for a specific register, allocate it before
5712 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5713 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5716 // Second pass - Loop over all of the operands, assigning virtual or physregs
5717 // to register class operands.
5718 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5719 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5721 // C_Register operands have already been allocated, Other/Memory don't need
5723 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5724 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5727 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5728 std::vector<SDValue> AsmNodeOperands;
5729 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5730 AsmNodeOperands.push_back(
5731 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5732 TLI.getPointerTy()));
5734 // If we have a !srcloc metadata node associated with it, we want to attach
5735 // this to the ultimately generated inline asm machineinstr. To do this, we
5736 // pass in the third operand as this (potentially null) inline asm MDNode.
5737 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5738 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5740 // Remember the HasSideEffect and AlignStack bits as operand 3.
5741 unsigned ExtraInfo = 0;
5742 if (IA->hasSideEffects())
5743 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5744 if (IA->isAlignStack())
5745 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5746 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5747 TLI.getPointerTy()));
5749 // Loop over all of the inputs, copying the operand values into the
5750 // appropriate registers and processing the output regs.
5751 RegsForValue RetValRegs;
5753 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5754 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5756 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5757 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5759 switch (OpInfo.Type) {
5760 case InlineAsm::isOutput: {
5761 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5762 OpInfo.ConstraintType != TargetLowering::C_Register) {
5763 // Memory output, or 'other' output (e.g. 'X' constraint).
5764 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5766 // Add information to the INLINEASM node to know about this output.
5767 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5768 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5769 TLI.getPointerTy()));
5770 AsmNodeOperands.push_back(OpInfo.CallOperand);
5774 // Otherwise, this is a register or register class output.
5776 // Copy the output from the appropriate register. Find a register that
5778 if (OpInfo.AssignedRegs.Regs.empty())
5779 report_fatal_error("Couldn't allocate output reg for constraint '" +
5780 Twine(OpInfo.ConstraintCode) + "'!");
5782 // If this is an indirect operand, store through the pointer after the
5784 if (OpInfo.isIndirect) {
5785 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5786 OpInfo.CallOperandVal));
5788 // This is the result value of the call.
5789 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5790 // Concatenate this output onto the outputs list.
5791 RetValRegs.append(OpInfo.AssignedRegs);
5794 // Add information to the INLINEASM node to know that this register is
5796 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5797 InlineAsm::Kind_RegDefEarlyClobber :
5798 InlineAsm::Kind_RegDef,
5805 case InlineAsm::isInput: {
5806 SDValue InOperandVal = OpInfo.CallOperand;
5808 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5809 // If this is required to match an output register we have already set,
5810 // just use its register.
5811 unsigned OperandNo = OpInfo.getMatchedOperand();
5813 // Scan until we find the definition we already emitted of this operand.
5814 // When we find it, create a RegsForValue operand.
5815 unsigned CurOp = InlineAsm::Op_FirstOperand;
5816 for (; OperandNo; --OperandNo) {
5817 // Advance to the next operand.
5819 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5820 assert((InlineAsm::isRegDefKind(OpFlag) ||
5821 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5822 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5823 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5827 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5828 if (InlineAsm::isRegDefKind(OpFlag) ||
5829 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5830 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5831 if (OpInfo.isIndirect) {
5832 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5833 LLVMContext &Ctx = *DAG.getContext();
5834 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5835 " don't know how to handle tied "
5836 "indirect register inputs");
5839 RegsForValue MatchedRegs;
5840 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5841 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5842 MatchedRegs.RegVTs.push_back(RegVT);
5843 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5844 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5846 MatchedRegs.Regs.push_back
5847 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5849 // Use the produced MatchedRegs object to
5850 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5852 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5853 true, OpInfo.getMatchedOperand(),
5854 DAG, AsmNodeOperands);
5858 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5859 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5860 "Unexpected number of operands");
5861 // Add information to the INLINEASM node to know about this input.
5862 // See InlineAsm.h isUseOperandTiedToDef.
5863 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5864 OpInfo.getMatchedOperand());
5865 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5866 TLI.getPointerTy()));
5867 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5871 // Treat indirect 'X' constraint as memory.
5872 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5874 OpInfo.ConstraintType = TargetLowering::C_Memory;
5876 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5877 std::vector<SDValue> Ops;
5878 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5881 report_fatal_error("Invalid operand for inline asm constraint '" +
5882 Twine(OpInfo.ConstraintCode) + "'!");
5884 // Add information to the INLINEASM node to know about this input.
5885 unsigned ResOpType =
5886 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5887 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5888 TLI.getPointerTy()));
5889 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5893 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5894 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5895 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5896 "Memory operands expect pointer values");
5898 // Add information to the INLINEASM node to know about this input.
5899 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5900 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5901 TLI.getPointerTy()));
5902 AsmNodeOperands.push_back(InOperandVal);
5906 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5907 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5908 "Unknown constraint type!");
5909 assert(!OpInfo.isIndirect &&
5910 "Don't know how to handle indirect register inputs yet!");
5912 // Copy the input into the appropriate registers.
5913 if (OpInfo.AssignedRegs.Regs.empty() ||
5914 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5915 report_fatal_error("Couldn't allocate input reg for constraint '" +
5916 Twine(OpInfo.ConstraintCode) + "'!");
5918 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5921 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5922 DAG, AsmNodeOperands);
5925 case InlineAsm::isClobber: {
5926 // Add the clobbered value to the operand list, so that the register
5927 // allocator is aware that the physreg got clobbered.
5928 if (!OpInfo.AssignedRegs.Regs.empty())
5929 OpInfo.AssignedRegs.AddInlineAsmOperands(
5930 InlineAsm::Kind_RegDefEarlyClobber,
5938 // Finish up input operands. Set the input chain and add the flag last.
5939 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5940 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5942 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5943 DAG.getVTList(MVT::Other, MVT::Glue),
5944 &AsmNodeOperands[0], AsmNodeOperands.size());
5945 Flag = Chain.getValue(1);
5947 // If this asm returns a register value, copy the result from that register
5948 // and set it as the value of the call.
5949 if (!RetValRegs.Regs.empty()) {
5950 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5953 // FIXME: Why don't we do this for inline asms with MRVs?
5954 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5955 EVT ResultType = TLI.getValueType(CS.getType());
5957 // If any of the results of the inline asm is a vector, it may have the
5958 // wrong width/num elts. This can happen for register classes that can
5959 // contain multiple different value types. The preg or vreg allocated may
5960 // not have the same VT as was expected. Convert it to the right type
5961 // with bit_convert.
5962 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5963 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5966 } else if (ResultType != Val.getValueType() &&
5967 ResultType.isInteger() && Val.getValueType().isInteger()) {
5968 // If a result value was tied to an input value, the computed result may
5969 // have a wider width than the expected result. Extract the relevant
5971 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5974 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5977 setValue(CS.getInstruction(), Val);
5978 // Don't need to use this as a chain in this case.
5979 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5983 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5985 // Process indirect outputs, first output all of the flagged copies out of
5987 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5988 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5989 const Value *Ptr = IndirectStoresToEmit[i].second;
5990 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5992 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5995 // Emit the non-flagged stores from the physregs.
5996 SmallVector<SDValue, 8> OutChains;
5997 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5998 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5999 StoresToEmit[i].first,
6000 getValue(StoresToEmit[i].second),
6001 MachinePointerInfo(StoresToEmit[i].second),
6003 OutChains.push_back(Val);
6006 if (!OutChains.empty())
6007 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6008 &OutChains[0], OutChains.size());
6013 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6014 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6015 MVT::Other, getRoot(),
6016 getValue(I.getArgOperand(0)),
6017 DAG.getSrcValue(I.getArgOperand(0))));
6020 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6021 const TargetData &TD = *TLI.getTargetData();
6022 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6023 getRoot(), getValue(I.getOperand(0)),
6024 DAG.getSrcValue(I.getOperand(0)),
6025 TD.getABITypeAlignment(I.getType()));
6027 DAG.setRoot(V.getValue(1));
6030 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6031 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6032 MVT::Other, getRoot(),
6033 getValue(I.getArgOperand(0)),
6034 DAG.getSrcValue(I.getArgOperand(0))));
6037 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6038 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6039 MVT::Other, getRoot(),
6040 getValue(I.getArgOperand(0)),
6041 getValue(I.getArgOperand(1)),
6042 DAG.getSrcValue(I.getArgOperand(0)),
6043 DAG.getSrcValue(I.getArgOperand(1))));
6046 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6047 /// implementation, which just calls LowerCall.
6048 /// FIXME: When all targets are
6049 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6050 std::pair<SDValue, SDValue>
6051 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6052 bool RetSExt, bool RetZExt, bool isVarArg,
6053 bool isInreg, unsigned NumFixedArgs,
6054 CallingConv::ID CallConv, bool isTailCall,
6055 bool isReturnValueUsed,
6057 ArgListTy &Args, SelectionDAG &DAG,
6058 DebugLoc dl) const {
6059 // Handle all of the outgoing arguments.
6060 SmallVector<ISD::OutputArg, 32> Outs;
6061 SmallVector<SDValue, 32> OutVals;
6062 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6063 SmallVector<EVT, 4> ValueVTs;
6064 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6065 for (unsigned Value = 0, NumValues = ValueVTs.size();
6066 Value != NumValues; ++Value) {
6067 EVT VT = ValueVTs[Value];
6068 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6069 SDValue Op = SDValue(Args[i].Node.getNode(),
6070 Args[i].Node.getResNo() + Value);
6071 ISD::ArgFlagsTy Flags;
6072 unsigned OriginalAlignment =
6073 getTargetData()->getABITypeAlignment(ArgTy);
6079 if (Args[i].isInReg)
6083 if (Args[i].isByVal) {
6085 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6086 const Type *ElementTy = Ty->getElementType();
6087 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6088 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6089 // For ByVal, alignment should come from FE. BE will guess if this
6090 // info is not there but there are cases it cannot get right.
6091 if (Args[i].Alignment)
6092 FrameAlign = Args[i].Alignment;
6093 Flags.setByValAlign(FrameAlign);
6094 Flags.setByValSize(FrameSize);
6098 Flags.setOrigAlign(OriginalAlignment);
6100 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6101 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6102 SmallVector<SDValue, 4> Parts(NumParts);
6103 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6106 ExtendKind = ISD::SIGN_EXTEND;
6107 else if (Args[i].isZExt)
6108 ExtendKind = ISD::ZERO_EXTEND;
6110 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6111 PartVT, ExtendKind);
6113 for (unsigned j = 0; j != NumParts; ++j) {
6114 // if it isn't first piece, alignment must be 1
6115 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6117 if (NumParts > 1 && j == 0)
6118 MyFlags.Flags.setSplit();
6120 MyFlags.Flags.setOrigAlign(1);
6122 Outs.push_back(MyFlags);
6123 OutVals.push_back(Parts[j]);
6128 // Handle the incoming return values from the call.
6129 SmallVector<ISD::InputArg, 32> Ins;
6130 SmallVector<EVT, 4> RetTys;
6131 ComputeValueVTs(*this, RetTy, RetTys);
6132 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6134 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6135 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6136 for (unsigned i = 0; i != NumRegs; ++i) {
6137 ISD::InputArg MyFlags;
6138 MyFlags.VT = RegisterVT.getSimpleVT();
6139 MyFlags.Used = isReturnValueUsed;
6141 MyFlags.Flags.setSExt();
6143 MyFlags.Flags.setZExt();
6145 MyFlags.Flags.setInReg();
6146 Ins.push_back(MyFlags);
6150 SmallVector<SDValue, 4> InVals;
6151 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6152 Outs, OutVals, Ins, dl, DAG, InVals);
6154 // Verify that the target's LowerCall behaved as expected.
6155 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6156 "LowerCall didn't return a valid chain!");
6157 assert((!isTailCall || InVals.empty()) &&
6158 "LowerCall emitted a return value for a tail call!");
6159 assert((isTailCall || InVals.size() == Ins.size()) &&
6160 "LowerCall didn't emit the correct number of values!");
6162 // For a tail call, the return value is merely live-out and there aren't
6163 // any nodes in the DAG representing it. Return a special value to
6164 // indicate that a tail call has been emitted and no more Instructions
6165 // should be processed in the current block.
6168 return std::make_pair(SDValue(), SDValue());
6171 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6172 assert(InVals[i].getNode() &&
6173 "LowerCall emitted a null value!");
6174 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6175 "LowerCall emitted a value with the wrong type!");
6178 // Collect the legal value parts into potentially illegal values
6179 // that correspond to the original function's return values.
6180 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6182 AssertOp = ISD::AssertSext;
6184 AssertOp = ISD::AssertZext;
6185 SmallVector<SDValue, 4> ReturnValues;
6186 unsigned CurReg = 0;
6187 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6189 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6190 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6192 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6193 NumRegs, RegisterVT, VT,
6198 // For a function returning void, there is no return value. We can't create
6199 // such a node, so we just return a null return value in that case. In
6200 // that case, nothing will actualy look at the value.
6201 if (ReturnValues.empty())
6202 return std::make_pair(SDValue(), Chain);
6204 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6205 DAG.getVTList(&RetTys[0], RetTys.size()),
6206 &ReturnValues[0], ReturnValues.size());
6207 return std::make_pair(Res, Chain);
6210 void TargetLowering::LowerOperationWrapper(SDNode *N,
6211 SmallVectorImpl<SDValue> &Results,
6212 SelectionDAG &DAG) const {
6213 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6215 Results.push_back(Res);
6218 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6219 llvm_unreachable("LowerOperation not implemented for this target!");
6224 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6225 SDValue Op = getNonRegisterValue(V);
6226 assert((Op.getOpcode() != ISD::CopyFromReg ||
6227 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6228 "Copy from a reg to the same reg!");
6229 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6231 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6232 SDValue Chain = DAG.getEntryNode();
6233 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6234 PendingExports.push_back(Chain);
6237 #include "llvm/CodeGen/SelectionDAGISel.h"
6239 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6240 // If this is the entry block, emit arguments.
6241 const Function &F = *LLVMBB->getParent();
6242 SelectionDAG &DAG = SDB->DAG;
6243 DebugLoc dl = SDB->getCurDebugLoc();
6244 const TargetData *TD = TLI.getTargetData();
6245 SmallVector<ISD::InputArg, 16> Ins;
6247 // Check whether the function can return without sret-demotion.
6248 SmallVector<ISD::OutputArg, 4> Outs;
6249 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6252 if (!FuncInfo->CanLowerReturn) {
6253 // Put in an sret pointer parameter before all the other parameters.
6254 SmallVector<EVT, 1> ValueVTs;
6255 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6257 // NOTE: Assuming that a pointer will never break down to more than one VT
6259 ISD::ArgFlagsTy Flags;
6261 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6262 ISD::InputArg RetArg(Flags, RegisterVT, true);
6263 Ins.push_back(RetArg);
6266 // Set up the incoming argument description vector.
6268 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6269 I != E; ++I, ++Idx) {
6270 SmallVector<EVT, 4> ValueVTs;
6271 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6272 bool isArgValueUsed = !I->use_empty();
6273 for (unsigned Value = 0, NumValues = ValueVTs.size();
6274 Value != NumValues; ++Value) {
6275 EVT VT = ValueVTs[Value];
6276 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6277 ISD::ArgFlagsTy Flags;
6278 unsigned OriginalAlignment =
6279 TD->getABITypeAlignment(ArgTy);
6281 if (F.paramHasAttr(Idx, Attribute::ZExt))
6283 if (F.paramHasAttr(Idx, Attribute::SExt))
6285 if (F.paramHasAttr(Idx, Attribute::InReg))
6287 if (F.paramHasAttr(Idx, Attribute::StructRet))
6289 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6291 const PointerType *Ty = cast<PointerType>(I->getType());
6292 const Type *ElementTy = Ty->getElementType();
6293 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6294 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6295 // For ByVal, alignment should be passed from FE. BE will guess if
6296 // this info is not there but there are cases it cannot get right.
6297 if (F.getParamAlignment(Idx))
6298 FrameAlign = F.getParamAlignment(Idx);
6299 Flags.setByValAlign(FrameAlign);
6300 Flags.setByValSize(FrameSize);
6302 if (F.paramHasAttr(Idx, Attribute::Nest))
6304 Flags.setOrigAlign(OriginalAlignment);
6306 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6307 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6308 for (unsigned i = 0; i != NumRegs; ++i) {
6309 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6310 if (NumRegs > 1 && i == 0)
6311 MyFlags.Flags.setSplit();
6312 // if it isn't first piece, alignment must be 1
6314 MyFlags.Flags.setOrigAlign(1);
6315 Ins.push_back(MyFlags);
6320 // Call the target to set up the argument values.
6321 SmallVector<SDValue, 8> InVals;
6322 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6326 // Verify that the target's LowerFormalArguments behaved as expected.
6327 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6328 "LowerFormalArguments didn't return a valid chain!");
6329 assert(InVals.size() == Ins.size() &&
6330 "LowerFormalArguments didn't emit the correct number of values!");
6332 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6333 assert(InVals[i].getNode() &&
6334 "LowerFormalArguments emitted a null value!");
6335 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6336 "LowerFormalArguments emitted a value with the wrong type!");
6340 // Update the DAG with the new chain value resulting from argument lowering.
6341 DAG.setRoot(NewRoot);
6343 // Set up the argument values.
6346 if (!FuncInfo->CanLowerReturn) {
6347 // Create a virtual register for the sret pointer, and put in a copy
6348 // from the sret argument into it.
6349 SmallVector<EVT, 1> ValueVTs;
6350 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6351 EVT VT = ValueVTs[0];
6352 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6353 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6354 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6355 RegVT, VT, AssertOp);
6357 MachineFunction& MF = SDB->DAG.getMachineFunction();
6358 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6359 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6360 FuncInfo->DemoteRegister = SRetReg;
6361 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6363 DAG.setRoot(NewRoot);
6365 // i indexes lowered arguments. Bump it past the hidden sret argument.
6366 // Idx indexes LLVM arguments. Don't touch it.
6370 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6372 SmallVector<SDValue, 4> ArgValues;
6373 SmallVector<EVT, 4> ValueVTs;
6374 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6375 unsigned NumValues = ValueVTs.size();
6377 // If this argument is unused then remember its value. It is used to generate
6378 // debugging information.
6379 if (I->use_empty() && NumValues)
6380 SDB->setUnusedArgValue(I, InVals[i]);
6382 for (unsigned Value = 0; Value != NumValues; ++Value) {
6383 EVT VT = ValueVTs[Value];
6384 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6385 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6387 if (!I->use_empty()) {
6388 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6389 if (F.paramHasAttr(Idx, Attribute::SExt))
6390 AssertOp = ISD::AssertSext;
6391 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6392 AssertOp = ISD::AssertZext;
6394 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6395 NumParts, PartVT, VT,
6402 // Note down frame index for byval arguments.
6403 if (I->hasByValAttr() && !ArgValues.empty())
6404 if (FrameIndexSDNode *FI =
6405 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6406 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6408 if (!I->use_empty()) {
6410 if (!ArgValues.empty())
6411 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6412 SDB->getCurDebugLoc());
6413 SDB->setValue(I, Res);
6415 // If this argument is live outside of the entry block, insert a copy from
6416 // whereever we got it to the vreg that other BB's will reference it as.
6417 SDB->CopyToExportRegsIfNeeded(I);
6421 assert(i == InVals.size() && "Argument register count mismatch!");
6423 // Finally, if the target has anything special to do, allow it to do so.
6424 // FIXME: this should insert code into the DAG!
6425 EmitFunctionEntryCode();
6428 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6429 /// ensure constants are generated when needed. Remember the virtual registers
6430 /// that need to be added to the Machine PHI nodes as input. We cannot just
6431 /// directly add them, because expansion might result in multiple MBB's for one
6432 /// BB. As such, the start of the BB might correspond to a different MBB than
6436 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6437 const TerminatorInst *TI = LLVMBB->getTerminator();
6439 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6441 // Check successor nodes' PHI nodes that expect a constant to be available
6443 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6444 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6445 if (!isa<PHINode>(SuccBB->begin())) continue;
6446 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6448 // If this terminator has multiple identical successors (common for
6449 // switches), only handle each succ once.
6450 if (!SuccsHandled.insert(SuccMBB)) continue;
6452 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6454 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6455 // nodes and Machine PHI nodes, but the incoming operands have not been
6457 for (BasicBlock::const_iterator I = SuccBB->begin();
6458 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6459 // Ignore dead phi's.
6460 if (PN->use_empty()) continue;
6463 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6465 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6466 unsigned &RegOut = ConstantsOut[C];
6468 RegOut = FuncInfo.CreateRegs(C->getType());
6469 CopyValueToVirtualRegister(C, RegOut);
6473 DenseMap<const Value *, unsigned>::iterator I =
6474 FuncInfo.ValueMap.find(PHIOp);
6475 if (I != FuncInfo.ValueMap.end())
6478 assert(isa<AllocaInst>(PHIOp) &&
6479 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6480 "Didn't codegen value into a register!??");
6481 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6482 CopyValueToVirtualRegister(PHIOp, Reg);
6486 // Remember that this register needs to added to the machine PHI node as
6487 // the input for this MBB.
6488 SmallVector<EVT, 4> ValueVTs;
6489 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6490 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6491 EVT VT = ValueVTs[vti];
6492 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6493 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6494 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6495 Reg += NumRegisters;
6499 ConstantsOut.clear();