1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
65 #define DEBUG_TYPE "isel"
67 /// LimitFloatPrecision - Generate low-precision inline sequences for
68 /// some float libcalls (6, 8 or 12 bits).
69 static unsigned LimitFloatPrecision;
71 static cl::opt<unsigned, true>
72 LimitFPPrecision("limit-float-precision",
73 cl::desc("Generate low-precision inline sequences "
74 "for some float libcalls"),
75 cl::location(LimitFloatPrecision),
78 // Limit the width of DAG chains. This is important in general to prevent
79 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // load clustering may not complete in reasonable time. It is difficult to
81 // recognize and avoid this situation within each individual analysis, and
82 // future analyses are likely to have the same behavior. Limiting DAG width is
83 // the safe approach, and will be especially important with global DAGs.
85 // MaxParallelChains default is arbitrarily high to avoid affecting
86 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
87 // sequence over this should have been converted to llvm.memcpy by the
88 // frontend. It easy to induce this behavior with .ll code such as:
89 // %buffer = alloca [4096 x i8]
90 // %data = load [4096 x i8]* %argPtr
91 // store [4096 x i8] %data, [4096 x i8]* %buffer
92 static const unsigned MaxParallelChains = 64;
94 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
95 const SDValue *Parts, unsigned NumParts,
96 MVT PartVT, EVT ValueVT, const Value *V);
98 /// getCopyFromParts - Create a value that contains the specified legal parts
99 /// combined into the value they represent. If the parts combine to a type
100 /// larger then ValueVT then AssertOp can be used to specify whether the extra
101 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 /// (ISD::AssertSext).
103 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts,
105 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
108 if (ValueVT.isVector())
109 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
112 assert(NumParts > 0 && "No parts to assemble!");
113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
114 SDValue Val = Parts[0];
117 // Assemble the value from multiple parts.
118 if (ValueVT.isInteger()) {
119 unsigned PartBits = PartVT.getSizeInBits();
120 unsigned ValueBits = ValueVT.getSizeInBits();
122 // Assemble the power of 2 part.
123 unsigned RoundParts = NumParts & (NumParts - 1) ?
124 1 << Log2_32(NumParts) : NumParts;
125 unsigned RoundBits = PartBits * RoundParts;
126 EVT RoundVT = RoundBits == ValueBits ?
127 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
130 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
132 if (RoundParts > 2) {
133 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
135 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
136 RoundParts / 2, PartVT, HalfVT, V);
138 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 if (TLI.isBigEndian())
145 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
147 if (RoundParts < NumParts) {
148 // Assemble the trailing non-power-of-2 part.
149 unsigned OddParts = NumParts - RoundParts;
150 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
151 Hi = getCopyFromParts(DAG, DL,
152 Parts + RoundParts, OddParts, PartVT, OddVT, V);
154 // Combine the round and odd parts.
156 if (TLI.isBigEndian())
158 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
159 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
160 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
161 DAG.getConstant(Lo.getValueType().getSizeInBits(),
162 TLI.getPointerTy()));
163 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
164 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
166 } else if (PartVT.isFloatingPoint()) {
167 // FP split into multiple FP parts (for ppcf128)
168 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
171 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
172 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
173 if (TLI.hasBigEndianPartOrdering(ValueVT))
175 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
177 // FP split into integer parts (soft fp)
178 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
179 !PartVT.isVector() && "Unexpected split");
180 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
181 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 // There is now one part, held in Val. Correct it to match ValueVT.
186 EVT PartEVT = Val.getValueType();
188 if (PartEVT == ValueVT)
191 if (PartEVT.isInteger() && ValueVT.isInteger()) {
192 if (ValueVT.bitsLT(PartEVT)) {
193 // For a truncate, see if we have any information to
194 // indicate whether the truncated bits will always be
195 // zero or sign-extension.
196 if (AssertOp != ISD::DELETED_NODE)
197 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
198 DAG.getValueType(ValueVT));
199 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
201 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
204 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
205 // FP_ROUND's are always exact here.
206 if (ValueVT.bitsLT(Val.getValueType()))
207 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
208 DAG.getTargetConstant(1, TLI.getPointerTy()));
210 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
214 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
216 llvm_unreachable("Unknown mismatch!");
219 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
220 const Twine &ErrMsg) {
221 const Instruction *I = dyn_cast_or_null<Instruction>(V);
223 return Ctx.emitError(ErrMsg);
225 const char *AsmError = ", possible invalid constraint for vector type";
226 if (const CallInst *CI = dyn_cast<CallInst>(I))
227 if (isa<InlineAsm>(CI->getCalledValue()))
228 return Ctx.emitError(I, ErrMsg + AsmError);
230 return Ctx.emitError(I, ErrMsg);
233 /// getCopyFromPartsVector - Create a value that contains the specified legal
234 /// parts combined into the value they represent. If the parts combine to a
235 /// type larger then ValueVT then AssertOp can be used to specify whether the
236 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
237 /// ValueVT (ISD::AssertSext).
238 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
239 const SDValue *Parts, unsigned NumParts,
240 MVT PartVT, EVT ValueVT, const Value *V) {
241 assert(ValueVT.isVector() && "Not a vector value");
242 assert(NumParts > 0 && "No parts to assemble!");
243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
244 SDValue Val = Parts[0];
246 // Handle a multi-element vector.
250 unsigned NumIntermediates;
252 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
253 NumIntermediates, RegisterVT);
254 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
255 NumParts = NumRegs; // Silence a compiler warning.
256 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
257 assert(RegisterVT == Parts[0].getSimpleValueType() &&
258 "Part type doesn't match part!");
260 // Assemble the parts into intermediate operands.
261 SmallVector<SDValue, 8> Ops(NumIntermediates);
262 if (NumIntermediates == NumParts) {
263 // If the register was not expanded, truncate or copy the value,
265 for (unsigned i = 0; i != NumParts; ++i)
266 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
267 PartVT, IntermediateVT, V);
268 } else if (NumParts > 0) {
269 // If the intermediate type was expanded, build the intermediate
270 // operands from the parts.
271 assert(NumParts % NumIntermediates == 0 &&
272 "Must expand into a divisible number of parts!");
273 unsigned Factor = NumParts / NumIntermediates;
274 for (unsigned i = 0; i != NumIntermediates; ++i)
275 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
276 PartVT, IntermediateVT, V);
279 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 // intermediate operands.
281 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
286 // There is now one part, held in Val. Correct it to match ValueVT.
287 EVT PartEVT = Val.getValueType();
289 if (PartEVT == ValueVT)
292 if (PartEVT.isVector()) {
293 // If the element type of the source/dest vectors are the same, but the
294 // parts vector has more elements than the value vector, then we have a
295 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
297 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
298 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
299 "Cannot narrow, it would be a lossy transformation");
300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
301 DAG.getConstant(0, TLI.getVectorIdxTy()));
304 // Vector/Vector bitcast.
305 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
306 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
308 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
309 "Cannot handle this kind of promotion");
310 // Promoted vector extract
311 bool Smaller = ValueVT.bitsLE(PartEVT);
312 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
317 // Trivial bitcast if the types are the same size and the destination
318 // vector type is legal.
319 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
320 TLI.isTypeLegal(ValueVT))
321 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
323 // Handle cases such as i8 -> <1 x i1>
324 if (ValueVT.getVectorNumElements() != 1) {
325 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
326 "non-trivial scalar-to-vector conversion");
327 return DAG.getUNDEF(ValueVT);
330 if (ValueVT.getVectorNumElements() == 1 &&
331 ValueVT.getVectorElementType() != PartEVT) {
332 bool Smaller = ValueVT.bitsLE(PartEVT);
333 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
334 DL, ValueVT.getScalarType(), Val);
337 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
340 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
341 SDValue Val, SDValue *Parts, unsigned NumParts,
342 MVT PartVT, const Value *V);
344 /// getCopyToParts - Create a series of nodes that contain the specified value
345 /// split into legal parts. If the parts contain more bits than Val, then, for
346 /// integers, ExtendKind can be used to specify how to generate the extra bits.
347 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V,
350 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
351 EVT ValueVT = Val.getValueType();
353 // Handle the vector case separately.
354 if (ValueVT.isVector())
355 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 unsigned PartBits = PartVT.getSizeInBits();
359 unsigned OrigNumParts = NumParts;
360 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
366 EVT PartEVT = PartVT;
367 if (PartEVT == ValueVT) {
368 assert(NumParts == 1 && "No-op copy with multiple parts!");
373 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
374 // If the parts cover more bits than the value has, promote the value.
375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
376 assert(NumParts == 1 && "Do not know what to promote to!");
377 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
379 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
380 ValueVT.isInteger() &&
381 "Unknown mismatch!");
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
384 if (PartVT == MVT::x86mmx)
385 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
387 } else if (PartBits == ValueVT.getSizeInBits()) {
388 // Different types of the same size.
389 assert(NumParts == 1 && PartEVT != ValueVT);
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
392 // If the parts cover less bits than value has, truncate the value.
393 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
394 ValueVT.isInteger() &&
395 "Unknown mismatch!");
396 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
397 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
398 if (PartVT == MVT::x86mmx)
399 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
402 // The value may have changed - recompute ValueVT.
403 ValueVT = Val.getValueType();
404 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
405 "Failed to tile the value with PartVT!");
408 if (PartEVT != ValueVT)
409 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
410 "scalar-to-vector conversion failed");
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getConstant(i,
494 TLI.getVectorIdxTy())));
496 for (unsigned i = ValueVT.getVectorNumElements(),
497 e = PartVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getUNDEF(ElementVT));
500 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
502 // FIXME: Use CONCAT for 2x -> 4x.
504 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
505 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType().bitsGE(
508 ValueVT.getVectorElementType()) &&
509 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
511 // Promoted vector extract
512 bool Smaller = PartEVT.bitsLE(ValueVT);
513 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
516 // Vector -> scalar conversion.
517 assert(ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
520 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
522 bool Smaller = ValueVT.bitsLE(PartVT);
523 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
531 // Handle a multi-element vector.
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
537 NumIntermediates, RegisterVT);
538 unsigned NumElements = ValueVT.getVectorNumElements();
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
542 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
544 // Split the vector into intermediate operands.
545 SmallVector<SDValue, 8> Ops(NumIntermediates);
546 for (unsigned i = 0; i != NumIntermediates; ++i) {
547 if (IntermediateVT.isVector())
548 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
550 DAG.getConstant(i * (NumElements / NumIntermediates),
551 TLI.getVectorIdxTy()));
553 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
555 DAG.getConstant(i, TLI.getVectorIdxTy()));
558 // Split the intermediate operands into legal parts.
559 if (NumParts == NumIntermediates) {
560 // If the register was not expanded, promote or copy the value,
562 for (unsigned i = 0; i != NumParts; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
564 } else if (NumParts > 0) {
565 // If the intermediate type was expanded, split each the value into
567 assert(NumParts % NumIntermediates == 0 &&
568 "Must expand into a divisible number of parts!");
569 unsigned Factor = NumParts / NumIntermediates;
570 for (unsigned i = 0; i != NumIntermediates; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 /// RegsForValue - This struct represents the registers (physical or virtual)
577 /// that a particular set of values is assigned, and the type information
578 /// about the value. The most common situation is to represent one value at a
579 /// time, but struct or array values are handled element-wise as multiple
580 /// values. The splitting of aggregates is performed recursively, so that we
581 /// never have aggregate-typed registers. The values at this point do not
582 /// necessarily have legal types, so each value may require one or more
583 /// registers of some legal type.
585 struct RegsForValue {
586 /// ValueVTs - The value types of the values, which may not be legal, and
587 /// may need be promoted or synthesized from one or more registers.
589 SmallVector<EVT, 4> ValueVTs;
591 /// RegVTs - The value types of the registers. This is the same size as
592 /// ValueVTs and it records, for each value, what the type of the assigned
593 /// register or registers are. (Individual values are never synthesized
594 /// from more than one type of register.)
596 /// With virtual registers, the contents of RegVTs is redundant with TLI's
597 /// getRegisterType member function, however when with physical registers
598 /// it is necessary to have a separate record of the types.
600 SmallVector<MVT, 4> RegVTs;
602 /// Regs - This list holds the registers assigned to the values.
603 /// Each legal or promoted value requires one register, and each
604 /// expanded value requires multiple registers.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
614 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
615 unsigned Reg, Type *Ty) {
616 ComputeValueVTs(tli, Ty, ValueVTs);
618 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
623 Regs.push_back(Reg + i);
624 RegVTs.push_back(RegisterVT);
629 /// append - Add the specified values to this one.
630 void append(const RegsForValue &RHS) {
631 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
632 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
633 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVTs value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
642 SDValue &Chain, SDValue *Flag,
643 const Value *V = nullptr) const;
645 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
646 /// specified value into the registers specified by this object. This uses
647 /// Chain/Flag as the input and updates them for the output Chain/Flag.
648 /// If the Flag pointer is NULL, no flag is used.
650 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
651 SDValue *Flag, const Value *V,
652 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
654 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
655 /// operand list. This adds the code marker, matching input operand index
656 /// (if applicable), and includes the number of values added into it.
657 void AddInlineAsmOperands(unsigned Kind,
658 bool HasMatching, unsigned MatchingIdx,
660 std::vector<SDValue> &Ops) const;
664 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
665 /// this value and returns the result as a ValueVT value. This uses
666 /// Chain/Flag as the input and updates them for the output Chain/Flag.
667 /// If the Flag pointer is NULL, no flag is used.
668 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
669 FunctionLoweringInfo &FuncInfo,
671 SDValue &Chain, SDValue *Flag,
672 const Value *V) const {
673 // A Value with type {} or [0 x %t] needs no registers.
674 if (ValueVTs.empty())
677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 // Assemble the legal parts into the final values.
680 SmallVector<SDValue, 4> Values(ValueVTs.size());
681 SmallVector<SDValue, 8> Parts;
682 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
683 // Copy the legal parts from the registers.
684 EVT ValueVT = ValueVTs[Value];
685 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
686 MVT RegisterVT = RegVTs[Value];
688 Parts.resize(NumRegs);
689 for (unsigned i = 0; i != NumRegs; ++i) {
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
694 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
695 *Flag = P.getValue(2);
698 Chain = P.getValue(1);
701 // If the source register was virtual and if we know something about it,
702 // add an assert node.
703 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
704 !RegisterVT.isInteger() || RegisterVT.isVector())
707 const FunctionLoweringInfo::LiveOutInfo *LOI =
708 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
712 unsigned RegSize = RegisterVT.getSizeInBits();
713 unsigned NumSignBits = LOI->NumSignBits;
714 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
716 if (NumZeroBits == RegSize) {
717 // The current value is a zero.
718 // Explicitly express that as it would be easier for
719 // optimizations to kick in.
720 Parts[i] = DAG.getConstant(0, RegisterVT);
724 // FIXME: We capture more information than the dag can represent. For
725 // now, just use the tightest assertzext/assertsext possible.
727 EVT FromVT(MVT::Other);
728 if (NumSignBits == RegSize)
729 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
730 else if (NumZeroBits >= RegSize-1)
731 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
732 else if (NumSignBits > RegSize-8)
733 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
734 else if (NumZeroBits >= RegSize-8)
735 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
736 else if (NumSignBits > RegSize-16)
737 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
738 else if (NumZeroBits >= RegSize-16)
739 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
740 else if (NumSignBits > RegSize-32)
741 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
742 else if (NumZeroBits >= RegSize-32)
743 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
747 // Add an assertion node.
748 assert(FromVT != MVT::Other);
749 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
750 RegisterVT, P, DAG.getValueType(FromVT));
753 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
754 NumRegs, RegisterVT, ValueVT, V);
759 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
762 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
763 /// specified value into the registers specified by this object. This uses
764 /// Chain/Flag as the input and updates them for the output Chain/Flag.
765 /// If the Flag pointer is NULL, no flag is used.
766 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
767 SDValue &Chain, SDValue *Flag, const Value *V,
768 ISD::NodeType PreferredExtendType) const {
769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
770 ISD::NodeType ExtendKind = PreferredExtendType;
772 // Get the list of the values's legal parts.
773 unsigned NumRegs = Regs.size();
774 SmallVector<SDValue, 8> Parts(NumRegs);
775 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
776 EVT ValueVT = ValueVTs[Value];
777 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
778 MVT RegisterVT = RegVTs[Value];
780 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
781 ExtendKind = ISD::ZERO_EXTEND;
783 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
784 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
788 // Copy the parts into the registers.
789 SmallVector<SDValue, 8> Chains(NumRegs);
790 for (unsigned i = 0; i != NumRegs; ++i) {
793 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
795 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
796 *Flag = Part.getValue(1);
799 Chains[i] = Part.getValue(0);
802 if (NumRegs == 1 || Flag)
803 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
804 // flagged to it. That is the CopyToReg nodes and the user are considered
805 // a single scheduling unit. If we create a TokenFactor and return it as
806 // chain, then the TokenFactor is both a predecessor (operand) of the
807 // user as well as a successor (the TF operands are flagged to the user).
808 // c1, f1 = CopyToReg
809 // c2, f2 = CopyToReg
810 // c3 = TokenFactor c1, c2
813 Chain = Chains[NumRegs-1];
815 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
818 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
819 /// operand list. This adds the code marker and includes the number of
820 /// values added into it.
821 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
822 unsigned MatchingIdx,
824 std::vector<SDValue> &Ops) const {
825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
827 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
829 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
830 else if (!Regs.empty() &&
831 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
832 // Put the register class of the virtual registers in the flag word. That
833 // way, later passes can recompute register class constraints for inline
834 // assembly as well as normal instructions.
835 // Don't do this for tied operands that can use the regclass information
837 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
838 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
839 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
842 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
845 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
846 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
847 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
848 MVT RegisterVT = RegVTs[Value];
849 for (unsigned i = 0; i != NumRegs; ++i) {
850 assert(Reg < Regs.size() && "Mismatch in # registers expected");
851 unsigned TheReg = Regs[Reg++];
852 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
854 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
855 // If we clobbered the stack pointer, MFI should know about it.
856 assert(DAG.getMachineFunction().getFrameInfo()->
857 hasInlineAsmWithSPAdjust());
863 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
864 const TargetLibraryInfo *li) {
868 DL = DAG.getSubtarget().getDataLayout();
869 Context = DAG.getContext();
870 LPadToCallSiteMap.clear();
873 /// clear - Clear out the current SelectionDAG and the associated
874 /// state and prepare this SelectionDAGBuilder object to be used
875 /// for a new block. This doesn't clear out information about
876 /// additional blocks that are needed to complete switch lowering
877 /// or PHI node updating; that information is cleared out as it is
879 void SelectionDAGBuilder::clear() {
881 UnusedArgNodeMap.clear();
882 PendingLoads.clear();
883 PendingExports.clear();
886 SDNodeOrder = LowestSDNodeOrder;
889 /// clearDanglingDebugInfo - Clear the dangling debug information
890 /// map. This function is separated from the clear so that debug
891 /// information that is dangling in a basic block can be properly
892 /// resolved in a different basic block. This allows the
893 /// SelectionDAG to resolve dangling debug information attached
895 void SelectionDAGBuilder::clearDanglingDebugInfo() {
896 DanglingDebugInfoMap.clear();
899 /// getRoot - Return the current virtual root of the Selection DAG,
900 /// flushing any PendingLoad items. This must be done before emitting
901 /// a store or any other node that may need to be ordered after any
902 /// prior load instructions.
904 SDValue SelectionDAGBuilder::getRoot() {
905 if (PendingLoads.empty())
906 return DAG.getRoot();
908 if (PendingLoads.size() == 1) {
909 SDValue Root = PendingLoads[0];
911 PendingLoads.clear();
915 // Otherwise, we have to make a token factor node.
916 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
918 PendingLoads.clear();
923 /// getControlRoot - Similar to getRoot, but instead of flushing all the
924 /// PendingLoad items, flush all the PendingExports items. It is necessary
925 /// to do this before emitting a terminator instruction.
927 SDValue SelectionDAGBuilder::getControlRoot() {
928 SDValue Root = DAG.getRoot();
930 if (PendingExports.empty())
933 // Turn all of the CopyToReg chains into one factored node.
934 if (Root.getOpcode() != ISD::EntryToken) {
935 unsigned i = 0, e = PendingExports.size();
936 for (; i != e; ++i) {
937 assert(PendingExports[i].getNode()->getNumOperands() > 1);
938 if (PendingExports[i].getNode()->getOperand(0) == Root)
939 break; // Don't add the root if we already indirectly depend on it.
943 PendingExports.push_back(Root);
946 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
948 PendingExports.clear();
953 void SelectionDAGBuilder::visit(const Instruction &I) {
954 // Set up outgoing PHI node register values before emitting the terminator.
955 if (isa<TerminatorInst>(&I))
956 HandlePHINodesInSuccessorBlocks(I.getParent());
962 visit(I.getOpcode(), I);
964 if (!isa<TerminatorInst>(&I) && !HasTailCall)
965 CopyToExportRegsIfNeeded(&I);
970 void SelectionDAGBuilder::visitPHI(const PHINode &) {
971 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
974 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
975 // Note: this doesn't use InstVisitor, because it has to work with
976 // ConstantExpr's in addition to instructions.
978 default: llvm_unreachable("Unknown instruction type encountered!");
979 // Build the switch statement using the Instruction.def file.
980 #define HANDLE_INST(NUM, OPCODE, CLASS) \
981 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
982 #include "llvm/IR/Instruction.def"
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 MDNode *Expr = DI->getExpression();
997 uint64_t Offset = DI->getOffset();
998 // A dbg.value for an alloca is always indirect.
999 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1001 if (Val.getNode()) {
1002 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1004 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1005 IsIndirect, Offset, dl, DbgSDNodeOrder);
1006 DAG.AddDbgValue(SDV, Val.getNode(), false);
1009 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1010 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1014 /// getValue - Return an SDValue for the given Value.
1015 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it. It's important
1017 // to do this first, so that we don't create a CopyFromReg if we already
1018 // have a regular SDValue.
1019 SDValue &N = NodeMap[V];
1020 if (N.getNode()) return N;
1022 // If there's a virtual register allocated and initialized for this
1024 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, N);
1035 // Otherwise create a new SDValue and remember it.
1036 SDValue Val = getValueImpl(V);
1038 resolveDanglingDebugInfo(V, Val);
1042 /// getNonRegisterValue - Return an SDValue for the given Value, but
1043 /// don't look in FuncInfo.ValueMap for a virtual register.
1044 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1045 // If we already have an SDValue for this value, use it.
1046 SDValue &N = NodeMap[V];
1047 if (N.getNode()) return N;
1049 // Otherwise create a new SDValue and remember it.
1050 SDValue Val = getValueImpl(V);
1052 resolveDanglingDebugInfo(V, Val);
1056 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1057 /// Create an SDValue for the given value.
1058 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1061 if (const Constant *C = dyn_cast<Constant>(V)) {
1062 EVT VT = TLI.getValueType(V->getType(), true);
1064 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1065 return DAG.getConstant(*CI, VT);
1067 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1068 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1070 if (isa<ConstantPointerNull>(C)) {
1071 unsigned AS = V->getType()->getPointerAddressSpace();
1072 return DAG.getConstant(0, TLI.getPointerTy(AS));
1075 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1076 return DAG.getConstantFP(*CFP, VT);
1078 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1079 return DAG.getUNDEF(VT);
1081 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1082 visit(CE->getOpcode(), *CE);
1083 SDValue N1 = NodeMap[V];
1084 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1088 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1089 SmallVector<SDValue, 4> Constants;
1090 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1092 SDNode *Val = getValue(*OI).getNode();
1093 // If the operand is an empty aggregate, there are no values.
1095 // Add each leaf value from the operand to the Constants list
1096 // to form a flattened list of all the values.
1097 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1098 Constants.push_back(SDValue(Val, i));
1101 return DAG.getMergeValues(Constants, getCurSDLoc());
1104 if (const ConstantDataSequential *CDS =
1105 dyn_cast<ConstantDataSequential>(C)) {
1106 SmallVector<SDValue, 4> Ops;
1107 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1108 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1109 // Add each leaf value from the operand to the Constants list
1110 // to form a flattened list of all the values.
1111 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1112 Ops.push_back(SDValue(Val, i));
1115 if (isa<ArrayType>(CDS->getType()))
1116 return DAG.getMergeValues(Ops, getCurSDLoc());
1117 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1121 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1122 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1123 "Unknown struct or array constant!");
1125 SmallVector<EVT, 4> ValueVTs;
1126 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1127 unsigned NumElts = ValueVTs.size();
1129 return SDValue(); // empty struct
1130 SmallVector<SDValue, 4> Constants(NumElts);
1131 for (unsigned i = 0; i != NumElts; ++i) {
1132 EVT EltVT = ValueVTs[i];
1133 if (isa<UndefValue>(C))
1134 Constants[i] = DAG.getUNDEF(EltVT);
1135 else if (EltVT.isFloatingPoint())
1136 Constants[i] = DAG.getConstantFP(0, EltVT);
1138 Constants[i] = DAG.getConstant(0, EltVT);
1141 return DAG.getMergeValues(Constants, getCurSDLoc());
1144 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1145 return DAG.getBlockAddress(BA, VT);
1147 VectorType *VecTy = cast<VectorType>(V->getType());
1148 unsigned NumElements = VecTy->getNumElements();
1150 // Now that we know the number and type of the elements, get that number of
1151 // elements into the Ops array based on what kind of constant it is.
1152 SmallVector<SDValue, 16> Ops;
1153 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1154 for (unsigned i = 0; i != NumElements; ++i)
1155 Ops.push_back(getValue(CV->getOperand(i)));
1157 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1158 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1161 if (EltVT.isFloatingPoint())
1162 Op = DAG.getConstantFP(0, EltVT);
1164 Op = DAG.getConstant(0, EltVT);
1165 Ops.assign(NumElements, Op);
1168 // Create a BUILD_VECTOR node.
1169 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1172 // If this is a static alloca, generate it as the frameindex instead of
1174 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1175 DenseMap<const AllocaInst*, int>::iterator SI =
1176 FuncInfo.StaticAllocaMap.find(AI);
1177 if (SI != FuncInfo.StaticAllocaMap.end())
1178 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1181 // If this is an instruction which fast-isel has deferred, select it now.
1182 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1183 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1184 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1185 SDValue Chain = DAG.getEntryNode();
1186 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1189 llvm_unreachable("Can't get register for value!");
1192 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1194 SDValue Chain = getControlRoot();
1195 SmallVector<ISD::OutputArg, 8> Outs;
1196 SmallVector<SDValue, 8> OutVals;
1198 if (!FuncInfo.CanLowerReturn) {
1199 unsigned DemoteReg = FuncInfo.DemoteRegister;
1200 const Function *F = I.getParent()->getParent();
1202 // Emit a store of the return value through the virtual register.
1203 // Leave Outs empty so that LowerReturn won't try to load return
1204 // registers the usual way.
1205 SmallVector<EVT, 1> PtrValueVTs;
1206 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1209 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1210 SDValue RetOp = getValue(I.getOperand(0));
1212 SmallVector<EVT, 4> ValueVTs;
1213 SmallVector<uint64_t, 4> Offsets;
1214 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1215 unsigned NumValues = ValueVTs.size();
1217 SmallVector<SDValue, 4> Chains(NumValues);
1218 for (unsigned i = 0; i != NumValues; ++i) {
1219 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1220 RetPtr.getValueType(), RetPtr,
1221 DAG.getIntPtrConstant(Offsets[i]));
1223 DAG.getStore(Chain, getCurSDLoc(),
1224 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1225 // FIXME: better loc info would be nice.
1226 Add, MachinePointerInfo(), false, false, 0);
1229 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1230 MVT::Other, Chains);
1231 } else if (I.getNumOperands() != 0) {
1232 SmallVector<EVT, 4> ValueVTs;
1233 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1234 unsigned NumValues = ValueVTs.size();
1236 SDValue RetOp = getValue(I.getOperand(0));
1237 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1238 EVT VT = ValueVTs[j];
1240 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1242 const Function *F = I.getParent()->getParent();
1243 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1245 ExtendKind = ISD::SIGN_EXTEND;
1246 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1248 ExtendKind = ISD::ZERO_EXTEND;
1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1251 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1253 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1254 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1255 SmallVector<SDValue, 4> Parts(NumParts);
1256 getCopyToParts(DAG, getCurSDLoc(),
1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1258 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1260 // 'inreg' on function refers to return value
1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1262 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1266 // Propagate extension type if any
1267 if (ExtendKind == ISD::SIGN_EXTEND)
1269 else if (ExtendKind == ISD::ZERO_EXTEND)
1272 for (unsigned i = 0; i < NumParts; ++i) {
1273 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1274 VT, /*isfixed=*/true, 0, 0));
1275 OutVals.push_back(Parts[i]);
1281 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1282 CallingConv::ID CallConv =
1283 DAG.getMachineFunction().getFunction()->getCallingConv();
1284 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1285 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1287 // Verify that the target's LowerReturn behaved as expected.
1288 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1289 "LowerReturn didn't return a valid chain!");
1291 // Update the DAG with the new chain value resulting from return lowering.
1295 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1296 /// created for it, emit nodes to copy the value into the virtual
1298 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1300 if (V->getType()->isEmptyTy())
1303 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1304 if (VMI != FuncInfo.ValueMap.end()) {
1305 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1306 CopyValueToVirtualRegister(V, VMI->second);
1310 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1311 /// the current basic block, add it to ValueMap now so that we'll get a
1313 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1314 // No need to export constants.
1315 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1317 // Already exported?
1318 if (FuncInfo.isExportedInst(V)) return;
1320 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1321 CopyValueToVirtualRegister(V, Reg);
1324 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1325 const BasicBlock *FromBB) {
1326 // The operands of the setcc have to be in this block. We don't know
1327 // how to export them from some other block.
1328 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1329 // Can export from current BB.
1330 if (VI->getParent() == FromBB)
1333 // Is already exported, noop.
1334 return FuncInfo.isExportedInst(V);
1337 // If this is an argument, we can export it if the BB is the entry block or
1338 // if it is already exported.
1339 if (isa<Argument>(V)) {
1340 if (FromBB == &FromBB->getParent()->getEntryBlock())
1343 // Otherwise, can only export this if it is already exported.
1344 return FuncInfo.isExportedInst(V);
1347 // Otherwise, constants can always be exported.
1351 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1352 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1353 const MachineBasicBlock *Dst) const {
1354 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1357 const BasicBlock *SrcBB = Src->getBasicBlock();
1358 const BasicBlock *DstBB = Dst->getBasicBlock();
1359 return BPI->getEdgeWeight(SrcBB, DstBB);
1362 void SelectionDAGBuilder::
1363 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1364 uint32_t Weight /* = 0 */) {
1366 Weight = getEdgeWeight(Src, Dst);
1367 Src->addSuccessor(Dst, Weight);
1371 static bool InBlock(const Value *V, const BasicBlock *BB) {
1372 if (const Instruction *I = dyn_cast<Instruction>(V))
1373 return I->getParent() == BB;
1377 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1378 /// This function emits a branch and is used at the leaves of an OR or an
1379 /// AND operator tree.
1382 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1383 MachineBasicBlock *TBB,
1384 MachineBasicBlock *FBB,
1385 MachineBasicBlock *CurBB,
1386 MachineBasicBlock *SwitchBB,
1389 const BasicBlock *BB = CurBB->getBasicBlock();
1391 // If the leaf of the tree is a comparison, merge the condition into
1393 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1394 // The operands of the cmp have to be in this block. We don't know
1395 // how to export them from some other block. If this is the first block
1396 // of the sequence, no exporting is needed.
1397 if (CurBB == SwitchBB ||
1398 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1399 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1400 ISD::CondCode Condition;
1401 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1402 Condition = getICmpCondCode(IC->getPredicate());
1403 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1404 Condition = getFCmpCondCode(FC->getPredicate());
1405 if (TM.Options.NoNaNsFPMath)
1406 Condition = getFCmpCodeWithoutNaN(Condition);
1408 Condition = ISD::SETEQ; // silence warning.
1409 llvm_unreachable("Unknown compare instruction");
1412 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1413 TBB, FBB, CurBB, TWeight, FWeight);
1414 SwitchCases.push_back(CB);
1419 // Create a CaseBlock record representing this branch.
1420 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1421 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1422 SwitchCases.push_back(CB);
1425 /// Scale down both weights to fit into uint32_t.
1426 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1427 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1428 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1429 NewTrue = NewTrue / Scale;
1430 NewFalse = NewFalse / Scale;
1433 /// FindMergedConditions - If Cond is an expression like
1434 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1435 MachineBasicBlock *TBB,
1436 MachineBasicBlock *FBB,
1437 MachineBasicBlock *CurBB,
1438 MachineBasicBlock *SwitchBB,
1439 unsigned Opc, uint32_t TWeight,
1441 // If this node is not part of the or/and tree, emit it as a branch.
1442 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1443 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1444 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1445 BOp->getParent() != CurBB->getBasicBlock() ||
1446 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1447 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1448 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1453 // Create TmpBB after CurBB.
1454 MachineFunction::iterator BBI = CurBB;
1455 MachineFunction &MF = DAG.getMachineFunction();
1456 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1457 CurBB->getParent()->insert(++BBI, TmpBB);
1459 if (Opc == Instruction::Or) {
1460 // Codegen X | Y as:
1469 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1470 // The requirement is that
1471 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1472 // = TrueProb for orignal BB.
1473 // Assuming the orignal weights are A and B, one choice is to set BB1's
1474 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1476 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1477 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1478 // TmpBB, but the math is more complicated.
1480 uint64_t NewTrueWeight = TWeight;
1481 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1482 ScaleWeights(NewTrueWeight, NewFalseWeight);
1483 // Emit the LHS condition.
1484 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1485 NewTrueWeight, NewFalseWeight);
1487 NewTrueWeight = TWeight;
1488 NewFalseWeight = 2 * (uint64_t)FWeight;
1489 ScaleWeights(NewTrueWeight, NewFalseWeight);
1490 // Emit the RHS condition into TmpBB.
1491 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1492 NewTrueWeight, NewFalseWeight);
1494 assert(Opc == Instruction::And && "Unknown merge op!");
1495 // Codegen X & Y as:
1503 // This requires creation of TmpBB after CurBB.
1505 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1506 // The requirement is that
1507 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1508 // = FalseProb for orignal BB.
1509 // Assuming the orignal weights are A and B, one choice is to set BB1's
1510 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1512 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1514 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1515 uint64_t NewFalseWeight = FWeight;
1516 ScaleWeights(NewTrueWeight, NewFalseWeight);
1517 // Emit the LHS condition.
1518 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1519 NewTrueWeight, NewFalseWeight);
1521 NewTrueWeight = 2 * (uint64_t)TWeight;
1522 NewFalseWeight = FWeight;
1523 ScaleWeights(NewTrueWeight, NewFalseWeight);
1524 // Emit the RHS condition into TmpBB.
1525 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1526 NewTrueWeight, NewFalseWeight);
1530 /// If the set of cases should be emitted as a series of branches, return true.
1531 /// If we should emit this as a bunch of and/or'd together conditions, return
1534 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1535 if (Cases.size() != 2) return true;
1537 // If this is two comparisons of the same values or'd or and'd together, they
1538 // will get folded into a single comparison, so don't emit two blocks.
1539 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1540 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1541 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1542 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1546 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1547 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1548 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1549 Cases[0].CC == Cases[1].CC &&
1550 isa<Constant>(Cases[0].CmpRHS) &&
1551 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1552 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1554 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1561 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1562 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1564 // Update machine-CFG edges.
1565 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1567 // Figure out which block is immediately after the current one.
1568 MachineBasicBlock *NextBlock = nullptr;
1569 MachineFunction::iterator BBI = BrMBB;
1570 if (++BBI != FuncInfo.MF->end())
1573 if (I.isUnconditional()) {
1574 // Update machine-CFG edges.
1575 BrMBB->addSuccessor(Succ0MBB);
1577 // If this is not a fall-through branch or optimizations are switched off,
1579 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1580 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1581 MVT::Other, getControlRoot(),
1582 DAG.getBasicBlock(Succ0MBB)));
1587 // If this condition is one of the special cases we handle, do special stuff
1589 const Value *CondVal = I.getCondition();
1590 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1592 // If this is a series of conditions that are or'd or and'd together, emit
1593 // this as a sequence of branches instead of setcc's with and/or operations.
1594 // As long as jumps are not expensive, this should improve performance.
1595 // For example, instead of something like:
1608 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1609 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1610 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1611 BOp->getOpcode() == Instruction::Or)) {
1612 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1613 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1614 getEdgeWeight(BrMBB, Succ1MBB));
1615 // If the compares in later blocks need to use values not currently
1616 // exported from this block, export them now. This block should always
1617 // be the first entry.
1618 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1620 // Allow some cases to be rejected.
1621 if (ShouldEmitAsBranches(SwitchCases)) {
1622 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1623 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1624 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1627 // Emit the branch for this block.
1628 visitSwitchCase(SwitchCases[0], BrMBB);
1629 SwitchCases.erase(SwitchCases.begin());
1633 // Okay, we decided not to do this, remove any inserted MBB's and clear
1635 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1636 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1638 SwitchCases.clear();
1642 // Create a CaseBlock record representing this branch.
1643 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1644 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1646 // Use visitSwitchCase to actually insert the fast branch sequence for this
1648 visitSwitchCase(CB, BrMBB);
1651 /// visitSwitchCase - Emits the necessary code to represent a single node in
1652 /// the binary search tree resulting from lowering a switch instruction.
1653 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1654 MachineBasicBlock *SwitchBB) {
1656 SDValue CondLHS = getValue(CB.CmpLHS);
1657 SDLoc dl = getCurSDLoc();
1659 // Build the setcc now.
1661 // Fold "(X == true)" to X and "(X == false)" to !X to
1662 // handle common cases produced by branch lowering.
1663 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1664 CB.CC == ISD::SETEQ)
1666 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1667 CB.CC == ISD::SETEQ) {
1668 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1669 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1671 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1673 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1675 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1676 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1678 SDValue CmpOp = getValue(CB.CmpMHS);
1679 EVT VT = CmpOp.getValueType();
1681 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1682 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1685 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1686 VT, CmpOp, DAG.getConstant(Low, VT));
1687 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1688 DAG.getConstant(High-Low, VT), ISD::SETULE);
1692 // Update successor info
1693 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1694 // TrueBB and FalseBB are always different unless the incoming IR is
1695 // degenerate. This only happens when running llc on weird IR.
1696 if (CB.TrueBB != CB.FalseBB)
1697 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1699 // Set NextBlock to be the MBB immediately after the current one, if any.
1700 // This is used to avoid emitting unnecessary branches to the next block.
1701 MachineBasicBlock *NextBlock = nullptr;
1702 MachineFunction::iterator BBI = SwitchBB;
1703 if (++BBI != FuncInfo.MF->end())
1706 // If the lhs block is the next block, invert the condition so that we can
1707 // fall through to the lhs instead of the rhs block.
1708 if (CB.TrueBB == NextBlock) {
1709 std::swap(CB.TrueBB, CB.FalseBB);
1710 SDValue True = DAG.getConstant(1, Cond.getValueType());
1711 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1714 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1715 MVT::Other, getControlRoot(), Cond,
1716 DAG.getBasicBlock(CB.TrueBB));
1718 // Insert the false branch. Do this even if it's a fall through branch,
1719 // this makes it easier to do DAG optimizations which require inverting
1720 // the branch condition.
1721 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1722 DAG.getBasicBlock(CB.FalseBB));
1724 DAG.setRoot(BrCond);
1727 /// visitJumpTable - Emit JumpTable node in the current MBB
1728 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1729 // Emit the code for the jump table
1730 assert(JT.Reg != -1U && "Should lower JT Header first!");
1731 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1732 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1734 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1735 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1736 MVT::Other, Index.getValue(1),
1738 DAG.setRoot(BrJumpTable);
1741 /// visitJumpTableHeader - This function emits necessary code to produce index
1742 /// in the JumpTable from switch case.
1743 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1744 JumpTableHeader &JTH,
1745 MachineBasicBlock *SwitchBB) {
1746 // Subtract the lowest switch case value from the value being switched on and
1747 // conditional branch to default mbb if the result is greater than the
1748 // difference between smallest and largest cases.
1749 SDValue SwitchOp = getValue(JTH.SValue);
1750 EVT VT = SwitchOp.getValueType();
1751 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1752 DAG.getConstant(JTH.First, VT));
1754 // The SDNode we just created, which holds the value being switched on minus
1755 // the smallest case value, needs to be copied to a virtual register so it
1756 // can be used as an index into the jump table in a subsequent basic block.
1757 // This value may be smaller or larger than the target's pointer type, and
1758 // therefore require extension or truncating.
1759 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1760 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1762 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1763 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1764 JumpTableReg, SwitchOp);
1765 JT.Reg = JumpTableReg;
1767 // Emit the range check for the jump table, and branch to the default block
1768 // for the switch statement if the value being switched on exceeds the largest
1769 // case in the switch.
1771 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1772 Sub.getValueType()),
1773 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1775 // Set NextBlock to be the MBB immediately after the current one, if any.
1776 // This is used to avoid emitting unnecessary branches to the next block.
1777 MachineBasicBlock *NextBlock = nullptr;
1778 MachineFunction::iterator BBI = SwitchBB;
1780 if (++BBI != FuncInfo.MF->end())
1783 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1784 MVT::Other, CopyTo, CMP,
1785 DAG.getBasicBlock(JT.Default));
1787 if (JT.MBB != NextBlock)
1788 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1789 DAG.getBasicBlock(JT.MBB));
1791 DAG.setRoot(BrCond);
1794 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1795 /// tail spliced into a stack protector check success bb.
1797 /// For a high level explanation of how this fits into the stack protector
1798 /// generation see the comment on the declaration of class
1799 /// StackProtectorDescriptor.
1800 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1801 MachineBasicBlock *ParentBB) {
1803 // First create the loads to the guard/stack slot for the comparison.
1804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1805 EVT PtrTy = TLI.getPointerTy();
1807 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1808 int FI = MFI->getStackProtectorIndex();
1810 const Value *IRGuard = SPD.getGuard();
1811 SDValue GuardPtr = getValue(IRGuard);
1812 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1815 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1819 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1820 // guard value from the virtual register holding the value. Otherwise, emit a
1821 // volatile load to retrieve the stack guard value.
1822 unsigned GuardReg = SPD.getGuardReg();
1824 if (GuardReg && TLI.useLoadStackGuardNode())
1825 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1828 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1829 GuardPtr, MachinePointerInfo(IRGuard, 0),
1830 true, false, false, Align);
1832 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1834 MachinePointerInfo::getFixedStack(FI),
1835 true, false, false, Align);
1837 // Perform the comparison via a subtract/getsetcc.
1838 EVT VT = Guard.getValueType();
1839 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1842 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1843 Sub.getValueType()),
1844 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1846 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1847 // branch to failure MBB.
1848 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1849 MVT::Other, StackSlot.getOperand(0),
1850 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1851 // Otherwise branch to success MBB.
1852 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1854 DAG.getBasicBlock(SPD.getSuccessMBB()));
1859 /// Codegen the failure basic block for a stack protector check.
1861 /// A failure stack protector machine basic block consists simply of a call to
1862 /// __stack_chk_fail().
1864 /// For a high level explanation of how this fits into the stack protector
1865 /// generation see the comment on the declaration of class
1866 /// StackProtectorDescriptor.
1868 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1871 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1872 nullptr, 0, false, getCurSDLoc(), false, false).second;
1876 /// visitBitTestHeader - This function emits necessary code to produce value
1877 /// suitable for "bit tests"
1878 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1879 MachineBasicBlock *SwitchBB) {
1880 // Subtract the minimum value
1881 SDValue SwitchOp = getValue(B.SValue);
1882 EVT VT = SwitchOp.getValueType();
1883 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1884 DAG.getConstant(B.First, VT));
1887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1889 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1890 Sub.getValueType()),
1891 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1893 // Determine the type of the test operands.
1894 bool UsePtrType = false;
1895 if (!TLI.isTypeLegal(VT))
1898 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1899 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1900 // Switch table case range are encoded into series of masks.
1901 // Just use pointer type, it's guaranteed to fit.
1907 VT = TLI.getPointerTy();
1908 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1911 B.RegVT = VT.getSimpleVT();
1912 B.Reg = FuncInfo.CreateReg(B.RegVT);
1913 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1916 // Set NextBlock to be the MBB immediately after the current one, if any.
1917 // This is used to avoid emitting unnecessary branches to the next block.
1918 MachineBasicBlock *NextBlock = nullptr;
1919 MachineFunction::iterator BBI = SwitchBB;
1920 if (++BBI != FuncInfo.MF->end())
1923 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1925 addSuccessorWithWeight(SwitchBB, B.Default);
1926 addSuccessorWithWeight(SwitchBB, MBB);
1928 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1929 MVT::Other, CopyTo, RangeCmp,
1930 DAG.getBasicBlock(B.Default));
1932 if (MBB != NextBlock)
1933 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1934 DAG.getBasicBlock(MBB));
1936 DAG.setRoot(BrRange);
1939 /// visitBitTestCase - this function produces one "bit test"
1940 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1941 MachineBasicBlock* NextMBB,
1942 uint32_t BranchWeightToNext,
1945 MachineBasicBlock *SwitchBB) {
1947 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1950 unsigned PopCount = CountPopulation_64(B.Mask);
1951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1952 if (PopCount == 1) {
1953 // Testing for a single bit; just compare the shift count with what it
1954 // would need to be to shift a 1 bit in that position.
1956 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1957 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1958 } else if (PopCount == BB.Range) {
1959 // There is only one zero bit in the range, test for it directly.
1961 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1962 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE);
1964 // Make desired shift
1965 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1966 DAG.getConstant(1, VT), ShiftOp);
1968 // Emit bit tests and jumps
1969 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1970 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1971 Cmp = DAG.getSetCC(getCurSDLoc(),
1972 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1973 DAG.getConstant(0, VT), ISD::SETNE);
1976 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1977 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1978 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1979 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1981 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1982 MVT::Other, getControlRoot(),
1983 Cmp, DAG.getBasicBlock(B.TargetBB));
1985 // Set NextBlock to be the MBB immediately after the current one, if any.
1986 // This is used to avoid emitting unnecessary branches to the next block.
1987 MachineBasicBlock *NextBlock = nullptr;
1988 MachineFunction::iterator BBI = SwitchBB;
1989 if (++BBI != FuncInfo.MF->end())
1992 if (NextMBB != NextBlock)
1993 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1994 DAG.getBasicBlock(NextMBB));
1999 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2000 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2002 // Retrieve successors.
2003 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2004 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2006 const Value *Callee(I.getCalledValue());
2007 const Function *Fn = dyn_cast<Function>(Callee);
2008 if (isa<InlineAsm>(Callee))
2010 else if (Fn && Fn->isIntrinsic()) {
2011 switch (Fn->getIntrinsicID()) {
2013 llvm_unreachable("Cannot invoke this intrinsic");
2014 case Intrinsic::donothing:
2015 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2017 case Intrinsic::experimental_patchpoint_void:
2018 case Intrinsic::experimental_patchpoint_i64:
2019 visitPatchpoint(&I, LandingPad);
2023 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2025 // If the value of the invoke is used outside of its defining block, make it
2026 // available as a virtual register.
2027 CopyToExportRegsIfNeeded(&I);
2029 // Update successor info
2030 addSuccessorWithWeight(InvokeMBB, Return);
2031 addSuccessorWithWeight(InvokeMBB, LandingPad);
2033 // Drop into normal successor.
2034 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2035 MVT::Other, getControlRoot(),
2036 DAG.getBasicBlock(Return)));
2039 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2040 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2043 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2044 assert(FuncInfo.MBB->isLandingPad() &&
2045 "Call to landingpad not in landing pad!");
2047 MachineBasicBlock *MBB = FuncInfo.MBB;
2048 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2049 AddLandingPadInfo(LP, MMI, MBB);
2051 // If there aren't registers to copy the values into (e.g., during SjLj
2052 // exceptions), then don't bother to create these DAG nodes.
2053 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2054 if (TLI.getExceptionPointerRegister() == 0 &&
2055 TLI.getExceptionSelectorRegister() == 0)
2058 SmallVector<EVT, 2> ValueVTs;
2059 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2060 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2062 // Get the two live-in registers as SDValues. The physregs have already been
2063 // copied into virtual registers.
2065 Ops[0] = DAG.getZExtOrTrunc(
2066 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2067 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2068 getCurSDLoc(), ValueVTs[0]);
2069 Ops[1] = DAG.getZExtOrTrunc(
2070 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2071 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2072 getCurSDLoc(), ValueVTs[1]);
2075 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2076 DAG.getVTList(ValueVTs), Ops);
2080 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2081 /// small case ranges).
2082 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2083 CaseRecVector& WorkList,
2085 MachineBasicBlock *Default,
2086 MachineBasicBlock *SwitchBB) {
2087 // Size is the number of Cases represented by this range.
2088 size_t Size = CR.Range.second - CR.Range.first;
2092 // Get the MachineFunction which holds the current MBB. This is used when
2093 // inserting any additional MBBs necessary to represent the switch.
2094 MachineFunction *CurMF = FuncInfo.MF;
2096 // Figure out which block is immediately after the current one.
2097 MachineBasicBlock *NextBlock = nullptr;
2098 MachineFunction::iterator BBI = CR.CaseBB;
2100 if (++BBI != FuncInfo.MF->end())
2103 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2104 // If any two of the cases has the same destination, and if one value
2105 // is the same as the other, but has one bit unset that the other has set,
2106 // use bit manipulation to do two compares at once. For example:
2107 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2108 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2109 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2110 if (Size == 2 && CR.CaseBB == SwitchBB) {
2111 Case &Small = *CR.Range.first;
2112 Case &Big = *(CR.Range.second-1);
2114 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2115 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2116 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2118 // Check that there is only one bit different.
2119 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2120 (SmallValue | BigValue) == BigValue) {
2121 // Isolate the common bit.
2122 APInt CommonBit = BigValue & ~SmallValue;
2123 assert((SmallValue | CommonBit) == BigValue &&
2124 CommonBit.countPopulation() == 1 && "Not a common bit?");
2126 SDValue CondLHS = getValue(SV);
2127 EVT VT = CondLHS.getValueType();
2128 SDLoc DL = getCurSDLoc();
2130 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2131 DAG.getConstant(CommonBit, VT));
2132 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2133 Or, DAG.getConstant(BigValue, VT),
2136 // Update successor info.
2137 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2138 addSuccessorWithWeight(SwitchBB, Small.BB,
2139 Small.ExtraWeight + Big.ExtraWeight);
2140 addSuccessorWithWeight(SwitchBB, Default,
2141 // The default destination is the first successor in IR.
2142 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2144 // Insert the true branch.
2145 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2146 getControlRoot(), Cond,
2147 DAG.getBasicBlock(Small.BB));
2149 // Insert the false branch.
2150 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2151 DAG.getBasicBlock(Default));
2153 DAG.setRoot(BrCond);
2159 // Order cases by weight so the most likely case will be checked first.
2160 uint32_t UnhandledWeights = 0;
2162 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2163 uint32_t IWeight = I->ExtraWeight;
2164 UnhandledWeights += IWeight;
2165 for (CaseItr J = CR.Range.first; J < I; ++J) {
2166 uint32_t JWeight = J->ExtraWeight;
2167 if (IWeight > JWeight)
2172 // Rearrange the case blocks so that the last one falls through if possible.
2173 Case &BackCase = *(CR.Range.second-1);
2175 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2176 // The last case block won't fall through into 'NextBlock' if we emit the
2177 // branches in this order. See if rearranging a case value would help.
2178 // We start at the bottom as it's the case with the least weight.
2179 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2180 if (I->BB == NextBlock) {
2181 std::swap(*I, BackCase);
2186 // Create a CaseBlock record representing a conditional branch to
2187 // the Case's target mbb if the value being switched on SV is equal
2189 MachineBasicBlock *CurBlock = CR.CaseBB;
2190 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2191 MachineBasicBlock *FallThrough;
2193 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2194 CurMF->insert(BBI, FallThrough);
2196 // Put SV in a virtual register to make it available from the new blocks.
2197 ExportFromCurrentBlock(SV);
2199 // If the last case doesn't match, go to the default block.
2200 FallThrough = Default;
2203 const Value *RHS, *LHS, *MHS;
2205 if (I->High == I->Low) {
2206 // This is just small small case range :) containing exactly 1 case
2208 LHS = SV; RHS = I->High; MHS = nullptr;
2211 LHS = I->Low; MHS = SV; RHS = I->High;
2214 // The false weight should be sum of all un-handled cases.
2215 UnhandledWeights -= I->ExtraWeight;
2216 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2218 /* trueweight */ I->ExtraWeight,
2219 /* falseweight */ UnhandledWeights);
2221 // If emitting the first comparison, just call visitSwitchCase to emit the
2222 // code into the current block. Otherwise, push the CaseBlock onto the
2223 // vector to be later processed by SDISel, and insert the node's MBB
2224 // before the next MBB.
2225 if (CurBlock == SwitchBB)
2226 visitSwitchCase(CB, SwitchBB);
2228 SwitchCases.push_back(CB);
2230 CurBlock = FallThrough;
2236 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2237 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2238 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2241 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2242 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2243 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2244 return (LastExt - FirstExt + 1ULL);
2247 /// handleJTSwitchCase - Emit jumptable for current switch case range
2248 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2249 CaseRecVector &WorkList,
2251 MachineBasicBlock *Default,
2252 MachineBasicBlock *SwitchBB) {
2253 Case& FrontCase = *CR.Range.first;
2254 Case& BackCase = *(CR.Range.second-1);
2256 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2257 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2259 APInt TSize(First.getBitWidth(), 0);
2260 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2263 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2264 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2267 APInt Range = ComputeRange(First, Last);
2268 // The density is TSize / Range. Require at least 40%.
2269 // It should not be possible for IntTSize to saturate for sane code, but make
2270 // sure we handle Range saturation correctly.
2271 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2272 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2273 if (IntTSize * 10 < IntRange * 4)
2276 DEBUG(dbgs() << "Lowering jump table\n"
2277 << "First entry: " << First << ". Last entry: " << Last << '\n'
2278 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2280 // Get the MachineFunction which holds the current MBB. This is used when
2281 // inserting any additional MBBs necessary to represent the switch.
2282 MachineFunction *CurMF = FuncInfo.MF;
2284 // Figure out which block is immediately after the current one.
2285 MachineFunction::iterator BBI = CR.CaseBB;
2288 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2290 // Create a new basic block to hold the code for loading the address
2291 // of the jump table, and jumping to it. Update successor information;
2292 // we will either branch to the default case for the switch, or the jump
2294 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2295 CurMF->insert(BBI, JumpTableBB);
2297 addSuccessorWithWeight(CR.CaseBB, Default);
2298 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2300 // Build a vector of destination BBs, corresponding to each target
2301 // of the jump table. If the value of the jump table slot corresponds to
2302 // a case statement, push the case's BB onto the vector, otherwise, push
2304 std::vector<MachineBasicBlock*> DestBBs;
2306 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2307 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2308 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2310 if (Low.sle(TEI) && TEI.sle(High)) {
2311 DestBBs.push_back(I->BB);
2315 DestBBs.push_back(Default);
2319 // Calculate weight for each unique destination in CR.
2320 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2322 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2323 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2324 DestWeights.find(I->BB);
2325 if (Itr != DestWeights.end())
2326 Itr->second += I->ExtraWeight;
2328 DestWeights[I->BB] = I->ExtraWeight;
2331 // Update successor info. Add one edge to each unique successor.
2332 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2333 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2334 E = DestBBs.end(); I != E; ++I) {
2335 if (!SuccsHandled[(*I)->getNumber()]) {
2336 SuccsHandled[(*I)->getNumber()] = true;
2337 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2338 DestWeights.find(*I);
2339 addSuccessorWithWeight(JumpTableBB, *I,
2340 Itr != DestWeights.end() ? Itr->second : 0);
2344 // Create a jump table index for this jump table.
2345 unsigned JTEncoding = TLI.getJumpTableEncoding();
2346 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2347 ->createJumpTableIndex(DestBBs);
2349 // Set the jump table information so that we can codegen it as a second
2350 // MachineBasicBlock
2351 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2352 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2353 if (CR.CaseBB == SwitchBB)
2354 visitJumpTableHeader(JT, JTH, SwitchBB);
2356 JTCases.push_back(JumpTableBlock(JTH, JT));
2360 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2362 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2363 CaseRecVector& WorkList,
2365 MachineBasicBlock* SwitchBB) {
2366 // Get the MachineFunction which holds the current MBB. This is used when
2367 // inserting any additional MBBs necessary to represent the switch.
2368 MachineFunction *CurMF = FuncInfo.MF;
2370 // Figure out which block is immediately after the current one.
2371 MachineFunction::iterator BBI = CR.CaseBB;
2374 Case& FrontCase = *CR.Range.first;
2375 Case& BackCase = *(CR.Range.second-1);
2376 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2378 // Size is the number of Cases represented by this range.
2379 unsigned Size = CR.Range.second - CR.Range.first;
2381 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2382 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2384 CaseItr Pivot = CR.Range.first + Size/2;
2386 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2387 // (heuristically) allow us to emit JumpTable's later.
2388 APInt TSize(First.getBitWidth(), 0);
2389 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2393 APInt LSize = FrontCase.size();
2394 APInt RSize = TSize-LSize;
2395 DEBUG(dbgs() << "Selecting best pivot: \n"
2396 << "First: " << First << ", Last: " << Last <<'\n'
2397 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2398 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2400 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2401 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2402 APInt Range = ComputeRange(LEnd, RBegin);
2403 assert((Range - 2ULL).isNonNegative() &&
2404 "Invalid case distance");
2405 // Use volatile double here to avoid excess precision issues on some hosts,
2406 // e.g. that use 80-bit X87 registers.
2407 volatile double LDensity =
2408 (double)LSize.roundToDouble() /
2409 (LEnd - First + 1ULL).roundToDouble();
2410 volatile double RDensity =
2411 (double)RSize.roundToDouble() /
2412 (Last - RBegin + 1ULL).roundToDouble();
2413 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2414 // Should always split in some non-trivial place
2415 DEBUG(dbgs() <<"=>Step\n"
2416 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2417 << "LDensity: " << LDensity
2418 << ", RDensity: " << RDensity << '\n'
2419 << "Metric: " << Metric << '\n');
2420 if (FMetric < Metric) {
2423 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2431 if (areJTsAllowed(TLI)) {
2432 // If our case is dense we *really* should handle it earlier!
2433 assert((FMetric > 0) && "Should handle dense range earlier!");
2435 Pivot = CR.Range.first + Size/2;
2438 CaseRange LHSR(CR.Range.first, Pivot);
2439 CaseRange RHSR(Pivot, CR.Range.second);
2440 const Constant *C = Pivot->Low;
2441 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2443 // We know that we branch to the LHS if the Value being switched on is
2444 // less than the Pivot value, C. We use this to optimize our binary
2445 // tree a bit, by recognizing that if SV is greater than or equal to the
2446 // LHS's Case Value, and that Case Value is exactly one less than the
2447 // Pivot's Value, then we can branch directly to the LHS's Target,
2448 // rather than creating a leaf node for it.
2449 if ((LHSR.second - LHSR.first) == 1 &&
2450 LHSR.first->High == CR.GE &&
2451 cast<ConstantInt>(C)->getValue() ==
2452 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2453 TrueBB = LHSR.first->BB;
2455 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2456 CurMF->insert(BBI, TrueBB);
2457 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2459 // Put SV in a virtual register to make it available from the new blocks.
2460 ExportFromCurrentBlock(SV);
2463 // Similar to the optimization above, if the Value being switched on is
2464 // known to be less than the Constant CR.LT, and the current Case Value
2465 // is CR.LT - 1, then we can branch directly to the target block for
2466 // the current Case Value, rather than emitting a RHS leaf node for it.
2467 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2468 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2469 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2470 FalseBB = RHSR.first->BB;
2472 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2473 CurMF->insert(BBI, FalseBB);
2474 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2476 // Put SV in a virtual register to make it available from the new blocks.
2477 ExportFromCurrentBlock(SV);
2480 // Create a CaseBlock record representing a conditional branch to
2481 // the LHS node if the value being switched on SV is less than C.
2482 // Otherwise, branch to LHS.
2483 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2485 if (CR.CaseBB == SwitchBB)
2486 visitSwitchCase(CB, SwitchBB);
2488 SwitchCases.push_back(CB);
2493 /// handleBitTestsSwitchCase - if current case range has few destination and
2494 /// range span less, than machine word bitwidth, encode case range into series
2495 /// of masks and emit bit tests with these masks.
2496 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2497 CaseRecVector& WorkList,
2499 MachineBasicBlock* Default,
2500 MachineBasicBlock* SwitchBB) {
2501 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2502 EVT PTy = TLI.getPointerTy();
2503 unsigned IntPtrBits = PTy.getSizeInBits();
2505 Case& FrontCase = *CR.Range.first;
2506 Case& BackCase = *(CR.Range.second-1);
2508 // Get the MachineFunction which holds the current MBB. This is used when
2509 // inserting any additional MBBs necessary to represent the switch.
2510 MachineFunction *CurMF = FuncInfo.MF;
2512 // If target does not have legal shift left, do not emit bit tests at all.
2513 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2517 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2518 // Single case counts one, case range - two.
2519 numCmps += (I->Low == I->High ? 1 : 2);
2522 // Count unique destinations
2523 SmallSet<MachineBasicBlock*, 4> Dests;
2524 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2525 Dests.insert(I->BB);
2526 if (Dests.size() > 3)
2527 // Don't bother the code below, if there are too much unique destinations
2530 DEBUG(dbgs() << "Total number of unique destinations: "
2531 << Dests.size() << '\n'
2532 << "Total number of comparisons: " << numCmps << '\n');
2534 // Compute span of values.
2535 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2536 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2537 APInt cmpRange = maxValue - minValue;
2539 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2540 << "Low bound: " << minValue << '\n'
2541 << "High bound: " << maxValue << '\n');
2543 if (cmpRange.uge(IntPtrBits) ||
2544 (!(Dests.size() == 1 && numCmps >= 3) &&
2545 !(Dests.size() == 2 && numCmps >= 5) &&
2546 !(Dests.size() >= 3 && numCmps >= 6)))
2549 DEBUG(dbgs() << "Emitting bit tests\n");
2550 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2552 // Optimize the case where all the case values fit in a
2553 // word without having to subtract minValue. In this case,
2554 // we can optimize away the subtraction.
2555 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2556 cmpRange = maxValue;
2558 lowBound = minValue;
2561 CaseBitsVector CasesBits;
2562 unsigned i, count = 0;
2564 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2565 MachineBasicBlock* Dest = I->BB;
2566 for (i = 0; i < count; ++i)
2567 if (Dest == CasesBits[i].BB)
2571 assert((count < 3) && "Too much destinations to test!");
2572 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2576 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2577 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2579 uint64_t lo = (lowValue - lowBound).getZExtValue();
2580 uint64_t hi = (highValue - lowBound).getZExtValue();
2581 CasesBits[i].ExtraWeight += I->ExtraWeight;
2583 for (uint64_t j = lo; j <= hi; j++) {
2584 CasesBits[i].Mask |= 1ULL << j;
2585 CasesBits[i].Bits++;
2589 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2593 // Figure out which block is immediately after the current one.
2594 MachineFunction::iterator BBI = CR.CaseBB;
2597 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2599 DEBUG(dbgs() << "Cases:\n");
2600 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2601 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2602 << ", Bits: " << CasesBits[i].Bits
2603 << ", BB: " << CasesBits[i].BB << '\n');
2605 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2606 CurMF->insert(BBI, CaseBB);
2607 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2609 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2611 // Put SV in a virtual register to make it available from the new blocks.
2612 ExportFromCurrentBlock(SV);
2615 BitTestBlock BTB(lowBound, cmpRange, SV,
2616 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2617 CR.CaseBB, Default, std::move(BTC));
2619 if (CR.CaseBB == SwitchBB)
2620 visitBitTestHeader(BTB, SwitchBB);
2622 BitTestCases.push_back(std::move(BTB));
2627 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2628 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2629 const SwitchInst& SI) {
2630 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2631 // Start with "simple" cases.
2632 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2633 const BasicBlock *SuccBB = i.getCaseSuccessor();
2634 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2636 uint32_t ExtraWeight =
2637 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2639 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2640 SMBB, ExtraWeight));
2642 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2644 // Merge case into clusters
2645 if (Cases.size() >= 2)
2646 // Must recompute end() each iteration because it may be
2647 // invalidated by erase if we hold on to it
2648 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2649 J != Cases.end(); ) {
2650 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2651 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2652 MachineBasicBlock* nextBB = J->BB;
2653 MachineBasicBlock* currentBB = I->BB;
2655 // If the two neighboring cases go to the same destination, merge them
2656 // into a single case.
2657 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2659 I->ExtraWeight += J->ExtraWeight;
2668 for (auto &I : Cases)
2669 // A range counts double, since it requires two compares.
2670 numCmps += I.Low != I.High ? 2 : 1;
2672 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2673 << ". Total compares: " << numCmps << '\n';
2677 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2678 MachineBasicBlock *Last) {
2680 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2681 if (JTCases[i].first.HeaderBB == First)
2682 JTCases[i].first.HeaderBB = Last;
2684 // Update BitTestCases.
2685 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2686 if (BitTestCases[i].Parent == First)
2687 BitTestCases[i].Parent = Last;
2690 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2691 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2693 // Figure out which block is immediately after the current one.
2694 MachineBasicBlock *NextBlock = nullptr;
2695 if (SwitchMBB + 1 != FuncInfo.MF->end())
2696 NextBlock = SwitchMBB + 1;
2699 // Create a vector of Cases, sorted so that we can efficiently create a binary
2700 // search tree from them.
2702 Clusterify(Cases, SI);
2704 // Get the default destination MBB.
2705 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2707 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg())) {
2708 // Replace an unreachable default destination with the most popular case
2710 DenseMap<const BasicBlock*, uint64_t> Popularity;
2711 uint64_t MaxPop = 0;
2712 const BasicBlock *MaxBB = nullptr;
2713 for (auto I : SI.cases()) {
2714 const BasicBlock *BB = I.getCaseSuccessor();
2715 if (++Popularity[BB] > MaxPop) {
2716 MaxPop = Popularity[BB];
2722 Default = FuncInfo.MBBMap[MaxBB];
2724 // Remove cases that have been replaced by the default.
2725 CaseItr I = Cases.begin();
2726 while (I != Cases.end()) {
2727 if (I->BB == Default) {
2735 // If there is only the default destination, go there directly.
2736 if (Cases.empty()) {
2737 // Update machine-CFG edges.
2738 SwitchMBB->addSuccessor(Default);
2740 // If this is not a fall-through branch, emit the branch.
2741 if (Default != NextBlock) {
2742 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2743 getControlRoot(), DAG.getBasicBlock(Default)));
2748 // Get the Value to be switched on.
2749 const Value *SV = SI.getCondition();
2751 // Push the initial CaseRec onto the worklist
2752 CaseRecVector WorkList;
2753 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2754 CaseRange(Cases.begin(),Cases.end())));
2756 while (!WorkList.empty()) {
2757 // Grab a record representing a case range to process off the worklist
2758 CaseRec CR = WorkList.back();
2759 WorkList.pop_back();
2761 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2764 // If the range has few cases (two or less) emit a series of specific
2766 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2769 // If the switch has more than N blocks, and is at least 40% dense, and the
2770 // target supports indirect branches, then emit a jump table rather than
2771 // lowering the switch to a binary tree of conditional branches.
2772 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2773 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2776 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2777 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2778 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2782 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2783 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2785 // Update machine-CFG edges with unique successors.
2786 SmallSet<BasicBlock*, 32> Done;
2787 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2788 BasicBlock *BB = I.getSuccessor(i);
2789 bool Inserted = Done.insert(BB).second;
2793 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2794 addSuccessorWithWeight(IndirectBrMBB, Succ);
2797 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2798 MVT::Other, getControlRoot(),
2799 getValue(I.getAddress())));
2802 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2803 if (DAG.getTarget().Options.TrapUnreachable)
2804 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2807 void SelectionDAGBuilder::visitFSub(const User &I) {
2808 // -0.0 - X --> fneg
2809 Type *Ty = I.getType();
2810 if (isa<Constant>(I.getOperand(0)) &&
2811 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2812 SDValue Op2 = getValue(I.getOperand(1));
2813 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2814 Op2.getValueType(), Op2));
2818 visitBinary(I, ISD::FSUB);
2821 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2822 SDValue Op1 = getValue(I.getOperand(0));
2823 SDValue Op2 = getValue(I.getOperand(1));
2828 if (const OverflowingBinaryOperator *OFBinOp =
2829 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2830 nuw = OFBinOp->hasNoUnsignedWrap();
2831 nsw = OFBinOp->hasNoSignedWrap();
2833 if (const PossiblyExactOperator *ExactOp =
2834 dyn_cast<const PossiblyExactOperator>(&I))
2835 exact = ExactOp->isExact();
2837 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2838 Op1, Op2, nuw, nsw, exact);
2839 setValue(&I, BinNodeValue);
2842 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2843 SDValue Op1 = getValue(I.getOperand(0));
2844 SDValue Op2 = getValue(I.getOperand(1));
2847 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2849 // Coerce the shift amount to the right type if we can.
2850 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2851 unsigned ShiftSize = ShiftTy.getSizeInBits();
2852 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2853 SDLoc DL = getCurSDLoc();
2855 // If the operand is smaller than the shift count type, promote it.
2856 if (ShiftSize > Op2Size)
2857 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2859 // If the operand is larger than the shift count type but the shift
2860 // count type has enough bits to represent any shift value, truncate
2861 // it now. This is a common case and it exposes the truncate to
2862 // optimization early.
2863 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2864 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2865 // Otherwise we'll need to temporarily settle for some other convenient
2866 // type. Type legalization will make adjustments once the shiftee is split.
2868 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2875 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2877 if (const OverflowingBinaryOperator *OFBinOp =
2878 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2879 nuw = OFBinOp->hasNoUnsignedWrap();
2880 nsw = OFBinOp->hasNoSignedWrap();
2882 if (const PossiblyExactOperator *ExactOp =
2883 dyn_cast<const PossiblyExactOperator>(&I))
2884 exact = ExactOp->isExact();
2887 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2892 void SelectionDAGBuilder::visitSDiv(const User &I) {
2893 SDValue Op1 = getValue(I.getOperand(0));
2894 SDValue Op2 = getValue(I.getOperand(1));
2896 // Turn exact SDivs into multiplications.
2897 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2899 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2900 !isa<ConstantSDNode>(Op1) &&
2901 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2902 setValue(&I, DAG.getTargetLoweringInfo()
2903 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2905 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2909 void SelectionDAGBuilder::visitICmp(const User &I) {
2910 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2911 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2912 predicate = IC->getPredicate();
2913 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2914 predicate = ICmpInst::Predicate(IC->getPredicate());
2915 SDValue Op1 = getValue(I.getOperand(0));
2916 SDValue Op2 = getValue(I.getOperand(1));
2917 ISD::CondCode Opcode = getICmpCondCode(predicate);
2919 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2920 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2923 void SelectionDAGBuilder::visitFCmp(const User &I) {
2924 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2925 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2926 predicate = FC->getPredicate();
2927 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2928 predicate = FCmpInst::Predicate(FC->getPredicate());
2929 SDValue Op1 = getValue(I.getOperand(0));
2930 SDValue Op2 = getValue(I.getOperand(1));
2931 ISD::CondCode Condition = getFCmpCondCode(predicate);
2932 if (TM.Options.NoNaNsFPMath)
2933 Condition = getFCmpCodeWithoutNaN(Condition);
2934 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2935 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2938 void SelectionDAGBuilder::visitSelect(const User &I) {
2939 SmallVector<EVT, 4> ValueVTs;
2940 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2941 unsigned NumValues = ValueVTs.size();
2942 if (NumValues == 0) return;
2944 SmallVector<SDValue, 4> Values(NumValues);
2945 SDValue Cond = getValue(I.getOperand(0));
2946 SDValue TrueVal = getValue(I.getOperand(1));
2947 SDValue FalseVal = getValue(I.getOperand(2));
2948 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2949 ISD::VSELECT : ISD::SELECT;
2951 for (unsigned i = 0; i != NumValues; ++i)
2952 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2953 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2955 SDValue(TrueVal.getNode(),
2956 TrueVal.getResNo() + i),
2957 SDValue(FalseVal.getNode(),
2958 FalseVal.getResNo() + i));
2960 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2961 DAG.getVTList(ValueVTs), Values));
2964 void SelectionDAGBuilder::visitTrunc(const User &I) {
2965 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2966 SDValue N = getValue(I.getOperand(0));
2967 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2968 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2971 void SelectionDAGBuilder::visitZExt(const User &I) {
2972 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2973 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2974 SDValue N = getValue(I.getOperand(0));
2975 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2976 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2979 void SelectionDAGBuilder::visitSExt(const User &I) {
2980 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2981 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2982 SDValue N = getValue(I.getOperand(0));
2983 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2984 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2987 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2988 // FPTrunc is never a no-op cast, no need to check
2989 SDValue N = getValue(I.getOperand(0));
2990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2991 EVT DestVT = TLI.getValueType(I.getType());
2992 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2993 DAG.getTargetConstant(0, TLI.getPointerTy())));
2996 void SelectionDAGBuilder::visitFPExt(const User &I) {
2997 // FPExt is never a no-op cast, no need to check
2998 SDValue N = getValue(I.getOperand(0));
2999 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3000 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3003 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3004 // FPToUI is never a no-op cast, no need to check
3005 SDValue N = getValue(I.getOperand(0));
3006 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3007 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3010 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3011 // FPToSI is never a no-op cast, no need to check
3012 SDValue N = getValue(I.getOperand(0));
3013 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3014 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3017 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3018 // UIToFP is never a no-op cast, no need to check
3019 SDValue N = getValue(I.getOperand(0));
3020 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3021 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3024 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3025 // SIToFP is never a no-op cast, no need to check
3026 SDValue N = getValue(I.getOperand(0));
3027 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3028 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3031 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3032 // What to do depends on the size of the integer and the size of the pointer.
3033 // We can either truncate, zero extend, or no-op, accordingly.
3034 SDValue N = getValue(I.getOperand(0));
3035 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3036 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3039 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3040 // What to do depends on the size of the integer and the size of the pointer.
3041 // We can either truncate, zero extend, or no-op, accordingly.
3042 SDValue N = getValue(I.getOperand(0));
3043 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3044 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3047 void SelectionDAGBuilder::visitBitCast(const User &I) {
3048 SDValue N = getValue(I.getOperand(0));
3049 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3051 // BitCast assures us that source and destination are the same size so this is
3052 // either a BITCAST or a no-op.
3053 if (DestVT != N.getValueType())
3054 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3055 DestVT, N)); // convert types.
3056 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3057 // might fold any kind of constant expression to an integer constant and that
3058 // is not what we are looking for. Only regcognize a bitcast of a genuine
3059 // constant integer as an opaque constant.
3060 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3061 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3064 setValue(&I, N); // noop cast.
3067 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3068 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3069 const Value *SV = I.getOperand(0);
3070 SDValue N = getValue(SV);
3071 EVT DestVT = TLI.getValueType(I.getType());
3073 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3074 unsigned DestAS = I.getType()->getPointerAddressSpace();
3076 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3077 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3082 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3084 SDValue InVec = getValue(I.getOperand(0));
3085 SDValue InVal = getValue(I.getOperand(1));
3086 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3087 getCurSDLoc(), TLI.getVectorIdxTy());
3088 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3089 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3092 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3094 SDValue InVec = getValue(I.getOperand(0));
3095 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3096 getCurSDLoc(), TLI.getVectorIdxTy());
3097 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3098 TLI.getValueType(I.getType()), InVec, InIdx));
3101 // Utility for visitShuffleVector - Return true if every element in Mask,
3102 // beginning from position Pos and ending in Pos+Size, falls within the
3103 // specified sequential range [L, L+Pos). or is undef.
3104 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3105 unsigned Pos, unsigned Size, int Low) {
3106 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3107 if (Mask[i] >= 0 && Mask[i] != Low)
3112 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3113 SDValue Src1 = getValue(I.getOperand(0));
3114 SDValue Src2 = getValue(I.getOperand(1));
3116 SmallVector<int, 8> Mask;
3117 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3118 unsigned MaskNumElts = Mask.size();
3120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3121 EVT VT = TLI.getValueType(I.getType());
3122 EVT SrcVT = Src1.getValueType();
3123 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3125 if (SrcNumElts == MaskNumElts) {
3126 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3131 // Normalize the shuffle vector since mask and vector length don't match.
3132 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3133 // Mask is longer than the source vectors and is a multiple of the source
3134 // vectors. We can use concatenate vector to make the mask and vectors
3136 if (SrcNumElts*2 == MaskNumElts) {
3137 // First check for Src1 in low and Src2 in high
3138 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3139 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3140 // The shuffle is concatenating two vectors together.
3141 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3145 // Then check for Src2 in low and Src1 in high
3146 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3147 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3148 // The shuffle is concatenating two vectors together.
3149 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3155 // Pad both vectors with undefs to make them the same length as the mask.
3156 unsigned NumConcat = MaskNumElts / SrcNumElts;
3157 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3158 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3159 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3161 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3162 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3166 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3167 getCurSDLoc(), VT, MOps1);
3168 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3169 getCurSDLoc(), VT, MOps2);
3171 // Readjust mask for new input vector length.
3172 SmallVector<int, 8> MappedOps;
3173 for (unsigned i = 0; i != MaskNumElts; ++i) {
3175 if (Idx >= (int)SrcNumElts)
3176 Idx -= SrcNumElts - MaskNumElts;
3177 MappedOps.push_back(Idx);
3180 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3185 if (SrcNumElts > MaskNumElts) {
3186 // Analyze the access pattern of the vector to see if we can extract
3187 // two subvectors and do the shuffle. The analysis is done by calculating
3188 // the range of elements the mask access on both vectors.
3189 int MinRange[2] = { static_cast<int>(SrcNumElts),
3190 static_cast<int>(SrcNumElts)};
3191 int MaxRange[2] = {-1, -1};
3193 for (unsigned i = 0; i != MaskNumElts; ++i) {
3199 if (Idx >= (int)SrcNumElts) {
3203 if (Idx > MaxRange[Input])
3204 MaxRange[Input] = Idx;
3205 if (Idx < MinRange[Input])
3206 MinRange[Input] = Idx;
3209 // Check if the access is smaller than the vector size and can we find
3210 // a reasonable extract index.
3211 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3213 int StartIdx[2]; // StartIdx to extract from
3214 for (unsigned Input = 0; Input < 2; ++Input) {
3215 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3216 RangeUse[Input] = 0; // Unused
3217 StartIdx[Input] = 0;
3221 // Find a good start index that is a multiple of the mask length. Then
3222 // see if the rest of the elements are in range.
3223 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3224 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3225 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3226 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3229 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3230 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3233 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3234 // Extract appropriate subvector and generate a vector shuffle
3235 for (unsigned Input = 0; Input < 2; ++Input) {
3236 SDValue &Src = Input == 0 ? Src1 : Src2;
3237 if (RangeUse[Input] == 0)
3238 Src = DAG.getUNDEF(VT);
3241 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3242 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3245 // Calculate new mask.
3246 SmallVector<int, 8> MappedOps;
3247 for (unsigned i = 0; i != MaskNumElts; ++i) {
3250 if (Idx < (int)SrcNumElts)
3253 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3255 MappedOps.push_back(Idx);
3258 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3264 // We can't use either concat vectors or extract subvectors so fall back to
3265 // replacing the shuffle with extract and build vector.
3266 // to insert and build vector.
3267 EVT EltVT = VT.getVectorElementType();
3268 EVT IdxVT = TLI.getVectorIdxTy();
3269 SmallVector<SDValue,8> Ops;
3270 for (unsigned i = 0; i != MaskNumElts; ++i) {
3275 Res = DAG.getUNDEF(EltVT);
3277 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3278 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3280 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3281 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3287 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3290 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3291 const Value *Op0 = I.getOperand(0);
3292 const Value *Op1 = I.getOperand(1);
3293 Type *AggTy = I.getType();
3294 Type *ValTy = Op1->getType();
3295 bool IntoUndef = isa<UndefValue>(Op0);
3296 bool FromUndef = isa<UndefValue>(Op1);
3298 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3300 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3301 SmallVector<EVT, 4> AggValueVTs;
3302 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3303 SmallVector<EVT, 4> ValValueVTs;
3304 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3306 unsigned NumAggValues = AggValueVTs.size();
3307 unsigned NumValValues = ValValueVTs.size();
3308 SmallVector<SDValue, 4> Values(NumAggValues);
3310 // Ignore an insertvalue that produces an empty object
3311 if (!NumAggValues) {
3312 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3316 SDValue Agg = getValue(Op0);
3318 // Copy the beginning value(s) from the original aggregate.
3319 for (; i != LinearIndex; ++i)
3320 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3321 SDValue(Agg.getNode(), Agg.getResNo() + i);
3322 // Copy values from the inserted value(s).
3324 SDValue Val = getValue(Op1);
3325 for (; i != LinearIndex + NumValValues; ++i)
3326 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3327 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3329 // Copy remaining value(s) from the original aggregate.
3330 for (; i != NumAggValues; ++i)
3331 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3332 SDValue(Agg.getNode(), Agg.getResNo() + i);
3334 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3335 DAG.getVTList(AggValueVTs), Values));
3338 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3339 const Value *Op0 = I.getOperand(0);
3340 Type *AggTy = Op0->getType();
3341 Type *ValTy = I.getType();
3342 bool OutOfUndef = isa<UndefValue>(Op0);
3344 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3347 SmallVector<EVT, 4> ValValueVTs;
3348 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3350 unsigned NumValValues = ValValueVTs.size();
3352 // Ignore a extractvalue that produces an empty object
3353 if (!NumValValues) {
3354 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3358 SmallVector<SDValue, 4> Values(NumValValues);
3360 SDValue Agg = getValue(Op0);
3361 // Copy out the selected value(s).
3362 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3363 Values[i - LinearIndex] =
3365 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3366 SDValue(Agg.getNode(), Agg.getResNo() + i);
3368 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3369 DAG.getVTList(ValValueVTs), Values));
3372 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3373 Value *Op0 = I.getOperand(0);
3374 // Note that the pointer operand may be a vector of pointers. Take the scalar
3375 // element which holds a pointer.
3376 Type *Ty = Op0->getType()->getScalarType();
3377 unsigned AS = Ty->getPointerAddressSpace();
3378 SDValue N = getValue(Op0);
3380 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3382 const Value *Idx = *OI;
3383 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3384 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3387 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3388 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3389 DAG.getConstant(Offset, N.getValueType()));
3392 Ty = StTy->getElementType(Field);
3394 Ty = cast<SequentialType>(Ty)->getElementType();
3396 // If this is a constant subscript, handle it quickly.
3397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3398 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3399 if (CI->isZero()) continue;
3401 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3403 EVT PTy = TLI.getPointerTy(AS);
3404 unsigned PtrBits = PTy.getSizeInBits();
3406 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3407 DAG.getConstant(Offs, MVT::i64));
3409 OffsVal = DAG.getConstant(Offs, PTy);
3411 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3416 // N = N + Idx * ElementSize;
3418 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3419 SDValue IdxN = getValue(Idx);
3421 // If the index is smaller or larger than intptr_t, truncate or extend
3423 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3425 // If this is a multiply by a power of two, turn it into a shl
3426 // immediately. This is a very common case.
3427 if (ElementSize != 1) {
3428 if (ElementSize.isPowerOf2()) {
3429 unsigned Amt = ElementSize.logBase2();
3430 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3431 N.getValueType(), IdxN,
3432 DAG.getConstant(Amt, IdxN.getValueType()));
3434 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3435 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3436 N.getValueType(), IdxN, Scale);
3440 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3441 N.getValueType(), N, IdxN);
3448 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3449 // If this is a fixed sized alloca in the entry block of the function,
3450 // allocate it statically on the stack.
3451 if (FuncInfo.StaticAllocaMap.count(&I))
3452 return; // getValue will auto-populate this.
3454 Type *Ty = I.getAllocatedType();
3455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3456 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3458 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3461 SDValue AllocSize = getValue(I.getArraySize());
3463 EVT IntPtr = TLI.getPointerTy();
3464 if (AllocSize.getValueType() != IntPtr)
3465 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3467 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3469 DAG.getConstant(TySize, IntPtr));
3471 // Handle alignment. If the requested alignment is less than or equal to
3472 // the stack alignment, ignore it. If the size is greater than or equal to
3473 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3474 unsigned StackAlign =
3475 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3476 if (Align <= StackAlign)
3479 // Round the size of the allocation up to the stack alignment size
3480 // by add SA-1 to the size.
3481 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3482 AllocSize.getValueType(), AllocSize,
3483 DAG.getIntPtrConstant(StackAlign-1));
3485 // Mask out the low bits for alignment purposes.
3486 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3487 AllocSize.getValueType(), AllocSize,
3488 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3490 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3491 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3492 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3494 DAG.setRoot(DSA.getValue(1));
3496 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3499 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3501 return visitAtomicLoad(I);
3503 const Value *SV = I.getOperand(0);
3504 SDValue Ptr = getValue(SV);
3506 Type *Ty = I.getType();
3508 bool isVolatile = I.isVolatile();
3509 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3510 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3511 unsigned Alignment = I.getAlignment();
3514 I.getAAMetadata(AAInfo);
3515 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3517 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3518 SmallVector<EVT, 4> ValueVTs;
3519 SmallVector<uint64_t, 4> Offsets;
3520 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3521 unsigned NumValues = ValueVTs.size();
3526 bool ConstantMemory = false;
3527 if (isVolatile || NumValues > MaxParallelChains)
3528 // Serialize volatile loads with other side effects.
3530 else if (AA->pointsToConstantMemory(
3531 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3532 // Do not serialize (non-volatile) loads of constant memory with anything.
3533 Root = DAG.getEntryNode();
3534 ConstantMemory = true;
3536 // Do not serialize non-volatile loads against each other.
3537 Root = DAG.getRoot();
3541 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3543 SmallVector<SDValue, 4> Values(NumValues);
3544 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3546 EVT PtrVT = Ptr.getValueType();
3547 unsigned ChainI = 0;
3548 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3549 // Serializing loads here may result in excessive register pressure, and
3550 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3551 // could recover a bit by hoisting nodes upward in the chain by recognizing
3552 // they are side-effect free or do not alias. The optimizer should really
3553 // avoid this case by converting large object/array copies to llvm.memcpy
3554 // (MaxParallelChains should always remain as failsafe).
3555 if (ChainI == MaxParallelChains) {
3556 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3557 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3558 makeArrayRef(Chains.data(), ChainI));
3562 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3564 DAG.getConstant(Offsets[i], PtrVT));
3565 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3566 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3567 isNonTemporal, isInvariant, Alignment, AAInfo,
3571 Chains[ChainI] = L.getValue(1);
3574 if (!ConstantMemory) {
3575 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3576 makeArrayRef(Chains.data(), ChainI));
3580 PendingLoads.push_back(Chain);
3583 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3584 DAG.getVTList(ValueVTs), Values));
3587 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3589 return visitAtomicStore(I);
3591 const Value *SrcV = I.getOperand(0);
3592 const Value *PtrV = I.getOperand(1);
3594 SmallVector<EVT, 4> ValueVTs;
3595 SmallVector<uint64_t, 4> Offsets;
3596 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3597 ValueVTs, &Offsets);
3598 unsigned NumValues = ValueVTs.size();
3602 // Get the lowered operands. Note that we do this after
3603 // checking if NumResults is zero, because with zero results
3604 // the operands won't have values in the map.
3605 SDValue Src = getValue(SrcV);
3606 SDValue Ptr = getValue(PtrV);
3608 SDValue Root = getRoot();
3609 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3611 EVT PtrVT = Ptr.getValueType();
3612 bool isVolatile = I.isVolatile();
3613 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3614 unsigned Alignment = I.getAlignment();
3617 I.getAAMetadata(AAInfo);
3619 unsigned ChainI = 0;
3620 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3621 // See visitLoad comments.
3622 if (ChainI == MaxParallelChains) {
3623 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3624 makeArrayRef(Chains.data(), ChainI));
3628 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3629 DAG.getConstant(Offsets[i], PtrVT));
3630 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3631 SDValue(Src.getNode(), Src.getResNo() + i),
3632 Add, MachinePointerInfo(PtrV, Offsets[i]),
3633 isVolatile, isNonTemporal, Alignment, AAInfo);
3634 Chains[ChainI] = St;
3637 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3638 makeArrayRef(Chains.data(), ChainI));
3639 DAG.setRoot(StoreNode);
3642 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3643 SDLoc dl = getCurSDLoc();
3644 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3645 AtomicOrdering FailureOrder = I.getFailureOrdering();
3646 SynchronizationScope Scope = I.getSynchScope();
3648 SDValue InChain = getRoot();
3650 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3651 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3652 SDValue L = DAG.getAtomicCmpSwap(
3653 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3654 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3655 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3656 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3658 SDValue OutChain = L.getValue(2);
3661 DAG.setRoot(OutChain);
3664 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3665 SDLoc dl = getCurSDLoc();
3667 switch (I.getOperation()) {
3668 default: llvm_unreachable("Unknown atomicrmw operation");
3669 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3670 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3671 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3672 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3673 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3674 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3675 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3676 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3677 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3678 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3679 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3681 AtomicOrdering Order = I.getOrdering();
3682 SynchronizationScope Scope = I.getSynchScope();
3684 SDValue InChain = getRoot();
3687 DAG.getAtomic(NT, dl,
3688 getValue(I.getValOperand()).getSimpleValueType(),
3690 getValue(I.getPointerOperand()),
3691 getValue(I.getValOperand()),
3692 I.getPointerOperand(),
3693 /* Alignment=*/ 0, Order, Scope);
3695 SDValue OutChain = L.getValue(1);
3698 DAG.setRoot(OutChain);
3701 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3702 SDLoc dl = getCurSDLoc();
3703 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3706 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3707 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3708 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3711 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3712 SDLoc dl = getCurSDLoc();
3713 AtomicOrdering Order = I.getOrdering();
3714 SynchronizationScope Scope = I.getSynchScope();
3716 SDValue InChain = getRoot();
3718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3719 EVT VT = TLI.getValueType(I.getType());
3721 if (I.getAlignment() < VT.getSizeInBits() / 8)
3722 report_fatal_error("Cannot generate unaligned atomic load");
3724 MachineMemOperand *MMO =
3725 DAG.getMachineFunction().
3726 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3727 MachineMemOperand::MOVolatile |
3728 MachineMemOperand::MOLoad,
3730 I.getAlignment() ? I.getAlignment() :
3731 DAG.getEVTAlignment(VT));
3733 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3735 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3736 getValue(I.getPointerOperand()), MMO,
3739 SDValue OutChain = L.getValue(1);
3742 DAG.setRoot(OutChain);
3745 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3746 SDLoc dl = getCurSDLoc();
3748 AtomicOrdering Order = I.getOrdering();
3749 SynchronizationScope Scope = I.getSynchScope();
3751 SDValue InChain = getRoot();
3753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3754 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3756 if (I.getAlignment() < VT.getSizeInBits() / 8)
3757 report_fatal_error("Cannot generate unaligned atomic store");
3760 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3762 getValue(I.getPointerOperand()),
3763 getValue(I.getValueOperand()),
3764 I.getPointerOperand(), I.getAlignment(),
3767 DAG.setRoot(OutChain);
3770 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3772 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3773 unsigned Intrinsic) {
3774 bool HasChain = !I.doesNotAccessMemory();
3775 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3777 // Build the operand list.
3778 SmallVector<SDValue, 8> Ops;
3779 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3781 // We don't need to serialize loads against other loads.
3782 Ops.push_back(DAG.getRoot());
3784 Ops.push_back(getRoot());
3788 // Info is set by getTgtMemInstrinsic
3789 TargetLowering::IntrinsicInfo Info;
3790 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3791 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3793 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3794 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3795 Info.opc == ISD::INTRINSIC_W_CHAIN)
3796 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3798 // Add all operands of the call to the operand list.
3799 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3800 SDValue Op = getValue(I.getArgOperand(i));
3804 SmallVector<EVT, 4> ValueVTs;
3805 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3808 ValueVTs.push_back(MVT::Other);
3810 SDVTList VTs = DAG.getVTList(ValueVTs);
3814 if (IsTgtIntrinsic) {
3815 // This is target intrinsic that touches memory
3816 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3817 VTs, Ops, Info.memVT,
3818 MachinePointerInfo(Info.ptrVal, Info.offset),
3819 Info.align, Info.vol,
3820 Info.readMem, Info.writeMem, Info.size);
3821 } else if (!HasChain) {
3822 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3823 } else if (!I.getType()->isVoidTy()) {
3824 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3826 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3830 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3832 PendingLoads.push_back(Chain);
3837 if (!I.getType()->isVoidTy()) {
3838 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3839 EVT VT = TLI.getValueType(PTy);
3840 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3843 setValue(&I, Result);
3847 /// GetSignificand - Get the significand and build it into a floating-point
3848 /// number with exponent of 1:
3850 /// Op = (Op & 0x007fffff) | 0x3f800000;
3852 /// where Op is the hexadecimal representation of floating point value.
3854 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3855 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3856 DAG.getConstant(0x007fffff, MVT::i32));
3857 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3858 DAG.getConstant(0x3f800000, MVT::i32));
3859 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3862 /// GetExponent - Get the exponent:
3864 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3866 /// where Op is the hexadecimal representation of floating point value.
3868 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3870 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3871 DAG.getConstant(0x7f800000, MVT::i32));
3872 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3873 DAG.getConstant(23, TLI.getPointerTy()));
3874 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3875 DAG.getConstant(127, MVT::i32));
3876 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3879 /// getF32Constant - Get 32-bit floating point constant.
3881 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3882 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3886 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3887 /// limited-precision mode.
3888 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3889 const TargetLowering &TLI) {
3890 if (Op.getValueType() == MVT::f32 &&
3891 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3893 // Put the exponent in the right bit position for later addition to the
3896 // #define LOG2OFe 1.4426950f
3897 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3898 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3899 getF32Constant(DAG, 0x3fb8aa3b));
3900 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3902 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3903 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3904 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3906 // IntegerPartOfX <<= 23;
3907 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3908 DAG.getConstant(23, TLI.getPointerTy()));
3910 SDValue TwoToFracPartOfX;
3911 if (LimitFloatPrecision <= 6) {
3912 // For floating-point precision of 6:
3914 // TwoToFractionalPartOfX =
3916 // (0.735607626f + 0.252464424f * x) * x;
3918 // error 0.0144103317, which is 6 bits
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3920 getF32Constant(DAG, 0x3e814304));
3921 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3922 getF32Constant(DAG, 0x3f3c50c8));
3923 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3924 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3925 getF32Constant(DAG, 0x3f7f5e7e));
3926 } else if (LimitFloatPrecision <= 12) {
3927 // For floating-point precision of 12:
3929 // TwoToFractionalPartOfX =
3932 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3934 // 0.000107046256 error, which is 13 to 14 bits
3935 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3936 getF32Constant(DAG, 0x3da235e3));
3937 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x3e65b8f3));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x3f324b07));
3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3943 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3944 getF32Constant(DAG, 0x3f7ff8fd));
3945 } else { // LimitFloatPrecision <= 18
3946 // For floating-point precision of 18:
3948 // TwoToFractionalPartOfX =
3952 // (0.554906021e-1f +
3953 // (0.961591928e-2f +
3954 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3956 // error 2.47208000*10^(-7), which is better than 18 bits
3957 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3958 getF32Constant(DAG, 0x3924b03e));
3959 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3960 getF32Constant(DAG, 0x3ab24b87));
3961 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3962 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3963 getF32Constant(DAG, 0x3c1d8c17));
3964 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3965 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3966 getF32Constant(DAG, 0x3d634a1d));
3967 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3968 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3969 getF32Constant(DAG, 0x3e75fe14));
3970 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3971 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3972 getF32Constant(DAG, 0x3f317234));
3973 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3974 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3975 getF32Constant(DAG, 0x3f800000));
3978 // Add the exponent into the result in integer domain.
3979 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3980 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3981 DAG.getNode(ISD::ADD, dl, MVT::i32,
3982 t13, IntegerPartOfX));
3985 // No special expansion.
3986 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3989 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3990 /// limited-precision mode.
3991 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3992 const TargetLowering &TLI) {
3993 if (Op.getValueType() == MVT::f32 &&
3994 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3995 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3997 // Scale the exponent by log(2) [0.69314718f].
3998 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3999 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4000 getF32Constant(DAG, 0x3f317218));
4002 // Get the significand and build it into a floating-point number with
4004 SDValue X = GetSignificand(DAG, Op1, dl);
4006 SDValue LogOfMantissa;
4007 if (LimitFloatPrecision <= 6) {
4008 // For floating-point precision of 6:
4012 // (1.4034025f - 0.23903021f * x) * x;
4014 // error 0.0034276066, which is better than 8 bits
4015 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4016 getF32Constant(DAG, 0xbe74c456));
4017 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4018 getF32Constant(DAG, 0x3fb3a2b1));
4019 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4020 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4021 getF32Constant(DAG, 0x3f949a29));
4022 } else if (LimitFloatPrecision <= 12) {
4023 // For floating-point precision of 12:
4029 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4031 // error 0.000061011436, which is 14 bits
4032 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4033 getF32Constant(DAG, 0xbd67b6d6));
4034 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4035 getF32Constant(DAG, 0x3ee4f4b8));
4036 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4037 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4038 getF32Constant(DAG, 0x3fbc278b));
4039 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4040 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4041 getF32Constant(DAG, 0x40348e95));
4042 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4043 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4044 getF32Constant(DAG, 0x3fdef31a));
4045 } else { // LimitFloatPrecision <= 18
4046 // For floating-point precision of 18:
4054 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4056 // error 0.0000023660568, which is better than 18 bits
4057 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4058 getF32Constant(DAG, 0xbc91e5ac));
4059 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4060 getF32Constant(DAG, 0x3e4350aa));
4061 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4062 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4063 getF32Constant(DAG, 0x3f60d3e3));
4064 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4065 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4066 getF32Constant(DAG, 0x4011cdf0));
4067 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4068 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4069 getF32Constant(DAG, 0x406cfd1c));
4070 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4071 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4072 getF32Constant(DAG, 0x408797cb));
4073 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4074 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4075 getF32Constant(DAG, 0x4006dcab));
4078 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4081 // No special expansion.
4082 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4085 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4086 /// limited-precision mode.
4087 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4088 const TargetLowering &TLI) {
4089 if (Op.getValueType() == MVT::f32 &&
4090 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4091 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4093 // Get the exponent.
4094 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4096 // Get the significand and build it into a floating-point number with
4098 SDValue X = GetSignificand(DAG, Op1, dl);
4100 // Different possible minimax approximations of significand in
4101 // floating-point for various degrees of accuracy over [1,2].
4102 SDValue Log2ofMantissa;
4103 if (LimitFloatPrecision <= 6) {
4104 // For floating-point precision of 6:
4106 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4108 // error 0.0049451742, which is more than 7 bits
4109 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4110 getF32Constant(DAG, 0xbeb08fe0));
4111 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4112 getF32Constant(DAG, 0x40019463));
4113 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4114 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4115 getF32Constant(DAG, 0x3fd6633d));
4116 } else if (LimitFloatPrecision <= 12) {
4117 // For floating-point precision of 12:
4123 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4125 // error 0.0000876136000, which is better than 13 bits
4126 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4127 getF32Constant(DAG, 0xbda7262e));
4128 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4129 getF32Constant(DAG, 0x3f25280b));
4130 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4131 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4132 getF32Constant(DAG, 0x4007b923));
4133 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4134 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4135 getF32Constant(DAG, 0x40823e2f));
4136 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4137 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4138 getF32Constant(DAG, 0x4020d29c));
4139 } else { // LimitFloatPrecision <= 18
4140 // For floating-point precision of 18:
4149 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4151 // error 0.0000018516, which is better than 18 bits
4152 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4153 getF32Constant(DAG, 0xbcd2769e));
4154 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4155 getF32Constant(DAG, 0x3e8ce0b9));
4156 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4157 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4158 getF32Constant(DAG, 0x3fa22ae7));
4159 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4160 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4161 getF32Constant(DAG, 0x40525723));
4162 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4163 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4164 getF32Constant(DAG, 0x40aaf200));
4165 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4166 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4167 getF32Constant(DAG, 0x40c39dad));
4168 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4169 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4170 getF32Constant(DAG, 0x4042902c));
4173 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4176 // No special expansion.
4177 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4180 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4181 /// limited-precision mode.
4182 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4183 const TargetLowering &TLI) {
4184 if (Op.getValueType() == MVT::f32 &&
4185 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4186 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4188 // Scale the exponent by log10(2) [0.30102999f].
4189 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4190 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4191 getF32Constant(DAG, 0x3e9a209a));
4193 // Get the significand and build it into a floating-point number with
4195 SDValue X = GetSignificand(DAG, Op1, dl);
4197 SDValue Log10ofMantissa;
4198 if (LimitFloatPrecision <= 6) {
4199 // For floating-point precision of 6:
4201 // Log10ofMantissa =
4203 // (0.60948995f - 0.10380950f * x) * x;
4205 // error 0.0014886165, which is 6 bits
4206 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4207 getF32Constant(DAG, 0xbdd49a13));
4208 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4209 getF32Constant(DAG, 0x3f1c0789));
4210 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4211 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4212 getF32Constant(DAG, 0x3f011300));
4213 } else if (LimitFloatPrecision <= 12) {
4214 // For floating-point precision of 12:
4216 // Log10ofMantissa =
4219 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4221 // error 0.00019228036, which is better than 12 bits
4222 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4223 getF32Constant(DAG, 0x3d431f31));
4224 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4225 getF32Constant(DAG, 0x3ea21fb2));
4226 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4227 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4228 getF32Constant(DAG, 0x3f6ae232));
4229 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4230 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4231 getF32Constant(DAG, 0x3f25f7c3));
4232 } else { // LimitFloatPrecision <= 18
4233 // For floating-point precision of 18:
4235 // Log10ofMantissa =
4240 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4242 // error 0.0000037995730, which is better than 18 bits
4243 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4244 getF32Constant(DAG, 0x3c5d51ce));
4245 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4246 getF32Constant(DAG, 0x3e00685a));
4247 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4248 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4249 getF32Constant(DAG, 0x3efb6798));
4250 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4251 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4252 getF32Constant(DAG, 0x3f88d192));
4253 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4254 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4255 getF32Constant(DAG, 0x3fc4316c));
4256 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4257 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4258 getF32Constant(DAG, 0x3f57ce70));
4261 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4264 // No special expansion.
4265 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4268 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4269 /// limited-precision mode.
4270 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4271 const TargetLowering &TLI) {
4272 if (Op.getValueType() == MVT::f32 &&
4273 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4274 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4276 // FractionalPartOfX = x - (float)IntegerPartOfX;
4277 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4278 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4280 // IntegerPartOfX <<= 23;
4281 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4282 DAG.getConstant(23, TLI.getPointerTy()));
4284 SDValue TwoToFractionalPartOfX;
4285 if (LimitFloatPrecision <= 6) {
4286 // For floating-point precision of 6:
4288 // TwoToFractionalPartOfX =
4290 // (0.735607626f + 0.252464424f * x) * x;
4292 // error 0.0144103317, which is 6 bits
4293 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4294 getF32Constant(DAG, 0x3e814304));
4295 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4296 getF32Constant(DAG, 0x3f3c50c8));
4297 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4298 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4299 getF32Constant(DAG, 0x3f7f5e7e));
4300 } else if (LimitFloatPrecision <= 12) {
4301 // For floating-point precision of 12:
4303 // TwoToFractionalPartOfX =
4306 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4308 // error 0.000107046256, which is 13 to 14 bits
4309 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4310 getF32Constant(DAG, 0x3da235e3));
4311 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4312 getF32Constant(DAG, 0x3e65b8f3));
4313 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4314 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4315 getF32Constant(DAG, 0x3f324b07));
4316 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4317 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4318 getF32Constant(DAG, 0x3f7ff8fd));
4319 } else { // LimitFloatPrecision <= 18
4320 // For floating-point precision of 18:
4322 // TwoToFractionalPartOfX =
4326 // (0.554906021e-1f +
4327 // (0.961591928e-2f +
4328 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4329 // error 2.47208000*10^(-7), which is better than 18 bits
4330 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4331 getF32Constant(DAG, 0x3924b03e));
4332 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4333 getF32Constant(DAG, 0x3ab24b87));
4334 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4335 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4336 getF32Constant(DAG, 0x3c1d8c17));
4337 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4338 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4339 getF32Constant(DAG, 0x3d634a1d));
4340 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4341 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4342 getF32Constant(DAG, 0x3e75fe14));
4343 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4344 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4345 getF32Constant(DAG, 0x3f317234));
4346 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4347 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4348 getF32Constant(DAG, 0x3f800000));
4351 // Add the exponent into the result in integer domain.
4352 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4353 TwoToFractionalPartOfX);
4354 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4355 DAG.getNode(ISD::ADD, dl, MVT::i32,
4356 t13, IntegerPartOfX));
4359 // No special expansion.
4360 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4363 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4364 /// limited-precision mode with x == 10.0f.
4365 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4366 SelectionDAG &DAG, const TargetLowering &TLI) {
4367 bool IsExp10 = false;
4368 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4369 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4370 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4372 IsExp10 = LHSC->isExactlyValue(Ten);
4377 // Put the exponent in the right bit position for later addition to the
4380 // #define LOG2OF10 3.3219281f
4381 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4382 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4383 getF32Constant(DAG, 0x40549a78));
4384 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4386 // FractionalPartOfX = x - (float)IntegerPartOfX;
4387 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4388 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4390 // IntegerPartOfX <<= 23;
4391 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4392 DAG.getConstant(23, TLI.getPointerTy()));
4394 SDValue TwoToFractionalPartOfX;
4395 if (LimitFloatPrecision <= 6) {
4396 // For floating-point precision of 6:
4398 // twoToFractionalPartOfX =
4400 // (0.735607626f + 0.252464424f * x) * x;
4402 // error 0.0144103317, which is 6 bits
4403 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4404 getF32Constant(DAG, 0x3e814304));
4405 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4406 getF32Constant(DAG, 0x3f3c50c8));
4407 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4408 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4409 getF32Constant(DAG, 0x3f7f5e7e));
4410 } else if (LimitFloatPrecision <= 12) {
4411 // For floating-point precision of 12:
4413 // TwoToFractionalPartOfX =
4416 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4418 // error 0.000107046256, which is 13 to 14 bits
4419 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4420 getF32Constant(DAG, 0x3da235e3));
4421 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4422 getF32Constant(DAG, 0x3e65b8f3));
4423 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4424 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4425 getF32Constant(DAG, 0x3f324b07));
4426 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4427 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4428 getF32Constant(DAG, 0x3f7ff8fd));
4429 } else { // LimitFloatPrecision <= 18
4430 // For floating-point precision of 18:
4432 // TwoToFractionalPartOfX =
4436 // (0.554906021e-1f +
4437 // (0.961591928e-2f +
4438 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4439 // error 2.47208000*10^(-7), which is better than 18 bits
4440 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4441 getF32Constant(DAG, 0x3924b03e));
4442 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4443 getF32Constant(DAG, 0x3ab24b87));
4444 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4445 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4446 getF32Constant(DAG, 0x3c1d8c17));
4447 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4448 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4449 getF32Constant(DAG, 0x3d634a1d));
4450 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4451 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4452 getF32Constant(DAG, 0x3e75fe14));
4453 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4454 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4455 getF32Constant(DAG, 0x3f317234));
4456 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4457 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4458 getF32Constant(DAG, 0x3f800000));
4461 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4462 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4463 DAG.getNode(ISD::ADD, dl, MVT::i32,
4464 t13, IntegerPartOfX));
4467 // No special expansion.
4468 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4472 /// ExpandPowI - Expand a llvm.powi intrinsic.
4473 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4474 SelectionDAG &DAG) {
4475 // If RHS is a constant, we can expand this out to a multiplication tree,
4476 // otherwise we end up lowering to a call to __powidf2 (for example). When
4477 // optimizing for size, we only want to do this if the expansion would produce
4478 // a small number of multiplies, otherwise we do the full expansion.
4479 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4480 // Get the exponent as a positive value.
4481 unsigned Val = RHSC->getSExtValue();
4482 if ((int)Val < 0) Val = -Val;
4484 // powi(x, 0) -> 1.0
4486 return DAG.getConstantFP(1.0, LHS.getValueType());
4488 const Function *F = DAG.getMachineFunction().getFunction();
4489 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4490 Attribute::OptimizeForSize) ||
4491 // If optimizing for size, don't insert too many multiplies. This
4492 // inserts up to 5 multiplies.
4493 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4494 // We use the simple binary decomposition method to generate the multiply
4495 // sequence. There are more optimal ways to do this (for example,
4496 // powi(x,15) generates one more multiply than it should), but this has
4497 // the benefit of being both really simple and much better than a libcall.
4498 SDValue Res; // Logically starts equal to 1.0
4499 SDValue CurSquare = LHS;
4503 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4505 Res = CurSquare; // 1.0*CurSquare.
4508 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4509 CurSquare, CurSquare);
4513 // If the original was negative, invert the result, producing 1/(x*x*x).
4514 if (RHSC->getSExtValue() < 0)
4515 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4516 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4521 // Otherwise, expand to a libcall.
4522 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4525 // getTruncatedArgReg - Find underlying register used for an truncated
4527 static unsigned getTruncatedArgReg(const SDValue &N) {
4528 if (N.getOpcode() != ISD::TRUNCATE)
4531 const SDValue &Ext = N.getOperand(0);
4532 if (Ext.getOpcode() == ISD::AssertZext ||
4533 Ext.getOpcode() == ISD::AssertSext) {
4534 const SDValue &CFR = Ext.getOperand(0);
4535 if (CFR.getOpcode() == ISD::CopyFromReg)
4536 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4537 if (CFR.getOpcode() == ISD::TRUNCATE)
4538 return getTruncatedArgReg(CFR);
4543 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4544 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4545 /// At the end of instruction selection, they will be inserted to the entry BB.
4546 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4548 MDNode *Expr, int64_t Offset,
4551 const Argument *Arg = dyn_cast<Argument>(V);
4555 MachineFunction &MF = DAG.getMachineFunction();
4556 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4558 // Ignore inlined function arguments here.
4559 DIVariable DV(Variable);
4560 if (DV.isInlinedFnArgument(MF.getFunction()))
4563 Optional<MachineOperand> Op;
4564 // Some arguments' frame index is recorded during argument lowering.
4565 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4566 Op = MachineOperand::CreateFI(FI);
4568 if (!Op && N.getNode()) {
4570 if (N.getOpcode() == ISD::CopyFromReg)
4571 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4573 Reg = getTruncatedArgReg(N);
4574 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4575 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4576 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4581 Op = MachineOperand::CreateReg(Reg, false);
4585 // Check if ValueMap has reg number.
4586 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4587 if (VMI != FuncInfo.ValueMap.end())
4588 Op = MachineOperand::CreateReg(VMI->second, false);
4591 if (!Op && N.getNode())
4592 // Check if frame index is available.
4593 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4594 if (FrameIndexSDNode *FINode =
4595 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4596 Op = MachineOperand::CreateFI(FINode->getIndex());
4602 FuncInfo.ArgDbgValues.push_back(
4603 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4604 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4606 FuncInfo.ArgDbgValues.push_back(
4607 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4610 .addMetadata(Variable)
4611 .addMetadata(Expr));
4616 // VisualStudio defines setjmp as _setjmp
4617 #if defined(_MSC_VER) && defined(setjmp) && \
4618 !defined(setjmp_undefined_for_msvc)
4619 # pragma push_macro("setjmp")
4621 # define setjmp_undefined_for_msvc
4624 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4625 /// we want to emit this as a call to a named external function, return the name
4626 /// otherwise lower it and return null.
4628 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4630 SDLoc sdl = getCurSDLoc();
4631 DebugLoc dl = getCurDebugLoc();
4634 switch (Intrinsic) {
4636 // By default, turn this into a target intrinsic node.
4637 visitTargetIntrinsic(I, Intrinsic);
4639 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4640 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4641 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4642 case Intrinsic::returnaddress:
4643 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4644 getValue(I.getArgOperand(0))));
4646 case Intrinsic::frameaddress:
4647 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4648 getValue(I.getArgOperand(0))));
4650 case Intrinsic::read_register: {
4651 Value *Reg = I.getArgOperand(0);
4652 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4653 EVT VT = TLI.getValueType(I.getType());
4654 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4657 case Intrinsic::write_register: {
4658 Value *Reg = I.getArgOperand(0);
4659 Value *RegValue = I.getArgOperand(1);
4660 SDValue Chain = getValue(RegValue).getOperand(0);
4661 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4662 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4663 RegName, getValue(RegValue)));
4666 case Intrinsic::setjmp:
4667 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4668 case Intrinsic::longjmp:
4669 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4670 case Intrinsic::memcpy: {
4671 // Assert for address < 256 since we support only user defined address
4673 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4675 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4677 "Unknown address space");
4678 SDValue Op1 = getValue(I.getArgOperand(0));
4679 SDValue Op2 = getValue(I.getArgOperand(1));
4680 SDValue Op3 = getValue(I.getArgOperand(2));
4681 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4683 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4684 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4685 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4686 MachinePointerInfo(I.getArgOperand(0)),
4687 MachinePointerInfo(I.getArgOperand(1))));
4690 case Intrinsic::memset: {
4691 // Assert for address < 256 since we support only user defined address
4693 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4695 "Unknown address space");
4696 SDValue Op1 = getValue(I.getArgOperand(0));
4697 SDValue Op2 = getValue(I.getArgOperand(1));
4698 SDValue Op3 = getValue(I.getArgOperand(2));
4699 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4701 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4702 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4703 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4704 MachinePointerInfo(I.getArgOperand(0))));
4707 case Intrinsic::memmove: {
4708 // Assert for address < 256 since we support only user defined address
4710 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4712 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4714 "Unknown address space");
4715 SDValue Op1 = getValue(I.getArgOperand(0));
4716 SDValue Op2 = getValue(I.getArgOperand(1));
4717 SDValue Op3 = getValue(I.getArgOperand(2));
4718 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4720 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4721 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4722 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4723 MachinePointerInfo(I.getArgOperand(0)),
4724 MachinePointerInfo(I.getArgOperand(1))));
4727 case Intrinsic::dbg_declare: {
4728 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4729 MDNode *Variable = DI.getVariable();
4730 MDNode *Expression = DI.getExpression();
4731 const Value *Address = DI.getAddress();
4732 DIVariable DIVar(Variable);
4733 assert((!DIVar || DIVar.isVariable()) &&
4734 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4735 if (!Address || !DIVar) {
4736 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4740 // Check if address has undef value.
4741 if (isa<UndefValue>(Address) ||
4742 (Address->use_empty() && !isa<Argument>(Address))) {
4743 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4747 SDValue &N = NodeMap[Address];
4748 if (!N.getNode() && isa<Argument>(Address))
4749 // Check unused arguments map.
4750 N = UnusedArgNodeMap[Address];
4753 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4754 Address = BCI->getOperand(0);
4755 // Parameters are handled specially.
4757 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4758 isa<Argument>(Address));
4760 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4762 if (isParameter && !AI) {
4763 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4765 // Byval parameter. We have a frame index at this point.
4766 SDV = DAG.getFrameIndexDbgValue(
4767 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4769 // Address is an argument, so try to emit its dbg value using
4770 // virtual register info from the FuncInfo.ValueMap.
4771 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4775 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4776 true, 0, dl, SDNodeOrder);
4778 // Can't do anything with other non-AI cases yet.
4779 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4780 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4781 DEBUG(Address->dump());
4784 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4786 // If Address is an argument then try to emit its dbg value using
4787 // virtual register info from the FuncInfo.ValueMap.
4788 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4790 // If variable is pinned by a alloca in dominating bb then
4791 // use StaticAllocaMap.
4792 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4793 if (AI->getParent() != DI.getParent()) {
4794 DenseMap<const AllocaInst*, int>::iterator SI =
4795 FuncInfo.StaticAllocaMap.find(AI);
4796 if (SI != FuncInfo.StaticAllocaMap.end()) {
4797 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4798 0, dl, SDNodeOrder);
4799 DAG.AddDbgValue(SDV, nullptr, false);
4804 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4809 case Intrinsic::dbg_value: {
4810 const DbgValueInst &DI = cast<DbgValueInst>(I);
4811 DIVariable DIVar(DI.getVariable());
4812 assert((!DIVar || DIVar.isVariable()) &&
4813 "Variable in DbgValueInst should be either null or a DIVariable.");
4817 MDNode *Variable = DI.getVariable();
4818 MDNode *Expression = DI.getExpression();
4819 uint64_t Offset = DI.getOffset();
4820 const Value *V = DI.getValue();
4825 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4826 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4828 DAG.AddDbgValue(SDV, nullptr, false);
4830 // Do not use getValue() in here; we don't want to generate code at
4831 // this point if it hasn't been done yet.
4832 SDValue N = NodeMap[V];
4833 if (!N.getNode() && isa<Argument>(V))
4834 // Check unused arguments map.
4835 N = UnusedArgNodeMap[V];
4837 // A dbg.value for an alloca is always indirect.
4838 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4839 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4841 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4842 IsIndirect, Offset, dl, SDNodeOrder);
4843 DAG.AddDbgValue(SDV, N.getNode(), false);
4845 } else if (!V->use_empty() ) {
4846 // Do not call getValue(V) yet, as we don't want to generate code.
4847 // Remember it for later.
4848 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4849 DanglingDebugInfoMap[V] = DDI;
4851 // We may expand this to cover more cases. One case where we have no
4852 // data available is an unreferenced parameter.
4853 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4857 // Build a debug info table entry.
4858 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4859 V = BCI->getOperand(0);
4860 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4861 // Don't handle byval struct arguments or VLAs, for example.
4863 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4864 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4867 DenseMap<const AllocaInst*, int>::iterator SI =
4868 FuncInfo.StaticAllocaMap.find(AI);
4869 if (SI == FuncInfo.StaticAllocaMap.end())
4870 return nullptr; // VLAs.
4874 case Intrinsic::eh_typeid_for: {
4875 // Find the type id for the given typeinfo.
4876 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4877 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4878 Res = DAG.getConstant(TypeID, MVT::i32);
4883 case Intrinsic::eh_return_i32:
4884 case Intrinsic::eh_return_i64:
4885 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4886 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4889 getValue(I.getArgOperand(0)),
4890 getValue(I.getArgOperand(1))));
4892 case Intrinsic::eh_unwind_init:
4893 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4895 case Intrinsic::eh_dwarf_cfa: {
4896 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4897 TLI.getPointerTy());
4898 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4899 CfaArg.getValueType(),
4900 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4901 CfaArg.getValueType()),
4903 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4904 DAG.getConstant(0, TLI.getPointerTy()));
4905 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4909 case Intrinsic::eh_sjlj_callsite: {
4910 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4911 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4912 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4913 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4915 MMI.setCurrentCallSite(CI->getZExtValue());
4918 case Intrinsic::eh_sjlj_functioncontext: {
4919 // Get and store the index of the function context.
4920 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4922 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4923 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4924 MFI->setFunctionContextIndex(FI);
4927 case Intrinsic::eh_sjlj_setjmp: {
4930 Ops[1] = getValue(I.getArgOperand(0));
4931 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4932 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4933 setValue(&I, Op.getValue(0));
4934 DAG.setRoot(Op.getValue(1));
4937 case Intrinsic::eh_sjlj_longjmp: {
4938 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4939 getRoot(), getValue(I.getArgOperand(0))));
4943 case Intrinsic::x86_mmx_pslli_w:
4944 case Intrinsic::x86_mmx_pslli_d:
4945 case Intrinsic::x86_mmx_pslli_q:
4946 case Intrinsic::x86_mmx_psrli_w:
4947 case Intrinsic::x86_mmx_psrli_d:
4948 case Intrinsic::x86_mmx_psrli_q:
4949 case Intrinsic::x86_mmx_psrai_w:
4950 case Intrinsic::x86_mmx_psrai_d: {
4951 SDValue ShAmt = getValue(I.getArgOperand(1));
4952 if (isa<ConstantSDNode>(ShAmt)) {
4953 visitTargetIntrinsic(I, Intrinsic);
4956 unsigned NewIntrinsic = 0;
4957 EVT ShAmtVT = MVT::v2i32;
4958 switch (Intrinsic) {
4959 case Intrinsic::x86_mmx_pslli_w:
4960 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4962 case Intrinsic::x86_mmx_pslli_d:
4963 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4965 case Intrinsic::x86_mmx_pslli_q:
4966 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4968 case Intrinsic::x86_mmx_psrli_w:
4969 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4971 case Intrinsic::x86_mmx_psrli_d:
4972 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4974 case Intrinsic::x86_mmx_psrli_q:
4975 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4977 case Intrinsic::x86_mmx_psrai_w:
4978 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4980 case Intrinsic::x86_mmx_psrai_d:
4981 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4983 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4986 // The vector shift intrinsics with scalars uses 32b shift amounts but
4987 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4989 // We must do this early because v2i32 is not a legal type.
4992 ShOps[1] = DAG.getConstant(0, MVT::i32);
4993 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4994 EVT DestVT = TLI.getValueType(I.getType());
4995 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4996 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4997 DAG.getConstant(NewIntrinsic, MVT::i32),
4998 getValue(I.getArgOperand(0)), ShAmt);
5002 case Intrinsic::x86_avx_vinsertf128_pd_256:
5003 case Intrinsic::x86_avx_vinsertf128_ps_256:
5004 case Intrinsic::x86_avx_vinsertf128_si_256:
5005 case Intrinsic::x86_avx2_vinserti128: {
5006 EVT DestVT = TLI.getValueType(I.getType());
5007 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5008 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5009 ElVT.getVectorNumElements();
5011 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5012 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5013 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5017 case Intrinsic::x86_avx_vextractf128_pd_256:
5018 case Intrinsic::x86_avx_vextractf128_ps_256:
5019 case Intrinsic::x86_avx_vextractf128_si_256:
5020 case Intrinsic::x86_avx2_vextracti128: {
5021 EVT DestVT = TLI.getValueType(I.getType());
5022 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5023 DestVT.getVectorNumElements();
5024 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5025 getValue(I.getArgOperand(0)),
5026 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5030 case Intrinsic::convertff:
5031 case Intrinsic::convertfsi:
5032 case Intrinsic::convertfui:
5033 case Intrinsic::convertsif:
5034 case Intrinsic::convertuif:
5035 case Intrinsic::convertss:
5036 case Intrinsic::convertsu:
5037 case Intrinsic::convertus:
5038 case Intrinsic::convertuu: {
5039 ISD::CvtCode Code = ISD::CVT_INVALID;
5040 switch (Intrinsic) {
5041 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5042 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5043 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5044 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5045 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5046 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5047 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5048 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5049 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5050 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5052 EVT DestVT = TLI.getValueType(I.getType());
5053 const Value *Op1 = I.getArgOperand(0);
5054 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5055 DAG.getValueType(DestVT),
5056 DAG.getValueType(getValue(Op1).getValueType()),
5057 getValue(I.getArgOperand(1)),
5058 getValue(I.getArgOperand(2)),
5063 case Intrinsic::powi:
5064 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5065 getValue(I.getArgOperand(1)), DAG));
5067 case Intrinsic::log:
5068 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5070 case Intrinsic::log2:
5071 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5073 case Intrinsic::log10:
5074 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5076 case Intrinsic::exp:
5077 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5079 case Intrinsic::exp2:
5080 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5082 case Intrinsic::pow:
5083 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5084 getValue(I.getArgOperand(1)), DAG, TLI));
5086 case Intrinsic::sqrt:
5087 case Intrinsic::fabs:
5088 case Intrinsic::sin:
5089 case Intrinsic::cos:
5090 case Intrinsic::floor:
5091 case Intrinsic::ceil:
5092 case Intrinsic::trunc:
5093 case Intrinsic::rint:
5094 case Intrinsic::nearbyint:
5095 case Intrinsic::round: {
5097 switch (Intrinsic) {
5098 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5099 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5100 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5101 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5102 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5103 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5104 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5105 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5106 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5107 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5108 case Intrinsic::round: Opcode = ISD::FROUND; break;
5111 setValue(&I, DAG.getNode(Opcode, sdl,
5112 getValue(I.getArgOperand(0)).getValueType(),
5113 getValue(I.getArgOperand(0))));
5116 case Intrinsic::minnum:
5117 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5118 getValue(I.getArgOperand(0)).getValueType(),
5119 getValue(I.getArgOperand(0)),
5120 getValue(I.getArgOperand(1))));
5122 case Intrinsic::maxnum:
5123 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5124 getValue(I.getArgOperand(0)).getValueType(),
5125 getValue(I.getArgOperand(0)),
5126 getValue(I.getArgOperand(1))));
5128 case Intrinsic::copysign:
5129 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5130 getValue(I.getArgOperand(0)).getValueType(),
5131 getValue(I.getArgOperand(0)),
5132 getValue(I.getArgOperand(1))));
5134 case Intrinsic::fma:
5135 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5136 getValue(I.getArgOperand(0)).getValueType(),
5137 getValue(I.getArgOperand(0)),
5138 getValue(I.getArgOperand(1)),
5139 getValue(I.getArgOperand(2))));
5141 case Intrinsic::fmuladd: {
5142 EVT VT = TLI.getValueType(I.getType());
5143 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5144 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5145 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5146 getValue(I.getArgOperand(0)).getValueType(),
5147 getValue(I.getArgOperand(0)),
5148 getValue(I.getArgOperand(1)),
5149 getValue(I.getArgOperand(2))));
5151 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5152 getValue(I.getArgOperand(0)).getValueType(),
5153 getValue(I.getArgOperand(0)),
5154 getValue(I.getArgOperand(1)));
5155 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5156 getValue(I.getArgOperand(0)).getValueType(),
5158 getValue(I.getArgOperand(2)));
5163 case Intrinsic::convert_to_fp16:
5164 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5165 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5166 getValue(I.getArgOperand(0)),
5167 DAG.getTargetConstant(0, MVT::i32))));
5169 case Intrinsic::convert_from_fp16:
5171 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5172 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5173 getValue(I.getArgOperand(0)))));
5175 case Intrinsic::pcmarker: {
5176 SDValue Tmp = getValue(I.getArgOperand(0));
5177 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5180 case Intrinsic::readcyclecounter: {
5181 SDValue Op = getRoot();
5182 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5183 DAG.getVTList(MVT::i64, MVT::Other), Op);
5185 DAG.setRoot(Res.getValue(1));
5188 case Intrinsic::bswap:
5189 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5190 getValue(I.getArgOperand(0)).getValueType(),
5191 getValue(I.getArgOperand(0))));
5193 case Intrinsic::cttz: {
5194 SDValue Arg = getValue(I.getArgOperand(0));
5195 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5196 EVT Ty = Arg.getValueType();
5197 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5201 case Intrinsic::ctlz: {
5202 SDValue Arg = getValue(I.getArgOperand(0));
5203 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5204 EVT Ty = Arg.getValueType();
5205 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5209 case Intrinsic::ctpop: {
5210 SDValue Arg = getValue(I.getArgOperand(0));
5211 EVT Ty = Arg.getValueType();
5212 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5215 case Intrinsic::stacksave: {
5216 SDValue Op = getRoot();
5217 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5218 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5220 DAG.setRoot(Res.getValue(1));
5223 case Intrinsic::stackrestore: {
5224 Res = getValue(I.getArgOperand(0));
5225 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5228 case Intrinsic::stackprotector: {
5229 // Emit code into the DAG to store the stack guard onto the stack.
5230 MachineFunction &MF = DAG.getMachineFunction();
5231 MachineFrameInfo *MFI = MF.getFrameInfo();
5232 EVT PtrTy = TLI.getPointerTy();
5233 SDValue Src, Chain = getRoot();
5234 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5235 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5237 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5238 // global variable __stack_chk_guard.
5240 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5241 if (BC->getOpcode() == Instruction::BitCast)
5242 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5244 if (GV && TLI.useLoadStackGuardNode()) {
5245 // Emit a LOAD_STACK_GUARD node.
5246 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5248 MachinePointerInfo MPInfo(GV);
5249 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5250 unsigned Flags = MachineMemOperand::MOLoad |
5251 MachineMemOperand::MOInvariant;
5252 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5253 PtrTy.getSizeInBits() / 8,
5254 DAG.getEVTAlignment(PtrTy));
5255 Node->setMemRefs(MemRefs, MemRefs + 1);
5257 // Copy the guard value to a virtual register so that it can be
5258 // retrieved in the epilogue.
5259 Src = SDValue(Node, 0);
5260 const TargetRegisterClass *RC =
5261 TLI.getRegClassFor(Src.getSimpleValueType());
5262 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5264 SPDescriptor.setGuardReg(Reg);
5265 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5267 Src = getValue(I.getArgOperand(0)); // The guard's value.
5270 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5272 int FI = FuncInfo.StaticAllocaMap[Slot];
5273 MFI->setStackProtectorIndex(FI);
5275 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5277 // Store the stack protector onto the stack.
5278 Res = DAG.getStore(Chain, sdl, Src, FIN,
5279 MachinePointerInfo::getFixedStack(FI),
5285 case Intrinsic::objectsize: {
5286 // If we don't know by now, we're never going to know.
5287 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5289 assert(CI && "Non-constant type in __builtin_object_size?");
5291 SDValue Arg = getValue(I.getCalledValue());
5292 EVT Ty = Arg.getValueType();
5295 Res = DAG.getConstant(-1ULL, Ty);
5297 Res = DAG.getConstant(0, Ty);
5302 case Intrinsic::annotation:
5303 case Intrinsic::ptr_annotation:
5304 // Drop the intrinsic, but forward the value
5305 setValue(&I, getValue(I.getOperand(0)));
5307 case Intrinsic::assume:
5308 case Intrinsic::var_annotation:
5309 // Discard annotate attributes and assumptions
5312 case Intrinsic::init_trampoline: {
5313 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5317 Ops[1] = getValue(I.getArgOperand(0));
5318 Ops[2] = getValue(I.getArgOperand(1));
5319 Ops[3] = getValue(I.getArgOperand(2));
5320 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5321 Ops[5] = DAG.getSrcValue(F);
5323 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5328 case Intrinsic::adjust_trampoline: {
5329 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5331 getValue(I.getArgOperand(0))));
5334 case Intrinsic::gcroot:
5336 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5337 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5339 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5340 GFI->addStackRoot(FI->getIndex(), TypeMap);
5343 case Intrinsic::gcread:
5344 case Intrinsic::gcwrite:
5345 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5346 case Intrinsic::flt_rounds:
5347 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5350 case Intrinsic::expect: {
5351 // Just replace __builtin_expect(exp, c) with EXP.
5352 setValue(&I, getValue(I.getArgOperand(0)));
5356 case Intrinsic::debugtrap:
5357 case Intrinsic::trap: {
5358 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5359 if (TrapFuncName.empty()) {
5360 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5361 ISD::TRAP : ISD::DEBUGTRAP;
5362 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5365 TargetLowering::ArgListTy Args;
5367 TargetLowering::CallLoweringInfo CLI(DAG);
5368 CLI.setDebugLoc(sdl).setChain(getRoot())
5369 .setCallee(CallingConv::C, I.getType(),
5370 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5371 std::move(Args), 0);
5373 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5374 DAG.setRoot(Result.second);
5378 case Intrinsic::uadd_with_overflow:
5379 case Intrinsic::sadd_with_overflow:
5380 case Intrinsic::usub_with_overflow:
5381 case Intrinsic::ssub_with_overflow:
5382 case Intrinsic::umul_with_overflow:
5383 case Intrinsic::smul_with_overflow: {
5385 switch (Intrinsic) {
5386 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5387 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5388 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5389 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5390 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5391 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5392 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5394 SDValue Op1 = getValue(I.getArgOperand(0));
5395 SDValue Op2 = getValue(I.getArgOperand(1));
5397 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5398 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5401 case Intrinsic::prefetch: {
5403 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5405 Ops[1] = getValue(I.getArgOperand(0));
5406 Ops[2] = getValue(I.getArgOperand(1));
5407 Ops[3] = getValue(I.getArgOperand(2));
5408 Ops[4] = getValue(I.getArgOperand(3));
5409 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5410 DAG.getVTList(MVT::Other), Ops,
5411 EVT::getIntegerVT(*Context, 8),
5412 MachinePointerInfo(I.getArgOperand(0)),
5414 false, /* volatile */
5416 rw==1)); /* write */
5419 case Intrinsic::lifetime_start:
5420 case Intrinsic::lifetime_end: {
5421 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5422 // Stack coloring is not enabled in O0, discard region information.
5423 if (TM.getOptLevel() == CodeGenOpt::None)
5426 SmallVector<Value *, 4> Allocas;
5427 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5429 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5430 E = Allocas.end(); Object != E; ++Object) {
5431 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5433 // Could not find an Alloca.
5434 if (!LifetimeObject)
5437 // First check that the Alloca is static, otherwise it won't have a
5438 // valid frame index.
5439 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5440 if (SI == FuncInfo.StaticAllocaMap.end())
5443 int FI = SI->second;
5447 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5448 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5450 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5455 case Intrinsic::invariant_start:
5456 // Discard region information.
5457 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5459 case Intrinsic::invariant_end:
5460 // Discard region information.
5462 case Intrinsic::stackprotectorcheck: {
5463 // Do not actually emit anything for this basic block. Instead we initialize
5464 // the stack protector descriptor and export the guard variable so we can
5465 // access it in FinishBasicBlock.
5466 const BasicBlock *BB = I.getParent();
5467 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5468 ExportFromCurrentBlock(SPDescriptor.getGuard());
5470 // Flush our exports since we are going to process a terminator.
5471 (void)getControlRoot();
5474 case Intrinsic::clear_cache:
5475 return TLI.getClearCacheBuiltinName();
5476 case Intrinsic::donothing:
5479 case Intrinsic::experimental_stackmap: {
5483 case Intrinsic::experimental_patchpoint_void:
5484 case Intrinsic::experimental_patchpoint_i64: {
5485 visitPatchpoint(&I);
5491 std::pair<SDValue, SDValue>
5492 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5493 MachineBasicBlock *LandingPad) {
5494 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5495 MCSymbol *BeginLabel = nullptr;
5498 // Insert a label before the invoke call to mark the try range. This can be
5499 // used to detect deletion of the invoke via the MachineModuleInfo.
5500 BeginLabel = MMI.getContext().CreateTempSymbol();
5502 // For SjLj, keep track of which landing pads go with which invokes
5503 // so as to maintain the ordering of pads in the LSDA.
5504 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5505 if (CallSiteIndex) {
5506 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5507 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5509 // Now that the call site is handled, stop tracking it.
5510 MMI.setCurrentCallSite(0);
5513 // Both PendingLoads and PendingExports must be flushed here;
5514 // this call might not return.
5516 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5518 CLI.setChain(getRoot());
5521 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5522 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5524 assert((CLI.IsTailCall || Result.second.getNode()) &&
5525 "Non-null chain expected with non-tail call!");
5526 assert((Result.second.getNode() || !Result.first.getNode()) &&
5527 "Null value expected with tail call!");
5529 if (!Result.second.getNode()) {
5530 // As a special case, a null chain means that a tail call has been emitted
5531 // and the DAG root is already updated.
5534 // Since there's no actual continuation from this block, nothing can be
5535 // relying on us setting vregs for them.
5536 PendingExports.clear();
5538 DAG.setRoot(Result.second);
5542 // Insert a label at the end of the invoke call to mark the try range. This
5543 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5544 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5545 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5547 // Inform MachineModuleInfo of range.
5548 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5554 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5556 MachineBasicBlock *LandingPad) {
5557 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5558 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5559 Type *RetTy = FTy->getReturnType();
5561 TargetLowering::ArgListTy Args;
5562 TargetLowering::ArgListEntry Entry;
5563 Args.reserve(CS.arg_size());
5565 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5567 const Value *V = *i;
5570 if (V->getType()->isEmptyTy())
5573 SDValue ArgNode = getValue(V);
5574 Entry.Node = ArgNode; Entry.Ty = V->getType();
5576 // Skip the first return-type Attribute to get to params.
5577 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5578 Args.push_back(Entry);
5581 // Check if target-independent constraints permit a tail call here.
5582 // Target-dependent constraints are checked within TLI->LowerCallTo.
5583 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5586 TargetLowering::CallLoweringInfo CLI(DAG);
5587 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5588 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5589 .setTailCall(isTailCall);
5590 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5592 if (Result.first.getNode())
5593 setValue(CS.getInstruction(), Result.first);
5596 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5597 /// value is equal or not-equal to zero.
5598 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5599 for (const User *U : V->users()) {
5600 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5601 if (IC->isEquality())
5602 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5603 if (C->isNullValue())
5605 // Unknown instruction.
5611 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5613 SelectionDAGBuilder &Builder) {
5615 // Check to see if this load can be trivially constant folded, e.g. if the
5616 // input is from a string literal.
5617 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5618 // Cast pointer to the type we really want to load.
5619 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5620 PointerType::getUnqual(LoadTy));
5622 if (const Constant *LoadCst =
5623 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5625 return Builder.getValue(LoadCst);
5628 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5629 // still constant memory, the input chain can be the entry node.
5631 bool ConstantMemory = false;
5633 // Do not serialize (non-volatile) loads of constant memory with anything.
5634 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5635 Root = Builder.DAG.getEntryNode();
5636 ConstantMemory = true;
5638 // Do not serialize non-volatile loads against each other.
5639 Root = Builder.DAG.getRoot();
5642 SDValue Ptr = Builder.getValue(PtrVal);
5643 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5644 Ptr, MachinePointerInfo(PtrVal),
5646 false /*nontemporal*/,
5647 false /*isinvariant*/, 1 /* align=1 */);
5649 if (!ConstantMemory)
5650 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5654 /// processIntegerCallValue - Record the value for an instruction that
5655 /// produces an integer result, converting the type where necessary.
5656 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5659 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5661 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5663 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5664 setValue(&I, Value);
5667 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5668 /// If so, return true and lower it, otherwise return false and it will be
5669 /// lowered like a normal call.
5670 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5671 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5672 if (I.getNumArgOperands() != 3)
5675 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5676 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5677 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5678 !I.getType()->isIntegerTy())
5681 const Value *Size = I.getArgOperand(2);
5682 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5683 if (CSize && CSize->getZExtValue() == 0) {
5684 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5685 setValue(&I, DAG.getConstant(0, CallVT));
5689 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5690 std::pair<SDValue, SDValue> Res =
5691 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5692 getValue(LHS), getValue(RHS), getValue(Size),
5693 MachinePointerInfo(LHS),
5694 MachinePointerInfo(RHS));
5695 if (Res.first.getNode()) {
5696 processIntegerCallValue(I, Res.first, true);
5697 PendingLoads.push_back(Res.second);
5701 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5702 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5703 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5704 bool ActuallyDoIt = true;
5707 switch (CSize->getZExtValue()) {
5709 LoadVT = MVT::Other;
5711 ActuallyDoIt = false;
5715 LoadTy = Type::getInt16Ty(CSize->getContext());
5719 LoadTy = Type::getInt32Ty(CSize->getContext());
5723 LoadTy = Type::getInt64Ty(CSize->getContext());
5727 LoadVT = MVT::v4i32;
5728 LoadTy = Type::getInt32Ty(CSize->getContext());
5729 LoadTy = VectorType::get(LoadTy, 4);
5734 // This turns into unaligned loads. We only do this if the target natively
5735 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5736 // we'll only produce a small number of byte loads.
5738 // Require that we can find a legal MVT, and only do this if the target
5739 // supports unaligned loads of that type. Expanding into byte loads would
5741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5742 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5743 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5744 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5745 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5746 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5747 // TODO: Check alignment of src and dest ptrs.
5748 if (!TLI.isTypeLegal(LoadVT) ||
5749 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5750 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5751 ActuallyDoIt = false;
5755 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5756 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5758 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5760 processIntegerCallValue(I, Res, false);
5769 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5770 /// form. If so, return true and lower it, otherwise return false and it
5771 /// will be lowered like a normal call.
5772 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5773 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5774 if (I.getNumArgOperands() != 3)
5777 const Value *Src = I.getArgOperand(0);
5778 const Value *Char = I.getArgOperand(1);
5779 const Value *Length = I.getArgOperand(2);
5780 if (!Src->getType()->isPointerTy() ||
5781 !Char->getType()->isIntegerTy() ||
5782 !Length->getType()->isIntegerTy() ||
5783 !I.getType()->isPointerTy())
5786 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5787 std::pair<SDValue, SDValue> Res =
5788 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5789 getValue(Src), getValue(Char), getValue(Length),
5790 MachinePointerInfo(Src));
5791 if (Res.first.getNode()) {
5792 setValue(&I, Res.first);
5793 PendingLoads.push_back(Res.second);
5800 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5801 /// optimized form. If so, return true and lower it, otherwise return false
5802 /// and it will be lowered like a normal call.
5803 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5804 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5805 if (I.getNumArgOperands() != 2)
5808 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5809 if (!Arg0->getType()->isPointerTy() ||
5810 !Arg1->getType()->isPointerTy() ||
5811 !I.getType()->isPointerTy())
5814 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5815 std::pair<SDValue, SDValue> Res =
5816 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5817 getValue(Arg0), getValue(Arg1),
5818 MachinePointerInfo(Arg0),
5819 MachinePointerInfo(Arg1), isStpcpy);
5820 if (Res.first.getNode()) {
5821 setValue(&I, Res.first);
5822 DAG.setRoot(Res.second);
5829 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5830 /// If so, return true and lower it, otherwise return false and it will be
5831 /// lowered like a normal call.
5832 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5833 // Verify that the prototype makes sense. int strcmp(void*,void*)
5834 if (I.getNumArgOperands() != 2)
5837 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5838 if (!Arg0->getType()->isPointerTy() ||
5839 !Arg1->getType()->isPointerTy() ||
5840 !I.getType()->isIntegerTy())
5843 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5844 std::pair<SDValue, SDValue> Res =
5845 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5846 getValue(Arg0), getValue(Arg1),
5847 MachinePointerInfo(Arg0),
5848 MachinePointerInfo(Arg1));
5849 if (Res.first.getNode()) {
5850 processIntegerCallValue(I, Res.first, true);
5851 PendingLoads.push_back(Res.second);
5858 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5859 /// form. If so, return true and lower it, otherwise return false and it
5860 /// will be lowered like a normal call.
5861 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5862 // Verify that the prototype makes sense. size_t strlen(char *)
5863 if (I.getNumArgOperands() != 1)
5866 const Value *Arg0 = I.getArgOperand(0);
5867 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5870 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5871 std::pair<SDValue, SDValue> Res =
5872 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5873 getValue(Arg0), MachinePointerInfo(Arg0));
5874 if (Res.first.getNode()) {
5875 processIntegerCallValue(I, Res.first, false);
5876 PendingLoads.push_back(Res.second);
5883 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5884 /// form. If so, return true and lower it, otherwise return false and it
5885 /// will be lowered like a normal call.
5886 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5887 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5888 if (I.getNumArgOperands() != 2)
5891 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5892 if (!Arg0->getType()->isPointerTy() ||
5893 !Arg1->getType()->isIntegerTy() ||
5894 !I.getType()->isIntegerTy())
5897 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5898 std::pair<SDValue, SDValue> Res =
5899 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5900 getValue(Arg0), getValue(Arg1),
5901 MachinePointerInfo(Arg0));
5902 if (Res.first.getNode()) {
5903 processIntegerCallValue(I, Res.first, false);
5904 PendingLoads.push_back(Res.second);
5911 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5912 /// operation (as expected), translate it to an SDNode with the specified opcode
5913 /// and return true.
5914 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5916 // Sanity check that it really is a unary floating-point call.
5917 if (I.getNumArgOperands() != 1 ||
5918 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5919 I.getType() != I.getArgOperand(0)->getType() ||
5920 !I.onlyReadsMemory())
5923 SDValue Tmp = getValue(I.getArgOperand(0));
5924 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5928 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5929 /// operation (as expected), translate it to an SDNode with the specified opcode
5930 /// and return true.
5931 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5933 // Sanity check that it really is a binary floating-point call.
5934 if (I.getNumArgOperands() != 2 ||
5935 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5936 I.getType() != I.getArgOperand(0)->getType() ||
5937 I.getType() != I.getArgOperand(1)->getType() ||
5938 !I.onlyReadsMemory())
5941 SDValue Tmp0 = getValue(I.getArgOperand(0));
5942 SDValue Tmp1 = getValue(I.getArgOperand(1));
5943 EVT VT = Tmp0.getValueType();
5944 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5948 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5949 // Handle inline assembly differently.
5950 if (isa<InlineAsm>(I.getCalledValue())) {
5955 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5956 ComputeUsesVAFloatArgument(I, &MMI);
5958 const char *RenameFn = nullptr;
5959 if (Function *F = I.getCalledFunction()) {
5960 if (F->isDeclaration()) {
5961 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5962 if (unsigned IID = II->getIntrinsicID(F)) {
5963 RenameFn = visitIntrinsicCall(I, IID);
5968 if (unsigned IID = F->getIntrinsicID()) {
5969 RenameFn = visitIntrinsicCall(I, IID);
5975 // Check for well-known libc/libm calls. If the function is internal, it
5976 // can't be a library call.
5978 if (!F->hasLocalLinkage() && F->hasName() &&
5979 LibInfo->getLibFunc(F->getName(), Func) &&
5980 LibInfo->hasOptimizedCodeGen(Func)) {
5983 case LibFunc::copysign:
5984 case LibFunc::copysignf:
5985 case LibFunc::copysignl:
5986 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5987 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5988 I.getType() == I.getArgOperand(0)->getType() &&
5989 I.getType() == I.getArgOperand(1)->getType() &&
5990 I.onlyReadsMemory()) {
5991 SDValue LHS = getValue(I.getArgOperand(0));
5992 SDValue RHS = getValue(I.getArgOperand(1));
5993 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5994 LHS.getValueType(), LHS, RHS));
5999 case LibFunc::fabsf:
6000 case LibFunc::fabsl:
6001 if (visitUnaryFloatCall(I, ISD::FABS))
6005 case LibFunc::fminf:
6006 case LibFunc::fminl:
6007 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6011 case LibFunc::fmaxf:
6012 case LibFunc::fmaxl:
6013 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6019 if (visitUnaryFloatCall(I, ISD::FSIN))
6025 if (visitUnaryFloatCall(I, ISD::FCOS))
6029 case LibFunc::sqrtf:
6030 case LibFunc::sqrtl:
6031 case LibFunc::sqrt_finite:
6032 case LibFunc::sqrtf_finite:
6033 case LibFunc::sqrtl_finite:
6034 if (visitUnaryFloatCall(I, ISD::FSQRT))
6037 case LibFunc::floor:
6038 case LibFunc::floorf:
6039 case LibFunc::floorl:
6040 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6043 case LibFunc::nearbyint:
6044 case LibFunc::nearbyintf:
6045 case LibFunc::nearbyintl:
6046 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6050 case LibFunc::ceilf:
6051 case LibFunc::ceill:
6052 if (visitUnaryFloatCall(I, ISD::FCEIL))
6056 case LibFunc::rintf:
6057 case LibFunc::rintl:
6058 if (visitUnaryFloatCall(I, ISD::FRINT))
6061 case LibFunc::round:
6062 case LibFunc::roundf:
6063 case LibFunc::roundl:
6064 if (visitUnaryFloatCall(I, ISD::FROUND))
6067 case LibFunc::trunc:
6068 case LibFunc::truncf:
6069 case LibFunc::truncl:
6070 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6074 case LibFunc::log2f:
6075 case LibFunc::log2l:
6076 if (visitUnaryFloatCall(I, ISD::FLOG2))
6080 case LibFunc::exp2f:
6081 case LibFunc::exp2l:
6082 if (visitUnaryFloatCall(I, ISD::FEXP2))
6085 case LibFunc::memcmp:
6086 if (visitMemCmpCall(I))
6089 case LibFunc::memchr:
6090 if (visitMemChrCall(I))
6093 case LibFunc::strcpy:
6094 if (visitStrCpyCall(I, false))
6097 case LibFunc::stpcpy:
6098 if (visitStrCpyCall(I, true))
6101 case LibFunc::strcmp:
6102 if (visitStrCmpCall(I))
6105 case LibFunc::strlen:
6106 if (visitStrLenCall(I))
6109 case LibFunc::strnlen:
6110 if (visitStrNLenCall(I))
6119 Callee = getValue(I.getCalledValue());
6121 Callee = DAG.getExternalSymbol(RenameFn,
6122 DAG.getTargetLoweringInfo().getPointerTy());
6124 // Check if we can potentially perform a tail call. More detailed checking is
6125 // be done within LowerCallTo, after more information about the call is known.
6126 LowerCallTo(&I, Callee, I.isTailCall());
6131 /// AsmOperandInfo - This contains information for each constraint that we are
6133 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6135 /// CallOperand - If this is the result output operand or a clobber
6136 /// this is null, otherwise it is the incoming operand to the CallInst.
6137 /// This gets modified as the asm is processed.
6138 SDValue CallOperand;
6140 /// AssignedRegs - If this is a register or register class operand, this
6141 /// contains the set of register corresponding to the operand.
6142 RegsForValue AssignedRegs;
6144 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6145 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6148 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6149 /// corresponds to. If there is no Value* for this operand, it returns
6151 EVT getCallOperandValEVT(LLVMContext &Context,
6152 const TargetLowering &TLI,
6153 const DataLayout *DL) const {
6154 if (!CallOperandVal) return MVT::Other;
6156 if (isa<BasicBlock>(CallOperandVal))
6157 return TLI.getPointerTy();
6159 llvm::Type *OpTy = CallOperandVal->getType();
6161 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6162 // If this is an indirect operand, the operand is a pointer to the
6165 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6167 report_fatal_error("Indirect operand for inline asm not a pointer!");
6168 OpTy = PtrTy->getElementType();
6171 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6172 if (StructType *STy = dyn_cast<StructType>(OpTy))
6173 if (STy->getNumElements() == 1)
6174 OpTy = STy->getElementType(0);
6176 // If OpTy is not a single value, it may be a struct/union that we
6177 // can tile with integers.
6178 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6179 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6188 OpTy = IntegerType::get(Context, BitSize);
6193 return TLI.getValueType(OpTy, true);
6197 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6199 } // end anonymous namespace
6201 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6202 /// specified operand. We prefer to assign virtual registers, to allow the
6203 /// register allocator to handle the assignment process. However, if the asm
6204 /// uses features that we can't model on machineinstrs, we have SDISel do the
6205 /// allocation. This produces generally horrible, but correct, code.
6207 /// OpInfo describes the operand.
6209 static void GetRegistersForValue(SelectionDAG &DAG,
6210 const TargetLowering &TLI,
6212 SDISelAsmOperandInfo &OpInfo) {
6213 LLVMContext &Context = *DAG.getContext();
6215 MachineFunction &MF = DAG.getMachineFunction();
6216 SmallVector<unsigned, 4> Regs;
6218 // If this is a constraint for a single physreg, or a constraint for a
6219 // register class, find it.
6220 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6221 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6222 OpInfo.ConstraintVT);
6224 unsigned NumRegs = 1;
6225 if (OpInfo.ConstraintVT != MVT::Other) {
6226 // If this is a FP input in an integer register (or visa versa) insert a bit
6227 // cast of the input value. More generally, handle any case where the input
6228 // value disagrees with the register class we plan to stick this in.
6229 if (OpInfo.Type == InlineAsm::isInput &&
6230 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6231 // Try to convert to the first EVT that the reg class contains. If the
6232 // types are identical size, use a bitcast to convert (e.g. two differing
6234 MVT RegVT = *PhysReg.second->vt_begin();
6235 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6236 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6237 RegVT, OpInfo.CallOperand);
6238 OpInfo.ConstraintVT = RegVT;
6239 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6240 // If the input is a FP value and we want it in FP registers, do a
6241 // bitcast to the corresponding integer type. This turns an f64 value
6242 // into i64, which can be passed with two i32 values on a 32-bit
6244 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6245 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6246 RegVT, OpInfo.CallOperand);
6247 OpInfo.ConstraintVT = RegVT;
6251 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6255 EVT ValueVT = OpInfo.ConstraintVT;
6257 // If this is a constraint for a specific physical register, like {r17},
6259 if (unsigned AssignedReg = PhysReg.first) {
6260 const TargetRegisterClass *RC = PhysReg.second;
6261 if (OpInfo.ConstraintVT == MVT::Other)
6262 ValueVT = *RC->vt_begin();
6264 // Get the actual register value type. This is important, because the user
6265 // may have asked for (e.g.) the AX register in i32 type. We need to
6266 // remember that AX is actually i16 to get the right extension.
6267 RegVT = *RC->vt_begin();
6269 // This is a explicit reference to a physical register.
6270 Regs.push_back(AssignedReg);
6272 // If this is an expanded reference, add the rest of the regs to Regs.
6274 TargetRegisterClass::iterator I = RC->begin();
6275 for (; *I != AssignedReg; ++I)
6276 assert(I != RC->end() && "Didn't find reg!");
6278 // Already added the first reg.
6280 for (; NumRegs; --NumRegs, ++I) {
6281 assert(I != RC->end() && "Ran out of registers to allocate!");
6286 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6290 // Otherwise, if this was a reference to an LLVM register class, create vregs
6291 // for this reference.
6292 if (const TargetRegisterClass *RC = PhysReg.second) {
6293 RegVT = *RC->vt_begin();
6294 if (OpInfo.ConstraintVT == MVT::Other)
6297 // Create the appropriate number of virtual registers.
6298 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6299 for (; NumRegs; --NumRegs)
6300 Regs.push_back(RegInfo.createVirtualRegister(RC));
6302 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6306 // Otherwise, we couldn't allocate enough registers for this.
6309 /// visitInlineAsm - Handle a call to an InlineAsm object.
6311 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6312 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6314 /// ConstraintOperands - Information about all of the constraints.
6315 SDISelAsmOperandInfoVector ConstraintOperands;
6317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6318 TargetLowering::AsmOperandInfoVector
6319 TargetConstraints = TLI.ParseConstraints(CS);
6321 bool hasMemory = false;
6323 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6324 unsigned ResNo = 0; // ResNo - The result number of the next output.
6325 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6326 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6327 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6329 MVT OpVT = MVT::Other;
6331 // Compute the value type for each operand.
6332 switch (OpInfo.Type) {
6333 case InlineAsm::isOutput:
6334 // Indirect outputs just consume an argument.
6335 if (OpInfo.isIndirect) {
6336 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6340 // The return value of the call is this value. As such, there is no
6341 // corresponding argument.
6342 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6343 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6344 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6346 assert(ResNo == 0 && "Asm only has one result!");
6347 OpVT = TLI.getSimpleValueType(CS.getType());
6351 case InlineAsm::isInput:
6352 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6354 case InlineAsm::isClobber:
6359 // If this is an input or an indirect output, process the call argument.
6360 // BasicBlocks are labels, currently appearing only in asm's.
6361 if (OpInfo.CallOperandVal) {
6362 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6363 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6365 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6369 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6372 OpInfo.ConstraintVT = OpVT;
6374 // Indirect operand accesses access memory.
6375 if (OpInfo.isIndirect)
6378 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6379 TargetLowering::ConstraintType
6380 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6381 if (CType == TargetLowering::C_Memory) {
6389 SDValue Chain, Flag;
6391 // We won't need to flush pending loads if this asm doesn't touch
6392 // memory and is nonvolatile.
6393 if (hasMemory || IA->hasSideEffects())
6396 Chain = DAG.getRoot();
6398 // Second pass over the constraints: compute which constraint option to use
6399 // and assign registers to constraints that want a specific physreg.
6400 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6401 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6403 // If this is an output operand with a matching input operand, look up the
6404 // matching input. If their types mismatch, e.g. one is an integer, the
6405 // other is floating point, or their sizes are different, flag it as an
6407 if (OpInfo.hasMatchingInput()) {
6408 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6410 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6411 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6412 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6413 OpInfo.ConstraintVT);
6414 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6415 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6416 Input.ConstraintVT);
6417 if ((OpInfo.ConstraintVT.isInteger() !=
6418 Input.ConstraintVT.isInteger()) ||
6419 (MatchRC.second != InputRC.second)) {
6420 report_fatal_error("Unsupported asm: input constraint"
6421 " with a matching output constraint of"
6422 " incompatible type!");
6424 Input.ConstraintVT = OpInfo.ConstraintVT;
6428 // Compute the constraint code and ConstraintType to use.
6429 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6431 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6432 OpInfo.Type == InlineAsm::isClobber)
6435 // If this is a memory input, and if the operand is not indirect, do what we
6436 // need to to provide an address for the memory input.
6437 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6438 !OpInfo.isIndirect) {
6439 assert((OpInfo.isMultipleAlternative ||
6440 (OpInfo.Type == InlineAsm::isInput)) &&
6441 "Can only indirectify direct input operands!");
6443 // Memory operands really want the address of the value. If we don't have
6444 // an indirect input, put it in the constpool if we can, otherwise spill
6445 // it to a stack slot.
6446 // TODO: This isn't quite right. We need to handle these according to
6447 // the addressing mode that the constraint wants. Also, this may take
6448 // an additional register for the computation and we don't want that
6451 // If the operand is a float, integer, or vector constant, spill to a
6452 // constant pool entry to get its address.
6453 const Value *OpVal = OpInfo.CallOperandVal;
6454 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6455 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6456 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6457 TLI.getPointerTy());
6459 // Otherwise, create a stack slot and emit a store to it before the
6461 Type *Ty = OpVal->getType();
6462 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6463 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6464 MachineFunction &MF = DAG.getMachineFunction();
6465 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6466 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6467 Chain = DAG.getStore(Chain, getCurSDLoc(),
6468 OpInfo.CallOperand, StackSlot,
6469 MachinePointerInfo::getFixedStack(SSFI),
6471 OpInfo.CallOperand = StackSlot;
6474 // There is no longer a Value* corresponding to this operand.
6475 OpInfo.CallOperandVal = nullptr;
6477 // It is now an indirect operand.
6478 OpInfo.isIndirect = true;
6481 // If this constraint is for a specific register, allocate it before
6483 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6484 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6487 // Second pass - Loop over all of the operands, assigning virtual or physregs
6488 // to register class operands.
6489 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6490 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6492 // C_Register operands have already been allocated, Other/Memory don't need
6494 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6495 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6498 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6499 std::vector<SDValue> AsmNodeOperands;
6500 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6501 AsmNodeOperands.push_back(
6502 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6503 TLI.getPointerTy()));
6505 // If we have a !srcloc metadata node associated with it, we want to attach
6506 // this to the ultimately generated inline asm machineinstr. To do this, we
6507 // pass in the third operand as this (potentially null) inline asm MDNode.
6508 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6509 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6511 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6512 // bits as operand 3.
6513 unsigned ExtraInfo = 0;
6514 if (IA->hasSideEffects())
6515 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6516 if (IA->isAlignStack())
6517 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6518 // Set the asm dialect.
6519 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6521 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6522 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6523 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6525 // Compute the constraint code and ConstraintType to use.
6526 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6528 // Ideally, we would only check against memory constraints. However, the
6529 // meaning of an other constraint can be target-specific and we can't easily
6530 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6531 // for other constriants as well.
6532 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6533 OpInfo.ConstraintType == TargetLowering::C_Other) {
6534 if (OpInfo.Type == InlineAsm::isInput)
6535 ExtraInfo |= InlineAsm::Extra_MayLoad;
6536 else if (OpInfo.Type == InlineAsm::isOutput)
6537 ExtraInfo |= InlineAsm::Extra_MayStore;
6538 else if (OpInfo.Type == InlineAsm::isClobber)
6539 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6543 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6544 TLI.getPointerTy()));
6546 // Loop over all of the inputs, copying the operand values into the
6547 // appropriate registers and processing the output regs.
6548 RegsForValue RetValRegs;
6550 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6551 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6553 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6554 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6556 switch (OpInfo.Type) {
6557 case InlineAsm::isOutput: {
6558 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6559 OpInfo.ConstraintType != TargetLowering::C_Register) {
6560 // Memory output, or 'other' output (e.g. 'X' constraint).
6561 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6563 // Add information to the INLINEASM node to know about this output.
6564 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6565 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6566 TLI.getPointerTy()));
6567 AsmNodeOperands.push_back(OpInfo.CallOperand);
6571 // Otherwise, this is a register or register class output.
6573 // Copy the output from the appropriate register. Find a register that
6575 if (OpInfo.AssignedRegs.Regs.empty()) {
6576 LLVMContext &Ctx = *DAG.getContext();
6577 Ctx.emitError(CS.getInstruction(),
6578 "couldn't allocate output register for constraint '" +
6579 Twine(OpInfo.ConstraintCode) + "'");
6583 // If this is an indirect operand, store through the pointer after the
6585 if (OpInfo.isIndirect) {
6586 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6587 OpInfo.CallOperandVal));
6589 // This is the result value of the call.
6590 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6591 // Concatenate this output onto the outputs list.
6592 RetValRegs.append(OpInfo.AssignedRegs);
6595 // Add information to the INLINEASM node to know that this register is
6598 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6599 ? InlineAsm::Kind_RegDefEarlyClobber
6600 : InlineAsm::Kind_RegDef,
6601 false, 0, DAG, AsmNodeOperands);
6604 case InlineAsm::isInput: {
6605 SDValue InOperandVal = OpInfo.CallOperand;
6607 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6608 // If this is required to match an output register we have already set,
6609 // just use its register.
6610 unsigned OperandNo = OpInfo.getMatchedOperand();
6612 // Scan until we find the definition we already emitted of this operand.
6613 // When we find it, create a RegsForValue operand.
6614 unsigned CurOp = InlineAsm::Op_FirstOperand;
6615 for (; OperandNo; --OperandNo) {
6616 // Advance to the next operand.
6618 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6619 assert((InlineAsm::isRegDefKind(OpFlag) ||
6620 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6621 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6622 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6626 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6627 if (InlineAsm::isRegDefKind(OpFlag) ||
6628 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6629 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6630 if (OpInfo.isIndirect) {
6631 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6632 LLVMContext &Ctx = *DAG.getContext();
6633 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6634 " don't know how to handle tied "
6635 "indirect register inputs");
6639 RegsForValue MatchedRegs;
6640 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6641 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6642 MatchedRegs.RegVTs.push_back(RegVT);
6643 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6644 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6646 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6647 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6649 LLVMContext &Ctx = *DAG.getContext();
6650 Ctx.emitError(CS.getInstruction(),
6651 "inline asm error: This value"
6652 " type register class is not natively supported!");
6656 // Use the produced MatchedRegs object to
6657 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6658 Chain, &Flag, CS.getInstruction());
6659 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6660 true, OpInfo.getMatchedOperand(),
6661 DAG, AsmNodeOperands);
6665 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6666 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6667 "Unexpected number of operands");
6668 // Add information to the INLINEASM node to know about this input.
6669 // See InlineAsm.h isUseOperandTiedToDef.
6670 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6671 OpInfo.getMatchedOperand());
6672 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6673 TLI.getPointerTy()));
6674 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6678 // Treat indirect 'X' constraint as memory.
6679 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6681 OpInfo.ConstraintType = TargetLowering::C_Memory;
6683 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6684 std::vector<SDValue> Ops;
6685 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6688 LLVMContext &Ctx = *DAG.getContext();
6689 Ctx.emitError(CS.getInstruction(),
6690 "invalid operand for inline asm constraint '" +
6691 Twine(OpInfo.ConstraintCode) + "'");
6695 // Add information to the INLINEASM node to know about this input.
6696 unsigned ResOpType =
6697 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6698 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6699 TLI.getPointerTy()));
6700 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6704 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6705 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6706 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6707 "Memory operands expect pointer values");
6709 // Add information to the INLINEASM node to know about this input.
6710 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6711 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6712 TLI.getPointerTy()));
6713 AsmNodeOperands.push_back(InOperandVal);
6717 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6718 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6719 "Unknown constraint type!");
6721 // TODO: Support this.
6722 if (OpInfo.isIndirect) {
6723 LLVMContext &Ctx = *DAG.getContext();
6724 Ctx.emitError(CS.getInstruction(),
6725 "Don't know how to handle indirect register inputs yet "
6726 "for constraint '" +
6727 Twine(OpInfo.ConstraintCode) + "'");
6731 // Copy the input into the appropriate registers.
6732 if (OpInfo.AssignedRegs.Regs.empty()) {
6733 LLVMContext &Ctx = *DAG.getContext();
6734 Ctx.emitError(CS.getInstruction(),
6735 "couldn't allocate input reg for constraint '" +
6736 Twine(OpInfo.ConstraintCode) + "'");
6740 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6741 Chain, &Flag, CS.getInstruction());
6743 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6744 DAG, AsmNodeOperands);
6747 case InlineAsm::isClobber: {
6748 // Add the clobbered value to the operand list, so that the register
6749 // allocator is aware that the physreg got clobbered.
6750 if (!OpInfo.AssignedRegs.Regs.empty())
6751 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6759 // Finish up input operands. Set the input chain and add the flag last.
6760 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6761 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6763 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6764 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6765 Flag = Chain.getValue(1);
6767 // If this asm returns a register value, copy the result from that register
6768 // and set it as the value of the call.
6769 if (!RetValRegs.Regs.empty()) {
6770 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6771 Chain, &Flag, CS.getInstruction());
6773 // FIXME: Why don't we do this for inline asms with MRVs?
6774 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6775 EVT ResultType = TLI.getValueType(CS.getType());
6777 // If any of the results of the inline asm is a vector, it may have the
6778 // wrong width/num elts. This can happen for register classes that can
6779 // contain multiple different value types. The preg or vreg allocated may
6780 // not have the same VT as was expected. Convert it to the right type
6781 // with bit_convert.
6782 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6783 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6786 } else if (ResultType != Val.getValueType() &&
6787 ResultType.isInteger() && Val.getValueType().isInteger()) {
6788 // If a result value was tied to an input value, the computed result may
6789 // have a wider width than the expected result. Extract the relevant
6791 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6794 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6797 setValue(CS.getInstruction(), Val);
6798 // Don't need to use this as a chain in this case.
6799 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6803 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6805 // Process indirect outputs, first output all of the flagged copies out of
6807 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6808 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6809 const Value *Ptr = IndirectStoresToEmit[i].second;
6810 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6812 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6815 // Emit the non-flagged stores from the physregs.
6816 SmallVector<SDValue, 8> OutChains;
6817 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6818 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6819 StoresToEmit[i].first,
6820 getValue(StoresToEmit[i].second),
6821 MachinePointerInfo(StoresToEmit[i].second),
6823 OutChains.push_back(Val);
6826 if (!OutChains.empty())
6827 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6832 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6833 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6834 MVT::Other, getRoot(),
6835 getValue(I.getArgOperand(0)),
6836 DAG.getSrcValue(I.getArgOperand(0))));
6839 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6841 const DataLayout &DL = *TLI.getDataLayout();
6842 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6843 getRoot(), getValue(I.getOperand(0)),
6844 DAG.getSrcValue(I.getOperand(0)),
6845 DL.getABITypeAlignment(I.getType()));
6847 DAG.setRoot(V.getValue(1));
6850 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6851 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6852 MVT::Other, getRoot(),
6853 getValue(I.getArgOperand(0)),
6854 DAG.getSrcValue(I.getArgOperand(0))));
6857 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6858 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6859 MVT::Other, getRoot(),
6860 getValue(I.getArgOperand(0)),
6861 getValue(I.getArgOperand(1)),
6862 DAG.getSrcValue(I.getArgOperand(0)),
6863 DAG.getSrcValue(I.getArgOperand(1))));
6866 /// \brief Lower an argument list according to the target calling convention.
6868 /// \return A tuple of <return-value, token-chain>
6870 /// This is a helper for lowering intrinsics that follow a target calling
6871 /// convention or require stack pointer adjustment. Only a subset of the
6872 /// intrinsic's operands need to participate in the calling convention.
6873 std::pair<SDValue, SDValue>
6874 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6875 unsigned NumArgs, SDValue Callee,
6877 MachineBasicBlock *LandingPad) {
6878 TargetLowering::ArgListTy Args;
6879 Args.reserve(NumArgs);
6881 // Populate the argument list.
6882 // Attributes for args start at offset 1, after the return attribute.
6883 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6884 ArgI != ArgE; ++ArgI) {
6885 const Value *V = CS->getOperand(ArgI);
6887 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6889 TargetLowering::ArgListEntry Entry;
6890 Entry.Node = getValue(V);
6891 Entry.Ty = V->getType();
6892 Entry.setAttributes(&CS, AttrI);
6893 Args.push_back(Entry);
6896 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6897 TargetLowering::CallLoweringInfo CLI(DAG);
6898 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6899 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6900 .setDiscardResult(CS->use_empty());
6902 return lowerInvokable(CLI, LandingPad);
6905 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6906 /// or patchpoint target node's operand list.
6908 /// Constants are converted to TargetConstants purely as an optimization to
6909 /// avoid constant materialization and register allocation.
6911 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6912 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6913 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6914 /// address materialization and register allocation, but may also be required
6915 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6916 /// alloca in the entry block, then the runtime may assume that the alloca's
6917 /// StackMap location can be read immediately after compilation and that the
6918 /// location is valid at any point during execution (this is similar to the
6919 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6920 /// only available in a register, then the runtime would need to trap when
6921 /// execution reaches the StackMap in order to read the alloca's location.
6922 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6923 SmallVectorImpl<SDValue> &Ops,
6924 SelectionDAGBuilder &Builder) {
6925 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6926 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6927 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6929 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6931 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6932 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6933 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6935 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6937 Ops.push_back(OpVal);
6941 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6942 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6943 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6944 // [live variables...])
6946 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6948 SDValue Chain, InFlag, Callee, NullPtr;
6949 SmallVector<SDValue, 32> Ops;
6951 SDLoc DL = getCurSDLoc();
6952 Callee = getValue(CI.getCalledValue());
6953 NullPtr = DAG.getIntPtrConstant(0, true);
6955 // The stackmap intrinsic only records the live variables (the arguemnts
6956 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6957 // intrinsic, this won't be lowered to a function call. This means we don't
6958 // have to worry about calling conventions and target specific lowering code.
6959 // Instead we perform the call lowering right here.
6961 // chain, flag = CALLSEQ_START(chain, 0)
6962 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6963 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6965 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6966 InFlag = Chain.getValue(1);
6968 // Add the <id> and <numBytes> constants.
6969 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6970 Ops.push_back(DAG.getTargetConstant(
6971 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6972 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6973 Ops.push_back(DAG.getTargetConstant(
6974 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6976 // Push live variables for the stack map.
6977 addStackMapLiveVars(&CI, 2, Ops, *this);
6979 // We are not pushing any register mask info here on the operands list,
6980 // because the stackmap doesn't clobber anything.
6982 // Push the chain and the glue flag.
6983 Ops.push_back(Chain);
6984 Ops.push_back(InFlag);
6986 // Create the STACKMAP node.
6987 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6988 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6989 Chain = SDValue(SM, 0);
6990 InFlag = Chain.getValue(1);
6992 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6994 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6996 // Set the root to the target-lowered call chain.
6999 // Inform the Frame Information that we have a stackmap in this function.
7000 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7003 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7004 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7005 MachineBasicBlock *LandingPad) {
7006 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7011 // [live variables...])
7013 CallingConv::ID CC = CS.getCallingConv();
7014 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7015 bool HasDef = !CS->getType()->isVoidTy();
7016 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7018 // Get the real number of arguments participating in the call <numArgs>
7019 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7020 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7022 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7023 // Intrinsics include all meta-operands up to but not including CC.
7024 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7025 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7026 "Not enough arguments provided to the patchpoint intrinsic");
7028 // For AnyRegCC the arguments are lowered later on manually.
7029 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7030 std::pair<SDValue, SDValue> Result =
7031 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7034 SDNode *CallEnd = Result.second.getNode();
7035 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7036 CallEnd = CallEnd->getOperand(0).getNode();
7038 /// Get a call instruction from the call sequence chain.
7039 /// Tail calls are not allowed.
7040 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7041 "Expected a callseq node.");
7042 SDNode *Call = CallEnd->getOperand(0).getNode();
7043 bool HasGlue = Call->getGluedNode();
7045 // Replace the target specific call node with the patchable intrinsic.
7046 SmallVector<SDValue, 8> Ops;
7048 // Add the <id> and <numBytes> constants.
7049 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7050 Ops.push_back(DAG.getTargetConstant(
7051 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7052 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7053 Ops.push_back(DAG.getTargetConstant(
7054 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7056 // Assume that the Callee is a constant address.
7057 // FIXME: handle function symbols in the future.
7059 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7060 /*isTarget=*/true));
7062 // Adjust <numArgs> to account for any arguments that have been passed on the
7064 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7065 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7066 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7067 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7069 // Add the calling convention
7070 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7072 // Add the arguments we omitted previously. The register allocator should
7073 // place these in any free register.
7075 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7076 Ops.push_back(getValue(CS.getArgument(i)));
7078 // Push the arguments from the call instruction up to the register mask.
7079 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7080 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7083 // Push live variables for the stack map.
7084 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7086 // Push the register mask info.
7088 Ops.push_back(*(Call->op_end()-2));
7090 Ops.push_back(*(Call->op_end()-1));
7092 // Push the chain (this is originally the first operand of the call, but
7093 // becomes now the last or second to last operand).
7094 Ops.push_back(*(Call->op_begin()));
7096 // Push the glue flag (last operand).
7098 Ops.push_back(*(Call->op_end()-1));
7101 if (IsAnyRegCC && HasDef) {
7102 // Create the return types based on the intrinsic definition
7103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7104 SmallVector<EVT, 3> ValueVTs;
7105 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7106 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7108 // There is always a chain and a glue type at the end
7109 ValueVTs.push_back(MVT::Other);
7110 ValueVTs.push_back(MVT::Glue);
7111 NodeTys = DAG.getVTList(ValueVTs);
7113 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7115 // Replace the target specific call node with a PATCHPOINT node.
7116 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7117 getCurSDLoc(), NodeTys, Ops);
7119 // Update the NodeMap.
7122 setValue(CS.getInstruction(), SDValue(MN, 0));
7124 setValue(CS.getInstruction(), Result.first);
7127 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7128 // call sequence. Furthermore the location of the chain and glue can change
7129 // when the AnyReg calling convention is used and the intrinsic returns a
7131 if (IsAnyRegCC && HasDef) {
7132 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7133 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7134 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7136 DAG.ReplaceAllUsesWith(Call, MN);
7137 DAG.DeleteNode(Call);
7139 // Inform the Frame Information that we have a patchpoint in this function.
7140 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7143 /// Returns an AttributeSet representing the attributes applied to the return
7144 /// value of the given call.
7145 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7146 SmallVector<Attribute::AttrKind, 2> Attrs;
7148 Attrs.push_back(Attribute::SExt);
7150 Attrs.push_back(Attribute::ZExt);
7152 Attrs.push_back(Attribute::InReg);
7154 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7158 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7159 /// implementation, which just calls LowerCall.
7160 /// FIXME: When all targets are
7161 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7162 std::pair<SDValue, SDValue>
7163 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7164 // Handle the incoming return values from the call.
7166 Type *OrigRetTy = CLI.RetTy;
7167 SmallVector<EVT, 4> RetTys;
7168 SmallVector<uint64_t, 4> Offsets;
7169 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7171 SmallVector<ISD::OutputArg, 4> Outs;
7172 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7174 bool CanLowerReturn =
7175 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7176 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7178 SDValue DemoteStackSlot;
7179 int DemoteStackIdx = -100;
7180 if (!CanLowerReturn) {
7181 // FIXME: equivalent assert?
7182 // assert(!CS.hasInAllocaArgument() &&
7183 // "sret demotion is incompatible with inalloca");
7184 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7185 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7186 MachineFunction &MF = CLI.DAG.getMachineFunction();
7187 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7188 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7190 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7192 Entry.Node = DemoteStackSlot;
7193 Entry.Ty = StackSlotPtrType;
7194 Entry.isSExt = false;
7195 Entry.isZExt = false;
7196 Entry.isInReg = false;
7197 Entry.isSRet = true;
7198 Entry.isNest = false;
7199 Entry.isByVal = false;
7200 Entry.isReturned = false;
7201 Entry.Alignment = Align;
7202 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7203 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7205 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7207 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7208 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7209 for (unsigned i = 0; i != NumRegs; ++i) {
7210 ISD::InputArg MyFlags;
7211 MyFlags.VT = RegisterVT;
7213 MyFlags.Used = CLI.IsReturnValueUsed;
7215 MyFlags.Flags.setSExt();
7217 MyFlags.Flags.setZExt();
7219 MyFlags.Flags.setInReg();
7220 CLI.Ins.push_back(MyFlags);
7225 // Handle all of the outgoing arguments.
7227 CLI.OutVals.clear();
7228 ArgListTy &Args = CLI.getArgs();
7229 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7230 SmallVector<EVT, 4> ValueVTs;
7231 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7232 Type *FinalType = Args[i].Ty;
7233 if (Args[i].isByVal)
7234 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7235 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7236 FinalType, CLI.CallConv, CLI.IsVarArg);
7237 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7239 EVT VT = ValueVTs[Value];
7240 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7241 SDValue Op = SDValue(Args[i].Node.getNode(),
7242 Args[i].Node.getResNo() + Value);
7243 ISD::ArgFlagsTy Flags;
7244 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7250 if (Args[i].isInReg)
7254 if (Args[i].isByVal)
7256 if (Args[i].isInAlloca) {
7257 Flags.setInAlloca();
7258 // Set the byval flag for CCAssignFn callbacks that don't know about
7259 // inalloca. This way we can know how many bytes we should've allocated
7260 // and how many bytes a callee cleanup function will pop. If we port
7261 // inalloca to more targets, we'll have to add custom inalloca handling
7262 // in the various CC lowering callbacks.
7265 if (Args[i].isByVal || Args[i].isInAlloca) {
7266 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7267 Type *ElementTy = Ty->getElementType();
7268 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7269 // For ByVal, alignment should come from FE. BE will guess if this
7270 // info is not there but there are cases it cannot get right.
7271 unsigned FrameAlign;
7272 if (Args[i].Alignment)
7273 FrameAlign = Args[i].Alignment;
7275 FrameAlign = getByValTypeAlignment(ElementTy);
7276 Flags.setByValAlign(FrameAlign);
7280 if (NeedsRegBlock) {
7281 Flags.setInConsecutiveRegs();
7282 if (Value == NumValues - 1)
7283 Flags.setInConsecutiveRegsLast();
7285 Flags.setOrigAlign(OriginalAlignment);
7287 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7288 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7289 SmallVector<SDValue, 4> Parts(NumParts);
7290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7293 ExtendKind = ISD::SIGN_EXTEND;
7294 else if (Args[i].isZExt)
7295 ExtendKind = ISD::ZERO_EXTEND;
7297 // Conservatively only handle 'returned' on non-vectors for now
7298 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7299 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7300 "unexpected use of 'returned'");
7301 // Before passing 'returned' to the target lowering code, ensure that
7302 // either the register MVT and the actual EVT are the same size or that
7303 // the return value and argument are extended in the same way; in these
7304 // cases it's safe to pass the argument register value unchanged as the
7305 // return register value (although it's at the target's option whether
7307 // TODO: allow code generation to take advantage of partially preserved
7308 // registers rather than clobbering the entire register when the
7309 // parameter extension method is not compatible with the return
7311 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7312 (ExtendKind != ISD::ANY_EXTEND &&
7313 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7314 Flags.setReturned();
7317 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7318 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7320 for (unsigned j = 0; j != NumParts; ++j) {
7321 // if it isn't first piece, alignment must be 1
7322 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7323 i < CLI.NumFixedArgs,
7324 i, j*Parts[j].getValueType().getStoreSize());
7325 if (NumParts > 1 && j == 0)
7326 MyFlags.Flags.setSplit();
7328 MyFlags.Flags.setOrigAlign(1);
7330 CLI.Outs.push_back(MyFlags);
7331 CLI.OutVals.push_back(Parts[j]);
7336 SmallVector<SDValue, 4> InVals;
7337 CLI.Chain = LowerCall(CLI, InVals);
7339 // Verify that the target's LowerCall behaved as expected.
7340 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7341 "LowerCall didn't return a valid chain!");
7342 assert((!CLI.IsTailCall || InVals.empty()) &&
7343 "LowerCall emitted a return value for a tail call!");
7344 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7345 "LowerCall didn't emit the correct number of values!");
7347 // For a tail call, the return value is merely live-out and there aren't
7348 // any nodes in the DAG representing it. Return a special value to
7349 // indicate that a tail call has been emitted and no more Instructions
7350 // should be processed in the current block.
7351 if (CLI.IsTailCall) {
7352 CLI.DAG.setRoot(CLI.Chain);
7353 return std::make_pair(SDValue(), SDValue());
7356 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7357 assert(InVals[i].getNode() &&
7358 "LowerCall emitted a null value!");
7359 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7360 "LowerCall emitted a value with the wrong type!");
7363 SmallVector<SDValue, 4> ReturnValues;
7364 if (!CanLowerReturn) {
7365 // The instruction result is the result of loading from the
7366 // hidden sret parameter.
7367 SmallVector<EVT, 1> PVTs;
7368 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7370 ComputeValueVTs(*this, PtrRetTy, PVTs);
7371 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7372 EVT PtrVT = PVTs[0];
7374 unsigned NumValues = RetTys.size();
7375 ReturnValues.resize(NumValues);
7376 SmallVector<SDValue, 4> Chains(NumValues);
7378 for (unsigned i = 0; i < NumValues; ++i) {
7379 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7380 CLI.DAG.getConstant(Offsets[i], PtrVT));
7381 SDValue L = CLI.DAG.getLoad(
7382 RetTys[i], CLI.DL, CLI.Chain, Add,
7383 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7385 ReturnValues[i] = L;
7386 Chains[i] = L.getValue(1);
7389 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7391 // Collect the legal value parts into potentially illegal values
7392 // that correspond to the original function's return values.
7393 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7395 AssertOp = ISD::AssertSext;
7396 else if (CLI.RetZExt)
7397 AssertOp = ISD::AssertZext;
7398 unsigned CurReg = 0;
7399 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7401 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7402 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7404 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7405 NumRegs, RegisterVT, VT, nullptr,
7410 // For a function returning void, there is no return value. We can't create
7411 // such a node, so we just return a null return value in that case. In
7412 // that case, nothing will actually look at the value.
7413 if (ReturnValues.empty())
7414 return std::make_pair(SDValue(), CLI.Chain);
7417 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7418 CLI.DAG.getVTList(RetTys), ReturnValues);
7419 return std::make_pair(Res, CLI.Chain);
7422 void TargetLowering::LowerOperationWrapper(SDNode *N,
7423 SmallVectorImpl<SDValue> &Results,
7424 SelectionDAG &DAG) const {
7425 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7427 Results.push_back(Res);
7430 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7431 llvm_unreachable("LowerOperation not implemented for this target!");
7435 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7436 SDValue Op = getNonRegisterValue(V);
7437 assert((Op.getOpcode() != ISD::CopyFromReg ||
7438 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7439 "Copy from a reg to the same reg!");
7440 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7443 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7444 SDValue Chain = DAG.getEntryNode();
7446 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7447 FuncInfo.PreferredExtendType.end())
7449 : FuncInfo.PreferredExtendType[V];
7450 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7451 PendingExports.push_back(Chain);
7454 #include "llvm/CodeGen/SelectionDAGISel.h"
7456 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7457 /// entry block, return true. This includes arguments used by switches, since
7458 /// the switch may expand into multiple basic blocks.
7459 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7460 // With FastISel active, we may be splitting blocks, so force creation
7461 // of virtual registers for all non-dead arguments.
7463 return A->use_empty();
7465 const BasicBlock *Entry = A->getParent()->begin();
7466 for (const User *U : A->users())
7467 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7468 return false; // Use not in entry block.
7473 void SelectionDAGISel::LowerArguments(const Function &F) {
7474 SelectionDAG &DAG = SDB->DAG;
7475 SDLoc dl = SDB->getCurSDLoc();
7476 const DataLayout *DL = TLI->getDataLayout();
7477 SmallVector<ISD::InputArg, 16> Ins;
7479 if (!FuncInfo->CanLowerReturn) {
7480 // Put in an sret pointer parameter before all the other parameters.
7481 SmallVector<EVT, 1> ValueVTs;
7482 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7484 // NOTE: Assuming that a pointer will never break down to more than one VT
7486 ISD::ArgFlagsTy Flags;
7488 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7489 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7490 Ins.push_back(RetArg);
7493 // Set up the incoming argument description vector.
7495 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7496 I != E; ++I, ++Idx) {
7497 SmallVector<EVT, 4> ValueVTs;
7498 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7499 bool isArgValueUsed = !I->use_empty();
7500 unsigned PartBase = 0;
7501 Type *FinalType = I->getType();
7502 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7503 FinalType = cast<PointerType>(FinalType)->getElementType();
7504 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7505 FinalType, F.getCallingConv(), F.isVarArg());
7506 for (unsigned Value = 0, NumValues = ValueVTs.size();
7507 Value != NumValues; ++Value) {
7508 EVT VT = ValueVTs[Value];
7509 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7510 ISD::ArgFlagsTy Flags;
7511 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7513 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7515 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7517 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7519 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7521 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7523 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7524 Flags.setInAlloca();
7525 // Set the byval flag for CCAssignFn callbacks that don't know about
7526 // inalloca. This way we can know how many bytes we should've allocated
7527 // and how many bytes a callee cleanup function will pop. If we port
7528 // inalloca to more targets, we'll have to add custom inalloca handling
7529 // in the various CC lowering callbacks.
7532 if (Flags.isByVal() || Flags.isInAlloca()) {
7533 PointerType *Ty = cast<PointerType>(I->getType());
7534 Type *ElementTy = Ty->getElementType();
7535 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7536 // For ByVal, alignment should be passed from FE. BE will guess if
7537 // this info is not there but there are cases it cannot get right.
7538 unsigned FrameAlign;
7539 if (F.getParamAlignment(Idx))
7540 FrameAlign = F.getParamAlignment(Idx);
7542 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7543 Flags.setByValAlign(FrameAlign);
7545 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7547 if (NeedsRegBlock) {
7548 Flags.setInConsecutiveRegs();
7549 if (Value == NumValues - 1)
7550 Flags.setInConsecutiveRegsLast();
7552 Flags.setOrigAlign(OriginalAlignment);
7554 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7555 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7556 for (unsigned i = 0; i != NumRegs; ++i) {
7557 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7558 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7559 if (NumRegs > 1 && i == 0)
7560 MyFlags.Flags.setSplit();
7561 // if it isn't first piece, alignment must be 1
7563 MyFlags.Flags.setOrigAlign(1);
7564 Ins.push_back(MyFlags);
7566 PartBase += VT.getStoreSize();
7570 // Call the target to set up the argument values.
7571 SmallVector<SDValue, 8> InVals;
7572 SDValue NewRoot = TLI->LowerFormalArguments(
7573 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7575 // Verify that the target's LowerFormalArguments behaved as expected.
7576 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7577 "LowerFormalArguments didn't return a valid chain!");
7578 assert(InVals.size() == Ins.size() &&
7579 "LowerFormalArguments didn't emit the correct number of values!");
7581 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7582 assert(InVals[i].getNode() &&
7583 "LowerFormalArguments emitted a null value!");
7584 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7585 "LowerFormalArguments emitted a value with the wrong type!");
7589 // Update the DAG with the new chain value resulting from argument lowering.
7590 DAG.setRoot(NewRoot);
7592 // Set up the argument values.
7595 if (!FuncInfo->CanLowerReturn) {
7596 // Create a virtual register for the sret pointer, and put in a copy
7597 // from the sret argument into it.
7598 SmallVector<EVT, 1> ValueVTs;
7599 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7600 MVT VT = ValueVTs[0].getSimpleVT();
7601 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7602 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7603 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7604 RegVT, VT, nullptr, AssertOp);
7606 MachineFunction& MF = SDB->DAG.getMachineFunction();
7607 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7608 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7609 FuncInfo->DemoteRegister = SRetReg;
7611 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7612 DAG.setRoot(NewRoot);
7614 // i indexes lowered arguments. Bump it past the hidden sret argument.
7615 // Idx indexes LLVM arguments. Don't touch it.
7619 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7621 SmallVector<SDValue, 4> ArgValues;
7622 SmallVector<EVT, 4> ValueVTs;
7623 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7624 unsigned NumValues = ValueVTs.size();
7626 // If this argument is unused then remember its value. It is used to generate
7627 // debugging information.
7628 if (I->use_empty() && NumValues) {
7629 SDB->setUnusedArgValue(I, InVals[i]);
7631 // Also remember any frame index for use in FastISel.
7632 if (FrameIndexSDNode *FI =
7633 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7634 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7637 for (unsigned Val = 0; Val != NumValues; ++Val) {
7638 EVT VT = ValueVTs[Val];
7639 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7640 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7642 if (!I->use_empty()) {
7643 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7644 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7645 AssertOp = ISD::AssertSext;
7646 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7647 AssertOp = ISD::AssertZext;
7649 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7650 NumParts, PartVT, VT,
7651 nullptr, AssertOp));
7657 // We don't need to do anything else for unused arguments.
7658 if (ArgValues.empty())
7661 // Note down frame index.
7662 if (FrameIndexSDNode *FI =
7663 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7664 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7666 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7667 SDB->getCurSDLoc());
7669 SDB->setValue(I, Res);
7670 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7671 if (LoadSDNode *LNode =
7672 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7673 if (FrameIndexSDNode *FI =
7674 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7675 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7678 // If this argument is live outside of the entry block, insert a copy from
7679 // wherever we got it to the vreg that other BB's will reference it as.
7680 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7681 // If we can, though, try to skip creating an unnecessary vreg.
7682 // FIXME: This isn't very clean... it would be nice to make this more
7683 // general. It's also subtly incompatible with the hacks FastISel
7685 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7686 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7687 FuncInfo->ValueMap[I] = Reg;
7691 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7692 FuncInfo->InitializeRegForValue(I);
7693 SDB->CopyToExportRegsIfNeeded(I);
7697 assert(i == InVals.size() && "Argument register count mismatch!");
7699 // Finally, if the target has anything special to do, allow it to do so.
7700 // FIXME: this should insert code into the DAG!
7701 EmitFunctionEntryCode();
7704 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7705 /// ensure constants are generated when needed. Remember the virtual registers
7706 /// that need to be added to the Machine PHI nodes as input. We cannot just
7707 /// directly add them, because expansion might result in multiple MBB's for one
7708 /// BB. As such, the start of the BB might correspond to a different MBB than
7712 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7713 const TerminatorInst *TI = LLVMBB->getTerminator();
7715 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7717 // Check successor nodes' PHI nodes that expect a constant to be available
7719 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7720 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7721 if (!isa<PHINode>(SuccBB->begin())) continue;
7722 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7724 // If this terminator has multiple identical successors (common for
7725 // switches), only handle each succ once.
7726 if (!SuccsHandled.insert(SuccMBB).second)
7729 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7731 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7732 // nodes and Machine PHI nodes, but the incoming operands have not been
7734 for (BasicBlock::const_iterator I = SuccBB->begin();
7735 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7736 // Ignore dead phi's.
7737 if (PN->use_empty()) continue;
7740 if (PN->getType()->isEmptyTy())
7744 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7746 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7747 unsigned &RegOut = ConstantsOut[C];
7749 RegOut = FuncInfo.CreateRegs(C->getType());
7750 CopyValueToVirtualRegister(C, RegOut);
7754 DenseMap<const Value *, unsigned>::iterator I =
7755 FuncInfo.ValueMap.find(PHIOp);
7756 if (I != FuncInfo.ValueMap.end())
7759 assert(isa<AllocaInst>(PHIOp) &&
7760 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7761 "Didn't codegen value into a register!??");
7762 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7763 CopyValueToVirtualRegister(PHIOp, Reg);
7767 // Remember that this register needs to added to the machine PHI node as
7768 // the input for this MBB.
7769 SmallVector<EVT, 4> ValueVTs;
7770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7771 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7772 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7773 EVT VT = ValueVTs[vti];
7774 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7775 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7776 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7777 Reg += NumRegisters;
7782 ConstantsOut.clear();
7785 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7788 SelectionDAGBuilder::StackProtectorDescriptor::
7789 AddSuccessorMBB(const BasicBlock *BB,
7790 MachineBasicBlock *ParentMBB,
7792 MachineBasicBlock *SuccMBB) {
7793 // If SuccBB has not been created yet, create it.
7795 MachineFunction *MF = ParentMBB->getParent();
7796 MachineFunction::iterator BBI = ParentMBB;
7797 SuccMBB = MF->CreateMachineBasicBlock(BB);
7798 MF->insert(++BBI, SuccMBB);
7800 // Add it as a successor of ParentMBB.
7801 ParentMBB->addSuccessor(
7802 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));