1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/IntegersSubsetMapping.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetIntrinsicInfo.h"
58 #include "llvm/Target/TargetLibraryInfo.h"
59 #include "llvm/Target/TargetLowering.h"
60 #include "llvm/Target/TargetOptions.h"
64 /// LimitFloatPrecision - Generate low-precision inline sequences for
65 /// some float libcalls (6, 8 or 12 bits).
66 static unsigned LimitFloatPrecision;
68 static cl::opt<unsigned, true>
69 LimitFPPrecision("limit-float-precision",
70 cl::desc("Generate low-precision inline sequences "
71 "for some float libcalls"),
72 cl::location(LimitFloatPrecision),
75 // Limit the width of DAG chains. This is important in general to prevent
76 // prevent DAG-based analysis from blowing up. For example, alias analysis and
77 // load clustering may not complete in reasonable time. It is difficult to
78 // recognize and avoid this situation within each individual analysis, and
79 // future analyses are likely to have the same behavior. Limiting DAG width is
80 // the safe approach, and will be especially important with global DAGs.
82 // MaxParallelChains default is arbitrarily high to avoid affecting
83 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
84 // sequence over this should have been converted to llvm.memcpy by the
85 // frontend. It easy to induce this behavior with .ll code such as:
86 // %buffer = alloca [4096 x i8]
87 // %data = load [4096 x i8]* %argPtr
88 // store [4096 x i8] %data, [4096 x i8]* %buffer
89 static const unsigned MaxParallelChains = 64;
91 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
92 const SDValue *Parts, unsigned NumParts,
93 MVT PartVT, EVT ValueVT, const Value *V);
95 /// getCopyFromParts - Create a value that contains the specified legal parts
96 /// combined into the value they represent. If the parts combine to a type
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
100 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
101 const SDValue *Parts,
102 unsigned NumParts, MVT PartVT, EVT ValueVT,
104 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
105 if (ValueVT.isVector())
106 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
109 assert(NumParts > 0 && "No parts to assemble!");
110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
111 SDValue Val = Parts[0];
114 // Assemble the value from multiple parts.
115 if (ValueVT.isInteger()) {
116 unsigned PartBits = PartVT.getSizeInBits();
117 unsigned ValueBits = ValueVT.getSizeInBits();
119 // Assemble the power of 2 part.
120 unsigned RoundParts = NumParts & (NumParts - 1) ?
121 1 << Log2_32(NumParts) : NumParts;
122 unsigned RoundBits = PartBits * RoundParts;
123 EVT RoundVT = RoundBits == ValueBits ?
124 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
127 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
129 if (RoundParts > 2) {
130 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
132 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
133 RoundParts / 2, PartVT, HalfVT, V);
135 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
136 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
139 if (TLI.isBigEndian())
142 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
144 if (RoundParts < NumParts) {
145 // Assemble the trailing non-power-of-2 part.
146 unsigned OddParts = NumParts - RoundParts;
147 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
148 Hi = getCopyFromParts(DAG, DL,
149 Parts + RoundParts, OddParts, PartVT, OddVT, V);
151 // Combine the round and odd parts.
153 if (TLI.isBigEndian())
155 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
156 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
157 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
158 DAG.getConstant(Lo.getValueType().getSizeInBits(),
159 TLI.getPointerTy()));
160 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
161 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
163 } else if (PartVT.isFloatingPoint()) {
164 // FP split into multiple FP parts (for ppcf128)
165 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
168 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
169 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
170 if (TLI.isBigEndian())
172 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
174 // FP split into integer parts (soft fp)
175 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
176 !PartVT.isVector() && "Unexpected split");
177 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
178 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
182 // There is now one part, held in Val. Correct it to match ValueVT.
183 EVT PartEVT = Val.getValueType();
185 if (PartEVT == ValueVT)
188 if (PartEVT.isInteger() && ValueVT.isInteger()) {
189 if (ValueVT.bitsLT(PartEVT)) {
190 // For a truncate, see if we have any information to
191 // indicate whether the truncated bits will always be
192 // zero or sign-extension.
193 if (AssertOp != ISD::DELETED_NODE)
194 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
195 DAG.getValueType(ValueVT));
196 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
198 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
201 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
202 // FP_ROUND's are always exact here.
203 if (ValueVT.bitsLT(Val.getValueType()))
204 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
205 DAG.getTargetConstant(1, TLI.getPointerTy()));
207 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
210 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
211 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
213 llvm_unreachable("Unknown mismatch!");
216 /// getCopyFromPartsVector - Create a value that contains the specified legal
217 /// parts combined into the value they represent. If the parts combine to a
218 /// type larger then ValueVT then AssertOp can be used to specify whether the
219 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
220 /// ValueVT (ISD::AssertSext).
221 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
222 const SDValue *Parts, unsigned NumParts,
223 MVT PartVT, EVT ValueVT, const Value *V) {
224 assert(ValueVT.isVector() && "Not a vector value");
225 assert(NumParts > 0 && "No parts to assemble!");
226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
227 SDValue Val = Parts[0];
229 // Handle a multi-element vector.
233 unsigned NumIntermediates;
235 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
236 NumIntermediates, RegisterVT);
237 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
238 NumParts = NumRegs; // Silence a compiler warning.
239 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
240 assert(RegisterVT == Parts[0].getSimpleValueType() &&
241 "Part type doesn't match part!");
243 // Assemble the parts into intermediate operands.
244 SmallVector<SDValue, 8> Ops(NumIntermediates);
245 if (NumIntermediates == NumParts) {
246 // If the register was not expanded, truncate or copy the value,
248 for (unsigned i = 0; i != NumParts; ++i)
249 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
250 PartVT, IntermediateVT, V);
251 } else if (NumParts > 0) {
252 // If the intermediate type was expanded, build the intermediate
253 // operands from the parts.
254 assert(NumParts % NumIntermediates == 0 &&
255 "Must expand into a divisible number of parts!");
256 unsigned Factor = NumParts / NumIntermediates;
257 for (unsigned i = 0; i != NumIntermediates; ++i)
258 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
259 PartVT, IntermediateVT, V);
262 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
263 // intermediate operands.
264 Val = DAG.getNode(IntermediateVT.isVector() ?
265 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
266 ValueVT, &Ops[0], NumIntermediates);
269 // There is now one part, held in Val. Correct it to match ValueVT.
270 EVT PartEVT = Val.getValueType();
272 if (PartEVT == ValueVT)
275 if (PartEVT.isVector()) {
276 // If the element type of the source/dest vectors are the same, but the
277 // parts vector has more elements than the value vector, then we have a
278 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
280 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
281 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
282 "Cannot narrow, it would be a lossy transformation");
283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
284 DAG.getIntPtrConstant(0));
287 // Vector/Vector bitcast.
288 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
289 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
291 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
292 "Cannot handle this kind of promotion");
293 // Promoted vector extract
294 bool Smaller = ValueVT.bitsLE(PartEVT);
295 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
300 // Trivial bitcast if the types are the same size and the destination
301 // vector type is legal.
302 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
303 TLI.isTypeLegal(ValueVT))
304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
306 // Handle cases such as i8 -> <1 x i1>
307 if (ValueVT.getVectorNumElements() != 1) {
308 LLVMContext &Ctx = *DAG.getContext();
309 Twine ErrMsg("non-trivial scalar-to-vector conversion");
310 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
311 if (const CallInst *CI = dyn_cast<CallInst>(I))
312 if (isa<InlineAsm>(CI->getCalledValue()))
313 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
314 Ctx.emitError(I, ErrMsg);
316 Ctx.emitError(ErrMsg);
318 return DAG.getUNDEF(ValueVT);
321 if (ValueVT.getVectorNumElements() == 1 &&
322 ValueVT.getVectorElementType() != PartEVT) {
323 bool Smaller = ValueVT.bitsLE(PartEVT);
324 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
325 DL, ValueVT.getScalarType(), Val);
328 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
331 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
332 SDValue Val, SDValue *Parts, unsigned NumParts,
333 MVT PartVT, const Value *V);
335 /// getCopyToParts - Create a series of nodes that contain the specified value
336 /// split into legal parts. If the parts contain more bits than Val, then, for
337 /// integers, ExtendKind can be used to specify how to generate the extra bits.
338 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
339 SDValue Val, SDValue *Parts, unsigned NumParts,
340 MVT PartVT, const Value *V,
341 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
342 EVT ValueVT = Val.getValueType();
344 // Handle the vector case separately.
345 if (ValueVT.isVector())
346 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
349 unsigned PartBits = PartVT.getSizeInBits();
350 unsigned OrigNumParts = NumParts;
351 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
356 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
357 EVT PartEVT = PartVT;
358 if (PartEVT == ValueVT) {
359 assert(NumParts == 1 && "No-op copy with multiple parts!");
364 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
365 // If the parts cover more bits than the value has, promote the value.
366 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
367 assert(NumParts == 1 && "Do not know what to promote to!");
368 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
371 ValueVT.isInteger() &&
372 "Unknown mismatch!");
373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
374 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
375 if (PartVT == MVT::x86mmx)
376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
378 } else if (PartBits == ValueVT.getSizeInBits()) {
379 // Different types of the same size.
380 assert(NumParts == 1 && PartEVT != ValueVT);
381 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
382 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
383 // If the parts cover less bits than value has, truncate the value.
384 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
385 ValueVT.isInteger() &&
386 "Unknown mismatch!");
387 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
388 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
389 if (PartVT == MVT::x86mmx)
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 // The value may have changed - recompute ValueVT.
394 ValueVT = Val.getValueType();
395 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
396 "Failed to tile the value with PartVT!");
399 if (PartEVT != ValueVT) {
400 LLVMContext &Ctx = *DAG.getContext();
401 Twine ErrMsg("scalar-to-vector conversion failed");
402 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
403 if (const CallInst *CI = dyn_cast<CallInst>(I))
404 if (isa<InlineAsm>(CI->getCalledValue()))
405 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
406 Ctx.emitError(I, ErrMsg);
408 Ctx.emitError(ErrMsg);
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getIntPtrConstant(i)));
495 for (unsigned i = ValueVT.getVectorNumElements(),
496 e = PartVT.getVectorNumElements(); i != e; ++i)
497 Ops.push_back(DAG.getUNDEF(ElementVT));
499 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
501 // FIXME: Use CONCAT for 2x -> 4x.
503 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
504 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
505 } else if (PartVT.isVector() &&
506 PartEVT.getVectorElementType().bitsGE(
507 ValueVT.getVectorElementType()) &&
508 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
510 // Promoted vector extract
511 bool Smaller = PartEVT.bitsLE(ValueVT);
512 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
515 // Vector -> scalar conversion.
516 assert(ValueVT.getVectorNumElements() == 1 &&
517 "Only trivial vector-to-scalar conversions should get here!");
518 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
519 PartVT, Val, DAG.getIntPtrConstant(0));
521 bool Smaller = ValueVT.bitsLE(PartVT);
522 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
530 // Handle a multi-element vector.
533 unsigned NumIntermediates;
534 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
536 NumIntermediates, RegisterVT);
537 unsigned NumElements = ValueVT.getVectorNumElements();
539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540 NumParts = NumRegs; // Silence a compiler warning.
541 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
543 // Split the vector into intermediate operands.
544 SmallVector<SDValue, 8> Ops(NumIntermediates);
545 for (unsigned i = 0; i != NumIntermediates; ++i) {
546 if (IntermediateVT.isVector())
547 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
549 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
551 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
552 IntermediateVT, Val, DAG.getIntPtrConstant(i));
555 // Split the intermediate operands into legal parts.
556 if (NumParts == NumIntermediates) {
557 // If the register was not expanded, promote or copy the value,
559 for (unsigned i = 0; i != NumParts; ++i)
560 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
561 } else if (NumParts > 0) {
562 // If the intermediate type was expanded, split each the value into
564 assert(NumParts % NumIntermediates == 0 &&
565 "Must expand into a divisible number of parts!");
566 unsigned Factor = NumParts / NumIntermediates;
567 for (unsigned i = 0; i != NumIntermediates; ++i)
568 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
573 /// RegsForValue - This struct represents the registers (physical or virtual)
574 /// that a particular set of values is assigned, and the type information
575 /// about the value. The most common situation is to represent one value at a
576 /// time, but struct or array values are handled element-wise as multiple
577 /// values. The splitting of aggregates is performed recursively, so that we
578 /// never have aggregate-typed registers. The values at this point do not
579 /// necessarily have legal types, so each value may require one or more
580 /// registers of some legal type.
582 struct RegsForValue {
583 /// ValueVTs - The value types of the values, which may not be legal, and
584 /// may need be promoted or synthesized from one or more registers.
586 SmallVector<EVT, 4> ValueVTs;
588 /// RegVTs - The value types of the registers. This is the same size as
589 /// ValueVTs and it records, for each value, what the type of the assigned
590 /// register or registers are. (Individual values are never synthesized
591 /// from more than one type of register.)
593 /// With virtual registers, the contents of RegVTs is redundant with TLI's
594 /// getRegisterType member function, however when with physical registers
595 /// it is necessary to have a separate record of the types.
597 SmallVector<MVT, 4> RegVTs;
599 /// Regs - This list holds the registers assigned to the values.
600 /// Each legal or promoted value requires one register, and each
601 /// expanded value requires multiple registers.
603 SmallVector<unsigned, 4> Regs;
607 RegsForValue(const SmallVector<unsigned, 4> ®s,
608 MVT regvt, EVT valuevt)
609 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
611 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
612 unsigned Reg, Type *Ty) {
613 ComputeValueVTs(tli, Ty, ValueVTs);
615 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
616 EVT ValueVT = ValueVTs[Value];
617 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
618 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
619 for (unsigned i = 0; i != NumRegs; ++i)
620 Regs.push_back(Reg + i);
621 RegVTs.push_back(RegisterVT);
626 /// areValueTypesLegal - Return true if types of all the values are legal.
627 bool areValueTypesLegal(const TargetLowering &TLI) {
628 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
629 MVT RegisterVT = RegVTs[Value];
630 if (!TLI.isTypeLegal(RegisterVT))
636 /// append - Add the specified values to this one.
637 void append(const RegsForValue &RHS) {
638 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
639 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
640 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
644 /// this value and returns the result as a ValueVTs value. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
649 SDValue &Chain, SDValue *Flag,
650 const Value *V = 0) const;
652 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
653 /// specified value into the registers specified by this object. This uses
654 /// Chain/Flag as the input and updates them for the output Chain/Flag.
655 /// If the Flag pointer is NULL, no flag is used.
656 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
657 SDValue &Chain, SDValue *Flag, const Value *V) const;
659 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
660 /// operand list. This adds the code marker, matching input operand index
661 /// (if applicable), and includes the number of values added into it.
662 void AddInlineAsmOperands(unsigned Kind,
663 bool HasMatching, unsigned MatchingIdx,
665 std::vector<SDValue> &Ops) const;
669 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
670 /// this value and returns the result as a ValueVT value. This uses
671 /// Chain/Flag as the input and updates them for the output Chain/Flag.
672 /// If the Flag pointer is NULL, no flag is used.
673 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
674 FunctionLoweringInfo &FuncInfo,
676 SDValue &Chain, SDValue *Flag,
677 const Value *V) const {
678 // A Value with type {} or [0 x %t] needs no registers.
679 if (ValueVTs.empty())
682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
684 // Assemble the legal parts into the final values.
685 SmallVector<SDValue, 4> Values(ValueVTs.size());
686 SmallVector<SDValue, 8> Parts;
687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
688 // Copy the legal parts from the registers.
689 EVT ValueVT = ValueVTs[Value];
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
691 MVT RegisterVT = RegVTs[Value];
693 Parts.resize(NumRegs);
694 for (unsigned i = 0; i != NumRegs; ++i) {
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
700 *Flag = P.getValue(2);
703 Chain = P.getValue(1);
706 // If the source register was virtual and if we know something about it,
707 // add an assert node.
708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
709 !RegisterVT.isInteger() || RegisterVT.isVector())
712 const FunctionLoweringInfo::LiveOutInfo *LOI =
713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
717 unsigned RegSize = RegisterVT.getSizeInBits();
718 unsigned NumSignBits = LOI->NumSignBits;
719 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
721 if (NumZeroBits == RegSize) {
722 // The current value is a zero.
723 // Explicitly express that as it would be easier for
724 // optimizations to kick in.
725 Parts[i] = DAG.getConstant(0, RegisterVT);
729 // FIXME: We capture more information than the dag can represent. For
730 // now, just use the tightest assertzext/assertsext possible.
732 EVT FromVT(MVT::Other);
733 if (NumSignBits == RegSize)
734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
735 else if (NumZeroBits >= RegSize-1)
736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
737 else if (NumSignBits > RegSize-8)
738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
739 else if (NumZeroBits >= RegSize-8)
740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
741 else if (NumSignBits > RegSize-16)
742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
743 else if (NumZeroBits >= RegSize-16)
744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
745 else if (NumSignBits > RegSize-32)
746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
747 else if (NumZeroBits >= RegSize-32)
748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
752 // Add an assertion node.
753 assert(FromVT != MVT::Other);
754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
755 RegisterVT, P, DAG.getValueType(FromVT));
758 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
759 NumRegs, RegisterVT, ValueVT, V);
764 return DAG.getNode(ISD::MERGE_VALUES, dl,
765 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
766 &Values[0], ValueVTs.size());
769 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
770 /// specified value into the registers specified by this object. This uses
771 /// Chain/Flag as the input and updates them for the output Chain/Flag.
772 /// If the Flag pointer is NULL, no flag is used.
773 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
774 SDValue &Chain, SDValue *Flag,
775 const Value *V) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 // Get the list of the values's legal parts.
779 unsigned NumRegs = Regs.size();
780 SmallVector<SDValue, 8> Parts(NumRegs);
781 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
782 EVT ValueVT = ValueVTs[Value];
783 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
784 MVT RegisterVT = RegVTs[Value];
785 ISD::NodeType ExtendKind =
786 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
789 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
793 // Copy the parts into the registers.
794 SmallVector<SDValue, 8> Chains(NumRegs);
795 for (unsigned i = 0; i != NumRegs; ++i) {
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
800 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
801 *Flag = Part.getValue(1);
804 Chains[i] = Part.getValue(0);
807 if (NumRegs == 1 || Flag)
808 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
809 // flagged to it. That is the CopyToReg nodes and the user are considered
810 // a single scheduling unit. If we create a TokenFactor and return it as
811 // chain, then the TokenFactor is both a predecessor (operand) of the
812 // user as well as a successor (the TF operands are flagged to the user).
813 // c1, f1 = CopyToReg
814 // c2, f2 = CopyToReg
815 // c3 = TokenFactor c1, c2
818 Chain = Chains[NumRegs-1];
820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
823 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
824 /// operand list. This adds the code marker and includes the number of
825 /// values added into it.
826 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
827 unsigned MatchingIdx,
829 std::vector<SDValue> &Ops) const {
830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
832 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
834 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
835 else if (!Regs.empty() &&
836 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
837 // Put the register class of the virtual registers in the flag word. That
838 // way, later passes can recompute register class constraints for inline
839 // assembly as well as normal instructions.
840 // Don't do this for tied operands that can use the regclass information
842 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
843 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
844 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
847 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
860 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
861 const TargetLibraryInfo *li) {
865 TD = DAG.getTarget().getDataLayout();
866 Context = DAG.getContext();
867 LPadToCallSiteMap.clear();
870 /// clear - Clear out the current SelectionDAG and the associated
871 /// state and prepare this SelectionDAGBuilder object to be used
872 /// for a new block. This doesn't clear out information about
873 /// additional blocks that are needed to complete switch lowering
874 /// or PHI node updating; that information is cleared out as it is
876 void SelectionDAGBuilder::clear() {
878 UnusedArgNodeMap.clear();
879 PendingLoads.clear();
880 PendingExports.clear();
885 /// clearDanglingDebugInfo - Clear the dangling debug information
886 /// map. This function is separated from the clear so that debug
887 /// information that is dangling in a basic block can be properly
888 /// resolved in a different basic block. This allows the
889 /// SelectionDAG to resolve dangling debug information attached
891 void SelectionDAGBuilder::clearDanglingDebugInfo() {
892 DanglingDebugInfoMap.clear();
895 /// getRoot - Return the current virtual root of the Selection DAG,
896 /// flushing any PendingLoad items. This must be done before emitting
897 /// a store or any other node that may need to be ordered after any
898 /// prior load instructions.
900 SDValue SelectionDAGBuilder::getRoot() {
901 if (PendingLoads.empty())
902 return DAG.getRoot();
904 if (PendingLoads.size() == 1) {
905 SDValue Root = PendingLoads[0];
907 PendingLoads.clear();
911 // Otherwise, we have to make a token factor node.
912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
913 &PendingLoads[0], PendingLoads.size());
914 PendingLoads.clear();
919 /// getControlRoot - Similar to getRoot, but instead of flushing all the
920 /// PendingLoad items, flush all the PendingExports items. It is necessary
921 /// to do this before emitting a terminator instruction.
923 SDValue SelectionDAGBuilder::getControlRoot() {
924 SDValue Root = DAG.getRoot();
926 if (PendingExports.empty())
929 // Turn all of the CopyToReg chains into one factored node.
930 if (Root.getOpcode() != ISD::EntryToken) {
931 unsigned i = 0, e = PendingExports.size();
932 for (; i != e; ++i) {
933 assert(PendingExports[i].getNode()->getNumOperands() > 1);
934 if (PendingExports[i].getNode()->getOperand(0) == Root)
935 break; // Don't add the root if we already indirectly depend on it.
939 PendingExports.push_back(Root);
942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 PendingExports.size());
945 PendingExports.clear();
950 void SelectionDAGBuilder::visit(const Instruction &I) {
951 // Set up outgoing PHI node register values before emitting the terminator.
952 if (isa<TerminatorInst>(&I))
953 HandlePHINodesInSuccessorBlocks(I.getParent());
959 visit(I.getOpcode(), I);
961 if (!isa<TerminatorInst>(&I) && !HasTailCall)
962 CopyToExportRegsIfNeeded(&I);
967 void SelectionDAGBuilder::visitPHI(const PHINode &) {
968 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
971 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
972 // Note: this doesn't use InstVisitor, because it has to work with
973 // ConstantExpr's in addition to instructions.
975 default: llvm_unreachable("Unknown instruction type encountered!");
976 // Build the switch statement using the Instruction.def file.
977 #define HANDLE_INST(NUM, OPCODE, CLASS) \
978 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
979 #include "llvm/IR/Instruction.def"
983 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
984 // generate the debug data structures now that we've seen its definition.
985 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
987 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
989 const DbgValueInst *DI = DDI.getDI();
990 DebugLoc dl = DDI.getdl();
991 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
992 MDNode *Variable = DI->getVariable();
993 uint64_t Offset = DI->getOffset();
996 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
997 SDV = DAG.getDbgValue(Variable, Val.getNode(),
998 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
999 DAG.AddDbgValue(SDV, Val.getNode(), false);
1002 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1003 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1007 /// getValue - Return an SDValue for the given Value.
1008 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1009 // If we already have an SDValue for this value, use it. It's important
1010 // to do this first, so that we don't create a CopyFromReg if we already
1011 // have a regular SDValue.
1012 SDValue &N = NodeMap[V];
1013 if (N.getNode()) return N;
1015 // If there's a virtual register allocated and initialized for this
1017 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1018 if (It != FuncInfo.ValueMap.end()) {
1019 unsigned InReg = It->second;
1020 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1021 InReg, V->getType());
1022 SDValue Chain = DAG.getEntryNode();
1023 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1024 resolveDanglingDebugInfo(V, N);
1028 // Otherwise create a new SDValue and remember it.
1029 SDValue Val = getValueImpl(V);
1031 resolveDanglingDebugInfo(V, Val);
1035 /// getNonRegisterValue - Return an SDValue for the given Value, but
1036 /// don't look in FuncInfo.ValueMap for a virtual register.
1037 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1038 // If we already have an SDValue for this value, use it.
1039 SDValue &N = NodeMap[V];
1040 if (N.getNode()) return N;
1042 // Otherwise create a new SDValue and remember it.
1043 SDValue Val = getValueImpl(V);
1045 resolveDanglingDebugInfo(V, Val);
1049 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1050 /// Create an SDValue for the given value.
1051 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1052 const TargetLowering *TLI = TM.getTargetLowering();
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI->getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1063 if (isa<ConstantPointerNull>(C))
1064 return DAG.getConstant(0, TLI->getPointerTy());
1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1067 return DAG.getConstantFP(*CFP, VT);
1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1070 return DAG.getUNDEF(VT);
1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1073 visit(CE->getOpcode(), *CE);
1074 SDValue N1 = NodeMap[V];
1075 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1080 SmallVector<SDValue, 4> Constants;
1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1083 SDNode *Val = getValue(*OI).getNode();
1084 // If the operand is an empty aggregate, there are no values.
1086 // Add each leaf value from the operand to the Constants list
1087 // to form a flattened list of all the values.
1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1089 Constants.push_back(SDValue(Val, i));
1092 return DAG.getMergeValues(&Constants[0], Constants.size(),
1096 if (const ConstantDataSequential *CDS =
1097 dyn_cast<ConstantDataSequential>(C)) {
1098 SmallVector<SDValue, 4> Ops;
1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Ops.push_back(SDValue(Val, i));
1107 if (isa<ArrayType>(CDS->getType()))
1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1110 VT, &Ops[0], Ops.size());
1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1115 "Unknown struct or array constant!");
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1119 unsigned NumElts = ValueVTs.size();
1121 return SDValue(); // empty struct
1122 SmallVector<SDValue, 4> Constants(NumElts);
1123 for (unsigned i = 0; i != NumElts; ++i) {
1124 EVT EltVT = ValueVTs[i];
1125 if (isa<UndefValue>(C))
1126 Constants[i] = DAG.getUNDEF(EltVT);
1127 else if (EltVT.isFloatingPoint())
1128 Constants[i] = DAG.getConstantFP(0, EltVT);
1130 Constants[i] = DAG.getConstant(0, EltVT);
1133 return DAG.getMergeValues(&Constants[0], NumElts,
1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1138 return DAG.getBlockAddress(BA, VT);
1140 VectorType *VecTy = cast<VectorType>(V->getType());
1141 unsigned NumElements = VecTy->getNumElements();
1143 // Now that we know the number and type of the elements, get that number of
1144 // elements into the Ops array based on what kind of constant it is.
1145 SmallVector<SDValue, 16> Ops;
1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1147 for (unsigned i = 0; i != NumElements; ++i)
1148 Ops.push_back(getValue(CV->getOperand(i)));
1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1151 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1154 if (EltVT.isFloatingPoint())
1155 Op = DAG.getConstantFP(0, EltVT);
1157 Op = DAG.getConstant(0, EltVT);
1158 Ops.assign(NumElements, Op);
1161 // Create a BUILD_VECTOR node.
1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1163 VT, &Ops[0], Ops.size());
1166 // If this is a static alloca, generate it as the frameindex instead of
1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1169 DenseMap<const AllocaInst*, int>::iterator SI =
1170 FuncInfo.StaticAllocaMap.find(AI);
1171 if (SI != FuncInfo.StaticAllocaMap.end())
1172 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1175 // If this is an instruction which fast-isel has deferred, select it now.
1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1178 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1179 SDValue Chain = DAG.getEntryNode();
1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1183 llvm_unreachable("Can't get register for value!");
1186 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1187 const TargetLowering *TLI = TM.getTargetLowering();
1188 SDValue Chain = getControlRoot();
1189 SmallVector<ISD::OutputArg, 8> Outs;
1190 SmallVector<SDValue, 8> OutVals;
1192 if (!FuncInfo.CanLowerReturn) {
1193 unsigned DemoteReg = FuncInfo.DemoteRegister;
1194 const Function *F = I.getParent()->getParent();
1196 // Emit a store of the return value through the virtual register.
1197 // Leave Outs empty so that LowerReturn won't try to load return
1198 // registers the usual way.
1199 SmallVector<EVT, 1> PtrValueVTs;
1200 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1203 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1204 SDValue RetOp = getValue(I.getOperand(0));
1206 SmallVector<EVT, 4> ValueVTs;
1207 SmallVector<uint64_t, 4> Offsets;
1208 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1209 unsigned NumValues = ValueVTs.size();
1211 SmallVector<SDValue, 4> Chains(NumValues);
1212 for (unsigned i = 0; i != NumValues; ++i) {
1213 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1214 RetPtr.getValueType(), RetPtr,
1215 DAG.getIntPtrConstant(Offsets[i]));
1217 DAG.getStore(Chain, getCurSDLoc(),
1218 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1219 // FIXME: better loc info would be nice.
1220 Add, MachinePointerInfo(), false, false, 0);
1223 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1224 MVT::Other, &Chains[0], NumValues);
1225 } else if (I.getNumOperands() != 0) {
1226 SmallVector<EVT, 4> ValueVTs;
1227 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1228 unsigned NumValues = ValueVTs.size();
1230 SDValue RetOp = getValue(I.getOperand(0));
1231 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1232 EVT VT = ValueVTs[j];
1234 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1236 const Function *F = I.getParent()->getParent();
1237 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1239 ExtendKind = ISD::SIGN_EXTEND;
1240 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1242 ExtendKind = ISD::ZERO_EXTEND;
1244 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1245 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1247 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1248 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1249 SmallVector<SDValue, 4> Parts(NumParts);
1250 getCopyToParts(DAG, getCurSDLoc(),
1251 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1252 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1254 // 'inreg' on function refers to return value
1255 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1256 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 // Propagate extension type if any
1261 if (ExtendKind == ISD::SIGN_EXTEND)
1263 else if (ExtendKind == ISD::ZERO_EXTEND)
1266 for (unsigned i = 0; i < NumParts; ++i) {
1267 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1268 /*isfixed=*/true, 0, 0));
1269 OutVals.push_back(Parts[i]);
1275 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1276 CallingConv::ID CallConv =
1277 DAG.getMachineFunction().getFunction()->getCallingConv();
1278 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1279 Outs, OutVals, getCurSDLoc(),
1282 // Verify that the target's LowerReturn behaved as expected.
1283 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1284 "LowerReturn didn't return a valid chain!");
1286 // Update the DAG with the new chain value resulting from return lowering.
1290 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1291 /// created for it, emit nodes to copy the value into the virtual
1293 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1295 if (V->getType()->isEmptyTy())
1298 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1299 if (VMI != FuncInfo.ValueMap.end()) {
1300 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1301 CopyValueToVirtualRegister(V, VMI->second);
1305 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1306 /// the current basic block, add it to ValueMap now so that we'll get a
1308 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1309 // No need to export constants.
1310 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1312 // Already exported?
1313 if (FuncInfo.isExportedInst(V)) return;
1315 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1316 CopyValueToVirtualRegister(V, Reg);
1319 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1320 const BasicBlock *FromBB) {
1321 // The operands of the setcc have to be in this block. We don't know
1322 // how to export them from some other block.
1323 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1324 // Can export from current BB.
1325 if (VI->getParent() == FromBB)
1328 // Is already exported, noop.
1329 return FuncInfo.isExportedInst(V);
1332 // If this is an argument, we can export it if the BB is the entry block or
1333 // if it is already exported.
1334 if (isa<Argument>(V)) {
1335 if (FromBB == &FromBB->getParent()->getEntryBlock())
1338 // Otherwise, can only export this if it is already exported.
1339 return FuncInfo.isExportedInst(V);
1342 // Otherwise, constants can always be exported.
1346 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1347 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1348 const MachineBasicBlock *Dst) const {
1349 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1352 const BasicBlock *SrcBB = Src->getBasicBlock();
1353 const BasicBlock *DstBB = Dst->getBasicBlock();
1354 return BPI->getEdgeWeight(SrcBB, DstBB);
1357 void SelectionDAGBuilder::
1358 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1359 uint32_t Weight /* = 0 */) {
1361 Weight = getEdgeWeight(Src, Dst);
1362 Src->addSuccessor(Dst, Weight);
1366 static bool InBlock(const Value *V, const BasicBlock *BB) {
1367 if (const Instruction *I = dyn_cast<Instruction>(V))
1368 return I->getParent() == BB;
1372 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1373 /// This function emits a branch and is used at the leaves of an OR or an
1374 /// AND operator tree.
1377 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1378 MachineBasicBlock *TBB,
1379 MachineBasicBlock *FBB,
1380 MachineBasicBlock *CurBB,
1381 MachineBasicBlock *SwitchBB) {
1382 const BasicBlock *BB = CurBB->getBasicBlock();
1384 // If the leaf of the tree is a comparison, merge the condition into
1386 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1387 // The operands of the cmp have to be in this block. We don't know
1388 // how to export them from some other block. If this is the first block
1389 // of the sequence, no exporting is needed.
1390 if (CurBB == SwitchBB ||
1391 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1392 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1393 ISD::CondCode Condition;
1394 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1395 Condition = getICmpCondCode(IC->getPredicate());
1396 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1397 Condition = getFCmpCondCode(FC->getPredicate());
1398 if (TM.Options.NoNaNsFPMath)
1399 Condition = getFCmpCodeWithoutNaN(Condition);
1401 Condition = ISD::SETEQ; // silence warning.
1402 llvm_unreachable("Unknown compare instruction");
1405 CaseBlock CB(Condition, BOp->getOperand(0),
1406 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1407 SwitchCases.push_back(CB);
1412 // Create a CaseBlock record representing this branch.
1413 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1414 NULL, TBB, FBB, CurBB);
1415 SwitchCases.push_back(CB);
1418 /// FindMergedConditions - If Cond is an expression like
1419 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1420 MachineBasicBlock *TBB,
1421 MachineBasicBlock *FBB,
1422 MachineBasicBlock *CurBB,
1423 MachineBasicBlock *SwitchBB,
1425 // If this node is not part of the or/and tree, emit it as a branch.
1426 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1427 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1428 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1429 BOp->getParent() != CurBB->getBasicBlock() ||
1430 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1431 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1432 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1436 // Create TmpBB after CurBB.
1437 MachineFunction::iterator BBI = CurBB;
1438 MachineFunction &MF = DAG.getMachineFunction();
1439 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1440 CurBB->getParent()->insert(++BBI, TmpBB);
1442 if (Opc == Instruction::Or) {
1443 // Codegen X | Y as:
1451 // Emit the LHS condition.
1452 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1454 // Emit the RHS condition into TmpBB.
1455 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1457 assert(Opc == Instruction::And && "Unknown merge op!");
1458 // Codegen X & Y as:
1465 // This requires creation of TmpBB after CurBB.
1467 // Emit the LHS condition.
1468 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1470 // Emit the RHS condition into TmpBB.
1471 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1475 /// If the set of cases should be emitted as a series of branches, return true.
1476 /// If we should emit this as a bunch of and/or'd together conditions, return
1479 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1480 if (Cases.size() != 2) return true;
1482 // If this is two comparisons of the same values or'd or and'd together, they
1483 // will get folded into a single comparison, so don't emit two blocks.
1484 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1485 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1486 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1487 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1491 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1492 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1493 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1494 Cases[0].CC == Cases[1].CC &&
1495 isa<Constant>(Cases[0].CmpRHS) &&
1496 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1497 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1499 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1506 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1507 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1509 // Update machine-CFG edges.
1510 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1512 // Figure out which block is immediately after the current one.
1513 MachineBasicBlock *NextBlock = 0;
1514 MachineFunction::iterator BBI = BrMBB;
1515 if (++BBI != FuncInfo.MF->end())
1518 if (I.isUnconditional()) {
1519 // Update machine-CFG edges.
1520 BrMBB->addSuccessor(Succ0MBB);
1522 // If this is not a fall-through branch, emit the branch.
1523 if (Succ0MBB != NextBlock)
1524 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1525 MVT::Other, getControlRoot(),
1526 DAG.getBasicBlock(Succ0MBB)));
1531 // If this condition is one of the special cases we handle, do special stuff
1533 const Value *CondVal = I.getCondition();
1534 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1536 // If this is a series of conditions that are or'd or and'd together, emit
1537 // this as a sequence of branches instead of setcc's with and/or operations.
1538 // As long as jumps are not expensive, this should improve performance.
1539 // For example, instead of something like:
1552 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1553 if (!TM.getTargetLowering()->isJumpExpensive() &&
1555 (BOp->getOpcode() == Instruction::And ||
1556 BOp->getOpcode() == Instruction::Or)) {
1557 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1559 // If the compares in later blocks need to use values not currently
1560 // exported from this block, export them now. This block should always
1561 // be the first entry.
1562 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1564 // Allow some cases to be rejected.
1565 if (ShouldEmitAsBranches(SwitchCases)) {
1566 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1567 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1568 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1571 // Emit the branch for this block.
1572 visitSwitchCase(SwitchCases[0], BrMBB);
1573 SwitchCases.erase(SwitchCases.begin());
1577 // Okay, we decided not to do this, remove any inserted MBB's and clear
1579 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1580 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1582 SwitchCases.clear();
1586 // Create a CaseBlock record representing this branch.
1587 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1588 NULL, Succ0MBB, Succ1MBB, BrMBB);
1590 // Use visitSwitchCase to actually insert the fast branch sequence for this
1592 visitSwitchCase(CB, BrMBB);
1595 /// visitSwitchCase - Emits the necessary code to represent a single node in
1596 /// the binary search tree resulting from lowering a switch instruction.
1597 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1598 MachineBasicBlock *SwitchBB) {
1600 SDValue CondLHS = getValue(CB.CmpLHS);
1601 SDLoc dl = getCurSDLoc();
1603 // Build the setcc now.
1604 if (CB.CmpMHS == NULL) {
1605 // Fold "(X == true)" to X and "(X == false)" to !X to
1606 // handle common cases produced by branch lowering.
1607 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1608 CB.CC == ISD::SETEQ)
1610 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1611 CB.CC == ISD::SETEQ) {
1612 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1613 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1615 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1617 assert(CB.CC == ISD::SETCC_INVALID &&
1618 "Condition is undefined for to-the-range belonging check.");
1620 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1621 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1623 SDValue CmpOp = getValue(CB.CmpMHS);
1624 EVT VT = CmpOp.getValueType();
1626 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1627 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1630 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1631 VT, CmpOp, DAG.getConstant(Low, VT));
1632 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1633 DAG.getConstant(High-Low, VT), ISD::SETULE);
1637 // Update successor info
1638 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1639 // TrueBB and FalseBB are always different unless the incoming IR is
1640 // degenerate. This only happens when running llc on weird IR.
1641 if (CB.TrueBB != CB.FalseBB)
1642 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1644 // Set NextBlock to be the MBB immediately after the current one, if any.
1645 // This is used to avoid emitting unnecessary branches to the next block.
1646 MachineBasicBlock *NextBlock = 0;
1647 MachineFunction::iterator BBI = SwitchBB;
1648 if (++BBI != FuncInfo.MF->end())
1651 // If the lhs block is the next block, invert the condition so that we can
1652 // fall through to the lhs instead of the rhs block.
1653 if (CB.TrueBB == NextBlock) {
1654 std::swap(CB.TrueBB, CB.FalseBB);
1655 SDValue True = DAG.getConstant(1, Cond.getValueType());
1656 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1659 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1660 MVT::Other, getControlRoot(), Cond,
1661 DAG.getBasicBlock(CB.TrueBB));
1663 // Insert the false branch. Do this even if it's a fall through branch,
1664 // this makes it easier to do DAG optimizations which require inverting
1665 // the branch condition.
1666 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1667 DAG.getBasicBlock(CB.FalseBB));
1669 DAG.setRoot(BrCond);
1672 /// visitJumpTable - Emit JumpTable node in the current MBB
1673 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1674 // Emit the code for the jump table
1675 assert(JT.Reg != -1U && "Should lower JT Header first!");
1676 EVT PTy = TM.getTargetLowering()->getPointerTy();
1677 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1679 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1680 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1681 MVT::Other, Index.getValue(1),
1683 DAG.setRoot(BrJumpTable);
1686 /// visitJumpTableHeader - This function emits necessary code to produce index
1687 /// in the JumpTable from switch case.
1688 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1689 JumpTableHeader &JTH,
1690 MachineBasicBlock *SwitchBB) {
1691 // Subtract the lowest switch case value from the value being switched on and
1692 // conditional branch to default mbb if the result is greater than the
1693 // difference between smallest and largest cases.
1694 SDValue SwitchOp = getValue(JTH.SValue);
1695 EVT VT = SwitchOp.getValueType();
1696 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1697 DAG.getConstant(JTH.First, VT));
1699 // The SDNode we just created, which holds the value being switched on minus
1700 // the smallest case value, needs to be copied to a virtual register so it
1701 // can be used as an index into the jump table in a subsequent basic block.
1702 // This value may be smaller or larger than the target's pointer type, and
1703 // therefore require extension or truncating.
1704 const TargetLowering *TLI = TM.getTargetLowering();
1705 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1707 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1708 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1709 JumpTableReg, SwitchOp);
1710 JT.Reg = JumpTableReg;
1712 // Emit the range check for the jump table, and branch to the default block
1713 // for the switch statement if the value being switched on exceeds the largest
1714 // case in the switch.
1715 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1716 TLI->getSetCCResultType(*DAG.getContext(),
1717 Sub.getValueType()),
1719 DAG.getConstant(JTH.Last - JTH.First,VT),
1722 // Set NextBlock to be the MBB immediately after the current one, if any.
1723 // This is used to avoid emitting unnecessary branches to the next block.
1724 MachineBasicBlock *NextBlock = 0;
1725 MachineFunction::iterator BBI = SwitchBB;
1727 if (++BBI != FuncInfo.MF->end())
1730 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1731 MVT::Other, CopyTo, CMP,
1732 DAG.getBasicBlock(JT.Default));
1734 if (JT.MBB != NextBlock)
1735 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1736 DAG.getBasicBlock(JT.MBB));
1738 DAG.setRoot(BrCond);
1741 /// visitBitTestHeader - This function emits necessary code to produce value
1742 /// suitable for "bit tests"
1743 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1744 MachineBasicBlock *SwitchBB) {
1745 // Subtract the minimum value
1746 SDValue SwitchOp = getValue(B.SValue);
1747 EVT VT = SwitchOp.getValueType();
1748 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1749 DAG.getConstant(B.First, VT));
1752 const TargetLowering *TLI = TM.getTargetLowering();
1753 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1754 TLI->getSetCCResultType(*DAG.getContext(),
1755 Sub.getValueType()),
1756 Sub, DAG.getConstant(B.Range, VT),
1759 // Determine the type of the test operands.
1760 bool UsePtrType = false;
1761 if (!TLI->isTypeLegal(VT))
1764 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1765 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1766 // Switch table case range are encoded into series of masks.
1767 // Just use pointer type, it's guaranteed to fit.
1773 VT = TLI->getPointerTy();
1774 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1777 B.RegVT = VT.getSimpleVT();
1778 B.Reg = FuncInfo.CreateReg(B.RegVT);
1779 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1782 // Set NextBlock to be the MBB immediately after the current one, if any.
1783 // This is used to avoid emitting unnecessary branches to the next block.
1784 MachineBasicBlock *NextBlock = 0;
1785 MachineFunction::iterator BBI = SwitchBB;
1786 if (++BBI != FuncInfo.MF->end())
1789 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1791 addSuccessorWithWeight(SwitchBB, B.Default);
1792 addSuccessorWithWeight(SwitchBB, MBB);
1794 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1795 MVT::Other, CopyTo, RangeCmp,
1796 DAG.getBasicBlock(B.Default));
1798 if (MBB != NextBlock)
1799 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1800 DAG.getBasicBlock(MBB));
1802 DAG.setRoot(BrRange);
1805 /// visitBitTestCase - this function produces one "bit test"
1806 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1807 MachineBasicBlock* NextMBB,
1808 uint32_t BranchWeightToNext,
1811 MachineBasicBlock *SwitchBB) {
1813 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1816 unsigned PopCount = CountPopulation_64(B.Mask);
1817 const TargetLowering *TLI = TM.getTargetLowering();
1818 if (PopCount == 1) {
1819 // Testing for a single bit; just compare the shift count with what it
1820 // would need to be to shift a 1 bit in that position.
1821 Cmp = DAG.getSetCC(getCurSDLoc(),
1822 TLI->getSetCCResultType(*DAG.getContext(), VT),
1824 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1826 } else if (PopCount == BB.Range) {
1827 // There is only one zero bit in the range, test for it directly.
1828 Cmp = DAG.getSetCC(getCurSDLoc(),
1829 TLI->getSetCCResultType(*DAG.getContext(), VT),
1831 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1834 // Make desired shift
1835 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1836 DAG.getConstant(1, VT), ShiftOp);
1838 // Emit bit tests and jumps
1839 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1840 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1841 Cmp = DAG.getSetCC(getCurSDLoc(),
1842 TLI->getSetCCResultType(*DAG.getContext(), VT),
1843 AndOp, DAG.getConstant(0, VT),
1847 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1848 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1849 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1850 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1852 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1853 MVT::Other, getControlRoot(),
1854 Cmp, DAG.getBasicBlock(B.TargetBB));
1856 // Set NextBlock to be the MBB immediately after the current one, if any.
1857 // This is used to avoid emitting unnecessary branches to the next block.
1858 MachineBasicBlock *NextBlock = 0;
1859 MachineFunction::iterator BBI = SwitchBB;
1860 if (++BBI != FuncInfo.MF->end())
1863 if (NextMBB != NextBlock)
1864 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1865 DAG.getBasicBlock(NextMBB));
1870 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1871 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1873 // Retrieve successors.
1874 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1875 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1877 const Value *Callee(I.getCalledValue());
1878 const Function *Fn = dyn_cast<Function>(Callee);
1879 if (isa<InlineAsm>(Callee))
1881 else if (Fn && Fn->isIntrinsic()) {
1882 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1883 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1885 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1887 // If the value of the invoke is used outside of its defining block, make it
1888 // available as a virtual register.
1889 CopyToExportRegsIfNeeded(&I);
1891 // Update successor info
1892 addSuccessorWithWeight(InvokeMBB, Return);
1893 addSuccessorWithWeight(InvokeMBB, LandingPad);
1895 // Drop into normal successor.
1896 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1897 MVT::Other, getControlRoot(),
1898 DAG.getBasicBlock(Return)));
1901 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1902 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1905 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1906 assert(FuncInfo.MBB->isLandingPad() &&
1907 "Call to landingpad not in landing pad!");
1909 MachineBasicBlock *MBB = FuncInfo.MBB;
1910 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1911 AddLandingPadInfo(LP, MMI, MBB);
1913 // If there aren't registers to copy the values into (e.g., during SjLj
1914 // exceptions), then don't bother to create these DAG nodes.
1915 const TargetLowering *TLI = TM.getTargetLowering();
1916 if (TLI->getExceptionPointerRegister() == 0 &&
1917 TLI->getExceptionSelectorRegister() == 0)
1920 SmallVector<EVT, 2> ValueVTs;
1921 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
1922 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
1924 // Get the two live-in registers as SDValues. The physregs have already been
1925 // copied into virtual registers.
1927 Ops[0] = DAG.getZExtOrTrunc(
1928 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1929 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
1930 getCurSDLoc(), ValueVTs[0]);
1931 Ops[1] = DAG.getZExtOrTrunc(
1932 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1933 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
1934 getCurSDLoc(), ValueVTs[1]);
1937 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
1938 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1943 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1944 /// small case ranges).
1945 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1946 CaseRecVector& WorkList,
1948 MachineBasicBlock *Default,
1949 MachineBasicBlock *SwitchBB) {
1950 // Size is the number of Cases represented by this range.
1951 size_t Size = CR.Range.second - CR.Range.first;
1955 // Get the MachineFunction which holds the current MBB. This is used when
1956 // inserting any additional MBBs necessary to represent the switch.
1957 MachineFunction *CurMF = FuncInfo.MF;
1959 // Figure out which block is immediately after the current one.
1960 MachineBasicBlock *NextBlock = 0;
1961 MachineFunction::iterator BBI = CR.CaseBB;
1963 if (++BBI != FuncInfo.MF->end())
1966 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1967 // If any two of the cases has the same destination, and if one value
1968 // is the same as the other, but has one bit unset that the other has set,
1969 // use bit manipulation to do two compares at once. For example:
1970 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1971 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1972 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1973 if (Size == 2 && CR.CaseBB == SwitchBB) {
1974 Case &Small = *CR.Range.first;
1975 Case &Big = *(CR.Range.second-1);
1977 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1978 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1979 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1981 // Check that there is only one bit different.
1982 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1983 (SmallValue | BigValue) == BigValue) {
1984 // Isolate the common bit.
1985 APInt CommonBit = BigValue & ~SmallValue;
1986 assert((SmallValue | CommonBit) == BigValue &&
1987 CommonBit.countPopulation() == 1 && "Not a common bit?");
1989 SDValue CondLHS = getValue(SV);
1990 EVT VT = CondLHS.getValueType();
1991 SDLoc DL = getCurSDLoc();
1993 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1994 DAG.getConstant(CommonBit, VT));
1995 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1996 Or, DAG.getConstant(BigValue, VT),
1999 // Update successor info.
2000 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2001 addSuccessorWithWeight(SwitchBB, Small.BB,
2002 Small.ExtraWeight + Big.ExtraWeight);
2003 addSuccessorWithWeight(SwitchBB, Default,
2004 // The default destination is the first successor in IR.
2005 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2007 // Insert the true branch.
2008 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2009 getControlRoot(), Cond,
2010 DAG.getBasicBlock(Small.BB));
2012 // Insert the false branch.
2013 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2014 DAG.getBasicBlock(Default));
2016 DAG.setRoot(BrCond);
2022 // Order cases by weight so the most likely case will be checked first.
2023 uint32_t UnhandledWeights = 0;
2025 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2026 uint32_t IWeight = I->ExtraWeight;
2027 UnhandledWeights += IWeight;
2028 for (CaseItr J = CR.Range.first; J < I; ++J) {
2029 uint32_t JWeight = J->ExtraWeight;
2030 if (IWeight > JWeight)
2035 // Rearrange the case blocks so that the last one falls through if possible.
2036 Case &BackCase = *(CR.Range.second-1);
2038 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2039 // The last case block won't fall through into 'NextBlock' if we emit the
2040 // branches in this order. See if rearranging a case value would help.
2041 // We start at the bottom as it's the case with the least weight.
2042 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2043 if (I->BB == NextBlock) {
2044 std::swap(*I, BackCase);
2050 // Create a CaseBlock record representing a conditional branch to
2051 // the Case's target mbb if the value being switched on SV is equal
2053 MachineBasicBlock *CurBlock = CR.CaseBB;
2054 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2055 MachineBasicBlock *FallThrough;
2057 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2058 CurMF->insert(BBI, FallThrough);
2060 // Put SV in a virtual register to make it available from the new blocks.
2061 ExportFromCurrentBlock(SV);
2063 // If the last case doesn't match, go to the default block.
2064 FallThrough = Default;
2067 const Value *RHS, *LHS, *MHS;
2069 if (I->High == I->Low) {
2070 // This is just small small case range :) containing exactly 1 case
2072 LHS = SV; RHS = I->High; MHS = NULL;
2074 CC = ISD::SETCC_INVALID;
2075 LHS = I->Low; MHS = SV; RHS = I->High;
2078 // The false weight should be sum of all un-handled cases.
2079 UnhandledWeights -= I->ExtraWeight;
2080 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2082 /* trueweight */ I->ExtraWeight,
2083 /* falseweight */ UnhandledWeights);
2085 // If emitting the first comparison, just call visitSwitchCase to emit the
2086 // code into the current block. Otherwise, push the CaseBlock onto the
2087 // vector to be later processed by SDISel, and insert the node's MBB
2088 // before the next MBB.
2089 if (CurBlock == SwitchBB)
2090 visitSwitchCase(CB, SwitchBB);
2092 SwitchCases.push_back(CB);
2094 CurBlock = FallThrough;
2100 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2101 return TLI.supportJumpTables() &&
2102 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2103 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2106 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2107 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2108 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2109 return (LastExt - FirstExt + 1ULL);
2112 /// handleJTSwitchCase - Emit jumptable for current switch case range
2113 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2114 CaseRecVector &WorkList,
2116 MachineBasicBlock *Default,
2117 MachineBasicBlock *SwitchBB) {
2118 Case& FrontCase = *CR.Range.first;
2119 Case& BackCase = *(CR.Range.second-1);
2121 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2122 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2124 APInt TSize(First.getBitWidth(), 0);
2125 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2128 const TargetLowering *TLI = TM.getTargetLowering();
2129 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2132 APInt Range = ComputeRange(First, Last);
2133 // The density is TSize / Range. Require at least 40%.
2134 // It should not be possible for IntTSize to saturate for sane code, but make
2135 // sure we handle Range saturation correctly.
2136 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2137 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2138 if (IntTSize * 10 < IntRange * 4)
2141 DEBUG(dbgs() << "Lowering jump table\n"
2142 << "First entry: " << First << ". Last entry: " << Last << '\n'
2143 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2145 // Get the MachineFunction which holds the current MBB. This is used when
2146 // inserting any additional MBBs necessary to represent the switch.
2147 MachineFunction *CurMF = FuncInfo.MF;
2149 // Figure out which block is immediately after the current one.
2150 MachineFunction::iterator BBI = CR.CaseBB;
2153 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2155 // Create a new basic block to hold the code for loading the address
2156 // of the jump table, and jumping to it. Update successor information;
2157 // we will either branch to the default case for the switch, or the jump
2159 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2160 CurMF->insert(BBI, JumpTableBB);
2162 addSuccessorWithWeight(CR.CaseBB, Default);
2163 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2165 // Build a vector of destination BBs, corresponding to each target
2166 // of the jump table. If the value of the jump table slot corresponds to
2167 // a case statement, push the case's BB onto the vector, otherwise, push
2169 std::vector<MachineBasicBlock*> DestBBs;
2171 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2172 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2173 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2175 if (Low.ule(TEI) && TEI.ule(High)) {
2176 DestBBs.push_back(I->BB);
2180 DestBBs.push_back(Default);
2184 // Calculate weight for each unique destination in CR.
2185 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2187 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2188 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2189 DestWeights.find(I->BB);
2190 if (Itr != DestWeights.end())
2191 Itr->second += I->ExtraWeight;
2193 DestWeights[I->BB] = I->ExtraWeight;
2196 // Update successor info. Add one edge to each unique successor.
2197 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2198 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2199 E = DestBBs.end(); I != E; ++I) {
2200 if (!SuccsHandled[(*I)->getNumber()]) {
2201 SuccsHandled[(*I)->getNumber()] = true;
2202 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2203 DestWeights.find(*I);
2204 addSuccessorWithWeight(JumpTableBB, *I,
2205 Itr != DestWeights.end() ? Itr->second : 0);
2209 // Create a jump table index for this jump table.
2210 unsigned JTEncoding = TLI->getJumpTableEncoding();
2211 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2212 ->createJumpTableIndex(DestBBs);
2214 // Set the jump table information so that we can codegen it as a second
2215 // MachineBasicBlock
2216 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2217 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2218 if (CR.CaseBB == SwitchBB)
2219 visitJumpTableHeader(JT, JTH, SwitchBB);
2221 JTCases.push_back(JumpTableBlock(JTH, JT));
2225 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2227 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2228 CaseRecVector& WorkList,
2230 MachineBasicBlock *Default,
2231 MachineBasicBlock *SwitchBB) {
2232 // Get the MachineFunction which holds the current MBB. This is used when
2233 // inserting any additional MBBs necessary to represent the switch.
2234 MachineFunction *CurMF = FuncInfo.MF;
2236 // Figure out which block is immediately after the current one.
2237 MachineFunction::iterator BBI = CR.CaseBB;
2240 Case& FrontCase = *CR.Range.first;
2241 Case& BackCase = *(CR.Range.second-1);
2242 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2244 // Size is the number of Cases represented by this range.
2245 unsigned Size = CR.Range.second - CR.Range.first;
2247 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2248 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2250 CaseItr Pivot = CR.Range.first + Size/2;
2252 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2253 // (heuristically) allow us to emit JumpTable's later.
2254 APInt TSize(First.getBitWidth(), 0);
2255 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2259 APInt LSize = FrontCase.size();
2260 APInt RSize = TSize-LSize;
2261 DEBUG(dbgs() << "Selecting best pivot: \n"
2262 << "First: " << First << ", Last: " << Last <<'\n'
2263 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2264 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2266 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2267 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2268 APInt Range = ComputeRange(LEnd, RBegin);
2269 assert((Range - 2ULL).isNonNegative() &&
2270 "Invalid case distance");
2271 // Use volatile double here to avoid excess precision issues on some hosts,
2272 // e.g. that use 80-bit X87 registers.
2273 volatile double LDensity =
2274 (double)LSize.roundToDouble() /
2275 (LEnd - First + 1ULL).roundToDouble();
2276 volatile double RDensity =
2277 (double)RSize.roundToDouble() /
2278 (Last - RBegin + 1ULL).roundToDouble();
2279 double Metric = Range.logBase2()*(LDensity+RDensity);
2280 // Should always split in some non-trivial place
2281 DEBUG(dbgs() <<"=>Step\n"
2282 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2283 << "LDensity: " << LDensity
2284 << ", RDensity: " << RDensity << '\n'
2285 << "Metric: " << Metric << '\n');
2286 if (FMetric < Metric) {
2289 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2296 const TargetLowering *TLI = TM.getTargetLowering();
2297 if (areJTsAllowed(*TLI)) {
2298 // If our case is dense we *really* should handle it earlier!
2299 assert((FMetric > 0) && "Should handle dense range earlier!");
2301 Pivot = CR.Range.first + Size/2;
2304 CaseRange LHSR(CR.Range.first, Pivot);
2305 CaseRange RHSR(Pivot, CR.Range.second);
2306 const Constant *C = Pivot->Low;
2307 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2309 // We know that we branch to the LHS if the Value being switched on is
2310 // less than the Pivot value, C. We use this to optimize our binary
2311 // tree a bit, by recognizing that if SV is greater than or equal to the
2312 // LHS's Case Value, and that Case Value is exactly one less than the
2313 // Pivot's Value, then we can branch directly to the LHS's Target,
2314 // rather than creating a leaf node for it.
2315 if ((LHSR.second - LHSR.first) == 1 &&
2316 LHSR.first->High == CR.GE &&
2317 cast<ConstantInt>(C)->getValue() ==
2318 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2319 TrueBB = LHSR.first->BB;
2321 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2322 CurMF->insert(BBI, TrueBB);
2323 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2325 // Put SV in a virtual register to make it available from the new blocks.
2326 ExportFromCurrentBlock(SV);
2329 // Similar to the optimization above, if the Value being switched on is
2330 // known to be less than the Constant CR.LT, and the current Case Value
2331 // is CR.LT - 1, then we can branch directly to the target block for
2332 // the current Case Value, rather than emitting a RHS leaf node for it.
2333 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2334 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2335 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2336 FalseBB = RHSR.first->BB;
2338 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2339 CurMF->insert(BBI, FalseBB);
2340 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2342 // Put SV in a virtual register to make it available from the new blocks.
2343 ExportFromCurrentBlock(SV);
2346 // Create a CaseBlock record representing a conditional branch to
2347 // the LHS node if the value being switched on SV is less than C.
2348 // Otherwise, branch to LHS.
2349 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2351 if (CR.CaseBB == SwitchBB)
2352 visitSwitchCase(CB, SwitchBB);
2354 SwitchCases.push_back(CB);
2359 /// handleBitTestsSwitchCase - if current case range has few destination and
2360 /// range span less, than machine word bitwidth, encode case range into series
2361 /// of masks and emit bit tests with these masks.
2362 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2363 CaseRecVector& WorkList,
2365 MachineBasicBlock* Default,
2366 MachineBasicBlock *SwitchBB){
2367 const TargetLowering *TLI = TM.getTargetLowering();
2368 EVT PTy = TLI->getPointerTy();
2369 unsigned IntPtrBits = PTy.getSizeInBits();
2371 Case& FrontCase = *CR.Range.first;
2372 Case& BackCase = *(CR.Range.second-1);
2374 // Get the MachineFunction which holds the current MBB. This is used when
2375 // inserting any additional MBBs necessary to represent the switch.
2376 MachineFunction *CurMF = FuncInfo.MF;
2378 // If target does not have legal shift left, do not emit bit tests at all.
2379 if (!TLI->isOperationLegal(ISD::SHL, TLI->getPointerTy()))
2383 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2385 // Single case counts one, case range - two.
2386 numCmps += (I->Low == I->High ? 1 : 2);
2389 // Count unique destinations
2390 SmallSet<MachineBasicBlock*, 4> Dests;
2391 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2392 Dests.insert(I->BB);
2393 if (Dests.size() > 3)
2394 // Don't bother the code below, if there are too much unique destinations
2397 DEBUG(dbgs() << "Total number of unique destinations: "
2398 << Dests.size() << '\n'
2399 << "Total number of comparisons: " << numCmps << '\n');
2401 // Compute span of values.
2402 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2403 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2404 APInt cmpRange = maxValue - minValue;
2406 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2407 << "Low bound: " << minValue << '\n'
2408 << "High bound: " << maxValue << '\n');
2410 if (cmpRange.uge(IntPtrBits) ||
2411 (!(Dests.size() == 1 && numCmps >= 3) &&
2412 !(Dests.size() == 2 && numCmps >= 5) &&
2413 !(Dests.size() >= 3 && numCmps >= 6)))
2416 DEBUG(dbgs() << "Emitting bit tests\n");
2417 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2419 // Optimize the case where all the case values fit in a
2420 // word without having to subtract minValue. In this case,
2421 // we can optimize away the subtraction.
2422 if (maxValue.ult(IntPtrBits)) {
2423 cmpRange = maxValue;
2425 lowBound = minValue;
2428 CaseBitsVector CasesBits;
2429 unsigned i, count = 0;
2431 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2432 MachineBasicBlock* Dest = I->BB;
2433 for (i = 0; i < count; ++i)
2434 if (Dest == CasesBits[i].BB)
2438 assert((count < 3) && "Too much destinations to test!");
2439 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2443 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2444 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2446 uint64_t lo = (lowValue - lowBound).getZExtValue();
2447 uint64_t hi = (highValue - lowBound).getZExtValue();
2448 CasesBits[i].ExtraWeight += I->ExtraWeight;
2450 for (uint64_t j = lo; j <= hi; j++) {
2451 CasesBits[i].Mask |= 1ULL << j;
2452 CasesBits[i].Bits++;
2456 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2460 // Figure out which block is immediately after the current one.
2461 MachineFunction::iterator BBI = CR.CaseBB;
2464 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2466 DEBUG(dbgs() << "Cases:\n");
2467 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2468 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2469 << ", Bits: " << CasesBits[i].Bits
2470 << ", BB: " << CasesBits[i].BB << '\n');
2472 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2473 CurMF->insert(BBI, CaseBB);
2474 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2476 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2478 // Put SV in a virtual register to make it available from the new blocks.
2479 ExportFromCurrentBlock(SV);
2482 BitTestBlock BTB(lowBound, cmpRange, SV,
2483 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2484 CR.CaseBB, Default, BTC);
2486 if (CR.CaseBB == SwitchBB)
2487 visitBitTestHeader(BTB, SwitchBB);
2489 BitTestCases.push_back(BTB);
2494 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2495 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2496 const SwitchInst& SI) {
2498 /// Use a shorter form of declaration, and also
2499 /// show the we want to use CRSBuilder as Clusterifier.
2500 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2502 Clusterifier TheClusterifier;
2504 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2505 // Start with "simple" cases
2506 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2508 const BasicBlock *SuccBB = i.getCaseSuccessor();
2509 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2511 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2512 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2515 TheClusterifier.optimize();
2518 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2519 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2520 Clusterifier::Cluster &C = *i;
2521 // Update edge weight for the cluster.
2522 unsigned W = C.first.Weight;
2524 // FIXME: Currently work with ConstantInt based numbers.
2525 // Changing it to APInt based is a pretty heavy for this commit.
2526 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2527 C.first.getHigh().toConstantInt(), C.second, W));
2529 if (C.first.getLow() != C.first.getHigh())
2530 // A range counts double, since it requires two compares.
2537 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2538 MachineBasicBlock *Last) {
2540 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2541 if (JTCases[i].first.HeaderBB == First)
2542 JTCases[i].first.HeaderBB = Last;
2544 // Update BitTestCases.
2545 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2546 if (BitTestCases[i].Parent == First)
2547 BitTestCases[i].Parent = Last;
2550 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2551 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2553 // Figure out which block is immediately after the current one.
2554 MachineBasicBlock *NextBlock = 0;
2555 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2557 // If there is only the default destination, branch to it if it is not the
2558 // next basic block. Otherwise, just fall through.
2559 if (!SI.getNumCases()) {
2560 // Update machine-CFG edges.
2562 // If this is not a fall-through branch, emit the branch.
2563 SwitchMBB->addSuccessor(Default);
2564 if (Default != NextBlock)
2565 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2566 MVT::Other, getControlRoot(),
2567 DAG.getBasicBlock(Default)));
2572 // If there are any non-default case statements, create a vector of Cases
2573 // representing each one, and sort the vector so that we can efficiently
2574 // create a binary search tree from them.
2576 size_t numCmps = Clusterify(Cases, SI);
2577 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2578 << ". Total compares: " << numCmps << '\n');
2581 // Get the Value to be switched on and default basic blocks, which will be
2582 // inserted into CaseBlock records, representing basic blocks in the binary
2584 const Value *SV = SI.getCondition();
2586 // Push the initial CaseRec onto the worklist
2587 CaseRecVector WorkList;
2588 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2589 CaseRange(Cases.begin(),Cases.end())));
2591 while (!WorkList.empty()) {
2592 // Grab a record representing a case range to process off the worklist
2593 CaseRec CR = WorkList.back();
2594 WorkList.pop_back();
2596 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2599 // If the range has few cases (two or less) emit a series of specific
2601 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2604 // If the switch has more than N blocks, and is at least 40% dense, and the
2605 // target supports indirect branches, then emit a jump table rather than
2606 // lowering the switch to a binary tree of conditional branches.
2607 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2608 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2611 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2612 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2613 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2617 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2618 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2620 // Update machine-CFG edges with unique successors.
2621 SmallSet<BasicBlock*, 32> Done;
2622 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2623 BasicBlock *BB = I.getSuccessor(i);
2624 bool Inserted = Done.insert(BB);
2628 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2629 addSuccessorWithWeight(IndirectBrMBB, Succ);
2632 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2633 MVT::Other, getControlRoot(),
2634 getValue(I.getAddress())));
2637 void SelectionDAGBuilder::visitFSub(const User &I) {
2638 // -0.0 - X --> fneg
2639 Type *Ty = I.getType();
2640 if (isa<Constant>(I.getOperand(0)) &&
2641 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2642 SDValue Op2 = getValue(I.getOperand(1));
2643 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2644 Op2.getValueType(), Op2));
2648 visitBinary(I, ISD::FSUB);
2651 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2652 SDValue Op1 = getValue(I.getOperand(0));
2653 SDValue Op2 = getValue(I.getOperand(1));
2654 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2655 Op1.getValueType(), Op1, Op2));
2658 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2659 SDValue Op1 = getValue(I.getOperand(0));
2660 SDValue Op2 = getValue(I.getOperand(1));
2662 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2664 // Coerce the shift amount to the right type if we can.
2665 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2666 unsigned ShiftSize = ShiftTy.getSizeInBits();
2667 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2668 SDLoc DL = getCurSDLoc();
2670 // If the operand is smaller than the shift count type, promote it.
2671 if (ShiftSize > Op2Size)
2672 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2674 // If the operand is larger than the shift count type but the shift
2675 // count type has enough bits to represent any shift value, truncate
2676 // it now. This is a common case and it exposes the truncate to
2677 // optimization early.
2678 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2679 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2680 // Otherwise we'll need to temporarily settle for some other convenient
2681 // type. Type legalization will make adjustments once the shiftee is split.
2683 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2686 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2687 Op1.getValueType(), Op1, Op2));
2690 void SelectionDAGBuilder::visitSDiv(const User &I) {
2691 SDValue Op1 = getValue(I.getOperand(0));
2692 SDValue Op2 = getValue(I.getOperand(1));
2694 // Turn exact SDivs into multiplications.
2695 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2697 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2698 !isa<ConstantSDNode>(Op1) &&
2699 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2700 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2701 getCurSDLoc(), DAG));
2703 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2707 void SelectionDAGBuilder::visitICmp(const User &I) {
2708 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2709 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2710 predicate = IC->getPredicate();
2711 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2712 predicate = ICmpInst::Predicate(IC->getPredicate());
2713 SDValue Op1 = getValue(I.getOperand(0));
2714 SDValue Op2 = getValue(I.getOperand(1));
2715 ISD::CondCode Opcode = getICmpCondCode(predicate);
2717 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2718 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2721 void SelectionDAGBuilder::visitFCmp(const User &I) {
2722 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2723 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2724 predicate = FC->getPredicate();
2725 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2726 predicate = FCmpInst::Predicate(FC->getPredicate());
2727 SDValue Op1 = getValue(I.getOperand(0));
2728 SDValue Op2 = getValue(I.getOperand(1));
2729 ISD::CondCode Condition = getFCmpCondCode(predicate);
2730 if (TM.Options.NoNaNsFPMath)
2731 Condition = getFCmpCodeWithoutNaN(Condition);
2732 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2733 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2736 void SelectionDAGBuilder::visitSelect(const User &I) {
2737 SmallVector<EVT, 4> ValueVTs;
2738 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2739 unsigned NumValues = ValueVTs.size();
2740 if (NumValues == 0) return;
2742 SmallVector<SDValue, 4> Values(NumValues);
2743 SDValue Cond = getValue(I.getOperand(0));
2744 SDValue TrueVal = getValue(I.getOperand(1));
2745 SDValue FalseVal = getValue(I.getOperand(2));
2746 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2747 ISD::VSELECT : ISD::SELECT;
2749 for (unsigned i = 0; i != NumValues; ++i)
2750 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2751 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2753 SDValue(TrueVal.getNode(),
2754 TrueVal.getResNo() + i),
2755 SDValue(FalseVal.getNode(),
2756 FalseVal.getResNo() + i));
2758 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2759 DAG.getVTList(&ValueVTs[0], NumValues),
2760 &Values[0], NumValues));
2763 void SelectionDAGBuilder::visitTrunc(const User &I) {
2764 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2765 SDValue N = getValue(I.getOperand(0));
2766 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2767 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2770 void SelectionDAGBuilder::visitZExt(const User &I) {
2771 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2772 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2773 SDValue N = getValue(I.getOperand(0));
2774 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2775 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2778 void SelectionDAGBuilder::visitSExt(const User &I) {
2779 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2780 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2781 SDValue N = getValue(I.getOperand(0));
2782 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2783 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2786 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2787 // FPTrunc is never a no-op cast, no need to check
2788 SDValue N = getValue(I.getOperand(0));
2789 const TargetLowering *TLI = TM.getTargetLowering();
2790 EVT DestVT = TLI->getValueType(I.getType());
2791 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2793 DAG.getTargetConstant(0, TLI->getPointerTy())));
2796 void SelectionDAGBuilder::visitFPExt(const User &I){
2797 // FPExt is never a no-op cast, no need to check
2798 SDValue N = getValue(I.getOperand(0));
2799 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2800 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2803 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2804 // FPToUI is never a no-op cast, no need to check
2805 SDValue N = getValue(I.getOperand(0));
2806 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2807 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2810 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2811 // FPToSI is never a no-op cast, no need to check
2812 SDValue N = getValue(I.getOperand(0));
2813 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2814 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2817 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2818 // UIToFP is never a no-op cast, no need to check
2819 SDValue N = getValue(I.getOperand(0));
2820 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2821 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2824 void SelectionDAGBuilder::visitSIToFP(const User &I){
2825 // SIToFP is never a no-op cast, no need to check
2826 SDValue N = getValue(I.getOperand(0));
2827 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2828 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2831 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2832 // What to do depends on the size of the integer and the size of the pointer.
2833 // We can either truncate, zero extend, or no-op, accordingly.
2834 SDValue N = getValue(I.getOperand(0));
2835 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2836 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2839 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2840 // What to do depends on the size of the integer and the size of the pointer.
2841 // We can either truncate, zero extend, or no-op, accordingly.
2842 SDValue N = getValue(I.getOperand(0));
2843 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2844 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2847 void SelectionDAGBuilder::visitBitCast(const User &I) {
2848 SDValue N = getValue(I.getOperand(0));
2849 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2851 // BitCast assures us that source and destination are the same size so this is
2852 // either a BITCAST or a no-op.
2853 if (DestVT != N.getValueType())
2854 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2855 DestVT, N)); // convert types.
2857 setValue(&I, N); // noop cast.
2860 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2861 SDValue InVec = getValue(I.getOperand(0));
2862 SDValue InVal = getValue(I.getOperand(1));
2863 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
2864 TM.getTargetLowering()->getPointerTy(),
2865 getValue(I.getOperand(2)));
2866 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2867 TM.getTargetLowering()->getValueType(I.getType()),
2868 InVec, InVal, InIdx));
2871 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2872 SDValue InVec = getValue(I.getOperand(0));
2873 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
2874 TM.getTargetLowering()->getPointerTy(),
2875 getValue(I.getOperand(1)));
2876 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2877 TM.getTargetLowering()->getValueType(I.getType()),
2881 // Utility for visitShuffleVector - Return true if every element in Mask,
2882 // beginning from position Pos and ending in Pos+Size, falls within the
2883 // specified sequential range [L, L+Pos). or is undef.
2884 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2885 unsigned Pos, unsigned Size, int Low) {
2886 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2887 if (Mask[i] >= 0 && Mask[i] != Low)
2892 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2893 SDValue Src1 = getValue(I.getOperand(0));
2894 SDValue Src2 = getValue(I.getOperand(1));
2896 SmallVector<int, 8> Mask;
2897 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2898 unsigned MaskNumElts = Mask.size();
2900 const TargetLowering *TLI = TM.getTargetLowering();
2901 EVT VT = TLI->getValueType(I.getType());
2902 EVT SrcVT = Src1.getValueType();
2903 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2905 if (SrcNumElts == MaskNumElts) {
2906 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2911 // Normalize the shuffle vector since mask and vector length don't match.
2912 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2913 // Mask is longer than the source vectors and is a multiple of the source
2914 // vectors. We can use concatenate vector to make the mask and vectors
2916 if (SrcNumElts*2 == MaskNumElts) {
2917 // First check for Src1 in low and Src2 in high
2918 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2919 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2920 // The shuffle is concatenating two vectors together.
2921 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2925 // Then check for Src2 in low and Src1 in high
2926 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2927 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2928 // The shuffle is concatenating two vectors together.
2929 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2935 // Pad both vectors with undefs to make them the same length as the mask.
2936 unsigned NumConcat = MaskNumElts / SrcNumElts;
2937 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2938 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2939 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2941 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2942 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2946 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2948 &MOps1[0], NumConcat);
2949 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2951 &MOps2[0], NumConcat);
2953 // Readjust mask for new input vector length.
2954 SmallVector<int, 8> MappedOps;
2955 for (unsigned i = 0; i != MaskNumElts; ++i) {
2957 if (Idx >= (int)SrcNumElts)
2958 Idx -= SrcNumElts - MaskNumElts;
2959 MappedOps.push_back(Idx);
2962 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2967 if (SrcNumElts > MaskNumElts) {
2968 // Analyze the access pattern of the vector to see if we can extract
2969 // two subvectors and do the shuffle. The analysis is done by calculating
2970 // the range of elements the mask access on both vectors.
2971 int MinRange[2] = { static_cast<int>(SrcNumElts),
2972 static_cast<int>(SrcNumElts)};
2973 int MaxRange[2] = {-1, -1};
2975 for (unsigned i = 0; i != MaskNumElts; ++i) {
2981 if (Idx >= (int)SrcNumElts) {
2985 if (Idx > MaxRange[Input])
2986 MaxRange[Input] = Idx;
2987 if (Idx < MinRange[Input])
2988 MinRange[Input] = Idx;
2991 // Check if the access is smaller than the vector size and can we find
2992 // a reasonable extract index.
2993 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2995 int StartIdx[2]; // StartIdx to extract from
2996 for (unsigned Input = 0; Input < 2; ++Input) {
2997 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2998 RangeUse[Input] = 0; // Unused
2999 StartIdx[Input] = 0;
3003 // Find a good start index that is a multiple of the mask length. Then
3004 // see if the rest of the elements are in range.
3005 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3006 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3007 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3008 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3011 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3012 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3015 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3016 // Extract appropriate subvector and generate a vector shuffle
3017 for (unsigned Input = 0; Input < 2; ++Input) {
3018 SDValue &Src = Input == 0 ? Src1 : Src2;
3019 if (RangeUse[Input] == 0)
3020 Src = DAG.getUNDEF(VT);
3022 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3023 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3026 // Calculate new mask.
3027 SmallVector<int, 8> MappedOps;
3028 for (unsigned i = 0; i != MaskNumElts; ++i) {
3031 if (Idx < (int)SrcNumElts)
3034 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3036 MappedOps.push_back(Idx);
3039 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3045 // We can't use either concat vectors or extract subvectors so fall back to
3046 // replacing the shuffle with extract and build vector.
3047 // to insert and build vector.
3048 EVT EltVT = VT.getVectorElementType();
3049 EVT PtrVT = TLI->getPointerTy();
3050 SmallVector<SDValue,8> Ops;
3051 for (unsigned i = 0; i != MaskNumElts; ++i) {
3056 Res = DAG.getUNDEF(EltVT);
3058 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3059 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3061 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3062 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3068 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3069 VT, &Ops[0], Ops.size()));
3072 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3073 const Value *Op0 = I.getOperand(0);
3074 const Value *Op1 = I.getOperand(1);
3075 Type *AggTy = I.getType();
3076 Type *ValTy = Op1->getType();
3077 bool IntoUndef = isa<UndefValue>(Op0);
3078 bool FromUndef = isa<UndefValue>(Op1);
3080 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3082 const TargetLowering *TLI = TM.getTargetLowering();
3083 SmallVector<EVT, 4> AggValueVTs;
3084 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3085 SmallVector<EVT, 4> ValValueVTs;
3086 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3088 unsigned NumAggValues = AggValueVTs.size();
3089 unsigned NumValValues = ValValueVTs.size();
3090 SmallVector<SDValue, 4> Values(NumAggValues);
3092 SDValue Agg = getValue(Op0);
3094 // Copy the beginning value(s) from the original aggregate.
3095 for (; i != LinearIndex; ++i)
3096 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3097 SDValue(Agg.getNode(), Agg.getResNo() + i);
3098 // Copy values from the inserted value(s).
3100 SDValue Val = getValue(Op1);
3101 for (; i != LinearIndex + NumValValues; ++i)
3102 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3103 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3105 // Copy remaining value(s) from the original aggregate.
3106 for (; i != NumAggValues; ++i)
3107 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3108 SDValue(Agg.getNode(), Agg.getResNo() + i);
3110 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3111 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3112 &Values[0], NumAggValues));
3115 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3116 const Value *Op0 = I.getOperand(0);
3117 Type *AggTy = Op0->getType();
3118 Type *ValTy = I.getType();
3119 bool OutOfUndef = isa<UndefValue>(Op0);
3121 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3123 const TargetLowering *TLI = TM.getTargetLowering();
3124 SmallVector<EVT, 4> ValValueVTs;
3125 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3127 unsigned NumValValues = ValValueVTs.size();
3129 // Ignore a extractvalue that produces an empty object
3130 if (!NumValValues) {
3131 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3135 SmallVector<SDValue, 4> Values(NumValValues);
3137 SDValue Agg = getValue(Op0);
3138 // Copy out the selected value(s).
3139 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3140 Values[i - LinearIndex] =
3142 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3143 SDValue(Agg.getNode(), Agg.getResNo() + i);
3145 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3146 DAG.getVTList(&ValValueVTs[0], NumValValues),
3147 &Values[0], NumValValues));
3150 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3151 SDValue N = getValue(I.getOperand(0));
3152 // Note that the pointer operand may be a vector of pointers. Take the scalar
3153 // element which holds a pointer.
3154 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3156 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3158 const Value *Idx = *OI;
3159 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3160 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3163 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3164 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3165 DAG.getConstant(Offset, N.getValueType()));
3168 Ty = StTy->getElementType(Field);
3170 Ty = cast<SequentialType>(Ty)->getElementType();
3172 // If this is a constant subscript, handle it quickly.
3173 const TargetLowering *TLI = TM.getTargetLowering();
3174 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3175 if (CI->isZero()) continue;
3177 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3179 EVT PTy = TLI->getPointerTy();
3180 unsigned PtrBits = PTy.getSizeInBits();
3182 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(),
3183 TLI->getPointerTy(),
3184 DAG.getConstant(Offs, MVT::i64));
3186 OffsVal = DAG.getIntPtrConstant(Offs);
3188 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3193 // N = N + Idx * ElementSize;
3194 APInt ElementSize = APInt(TLI->getPointerTy().getSizeInBits(),
3195 TD->getTypeAllocSize(Ty));
3196 SDValue IdxN = getValue(Idx);
3198 // If the index is smaller or larger than intptr_t, truncate or extend
3200 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3202 // If this is a multiply by a power of two, turn it into a shl
3203 // immediately. This is a very common case.
3204 if (ElementSize != 1) {
3205 if (ElementSize.isPowerOf2()) {
3206 unsigned Amt = ElementSize.logBase2();
3207 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3208 N.getValueType(), IdxN,
3209 DAG.getConstant(Amt, IdxN.getValueType()));
3211 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3212 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3213 N.getValueType(), IdxN, Scale);
3217 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3218 N.getValueType(), N, IdxN);
3225 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3226 // If this is a fixed sized alloca in the entry block of the function,
3227 // allocate it statically on the stack.
3228 if (FuncInfo.StaticAllocaMap.count(&I))
3229 return; // getValue will auto-populate this.
3231 Type *Ty = I.getAllocatedType();
3232 const TargetLowering *TLI = TM.getTargetLowering();
3233 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3235 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3238 SDValue AllocSize = getValue(I.getArraySize());
3240 EVT IntPtr = TLI->getPointerTy();
3241 if (AllocSize.getValueType() != IntPtr)
3242 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3244 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3246 DAG.getConstant(TySize, IntPtr));
3248 // Handle alignment. If the requested alignment is less than or equal to
3249 // the stack alignment, ignore it. If the size is greater than or equal to
3250 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3251 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3252 if (Align <= StackAlign)
3255 // Round the size of the allocation up to the stack alignment size
3256 // by add SA-1 to the size.
3257 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3258 AllocSize.getValueType(), AllocSize,
3259 DAG.getIntPtrConstant(StackAlign-1));
3261 // Mask out the low bits for alignment purposes.
3262 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3263 AllocSize.getValueType(), AllocSize,
3264 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3266 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3267 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3268 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3271 DAG.setRoot(DSA.getValue(1));
3273 // Inform the Frame Information that we have just allocated a variable-sized
3275 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3278 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3280 return visitAtomicLoad(I);
3282 const Value *SV = I.getOperand(0);
3283 SDValue Ptr = getValue(SV);
3285 Type *Ty = I.getType();
3287 bool isVolatile = I.isVolatile();
3288 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3289 bool isInvariant = I.getMetadata("invariant.load") != 0;
3290 unsigned Alignment = I.getAlignment();
3291 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3292 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3294 SmallVector<EVT, 4> ValueVTs;
3295 SmallVector<uint64_t, 4> Offsets;
3296 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3297 unsigned NumValues = ValueVTs.size();
3302 bool ConstantMemory = false;
3303 if (I.isVolatile() || NumValues > MaxParallelChains)
3304 // Serialize volatile loads with other side effects.
3306 else if (AA->pointsToConstantMemory(
3307 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3308 // Do not serialize (non-volatile) loads of constant memory with anything.
3309 Root = DAG.getEntryNode();
3310 ConstantMemory = true;
3312 // Do not serialize non-volatile loads against each other.
3313 Root = DAG.getRoot();
3316 SmallVector<SDValue, 4> Values(NumValues);
3317 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3319 EVT PtrVT = Ptr.getValueType();
3320 unsigned ChainI = 0;
3321 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3322 // Serializing loads here may result in excessive register pressure, and
3323 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3324 // could recover a bit by hoisting nodes upward in the chain by recognizing
3325 // they are side-effect free or do not alias. The optimizer should really
3326 // avoid this case by converting large object/array copies to llvm.memcpy
3327 // (MaxParallelChains should always remain as failsafe).
3328 if (ChainI == MaxParallelChains) {
3329 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3330 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3331 MVT::Other, &Chains[0], ChainI);
3335 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3337 DAG.getConstant(Offsets[i], PtrVT));
3338 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3339 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3340 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3344 Chains[ChainI] = L.getValue(1);
3347 if (!ConstantMemory) {
3348 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3349 MVT::Other, &Chains[0], ChainI);
3353 PendingLoads.push_back(Chain);
3356 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3357 DAG.getVTList(&ValueVTs[0], NumValues),
3358 &Values[0], NumValues));
3361 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3363 return visitAtomicStore(I);
3365 const Value *SrcV = I.getOperand(0);
3366 const Value *PtrV = I.getOperand(1);
3368 SmallVector<EVT, 4> ValueVTs;
3369 SmallVector<uint64_t, 4> Offsets;
3370 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3371 unsigned NumValues = ValueVTs.size();
3375 // Get the lowered operands. Note that we do this after
3376 // checking if NumResults is zero, because with zero results
3377 // the operands won't have values in the map.
3378 SDValue Src = getValue(SrcV);
3379 SDValue Ptr = getValue(PtrV);
3381 SDValue Root = getRoot();
3382 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3384 EVT PtrVT = Ptr.getValueType();
3385 bool isVolatile = I.isVolatile();
3386 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3387 unsigned Alignment = I.getAlignment();
3388 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3390 unsigned ChainI = 0;
3391 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3392 // See visitLoad comments.
3393 if (ChainI == MaxParallelChains) {
3394 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3395 MVT::Other, &Chains[0], ChainI);
3399 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3400 DAG.getConstant(Offsets[i], PtrVT));
3401 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3402 SDValue(Src.getNode(), Src.getResNo() + i),
3403 Add, MachinePointerInfo(PtrV, Offsets[i]),
3404 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3405 Chains[ChainI] = St;
3408 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3409 MVT::Other, &Chains[0], ChainI);
3410 DAG.setRoot(StoreNode);
3413 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3414 SynchronizationScope Scope,
3415 bool Before, SDLoc dl,
3417 const TargetLowering &TLI) {
3418 // Fence, if necessary
3420 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3422 else if (Order == Acquire || Order == Monotonic)
3425 if (Order == AcquireRelease)
3427 else if (Order == Release || Order == Monotonic)
3432 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3433 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3434 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3437 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3438 SDLoc dl = getCurSDLoc();
3439 AtomicOrdering Order = I.getOrdering();
3440 SynchronizationScope Scope = I.getSynchScope();
3442 SDValue InChain = getRoot();
3444 const TargetLowering *TLI = TM.getTargetLowering();
3445 if (TLI->getInsertFencesForAtomic())
3446 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3450 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3451 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3453 getValue(I.getPointerOperand()),
3454 getValue(I.getCompareOperand()),
3455 getValue(I.getNewValOperand()),
3456 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3457 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3460 SDValue OutChain = L.getValue(1);
3462 if (TLI->getInsertFencesForAtomic())
3463 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3467 DAG.setRoot(OutChain);
3470 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3471 SDLoc dl = getCurSDLoc();
3473 switch (I.getOperation()) {
3474 default: llvm_unreachable("Unknown atomicrmw operation");
3475 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3476 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3477 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3478 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3479 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3480 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3481 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3482 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3483 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3484 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3485 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3487 AtomicOrdering Order = I.getOrdering();
3488 SynchronizationScope Scope = I.getSynchScope();
3490 SDValue InChain = getRoot();
3492 const TargetLowering *TLI = TM.getTargetLowering();
3493 if (TLI->getInsertFencesForAtomic())
3494 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3498 DAG.getAtomic(NT, dl,
3499 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3501 getValue(I.getPointerOperand()),
3502 getValue(I.getValOperand()),
3503 I.getPointerOperand(), 0 /* Alignment */,
3504 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3507 SDValue OutChain = L.getValue(1);
3509 if (TLI->getInsertFencesForAtomic())
3510 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3514 DAG.setRoot(OutChain);
3517 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3518 SDLoc dl = getCurSDLoc();
3519 const TargetLowering *TLI = TM.getTargetLowering();
3522 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3523 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3524 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3527 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3528 SDLoc dl = getCurSDLoc();
3529 AtomicOrdering Order = I.getOrdering();
3530 SynchronizationScope Scope = I.getSynchScope();
3532 SDValue InChain = getRoot();
3534 const TargetLowering *TLI = TM.getTargetLowering();
3535 EVT VT = TLI->getValueType(I.getType());
3537 if (I.getAlignment() < VT.getSizeInBits() / 8)
3538 report_fatal_error("Cannot generate unaligned atomic load");
3541 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3542 getValue(I.getPointerOperand()),
3543 I.getPointerOperand(), I.getAlignment(),
3544 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3547 SDValue OutChain = L.getValue(1);
3549 if (TLI->getInsertFencesForAtomic())
3550 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3554 DAG.setRoot(OutChain);
3557 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3558 SDLoc dl = getCurSDLoc();
3560 AtomicOrdering Order = I.getOrdering();
3561 SynchronizationScope Scope = I.getSynchScope();
3563 SDValue InChain = getRoot();
3565 const TargetLowering *TLI = TM.getTargetLowering();
3566 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3568 if (I.getAlignment() < VT.getSizeInBits() / 8)
3569 report_fatal_error("Cannot generate unaligned atomic store");
3571 if (TLI->getInsertFencesForAtomic())
3572 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3576 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3578 getValue(I.getPointerOperand()),
3579 getValue(I.getValueOperand()),
3580 I.getPointerOperand(), I.getAlignment(),
3581 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3584 if (TLI->getInsertFencesForAtomic())
3585 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3588 DAG.setRoot(OutChain);
3591 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3593 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3594 unsigned Intrinsic) {
3595 bool HasChain = !I.doesNotAccessMemory();
3596 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3598 // Build the operand list.
3599 SmallVector<SDValue, 8> Ops;
3600 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3602 // We don't need to serialize loads against other loads.
3603 Ops.push_back(DAG.getRoot());
3605 Ops.push_back(getRoot());
3609 // Info is set by getTgtMemInstrinsic
3610 TargetLowering::IntrinsicInfo Info;
3611 const TargetLowering *TLI = TM.getTargetLowering();
3612 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3614 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3615 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3616 Info.opc == ISD::INTRINSIC_W_CHAIN)
3617 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3619 // Add all operands of the call to the operand list.
3620 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3621 SDValue Op = getValue(I.getArgOperand(i));
3625 SmallVector<EVT, 4> ValueVTs;
3626 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3629 ValueVTs.push_back(MVT::Other);
3631 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3635 if (IsTgtIntrinsic) {
3636 // This is target intrinsic that touches memory
3637 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3638 VTs, &Ops[0], Ops.size(),
3640 MachinePointerInfo(Info.ptrVal, Info.offset),
3641 Info.align, Info.vol,
3642 Info.readMem, Info.writeMem);
3643 } else if (!HasChain) {
3644 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3645 VTs, &Ops[0], Ops.size());
3646 } else if (!I.getType()->isVoidTy()) {
3647 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3648 VTs, &Ops[0], Ops.size());
3650 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3651 VTs, &Ops[0], Ops.size());
3655 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3657 PendingLoads.push_back(Chain);
3662 if (!I.getType()->isVoidTy()) {
3663 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3664 EVT VT = TLI->getValueType(PTy);
3665 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3668 setValue(&I, Result);
3672 /// GetSignificand - Get the significand and build it into a floating-point
3673 /// number with exponent of 1:
3675 /// Op = (Op & 0x007fffff) | 0x3f800000;
3677 /// where Op is the hexadecimal representation of floating point value.
3679 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3680 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3681 DAG.getConstant(0x007fffff, MVT::i32));
3682 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3683 DAG.getConstant(0x3f800000, MVT::i32));
3684 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3687 /// GetExponent - Get the exponent:
3689 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3691 /// where Op is the hexadecimal representation of floating point value.
3693 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3695 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3696 DAG.getConstant(0x7f800000, MVT::i32));
3697 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3698 DAG.getConstant(23, TLI.getPointerTy()));
3699 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3700 DAG.getConstant(127, MVT::i32));
3701 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3704 /// getF32Constant - Get 32-bit floating point constant.
3706 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3707 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3711 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3712 /// limited-precision mode.
3713 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3714 const TargetLowering &TLI) {
3715 if (Op.getValueType() == MVT::f32 &&
3716 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3718 // Put the exponent in the right bit position for later addition to the
3721 // #define LOG2OFe 1.4426950f
3722 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3723 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3724 getF32Constant(DAG, 0x3fb8aa3b));
3725 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3727 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3728 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3729 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3731 // IntegerPartOfX <<= 23;
3732 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3733 DAG.getConstant(23, TLI.getPointerTy()));
3735 SDValue TwoToFracPartOfX;
3736 if (LimitFloatPrecision <= 6) {
3737 // For floating-point precision of 6:
3739 // TwoToFractionalPartOfX =
3741 // (0.735607626f + 0.252464424f * x) * x;
3743 // error 0.0144103317, which is 6 bits
3744 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3745 getF32Constant(DAG, 0x3e814304));
3746 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3747 getF32Constant(DAG, 0x3f3c50c8));
3748 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3749 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3750 getF32Constant(DAG, 0x3f7f5e7e));
3751 } else if (LimitFloatPrecision <= 12) {
3752 // For floating-point precision of 12:
3754 // TwoToFractionalPartOfX =
3757 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3759 // 0.000107046256 error, which is 13 to 14 bits
3760 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3761 getF32Constant(DAG, 0x3da235e3));
3762 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3763 getF32Constant(DAG, 0x3e65b8f3));
3764 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3765 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3766 getF32Constant(DAG, 0x3f324b07));
3767 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3768 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3769 getF32Constant(DAG, 0x3f7ff8fd));
3770 } else { // LimitFloatPrecision <= 18
3771 // For floating-point precision of 18:
3773 // TwoToFractionalPartOfX =
3777 // (0.554906021e-1f +
3778 // (0.961591928e-2f +
3779 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3781 // error 2.47208000*10^(-7), which is better than 18 bits
3782 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3783 getF32Constant(DAG, 0x3924b03e));
3784 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3785 getF32Constant(DAG, 0x3ab24b87));
3786 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3787 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3788 getF32Constant(DAG, 0x3c1d8c17));
3789 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3790 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3791 getF32Constant(DAG, 0x3d634a1d));
3792 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3793 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3794 getF32Constant(DAG, 0x3e75fe14));
3795 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3796 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3797 getF32Constant(DAG, 0x3f317234));
3798 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3799 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3800 getF32Constant(DAG, 0x3f800000));
3803 // Add the exponent into the result in integer domain.
3804 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3805 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3806 DAG.getNode(ISD::ADD, dl, MVT::i32,
3807 t13, IntegerPartOfX));
3810 // No special expansion.
3811 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3814 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3815 /// limited-precision mode.
3816 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3817 const TargetLowering &TLI) {
3818 if (Op.getValueType() == MVT::f32 &&
3819 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3820 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3822 // Scale the exponent by log(2) [0.69314718f].
3823 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3824 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3825 getF32Constant(DAG, 0x3f317218));
3827 // Get the significand and build it into a floating-point number with
3829 SDValue X = GetSignificand(DAG, Op1, dl);
3831 SDValue LogOfMantissa;
3832 if (LimitFloatPrecision <= 6) {
3833 // For floating-point precision of 6:
3837 // (1.4034025f - 0.23903021f * x) * x;
3839 // error 0.0034276066, which is better than 8 bits
3840 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3841 getF32Constant(DAG, 0xbe74c456));
3842 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3843 getF32Constant(DAG, 0x3fb3a2b1));
3844 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3845 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3846 getF32Constant(DAG, 0x3f949a29));
3847 } else if (LimitFloatPrecision <= 12) {
3848 // For floating-point precision of 12:
3854 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3856 // error 0.000061011436, which is 14 bits
3857 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3858 getF32Constant(DAG, 0xbd67b6d6));
3859 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3860 getF32Constant(DAG, 0x3ee4f4b8));
3861 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3862 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3863 getF32Constant(DAG, 0x3fbc278b));
3864 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3865 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3866 getF32Constant(DAG, 0x40348e95));
3867 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3868 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3869 getF32Constant(DAG, 0x3fdef31a));
3870 } else { // LimitFloatPrecision <= 18
3871 // For floating-point precision of 18:
3879 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3881 // error 0.0000023660568, which is better than 18 bits
3882 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3883 getF32Constant(DAG, 0xbc91e5ac));
3884 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3885 getF32Constant(DAG, 0x3e4350aa));
3886 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3887 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3888 getF32Constant(DAG, 0x3f60d3e3));
3889 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3890 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3891 getF32Constant(DAG, 0x4011cdf0));
3892 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3893 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3894 getF32Constant(DAG, 0x406cfd1c));
3895 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3896 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3897 getF32Constant(DAG, 0x408797cb));
3898 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3899 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3900 getF32Constant(DAG, 0x4006dcab));
3903 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3906 // No special expansion.
3907 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3910 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3911 /// limited-precision mode.
3912 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3913 const TargetLowering &TLI) {
3914 if (Op.getValueType() == MVT::f32 &&
3915 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3916 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3918 // Get the exponent.
3919 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3921 // Get the significand and build it into a floating-point number with
3923 SDValue X = GetSignificand(DAG, Op1, dl);
3925 // Different possible minimax approximations of significand in
3926 // floating-point for various degrees of accuracy over [1,2].
3927 SDValue Log2ofMantissa;
3928 if (LimitFloatPrecision <= 6) {
3929 // For floating-point precision of 6:
3931 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3933 // error 0.0049451742, which is more than 7 bits
3934 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3935 getF32Constant(DAG, 0xbeb08fe0));
3936 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3937 getF32Constant(DAG, 0x40019463));
3938 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3939 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3940 getF32Constant(DAG, 0x3fd6633d));
3941 } else if (LimitFloatPrecision <= 12) {
3942 // For floating-point precision of 12:
3948 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3950 // error 0.0000876136000, which is better than 13 bits
3951 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3952 getF32Constant(DAG, 0xbda7262e));
3953 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3954 getF32Constant(DAG, 0x3f25280b));
3955 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3956 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3957 getF32Constant(DAG, 0x4007b923));
3958 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3959 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3960 getF32Constant(DAG, 0x40823e2f));
3961 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3962 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3963 getF32Constant(DAG, 0x4020d29c));
3964 } else { // LimitFloatPrecision <= 18
3965 // For floating-point precision of 18:
3974 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3976 // error 0.0000018516, which is better than 18 bits
3977 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3978 getF32Constant(DAG, 0xbcd2769e));
3979 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3980 getF32Constant(DAG, 0x3e8ce0b9));
3981 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3982 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3983 getF32Constant(DAG, 0x3fa22ae7));
3984 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3985 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3986 getF32Constant(DAG, 0x40525723));
3987 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3988 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3989 getF32Constant(DAG, 0x40aaf200));
3990 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3991 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3992 getF32Constant(DAG, 0x40c39dad));
3993 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3994 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3995 getF32Constant(DAG, 0x4042902c));
3998 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4001 // No special expansion.
4002 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4005 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4006 /// limited-precision mode.
4007 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4008 const TargetLowering &TLI) {
4009 if (Op.getValueType() == MVT::f32 &&
4010 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4011 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4013 // Scale the exponent by log10(2) [0.30102999f].
4014 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4015 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4016 getF32Constant(DAG, 0x3e9a209a));
4018 // Get the significand and build it into a floating-point number with
4020 SDValue X = GetSignificand(DAG, Op1, dl);
4022 SDValue Log10ofMantissa;
4023 if (LimitFloatPrecision <= 6) {
4024 // For floating-point precision of 6:
4026 // Log10ofMantissa =
4028 // (0.60948995f - 0.10380950f * x) * x;
4030 // error 0.0014886165, which is 6 bits
4031 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4032 getF32Constant(DAG, 0xbdd49a13));
4033 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4034 getF32Constant(DAG, 0x3f1c0789));
4035 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4036 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4037 getF32Constant(DAG, 0x3f011300));
4038 } else if (LimitFloatPrecision <= 12) {
4039 // For floating-point precision of 12:
4041 // Log10ofMantissa =
4044 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4046 // error 0.00019228036, which is better than 12 bits
4047 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4048 getF32Constant(DAG, 0x3d431f31));
4049 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4050 getF32Constant(DAG, 0x3ea21fb2));
4051 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4052 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4053 getF32Constant(DAG, 0x3f6ae232));
4054 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4055 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4056 getF32Constant(DAG, 0x3f25f7c3));
4057 } else { // LimitFloatPrecision <= 18
4058 // For floating-point precision of 18:
4060 // Log10ofMantissa =
4065 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4067 // error 0.0000037995730, which is better than 18 bits
4068 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4069 getF32Constant(DAG, 0x3c5d51ce));
4070 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4071 getF32Constant(DAG, 0x3e00685a));
4072 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4073 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4074 getF32Constant(DAG, 0x3efb6798));
4075 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4076 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4077 getF32Constant(DAG, 0x3f88d192));
4078 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4079 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4080 getF32Constant(DAG, 0x3fc4316c));
4081 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4082 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4083 getF32Constant(DAG, 0x3f57ce70));
4086 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4089 // No special expansion.
4090 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4093 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4094 /// limited-precision mode.
4095 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4096 const TargetLowering &TLI) {
4097 if (Op.getValueType() == MVT::f32 &&
4098 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4099 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4101 // FractionalPartOfX = x - (float)IntegerPartOfX;
4102 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4103 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4105 // IntegerPartOfX <<= 23;
4106 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4107 DAG.getConstant(23, TLI.getPointerTy()));
4109 SDValue TwoToFractionalPartOfX;
4110 if (LimitFloatPrecision <= 6) {
4111 // For floating-point precision of 6:
4113 // TwoToFractionalPartOfX =
4115 // (0.735607626f + 0.252464424f * x) * x;
4117 // error 0.0144103317, which is 6 bits
4118 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4119 getF32Constant(DAG, 0x3e814304));
4120 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4121 getF32Constant(DAG, 0x3f3c50c8));
4122 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4123 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4124 getF32Constant(DAG, 0x3f7f5e7e));
4125 } else if (LimitFloatPrecision <= 12) {
4126 // For floating-point precision of 12:
4128 // TwoToFractionalPartOfX =
4131 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4133 // error 0.000107046256, which is 13 to 14 bits
4134 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4135 getF32Constant(DAG, 0x3da235e3));
4136 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4137 getF32Constant(DAG, 0x3e65b8f3));
4138 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4139 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4140 getF32Constant(DAG, 0x3f324b07));
4141 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4142 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4143 getF32Constant(DAG, 0x3f7ff8fd));
4144 } else { // LimitFloatPrecision <= 18
4145 // For floating-point precision of 18:
4147 // TwoToFractionalPartOfX =
4151 // (0.554906021e-1f +
4152 // (0.961591928e-2f +
4153 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4154 // error 2.47208000*10^(-7), which is better than 18 bits
4155 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4156 getF32Constant(DAG, 0x3924b03e));
4157 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4158 getF32Constant(DAG, 0x3ab24b87));
4159 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4160 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4161 getF32Constant(DAG, 0x3c1d8c17));
4162 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4163 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4164 getF32Constant(DAG, 0x3d634a1d));
4165 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4166 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4167 getF32Constant(DAG, 0x3e75fe14));
4168 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4169 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4170 getF32Constant(DAG, 0x3f317234));
4171 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4172 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4173 getF32Constant(DAG, 0x3f800000));
4176 // Add the exponent into the result in integer domain.
4177 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4178 TwoToFractionalPartOfX);
4179 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4180 DAG.getNode(ISD::ADD, dl, MVT::i32,
4181 t13, IntegerPartOfX));
4184 // No special expansion.
4185 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4188 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4189 /// limited-precision mode with x == 10.0f.
4190 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4191 SelectionDAG &DAG, const TargetLowering &TLI) {
4192 bool IsExp10 = false;
4193 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4194 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4195 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4197 IsExp10 = LHSC->isExactlyValue(Ten);
4202 // Put the exponent in the right bit position for later addition to the
4205 // #define LOG2OF10 3.3219281f
4206 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4207 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4208 getF32Constant(DAG, 0x40549a78));
4209 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4211 // FractionalPartOfX = x - (float)IntegerPartOfX;
4212 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4213 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4215 // IntegerPartOfX <<= 23;
4216 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4217 DAG.getConstant(23, TLI.getPointerTy()));
4219 SDValue TwoToFractionalPartOfX;
4220 if (LimitFloatPrecision <= 6) {
4221 // For floating-point precision of 6:
4223 // twoToFractionalPartOfX =
4225 // (0.735607626f + 0.252464424f * x) * x;
4227 // error 0.0144103317, which is 6 bits
4228 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4229 getF32Constant(DAG, 0x3e814304));
4230 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4231 getF32Constant(DAG, 0x3f3c50c8));
4232 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4233 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4234 getF32Constant(DAG, 0x3f7f5e7e));
4235 } else if (LimitFloatPrecision <= 12) {
4236 // For floating-point precision of 12:
4238 // TwoToFractionalPartOfX =
4241 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4243 // error 0.000107046256, which is 13 to 14 bits
4244 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4245 getF32Constant(DAG, 0x3da235e3));
4246 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4247 getF32Constant(DAG, 0x3e65b8f3));
4248 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4249 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4250 getF32Constant(DAG, 0x3f324b07));
4251 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4252 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4253 getF32Constant(DAG, 0x3f7ff8fd));
4254 } else { // LimitFloatPrecision <= 18
4255 // For floating-point precision of 18:
4257 // TwoToFractionalPartOfX =
4261 // (0.554906021e-1f +
4262 // (0.961591928e-2f +
4263 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4264 // error 2.47208000*10^(-7), which is better than 18 bits
4265 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4266 getF32Constant(DAG, 0x3924b03e));
4267 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4268 getF32Constant(DAG, 0x3ab24b87));
4269 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4270 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4271 getF32Constant(DAG, 0x3c1d8c17));
4272 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4273 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4274 getF32Constant(DAG, 0x3d634a1d));
4275 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4276 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4277 getF32Constant(DAG, 0x3e75fe14));
4278 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4279 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4280 getF32Constant(DAG, 0x3f317234));
4281 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4282 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4283 getF32Constant(DAG, 0x3f800000));
4286 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4287 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4288 DAG.getNode(ISD::ADD, dl, MVT::i32,
4289 t13, IntegerPartOfX));
4292 // No special expansion.
4293 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4297 /// ExpandPowI - Expand a llvm.powi intrinsic.
4298 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4299 SelectionDAG &DAG) {
4300 // If RHS is a constant, we can expand this out to a multiplication tree,
4301 // otherwise we end up lowering to a call to __powidf2 (for example). When
4302 // optimizing for size, we only want to do this if the expansion would produce
4303 // a small number of multiplies, otherwise we do the full expansion.
4304 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4305 // Get the exponent as a positive value.
4306 unsigned Val = RHSC->getSExtValue();
4307 if ((int)Val < 0) Val = -Val;
4309 // powi(x, 0) -> 1.0
4311 return DAG.getConstantFP(1.0, LHS.getValueType());
4313 const Function *F = DAG.getMachineFunction().getFunction();
4314 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4315 Attribute::OptimizeForSize) ||
4316 // If optimizing for size, don't insert too many multiplies. This
4317 // inserts up to 5 multiplies.
4318 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4319 // We use the simple binary decomposition method to generate the multiply
4320 // sequence. There are more optimal ways to do this (for example,
4321 // powi(x,15) generates one more multiply than it should), but this has
4322 // the benefit of being both really simple and much better than a libcall.
4323 SDValue Res; // Logically starts equal to 1.0
4324 SDValue CurSquare = LHS;
4328 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4330 Res = CurSquare; // 1.0*CurSquare.
4333 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4334 CurSquare, CurSquare);
4338 // If the original was negative, invert the result, producing 1/(x*x*x).
4339 if (RHSC->getSExtValue() < 0)
4340 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4341 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4346 // Otherwise, expand to a libcall.
4347 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4350 // getTruncatedArgReg - Find underlying register used for an truncated
4352 static unsigned getTruncatedArgReg(const SDValue &N) {
4353 if (N.getOpcode() != ISD::TRUNCATE)
4356 const SDValue &Ext = N.getOperand(0);
4357 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4358 const SDValue &CFR = Ext.getOperand(0);
4359 if (CFR.getOpcode() == ISD::CopyFromReg)
4360 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4361 if (CFR.getOpcode() == ISD::TRUNCATE)
4362 return getTruncatedArgReg(CFR);
4367 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4368 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4369 /// At the end of instruction selection, they will be inserted to the entry BB.
4371 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4374 const Argument *Arg = dyn_cast<Argument>(V);
4378 MachineFunction &MF = DAG.getMachineFunction();
4379 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4381 // Ignore inlined function arguments here.
4382 DIVariable DV(Variable);
4383 if (DV.isInlinedFnArgument(MF.getFunction()))
4386 Optional<MachineOperand> Op;
4387 // Some arguments' frame index is recorded during argument lowering.
4388 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4389 Op = MachineOperand::CreateFI(FI);
4391 if (!Op && N.getNode()) {
4393 if (N.getOpcode() == ISD::CopyFromReg)
4394 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4396 Reg = getTruncatedArgReg(N);
4397 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4398 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4399 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4404 Op = MachineOperand::CreateReg(Reg, false);
4408 // Check if ValueMap has reg number.
4409 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4410 if (VMI != FuncInfo.ValueMap.end())
4411 Op = MachineOperand::CreateReg(VMI->second, false);
4414 if (!Op && N.getNode())
4415 // Check if frame index is available.
4416 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4417 if (FrameIndexSDNode *FINode =
4418 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4419 Op = MachineOperand::CreateFI(FINode->getIndex());
4427 FuncInfo.ArgDbgValues.push_back(
4428 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4429 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4433 // VisualStudio defines setjmp as _setjmp
4434 #if defined(_MSC_VER) && defined(setjmp) && \
4435 !defined(setjmp_undefined_for_msvc)
4436 # pragma push_macro("setjmp")
4438 # define setjmp_undefined_for_msvc
4441 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4442 /// we want to emit this as a call to a named external function, return the name
4443 /// otherwise lower it and return null.
4445 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4446 const TargetLowering *TLI = TM.getTargetLowering();
4447 SDLoc sdl = getCurSDLoc();
4448 DebugLoc dl = getCurDebugLoc();
4451 switch (Intrinsic) {
4453 // By default, turn this into a target intrinsic node.
4454 visitTargetIntrinsic(I, Intrinsic);
4456 case Intrinsic::vastart: visitVAStart(I); return 0;
4457 case Intrinsic::vaend: visitVAEnd(I); return 0;
4458 case Intrinsic::vacopy: visitVACopy(I); return 0;
4459 case Intrinsic::returnaddress:
4460 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4461 getValue(I.getArgOperand(0))));
4463 case Intrinsic::frameaddress:
4464 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4465 getValue(I.getArgOperand(0))));
4467 case Intrinsic::setjmp:
4468 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4469 case Intrinsic::longjmp:
4470 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4471 case Intrinsic::memcpy: {
4472 // Assert for address < 256 since we support only user defined address
4474 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4476 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4478 "Unknown address space");
4479 SDValue Op1 = getValue(I.getArgOperand(0));
4480 SDValue Op2 = getValue(I.getArgOperand(1));
4481 SDValue Op3 = getValue(I.getArgOperand(2));
4482 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4484 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4485 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4486 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4487 MachinePointerInfo(I.getArgOperand(0)),
4488 MachinePointerInfo(I.getArgOperand(1))));
4491 case Intrinsic::memset: {
4492 // Assert for address < 256 since we support only user defined address
4494 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4496 "Unknown address space");
4497 SDValue Op1 = getValue(I.getArgOperand(0));
4498 SDValue Op2 = getValue(I.getArgOperand(1));
4499 SDValue Op3 = getValue(I.getArgOperand(2));
4500 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4502 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4503 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4504 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4505 MachinePointerInfo(I.getArgOperand(0))));
4508 case Intrinsic::memmove: {
4509 // Assert for address < 256 since we support only user defined address
4511 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4513 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4515 "Unknown address space");
4516 SDValue Op1 = getValue(I.getArgOperand(0));
4517 SDValue Op2 = getValue(I.getArgOperand(1));
4518 SDValue Op3 = getValue(I.getArgOperand(2));
4519 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4521 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4522 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4523 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4524 MachinePointerInfo(I.getArgOperand(0)),
4525 MachinePointerInfo(I.getArgOperand(1))));
4528 case Intrinsic::dbg_declare: {
4529 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4530 MDNode *Variable = DI.getVariable();
4531 const Value *Address = DI.getAddress();
4532 DIVariable DIVar(Variable);
4533 assert((!DIVar || DIVar.isVariable()) &&
4534 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4535 if (!Address || !DIVar) {
4536 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4540 // Check if address has undef value.
4541 if (isa<UndefValue>(Address) ||
4542 (Address->use_empty() && !isa<Argument>(Address))) {
4543 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4547 SDValue &N = NodeMap[Address];
4548 if (!N.getNode() && isa<Argument>(Address))
4549 // Check unused arguments map.
4550 N = UnusedArgNodeMap[Address];
4553 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4554 Address = BCI->getOperand(0);
4555 // Parameters are handled specially.
4557 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4558 isa<Argument>(Address));
4560 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4562 if (isParameter && !AI) {
4563 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4565 // Byval parameter. We have a frame index at this point.
4566 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4567 0, dl, SDNodeOrder);
4569 // Address is an argument, so try to emit its dbg value using
4570 // virtual register info from the FuncInfo.ValueMap.
4571 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4575 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4576 0, dl, SDNodeOrder);
4578 // Can't do anything with other non-AI cases yet.
4579 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4580 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4581 DEBUG(Address->dump());
4584 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4586 // If Address is an argument then try to emit its dbg value using
4587 // virtual register info from the FuncInfo.ValueMap.
4588 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4589 // If variable is pinned by a alloca in dominating bb then
4590 // use StaticAllocaMap.
4591 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4592 if (AI->getParent() != DI.getParent()) {
4593 DenseMap<const AllocaInst*, int>::iterator SI =
4594 FuncInfo.StaticAllocaMap.find(AI);
4595 if (SI != FuncInfo.StaticAllocaMap.end()) {
4596 SDV = DAG.getDbgValue(Variable, SI->second,
4597 0, dl, SDNodeOrder);
4598 DAG.AddDbgValue(SDV, 0, false);
4603 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4608 case Intrinsic::dbg_value: {
4609 const DbgValueInst &DI = cast<DbgValueInst>(I);
4610 DIVariable DIVar(DI.getVariable());
4611 assert((!DIVar || DIVar.isVariable()) &&
4612 "Variable in DbgValueInst should be either null or a DIVariable.");
4616 MDNode *Variable = DI.getVariable();
4617 uint64_t Offset = DI.getOffset();
4618 const Value *V = DI.getValue();
4623 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4624 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4625 DAG.AddDbgValue(SDV, 0, false);
4627 // Do not use getValue() in here; we don't want to generate code at
4628 // this point if it hasn't been done yet.
4629 SDValue N = NodeMap[V];
4630 if (!N.getNode() && isa<Argument>(V))
4631 // Check unused arguments map.
4632 N = UnusedArgNodeMap[V];
4634 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4635 SDV = DAG.getDbgValue(Variable, N.getNode(),
4636 N.getResNo(), Offset, dl, SDNodeOrder);
4637 DAG.AddDbgValue(SDV, N.getNode(), false);
4639 } else if (!V->use_empty() ) {
4640 // Do not call getValue(V) yet, as we don't want to generate code.
4641 // Remember it for later.
4642 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4643 DanglingDebugInfoMap[V] = DDI;
4645 // We may expand this to cover more cases. One case where we have no
4646 // data available is an unreferenced parameter.
4647 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4651 // Build a debug info table entry.
4652 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4653 V = BCI->getOperand(0);
4654 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4655 // Don't handle byval struct arguments or VLAs, for example.
4657 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4658 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4661 DenseMap<const AllocaInst*, int>::iterator SI =
4662 FuncInfo.StaticAllocaMap.find(AI);
4663 if (SI == FuncInfo.StaticAllocaMap.end())
4665 int FI = SI->second;
4667 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4668 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4669 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4673 case Intrinsic::eh_typeid_for: {
4674 // Find the type id for the given typeinfo.
4675 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4676 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4677 Res = DAG.getConstant(TypeID, MVT::i32);
4682 case Intrinsic::eh_return_i32:
4683 case Intrinsic::eh_return_i64:
4684 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4685 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4688 getValue(I.getArgOperand(0)),
4689 getValue(I.getArgOperand(1))));
4691 case Intrinsic::eh_unwind_init:
4692 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4694 case Intrinsic::eh_dwarf_cfa: {
4695 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4696 TLI->getPointerTy());
4697 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4698 TLI->getPointerTy(),
4699 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4700 TLI->getPointerTy()),
4702 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4703 TLI->getPointerTy(),
4704 DAG.getConstant(0, TLI->getPointerTy()));
4705 setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI->getPointerTy(),
4709 case Intrinsic::eh_sjlj_callsite: {
4710 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4711 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4712 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4713 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4715 MMI.setCurrentCallSite(CI->getZExtValue());
4718 case Intrinsic::eh_sjlj_functioncontext: {
4719 // Get and store the index of the function context.
4720 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4722 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4723 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4724 MFI->setFunctionContextIndex(FI);
4727 case Intrinsic::eh_sjlj_setjmp: {
4730 Ops[1] = getValue(I.getArgOperand(0));
4731 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4732 DAG.getVTList(MVT::i32, MVT::Other),
4734 setValue(&I, Op.getValue(0));
4735 DAG.setRoot(Op.getValue(1));
4738 case Intrinsic::eh_sjlj_longjmp: {
4739 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4740 getRoot(), getValue(I.getArgOperand(0))));
4744 case Intrinsic::x86_mmx_pslli_w:
4745 case Intrinsic::x86_mmx_pslli_d:
4746 case Intrinsic::x86_mmx_pslli_q:
4747 case Intrinsic::x86_mmx_psrli_w:
4748 case Intrinsic::x86_mmx_psrli_d:
4749 case Intrinsic::x86_mmx_psrli_q:
4750 case Intrinsic::x86_mmx_psrai_w:
4751 case Intrinsic::x86_mmx_psrai_d: {
4752 SDValue ShAmt = getValue(I.getArgOperand(1));
4753 if (isa<ConstantSDNode>(ShAmt)) {
4754 visitTargetIntrinsic(I, Intrinsic);
4757 unsigned NewIntrinsic = 0;
4758 EVT ShAmtVT = MVT::v2i32;
4759 switch (Intrinsic) {
4760 case Intrinsic::x86_mmx_pslli_w:
4761 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4763 case Intrinsic::x86_mmx_pslli_d:
4764 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4766 case Intrinsic::x86_mmx_pslli_q:
4767 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4769 case Intrinsic::x86_mmx_psrli_w:
4770 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4772 case Intrinsic::x86_mmx_psrli_d:
4773 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4775 case Intrinsic::x86_mmx_psrli_q:
4776 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4778 case Intrinsic::x86_mmx_psrai_w:
4779 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4781 case Intrinsic::x86_mmx_psrai_d:
4782 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4784 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4787 // The vector shift intrinsics with scalars uses 32b shift amounts but
4788 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4790 // We must do this early because v2i32 is not a legal type.
4793 ShOps[1] = DAG.getConstant(0, MVT::i32);
4794 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4795 EVT DestVT = TLI->getValueType(I.getType());
4796 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4797 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4798 DAG.getConstant(NewIntrinsic, MVT::i32),
4799 getValue(I.getArgOperand(0)), ShAmt);
4803 case Intrinsic::x86_avx_vinsertf128_pd_256:
4804 case Intrinsic::x86_avx_vinsertf128_ps_256:
4805 case Intrinsic::x86_avx_vinsertf128_si_256:
4806 case Intrinsic::x86_avx2_vinserti128: {
4807 EVT DestVT = TLI->getValueType(I.getType());
4808 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4809 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4810 ElVT.getVectorNumElements();
4811 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4812 getValue(I.getArgOperand(0)),
4813 getValue(I.getArgOperand(1)),
4814 DAG.getIntPtrConstant(Idx));
4818 case Intrinsic::x86_avx_vextractf128_pd_256:
4819 case Intrinsic::x86_avx_vextractf128_ps_256:
4820 case Intrinsic::x86_avx_vextractf128_si_256:
4821 case Intrinsic::x86_avx2_vextracti128: {
4822 EVT DestVT = TLI->getValueType(I.getType());
4823 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4824 DestVT.getVectorNumElements();
4825 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
4826 getValue(I.getArgOperand(0)),
4827 DAG.getIntPtrConstant(Idx));
4831 case Intrinsic::convertff:
4832 case Intrinsic::convertfsi:
4833 case Intrinsic::convertfui:
4834 case Intrinsic::convertsif:
4835 case Intrinsic::convertuif:
4836 case Intrinsic::convertss:
4837 case Intrinsic::convertsu:
4838 case Intrinsic::convertus:
4839 case Intrinsic::convertuu: {
4840 ISD::CvtCode Code = ISD::CVT_INVALID;
4841 switch (Intrinsic) {
4842 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4843 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4844 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4845 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4846 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4847 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4848 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4849 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4850 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4851 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4853 EVT DestVT = TLI->getValueType(I.getType());
4854 const Value *Op1 = I.getArgOperand(0);
4855 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4856 DAG.getValueType(DestVT),
4857 DAG.getValueType(getValue(Op1).getValueType()),
4858 getValue(I.getArgOperand(1)),
4859 getValue(I.getArgOperand(2)),
4864 case Intrinsic::powi:
4865 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4866 getValue(I.getArgOperand(1)), DAG));
4868 case Intrinsic::log:
4869 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4871 case Intrinsic::log2:
4872 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4874 case Intrinsic::log10:
4875 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4877 case Intrinsic::exp:
4878 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4880 case Intrinsic::exp2:
4881 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4883 case Intrinsic::pow:
4884 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4885 getValue(I.getArgOperand(1)), DAG, *TLI));
4887 case Intrinsic::sqrt:
4888 case Intrinsic::fabs:
4889 case Intrinsic::sin:
4890 case Intrinsic::cos:
4891 case Intrinsic::floor:
4892 case Intrinsic::ceil:
4893 case Intrinsic::trunc:
4894 case Intrinsic::rint:
4895 case Intrinsic::nearbyint: {
4897 switch (Intrinsic) {
4898 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4899 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4900 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4901 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4902 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4903 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4904 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4905 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4906 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4907 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4910 setValue(&I, DAG.getNode(Opcode, sdl,
4911 getValue(I.getArgOperand(0)).getValueType(),
4912 getValue(I.getArgOperand(0))));
4915 case Intrinsic::fma:
4916 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4917 getValue(I.getArgOperand(0)).getValueType(),
4918 getValue(I.getArgOperand(0)),
4919 getValue(I.getArgOperand(1)),
4920 getValue(I.getArgOperand(2))));
4922 case Intrinsic::fmuladd: {
4923 EVT VT = TLI->getValueType(I.getType());
4924 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4925 TLI->isFMAFasterThanMulAndAdd(VT)){
4926 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4927 getValue(I.getArgOperand(0)).getValueType(),
4928 getValue(I.getArgOperand(0)),
4929 getValue(I.getArgOperand(1)),
4930 getValue(I.getArgOperand(2))));
4932 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4933 getValue(I.getArgOperand(0)).getValueType(),
4934 getValue(I.getArgOperand(0)),
4935 getValue(I.getArgOperand(1)));
4936 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4937 getValue(I.getArgOperand(0)).getValueType(),
4939 getValue(I.getArgOperand(2)));
4944 case Intrinsic::convert_to_fp16:
4945 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
4946 MVT::i16, getValue(I.getArgOperand(0))));
4948 case Intrinsic::convert_from_fp16:
4949 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
4950 MVT::f32, getValue(I.getArgOperand(0))));
4952 case Intrinsic::pcmarker: {
4953 SDValue Tmp = getValue(I.getArgOperand(0));
4954 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4957 case Intrinsic::readcyclecounter: {
4958 SDValue Op = getRoot();
4959 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4960 DAG.getVTList(MVT::i64, MVT::Other),
4963 DAG.setRoot(Res.getValue(1));
4966 case Intrinsic::bswap:
4967 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4968 getValue(I.getArgOperand(0)).getValueType(),
4969 getValue(I.getArgOperand(0))));
4971 case Intrinsic::cttz: {
4972 SDValue Arg = getValue(I.getArgOperand(0));
4973 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4974 EVT Ty = Arg.getValueType();
4975 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4979 case Intrinsic::ctlz: {
4980 SDValue Arg = getValue(I.getArgOperand(0));
4981 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4982 EVT Ty = Arg.getValueType();
4983 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4987 case Intrinsic::ctpop: {
4988 SDValue Arg = getValue(I.getArgOperand(0));
4989 EVT Ty = Arg.getValueType();
4990 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4993 case Intrinsic::stacksave: {
4994 SDValue Op = getRoot();
4995 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4996 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
4998 DAG.setRoot(Res.getValue(1));
5001 case Intrinsic::stackrestore: {
5002 Res = getValue(I.getArgOperand(0));
5003 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5006 case Intrinsic::stackprotector: {
5007 // Emit code into the DAG to store the stack guard onto the stack.
5008 MachineFunction &MF = DAG.getMachineFunction();
5009 MachineFrameInfo *MFI = MF.getFrameInfo();
5010 EVT PtrTy = TLI->getPointerTy();
5012 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5013 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5015 int FI = FuncInfo.StaticAllocaMap[Slot];
5016 MFI->setStackProtectorIndex(FI);
5018 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5020 // Store the stack protector onto the stack.
5021 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5022 MachinePointerInfo::getFixedStack(FI),
5028 case Intrinsic::objectsize: {
5029 // If we don't know by now, we're never going to know.
5030 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5032 assert(CI && "Non-constant type in __builtin_object_size?");
5034 SDValue Arg = getValue(I.getCalledValue());
5035 EVT Ty = Arg.getValueType();
5038 Res = DAG.getConstant(-1ULL, Ty);
5040 Res = DAG.getConstant(0, Ty);
5045 case Intrinsic::annotation:
5046 case Intrinsic::ptr_annotation:
5047 // Drop the intrinsic, but forward the value
5048 setValue(&I, getValue(I.getOperand(0)));
5050 case Intrinsic::var_annotation:
5051 // Discard annotate attributes
5054 case Intrinsic::init_trampoline: {
5055 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5059 Ops[1] = getValue(I.getArgOperand(0));
5060 Ops[2] = getValue(I.getArgOperand(1));
5061 Ops[3] = getValue(I.getArgOperand(2));
5062 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5063 Ops[5] = DAG.getSrcValue(F);
5065 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5070 case Intrinsic::adjust_trampoline: {
5071 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5072 TLI->getPointerTy(),
5073 getValue(I.getArgOperand(0))));
5076 case Intrinsic::gcroot:
5078 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5079 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5081 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5082 GFI->addStackRoot(FI->getIndex(), TypeMap);
5085 case Intrinsic::gcread:
5086 case Intrinsic::gcwrite:
5087 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5088 case Intrinsic::flt_rounds:
5089 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5092 case Intrinsic::expect: {
5093 // Just replace __builtin_expect(exp, c) with EXP.
5094 setValue(&I, getValue(I.getArgOperand(0)));
5098 case Intrinsic::debugtrap:
5099 case Intrinsic::trap: {
5100 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5101 if (TrapFuncName.empty()) {
5102 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5103 ISD::TRAP : ISD::DEBUGTRAP;
5104 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5107 TargetLowering::ArgListTy Args;
5109 CallLoweringInfo CLI(getRoot(), I.getType(),
5110 false, false, false, false, 0, CallingConv::C,
5111 /*isTailCall=*/false,
5112 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5113 DAG.getExternalSymbol(TrapFuncName.data(),
5114 TLI->getPointerTy()),
5116 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5117 DAG.setRoot(Result.second);
5121 case Intrinsic::uadd_with_overflow:
5122 case Intrinsic::sadd_with_overflow:
5123 case Intrinsic::usub_with_overflow:
5124 case Intrinsic::ssub_with_overflow:
5125 case Intrinsic::umul_with_overflow:
5126 case Intrinsic::smul_with_overflow: {
5128 switch (Intrinsic) {
5129 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5130 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5131 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5132 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5133 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5134 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5135 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5137 SDValue Op1 = getValue(I.getArgOperand(0));
5138 SDValue Op2 = getValue(I.getArgOperand(1));
5140 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5141 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5144 case Intrinsic::prefetch: {
5146 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5148 Ops[1] = getValue(I.getArgOperand(0));
5149 Ops[2] = getValue(I.getArgOperand(1));
5150 Ops[3] = getValue(I.getArgOperand(2));
5151 Ops[4] = getValue(I.getArgOperand(3));
5152 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5153 DAG.getVTList(MVT::Other),
5155 EVT::getIntegerVT(*Context, 8),
5156 MachinePointerInfo(I.getArgOperand(0)),
5158 false, /* volatile */
5160 rw==1)); /* write */
5163 case Intrinsic::lifetime_start:
5164 case Intrinsic::lifetime_end: {
5165 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5166 // Stack coloring is not enabled in O0, discard region information.
5167 if (TM.getOptLevel() == CodeGenOpt::None)
5170 SmallVector<Value *, 4> Allocas;
5171 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5173 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5174 E = Allocas.end(); Object != E; ++Object) {
5175 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5177 // Could not find an Alloca.
5178 if (!LifetimeObject)
5181 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5185 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5186 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5188 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5193 case Intrinsic::invariant_start:
5194 // Discard region information.
5195 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5197 case Intrinsic::invariant_end:
5198 // Discard region information.
5200 case Intrinsic::donothing:
5206 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5208 MachineBasicBlock *LandingPad) {
5209 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5210 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5211 Type *RetTy = FTy->getReturnType();
5212 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5213 MCSymbol *BeginLabel = 0;
5215 TargetLowering::ArgListTy Args;
5216 TargetLowering::ArgListEntry Entry;
5217 Args.reserve(CS.arg_size());
5219 // Check whether the function can return without sret-demotion.
5220 SmallVector<ISD::OutputArg, 4> Outs;
5221 const TargetLowering *TLI = TM.getTargetLowering();
5222 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5224 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5225 DAG.getMachineFunction(),
5226 FTy->isVarArg(), Outs,
5229 SDValue DemoteStackSlot;
5230 int DemoteStackIdx = -100;
5232 if (!CanLowerReturn) {
5233 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5234 FTy->getReturnType());
5235 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5236 FTy->getReturnType());
5237 MachineFunction &MF = DAG.getMachineFunction();
5238 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5239 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5241 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5242 Entry.Node = DemoteStackSlot;
5243 Entry.Ty = StackSlotPtrType;
5244 Entry.isSExt = false;
5245 Entry.isZExt = false;
5246 Entry.isInReg = false;
5247 Entry.isSRet = true;
5248 Entry.isNest = false;
5249 Entry.isByVal = false;
5250 Entry.isReturned = false;
5251 Entry.Alignment = Align;
5252 Args.push_back(Entry);
5253 RetTy = Type::getVoidTy(FTy->getContext());
5256 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5258 const Value *V = *i;
5261 if (V->getType()->isEmptyTy())
5264 SDValue ArgNode = getValue(V);
5265 Entry.Node = ArgNode; Entry.Ty = V->getType();
5267 unsigned attrInd = i - CS.arg_begin() + 1;
5268 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5269 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5270 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5271 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5272 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5273 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5274 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned);
5275 Entry.Alignment = CS.getParamAlignment(attrInd);
5276 Args.push_back(Entry);
5280 // Insert a label before the invoke call to mark the try range. This can be
5281 // used to detect deletion of the invoke via the MachineModuleInfo.
5282 BeginLabel = MMI.getContext().CreateTempSymbol();
5284 // For SjLj, keep track of which landing pads go with which invokes
5285 // so as to maintain the ordering of pads in the LSDA.
5286 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5287 if (CallSiteIndex) {
5288 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5289 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5291 // Now that the call site is handled, stop tracking it.
5292 MMI.setCurrentCallSite(0);
5295 // Both PendingLoads and PendingExports must be flushed here;
5296 // this call might not return.
5298 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5301 // Check if target-independent constraints permit a tail call here.
5302 // Target-dependent constraints are checked within TLI->LowerCallTo.
5303 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5307 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5309 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5310 assert((isTailCall || Result.second.getNode()) &&
5311 "Non-null chain expected with non-tail call!");
5312 assert((Result.second.getNode() || !Result.first.getNode()) &&
5313 "Null value expected with tail call!");
5314 if (Result.first.getNode()) {
5315 setValue(CS.getInstruction(), Result.first);
5316 } else if (!CanLowerReturn && Result.second.getNode()) {
5317 // The instruction result is the result of loading from the
5318 // hidden sret parameter.
5319 SmallVector<EVT, 1> PVTs;
5320 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5322 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5323 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5324 EVT PtrVT = PVTs[0];
5326 SmallVector<EVT, 4> RetTys;
5327 SmallVector<uint64_t, 4> Offsets;
5328 RetTy = FTy->getReturnType();
5329 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5331 unsigned NumValues = RetTys.size();
5332 SmallVector<SDValue, 4> Values(NumValues);
5333 SmallVector<SDValue, 4> Chains(NumValues);
5335 for (unsigned i = 0; i < NumValues; ++i) {
5336 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5338 DAG.getConstant(Offsets[i], PtrVT));
5339 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5340 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5341 false, false, false, 1);
5343 Chains[i] = L.getValue(1);
5346 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5347 MVT::Other, &Chains[0], NumValues);
5348 PendingLoads.push_back(Chain);
5350 setValue(CS.getInstruction(),
5351 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5352 DAG.getVTList(&RetTys[0], RetTys.size()),
5353 &Values[0], Values.size()));
5356 if (!Result.second.getNode()) {
5357 // As a special case, a null chain means that a tail call has been emitted and
5358 // the DAG root is already updated.
5361 DAG.setRoot(Result.second);
5365 // Insert a label at the end of the invoke call to mark the try range. This
5366 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5367 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5368 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5370 // Inform MachineModuleInfo of range.
5371 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5375 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5376 /// value is equal or not-equal to zero.
5377 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5378 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5380 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5381 if (IC->isEquality())
5382 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5383 if (C->isNullValue())
5385 // Unknown instruction.
5391 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5393 SelectionDAGBuilder &Builder) {
5395 // Check to see if this load can be trivially constant folded, e.g. if the
5396 // input is from a string literal.
5397 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5398 // Cast pointer to the type we really want to load.
5399 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5400 PointerType::getUnqual(LoadTy));
5402 if (const Constant *LoadCst =
5403 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5405 return Builder.getValue(LoadCst);
5408 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5409 // still constant memory, the input chain can be the entry node.
5411 bool ConstantMemory = false;
5413 // Do not serialize (non-volatile) loads of constant memory with anything.
5414 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5415 Root = Builder.DAG.getEntryNode();
5416 ConstantMemory = true;
5418 // Do not serialize non-volatile loads against each other.
5419 Root = Builder.DAG.getRoot();
5422 SDValue Ptr = Builder.getValue(PtrVal);
5423 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5424 Ptr, MachinePointerInfo(PtrVal),
5426 false /*nontemporal*/,
5427 false /*isinvariant*/, 1 /* align=1 */);
5429 if (!ConstantMemory)
5430 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5435 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5436 /// If so, return true and lower it, otherwise return false and it will be
5437 /// lowered like a normal call.
5438 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5439 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5440 if (I.getNumArgOperands() != 3)
5443 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5444 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5445 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5446 !I.getType()->isIntegerTy())
5449 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5451 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5452 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5453 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5454 bool ActuallyDoIt = true;
5457 switch (Size->getZExtValue()) {
5459 LoadVT = MVT::Other;
5461 ActuallyDoIt = false;
5465 LoadTy = Type::getInt16Ty(Size->getContext());
5469 LoadTy = Type::getInt32Ty(Size->getContext());
5473 LoadTy = Type::getInt64Ty(Size->getContext());
5477 LoadVT = MVT::v4i32;
5478 LoadTy = Type::getInt32Ty(Size->getContext());
5479 LoadTy = VectorType::get(LoadTy, 4);
5484 // This turns into unaligned loads. We only do this if the target natively
5485 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5486 // we'll only produce a small number of byte loads.
5488 // Require that we can find a legal MVT, and only do this if the target
5489 // supports unaligned loads of that type. Expanding into byte loads would
5491 const TargetLowering *TLI = TM.getTargetLowering();
5492 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5493 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5494 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5495 if (!TLI->isTypeLegal(LoadVT) ||!TLI->allowsUnalignedMemoryAccesses(LoadVT))
5496 ActuallyDoIt = false;
5500 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5501 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5503 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5505 EVT CallVT = TLI->getValueType(I.getType(), true);
5506 setValue(&I, DAG.getZExtOrTrunc(Res, getCurSDLoc(), CallVT));
5515 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5516 /// operation (as expected), translate it to an SDNode with the specified opcode
5517 /// and return true.
5518 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5520 // Sanity check that it really is a unary floating-point call.
5521 if (I.getNumArgOperands() != 1 ||
5522 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5523 I.getType() != I.getArgOperand(0)->getType() ||
5524 !I.onlyReadsMemory())
5527 SDValue Tmp = getValue(I.getArgOperand(0));
5528 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5532 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5533 // Handle inline assembly differently.
5534 if (isa<InlineAsm>(I.getCalledValue())) {
5539 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5540 ComputeUsesVAFloatArgument(I, &MMI);
5542 const char *RenameFn = 0;
5543 if (Function *F = I.getCalledFunction()) {
5544 if (F->isDeclaration()) {
5545 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5546 if (unsigned IID = II->getIntrinsicID(F)) {
5547 RenameFn = visitIntrinsicCall(I, IID);
5552 if (unsigned IID = F->getIntrinsicID()) {
5553 RenameFn = visitIntrinsicCall(I, IID);
5559 // Check for well-known libc/libm calls. If the function is internal, it
5560 // can't be a library call.
5562 if (!F->hasLocalLinkage() && F->hasName() &&
5563 LibInfo->getLibFunc(F->getName(), Func) &&
5564 LibInfo->hasOptimizedCodeGen(Func)) {
5567 case LibFunc::copysign:
5568 case LibFunc::copysignf:
5569 case LibFunc::copysignl:
5570 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5571 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5572 I.getType() == I.getArgOperand(0)->getType() &&
5573 I.getType() == I.getArgOperand(1)->getType() &&
5574 I.onlyReadsMemory()) {
5575 SDValue LHS = getValue(I.getArgOperand(0));
5576 SDValue RHS = getValue(I.getArgOperand(1));
5577 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5578 LHS.getValueType(), LHS, RHS));
5583 case LibFunc::fabsf:
5584 case LibFunc::fabsl:
5585 if (visitUnaryFloatCall(I, ISD::FABS))
5591 if (visitUnaryFloatCall(I, ISD::FSIN))
5597 if (visitUnaryFloatCall(I, ISD::FCOS))
5601 case LibFunc::sqrtf:
5602 case LibFunc::sqrtl:
5603 case LibFunc::sqrt_finite:
5604 case LibFunc::sqrtf_finite:
5605 case LibFunc::sqrtl_finite:
5606 if (visitUnaryFloatCall(I, ISD::FSQRT))
5609 case LibFunc::floor:
5610 case LibFunc::floorf:
5611 case LibFunc::floorl:
5612 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5615 case LibFunc::nearbyint:
5616 case LibFunc::nearbyintf:
5617 case LibFunc::nearbyintl:
5618 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5622 case LibFunc::ceilf:
5623 case LibFunc::ceill:
5624 if (visitUnaryFloatCall(I, ISD::FCEIL))
5628 case LibFunc::rintf:
5629 case LibFunc::rintl:
5630 if (visitUnaryFloatCall(I, ISD::FRINT))
5633 case LibFunc::trunc:
5634 case LibFunc::truncf:
5635 case LibFunc::truncl:
5636 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5640 case LibFunc::log2f:
5641 case LibFunc::log2l:
5642 if (visitUnaryFloatCall(I, ISD::FLOG2))
5646 case LibFunc::exp2f:
5647 case LibFunc::exp2l:
5648 if (visitUnaryFloatCall(I, ISD::FEXP2))
5651 case LibFunc::memcmp:
5652 if (visitMemCmpCall(I))
5661 Callee = getValue(I.getCalledValue());
5663 Callee = DAG.getExternalSymbol(RenameFn,
5664 TM.getTargetLowering()->getPointerTy());
5666 // Check if we can potentially perform a tail call. More detailed checking is
5667 // be done within LowerCallTo, after more information about the call is known.
5668 LowerCallTo(&I, Callee, I.isTailCall());
5673 /// AsmOperandInfo - This contains information for each constraint that we are
5675 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5677 /// CallOperand - If this is the result output operand or a clobber
5678 /// this is null, otherwise it is the incoming operand to the CallInst.
5679 /// This gets modified as the asm is processed.
5680 SDValue CallOperand;
5682 /// AssignedRegs - If this is a register or register class operand, this
5683 /// contains the set of register corresponding to the operand.
5684 RegsForValue AssignedRegs;
5686 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5687 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5690 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5691 /// corresponds to. If there is no Value* for this operand, it returns
5693 EVT getCallOperandValEVT(LLVMContext &Context,
5694 const TargetLowering &TLI,
5695 const DataLayout *TD) const {
5696 if (CallOperandVal == 0) return MVT::Other;
5698 if (isa<BasicBlock>(CallOperandVal))
5699 return TLI.getPointerTy();
5701 llvm::Type *OpTy = CallOperandVal->getType();
5703 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5704 // If this is an indirect operand, the operand is a pointer to the
5707 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5709 report_fatal_error("Indirect operand for inline asm not a pointer!");
5710 OpTy = PtrTy->getElementType();
5713 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5714 if (StructType *STy = dyn_cast<StructType>(OpTy))
5715 if (STy->getNumElements() == 1)
5716 OpTy = STy->getElementType(0);
5718 // If OpTy is not a single value, it may be a struct/union that we
5719 // can tile with integers.
5720 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5721 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5730 OpTy = IntegerType::get(Context, BitSize);
5735 return TLI.getValueType(OpTy, true);
5739 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5741 } // end anonymous namespace
5743 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5744 /// specified operand. We prefer to assign virtual registers, to allow the
5745 /// register allocator to handle the assignment process. However, if the asm
5746 /// uses features that we can't model on machineinstrs, we have SDISel do the
5747 /// allocation. This produces generally horrible, but correct, code.
5749 /// OpInfo describes the operand.
5751 static void GetRegistersForValue(SelectionDAG &DAG,
5752 const TargetLowering &TLI,
5754 SDISelAsmOperandInfo &OpInfo) {
5755 LLVMContext &Context = *DAG.getContext();
5757 MachineFunction &MF = DAG.getMachineFunction();
5758 SmallVector<unsigned, 4> Regs;
5760 // If this is a constraint for a single physreg, or a constraint for a
5761 // register class, find it.
5762 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5763 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5764 OpInfo.ConstraintVT);
5766 unsigned NumRegs = 1;
5767 if (OpInfo.ConstraintVT != MVT::Other) {
5768 // If this is a FP input in an integer register (or visa versa) insert a bit
5769 // cast of the input value. More generally, handle any case where the input
5770 // value disagrees with the register class we plan to stick this in.
5771 if (OpInfo.Type == InlineAsm::isInput &&
5772 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5773 // Try to convert to the first EVT that the reg class contains. If the
5774 // types are identical size, use a bitcast to convert (e.g. two differing
5776 MVT RegVT = *PhysReg.second->vt_begin();
5777 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5778 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5779 RegVT, OpInfo.CallOperand);
5780 OpInfo.ConstraintVT = RegVT;
5781 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5782 // If the input is a FP value and we want it in FP registers, do a
5783 // bitcast to the corresponding integer type. This turns an f64 value
5784 // into i64, which can be passed with two i32 values on a 32-bit
5786 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5787 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5788 RegVT, OpInfo.CallOperand);
5789 OpInfo.ConstraintVT = RegVT;
5793 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5797 EVT ValueVT = OpInfo.ConstraintVT;
5799 // If this is a constraint for a specific physical register, like {r17},
5801 if (unsigned AssignedReg = PhysReg.first) {
5802 const TargetRegisterClass *RC = PhysReg.second;
5803 if (OpInfo.ConstraintVT == MVT::Other)
5804 ValueVT = *RC->vt_begin();
5806 // Get the actual register value type. This is important, because the user
5807 // may have asked for (e.g.) the AX register in i32 type. We need to
5808 // remember that AX is actually i16 to get the right extension.
5809 RegVT = *RC->vt_begin();
5811 // This is a explicit reference to a physical register.
5812 Regs.push_back(AssignedReg);
5814 // If this is an expanded reference, add the rest of the regs to Regs.
5816 TargetRegisterClass::iterator I = RC->begin();
5817 for (; *I != AssignedReg; ++I)
5818 assert(I != RC->end() && "Didn't find reg!");
5820 // Already added the first reg.
5822 for (; NumRegs; --NumRegs, ++I) {
5823 assert(I != RC->end() && "Ran out of registers to allocate!");
5828 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5832 // Otherwise, if this was a reference to an LLVM register class, create vregs
5833 // for this reference.
5834 if (const TargetRegisterClass *RC = PhysReg.second) {
5835 RegVT = *RC->vt_begin();
5836 if (OpInfo.ConstraintVT == MVT::Other)
5839 // Create the appropriate number of virtual registers.
5840 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5841 for (; NumRegs; --NumRegs)
5842 Regs.push_back(RegInfo.createVirtualRegister(RC));
5844 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5848 // Otherwise, we couldn't allocate enough registers for this.
5851 /// visitInlineAsm - Handle a call to an InlineAsm object.
5853 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5854 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5856 /// ConstraintOperands - Information about all of the constraints.
5857 SDISelAsmOperandInfoVector ConstraintOperands;
5859 const TargetLowering *TLI = TM.getTargetLowering();
5860 TargetLowering::AsmOperandInfoVector
5861 TargetConstraints = TLI->ParseConstraints(CS);
5863 bool hasMemory = false;
5865 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5866 unsigned ResNo = 0; // ResNo - The result number of the next output.
5867 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5868 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5869 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5871 MVT OpVT = MVT::Other;
5873 // Compute the value type for each operand.
5874 switch (OpInfo.Type) {
5875 case InlineAsm::isOutput:
5876 // Indirect outputs just consume an argument.
5877 if (OpInfo.isIndirect) {
5878 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5882 // The return value of the call is this value. As such, there is no
5883 // corresponding argument.
5884 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5885 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5886 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
5888 assert(ResNo == 0 && "Asm only has one result!");
5889 OpVT = TLI->getSimpleValueType(CS.getType());
5893 case InlineAsm::isInput:
5894 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5896 case InlineAsm::isClobber:
5901 // If this is an input or an indirect output, process the call argument.
5902 // BasicBlocks are labels, currently appearing only in asm's.
5903 if (OpInfo.CallOperandVal) {
5904 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5905 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5907 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5910 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD).
5914 OpInfo.ConstraintVT = OpVT;
5916 // Indirect operand accesses access memory.
5917 if (OpInfo.isIndirect)
5920 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5921 TargetLowering::ConstraintType
5922 CType = TLI->getConstraintType(OpInfo.Codes[j]);
5923 if (CType == TargetLowering::C_Memory) {
5931 SDValue Chain, Flag;
5933 // We won't need to flush pending loads if this asm doesn't touch
5934 // memory and is nonvolatile.
5935 if (hasMemory || IA->hasSideEffects())
5938 Chain = DAG.getRoot();
5940 // Second pass over the constraints: compute which constraint option to use
5941 // and assign registers to constraints that want a specific physreg.
5942 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5943 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5945 // If this is an output operand with a matching input operand, look up the
5946 // matching input. If their types mismatch, e.g. one is an integer, the
5947 // other is floating point, or their sizes are different, flag it as an
5949 if (OpInfo.hasMatchingInput()) {
5950 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5952 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5953 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5954 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5955 OpInfo.ConstraintVT);
5956 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5957 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
5958 Input.ConstraintVT);
5959 if ((OpInfo.ConstraintVT.isInteger() !=
5960 Input.ConstraintVT.isInteger()) ||
5961 (MatchRC.second != InputRC.second)) {
5962 report_fatal_error("Unsupported asm: input constraint"
5963 " with a matching output constraint of"
5964 " incompatible type!");
5966 Input.ConstraintVT = OpInfo.ConstraintVT;
5970 // Compute the constraint code and ConstraintType to use.
5971 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5973 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5974 OpInfo.Type == InlineAsm::isClobber)
5977 // If this is a memory input, and if the operand is not indirect, do what we
5978 // need to to provide an address for the memory input.
5979 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5980 !OpInfo.isIndirect) {
5981 assert((OpInfo.isMultipleAlternative ||
5982 (OpInfo.Type == InlineAsm::isInput)) &&
5983 "Can only indirectify direct input operands!");
5985 // Memory operands really want the address of the value. If we don't have
5986 // an indirect input, put it in the constpool if we can, otherwise spill
5987 // it to a stack slot.
5988 // TODO: This isn't quite right. We need to handle these according to
5989 // the addressing mode that the constraint wants. Also, this may take
5990 // an additional register for the computation and we don't want that
5993 // If the operand is a float, integer, or vector constant, spill to a
5994 // constant pool entry to get its address.
5995 const Value *OpVal = OpInfo.CallOperandVal;
5996 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5997 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5998 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5999 TLI->getPointerTy());
6001 // Otherwise, create a stack slot and emit a store to it before the
6003 Type *Ty = OpVal->getType();
6004 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6005 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6006 MachineFunction &MF = DAG.getMachineFunction();
6007 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6008 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6009 Chain = DAG.getStore(Chain, getCurSDLoc(),
6010 OpInfo.CallOperand, StackSlot,
6011 MachinePointerInfo::getFixedStack(SSFI),
6013 OpInfo.CallOperand = StackSlot;
6016 // There is no longer a Value* corresponding to this operand.
6017 OpInfo.CallOperandVal = 0;
6019 // It is now an indirect operand.
6020 OpInfo.isIndirect = true;
6023 // If this constraint is for a specific register, allocate it before
6025 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6026 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6029 // Second pass - Loop over all of the operands, assigning virtual or physregs
6030 // to register class operands.
6031 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6032 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6034 // C_Register operands have already been allocated, Other/Memory don't need
6036 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6037 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6040 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6041 std::vector<SDValue> AsmNodeOperands;
6042 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6043 AsmNodeOperands.push_back(
6044 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6045 TLI->getPointerTy()));
6047 // If we have a !srcloc metadata node associated with it, we want to attach
6048 // this to the ultimately generated inline asm machineinstr. To do this, we
6049 // pass in the third operand as this (potentially null) inline asm MDNode.
6050 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6051 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6053 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6054 // bits as operand 3.
6055 unsigned ExtraInfo = 0;
6056 if (IA->hasSideEffects())
6057 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6058 if (IA->isAlignStack())
6059 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6060 // Set the asm dialect.
6061 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6063 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6064 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6065 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6067 // Compute the constraint code and ConstraintType to use.
6068 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6070 // Ideally, we would only check against memory constraints. However, the
6071 // meaning of an other constraint can be target-specific and we can't easily
6072 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6073 // for other constriants as well.
6074 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6075 OpInfo.ConstraintType == TargetLowering::C_Other) {
6076 if (OpInfo.Type == InlineAsm::isInput)
6077 ExtraInfo |= InlineAsm::Extra_MayLoad;
6078 else if (OpInfo.Type == InlineAsm::isOutput)
6079 ExtraInfo |= InlineAsm::Extra_MayStore;
6080 else if (OpInfo.Type == InlineAsm::isClobber)
6081 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6085 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6086 TLI->getPointerTy()));
6088 // Loop over all of the inputs, copying the operand values into the
6089 // appropriate registers and processing the output regs.
6090 RegsForValue RetValRegs;
6092 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6093 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6095 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6096 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6098 switch (OpInfo.Type) {
6099 case InlineAsm::isOutput: {
6100 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6101 OpInfo.ConstraintType != TargetLowering::C_Register) {
6102 // Memory output, or 'other' output (e.g. 'X' constraint).
6103 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6105 // Add information to the INLINEASM node to know about this output.
6106 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6107 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6108 TLI->getPointerTy()));
6109 AsmNodeOperands.push_back(OpInfo.CallOperand);
6113 // Otherwise, this is a register or register class output.
6115 // Copy the output from the appropriate register. Find a register that
6117 if (OpInfo.AssignedRegs.Regs.empty()) {
6118 LLVMContext &Ctx = *DAG.getContext();
6119 Ctx.emitError(CS.getInstruction(),
6120 "couldn't allocate output register for constraint '" +
6121 Twine(OpInfo.ConstraintCode) + "'");
6125 // If this is an indirect operand, store through the pointer after the
6127 if (OpInfo.isIndirect) {
6128 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6129 OpInfo.CallOperandVal));
6131 // This is the result value of the call.
6132 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6133 // Concatenate this output onto the outputs list.
6134 RetValRegs.append(OpInfo.AssignedRegs);
6137 // Add information to the INLINEASM node to know that this register is
6139 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6140 InlineAsm::Kind_RegDefEarlyClobber :
6141 InlineAsm::Kind_RegDef,
6148 case InlineAsm::isInput: {
6149 SDValue InOperandVal = OpInfo.CallOperand;
6151 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6152 // If this is required to match an output register we have already set,
6153 // just use its register.
6154 unsigned OperandNo = OpInfo.getMatchedOperand();
6156 // Scan until we find the definition we already emitted of this operand.
6157 // When we find it, create a RegsForValue operand.
6158 unsigned CurOp = InlineAsm::Op_FirstOperand;
6159 for (; OperandNo; --OperandNo) {
6160 // Advance to the next operand.
6162 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6163 assert((InlineAsm::isRegDefKind(OpFlag) ||
6164 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6165 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6166 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6170 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6171 if (InlineAsm::isRegDefKind(OpFlag) ||
6172 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6173 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6174 if (OpInfo.isIndirect) {
6175 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6176 LLVMContext &Ctx = *DAG.getContext();
6177 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6178 " don't know how to handle tied "
6179 "indirect register inputs");
6180 report_fatal_error("Cannot handle indirect register inputs!");
6183 RegsForValue MatchedRegs;
6184 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6185 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6186 MatchedRegs.RegVTs.push_back(RegVT);
6187 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6188 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6190 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6191 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6193 LLVMContext &Ctx = *DAG.getContext();
6194 Ctx.emitError(CS.getInstruction(), "inline asm error: This value"
6195 " type register class is not natively supported!");
6196 report_fatal_error("inline asm error: This value type register "
6197 "class is not natively supported!");
6200 // Use the produced MatchedRegs object to
6201 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6202 Chain, &Flag, CS.getInstruction());
6203 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6204 true, OpInfo.getMatchedOperand(),
6205 DAG, AsmNodeOperands);
6209 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6210 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6211 "Unexpected number of operands");
6212 // Add information to the INLINEASM node to know about this input.
6213 // See InlineAsm.h isUseOperandTiedToDef.
6214 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6215 OpInfo.getMatchedOperand());
6216 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6217 TLI->getPointerTy()));
6218 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6222 // Treat indirect 'X' constraint as memory.
6223 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6225 OpInfo.ConstraintType = TargetLowering::C_Memory;
6227 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6228 std::vector<SDValue> Ops;
6229 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6232 LLVMContext &Ctx = *DAG.getContext();
6233 Ctx.emitError(CS.getInstruction(),
6234 "invalid operand for inline asm constraint '" +
6235 Twine(OpInfo.ConstraintCode) + "'");
6239 // Add information to the INLINEASM node to know about this input.
6240 unsigned ResOpType =
6241 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6242 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6243 TLI->getPointerTy()));
6244 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6248 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6249 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6250 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6251 "Memory operands expect pointer values");
6253 // Add information to the INLINEASM node to know about this input.
6254 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6255 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6256 TLI->getPointerTy()));
6257 AsmNodeOperands.push_back(InOperandVal);
6261 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6262 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6263 "Unknown constraint type!");
6265 // TODO: Support this.
6266 if (OpInfo.isIndirect) {
6267 LLVMContext &Ctx = *DAG.getContext();
6268 Ctx.emitError(CS.getInstruction(),
6269 "Don't know how to handle indirect register inputs yet "
6270 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6274 // Copy the input into the appropriate registers.
6275 if (OpInfo.AssignedRegs.Regs.empty()) {
6276 LLVMContext &Ctx = *DAG.getContext();
6277 Ctx.emitError(CS.getInstruction(),
6278 "couldn't allocate input reg for constraint '" +
6279 Twine(OpInfo.ConstraintCode) + "'");
6283 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6284 Chain, &Flag, CS.getInstruction());
6286 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6287 DAG, AsmNodeOperands);
6290 case InlineAsm::isClobber: {
6291 // Add the clobbered value to the operand list, so that the register
6292 // allocator is aware that the physreg got clobbered.
6293 if (!OpInfo.AssignedRegs.Regs.empty())
6294 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6302 // Finish up input operands. Set the input chain and add the flag last.
6303 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6304 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6306 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6307 DAG.getVTList(MVT::Other, MVT::Glue),
6308 &AsmNodeOperands[0], AsmNodeOperands.size());
6309 Flag = Chain.getValue(1);
6311 // If this asm returns a register value, copy the result from that register
6312 // and set it as the value of the call.
6313 if (!RetValRegs.Regs.empty()) {
6314 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6315 Chain, &Flag, CS.getInstruction());
6317 // FIXME: Why don't we do this for inline asms with MRVs?
6318 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6319 EVT ResultType = TLI->getValueType(CS.getType());
6321 // If any of the results of the inline asm is a vector, it may have the
6322 // wrong width/num elts. This can happen for register classes that can
6323 // contain multiple different value types. The preg or vreg allocated may
6324 // not have the same VT as was expected. Convert it to the right type
6325 // with bit_convert.
6326 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6327 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6330 } else if (ResultType != Val.getValueType() &&
6331 ResultType.isInteger() && Val.getValueType().isInteger()) {
6332 // If a result value was tied to an input value, the computed result may
6333 // have a wider width than the expected result. Extract the relevant
6335 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6338 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6341 setValue(CS.getInstruction(), Val);
6342 // Don't need to use this as a chain in this case.
6343 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6347 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6349 // Process indirect outputs, first output all of the flagged copies out of
6351 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6352 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6353 const Value *Ptr = IndirectStoresToEmit[i].second;
6354 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6356 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6359 // Emit the non-flagged stores from the physregs.
6360 SmallVector<SDValue, 8> OutChains;
6361 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6362 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6363 StoresToEmit[i].first,
6364 getValue(StoresToEmit[i].second),
6365 MachinePointerInfo(StoresToEmit[i].second),
6367 OutChains.push_back(Val);
6370 if (!OutChains.empty())
6371 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6372 &OutChains[0], OutChains.size());
6377 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6378 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6379 MVT::Other, getRoot(),
6380 getValue(I.getArgOperand(0)),
6381 DAG.getSrcValue(I.getArgOperand(0))));
6384 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6385 const TargetLowering *TLI = TM.getTargetLowering();
6386 const DataLayout &TD = *TLI->getDataLayout();
6387 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6388 getRoot(), getValue(I.getOperand(0)),
6389 DAG.getSrcValue(I.getOperand(0)),
6390 TD.getABITypeAlignment(I.getType()));
6392 DAG.setRoot(V.getValue(1));
6395 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6396 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6397 MVT::Other, getRoot(),
6398 getValue(I.getArgOperand(0)),
6399 DAG.getSrcValue(I.getArgOperand(0))));
6402 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6403 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6404 MVT::Other, getRoot(),
6405 getValue(I.getArgOperand(0)),
6406 getValue(I.getArgOperand(1)),
6407 DAG.getSrcValue(I.getArgOperand(0)),
6408 DAG.getSrcValue(I.getArgOperand(1))));
6411 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6412 /// implementation, which just calls LowerCall.
6413 /// FIXME: When all targets are
6414 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6415 std::pair<SDValue, SDValue>
6416 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6417 // Handle the incoming return values from the call.
6419 SmallVector<EVT, 4> RetTys;
6420 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6421 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6423 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6424 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6425 for (unsigned i = 0; i != NumRegs; ++i) {
6426 ISD::InputArg MyFlags;
6427 MyFlags.VT = RegisterVT;
6428 MyFlags.Used = CLI.IsReturnValueUsed;
6430 MyFlags.Flags.setSExt();
6432 MyFlags.Flags.setZExt();
6434 MyFlags.Flags.setInReg();
6435 CLI.Ins.push_back(MyFlags);
6439 // Handle all of the outgoing arguments.
6441 CLI.OutVals.clear();
6442 ArgListTy &Args = CLI.Args;
6443 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6444 SmallVector<EVT, 4> ValueVTs;
6445 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6446 for (unsigned Value = 0, NumValues = ValueVTs.size();
6447 Value != NumValues; ++Value) {
6448 EVT VT = ValueVTs[Value];
6449 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6450 SDValue Op = SDValue(Args[i].Node.getNode(),
6451 Args[i].Node.getResNo() + Value);
6452 ISD::ArgFlagsTy Flags;
6453 unsigned OriginalAlignment =
6454 getDataLayout()->getABITypeAlignment(ArgTy);
6460 if (Args[i].isInReg)
6464 if (Args[i].isByVal) {
6466 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6467 Type *ElementTy = Ty->getElementType();
6468 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6469 // For ByVal, alignment should come from FE. BE will guess if this
6470 // info is not there but there are cases it cannot get right.
6471 unsigned FrameAlign;
6472 if (Args[i].Alignment)
6473 FrameAlign = Args[i].Alignment;
6475 FrameAlign = getByValTypeAlignment(ElementTy);
6476 Flags.setByValAlign(FrameAlign);
6480 Flags.setOrigAlign(OriginalAlignment);
6482 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6483 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6484 SmallVector<SDValue, 4> Parts(NumParts);
6485 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6488 ExtendKind = ISD::SIGN_EXTEND;
6489 else if (Args[i].isZExt)
6490 ExtendKind = ISD::ZERO_EXTEND;
6492 // Conservatively only handle 'returned' on non-vectors for now
6493 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6494 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6495 "unexpected use of 'returned'");
6496 // Before passing 'returned' to the target lowering code, ensure that
6497 // either the register MVT and the actual EVT are the same size or that
6498 // the return value and argument are extended in the same way; in these
6499 // cases it's safe to pass the argument register value unchanged as the
6500 // return register value (although it's at the target's option whether
6502 // TODO: allow code generation to take advantage of partially preserved
6503 // registers rather than clobbering the entire register when the
6504 // parameter extension method is not compatible with the return
6506 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6507 (ExtendKind != ISD::ANY_EXTEND &&
6508 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6509 Flags.setReturned();
6512 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6513 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6515 for (unsigned j = 0; j != NumParts; ++j) {
6516 // if it isn't first piece, alignment must be 1
6517 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6518 i < CLI.NumFixedArgs,
6519 i, j*Parts[j].getValueType().getStoreSize());
6520 if (NumParts > 1 && j == 0)
6521 MyFlags.Flags.setSplit();
6523 MyFlags.Flags.setOrigAlign(1);
6525 CLI.Outs.push_back(MyFlags);
6526 CLI.OutVals.push_back(Parts[j]);
6531 SmallVector<SDValue, 4> InVals;
6532 CLI.Chain = LowerCall(CLI, InVals);
6534 // Verify that the target's LowerCall behaved as expected.
6535 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6536 "LowerCall didn't return a valid chain!");
6537 assert((!CLI.IsTailCall || InVals.empty()) &&
6538 "LowerCall emitted a return value for a tail call!");
6539 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6540 "LowerCall didn't emit the correct number of values!");
6542 // For a tail call, the return value is merely live-out and there aren't
6543 // any nodes in the DAG representing it. Return a special value to
6544 // indicate that a tail call has been emitted and no more Instructions
6545 // should be processed in the current block.
6546 if (CLI.IsTailCall) {
6547 CLI.DAG.setRoot(CLI.Chain);
6548 return std::make_pair(SDValue(), SDValue());
6551 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6552 assert(InVals[i].getNode() &&
6553 "LowerCall emitted a null value!");
6554 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6555 "LowerCall emitted a value with the wrong type!");
6558 // Collect the legal value parts into potentially illegal values
6559 // that correspond to the original function's return values.
6560 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6562 AssertOp = ISD::AssertSext;
6563 else if (CLI.RetZExt)
6564 AssertOp = ISD::AssertZext;
6565 SmallVector<SDValue, 4> ReturnValues;
6566 unsigned CurReg = 0;
6567 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6569 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6570 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6572 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6573 NumRegs, RegisterVT, VT, NULL,
6578 // For a function returning void, there is no return value. We can't create
6579 // such a node, so we just return a null return value in that case. In
6580 // that case, nothing will actually look at the value.
6581 if (ReturnValues.empty())
6582 return std::make_pair(SDValue(), CLI.Chain);
6584 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6585 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6586 &ReturnValues[0], ReturnValues.size());
6587 return std::make_pair(Res, CLI.Chain);
6590 void TargetLowering::LowerOperationWrapper(SDNode *N,
6591 SmallVectorImpl<SDValue> &Results,
6592 SelectionDAG &DAG) const {
6593 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6595 Results.push_back(Res);
6598 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6599 llvm_unreachable("LowerOperation not implemented for this target!");
6603 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6604 SDValue Op = getNonRegisterValue(V);
6605 assert((Op.getOpcode() != ISD::CopyFromReg ||
6606 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6607 "Copy from a reg to the same reg!");
6608 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6610 const TargetLowering *TLI = TM.getTargetLowering();
6611 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
6612 SDValue Chain = DAG.getEntryNode();
6613 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
6614 PendingExports.push_back(Chain);
6617 #include "llvm/CodeGen/SelectionDAGISel.h"
6619 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6620 /// entry block, return true. This includes arguments used by switches, since
6621 /// the switch may expand into multiple basic blocks.
6622 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6623 // With FastISel active, we may be splitting blocks, so force creation
6624 // of virtual registers for all non-dead arguments.
6626 return A->use_empty();
6628 const BasicBlock *Entry = A->getParent()->begin();
6629 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6631 const User *U = *UI;
6632 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6633 return false; // Use not in entry block.
6638 void SelectionDAGISel::LowerArguments(const Function &F) {
6639 SelectionDAG &DAG = SDB->DAG;
6640 SDLoc dl = SDB->getCurSDLoc();
6641 const TargetLowering *TLI = getTargetLowering();
6642 const DataLayout *TD = TLI->getDataLayout();
6643 SmallVector<ISD::InputArg, 16> Ins;
6645 if (!FuncInfo->CanLowerReturn) {
6646 // Put in an sret pointer parameter before all the other parameters.
6647 SmallVector<EVT, 1> ValueVTs;
6648 ComputeValueVTs(*getTargetLowering(),
6649 PointerType::getUnqual(F.getReturnType()), ValueVTs);
6651 // NOTE: Assuming that a pointer will never break down to more than one VT
6653 ISD::ArgFlagsTy Flags;
6655 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
6656 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6657 Ins.push_back(RetArg);
6660 // Set up the incoming argument description vector.
6662 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6663 I != E; ++I, ++Idx) {
6664 SmallVector<EVT, 4> ValueVTs;
6665 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6666 bool isArgValueUsed = !I->use_empty();
6667 for (unsigned Value = 0, NumValues = ValueVTs.size();
6668 Value != NumValues; ++Value) {
6669 EVT VT = ValueVTs[Value];
6670 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6671 ISD::ArgFlagsTy Flags;
6672 unsigned OriginalAlignment =
6673 TD->getABITypeAlignment(ArgTy);
6675 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6677 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6679 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
6681 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
6683 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
6685 PointerType *Ty = cast<PointerType>(I->getType());
6686 Type *ElementTy = Ty->getElementType();
6687 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6688 // For ByVal, alignment should be passed from FE. BE will guess if
6689 // this info is not there but there are cases it cannot get right.
6690 unsigned FrameAlign;
6691 if (F.getParamAlignment(Idx))
6692 FrameAlign = F.getParamAlignment(Idx);
6694 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
6695 Flags.setByValAlign(FrameAlign);
6697 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
6699 Flags.setOrigAlign(OriginalAlignment);
6701 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6702 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
6703 for (unsigned i = 0; i != NumRegs; ++i) {
6704 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6705 Idx-1, i*RegisterVT.getStoreSize());
6706 if (NumRegs > 1 && i == 0)
6707 MyFlags.Flags.setSplit();
6708 // if it isn't first piece, alignment must be 1
6710 MyFlags.Flags.setOrigAlign(1);
6711 Ins.push_back(MyFlags);
6716 // Call the target to set up the argument values.
6717 SmallVector<SDValue, 8> InVals;
6718 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6722 // Verify that the target's LowerFormalArguments behaved as expected.
6723 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6724 "LowerFormalArguments didn't return a valid chain!");
6725 assert(InVals.size() == Ins.size() &&
6726 "LowerFormalArguments didn't emit the correct number of values!");
6728 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6729 assert(InVals[i].getNode() &&
6730 "LowerFormalArguments emitted a null value!");
6731 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6732 "LowerFormalArguments emitted a value with the wrong type!");
6736 // Update the DAG with the new chain value resulting from argument lowering.
6737 DAG.setRoot(NewRoot);
6739 // Set up the argument values.
6742 if (!FuncInfo->CanLowerReturn) {
6743 // Create a virtual register for the sret pointer, and put in a copy
6744 // from the sret argument into it.
6745 SmallVector<EVT, 1> ValueVTs;
6746 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6747 MVT VT = ValueVTs[0].getSimpleVT();
6748 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6749 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6750 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6751 RegVT, VT, NULL, AssertOp);
6753 MachineFunction& MF = SDB->DAG.getMachineFunction();
6754 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6755 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
6756 FuncInfo->DemoteRegister = SRetReg;
6757 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
6759 DAG.setRoot(NewRoot);
6761 // i indexes lowered arguments. Bump it past the hidden sret argument.
6762 // Idx indexes LLVM arguments. Don't touch it.
6766 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6768 SmallVector<SDValue, 4> ArgValues;
6769 SmallVector<EVT, 4> ValueVTs;
6770 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6771 unsigned NumValues = ValueVTs.size();
6773 // If this argument is unused then remember its value. It is used to generate
6774 // debugging information.
6775 if (I->use_empty() && NumValues) {
6776 SDB->setUnusedArgValue(I, InVals[i]);
6778 // Also remember any frame index for use in FastISel.
6779 if (FrameIndexSDNode *FI =
6780 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
6781 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6784 for (unsigned Val = 0; Val != NumValues; ++Val) {
6785 EVT VT = ValueVTs[Val];
6786 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6787 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
6789 if (!I->use_empty()) {
6790 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6791 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6792 AssertOp = ISD::AssertSext;
6793 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6794 AssertOp = ISD::AssertZext;
6796 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6797 NumParts, PartVT, VT,
6804 // We don't need to do anything else for unused arguments.
6805 if (ArgValues.empty())
6808 // Note down frame index.
6809 if (FrameIndexSDNode *FI =
6810 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6811 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6813 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6814 SDB->getCurSDLoc());
6816 SDB->setValue(I, Res);
6817 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6818 if (LoadSDNode *LNode =
6819 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6820 if (FrameIndexSDNode *FI =
6821 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6822 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6825 // If this argument is live outside of the entry block, insert a copy from
6826 // wherever we got it to the vreg that other BB's will reference it as.
6827 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6828 // If we can, though, try to skip creating an unnecessary vreg.
6829 // FIXME: This isn't very clean... it would be nice to make this more
6830 // general. It's also subtly incompatible with the hacks FastISel
6832 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6833 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6834 FuncInfo->ValueMap[I] = Reg;
6838 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6839 FuncInfo->InitializeRegForValue(I);
6840 SDB->CopyToExportRegsIfNeeded(I);
6844 assert(i == InVals.size() && "Argument register count mismatch!");
6846 // Finally, if the target has anything special to do, allow it to do so.
6847 // FIXME: this should insert code into the DAG!
6848 EmitFunctionEntryCode();
6851 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6852 /// ensure constants are generated when needed. Remember the virtual registers
6853 /// that need to be added to the Machine PHI nodes as input. We cannot just
6854 /// directly add them, because expansion might result in multiple MBB's for one
6855 /// BB. As such, the start of the BB might correspond to a different MBB than
6859 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6860 const TerminatorInst *TI = LLVMBB->getTerminator();
6862 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6864 // Check successor nodes' PHI nodes that expect a constant to be available
6866 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6867 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6868 if (!isa<PHINode>(SuccBB->begin())) continue;
6869 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6871 // If this terminator has multiple identical successors (common for
6872 // switches), only handle each succ once.
6873 if (!SuccsHandled.insert(SuccMBB)) continue;
6875 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6877 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6878 // nodes and Machine PHI nodes, but the incoming operands have not been
6880 for (BasicBlock::const_iterator I = SuccBB->begin();
6881 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6882 // Ignore dead phi's.
6883 if (PN->use_empty()) continue;
6886 if (PN->getType()->isEmptyTy())
6890 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6892 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6893 unsigned &RegOut = ConstantsOut[C];
6895 RegOut = FuncInfo.CreateRegs(C->getType());
6896 CopyValueToVirtualRegister(C, RegOut);
6900 DenseMap<const Value *, unsigned>::iterator I =
6901 FuncInfo.ValueMap.find(PHIOp);
6902 if (I != FuncInfo.ValueMap.end())
6905 assert(isa<AllocaInst>(PHIOp) &&
6906 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6907 "Didn't codegen value into a register!??");
6908 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6909 CopyValueToVirtualRegister(PHIOp, Reg);
6913 // Remember that this register needs to added to the machine PHI node as
6914 // the input for this MBB.
6915 SmallVector<EVT, 4> ValueVTs;
6916 const TargetLowering *TLI = TM.getTargetLowering();
6917 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
6918 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6919 EVT VT = ValueVTs[vti];
6920 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
6921 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6922 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6923 Reg += NumRegisters;
6928 ConstantsOut.clear();