1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "FunctionLoweringInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ConstantFolding.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/Module.h"
32 #include "llvm/CodeGen/FastISel.h"
33 #include "llvm/CodeGen/GCStrategy.h"
34 #include "llvm/CodeGen/GCMetadata.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/CodeGen/DwarfWriter.h"
44 #include "llvm/Analysis/DebugInfo.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
73 /// RegsForValue - This struct represents the registers (physical or virtual)
74 /// that a particular set of values is assigned, and the type information about
75 /// the value. The most common situation is to represent one value at a time,
76 /// but struct or array values are handled element-wise as multiple values.
77 /// The splitting of aggregates is performed recursively, so that we never
78 /// have aggregate-typed registers. The values at this point do not necessarily
79 /// have legal types, so each value may require one or more registers of some
83 /// TLI - The TargetLowering object.
85 const TargetLowering *TLI;
87 /// ValueVTs - The value types of the values, which may not be legal, and
88 /// may need be promoted or synthesized from one or more registers.
90 SmallVector<EVT, 4> ValueVTs;
92 /// RegVTs - The value types of the registers. This is the same size as
93 /// ValueVTs and it records, for each value, what the type of the assigned
94 /// register or registers are. (Individual values are never synthesized
95 /// from more than one type of register.)
97 /// With virtual registers, the contents of RegVTs is redundant with TLI's
98 /// getRegisterType member function, however when with physical registers
99 /// it is necessary to have a separate record of the types.
101 SmallVector<EVT, 4> RegVTs;
103 /// Regs - This list holds the registers assigned to the values.
104 /// Each legal or promoted value requires one register, and each
105 /// expanded value requires multiple registers.
107 SmallVector<unsigned, 4> Regs;
109 RegsForValue() : TLI(0) {}
111 RegsForValue(const TargetLowering &tli,
112 const SmallVector<unsigned, 4> ®s,
113 EVT regvt, EVT valuevt)
114 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
115 RegsForValue(const TargetLowering &tli,
116 const SmallVector<unsigned, 4> ®s,
117 const SmallVector<EVT, 4> ®vts,
118 const SmallVector<EVT, 4> &valuevts)
119 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
120 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
121 unsigned Reg, const Type *Ty) : TLI(&tli) {
122 ComputeValueVTs(tli, Ty, ValueVTs);
124 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
125 EVT ValueVT = ValueVTs[Value];
126 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
127 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
128 for (unsigned i = 0; i != NumRegs; ++i)
129 Regs.push_back(Reg + i);
130 RegVTs.push_back(RegisterVT);
135 /// append - Add the specified values to this one.
136 void append(const RegsForValue &RHS) {
138 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
139 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
140 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
144 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
145 /// this value and returns the result as a ValueVTs value. This uses
146 /// Chain/Flag as the input and updates them for the output Chain/Flag.
147 /// If the Flag pointer is NULL, no flag is used.
148 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
149 SDValue &Chain, SDValue *Flag) const;
151 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
152 /// specified value into the registers specified by this object. This uses
153 /// Chain/Flag as the input and updates them for the output Chain/Flag.
154 /// If the Flag pointer is NULL, no flag is used.
155 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
156 unsigned Order, SDValue &Chain, SDValue *Flag) const;
158 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
159 /// operand list. This adds the code marker, matching input operand index
160 /// (if applicable), and includes the number of values added into it.
161 void AddInlineAsmOperands(unsigned Code,
162 bool HasMatching, unsigned MatchingIdx,
163 SelectionDAG &DAG, unsigned Order,
164 std::vector<SDValue> &Ops) const;
168 /// getCopyFromParts - Create a value that contains the specified legal parts
169 /// combined into the value they represent. If the parts combine to a type
170 /// larger then ValueVT then AssertOp can be used to specify whether the extra
171 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
172 /// (ISD::AssertSext).
173 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
174 const SDValue *Parts,
175 unsigned NumParts, EVT PartVT, EVT ValueVT,
176 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
177 assert(NumParts > 0 && "No parts to assemble!");
178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
179 SDValue Val = Parts[0];
180 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
183 // Assemble the value from multiple parts.
184 if (!ValueVT.isVector() && ValueVT.isInteger()) {
185 unsigned PartBits = PartVT.getSizeInBits();
186 unsigned ValueBits = ValueVT.getSizeInBits();
188 // Assemble the power of 2 part.
189 unsigned RoundParts = NumParts & (NumParts - 1) ?
190 1 << Log2_32(NumParts) : NumParts;
191 unsigned RoundBits = PartBits * RoundParts;
192 EVT RoundVT = RoundBits == ValueBits ?
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
196 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
198 if (RoundParts > 2) {
199 Lo = getCopyFromParts(DAG, dl, Order, Parts, RoundParts / 2,
201 Hi = getCopyFromParts(DAG, dl, Order, Parts + RoundParts / 2,
202 RoundParts / 2, PartVT, HalfVT);
204 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
205 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
208 if (TLI.isBigEndian())
211 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
213 if (DisableScheduling) {
214 DAG.AssignOrdering(Lo.getNode(), Order);
215 DAG.AssignOrdering(Hi.getNode(), Order);
216 DAG.AssignOrdering(Val.getNode(), Order);
219 if (RoundParts < NumParts) {
220 // Assemble the trailing non-power-of-2 part.
221 unsigned OddParts = NumParts - RoundParts;
222 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
223 Hi = getCopyFromParts(DAG, dl, Order,
224 Parts + RoundParts, OddParts, PartVT, OddVT);
226 // Combine the round and odd parts.
228 if (TLI.isBigEndian())
230 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
231 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
232 if (DisableScheduling) DAG.AssignOrdering(Hi.getNode(), Order);
233 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
234 DAG.getConstant(Lo.getValueType().getSizeInBits(),
235 TLI.getPointerTy()));
236 if (DisableScheduling) DAG.AssignOrdering(Hi.getNode(), Order);
237 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
238 if (DisableScheduling) DAG.AssignOrdering(Lo.getNode(), Order);
239 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
240 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
242 } else if (ValueVT.isVector()) {
243 // Handle a multi-element vector.
244 EVT IntermediateVT, RegisterVT;
245 unsigned NumIntermediates;
247 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
248 NumIntermediates, RegisterVT);
249 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
250 NumParts = NumRegs; // Silence a compiler warning.
251 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
252 assert(RegisterVT == Parts[0].getValueType() &&
253 "Part type doesn't match part!");
255 // Assemble the parts into intermediate operands.
256 SmallVector<SDValue, 8> Ops(NumIntermediates);
257 if (NumIntermediates == NumParts) {
258 // If the register was not expanded, truncate or copy the value,
260 for (unsigned i = 0; i != NumParts; ++i)
261 Ops[i] = getCopyFromParts(DAG, dl, Order, &Parts[i], 1,
262 PartVT, IntermediateVT);
263 } else if (NumParts > 0) {
264 // If the intermediate type was expanded, build the intermediate operands
266 assert(NumParts % NumIntermediates == 0 &&
267 "Must expand into a divisible number of parts!");
268 unsigned Factor = NumParts / NumIntermediates;
269 for (unsigned i = 0; i != NumIntermediates; ++i)
270 Ops[i] = getCopyFromParts(DAG, dl, Order, &Parts[i * Factor], Factor,
271 PartVT, IntermediateVT);
274 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
276 Val = DAG.getNode(IntermediateVT.isVector() ?
277 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
278 ValueVT, &Ops[0], NumIntermediates);
279 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
280 } else if (PartVT.isFloatingPoint()) {
281 // FP split into multiple FP parts (for ppcf128)
282 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
285 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
286 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
287 if (TLI.isBigEndian())
289 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
291 if (DisableScheduling) {
292 DAG.AssignOrdering(Hi.getNode(), Order);
293 DAG.AssignOrdering(Lo.getNode(), Order);
294 DAG.AssignOrdering(Val.getNode(), Order);
297 // FP split into integer parts (soft fp)
298 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
299 !PartVT.isVector() && "Unexpected split");
300 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
301 Val = getCopyFromParts(DAG, dl, Order, Parts, NumParts, PartVT, IntVT);
305 // There is now one part, held in Val. Correct it to match ValueVT.
306 PartVT = Val.getValueType();
308 if (PartVT == ValueVT)
311 if (PartVT.isVector()) {
312 assert(ValueVT.isVector() && "Unknown vector conversion!");
313 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
314 if (DisableScheduling)
315 DAG.AssignOrdering(Res.getNode(), Order);
319 if (ValueVT.isVector()) {
320 assert(ValueVT.getVectorElementType() == PartVT &&
321 ValueVT.getVectorNumElements() == 1 &&
322 "Only trivial scalar-to-vector conversions should get here!");
323 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
324 if (DisableScheduling)
325 DAG.AssignOrdering(Res.getNode(), Order);
329 if (PartVT.isInteger() &&
330 ValueVT.isInteger()) {
331 if (ValueVT.bitsLT(PartVT)) {
332 // For a truncate, see if we have any information to
333 // indicate whether the truncated bits will always be
334 // zero or sign-extension.
335 if (AssertOp != ISD::DELETED_NODE)
336 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
337 DAG.getValueType(ValueVT));
338 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
339 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
340 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
343 Val = DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
344 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
349 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
350 if (ValueVT.bitsLT(Val.getValueType())) {
351 // FP_ROUND's are always exact here.
352 Val = DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
353 DAG.getIntPtrConstant(1));
354 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
358 Val = DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
359 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
363 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
364 Val = DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
365 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
369 llvm_unreachable("Unknown mismatch!");
373 /// getCopyToParts - Create a series of nodes that contain the specified value
374 /// split into legal parts. If the parts contain more bits than Val, then, for
375 /// integers, ExtendKind can be used to specify how to generate the extra bits.
376 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
377 SDValue Val, SDValue *Parts, unsigned NumParts,
379 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
380 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
381 EVT PtrVT = TLI.getPointerTy();
382 EVT ValueVT = Val.getValueType();
383 unsigned PartBits = PartVT.getSizeInBits();
384 unsigned OrigNumParts = NumParts;
385 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
390 if (!ValueVT.isVector()) {
391 if (PartVT == ValueVT) {
392 assert(NumParts == 1 && "No-op copy with multiple parts!");
397 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
398 // If the parts cover more bits than the value has, promote the value.
399 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
400 assert(NumParts == 1 && "Do not know what to promote to!");
401 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
402 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
406 llvm_unreachable("Unknown mismatch!");
408 } else if (PartBits == ValueVT.getSizeInBits()) {
409 // Different types of the same size.
410 assert(NumParts == 1 && PartVT != ValueVT);
411 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
412 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
413 // If the parts cover less bits than value has, truncate the value.
414 if (PartVT.isInteger() && ValueVT.isInteger()) {
415 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
416 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
418 llvm_unreachable("Unknown mismatch!");
422 if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 assert(PartVT == ValueVT && "Type conversion failed!");
435 // Expand the value into multiple parts.
436 if (NumParts & (NumParts - 1)) {
437 // The number of parts is not a power of 2. Split off and copy the tail.
438 assert(PartVT.isInteger() && ValueVT.isInteger() &&
439 "Do not know what to expand to!");
440 unsigned RoundParts = 1 << Log2_32(NumParts);
441 unsigned RoundBits = RoundParts * PartBits;
442 unsigned OddParts = NumParts - RoundParts;
443 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
444 DAG.getConstant(RoundBits,
445 TLI.getPointerTy()));
446 getCopyToParts(DAG, dl, Order, OddVal, Parts + RoundParts,
449 if (TLI.isBigEndian())
450 // The odd parts were reversed by getCopyToParts - unreverse them.
451 std::reverse(Parts + RoundParts, Parts + NumParts);
453 NumParts = RoundParts;
454 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
455 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
457 if (DisableScheduling) {
458 DAG.AssignOrdering(OddVal.getNode(), Order);
459 DAG.AssignOrdering(Val.getNode(), Order);
463 // The number of parts is a power of 2. Repeatedly bisect the value using
465 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
466 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()),
469 if (DisableScheduling)
470 DAG.AssignOrdering(Parts[0].getNode(), Order);
472 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
473 for (unsigned i = 0; i < NumParts; i += StepSize) {
474 unsigned ThisBits = StepSize * PartBits / 2;
475 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
476 SDValue &Part0 = Parts[i];
477 SDValue &Part1 = Parts[i+StepSize/2];
479 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
481 DAG.getConstant(1, PtrVT));
482 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
484 DAG.getConstant(0, PtrVT));
486 if (DisableScheduling) {
487 DAG.AssignOrdering(Part0.getNode(), Order);
488 DAG.AssignOrdering(Part1.getNode(), Order);
491 if (ThisBits == PartBits && ThisVT != PartVT) {
492 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
494 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
496 if (DisableScheduling) {
497 DAG.AssignOrdering(Part0.getNode(), Order);
498 DAG.AssignOrdering(Part1.getNode(), Order);
504 if (TLI.isBigEndian())
505 std::reverse(Parts, Parts + OrigNumParts);
512 if (PartVT != ValueVT) {
513 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
514 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
516 assert(ValueVT.getVectorElementType() == PartVT &&
517 ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
521 DAG.getConstant(0, PtrVT));
525 if (DisableScheduling)
526 DAG.AssignOrdering(Val.getNode(), Order);
532 // Handle a multi-element vector.
533 EVT IntermediateVT, RegisterVT;
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
536 IntermediateVT, NumIntermediates, RegisterVT);
537 unsigned NumElements = ValueVT.getVectorNumElements();
539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540 NumParts = NumRegs; // Silence a compiler warning.
541 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
543 // Split the vector into intermediate operands.
544 SmallVector<SDValue, 8> Ops(NumIntermediates);
545 for (unsigned i = 0; i != NumIntermediates; ++i) {
546 if (IntermediateVT.isVector())
547 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
549 DAG.getConstant(i * (NumElements / NumIntermediates),
552 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
554 DAG.getConstant(i, PtrVT));
556 if (DisableScheduling)
557 DAG.AssignOrdering(Ops[i].getNode(), Order);
560 // Split the intermediate operands into legal parts.
561 if (NumParts == NumIntermediates) {
562 // If the register was not expanded, promote or copy the value,
564 for (unsigned i = 0; i != NumParts; ++i)
565 getCopyToParts(DAG, dl, Order, Ops[i], &Parts[i], 1, PartVT);
566 } else if (NumParts > 0) {
567 // If the intermediate type was expanded, split each the value into
569 assert(NumParts % NumIntermediates == 0 &&
570 "Must expand into a divisible number of parts!");
571 unsigned Factor = NumParts / NumIntermediates;
572 for (unsigned i = 0; i != NumIntermediates; ++i)
573 getCopyToParts(DAG, dl, Order, Ops[i], &Parts[i*Factor], Factor, PartVT);
578 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
581 TD = DAG.getTarget().getTargetData();
584 /// clear - Clear out the curret SelectionDAG and the associated
585 /// state and prepare this SelectionDAGBuilder object to be used
586 /// for a new block. This doesn't clear out information about
587 /// additional blocks that are needed to complete switch lowering
588 /// or PHI node updating; that information is cleared out as it is
590 void SelectionDAGBuilder::clear() {
592 PendingLoads.clear();
593 PendingExports.clear();
596 CurDebugLoc = DebugLoc::getUnknownLoc();
600 /// getRoot - Return the current virtual root of the Selection DAG,
601 /// flushing any PendingLoad items. This must be done before emitting
602 /// a store or any other node that may need to be ordered after any
603 /// prior load instructions.
605 SDValue SelectionDAGBuilder::getRoot() {
606 if (PendingLoads.empty())
607 return DAG.getRoot();
609 if (PendingLoads.size() == 1) {
610 SDValue Root = PendingLoads[0];
612 PendingLoads.clear();
616 // Otherwise, we have to make a token factor node.
617 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
618 &PendingLoads[0], PendingLoads.size());
619 PendingLoads.clear();
624 /// getControlRoot - Similar to getRoot, but instead of flushing all the
625 /// PendingLoad items, flush all the PendingExports items. It is necessary
626 /// to do this before emitting a terminator instruction.
628 SDValue SelectionDAGBuilder::getControlRoot() {
629 SDValue Root = DAG.getRoot();
631 if (PendingExports.empty())
634 // Turn all of the CopyToReg chains into one factored node.
635 if (Root.getOpcode() != ISD::EntryToken) {
636 unsigned i = 0, e = PendingExports.size();
637 for (; i != e; ++i) {
638 assert(PendingExports[i].getNode()->getNumOperands() > 1);
639 if (PendingExports[i].getNode()->getOperand(0) == Root)
640 break; // Don't add the root if we already indirectly depend on it.
644 PendingExports.push_back(Root);
647 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
649 PendingExports.size());
650 PendingExports.clear();
655 void SelectionDAGBuilder::visit(Instruction &I) {
656 visit(I.getOpcode(), I);
659 void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
660 // We're processing a new instruction.
663 // Note: this doesn't use InstVisitor, because it has to work with
664 // ConstantExpr's in addition to instructions.
666 default: llvm_unreachable("Unknown instruction type encountered!");
667 // Build the switch statement using the Instruction.def file.
668 #define HANDLE_INST(NUM, OPCODE, CLASS) \
669 case Instruction::OPCODE: return visit##OPCODE((CLASS&)I);
670 #include "llvm/Instruction.def"
674 SDValue SelectionDAGBuilder::getValue(const Value *V) {
675 SDValue &N = NodeMap[V];
676 if (N.getNode()) return N;
678 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
679 EVT VT = TLI.getValueType(V->getType(), true);
681 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
682 return N = DAG.getConstant(*CI, VT);
684 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
685 return N = DAG.getGlobalAddress(GV, VT);
687 if (isa<ConstantPointerNull>(C))
688 return N = DAG.getConstant(0, TLI.getPointerTy());
690 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
691 return N = DAG.getConstantFP(*CFP, VT);
693 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
694 return N = DAG.getUNDEF(VT);
696 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
697 visit(CE->getOpcode(), *CE);
698 SDValue N1 = NodeMap[V];
699 assert(N1.getNode() && "visit didn't populate the ValueMap!");
703 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
704 SmallVector<SDValue, 4> Constants;
705 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
707 SDNode *Val = getValue(*OI).getNode();
708 // If the operand is an empty aggregate, there are no values.
710 // Add each leaf value from the operand to the Constants list
711 // to form a flattened list of all the values.
712 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
713 Constants.push_back(SDValue(Val, i));
716 SDValue Res = DAG.getMergeValues(&Constants[0], Constants.size(),
718 if (DisableScheduling)
719 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
723 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
724 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
725 "Unknown struct or array constant!");
727 SmallVector<EVT, 4> ValueVTs;
728 ComputeValueVTs(TLI, C->getType(), ValueVTs);
729 unsigned NumElts = ValueVTs.size();
731 return SDValue(); // empty struct
732 SmallVector<SDValue, 4> Constants(NumElts);
733 for (unsigned i = 0; i != NumElts; ++i) {
734 EVT EltVT = ValueVTs[i];
735 if (isa<UndefValue>(C))
736 Constants[i] = DAG.getUNDEF(EltVT);
737 else if (EltVT.isFloatingPoint())
738 Constants[i] = DAG.getConstantFP(0, EltVT);
740 Constants[i] = DAG.getConstant(0, EltVT);
743 SDValue Res = DAG.getMergeValues(&Constants[0], NumElts,
745 if (DisableScheduling)
746 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
750 if (BlockAddress *BA = dyn_cast<BlockAddress>(C))
751 return DAG.getBlockAddress(BA, VT);
753 const VectorType *VecTy = cast<VectorType>(V->getType());
754 unsigned NumElements = VecTy->getNumElements();
756 // Now that we know the number and type of the elements, get that number of
757 // elements into the Ops array based on what kind of constant it is.
758 SmallVector<SDValue, 16> Ops;
759 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
760 for (unsigned i = 0; i != NumElements; ++i)
761 Ops.push_back(getValue(CP->getOperand(i)));
763 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
764 EVT EltVT = TLI.getValueType(VecTy->getElementType());
767 if (EltVT.isFloatingPoint())
768 Op = DAG.getConstantFP(0, EltVT);
770 Op = DAG.getConstant(0, EltVT);
771 Ops.assign(NumElements, Op);
774 // Create a BUILD_VECTOR node.
775 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
776 VT, &Ops[0], Ops.size());
777 if (DisableScheduling)
778 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
780 return NodeMap[V] = Res;
783 // If this is a static alloca, generate it as the frameindex instead of
785 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
786 DenseMap<const AllocaInst*, int>::iterator SI =
787 FuncInfo.StaticAllocaMap.find(AI);
788 if (SI != FuncInfo.StaticAllocaMap.end())
789 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
792 unsigned InReg = FuncInfo.ValueMap[V];
793 assert(InReg && "Value not in map!");
795 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
796 SDValue Chain = DAG.getEntryNode();
797 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(),
798 SDNodeOrder, Chain, NULL);
801 /// Get the EVTs and ArgFlags collections that represent the return type
802 /// of the given function. This does not require a DAG or a return value, and
803 /// is suitable for use before any DAGs for the function are constructed.
804 static void getReturnInfo(const Type* ReturnType,
805 Attributes attr, SmallVectorImpl<EVT> &OutVTs,
806 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
808 SmallVectorImpl<uint64_t> *Offsets = 0) {
809 SmallVector<EVT, 4> ValueVTs;
810 ComputeValueVTs(TLI, ReturnType, ValueVTs, Offsets);
811 unsigned NumValues = ValueVTs.size();
812 if ( NumValues == 0 ) return;
814 for (unsigned j = 0, f = NumValues; j != f; ++j) {
815 EVT VT = ValueVTs[j];
816 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
818 if (attr & Attribute::SExt)
819 ExtendKind = ISD::SIGN_EXTEND;
820 else if (attr & Attribute::ZExt)
821 ExtendKind = ISD::ZERO_EXTEND;
823 // FIXME: C calling convention requires the return type to be promoted to
824 // at least 32-bit. But this is not necessary for non-C calling
825 // conventions. The frontend should mark functions whose return values
826 // require promoting with signext or zeroext attributes.
827 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
828 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
829 if (VT.bitsLT(MinVT))
833 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
834 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
835 // 'inreg' on function refers to return value
836 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
837 if (attr & Attribute::InReg)
840 // Propagate extension type if any
841 if (attr & Attribute::SExt)
843 else if (attr & Attribute::ZExt)
846 for (unsigned i = 0; i < NumParts; ++i) {
847 OutVTs.push_back(PartVT);
848 OutFlags.push_back(Flags);
853 void SelectionDAGBuilder::visitRet(ReturnInst &I) {
854 SDValue Chain = getControlRoot();
855 SmallVector<ISD::OutputArg, 8> Outs;
856 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
858 if (!FLI.CanLowerReturn) {
859 unsigned DemoteReg = FLI.DemoteRegister;
860 const Function *F = I.getParent()->getParent();
862 // Emit a store of the return value through the virtual register.
863 // Leave Outs empty so that LowerReturn won't try to load return
864 // registers the usual way.
865 SmallVector<EVT, 1> PtrValueVTs;
866 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
869 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
870 SDValue RetOp = getValue(I.getOperand(0));
872 SmallVector<EVT, 4> ValueVTs;
873 SmallVector<uint64_t, 4> Offsets;
874 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
875 unsigned NumValues = ValueVTs.size();
877 SmallVector<SDValue, 4> Chains(NumValues);
878 EVT PtrVT = PtrValueVTs[0];
879 for (unsigned i = 0; i != NumValues; ++i) {
880 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
881 DAG.getConstant(Offsets[i], PtrVT));
883 DAG.getStore(Chain, getCurDebugLoc(),
884 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
885 Add, NULL, Offsets[i], false, 0);
887 if (DisableScheduling) {
888 DAG.AssignOrdering(Add.getNode(), SDNodeOrder);
889 DAG.AssignOrdering(Chains[i].getNode(), SDNodeOrder);
893 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
894 MVT::Other, &Chains[0], NumValues);
896 if (DisableScheduling)
897 DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
899 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
900 SmallVector<EVT, 4> ValueVTs;
901 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
902 unsigned NumValues = ValueVTs.size();
903 if (NumValues == 0) continue;
905 SDValue RetOp = getValue(I.getOperand(i));
906 for (unsigned j = 0, f = NumValues; j != f; ++j) {
907 EVT VT = ValueVTs[j];
909 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
911 const Function *F = I.getParent()->getParent();
912 if (F->paramHasAttr(0, Attribute::SExt))
913 ExtendKind = ISD::SIGN_EXTEND;
914 else if (F->paramHasAttr(0, Attribute::ZExt))
915 ExtendKind = ISD::ZERO_EXTEND;
917 // FIXME: C calling convention requires the return type to be promoted to
918 // at least 32-bit. But this is not necessary for non-C calling
919 // conventions. The frontend should mark functions whose return values
920 // require promoting with signext or zeroext attributes.
921 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
922 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
923 if (VT.bitsLT(MinVT))
927 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
928 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
929 SmallVector<SDValue, 4> Parts(NumParts);
930 getCopyToParts(DAG, getCurDebugLoc(), SDNodeOrder,
931 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
932 &Parts[0], NumParts, PartVT, ExtendKind);
934 // 'inreg' on function refers to return value
935 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
936 if (F->paramHasAttr(0, Attribute::InReg))
939 // Propagate extension type if any
940 if (F->paramHasAttr(0, Attribute::SExt))
942 else if (F->paramHasAttr(0, Attribute::ZExt))
945 for (unsigned i = 0; i < NumParts; ++i)
946 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
951 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
952 CallingConv::ID CallConv =
953 DAG.getMachineFunction().getFunction()->getCallingConv();
954 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
955 Outs, getCurDebugLoc(), DAG);
957 // Verify that the target's LowerReturn behaved as expected.
958 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
959 "LowerReturn didn't return a valid chain!");
961 // Update the DAG with the new chain value resulting from return lowering.
964 if (DisableScheduling)
965 DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
968 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
969 /// created for it, emit nodes to copy the value into the virtual
971 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) {
972 if (!V->use_empty()) {
973 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
974 if (VMI != FuncInfo.ValueMap.end())
975 CopyValueToVirtualRegister(V, VMI->second);
979 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
980 /// the current basic block, add it to ValueMap now so that we'll get a
982 void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) {
983 // No need to export constants.
984 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
987 if (FuncInfo.isExportedInst(V)) return;
989 unsigned Reg = FuncInfo.InitializeRegForValue(V);
990 CopyValueToVirtualRegister(V, Reg);
993 bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V,
994 const BasicBlock *FromBB) {
995 // The operands of the setcc have to be in this block. We don't know
996 // how to export them from some other block.
997 if (Instruction *VI = dyn_cast<Instruction>(V)) {
998 // Can export from current BB.
999 if (VI->getParent() == FromBB)
1002 // Is already exported, noop.
1003 return FuncInfo.isExportedInst(V);
1006 // If this is an argument, we can export it if the BB is the entry block or
1007 // if it is already exported.
1008 if (isa<Argument>(V)) {
1009 if (FromBB == &FromBB->getParent()->getEntryBlock())
1012 // Otherwise, can only export this if it is already exported.
1013 return FuncInfo.isExportedInst(V);
1016 // Otherwise, constants can always be exported.
1020 static bool InBlock(const Value *V, const BasicBlock *BB) {
1021 if (const Instruction *I = dyn_cast<Instruction>(V))
1022 return I->getParent() == BB;
1026 /// getFCmpCondCode - Return the ISD condition code corresponding to
1027 /// the given LLVM IR floating-point condition code. This includes
1028 /// consideration of global floating-point math flags.
1030 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1031 ISD::CondCode FPC, FOC;
1033 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1034 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1035 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1036 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1037 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1038 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1039 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1040 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1041 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1042 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1043 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1044 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1045 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1046 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1047 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1048 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1050 llvm_unreachable("Invalid FCmp predicate opcode!");
1051 FOC = FPC = ISD::SETFALSE;
1054 if (FiniteOnlyFPMath())
1060 /// getICmpCondCode - Return the ISD condition code corresponding to
1061 /// the given LLVM IR integer condition code.
1063 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1065 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1066 case ICmpInst::ICMP_NE: return ISD::SETNE;
1067 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1068 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1069 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1070 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1071 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1072 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1073 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1074 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1076 llvm_unreachable("Invalid ICmp predicate opcode!");
1081 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1082 /// This function emits a branch and is used at the leaves of an OR or an
1083 /// AND operator tree.
1086 SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond,
1087 MachineBasicBlock *TBB,
1088 MachineBasicBlock *FBB,
1089 MachineBasicBlock *CurBB) {
1090 const BasicBlock *BB = CurBB->getBasicBlock();
1092 // If the leaf of the tree is a comparison, merge the condition into
1094 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1095 // The operands of the cmp have to be in this block. We don't know
1096 // how to export them from some other block. If this is the first block
1097 // of the sequence, no exporting is needed.
1098 if (CurBB == CurMBB ||
1099 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1100 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1101 ISD::CondCode Condition;
1102 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1103 Condition = getICmpCondCode(IC->getPredicate());
1104 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1105 Condition = getFCmpCondCode(FC->getPredicate());
1107 Condition = ISD::SETEQ; // silence warning.
1108 llvm_unreachable("Unknown compare instruction");
1111 CaseBlock CB(Condition, BOp->getOperand(0),
1112 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1113 SwitchCases.push_back(CB);
1118 // Create a CaseBlock record representing this branch.
1119 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1120 NULL, TBB, FBB, CurBB);
1121 SwitchCases.push_back(CB);
1124 /// FindMergedConditions - If Cond is an expression like
1125 void SelectionDAGBuilder::FindMergedConditions(Value *Cond,
1126 MachineBasicBlock *TBB,
1127 MachineBasicBlock *FBB,
1128 MachineBasicBlock *CurBB,
1130 // If this node is not part of the or/and tree, emit it as a branch.
1131 Instruction *BOp = dyn_cast<Instruction>(Cond);
1132 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1133 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1134 BOp->getParent() != CurBB->getBasicBlock() ||
1135 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1136 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1137 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1141 // Create TmpBB after CurBB.
1142 MachineFunction::iterator BBI = CurBB;
1143 MachineFunction &MF = DAG.getMachineFunction();
1144 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1145 CurBB->getParent()->insert(++BBI, TmpBB);
1147 if (Opc == Instruction::Or) {
1148 // Codegen X | Y as:
1156 // Emit the LHS condition.
1157 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1159 // Emit the RHS condition into TmpBB.
1160 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1162 assert(Opc == Instruction::And && "Unknown merge op!");
1163 // Codegen X & Y as:
1170 // This requires creation of TmpBB after CurBB.
1172 // Emit the LHS condition.
1173 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1175 // Emit the RHS condition into TmpBB.
1176 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1180 /// If the set of cases should be emitted as a series of branches, return true.
1181 /// If we should emit this as a bunch of and/or'd together conditions, return
1184 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1185 if (Cases.size() != 2) return true;
1187 // If this is two comparisons of the same values or'd or and'd together, they
1188 // will get folded into a single comparison, so don't emit two blocks.
1189 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1190 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1191 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1192 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1199 void SelectionDAGBuilder::visitBr(BranchInst &I) {
1200 // Update machine-CFG edges.
1201 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1203 // Figure out which block is immediately after the current one.
1204 MachineBasicBlock *NextBlock = 0;
1205 MachineFunction::iterator BBI = CurMBB;
1206 if (++BBI != FuncInfo.MF->end())
1209 if (I.isUnconditional()) {
1210 // Update machine-CFG edges.
1211 CurMBB->addSuccessor(Succ0MBB);
1213 // If this is not a fall-through branch, emit the branch.
1214 if (Succ0MBB != NextBlock) {
1215 SDValue V = DAG.getNode(ISD::BR, getCurDebugLoc(),
1216 MVT::Other, getControlRoot(),
1217 DAG.getBasicBlock(Succ0MBB));
1220 if (DisableScheduling)
1221 DAG.AssignOrdering(V.getNode(), SDNodeOrder);
1227 // If this condition is one of the special cases we handle, do special stuff
1229 Value *CondVal = I.getCondition();
1230 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1232 // If this is a series of conditions that are or'd or and'd together, emit
1233 // this as a sequence of branches instead of setcc's with and/or operations.
1234 // For example, instead of something like:
1247 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1248 if (BOp->hasOneUse() &&
1249 (BOp->getOpcode() == Instruction::And ||
1250 BOp->getOpcode() == Instruction::Or)) {
1251 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1252 // If the compares in later blocks need to use values not currently
1253 // exported from this block, export them now. This block should always
1254 // be the first entry.
1255 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1257 // Allow some cases to be rejected.
1258 if (ShouldEmitAsBranches(SwitchCases)) {
1259 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1260 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1261 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1264 // Emit the branch for this block.
1265 visitSwitchCase(SwitchCases[0]);
1266 SwitchCases.erase(SwitchCases.begin());
1270 // Okay, we decided not to do this, remove any inserted MBB's and clear
1272 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1273 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1275 SwitchCases.clear();
1279 // Create a CaseBlock record representing this branch.
1280 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1281 NULL, Succ0MBB, Succ1MBB, CurMBB);
1283 // Use visitSwitchCase to actually insert the fast branch sequence for this
1285 visitSwitchCase(CB);
1288 /// visitSwitchCase - Emits the necessary code to represent a single node in
1289 /// the binary search tree resulting from lowering a switch instruction.
1290 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
1292 SDValue CondLHS = getValue(CB.CmpLHS);
1293 DebugLoc dl = getCurDebugLoc();
1295 // Build the setcc now.
1296 if (CB.CmpMHS == NULL) {
1297 // Fold "(X == true)" to X and "(X == false)" to !X to
1298 // handle common cases produced by branch lowering.
1299 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1300 CB.CC == ISD::SETEQ)
1302 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1303 CB.CC == ISD::SETEQ) {
1304 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1305 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1307 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1309 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1311 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1312 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1314 SDValue CmpOp = getValue(CB.CmpMHS);
1315 EVT VT = CmpOp.getValueType();
1317 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1318 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1321 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1322 VT, CmpOp, DAG.getConstant(Low, VT));
1323 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1324 DAG.getConstant(High-Low, VT), ISD::SETULE);
1328 if (DisableScheduling)
1329 DAG.AssignOrdering(Cond.getNode(), SDNodeOrder);
1331 // Update successor info
1332 CurMBB->addSuccessor(CB.TrueBB);
1333 CurMBB->addSuccessor(CB.FalseBB);
1335 // Set NextBlock to be the MBB immediately after the current one, if any.
1336 // This is used to avoid emitting unnecessary branches to the next block.
1337 MachineBasicBlock *NextBlock = 0;
1338 MachineFunction::iterator BBI = CurMBB;
1339 if (++BBI != FuncInfo.MF->end())
1342 // If the lhs block is the next block, invert the condition so that we can
1343 // fall through to the lhs instead of the rhs block.
1344 if (CB.TrueBB == NextBlock) {
1345 std::swap(CB.TrueBB, CB.FalseBB);
1346 SDValue True = DAG.getConstant(1, Cond.getValueType());
1347 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1349 if (DisableScheduling)
1350 DAG.AssignOrdering(Cond.getNode(), SDNodeOrder);
1353 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1354 MVT::Other, getControlRoot(), Cond,
1355 DAG.getBasicBlock(CB.TrueBB));
1357 if (DisableScheduling)
1358 DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
1360 // If the branch was constant folded, fix up the CFG.
1361 if (BrCond.getOpcode() == ISD::BR) {
1362 CurMBB->removeSuccessor(CB.FalseBB);
1364 // Otherwise, go ahead and insert the false branch.
1365 if (BrCond == getControlRoot())
1366 CurMBB->removeSuccessor(CB.TrueBB);
1368 if (CB.FalseBB != NextBlock) {
1369 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1370 DAG.getBasicBlock(CB.FalseBB));
1372 if (DisableScheduling)
1373 DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
1377 DAG.setRoot(BrCond);
1380 /// visitJumpTable - Emit JumpTable node in the current MBB
1381 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1382 // Emit the code for the jump table
1383 assert(JT.Reg != -1U && "Should lower JT Header first!");
1384 EVT PTy = TLI.getPointerTy();
1385 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1387 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1388 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1389 MVT::Other, Index.getValue(1),
1391 DAG.setRoot(BrJumpTable);
1393 if (DisableScheduling) {
1394 DAG.AssignOrdering(Index.getNode(), SDNodeOrder);
1395 DAG.AssignOrdering(Table.getNode(), SDNodeOrder);
1396 DAG.AssignOrdering(BrJumpTable.getNode(), SDNodeOrder);
1400 /// visitJumpTableHeader - This function emits necessary code to produce index
1401 /// in the JumpTable from switch case.
1402 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1403 JumpTableHeader &JTH) {
1404 // Subtract the lowest switch case value from the value being switched on and
1405 // conditional branch to default mbb if the result is greater than the
1406 // difference between smallest and largest cases.
1407 SDValue SwitchOp = getValue(JTH.SValue);
1408 EVT VT = SwitchOp.getValueType();
1409 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1410 DAG.getConstant(JTH.First, VT));
1412 // The SDNode we just created, which holds the value being switched on minus
1413 // the the smallest case value, needs to be copied to a virtual register so it
1414 // can be used as an index into the jump table in a subsequent basic block.
1415 // This value may be smaller or larger than the target's pointer type, and
1416 // therefore require extension or truncating.
1417 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1419 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1420 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1421 JumpTableReg, SwitchOp);
1422 JT.Reg = JumpTableReg;
1424 // Emit the range check for the jump table, and branch to the default block
1425 // for the switch statement if the value being switched on exceeds the largest
1426 // case in the switch.
1427 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1428 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1429 DAG.getConstant(JTH.Last-JTH.First,VT),
1432 if (DisableScheduling) {
1433 DAG.AssignOrdering(Sub.getNode(), SDNodeOrder);
1434 DAG.AssignOrdering(SwitchOp.getNode(), SDNodeOrder);
1435 DAG.AssignOrdering(CopyTo.getNode(), SDNodeOrder);
1436 DAG.AssignOrdering(CMP.getNode(), SDNodeOrder);
1439 // Set NextBlock to be the MBB immediately after the current one, if any.
1440 // This is used to avoid emitting unnecessary branches to the next block.
1441 MachineBasicBlock *NextBlock = 0;
1442 MachineFunction::iterator BBI = CurMBB;
1444 if (++BBI != FuncInfo.MF->end())
1447 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1448 MVT::Other, CopyTo, CMP,
1449 DAG.getBasicBlock(JT.Default));
1451 if (DisableScheduling)
1452 DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
1454 if (JT.MBB != NextBlock) {
1455 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1456 DAG.getBasicBlock(JT.MBB));
1458 if (DisableScheduling)
1459 DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
1462 DAG.setRoot(BrCond);
1465 /// visitBitTestHeader - This function emits necessary code to produce value
1466 /// suitable for "bit tests"
1467 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
1468 // Subtract the minimum value
1469 SDValue SwitchOp = getValue(B.SValue);
1470 EVT VT = SwitchOp.getValueType();
1471 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1472 DAG.getConstant(B.First, VT));
1475 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1476 TLI.getSetCCResultType(Sub.getValueType()),
1477 Sub, DAG.getConstant(B.Range, VT),
1480 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1481 TLI.getPointerTy());
1483 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1484 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1487 if (DisableScheduling) {
1488 DAG.AssignOrdering(Sub.getNode(), SDNodeOrder);
1489 DAG.AssignOrdering(RangeCmp.getNode(), SDNodeOrder);
1490 DAG.AssignOrdering(ShiftOp.getNode(), SDNodeOrder);
1491 DAG.AssignOrdering(CopyTo.getNode(), SDNodeOrder);
1494 // Set NextBlock to be the MBB immediately after the current one, if any.
1495 // This is used to avoid emitting unnecessary branches to the next block.
1496 MachineBasicBlock *NextBlock = 0;
1497 MachineFunction::iterator BBI = CurMBB;
1498 if (++BBI != FuncInfo.MF->end())
1501 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1503 CurMBB->addSuccessor(B.Default);
1504 CurMBB->addSuccessor(MBB);
1506 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1507 MVT::Other, CopyTo, RangeCmp,
1508 DAG.getBasicBlock(B.Default));
1510 if (DisableScheduling)
1511 DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
1513 if (MBB != NextBlock) {
1514 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1515 DAG.getBasicBlock(MBB));
1517 if (DisableScheduling)
1518 DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
1521 DAG.setRoot(BrRange);
1524 /// visitBitTestCase - this function produces one "bit test"
1525 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1528 // Make desired shift
1529 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1530 TLI.getPointerTy());
1531 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1533 DAG.getConstant(1, TLI.getPointerTy()),
1536 // Emit bit tests and jumps
1537 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1538 TLI.getPointerTy(), SwitchVal,
1539 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1540 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1541 TLI.getSetCCResultType(AndOp.getValueType()),
1542 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1545 if (DisableScheduling) {
1546 DAG.AssignOrdering(ShiftOp.getNode(), SDNodeOrder);
1547 DAG.AssignOrdering(SwitchVal.getNode(), SDNodeOrder);
1548 DAG.AssignOrdering(AndOp.getNode(), SDNodeOrder);
1549 DAG.AssignOrdering(AndCmp.getNode(), SDNodeOrder);
1552 CurMBB->addSuccessor(B.TargetBB);
1553 CurMBB->addSuccessor(NextMBB);
1555 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1556 MVT::Other, getControlRoot(),
1557 AndCmp, DAG.getBasicBlock(B.TargetBB));
1559 if (DisableScheduling)
1560 DAG.AssignOrdering(BrAnd.getNode(), SDNodeOrder);
1562 // Set NextBlock to be the MBB immediately after the current one, if any.
1563 // This is used to avoid emitting unnecessary branches to the next block.
1564 MachineBasicBlock *NextBlock = 0;
1565 MachineFunction::iterator BBI = CurMBB;
1566 if (++BBI != FuncInfo.MF->end())
1569 if (NextMBB != NextBlock) {
1570 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1571 DAG.getBasicBlock(NextMBB));
1573 if (DisableScheduling)
1574 DAG.AssignOrdering(BrAnd.getNode(), SDNodeOrder);
1580 void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
1581 // Retrieve successors.
1582 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1583 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1585 const Value *Callee(I.getCalledValue());
1586 if (isa<InlineAsm>(Callee))
1589 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1591 // If the value of the invoke is used outside of its defining block, make it
1592 // available as a virtual register.
1593 CopyToExportRegsIfNeeded(&I);
1595 // Update successor info
1596 CurMBB->addSuccessor(Return);
1597 CurMBB->addSuccessor(LandingPad);
1599 // Drop into normal successor.
1600 SDValue Branch = DAG.getNode(ISD::BR, getCurDebugLoc(),
1601 MVT::Other, getControlRoot(),
1602 DAG.getBasicBlock(Return));
1603 DAG.setRoot(Branch);
1605 if (DisableScheduling)
1606 DAG.AssignOrdering(Branch.getNode(), SDNodeOrder);
1609 void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
1612 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1613 /// small case ranges).
1614 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1615 CaseRecVector& WorkList,
1617 MachineBasicBlock* Default) {
1618 Case& BackCase = *(CR.Range.second-1);
1620 // Size is the number of Cases represented by this range.
1621 size_t Size = CR.Range.second - CR.Range.first;
1625 // Get the MachineFunction which holds the current MBB. This is used when
1626 // inserting any additional MBBs necessary to represent the switch.
1627 MachineFunction *CurMF = FuncInfo.MF;
1629 // Figure out which block is immediately after the current one.
1630 MachineBasicBlock *NextBlock = 0;
1631 MachineFunction::iterator BBI = CR.CaseBB;
1633 if (++BBI != FuncInfo.MF->end())
1636 // TODO: If any two of the cases has the same destination, and if one value
1637 // is the same as the other, but has one bit unset that the other has set,
1638 // use bit manipulation to do two compares at once. For example:
1639 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1641 // Rearrange the case blocks so that the last one falls through if possible.
1642 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1643 // The last case block won't fall through into 'NextBlock' if we emit the
1644 // branches in this order. See if rearranging a case value would help.
1645 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1646 if (I->BB == NextBlock) {
1647 std::swap(*I, BackCase);
1653 // Create a CaseBlock record representing a conditional branch to
1654 // the Case's target mbb if the value being switched on SV is equal
1656 MachineBasicBlock *CurBlock = CR.CaseBB;
1657 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1658 MachineBasicBlock *FallThrough;
1660 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1661 CurMF->insert(BBI, FallThrough);
1663 // Put SV in a virtual register to make it available from the new blocks.
1664 ExportFromCurrentBlock(SV);
1666 // If the last case doesn't match, go to the default block.
1667 FallThrough = Default;
1670 Value *RHS, *LHS, *MHS;
1672 if (I->High == I->Low) {
1673 // This is just small small case range :) containing exactly 1 case
1675 LHS = SV; RHS = I->High; MHS = NULL;
1678 LHS = I->Low; MHS = SV; RHS = I->High;
1680 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1682 // If emitting the first comparison, just call visitSwitchCase to emit the
1683 // code into the current block. Otherwise, push the CaseBlock onto the
1684 // vector to be later processed by SDISel, and insert the node's MBB
1685 // before the next MBB.
1686 if (CurBlock == CurMBB)
1687 visitSwitchCase(CB);
1689 SwitchCases.push_back(CB);
1691 CurBlock = FallThrough;
1697 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1698 return !DisableJumpTables &&
1699 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1700 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1703 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1704 APInt LastExt(Last), FirstExt(First);
1705 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1706 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1707 return (LastExt - FirstExt + 1ULL);
1710 /// handleJTSwitchCase - Emit jumptable for current switch case range
1711 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1712 CaseRecVector& WorkList,
1714 MachineBasicBlock* Default) {
1715 Case& FrontCase = *CR.Range.first;
1716 Case& BackCase = *(CR.Range.second-1);
1718 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1719 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1721 APInt TSize(First.getBitWidth(), 0);
1722 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1726 if (!areJTsAllowed(TLI) || TSize.ult(APInt(First.getBitWidth(), 4)))
1729 APInt Range = ComputeRange(First, Last);
1730 double Density = TSize.roundToDouble() / Range.roundToDouble();
1734 DEBUG(errs() << "Lowering jump table\n"
1735 << "First entry: " << First << ". Last entry: " << Last << '\n'
1736 << "Range: " << Range
1737 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1739 // Get the MachineFunction which holds the current MBB. This is used when
1740 // inserting any additional MBBs necessary to represent the switch.
1741 MachineFunction *CurMF = FuncInfo.MF;
1743 // Figure out which block is immediately after the current one.
1744 MachineFunction::iterator BBI = CR.CaseBB;
1747 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1749 // Create a new basic block to hold the code for loading the address
1750 // of the jump table, and jumping to it. Update successor information;
1751 // we will either branch to the default case for the switch, or the jump
1753 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1754 CurMF->insert(BBI, JumpTableBB);
1755 CR.CaseBB->addSuccessor(Default);
1756 CR.CaseBB->addSuccessor(JumpTableBB);
1758 // Build a vector of destination BBs, corresponding to each target
1759 // of the jump table. If the value of the jump table slot corresponds to
1760 // a case statement, push the case's BB onto the vector, otherwise, push
1762 std::vector<MachineBasicBlock*> DestBBs;
1764 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1765 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1766 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1768 if (Low.sle(TEI) && TEI.sle(High)) {
1769 DestBBs.push_back(I->BB);
1773 DestBBs.push_back(Default);
1777 // Update successor info. Add one edge to each unique successor.
1778 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1779 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1780 E = DestBBs.end(); I != E; ++I) {
1781 if (!SuccsHandled[(*I)->getNumber()]) {
1782 SuccsHandled[(*I)->getNumber()] = true;
1783 JumpTableBB->addSuccessor(*I);
1787 // Create a jump table index for this jump table, or return an existing
1789 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1791 // Set the jump table information so that we can codegen it as a second
1792 // MachineBasicBlock
1793 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1794 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1795 if (CR.CaseBB == CurMBB)
1796 visitJumpTableHeader(JT, JTH);
1798 JTCases.push_back(JumpTableBlock(JTH, JT));
1803 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1805 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1806 CaseRecVector& WorkList,
1808 MachineBasicBlock* Default) {
1809 // Get the MachineFunction which holds the current MBB. This is used when
1810 // inserting any additional MBBs necessary to represent the switch.
1811 MachineFunction *CurMF = FuncInfo.MF;
1813 // Figure out which block is immediately after the current one.
1814 MachineFunction::iterator BBI = CR.CaseBB;
1817 Case& FrontCase = *CR.Range.first;
1818 Case& BackCase = *(CR.Range.second-1);
1819 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1821 // Size is the number of Cases represented by this range.
1822 unsigned Size = CR.Range.second - CR.Range.first;
1824 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1825 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1827 CaseItr Pivot = CR.Range.first + Size/2;
1829 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1830 // (heuristically) allow us to emit JumpTable's later.
1831 APInt TSize(First.getBitWidth(), 0);
1832 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1836 APInt LSize = FrontCase.size();
1837 APInt RSize = TSize-LSize;
1838 DEBUG(errs() << "Selecting best pivot: \n"
1839 << "First: " << First << ", Last: " << Last <<'\n'
1840 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1841 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1843 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1844 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1845 APInt Range = ComputeRange(LEnd, RBegin);
1846 assert((Range - 2ULL).isNonNegative() &&
1847 "Invalid case distance");
1848 double LDensity = (double)LSize.roundToDouble() /
1849 (LEnd - First + 1ULL).roundToDouble();
1850 double RDensity = (double)RSize.roundToDouble() /
1851 (Last - RBegin + 1ULL).roundToDouble();
1852 double Metric = Range.logBase2()*(LDensity+RDensity);
1853 // Should always split in some non-trivial place
1854 DEBUG(errs() <<"=>Step\n"
1855 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1856 << "LDensity: " << LDensity
1857 << ", RDensity: " << RDensity << '\n'
1858 << "Metric: " << Metric << '\n');
1859 if (FMetric < Metric) {
1862 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1868 if (areJTsAllowed(TLI)) {
1869 // If our case is dense we *really* should handle it earlier!
1870 assert((FMetric > 0) && "Should handle dense range earlier!");
1872 Pivot = CR.Range.first + Size/2;
1875 CaseRange LHSR(CR.Range.first, Pivot);
1876 CaseRange RHSR(Pivot, CR.Range.second);
1877 Constant *C = Pivot->Low;
1878 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1880 // We know that we branch to the LHS if the Value being switched on is
1881 // less than the Pivot value, C. We use this to optimize our binary
1882 // tree a bit, by recognizing that if SV is greater than or equal to the
1883 // LHS's Case Value, and that Case Value is exactly one less than the
1884 // Pivot's Value, then we can branch directly to the LHS's Target,
1885 // rather than creating a leaf node for it.
1886 if ((LHSR.second - LHSR.first) == 1 &&
1887 LHSR.first->High == CR.GE &&
1888 cast<ConstantInt>(C)->getValue() ==
1889 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1890 TrueBB = LHSR.first->BB;
1892 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1893 CurMF->insert(BBI, TrueBB);
1894 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1896 // Put SV in a virtual register to make it available from the new blocks.
1897 ExportFromCurrentBlock(SV);
1900 // Similar to the optimization above, if the Value being switched on is
1901 // known to be less than the Constant CR.LT, and the current Case Value
1902 // is CR.LT - 1, then we can branch directly to the target block for
1903 // the current Case Value, rather than emitting a RHS leaf node for it.
1904 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1905 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1906 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1907 FalseBB = RHSR.first->BB;
1909 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1910 CurMF->insert(BBI, FalseBB);
1911 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1913 // Put SV in a virtual register to make it available from the new blocks.
1914 ExportFromCurrentBlock(SV);
1917 // Create a CaseBlock record representing a conditional branch to
1918 // the LHS node if the value being switched on SV is less than C.
1919 // Otherwise, branch to LHS.
1920 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1922 if (CR.CaseBB == CurMBB)
1923 visitSwitchCase(CB);
1925 SwitchCases.push_back(CB);
1930 /// handleBitTestsSwitchCase - if current case range has few destination and
1931 /// range span less, than machine word bitwidth, encode case range into series
1932 /// of masks and emit bit tests with these masks.
1933 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1934 CaseRecVector& WorkList,
1936 MachineBasicBlock* Default){
1937 EVT PTy = TLI.getPointerTy();
1938 unsigned IntPtrBits = PTy.getSizeInBits();
1940 Case& FrontCase = *CR.Range.first;
1941 Case& BackCase = *(CR.Range.second-1);
1943 // Get the MachineFunction which holds the current MBB. This is used when
1944 // inserting any additional MBBs necessary to represent the switch.
1945 MachineFunction *CurMF = FuncInfo.MF;
1947 // If target does not have legal shift left, do not emit bit tests at all.
1948 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1952 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1954 // Single case counts one, case range - two.
1955 numCmps += (I->Low == I->High ? 1 : 2);
1958 // Count unique destinations
1959 SmallSet<MachineBasicBlock*, 4> Dests;
1960 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1961 Dests.insert(I->BB);
1962 if (Dests.size() > 3)
1963 // Don't bother the code below, if there are too much unique destinations
1966 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1967 << "Total number of comparisons: " << numCmps << '\n');
1969 // Compute span of values.
1970 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1971 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1972 APInt cmpRange = maxValue - minValue;
1974 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1975 << "Low bound: " << minValue << '\n'
1976 << "High bound: " << maxValue << '\n');
1978 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1979 (!(Dests.size() == 1 && numCmps >= 3) &&
1980 !(Dests.size() == 2 && numCmps >= 5) &&
1981 !(Dests.size() >= 3 && numCmps >= 6)))
1984 DEBUG(errs() << "Emitting bit tests\n");
1985 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1987 // Optimize the case where all the case values fit in a
1988 // word without having to subtract minValue. In this case,
1989 // we can optimize away the subtraction.
1990 if (minValue.isNonNegative() &&
1991 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1992 cmpRange = maxValue;
1994 lowBound = minValue;
1997 CaseBitsVector CasesBits;
1998 unsigned i, count = 0;
2000 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2001 MachineBasicBlock* Dest = I->BB;
2002 for (i = 0; i < count; ++i)
2003 if (Dest == CasesBits[i].BB)
2007 assert((count < 3) && "Too much destinations to test!");
2008 CasesBits.push_back(CaseBits(0, Dest, 0));
2012 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2013 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2015 uint64_t lo = (lowValue - lowBound).getZExtValue();
2016 uint64_t hi = (highValue - lowBound).getZExtValue();
2018 for (uint64_t j = lo; j <= hi; j++) {
2019 CasesBits[i].Mask |= 1ULL << j;
2020 CasesBits[i].Bits++;
2024 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2028 // Figure out which block is immediately after the current one.
2029 MachineFunction::iterator BBI = CR.CaseBB;
2032 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2034 DEBUG(errs() << "Cases:\n");
2035 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2036 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2037 << ", Bits: " << CasesBits[i].Bits
2038 << ", BB: " << CasesBits[i].BB << '\n');
2040 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2041 CurMF->insert(BBI, CaseBB);
2042 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2046 // Put SV in a virtual register to make it available from the new blocks.
2047 ExportFromCurrentBlock(SV);
2050 BitTestBlock BTB(lowBound, cmpRange, SV,
2051 -1U, (CR.CaseBB == CurMBB),
2052 CR.CaseBB, Default, BTC);
2054 if (CR.CaseBB == CurMBB)
2055 visitBitTestHeader(BTB);
2057 BitTestCases.push_back(BTB);
2062 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2063 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2064 const SwitchInst& SI) {
2067 // Start with "simple" cases
2068 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2069 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2070 Cases.push_back(Case(SI.getSuccessorValue(i),
2071 SI.getSuccessorValue(i),
2074 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2076 // Merge case into clusters
2077 if (Cases.size() >= 2)
2078 // Must recompute end() each iteration because it may be
2079 // invalidated by erase if we hold on to it
2080 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2081 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2082 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2083 MachineBasicBlock* nextBB = J->BB;
2084 MachineBasicBlock* currentBB = I->BB;
2086 // If the two neighboring cases go to the same destination, merge them
2087 // into a single case.
2088 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2096 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2097 if (I->Low != I->High)
2098 // A range counts double, since it requires two compares.
2105 void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
2106 // Figure out which block is immediately after the current one.
2107 MachineBasicBlock *NextBlock = 0;
2108 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2110 // If there is only the default destination, branch to it if it is not the
2111 // next basic block. Otherwise, just fall through.
2112 if (SI.getNumOperands() == 2) {
2113 // Update machine-CFG edges.
2115 // If this is not a fall-through branch, emit the branch.
2116 CurMBB->addSuccessor(Default);
2117 if (Default != NextBlock) {
2118 SDValue Res = DAG.getNode(ISD::BR, getCurDebugLoc(),
2119 MVT::Other, getControlRoot(),
2120 DAG.getBasicBlock(Default));
2123 if (DisableScheduling)
2124 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2130 // If there are any non-default case statements, create a vector of Cases
2131 // representing each one, and sort the vector so that we can efficiently
2132 // create a binary search tree from them.
2134 size_t numCmps = Clusterify(Cases, SI);
2135 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2136 << ". Total compares: " << numCmps << '\n');
2139 // Get the Value to be switched on and default basic blocks, which will be
2140 // inserted into CaseBlock records, representing basic blocks in the binary
2142 Value *SV = SI.getOperand(0);
2144 // Push the initial CaseRec onto the worklist
2145 CaseRecVector WorkList;
2146 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2148 while (!WorkList.empty()) {
2149 // Grab a record representing a case range to process off the worklist
2150 CaseRec CR = WorkList.back();
2151 WorkList.pop_back();
2153 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2156 // If the range has few cases (two or less) emit a series of specific
2158 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2161 // If the switch has more than 5 blocks, and at least 40% dense, and the
2162 // target supports indirect branches, then emit a jump table rather than
2163 // lowering the switch to a binary tree of conditional branches.
2164 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2167 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2168 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2169 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2173 void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
2174 // Update machine-CFG edges.
2175 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2176 CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);
2178 SDValue Res = DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2179 MVT::Other, getControlRoot(),
2180 getValue(I.getAddress()));
2183 if (DisableScheduling)
2184 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2187 void SelectionDAGBuilder::visitFSub(User &I) {
2188 // -0.0 - X --> fneg
2189 const Type *Ty = I.getType();
2190 if (isa<VectorType>(Ty)) {
2191 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2192 const VectorType *DestTy = cast<VectorType>(I.getType());
2193 const Type *ElTy = DestTy->getElementType();
2194 unsigned VL = DestTy->getNumElements();
2195 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2196 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2198 SDValue Op2 = getValue(I.getOperand(1));
2199 SDValue Res = DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2200 Op2.getValueType(), Op2);
2203 if (DisableScheduling)
2204 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2211 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2212 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2213 SDValue Op2 = getValue(I.getOperand(1));
2214 SDValue Res = DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2215 Op2.getValueType(), Op2);
2218 if (DisableScheduling)
2219 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2224 visitBinary(I, ISD::FSUB);
2227 void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
2228 SDValue Op1 = getValue(I.getOperand(0));
2229 SDValue Op2 = getValue(I.getOperand(1));
2230 SDValue Res = DAG.getNode(OpCode, getCurDebugLoc(),
2231 Op1.getValueType(), Op1, Op2);
2234 if (DisableScheduling)
2235 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2238 void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
2239 SDValue Op1 = getValue(I.getOperand(0));
2240 SDValue Op2 = getValue(I.getOperand(1));
2241 if (!isa<VectorType>(I.getType()) &&
2242 Op2.getValueType() != TLI.getShiftAmountTy()) {
2243 // If the operand is smaller than the shift count type, promote it.
2244 EVT PTy = TLI.getPointerTy();
2245 EVT STy = TLI.getShiftAmountTy();
2246 if (STy.bitsGT(Op2.getValueType()))
2247 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2248 TLI.getShiftAmountTy(), Op2);
2249 // If the operand is larger than the shift count type but the shift
2250 // count type has enough bits to represent any shift value, truncate
2251 // it now. This is a common case and it exposes the truncate to
2252 // optimization early.
2253 else if (STy.getSizeInBits() >=
2254 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2255 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2256 TLI.getShiftAmountTy(), Op2);
2257 // Otherwise we'll need to temporarily settle for some other
2258 // convenient type; type legalization will make adjustments as
2260 else if (PTy.bitsLT(Op2.getValueType()))
2261 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2262 TLI.getPointerTy(), Op2);
2263 else if (PTy.bitsGT(Op2.getValueType()))
2264 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2265 TLI.getPointerTy(), Op2);
2268 SDValue Res = DAG.getNode(Opcode, getCurDebugLoc(),
2269 Op1.getValueType(), Op1, Op2);
2272 if (DisableScheduling) {
2273 DAG.AssignOrdering(Op1.getNode(), SDNodeOrder);
2274 DAG.AssignOrdering(Op2.getNode(), SDNodeOrder);
2275 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2279 void SelectionDAGBuilder::visitICmp(User &I) {
2280 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2281 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2282 predicate = IC->getPredicate();
2283 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2284 predicate = ICmpInst::Predicate(IC->getPredicate());
2285 SDValue Op1 = getValue(I.getOperand(0));
2286 SDValue Op2 = getValue(I.getOperand(1));
2287 ISD::CondCode Opcode = getICmpCondCode(predicate);
2289 EVT DestVT = TLI.getValueType(I.getType());
2290 SDValue Res = DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode);
2293 if (DisableScheduling)
2294 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2297 void SelectionDAGBuilder::visitFCmp(User &I) {
2298 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2299 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2300 predicate = FC->getPredicate();
2301 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2302 predicate = FCmpInst::Predicate(FC->getPredicate());
2303 SDValue Op1 = getValue(I.getOperand(0));
2304 SDValue Op2 = getValue(I.getOperand(1));
2305 ISD::CondCode Condition = getFCmpCondCode(predicate);
2306 EVT DestVT = TLI.getValueType(I.getType());
2307 SDValue Res = DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition);
2310 if (DisableScheduling)
2311 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2314 void SelectionDAGBuilder::visitSelect(User &I) {
2315 SmallVector<EVT, 4> ValueVTs;
2316 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2317 unsigned NumValues = ValueVTs.size();
2318 if (NumValues == 0) return;
2320 SmallVector<SDValue, 4> Values(NumValues);
2321 SDValue Cond = getValue(I.getOperand(0));
2322 SDValue TrueVal = getValue(I.getOperand(1));
2323 SDValue FalseVal = getValue(I.getOperand(2));
2325 for (unsigned i = 0; i != NumValues; ++i) {
2326 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2327 TrueVal.getNode()->getValueType(i), Cond,
2328 SDValue(TrueVal.getNode(),
2329 TrueVal.getResNo() + i),
2330 SDValue(FalseVal.getNode(),
2331 FalseVal.getResNo() + i));
2333 if (DisableScheduling)
2334 DAG.AssignOrdering(Values[i].getNode(), SDNodeOrder);
2337 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2338 DAG.getVTList(&ValueVTs[0], NumValues),
2339 &Values[0], NumValues);
2342 if (DisableScheduling)
2343 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2346 void SelectionDAGBuilder::visitTrunc(User &I) {
2347 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2348 SDValue N = getValue(I.getOperand(0));
2349 EVT DestVT = TLI.getValueType(I.getType());
2350 SDValue Res = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2353 if (DisableScheduling)
2354 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2357 void SelectionDAGBuilder::visitZExt(User &I) {
2358 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2359 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2360 SDValue N = getValue(I.getOperand(0));
2361 EVT DestVT = TLI.getValueType(I.getType());
2362 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2365 if (DisableScheduling)
2366 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2369 void SelectionDAGBuilder::visitSExt(User &I) {
2370 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2371 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2372 SDValue N = getValue(I.getOperand(0));
2373 EVT DestVT = TLI.getValueType(I.getType());
2374 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N);
2377 if (DisableScheduling)
2378 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2381 void SelectionDAGBuilder::visitFPTrunc(User &I) {
2382 // FPTrunc is never a no-op cast, no need to check
2383 SDValue N = getValue(I.getOperand(0));
2384 EVT DestVT = TLI.getValueType(I.getType());
2385 SDValue Res = DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2386 DestVT, N, DAG.getIntPtrConstant(0));
2389 if (DisableScheduling)
2390 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2393 void SelectionDAGBuilder::visitFPExt(User &I){
2394 // FPTrunc is never a no-op cast, no need to check
2395 SDValue N = getValue(I.getOperand(0));
2396 EVT DestVT = TLI.getValueType(I.getType());
2397 SDValue Res = DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N);
2400 if (DisableScheduling)
2401 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2404 void SelectionDAGBuilder::visitFPToUI(User &I) {
2405 // FPToUI is never a no-op cast, no need to check
2406 SDValue N = getValue(I.getOperand(0));
2407 EVT DestVT = TLI.getValueType(I.getType());
2408 SDValue Res = DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N);
2411 if (DisableScheduling)
2412 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2415 void SelectionDAGBuilder::visitFPToSI(User &I) {
2416 // FPToSI is never a no-op cast, no need to check
2417 SDValue N = getValue(I.getOperand(0));
2418 EVT DestVT = TLI.getValueType(I.getType());
2419 SDValue Res = DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N);
2422 if (DisableScheduling)
2423 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2426 void SelectionDAGBuilder::visitUIToFP(User &I) {
2427 // UIToFP is never a no-op cast, no need to check
2428 SDValue N = getValue(I.getOperand(0));
2429 EVT DestVT = TLI.getValueType(I.getType());
2430 SDValue Res = DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N);
2433 if (DisableScheduling)
2434 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2437 void SelectionDAGBuilder::visitSIToFP(User &I){
2438 // SIToFP is never a no-op cast, no need to check
2439 SDValue N = getValue(I.getOperand(0));
2440 EVT DestVT = TLI.getValueType(I.getType());
2441 SDValue Res = DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N);
2444 if (DisableScheduling)
2445 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2448 void SelectionDAGBuilder::visitPtrToInt(User &I) {
2449 // What to do depends on the size of the integer and the size of the pointer.
2450 // We can either truncate, zero extend, or no-op, accordingly.
2451 SDValue N = getValue(I.getOperand(0));
2452 EVT SrcVT = N.getValueType();
2453 EVT DestVT = TLI.getValueType(I.getType());
2454 SDValue Res = DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT);
2457 if (DisableScheduling)
2458 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2461 void SelectionDAGBuilder::visitIntToPtr(User &I) {
2462 // What to do depends on the size of the integer and the size of the pointer.
2463 // We can either truncate, zero extend, or no-op, accordingly.
2464 SDValue N = getValue(I.getOperand(0));
2465 EVT SrcVT = N.getValueType();
2466 EVT DestVT = TLI.getValueType(I.getType());
2467 SDValue Res = DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT);
2470 if (DisableScheduling)
2471 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2474 void SelectionDAGBuilder::visitBitCast(User &I) {
2475 SDValue N = getValue(I.getOperand(0));
2476 EVT DestVT = TLI.getValueType(I.getType());
2478 // BitCast assures us that source and destination are the same size so this is
2479 // either a BIT_CONVERT or a no-op.
2480 if (DestVT != N.getValueType()) {
2481 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2482 DestVT, N); // convert types.
2485 if (DisableScheduling)
2486 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2488 setValue(&I, N); // noop cast.
2492 void SelectionDAGBuilder::visitInsertElement(User &I) {
2493 SDValue InVec = getValue(I.getOperand(0));
2494 SDValue InVal = getValue(I.getOperand(1));
2495 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2497 getValue(I.getOperand(2)));
2498 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2499 TLI.getValueType(I.getType()),
2500 InVec, InVal, InIdx);
2503 if (DisableScheduling) {
2504 DAG.AssignOrdering(InIdx.getNode(), SDNodeOrder);
2505 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2509 void SelectionDAGBuilder::visitExtractElement(User &I) {
2510 SDValue InVec = getValue(I.getOperand(0));
2511 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2513 getValue(I.getOperand(1)));
2514 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2515 TLI.getValueType(I.getType()), InVec, InIdx);
2518 if (DisableScheduling) {
2519 DAG.AssignOrdering(InIdx.getNode(), SDNodeOrder);
2520 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2525 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2526 // from SIndx and increasing to the element length (undefs are allowed).
2527 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2528 unsigned MaskNumElts = Mask.size();
2529 for (unsigned i = 0; i != MaskNumElts; ++i)
2530 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2535 void SelectionDAGBuilder::visitShuffleVector(User &I) {
2536 SmallVector<int, 8> Mask;
2537 SDValue Src1 = getValue(I.getOperand(0));
2538 SDValue Src2 = getValue(I.getOperand(1));
2540 // Convert the ConstantVector mask operand into an array of ints, with -1
2541 // representing undef values.
2542 SmallVector<Constant*, 8> MaskElts;
2543 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2545 unsigned MaskNumElts = MaskElts.size();
2546 for (unsigned i = 0; i != MaskNumElts; ++i) {
2547 if (isa<UndefValue>(MaskElts[i]))
2550 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2553 EVT VT = TLI.getValueType(I.getType());
2554 EVT SrcVT = Src1.getValueType();
2555 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2557 if (SrcNumElts == MaskNumElts) {
2558 SDValue Res = DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2562 if (DisableScheduling)
2563 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2568 // Normalize the shuffle vector since mask and vector length don't match.
2569 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2570 // Mask is longer than the source vectors and is a multiple of the source
2571 // vectors. We can use concatenate vector to make the mask and vectors
2573 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2574 // The shuffle is concatenating two vectors together.
2575 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2579 if (DisableScheduling)
2580 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2585 // Pad both vectors with undefs to make them the same length as the mask.
2586 unsigned NumConcat = MaskNumElts / SrcNumElts;
2587 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2588 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2589 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2591 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2592 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2596 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2597 getCurDebugLoc(), VT,
2598 &MOps1[0], NumConcat);
2599 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2600 getCurDebugLoc(), VT,
2601 &MOps2[0], NumConcat);
2603 // Readjust mask for new input vector length.
2604 SmallVector<int, 8> MappedOps;
2605 for (unsigned i = 0; i != MaskNumElts; ++i) {
2607 if (Idx < (int)SrcNumElts)
2608 MappedOps.push_back(Idx);
2610 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2613 SDValue Res = DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2617 if (DisableScheduling) {
2618 DAG.AssignOrdering(Src1.getNode(), SDNodeOrder);
2619 DAG.AssignOrdering(Src2.getNode(), SDNodeOrder);
2620 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2626 if (SrcNumElts > MaskNumElts) {
2627 // Analyze the access pattern of the vector to see if we can extract
2628 // two subvectors and do the shuffle. The analysis is done by calculating
2629 // the range of elements the mask access on both vectors.
2630 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2631 int MaxRange[2] = {-1, -1};
2633 for (unsigned i = 0; i != MaskNumElts; ++i) {
2639 if (Idx >= (int)SrcNumElts) {
2643 if (Idx > MaxRange[Input])
2644 MaxRange[Input] = Idx;
2645 if (Idx < MinRange[Input])
2646 MinRange[Input] = Idx;
2649 // Check if the access is smaller than the vector size and can we find
2650 // a reasonable extract index.
2651 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2652 int StartIdx[2]; // StartIdx to extract from
2653 for (int Input=0; Input < 2; ++Input) {
2654 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2655 RangeUse[Input] = 0; // Unused
2656 StartIdx[Input] = 0;
2657 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2658 // Fits within range but we should see if we can find a good
2659 // start index that is a multiple of the mask length.
2660 if (MaxRange[Input] < (int)MaskNumElts) {
2661 RangeUse[Input] = 1; // Extract from beginning of the vector
2662 StartIdx[Input] = 0;
2664 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2665 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2666 StartIdx[Input] + MaskNumElts < SrcNumElts)
2667 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2672 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2673 SDValue Res = DAG.getUNDEF(VT);
2674 setValue(&I, Res); // Vectors are not used.
2676 if (DisableScheduling)
2677 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2681 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2682 // Extract appropriate subvector and generate a vector shuffle
2683 for (int Input=0; Input < 2; ++Input) {
2684 SDValue &Src = Input == 0 ? Src1 : Src2;
2685 if (RangeUse[Input] == 0)
2686 Src = DAG.getUNDEF(VT);
2688 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2689 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2691 if (DisableScheduling)
2692 DAG.AssignOrdering(Src.getNode(), SDNodeOrder);
2695 // Calculate new mask.
2696 SmallVector<int, 8> MappedOps;
2697 for (unsigned i = 0; i != MaskNumElts; ++i) {
2700 MappedOps.push_back(Idx);
2701 else if (Idx < (int)SrcNumElts)
2702 MappedOps.push_back(Idx - StartIdx[0]);
2704 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2707 SDValue Res = DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2711 if (DisableScheduling)
2712 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2718 // We can't use either concat vectors or extract subvectors so fall back to
2719 // replacing the shuffle with extract and build vector.
2720 // to insert and build vector.
2721 EVT EltVT = VT.getVectorElementType();
2722 EVT PtrVT = TLI.getPointerTy();
2723 SmallVector<SDValue,8> Ops;
2724 for (unsigned i = 0; i != MaskNumElts; ++i) {
2726 Ops.push_back(DAG.getUNDEF(EltVT));
2731 if (Idx < (int)SrcNumElts)
2732 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2733 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2735 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2737 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2741 if (DisableScheduling)
2742 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2746 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2747 VT, &Ops[0], Ops.size());
2750 if (DisableScheduling)
2751 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2754 void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) {
2755 const Value *Op0 = I.getOperand(0);
2756 const Value *Op1 = I.getOperand(1);
2757 const Type *AggTy = I.getType();
2758 const Type *ValTy = Op1->getType();
2759 bool IntoUndef = isa<UndefValue>(Op0);
2760 bool FromUndef = isa<UndefValue>(Op1);
2762 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2763 I.idx_begin(), I.idx_end());
2765 SmallVector<EVT, 4> AggValueVTs;
2766 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2767 SmallVector<EVT, 4> ValValueVTs;
2768 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2770 unsigned NumAggValues = AggValueVTs.size();
2771 unsigned NumValValues = ValValueVTs.size();
2772 SmallVector<SDValue, 4> Values(NumAggValues);
2774 SDValue Agg = getValue(Op0);
2775 SDValue Val = getValue(Op1);
2777 // Copy the beginning value(s) from the original aggregate.
2778 for (; i != LinearIndex; ++i)
2779 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2780 SDValue(Agg.getNode(), Agg.getResNo() + i);
2781 // Copy values from the inserted value(s).
2782 for (; i != LinearIndex + NumValValues; ++i)
2783 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2784 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2785 // Copy remaining value(s) from the original aggregate.
2786 for (; i != NumAggValues; ++i)
2787 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2788 SDValue(Agg.getNode(), Agg.getResNo() + i);
2790 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2791 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2792 &Values[0], NumAggValues);
2795 if (DisableScheduling)
2796 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2799 void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) {
2800 const Value *Op0 = I.getOperand(0);
2801 const Type *AggTy = Op0->getType();
2802 const Type *ValTy = I.getType();
2803 bool OutOfUndef = isa<UndefValue>(Op0);
2805 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2806 I.idx_begin(), I.idx_end());
2808 SmallVector<EVT, 4> ValValueVTs;
2809 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2811 unsigned NumValValues = ValValueVTs.size();
2812 SmallVector<SDValue, 4> Values(NumValValues);
2814 SDValue Agg = getValue(Op0);
2815 // Copy out the selected value(s).
2816 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2817 Values[i - LinearIndex] =
2819 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2820 SDValue(Agg.getNode(), Agg.getResNo() + i);
2822 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2823 DAG.getVTList(&ValValueVTs[0], NumValValues),
2824 &Values[0], NumValValues);
2827 if (DisableScheduling)
2828 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
2831 void SelectionDAGBuilder::visitGetElementPtr(User &I) {
2832 SDValue N = getValue(I.getOperand(0));
2833 const Type *Ty = I.getOperand(0)->getType();
2835 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2838 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2839 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2842 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2843 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2844 DAG.getIntPtrConstant(Offset));
2846 if (DisableScheduling)
2847 DAG.AssignOrdering(N.getNode(), SDNodeOrder);
2850 Ty = StTy->getElementType(Field);
2852 Ty = cast<SequentialType>(Ty)->getElementType();
2854 // If this is a constant subscript, handle it quickly.
2855 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2856 if (CI->getZExtValue() == 0) continue;
2858 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2860 EVT PTy = TLI.getPointerTy();
2861 unsigned PtrBits = PTy.getSizeInBits();
2863 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2865 DAG.getConstant(Offs, MVT::i64));
2867 OffsVal = DAG.getIntPtrConstant(Offs);
2869 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2872 if (DisableScheduling) {
2873 DAG.AssignOrdering(OffsVal.getNode(), SDNodeOrder);
2874 DAG.AssignOrdering(N.getNode(), SDNodeOrder);
2880 // N = N + Idx * ElementSize;
2881 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2882 TD->getTypeAllocSize(Ty));
2883 SDValue IdxN = getValue(Idx);
2885 // If the index is smaller or larger than intptr_t, truncate or extend
2887 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2889 // If this is a multiply by a power of two, turn it into a shl
2890 // immediately. This is a very common case.
2891 if (ElementSize != 1) {
2892 if (ElementSize.isPowerOf2()) {
2893 unsigned Amt = ElementSize.logBase2();
2894 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2895 N.getValueType(), IdxN,
2896 DAG.getConstant(Amt, TLI.getPointerTy()));
2898 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2899 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2900 N.getValueType(), IdxN, Scale);
2903 if (DisableScheduling)
2904 DAG.AssignOrdering(IdxN.getNode(), SDNodeOrder);
2907 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2908 N.getValueType(), N, IdxN);
2910 if (DisableScheduling)
2911 DAG.AssignOrdering(N.getNode(), SDNodeOrder);
2918 void SelectionDAGBuilder::visitAlloca(AllocaInst &I) {
2919 // If this is a fixed sized alloca in the entry block of the function,
2920 // allocate it statically on the stack.
2921 if (FuncInfo.StaticAllocaMap.count(&I))
2922 return; // getValue will auto-populate this.
2924 const Type *Ty = I.getAllocatedType();
2925 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2927 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2930 SDValue AllocSize = getValue(I.getArraySize());
2932 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2934 DAG.getConstant(TySize, AllocSize.getValueType()));
2936 if (DisableScheduling)
2937 DAG.AssignOrdering(AllocSize.getNode(), SDNodeOrder);
2939 EVT IntPtr = TLI.getPointerTy();
2940 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2942 if (DisableScheduling)
2943 DAG.AssignOrdering(AllocSize.getNode(), SDNodeOrder);
2945 // Handle alignment. If the requested alignment is less than or equal to
2946 // the stack alignment, ignore it. If the size is greater than or equal to
2947 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2948 unsigned StackAlign =
2949 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2950 if (Align <= StackAlign)
2953 // Round the size of the allocation up to the stack alignment size
2954 // by add SA-1 to the size.
2955 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2956 AllocSize.getValueType(), AllocSize,
2957 DAG.getIntPtrConstant(StackAlign-1));
2958 if (DisableScheduling)
2959 DAG.AssignOrdering(AllocSize.getNode(), SDNodeOrder);
2961 // Mask out the low bits for alignment purposes.
2962 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2963 AllocSize.getValueType(), AllocSize,
2964 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2965 if (DisableScheduling)
2966 DAG.AssignOrdering(AllocSize.getNode(), SDNodeOrder);
2968 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2969 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2970 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2973 DAG.setRoot(DSA.getValue(1));
2975 if (DisableScheduling)
2976 DAG.AssignOrdering(DSA.getNode(), SDNodeOrder);
2978 // Inform the Frame Information that we have just allocated a variable-sized
2980 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2983 void SelectionDAGBuilder::visitLoad(LoadInst &I) {
2984 const Value *SV = I.getOperand(0);
2985 SDValue Ptr = getValue(SV);
2987 const Type *Ty = I.getType();
2988 bool isVolatile = I.isVolatile();
2989 unsigned Alignment = I.getAlignment();
2991 SmallVector<EVT, 4> ValueVTs;
2992 SmallVector<uint64_t, 4> Offsets;
2993 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2994 unsigned NumValues = ValueVTs.size();
2999 bool ConstantMemory = false;
3001 // Serialize volatile loads with other side effects.
3003 else if (AA->pointsToConstantMemory(SV)) {
3004 // Do not serialize (non-volatile) loads of constant memory with anything.
3005 Root = DAG.getEntryNode();
3006 ConstantMemory = true;
3008 // Do not serialize non-volatile loads against each other.
3009 Root = DAG.getRoot();
3012 SmallVector<SDValue, 4> Values(NumValues);
3013 SmallVector<SDValue, 4> Chains(NumValues);
3014 EVT PtrVT = Ptr.getValueType();
3015 for (unsigned i = 0; i != NumValues; ++i) {
3016 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3018 DAG.getConstant(Offsets[i], PtrVT));
3019 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3020 A, SV, Offsets[i], isVolatile, Alignment);
3023 Chains[i] = L.getValue(1);
3025 if (DisableScheduling) {
3026 DAG.AssignOrdering(A.getNode(), SDNodeOrder);
3027 DAG.AssignOrdering(L.getNode(), SDNodeOrder);
3031 if (!ConstantMemory) {
3032 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3033 MVT::Other, &Chains[0], NumValues);
3037 PendingLoads.push_back(Chain);
3039 if (DisableScheduling)
3040 DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
3043 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3044 DAG.getVTList(&ValueVTs[0], NumValues),
3045 &Values[0], NumValues);
3048 if (DisableScheduling)
3049 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
3052 void SelectionDAGBuilder::visitStore(StoreInst &I) {
3053 Value *SrcV = I.getOperand(0);
3054 Value *PtrV = I.getOperand(1);
3056 SmallVector<EVT, 4> ValueVTs;
3057 SmallVector<uint64_t, 4> Offsets;
3058 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3059 unsigned NumValues = ValueVTs.size();
3063 // Get the lowered operands. Note that we do this after
3064 // checking if NumResults is zero, because with zero results
3065 // the operands won't have values in the map.
3066 SDValue Src = getValue(SrcV);
3067 SDValue Ptr = getValue(PtrV);
3069 SDValue Root = getRoot();
3070 SmallVector<SDValue, 4> Chains(NumValues);
3071 EVT PtrVT = Ptr.getValueType();
3072 bool isVolatile = I.isVolatile();
3073 unsigned Alignment = I.getAlignment();
3075 for (unsigned i = 0; i != NumValues; ++i) {
3076 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3077 DAG.getConstant(Offsets[i], PtrVT));
3078 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
3079 SDValue(Src.getNode(), Src.getResNo() + i),
3080 Add, PtrV, Offsets[i], isVolatile, Alignment);
3082 if (DisableScheduling) {
3083 DAG.AssignOrdering(Add.getNode(), SDNodeOrder);
3084 DAG.AssignOrdering(Chains[i].getNode(), SDNodeOrder);
3088 SDValue Res = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3089 MVT::Other, &Chains[0], NumValues);
3092 if (DisableScheduling)
3093 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
3096 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3098 void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
3099 unsigned Intrinsic) {
3100 bool HasChain = !I.doesNotAccessMemory();
3101 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3103 // Build the operand list.
3104 SmallVector<SDValue, 8> Ops;
3105 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3107 // We don't need to serialize loads against other loads.
3108 Ops.push_back(DAG.getRoot());
3110 Ops.push_back(getRoot());
3114 // Info is set by getTgtMemInstrinsic
3115 TargetLowering::IntrinsicInfo Info;
3116 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3118 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3119 if (!IsTgtIntrinsic)
3120 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3122 // Add all operands of the call to the operand list.
3123 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
3124 SDValue Op = getValue(I.getOperand(i));
3125 assert(TLI.isTypeLegal(Op.getValueType()) &&
3126 "Intrinsic uses a non-legal type?");
3130 SmallVector<EVT, 4> ValueVTs;
3131 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3133 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3134 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3135 "Intrinsic uses a non-legal type?");
3140 ValueVTs.push_back(MVT::Other);
3142 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3146 if (IsTgtIntrinsic) {
3147 // This is target intrinsic that touches memory
3148 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3149 VTs, &Ops[0], Ops.size(),
3150 Info.memVT, Info.ptrVal, Info.offset,
3151 Info.align, Info.vol,
3152 Info.readMem, Info.writeMem);
3153 } else if (!HasChain) {
3154 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3155 VTs, &Ops[0], Ops.size());
3156 } else if (I.getType() != Type::getVoidTy(*DAG.getContext())) {
3157 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3158 VTs, &Ops[0], Ops.size());
3160 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3161 VTs, &Ops[0], Ops.size());
3164 if (DisableScheduling)
3165 DAG.AssignOrdering(Result.getNode(), SDNodeOrder);
3168 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3170 PendingLoads.push_back(Chain);
3175 if (I.getType() != Type::getVoidTy(*DAG.getContext())) {
3176 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3177 EVT VT = TLI.getValueType(PTy);
3178 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3180 if (DisableScheduling)
3181 DAG.AssignOrdering(Result.getNode(), SDNodeOrder);
3184 setValue(&I, Result);
3188 /// GetSignificand - Get the significand and build it into a floating-point
3189 /// number with exponent of 1:
3191 /// Op = (Op & 0x007fffff) | 0x3f800000;
3193 /// where Op is the hexidecimal representation of floating point value.
3195 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl, unsigned Order) {
3196 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3197 DAG.getConstant(0x007fffff, MVT::i32));
3198 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3199 DAG.getConstant(0x3f800000, MVT::i32));
3200 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3202 if (DisableScheduling) {
3203 DAG.AssignOrdering(t1.getNode(), Order);
3204 DAG.AssignOrdering(t2.getNode(), Order);
3205 DAG.AssignOrdering(Res.getNode(), Order);
3211 /// GetExponent - Get the exponent:
3213 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3215 /// where Op is the hexidecimal representation of floating point value.
3217 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3218 DebugLoc dl, unsigned Order) {
3219 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3220 DAG.getConstant(0x7f800000, MVT::i32));
3221 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3222 DAG.getConstant(23, TLI.getPointerTy()));
3223 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3224 DAG.getConstant(127, MVT::i32));
3225 SDValue Res = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3227 if (DisableScheduling) {
3228 DAG.AssignOrdering(t0.getNode(), Order);
3229 DAG.AssignOrdering(t1.getNode(), Order);
3230 DAG.AssignOrdering(t2.getNode(), Order);
3231 DAG.AssignOrdering(Res.getNode(), Order);
3237 /// getF32Constant - Get 32-bit floating point constant.
3239 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3240 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3243 /// Inlined utility function to implement binary input atomic intrinsics for
3244 /// visitIntrinsicCall: I is a call instruction
3245 /// Op is the associated NodeType for I
3247 SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3248 SDValue Root = getRoot();
3250 DAG.getAtomic(Op, getCurDebugLoc(),
3251 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3253 getValue(I.getOperand(1)),
3254 getValue(I.getOperand(2)),
3257 DAG.setRoot(L.getValue(1));
3259 if (DisableScheduling)
3260 DAG.AssignOrdering(L.getNode(), SDNodeOrder);
3265 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3267 SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3268 SDValue Op1 = getValue(I.getOperand(1));
3269 SDValue Op2 = getValue(I.getOperand(2));
3271 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3272 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3274 setValue(&I, Result);
3276 if (DisableScheduling)
3277 DAG.AssignOrdering(Result.getNode(), SDNodeOrder);
3282 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3283 /// limited-precision mode.
3285 SelectionDAGBuilder::visitExp(CallInst &I) {
3287 DebugLoc dl = getCurDebugLoc();
3289 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3290 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3291 SDValue Op = getValue(I.getOperand(1));
3293 // Put the exponent in the right bit position for later addition to the
3296 // #define LOG2OFe 1.4426950f
3297 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3298 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3299 getF32Constant(DAG, 0x3fb8aa3b));
3300 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3302 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3303 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3304 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3306 if (DisableScheduling) {
3307 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3308 DAG.AssignOrdering(IntegerPartOfX.getNode(), SDNodeOrder);
3309 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3310 DAG.AssignOrdering(X.getNode(), SDNodeOrder);
3313 // IntegerPartOfX <<= 23;
3314 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3315 DAG.getConstant(23, TLI.getPointerTy()));
3317 if (DisableScheduling)
3318 DAG.AssignOrdering(IntegerPartOfX.getNode(), SDNodeOrder);
3320 if (LimitFloatPrecision <= 6) {
3321 // For floating-point precision of 6:
3323 // TwoToFractionalPartOfX =
3325 // (0.735607626f + 0.252464424f * x) * x;
3327 // error 0.0144103317, which is 6 bits
3328 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3329 getF32Constant(DAG, 0x3e814304));
3330 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3331 getF32Constant(DAG, 0x3f3c50c8));
3332 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3333 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3334 getF32Constant(DAG, 0x3f7f5e7e));
3335 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3337 // Add the exponent into the result in integer domain.
3338 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3339 TwoToFracPartOfX, IntegerPartOfX);
3341 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3343 if (DisableScheduling) {
3344 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3345 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3346 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3347 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3348 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3349 DAG.AssignOrdering(TwoToFracPartOfX.getNode(), SDNodeOrder);
3350 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3352 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3353 // For floating-point precision of 12:
3355 // TwoToFractionalPartOfX =
3358 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3360 // 0.000107046256 error, which is 13 to 14 bits
3361 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3362 getF32Constant(DAG, 0x3da235e3));
3363 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3364 getF32Constant(DAG, 0x3e65b8f3));
3365 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3366 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3367 getF32Constant(DAG, 0x3f324b07));
3368 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3369 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3370 getF32Constant(DAG, 0x3f7ff8fd));
3371 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3373 // Add the exponent into the result in integer domain.
3374 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3375 TwoToFracPartOfX, IntegerPartOfX);
3377 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3379 if (DisableScheduling) {
3380 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3381 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3382 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3383 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3384 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3385 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
3386 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
3387 DAG.AssignOrdering(TwoToFracPartOfX.getNode(), SDNodeOrder);
3388 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3390 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3391 // For floating-point precision of 18:
3393 // TwoToFractionalPartOfX =
3397 // (0.554906021e-1f +
3398 // (0.961591928e-2f +
3399 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3401 // error 2.47208000*10^(-7), which is better than 18 bits
3402 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3403 getF32Constant(DAG, 0x3924b03e));
3404 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3405 getF32Constant(DAG, 0x3ab24b87));
3406 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3407 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3408 getF32Constant(DAG, 0x3c1d8c17));
3409 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3410 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3411 getF32Constant(DAG, 0x3d634a1d));
3412 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3413 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3414 getF32Constant(DAG, 0x3e75fe14));
3415 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3416 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3417 getF32Constant(DAG, 0x3f317234));
3418 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3419 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3420 getF32Constant(DAG, 0x3f800000));
3421 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3424 // Add the exponent into the result in integer domain.
3425 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3426 TwoToFracPartOfX, IntegerPartOfX);
3428 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3430 if (DisableScheduling) {
3431 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3432 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3433 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3434 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3435 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3436 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
3437 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
3438 DAG.AssignOrdering(t9.getNode(), SDNodeOrder);
3439 DAG.AssignOrdering(t10.getNode(), SDNodeOrder);
3440 DAG.AssignOrdering(t11.getNode(), SDNodeOrder);
3441 DAG.AssignOrdering(t12.getNode(), SDNodeOrder);
3442 DAG.AssignOrdering(t13.getNode(), SDNodeOrder);
3443 DAG.AssignOrdering(t14.getNode(), SDNodeOrder);
3444 DAG.AssignOrdering(TwoToFracPartOfX.getNode(), SDNodeOrder);
3445 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3449 // No special expansion.
3450 result = DAG.getNode(ISD::FEXP, dl,
3451 getValue(I.getOperand(1)).getValueType(),
3452 getValue(I.getOperand(1)));
3453 if (DisableScheduling)
3454 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3457 setValue(&I, result);
3460 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3461 /// limited-precision mode.
3463 SelectionDAGBuilder::visitLog(CallInst &I) {
3465 DebugLoc dl = getCurDebugLoc();
3467 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3468 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3469 SDValue Op = getValue(I.getOperand(1));
3470 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3472 if (DisableScheduling)
3473 DAG.AssignOrdering(Op1.getNode(), SDNodeOrder);
3475 // Scale the exponent by log(2) [0.69314718f].
3476 SDValue Exp = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
3477 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3478 getF32Constant(DAG, 0x3f317218));
3480 if (DisableScheduling)
3481 DAG.AssignOrdering(LogOfExponent.getNode(), SDNodeOrder);
3483 // Get the significand and build it into a floating-point number with
3485 SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
3487 if (LimitFloatPrecision <= 6) {
3488 // For floating-point precision of 6:
3492 // (1.4034025f - 0.23903021f * x) * x;
3494 // error 0.0034276066, which is better than 8 bits
3495 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3496 getF32Constant(DAG, 0xbe74c456));
3497 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3498 getF32Constant(DAG, 0x3fb3a2b1));
3499 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3500 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3501 getF32Constant(DAG, 0x3f949a29));
3503 result = DAG.getNode(ISD::FADD, dl,
3504 MVT::f32, LogOfExponent, LogOfMantissa);
3506 if (DisableScheduling) {
3507 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3508 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3509 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3510 DAG.AssignOrdering(LogOfMantissa.getNode(), SDNodeOrder);
3511 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3513 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3514 // For floating-point precision of 12:
3520 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3522 // error 0.000061011436, which is 14 bits
3523 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3524 getF32Constant(DAG, 0xbd67b6d6));
3525 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3526 getF32Constant(DAG, 0x3ee4f4b8));
3527 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3528 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3529 getF32Constant(DAG, 0x3fbc278b));
3530 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3531 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3532 getF32Constant(DAG, 0x40348e95));
3533 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3534 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3535 getF32Constant(DAG, 0x3fdef31a));
3537 result = DAG.getNode(ISD::FADD, dl,
3538 MVT::f32, LogOfExponent, LogOfMantissa);
3540 if (DisableScheduling) {
3541 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3542 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3543 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3544 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3545 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3546 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3547 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3548 DAG.AssignOrdering(LogOfMantissa.getNode(), SDNodeOrder);
3549 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3551 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3552 // For floating-point precision of 18:
3560 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3562 // error 0.0000023660568, which is better than 18 bits
3563 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3564 getF32Constant(DAG, 0xbc91e5ac));
3565 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3566 getF32Constant(DAG, 0x3e4350aa));
3567 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3568 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3569 getF32Constant(DAG, 0x3f60d3e3));
3570 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3571 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3572 getF32Constant(DAG, 0x4011cdf0));
3573 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3574 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3575 getF32Constant(DAG, 0x406cfd1c));
3576 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3577 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3578 getF32Constant(DAG, 0x408797cb));
3579 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3580 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3581 getF32Constant(DAG, 0x4006dcab));
3583 result = DAG.getNode(ISD::FADD, dl,
3584 MVT::f32, LogOfExponent, LogOfMantissa);
3586 if (DisableScheduling) {
3587 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3588 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3589 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3590 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3591 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3592 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3593 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3594 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
3595 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
3596 DAG.AssignOrdering(t9.getNode(), SDNodeOrder);
3597 DAG.AssignOrdering(t10.getNode(), SDNodeOrder);
3598 DAG.AssignOrdering(LogOfMantissa.getNode(), SDNodeOrder);
3599 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3603 // No special expansion.
3604 result = DAG.getNode(ISD::FLOG, dl,
3605 getValue(I.getOperand(1)).getValueType(),
3606 getValue(I.getOperand(1)));
3608 if (DisableScheduling)
3609 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3612 setValue(&I, result);
3615 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3616 /// limited-precision mode.
3618 SelectionDAGBuilder::visitLog2(CallInst &I) {
3620 DebugLoc dl = getCurDebugLoc();
3622 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3623 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3624 SDValue Op = getValue(I.getOperand(1));
3625 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3627 if (DisableScheduling)
3628 DAG.AssignOrdering(Op1.getNode(), SDNodeOrder);
3630 // Get the exponent.
3631 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
3633 if (DisableScheduling)
3634 DAG.AssignOrdering(LogOfExponent.getNode(), SDNodeOrder);
3636 // Get the significand and build it into a floating-point number with
3638 SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
3640 // Different possible minimax approximations of significand in
3641 // floating-point for various degrees of accuracy over [1,2].
3642 if (LimitFloatPrecision <= 6) {
3643 // For floating-point precision of 6:
3645 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3647 // error 0.0049451742, which is more than 7 bits
3648 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3649 getF32Constant(DAG, 0xbeb08fe0));
3650 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3651 getF32Constant(DAG, 0x40019463));
3652 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3653 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3654 getF32Constant(DAG, 0x3fd6633d));
3656 result = DAG.getNode(ISD::FADD, dl,
3657 MVT::f32, LogOfExponent, Log2ofMantissa);
3659 if (DisableScheduling) {
3660 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3661 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3662 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3663 DAG.AssignOrdering(Log2ofMantissa.getNode(), SDNodeOrder);
3664 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3666 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3667 // For floating-point precision of 12:
3673 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3675 // error 0.0000876136000, which is better than 13 bits
3676 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3677 getF32Constant(DAG, 0xbda7262e));
3678 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3679 getF32Constant(DAG, 0x3f25280b));
3680 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3681 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3682 getF32Constant(DAG, 0x4007b923));
3683 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3684 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3685 getF32Constant(DAG, 0x40823e2f));
3686 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3687 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3688 getF32Constant(DAG, 0x4020d29c));
3690 result = DAG.getNode(ISD::FADD, dl,
3691 MVT::f32, LogOfExponent, Log2ofMantissa);
3693 if (DisableScheduling) {
3694 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3695 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3696 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3697 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3698 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3699 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3700 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3701 DAG.AssignOrdering(Log2ofMantissa.getNode(), SDNodeOrder);
3702 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3704 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3705 // For floating-point precision of 18:
3714 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3716 // error 0.0000018516, which is better than 18 bits
3717 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3718 getF32Constant(DAG, 0xbcd2769e));
3719 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3720 getF32Constant(DAG, 0x3e8ce0b9));
3721 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3722 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3723 getF32Constant(DAG, 0x3fa22ae7));
3724 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3725 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3726 getF32Constant(DAG, 0x40525723));
3727 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3728 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3729 getF32Constant(DAG, 0x40aaf200));
3730 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3731 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3732 getF32Constant(DAG, 0x40c39dad));
3733 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3734 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3735 getF32Constant(DAG, 0x4042902c));
3737 result = DAG.getNode(ISD::FADD, dl,
3738 MVT::f32, LogOfExponent, Log2ofMantissa);
3740 if (DisableScheduling) {
3741 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3742 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3743 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3744 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3745 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3746 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3747 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3748 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
3749 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
3750 DAG.AssignOrdering(t9.getNode(), SDNodeOrder);
3751 DAG.AssignOrdering(t10.getNode(), SDNodeOrder);
3752 DAG.AssignOrdering(Log2ofMantissa.getNode(), SDNodeOrder);
3753 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3757 // No special expansion.
3758 result = DAG.getNode(ISD::FLOG2, dl,
3759 getValue(I.getOperand(1)).getValueType(),
3760 getValue(I.getOperand(1)));
3762 if (DisableScheduling)
3763 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3766 setValue(&I, result);
3769 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3770 /// limited-precision mode.
3772 SelectionDAGBuilder::visitLog10(CallInst &I) {
3774 DebugLoc dl = getCurDebugLoc();
3776 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3777 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3778 SDValue Op = getValue(I.getOperand(1));
3779 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3781 if (DisableScheduling)
3782 DAG.AssignOrdering(Op1.getNode(), SDNodeOrder);
3784 // Scale the exponent by log10(2) [0.30102999f].
3785 SDValue Exp = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
3786 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3787 getF32Constant(DAG, 0x3e9a209a));
3789 if (DisableScheduling)
3790 DAG.AssignOrdering(LogOfExponent.getNode(), SDNodeOrder);
3792 // Get the significand and build it into a floating-point number with
3794 SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
3796 if (LimitFloatPrecision <= 6) {
3797 // For floating-point precision of 6:
3799 // Log10ofMantissa =
3801 // (0.60948995f - 0.10380950f * x) * x;
3803 // error 0.0014886165, which is 6 bits
3804 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3805 getF32Constant(DAG, 0xbdd49a13));
3806 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3807 getF32Constant(DAG, 0x3f1c0789));
3808 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3809 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3810 getF32Constant(DAG, 0x3f011300));
3812 result = DAG.getNode(ISD::FADD, dl,
3813 MVT::f32, LogOfExponent, Log10ofMantissa);
3815 if (DisableScheduling) {
3816 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3817 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3818 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3819 DAG.AssignOrdering(Log10ofMantissa.getNode(), SDNodeOrder);
3820 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3822 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3823 // For floating-point precision of 12:
3825 // Log10ofMantissa =
3828 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3830 // error 0.00019228036, which is better than 12 bits
3831 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3832 getF32Constant(DAG, 0x3d431f31));
3833 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3834 getF32Constant(DAG, 0x3ea21fb2));
3835 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3836 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3837 getF32Constant(DAG, 0x3f6ae232));
3838 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3839 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3840 getF32Constant(DAG, 0x3f25f7c3));
3842 result = DAG.getNode(ISD::FADD, dl,
3843 MVT::f32, LogOfExponent, Log10ofMantissa);
3845 if (DisableScheduling) {
3846 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3847 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3848 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3849 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3850 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3851 DAG.AssignOrdering(Log10ofMantissa.getNode(), SDNodeOrder);
3852 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3854 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3855 // For floating-point precision of 18:
3857 // Log10ofMantissa =
3862 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3864 // error 0.0000037995730, which is better than 18 bits
3865 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3866 getF32Constant(DAG, 0x3c5d51ce));
3867 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3868 getF32Constant(DAG, 0x3e00685a));
3869 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3870 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3871 getF32Constant(DAG, 0x3efb6798));
3872 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3873 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3874 getF32Constant(DAG, 0x3f88d192));
3875 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3876 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3877 getF32Constant(DAG, 0x3fc4316c));
3878 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3879 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3880 getF32Constant(DAG, 0x3f57ce70));
3882 result = DAG.getNode(ISD::FADD, dl,
3883 MVT::f32, LogOfExponent, Log10ofMantissa);
3885 if (DisableScheduling) {
3886 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
3887 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3888 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3889 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3890 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3891 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3892 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3893 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
3894 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
3895 DAG.AssignOrdering(Log10ofMantissa.getNode(), SDNodeOrder);
3896 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3900 // No special expansion.
3901 result = DAG.getNode(ISD::FLOG10, dl,
3902 getValue(I.getOperand(1)).getValueType(),
3903 getValue(I.getOperand(1)));
3905 if (DisableScheduling)
3906 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3909 setValue(&I, result);
3912 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3913 /// limited-precision mode.
3915 SelectionDAGBuilder::visitExp2(CallInst &I) {
3917 DebugLoc dl = getCurDebugLoc();
3919 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3920 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3921 SDValue Op = getValue(I.getOperand(1));
3923 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3925 if (DisableScheduling)
3926 DAG.AssignOrdering(IntegerPartOfX.getNode(), SDNodeOrder);
3928 // FractionalPartOfX = x - (float)IntegerPartOfX;
3929 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3930 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3932 // IntegerPartOfX <<= 23;
3933 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3934 DAG.getConstant(23, TLI.getPointerTy()));
3936 if (DisableScheduling) {
3937 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
3938 DAG.AssignOrdering(X.getNode(), SDNodeOrder);
3939 DAG.AssignOrdering(IntegerPartOfX.getNode(), SDNodeOrder);
3942 if (LimitFloatPrecision <= 6) {
3943 // For floating-point precision of 6:
3945 // TwoToFractionalPartOfX =
3947 // (0.735607626f + 0.252464424f * x) * x;
3949 // error 0.0144103317, which is 6 bits
3950 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3951 getF32Constant(DAG, 0x3e814304));
3952 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3953 getF32Constant(DAG, 0x3f3c50c8));
3954 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3955 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3956 getF32Constant(DAG, 0x3f7f5e7e));
3957 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3958 SDValue TwoToFractionalPartOfX =
3959 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3961 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3962 MVT::f32, TwoToFractionalPartOfX);
3964 if (DisableScheduling) {
3965 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
3966 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
3967 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
3968 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
3969 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
3970 DAG.AssignOrdering(TwoToFractionalPartOfX.getNode(), SDNodeOrder);
3971 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
3973 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3974 // For floating-point precision of 12:
3976 // TwoToFractionalPartOfX =
3979 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3981 // error 0.000107046256, which is 13 to 14 bits
3982 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3983 getF32Constant(DAG, 0x3da235e3));
3984 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3985 getF32Constant(DAG, 0x3e65b8f3));
3986 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3987 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3988 getF32Constant(DAG, 0x3f324b07));
3989 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3990 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3991 getF32Constant(DAG, 0x3f7ff8fd));
3992 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3993 SDValue TwoToFractionalPartOfX =
3994 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3996 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3997 MVT::f32, TwoToFractionalPartOfX);
3999 if (DisableScheduling) {
4000 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
4001 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
4002 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
4003 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
4004 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
4005 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
4006 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
4007 DAG.AssignOrdering(TwoToFractionalPartOfX.getNode(), SDNodeOrder);
4008 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4010 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4011 // For floating-point precision of 18:
4013 // TwoToFractionalPartOfX =
4017 // (0.554906021e-1f +
4018 // (0.961591928e-2f +
4019 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4020 // error 2.47208000*10^(-7), which is better than 18 bits
4021 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4022 getF32Constant(DAG, 0x3924b03e));
4023 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4024 getF32Constant(DAG, 0x3ab24b87));
4025 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4026 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4027 getF32Constant(DAG, 0x3c1d8c17));
4028 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4029 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4030 getF32Constant(DAG, 0x3d634a1d));
4031 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4032 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4033 getF32Constant(DAG, 0x3e75fe14));
4034 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4035 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4036 getF32Constant(DAG, 0x3f317234));
4037 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4038 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4039 getF32Constant(DAG, 0x3f800000));
4040 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
4041 SDValue TwoToFractionalPartOfX =
4042 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4044 result = DAG.getNode(ISD::BIT_CONVERT, dl,
4045 MVT::f32, TwoToFractionalPartOfX);
4047 if (DisableScheduling) {
4048 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
4049 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
4050 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
4051 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
4052 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
4053 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
4054 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
4055 DAG.AssignOrdering(t9.getNode(), SDNodeOrder);
4056 DAG.AssignOrdering(t10.getNode(), SDNodeOrder);
4057 DAG.AssignOrdering(t11.getNode(), SDNodeOrder);
4058 DAG.AssignOrdering(t12.getNode(), SDNodeOrder);
4059 DAG.AssignOrdering(t13.getNode(), SDNodeOrder);
4060 DAG.AssignOrdering(t14.getNode(), SDNodeOrder);
4061 DAG.AssignOrdering(TwoToFractionalPartOfX.getNode(), SDNodeOrder);
4062 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4066 // No special expansion.
4067 result = DAG.getNode(ISD::FEXP2, dl,
4068 getValue(I.getOperand(1)).getValueType(),
4069 getValue(I.getOperand(1)));
4071 if (DisableScheduling)
4072 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4075 setValue(&I, result);
4078 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4079 /// limited-precision mode with x == 10.0f.
4081 SelectionDAGBuilder::visitPow(CallInst &I) {
4083 Value *Val = I.getOperand(1);
4084 DebugLoc dl = getCurDebugLoc();
4085 bool IsExp10 = false;
4087 if (getValue(Val).getValueType() == MVT::f32 &&
4088 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
4089 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4090 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4091 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4093 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4098 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4099 SDValue Op = getValue(I.getOperand(2));
4101 // Put the exponent in the right bit position for later addition to the
4104 // #define LOG2OF10 3.3219281f
4105 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4106 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4107 getF32Constant(DAG, 0x40549a78));
4108 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4110 // FractionalPartOfX = x - (float)IntegerPartOfX;
4111 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4112 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4114 if (DisableScheduling) {
4115 DAG.AssignOrdering(t0.getNode(), SDNodeOrder);
4116 DAG.AssignOrdering(t1.getNode(), SDNodeOrder);
4117 DAG.AssignOrdering(IntegerPartOfX.getNode(), SDNodeOrder);
4118 DAG.AssignOrdering(X.getNode(), SDNodeOrder);
4121 // IntegerPartOfX <<= 23;
4122 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4123 DAG.getConstant(23, TLI.getPointerTy()));
4125 if (DisableScheduling)
4126 DAG.AssignOrdering(IntegerPartOfX.getNode(), SDNodeOrder);
4128 if (LimitFloatPrecision <= 6) {
4129 // For floating-point precision of 6:
4131 // twoToFractionalPartOfX =
4133 // (0.735607626f + 0.252464424f * x) * x;
4135 // error 0.0144103317, which is 6 bits
4136 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4137 getF32Constant(DAG, 0x3e814304));
4138 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4139 getF32Constant(DAG, 0x3f3c50c8));
4140 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4141 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4142 getF32Constant(DAG, 0x3f7f5e7e));
4143 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
4144 SDValue TwoToFractionalPartOfX =
4145 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4147 result = DAG.getNode(ISD::BIT_CONVERT, dl,
4148 MVT::f32, TwoToFractionalPartOfX);
4150 if (DisableScheduling) {
4151 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
4152 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
4153 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
4154 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
4155 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
4156 DAG.AssignOrdering(TwoToFractionalPartOfX.getNode(), SDNodeOrder);
4157 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4159 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4160 // For floating-point precision of 12:
4162 // TwoToFractionalPartOfX =
4165 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4167 // error 0.000107046256, which is 13 to 14 bits
4168 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4169 getF32Constant(DAG, 0x3da235e3));
4170 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4171 getF32Constant(DAG, 0x3e65b8f3));
4172 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4173 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4174 getF32Constant(DAG, 0x3f324b07));
4175 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4176 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4177 getF32Constant(DAG, 0x3f7ff8fd));
4178 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
4179 SDValue TwoToFractionalPartOfX =
4180 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4182 result = DAG.getNode(ISD::BIT_CONVERT, dl,
4183 MVT::f32, TwoToFractionalPartOfX);
4185 if (DisableScheduling) {
4186 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
4187 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
4188 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
4189 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
4190 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
4191 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
4192 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
4193 DAG.AssignOrdering(TwoToFractionalPartOfX.getNode(), SDNodeOrder);
4194 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4196 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4197 // For floating-point precision of 18:
4199 // TwoToFractionalPartOfX =
4203 // (0.554906021e-1f +
4204 // (0.961591928e-2f +
4205 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4206 // error 2.47208000*10^(-7), which is better than 18 bits
4207 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4208 getF32Constant(DAG, 0x3924b03e));
4209 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4210 getF32Constant(DAG, 0x3ab24b87));
4211 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4212 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4213 getF32Constant(DAG, 0x3c1d8c17));
4214 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4215 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4216 getF32Constant(DAG, 0x3d634a1d));
4217 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4218 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4219 getF32Constant(DAG, 0x3e75fe14));
4220 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4221 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4222 getF32Constant(DAG, 0x3f317234));
4223 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4224 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4225 getF32Constant(DAG, 0x3f800000));
4226 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
4227 SDValue TwoToFractionalPartOfX =
4228 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4230 result = DAG.getNode(ISD::BIT_CONVERT, dl,
4231 MVT::f32, TwoToFractionalPartOfX);
4233 if (DisableScheduling) {
4234 DAG.AssignOrdering(t2.getNode(), SDNodeOrder);
4235 DAG.AssignOrdering(t3.getNode(), SDNodeOrder);
4236 DAG.AssignOrdering(t4.getNode(), SDNodeOrder);
4237 DAG.AssignOrdering(t5.getNode(), SDNodeOrder);
4238 DAG.AssignOrdering(t6.getNode(), SDNodeOrder);
4239 DAG.AssignOrdering(t7.getNode(), SDNodeOrder);
4240 DAG.AssignOrdering(t8.getNode(), SDNodeOrder);
4241 DAG.AssignOrdering(t9.getNode(), SDNodeOrder);
4242 DAG.AssignOrdering(t10.getNode(), SDNodeOrder);
4243 DAG.AssignOrdering(t11.getNode(), SDNodeOrder);
4244 DAG.AssignOrdering(t12.getNode(), SDNodeOrder);
4245 DAG.AssignOrdering(t13.getNode(), SDNodeOrder);
4246 DAG.AssignOrdering(t14.getNode(), SDNodeOrder);
4247 DAG.AssignOrdering(TwoToFractionalPartOfX.getNode(), SDNodeOrder);
4248 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4252 // No special expansion.
4253 result = DAG.getNode(ISD::FPOW, dl,
4254 getValue(I.getOperand(1)).getValueType(),
4255 getValue(I.getOperand(1)),
4256 getValue(I.getOperand(2)));
4258 if (DisableScheduling)
4259 DAG.AssignOrdering(result.getNode(), SDNodeOrder);
4262 setValue(&I, result);
4265 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4266 /// we want to emit this as a call to a named external function, return the name
4267 /// otherwise lower it and return null.
4269 SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
4270 DebugLoc dl = getCurDebugLoc();
4273 switch (Intrinsic) {
4275 // By default, turn this into a target intrinsic node.
4276 visitTargetIntrinsic(I, Intrinsic);
4278 case Intrinsic::vastart: visitVAStart(I); return 0;
4279 case Intrinsic::vaend: visitVAEnd(I); return 0;
4280 case Intrinsic::vacopy: visitVACopy(I); return 0;
4281 case Intrinsic::returnaddress:
4282 Res = DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4283 getValue(I.getOperand(1)));
4285 if (DisableScheduling)
4286 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4288 case Intrinsic::frameaddress:
4289 Res = DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4290 getValue(I.getOperand(1)));
4292 if (DisableScheduling)
4293 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4295 case Intrinsic::setjmp:
4296 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4297 case Intrinsic::longjmp:
4298 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4299 case Intrinsic::memcpy: {
4300 SDValue Op1 = getValue(I.getOperand(1));
4301 SDValue Op2 = getValue(I.getOperand(2));
4302 SDValue Op3 = getValue(I.getOperand(3));
4303 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
4304 Res = DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
4305 I.getOperand(1), 0, I.getOperand(2), 0);
4307 if (DisableScheduling)
4308 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4311 case Intrinsic::memset: {
4312 SDValue Op1 = getValue(I.getOperand(1));
4313 SDValue Op2 = getValue(I.getOperand(2));
4314 SDValue Op3 = getValue(I.getOperand(3));
4315 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
4316 Res = DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
4317 I.getOperand(1), 0);
4319 if (DisableScheduling)
4320 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4323 case Intrinsic::memmove: {
4324 SDValue Op1 = getValue(I.getOperand(1));
4325 SDValue Op2 = getValue(I.getOperand(2));
4326 SDValue Op3 = getValue(I.getOperand(3));
4327 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
4329 // If the source and destination are known to not be aliases, we can
4330 // lower memmove as memcpy.
4331 uint64_t Size = -1ULL;
4332 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4333 Size = C->getZExtValue();
4334 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4335 AliasAnalysis::NoAlias) {
4336 Res = DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
4337 I.getOperand(1), 0, I.getOperand(2), 0);
4339 if (DisableScheduling)
4340 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4344 Res = DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
4345 I.getOperand(1), 0, I.getOperand(2), 0);
4347 if (DisableScheduling)
4348 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4351 case Intrinsic::dbg_stoppoint:
4352 case Intrinsic::dbg_region_start:
4353 case Intrinsic::dbg_region_end:
4354 case Intrinsic::dbg_func_start:
4355 // FIXME - Remove this instructions once the dust settles.
4357 case Intrinsic::dbg_declare: {
4358 if (OptLevel != CodeGenOpt::None)
4359 // FIXME: Variable debug info is not supported here.
4361 DwarfWriter *DW = DAG.getDwarfWriter();
4364 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4365 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
4368 MDNode *Variable = DI.getVariable();
4369 Value *Address = DI.getAddress();
4370 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4371 Address = BCI->getOperand(0);
4372 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4373 // Don't handle byval struct arguments or VLAs, for example.
4376 DenseMap<const AllocaInst*, int>::iterator SI =
4377 FuncInfo.StaticAllocaMap.find(AI);
4378 if (SI == FuncInfo.StaticAllocaMap.end())
4380 int FI = SI->second;
4382 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4384 MetadataContext &TheMetadata =
4385 DI.getParent()->getContext().getMetadata();
4386 unsigned MDDbgKind = TheMetadata.getMDKindID("dbg");
4387 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, &DI))
4388 MMI->setVariableDbgInfo(Variable, FI, Dbg);
4392 case Intrinsic::eh_exception: {
4393 // Insert the EXCEPTIONADDR instruction.
4394 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
4395 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4397 Ops[0] = DAG.getRoot();
4398 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4400 DAG.setRoot(Op.getValue(1));
4401 if (DisableScheduling)
4402 DAG.AssignOrdering(Op.getNode(), SDNodeOrder);
4406 case Intrinsic::eh_selector: {
4407 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4409 if (CurMBB->isLandingPad())
4410 AddCatchInfo(I, MMI, CurMBB);
4413 FuncInfo.CatchInfoLost.insert(&I);
4415 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4416 unsigned Reg = TLI.getExceptionSelectorRegister();
4417 if (Reg) CurMBB->addLiveIn(Reg);
4420 // Insert the EHSELECTION instruction.
4421 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4423 Ops[0] = getValue(I.getOperand(1));
4425 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4427 DAG.setRoot(Op.getValue(1));
4429 Res = DAG.getSExtOrTrunc(Op, dl, MVT::i32);
4431 if (DisableScheduling) {
4432 DAG.AssignOrdering(Op.getNode(), SDNodeOrder);
4433 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4438 case Intrinsic::eh_typeid_for: {
4439 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4442 // Find the type id for the given typeinfo.
4443 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4444 unsigned TypeID = MMI->getTypeIDFor(GV);
4445 Res = DAG.getConstant(TypeID, MVT::i32);
4447 // Return something different to eh_selector.
4448 Res = DAG.getConstant(1, MVT::i32);
4452 if (DisableScheduling)
4453 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4457 case Intrinsic::eh_return_i32:
4458 case Intrinsic::eh_return_i64:
4459 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4460 MMI->setCallsEHReturn(true);
4461 Res = DAG.getNode(ISD::EH_RETURN, dl,
4464 getValue(I.getOperand(1)),
4465 getValue(I.getOperand(2)));
4467 if (DisableScheduling)
4468 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4470 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4474 case Intrinsic::eh_unwind_init:
4475 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4476 MMI->setCallsUnwindInit(true);
4479 case Intrinsic::eh_dwarf_cfa: {
4480 EVT VT = getValue(I.getOperand(1)).getValueType();
4481 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
4482 TLI.getPointerTy());
4483 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4485 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4486 TLI.getPointerTy()),
4488 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4490 DAG.getConstant(0, TLI.getPointerTy()));
4491 Res = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4494 if (DisableScheduling) {
4495 DAG.AssignOrdering(CfaArg.getNode(), SDNodeOrder);
4496 DAG.AssignOrdering(Offset.getNode(), SDNodeOrder);
4497 DAG.AssignOrdering(FA.getNode(), SDNodeOrder);
4498 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4502 case Intrinsic::convertff:
4503 case Intrinsic::convertfsi:
4504 case Intrinsic::convertfui:
4505 case Intrinsic::convertsif:
4506 case Intrinsic::convertuif:
4507 case Intrinsic::convertss:
4508 case Intrinsic::convertsu:
4509 case Intrinsic::convertus:
4510 case Intrinsic::convertuu: {
4511 ISD::CvtCode Code = ISD::CVT_INVALID;
4512 switch (Intrinsic) {
4513 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4514 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4515 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4516 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4517 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4518 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4519 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4520 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4521 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4523 EVT DestVT = TLI.getValueType(I.getType());
4524 Value *Op1 = I.getOperand(1);
4525 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4526 DAG.getValueType(DestVT),
4527 DAG.getValueType(getValue(Op1).getValueType()),
4528 getValue(I.getOperand(2)),
4529 getValue(I.getOperand(3)),
4532 if (DisableScheduling)
4533 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4536 case Intrinsic::sqrt:
4537 Res = DAG.getNode(ISD::FSQRT, dl,
4538 getValue(I.getOperand(1)).getValueType(),
4539 getValue(I.getOperand(1)));
4541 if (DisableScheduling)
4542 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4544 case Intrinsic::powi:
4545 Res = DAG.getNode(ISD::FPOWI, dl,
4546 getValue(I.getOperand(1)).getValueType(),
4547 getValue(I.getOperand(1)),
4548 getValue(I.getOperand(2)));
4550 if (DisableScheduling)
4551 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4553 case Intrinsic::sin:
4554 Res = DAG.getNode(ISD::FSIN, dl,
4555 getValue(I.getOperand(1)).getValueType(),
4556 getValue(I.getOperand(1)));
4558 if (DisableScheduling)
4559 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4561 case Intrinsic::cos:
4562 Res = DAG.getNode(ISD::FCOS, dl,
4563 getValue(I.getOperand(1)).getValueType(),
4564 getValue(I.getOperand(1)));
4566 if (DisableScheduling)
4567 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4569 case Intrinsic::log:
4572 case Intrinsic::log2:
4575 case Intrinsic::log10:
4578 case Intrinsic::exp:
4581 case Intrinsic::exp2:
4584 case Intrinsic::pow:
4587 case Intrinsic::pcmarker: {
4588 SDValue Tmp = getValue(I.getOperand(1));
4589 Res = DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp);
4591 if (DisableScheduling)
4592 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4595 case Intrinsic::readcyclecounter: {
4596 SDValue Op = getRoot();
4597 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4598 DAG.getVTList(MVT::i64, MVT::Other),
4601 DAG.setRoot(Res.getValue(1));
4602 if (DisableScheduling)
4603 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4606 case Intrinsic::bswap:
4607 Res = DAG.getNode(ISD::BSWAP, dl,
4608 getValue(I.getOperand(1)).getValueType(),
4609 getValue(I.getOperand(1)));
4611 if (DisableScheduling)
4612 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4614 case Intrinsic::cttz: {
4615 SDValue Arg = getValue(I.getOperand(1));
4616 EVT Ty = Arg.getValueType();
4617 Res = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4619 if (DisableScheduling)
4620 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4623 case Intrinsic::ctlz: {
4624 SDValue Arg = getValue(I.getOperand(1));
4625 EVT Ty = Arg.getValueType();
4626 Res = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4628 if (DisableScheduling)
4629 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4632 case Intrinsic::ctpop: {
4633 SDValue Arg = getValue(I.getOperand(1));
4634 EVT Ty = Arg.getValueType();
4635 Res = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4637 if (DisableScheduling)
4638 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4641 case Intrinsic::stacksave: {
4642 SDValue Op = getRoot();
4643 Res = DAG.getNode(ISD::STACKSAVE, dl,
4644 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4646 DAG.setRoot(Res.getValue(1));
4647 if (DisableScheduling)
4648 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4651 case Intrinsic::stackrestore: {
4652 Res = getValue(I.getOperand(1));
4653 Res = DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res);
4655 if (DisableScheduling)
4656 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4659 case Intrinsic::stackprotector: {
4660 // Emit code into the DAG to store the stack guard onto the stack.
4661 MachineFunction &MF = DAG.getMachineFunction();
4662 MachineFrameInfo *MFI = MF.getFrameInfo();
4663 EVT PtrTy = TLI.getPointerTy();
4665 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4666 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4668 int FI = FuncInfo.StaticAllocaMap[Slot];
4669 MFI->setStackProtectorIndex(FI);
4671 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4673 // Store the stack protector onto the stack.
4674 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4675 PseudoSourceValue::getFixedStack(FI),
4679 if (DisableScheduling)
4680 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4683 case Intrinsic::objectsize: {
4684 // If we don't know by now, we're never going to know.
4685 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4687 assert(CI && "Non-constant type in __builtin_object_size?");
4689 SDValue Arg = getValue(I.getOperand(0));
4690 EVT Ty = Arg.getValueType();
4692 if (CI->getZExtValue() == 0)
4693 Res = DAG.getConstant(-1ULL, Ty);
4695 Res = DAG.getConstant(0, Ty);
4698 if (DisableScheduling)
4699 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4702 case Intrinsic::var_annotation:
4703 // Discard annotate attributes
4706 case Intrinsic::init_trampoline: {
4707 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4711 Ops[1] = getValue(I.getOperand(1));
4712 Ops[2] = getValue(I.getOperand(2));
4713 Ops[3] = getValue(I.getOperand(3));
4714 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4715 Ops[5] = DAG.getSrcValue(F);
4717 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4718 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4722 DAG.setRoot(Res.getValue(1));
4723 if (DisableScheduling)
4724 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4727 case Intrinsic::gcroot:
4729 Value *Alloca = I.getOperand(1);
4730 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4732 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4733 GFI->addStackRoot(FI->getIndex(), TypeMap);
4736 case Intrinsic::gcread:
4737 case Intrinsic::gcwrite:
4738 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4740 case Intrinsic::flt_rounds:
4741 Res = DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32);
4743 if (DisableScheduling)
4744 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4746 case Intrinsic::trap:
4747 Res = DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot());
4749 if (DisableScheduling)
4750 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4752 case Intrinsic::uadd_with_overflow:
4753 return implVisitAluOverflow(I, ISD::UADDO);
4754 case Intrinsic::sadd_with_overflow:
4755 return implVisitAluOverflow(I, ISD::SADDO);
4756 case Intrinsic::usub_with_overflow:
4757 return implVisitAluOverflow(I, ISD::USUBO);
4758 case Intrinsic::ssub_with_overflow:
4759 return implVisitAluOverflow(I, ISD::SSUBO);
4760 case Intrinsic::umul_with_overflow:
4761 return implVisitAluOverflow(I, ISD::UMULO);
4762 case Intrinsic::smul_with_overflow:
4763 return implVisitAluOverflow(I, ISD::SMULO);
4765 case Intrinsic::prefetch: {
4768 Ops[1] = getValue(I.getOperand(1));
4769 Ops[2] = getValue(I.getOperand(2));
4770 Ops[3] = getValue(I.getOperand(3));
4771 Res = DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4);
4773 if (DisableScheduling)
4774 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4778 case Intrinsic::memory_barrier: {
4781 for (int x = 1; x < 6; ++x)
4782 Ops[x] = getValue(I.getOperand(x));
4784 Res = DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6);
4786 if (DisableScheduling)
4787 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4790 case Intrinsic::atomic_cmp_swap: {
4791 SDValue Root = getRoot();
4793 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4794 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4796 getValue(I.getOperand(1)),
4797 getValue(I.getOperand(2)),
4798 getValue(I.getOperand(3)),
4801 DAG.setRoot(L.getValue(1));
4802 if (DisableScheduling)
4803 DAG.AssignOrdering(L.getNode(), SDNodeOrder);
4806 case Intrinsic::atomic_load_add:
4807 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4808 case Intrinsic::atomic_load_sub:
4809 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4810 case Intrinsic::atomic_load_or:
4811 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4812 case Intrinsic::atomic_load_xor:
4813 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4814 case Intrinsic::atomic_load_and:
4815 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4816 case Intrinsic::atomic_load_nand:
4817 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4818 case Intrinsic::atomic_load_max:
4819 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4820 case Intrinsic::atomic_load_min:
4821 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4822 case Intrinsic::atomic_load_umin:
4823 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4824 case Intrinsic::atomic_load_umax:
4825 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4826 case Intrinsic::atomic_swap:
4827 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4829 case Intrinsic::invariant_start:
4830 case Intrinsic::lifetime_start:
4831 // Discard region information.
4832 Res = DAG.getUNDEF(TLI.getPointerTy());
4834 if (DisableScheduling)
4835 DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
4837 case Intrinsic::invariant_end:
4838 case Intrinsic::lifetime_end:
4839 // Discard region information.
4844 /// Test if the given instruction is in a position to be optimized
4845 /// with a tail-call. This roughly means that it's in a block with
4846 /// a return and there's nothing that needs to be scheduled
4847 /// between it and the return.
4849 /// This function only tests target-independent requirements.
4850 /// For target-dependent requirements, a target should override
4851 /// TargetLowering::IsEligibleForTailCallOptimization.
4854 isInTailCallPosition(const Instruction *I, Attributes CalleeRetAttr,
4855 const TargetLowering &TLI) {
4856 const BasicBlock *ExitBB = I->getParent();
4857 const TerminatorInst *Term = ExitBB->getTerminator();
4858 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4859 const Function *F = ExitBB->getParent();
4861 // The block must end in a return statement or an unreachable.
4862 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4864 // If I will have a chain, make sure no other instruction that will have a
4865 // chain interposes between I and the return.
4866 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4867 !I->isSafeToSpeculativelyExecute())
4868 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4872 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4873 !BBI->isSafeToSpeculativelyExecute())
4877 // If the block ends with a void return or unreachable, it doesn't matter
4878 // what the call's return type is.
4879 if (!Ret || Ret->getNumOperands() == 0) return true;
4881 // If the return value is undef, it doesn't matter what the call's
4883 if (isa<UndefValue>(Ret->getOperand(0))) return true;
4885 // Conservatively require the attributes of the call to match those of
4886 // the return. Ignore noalias because it doesn't affect the call sequence.
4887 unsigned CallerRetAttr = F->getAttributes().getRetAttributes();
4888 if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias)
4891 // Otherwise, make sure the unmodified return value of I is the return value.
4892 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4893 U = dyn_cast<Instruction>(U->getOperand(0))) {
4896 if (!U->hasOneUse())
4900 // Check for a truly no-op truncate.
4901 if (isa<TruncInst>(U) &&
4902 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4904 // Check for a truly no-op bitcast.
4905 if (isa<BitCastInst>(U) &&
4906 (U->getOperand(0)->getType() == U->getType() ||
4907 (isa<PointerType>(U->getOperand(0)->getType()) &&
4908 isa<PointerType>(U->getType()))))
4910 // Otherwise it's not a true no-op.
4917 void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
4919 MachineBasicBlock *LandingPad) {
4920 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4921 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4922 const Type *RetTy = FTy->getReturnType();
4923 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4924 unsigned BeginLabel = 0, EndLabel = 0;
4926 TargetLowering::ArgListTy Args;
4927 TargetLowering::ArgListEntry Entry;
4928 Args.reserve(CS.arg_size());
4930 // Check whether the function can return without sret-demotion.
4931 SmallVector<EVT, 4> OutVTs;
4932 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4933 SmallVector<uint64_t, 4> Offsets;
4934 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4935 OutVTs, OutsFlags, TLI, &Offsets);
4937 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4938 FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4940 SDValue DemoteStackSlot;
4942 if (!CanLowerReturn) {
4943 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4944 FTy->getReturnType());
4945 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4946 FTy->getReturnType());
4947 MachineFunction &MF = DAG.getMachineFunction();
4948 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4949 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4951 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4952 Entry.Node = DemoteStackSlot;
4953 Entry.Ty = StackSlotPtrType;
4954 Entry.isSExt = false;
4955 Entry.isZExt = false;
4956 Entry.isInReg = false;
4957 Entry.isSRet = true;
4958 Entry.isNest = false;
4959 Entry.isByVal = false;
4960 Entry.Alignment = Align;
4961 Args.push_back(Entry);
4962 RetTy = Type::getVoidTy(FTy->getContext());
4965 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4967 SDValue ArgNode = getValue(*i);
4968 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4970 unsigned attrInd = i - CS.arg_begin() + 1;
4971 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4972 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4973 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4974 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4975 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4976 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4977 Entry.Alignment = CS.getParamAlignment(attrInd);
4978 Args.push_back(Entry);
4981 if (LandingPad && MMI) {
4982 // Insert a label before the invoke call to mark the try range. This can be
4983 // used to detect deletion of the invoke via the MachineModuleInfo.
4984 BeginLabel = MMI->NextLabelID();
4986 // Both PendingLoads and PendingExports must be flushed here;
4987 // this call might not return.
4989 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4990 getControlRoot(), BeginLabel));
4993 // Check if target-independent constraints permit a tail call here.
4994 // Target-dependent constraints are checked within TLI.LowerCallTo.
4996 !isInTailCallPosition(CS.getInstruction(),
4997 CS.getAttributes().getRetAttributes(),
5001 std::pair<SDValue,SDValue> Result =
5002 TLI.LowerCallTo(getRoot(), RetTy,
5003 CS.paramHasAttr(0, Attribute::SExt),
5004 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5005 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5006 CS.getCallingConv(),
5008 !CS.getInstruction()->use_empty(),
5009 Callee, Args, DAG, getCurDebugLoc(), SDNodeOrder);
5010 assert((isTailCall || Result.second.getNode()) &&
5011 "Non-null chain expected with non-tail call!");
5012 assert((Result.second.getNode() || !Result.first.getNode()) &&
5013 "Null value expected with tail call!");
5014 if (Result.first.getNode()) {
5015 setValue(CS.getInstruction(), Result.first);
5016 if (DisableScheduling)
5017 DAG.AssignOrdering(Result.first.getNode(), SDNodeOrder);
5018 } else if (!CanLowerReturn && Result.second.getNode()) {
5019 // The instruction result is the result of loading from the
5020 // hidden sret parameter.
5021 SmallVector<EVT, 1> PVTs;
5022 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5024 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5025 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5026 EVT PtrVT = PVTs[0];
5027 unsigned NumValues = OutVTs.size();
5028 SmallVector<SDValue, 4> Values(NumValues);
5029 SmallVector<SDValue, 4> Chains(NumValues);
5031 for (unsigned i = 0; i < NumValues; ++i) {
5032 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5034 DAG.getConstant(Offsets[i], PtrVT));
5035 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
5036 Add, NULL, Offsets[i], false, 1);
5038 Chains[i] = L.getValue(1);
5041 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5042 MVT::Other, &Chains[0], NumValues);
5043 PendingLoads.push_back(Chain);
5045 SDValue MV = DAG.getNode(ISD::MERGE_VALUES,
5047 DAG.getVTList(&OutVTs[0], NumValues),
5048 &Values[0], NumValues);
5049 setValue(CS.getInstruction(), MV);
5051 if (DisableScheduling) {
5052 DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
5053 DAG.AssignOrdering(MV.getNode(), SDNodeOrder);
5057 // As a special case, a null chain means that a tail call has been emitted and
5058 // the DAG root is already updated.
5059 if (Result.second.getNode()) {
5060 DAG.setRoot(Result.second);
5061 if (DisableScheduling)
5062 DAG.AssignOrdering(Result.second.getNode(), SDNodeOrder);
5067 if (LandingPad && MMI) {
5068 // Insert a label at the end of the invoke call to mark the try range. This
5069 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5070 EndLabel = MMI->NextLabelID();
5071 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
5072 getRoot(), EndLabel));
5074 // Inform MachineModuleInfo of range.
5075 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
5079 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5080 /// value is equal or not-equal to zero.
5081 static bool IsOnlyUsedInZeroEqualityComparison(Value *V) {
5082 for (Value::use_iterator UI = V->use_begin(), E = V->use_end();
5084 if (ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5085 if (IC->isEquality())
5086 if (Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5087 if (C->isNullValue())
5089 // Unknown instruction.
5095 static SDValue getMemCmpLoad(Value *PtrVal, MVT LoadVT, const Type *LoadTy,
5096 SelectionDAGBuilder &Builder) {
5098 // Check to see if this load can be trivially constant folded, e.g. if the
5099 // input is from a string literal.
5100 if (Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5101 // Cast pointer to the type we really want to load.
5102 LoadInput = ConstantExpr::getBitCast(LoadInput,
5103 PointerType::getUnqual(LoadTy));
5105 if (Constant *LoadCst = ConstantFoldLoadFromConstPtr(LoadInput, Builder.TD))
5106 return Builder.getValue(LoadCst);
5109 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5110 // still constant memory, the input chain can be the entry node.
5112 bool ConstantMemory = false;
5114 // Do not serialize (non-volatile) loads of constant memory with anything.
5115 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5116 Root = Builder.DAG.getEntryNode();
5117 ConstantMemory = true;
5119 // Do not serialize non-volatile loads against each other.
5120 Root = Builder.DAG.getRoot();
5123 SDValue Ptr = Builder.getValue(PtrVal);
5124 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5125 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
5126 false /*volatile*/, 1 /* align=1 */);
5128 if (!ConstantMemory)
5129 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5134 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5135 /// If so, return true and lower it, otherwise return false and it will be
5136 /// lowered like a normal call.
5137 bool SelectionDAGBuilder::visitMemCmpCall(CallInst &I) {
5138 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5139 if (I.getNumOperands() != 4)
5142 Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
5143 if (!isa<PointerType>(LHS->getType()) || !isa<PointerType>(RHS->getType()) ||
5144 !isa<IntegerType>(I.getOperand(3)->getType()) ||
5145 !isa<IntegerType>(I.getType()))
5148 ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
5150 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5151 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5152 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5153 bool ActuallyDoIt = true;
5156 switch (Size->getZExtValue()) {
5158 LoadVT = MVT::Other;
5160 ActuallyDoIt = false;
5164 LoadTy = Type::getInt16Ty(Size->getContext());
5168 LoadTy = Type::getInt32Ty(Size->getContext());
5172 LoadTy = Type::getInt64Ty(Size->getContext());
5176 LoadVT = MVT::v4i32;
5177 LoadTy = Type::getInt32Ty(Size->getContext());
5178 LoadTy = VectorType::get(LoadTy, 4);
5183 // This turns into unaligned loads. We only do this if the target natively
5184 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5185 // we'll only produce a small number of byte loads.
5187 // Require that we can find a legal MVT, and only do this if the target
5188 // supports unaligned loads of that type. Expanding into byte loads would
5190 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5191 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5192 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5193 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5194 ActuallyDoIt = false;
5198 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5199 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5201 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5203 EVT CallVT = TLI.getValueType(I.getType(), true);
5204 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5214 void SelectionDAGBuilder::visitCall(CallInst &I) {
5215 const char *RenameFn = 0;
5216 if (Function *F = I.getCalledFunction()) {
5217 if (F->isDeclaration()) {
5218 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
5220 if (unsigned IID = II->getIntrinsicID(F)) {
5221 RenameFn = visitIntrinsicCall(I, IID);
5226 if (unsigned IID = F->getIntrinsicID()) {
5227 RenameFn = visitIntrinsicCall(I, IID);
5233 // Check for well-known libc/libm calls. If the function is internal, it
5234 // can't be a library call.
5235 if (!F->hasLocalLinkage() && F->hasName()) {
5236 StringRef Name = F->getName();
5237 if (Name == "copysign" || Name == "copysignf") {
5238 if (I.getNumOperands() == 3 && // Basic sanity checks.
5239 I.getOperand(1)->getType()->isFloatingPoint() &&
5240 I.getType() == I.getOperand(1)->getType() &&
5241 I.getType() == I.getOperand(2)->getType()) {
5242 SDValue LHS = getValue(I.getOperand(1));
5243 SDValue RHS = getValue(I.getOperand(2));
5244 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5245 LHS.getValueType(), LHS, RHS));
5248 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5249 if (I.getNumOperands() == 2 && // Basic sanity checks.
5250 I.getOperand(1)->getType()->isFloatingPoint() &&
5251 I.getType() == I.getOperand(1)->getType()) {
5252 SDValue Tmp = getValue(I.getOperand(1));
5253 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5254 Tmp.getValueType(), Tmp));
5257 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5258 if (I.getNumOperands() == 2 && // Basic sanity checks.
5259 I.getOperand(1)->getType()->isFloatingPoint() &&
5260 I.getType() == I.getOperand(1)->getType() &&
5261 I.onlyReadsMemory()) {
5262 SDValue Tmp = getValue(I.getOperand(1));
5263 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5264 Tmp.getValueType(), Tmp));
5267 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5268 if (I.getNumOperands() == 2 && // Basic sanity checks.
5269 I.getOperand(1)->getType()->isFloatingPoint() &&
5270 I.getType() == I.getOperand(1)->getType() &&
5271 I.onlyReadsMemory()) {
5272 SDValue Tmp = getValue(I.getOperand(1));
5273 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5274 Tmp.getValueType(), Tmp));
5277 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5278 if (I.getNumOperands() == 2 && // Basic sanity checks.
5279 I.getOperand(1)->getType()->isFloatingPoint() &&
5280 I.getType() == I.getOperand(1)->getType() &&
5281 I.onlyReadsMemory()) {
5282 SDValue Tmp = getValue(I.getOperand(1));
5283 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5284 Tmp.getValueType(), Tmp));
5287 } else if (Name == "memcmp") {
5288 if (visitMemCmpCall(I))
5292 } else if (isa<InlineAsm>(I.getOperand(0))) {
5299 Callee = getValue(I.getOperand(0));
5301 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5303 // Check if we can potentially perform a tail call. More detailed checking is
5304 // be done within LowerCallTo, after more information about the call is known.
5305 bool isTailCall = PerformTailCallOpt && I.isTailCall();
5307 LowerCallTo(&I, Callee, isTailCall);
5310 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
5311 /// this value and returns the result as a ValueVT value. This uses
5312 /// Chain/Flag as the input and updates them for the output Chain/Flag.
5313 /// If the Flag pointer is NULL, no flag is used.
5314 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
5315 unsigned Order, SDValue &Chain,
5316 SDValue *Flag) const {
5317 // Assemble the legal parts into the final values.
5318 SmallVector<SDValue, 4> Values(ValueVTs.size());
5319 SmallVector<SDValue, 8> Parts;
5320 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
5321 // Copy the legal parts from the registers.
5322 EVT ValueVT = ValueVTs[Value];
5323 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
5324 EVT RegisterVT = RegVTs[Value];
5326 Parts.resize(NumRegs);
5327 for (unsigned i = 0; i != NumRegs; ++i) {
5330 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
5332 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
5333 *Flag = P.getValue(2);
5336 Chain = P.getValue(1);
5338 if (DisableScheduling)
5339 DAG.AssignOrdering(P.getNode(), Order);
5341 // If the source register was virtual and if we know something about it,
5342 // add an assert node.
5343 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
5344 RegisterVT.isInteger() && !RegisterVT.isVector()) {
5345 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
5346 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5347 if (FLI.LiveOutRegInfo.size() > SlotNo) {
5348 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
5350 unsigned RegSize = RegisterVT.getSizeInBits();
5351 unsigned NumSignBits = LOI.NumSignBits;
5352 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
5354 // FIXME: We capture more information than the dag can represent. For
5355 // now, just use the tightest assertzext/assertsext possible.
5357 EVT FromVT(MVT::Other);
5358 if (NumSignBits == RegSize)
5359 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
5360 else if (NumZeroBits >= RegSize-1)
5361 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
5362 else if (NumSignBits > RegSize-8)
5363 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
5364 else if (NumZeroBits >= RegSize-8)
5365 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
5366 else if (NumSignBits > RegSize-16)
5367 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
5368 else if (NumZeroBits >= RegSize-16)
5369 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
5370 else if (NumSignBits > RegSize-32)
5371 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
5372 else if (NumZeroBits >= RegSize-32)
5373 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
5375 if (FromVT != MVT::Other) {
5376 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
5377 RegisterVT, P, DAG.getValueType(FromVT));
5379 if (DisableScheduling)
5380 DAG.AssignOrdering(P.getNode(), Order);
5388 Values[Value] = getCopyFromParts(DAG, dl, Order, Parts.begin(),
5389 NumRegs, RegisterVT, ValueVT);
5390 if (DisableScheduling)
5391 DAG.AssignOrdering(Values[Value].getNode(), Order);
5396 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5397 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
5398 &Values[0], ValueVTs.size());
5399 if (DisableScheduling)
5400 DAG.AssignOrdering(Res.getNode(), Order);
5404 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
5405 /// specified value into the registers specified by this object. This uses
5406 /// Chain/Flag as the input and updates them for the output Chain/Flag.
5407 /// If the Flag pointer is NULL, no flag is used.
5408 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
5409 unsigned Order, SDValue &Chain,
5410 SDValue *Flag) const {
5411 // Get the list of the values's legal parts.
5412 unsigned NumRegs = Regs.size();
5413 SmallVector<SDValue, 8> Parts(NumRegs);
5414 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
5415 EVT ValueVT = ValueVTs[Value];
5416 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
5417 EVT RegisterVT = RegVTs[Value];
5419 getCopyToParts(DAG, dl, Order,
5420 Val.getValue(Val.getResNo() + Value),
5421 &Parts[Part], NumParts, RegisterVT);
5425 // Copy the parts into the registers.
5426 SmallVector<SDValue, 8> Chains(NumRegs);
5427 for (unsigned i = 0; i != NumRegs; ++i) {
5430 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
5432 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
5433 *Flag = Part.getValue(1);
5436 Chains[i] = Part.getValue(0);
5438 if (DisableScheduling)
5439 DAG.AssignOrdering(Part.getNode(), Order);
5442 if (NumRegs == 1 || Flag)
5443 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
5444 // flagged to it. That is the CopyToReg nodes and the user are considered
5445 // a single scheduling unit. If we create a TokenFactor and return it as
5446 // chain, then the TokenFactor is both a predecessor (operand) of the
5447 // user as well as a successor (the TF operands are flagged to the user).
5448 // c1, f1 = CopyToReg
5449 // c2, f2 = CopyToReg
5450 // c3 = TokenFactor c1, c2
5453 Chain = Chains[NumRegs-1];
5455 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
5457 if (DisableScheduling)
5458 DAG.AssignOrdering(Chain.getNode(), Order);
5461 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
5462 /// operand list. This adds the code marker and includes the number of
5463 /// values added into it.
5464 void RegsForValue::AddInlineAsmOperands(unsigned Code,
5465 bool HasMatching,unsigned MatchingIdx,
5466 SelectionDAG &DAG, unsigned Order,
5467 std::vector<SDValue> &Ops) const {
5468 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
5469 unsigned Flag = Code | (Regs.size() << 3);
5471 Flag |= 0x80000000 | (MatchingIdx << 16);
5472 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
5475 if (DisableScheduling)
5476 DAG.AssignOrdering(Res.getNode(), Order);
5478 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
5479 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
5480 EVT RegisterVT = RegVTs[Value];
5481 for (unsigned i = 0; i != NumRegs; ++i) {
5482 assert(Reg < Regs.size() && "Mismatch in # registers expected");
5483 SDValue Res = DAG.getRegister(Regs[Reg++], RegisterVT);
5486 if (DisableScheduling)
5487 DAG.AssignOrdering(Res.getNode(), Order);
5492 /// isAllocatableRegister - If the specified register is safe to allocate,
5493 /// i.e. it isn't a stack pointer or some other special register, return the
5494 /// register class for the register. Otherwise, return null.
5495 static const TargetRegisterClass *
5496 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5497 const TargetLowering &TLI,
5498 const TargetRegisterInfo *TRI) {
5499 EVT FoundVT = MVT::Other;
5500 const TargetRegisterClass *FoundRC = 0;
5501 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5502 E = TRI->regclass_end(); RCI != E; ++RCI) {
5503 EVT ThisVT = MVT::Other;
5505 const TargetRegisterClass *RC = *RCI;
5506 // If none of the the value types for this register class are valid, we
5507 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5508 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5510 if (TLI.isTypeLegal(*I)) {
5511 // If we have already found this register in a different register class,
5512 // choose the one with the largest VT specified. For example, on
5513 // PowerPC, we favor f64 register classes over f32.
5514 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5521 if (ThisVT == MVT::Other) continue;
5523 // NOTE: This isn't ideal. In particular, this might allocate the
5524 // frame pointer in functions that need it (due to them not being taken
5525 // out of allocation, because a variable sized allocation hasn't been seen
5526 // yet). This is a slight code pessimization, but should still work.
5527 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5528 E = RC->allocation_order_end(MF); I != E; ++I)
5530 // We found a matching register class. Keep looking at others in case
5531 // we find one with larger registers that this physreg is also in.
5542 /// AsmOperandInfo - This contains information for each constraint that we are
5544 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
5545 public TargetLowering::AsmOperandInfo {
5547 /// CallOperand - If this is the result output operand or a clobber
5548 /// this is null, otherwise it is the incoming operand to the CallInst.
5549 /// This gets modified as the asm is processed.
5550 SDValue CallOperand;
5552 /// AssignedRegs - If this is a register or register class operand, this
5553 /// contains the set of register corresponding to the operand.
5554 RegsForValue AssignedRegs;
5556 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
5557 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5560 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5561 /// busy in OutputRegs/InputRegs.
5562 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5563 std::set<unsigned> &OutputRegs,
5564 std::set<unsigned> &InputRegs,
5565 const TargetRegisterInfo &TRI) const {
5567 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5568 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5571 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5572 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5576 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5577 /// corresponds to. If there is no Value* for this operand, it returns
5579 EVT getCallOperandValEVT(LLVMContext &Context,
5580 const TargetLowering &TLI,
5581 const TargetData *TD) const {
5582 if (CallOperandVal == 0) return MVT::Other;
5584 if (isa<BasicBlock>(CallOperandVal))
5585 return TLI.getPointerTy();
5587 const llvm::Type *OpTy = CallOperandVal->getType();
5589 // If this is an indirect operand, the operand is a pointer to the
5592 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5594 llvm_report_error("Indirect operand for inline asm not a pointer!");
5595 OpTy = PtrTy->getElementType();
5598 // If OpTy is not a single value, it may be a struct/union that we
5599 // can tile with integers.
5600 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5601 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5610 OpTy = IntegerType::get(Context, BitSize);
5615 return TLI.getValueType(OpTy, true);
5619 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5621 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5622 const TargetRegisterInfo &TRI) {
5623 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5625 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5626 for (; *Aliases; ++Aliases)
5627 Regs.insert(*Aliases);
5630 } // end llvm namespace.
5633 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5634 /// specified operand. We prefer to assign virtual registers, to allow the
5635 /// register allocator to handle the assignment process. However, if the asm
5636 /// uses features that we can't model on machineinstrs, we have SDISel do the
5637 /// allocation. This produces generally horrible, but correct, code.
5639 /// OpInfo describes the operand.
5640 /// Input and OutputRegs are the set of already allocated physical registers.
5642 void SelectionDAGBuilder::
5643 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5644 std::set<unsigned> &OutputRegs,
5645 std::set<unsigned> &InputRegs) {
5646 LLVMContext &Context = FuncInfo.Fn->getContext();
5648 // Compute whether this value requires an input register, an output register,
5650 bool isOutReg = false;
5651 bool isInReg = false;
5652 switch (OpInfo.Type) {
5653 case InlineAsm::isOutput:
5656 // If there is an input constraint that matches this, we need to reserve
5657 // the input register so no other inputs allocate to it.
5658 isInReg = OpInfo.hasMatchingInput();
5660 case InlineAsm::isInput:
5664 case InlineAsm::isClobber:
5671 MachineFunction &MF = DAG.getMachineFunction();
5672 SmallVector<unsigned, 4> Regs;
5674 // If this is a constraint for a single physreg, or a constraint for a
5675 // register class, find it.
5676 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5677 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5678 OpInfo.ConstraintVT);
5680 unsigned NumRegs = 1;
5681 if (OpInfo.ConstraintVT != MVT::Other) {
5682 // If this is a FP input in an integer register (or visa versa) insert a bit
5683 // cast of the input value. More generally, handle any case where the input
5684 // value disagrees with the register class we plan to stick this in.
5685 if (OpInfo.Type == InlineAsm::isInput &&
5686 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5687 // Try to convert to the first EVT that the reg class contains. If the
5688 // types are identical size, use a bitcast to convert (e.g. two differing
5690 EVT RegVT = *PhysReg.second->vt_begin();
5691 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5692 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5693 RegVT, OpInfo.CallOperand);
5694 OpInfo.ConstraintVT = RegVT;
5695 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5696 // If the input is a FP value and we want it in FP registers, do a
5697 // bitcast to the corresponding integer type. This turns an f64 value
5698 // into i64, which can be passed with two i32 values on a 32-bit
5700 RegVT = EVT::getIntegerVT(Context,
5701 OpInfo.ConstraintVT.getSizeInBits());
5702 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5703 RegVT, OpInfo.CallOperand);
5704 OpInfo.ConstraintVT = RegVT;
5707 if (DisableScheduling)
5708 DAG.AssignOrdering(OpInfo.CallOperand.getNode(), SDNodeOrder);
5711 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5715 EVT ValueVT = OpInfo.ConstraintVT;
5717 // If this is a constraint for a specific physical register, like {r17},
5719 if (unsigned AssignedReg = PhysReg.first) {
5720 const TargetRegisterClass *RC = PhysReg.second;
5721 if (OpInfo.ConstraintVT == MVT::Other)
5722 ValueVT = *RC->vt_begin();
5724 // Get the actual register value type. This is important, because the user
5725 // may have asked for (e.g.) the AX register in i32 type. We need to
5726 // remember that AX is actually i16 to get the right extension.
5727 RegVT = *RC->vt_begin();
5729 // This is a explicit reference to a physical register.
5730 Regs.push_back(AssignedReg);
5732 // If this is an expanded reference, add the rest of the regs to Regs.
5734 TargetRegisterClass::iterator I = RC->begin();
5735 for (; *I != AssignedReg; ++I)
5736 assert(I != RC->end() && "Didn't find reg!");
5738 // Already added the first reg.
5740 for (; NumRegs; --NumRegs, ++I) {
5741 assert(I != RC->end() && "Ran out of registers to allocate!");
5746 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5747 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5748 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5752 // Otherwise, if this was a reference to an LLVM register class, create vregs
5753 // for this reference.
5754 if (const TargetRegisterClass *RC = PhysReg.second) {
5755 RegVT = *RC->vt_begin();
5756 if (OpInfo.ConstraintVT == MVT::Other)
5759 // Create the appropriate number of virtual registers.
5760 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5761 for (; NumRegs; --NumRegs)
5762 Regs.push_back(RegInfo.createVirtualRegister(RC));
5764 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5768 // This is a reference to a register class that doesn't directly correspond
5769 // to an LLVM register class. Allocate NumRegs consecutive, available,
5770 // registers from the class.
5771 std::vector<unsigned> RegClassRegs
5772 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5773 OpInfo.ConstraintVT);
5775 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5776 unsigned NumAllocated = 0;
5777 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5778 unsigned Reg = RegClassRegs[i];
5779 // See if this register is available.
5780 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5781 (isInReg && InputRegs.count(Reg))) { // Already used.
5782 // Make sure we find consecutive registers.
5787 // Check to see if this register is allocatable (i.e. don't give out the
5789 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5790 if (!RC) { // Couldn't allocate this register.
5791 // Reset NumAllocated to make sure we return consecutive registers.
5796 // Okay, this register is good, we can use it.
5799 // If we allocated enough consecutive registers, succeed.
5800 if (NumAllocated == NumRegs) {
5801 unsigned RegStart = (i-NumAllocated)+1;
5802 unsigned RegEnd = i+1;
5803 // Mark all of the allocated registers used.
5804 for (unsigned i = RegStart; i != RegEnd; ++i)
5805 Regs.push_back(RegClassRegs[i]);
5807 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5808 OpInfo.ConstraintVT);
5809 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5814 // Otherwise, we couldn't allocate enough registers for this.
5817 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5818 /// processed uses a memory 'm' constraint.
5820 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5821 const TargetLowering &TLI) {
5822 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5823 InlineAsm::ConstraintInfo &CI = CInfos[i];
5824 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5825 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5826 if (CType == TargetLowering::C_Memory)
5830 // Indirect operand accesses access memory.
5838 /// visitInlineAsm - Handle a call to an InlineAsm object.
5840 void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
5841 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5843 /// ConstraintOperands - Information about all of the constraints.
5844 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5846 std::set<unsigned> OutputRegs, InputRegs;
5848 // Do a prepass over the constraints, canonicalizing them, and building up the
5849 // ConstraintOperands list.
5850 std::vector<InlineAsm::ConstraintInfo>
5851 ConstraintInfos = IA->ParseConstraints();
5853 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5855 SDValue Chain, Flag;
5857 // We won't need to flush pending loads if this asm doesn't touch
5858 // memory and is nonvolatile.
5859 if (hasMemory || IA->hasSideEffects())
5862 Chain = DAG.getRoot();
5864 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5865 unsigned ResNo = 0; // ResNo - The result number of the next output.
5866 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5867 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5868 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5870 EVT OpVT = MVT::Other;
5872 // Compute the value type for each operand.
5873 switch (OpInfo.Type) {
5874 case InlineAsm::isOutput:
5875 // Indirect outputs just consume an argument.
5876 if (OpInfo.isIndirect) {
5877 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5881 // The return value of the call is this value. As such, there is no
5882 // corresponding argument.
5883 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5885 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5886 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5888 assert(ResNo == 0 && "Asm only has one result!");
5889 OpVT = TLI.getValueType(CS.getType());
5893 case InlineAsm::isInput:
5894 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5896 case InlineAsm::isClobber:
5901 // If this is an input or an indirect output, process the call argument.
5902 // BasicBlocks are labels, currently appearing only in asm's.
5903 if (OpInfo.CallOperandVal) {
5904 // Strip bitcasts, if any. This mostly comes up for functions.
5905 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5907 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5908 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5910 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5913 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5916 OpInfo.ConstraintVT = OpVT;
5919 // Second pass over the constraints: compute which constraint option to use
5920 // and assign registers to constraints that want a specific physreg.
5921 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5922 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5924 // If this is an output operand with a matching input operand, look up the
5925 // matching input. If their types mismatch, e.g. one is an integer, the
5926 // other is floating point, or their sizes are different, flag it as an
5928 if (OpInfo.hasMatchingInput()) {
5929 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5930 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5931 if ((OpInfo.ConstraintVT.isInteger() !=
5932 Input.ConstraintVT.isInteger()) ||
5933 (OpInfo.ConstraintVT.getSizeInBits() !=
5934 Input.ConstraintVT.getSizeInBits())) {
5935 llvm_report_error("Unsupported asm: input constraint"
5936 " with a matching output constraint of incompatible"
5939 Input.ConstraintVT = OpInfo.ConstraintVT;
5943 // Compute the constraint code and ConstraintType to use.
5944 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5946 // If this is a memory input, and if the operand is not indirect, do what we
5947 // need to to provide an address for the memory input.
5948 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5949 !OpInfo.isIndirect) {
5950 assert(OpInfo.Type == InlineAsm::isInput &&
5951 "Can only indirectify direct input operands!");
5953 // Memory operands really want the address of the value. If we don't have
5954 // an indirect input, put it in the constpool if we can, otherwise spill
5955 // it to a stack slot.
5957 // If the operand is a float, integer, or vector constant, spill to a
5958 // constant pool entry to get its address.
5959 Value *OpVal = OpInfo.CallOperandVal;
5960 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5961 isa<ConstantVector>(OpVal)) {
5962 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5963 TLI.getPointerTy());
5965 // Otherwise, create a stack slot and emit a store to it before the
5967 const Type *Ty = OpVal->getType();
5968 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5969 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5970 MachineFunction &MF = DAG.getMachineFunction();
5971 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5972 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5973 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5974 OpInfo.CallOperand, StackSlot, NULL, 0);
5975 OpInfo.CallOperand = StackSlot;
5978 // There is no longer a Value* corresponding to this operand.
5979 OpInfo.CallOperandVal = 0;
5981 // It is now an indirect operand.
5982 OpInfo.isIndirect = true;
5985 // If this constraint is for a specific register, allocate it before
5987 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5988 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5991 ConstraintInfos.clear();
5993 // Second pass - Loop over all of the operands, assigning virtual or physregs
5994 // to register class operands.
5995 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5996 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5998 // C_Register operands have already been allocated, Other/Memory don't need
6000 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6001 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
6004 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6005 std::vector<SDValue> AsmNodeOperands;
6006 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6007 AsmNodeOperands.push_back(
6008 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
6011 // Loop over all of the inputs, copying the operand values into the
6012 // appropriate registers and processing the output regs.
6013 RegsForValue RetValRegs;
6015 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6016 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6018 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6019 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6021 switch (OpInfo.Type) {
6022 case InlineAsm::isOutput: {
6023 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6024 OpInfo.ConstraintType != TargetLowering::C_Register) {
6025 // Memory output, or 'other' output (e.g. 'X' constraint).
6026 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6028 // Add information to the INLINEASM node to know about this output.
6029 unsigned ResOpType = 4/*MEM*/ | (1<<3);
6030 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6031 TLI.getPointerTy()));
6032 AsmNodeOperands.push_back(OpInfo.CallOperand);
6036 // Otherwise, this is a register or register class output.
6038 // Copy the output from the appropriate register. Find a register that
6040 if (OpInfo.AssignedRegs.Regs.empty()) {
6041 llvm_report_error("Couldn't allocate output reg for"
6042 " constraint '" + OpInfo.ConstraintCode + "'!");
6045 // If this is an indirect operand, store through the pointer after the
6047 if (OpInfo.isIndirect) {
6048 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6049 OpInfo.CallOperandVal));
6051 // This is the result value of the call.
6052 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
6054 // Concatenate this output onto the outputs list.
6055 RetValRegs.append(OpInfo.AssignedRegs);
6058 // Add information to the INLINEASM node to know that this register is
6060 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6061 6 /* EARLYCLOBBER REGDEF */ :
6069 case InlineAsm::isInput: {
6070 SDValue InOperandVal = OpInfo.CallOperand;
6072 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6073 // If this is required to match an output register we have already set,
6074 // just use its register.
6075 unsigned OperandNo = OpInfo.getMatchedOperand();
6077 // Scan until we find the definition we already emitted of this operand.
6078 // When we find it, create a RegsForValue operand.
6079 unsigned CurOp = 2; // The first operand.
6080 for (; OperandNo; --OperandNo) {
6081 // Advance to the next operand.
6083 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6084 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
6085 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
6086 (OpFlag & 7) == 4 /*MEM*/) &&
6087 "Skipped past definitions?");
6088 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6092 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6093 if ((OpFlag & 7) == 2 /*REGDEF*/
6094 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
6095 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6096 if (OpInfo.isIndirect) {
6097 llvm_report_error("Don't know how to handle tied indirect "
6098 "register inputs yet!");
6100 RegsForValue MatchedRegs;
6101 MatchedRegs.TLI = &TLI;
6102 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6103 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6104 MatchedRegs.RegVTs.push_back(RegVT);
6105 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6106 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6109 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6111 // Use the produced MatchedRegs object to
6112 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6113 SDNodeOrder, Chain, &Flag);
6114 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
6115 true, OpInfo.getMatchedOperand(),
6116 DAG, SDNodeOrder, AsmNodeOperands);
6119 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
6120 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
6121 "Unexpected number of operands");
6122 // Add information to the INLINEASM node to know about this input.
6123 // See InlineAsm.h isUseOperandTiedToDef.
6124 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
6125 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6126 TLI.getPointerTy()));
6127 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6132 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6133 assert(!OpInfo.isIndirect &&
6134 "Don't know how to handle indirect other inputs yet!");
6136 std::vector<SDValue> Ops;
6137 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
6138 hasMemory, Ops, DAG);
6140 llvm_report_error("Invalid operand for inline asm"
6141 " constraint '" + OpInfo.ConstraintCode + "'!");
6144 // Add information to the INLINEASM node to know about this input.
6145 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
6146 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6147 TLI.getPointerTy()));
6148 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6150 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6151 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6152 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6153 "Memory operands expect pointer values");
6155 // Add information to the INLINEASM node to know about this input.
6156 unsigned ResOpType = 4/*MEM*/ | (1<<3);
6157 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6158 TLI.getPointerTy()));
6159 AsmNodeOperands.push_back(InOperandVal);
6163 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6164 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6165 "Unknown constraint type!");
6166 assert(!OpInfo.isIndirect &&
6167 "Don't know how to handle indirect register inputs yet!");
6169 // Copy the input into the appropriate registers.
6170 if (OpInfo.AssignedRegs.Regs.empty()) {
6171 llvm_report_error("Couldn't allocate input reg for"
6172 " constraint '"+ OpInfo.ConstraintCode +"'!");
6175 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6176 SDNodeOrder, Chain, &Flag);
6178 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
6183 case InlineAsm::isClobber: {
6184 // Add the clobbered value to the operand list, so that the register
6185 // allocator is aware that the physreg got clobbered.
6186 if (!OpInfo.AssignedRegs.Regs.empty())
6187 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
6188 false, 0, DAG, SDNodeOrder,
6195 // Finish up input operands.
6196 AsmNodeOperands[0] = Chain;
6197 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6199 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6200 DAG.getVTList(MVT::Other, MVT::Flag),
6201 &AsmNodeOperands[0], AsmNodeOperands.size());
6202 Flag = Chain.getValue(1);
6204 // If this asm returns a register value, copy the result from that register
6205 // and set it as the value of the call.
6206 if (!RetValRegs.Regs.empty()) {
6207 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
6208 SDNodeOrder, Chain, &Flag);
6210 // FIXME: Why don't we do this for inline asms with MRVs?
6211 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6212 EVT ResultType = TLI.getValueType(CS.getType());
6214 // If any of the results of the inline asm is a vector, it may have the
6215 // wrong width/num elts. This can happen for register classes that can
6216 // contain multiple different value types. The preg or vreg allocated may
6217 // not have the same VT as was expected. Convert it to the right type
6218 // with bit_convert.
6219 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6220 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
6223 } else if (ResultType != Val.getValueType() &&
6224 ResultType.isInteger() && Val.getValueType().isInteger()) {
6225 // If a result value was tied to an input value, the computed result may
6226 // have a wider width than the expected result. Extract the relevant
6228 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6231 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6234 setValue(CS.getInstruction(), Val);
6235 // Don't need to use this as a chain in this case.
6236 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6240 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
6242 // Process indirect outputs, first output all of the flagged copies out of
6244 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6245 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6246 Value *Ptr = IndirectStoresToEmit[i].second;
6247 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
6248 SDNodeOrder, Chain, &Flag);
6249 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6253 // Emit the non-flagged stores from the physregs.
6254 SmallVector<SDValue, 8> OutChains;
6255 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6256 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6257 StoresToEmit[i].first,
6258 getValue(StoresToEmit[i].second),
6259 StoresToEmit[i].second, 0);
6260 OutChains.push_back(Val);
6263 if (!OutChains.empty())
6264 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6265 &OutChains[0], OutChains.size());
6270 void SelectionDAGBuilder::visitVAStart(CallInst &I) {
6271 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6272 MVT::Other, getRoot(),
6273 getValue(I.getOperand(1)),
6274 DAG.getSrcValue(I.getOperand(1))));
6277 void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
6278 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6279 getRoot(), getValue(I.getOperand(0)),
6280 DAG.getSrcValue(I.getOperand(0)));
6282 DAG.setRoot(V.getValue(1));
6285 void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
6286 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6287 MVT::Other, getRoot(),
6288 getValue(I.getOperand(1)),
6289 DAG.getSrcValue(I.getOperand(1))));
6292 void SelectionDAGBuilder::visitVACopy(CallInst &I) {
6293 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6294 MVT::Other, getRoot(),
6295 getValue(I.getOperand(1)),
6296 getValue(I.getOperand(2)),
6297 DAG.getSrcValue(I.getOperand(1)),
6298 DAG.getSrcValue(I.getOperand(2))));
6301 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6302 /// implementation, which just calls LowerCall.
6303 /// FIXME: When all targets are
6304 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6305 std::pair<SDValue, SDValue>
6306 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6307 bool RetSExt, bool RetZExt, bool isVarArg,
6308 bool isInreg, unsigned NumFixedArgs,
6309 CallingConv::ID CallConv, bool isTailCall,
6310 bool isReturnValueUsed,
6312 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl,
6314 assert((!isTailCall || PerformTailCallOpt) &&
6315 "isTailCall set when tail-call optimizations are disabled!");
6317 // Handle all of the outgoing arguments.
6318 SmallVector<ISD::OutputArg, 32> Outs;
6319 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6320 SmallVector<EVT, 4> ValueVTs;
6321 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6322 for (unsigned Value = 0, NumValues = ValueVTs.size();
6323 Value != NumValues; ++Value) {
6324 EVT VT = ValueVTs[Value];
6325 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6326 SDValue Op = SDValue(Args[i].Node.getNode(),
6327 Args[i].Node.getResNo() + Value);
6328 ISD::ArgFlagsTy Flags;
6329 unsigned OriginalAlignment =
6330 getTargetData()->getABITypeAlignment(ArgTy);
6336 if (Args[i].isInReg)
6340 if (Args[i].isByVal) {
6342 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6343 const Type *ElementTy = Ty->getElementType();
6344 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6345 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6346 // For ByVal, alignment should come from FE. BE will guess if this
6347 // info is not there but there are cases it cannot get right.
6348 if (Args[i].Alignment)
6349 FrameAlign = Args[i].Alignment;
6350 Flags.setByValAlign(FrameAlign);
6351 Flags.setByValSize(FrameSize);
6355 Flags.setOrigAlign(OriginalAlignment);
6357 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6358 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6359 SmallVector<SDValue, 4> Parts(NumParts);
6360 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6363 ExtendKind = ISD::SIGN_EXTEND;
6364 else if (Args[i].isZExt)
6365 ExtendKind = ISD::ZERO_EXTEND;
6367 getCopyToParts(DAG, dl, Order, Op, &Parts[0], NumParts,
6368 PartVT, ExtendKind);
6370 for (unsigned j = 0; j != NumParts; ++j) {
6371 // if it isn't first piece, alignment must be 1
6372 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
6373 if (NumParts > 1 && j == 0)
6374 MyFlags.Flags.setSplit();
6376 MyFlags.Flags.setOrigAlign(1);
6378 Outs.push_back(MyFlags);
6383 // Handle the incoming return values from the call.
6384 SmallVector<ISD::InputArg, 32> Ins;
6385 SmallVector<EVT, 4> RetTys;
6386 ComputeValueVTs(*this, RetTy, RetTys);
6387 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6389 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6390 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6391 for (unsigned i = 0; i != NumRegs; ++i) {
6392 ISD::InputArg MyFlags;
6393 MyFlags.VT = RegisterVT;
6394 MyFlags.Used = isReturnValueUsed;
6396 MyFlags.Flags.setSExt();
6398 MyFlags.Flags.setZExt();
6400 MyFlags.Flags.setInReg();
6401 Ins.push_back(MyFlags);
6405 // Check if target-dependent constraints permit a tail call here.
6406 // Target-independent constraints should be checked by the caller.
6408 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
6411 SmallVector<SDValue, 4> InVals;
6412 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6413 Outs, Ins, dl, DAG, InVals);
6415 // Verify that the target's LowerCall behaved as expected.
6416 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6417 "LowerCall didn't return a valid chain!");
6418 assert((!isTailCall || InVals.empty()) &&
6419 "LowerCall emitted a return value for a tail call!");
6420 assert((isTailCall || InVals.size() == Ins.size()) &&
6421 "LowerCall didn't emit the correct number of values!");
6422 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6423 assert(InVals[i].getNode() &&
6424 "LowerCall emitted a null value!");
6425 assert(Ins[i].VT == InVals[i].getValueType() &&
6426 "LowerCall emitted a value with the wrong type!");
6429 if (DisableScheduling)
6430 DAG.AssignOrdering(Chain.getNode(), Order);
6432 // For a tail call, the return value is merely live-out and there aren't
6433 // any nodes in the DAG representing it. Return a special value to
6434 // indicate that a tail call has been emitted and no more Instructions
6435 // should be processed in the current block.
6438 return std::make_pair(SDValue(), SDValue());
6441 // Collect the legal value parts into potentially illegal values
6442 // that correspond to the original function's return values.
6443 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6445 AssertOp = ISD::AssertSext;
6447 AssertOp = ISD::AssertZext;
6448 SmallVector<SDValue, 4> ReturnValues;
6449 unsigned CurReg = 0;
6450 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6452 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6453 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6455 SDValue ReturnValue =
6456 getCopyFromParts(DAG, dl, Order, &InVals[CurReg], NumRegs,
6457 RegisterVT, VT, AssertOp);
6458 ReturnValues.push_back(ReturnValue);
6459 if (DisableScheduling)
6460 DAG.AssignOrdering(ReturnValue.getNode(), Order);
6464 // For a function returning void, there is no return value. We can't create
6465 // such a node, so we just return a null return value in that case. In
6466 // that case, nothing will actualy look at the value.
6467 if (ReturnValues.empty())
6468 return std::make_pair(SDValue(), Chain);
6470 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6471 DAG.getVTList(&RetTys[0], RetTys.size()),
6472 &ReturnValues[0], ReturnValues.size());
6473 if (DisableScheduling)
6474 DAG.AssignOrdering(Res.getNode(), Order);
6475 return std::make_pair(Res, Chain);
6478 void TargetLowering::LowerOperationWrapper(SDNode *N,
6479 SmallVectorImpl<SDValue> &Results,
6480 SelectionDAG &DAG) {
6481 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6483 Results.push_back(Res);
6486 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6487 llvm_unreachable("LowerOperation not implemented for this target!");
6491 void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
6492 SDValue Op = getValue(V);
6493 assert((Op.getOpcode() != ISD::CopyFromReg ||
6494 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6495 "Copy from a reg to the same reg!");
6496 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6498 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6499 SDValue Chain = DAG.getEntryNode();
6500 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), SDNodeOrder, Chain, 0);
6501 PendingExports.push_back(Chain);
6504 #include "llvm/CodeGen/SelectionDAGISel.h"
6506 void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
6507 // If this is the entry block, emit arguments.
6508 Function &F = *LLVMBB->getParent();
6509 SelectionDAG &DAG = SDB->DAG;
6510 SDValue OldRoot = DAG.getRoot();
6511 DebugLoc dl = SDB->getCurDebugLoc();
6512 const TargetData *TD = TLI.getTargetData();
6513 SmallVector<ISD::InputArg, 16> Ins;
6515 // Check whether the function can return without sret-demotion.
6516 SmallVector<EVT, 4> OutVTs;
6517 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
6518 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6519 OutVTs, OutsFlags, TLI);
6520 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
6522 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
6523 OutVTs, OutsFlags, DAG);
6524 if (!FLI.CanLowerReturn) {
6525 // Put in an sret pointer parameter before all the other parameters.
6526 SmallVector<EVT, 1> ValueVTs;
6527 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6529 // NOTE: Assuming that a pointer will never break down to more than one VT
6531 ISD::ArgFlagsTy Flags;
6533 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]);
6534 ISD::InputArg RetArg(Flags, RegisterVT, true);
6535 Ins.push_back(RetArg);
6538 // Set up the incoming argument description vector.
6540 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
6541 I != E; ++I, ++Idx) {
6542 SmallVector<EVT, 4> ValueVTs;
6543 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6544 bool isArgValueUsed = !I->use_empty();
6545 for (unsigned Value = 0, NumValues = ValueVTs.size();
6546 Value != NumValues; ++Value) {
6547 EVT VT = ValueVTs[Value];
6548 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6549 ISD::ArgFlagsTy Flags;
6550 unsigned OriginalAlignment =
6551 TD->getABITypeAlignment(ArgTy);
6553 if (F.paramHasAttr(Idx, Attribute::ZExt))
6555 if (F.paramHasAttr(Idx, Attribute::SExt))
6557 if (F.paramHasAttr(Idx, Attribute::InReg))
6559 if (F.paramHasAttr(Idx, Attribute::StructRet))
6561 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6563 const PointerType *Ty = cast<PointerType>(I->getType());
6564 const Type *ElementTy = Ty->getElementType();
6565 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6566 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6567 // For ByVal, alignment should be passed from FE. BE will guess if
6568 // this info is not there but there are cases it cannot get right.
6569 if (F.getParamAlignment(Idx))
6570 FrameAlign = F.getParamAlignment(Idx);
6571 Flags.setByValAlign(FrameAlign);
6572 Flags.setByValSize(FrameSize);
6574 if (F.paramHasAttr(Idx, Attribute::Nest))
6576 Flags.setOrigAlign(OriginalAlignment);
6578 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6579 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6580 for (unsigned i = 0; i != NumRegs; ++i) {
6581 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6582 if (NumRegs > 1 && i == 0)
6583 MyFlags.Flags.setSplit();
6584 // if it isn't first piece, alignment must be 1
6586 MyFlags.Flags.setOrigAlign(1);
6587 Ins.push_back(MyFlags);
6592 // Call the target to set up the argument values.
6593 SmallVector<SDValue, 8> InVals;
6594 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6598 // Verify that the target's LowerFormalArguments behaved as expected.
6599 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6600 "LowerFormalArguments didn't return a valid chain!");
6601 assert(InVals.size() == Ins.size() &&
6602 "LowerFormalArguments didn't emit the correct number of values!");
6604 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6605 assert(InVals[i].getNode() &&
6606 "LowerFormalArguments emitted a null value!");
6607 assert(Ins[i].VT == InVals[i].getValueType() &&
6608 "LowerFormalArguments emitted a value with the wrong type!");
6612 // Update the DAG with the new chain value resulting from argument lowering.
6613 DAG.setRoot(NewRoot);
6615 // Set up the argument values.
6618 if (!FLI.CanLowerReturn) {
6619 // Create a virtual register for the sret pointer, and put in a copy
6620 // from the sret argument into it.
6621 SmallVector<EVT, 1> ValueVTs;
6622 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6623 EVT VT = ValueVTs[0];
6624 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6625 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6626 SDValue ArgValue = getCopyFromParts(DAG, dl, 0, &InVals[0], 1,
6627 RegVT, VT, AssertOp);
6629 MachineFunction& MF = SDB->DAG.getMachineFunction();
6630 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6631 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6632 FLI.DemoteRegister = SRetReg;
6633 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), SRetReg, ArgValue);
6634 DAG.setRoot(NewRoot);
6636 // i indexes lowered arguments. Bump it past the hidden sret argument.
6637 // Idx indexes LLVM arguments. Don't touch it.
6641 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6643 SmallVector<SDValue, 4> ArgValues;
6644 SmallVector<EVT, 4> ValueVTs;
6645 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6646 unsigned NumValues = ValueVTs.size();
6647 for (unsigned Value = 0; Value != NumValues; ++Value) {
6648 EVT VT = ValueVTs[Value];
6649 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6650 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6652 if (!I->use_empty()) {
6653 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6654 if (F.paramHasAttr(Idx, Attribute::SExt))
6655 AssertOp = ISD::AssertSext;
6656 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6657 AssertOp = ISD::AssertZext;
6659 ArgValues.push_back(getCopyFromParts(DAG, dl, 0, &InVals[i],
6660 NumParts, PartVT, VT,
6667 if (!I->use_empty()) {
6668 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6669 SDB->getCurDebugLoc());
6670 SDB->setValue(I, Res);
6672 // If this argument is live outside of the entry block, insert a copy from
6673 // whereever we got it to the vreg that other BB's will reference it as.
6674 SDB->CopyToExportRegsIfNeeded(I);
6678 assert(i == InVals.size() && "Argument register count mismatch!");
6680 // Finally, if the target has anything special to do, allow it to do so.
6681 // FIXME: this should insert code into the DAG!
6682 EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction());
6685 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6686 /// ensure constants are generated when needed. Remember the virtual registers
6687 /// that need to be added to the Machine PHI nodes as input. We cannot just
6688 /// directly add them, because expansion might result in multiple MBB's for one
6689 /// BB. As such, the start of the BB might correspond to a different MBB than
6693 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
6694 TerminatorInst *TI = LLVMBB->getTerminator();
6696 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6698 // Check successor nodes' PHI nodes that expect a constant to be available
6700 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6701 BasicBlock *SuccBB = TI->getSuccessor(succ);
6702 if (!isa<PHINode>(SuccBB->begin())) continue;
6703 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6705 // If this terminator has multiple identical successors (common for
6706 // switches), only handle each succ once.
6707 if (!SuccsHandled.insert(SuccMBB)) continue;
6709 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6712 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6713 // nodes and Machine PHI nodes, but the incoming operands have not been
6715 for (BasicBlock::iterator I = SuccBB->begin();
6716 (PN = dyn_cast<PHINode>(I)); ++I) {
6717 // Ignore dead phi's.
6718 if (PN->use_empty()) continue;
6721 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6723 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
6724 unsigned &RegOut = SDB->ConstantsOut[C];
6726 RegOut = FuncInfo->CreateRegForValue(C);
6727 SDB->CopyValueToVirtualRegister(C, RegOut);
6731 Reg = FuncInfo->ValueMap[PHIOp];
6733 assert(isa<AllocaInst>(PHIOp) &&
6734 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6735 "Didn't codegen value into a register!??");
6736 Reg = FuncInfo->CreateRegForValue(PHIOp);
6737 SDB->CopyValueToVirtualRegister(PHIOp, Reg);
6741 // Remember that this register needs to added to the machine PHI node as
6742 // the input for this MBB.
6743 SmallVector<EVT, 4> ValueVTs;
6744 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6745 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6746 EVT VT = ValueVTs[vti];
6747 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6748 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6749 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6750 Reg += NumRegisters;
6754 SDB->ConstantsOut.clear();
6757 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6758 /// supports legal types, and it emits MachineInstrs directly instead of
6759 /// creating SelectionDAG nodes.
6762 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6764 TerminatorInst *TI = LLVMBB->getTerminator();
6766 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6767 unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
6769 // Check successor nodes' PHI nodes that expect a constant to be available
6771 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6772 BasicBlock *SuccBB = TI->getSuccessor(succ);
6773 if (!isa<PHINode>(SuccBB->begin())) continue;
6774 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6776 // If this terminator has multiple identical successors (common for
6777 // switches), only handle each succ once.
6778 if (!SuccsHandled.insert(SuccMBB)) continue;
6780 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6783 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6784 // nodes and Machine PHI nodes, but the incoming operands have not been
6786 for (BasicBlock::iterator I = SuccBB->begin();
6787 (PN = dyn_cast<PHINode>(I)); ++I) {
6788 // Ignore dead phi's.
6789 if (PN->use_empty()) continue;
6791 // Only handle legal types. Two interesting things to note here. First,
6792 // by bailing out early, we may leave behind some dead instructions,
6793 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6794 // own moves. Second, this check is necessary becuase FastISel doesn't
6795 // use CreateRegForValue to create registers, so it always creates
6796 // exactly one register for each non-void instruction.
6797 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6798 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6801 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6803 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6808 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6810 unsigned Reg = F->getRegForValue(PHIOp);
6812 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6815 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));