1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/GCStrategy.h"
36 #include "llvm/CodeGen/GCMetadata.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineJumpTableInfo.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
74 /// RegsForValue - This struct represents the registers (physical or virtual)
75 /// that a particular set of values is assigned, and the type information
76 /// about the value. The most common situation is to represent one value at a
77 /// time, but struct or array values are handled element-wise as multiple
78 /// values. The splitting of aggregates is performed recursively, so that we
79 /// never have aggregate-typed registers. The values at this point do not
80 /// necessarily have legal types, so each value may require one or more
81 /// registers of some legal type.
84 /// TLI - The TargetLowering object.
86 const TargetLowering *TLI;
88 /// ValueVTs - The value types of the values, which may not be legal, and
89 /// may need be promoted or synthesized from one or more registers.
91 SmallVector<EVT, 4> ValueVTs;
93 /// RegVTs - The value types of the registers. This is the same size as
94 /// ValueVTs and it records, for each value, what the type of the assigned
95 /// register or registers are. (Individual values are never synthesized
96 /// from more than one type of register.)
98 /// With virtual registers, the contents of RegVTs is redundant with TLI's
99 /// getRegisterType member function, however when with physical registers
100 /// it is necessary to have a separate record of the types.
102 SmallVector<EVT, 4> RegVTs;
104 /// Regs - This list holds the registers assigned to the values.
105 /// Each legal or promoted value requires one register, and each
106 /// expanded value requires multiple registers.
108 SmallVector<unsigned, 4> Regs;
110 RegsForValue() : TLI(0) {}
112 RegsForValue(const TargetLowering &tli,
113 const SmallVector<unsigned, 4> ®s,
114 EVT regvt, EVT valuevt)
115 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
116 RegsForValue(const TargetLowering &tli,
117 const SmallVector<unsigned, 4> ®s,
118 const SmallVector<EVT, 4> ®vts,
119 const SmallVector<EVT, 4> &valuevts)
120 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
121 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
122 unsigned Reg, const Type *Ty) : TLI(&tli) {
123 ComputeValueVTs(tli, Ty, ValueVTs);
125 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
126 EVT ValueVT = ValueVTs[Value];
127 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
128 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
129 for (unsigned i = 0; i != NumRegs; ++i)
130 Regs.push_back(Reg + i);
131 RegVTs.push_back(RegisterVT);
136 /// areValueTypesLegal - Return true if types of all the values are legal.
137 bool areValueTypesLegal() {
138 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
139 EVT RegisterVT = RegVTs[Value];
140 if (!TLI->isTypeLegal(RegisterVT))
147 /// append - Add the specified values to this one.
148 void append(const RegsForValue &RHS) {
150 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
151 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
152 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
156 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
157 /// this value and returns the result as a ValueVTs value. This uses
158 /// Chain/Flag as the input and updates them for the output Chain/Flag.
159 /// If the Flag pointer is NULL, no flag is used.
160 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
161 SDValue &Chain, SDValue *Flag) const;
163 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
164 /// specified value into the registers specified by this object. This uses
165 /// Chain/Flag as the input and updates them for the output Chain/Flag.
166 /// If the Flag pointer is NULL, no flag is used.
167 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
168 SDValue &Chain, SDValue *Flag) const;
170 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
171 /// operand list. This adds the code marker, matching input operand index
172 /// (if applicable), and includes the number of values added into it.
173 void AddInlineAsmOperands(unsigned Kind,
174 bool HasMatching, unsigned MatchingIdx,
176 std::vector<SDValue> &Ops) const;
180 /// getCopyFromParts - Create a value that contains the specified legal parts
181 /// combined into the value they represent. If the parts combine to a type
182 /// larger then ValueVT then AssertOp can be used to specify whether the extra
183 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
184 /// (ISD::AssertSext).
185 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
186 const SDValue *Parts,
187 unsigned NumParts, EVT PartVT, EVT ValueVT,
188 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
189 assert(NumParts > 0 && "No parts to assemble!");
190 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
191 SDValue Val = Parts[0];
194 // Assemble the value from multiple parts.
195 if (!ValueVT.isVector() && ValueVT.isInteger()) {
196 unsigned PartBits = PartVT.getSizeInBits();
197 unsigned ValueBits = ValueVT.getSizeInBits();
199 // Assemble the power of 2 part.
200 unsigned RoundParts = NumParts & (NumParts - 1) ?
201 1 << Log2_32(NumParts) : NumParts;
202 unsigned RoundBits = PartBits * RoundParts;
203 EVT RoundVT = RoundBits == ValueBits ?
204 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
207 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
209 if (RoundParts > 2) {
210 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
212 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
213 RoundParts / 2, PartVT, HalfVT);
215 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
216 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
219 if (TLI.isBigEndian())
222 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
224 if (RoundParts < NumParts) {
225 // Assemble the trailing non-power-of-2 part.
226 unsigned OddParts = NumParts - RoundParts;
227 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
228 Hi = getCopyFromParts(DAG, dl,
229 Parts + RoundParts, OddParts, PartVT, OddVT);
231 // Combine the round and odd parts.
233 if (TLI.isBigEndian())
235 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
236 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
237 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
238 DAG.getConstant(Lo.getValueType().getSizeInBits(),
239 TLI.getPointerTy()));
240 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
241 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
243 } else if (ValueVT.isVector()) {
244 // Handle a multi-element vector.
245 EVT IntermediateVT, RegisterVT;
246 unsigned NumIntermediates;
248 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
249 NumIntermediates, RegisterVT);
250 assert(NumRegs == NumParts
251 && "Part count doesn't match vector breakdown!");
252 NumParts = NumRegs; // Silence a compiler warning.
253 assert(RegisterVT == PartVT
254 && "Part type doesn't match vector breakdown!");
255 assert(RegisterVT == Parts[0].getValueType() &&
256 "Part type doesn't match part!");
258 // Assemble the parts into intermediate operands.
259 SmallVector<SDValue, 8> Ops(NumIntermediates);
260 if (NumIntermediates == NumParts) {
261 // If the register was not expanded, truncate or copy the value,
263 for (unsigned i = 0; i != NumParts; ++i)
264 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
265 PartVT, IntermediateVT);
266 } else if (NumParts > 0) {
267 // If the intermediate type was expanded, build the intermediate
268 // operands from the parts.
269 assert(NumParts % NumIntermediates == 0 &&
270 "Must expand into a divisible number of parts!");
271 unsigned Factor = NumParts / NumIntermediates;
272 for (unsigned i = 0; i != NumIntermediates; ++i)
273 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
274 PartVT, IntermediateVT);
277 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
278 // intermediate operands.
279 Val = DAG.getNode(IntermediateVT.isVector() ?
280 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
281 ValueVT, &Ops[0], NumIntermediates);
282 } else if (PartVT.isFloatingPoint()) {
283 // FP split into multiple FP parts (for ppcf128)
284 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
287 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
288 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
289 if (TLI.isBigEndian())
291 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
293 // FP split into integer parts (soft fp)
294 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
295 !PartVT.isVector() && "Unexpected split");
296 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
297 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
301 // There is now one part, held in Val. Correct it to match ValueVT.
302 PartVT = Val.getValueType();
304 if (PartVT == ValueVT)
307 if (PartVT.isVector()) {
308 assert(ValueVT.isVector() && "Unknown vector conversion!");
309 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
312 if (ValueVT.isVector()) {
313 assert(ValueVT.getVectorElementType() == PartVT &&
314 ValueVT.getVectorNumElements() == 1 &&
315 "Only trivial scalar-to-vector conversions should get here!");
316 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
319 if (PartVT.isInteger() &&
320 ValueVT.isInteger()) {
321 if (ValueVT.bitsLT(PartVT)) {
322 // For a truncate, see if we have any information to
323 // indicate whether the truncated bits will always be
324 // zero or sign-extension.
325 if (AssertOp != ISD::DELETED_NODE)
326 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
327 DAG.getValueType(ValueVT));
328 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
330 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
334 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
335 if (ValueVT.bitsLT(Val.getValueType())) {
336 // FP_ROUND's are always exact here.
337 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
338 DAG.getIntPtrConstant(1));
341 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
344 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
345 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
347 llvm_unreachable("Unknown mismatch!");
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
359 EVT PtrVT = TLI.getPointerTy();
360 EVT ValueVT = Val.getValueType();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 if (!ValueVT.isVector()) {
369 if (PartVT == ValueVT) {
370 assert(NumParts == 1 && "No-op copy with multiple parts!");
375 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
376 // If the parts cover more bits than the value has, promote the value.
377 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
378 assert(NumParts == 1 && "Do not know what to promote to!");
379 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
380 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
384 llvm_unreachable("Unknown mismatch!");
386 } else if (PartBits == ValueVT.getSizeInBits()) {
387 // Different types of the same size.
388 assert(NumParts == 1 && PartVT != ValueVT);
389 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
390 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
391 // If the parts cover less bits than value has, truncate the value.
392 if (PartVT.isInteger() && ValueVT.isInteger()) {
393 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
394 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
396 llvm_unreachable("Unknown mismatch!");
400 // The value may have changed - recompute ValueVT.
401 ValueVT = Val.getValueType();
402 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
403 "Failed to tile the value with PartVT!");
406 assert(PartVT == ValueVT && "Type conversion failed!");
411 // Expand the value into multiple parts.
412 if (NumParts & (NumParts - 1)) {
413 // The number of parts is not a power of 2. Split off and copy the tail.
414 assert(PartVT.isInteger() && ValueVT.isInteger() &&
415 "Do not know what to expand to!");
416 unsigned RoundParts = 1 << Log2_32(NumParts);
417 unsigned RoundBits = RoundParts * PartBits;
418 unsigned OddParts = NumParts - RoundParts;
419 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
420 DAG.getConstant(RoundBits,
421 TLI.getPointerTy()));
422 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts,
425 if (TLI.isBigEndian())
426 // The odd parts were reversed by getCopyToParts - unreverse them.
427 std::reverse(Parts + RoundParts, Parts + NumParts);
429 NumParts = RoundParts;
430 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
431 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
434 // The number of parts is a power of 2. Repeatedly bisect the value using
436 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
437 EVT::getIntegerVT(*DAG.getContext(),
438 ValueVT.getSizeInBits()),
441 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
442 for (unsigned i = 0; i < NumParts; i += StepSize) {
443 unsigned ThisBits = StepSize * PartBits / 2;
444 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
445 SDValue &Part0 = Parts[i];
446 SDValue &Part1 = Parts[i+StepSize/2];
448 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
450 DAG.getConstant(1, PtrVT));
451 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
453 DAG.getConstant(0, PtrVT));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
458 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
464 if (TLI.isBigEndian())
465 std::reverse(Parts, Parts + OrigNumParts);
472 if (PartVT != ValueVT) {
473 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
474 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
476 assert(ValueVT.getVectorElementType() == PartVT &&
477 ValueVT.getVectorNumElements() == 1 &&
478 "Only trivial vector-to-scalar conversions should get here!");
479 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
481 DAG.getConstant(0, PtrVT));
489 // Handle a multi-element vector.
490 EVT IntermediateVT, RegisterVT;
491 unsigned NumIntermediates;
492 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
493 IntermediateVT, NumIntermediates, RegisterVT);
494 unsigned NumElements = ValueVT.getVectorNumElements();
496 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
497 NumParts = NumRegs; // Silence a compiler warning.
498 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
500 // Split the vector into intermediate operands.
501 SmallVector<SDValue, 8> Ops(NumIntermediates);
502 for (unsigned i = 0; i != NumIntermediates; ++i) {
503 if (IntermediateVT.isVector())
504 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
506 DAG.getConstant(i * (NumElements / NumIntermediates),
509 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
511 DAG.getConstant(i, PtrVT));
514 // Split the intermediate operands into legal parts.
515 if (NumParts == NumIntermediates) {
516 // If the register was not expanded, promote or copy the value,
518 for (unsigned i = 0; i != NumParts; ++i)
519 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
520 } else if (NumParts > 0) {
521 // If the intermediate type was expanded, split each the value into
523 assert(NumParts % NumIntermediates == 0 &&
524 "Must expand into a divisible number of parts!");
525 unsigned Factor = NumParts / NumIntermediates;
526 for (unsigned i = 0; i != NumIntermediates; ++i)
527 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT);
532 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
535 TD = DAG.getTarget().getTargetData();
538 /// clear - Clear out the current SelectionDAG and the associated
539 /// state and prepare this SelectionDAGBuilder object to be used
540 /// for a new block. This doesn't clear out information about
541 /// additional blocks that are needed to complete switch lowering
542 /// or PHI node updating; that information is cleared out as it is
544 void SelectionDAGBuilder::clear() {
546 PendingLoads.clear();
547 PendingExports.clear();
550 CurDebugLoc = DebugLoc();
554 /// getRoot - Return the current virtual root of the Selection DAG,
555 /// flushing any PendingLoad items. This must be done before emitting
556 /// a store or any other node that may need to be ordered after any
557 /// prior load instructions.
559 SDValue SelectionDAGBuilder::getRoot() {
560 if (PendingLoads.empty())
561 return DAG.getRoot();
563 if (PendingLoads.size() == 1) {
564 SDValue Root = PendingLoads[0];
566 PendingLoads.clear();
570 // Otherwise, we have to make a token factor node.
571 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
572 &PendingLoads[0], PendingLoads.size());
573 PendingLoads.clear();
578 /// getControlRoot - Similar to getRoot, but instead of flushing all the
579 /// PendingLoad items, flush all the PendingExports items. It is necessary
580 /// to do this before emitting a terminator instruction.
582 SDValue SelectionDAGBuilder::getControlRoot() {
583 SDValue Root = DAG.getRoot();
585 if (PendingExports.empty())
588 // Turn all of the CopyToReg chains into one factored node.
589 if (Root.getOpcode() != ISD::EntryToken) {
590 unsigned i = 0, e = PendingExports.size();
591 for (; i != e; ++i) {
592 assert(PendingExports[i].getNode()->getNumOperands() > 1);
593 if (PendingExports[i].getNode()->getOperand(0) == Root)
594 break; // Don't add the root if we already indirectly depend on it.
598 PendingExports.push_back(Root);
601 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
603 PendingExports.size());
604 PendingExports.clear();
609 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
610 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
611 DAG.AssignOrdering(Node, SDNodeOrder);
613 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
614 AssignOrderingToNode(Node->getOperand(I).getNode());
617 void SelectionDAGBuilder::visit(const Instruction &I) {
618 // Set up outgoing PHI node register values before emitting the terminator.
619 if (isa<TerminatorInst>(&I))
620 HandlePHINodesInSuccessorBlocks(I.getParent());
622 CurDebugLoc = I.getDebugLoc();
624 visit(I.getOpcode(), I);
626 if (!isa<TerminatorInst>(&I) && !HasTailCall)
627 CopyToExportRegsIfNeeded(&I);
629 CurDebugLoc = DebugLoc();
632 void SelectionDAGBuilder::visitPHI(const PHINode &) {
633 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
636 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
637 // Note: this doesn't use InstVisitor, because it has to work with
638 // ConstantExpr's in addition to instructions.
640 default: llvm_unreachable("Unknown instruction type encountered!");
641 // Build the switch statement using the Instruction.def file.
642 #define HANDLE_INST(NUM, OPCODE, CLASS) \
643 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
644 #include "llvm/Instruction.def"
647 // Assign the ordering to the freshly created DAG nodes.
648 if (NodeMap.count(&I)) {
650 AssignOrderingToNode(getValue(&I).getNode());
654 SDValue SelectionDAGBuilder::getValue(const Value *V) {
655 SDValue &N = NodeMap[V];
656 if (N.getNode()) return N;
658 if (const Constant *C = dyn_cast<Constant>(V)) {
659 EVT VT = TLI.getValueType(V->getType(), true);
661 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
662 return N = DAG.getConstant(*CI, VT);
664 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
665 return N = DAG.getGlobalAddress(GV, VT);
667 if (isa<ConstantPointerNull>(C))
668 return N = DAG.getConstant(0, TLI.getPointerTy());
670 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
671 return N = DAG.getConstantFP(*CFP, VT);
673 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
674 return N = DAG.getUNDEF(VT);
676 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
677 visit(CE->getOpcode(), *CE);
678 SDValue N1 = NodeMap[V];
679 assert(N1.getNode() && "visit didn't populate the NodeMap!");
683 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
684 SmallVector<SDValue, 4> Constants;
685 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
687 SDNode *Val = getValue(*OI).getNode();
688 // If the operand is an empty aggregate, there are no values.
690 // Add each leaf value from the operand to the Constants list
691 // to form a flattened list of all the values.
692 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
693 Constants.push_back(SDValue(Val, i));
696 return DAG.getMergeValues(&Constants[0], Constants.size(),
700 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
701 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
702 "Unknown struct or array constant!");
704 SmallVector<EVT, 4> ValueVTs;
705 ComputeValueVTs(TLI, C->getType(), ValueVTs);
706 unsigned NumElts = ValueVTs.size();
708 return SDValue(); // empty struct
709 SmallVector<SDValue, 4> Constants(NumElts);
710 for (unsigned i = 0; i != NumElts; ++i) {
711 EVT EltVT = ValueVTs[i];
712 if (isa<UndefValue>(C))
713 Constants[i] = DAG.getUNDEF(EltVT);
714 else if (EltVT.isFloatingPoint())
715 Constants[i] = DAG.getConstantFP(0, EltVT);
717 Constants[i] = DAG.getConstant(0, EltVT);
720 return DAG.getMergeValues(&Constants[0], NumElts,
724 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
725 return DAG.getBlockAddress(BA, VT);
727 const VectorType *VecTy = cast<VectorType>(V->getType());
728 unsigned NumElements = VecTy->getNumElements();
730 // Now that we know the number and type of the elements, get that number of
731 // elements into the Ops array based on what kind of constant it is.
732 SmallVector<SDValue, 16> Ops;
733 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
734 for (unsigned i = 0; i != NumElements; ++i)
735 Ops.push_back(getValue(CP->getOperand(i)));
737 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
738 EVT EltVT = TLI.getValueType(VecTy->getElementType());
741 if (EltVT.isFloatingPoint())
742 Op = DAG.getConstantFP(0, EltVT);
744 Op = DAG.getConstant(0, EltVT);
745 Ops.assign(NumElements, Op);
748 // Create a BUILD_VECTOR node.
749 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
750 VT, &Ops[0], Ops.size());
753 // If this is a static alloca, generate it as the frameindex instead of
755 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
756 DenseMap<const AllocaInst*, int>::iterator SI =
757 FuncInfo.StaticAllocaMap.find(AI);
758 if (SI != FuncInfo.StaticAllocaMap.end())
759 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
762 unsigned InReg = FuncInfo.ValueMap[V];
763 assert(InReg && "Value not in map!");
765 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
766 SDValue Chain = DAG.getEntryNode();
767 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
770 /// Get the EVTs and ArgFlags collections that represent the legalized return
771 /// type of the given function. This does not require a DAG or a return value,
772 /// and is suitable for use before any DAGs for the function are constructed.
773 static void getReturnInfo(const Type* ReturnType,
774 Attributes attr, SmallVectorImpl<EVT> &OutVTs,
775 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
776 const TargetLowering &TLI,
777 SmallVectorImpl<uint64_t> *Offsets = 0) {
778 SmallVector<EVT, 4> ValueVTs;
779 ComputeValueVTs(TLI, ReturnType, ValueVTs);
780 unsigned NumValues = ValueVTs.size();
781 if (NumValues == 0) return;
784 for (unsigned j = 0, f = NumValues; j != f; ++j) {
785 EVT VT = ValueVTs[j];
786 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
788 if (attr & Attribute::SExt)
789 ExtendKind = ISD::SIGN_EXTEND;
790 else if (attr & Attribute::ZExt)
791 ExtendKind = ISD::ZERO_EXTEND;
793 // FIXME: C calling convention requires the return type to be promoted to
794 // at least 32-bit. But this is not necessary for non-C calling
795 // conventions. The frontend should mark functions whose return values
796 // require promoting with signext or zeroext attributes.
797 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
798 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
799 if (VT.bitsLT(MinVT))
803 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
804 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
805 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
806 PartVT.getTypeForEVT(ReturnType->getContext()));
808 // 'inreg' on function refers to return value
809 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
810 if (attr & Attribute::InReg)
813 // Propagate extension type if any
814 if (attr & Attribute::SExt)
816 else if (attr & Attribute::ZExt)
819 for (unsigned i = 0; i < NumParts; ++i) {
820 OutVTs.push_back(PartVT);
821 OutFlags.push_back(Flags);
824 Offsets->push_back(Offset);
831 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
832 SDValue Chain = getControlRoot();
833 SmallVector<ISD::OutputArg, 8> Outs;
834 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
836 if (!FLI.CanLowerReturn) {
837 unsigned DemoteReg = FLI.DemoteRegister;
838 const Function *F = I.getParent()->getParent();
840 // Emit a store of the return value through the virtual register.
841 // Leave Outs empty so that LowerReturn won't try to load return
842 // registers the usual way.
843 SmallVector<EVT, 1> PtrValueVTs;
844 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
847 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
848 SDValue RetOp = getValue(I.getOperand(0));
850 SmallVector<EVT, 4> ValueVTs;
851 SmallVector<uint64_t, 4> Offsets;
852 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
853 unsigned NumValues = ValueVTs.size();
855 SmallVector<SDValue, 4> Chains(NumValues);
856 EVT PtrVT = PtrValueVTs[0];
857 for (unsigned i = 0; i != NumValues; ++i) {
858 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
859 DAG.getConstant(Offsets[i], PtrVT));
861 DAG.getStore(Chain, getCurDebugLoc(),
862 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
863 Add, NULL, Offsets[i], false, false, 0);
866 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
867 MVT::Other, &Chains[0], NumValues);
868 } else if (I.getNumOperands() != 0) {
869 SmallVector<EVT, 4> ValueVTs;
870 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
871 unsigned NumValues = ValueVTs.size();
873 SDValue RetOp = getValue(I.getOperand(0));
874 for (unsigned j = 0, f = NumValues; j != f; ++j) {
875 EVT VT = ValueVTs[j];
877 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
879 const Function *F = I.getParent()->getParent();
880 if (F->paramHasAttr(0, Attribute::SExt))
881 ExtendKind = ISD::SIGN_EXTEND;
882 else if (F->paramHasAttr(0, Attribute::ZExt))
883 ExtendKind = ISD::ZERO_EXTEND;
885 // FIXME: C calling convention requires the return type to be promoted
886 // to at least 32-bit. But this is not necessary for non-C calling
887 // conventions. The frontend should mark functions whose return values
888 // require promoting with signext or zeroext attributes.
889 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
890 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
891 if (VT.bitsLT(MinVT))
895 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
896 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
897 SmallVector<SDValue, 4> Parts(NumParts);
898 getCopyToParts(DAG, getCurDebugLoc(),
899 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
900 &Parts[0], NumParts, PartVT, ExtendKind);
902 // 'inreg' on function refers to return value
903 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
904 if (F->paramHasAttr(0, Attribute::InReg))
907 // Propagate extension type if any
908 if (F->paramHasAttr(0, Attribute::SExt))
910 else if (F->paramHasAttr(0, Attribute::ZExt))
913 for (unsigned i = 0; i < NumParts; ++i)
914 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
919 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
920 CallingConv::ID CallConv =
921 DAG.getMachineFunction().getFunction()->getCallingConv();
922 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
923 Outs, getCurDebugLoc(), DAG);
925 // Verify that the target's LowerReturn behaved as expected.
926 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
927 "LowerReturn didn't return a valid chain!");
929 // Update the DAG with the new chain value resulting from return lowering.
933 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
934 /// created for it, emit nodes to copy the value into the virtual
936 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
937 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
938 if (VMI != FuncInfo.ValueMap.end()) {
939 assert(!V->use_empty() && "Unused value assigned virtual registers!");
940 CopyValueToVirtualRegister(V, VMI->second);
944 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
945 /// the current basic block, add it to ValueMap now so that we'll get a
947 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
948 // No need to export constants.
949 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
952 if (FuncInfo.isExportedInst(V)) return;
954 unsigned Reg = FuncInfo.InitializeRegForValue(V);
955 CopyValueToVirtualRegister(V, Reg);
958 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
959 const BasicBlock *FromBB) {
960 // The operands of the setcc have to be in this block. We don't know
961 // how to export them from some other block.
962 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
963 // Can export from current BB.
964 if (VI->getParent() == FromBB)
967 // Is already exported, noop.
968 return FuncInfo.isExportedInst(V);
971 // If this is an argument, we can export it if the BB is the entry block or
972 // if it is already exported.
973 if (isa<Argument>(V)) {
974 if (FromBB == &FromBB->getParent()->getEntryBlock())
977 // Otherwise, can only export this if it is already exported.
978 return FuncInfo.isExportedInst(V);
981 // Otherwise, constants can always be exported.
985 static bool InBlock(const Value *V, const BasicBlock *BB) {
986 if (const Instruction *I = dyn_cast<Instruction>(V))
987 return I->getParent() == BB;
991 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
992 /// This function emits a branch and is used at the leaves of an OR or an
993 /// AND operator tree.
996 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
997 MachineBasicBlock *TBB,
998 MachineBasicBlock *FBB,
999 MachineBasicBlock *CurBB,
1000 MachineBasicBlock *SwitchBB) {
1001 const BasicBlock *BB = CurBB->getBasicBlock();
1003 // If the leaf of the tree is a comparison, merge the condition into
1005 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1006 // The operands of the cmp have to be in this block. We don't know
1007 // how to export them from some other block. If this is the first block
1008 // of the sequence, no exporting is needed.
1009 if (CurBB == SwitchBB ||
1010 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1011 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1012 ISD::CondCode Condition;
1013 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1014 Condition = getICmpCondCode(IC->getPredicate());
1015 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1016 Condition = getFCmpCondCode(FC->getPredicate());
1018 Condition = ISD::SETEQ; // silence warning.
1019 llvm_unreachable("Unknown compare instruction");
1022 CaseBlock CB(Condition, BOp->getOperand(0),
1023 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1024 SwitchCases.push_back(CB);
1029 // Create a CaseBlock record representing this branch.
1030 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1031 NULL, TBB, FBB, CurBB);
1032 SwitchCases.push_back(CB);
1035 /// FindMergedConditions - If Cond is an expression like
1036 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1037 MachineBasicBlock *TBB,
1038 MachineBasicBlock *FBB,
1039 MachineBasicBlock *CurBB,
1040 MachineBasicBlock *SwitchBB,
1042 // If this node is not part of the or/and tree, emit it as a branch.
1043 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1044 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1045 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1046 BOp->getParent() != CurBB->getBasicBlock() ||
1047 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1048 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1049 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1053 // Create TmpBB after CurBB.
1054 MachineFunction::iterator BBI = CurBB;
1055 MachineFunction &MF = DAG.getMachineFunction();
1056 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1057 CurBB->getParent()->insert(++BBI, TmpBB);
1059 if (Opc == Instruction::Or) {
1060 // Codegen X | Y as:
1068 // Emit the LHS condition.
1069 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1071 // Emit the RHS condition into TmpBB.
1072 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1074 assert(Opc == Instruction::And && "Unknown merge op!");
1075 // Codegen X & Y as:
1082 // This requires creation of TmpBB after CurBB.
1084 // Emit the LHS condition.
1085 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1087 // Emit the RHS condition into TmpBB.
1088 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1092 /// If the set of cases should be emitted as a series of branches, return true.
1093 /// If we should emit this as a bunch of and/or'd together conditions, return
1096 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1097 if (Cases.size() != 2) return true;
1099 // If this is two comparisons of the same values or'd or and'd together, they
1100 // will get folded into a single comparison, so don't emit two blocks.
1101 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1102 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1103 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1104 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1108 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1109 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1110 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1111 Cases[0].CC == Cases[1].CC &&
1112 isa<Constant>(Cases[0].CmpRHS) &&
1113 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1114 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1116 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1123 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1124 MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()];
1126 // Update machine-CFG edges.
1127 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1129 // Figure out which block is immediately after the current one.
1130 MachineBasicBlock *NextBlock = 0;
1131 MachineFunction::iterator BBI = BrMBB;
1132 if (++BBI != FuncInfo.MF->end())
1135 if (I.isUnconditional()) {
1136 // Update machine-CFG edges.
1137 BrMBB->addSuccessor(Succ0MBB);
1139 // If this is not a fall-through branch, emit the branch.
1140 if (Succ0MBB != NextBlock)
1141 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1142 MVT::Other, getControlRoot(),
1143 DAG.getBasicBlock(Succ0MBB)));
1148 // If this condition is one of the special cases we handle, do special stuff
1150 const Value *CondVal = I.getCondition();
1151 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1153 // If this is a series of conditions that are or'd or and'd together, emit
1154 // this as a sequence of branches instead of setcc's with and/or operations.
1155 // For example, instead of something like:
1168 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1169 if (BOp->hasOneUse() &&
1170 (BOp->getOpcode() == Instruction::And ||
1171 BOp->getOpcode() == Instruction::Or)) {
1172 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1174 // If the compares in later blocks need to use values not currently
1175 // exported from this block, export them now. This block should always
1176 // be the first entry.
1177 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1179 // Allow some cases to be rejected.
1180 if (ShouldEmitAsBranches(SwitchCases)) {
1181 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1182 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1183 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1186 // Emit the branch for this block.
1187 visitSwitchCase(SwitchCases[0], BrMBB);
1188 SwitchCases.erase(SwitchCases.begin());
1192 // Okay, we decided not to do this, remove any inserted MBB's and clear
1194 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1195 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1197 SwitchCases.clear();
1201 // Create a CaseBlock record representing this branch.
1202 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1203 NULL, Succ0MBB, Succ1MBB, BrMBB);
1205 // Use visitSwitchCase to actually insert the fast branch sequence for this
1207 visitSwitchCase(CB, BrMBB);
1210 /// visitSwitchCase - Emits the necessary code to represent a single node in
1211 /// the binary search tree resulting from lowering a switch instruction.
1212 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1213 MachineBasicBlock *SwitchBB) {
1215 SDValue CondLHS = getValue(CB.CmpLHS);
1216 DebugLoc dl = getCurDebugLoc();
1218 // Build the setcc now.
1219 if (CB.CmpMHS == NULL) {
1220 // Fold "(X == true)" to X and "(X == false)" to !X to
1221 // handle common cases produced by branch lowering.
1222 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1223 CB.CC == ISD::SETEQ)
1225 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1226 CB.CC == ISD::SETEQ) {
1227 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1228 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1230 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1232 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1234 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1235 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1237 SDValue CmpOp = getValue(CB.CmpMHS);
1238 EVT VT = CmpOp.getValueType();
1240 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1241 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1244 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1245 VT, CmpOp, DAG.getConstant(Low, VT));
1246 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1247 DAG.getConstant(High-Low, VT), ISD::SETULE);
1251 // Update successor info
1252 SwitchBB->addSuccessor(CB.TrueBB);
1253 SwitchBB->addSuccessor(CB.FalseBB);
1255 // Set NextBlock to be the MBB immediately after the current one, if any.
1256 // This is used to avoid emitting unnecessary branches to the next block.
1257 MachineBasicBlock *NextBlock = 0;
1258 MachineFunction::iterator BBI = SwitchBB;
1259 if (++BBI != FuncInfo.MF->end())
1262 // If the lhs block is the next block, invert the condition so that we can
1263 // fall through to the lhs instead of the rhs block.
1264 if (CB.TrueBB == NextBlock) {
1265 std::swap(CB.TrueBB, CB.FalseBB);
1266 SDValue True = DAG.getConstant(1, Cond.getValueType());
1267 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1270 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1271 MVT::Other, getControlRoot(), Cond,
1272 DAG.getBasicBlock(CB.TrueBB));
1274 // If the branch was constant folded, fix up the CFG.
1275 if (BrCond.getOpcode() == ISD::BR) {
1276 SwitchBB->removeSuccessor(CB.FalseBB);
1278 // Otherwise, go ahead and insert the false branch.
1279 if (BrCond == getControlRoot())
1280 SwitchBB->removeSuccessor(CB.TrueBB);
1282 if (CB.FalseBB != NextBlock)
1283 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1284 DAG.getBasicBlock(CB.FalseBB));
1287 DAG.setRoot(BrCond);
1290 /// visitJumpTable - Emit JumpTable node in the current MBB
1291 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1292 // Emit the code for the jump table
1293 assert(JT.Reg != -1U && "Should lower JT Header first!");
1294 EVT PTy = TLI.getPointerTy();
1295 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1297 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1298 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1299 MVT::Other, Index.getValue(1),
1301 DAG.setRoot(BrJumpTable);
1304 /// visitJumpTableHeader - This function emits necessary code to produce index
1305 /// in the JumpTable from switch case.
1306 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1307 JumpTableHeader &JTH,
1308 MachineBasicBlock *SwitchBB) {
1309 // Subtract the lowest switch case value from the value being switched on and
1310 // conditional branch to default mbb if the result is greater than the
1311 // difference between smallest and largest cases.
1312 SDValue SwitchOp = getValue(JTH.SValue);
1313 EVT VT = SwitchOp.getValueType();
1314 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1315 DAG.getConstant(JTH.First, VT));
1317 // The SDNode we just created, which holds the value being switched on minus
1318 // the smallest case value, needs to be copied to a virtual register so it
1319 // can be used as an index into the jump table in a subsequent basic block.
1320 // This value may be smaller or larger than the target's pointer type, and
1321 // therefore require extension or truncating.
1322 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1324 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1325 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1326 JumpTableReg, SwitchOp);
1327 JT.Reg = JumpTableReg;
1329 // Emit the range check for the jump table, and branch to the default block
1330 // for the switch statement if the value being switched on exceeds the largest
1331 // case in the switch.
1332 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1333 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1334 DAG.getConstant(JTH.Last-JTH.First,VT),
1337 // Set NextBlock to be the MBB immediately after the current one, if any.
1338 // This is used to avoid emitting unnecessary branches to the next block.
1339 MachineBasicBlock *NextBlock = 0;
1340 MachineFunction::iterator BBI = SwitchBB;
1342 if (++BBI != FuncInfo.MF->end())
1345 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1346 MVT::Other, CopyTo, CMP,
1347 DAG.getBasicBlock(JT.Default));
1349 if (JT.MBB != NextBlock)
1350 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1351 DAG.getBasicBlock(JT.MBB));
1353 DAG.setRoot(BrCond);
1356 /// visitBitTestHeader - This function emits necessary code to produce value
1357 /// suitable for "bit tests"
1358 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1359 MachineBasicBlock *SwitchBB) {
1360 // Subtract the minimum value
1361 SDValue SwitchOp = getValue(B.SValue);
1362 EVT VT = SwitchOp.getValueType();
1363 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1364 DAG.getConstant(B.First, VT));
1367 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1368 TLI.getSetCCResultType(Sub.getValueType()),
1369 Sub, DAG.getConstant(B.Range, VT),
1372 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1373 TLI.getPointerTy());
1375 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1376 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1379 // Set NextBlock to be the MBB immediately after the current one, if any.
1380 // This is used to avoid emitting unnecessary branches to the next block.
1381 MachineBasicBlock *NextBlock = 0;
1382 MachineFunction::iterator BBI = SwitchBB;
1383 if (++BBI != FuncInfo.MF->end())
1386 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1388 SwitchBB->addSuccessor(B.Default);
1389 SwitchBB->addSuccessor(MBB);
1391 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1392 MVT::Other, CopyTo, RangeCmp,
1393 DAG.getBasicBlock(B.Default));
1395 if (MBB != NextBlock)
1396 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1397 DAG.getBasicBlock(MBB));
1399 DAG.setRoot(BrRange);
1402 /// visitBitTestCase - this function produces one "bit test"
1403 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1406 MachineBasicBlock *SwitchBB) {
1407 // Make desired shift
1408 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1409 TLI.getPointerTy());
1410 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1412 DAG.getConstant(1, TLI.getPointerTy()),
1415 // Emit bit tests and jumps
1416 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1417 TLI.getPointerTy(), SwitchVal,
1418 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1419 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1420 TLI.getSetCCResultType(AndOp.getValueType()),
1421 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1424 SwitchBB->addSuccessor(B.TargetBB);
1425 SwitchBB->addSuccessor(NextMBB);
1427 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1428 MVT::Other, getControlRoot(),
1429 AndCmp, DAG.getBasicBlock(B.TargetBB));
1431 // Set NextBlock to be the MBB immediately after the current one, if any.
1432 // This is used to avoid emitting unnecessary branches to the next block.
1433 MachineBasicBlock *NextBlock = 0;
1434 MachineFunction::iterator BBI = SwitchBB;
1435 if (++BBI != FuncInfo.MF->end())
1438 if (NextMBB != NextBlock)
1439 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1440 DAG.getBasicBlock(NextMBB));
1445 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1446 MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()];
1448 // Retrieve successors.
1449 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1450 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1452 const Value *Callee(I.getCalledValue());
1453 if (isa<InlineAsm>(Callee))
1456 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1458 // If the value of the invoke is used outside of its defining block, make it
1459 // available as a virtual register.
1460 CopyToExportRegsIfNeeded(&I);
1462 // Update successor info
1463 InvokeMBB->addSuccessor(Return);
1464 InvokeMBB->addSuccessor(LandingPad);
1466 // Drop into normal successor.
1467 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1468 MVT::Other, getControlRoot(),
1469 DAG.getBasicBlock(Return)));
1472 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1475 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1476 /// small case ranges).
1477 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1478 CaseRecVector& WorkList,
1480 MachineBasicBlock *Default,
1481 MachineBasicBlock *SwitchBB) {
1482 Case& BackCase = *(CR.Range.second-1);
1484 // Size is the number of Cases represented by this range.
1485 size_t Size = CR.Range.second - CR.Range.first;
1489 // Get the MachineFunction which holds the current MBB. This is used when
1490 // inserting any additional MBBs necessary to represent the switch.
1491 MachineFunction *CurMF = FuncInfo.MF;
1493 // Figure out which block is immediately after the current one.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CR.CaseBB;
1497 if (++BBI != FuncInfo.MF->end())
1500 // TODO: If any two of the cases has the same destination, and if one value
1501 // is the same as the other, but has one bit unset that the other has set,
1502 // use bit manipulation to do two compares at once. For example:
1503 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1505 // Rearrange the case blocks so that the last one falls through if possible.
1506 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1507 // The last case block won't fall through into 'NextBlock' if we emit the
1508 // branches in this order. See if rearranging a case value would help.
1509 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1510 if (I->BB == NextBlock) {
1511 std::swap(*I, BackCase);
1517 // Create a CaseBlock record representing a conditional branch to
1518 // the Case's target mbb if the value being switched on SV is equal
1520 MachineBasicBlock *CurBlock = CR.CaseBB;
1521 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1522 MachineBasicBlock *FallThrough;
1524 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1525 CurMF->insert(BBI, FallThrough);
1527 // Put SV in a virtual register to make it available from the new blocks.
1528 ExportFromCurrentBlock(SV);
1530 // If the last case doesn't match, go to the default block.
1531 FallThrough = Default;
1534 const Value *RHS, *LHS, *MHS;
1536 if (I->High == I->Low) {
1537 // This is just small small case range :) containing exactly 1 case
1539 LHS = SV; RHS = I->High; MHS = NULL;
1542 LHS = I->Low; MHS = SV; RHS = I->High;
1544 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1546 // If emitting the first comparison, just call visitSwitchCase to emit the
1547 // code into the current block. Otherwise, push the CaseBlock onto the
1548 // vector to be later processed by SDISel, and insert the node's MBB
1549 // before the next MBB.
1550 if (CurBlock == SwitchBB)
1551 visitSwitchCase(CB, SwitchBB);
1553 SwitchCases.push_back(CB);
1555 CurBlock = FallThrough;
1561 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1562 return !DisableJumpTables &&
1563 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1564 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1567 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1568 APInt LastExt(Last), FirstExt(First);
1569 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1570 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1571 return (LastExt - FirstExt + 1ULL);
1574 /// handleJTSwitchCase - Emit jumptable for current switch case range
1575 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1576 CaseRecVector& WorkList,
1578 MachineBasicBlock* Default,
1579 MachineBasicBlock *SwitchBB) {
1580 Case& FrontCase = *CR.Range.first;
1581 Case& BackCase = *(CR.Range.second-1);
1583 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1584 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1586 APInt TSize(First.getBitWidth(), 0);
1587 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1591 if (!areJTsAllowed(TLI) || TSize.ult(4))
1594 APInt Range = ComputeRange(First, Last);
1595 double Density = TSize.roundToDouble() / Range.roundToDouble();
1599 DEBUG(dbgs() << "Lowering jump table\n"
1600 << "First entry: " << First << ". Last entry: " << Last << '\n'
1601 << "Range: " << Range
1602 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1604 // Get the MachineFunction which holds the current MBB. This is used when
1605 // inserting any additional MBBs necessary to represent the switch.
1606 MachineFunction *CurMF = FuncInfo.MF;
1608 // Figure out which block is immediately after the current one.
1609 MachineFunction::iterator BBI = CR.CaseBB;
1612 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1614 // Create a new basic block to hold the code for loading the address
1615 // of the jump table, and jumping to it. Update successor information;
1616 // we will either branch to the default case for the switch, or the jump
1618 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1619 CurMF->insert(BBI, JumpTableBB);
1620 CR.CaseBB->addSuccessor(Default);
1621 CR.CaseBB->addSuccessor(JumpTableBB);
1623 // Build a vector of destination BBs, corresponding to each target
1624 // of the jump table. If the value of the jump table slot corresponds to
1625 // a case statement, push the case's BB onto the vector, otherwise, push
1627 std::vector<MachineBasicBlock*> DestBBs;
1629 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1630 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1631 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1633 if (Low.sle(TEI) && TEI.sle(High)) {
1634 DestBBs.push_back(I->BB);
1638 DestBBs.push_back(Default);
1642 // Update successor info. Add one edge to each unique successor.
1643 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1644 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1645 E = DestBBs.end(); I != E; ++I) {
1646 if (!SuccsHandled[(*I)->getNumber()]) {
1647 SuccsHandled[(*I)->getNumber()] = true;
1648 JumpTableBB->addSuccessor(*I);
1652 // Create a jump table index for this jump table.
1653 unsigned JTEncoding = TLI.getJumpTableEncoding();
1654 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1655 ->createJumpTableIndex(DestBBs);
1657 // Set the jump table information so that we can codegen it as a second
1658 // MachineBasicBlock
1659 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1660 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1661 if (CR.CaseBB == SwitchBB)
1662 visitJumpTableHeader(JT, JTH, SwitchBB);
1664 JTCases.push_back(JumpTableBlock(JTH, JT));
1669 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1671 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1672 CaseRecVector& WorkList,
1674 MachineBasicBlock *Default,
1675 MachineBasicBlock *SwitchBB) {
1676 // Get the MachineFunction which holds the current MBB. This is used when
1677 // inserting any additional MBBs necessary to represent the switch.
1678 MachineFunction *CurMF = FuncInfo.MF;
1680 // Figure out which block is immediately after the current one.
1681 MachineFunction::iterator BBI = CR.CaseBB;
1684 Case& FrontCase = *CR.Range.first;
1685 Case& BackCase = *(CR.Range.second-1);
1686 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1688 // Size is the number of Cases represented by this range.
1689 unsigned Size = CR.Range.second - CR.Range.first;
1691 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1692 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1694 CaseItr Pivot = CR.Range.first + Size/2;
1696 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1697 // (heuristically) allow us to emit JumpTable's later.
1698 APInt TSize(First.getBitWidth(), 0);
1699 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1703 APInt LSize = FrontCase.size();
1704 APInt RSize = TSize-LSize;
1705 DEBUG(dbgs() << "Selecting best pivot: \n"
1706 << "First: " << First << ", Last: " << Last <<'\n'
1707 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1708 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1710 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1711 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1712 APInt Range = ComputeRange(LEnd, RBegin);
1713 assert((Range - 2ULL).isNonNegative() &&
1714 "Invalid case distance");
1715 double LDensity = (double)LSize.roundToDouble() /
1716 (LEnd - First + 1ULL).roundToDouble();
1717 double RDensity = (double)RSize.roundToDouble() /
1718 (Last - RBegin + 1ULL).roundToDouble();
1719 double Metric = Range.logBase2()*(LDensity+RDensity);
1720 // Should always split in some non-trivial place
1721 DEBUG(dbgs() <<"=>Step\n"
1722 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1723 << "LDensity: " << LDensity
1724 << ", RDensity: " << RDensity << '\n'
1725 << "Metric: " << Metric << '\n');
1726 if (FMetric < Metric) {
1729 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1735 if (areJTsAllowed(TLI)) {
1736 // If our case is dense we *really* should handle it earlier!
1737 assert((FMetric > 0) && "Should handle dense range earlier!");
1739 Pivot = CR.Range.first + Size/2;
1742 CaseRange LHSR(CR.Range.first, Pivot);
1743 CaseRange RHSR(Pivot, CR.Range.second);
1744 Constant *C = Pivot->Low;
1745 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1747 // We know that we branch to the LHS if the Value being switched on is
1748 // less than the Pivot value, C. We use this to optimize our binary
1749 // tree a bit, by recognizing that if SV is greater than or equal to the
1750 // LHS's Case Value, and that Case Value is exactly one less than the
1751 // Pivot's Value, then we can branch directly to the LHS's Target,
1752 // rather than creating a leaf node for it.
1753 if ((LHSR.second - LHSR.first) == 1 &&
1754 LHSR.first->High == CR.GE &&
1755 cast<ConstantInt>(C)->getValue() ==
1756 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1757 TrueBB = LHSR.first->BB;
1759 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1760 CurMF->insert(BBI, TrueBB);
1761 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1763 // Put SV in a virtual register to make it available from the new blocks.
1764 ExportFromCurrentBlock(SV);
1767 // Similar to the optimization above, if the Value being switched on is
1768 // known to be less than the Constant CR.LT, and the current Case Value
1769 // is CR.LT - 1, then we can branch directly to the target block for
1770 // the current Case Value, rather than emitting a RHS leaf node for it.
1771 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1772 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1773 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1774 FalseBB = RHSR.first->BB;
1776 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1777 CurMF->insert(BBI, FalseBB);
1778 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1780 // Put SV in a virtual register to make it available from the new blocks.
1781 ExportFromCurrentBlock(SV);
1784 // Create a CaseBlock record representing a conditional branch to
1785 // the LHS node if the value being switched on SV is less than C.
1786 // Otherwise, branch to LHS.
1787 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1789 if (CR.CaseBB == SwitchBB)
1790 visitSwitchCase(CB, SwitchBB);
1792 SwitchCases.push_back(CB);
1797 /// handleBitTestsSwitchCase - if current case range has few destination and
1798 /// range span less, than machine word bitwidth, encode case range into series
1799 /// of masks and emit bit tests with these masks.
1800 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1801 CaseRecVector& WorkList,
1803 MachineBasicBlock* Default,
1804 MachineBasicBlock *SwitchBB){
1805 EVT PTy = TLI.getPointerTy();
1806 unsigned IntPtrBits = PTy.getSizeInBits();
1808 Case& FrontCase = *CR.Range.first;
1809 Case& BackCase = *(CR.Range.second-1);
1811 // Get the MachineFunction which holds the current MBB. This is used when
1812 // inserting any additional MBBs necessary to represent the switch.
1813 MachineFunction *CurMF = FuncInfo.MF;
1815 // If target does not have legal shift left, do not emit bit tests at all.
1816 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1820 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1822 // Single case counts one, case range - two.
1823 numCmps += (I->Low == I->High ? 1 : 2);
1826 // Count unique destinations
1827 SmallSet<MachineBasicBlock*, 4> Dests;
1828 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1829 Dests.insert(I->BB);
1830 if (Dests.size() > 3)
1831 // Don't bother the code below, if there are too much unique destinations
1834 DEBUG(dbgs() << "Total number of unique destinations: "
1835 << Dests.size() << '\n'
1836 << "Total number of comparisons: " << numCmps << '\n');
1838 // Compute span of values.
1839 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1840 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1841 APInt cmpRange = maxValue - minValue;
1843 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
1844 << "Low bound: " << minValue << '\n'
1845 << "High bound: " << maxValue << '\n');
1847 if (cmpRange.uge(IntPtrBits) ||
1848 (!(Dests.size() == 1 && numCmps >= 3) &&
1849 !(Dests.size() == 2 && numCmps >= 5) &&
1850 !(Dests.size() >= 3 && numCmps >= 6)))
1853 DEBUG(dbgs() << "Emitting bit tests\n");
1854 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1856 // Optimize the case where all the case values fit in a
1857 // word without having to subtract minValue. In this case,
1858 // we can optimize away the subtraction.
1859 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
1860 cmpRange = maxValue;
1862 lowBound = minValue;
1865 CaseBitsVector CasesBits;
1866 unsigned i, count = 0;
1868 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1869 MachineBasicBlock* Dest = I->BB;
1870 for (i = 0; i < count; ++i)
1871 if (Dest == CasesBits[i].BB)
1875 assert((count < 3) && "Too much destinations to test!");
1876 CasesBits.push_back(CaseBits(0, Dest, 0));
1880 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1881 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1883 uint64_t lo = (lowValue - lowBound).getZExtValue();
1884 uint64_t hi = (highValue - lowBound).getZExtValue();
1886 for (uint64_t j = lo; j <= hi; j++) {
1887 CasesBits[i].Mask |= 1ULL << j;
1888 CasesBits[i].Bits++;
1892 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1896 // Figure out which block is immediately after the current one.
1897 MachineFunction::iterator BBI = CR.CaseBB;
1900 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1902 DEBUG(dbgs() << "Cases:\n");
1903 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1904 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
1905 << ", Bits: " << CasesBits[i].Bits
1906 << ", BB: " << CasesBits[i].BB << '\n');
1908 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1909 CurMF->insert(BBI, CaseBB);
1910 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1914 // Put SV in a virtual register to make it available from the new blocks.
1915 ExportFromCurrentBlock(SV);
1918 BitTestBlock BTB(lowBound, cmpRange, SV,
1919 -1U, (CR.CaseBB == SwitchBB),
1920 CR.CaseBB, Default, BTC);
1922 if (CR.CaseBB == SwitchBB)
1923 visitBitTestHeader(BTB, SwitchBB);
1925 BitTestCases.push_back(BTB);
1930 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1931 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
1932 const SwitchInst& SI) {
1935 // Start with "simple" cases
1936 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1937 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1938 Cases.push_back(Case(SI.getSuccessorValue(i),
1939 SI.getSuccessorValue(i),
1942 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1944 // Merge case into clusters
1945 if (Cases.size() >= 2)
1946 // Must recompute end() each iteration because it may be
1947 // invalidated by erase if we hold on to it
1948 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1949 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1950 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1951 MachineBasicBlock* nextBB = J->BB;
1952 MachineBasicBlock* currentBB = I->BB;
1954 // If the two neighboring cases go to the same destination, merge them
1955 // into a single case.
1956 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
1964 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1965 if (I->Low != I->High)
1966 // A range counts double, since it requires two compares.
1973 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
1974 MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()];
1976 // Figure out which block is immediately after the current one.
1977 MachineBasicBlock *NextBlock = 0;
1978 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1980 // If there is only the default destination, branch to it if it is not the
1981 // next basic block. Otherwise, just fall through.
1982 if (SI.getNumOperands() == 2) {
1983 // Update machine-CFG edges.
1985 // If this is not a fall-through branch, emit the branch.
1986 SwitchMBB->addSuccessor(Default);
1987 if (Default != NextBlock)
1988 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1989 MVT::Other, getControlRoot(),
1990 DAG.getBasicBlock(Default)));
1995 // If there are any non-default case statements, create a vector of Cases
1996 // representing each one, and sort the vector so that we can efficiently
1997 // create a binary search tree from them.
1999 size_t numCmps = Clusterify(Cases, SI);
2000 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2001 << ". Total compares: " << numCmps << '\n');
2004 // Get the Value to be switched on and default basic blocks, which will be
2005 // inserted into CaseBlock records, representing basic blocks in the binary
2007 const Value *SV = SI.getOperand(0);
2009 // Push the initial CaseRec onto the worklist
2010 CaseRecVector WorkList;
2011 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2012 CaseRange(Cases.begin(),Cases.end())));
2014 while (!WorkList.empty()) {
2015 // Grab a record representing a case range to process off the worklist
2016 CaseRec CR = WorkList.back();
2017 WorkList.pop_back();
2019 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2022 // If the range has few cases (two or less) emit a series of specific
2024 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2027 // If the switch has more than 5 blocks, and at least 40% dense, and the
2028 // target supports indirect branches, then emit a jump table rather than
2029 // lowering the switch to a binary tree of conditional branches.
2030 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2033 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2034 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2035 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2039 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2040 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()];
2042 // Update machine-CFG edges with unique successors.
2043 SmallVector<BasicBlock*, 32> succs;
2044 succs.reserve(I.getNumSuccessors());
2045 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2046 succs.push_back(I.getSuccessor(i));
2047 array_pod_sort(succs.begin(), succs.end());
2048 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2049 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2050 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2052 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2053 MVT::Other, getControlRoot(),
2054 getValue(I.getAddress())));
2057 void SelectionDAGBuilder::visitFSub(const User &I) {
2058 // -0.0 - X --> fneg
2059 const Type *Ty = I.getType();
2060 if (Ty->isVectorTy()) {
2061 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2062 const VectorType *DestTy = cast<VectorType>(I.getType());
2063 const Type *ElTy = DestTy->getElementType();
2064 unsigned VL = DestTy->getNumElements();
2065 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2066 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2068 SDValue Op2 = getValue(I.getOperand(1));
2069 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2070 Op2.getValueType(), Op2));
2076 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2077 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2078 SDValue Op2 = getValue(I.getOperand(1));
2079 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2080 Op2.getValueType(), Op2));
2084 visitBinary(I, ISD::FSUB);
2087 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2088 SDValue Op1 = getValue(I.getOperand(0));
2089 SDValue Op2 = getValue(I.getOperand(1));
2090 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2091 Op1.getValueType(), Op1, Op2));
2094 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2095 SDValue Op1 = getValue(I.getOperand(0));
2096 SDValue Op2 = getValue(I.getOperand(1));
2097 if (!I.getType()->isVectorTy() &&
2098 Op2.getValueType() != TLI.getShiftAmountTy()) {
2099 // If the operand is smaller than the shift count type, promote it.
2100 EVT PTy = TLI.getPointerTy();
2101 EVT STy = TLI.getShiftAmountTy();
2102 if (STy.bitsGT(Op2.getValueType()))
2103 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2104 TLI.getShiftAmountTy(), Op2);
2105 // If the operand is larger than the shift count type but the shift
2106 // count type has enough bits to represent any shift value, truncate
2107 // it now. This is a common case and it exposes the truncate to
2108 // optimization early.
2109 else if (STy.getSizeInBits() >=
2110 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2111 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2112 TLI.getShiftAmountTy(), Op2);
2113 // Otherwise we'll need to temporarily settle for some other
2114 // convenient type; type legalization will make adjustments as
2116 else if (PTy.bitsLT(Op2.getValueType()))
2117 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2118 TLI.getPointerTy(), Op2);
2119 else if (PTy.bitsGT(Op2.getValueType()))
2120 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2121 TLI.getPointerTy(), Op2);
2124 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2125 Op1.getValueType(), Op1, Op2));
2128 void SelectionDAGBuilder::visitICmp(const User &I) {
2129 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2130 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2131 predicate = IC->getPredicate();
2132 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2133 predicate = ICmpInst::Predicate(IC->getPredicate());
2134 SDValue Op1 = getValue(I.getOperand(0));
2135 SDValue Op2 = getValue(I.getOperand(1));
2136 ISD::CondCode Opcode = getICmpCondCode(predicate);
2138 EVT DestVT = TLI.getValueType(I.getType());
2139 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2142 void SelectionDAGBuilder::visitFCmp(const User &I) {
2143 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2144 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2145 predicate = FC->getPredicate();
2146 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2147 predicate = FCmpInst::Predicate(FC->getPredicate());
2148 SDValue Op1 = getValue(I.getOperand(0));
2149 SDValue Op2 = getValue(I.getOperand(1));
2150 ISD::CondCode Condition = getFCmpCondCode(predicate);
2151 EVT DestVT = TLI.getValueType(I.getType());
2152 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2155 void SelectionDAGBuilder::visitSelect(const User &I) {
2156 SmallVector<EVT, 4> ValueVTs;
2157 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2158 unsigned NumValues = ValueVTs.size();
2159 if (NumValues == 0) return;
2161 SmallVector<SDValue, 4> Values(NumValues);
2162 SDValue Cond = getValue(I.getOperand(0));
2163 SDValue TrueVal = getValue(I.getOperand(1));
2164 SDValue FalseVal = getValue(I.getOperand(2));
2166 for (unsigned i = 0; i != NumValues; ++i)
2167 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2168 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2170 SDValue(TrueVal.getNode(),
2171 TrueVal.getResNo() + i),
2172 SDValue(FalseVal.getNode(),
2173 FalseVal.getResNo() + i));
2175 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2176 DAG.getVTList(&ValueVTs[0], NumValues),
2177 &Values[0], NumValues));
2180 void SelectionDAGBuilder::visitTrunc(const User &I) {
2181 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2182 SDValue N = getValue(I.getOperand(0));
2183 EVT DestVT = TLI.getValueType(I.getType());
2184 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2187 void SelectionDAGBuilder::visitZExt(const User &I) {
2188 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2189 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2190 SDValue N = getValue(I.getOperand(0));
2191 EVT DestVT = TLI.getValueType(I.getType());
2192 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2195 void SelectionDAGBuilder::visitSExt(const User &I) {
2196 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2197 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2198 SDValue N = getValue(I.getOperand(0));
2199 EVT DestVT = TLI.getValueType(I.getType());
2200 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2203 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2204 // FPTrunc is never a no-op cast, no need to check
2205 SDValue N = getValue(I.getOperand(0));
2206 EVT DestVT = TLI.getValueType(I.getType());
2207 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2208 DestVT, N, DAG.getIntPtrConstant(0)));
2211 void SelectionDAGBuilder::visitFPExt(const User &I){
2212 // FPTrunc is never a no-op cast, no need to check
2213 SDValue N = getValue(I.getOperand(0));
2214 EVT DestVT = TLI.getValueType(I.getType());
2215 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2218 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2219 // FPToUI is never a no-op cast, no need to check
2220 SDValue N = getValue(I.getOperand(0));
2221 EVT DestVT = TLI.getValueType(I.getType());
2222 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2225 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2226 // FPToSI is never a no-op cast, no need to check
2227 SDValue N = getValue(I.getOperand(0));
2228 EVT DestVT = TLI.getValueType(I.getType());
2229 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2232 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2233 // UIToFP is never a no-op cast, no need to check
2234 SDValue N = getValue(I.getOperand(0));
2235 EVT DestVT = TLI.getValueType(I.getType());
2236 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2239 void SelectionDAGBuilder::visitSIToFP(const User &I){
2240 // SIToFP is never a no-op cast, no need to check
2241 SDValue N = getValue(I.getOperand(0));
2242 EVT DestVT = TLI.getValueType(I.getType());
2243 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2246 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2247 // What to do depends on the size of the integer and the size of the pointer.
2248 // We can either truncate, zero extend, or no-op, accordingly.
2249 SDValue N = getValue(I.getOperand(0));
2250 EVT SrcVT = N.getValueType();
2251 EVT DestVT = TLI.getValueType(I.getType());
2252 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2255 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2256 // What to do depends on the size of the integer and the size of the pointer.
2257 // We can either truncate, zero extend, or no-op, accordingly.
2258 SDValue N = getValue(I.getOperand(0));
2259 EVT SrcVT = N.getValueType();
2260 EVT DestVT = TLI.getValueType(I.getType());
2261 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2264 void SelectionDAGBuilder::visitBitCast(const User &I) {
2265 SDValue N = getValue(I.getOperand(0));
2266 EVT DestVT = TLI.getValueType(I.getType());
2268 // BitCast assures us that source and destination are the same size so this is
2269 // either a BIT_CONVERT or a no-op.
2270 if (DestVT != N.getValueType())
2271 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2272 DestVT, N)); // convert types.
2274 setValue(&I, N); // noop cast.
2277 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2278 SDValue InVec = getValue(I.getOperand(0));
2279 SDValue InVal = getValue(I.getOperand(1));
2280 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2282 getValue(I.getOperand(2)));
2283 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2284 TLI.getValueType(I.getType()),
2285 InVec, InVal, InIdx));
2288 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2289 SDValue InVec = getValue(I.getOperand(0));
2290 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2292 getValue(I.getOperand(1)));
2293 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2294 TLI.getValueType(I.getType()), InVec, InIdx));
2297 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2298 // from SIndx and increasing to the element length (undefs are allowed).
2299 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2300 unsigned MaskNumElts = Mask.size();
2301 for (unsigned i = 0; i != MaskNumElts; ++i)
2302 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2307 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2308 SmallVector<int, 8> Mask;
2309 SDValue Src1 = getValue(I.getOperand(0));
2310 SDValue Src2 = getValue(I.getOperand(1));
2312 // Convert the ConstantVector mask operand into an array of ints, with -1
2313 // representing undef values.
2314 SmallVector<Constant*, 8> MaskElts;
2315 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2316 unsigned MaskNumElts = MaskElts.size();
2317 for (unsigned i = 0; i != MaskNumElts; ++i) {
2318 if (isa<UndefValue>(MaskElts[i]))
2321 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2324 EVT VT = TLI.getValueType(I.getType());
2325 EVT SrcVT = Src1.getValueType();
2326 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2328 if (SrcNumElts == MaskNumElts) {
2329 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2334 // Normalize the shuffle vector since mask and vector length don't match.
2335 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2336 // Mask is longer than the source vectors and is a multiple of the source
2337 // vectors. We can use concatenate vector to make the mask and vectors
2339 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2340 // The shuffle is concatenating two vectors together.
2341 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2346 // Pad both vectors with undefs to make them the same length as the mask.
2347 unsigned NumConcat = MaskNumElts / SrcNumElts;
2348 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2349 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2350 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2352 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2353 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2357 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2358 getCurDebugLoc(), VT,
2359 &MOps1[0], NumConcat);
2360 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2361 getCurDebugLoc(), VT,
2362 &MOps2[0], NumConcat);
2364 // Readjust mask for new input vector length.
2365 SmallVector<int, 8> MappedOps;
2366 for (unsigned i = 0; i != MaskNumElts; ++i) {
2368 if (Idx < (int)SrcNumElts)
2369 MappedOps.push_back(Idx);
2371 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2374 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2379 if (SrcNumElts > MaskNumElts) {
2380 // Analyze the access pattern of the vector to see if we can extract
2381 // two subvectors and do the shuffle. The analysis is done by calculating
2382 // the range of elements the mask access on both vectors.
2383 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2384 int MaxRange[2] = {-1, -1};
2386 for (unsigned i = 0; i != MaskNumElts; ++i) {
2392 if (Idx >= (int)SrcNumElts) {
2396 if (Idx > MaxRange[Input])
2397 MaxRange[Input] = Idx;
2398 if (Idx < MinRange[Input])
2399 MinRange[Input] = Idx;
2402 // Check if the access is smaller than the vector size and can we find
2403 // a reasonable extract index.
2404 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2406 int StartIdx[2]; // StartIdx to extract from
2407 for (int Input=0; Input < 2; ++Input) {
2408 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2409 RangeUse[Input] = 0; // Unused
2410 StartIdx[Input] = 0;
2411 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2412 // Fits within range but we should see if we can find a good
2413 // start index that is a multiple of the mask length.
2414 if (MaxRange[Input] < (int)MaskNumElts) {
2415 RangeUse[Input] = 1; // Extract from beginning of the vector
2416 StartIdx[Input] = 0;
2418 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2419 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2420 StartIdx[Input] + MaskNumElts < SrcNumElts)
2421 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2426 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2427 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2430 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2431 // Extract appropriate subvector and generate a vector shuffle
2432 for (int Input=0; Input < 2; ++Input) {
2433 SDValue &Src = Input == 0 ? Src1 : Src2;
2434 if (RangeUse[Input] == 0)
2435 Src = DAG.getUNDEF(VT);
2437 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2438 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2441 // Calculate new mask.
2442 SmallVector<int, 8> MappedOps;
2443 for (unsigned i = 0; i != MaskNumElts; ++i) {
2446 MappedOps.push_back(Idx);
2447 else if (Idx < (int)SrcNumElts)
2448 MappedOps.push_back(Idx - StartIdx[0]);
2450 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2453 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2459 // We can't use either concat vectors or extract subvectors so fall back to
2460 // replacing the shuffle with extract and build vector.
2461 // to insert and build vector.
2462 EVT EltVT = VT.getVectorElementType();
2463 EVT PtrVT = TLI.getPointerTy();
2464 SmallVector<SDValue,8> Ops;
2465 for (unsigned i = 0; i != MaskNumElts; ++i) {
2467 Ops.push_back(DAG.getUNDEF(EltVT));
2472 if (Idx < (int)SrcNumElts)
2473 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2474 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2476 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2478 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2484 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2485 VT, &Ops[0], Ops.size()));
2488 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2489 const Value *Op0 = I.getOperand(0);
2490 const Value *Op1 = I.getOperand(1);
2491 const Type *AggTy = I.getType();
2492 const Type *ValTy = Op1->getType();
2493 bool IntoUndef = isa<UndefValue>(Op0);
2494 bool FromUndef = isa<UndefValue>(Op1);
2496 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2497 I.idx_begin(), I.idx_end());
2499 SmallVector<EVT, 4> AggValueVTs;
2500 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2501 SmallVector<EVT, 4> ValValueVTs;
2502 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2504 unsigned NumAggValues = AggValueVTs.size();
2505 unsigned NumValValues = ValValueVTs.size();
2506 SmallVector<SDValue, 4> Values(NumAggValues);
2508 SDValue Agg = getValue(Op0);
2509 SDValue Val = getValue(Op1);
2511 // Copy the beginning value(s) from the original aggregate.
2512 for (; i != LinearIndex; ++i)
2513 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2514 SDValue(Agg.getNode(), Agg.getResNo() + i);
2515 // Copy values from the inserted value(s).
2516 for (; i != LinearIndex + NumValValues; ++i)
2517 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2518 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2519 // Copy remaining value(s) from the original aggregate.
2520 for (; i != NumAggValues; ++i)
2521 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2522 SDValue(Agg.getNode(), Agg.getResNo() + i);
2524 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2525 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2526 &Values[0], NumAggValues));
2529 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2530 const Value *Op0 = I.getOperand(0);
2531 const Type *AggTy = Op0->getType();
2532 const Type *ValTy = I.getType();
2533 bool OutOfUndef = isa<UndefValue>(Op0);
2535 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2536 I.idx_begin(), I.idx_end());
2538 SmallVector<EVT, 4> ValValueVTs;
2539 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2541 unsigned NumValValues = ValValueVTs.size();
2542 SmallVector<SDValue, 4> Values(NumValValues);
2544 SDValue Agg = getValue(Op0);
2545 // Copy out the selected value(s).
2546 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2547 Values[i - LinearIndex] =
2549 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2550 SDValue(Agg.getNode(), Agg.getResNo() + i);
2552 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2553 DAG.getVTList(&ValValueVTs[0], NumValValues),
2554 &Values[0], NumValValues));
2557 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2558 SDValue N = getValue(I.getOperand(0));
2559 const Type *Ty = I.getOperand(0)->getType();
2561 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2563 const Value *Idx = *OI;
2564 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2565 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2568 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2569 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2570 DAG.getIntPtrConstant(Offset));
2573 Ty = StTy->getElementType(Field);
2574 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) {
2575 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2577 // Offset canonically 0 for unions, but type changes
2578 Ty = UnTy->getElementType(Field);
2580 Ty = cast<SequentialType>(Ty)->getElementType();
2582 // If this is a constant subscript, handle it quickly.
2583 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2584 if (CI->getZExtValue() == 0) continue;
2586 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2588 EVT PTy = TLI.getPointerTy();
2589 unsigned PtrBits = PTy.getSizeInBits();
2591 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2593 DAG.getConstant(Offs, MVT::i64));
2595 OffsVal = DAG.getIntPtrConstant(Offs);
2597 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2602 // N = N + Idx * ElementSize;
2603 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2604 TD->getTypeAllocSize(Ty));
2605 SDValue IdxN = getValue(Idx);
2607 // If the index is smaller or larger than intptr_t, truncate or extend
2609 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2611 // If this is a multiply by a power of two, turn it into a shl
2612 // immediately. This is a very common case.
2613 if (ElementSize != 1) {
2614 if (ElementSize.isPowerOf2()) {
2615 unsigned Amt = ElementSize.logBase2();
2616 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2617 N.getValueType(), IdxN,
2618 DAG.getConstant(Amt, TLI.getPointerTy()));
2620 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2621 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2622 N.getValueType(), IdxN, Scale);
2626 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2627 N.getValueType(), N, IdxN);
2634 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2635 // If this is a fixed sized alloca in the entry block of the function,
2636 // allocate it statically on the stack.
2637 if (FuncInfo.StaticAllocaMap.count(&I))
2638 return; // getValue will auto-populate this.
2640 const Type *Ty = I.getAllocatedType();
2641 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2643 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2646 SDValue AllocSize = getValue(I.getArraySize());
2648 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2650 DAG.getConstant(TySize, AllocSize.getValueType()));
2652 EVT IntPtr = TLI.getPointerTy();
2653 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2655 // Handle alignment. If the requested alignment is less than or equal to
2656 // the stack alignment, ignore it. If the size is greater than or equal to
2657 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2658 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2659 if (Align <= StackAlign)
2662 // Round the size of the allocation up to the stack alignment size
2663 // by add SA-1 to the size.
2664 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2665 AllocSize.getValueType(), AllocSize,
2666 DAG.getIntPtrConstant(StackAlign-1));
2668 // Mask out the low bits for alignment purposes.
2669 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2670 AllocSize.getValueType(), AllocSize,
2671 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2673 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2674 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2675 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2678 DAG.setRoot(DSA.getValue(1));
2680 // Inform the Frame Information that we have just allocated a variable-sized
2682 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2685 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2686 const Value *SV = I.getOperand(0);
2687 SDValue Ptr = getValue(SV);
2689 const Type *Ty = I.getType();
2691 bool isVolatile = I.isVolatile();
2692 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2693 unsigned Alignment = I.getAlignment();
2695 SmallVector<EVT, 4> ValueVTs;
2696 SmallVector<uint64_t, 4> Offsets;
2697 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2698 unsigned NumValues = ValueVTs.size();
2703 bool ConstantMemory = false;
2705 // Serialize volatile loads with other side effects.
2707 else if (AA->pointsToConstantMemory(SV)) {
2708 // Do not serialize (non-volatile) loads of constant memory with anything.
2709 Root = DAG.getEntryNode();
2710 ConstantMemory = true;
2712 // Do not serialize non-volatile loads against each other.
2713 Root = DAG.getRoot();
2716 SmallVector<SDValue, 4> Values(NumValues);
2717 SmallVector<SDValue, 4> Chains(NumValues);
2718 EVT PtrVT = Ptr.getValueType();
2719 for (unsigned i = 0; i != NumValues; ++i) {
2720 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2722 DAG.getConstant(Offsets[i], PtrVT));
2723 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2724 A, SV, Offsets[i], isVolatile,
2725 isNonTemporal, Alignment);
2728 Chains[i] = L.getValue(1);
2731 if (!ConstantMemory) {
2732 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2733 MVT::Other, &Chains[0], NumValues);
2737 PendingLoads.push_back(Chain);
2740 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2741 DAG.getVTList(&ValueVTs[0], NumValues),
2742 &Values[0], NumValues));
2745 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2746 const Value *SrcV = I.getOperand(0);
2747 const Value *PtrV = I.getOperand(1);
2749 SmallVector<EVT, 4> ValueVTs;
2750 SmallVector<uint64_t, 4> Offsets;
2751 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2752 unsigned NumValues = ValueVTs.size();
2756 // Get the lowered operands. Note that we do this after
2757 // checking if NumResults is zero, because with zero results
2758 // the operands won't have values in the map.
2759 SDValue Src = getValue(SrcV);
2760 SDValue Ptr = getValue(PtrV);
2762 SDValue Root = getRoot();
2763 SmallVector<SDValue, 4> Chains(NumValues);
2764 EVT PtrVT = Ptr.getValueType();
2765 bool isVolatile = I.isVolatile();
2766 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2767 unsigned Alignment = I.getAlignment();
2769 for (unsigned i = 0; i != NumValues; ++i) {
2770 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
2771 DAG.getConstant(Offsets[i], PtrVT));
2772 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2773 SDValue(Src.getNode(), Src.getResNo() + i),
2774 Add, PtrV, Offsets[i], isVolatile,
2775 isNonTemporal, Alignment);
2778 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2779 MVT::Other, &Chains[0], NumValues));
2782 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2784 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
2785 unsigned Intrinsic) {
2786 bool HasChain = !I.doesNotAccessMemory();
2787 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2789 // Build the operand list.
2790 SmallVector<SDValue, 8> Ops;
2791 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2793 // We don't need to serialize loads against other loads.
2794 Ops.push_back(DAG.getRoot());
2796 Ops.push_back(getRoot());
2800 // Info is set by getTgtMemInstrinsic
2801 TargetLowering::IntrinsicInfo Info;
2802 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2804 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2805 if (!IsTgtIntrinsic)
2806 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2808 // Add all operands of the call to the operand list.
2809 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2810 SDValue Op = getValue(I.getOperand(i));
2811 assert(TLI.isTypeLegal(Op.getValueType()) &&
2812 "Intrinsic uses a non-legal type?");
2816 SmallVector<EVT, 4> ValueVTs;
2817 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2819 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2820 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2821 "Intrinsic uses a non-legal type?");
2826 ValueVTs.push_back(MVT::Other);
2828 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2832 if (IsTgtIntrinsic) {
2833 // This is target intrinsic that touches memory
2834 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2835 VTs, &Ops[0], Ops.size(),
2836 Info.memVT, Info.ptrVal, Info.offset,
2837 Info.align, Info.vol,
2838 Info.readMem, Info.writeMem);
2839 } else if (!HasChain) {
2840 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2841 VTs, &Ops[0], Ops.size());
2842 } else if (!I.getType()->isVoidTy()) {
2843 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2844 VTs, &Ops[0], Ops.size());
2846 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2847 VTs, &Ops[0], Ops.size());
2851 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2853 PendingLoads.push_back(Chain);
2858 if (!I.getType()->isVoidTy()) {
2859 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2860 EVT VT = TLI.getValueType(PTy);
2861 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2864 setValue(&I, Result);
2868 /// GetSignificand - Get the significand and build it into a floating-point
2869 /// number with exponent of 1:
2871 /// Op = (Op & 0x007fffff) | 0x3f800000;
2873 /// where Op is the hexidecimal representation of floating point value.
2875 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
2876 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2877 DAG.getConstant(0x007fffff, MVT::i32));
2878 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
2879 DAG.getConstant(0x3f800000, MVT::i32));
2880 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
2883 /// GetExponent - Get the exponent:
2885 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
2887 /// where Op is the hexidecimal representation of floating point value.
2889 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
2891 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2892 DAG.getConstant(0x7f800000, MVT::i32));
2893 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
2894 DAG.getConstant(23, TLI.getPointerTy()));
2895 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
2896 DAG.getConstant(127, MVT::i32));
2897 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
2900 /// getF32Constant - Get 32-bit floating point constant.
2902 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2903 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2906 /// Inlined utility function to implement binary input atomic intrinsics for
2907 /// visitIntrinsicCall: I is a call instruction
2908 /// Op is the associated NodeType for I
2910 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
2912 SDValue Root = getRoot();
2914 DAG.getAtomic(Op, getCurDebugLoc(),
2915 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
2917 getValue(I.getOperand(1)),
2918 getValue(I.getOperand(2)),
2921 DAG.setRoot(L.getValue(1));
2925 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
2927 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
2928 SDValue Op1 = getValue(I.getOperand(1));
2929 SDValue Op2 = getValue(I.getOperand(2));
2931 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
2932 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
2936 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2937 /// limited-precision mode.
2939 SelectionDAGBuilder::visitExp(const CallInst &I) {
2941 DebugLoc dl = getCurDebugLoc();
2943 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2944 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2945 SDValue Op = getValue(I.getOperand(1));
2947 // Put the exponent in the right bit position for later addition to the
2950 // #define LOG2OFe 1.4426950f
2951 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2952 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
2953 getF32Constant(DAG, 0x3fb8aa3b));
2954 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
2956 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2957 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
2958 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
2960 // IntegerPartOfX <<= 23;
2961 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
2962 DAG.getConstant(23, TLI.getPointerTy()));
2964 if (LimitFloatPrecision <= 6) {
2965 // For floating-point precision of 6:
2967 // TwoToFractionalPartOfX =
2969 // (0.735607626f + 0.252464424f * x) * x;
2971 // error 0.0144103317, which is 6 bits
2972 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2973 getF32Constant(DAG, 0x3e814304));
2974 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2975 getF32Constant(DAG, 0x3f3c50c8));
2976 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2977 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2978 getF32Constant(DAG, 0x3f7f5e7e));
2979 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
2981 // Add the exponent into the result in integer domain.
2982 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2983 TwoToFracPartOfX, IntegerPartOfX);
2985 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
2986 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2987 // For floating-point precision of 12:
2989 // TwoToFractionalPartOfX =
2992 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2994 // 0.000107046256 error, which is 13 to 14 bits
2995 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2996 getF32Constant(DAG, 0x3da235e3));
2997 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2998 getF32Constant(DAG, 0x3e65b8f3));
2999 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3000 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3001 getF32Constant(DAG, 0x3f324b07));
3002 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3003 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3004 getF32Constant(DAG, 0x3f7ff8fd));
3005 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3007 // Add the exponent into the result in integer domain.
3008 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3009 TwoToFracPartOfX, IntegerPartOfX);
3011 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3012 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3013 // For floating-point precision of 18:
3015 // TwoToFractionalPartOfX =
3019 // (0.554906021e-1f +
3020 // (0.961591928e-2f +
3021 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3023 // error 2.47208000*10^(-7), which is better than 18 bits
3024 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3025 getF32Constant(DAG, 0x3924b03e));
3026 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3027 getF32Constant(DAG, 0x3ab24b87));
3028 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3029 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3030 getF32Constant(DAG, 0x3c1d8c17));
3031 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3032 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3033 getF32Constant(DAG, 0x3d634a1d));
3034 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3035 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3036 getF32Constant(DAG, 0x3e75fe14));
3037 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3038 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3039 getF32Constant(DAG, 0x3f317234));
3040 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3041 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3042 getF32Constant(DAG, 0x3f800000));
3043 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3046 // Add the exponent into the result in integer domain.
3047 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3048 TwoToFracPartOfX, IntegerPartOfX);
3050 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3053 // No special expansion.
3054 result = DAG.getNode(ISD::FEXP, dl,
3055 getValue(I.getOperand(1)).getValueType(),
3056 getValue(I.getOperand(1)));
3059 setValue(&I, result);
3062 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3063 /// limited-precision mode.
3065 SelectionDAGBuilder::visitLog(const CallInst &I) {
3067 DebugLoc dl = getCurDebugLoc();
3069 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3070 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3071 SDValue Op = getValue(I.getOperand(1));
3072 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3074 // Scale the exponent by log(2) [0.69314718f].
3075 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3076 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3077 getF32Constant(DAG, 0x3f317218));
3079 // Get the significand and build it into a floating-point number with
3081 SDValue X = GetSignificand(DAG, Op1, dl);
3083 if (LimitFloatPrecision <= 6) {
3084 // For floating-point precision of 6:
3088 // (1.4034025f - 0.23903021f * x) * x;
3090 // error 0.0034276066, which is better than 8 bits
3091 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3092 getF32Constant(DAG, 0xbe74c456));
3093 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3094 getF32Constant(DAG, 0x3fb3a2b1));
3095 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3096 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3097 getF32Constant(DAG, 0x3f949a29));
3099 result = DAG.getNode(ISD::FADD, dl,
3100 MVT::f32, LogOfExponent, LogOfMantissa);
3101 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3102 // For floating-point precision of 12:
3108 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3110 // error 0.000061011436, which is 14 bits
3111 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3112 getF32Constant(DAG, 0xbd67b6d6));
3113 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3114 getF32Constant(DAG, 0x3ee4f4b8));
3115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3116 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3117 getF32Constant(DAG, 0x3fbc278b));
3118 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3119 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3120 getF32Constant(DAG, 0x40348e95));
3121 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3122 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3123 getF32Constant(DAG, 0x3fdef31a));
3125 result = DAG.getNode(ISD::FADD, dl,
3126 MVT::f32, LogOfExponent, LogOfMantissa);
3127 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3128 // For floating-point precision of 18:
3136 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3138 // error 0.0000023660568, which is better than 18 bits
3139 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3140 getF32Constant(DAG, 0xbc91e5ac));
3141 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3142 getF32Constant(DAG, 0x3e4350aa));
3143 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3144 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3145 getF32Constant(DAG, 0x3f60d3e3));
3146 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3147 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3148 getF32Constant(DAG, 0x4011cdf0));
3149 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3150 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3151 getF32Constant(DAG, 0x406cfd1c));
3152 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3153 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3154 getF32Constant(DAG, 0x408797cb));
3155 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3156 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3157 getF32Constant(DAG, 0x4006dcab));
3159 result = DAG.getNode(ISD::FADD, dl,
3160 MVT::f32, LogOfExponent, LogOfMantissa);
3163 // No special expansion.
3164 result = DAG.getNode(ISD::FLOG, dl,
3165 getValue(I.getOperand(1)).getValueType(),
3166 getValue(I.getOperand(1)));
3169 setValue(&I, result);
3172 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3173 /// limited-precision mode.
3175 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3177 DebugLoc dl = getCurDebugLoc();
3179 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3180 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3181 SDValue Op = getValue(I.getOperand(1));
3182 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3184 // Get the exponent.
3185 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3187 // Get the significand and build it into a floating-point number with
3189 SDValue X = GetSignificand(DAG, Op1, dl);
3191 // Different possible minimax approximations of significand in
3192 // floating-point for various degrees of accuracy over [1,2].
3193 if (LimitFloatPrecision <= 6) {
3194 // For floating-point precision of 6:
3196 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3198 // error 0.0049451742, which is more than 7 bits
3199 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3200 getF32Constant(DAG, 0xbeb08fe0));
3201 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3202 getF32Constant(DAG, 0x40019463));
3203 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3204 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3205 getF32Constant(DAG, 0x3fd6633d));
3207 result = DAG.getNode(ISD::FADD, dl,
3208 MVT::f32, LogOfExponent, Log2ofMantissa);
3209 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3210 // For floating-point precision of 12:
3216 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3218 // error 0.0000876136000, which is better than 13 bits
3219 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3220 getF32Constant(DAG, 0xbda7262e));
3221 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3222 getF32Constant(DAG, 0x3f25280b));
3223 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3224 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3225 getF32Constant(DAG, 0x4007b923));
3226 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3227 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3228 getF32Constant(DAG, 0x40823e2f));
3229 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3230 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3231 getF32Constant(DAG, 0x4020d29c));
3233 result = DAG.getNode(ISD::FADD, dl,
3234 MVT::f32, LogOfExponent, Log2ofMantissa);
3235 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3236 // For floating-point precision of 18:
3245 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3247 // error 0.0000018516, which is better than 18 bits
3248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3249 getF32Constant(DAG, 0xbcd2769e));
3250 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3251 getF32Constant(DAG, 0x3e8ce0b9));
3252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3253 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3254 getF32Constant(DAG, 0x3fa22ae7));
3255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3257 getF32Constant(DAG, 0x40525723));
3258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3259 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3260 getF32Constant(DAG, 0x40aaf200));
3261 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3262 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3263 getF32Constant(DAG, 0x40c39dad));
3264 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3265 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3266 getF32Constant(DAG, 0x4042902c));
3268 result = DAG.getNode(ISD::FADD, dl,
3269 MVT::f32, LogOfExponent, Log2ofMantissa);
3272 // No special expansion.
3273 result = DAG.getNode(ISD::FLOG2, dl,
3274 getValue(I.getOperand(1)).getValueType(),
3275 getValue(I.getOperand(1)));
3278 setValue(&I, result);
3281 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3282 /// limited-precision mode.
3284 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3286 DebugLoc dl = getCurDebugLoc();
3288 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3289 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3290 SDValue Op = getValue(I.getOperand(1));
3291 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3293 // Scale the exponent by log10(2) [0.30102999f].
3294 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3295 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3296 getF32Constant(DAG, 0x3e9a209a));
3298 // Get the significand and build it into a floating-point number with
3300 SDValue X = GetSignificand(DAG, Op1, dl);
3302 if (LimitFloatPrecision <= 6) {
3303 // For floating-point precision of 6:
3305 // Log10ofMantissa =
3307 // (0.60948995f - 0.10380950f * x) * x;
3309 // error 0.0014886165, which is 6 bits
3310 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3311 getF32Constant(DAG, 0xbdd49a13));
3312 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3313 getF32Constant(DAG, 0x3f1c0789));
3314 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3315 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3316 getF32Constant(DAG, 0x3f011300));
3318 result = DAG.getNode(ISD::FADD, dl,
3319 MVT::f32, LogOfExponent, Log10ofMantissa);
3320 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3321 // For floating-point precision of 12:
3323 // Log10ofMantissa =
3326 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3328 // error 0.00019228036, which is better than 12 bits
3329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3330 getF32Constant(DAG, 0x3d431f31));
3331 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3332 getF32Constant(DAG, 0x3ea21fb2));
3333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3334 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3335 getF32Constant(DAG, 0x3f6ae232));
3336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3337 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3338 getF32Constant(DAG, 0x3f25f7c3));
3340 result = DAG.getNode(ISD::FADD, dl,
3341 MVT::f32, LogOfExponent, Log10ofMantissa);
3342 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3343 // For floating-point precision of 18:
3345 // Log10ofMantissa =
3350 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3352 // error 0.0000037995730, which is better than 18 bits
3353 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3354 getF32Constant(DAG, 0x3c5d51ce));
3355 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3356 getF32Constant(DAG, 0x3e00685a));
3357 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3358 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3359 getF32Constant(DAG, 0x3efb6798));
3360 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3361 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3362 getF32Constant(DAG, 0x3f88d192));
3363 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3364 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3365 getF32Constant(DAG, 0x3fc4316c));
3366 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3367 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3368 getF32Constant(DAG, 0x3f57ce70));
3370 result = DAG.getNode(ISD::FADD, dl,
3371 MVT::f32, LogOfExponent, Log10ofMantissa);
3374 // No special expansion.
3375 result = DAG.getNode(ISD::FLOG10, dl,
3376 getValue(I.getOperand(1)).getValueType(),
3377 getValue(I.getOperand(1)));
3380 setValue(&I, result);
3383 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3384 /// limited-precision mode.
3386 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3388 DebugLoc dl = getCurDebugLoc();
3390 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3391 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3392 SDValue Op = getValue(I.getOperand(1));
3394 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3396 // FractionalPartOfX = x - (float)IntegerPartOfX;
3397 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3398 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3400 // IntegerPartOfX <<= 23;
3401 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3402 DAG.getConstant(23, TLI.getPointerTy()));
3404 if (LimitFloatPrecision <= 6) {
3405 // For floating-point precision of 6:
3407 // TwoToFractionalPartOfX =
3409 // (0.735607626f + 0.252464424f * x) * x;
3411 // error 0.0144103317, which is 6 bits
3412 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3413 getF32Constant(DAG, 0x3e814304));
3414 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3415 getF32Constant(DAG, 0x3f3c50c8));
3416 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3417 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3418 getF32Constant(DAG, 0x3f7f5e7e));
3419 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3420 SDValue TwoToFractionalPartOfX =
3421 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3423 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3424 MVT::f32, TwoToFractionalPartOfX);
3425 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3426 // For floating-point precision of 12:
3428 // TwoToFractionalPartOfX =
3431 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3433 // error 0.000107046256, which is 13 to 14 bits
3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3435 getF32Constant(DAG, 0x3da235e3));
3436 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3437 getF32Constant(DAG, 0x3e65b8f3));
3438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3439 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3440 getF32Constant(DAG, 0x3f324b07));
3441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3442 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3443 getF32Constant(DAG, 0x3f7ff8fd));
3444 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3445 SDValue TwoToFractionalPartOfX =
3446 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3448 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3449 MVT::f32, TwoToFractionalPartOfX);
3450 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3451 // For floating-point precision of 18:
3453 // TwoToFractionalPartOfX =
3457 // (0.554906021e-1f +
3458 // (0.961591928e-2f +
3459 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3460 // error 2.47208000*10^(-7), which is better than 18 bits
3461 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3462 getF32Constant(DAG, 0x3924b03e));
3463 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3464 getF32Constant(DAG, 0x3ab24b87));
3465 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3466 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3467 getF32Constant(DAG, 0x3c1d8c17));
3468 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3469 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3470 getF32Constant(DAG, 0x3d634a1d));
3471 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3472 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3473 getF32Constant(DAG, 0x3e75fe14));
3474 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3475 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3476 getF32Constant(DAG, 0x3f317234));
3477 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3478 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3479 getF32Constant(DAG, 0x3f800000));
3480 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3481 SDValue TwoToFractionalPartOfX =
3482 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3484 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3485 MVT::f32, TwoToFractionalPartOfX);
3488 // No special expansion.
3489 result = DAG.getNode(ISD::FEXP2, dl,
3490 getValue(I.getOperand(1)).getValueType(),
3491 getValue(I.getOperand(1)));
3494 setValue(&I, result);
3497 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3498 /// limited-precision mode with x == 10.0f.
3500 SelectionDAGBuilder::visitPow(const CallInst &I) {
3502 const Value *Val = I.getOperand(1);
3503 DebugLoc dl = getCurDebugLoc();
3504 bool IsExp10 = false;
3506 if (getValue(Val).getValueType() == MVT::f32 &&
3507 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3508 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3509 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3510 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3512 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3517 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3518 SDValue Op = getValue(I.getOperand(2));
3520 // Put the exponent in the right bit position for later addition to the
3523 // #define LOG2OF10 3.3219281f
3524 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3525 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3526 getF32Constant(DAG, 0x40549a78));
3527 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3529 // FractionalPartOfX = x - (float)IntegerPartOfX;
3530 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3531 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3533 // IntegerPartOfX <<= 23;
3534 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3535 DAG.getConstant(23, TLI.getPointerTy()));
3537 if (LimitFloatPrecision <= 6) {
3538 // For floating-point precision of 6:
3540 // twoToFractionalPartOfX =
3542 // (0.735607626f + 0.252464424f * x) * x;
3544 // error 0.0144103317, which is 6 bits
3545 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3546 getF32Constant(DAG, 0x3e814304));
3547 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3548 getF32Constant(DAG, 0x3f3c50c8));
3549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3550 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3551 getF32Constant(DAG, 0x3f7f5e7e));
3552 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3553 SDValue TwoToFractionalPartOfX =
3554 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3556 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3557 MVT::f32, TwoToFractionalPartOfX);
3558 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3559 // For floating-point precision of 12:
3561 // TwoToFractionalPartOfX =
3564 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3566 // error 0.000107046256, which is 13 to 14 bits
3567 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3568 getF32Constant(DAG, 0x3da235e3));
3569 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3570 getF32Constant(DAG, 0x3e65b8f3));
3571 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3572 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3573 getF32Constant(DAG, 0x3f324b07));
3574 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3575 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3576 getF32Constant(DAG, 0x3f7ff8fd));
3577 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3578 SDValue TwoToFractionalPartOfX =
3579 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3581 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3582 MVT::f32, TwoToFractionalPartOfX);
3583 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3584 // For floating-point precision of 18:
3586 // TwoToFractionalPartOfX =
3590 // (0.554906021e-1f +
3591 // (0.961591928e-2f +
3592 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3593 // error 2.47208000*10^(-7), which is better than 18 bits
3594 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3595 getF32Constant(DAG, 0x3924b03e));
3596 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3597 getF32Constant(DAG, 0x3ab24b87));
3598 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3599 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3600 getF32Constant(DAG, 0x3c1d8c17));
3601 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3602 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3603 getF32Constant(DAG, 0x3d634a1d));
3604 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3605 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3606 getF32Constant(DAG, 0x3e75fe14));
3607 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3608 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3609 getF32Constant(DAG, 0x3f317234));
3610 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3611 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3612 getF32Constant(DAG, 0x3f800000));
3613 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3614 SDValue TwoToFractionalPartOfX =
3615 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3617 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3618 MVT::f32, TwoToFractionalPartOfX);
3621 // No special expansion.
3622 result = DAG.getNode(ISD::FPOW, dl,
3623 getValue(I.getOperand(1)).getValueType(),
3624 getValue(I.getOperand(1)),
3625 getValue(I.getOperand(2)));
3628 setValue(&I, result);
3632 /// ExpandPowI - Expand a llvm.powi intrinsic.
3633 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3634 SelectionDAG &DAG) {
3635 // If RHS is a constant, we can expand this out to a multiplication tree,
3636 // otherwise we end up lowering to a call to __powidf2 (for example). When
3637 // optimizing for size, we only want to do this if the expansion would produce
3638 // a small number of multiplies, otherwise we do the full expansion.
3639 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3640 // Get the exponent as a positive value.
3641 unsigned Val = RHSC->getSExtValue();
3642 if ((int)Val < 0) Val = -Val;
3644 // powi(x, 0) -> 1.0
3646 return DAG.getConstantFP(1.0, LHS.getValueType());
3648 const Function *F = DAG.getMachineFunction().getFunction();
3649 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3650 // If optimizing for size, don't insert too many multiplies. This
3651 // inserts up to 5 multiplies.
3652 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3653 // We use the simple binary decomposition method to generate the multiply
3654 // sequence. There are more optimal ways to do this (for example,
3655 // powi(x,15) generates one more multiply than it should), but this has
3656 // the benefit of being both really simple and much better than a libcall.
3657 SDValue Res; // Logically starts equal to 1.0
3658 SDValue CurSquare = LHS;
3662 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3664 Res = CurSquare; // 1.0*CurSquare.
3667 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3668 CurSquare, CurSquare);
3672 // If the original was negative, invert the result, producing 1/(x*x*x).
3673 if (RHSC->getSExtValue() < 0)
3674 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3675 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3680 // Otherwise, expand to a libcall.
3681 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3685 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3686 /// we want to emit this as a call to a named external function, return the name
3687 /// otherwise lower it and return null.
3689 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3690 DebugLoc dl = getCurDebugLoc();
3693 switch (Intrinsic) {
3695 // By default, turn this into a target intrinsic node.
3696 visitTargetIntrinsic(I, Intrinsic);
3698 case Intrinsic::vastart: visitVAStart(I); return 0;
3699 case Intrinsic::vaend: visitVAEnd(I); return 0;
3700 case Intrinsic::vacopy: visitVACopy(I); return 0;
3701 case Intrinsic::returnaddress:
3702 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3703 getValue(I.getOperand(1))));
3705 case Intrinsic::frameaddress:
3706 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3707 getValue(I.getOperand(1))));
3709 case Intrinsic::setjmp:
3710 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3711 case Intrinsic::longjmp:
3712 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3713 case Intrinsic::memcpy: {
3714 // Assert for address < 256 since we support only user defined address
3716 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3718 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3720 "Unknown address space");
3721 SDValue Op1 = getValue(I.getOperand(1));
3722 SDValue Op2 = getValue(I.getOperand(2));
3723 SDValue Op3 = getValue(I.getOperand(3));
3724 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3725 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3726 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
3727 I.getOperand(1), 0, I.getOperand(2), 0));
3730 case Intrinsic::memset: {
3731 // Assert for address < 256 since we support only user defined address
3733 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3735 "Unknown address space");
3736 SDValue Op1 = getValue(I.getOperand(1));
3737 SDValue Op2 = getValue(I.getOperand(2));
3738 SDValue Op3 = getValue(I.getOperand(3));
3739 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3740 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3741 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3742 I.getOperand(1), 0));
3745 case Intrinsic::memmove: {
3746 // Assert for address < 256 since we support only user defined address
3748 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3750 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3752 "Unknown address space");
3753 SDValue Op1 = getValue(I.getOperand(1));
3754 SDValue Op2 = getValue(I.getOperand(2));
3755 SDValue Op3 = getValue(I.getOperand(3));
3756 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3757 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3759 // If the source and destination are known to not be aliases, we can
3760 // lower memmove as memcpy.
3761 uint64_t Size = -1ULL;
3762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3763 Size = C->getZExtValue();
3764 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3765 AliasAnalysis::NoAlias) {
3766 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3767 false, I.getOperand(1), 0, I.getOperand(2), 0));
3771 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3772 I.getOperand(1), 0, I.getOperand(2), 0));
3775 case Intrinsic::dbg_declare: {
3776 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3777 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3780 MDNode *Variable = DI.getVariable();
3781 // Parameters are handled specially.
3782 bool isParameter = false;
3783 ConstantInt *CI = dyn_cast_or_null<ConstantInt>(Variable->getOperand(0));
3785 unsigned Val = CI->getZExtValue();
3786 unsigned Tag = Val & ~LLVMDebugVersionMask;
3787 if (Tag == dwarf::DW_TAG_arg_variable)
3790 const Value *Address = DI.getAddress();
3793 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3794 Address = BCI->getOperand(0);
3795 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3797 // Don't handle byval arguments or VLAs, for example.
3798 // Non-byval arguments are handled here (they refer to the stack temporary
3799 // alloca at this point).
3800 DenseMap<const AllocaInst*, int>::iterator SI =
3801 FuncInfo.StaticAllocaMap.find(AI);
3802 if (SI == FuncInfo.StaticAllocaMap.end())
3804 int FI = SI->second;
3806 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3807 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3808 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3811 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
3812 // but do not always have a corresponding SDNode built. The SDNodeOrder
3813 // absolute, but not relative, values are different depending on whether
3814 // debug info exists.
3816 SDValue &N = NodeMap[Address];
3819 if (isParameter && !AI) {
3820 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
3822 // Byval parameter. We have a frame index at this point.
3823 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
3824 0, dl, SDNodeOrder);
3826 // Can't do anything with other non-AI cases yet. This might be a
3827 // parameter of a callee function that got inlined, for example.
3830 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
3831 0, dl, SDNodeOrder);
3833 // Can't do anything with other non-AI cases yet.
3835 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
3837 // This isn't useful, but it shows what we're missing.
3838 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
3839 0, dl, SDNodeOrder);
3840 DAG.AddDbgValue(SDV, 0, isParameter);
3844 case Intrinsic::dbg_value: {
3845 const DbgValueInst &DI = cast<DbgValueInst>(I);
3846 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3849 MDNode *Variable = DI.getVariable();
3850 uint64_t Offset = DI.getOffset();
3851 const Value *V = DI.getValue();
3855 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
3856 // but do not always have a corresponding SDNode built. The SDNodeOrder
3857 // absolute, but not relative, values are different depending on whether
3858 // debug info exists.
3861 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
3862 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
3863 DAG.AddDbgValue(SDV, 0, false);
3865 SDValue &N = NodeMap[V];
3867 SDV = DAG.getDbgValue(Variable, N.getNode(),
3868 N.getResNo(), Offset, dl, SDNodeOrder);
3869 DAG.AddDbgValue(SDV, N.getNode(), false);
3871 // We may expand this to cover more cases. One case where we have no
3872 // data available is an unreferenced parameter; we need this fallback.
3873 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
3874 Offset, dl, SDNodeOrder);
3875 DAG.AddDbgValue(SDV, 0, false);
3879 // Build a debug info table entry.
3880 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
3881 V = BCI->getOperand(0);
3882 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
3883 // Don't handle byval struct arguments or VLAs, for example.
3886 DenseMap<const AllocaInst*, int>::iterator SI =
3887 FuncInfo.StaticAllocaMap.find(AI);
3888 if (SI == FuncInfo.StaticAllocaMap.end())
3890 int FI = SI->second;
3892 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3893 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3894 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3897 case Intrinsic::eh_exception: {
3898 // Insert the EXCEPTIONADDR instruction.
3899 assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
3900 "Call to eh.exception not in landing pad!");
3901 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3903 Ops[0] = DAG.getRoot();
3904 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3906 DAG.setRoot(Op.getValue(1));
3910 case Intrinsic::eh_selector: {
3911 MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()];
3912 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3913 if (CallMBB->isLandingPad())
3914 AddCatchInfo(I, &MMI, CallMBB);
3917 FuncInfo.CatchInfoLost.insert(&I);
3919 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3920 unsigned Reg = TLI.getExceptionSelectorRegister();
3921 if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg);
3924 // Insert the EHSELECTION instruction.
3925 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3927 Ops[0] = getValue(I.getOperand(1));
3929 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3930 DAG.setRoot(Op.getValue(1));
3931 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
3935 case Intrinsic::eh_typeid_for: {
3936 // Find the type id for the given typeinfo.
3937 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3938 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
3939 Res = DAG.getConstant(TypeID, MVT::i32);
3944 case Intrinsic::eh_return_i32:
3945 case Intrinsic::eh_return_i64:
3946 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
3947 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3950 getValue(I.getOperand(1)),
3951 getValue(I.getOperand(2))));
3953 case Intrinsic::eh_unwind_init:
3954 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
3956 case Intrinsic::eh_dwarf_cfa: {
3957 EVT VT = getValue(I.getOperand(1)).getValueType();
3958 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
3959 TLI.getPointerTy());
3960 SDValue Offset = DAG.getNode(ISD::ADD, dl,
3962 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
3963 TLI.getPointerTy()),
3965 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
3967 DAG.getConstant(0, TLI.getPointerTy()));
3968 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
3972 case Intrinsic::eh_sjlj_callsite: {
3973 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3974 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
3975 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
3976 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
3978 MMI.setCurrentCallSite(CI->getZExtValue());
3982 case Intrinsic::convertff:
3983 case Intrinsic::convertfsi:
3984 case Intrinsic::convertfui:
3985 case Intrinsic::convertsif:
3986 case Intrinsic::convertuif:
3987 case Intrinsic::convertss:
3988 case Intrinsic::convertsu:
3989 case Intrinsic::convertus:
3990 case Intrinsic::convertuu: {
3991 ISD::CvtCode Code = ISD::CVT_INVALID;
3992 switch (Intrinsic) {
3993 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
3994 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
3995 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
3996 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
3997 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
3998 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
3999 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4000 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4001 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4003 EVT DestVT = TLI.getValueType(I.getType());
4004 const Value *Op1 = I.getOperand(1);
4005 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4006 DAG.getValueType(DestVT),
4007 DAG.getValueType(getValue(Op1).getValueType()),
4008 getValue(I.getOperand(2)),
4009 getValue(I.getOperand(3)),
4014 case Intrinsic::sqrt:
4015 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4016 getValue(I.getOperand(1)).getValueType(),
4017 getValue(I.getOperand(1))));
4019 case Intrinsic::powi:
4020 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)),
4021 getValue(I.getOperand(2)), DAG));
4023 case Intrinsic::sin:
4024 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4025 getValue(I.getOperand(1)).getValueType(),
4026 getValue(I.getOperand(1))));
4028 case Intrinsic::cos:
4029 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4030 getValue(I.getOperand(1)).getValueType(),
4031 getValue(I.getOperand(1))));
4033 case Intrinsic::log:
4036 case Intrinsic::log2:
4039 case Intrinsic::log10:
4042 case Intrinsic::exp:
4045 case Intrinsic::exp2:
4048 case Intrinsic::pow:
4051 case Intrinsic::convert_to_fp16:
4052 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4053 MVT::i16, getValue(I.getOperand(1))));
4055 case Intrinsic::convert_from_fp16:
4056 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4057 MVT::f32, getValue(I.getOperand(1))));
4059 case Intrinsic::pcmarker: {
4060 SDValue Tmp = getValue(I.getOperand(1));
4061 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4064 case Intrinsic::readcyclecounter: {
4065 SDValue Op = getRoot();
4066 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4067 DAG.getVTList(MVT::i64, MVT::Other),
4070 DAG.setRoot(Res.getValue(1));
4073 case Intrinsic::bswap:
4074 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4075 getValue(I.getOperand(1)).getValueType(),
4076 getValue(I.getOperand(1))));
4078 case Intrinsic::cttz: {
4079 SDValue Arg = getValue(I.getOperand(1));
4080 EVT Ty = Arg.getValueType();
4081 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4084 case Intrinsic::ctlz: {
4085 SDValue Arg = getValue(I.getOperand(1));
4086 EVT Ty = Arg.getValueType();
4087 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4090 case Intrinsic::ctpop: {
4091 SDValue Arg = getValue(I.getOperand(1));
4092 EVT Ty = Arg.getValueType();
4093 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4096 case Intrinsic::stacksave: {
4097 SDValue Op = getRoot();
4098 Res = DAG.getNode(ISD::STACKSAVE, dl,
4099 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4101 DAG.setRoot(Res.getValue(1));
4104 case Intrinsic::stackrestore: {
4105 Res = getValue(I.getOperand(1));
4106 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4109 case Intrinsic::stackprotector: {
4110 // Emit code into the DAG to store the stack guard onto the stack.
4111 MachineFunction &MF = DAG.getMachineFunction();
4112 MachineFrameInfo *MFI = MF.getFrameInfo();
4113 EVT PtrTy = TLI.getPointerTy();
4115 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4116 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4118 int FI = FuncInfo.StaticAllocaMap[Slot];
4119 MFI->setStackProtectorIndex(FI);
4121 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4123 // Store the stack protector onto the stack.
4124 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4125 PseudoSourceValue::getFixedStack(FI),
4131 case Intrinsic::objectsize: {
4132 // If we don't know by now, we're never going to know.
4133 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4135 assert(CI && "Non-constant type in __builtin_object_size?");
4137 SDValue Arg = getValue(I.getOperand(0));
4138 EVT Ty = Arg.getValueType();
4140 if (CI->getZExtValue() == 0)
4141 Res = DAG.getConstant(-1ULL, Ty);
4143 Res = DAG.getConstant(0, Ty);
4148 case Intrinsic::var_annotation:
4149 // Discard annotate attributes
4152 case Intrinsic::init_trampoline: {
4153 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4157 Ops[1] = getValue(I.getOperand(1));
4158 Ops[2] = getValue(I.getOperand(2));
4159 Ops[3] = getValue(I.getOperand(3));
4160 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4161 Ops[5] = DAG.getSrcValue(F);
4163 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4164 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4168 DAG.setRoot(Res.getValue(1));
4171 case Intrinsic::gcroot:
4173 const Value *Alloca = I.getOperand(1);
4174 const Constant *TypeMap = cast<Constant>(I.getOperand(2));
4176 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4177 GFI->addStackRoot(FI->getIndex(), TypeMap);
4180 case Intrinsic::gcread:
4181 case Intrinsic::gcwrite:
4182 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4184 case Intrinsic::flt_rounds:
4185 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4187 case Intrinsic::trap:
4188 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4190 case Intrinsic::uadd_with_overflow:
4191 return implVisitAluOverflow(I, ISD::UADDO);
4192 case Intrinsic::sadd_with_overflow:
4193 return implVisitAluOverflow(I, ISD::SADDO);
4194 case Intrinsic::usub_with_overflow:
4195 return implVisitAluOverflow(I, ISD::USUBO);
4196 case Intrinsic::ssub_with_overflow:
4197 return implVisitAluOverflow(I, ISD::SSUBO);
4198 case Intrinsic::umul_with_overflow:
4199 return implVisitAluOverflow(I, ISD::UMULO);
4200 case Intrinsic::smul_with_overflow:
4201 return implVisitAluOverflow(I, ISD::SMULO);
4203 case Intrinsic::prefetch: {
4206 Ops[1] = getValue(I.getOperand(1));
4207 Ops[2] = getValue(I.getOperand(2));
4208 Ops[3] = getValue(I.getOperand(3));
4209 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4213 case Intrinsic::memory_barrier: {
4216 for (int x = 1; x < 6; ++x)
4217 Ops[x] = getValue(I.getOperand(x));
4219 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4222 case Intrinsic::atomic_cmp_swap: {
4223 SDValue Root = getRoot();
4225 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4226 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4228 getValue(I.getOperand(1)),
4229 getValue(I.getOperand(2)),
4230 getValue(I.getOperand(3)),
4233 DAG.setRoot(L.getValue(1));
4236 case Intrinsic::atomic_load_add:
4237 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4238 case Intrinsic::atomic_load_sub:
4239 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4240 case Intrinsic::atomic_load_or:
4241 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4242 case Intrinsic::atomic_load_xor:
4243 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4244 case Intrinsic::atomic_load_and:
4245 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4246 case Intrinsic::atomic_load_nand:
4247 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4248 case Intrinsic::atomic_load_max:
4249 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4250 case Intrinsic::atomic_load_min:
4251 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4252 case Intrinsic::atomic_load_umin:
4253 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4254 case Intrinsic::atomic_load_umax:
4255 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4256 case Intrinsic::atomic_swap:
4257 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4259 case Intrinsic::invariant_start:
4260 case Intrinsic::lifetime_start:
4261 // Discard region information.
4262 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4264 case Intrinsic::invariant_end:
4265 case Intrinsic::lifetime_end:
4266 // Discard region information.
4271 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4273 MachineBasicBlock *LandingPad) {
4274 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4275 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4276 const Type *RetTy = FTy->getReturnType();
4277 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4278 MCSymbol *BeginLabel = 0;
4280 TargetLowering::ArgListTy Args;
4281 TargetLowering::ArgListEntry Entry;
4282 Args.reserve(CS.arg_size());
4284 // Check whether the function can return without sret-demotion.
4285 SmallVector<EVT, 4> OutVTs;
4286 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4287 SmallVector<uint64_t, 4> Offsets;
4288 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4289 OutVTs, OutsFlags, TLI, &Offsets);
4291 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4292 FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4294 SDValue DemoteStackSlot;
4296 if (!CanLowerReturn) {
4297 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4298 FTy->getReturnType());
4299 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4300 FTy->getReturnType());
4301 MachineFunction &MF = DAG.getMachineFunction();
4302 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4303 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4305 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4306 Entry.Node = DemoteStackSlot;
4307 Entry.Ty = StackSlotPtrType;
4308 Entry.isSExt = false;
4309 Entry.isZExt = false;
4310 Entry.isInReg = false;
4311 Entry.isSRet = true;
4312 Entry.isNest = false;
4313 Entry.isByVal = false;
4314 Entry.Alignment = Align;
4315 Args.push_back(Entry);
4316 RetTy = Type::getVoidTy(FTy->getContext());
4319 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4321 SDValue ArgNode = getValue(*i);
4322 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4324 unsigned attrInd = i - CS.arg_begin() + 1;
4325 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4326 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4327 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4328 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4329 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4330 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4331 Entry.Alignment = CS.getParamAlignment(attrInd);
4332 Args.push_back(Entry);
4336 // Insert a label before the invoke call to mark the try range. This can be
4337 // used to detect deletion of the invoke via the MachineModuleInfo.
4338 BeginLabel = MMI.getContext().CreateTempSymbol();
4340 // For SjLj, keep track of which landing pads go with which invokes
4341 // so as to maintain the ordering of pads in the LSDA.
4342 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4343 if (CallSiteIndex) {
4344 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4345 // Now that the call site is handled, stop tracking it.
4346 MMI.setCurrentCallSite(0);
4349 // Both PendingLoads and PendingExports must be flushed here;
4350 // this call might not return.
4352 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4355 // Check if target-independent constraints permit a tail call here.
4356 // Target-dependent constraints are checked within TLI.LowerCallTo.
4358 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4361 std::pair<SDValue,SDValue> Result =
4362 TLI.LowerCallTo(getRoot(), RetTy,
4363 CS.paramHasAttr(0, Attribute::SExt),
4364 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4365 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4366 CS.getCallingConv(),
4368 !CS.getInstruction()->use_empty(),
4369 Callee, Args, DAG, getCurDebugLoc());
4370 assert((isTailCall || Result.second.getNode()) &&
4371 "Non-null chain expected with non-tail call!");
4372 assert((Result.second.getNode() || !Result.first.getNode()) &&
4373 "Null value expected with tail call!");
4374 if (Result.first.getNode()) {
4375 setValue(CS.getInstruction(), Result.first);
4376 } else if (!CanLowerReturn && Result.second.getNode()) {
4377 // The instruction result is the result of loading from the
4378 // hidden sret parameter.
4379 SmallVector<EVT, 1> PVTs;
4380 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4382 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4383 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4384 EVT PtrVT = PVTs[0];
4385 unsigned NumValues = OutVTs.size();
4386 SmallVector<SDValue, 4> Values(NumValues);
4387 SmallVector<SDValue, 4> Chains(NumValues);
4389 for (unsigned i = 0; i < NumValues; ++i) {
4390 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4392 DAG.getConstant(Offsets[i], PtrVT));
4393 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4394 Add, NULL, Offsets[i], false, false, 1);
4396 Chains[i] = L.getValue(1);
4399 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4400 MVT::Other, &Chains[0], NumValues);
4401 PendingLoads.push_back(Chain);
4403 // Collect the legal value parts into potentially illegal values
4404 // that correspond to the original function's return values.
4405 SmallVector<EVT, 4> RetTys;
4406 RetTy = FTy->getReturnType();
4407 ComputeValueVTs(TLI, RetTy, RetTys);
4408 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4409 SmallVector<SDValue, 4> ReturnValues;
4410 unsigned CurReg = 0;
4411 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4413 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4414 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4416 SDValue ReturnValue =
4417 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4418 RegisterVT, VT, AssertOp);
4419 ReturnValues.push_back(ReturnValue);
4423 setValue(CS.getInstruction(),
4424 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4425 DAG.getVTList(&RetTys[0], RetTys.size()),
4426 &ReturnValues[0], ReturnValues.size()));
4430 // As a special case, a null chain means that a tail call has been emitted and
4431 // the DAG root is already updated.
4432 if (Result.second.getNode())
4433 DAG.setRoot(Result.second);
4438 // Insert a label at the end of the invoke call to mark the try range. This
4439 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4440 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4441 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4443 // Inform MachineModuleInfo of range.
4444 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4448 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4449 /// value is equal or not-equal to zero.
4450 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4451 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4453 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4454 if (IC->isEquality())
4455 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4456 if (C->isNullValue())
4458 // Unknown instruction.
4464 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4466 SelectionDAGBuilder &Builder) {
4468 // Check to see if this load can be trivially constant folded, e.g. if the
4469 // input is from a string literal.
4470 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4471 // Cast pointer to the type we really want to load.
4472 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4473 PointerType::getUnqual(LoadTy));
4475 if (const Constant *LoadCst =
4476 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4478 return Builder.getValue(LoadCst);
4481 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4482 // still constant memory, the input chain can be the entry node.
4484 bool ConstantMemory = false;
4486 // Do not serialize (non-volatile) loads of constant memory with anything.
4487 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4488 Root = Builder.DAG.getEntryNode();
4489 ConstantMemory = true;
4491 // Do not serialize non-volatile loads against each other.
4492 Root = Builder.DAG.getRoot();
4495 SDValue Ptr = Builder.getValue(PtrVal);
4496 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4497 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4499 false /*nontemporal*/, 1 /* align=1 */);
4501 if (!ConstantMemory)
4502 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4507 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4508 /// If so, return true and lower it, otherwise return false and it will be
4509 /// lowered like a normal call.
4510 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4511 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4512 if (I.getNumOperands() != 4)
4515 const Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
4516 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4517 !I.getOperand(3)->getType()->isIntegerTy() ||
4518 !I.getType()->isIntegerTy())
4521 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
4523 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4524 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4525 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4526 bool ActuallyDoIt = true;
4529 switch (Size->getZExtValue()) {
4531 LoadVT = MVT::Other;
4533 ActuallyDoIt = false;
4537 LoadTy = Type::getInt16Ty(Size->getContext());
4541 LoadTy = Type::getInt32Ty(Size->getContext());
4545 LoadTy = Type::getInt64Ty(Size->getContext());
4549 LoadVT = MVT::v4i32;
4550 LoadTy = Type::getInt32Ty(Size->getContext());
4551 LoadTy = VectorType::get(LoadTy, 4);
4556 // This turns into unaligned loads. We only do this if the target natively
4557 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4558 // we'll only produce a small number of byte loads.
4560 // Require that we can find a legal MVT, and only do this if the target
4561 // supports unaligned loads of that type. Expanding into byte loads would
4563 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4564 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4565 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4566 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4567 ActuallyDoIt = false;
4571 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4572 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4574 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4576 EVT CallVT = TLI.getValueType(I.getType(), true);
4577 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4587 void SelectionDAGBuilder::visitCall(const CallInst &I) {
4588 const char *RenameFn = 0;
4589 if (Function *F = I.getCalledFunction()) {
4590 if (F->isDeclaration()) {
4591 const TargetIntrinsicInfo *II = TM.getIntrinsicInfo();
4593 if (unsigned IID = II->getIntrinsicID(F)) {
4594 RenameFn = visitIntrinsicCall(I, IID);
4599 if (unsigned IID = F->getIntrinsicID()) {
4600 RenameFn = visitIntrinsicCall(I, IID);
4606 // Check for well-known libc/libm calls. If the function is internal, it
4607 // can't be a library call.
4608 if (!F->hasLocalLinkage() && F->hasName()) {
4609 StringRef Name = F->getName();
4610 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
4611 if (I.getNumOperands() == 3 && // Basic sanity checks.
4612 I.getOperand(1)->getType()->isFloatingPointTy() &&
4613 I.getType() == I.getOperand(1)->getType() &&
4614 I.getType() == I.getOperand(2)->getType()) {
4615 SDValue LHS = getValue(I.getOperand(1));
4616 SDValue RHS = getValue(I.getOperand(2));
4617 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4618 LHS.getValueType(), LHS, RHS));
4621 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4622 if (I.getNumOperands() == 2 && // Basic sanity checks.
4623 I.getOperand(1)->getType()->isFloatingPointTy() &&
4624 I.getType() == I.getOperand(1)->getType()) {
4625 SDValue Tmp = getValue(I.getOperand(1));
4626 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4627 Tmp.getValueType(), Tmp));
4630 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4631 if (I.getNumOperands() == 2 && // Basic sanity checks.
4632 I.getOperand(1)->getType()->isFloatingPointTy() &&
4633 I.getType() == I.getOperand(1)->getType() &&
4634 I.onlyReadsMemory()) {
4635 SDValue Tmp = getValue(I.getOperand(1));
4636 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4637 Tmp.getValueType(), Tmp));
4640 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4641 if (I.getNumOperands() == 2 && // Basic sanity checks.
4642 I.getOperand(1)->getType()->isFloatingPointTy() &&
4643 I.getType() == I.getOperand(1)->getType() &&
4644 I.onlyReadsMemory()) {
4645 SDValue Tmp = getValue(I.getOperand(1));
4646 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4647 Tmp.getValueType(), Tmp));
4650 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4651 if (I.getNumOperands() == 2 && // Basic sanity checks.
4652 I.getOperand(1)->getType()->isFloatingPointTy() &&
4653 I.getType() == I.getOperand(1)->getType() &&
4654 I.onlyReadsMemory()) {
4655 SDValue Tmp = getValue(I.getOperand(1));
4656 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4657 Tmp.getValueType(), Tmp));
4660 } else if (Name == "memcmp") {
4661 if (visitMemCmpCall(I))
4665 } else if (isa<InlineAsm>(I.getOperand(0))) {
4672 Callee = getValue(I.getOperand(0));
4674 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4676 // Check if we can potentially perform a tail call. More detailed checking is
4677 // be done within LowerCallTo, after more information about the call is known.
4678 LowerCallTo(&I, Callee, I.isTailCall());
4681 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4682 /// this value and returns the result as a ValueVT value. This uses
4683 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4684 /// If the Flag pointer is NULL, no flag is used.
4685 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4686 SDValue &Chain, SDValue *Flag) const {
4687 // Assemble the legal parts into the final values.
4688 SmallVector<SDValue, 4> Values(ValueVTs.size());
4689 SmallVector<SDValue, 8> Parts;
4690 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4691 // Copy the legal parts from the registers.
4692 EVT ValueVT = ValueVTs[Value];
4693 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4694 EVT RegisterVT = RegVTs[Value];
4696 Parts.resize(NumRegs);
4697 for (unsigned i = 0; i != NumRegs; ++i) {
4700 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4702 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4703 *Flag = P.getValue(2);
4706 Chain = P.getValue(1);
4708 // If the source register was virtual and if we know something about it,
4709 // add an assert node.
4710 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4711 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4712 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4713 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4714 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4715 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4717 unsigned RegSize = RegisterVT.getSizeInBits();
4718 unsigned NumSignBits = LOI.NumSignBits;
4719 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4721 // FIXME: We capture more information than the dag can represent. For
4722 // now, just use the tightest assertzext/assertsext possible.
4724 EVT FromVT(MVT::Other);
4725 if (NumSignBits == RegSize)
4726 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4727 else if (NumZeroBits >= RegSize-1)
4728 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4729 else if (NumSignBits > RegSize-8)
4730 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4731 else if (NumZeroBits >= RegSize-8)
4732 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4733 else if (NumSignBits > RegSize-16)
4734 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4735 else if (NumZeroBits >= RegSize-16)
4736 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4737 else if (NumSignBits > RegSize-32)
4738 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4739 else if (NumZeroBits >= RegSize-32)
4740 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4742 if (FromVT != MVT::Other)
4743 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4744 RegisterVT, P, DAG.getValueType(FromVT));
4751 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4752 NumRegs, RegisterVT, ValueVT);
4757 return DAG.getNode(ISD::MERGE_VALUES, dl,
4758 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4759 &Values[0], ValueVTs.size());
4762 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4763 /// specified value into the registers specified by this object. This uses
4764 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4765 /// If the Flag pointer is NULL, no flag is used.
4766 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4767 SDValue &Chain, SDValue *Flag) const {
4768 // Get the list of the values's legal parts.
4769 unsigned NumRegs = Regs.size();
4770 SmallVector<SDValue, 8> Parts(NumRegs);
4771 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4772 EVT ValueVT = ValueVTs[Value];
4773 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4774 EVT RegisterVT = RegVTs[Value];
4776 getCopyToParts(DAG, dl,
4777 Val.getValue(Val.getResNo() + Value),
4778 &Parts[Part], NumParts, RegisterVT);
4782 // Copy the parts into the registers.
4783 SmallVector<SDValue, 8> Chains(NumRegs);
4784 for (unsigned i = 0; i != NumRegs; ++i) {
4787 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4790 *Flag = Part.getValue(1);
4793 Chains[i] = Part.getValue(0);
4796 if (NumRegs == 1 || Flag)
4797 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4798 // flagged to it. That is the CopyToReg nodes and the user are considered
4799 // a single scheduling unit. If we create a TokenFactor and return it as
4800 // chain, then the TokenFactor is both a predecessor (operand) of the
4801 // user as well as a successor (the TF operands are flagged to the user).
4802 // c1, f1 = CopyToReg
4803 // c2, f2 = CopyToReg
4804 // c3 = TokenFactor c1, c2
4807 Chain = Chains[NumRegs-1];
4809 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4812 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4813 /// operand list. This adds the code marker and includes the number of
4814 /// values added into it.
4815 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
4816 unsigned MatchingIdx,
4818 std::vector<SDValue> &Ops) const {
4819 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
4821 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
4822 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
4825 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4826 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4827 EVT RegisterVT = RegVTs[Value];
4828 for (unsigned i = 0; i != NumRegs; ++i) {
4829 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4830 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4835 /// isAllocatableRegister - If the specified register is safe to allocate,
4836 /// i.e. it isn't a stack pointer or some other special register, return the
4837 /// register class for the register. Otherwise, return null.
4838 static const TargetRegisterClass *
4839 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4840 const TargetLowering &TLI,
4841 const TargetRegisterInfo *TRI) {
4842 EVT FoundVT = MVT::Other;
4843 const TargetRegisterClass *FoundRC = 0;
4844 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4845 E = TRI->regclass_end(); RCI != E; ++RCI) {
4846 EVT ThisVT = MVT::Other;
4848 const TargetRegisterClass *RC = *RCI;
4849 // If none of the value types for this register class are valid, we
4850 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4851 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4853 if (TLI.isTypeLegal(*I)) {
4854 // If we have already found this register in a different register class,
4855 // choose the one with the largest VT specified. For example, on
4856 // PowerPC, we favor f64 register classes over f32.
4857 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4864 if (ThisVT == MVT::Other) continue;
4866 // NOTE: This isn't ideal. In particular, this might allocate the
4867 // frame pointer in functions that need it (due to them not being taken
4868 // out of allocation, because a variable sized allocation hasn't been seen
4869 // yet). This is a slight code pessimization, but should still work.
4870 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4871 E = RC->allocation_order_end(MF); I != E; ++I)
4873 // We found a matching register class. Keep looking at others in case
4874 // we find one with larger registers that this physreg is also in.
4885 /// AsmOperandInfo - This contains information for each constraint that we are
4887 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4888 public TargetLowering::AsmOperandInfo {
4890 /// CallOperand - If this is the result output operand or a clobber
4891 /// this is null, otherwise it is the incoming operand to the CallInst.
4892 /// This gets modified as the asm is processed.
4893 SDValue CallOperand;
4895 /// AssignedRegs - If this is a register or register class operand, this
4896 /// contains the set of register corresponding to the operand.
4897 RegsForValue AssignedRegs;
4899 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4900 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4903 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4904 /// busy in OutputRegs/InputRegs.
4905 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4906 std::set<unsigned> &OutputRegs,
4907 std::set<unsigned> &InputRegs,
4908 const TargetRegisterInfo &TRI) const {
4910 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4911 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4914 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4915 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4919 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4920 /// corresponds to. If there is no Value* for this operand, it returns
4922 EVT getCallOperandValEVT(LLVMContext &Context,
4923 const TargetLowering &TLI,
4924 const TargetData *TD) const {
4925 if (CallOperandVal == 0) return MVT::Other;
4927 if (isa<BasicBlock>(CallOperandVal))
4928 return TLI.getPointerTy();
4930 const llvm::Type *OpTy = CallOperandVal->getType();
4932 // If this is an indirect operand, the operand is a pointer to the
4935 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4937 report_fatal_error("Indirect operand for inline asm not a pointer!");
4938 OpTy = PtrTy->getElementType();
4941 // If OpTy is not a single value, it may be a struct/union that we
4942 // can tile with integers.
4943 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4944 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4953 OpTy = IntegerType::get(Context, BitSize);
4958 return TLI.getValueType(OpTy, true);
4962 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4964 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4965 const TargetRegisterInfo &TRI) {
4966 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4968 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4969 for (; *Aliases; ++Aliases)
4970 Regs.insert(*Aliases);
4973 } // end llvm namespace.
4976 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4977 /// specified operand. We prefer to assign virtual registers, to allow the
4978 /// register allocator to handle the assignment process. However, if the asm
4979 /// uses features that we can't model on machineinstrs, we have SDISel do the
4980 /// allocation. This produces generally horrible, but correct, code.
4982 /// OpInfo describes the operand.
4983 /// Input and OutputRegs are the set of already allocated physical registers.
4985 void SelectionDAGBuilder::
4986 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4987 std::set<unsigned> &OutputRegs,
4988 std::set<unsigned> &InputRegs) {
4989 LLVMContext &Context = FuncInfo.Fn->getContext();
4991 // Compute whether this value requires an input register, an output register,
4993 bool isOutReg = false;
4994 bool isInReg = false;
4995 switch (OpInfo.Type) {
4996 case InlineAsm::isOutput:
4999 // If there is an input constraint that matches this, we need to reserve
5000 // the input register so no other inputs allocate to it.
5001 isInReg = OpInfo.hasMatchingInput();
5003 case InlineAsm::isInput:
5007 case InlineAsm::isClobber:
5014 MachineFunction &MF = DAG.getMachineFunction();
5015 SmallVector<unsigned, 4> Regs;
5017 // If this is a constraint for a single physreg, or a constraint for a
5018 // register class, find it.
5019 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5020 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5021 OpInfo.ConstraintVT);
5023 unsigned NumRegs = 1;
5024 if (OpInfo.ConstraintVT != MVT::Other) {
5025 // If this is a FP input in an integer register (or visa versa) insert a bit
5026 // cast of the input value. More generally, handle any case where the input
5027 // value disagrees with the register class we plan to stick this in.
5028 if (OpInfo.Type == InlineAsm::isInput &&
5029 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5030 // Try to convert to the first EVT that the reg class contains. If the
5031 // types are identical size, use a bitcast to convert (e.g. two differing
5033 EVT RegVT = *PhysReg.second->vt_begin();
5034 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5035 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5036 RegVT, OpInfo.CallOperand);
5037 OpInfo.ConstraintVT = RegVT;
5038 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5039 // If the input is a FP value and we want it in FP registers, do a
5040 // bitcast to the corresponding integer type. This turns an f64 value
5041 // into i64, which can be passed with two i32 values on a 32-bit
5043 RegVT = EVT::getIntegerVT(Context,
5044 OpInfo.ConstraintVT.getSizeInBits());
5045 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5046 RegVT, OpInfo.CallOperand);
5047 OpInfo.ConstraintVT = RegVT;
5051 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5055 EVT ValueVT = OpInfo.ConstraintVT;
5057 // If this is a constraint for a specific physical register, like {r17},
5059 if (unsigned AssignedReg = PhysReg.first) {
5060 const TargetRegisterClass *RC = PhysReg.second;
5061 if (OpInfo.ConstraintVT == MVT::Other)
5062 ValueVT = *RC->vt_begin();
5064 // Get the actual register value type. This is important, because the user
5065 // may have asked for (e.g.) the AX register in i32 type. We need to
5066 // remember that AX is actually i16 to get the right extension.
5067 RegVT = *RC->vt_begin();
5069 // This is a explicit reference to a physical register.
5070 Regs.push_back(AssignedReg);
5072 // If this is an expanded reference, add the rest of the regs to Regs.
5074 TargetRegisterClass::iterator I = RC->begin();
5075 for (; *I != AssignedReg; ++I)
5076 assert(I != RC->end() && "Didn't find reg!");
5078 // Already added the first reg.
5080 for (; NumRegs; --NumRegs, ++I) {
5081 assert(I != RC->end() && "Ran out of registers to allocate!");
5086 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5087 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5088 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5092 // Otherwise, if this was a reference to an LLVM register class, create vregs
5093 // for this reference.
5094 if (const TargetRegisterClass *RC = PhysReg.second) {
5095 RegVT = *RC->vt_begin();
5096 if (OpInfo.ConstraintVT == MVT::Other)
5099 // Create the appropriate number of virtual registers.
5100 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5101 for (; NumRegs; --NumRegs)
5102 Regs.push_back(RegInfo.createVirtualRegister(RC));
5104 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5108 // This is a reference to a register class that doesn't directly correspond
5109 // to an LLVM register class. Allocate NumRegs consecutive, available,
5110 // registers from the class.
5111 std::vector<unsigned> RegClassRegs
5112 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5113 OpInfo.ConstraintVT);
5115 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5116 unsigned NumAllocated = 0;
5117 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5118 unsigned Reg = RegClassRegs[i];
5119 // See if this register is available.
5120 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5121 (isInReg && InputRegs.count(Reg))) { // Already used.
5122 // Make sure we find consecutive registers.
5127 // Check to see if this register is allocatable (i.e. don't give out the
5129 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5130 if (!RC) { // Couldn't allocate this register.
5131 // Reset NumAllocated to make sure we return consecutive registers.
5136 // Okay, this register is good, we can use it.
5139 // If we allocated enough consecutive registers, succeed.
5140 if (NumAllocated == NumRegs) {
5141 unsigned RegStart = (i-NumAllocated)+1;
5142 unsigned RegEnd = i+1;
5143 // Mark all of the allocated registers used.
5144 for (unsigned i = RegStart; i != RegEnd; ++i)
5145 Regs.push_back(RegClassRegs[i]);
5147 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5148 OpInfo.ConstraintVT);
5149 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5154 // Otherwise, we couldn't allocate enough registers for this.
5157 /// visitInlineAsm - Handle a call to an InlineAsm object.
5159 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5160 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5162 /// ConstraintOperands - Information about all of the constraints.
5163 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5165 std::set<unsigned> OutputRegs, InputRegs;
5167 // Do a prepass over the constraints, canonicalizing them, and building up the
5168 // ConstraintOperands list.
5169 std::vector<InlineAsm::ConstraintInfo>
5170 ConstraintInfos = IA->ParseConstraints();
5172 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5174 SDValue Chain, Flag;
5176 // We won't need to flush pending loads if this asm doesn't touch
5177 // memory and is nonvolatile.
5178 if (hasMemory || IA->hasSideEffects())
5181 Chain = DAG.getRoot();
5183 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5184 unsigned ResNo = 0; // ResNo - The result number of the next output.
5185 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5186 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5187 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5189 EVT OpVT = MVT::Other;
5191 // Compute the value type for each operand.
5192 switch (OpInfo.Type) {
5193 case InlineAsm::isOutput:
5194 // Indirect outputs just consume an argument.
5195 if (OpInfo.isIndirect) {
5196 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5200 // The return value of the call is this value. As such, there is no
5201 // corresponding argument.
5202 assert(!CS.getType()->isVoidTy() &&
5204 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5205 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5207 assert(ResNo == 0 && "Asm only has one result!");
5208 OpVT = TLI.getValueType(CS.getType());
5212 case InlineAsm::isInput:
5213 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5215 case InlineAsm::isClobber:
5220 // If this is an input or an indirect output, process the call argument.
5221 // BasicBlocks are labels, currently appearing only in asm's.
5222 if (OpInfo.CallOperandVal) {
5223 // Strip bitcasts, if any. This mostly comes up for functions.
5224 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5226 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5227 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5229 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5232 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5235 OpInfo.ConstraintVT = OpVT;
5238 // Second pass over the constraints: compute which constraint option to use
5239 // and assign registers to constraints that want a specific physreg.
5240 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5241 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5243 // If this is an output operand with a matching input operand, look up the
5244 // matching input. If their types mismatch, e.g. one is an integer, the
5245 // other is floating point, or their sizes are different, flag it as an
5247 if (OpInfo.hasMatchingInput()) {
5248 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5250 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5251 if ((OpInfo.ConstraintVT.isInteger() !=
5252 Input.ConstraintVT.isInteger()) ||
5253 (OpInfo.ConstraintVT.getSizeInBits() !=
5254 Input.ConstraintVT.getSizeInBits())) {
5255 report_fatal_error("Unsupported asm: input constraint"
5256 " with a matching output constraint of"
5257 " incompatible type!");
5259 Input.ConstraintVT = OpInfo.ConstraintVT;
5263 // Compute the constraint code and ConstraintType to use.
5264 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5266 // If this is a memory input, and if the operand is not indirect, do what we
5267 // need to to provide an address for the memory input.
5268 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5269 !OpInfo.isIndirect) {
5270 assert(OpInfo.Type == InlineAsm::isInput &&
5271 "Can only indirectify direct input operands!");
5273 // Memory operands really want the address of the value. If we don't have
5274 // an indirect input, put it in the constpool if we can, otherwise spill
5275 // it to a stack slot.
5277 // If the operand is a float, integer, or vector constant, spill to a
5278 // constant pool entry to get its address.
5279 const Value *OpVal = OpInfo.CallOperandVal;
5280 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5281 isa<ConstantVector>(OpVal)) {
5282 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5283 TLI.getPointerTy());
5285 // Otherwise, create a stack slot and emit a store to it before the
5287 const Type *Ty = OpVal->getType();
5288 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5289 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5290 MachineFunction &MF = DAG.getMachineFunction();
5291 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5292 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5293 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5294 OpInfo.CallOperand, StackSlot, NULL, 0,
5296 OpInfo.CallOperand = StackSlot;
5299 // There is no longer a Value* corresponding to this operand.
5300 OpInfo.CallOperandVal = 0;
5302 // It is now an indirect operand.
5303 OpInfo.isIndirect = true;
5306 // If this constraint is for a specific register, allocate it before
5308 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5309 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5312 ConstraintInfos.clear();
5314 // Second pass - Loop over all of the operands, assigning virtual or physregs
5315 // to register class operands.
5316 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5317 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5319 // C_Register operands have already been allocated, Other/Memory don't need
5321 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5322 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5325 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5326 std::vector<SDValue> AsmNodeOperands;
5327 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5328 AsmNodeOperands.push_back(
5329 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5330 TLI.getPointerTy()));
5332 // If we have a !srcloc metadata node associated with it, we want to attach
5333 // this to the ultimately generated inline asm machineinstr. To do this, we
5334 // pass in the third operand as this (potentially null) inline asm MDNode.
5335 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5336 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5338 // Loop over all of the inputs, copying the operand values into the
5339 // appropriate registers and processing the output regs.
5340 RegsForValue RetValRegs;
5342 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5343 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5345 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5346 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5348 switch (OpInfo.Type) {
5349 case InlineAsm::isOutput: {
5350 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5351 OpInfo.ConstraintType != TargetLowering::C_Register) {
5352 // Memory output, or 'other' output (e.g. 'X' constraint).
5353 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5355 // Add information to the INLINEASM node to know about this output.
5356 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5357 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5358 TLI.getPointerTy()));
5359 AsmNodeOperands.push_back(OpInfo.CallOperand);
5363 // Otherwise, this is a register or register class output.
5365 // Copy the output from the appropriate register. Find a register that
5367 if (OpInfo.AssignedRegs.Regs.empty())
5368 report_fatal_error("Couldn't allocate output reg for constraint '" +
5369 Twine(OpInfo.ConstraintCode) + "'!");
5371 // If this is an indirect operand, store through the pointer after the
5373 if (OpInfo.isIndirect) {
5374 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5375 OpInfo.CallOperandVal));
5377 // This is the result value of the call.
5378 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5379 // Concatenate this output onto the outputs list.
5380 RetValRegs.append(OpInfo.AssignedRegs);
5383 // Add information to the INLINEASM node to know that this register is
5385 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5386 InlineAsm::Kind_RegDefEarlyClobber :
5387 InlineAsm::Kind_RegDef,
5394 case InlineAsm::isInput: {
5395 SDValue InOperandVal = OpInfo.CallOperand;
5397 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5398 // If this is required to match an output register we have already set,
5399 // just use its register.
5400 unsigned OperandNo = OpInfo.getMatchedOperand();
5402 // Scan until we find the definition we already emitted of this operand.
5403 // When we find it, create a RegsForValue operand.
5404 unsigned CurOp = InlineAsm::Op_FirstOperand;
5405 for (; OperandNo; --OperandNo) {
5406 // Advance to the next operand.
5408 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5409 assert((InlineAsm::isRegDefKind(OpFlag) ||
5410 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5411 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5412 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5416 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5417 if (InlineAsm::isRegDefKind(OpFlag) ||
5418 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5419 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5420 if (OpInfo.isIndirect) {
5421 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5422 LLVMContext &Ctx = *DAG.getContext();
5423 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5424 " don't know how to handle tied "
5425 "indirect register inputs");
5428 RegsForValue MatchedRegs;
5429 MatchedRegs.TLI = &TLI;
5430 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5431 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5432 MatchedRegs.RegVTs.push_back(RegVT);
5433 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5434 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5436 MatchedRegs.Regs.push_back
5437 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5439 // Use the produced MatchedRegs object to
5440 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5442 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5443 true, OpInfo.getMatchedOperand(),
5444 DAG, AsmNodeOperands);
5448 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5449 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5450 "Unexpected number of operands");
5451 // Add information to the INLINEASM node to know about this input.
5452 // See InlineAsm.h isUseOperandTiedToDef.
5453 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5454 OpInfo.getMatchedOperand());
5455 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5456 TLI.getPointerTy()));
5457 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5461 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5462 assert(!OpInfo.isIndirect &&
5463 "Don't know how to handle indirect other inputs yet!");
5465 std::vector<SDValue> Ops;
5466 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5467 hasMemory, Ops, DAG);
5469 report_fatal_error("Invalid operand for inline asm constraint '" +
5470 Twine(OpInfo.ConstraintCode) + "'!");
5472 // Add information to the INLINEASM node to know about this input.
5473 unsigned ResOpType =
5474 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5475 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5476 TLI.getPointerTy()));
5477 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5481 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5482 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5483 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5484 "Memory operands expect pointer values");
5486 // Add information to the INLINEASM node to know about this input.
5487 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5488 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5489 TLI.getPointerTy()));
5490 AsmNodeOperands.push_back(InOperandVal);
5494 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5495 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5496 "Unknown constraint type!");
5497 assert(!OpInfo.isIndirect &&
5498 "Don't know how to handle indirect register inputs yet!");
5500 // Copy the input into the appropriate registers.
5501 if (OpInfo.AssignedRegs.Regs.empty() ||
5502 !OpInfo.AssignedRegs.areValueTypesLegal())
5503 report_fatal_error("Couldn't allocate input reg for constraint '" +
5504 Twine(OpInfo.ConstraintCode) + "'!");
5506 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5509 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5510 DAG, AsmNodeOperands);
5513 case InlineAsm::isClobber: {
5514 // Add the clobbered value to the operand list, so that the register
5515 // allocator is aware that the physreg got clobbered.
5516 if (!OpInfo.AssignedRegs.Regs.empty())
5517 OpInfo.AssignedRegs.AddInlineAsmOperands(
5518 InlineAsm::Kind_RegDefEarlyClobber,
5526 // Finish up input operands. Set the input chain and add the flag last.
5527 AsmNodeOperands[0] = Chain;
5528 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5530 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5531 DAG.getVTList(MVT::Other, MVT::Flag),
5532 &AsmNodeOperands[0], AsmNodeOperands.size());
5533 Flag = Chain.getValue(1);
5535 // If this asm returns a register value, copy the result from that register
5536 // and set it as the value of the call.
5537 if (!RetValRegs.Regs.empty()) {
5538 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5541 // FIXME: Why don't we do this for inline asms with MRVs?
5542 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5543 EVT ResultType = TLI.getValueType(CS.getType());
5545 // If any of the results of the inline asm is a vector, it may have the
5546 // wrong width/num elts. This can happen for register classes that can
5547 // contain multiple different value types. The preg or vreg allocated may
5548 // not have the same VT as was expected. Convert it to the right type
5549 // with bit_convert.
5550 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5551 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5554 } else if (ResultType != Val.getValueType() &&
5555 ResultType.isInteger() && Val.getValueType().isInteger()) {
5556 // If a result value was tied to an input value, the computed result may
5557 // have a wider width than the expected result. Extract the relevant
5559 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5562 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5565 setValue(CS.getInstruction(), Val);
5566 // Don't need to use this as a chain in this case.
5567 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5571 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5573 // Process indirect outputs, first output all of the flagged copies out of
5575 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5576 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5577 const Value *Ptr = IndirectStoresToEmit[i].second;
5578 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5580 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5583 // Emit the non-flagged stores from the physregs.
5584 SmallVector<SDValue, 8> OutChains;
5585 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5586 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5587 StoresToEmit[i].first,
5588 getValue(StoresToEmit[i].second),
5589 StoresToEmit[i].second, 0,
5591 OutChains.push_back(Val);
5594 if (!OutChains.empty())
5595 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5596 &OutChains[0], OutChains.size());
5601 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5602 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5603 MVT::Other, getRoot(),
5604 getValue(I.getOperand(1)),
5605 DAG.getSrcValue(I.getOperand(1))));
5608 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5609 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5610 getRoot(), getValue(I.getOperand(0)),
5611 DAG.getSrcValue(I.getOperand(0)));
5613 DAG.setRoot(V.getValue(1));
5616 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5617 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5618 MVT::Other, getRoot(),
5619 getValue(I.getOperand(1)),
5620 DAG.getSrcValue(I.getOperand(1))));
5623 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5624 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5625 MVT::Other, getRoot(),
5626 getValue(I.getOperand(1)),
5627 getValue(I.getOperand(2)),
5628 DAG.getSrcValue(I.getOperand(1)),
5629 DAG.getSrcValue(I.getOperand(2))));
5632 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5633 /// implementation, which just calls LowerCall.
5634 /// FIXME: When all targets are
5635 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5636 std::pair<SDValue, SDValue>
5637 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5638 bool RetSExt, bool RetZExt, bool isVarArg,
5639 bool isInreg, unsigned NumFixedArgs,
5640 CallingConv::ID CallConv, bool isTailCall,
5641 bool isReturnValueUsed,
5643 ArgListTy &Args, SelectionDAG &DAG,
5644 DebugLoc dl) const {
5645 // Handle all of the outgoing arguments.
5646 SmallVector<ISD::OutputArg, 32> Outs;
5647 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5648 SmallVector<EVT, 4> ValueVTs;
5649 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5650 for (unsigned Value = 0, NumValues = ValueVTs.size();
5651 Value != NumValues; ++Value) {
5652 EVT VT = ValueVTs[Value];
5653 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5654 SDValue Op = SDValue(Args[i].Node.getNode(),
5655 Args[i].Node.getResNo() + Value);
5656 ISD::ArgFlagsTy Flags;
5657 unsigned OriginalAlignment =
5658 getTargetData()->getABITypeAlignment(ArgTy);
5664 if (Args[i].isInReg)
5668 if (Args[i].isByVal) {
5670 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5671 const Type *ElementTy = Ty->getElementType();
5672 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5673 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5674 // For ByVal, alignment should come from FE. BE will guess if this
5675 // info is not there but there are cases it cannot get right.
5676 if (Args[i].Alignment)
5677 FrameAlign = Args[i].Alignment;
5678 Flags.setByValAlign(FrameAlign);
5679 Flags.setByValSize(FrameSize);
5683 Flags.setOrigAlign(OriginalAlignment);
5685 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5686 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5687 SmallVector<SDValue, 4> Parts(NumParts);
5688 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5691 ExtendKind = ISD::SIGN_EXTEND;
5692 else if (Args[i].isZExt)
5693 ExtendKind = ISD::ZERO_EXTEND;
5695 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5696 PartVT, ExtendKind);
5698 for (unsigned j = 0; j != NumParts; ++j) {
5699 // if it isn't first piece, alignment must be 1
5700 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5701 if (NumParts > 1 && j == 0)
5702 MyFlags.Flags.setSplit();
5704 MyFlags.Flags.setOrigAlign(1);
5706 Outs.push_back(MyFlags);
5711 // Handle the incoming return values from the call.
5712 SmallVector<ISD::InputArg, 32> Ins;
5713 SmallVector<EVT, 4> RetTys;
5714 ComputeValueVTs(*this, RetTy, RetTys);
5715 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5717 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5718 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5719 for (unsigned i = 0; i != NumRegs; ++i) {
5720 ISD::InputArg MyFlags;
5721 MyFlags.VT = RegisterVT;
5722 MyFlags.Used = isReturnValueUsed;
5724 MyFlags.Flags.setSExt();
5726 MyFlags.Flags.setZExt();
5728 MyFlags.Flags.setInReg();
5729 Ins.push_back(MyFlags);
5733 SmallVector<SDValue, 4> InVals;
5734 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5735 Outs, Ins, dl, DAG, InVals);
5737 // Verify that the target's LowerCall behaved as expected.
5738 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5739 "LowerCall didn't return a valid chain!");
5740 assert((!isTailCall || InVals.empty()) &&
5741 "LowerCall emitted a return value for a tail call!");
5742 assert((isTailCall || InVals.size() == Ins.size()) &&
5743 "LowerCall didn't emit the correct number of values!");
5745 // For a tail call, the return value is merely live-out and there aren't
5746 // any nodes in the DAG representing it. Return a special value to
5747 // indicate that a tail call has been emitted and no more Instructions
5748 // should be processed in the current block.
5751 return std::make_pair(SDValue(), SDValue());
5754 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5755 assert(InVals[i].getNode() &&
5756 "LowerCall emitted a null value!");
5757 assert(Ins[i].VT == InVals[i].getValueType() &&
5758 "LowerCall emitted a value with the wrong type!");
5761 // Collect the legal value parts into potentially illegal values
5762 // that correspond to the original function's return values.
5763 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5765 AssertOp = ISD::AssertSext;
5767 AssertOp = ISD::AssertZext;
5768 SmallVector<SDValue, 4> ReturnValues;
5769 unsigned CurReg = 0;
5770 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5772 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5773 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5775 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5776 NumRegs, RegisterVT, VT,
5781 // For a function returning void, there is no return value. We can't create
5782 // such a node, so we just return a null return value in that case. In
5783 // that case, nothing will actualy look at the value.
5784 if (ReturnValues.empty())
5785 return std::make_pair(SDValue(), Chain);
5787 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5788 DAG.getVTList(&RetTys[0], RetTys.size()),
5789 &ReturnValues[0], ReturnValues.size());
5790 return std::make_pair(Res, Chain);
5793 void TargetLowering::LowerOperationWrapper(SDNode *N,
5794 SmallVectorImpl<SDValue> &Results,
5795 SelectionDAG &DAG) const {
5796 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5798 Results.push_back(Res);
5801 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5802 llvm_unreachable("LowerOperation not implemented for this target!");
5807 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
5808 SDValue Op = getValue(V);
5809 assert((Op.getOpcode() != ISD::CopyFromReg ||
5810 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5811 "Copy from a reg to the same reg!");
5812 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5814 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5815 SDValue Chain = DAG.getEntryNode();
5816 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5817 PendingExports.push_back(Chain);
5820 #include "llvm/CodeGen/SelectionDAGISel.h"
5822 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
5823 // If this is the entry block, emit arguments.
5824 const Function &F = *LLVMBB->getParent();
5825 SelectionDAG &DAG = SDB->DAG;
5826 SDValue OldRoot = DAG.getRoot();
5827 DebugLoc dl = SDB->getCurDebugLoc();
5828 const TargetData *TD = TLI.getTargetData();
5829 SmallVector<ISD::InputArg, 16> Ins;
5831 // Check whether the function can return without sret-demotion.
5832 SmallVector<EVT, 4> OutVTs;
5833 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
5834 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5835 OutVTs, OutsFlags, TLI);
5836 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5838 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
5839 OutVTs, OutsFlags, DAG);
5840 if (!FLI.CanLowerReturn) {
5841 // Put in an sret pointer parameter before all the other parameters.
5842 SmallVector<EVT, 1> ValueVTs;
5843 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5845 // NOTE: Assuming that a pointer will never break down to more than one VT
5847 ISD::ArgFlagsTy Flags;
5849 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
5850 ISD::InputArg RetArg(Flags, RegisterVT, true);
5851 Ins.push_back(RetArg);
5854 // Set up the incoming argument description vector.
5856 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
5857 I != E; ++I, ++Idx) {
5858 SmallVector<EVT, 4> ValueVTs;
5859 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5860 bool isArgValueUsed = !I->use_empty();
5861 for (unsigned Value = 0, NumValues = ValueVTs.size();
5862 Value != NumValues; ++Value) {
5863 EVT VT = ValueVTs[Value];
5864 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5865 ISD::ArgFlagsTy Flags;
5866 unsigned OriginalAlignment =
5867 TD->getABITypeAlignment(ArgTy);
5869 if (F.paramHasAttr(Idx, Attribute::ZExt))
5871 if (F.paramHasAttr(Idx, Attribute::SExt))
5873 if (F.paramHasAttr(Idx, Attribute::InReg))
5875 if (F.paramHasAttr(Idx, Attribute::StructRet))
5877 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5879 const PointerType *Ty = cast<PointerType>(I->getType());
5880 const Type *ElementTy = Ty->getElementType();
5881 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5882 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5883 // For ByVal, alignment should be passed from FE. BE will guess if
5884 // this info is not there but there are cases it cannot get right.
5885 if (F.getParamAlignment(Idx))
5886 FrameAlign = F.getParamAlignment(Idx);
5887 Flags.setByValAlign(FrameAlign);
5888 Flags.setByValSize(FrameSize);
5890 if (F.paramHasAttr(Idx, Attribute::Nest))
5892 Flags.setOrigAlign(OriginalAlignment);
5894 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5895 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5896 for (unsigned i = 0; i != NumRegs; ++i) {
5897 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5898 if (NumRegs > 1 && i == 0)
5899 MyFlags.Flags.setSplit();
5900 // if it isn't first piece, alignment must be 1
5902 MyFlags.Flags.setOrigAlign(1);
5903 Ins.push_back(MyFlags);
5908 // Call the target to set up the argument values.
5909 SmallVector<SDValue, 8> InVals;
5910 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5914 // Verify that the target's LowerFormalArguments behaved as expected.
5915 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5916 "LowerFormalArguments didn't return a valid chain!");
5917 assert(InVals.size() == Ins.size() &&
5918 "LowerFormalArguments didn't emit the correct number of values!");
5920 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5921 assert(InVals[i].getNode() &&
5922 "LowerFormalArguments emitted a null value!");
5923 assert(Ins[i].VT == InVals[i].getValueType() &&
5924 "LowerFormalArguments emitted a value with the wrong type!");
5928 // Update the DAG with the new chain value resulting from argument lowering.
5929 DAG.setRoot(NewRoot);
5931 // Set up the argument values.
5934 if (!FLI.CanLowerReturn) {
5935 // Create a virtual register for the sret pointer, and put in a copy
5936 // from the sret argument into it.
5937 SmallVector<EVT, 1> ValueVTs;
5938 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5939 EVT VT = ValueVTs[0];
5940 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5941 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5942 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
5943 RegVT, VT, AssertOp);
5945 MachineFunction& MF = SDB->DAG.getMachineFunction();
5946 MachineRegisterInfo& RegInfo = MF.getRegInfo();
5947 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
5948 FLI.DemoteRegister = SRetReg;
5949 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
5951 DAG.setRoot(NewRoot);
5953 // i indexes lowered arguments. Bump it past the hidden sret argument.
5954 // Idx indexes LLVM arguments. Don't touch it.
5958 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5960 SmallVector<SDValue, 4> ArgValues;
5961 SmallVector<EVT, 4> ValueVTs;
5962 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5963 unsigned NumValues = ValueVTs.size();
5964 for (unsigned Value = 0; Value != NumValues; ++Value) {
5965 EVT VT = ValueVTs[Value];
5966 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5967 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5969 if (!I->use_empty()) {
5970 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5971 if (F.paramHasAttr(Idx, Attribute::SExt))
5972 AssertOp = ISD::AssertSext;
5973 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5974 AssertOp = ISD::AssertZext;
5976 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
5977 NumParts, PartVT, VT,
5984 if (!I->use_empty()) {
5986 if (!ArgValues.empty())
5987 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
5988 SDB->getCurDebugLoc());
5989 SDB->setValue(I, Res);
5991 // If this argument is live outside of the entry block, insert a copy from
5992 // whereever we got it to the vreg that other BB's will reference it as.
5993 SDB->CopyToExportRegsIfNeeded(I);
5997 assert(i == InVals.size() && "Argument register count mismatch!");
5999 // Finally, if the target has anything special to do, allow it to do so.
6000 // FIXME: this should insert code into the DAG!
6001 EmitFunctionEntryCode();
6004 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6005 /// ensure constants are generated when needed. Remember the virtual registers
6006 /// that need to be added to the Machine PHI nodes as input. We cannot just
6007 /// directly add them, because expansion might result in multiple MBB's for one
6008 /// BB. As such, the start of the BB might correspond to a different MBB than
6012 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6013 const TerminatorInst *TI = LLVMBB->getTerminator();
6015 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6017 // Check successor nodes' PHI nodes that expect a constant to be available
6019 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6020 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6021 if (!isa<PHINode>(SuccBB->begin())) continue;
6022 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6024 // If this terminator has multiple identical successors (common for
6025 // switches), only handle each succ once.
6026 if (!SuccsHandled.insert(SuccMBB)) continue;
6028 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6030 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6031 // nodes and Machine PHI nodes, but the incoming operands have not been
6033 for (BasicBlock::const_iterator I = SuccBB->begin();
6034 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6035 // Ignore dead phi's.
6036 if (PN->use_empty()) continue;
6039 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6041 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6042 unsigned &RegOut = ConstantsOut[C];
6044 RegOut = FuncInfo.CreateRegForValue(C);
6045 CopyValueToVirtualRegister(C, RegOut);
6049 Reg = FuncInfo.ValueMap[PHIOp];
6051 assert(isa<AllocaInst>(PHIOp) &&
6052 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6053 "Didn't codegen value into a register!??");
6054 Reg = FuncInfo.CreateRegForValue(PHIOp);
6055 CopyValueToVirtualRegister(PHIOp, Reg);
6059 // Remember that this register needs to added to the machine PHI node as
6060 // the input for this MBB.
6061 SmallVector<EVT, 4> ValueVTs;
6062 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6063 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6064 EVT VT = ValueVTs[vti];
6065 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6066 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6067 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6068 Reg += NumRegisters;
6072 ConstantsOut.clear();