1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, DL, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits, DL));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i, DL,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
526 bool Smaller = ValueVT.bitsLE(PartVT);
527 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
552 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy()));
557 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
602 /// this value and returns the result as a ValueVT value. This uses
603 /// Chain/Flag as the input and updates them for the output Chain/Flag.
604 /// If the Flag pointer is NULL, no flag is used.
605 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
606 FunctionLoweringInfo &FuncInfo,
608 SDValue &Chain, SDValue *Flag,
609 const Value *V) const {
610 // A Value with type {} or [0 x %t] needs no registers.
611 if (ValueVTs.empty())
614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
616 // Assemble the legal parts into the final values.
617 SmallVector<SDValue, 4> Values(ValueVTs.size());
618 SmallVector<SDValue, 8> Parts;
619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 // Copy the legal parts from the registers.
621 EVT ValueVT = ValueVTs[Value];
622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
623 MVT RegisterVT = RegVTs[Value];
625 Parts.resize(NumRegs);
626 for (unsigned i = 0; i != NumRegs; ++i) {
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
632 *Flag = P.getValue(2);
635 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
641 !RegisterVT.isInteger() || RegisterVT.isVector())
644 const FunctionLoweringInfo::LiveOutInfo *LOI =
645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
649 unsigned RegSize = RegisterVT.getSizeInBits();
650 unsigned NumSignBits = LOI->NumSignBits;
651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
653 if (NumZeroBits == RegSize) {
654 // The current value is a zero.
655 // Explicitly express that as it would be easier for
656 // optimizations to kick in.
657 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
661 // FIXME: We capture more information than the dag can represent. For
662 // now, just use the tightest assertzext/assertsext possible.
664 EVT FromVT(MVT::Other);
665 if (NumSignBits == RegSize)
666 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
667 else if (NumZeroBits >= RegSize-1)
668 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
669 else if (NumSignBits > RegSize-8)
670 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
671 else if (NumZeroBits >= RegSize-8)
672 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
673 else if (NumSignBits > RegSize-16)
674 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
675 else if (NumZeroBits >= RegSize-16)
676 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
677 else if (NumSignBits > RegSize-32)
678 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
679 else if (NumZeroBits >= RegSize-32)
680 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
684 // Add an assertion node.
685 assert(FromVT != MVT::Other);
686 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
687 RegisterVT, P, DAG.getValueType(FromVT));
690 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
691 NumRegs, RegisterVT, ValueVT, V);
696 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
699 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
700 /// specified value into the registers specified by this object. This uses
701 /// Chain/Flag as the input and updates them for the output Chain/Flag.
702 /// If the Flag pointer is NULL, no flag is used.
703 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
704 SDValue &Chain, SDValue *Flag, const Value *V,
705 ISD::NodeType PreferredExtendType) const {
706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
707 ISD::NodeType ExtendKind = PreferredExtendType;
709 // Get the list of the values's legal parts.
710 unsigned NumRegs = Regs.size();
711 SmallVector<SDValue, 8> Parts(NumRegs);
712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
713 EVT ValueVT = ValueVTs[Value];
714 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
715 MVT RegisterVT = RegVTs[Value];
717 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
718 ExtendKind = ISD::ZERO_EXTEND;
720 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
721 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
725 // Copy the parts into the registers.
726 SmallVector<SDValue, 8> Chains(NumRegs);
727 for (unsigned i = 0; i != NumRegs; ++i) {
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
732 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
733 *Flag = Part.getValue(1);
736 Chains[i] = Part.getValue(0);
739 if (NumRegs == 1 || Flag)
740 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
741 // flagged to it. That is the CopyToReg nodes and the user are considered
742 // a single scheduling unit. If we create a TokenFactor and return it as
743 // chain, then the TokenFactor is both a predecessor (operand) of the
744 // user as well as a successor (the TF operands are flagged to the user).
745 // c1, f1 = CopyToReg
746 // c2, f2 = CopyToReg
747 // c3 = TokenFactor c1, c2
750 Chain = Chains[NumRegs-1];
752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
755 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
756 /// operand list. This adds the code marker and includes the number of
757 /// values added into it.
758 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
759 unsigned MatchingIdx, SDLoc dl,
761 std::vector<SDValue> &Ops) const {
762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
764 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
766 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
767 else if (!Regs.empty() &&
768 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
769 // Put the register class of the virtual registers in the flag word. That
770 // way, later passes can recompute register class constraints for inline
771 // assembly as well as normal instructions.
772 // Don't do this for tied operands that can use the regclass information
774 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
775 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
776 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
779 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
782 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
783 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
784 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
785 MVT RegisterVT = RegVTs[Value];
786 for (unsigned i = 0; i != NumRegs; ++i) {
787 assert(Reg < Regs.size() && "Mismatch in # registers expected");
788 unsigned TheReg = Regs[Reg++];
789 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
791 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
792 // If we clobbered the stack pointer, MFI should know about it.
793 assert(DAG.getMachineFunction().getFrameInfo()->
794 hasInlineAsmWithSPAdjust());
800 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
801 const TargetLibraryInfo *li) {
805 DL = DAG.getTarget().getDataLayout();
806 Context = DAG.getContext();
807 LPadToCallSiteMap.clear();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
823 SDNodeOrder = LowestSDNodeOrder;
824 StatepointLowering.clear();
827 /// clearDanglingDebugInfo - Clear the dangling debug information
828 /// map. This function is separated from the clear so that debug
829 /// information that is dangling in a basic block can be properly
830 /// resolved in a different basic block. This allows the
831 /// SelectionDAG to resolve dangling debug information attached
833 void SelectionDAGBuilder::clearDanglingDebugInfo() {
834 DanglingDebugInfoMap.clear();
837 /// getRoot - Return the current virtual root of the Selection DAG,
838 /// flushing any PendingLoad items. This must be done before emitting
839 /// a store or any other node that may need to be ordered after any
840 /// prior load instructions.
842 SDValue SelectionDAGBuilder::getRoot() {
843 if (PendingLoads.empty())
844 return DAG.getRoot();
846 if (PendingLoads.size() == 1) {
847 SDValue Root = PendingLoads[0];
849 PendingLoads.clear();
853 // Otherwise, we have to make a token factor node.
854 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
856 PendingLoads.clear();
861 /// getControlRoot - Similar to getRoot, but instead of flushing all the
862 /// PendingLoad items, flush all the PendingExports items. It is necessary
863 /// to do this before emitting a terminator instruction.
865 SDValue SelectionDAGBuilder::getControlRoot() {
866 SDValue Root = DAG.getRoot();
868 if (PendingExports.empty())
871 // Turn all of the CopyToReg chains into one factored node.
872 if (Root.getOpcode() != ISD::EntryToken) {
873 unsigned i = 0, e = PendingExports.size();
874 for (; i != e; ++i) {
875 assert(PendingExports[i].getNode()->getNumOperands() > 1);
876 if (PendingExports[i].getNode()->getOperand(0) == Root)
877 break; // Don't add the root if we already indirectly depend on it.
881 PendingExports.push_back(Root);
884 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
886 PendingExports.clear();
891 void SelectionDAGBuilder::visit(const Instruction &I) {
892 // Set up outgoing PHI node register values before emitting the terminator.
893 if (isa<TerminatorInst>(&I))
894 HandlePHINodesInSuccessorBlocks(I.getParent());
900 visit(I.getOpcode(), I);
902 if (!isa<TerminatorInst>(&I) && !HasTailCall)
903 CopyToExportRegsIfNeeded(&I);
908 void SelectionDAGBuilder::visitPHI(const PHINode &) {
909 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
912 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
913 // Note: this doesn't use InstVisitor, because it has to work with
914 // ConstantExpr's in addition to instructions.
916 default: llvm_unreachable("Unknown instruction type encountered!");
917 // Build the switch statement using the Instruction.def file.
918 #define HANDLE_INST(NUM, OPCODE, CLASS) \
919 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
920 #include "llvm/IR/Instruction.def"
924 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
925 // generate the debug data structures now that we've seen its definition.
926 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
928 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
930 const DbgValueInst *DI = DDI.getDI();
931 DebugLoc dl = DDI.getdl();
932 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
933 DILocalVariable *Variable = DI->getVariable();
934 DIExpression *Expr = DI->getExpression();
935 assert(Variable->isValidLocationForIntrinsic(dl) &&
936 "Expected inlined-at fields to agree");
937 uint64_t Offset = DI->getOffset();
938 // A dbg.value for an alloca is always indirect.
939 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
942 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
944 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
945 IsIndirect, Offset, dl, DbgSDNodeOrder);
946 DAG.AddDbgValue(SDV, Val.getNode(), false);
949 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
950 DanglingDebugInfoMap[V] = DanglingDebugInfo();
954 /// getCopyFromRegs - If there was virtual register allocated for the value V
955 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
956 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
957 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
960 if (It != FuncInfo.ValueMap.end()) {
961 unsigned InReg = It->second;
962 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
964 SDValue Chain = DAG.getEntryNode();
965 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
966 resolveDanglingDebugInfo(V, Result);
972 /// getValue - Return an SDValue for the given Value.
973 SDValue SelectionDAGBuilder::getValue(const Value *V) {
974 // If we already have an SDValue for this value, use it. It's important
975 // to do this first, so that we don't create a CopyFromReg if we already
976 // have a regular SDValue.
977 SDValue &N = NodeMap[V];
978 if (N.getNode()) return N;
980 // If there's a virtual register allocated and initialized for this
982 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
983 if (copyFromReg.getNode()) {
987 // Otherwise create a new SDValue and remember it.
988 SDValue Val = getValueImpl(V);
990 resolveDanglingDebugInfo(V, Val);
994 // Return true if SDValue exists for the given Value
995 bool SelectionDAGBuilder::findValue(const Value *V) const {
996 return (NodeMap.find(V) != NodeMap.end()) ||
997 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1000 /// getNonRegisterValue - Return an SDValue for the given Value, but
1001 /// don't look in FuncInfo.ValueMap for a virtual register.
1002 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1003 // If we already have an SDValue for this value, use it.
1004 SDValue &N = NodeMap[V];
1005 if (N.getNode()) return N;
1007 // Otherwise create a new SDValue and remember it.
1008 SDValue Val = getValueImpl(V);
1010 resolveDanglingDebugInfo(V, Val);
1014 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1015 /// Create an SDValue for the given value.
1016 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1017 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1019 if (const Constant *C = dyn_cast<Constant>(V)) {
1020 EVT VT = TLI.getValueType(V->getType(), true);
1022 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1023 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1025 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1026 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1028 if (isa<ConstantPointerNull>(C)) {
1029 unsigned AS = V->getType()->getPointerAddressSpace();
1030 return DAG.getConstant(0, getCurSDLoc(), TLI.getPointerTy(AS));
1033 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1034 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1036 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1037 return DAG.getUNDEF(VT);
1039 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1040 visit(CE->getOpcode(), *CE);
1041 SDValue N1 = NodeMap[V];
1042 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1046 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1047 SmallVector<SDValue, 4> Constants;
1048 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1050 SDNode *Val = getValue(*OI).getNode();
1051 // If the operand is an empty aggregate, there are no values.
1053 // Add each leaf value from the operand to the Constants list
1054 // to form a flattened list of all the values.
1055 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1056 Constants.push_back(SDValue(Val, i));
1059 return DAG.getMergeValues(Constants, getCurSDLoc());
1062 if (const ConstantDataSequential *CDS =
1063 dyn_cast<ConstantDataSequential>(C)) {
1064 SmallVector<SDValue, 4> Ops;
1065 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1066 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1067 // Add each leaf value from the operand to the Constants list
1068 // to form a flattened list of all the values.
1069 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1070 Ops.push_back(SDValue(Val, i));
1073 if (isa<ArrayType>(CDS->getType()))
1074 return DAG.getMergeValues(Ops, getCurSDLoc());
1075 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1079 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1080 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1081 "Unknown struct or array constant!");
1083 SmallVector<EVT, 4> ValueVTs;
1084 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1085 unsigned NumElts = ValueVTs.size();
1087 return SDValue(); // empty struct
1088 SmallVector<SDValue, 4> Constants(NumElts);
1089 for (unsigned i = 0; i != NumElts; ++i) {
1090 EVT EltVT = ValueVTs[i];
1091 if (isa<UndefValue>(C))
1092 Constants[i] = DAG.getUNDEF(EltVT);
1093 else if (EltVT.isFloatingPoint())
1094 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1096 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1099 return DAG.getMergeValues(Constants, getCurSDLoc());
1102 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1103 return DAG.getBlockAddress(BA, VT);
1105 VectorType *VecTy = cast<VectorType>(V->getType());
1106 unsigned NumElements = VecTy->getNumElements();
1108 // Now that we know the number and type of the elements, get that number of
1109 // elements into the Ops array based on what kind of constant it is.
1110 SmallVector<SDValue, 16> Ops;
1111 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1112 for (unsigned i = 0; i != NumElements; ++i)
1113 Ops.push_back(getValue(CV->getOperand(i)));
1115 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1116 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1119 if (EltVT.isFloatingPoint())
1120 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1122 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1123 Ops.assign(NumElements, Op);
1126 // Create a BUILD_VECTOR node.
1127 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1130 // If this is a static alloca, generate it as the frameindex instead of
1132 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1133 DenseMap<const AllocaInst*, int>::iterator SI =
1134 FuncInfo.StaticAllocaMap.find(AI);
1135 if (SI != FuncInfo.StaticAllocaMap.end())
1136 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1139 // If this is an instruction which fast-isel has deferred, select it now.
1140 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1141 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1142 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1143 SDValue Chain = DAG.getEntryNode();
1144 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1147 llvm_unreachable("Can't get register for value!");
1150 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1152 SDValue Chain = getControlRoot();
1153 SmallVector<ISD::OutputArg, 8> Outs;
1154 SmallVector<SDValue, 8> OutVals;
1156 if (!FuncInfo.CanLowerReturn) {
1157 unsigned DemoteReg = FuncInfo.DemoteRegister;
1158 const Function *F = I.getParent()->getParent();
1160 // Emit a store of the return value through the virtual register.
1161 // Leave Outs empty so that LowerReturn won't try to load return
1162 // registers the usual way.
1163 SmallVector<EVT, 1> PtrValueVTs;
1164 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1167 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1168 SDValue RetOp = getValue(I.getOperand(0));
1170 SmallVector<EVT, 4> ValueVTs;
1171 SmallVector<uint64_t, 4> Offsets;
1172 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1173 unsigned NumValues = ValueVTs.size();
1175 SmallVector<SDValue, 4> Chains(NumValues);
1176 for (unsigned i = 0; i != NumValues; ++i) {
1177 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1178 RetPtr.getValueType(), RetPtr,
1179 DAG.getIntPtrConstant(Offsets[i],
1182 DAG.getStore(Chain, getCurSDLoc(),
1183 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1184 // FIXME: better loc info would be nice.
1185 Add, MachinePointerInfo(), false, false, 0);
1188 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1189 MVT::Other, Chains);
1190 } else if (I.getNumOperands() != 0) {
1191 SmallVector<EVT, 4> ValueVTs;
1192 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1193 unsigned NumValues = ValueVTs.size();
1195 SDValue RetOp = getValue(I.getOperand(0));
1197 const Function *F = I.getParent()->getParent();
1199 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1200 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1202 ExtendKind = ISD::SIGN_EXTEND;
1203 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1205 ExtendKind = ISD::ZERO_EXTEND;
1207 LLVMContext &Context = F->getContext();
1208 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1211 for (unsigned j = 0; j != NumValues; ++j) {
1212 EVT VT = ValueVTs[j];
1214 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1215 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1217 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1218 MVT PartVT = TLI.getRegisterType(Context, VT);
1219 SmallVector<SDValue, 4> Parts(NumParts);
1220 getCopyToParts(DAG, getCurSDLoc(),
1221 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1222 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1224 // 'inreg' on function refers to return value
1225 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1229 // Propagate extension type if any
1230 if (ExtendKind == ISD::SIGN_EXTEND)
1232 else if (ExtendKind == ISD::ZERO_EXTEND)
1235 for (unsigned i = 0; i < NumParts; ++i) {
1236 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1237 VT, /*isfixed=*/true, 0, 0));
1238 OutVals.push_back(Parts[i]);
1244 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1245 CallingConv::ID CallConv =
1246 DAG.getMachineFunction().getFunction()->getCallingConv();
1247 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1248 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1250 // Verify that the target's LowerReturn behaved as expected.
1251 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1252 "LowerReturn didn't return a valid chain!");
1254 // Update the DAG with the new chain value resulting from return lowering.
1258 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1259 /// created for it, emit nodes to copy the value into the virtual
1261 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1263 if (V->getType()->isEmptyTy())
1266 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1267 if (VMI != FuncInfo.ValueMap.end()) {
1268 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1269 CopyValueToVirtualRegister(V, VMI->second);
1273 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1274 /// the current basic block, add it to ValueMap now so that we'll get a
1276 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1277 // No need to export constants.
1278 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1280 // Already exported?
1281 if (FuncInfo.isExportedInst(V)) return;
1283 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1284 CopyValueToVirtualRegister(V, Reg);
1287 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1288 const BasicBlock *FromBB) {
1289 // The operands of the setcc have to be in this block. We don't know
1290 // how to export them from some other block.
1291 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1292 // Can export from current BB.
1293 if (VI->getParent() == FromBB)
1296 // Is already exported, noop.
1297 return FuncInfo.isExportedInst(V);
1300 // If this is an argument, we can export it if the BB is the entry block or
1301 // if it is already exported.
1302 if (isa<Argument>(V)) {
1303 if (FromBB == &FromBB->getParent()->getEntryBlock())
1306 // Otherwise, can only export this if it is already exported.
1307 return FuncInfo.isExportedInst(V);
1310 // Otherwise, constants can always be exported.
1314 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1315 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1316 const MachineBasicBlock *Dst) const {
1317 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1320 const BasicBlock *SrcBB = Src->getBasicBlock();
1321 const BasicBlock *DstBB = Dst->getBasicBlock();
1322 return BPI->getEdgeWeight(SrcBB, DstBB);
1325 void SelectionDAGBuilder::
1326 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1327 uint32_t Weight /* = 0 */) {
1329 Weight = getEdgeWeight(Src, Dst);
1330 Src->addSuccessor(Dst, Weight);
1334 static bool InBlock(const Value *V, const BasicBlock *BB) {
1335 if (const Instruction *I = dyn_cast<Instruction>(V))
1336 return I->getParent() == BB;
1340 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1341 /// This function emits a branch and is used at the leaves of an OR or an
1342 /// AND operator tree.
1345 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1346 MachineBasicBlock *TBB,
1347 MachineBasicBlock *FBB,
1348 MachineBasicBlock *CurBB,
1349 MachineBasicBlock *SwitchBB,
1352 const BasicBlock *BB = CurBB->getBasicBlock();
1354 // If the leaf of the tree is a comparison, merge the condition into
1356 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1357 // The operands of the cmp have to be in this block. We don't know
1358 // how to export them from some other block. If this is the first block
1359 // of the sequence, no exporting is needed.
1360 if (CurBB == SwitchBB ||
1361 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1362 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1363 ISD::CondCode Condition;
1364 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1365 Condition = getICmpCondCode(IC->getPredicate());
1366 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1367 Condition = getFCmpCondCode(FC->getPredicate());
1368 if (TM.Options.NoNaNsFPMath)
1369 Condition = getFCmpCodeWithoutNaN(Condition);
1371 (void)Condition; // silence warning.
1372 llvm_unreachable("Unknown compare instruction");
1375 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1376 TBB, FBB, CurBB, TWeight, FWeight);
1377 SwitchCases.push_back(CB);
1382 // Create a CaseBlock record representing this branch.
1383 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1384 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1385 SwitchCases.push_back(CB);
1388 /// Scale down both weights to fit into uint32_t.
1389 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1390 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1391 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1392 NewTrue = NewTrue / Scale;
1393 NewFalse = NewFalse / Scale;
1396 /// FindMergedConditions - If Cond is an expression like
1397 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1398 MachineBasicBlock *TBB,
1399 MachineBasicBlock *FBB,
1400 MachineBasicBlock *CurBB,
1401 MachineBasicBlock *SwitchBB,
1402 unsigned Opc, uint32_t TWeight,
1404 // If this node is not part of the or/and tree, emit it as a branch.
1405 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1406 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1407 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1408 BOp->getParent() != CurBB->getBasicBlock() ||
1409 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1410 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1411 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1416 // Create TmpBB after CurBB.
1417 MachineFunction::iterator BBI = CurBB;
1418 MachineFunction &MF = DAG.getMachineFunction();
1419 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1420 CurBB->getParent()->insert(++BBI, TmpBB);
1422 if (Opc == Instruction::Or) {
1423 // Codegen X | Y as:
1432 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1433 // The requirement is that
1434 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1435 // = TrueProb for orignal BB.
1436 // Assuming the orignal weights are A and B, one choice is to set BB1's
1437 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1439 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1440 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1441 // TmpBB, but the math is more complicated.
1443 uint64_t NewTrueWeight = TWeight;
1444 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1445 ScaleWeights(NewTrueWeight, NewFalseWeight);
1446 // Emit the LHS condition.
1447 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1448 NewTrueWeight, NewFalseWeight);
1450 NewTrueWeight = TWeight;
1451 NewFalseWeight = 2 * (uint64_t)FWeight;
1452 ScaleWeights(NewTrueWeight, NewFalseWeight);
1453 // Emit the RHS condition into TmpBB.
1454 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1455 NewTrueWeight, NewFalseWeight);
1457 assert(Opc == Instruction::And && "Unknown merge op!");
1458 // Codegen X & Y as:
1466 // This requires creation of TmpBB after CurBB.
1468 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1469 // The requirement is that
1470 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1471 // = FalseProb for orignal BB.
1472 // Assuming the orignal weights are A and B, one choice is to set BB1's
1473 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1475 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1477 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1478 uint64_t NewFalseWeight = FWeight;
1479 ScaleWeights(NewTrueWeight, NewFalseWeight);
1480 // Emit the LHS condition.
1481 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1482 NewTrueWeight, NewFalseWeight);
1484 NewTrueWeight = 2 * (uint64_t)TWeight;
1485 NewFalseWeight = FWeight;
1486 ScaleWeights(NewTrueWeight, NewFalseWeight);
1487 // Emit the RHS condition into TmpBB.
1488 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1489 NewTrueWeight, NewFalseWeight);
1493 /// If the set of cases should be emitted as a series of branches, return true.
1494 /// If we should emit this as a bunch of and/or'd together conditions, return
1497 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1498 if (Cases.size() != 2) return true;
1500 // If this is two comparisons of the same values or'd or and'd together, they
1501 // will get folded into a single comparison, so don't emit two blocks.
1502 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1503 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1504 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1505 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1509 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1510 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1511 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1512 Cases[0].CC == Cases[1].CC &&
1513 isa<Constant>(Cases[0].CmpRHS) &&
1514 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1515 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1517 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1524 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1525 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1527 // Update machine-CFG edges.
1528 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1530 if (I.isUnconditional()) {
1531 // Update machine-CFG edges.
1532 BrMBB->addSuccessor(Succ0MBB);
1534 // If this is not a fall-through branch or optimizations are switched off,
1536 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1537 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1538 MVT::Other, getControlRoot(),
1539 DAG.getBasicBlock(Succ0MBB)));
1544 // If this condition is one of the special cases we handle, do special stuff
1546 const Value *CondVal = I.getCondition();
1547 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1549 // If this is a series of conditions that are or'd or and'd together, emit
1550 // this as a sequence of branches instead of setcc's with and/or operations.
1551 // As long as jumps are not expensive, this should improve performance.
1552 // For example, instead of something like:
1565 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1566 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1567 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1568 BOp->getOpcode() == Instruction::Or)) {
1569 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1570 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1571 getEdgeWeight(BrMBB, Succ1MBB));
1572 // If the compares in later blocks need to use values not currently
1573 // exported from this block, export them now. This block should always
1574 // be the first entry.
1575 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1577 // Allow some cases to be rejected.
1578 if (ShouldEmitAsBranches(SwitchCases)) {
1579 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1580 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1581 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1584 // Emit the branch for this block.
1585 visitSwitchCase(SwitchCases[0], BrMBB);
1586 SwitchCases.erase(SwitchCases.begin());
1590 // Okay, we decided not to do this, remove any inserted MBB's and clear
1592 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1593 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1595 SwitchCases.clear();
1599 // Create a CaseBlock record representing this branch.
1600 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1601 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1603 // Use visitSwitchCase to actually insert the fast branch sequence for this
1605 visitSwitchCase(CB, BrMBB);
1608 /// visitSwitchCase - Emits the necessary code to represent a single node in
1609 /// the binary search tree resulting from lowering a switch instruction.
1610 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1611 MachineBasicBlock *SwitchBB) {
1613 SDValue CondLHS = getValue(CB.CmpLHS);
1614 SDLoc dl = getCurSDLoc();
1616 // Build the setcc now.
1618 // Fold "(X == true)" to X and "(X == false)" to !X to
1619 // handle common cases produced by branch lowering.
1620 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1621 CB.CC == ISD::SETEQ)
1623 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1624 CB.CC == ISD::SETEQ) {
1625 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1626 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1628 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1630 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1632 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1633 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1635 SDValue CmpOp = getValue(CB.CmpMHS);
1636 EVT VT = CmpOp.getValueType();
1638 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1639 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1642 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1643 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1644 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1645 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1649 // Update successor info
1650 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1651 // TrueBB and FalseBB are always different unless the incoming IR is
1652 // degenerate. This only happens when running llc on weird IR.
1653 if (CB.TrueBB != CB.FalseBB)
1654 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1656 // If the lhs block is the next block, invert the condition so that we can
1657 // fall through to the lhs instead of the rhs block.
1658 if (CB.TrueBB == NextBlock(SwitchBB)) {
1659 std::swap(CB.TrueBB, CB.FalseBB);
1660 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1661 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1664 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1665 MVT::Other, getControlRoot(), Cond,
1666 DAG.getBasicBlock(CB.TrueBB));
1668 // Insert the false branch. Do this even if it's a fall through branch,
1669 // this makes it easier to do DAG optimizations which require inverting
1670 // the branch condition.
1671 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1672 DAG.getBasicBlock(CB.FalseBB));
1674 DAG.setRoot(BrCond);
1677 /// visitJumpTable - Emit JumpTable node in the current MBB
1678 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1679 // Emit the code for the jump table
1680 assert(JT.Reg != -1U && "Should lower JT Header first!");
1681 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1682 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1684 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1685 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1686 MVT::Other, Index.getValue(1),
1688 DAG.setRoot(BrJumpTable);
1691 /// visitJumpTableHeader - This function emits necessary code to produce index
1692 /// in the JumpTable from switch case.
1693 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1694 JumpTableHeader &JTH,
1695 MachineBasicBlock *SwitchBB) {
1696 SDLoc dl = getCurSDLoc();
1698 // Subtract the lowest switch case value from the value being switched on and
1699 // conditional branch to default mbb if the result is greater than the
1700 // difference between smallest and largest cases.
1701 SDValue SwitchOp = getValue(JTH.SValue);
1702 EVT VT = SwitchOp.getValueType();
1703 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1704 DAG.getConstant(JTH.First, dl, VT));
1706 // The SDNode we just created, which holds the value being switched on minus
1707 // the smallest case value, needs to be copied to a virtual register so it
1708 // can be used as an index into the jump table in a subsequent basic block.
1709 // This value may be smaller or larger than the target's pointer type, and
1710 // therefore require extension or truncating.
1711 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1712 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy());
1714 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1715 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1716 JumpTableReg, SwitchOp);
1717 JT.Reg = JumpTableReg;
1719 // Emit the range check for the jump table, and branch to the default block
1720 // for the switch statement if the value being switched on exceeds the largest
1721 // case in the switch.
1723 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1724 Sub.getValueType()),
1725 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT),
1728 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1729 MVT::Other, CopyTo, CMP,
1730 DAG.getBasicBlock(JT.Default));
1732 // Avoid emitting unnecessary branches to the next block.
1733 if (JT.MBB != NextBlock(SwitchBB))
1734 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1735 DAG.getBasicBlock(JT.MBB));
1737 DAG.setRoot(BrCond);
1740 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1741 /// tail spliced into a stack protector check success bb.
1743 /// For a high level explanation of how this fits into the stack protector
1744 /// generation see the comment on the declaration of class
1745 /// StackProtectorDescriptor.
1746 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1747 MachineBasicBlock *ParentBB) {
1749 // First create the loads to the guard/stack slot for the comparison.
1750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1751 EVT PtrTy = TLI.getPointerTy();
1753 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1754 int FI = MFI->getStackProtectorIndex();
1756 const Value *IRGuard = SPD.getGuard();
1757 SDValue GuardPtr = getValue(IRGuard);
1758 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1761 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1764 SDLoc dl = getCurSDLoc();
1766 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1767 // guard value from the virtual register holding the value. Otherwise, emit a
1768 // volatile load to retrieve the stack guard value.
1769 unsigned GuardReg = SPD.getGuardReg();
1771 if (GuardReg && TLI.useLoadStackGuardNode())
1772 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1775 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1776 GuardPtr, MachinePointerInfo(IRGuard, 0),
1777 true, false, false, Align);
1779 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1781 MachinePointerInfo::getFixedStack(FI),
1782 true, false, false, Align);
1784 // Perform the comparison via a subtract/getsetcc.
1785 EVT VT = Guard.getValueType();
1786 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1789 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1790 Sub.getValueType()),
1791 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1793 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1794 // branch to failure MBB.
1795 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1796 MVT::Other, StackSlot.getOperand(0),
1797 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1798 // Otherwise branch to success MBB.
1799 SDValue Br = DAG.getNode(ISD::BR, dl,
1801 DAG.getBasicBlock(SPD.getSuccessMBB()));
1806 /// Codegen the failure basic block for a stack protector check.
1808 /// A failure stack protector machine basic block consists simply of a call to
1809 /// __stack_chk_fail().
1811 /// For a high level explanation of how this fits into the stack protector
1812 /// generation see the comment on the declaration of class
1813 /// StackProtectorDescriptor.
1815 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1818 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1819 nullptr, 0, false, getCurSDLoc(), false, false).second;
1823 /// visitBitTestHeader - This function emits necessary code to produce value
1824 /// suitable for "bit tests"
1825 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1826 MachineBasicBlock *SwitchBB) {
1827 SDLoc dl = getCurSDLoc();
1829 // Subtract the minimum value
1830 SDValue SwitchOp = getValue(B.SValue);
1831 EVT VT = SwitchOp.getValueType();
1832 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1833 DAG.getConstant(B.First, dl, VT));
1836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1838 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1839 Sub.getValueType()),
1840 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1842 // Determine the type of the test operands.
1843 bool UsePtrType = false;
1844 if (!TLI.isTypeLegal(VT))
1847 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1848 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1849 // Switch table case range are encoded into series of masks.
1850 // Just use pointer type, it's guaranteed to fit.
1856 VT = TLI.getPointerTy();
1857 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1860 B.RegVT = VT.getSimpleVT();
1861 B.Reg = FuncInfo.CreateReg(B.RegVT);
1862 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1864 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1866 addSuccessorWithWeight(SwitchBB, B.Default);
1867 addSuccessorWithWeight(SwitchBB, MBB);
1869 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1870 MVT::Other, CopyTo, RangeCmp,
1871 DAG.getBasicBlock(B.Default));
1873 // Avoid emitting unnecessary branches to the next block.
1874 if (MBB != NextBlock(SwitchBB))
1875 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1876 DAG.getBasicBlock(MBB));
1878 DAG.setRoot(BrRange);
1881 /// visitBitTestCase - this function produces one "bit test"
1882 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1883 MachineBasicBlock* NextMBB,
1884 uint32_t BranchWeightToNext,
1887 MachineBasicBlock *SwitchBB) {
1888 SDLoc dl = getCurSDLoc();
1890 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1892 unsigned PopCount = countPopulation(B.Mask);
1893 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1894 if (PopCount == 1) {
1895 // Testing for a single bit; just compare the shift count with what it
1896 // would need to be to shift a 1 bit in that position.
1898 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1899 DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), ISD::SETEQ);
1900 } else if (PopCount == BB.Range) {
1901 // There is only one zero bit in the range, test for it directly.
1903 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1904 DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), ISD::SETNE);
1906 // Make desired shift
1907 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1908 DAG.getConstant(1, dl, VT), ShiftOp);
1910 // Emit bit tests and jumps
1911 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1912 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1913 Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1914 DAG.getConstant(0, dl, VT), ISD::SETNE);
1917 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1918 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1919 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1920 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1922 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1923 MVT::Other, getControlRoot(),
1924 Cmp, DAG.getBasicBlock(B.TargetBB));
1926 // Avoid emitting unnecessary branches to the next block.
1927 if (NextMBB != NextBlock(SwitchBB))
1928 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1929 DAG.getBasicBlock(NextMBB));
1934 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1935 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1937 // Retrieve successors.
1938 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1939 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1941 const Value *Callee(I.getCalledValue());
1942 const Function *Fn = dyn_cast<Function>(Callee);
1943 if (isa<InlineAsm>(Callee))
1945 else if (Fn && Fn->isIntrinsic()) {
1946 switch (Fn->getIntrinsicID()) {
1948 llvm_unreachable("Cannot invoke this intrinsic");
1949 case Intrinsic::donothing:
1950 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1952 case Intrinsic::experimental_patchpoint_void:
1953 case Intrinsic::experimental_patchpoint_i64:
1954 visitPatchpoint(&I, LandingPad);
1956 case Intrinsic::experimental_gc_statepoint:
1957 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1961 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1963 // If the value of the invoke is used outside of its defining block, make it
1964 // available as a virtual register.
1965 // We already took care of the exported value for the statepoint instruction
1966 // during call to the LowerStatepoint.
1967 if (!isStatepoint(I)) {
1968 CopyToExportRegsIfNeeded(&I);
1971 // Update successor info
1972 addSuccessorWithWeight(InvokeMBB, Return);
1973 addSuccessorWithWeight(InvokeMBB, LandingPad);
1975 // Drop into normal successor.
1976 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1977 MVT::Other, getControlRoot(),
1978 DAG.getBasicBlock(Return)));
1981 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1982 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1985 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1986 assert(FuncInfo.MBB->isLandingPad() &&
1987 "Call to landingpad not in landing pad!");
1989 MachineBasicBlock *MBB = FuncInfo.MBB;
1990 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1991 AddLandingPadInfo(LP, MMI, MBB);
1993 // If there aren't registers to copy the values into (e.g., during SjLj
1994 // exceptions), then don't bother to create these DAG nodes.
1995 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1996 if (TLI.getExceptionPointerRegister() == 0 &&
1997 TLI.getExceptionSelectorRegister() == 0)
2000 SmallVector<EVT, 2> ValueVTs;
2001 SDLoc dl = getCurSDLoc();
2002 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2003 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2005 // Get the two live-in registers as SDValues. The physregs have already been
2006 // copied into virtual registers.
2008 if (FuncInfo.ExceptionPointerVirtReg) {
2009 Ops[0] = DAG.getZExtOrTrunc(
2010 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2011 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2014 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy());
2016 Ops[1] = DAG.getZExtOrTrunc(
2017 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2018 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2022 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2023 DAG.getVTList(ValueVTs), Ops);
2028 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2029 MachineBasicBlock *LPadBB) {
2030 SDValue Chain = getControlRoot();
2031 SDLoc dl = getCurSDLoc();
2033 // Get the typeid that we will dispatch on later.
2034 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2035 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2036 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2037 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2038 SDValue Sel = DAG.getConstant(TypeID, dl, TLI.getPointerTy());
2039 Chain = DAG.getCopyToReg(Chain, dl, VReg, Sel);
2041 // Branch to the main landing pad block.
2042 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2043 ClauseMBB->addSuccessor(LPadBB);
2044 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, Chain,
2045 DAG.getBasicBlock(LPadBB)));
2049 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2051 for (const CaseCluster &CC : Clusters)
2052 assert(CC.Low == CC.High && "Input clusters must be single-case");
2055 std::sort(Clusters.begin(), Clusters.end(),
2056 [](const CaseCluster &a, const CaseCluster &b) {
2057 return a.Low->getValue().slt(b.Low->getValue());
2060 // Merge adjacent clusters with the same destination.
2061 const unsigned N = Clusters.size();
2062 unsigned DstIndex = 0;
2063 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2064 CaseCluster &CC = Clusters[SrcIndex];
2065 const ConstantInt *CaseVal = CC.Low;
2066 MachineBasicBlock *Succ = CC.MBB;
2068 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2069 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2070 // If this case has the same successor and is a neighbour, merge it into
2071 // the previous cluster.
2072 Clusters[DstIndex - 1].High = CaseVal;
2073 Clusters[DstIndex - 1].Weight += CC.Weight;
2074 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2076 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2077 sizeof(Clusters[SrcIndex]));
2080 Clusters.resize(DstIndex);
2083 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2084 MachineBasicBlock *Last) {
2086 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2087 if (JTCases[i].first.HeaderBB == First)
2088 JTCases[i].first.HeaderBB = Last;
2090 // Update BitTestCases.
2091 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2092 if (BitTestCases[i].Parent == First)
2093 BitTestCases[i].Parent = Last;
2096 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2097 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2099 // Update machine-CFG edges with unique successors.
2100 SmallSet<BasicBlock*, 32> Done;
2101 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2102 BasicBlock *BB = I.getSuccessor(i);
2103 bool Inserted = Done.insert(BB).second;
2107 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2108 addSuccessorWithWeight(IndirectBrMBB, Succ);
2111 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2112 MVT::Other, getControlRoot(),
2113 getValue(I.getAddress())));
2116 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2117 if (DAG.getTarget().Options.TrapUnreachable)
2118 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2121 void SelectionDAGBuilder::visitFSub(const User &I) {
2122 // -0.0 - X --> fneg
2123 Type *Ty = I.getType();
2124 if (isa<Constant>(I.getOperand(0)) &&
2125 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2126 SDValue Op2 = getValue(I.getOperand(1));
2127 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2128 Op2.getValueType(), Op2));
2132 visitBinary(I, ISD::FSUB);
2135 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2136 SDValue Op1 = getValue(I.getOperand(0));
2137 SDValue Op2 = getValue(I.getOperand(1));
2142 if (const OverflowingBinaryOperator *OFBinOp =
2143 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2144 nuw = OFBinOp->hasNoUnsignedWrap();
2145 nsw = OFBinOp->hasNoSignedWrap();
2147 if (const PossiblyExactOperator *ExactOp =
2148 dyn_cast<const PossiblyExactOperator>(&I))
2149 exact = ExactOp->isExact();
2151 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2152 Op1, Op2, nuw, nsw, exact);
2153 setValue(&I, BinNodeValue);
2156 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2157 SDValue Op1 = getValue(I.getOperand(0));
2158 SDValue Op2 = getValue(I.getOperand(1));
2161 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2163 // Coerce the shift amount to the right type if we can.
2164 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2165 unsigned ShiftSize = ShiftTy.getSizeInBits();
2166 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2167 SDLoc DL = getCurSDLoc();
2169 // If the operand is smaller than the shift count type, promote it.
2170 if (ShiftSize > Op2Size)
2171 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2173 // If the operand is larger than the shift count type but the shift
2174 // count type has enough bits to represent any shift value, truncate
2175 // it now. This is a common case and it exposes the truncate to
2176 // optimization early.
2177 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2178 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2179 // Otherwise we'll need to temporarily settle for some other convenient
2180 // type. Type legalization will make adjustments once the shiftee is split.
2182 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2189 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2191 if (const OverflowingBinaryOperator *OFBinOp =
2192 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2193 nuw = OFBinOp->hasNoUnsignedWrap();
2194 nsw = OFBinOp->hasNoSignedWrap();
2196 if (const PossiblyExactOperator *ExactOp =
2197 dyn_cast<const PossiblyExactOperator>(&I))
2198 exact = ExactOp->isExact();
2201 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2206 void SelectionDAGBuilder::visitSDiv(const User &I) {
2207 SDValue Op1 = getValue(I.getOperand(0));
2208 SDValue Op2 = getValue(I.getOperand(1));
2210 // Turn exact SDivs into multiplications.
2211 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2213 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2214 !isa<ConstantSDNode>(Op1) &&
2215 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2216 setValue(&I, DAG.getTargetLoweringInfo()
2217 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2219 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2223 void SelectionDAGBuilder::visitICmp(const User &I) {
2224 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2225 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2226 predicate = IC->getPredicate();
2227 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2228 predicate = ICmpInst::Predicate(IC->getPredicate());
2229 SDValue Op1 = getValue(I.getOperand(0));
2230 SDValue Op2 = getValue(I.getOperand(1));
2231 ISD::CondCode Opcode = getICmpCondCode(predicate);
2233 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2234 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2237 void SelectionDAGBuilder::visitFCmp(const User &I) {
2238 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2239 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2240 predicate = FC->getPredicate();
2241 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2242 predicate = FCmpInst::Predicate(FC->getPredicate());
2243 SDValue Op1 = getValue(I.getOperand(0));
2244 SDValue Op2 = getValue(I.getOperand(1));
2245 ISD::CondCode Condition = getFCmpCondCode(predicate);
2246 if (TM.Options.NoNaNsFPMath)
2247 Condition = getFCmpCodeWithoutNaN(Condition);
2248 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2249 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2252 void SelectionDAGBuilder::visitSelect(const User &I) {
2253 SmallVector<EVT, 4> ValueVTs;
2254 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2255 unsigned NumValues = ValueVTs.size();
2256 if (NumValues == 0) return;
2258 SmallVector<SDValue, 4> Values(NumValues);
2259 SDValue Cond = getValue(I.getOperand(0));
2260 SDValue TrueVal = getValue(I.getOperand(1));
2261 SDValue FalseVal = getValue(I.getOperand(2));
2262 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2263 ISD::VSELECT : ISD::SELECT;
2265 for (unsigned i = 0; i != NumValues; ++i)
2266 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2267 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2269 SDValue(TrueVal.getNode(),
2270 TrueVal.getResNo() + i),
2271 SDValue(FalseVal.getNode(),
2272 FalseVal.getResNo() + i));
2274 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2275 DAG.getVTList(ValueVTs), Values));
2278 void SelectionDAGBuilder::visitTrunc(const User &I) {
2279 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2280 SDValue N = getValue(I.getOperand(0));
2281 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2282 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2285 void SelectionDAGBuilder::visitZExt(const User &I) {
2286 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2287 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2288 SDValue N = getValue(I.getOperand(0));
2289 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2290 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2293 void SelectionDAGBuilder::visitSExt(const User &I) {
2294 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2295 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2296 SDValue N = getValue(I.getOperand(0));
2297 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2298 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2301 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2302 // FPTrunc is never a no-op cast, no need to check
2303 SDValue N = getValue(I.getOperand(0));
2304 SDLoc dl = getCurSDLoc();
2305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2306 EVT DestVT = TLI.getValueType(I.getType());
2307 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2308 DAG.getTargetConstant(0, dl, TLI.getPointerTy())));
2311 void SelectionDAGBuilder::visitFPExt(const User &I) {
2312 // FPExt is never a no-op cast, no need to check
2313 SDValue N = getValue(I.getOperand(0));
2314 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2315 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2318 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2319 // FPToUI is never a no-op cast, no need to check
2320 SDValue N = getValue(I.getOperand(0));
2321 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2322 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2325 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2326 // FPToSI is never a no-op cast, no need to check
2327 SDValue N = getValue(I.getOperand(0));
2328 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2329 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2332 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2333 // UIToFP is never a no-op cast, no need to check
2334 SDValue N = getValue(I.getOperand(0));
2335 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2336 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2339 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2340 // SIToFP is never a no-op cast, no need to check
2341 SDValue N = getValue(I.getOperand(0));
2342 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2343 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2346 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2347 // What to do depends on the size of the integer and the size of the pointer.
2348 // We can either truncate, zero extend, or no-op, accordingly.
2349 SDValue N = getValue(I.getOperand(0));
2350 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2351 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2354 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2355 // What to do depends on the size of the integer and the size of the pointer.
2356 // We can either truncate, zero extend, or no-op, accordingly.
2357 SDValue N = getValue(I.getOperand(0));
2358 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2359 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2362 void SelectionDAGBuilder::visitBitCast(const User &I) {
2363 SDValue N = getValue(I.getOperand(0));
2364 SDLoc dl = getCurSDLoc();
2365 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2367 // BitCast assures us that source and destination are the same size so this is
2368 // either a BITCAST or a no-op.
2369 if (DestVT != N.getValueType())
2370 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2371 DestVT, N)); // convert types.
2372 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2373 // might fold any kind of constant expression to an integer constant and that
2374 // is not what we are looking for. Only regcognize a bitcast of a genuine
2375 // constant integer as an opaque constant.
2376 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2377 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2380 setValue(&I, N); // noop cast.
2383 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2384 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2385 const Value *SV = I.getOperand(0);
2386 SDValue N = getValue(SV);
2387 EVT DestVT = TLI.getValueType(I.getType());
2389 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2390 unsigned DestAS = I.getType()->getPointerAddressSpace();
2392 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2393 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2398 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2399 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2400 SDValue InVec = getValue(I.getOperand(0));
2401 SDValue InVal = getValue(I.getOperand(1));
2402 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2403 getCurSDLoc(), TLI.getVectorIdxTy());
2404 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2405 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2408 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2409 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2410 SDValue InVec = getValue(I.getOperand(0));
2411 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2412 getCurSDLoc(), TLI.getVectorIdxTy());
2413 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2414 TLI.getValueType(I.getType()), InVec, InIdx));
2417 // Utility for visitShuffleVector - Return true if every element in Mask,
2418 // beginning from position Pos and ending in Pos+Size, falls within the
2419 // specified sequential range [L, L+Pos). or is undef.
2420 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2421 unsigned Pos, unsigned Size, int Low) {
2422 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2423 if (Mask[i] >= 0 && Mask[i] != Low)
2428 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2429 SDValue Src1 = getValue(I.getOperand(0));
2430 SDValue Src2 = getValue(I.getOperand(1));
2432 SmallVector<int, 8> Mask;
2433 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2434 unsigned MaskNumElts = Mask.size();
2436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2437 EVT VT = TLI.getValueType(I.getType());
2438 EVT SrcVT = Src1.getValueType();
2439 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2441 if (SrcNumElts == MaskNumElts) {
2442 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2447 // Normalize the shuffle vector since mask and vector length don't match.
2448 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2449 // Mask is longer than the source vectors and is a multiple of the source
2450 // vectors. We can use concatenate vector to make the mask and vectors
2452 if (SrcNumElts*2 == MaskNumElts) {
2453 // First check for Src1 in low and Src2 in high
2454 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2455 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2456 // The shuffle is concatenating two vectors together.
2457 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2461 // Then check for Src2 in low and Src1 in high
2462 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2463 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2464 // The shuffle is concatenating two vectors together.
2465 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2471 // Pad both vectors with undefs to make them the same length as the mask.
2472 unsigned NumConcat = MaskNumElts / SrcNumElts;
2473 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2474 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2475 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2477 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2478 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2482 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2483 getCurSDLoc(), VT, MOps1);
2484 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2485 getCurSDLoc(), VT, MOps2);
2487 // Readjust mask for new input vector length.
2488 SmallVector<int, 8> MappedOps;
2489 for (unsigned i = 0; i != MaskNumElts; ++i) {
2491 if (Idx >= (int)SrcNumElts)
2492 Idx -= SrcNumElts - MaskNumElts;
2493 MappedOps.push_back(Idx);
2496 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2501 if (SrcNumElts > MaskNumElts) {
2502 // Analyze the access pattern of the vector to see if we can extract
2503 // two subvectors and do the shuffle. The analysis is done by calculating
2504 // the range of elements the mask access on both vectors.
2505 int MinRange[2] = { static_cast<int>(SrcNumElts),
2506 static_cast<int>(SrcNumElts)};
2507 int MaxRange[2] = {-1, -1};
2509 for (unsigned i = 0; i != MaskNumElts; ++i) {
2515 if (Idx >= (int)SrcNumElts) {
2519 if (Idx > MaxRange[Input])
2520 MaxRange[Input] = Idx;
2521 if (Idx < MinRange[Input])
2522 MinRange[Input] = Idx;
2525 // Check if the access is smaller than the vector size and can we find
2526 // a reasonable extract index.
2527 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2529 int StartIdx[2]; // StartIdx to extract from
2530 for (unsigned Input = 0; Input < 2; ++Input) {
2531 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2532 RangeUse[Input] = 0; // Unused
2533 StartIdx[Input] = 0;
2537 // Find a good start index that is a multiple of the mask length. Then
2538 // see if the rest of the elements are in range.
2539 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2540 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2541 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2542 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2545 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2546 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2549 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2550 // Extract appropriate subvector and generate a vector shuffle
2551 for (unsigned Input = 0; Input < 2; ++Input) {
2552 SDValue &Src = Input == 0 ? Src1 : Src2;
2553 if (RangeUse[Input] == 0)
2554 Src = DAG.getUNDEF(VT);
2556 SDLoc dl = getCurSDLoc();
2558 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2559 DAG.getConstant(StartIdx[Input], dl, TLI.getVectorIdxTy()));
2563 // Calculate new mask.
2564 SmallVector<int, 8> MappedOps;
2565 for (unsigned i = 0; i != MaskNumElts; ++i) {
2568 if (Idx < (int)SrcNumElts)
2571 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2573 MappedOps.push_back(Idx);
2576 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2582 // We can't use either concat vectors or extract subvectors so fall back to
2583 // replacing the shuffle with extract and build vector.
2584 // to insert and build vector.
2585 EVT EltVT = VT.getVectorElementType();
2586 EVT IdxVT = TLI.getVectorIdxTy();
2587 SDLoc dl = getCurSDLoc();
2588 SmallVector<SDValue,8> Ops;
2589 for (unsigned i = 0; i != MaskNumElts; ++i) {
2594 Res = DAG.getUNDEF(EltVT);
2596 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2597 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2599 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2600 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2606 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2609 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2610 const Value *Op0 = I.getOperand(0);
2611 const Value *Op1 = I.getOperand(1);
2612 Type *AggTy = I.getType();
2613 Type *ValTy = Op1->getType();
2614 bool IntoUndef = isa<UndefValue>(Op0);
2615 bool FromUndef = isa<UndefValue>(Op1);
2617 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2619 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2620 SmallVector<EVT, 4> AggValueVTs;
2621 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2622 SmallVector<EVT, 4> ValValueVTs;
2623 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2625 unsigned NumAggValues = AggValueVTs.size();
2626 unsigned NumValValues = ValValueVTs.size();
2627 SmallVector<SDValue, 4> Values(NumAggValues);
2629 // Ignore an insertvalue that produces an empty object
2630 if (!NumAggValues) {
2631 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2635 SDValue Agg = getValue(Op0);
2637 // Copy the beginning value(s) from the original aggregate.
2638 for (; i != LinearIndex; ++i)
2639 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2640 SDValue(Agg.getNode(), Agg.getResNo() + i);
2641 // Copy values from the inserted value(s).
2643 SDValue Val = getValue(Op1);
2644 for (; i != LinearIndex + NumValValues; ++i)
2645 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2646 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2648 // Copy remaining value(s) from the original aggregate.
2649 for (; i != NumAggValues; ++i)
2650 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2651 SDValue(Agg.getNode(), Agg.getResNo() + i);
2653 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2654 DAG.getVTList(AggValueVTs), Values));
2657 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2658 const Value *Op0 = I.getOperand(0);
2659 Type *AggTy = Op0->getType();
2660 Type *ValTy = I.getType();
2661 bool OutOfUndef = isa<UndefValue>(Op0);
2663 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2665 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2666 SmallVector<EVT, 4> ValValueVTs;
2667 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2669 unsigned NumValValues = ValValueVTs.size();
2671 // Ignore a extractvalue that produces an empty object
2672 if (!NumValValues) {
2673 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2677 SmallVector<SDValue, 4> Values(NumValValues);
2679 SDValue Agg = getValue(Op0);
2680 // Copy out the selected value(s).
2681 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2682 Values[i - LinearIndex] =
2684 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2685 SDValue(Agg.getNode(), Agg.getResNo() + i);
2687 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2688 DAG.getVTList(ValValueVTs), Values));
2691 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2692 Value *Op0 = I.getOperand(0);
2693 // Note that the pointer operand may be a vector of pointers. Take the scalar
2694 // element which holds a pointer.
2695 Type *Ty = Op0->getType()->getScalarType();
2696 unsigned AS = Ty->getPointerAddressSpace();
2697 SDValue N = getValue(Op0);
2698 SDLoc dl = getCurSDLoc();
2700 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2702 const Value *Idx = *OI;
2703 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2704 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2707 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2708 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2709 DAG.getConstant(Offset, dl, N.getValueType()));
2712 Ty = StTy->getElementType(Field);
2714 Ty = cast<SequentialType>(Ty)->getElementType();
2715 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2716 unsigned PtrSize = PtrTy.getSizeInBits();
2717 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2719 // If this is a constant subscript, handle it quickly.
2720 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2723 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2724 SDValue OffsVal = DAG.getConstant(Offs, dl, PtrTy);
2725 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2729 // N = N + Idx * ElementSize;
2730 SDValue IdxN = getValue(Idx);
2732 // If the index is smaller or larger than intptr_t, truncate or extend
2734 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2736 // If this is a multiply by a power of two, turn it into a shl
2737 // immediately. This is a very common case.
2738 if (ElementSize != 1) {
2739 if (ElementSize.isPowerOf2()) {
2740 unsigned Amt = ElementSize.logBase2();
2741 IdxN = DAG.getNode(ISD::SHL, dl,
2742 N.getValueType(), IdxN,
2743 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2745 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2746 IdxN = DAG.getNode(ISD::MUL, dl,
2747 N.getValueType(), IdxN, Scale);
2751 N = DAG.getNode(ISD::ADD, dl,
2752 N.getValueType(), N, IdxN);
2759 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2760 // If this is a fixed sized alloca in the entry block of the function,
2761 // allocate it statically on the stack.
2762 if (FuncInfo.StaticAllocaMap.count(&I))
2763 return; // getValue will auto-populate this.
2765 SDLoc dl = getCurSDLoc();
2766 Type *Ty = I.getAllocatedType();
2767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2768 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2770 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2773 SDValue AllocSize = getValue(I.getArraySize());
2775 EVT IntPtr = TLI.getPointerTy();
2776 if (AllocSize.getValueType() != IntPtr)
2777 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2779 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2781 DAG.getConstant(TySize, dl, IntPtr));
2783 // Handle alignment. If the requested alignment is less than or equal to
2784 // the stack alignment, ignore it. If the size is greater than or equal to
2785 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2786 unsigned StackAlign =
2787 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2788 if (Align <= StackAlign)
2791 // Round the size of the allocation up to the stack alignment size
2792 // by add SA-1 to the size.
2793 AllocSize = DAG.getNode(ISD::ADD, dl,
2794 AllocSize.getValueType(), AllocSize,
2795 DAG.getIntPtrConstant(StackAlign - 1, dl));
2797 // Mask out the low bits for alignment purposes.
2798 AllocSize = DAG.getNode(ISD::AND, dl,
2799 AllocSize.getValueType(), AllocSize,
2800 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2803 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2804 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2805 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2807 DAG.setRoot(DSA.getValue(1));
2809 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2812 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2814 return visitAtomicLoad(I);
2816 const Value *SV = I.getOperand(0);
2817 SDValue Ptr = getValue(SV);
2819 Type *Ty = I.getType();
2821 bool isVolatile = I.isVolatile();
2822 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2823 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2824 unsigned Alignment = I.getAlignment();
2827 I.getAAMetadata(AAInfo);
2828 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2831 SmallVector<EVT, 4> ValueVTs;
2832 SmallVector<uint64_t, 4> Offsets;
2833 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2834 unsigned NumValues = ValueVTs.size();
2839 bool ConstantMemory = false;
2840 if (isVolatile || NumValues > MaxParallelChains)
2841 // Serialize volatile loads with other side effects.
2843 else if (AA->pointsToConstantMemory(
2844 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2845 // Do not serialize (non-volatile) loads of constant memory with anything.
2846 Root = DAG.getEntryNode();
2847 ConstantMemory = true;
2849 // Do not serialize non-volatile loads against each other.
2850 Root = DAG.getRoot();
2853 SDLoc dl = getCurSDLoc();
2856 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2858 SmallVector<SDValue, 4> Values(NumValues);
2859 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2861 EVT PtrVT = Ptr.getValueType();
2862 unsigned ChainI = 0;
2863 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2864 // Serializing loads here may result in excessive register pressure, and
2865 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2866 // could recover a bit by hoisting nodes upward in the chain by recognizing
2867 // they are side-effect free or do not alias. The optimizer should really
2868 // avoid this case by converting large object/array copies to llvm.memcpy
2869 // (MaxParallelChains should always remain as failsafe).
2870 if (ChainI == MaxParallelChains) {
2871 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2872 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2873 makeArrayRef(Chains.data(), ChainI));
2877 SDValue A = DAG.getNode(ISD::ADD, dl,
2879 DAG.getConstant(Offsets[i], dl, PtrVT));
2880 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2881 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2882 isNonTemporal, isInvariant, Alignment, AAInfo,
2886 Chains[ChainI] = L.getValue(1);
2889 if (!ConstantMemory) {
2890 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2891 makeArrayRef(Chains.data(), ChainI));
2895 PendingLoads.push_back(Chain);
2898 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2899 DAG.getVTList(ValueVTs), Values));
2902 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2904 return visitAtomicStore(I);
2906 const Value *SrcV = I.getOperand(0);
2907 const Value *PtrV = I.getOperand(1);
2909 SmallVector<EVT, 4> ValueVTs;
2910 SmallVector<uint64_t, 4> Offsets;
2911 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2912 ValueVTs, &Offsets);
2913 unsigned NumValues = ValueVTs.size();
2917 // Get the lowered operands. Note that we do this after
2918 // checking if NumResults is zero, because with zero results
2919 // the operands won't have values in the map.
2920 SDValue Src = getValue(SrcV);
2921 SDValue Ptr = getValue(PtrV);
2923 SDValue Root = getRoot();
2924 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2926 EVT PtrVT = Ptr.getValueType();
2927 bool isVolatile = I.isVolatile();
2928 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2929 unsigned Alignment = I.getAlignment();
2930 SDLoc dl = getCurSDLoc();
2933 I.getAAMetadata(AAInfo);
2935 unsigned ChainI = 0;
2936 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2937 // See visitLoad comments.
2938 if (ChainI == MaxParallelChains) {
2939 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2940 makeArrayRef(Chains.data(), ChainI));
2944 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
2945 DAG.getConstant(Offsets[i], dl, PtrVT));
2946 SDValue St = DAG.getStore(Root, dl,
2947 SDValue(Src.getNode(), Src.getResNo() + i),
2948 Add, MachinePointerInfo(PtrV, Offsets[i]),
2949 isVolatile, isNonTemporal, Alignment, AAInfo);
2950 Chains[ChainI] = St;
2953 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2954 makeArrayRef(Chains.data(), ChainI));
2955 DAG.setRoot(StoreNode);
2958 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
2959 SDLoc sdl = getCurSDLoc();
2961 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
2962 Value *PtrOperand = I.getArgOperand(1);
2963 SDValue Ptr = getValue(PtrOperand);
2964 SDValue Src0 = getValue(I.getArgOperand(0));
2965 SDValue Mask = getValue(I.getArgOperand(3));
2966 EVT VT = Src0.getValueType();
2967 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
2969 Alignment = DAG.getEVTAlignment(VT);
2972 I.getAAMetadata(AAInfo);
2974 MachineMemOperand *MMO =
2975 DAG.getMachineFunction().
2976 getMachineMemOperand(MachinePointerInfo(PtrOperand),
2977 MachineMemOperand::MOStore, VT.getStoreSize(),
2979 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
2981 DAG.setRoot(StoreNode);
2982 setValue(&I, StoreNode);
2985 // Gather/scatter receive a vector of pointers.
2986 // This vector of pointers may be represented as a base pointer + vector of
2987 // indices, it depends on GEP and instruction preceeding GEP
2988 // that calculates indices
2989 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
2990 SelectionDAGBuilder* SDB) {
2992 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
2993 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
2994 if (!Gep || Gep->getNumOperands() > 2)
2996 ShuffleVectorInst *ShuffleInst =
2997 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
2998 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
2999 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3000 Instruction::InsertElement)
3003 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3005 SelectionDAG& DAG = SDB->DAG;
3006 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3007 // Check is the Ptr is inside current basic block
3008 // If not, look for the shuffle instruction
3009 if (SDB->findValue(Ptr))
3010 Base = SDB->getValue(Ptr);
3011 else if (SDB->findValue(ShuffleInst)) {
3012 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3013 SDLoc sdl = ShuffleNode;
3014 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3015 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3016 DAG.getConstant(0, sdl, TLI.getVectorIdxTy()));
3017 SDB->setValue(Ptr, Base);
3022 Value *IndexVal = Gep->getOperand(1);
3023 if (SDB->findValue(IndexVal)) {
3024 Index = SDB->getValue(IndexVal);
3026 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3027 IndexVal = Sext->getOperand(0);
3028 if (SDB->findValue(IndexVal))
3029 Index = SDB->getValue(IndexVal);
3036 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3037 SDLoc sdl = getCurSDLoc();
3039 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3040 Value *Ptr = I.getArgOperand(1);
3041 SDValue Src0 = getValue(I.getArgOperand(0));
3042 SDValue Mask = getValue(I.getArgOperand(3));
3043 EVT VT = Src0.getValueType();
3044 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3046 Alignment = DAG.getEVTAlignment(VT);
3047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3050 I.getAAMetadata(AAInfo);
3054 Value *BasePtr = Ptr;
3055 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3057 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3058 MachineMemOperand *MMO = DAG.getMachineFunction().
3059 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3060 MachineMemOperand::MOStore, VT.getStoreSize(),
3063 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3064 Index = getValue(Ptr);
3066 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3067 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3069 DAG.setRoot(Scatter);
3070 setValue(&I, Scatter);
3073 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3074 SDLoc sdl = getCurSDLoc();
3076 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3077 Value *PtrOperand = I.getArgOperand(0);
3078 SDValue Ptr = getValue(PtrOperand);
3079 SDValue Src0 = getValue(I.getArgOperand(3));
3080 SDValue Mask = getValue(I.getArgOperand(2));
3082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3083 EVT VT = TLI.getValueType(I.getType());
3084 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3086 Alignment = DAG.getEVTAlignment(VT);
3089 I.getAAMetadata(AAInfo);
3090 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3092 SDValue InChain = DAG.getRoot();
3093 if (AA->pointsToConstantMemory(
3094 AliasAnalysis::Location(PtrOperand,
3095 AA->getTypeStoreSize(I.getType()),
3097 // Do not serialize (non-volatile) loads of constant memory with anything.
3098 InChain = DAG.getEntryNode();
3101 MachineMemOperand *MMO =
3102 DAG.getMachineFunction().
3103 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3104 MachineMemOperand::MOLoad, VT.getStoreSize(),
3105 Alignment, AAInfo, Ranges);
3107 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3109 SDValue OutChain = Load.getValue(1);
3110 DAG.setRoot(OutChain);
3114 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3115 SDLoc sdl = getCurSDLoc();
3117 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3118 Value *Ptr = I.getArgOperand(0);
3119 SDValue Src0 = getValue(I.getArgOperand(3));
3120 SDValue Mask = getValue(I.getArgOperand(2));
3122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3123 EVT VT = TLI.getValueType(I.getType());
3124 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3126 Alignment = DAG.getEVTAlignment(VT);
3129 I.getAAMetadata(AAInfo);
3130 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3132 SDValue Root = DAG.getRoot();
3135 Value *BasePtr = Ptr;
3136 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3137 bool ConstantMemory = false;
3138 if (UniformBase && AA->pointsToConstantMemory(
3139 AliasAnalysis::Location(BasePtr,
3140 AA->getTypeStoreSize(I.getType()),
3142 // Do not serialize (non-volatile) loads of constant memory with anything.
3143 Root = DAG.getEntryNode();
3144 ConstantMemory = true;
3147 MachineMemOperand *MMO =
3148 DAG.getMachineFunction().
3149 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3150 MachineMemOperand::MOLoad, VT.getStoreSize(),
3151 Alignment, AAInfo, Ranges);
3154 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3155 Index = getValue(Ptr);
3157 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3158 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3161 SDValue OutChain = Gather.getValue(1);
3162 if (!ConstantMemory)
3163 PendingLoads.push_back(OutChain);
3164 setValue(&I, Gather);
3167 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3168 SDLoc dl = getCurSDLoc();
3169 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3170 AtomicOrdering FailureOrder = I.getFailureOrdering();
3171 SynchronizationScope Scope = I.getSynchScope();
3173 SDValue InChain = getRoot();
3175 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3176 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3177 SDValue L = DAG.getAtomicCmpSwap(
3178 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3179 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3180 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3181 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3183 SDValue OutChain = L.getValue(2);
3186 DAG.setRoot(OutChain);
3189 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3190 SDLoc dl = getCurSDLoc();
3192 switch (I.getOperation()) {
3193 default: llvm_unreachable("Unknown atomicrmw operation");
3194 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3195 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3196 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3197 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3198 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3199 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3200 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3201 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3202 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3203 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3204 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3206 AtomicOrdering Order = I.getOrdering();
3207 SynchronizationScope Scope = I.getSynchScope();
3209 SDValue InChain = getRoot();
3212 DAG.getAtomic(NT, dl,
3213 getValue(I.getValOperand()).getSimpleValueType(),
3215 getValue(I.getPointerOperand()),
3216 getValue(I.getValOperand()),
3217 I.getPointerOperand(),
3218 /* Alignment=*/ 0, Order, Scope);
3220 SDValue OutChain = L.getValue(1);
3223 DAG.setRoot(OutChain);
3226 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3227 SDLoc dl = getCurSDLoc();
3228 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3231 Ops[1] = DAG.getConstant(I.getOrdering(), dl, TLI.getPointerTy());
3232 Ops[2] = DAG.getConstant(I.getSynchScope(), dl, TLI.getPointerTy());
3233 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3236 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3237 SDLoc dl = getCurSDLoc();
3238 AtomicOrdering Order = I.getOrdering();
3239 SynchronizationScope Scope = I.getSynchScope();
3241 SDValue InChain = getRoot();
3243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3244 EVT VT = TLI.getValueType(I.getType());
3246 if (I.getAlignment() < VT.getSizeInBits() / 8)
3247 report_fatal_error("Cannot generate unaligned atomic load");
3249 MachineMemOperand *MMO =
3250 DAG.getMachineFunction().
3251 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3252 MachineMemOperand::MOVolatile |
3253 MachineMemOperand::MOLoad,
3255 I.getAlignment() ? I.getAlignment() :
3256 DAG.getEVTAlignment(VT));
3258 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3260 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3261 getValue(I.getPointerOperand()), MMO,
3264 SDValue OutChain = L.getValue(1);
3267 DAG.setRoot(OutChain);
3270 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3271 SDLoc dl = getCurSDLoc();
3273 AtomicOrdering Order = I.getOrdering();
3274 SynchronizationScope Scope = I.getSynchScope();
3276 SDValue InChain = getRoot();
3278 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3279 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3281 if (I.getAlignment() < VT.getSizeInBits() / 8)
3282 report_fatal_error("Cannot generate unaligned atomic store");
3285 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3287 getValue(I.getPointerOperand()),
3288 getValue(I.getValueOperand()),
3289 I.getPointerOperand(), I.getAlignment(),
3292 DAG.setRoot(OutChain);
3295 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3297 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3298 unsigned Intrinsic) {
3299 bool HasChain = !I.doesNotAccessMemory();
3300 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3302 // Build the operand list.
3303 SmallVector<SDValue, 8> Ops;
3304 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3306 // We don't need to serialize loads against other loads.
3307 Ops.push_back(DAG.getRoot());
3309 Ops.push_back(getRoot());
3313 // Info is set by getTgtMemInstrinsic
3314 TargetLowering::IntrinsicInfo Info;
3315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3316 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3318 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3319 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3320 Info.opc == ISD::INTRINSIC_W_CHAIN)
3321 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3322 TLI.getPointerTy()));
3324 // Add all operands of the call to the operand list.
3325 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3326 SDValue Op = getValue(I.getArgOperand(i));
3330 SmallVector<EVT, 4> ValueVTs;
3331 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3334 ValueVTs.push_back(MVT::Other);
3336 SDVTList VTs = DAG.getVTList(ValueVTs);
3340 if (IsTgtIntrinsic) {
3341 // This is target intrinsic that touches memory
3342 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3343 VTs, Ops, Info.memVT,
3344 MachinePointerInfo(Info.ptrVal, Info.offset),
3345 Info.align, Info.vol,
3346 Info.readMem, Info.writeMem, Info.size);
3347 } else if (!HasChain) {
3348 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3349 } else if (!I.getType()->isVoidTy()) {
3350 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3352 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3356 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3358 PendingLoads.push_back(Chain);
3363 if (!I.getType()->isVoidTy()) {
3364 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3365 EVT VT = TLI.getValueType(PTy);
3366 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3369 setValue(&I, Result);
3373 /// GetSignificand - Get the significand and build it into a floating-point
3374 /// number with exponent of 1:
3376 /// Op = (Op & 0x007fffff) | 0x3f800000;
3378 /// where Op is the hexadecimal representation of floating point value.
3380 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3381 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3382 DAG.getConstant(0x007fffff, dl, MVT::i32));
3383 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3384 DAG.getConstant(0x3f800000, dl, MVT::i32));
3385 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3388 /// GetExponent - Get the exponent:
3390 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3392 /// where Op is the hexadecimal representation of floating point value.
3394 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3396 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3397 DAG.getConstant(0x7f800000, dl, MVT::i32));
3398 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3399 DAG.getConstant(23, dl, TLI.getPointerTy()));
3400 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3401 DAG.getConstant(127, dl, MVT::i32));
3402 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3405 /// getF32Constant - Get 32-bit floating point constant.
3407 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3408 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3412 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3413 SelectionDAG &DAG) {
3414 // IntegerPartOfX = ((int32_t)(t0);
3415 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3417 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3418 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3419 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3421 // IntegerPartOfX <<= 23;
3422 IntegerPartOfX = DAG.getNode(
3423 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3424 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy()));
3426 SDValue TwoToFractionalPartOfX;
3427 if (LimitFloatPrecision <= 6) {
3428 // For floating-point precision of 6:
3430 // TwoToFractionalPartOfX =
3432 // (0.735607626f + 0.252464424f * x) * x;
3434 // error 0.0144103317, which is 6 bits
3435 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3436 getF32Constant(DAG, 0x3e814304, dl));
3437 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3438 getF32Constant(DAG, 0x3f3c50c8, dl));
3439 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3440 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3441 getF32Constant(DAG, 0x3f7f5e7e, dl));
3442 } else if (LimitFloatPrecision <= 12) {
3443 // For floating-point precision of 12:
3445 // TwoToFractionalPartOfX =
3448 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3450 // error 0.000107046256, which is 13 to 14 bits
3451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3452 getF32Constant(DAG, 0x3da235e3, dl));
3453 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3454 getF32Constant(DAG, 0x3e65b8f3, dl));
3455 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3456 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3457 getF32Constant(DAG, 0x3f324b07, dl));
3458 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3459 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3460 getF32Constant(DAG, 0x3f7ff8fd, dl));
3461 } else { // LimitFloatPrecision <= 18
3462 // For floating-point precision of 18:
3464 // TwoToFractionalPartOfX =
3468 // (0.554906021e-1f +
3469 // (0.961591928e-2f +
3470 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3471 // error 2.47208000*10^(-7), which is better than 18 bits
3472 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3473 getF32Constant(DAG, 0x3924b03e, dl));
3474 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3475 getF32Constant(DAG, 0x3ab24b87, dl));
3476 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3477 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3478 getF32Constant(DAG, 0x3c1d8c17, dl));
3479 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3480 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3481 getF32Constant(DAG, 0x3d634a1d, dl));
3482 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3483 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3484 getF32Constant(DAG, 0x3e75fe14, dl));
3485 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3486 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3487 getF32Constant(DAG, 0x3f317234, dl));
3488 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3489 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3490 getF32Constant(DAG, 0x3f800000, dl));
3493 // Add the exponent into the result in integer domain.
3494 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3495 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3496 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3499 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3500 /// limited-precision mode.
3501 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3502 const TargetLowering &TLI) {
3503 if (Op.getValueType() == MVT::f32 &&
3504 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3506 // Put the exponent in the right bit position for later addition to the
3509 // #define LOG2OFe 1.4426950f
3510 // t0 = Op * LOG2OFe
3511 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3512 getF32Constant(DAG, 0x3fb8aa3b, dl));
3513 return getLimitedPrecisionExp2(t0, dl, DAG);
3516 // No special expansion.
3517 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3520 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3521 /// limited-precision mode.
3522 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3523 const TargetLowering &TLI) {
3524 if (Op.getValueType() == MVT::f32 &&
3525 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3526 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3528 // Scale the exponent by log(2) [0.69314718f].
3529 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3530 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3531 getF32Constant(DAG, 0x3f317218, dl));
3533 // Get the significand and build it into a floating-point number with
3535 SDValue X = GetSignificand(DAG, Op1, dl);
3537 SDValue LogOfMantissa;
3538 if (LimitFloatPrecision <= 6) {
3539 // For floating-point precision of 6:
3543 // (1.4034025f - 0.23903021f * x) * x;
3545 // error 0.0034276066, which is better than 8 bits
3546 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3547 getF32Constant(DAG, 0xbe74c456, dl));
3548 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3549 getF32Constant(DAG, 0x3fb3a2b1, dl));
3550 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3551 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3552 getF32Constant(DAG, 0x3f949a29, dl));
3553 } else if (LimitFloatPrecision <= 12) {
3554 // For floating-point precision of 12:
3560 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3562 // error 0.000061011436, which is 14 bits
3563 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3564 getF32Constant(DAG, 0xbd67b6d6, dl));
3565 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3566 getF32Constant(DAG, 0x3ee4f4b8, dl));
3567 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3568 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3569 getF32Constant(DAG, 0x3fbc278b, dl));
3570 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3571 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3572 getF32Constant(DAG, 0x40348e95, dl));
3573 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3574 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3575 getF32Constant(DAG, 0x3fdef31a, dl));
3576 } else { // LimitFloatPrecision <= 18
3577 // For floating-point precision of 18:
3585 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3587 // error 0.0000023660568, which is better than 18 bits
3588 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3589 getF32Constant(DAG, 0xbc91e5ac, dl));
3590 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3591 getF32Constant(DAG, 0x3e4350aa, dl));
3592 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3593 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3594 getF32Constant(DAG, 0x3f60d3e3, dl));
3595 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3596 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3597 getF32Constant(DAG, 0x4011cdf0, dl));
3598 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3599 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3600 getF32Constant(DAG, 0x406cfd1c, dl));
3601 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3602 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3603 getF32Constant(DAG, 0x408797cb, dl));
3604 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3605 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3606 getF32Constant(DAG, 0x4006dcab, dl));
3609 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3612 // No special expansion.
3613 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3616 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3617 /// limited-precision mode.
3618 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3619 const TargetLowering &TLI) {
3620 if (Op.getValueType() == MVT::f32 &&
3621 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3622 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3624 // Get the exponent.
3625 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3627 // Get the significand and build it into a floating-point number with
3629 SDValue X = GetSignificand(DAG, Op1, dl);
3631 // Different possible minimax approximations of significand in
3632 // floating-point for various degrees of accuracy over [1,2].
3633 SDValue Log2ofMantissa;
3634 if (LimitFloatPrecision <= 6) {
3635 // For floating-point precision of 6:
3637 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3639 // error 0.0049451742, which is more than 7 bits
3640 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3641 getF32Constant(DAG, 0xbeb08fe0, dl));
3642 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3643 getF32Constant(DAG, 0x40019463, dl));
3644 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3645 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3646 getF32Constant(DAG, 0x3fd6633d, dl));
3647 } else if (LimitFloatPrecision <= 12) {
3648 // For floating-point precision of 12:
3654 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3656 // error 0.0000876136000, which is better than 13 bits
3657 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3658 getF32Constant(DAG, 0xbda7262e, dl));
3659 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3660 getF32Constant(DAG, 0x3f25280b, dl));
3661 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3662 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3663 getF32Constant(DAG, 0x4007b923, dl));
3664 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3665 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3666 getF32Constant(DAG, 0x40823e2f, dl));
3667 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3668 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3669 getF32Constant(DAG, 0x4020d29c, dl));
3670 } else { // LimitFloatPrecision <= 18
3671 // For floating-point precision of 18:
3680 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3682 // error 0.0000018516, which is better than 18 bits
3683 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3684 getF32Constant(DAG, 0xbcd2769e, dl));
3685 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3686 getF32Constant(DAG, 0x3e8ce0b9, dl));
3687 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3688 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3689 getF32Constant(DAG, 0x3fa22ae7, dl));
3690 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3691 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3692 getF32Constant(DAG, 0x40525723, dl));
3693 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3694 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3695 getF32Constant(DAG, 0x40aaf200, dl));
3696 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3697 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3698 getF32Constant(DAG, 0x40c39dad, dl));
3699 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3700 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3701 getF32Constant(DAG, 0x4042902c, dl));
3704 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3707 // No special expansion.
3708 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3711 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3712 /// limited-precision mode.
3713 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3714 const TargetLowering &TLI) {
3715 if (Op.getValueType() == MVT::f32 &&
3716 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3717 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3719 // Scale the exponent by log10(2) [0.30102999f].
3720 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3721 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3722 getF32Constant(DAG, 0x3e9a209a, dl));
3724 // Get the significand and build it into a floating-point number with
3726 SDValue X = GetSignificand(DAG, Op1, dl);
3728 SDValue Log10ofMantissa;
3729 if (LimitFloatPrecision <= 6) {
3730 // For floating-point precision of 6:
3732 // Log10ofMantissa =
3734 // (0.60948995f - 0.10380950f * x) * x;
3736 // error 0.0014886165, which is 6 bits
3737 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3738 getF32Constant(DAG, 0xbdd49a13, dl));
3739 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3740 getF32Constant(DAG, 0x3f1c0789, dl));
3741 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3742 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3743 getF32Constant(DAG, 0x3f011300, dl));
3744 } else if (LimitFloatPrecision <= 12) {
3745 // For floating-point precision of 12:
3747 // Log10ofMantissa =
3750 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3752 // error 0.00019228036, which is better than 12 bits
3753 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3754 getF32Constant(DAG, 0x3d431f31, dl));
3755 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3756 getF32Constant(DAG, 0x3ea21fb2, dl));
3757 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3758 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3f6ae232, dl));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x3f25f7c3, dl));
3763 } else { // LimitFloatPrecision <= 18
3764 // For floating-point precision of 18:
3766 // Log10ofMantissa =
3771 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3773 // error 0.0000037995730, which is better than 18 bits
3774 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3775 getF32Constant(DAG, 0x3c5d51ce, dl));
3776 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3777 getF32Constant(DAG, 0x3e00685a, dl));
3778 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3779 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3780 getF32Constant(DAG, 0x3efb6798, dl));
3781 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3782 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3783 getF32Constant(DAG, 0x3f88d192, dl));
3784 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3785 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3786 getF32Constant(DAG, 0x3fc4316c, dl));
3787 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3788 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3789 getF32Constant(DAG, 0x3f57ce70, dl));
3792 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3795 // No special expansion.
3796 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3799 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3800 /// limited-precision mode.
3801 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3802 const TargetLowering &TLI) {
3803 if (Op.getValueType() == MVT::f32 &&
3804 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3805 return getLimitedPrecisionExp2(Op, dl, DAG);
3807 // No special expansion.
3808 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3811 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3812 /// limited-precision mode with x == 10.0f.
3813 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3814 SelectionDAG &DAG, const TargetLowering &TLI) {
3815 bool IsExp10 = false;
3816 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3817 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3818 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3820 IsExp10 = LHSC->isExactlyValue(Ten);
3825 // Put the exponent in the right bit position for later addition to the
3828 // #define LOG2OF10 3.3219281f
3829 // t0 = Op * LOG2OF10;
3830 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3831 getF32Constant(DAG, 0x40549a78, dl));
3832 return getLimitedPrecisionExp2(t0, dl, DAG);
3835 // No special expansion.
3836 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3840 /// ExpandPowI - Expand a llvm.powi intrinsic.
3841 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3842 SelectionDAG &DAG) {
3843 // If RHS is a constant, we can expand this out to a multiplication tree,
3844 // otherwise we end up lowering to a call to __powidf2 (for example). When
3845 // optimizing for size, we only want to do this if the expansion would produce
3846 // a small number of multiplies, otherwise we do the full expansion.
3847 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3848 // Get the exponent as a positive value.
3849 unsigned Val = RHSC->getSExtValue();
3850 if ((int)Val < 0) Val = -Val;
3852 // powi(x, 0) -> 1.0
3854 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3856 const Function *F = DAG.getMachineFunction().getFunction();
3857 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3858 // If optimizing for size, don't insert too many multiplies. This
3859 // inserts up to 5 multiplies.
3860 countPopulation(Val) + Log2_32(Val) < 7) {
3861 // We use the simple binary decomposition method to generate the multiply
3862 // sequence. There are more optimal ways to do this (for example,
3863 // powi(x,15) generates one more multiply than it should), but this has
3864 // the benefit of being both really simple and much better than a libcall.
3865 SDValue Res; // Logically starts equal to 1.0
3866 SDValue CurSquare = LHS;
3870 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3872 Res = CurSquare; // 1.0*CurSquare.
3875 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3876 CurSquare, CurSquare);
3880 // If the original was negative, invert the result, producing 1/(x*x*x).
3881 if (RHSC->getSExtValue() < 0)
3882 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3883 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3888 // Otherwise, expand to a libcall.
3889 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3892 // getTruncatedArgReg - Find underlying register used for an truncated
3894 static unsigned getTruncatedArgReg(const SDValue &N) {
3895 if (N.getOpcode() != ISD::TRUNCATE)
3898 const SDValue &Ext = N.getOperand(0);
3899 if (Ext.getOpcode() == ISD::AssertZext ||
3900 Ext.getOpcode() == ISD::AssertSext) {
3901 const SDValue &CFR = Ext.getOperand(0);
3902 if (CFR.getOpcode() == ISD::CopyFromReg)
3903 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3904 if (CFR.getOpcode() == ISD::TRUNCATE)
3905 return getTruncatedArgReg(CFR);
3910 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3911 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3912 /// At the end of instruction selection, they will be inserted to the entry BB.
3913 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3914 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
3915 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3916 const Argument *Arg = dyn_cast<Argument>(V);
3920 MachineFunction &MF = DAG.getMachineFunction();
3921 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3923 // Ignore inlined function arguments here.
3925 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3926 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
3929 Optional<MachineOperand> Op;
3930 // Some arguments' frame index is recorded during argument lowering.
3931 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
3932 Op = MachineOperand::CreateFI(FI);
3934 if (!Op && N.getNode()) {
3936 if (N.getOpcode() == ISD::CopyFromReg)
3937 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3939 Reg = getTruncatedArgReg(N);
3940 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3941 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3942 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3947 Op = MachineOperand::CreateReg(Reg, false);
3951 // Check if ValueMap has reg number.
3952 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3953 if (VMI != FuncInfo.ValueMap.end())
3954 Op = MachineOperand::CreateReg(VMI->second, false);
3957 if (!Op && N.getNode())
3958 // Check if frame index is available.
3959 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
3960 if (FrameIndexSDNode *FINode =
3961 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
3962 Op = MachineOperand::CreateFI(FINode->getIndex());
3967 assert(Variable->isValidLocationForIntrinsic(DL) &&
3968 "Expected inlined-at fields to agree");
3970 FuncInfo.ArgDbgValues.push_back(
3971 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
3972 Op->getReg(), Offset, Variable, Expr));
3974 FuncInfo.ArgDbgValues.push_back(
3975 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
3978 .addMetadata(Variable)
3979 .addMetadata(Expr));
3984 // VisualStudio defines setjmp as _setjmp
3985 #if defined(_MSC_VER) && defined(setjmp) && \
3986 !defined(setjmp_undefined_for_msvc)
3987 # pragma push_macro("setjmp")
3989 # define setjmp_undefined_for_msvc
3992 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3993 /// we want to emit this as a call to a named external function, return the name
3994 /// otherwise lower it and return null.
3996 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3998 SDLoc sdl = getCurSDLoc();
3999 DebugLoc dl = getCurDebugLoc();
4002 switch (Intrinsic) {
4004 // By default, turn this into a target intrinsic node.
4005 visitTargetIntrinsic(I, Intrinsic);
4007 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4008 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4009 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4010 case Intrinsic::returnaddress:
4011 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4012 getValue(I.getArgOperand(0))));
4014 case Intrinsic::frameaddress:
4015 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4016 getValue(I.getArgOperand(0))));
4018 case Intrinsic::read_register: {
4019 Value *Reg = I.getArgOperand(0);
4021 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4022 EVT VT = TLI.getValueType(I.getType());
4023 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4026 case Intrinsic::write_register: {
4027 Value *Reg = I.getArgOperand(0);
4028 Value *RegValue = I.getArgOperand(1);
4029 SDValue Chain = getValue(RegValue).getOperand(0);
4031 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4032 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4033 RegName, getValue(RegValue)));
4036 case Intrinsic::setjmp:
4037 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4038 case Intrinsic::longjmp:
4039 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4040 case Intrinsic::memcpy: {
4041 // FIXME: this definition of "user defined address space" is x86-specific
4042 // Assert for address < 256 since we support only user defined address
4044 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4046 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4048 "Unknown address space");
4049 SDValue Op1 = getValue(I.getArgOperand(0));
4050 SDValue Op2 = getValue(I.getArgOperand(1));
4051 SDValue Op3 = getValue(I.getArgOperand(2));
4052 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4054 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4055 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4056 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4057 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4059 MachinePointerInfo(I.getArgOperand(0)),
4060 MachinePointerInfo(I.getArgOperand(1)));
4061 updateDAGForMaybeTailCall(MC);
4064 case Intrinsic::memset: {
4065 // FIXME: this definition of "user defined address space" is x86-specific
4066 // Assert for address < 256 since we support only user defined address
4068 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4070 "Unknown address space");
4071 SDValue Op1 = getValue(I.getArgOperand(0));
4072 SDValue Op2 = getValue(I.getArgOperand(1));
4073 SDValue Op3 = getValue(I.getArgOperand(2));
4074 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4076 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4077 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4078 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4079 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4080 isTC, MachinePointerInfo(I.getArgOperand(0)));
4081 updateDAGForMaybeTailCall(MS);
4084 case Intrinsic::memmove: {
4085 // FIXME: this definition of "user defined address space" is x86-specific
4086 // Assert for address < 256 since we support only user defined address
4088 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4090 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4092 "Unknown address space");
4093 SDValue Op1 = getValue(I.getArgOperand(0));
4094 SDValue Op2 = getValue(I.getArgOperand(1));
4095 SDValue Op3 = getValue(I.getArgOperand(2));
4096 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4098 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4099 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4100 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4101 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4102 isTC, MachinePointerInfo(I.getArgOperand(0)),
4103 MachinePointerInfo(I.getArgOperand(1)));
4104 updateDAGForMaybeTailCall(MM);
4107 case Intrinsic::dbg_declare: {
4108 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4109 DILocalVariable *Variable = DI.getVariable();
4110 DIExpression *Expression = DI.getExpression();
4111 const Value *Address = DI.getAddress();
4112 assert(Variable && "Missing variable");
4114 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4118 // Check if address has undef value.
4119 if (isa<UndefValue>(Address) ||
4120 (Address->use_empty() && !isa<Argument>(Address))) {
4121 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4125 SDValue &N = NodeMap[Address];
4126 if (!N.getNode() && isa<Argument>(Address))
4127 // Check unused arguments map.
4128 N = UnusedArgNodeMap[Address];
4131 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4132 Address = BCI->getOperand(0);
4133 // Parameters are handled specially.
4134 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4135 isa<Argument>(Address);
4137 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4139 if (isParameter && !AI) {
4140 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4142 // Byval parameter. We have a frame index at this point.
4143 SDV = DAG.getFrameIndexDbgValue(
4144 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4146 // Address is an argument, so try to emit its dbg value using
4147 // virtual register info from the FuncInfo.ValueMap.
4148 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4153 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4154 true, 0, dl, SDNodeOrder);
4156 // Can't do anything with other non-AI cases yet.
4157 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4158 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4159 DEBUG(Address->dump());
4162 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4164 // If Address is an argument then try to emit its dbg value using
4165 // virtual register info from the FuncInfo.ValueMap.
4166 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4168 // If variable is pinned by a alloca in dominating bb then
4169 // use StaticAllocaMap.
4170 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4171 if (AI->getParent() != DI.getParent()) {
4172 DenseMap<const AllocaInst*, int>::iterator SI =
4173 FuncInfo.StaticAllocaMap.find(AI);
4174 if (SI != FuncInfo.StaticAllocaMap.end()) {
4175 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4176 0, dl, SDNodeOrder);
4177 DAG.AddDbgValue(SDV, nullptr, false);
4182 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4187 case Intrinsic::dbg_value: {
4188 const DbgValueInst &DI = cast<DbgValueInst>(I);
4189 assert(DI.getVariable() && "Missing variable");
4191 DILocalVariable *Variable = DI.getVariable();
4192 DIExpression *Expression = DI.getExpression();
4193 uint64_t Offset = DI.getOffset();
4194 const Value *V = DI.getValue();
4199 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4200 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4202 DAG.AddDbgValue(SDV, nullptr, false);
4204 // Do not use getValue() in here; we don't want to generate code at
4205 // this point if it hasn't been done yet.
4206 SDValue N = NodeMap[V];
4207 if (!N.getNode() && isa<Argument>(V))
4208 // Check unused arguments map.
4209 N = UnusedArgNodeMap[V];
4211 // A dbg.value for an alloca is always indirect.
4212 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4213 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4215 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4216 IsIndirect, Offset, dl, SDNodeOrder);
4217 DAG.AddDbgValue(SDV, N.getNode(), false);
4219 } else if (!V->use_empty() ) {
4220 // Do not call getValue(V) yet, as we don't want to generate code.
4221 // Remember it for later.
4222 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4223 DanglingDebugInfoMap[V] = DDI;
4225 // We may expand this to cover more cases. One case where we have no
4226 // data available is an unreferenced parameter.
4227 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4231 // Build a debug info table entry.
4232 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4233 V = BCI->getOperand(0);
4234 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4235 // Don't handle byval struct arguments or VLAs, for example.
4237 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4238 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4241 DenseMap<const AllocaInst*, int>::iterator SI =
4242 FuncInfo.StaticAllocaMap.find(AI);
4243 if (SI == FuncInfo.StaticAllocaMap.end())
4244 return nullptr; // VLAs.
4248 case Intrinsic::eh_typeid_for: {
4249 // Find the type id for the given typeinfo.
4250 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4251 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4252 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4257 case Intrinsic::eh_return_i32:
4258 case Intrinsic::eh_return_i64:
4259 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4260 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4263 getValue(I.getArgOperand(0)),
4264 getValue(I.getArgOperand(1))));
4266 case Intrinsic::eh_unwind_init:
4267 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4269 case Intrinsic::eh_dwarf_cfa: {
4270 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4271 TLI.getPointerTy());
4272 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4273 CfaArg.getValueType(),
4274 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4275 CfaArg.getValueType()),
4277 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4278 DAG.getConstant(0, sdl, TLI.getPointerTy()));
4279 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4283 case Intrinsic::eh_sjlj_callsite: {
4284 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4285 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4286 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4287 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4289 MMI.setCurrentCallSite(CI->getZExtValue());
4292 case Intrinsic::eh_sjlj_functioncontext: {
4293 // Get and store the index of the function context.
4294 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4296 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4297 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4298 MFI->setFunctionContextIndex(FI);
4301 case Intrinsic::eh_sjlj_setjmp: {
4304 Ops[1] = getValue(I.getArgOperand(0));
4305 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4306 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4307 setValue(&I, Op.getValue(0));
4308 DAG.setRoot(Op.getValue(1));
4311 case Intrinsic::eh_sjlj_longjmp: {
4312 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4313 getRoot(), getValue(I.getArgOperand(0))));
4317 case Intrinsic::masked_gather:
4318 visitMaskedGather(I);
4320 case Intrinsic::masked_load:
4323 case Intrinsic::masked_scatter:
4324 visitMaskedScatter(I);
4326 case Intrinsic::masked_store:
4327 visitMaskedStore(I);
4329 case Intrinsic::x86_mmx_pslli_w:
4330 case Intrinsic::x86_mmx_pslli_d:
4331 case Intrinsic::x86_mmx_pslli_q:
4332 case Intrinsic::x86_mmx_psrli_w:
4333 case Intrinsic::x86_mmx_psrli_d:
4334 case Intrinsic::x86_mmx_psrli_q:
4335 case Intrinsic::x86_mmx_psrai_w:
4336 case Intrinsic::x86_mmx_psrai_d: {
4337 SDValue ShAmt = getValue(I.getArgOperand(1));
4338 if (isa<ConstantSDNode>(ShAmt)) {
4339 visitTargetIntrinsic(I, Intrinsic);
4342 unsigned NewIntrinsic = 0;
4343 EVT ShAmtVT = MVT::v2i32;
4344 switch (Intrinsic) {
4345 case Intrinsic::x86_mmx_pslli_w:
4346 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4348 case Intrinsic::x86_mmx_pslli_d:
4349 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4351 case Intrinsic::x86_mmx_pslli_q:
4352 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4354 case Intrinsic::x86_mmx_psrli_w:
4355 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4357 case Intrinsic::x86_mmx_psrli_d:
4358 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4360 case Intrinsic::x86_mmx_psrli_q:
4361 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4363 case Intrinsic::x86_mmx_psrai_w:
4364 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4366 case Intrinsic::x86_mmx_psrai_d:
4367 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4369 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4372 // The vector shift intrinsics with scalars uses 32b shift amounts but
4373 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4375 // We must do this early because v2i32 is not a legal type.
4378 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4379 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4380 EVT DestVT = TLI.getValueType(I.getType());
4381 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4382 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4383 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4384 getValue(I.getArgOperand(0)), ShAmt);
4388 case Intrinsic::convertff:
4389 case Intrinsic::convertfsi:
4390 case Intrinsic::convertfui:
4391 case Intrinsic::convertsif:
4392 case Intrinsic::convertuif:
4393 case Intrinsic::convertss:
4394 case Intrinsic::convertsu:
4395 case Intrinsic::convertus:
4396 case Intrinsic::convertuu: {
4397 ISD::CvtCode Code = ISD::CVT_INVALID;
4398 switch (Intrinsic) {
4399 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4400 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4401 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4402 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4403 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4404 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4405 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4406 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4407 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4408 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4410 EVT DestVT = TLI.getValueType(I.getType());
4411 const Value *Op1 = I.getArgOperand(0);
4412 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4413 DAG.getValueType(DestVT),
4414 DAG.getValueType(getValue(Op1).getValueType()),
4415 getValue(I.getArgOperand(1)),
4416 getValue(I.getArgOperand(2)),
4421 case Intrinsic::powi:
4422 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4423 getValue(I.getArgOperand(1)), DAG));
4425 case Intrinsic::log:
4426 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4428 case Intrinsic::log2:
4429 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4431 case Intrinsic::log10:
4432 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4434 case Intrinsic::exp:
4435 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4437 case Intrinsic::exp2:
4438 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4440 case Intrinsic::pow:
4441 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4442 getValue(I.getArgOperand(1)), DAG, TLI));
4444 case Intrinsic::sqrt:
4445 case Intrinsic::fabs:
4446 case Intrinsic::sin:
4447 case Intrinsic::cos:
4448 case Intrinsic::floor:
4449 case Intrinsic::ceil:
4450 case Intrinsic::trunc:
4451 case Intrinsic::rint:
4452 case Intrinsic::nearbyint:
4453 case Intrinsic::round: {
4455 switch (Intrinsic) {
4456 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4457 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4458 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4459 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4460 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4461 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4462 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4463 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4464 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4465 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4466 case Intrinsic::round: Opcode = ISD::FROUND; break;
4469 setValue(&I, DAG.getNode(Opcode, sdl,
4470 getValue(I.getArgOperand(0)).getValueType(),
4471 getValue(I.getArgOperand(0))));
4474 case Intrinsic::minnum:
4475 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4476 getValue(I.getArgOperand(0)).getValueType(),
4477 getValue(I.getArgOperand(0)),
4478 getValue(I.getArgOperand(1))));
4480 case Intrinsic::maxnum:
4481 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4482 getValue(I.getArgOperand(0)).getValueType(),
4483 getValue(I.getArgOperand(0)),
4484 getValue(I.getArgOperand(1))));
4486 case Intrinsic::copysign:
4487 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4488 getValue(I.getArgOperand(0)).getValueType(),
4489 getValue(I.getArgOperand(0)),
4490 getValue(I.getArgOperand(1))));
4492 case Intrinsic::fma:
4493 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4494 getValue(I.getArgOperand(0)).getValueType(),
4495 getValue(I.getArgOperand(0)),
4496 getValue(I.getArgOperand(1)),
4497 getValue(I.getArgOperand(2))));
4499 case Intrinsic::fmuladd: {
4500 EVT VT = TLI.getValueType(I.getType());
4501 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4502 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4503 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4504 getValue(I.getArgOperand(0)).getValueType(),
4505 getValue(I.getArgOperand(0)),
4506 getValue(I.getArgOperand(1)),
4507 getValue(I.getArgOperand(2))));
4509 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4510 getValue(I.getArgOperand(0)).getValueType(),
4511 getValue(I.getArgOperand(0)),
4512 getValue(I.getArgOperand(1)));
4513 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4514 getValue(I.getArgOperand(0)).getValueType(),
4516 getValue(I.getArgOperand(2)));
4521 case Intrinsic::convert_to_fp16:
4522 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4523 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4524 getValue(I.getArgOperand(0)),
4525 DAG.getTargetConstant(0, sdl,
4528 case Intrinsic::convert_from_fp16:
4530 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4531 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4532 getValue(I.getArgOperand(0)))));
4534 case Intrinsic::pcmarker: {
4535 SDValue Tmp = getValue(I.getArgOperand(0));
4536 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4539 case Intrinsic::readcyclecounter: {
4540 SDValue Op = getRoot();
4541 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4542 DAG.getVTList(MVT::i64, MVT::Other), Op);
4544 DAG.setRoot(Res.getValue(1));
4547 case Intrinsic::bswap:
4548 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4549 getValue(I.getArgOperand(0)).getValueType(),
4550 getValue(I.getArgOperand(0))));
4552 case Intrinsic::cttz: {
4553 SDValue Arg = getValue(I.getArgOperand(0));
4554 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4555 EVT Ty = Arg.getValueType();
4556 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4560 case Intrinsic::ctlz: {
4561 SDValue Arg = getValue(I.getArgOperand(0));
4562 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4563 EVT Ty = Arg.getValueType();
4564 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4568 case Intrinsic::ctpop: {
4569 SDValue Arg = getValue(I.getArgOperand(0));
4570 EVT Ty = Arg.getValueType();
4571 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4574 case Intrinsic::stacksave: {
4575 SDValue Op = getRoot();
4576 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4577 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4579 DAG.setRoot(Res.getValue(1));
4582 case Intrinsic::stackrestore: {
4583 Res = getValue(I.getArgOperand(0));
4584 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4587 case Intrinsic::stackprotector: {
4588 // Emit code into the DAG to store the stack guard onto the stack.
4589 MachineFunction &MF = DAG.getMachineFunction();
4590 MachineFrameInfo *MFI = MF.getFrameInfo();
4591 EVT PtrTy = TLI.getPointerTy();
4592 SDValue Src, Chain = getRoot();
4593 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4594 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4596 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4597 // global variable __stack_chk_guard.
4599 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4600 if (BC->getOpcode() == Instruction::BitCast)
4601 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4603 if (GV && TLI.useLoadStackGuardNode()) {
4604 // Emit a LOAD_STACK_GUARD node.
4605 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4607 MachinePointerInfo MPInfo(GV);
4608 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4609 unsigned Flags = MachineMemOperand::MOLoad |
4610 MachineMemOperand::MOInvariant;
4611 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4612 PtrTy.getSizeInBits() / 8,
4613 DAG.getEVTAlignment(PtrTy));
4614 Node->setMemRefs(MemRefs, MemRefs + 1);
4616 // Copy the guard value to a virtual register so that it can be
4617 // retrieved in the epilogue.
4618 Src = SDValue(Node, 0);
4619 const TargetRegisterClass *RC =
4620 TLI.getRegClassFor(Src.getSimpleValueType());
4621 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4623 SPDescriptor.setGuardReg(Reg);
4624 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4626 Src = getValue(I.getArgOperand(0)); // The guard's value.
4629 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4631 int FI = FuncInfo.StaticAllocaMap[Slot];
4632 MFI->setStackProtectorIndex(FI);
4634 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4636 // Store the stack protector onto the stack.
4637 Res = DAG.getStore(Chain, sdl, Src, FIN,
4638 MachinePointerInfo::getFixedStack(FI),
4644 case Intrinsic::objectsize: {
4645 // If we don't know by now, we're never going to know.
4646 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4648 assert(CI && "Non-constant type in __builtin_object_size?");
4650 SDValue Arg = getValue(I.getCalledValue());
4651 EVT Ty = Arg.getValueType();
4654 Res = DAG.getConstant(-1ULL, sdl, Ty);
4656 Res = DAG.getConstant(0, sdl, Ty);
4661 case Intrinsic::annotation:
4662 case Intrinsic::ptr_annotation:
4663 // Drop the intrinsic, but forward the value
4664 setValue(&I, getValue(I.getOperand(0)));
4666 case Intrinsic::assume:
4667 case Intrinsic::var_annotation:
4668 // Discard annotate attributes and assumptions
4671 case Intrinsic::init_trampoline: {
4672 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4676 Ops[1] = getValue(I.getArgOperand(0));
4677 Ops[2] = getValue(I.getArgOperand(1));
4678 Ops[3] = getValue(I.getArgOperand(2));
4679 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4680 Ops[5] = DAG.getSrcValue(F);
4682 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4687 case Intrinsic::adjust_trampoline: {
4688 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4690 getValue(I.getArgOperand(0))));
4693 case Intrinsic::gcroot:
4695 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4696 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4698 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4699 GFI->addStackRoot(FI->getIndex(), TypeMap);
4702 case Intrinsic::gcread:
4703 case Intrinsic::gcwrite:
4704 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4705 case Intrinsic::flt_rounds:
4706 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4709 case Intrinsic::expect: {
4710 // Just replace __builtin_expect(exp, c) with EXP.
4711 setValue(&I, getValue(I.getArgOperand(0)));
4715 case Intrinsic::debugtrap:
4716 case Intrinsic::trap: {
4717 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4718 if (TrapFuncName.empty()) {
4719 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4720 ISD::TRAP : ISD::DEBUGTRAP;
4721 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4724 TargetLowering::ArgListTy Args;
4726 TargetLowering::CallLoweringInfo CLI(DAG);
4727 CLI.setDebugLoc(sdl).setChain(getRoot())
4728 .setCallee(CallingConv::C, I.getType(),
4729 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4730 std::move(Args), 0);
4732 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4733 DAG.setRoot(Result.second);
4737 case Intrinsic::uadd_with_overflow:
4738 case Intrinsic::sadd_with_overflow:
4739 case Intrinsic::usub_with_overflow:
4740 case Intrinsic::ssub_with_overflow:
4741 case Intrinsic::umul_with_overflow:
4742 case Intrinsic::smul_with_overflow: {
4744 switch (Intrinsic) {
4745 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4746 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4747 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4748 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4749 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4750 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4751 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4753 SDValue Op1 = getValue(I.getArgOperand(0));
4754 SDValue Op2 = getValue(I.getArgOperand(1));
4756 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4757 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4760 case Intrinsic::prefetch: {
4762 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4764 Ops[1] = getValue(I.getArgOperand(0));
4765 Ops[2] = getValue(I.getArgOperand(1));
4766 Ops[3] = getValue(I.getArgOperand(2));
4767 Ops[4] = getValue(I.getArgOperand(3));
4768 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4769 DAG.getVTList(MVT::Other), Ops,
4770 EVT::getIntegerVT(*Context, 8),
4771 MachinePointerInfo(I.getArgOperand(0)),
4773 false, /* volatile */
4775 rw==1)); /* write */
4778 case Intrinsic::lifetime_start:
4779 case Intrinsic::lifetime_end: {
4780 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4781 // Stack coloring is not enabled in O0, discard region information.
4782 if (TM.getOptLevel() == CodeGenOpt::None)
4785 SmallVector<Value *, 4> Allocas;
4786 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4788 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4789 E = Allocas.end(); Object != E; ++Object) {
4790 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4792 // Could not find an Alloca.
4793 if (!LifetimeObject)
4796 // First check that the Alloca is static, otherwise it won't have a
4797 // valid frame index.
4798 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4799 if (SI == FuncInfo.StaticAllocaMap.end())
4802 int FI = SI->second;
4806 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4807 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4809 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4814 case Intrinsic::invariant_start:
4815 // Discard region information.
4816 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4818 case Intrinsic::invariant_end:
4819 // Discard region information.
4821 case Intrinsic::stackprotectorcheck: {
4822 // Do not actually emit anything for this basic block. Instead we initialize
4823 // the stack protector descriptor and export the guard variable so we can
4824 // access it in FinishBasicBlock.
4825 const BasicBlock *BB = I.getParent();
4826 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4827 ExportFromCurrentBlock(SPDescriptor.getGuard());
4829 // Flush our exports since we are going to process a terminator.
4830 (void)getControlRoot();
4833 case Intrinsic::clear_cache:
4834 return TLI.getClearCacheBuiltinName();
4835 case Intrinsic::eh_actions:
4836 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4838 case Intrinsic::donothing:
4841 case Intrinsic::experimental_stackmap: {
4845 case Intrinsic::experimental_patchpoint_void:
4846 case Intrinsic::experimental_patchpoint_i64: {
4847 visitPatchpoint(&I);
4850 case Intrinsic::experimental_gc_statepoint: {
4854 case Intrinsic::experimental_gc_result_int:
4855 case Intrinsic::experimental_gc_result_float:
4856 case Intrinsic::experimental_gc_result_ptr:
4857 case Intrinsic::experimental_gc_result: {
4861 case Intrinsic::experimental_gc_relocate: {
4865 case Intrinsic::instrprof_increment:
4866 llvm_unreachable("instrprof failed to lower an increment");
4868 case Intrinsic::frameescape: {
4869 MachineFunction &MF = DAG.getMachineFunction();
4870 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4872 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4873 // is the same on all targets.
4874 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4875 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4876 if (isa<ConstantPointerNull>(Arg))
4877 continue; // Skip null pointers. They represent a hole in index space.
4878 AllocaInst *Slot = cast<AllocaInst>(Arg);
4879 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4880 "can only escape static allocas");
4881 int FI = FuncInfo.StaticAllocaMap[Slot];
4882 MCSymbol *FrameAllocSym =
4883 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4884 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4886 TII->get(TargetOpcode::FRAME_ALLOC))
4887 .addSym(FrameAllocSym)
4894 case Intrinsic::framerecover: {
4895 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4896 MachineFunction &MF = DAG.getMachineFunction();
4897 MVT PtrVT = TLI.getPointerTy(0);
4899 // Get the symbol that defines the frame offset.
4900 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4901 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4902 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4903 MCSymbol *FrameAllocSym =
4904 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4905 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4907 // Create a TargetExternalSymbol for the label to avoid any target lowering
4908 // that would make this PC relative.
4909 StringRef Name = FrameAllocSym->getName();
4910 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4911 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4913 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4915 // Add the offset to the FP.
4916 Value *FP = I.getArgOperand(1);
4917 SDValue FPVal = getValue(FP);
4918 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4923 case Intrinsic::eh_begincatch:
4924 case Intrinsic::eh_endcatch:
4925 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4926 case Intrinsic::eh_exceptioncode: {
4927 unsigned Reg = TLI.getExceptionPointerRegister();
4928 assert(Reg && "cannot get exception code on this platform");
4929 MVT PtrVT = TLI.getPointerTy();
4930 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
4931 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
4933 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
4934 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
4941 std::pair<SDValue, SDValue>
4942 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
4943 MachineBasicBlock *LandingPad) {
4944 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4945 MCSymbol *BeginLabel = nullptr;
4948 // Insert a label before the invoke call to mark the try range. This can be
4949 // used to detect deletion of the invoke via the MachineModuleInfo.
4950 BeginLabel = MMI.getContext().CreateTempSymbol();
4952 // For SjLj, keep track of which landing pads go with which invokes
4953 // so as to maintain the ordering of pads in the LSDA.
4954 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4955 if (CallSiteIndex) {
4956 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4957 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
4959 // Now that the call site is handled, stop tracking it.
4960 MMI.setCurrentCallSite(0);
4963 // Both PendingLoads and PendingExports must be flushed here;
4964 // this call might not return.
4966 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
4968 CLI.setChain(getRoot());
4970 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4971 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4973 assert((CLI.IsTailCall || Result.second.getNode()) &&
4974 "Non-null chain expected with non-tail call!");
4975 assert((Result.second.getNode() || !Result.first.getNode()) &&
4976 "Null value expected with tail call!");
4978 if (!Result.second.getNode()) {
4979 // As a special case, a null chain means that a tail call has been emitted
4980 // and the DAG root is already updated.
4983 // Since there's no actual continuation from this block, nothing can be
4984 // relying on us setting vregs for them.
4985 PendingExports.clear();
4987 DAG.setRoot(Result.second);
4991 // Insert a label at the end of the invoke call to mark the try range. This
4992 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4993 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4994 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
4996 // Inform MachineModuleInfo of range.
4997 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5003 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5005 MachineBasicBlock *LandingPad) {
5006 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5007 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5008 Type *RetTy = FTy->getReturnType();
5010 TargetLowering::ArgListTy Args;
5011 TargetLowering::ArgListEntry Entry;
5012 Args.reserve(CS.arg_size());
5014 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5016 const Value *V = *i;
5019 if (V->getType()->isEmptyTy())
5022 SDValue ArgNode = getValue(V);
5023 Entry.Node = ArgNode; Entry.Ty = V->getType();
5025 // Skip the first return-type Attribute to get to params.
5026 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5027 Args.push_back(Entry);
5029 // If we have an explicit sret argument that is an Instruction, (i.e., it
5030 // might point to function-local memory), we can't meaningfully tail-call.
5031 if (Entry.isSRet && isa<Instruction>(V))
5035 // Check if target-independent constraints permit a tail call here.
5036 // Target-dependent constraints are checked within TLI->LowerCallTo.
5037 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5040 TargetLowering::CallLoweringInfo CLI(DAG);
5041 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5042 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5043 .setTailCall(isTailCall);
5044 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5046 if (Result.first.getNode())
5047 setValue(CS.getInstruction(), Result.first);
5050 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5051 /// value is equal or not-equal to zero.
5052 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5053 for (const User *U : V->users()) {
5054 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5055 if (IC->isEquality())
5056 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5057 if (C->isNullValue())
5059 // Unknown instruction.
5065 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5067 SelectionDAGBuilder &Builder) {
5069 // Check to see if this load can be trivially constant folded, e.g. if the
5070 // input is from a string literal.
5071 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5072 // Cast pointer to the type we really want to load.
5073 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5074 PointerType::getUnqual(LoadTy));
5076 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5077 const_cast<Constant *>(LoadInput), *Builder.DL))
5078 return Builder.getValue(LoadCst);
5081 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5082 // still constant memory, the input chain can be the entry node.
5084 bool ConstantMemory = false;
5086 // Do not serialize (non-volatile) loads of constant memory with anything.
5087 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5088 Root = Builder.DAG.getEntryNode();
5089 ConstantMemory = true;
5091 // Do not serialize non-volatile loads against each other.
5092 Root = Builder.DAG.getRoot();
5095 SDValue Ptr = Builder.getValue(PtrVal);
5096 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5097 Ptr, MachinePointerInfo(PtrVal),
5099 false /*nontemporal*/,
5100 false /*isinvariant*/, 1 /* align=1 */);
5102 if (!ConstantMemory)
5103 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5107 /// processIntegerCallValue - Record the value for an instruction that
5108 /// produces an integer result, converting the type where necessary.
5109 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5112 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5114 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5116 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5117 setValue(&I, Value);
5120 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5121 /// If so, return true and lower it, otherwise return false and it will be
5122 /// lowered like a normal call.
5123 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5124 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5125 if (I.getNumArgOperands() != 3)
5128 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5129 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5130 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5131 !I.getType()->isIntegerTy())
5134 const Value *Size = I.getArgOperand(2);
5135 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5136 if (CSize && CSize->getZExtValue() == 0) {
5137 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5138 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5142 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5143 std::pair<SDValue, SDValue> Res =
5144 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5145 getValue(LHS), getValue(RHS), getValue(Size),
5146 MachinePointerInfo(LHS),
5147 MachinePointerInfo(RHS));
5148 if (Res.first.getNode()) {
5149 processIntegerCallValue(I, Res.first, true);
5150 PendingLoads.push_back(Res.second);
5154 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5155 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5156 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5157 bool ActuallyDoIt = true;
5160 switch (CSize->getZExtValue()) {
5162 LoadVT = MVT::Other;
5164 ActuallyDoIt = false;
5168 LoadTy = Type::getInt16Ty(CSize->getContext());
5172 LoadTy = Type::getInt32Ty(CSize->getContext());
5176 LoadTy = Type::getInt64Ty(CSize->getContext());
5180 LoadVT = MVT::v4i32;
5181 LoadTy = Type::getInt32Ty(CSize->getContext());
5182 LoadTy = VectorType::get(LoadTy, 4);
5187 // This turns into unaligned loads. We only do this if the target natively
5188 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5189 // we'll only produce a small number of byte loads.
5191 // Require that we can find a legal MVT, and only do this if the target
5192 // supports unaligned loads of that type. Expanding into byte loads would
5194 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5195 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5196 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5197 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5198 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5199 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5200 // TODO: Check alignment of src and dest ptrs.
5201 if (!TLI.isTypeLegal(LoadVT) ||
5202 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5203 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5204 ActuallyDoIt = false;
5208 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5209 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5211 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5213 processIntegerCallValue(I, Res, false);
5222 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5223 /// form. If so, return true and lower it, otherwise return false and it
5224 /// will be lowered like a normal call.
5225 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5226 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5227 if (I.getNumArgOperands() != 3)
5230 const Value *Src = I.getArgOperand(0);
5231 const Value *Char = I.getArgOperand(1);
5232 const Value *Length = I.getArgOperand(2);
5233 if (!Src->getType()->isPointerTy() ||
5234 !Char->getType()->isIntegerTy() ||
5235 !Length->getType()->isIntegerTy() ||
5236 !I.getType()->isPointerTy())
5239 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5240 std::pair<SDValue, SDValue> Res =
5241 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5242 getValue(Src), getValue(Char), getValue(Length),
5243 MachinePointerInfo(Src));
5244 if (Res.first.getNode()) {
5245 setValue(&I, Res.first);
5246 PendingLoads.push_back(Res.second);
5253 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5254 /// optimized form. If so, return true and lower it, otherwise return false
5255 /// and it will be lowered like a normal call.
5256 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5257 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5258 if (I.getNumArgOperands() != 2)
5261 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5262 if (!Arg0->getType()->isPointerTy() ||
5263 !Arg1->getType()->isPointerTy() ||
5264 !I.getType()->isPointerTy())
5267 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5268 std::pair<SDValue, SDValue> Res =
5269 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5270 getValue(Arg0), getValue(Arg1),
5271 MachinePointerInfo(Arg0),
5272 MachinePointerInfo(Arg1), isStpcpy);
5273 if (Res.first.getNode()) {
5274 setValue(&I, Res.first);
5275 DAG.setRoot(Res.second);
5282 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5283 /// If so, return true and lower it, otherwise return false and it will be
5284 /// lowered like a normal call.
5285 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5286 // Verify that the prototype makes sense. int strcmp(void*,void*)
5287 if (I.getNumArgOperands() != 2)
5290 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5291 if (!Arg0->getType()->isPointerTy() ||
5292 !Arg1->getType()->isPointerTy() ||
5293 !I.getType()->isIntegerTy())
5296 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5297 std::pair<SDValue, SDValue> Res =
5298 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5299 getValue(Arg0), getValue(Arg1),
5300 MachinePointerInfo(Arg0),
5301 MachinePointerInfo(Arg1));
5302 if (Res.first.getNode()) {
5303 processIntegerCallValue(I, Res.first, true);
5304 PendingLoads.push_back(Res.second);
5311 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5312 /// form. If so, return true and lower it, otherwise return false and it
5313 /// will be lowered like a normal call.
5314 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5315 // Verify that the prototype makes sense. size_t strlen(char *)
5316 if (I.getNumArgOperands() != 1)
5319 const Value *Arg0 = I.getArgOperand(0);
5320 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5323 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5324 std::pair<SDValue, SDValue> Res =
5325 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5326 getValue(Arg0), MachinePointerInfo(Arg0));
5327 if (Res.first.getNode()) {
5328 processIntegerCallValue(I, Res.first, false);
5329 PendingLoads.push_back(Res.second);
5336 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5337 /// form. If so, return true and lower it, otherwise return false and it
5338 /// will be lowered like a normal call.
5339 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5340 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5341 if (I.getNumArgOperands() != 2)
5344 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5345 if (!Arg0->getType()->isPointerTy() ||
5346 !Arg1->getType()->isIntegerTy() ||
5347 !I.getType()->isIntegerTy())
5350 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5351 std::pair<SDValue, SDValue> Res =
5352 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5353 getValue(Arg0), getValue(Arg1),
5354 MachinePointerInfo(Arg0));
5355 if (Res.first.getNode()) {
5356 processIntegerCallValue(I, Res.first, false);
5357 PendingLoads.push_back(Res.second);
5364 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5365 /// operation (as expected), translate it to an SDNode with the specified opcode
5366 /// and return true.
5367 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5369 // Sanity check that it really is a unary floating-point call.
5370 if (I.getNumArgOperands() != 1 ||
5371 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5372 I.getType() != I.getArgOperand(0)->getType() ||
5373 !I.onlyReadsMemory())
5376 SDValue Tmp = getValue(I.getArgOperand(0));
5377 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5381 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5382 /// operation (as expected), translate it to an SDNode with the specified opcode
5383 /// and return true.
5384 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5386 // Sanity check that it really is a binary floating-point call.
5387 if (I.getNumArgOperands() != 2 ||
5388 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5389 I.getType() != I.getArgOperand(0)->getType() ||
5390 I.getType() != I.getArgOperand(1)->getType() ||
5391 !I.onlyReadsMemory())
5394 SDValue Tmp0 = getValue(I.getArgOperand(0));
5395 SDValue Tmp1 = getValue(I.getArgOperand(1));
5396 EVT VT = Tmp0.getValueType();
5397 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5401 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5402 // Handle inline assembly differently.
5403 if (isa<InlineAsm>(I.getCalledValue())) {
5408 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5409 ComputeUsesVAFloatArgument(I, &MMI);
5411 const char *RenameFn = nullptr;
5412 if (Function *F = I.getCalledFunction()) {
5413 if (F->isDeclaration()) {
5414 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5415 if (unsigned IID = II->getIntrinsicID(F)) {
5416 RenameFn = visitIntrinsicCall(I, IID);
5421 if (unsigned IID = F->getIntrinsicID()) {
5422 RenameFn = visitIntrinsicCall(I, IID);
5428 // Check for well-known libc/libm calls. If the function is internal, it
5429 // can't be a library call.
5431 if (!F->hasLocalLinkage() && F->hasName() &&
5432 LibInfo->getLibFunc(F->getName(), Func) &&
5433 LibInfo->hasOptimizedCodeGen(Func)) {
5436 case LibFunc::copysign:
5437 case LibFunc::copysignf:
5438 case LibFunc::copysignl:
5439 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5440 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5441 I.getType() == I.getArgOperand(0)->getType() &&
5442 I.getType() == I.getArgOperand(1)->getType() &&
5443 I.onlyReadsMemory()) {
5444 SDValue LHS = getValue(I.getArgOperand(0));
5445 SDValue RHS = getValue(I.getArgOperand(1));
5446 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5447 LHS.getValueType(), LHS, RHS));
5452 case LibFunc::fabsf:
5453 case LibFunc::fabsl:
5454 if (visitUnaryFloatCall(I, ISD::FABS))
5458 case LibFunc::fminf:
5459 case LibFunc::fminl:
5460 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5464 case LibFunc::fmaxf:
5465 case LibFunc::fmaxl:
5466 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5472 if (visitUnaryFloatCall(I, ISD::FSIN))
5478 if (visitUnaryFloatCall(I, ISD::FCOS))
5482 case LibFunc::sqrtf:
5483 case LibFunc::sqrtl:
5484 case LibFunc::sqrt_finite:
5485 case LibFunc::sqrtf_finite:
5486 case LibFunc::sqrtl_finite:
5487 if (visitUnaryFloatCall(I, ISD::FSQRT))
5490 case LibFunc::floor:
5491 case LibFunc::floorf:
5492 case LibFunc::floorl:
5493 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5496 case LibFunc::nearbyint:
5497 case LibFunc::nearbyintf:
5498 case LibFunc::nearbyintl:
5499 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5503 case LibFunc::ceilf:
5504 case LibFunc::ceill:
5505 if (visitUnaryFloatCall(I, ISD::FCEIL))
5509 case LibFunc::rintf:
5510 case LibFunc::rintl:
5511 if (visitUnaryFloatCall(I, ISD::FRINT))
5514 case LibFunc::round:
5515 case LibFunc::roundf:
5516 case LibFunc::roundl:
5517 if (visitUnaryFloatCall(I, ISD::FROUND))
5520 case LibFunc::trunc:
5521 case LibFunc::truncf:
5522 case LibFunc::truncl:
5523 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5527 case LibFunc::log2f:
5528 case LibFunc::log2l:
5529 if (visitUnaryFloatCall(I, ISD::FLOG2))
5533 case LibFunc::exp2f:
5534 case LibFunc::exp2l:
5535 if (visitUnaryFloatCall(I, ISD::FEXP2))
5538 case LibFunc::memcmp:
5539 if (visitMemCmpCall(I))
5542 case LibFunc::memchr:
5543 if (visitMemChrCall(I))
5546 case LibFunc::strcpy:
5547 if (visitStrCpyCall(I, false))
5550 case LibFunc::stpcpy:
5551 if (visitStrCpyCall(I, true))
5554 case LibFunc::strcmp:
5555 if (visitStrCmpCall(I))
5558 case LibFunc::strlen:
5559 if (visitStrLenCall(I))
5562 case LibFunc::strnlen:
5563 if (visitStrNLenCall(I))
5572 Callee = getValue(I.getCalledValue());
5574 Callee = DAG.getExternalSymbol(RenameFn,
5575 DAG.getTargetLoweringInfo().getPointerTy());
5577 // Check if we can potentially perform a tail call. More detailed checking is
5578 // be done within LowerCallTo, after more information about the call is known.
5579 LowerCallTo(&I, Callee, I.isTailCall());
5584 /// AsmOperandInfo - This contains information for each constraint that we are
5586 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5588 /// CallOperand - If this is the result output operand or a clobber
5589 /// this is null, otherwise it is the incoming operand to the CallInst.
5590 /// This gets modified as the asm is processed.
5591 SDValue CallOperand;
5593 /// AssignedRegs - If this is a register or register class operand, this
5594 /// contains the set of register corresponding to the operand.
5595 RegsForValue AssignedRegs;
5597 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5598 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5601 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5602 /// corresponds to. If there is no Value* for this operand, it returns
5604 EVT getCallOperandValEVT(LLVMContext &Context,
5605 const TargetLowering &TLI,
5606 const DataLayout *DL) const {
5607 if (!CallOperandVal) return MVT::Other;
5609 if (isa<BasicBlock>(CallOperandVal))
5610 return TLI.getPointerTy();
5612 llvm::Type *OpTy = CallOperandVal->getType();
5614 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5615 // If this is an indirect operand, the operand is a pointer to the
5618 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5620 report_fatal_error("Indirect operand for inline asm not a pointer!");
5621 OpTy = PtrTy->getElementType();
5624 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5625 if (StructType *STy = dyn_cast<StructType>(OpTy))
5626 if (STy->getNumElements() == 1)
5627 OpTy = STy->getElementType(0);
5629 // If OpTy is not a single value, it may be a struct/union that we
5630 // can tile with integers.
5631 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5632 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5641 OpTy = IntegerType::get(Context, BitSize);
5646 return TLI.getValueType(OpTy, true);
5650 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5652 } // end anonymous namespace
5654 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5655 /// specified operand. We prefer to assign virtual registers, to allow the
5656 /// register allocator to handle the assignment process. However, if the asm
5657 /// uses features that we can't model on machineinstrs, we have SDISel do the
5658 /// allocation. This produces generally horrible, but correct, code.
5660 /// OpInfo describes the operand.
5662 static void GetRegistersForValue(SelectionDAG &DAG,
5663 const TargetLowering &TLI,
5665 SDISelAsmOperandInfo &OpInfo) {
5666 LLVMContext &Context = *DAG.getContext();
5668 MachineFunction &MF = DAG.getMachineFunction();
5669 SmallVector<unsigned, 4> Regs;
5671 // If this is a constraint for a single physreg, or a constraint for a
5672 // register class, find it.
5673 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5674 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5675 OpInfo.ConstraintCode,
5676 OpInfo.ConstraintVT);
5678 unsigned NumRegs = 1;
5679 if (OpInfo.ConstraintVT != MVT::Other) {
5680 // If this is a FP input in an integer register (or visa versa) insert a bit
5681 // cast of the input value. More generally, handle any case where the input
5682 // value disagrees with the register class we plan to stick this in.
5683 if (OpInfo.Type == InlineAsm::isInput &&
5684 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5685 // Try to convert to the first EVT that the reg class contains. If the
5686 // types are identical size, use a bitcast to convert (e.g. two differing
5688 MVT RegVT = *PhysReg.second->vt_begin();
5689 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5690 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5691 RegVT, OpInfo.CallOperand);
5692 OpInfo.ConstraintVT = RegVT;
5693 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5694 // If the input is a FP value and we want it in FP registers, do a
5695 // bitcast to the corresponding integer type. This turns an f64 value
5696 // into i64, which can be passed with two i32 values on a 32-bit
5698 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5699 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5700 RegVT, OpInfo.CallOperand);
5701 OpInfo.ConstraintVT = RegVT;
5705 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5709 EVT ValueVT = OpInfo.ConstraintVT;
5711 // If this is a constraint for a specific physical register, like {r17},
5713 if (unsigned AssignedReg = PhysReg.first) {
5714 const TargetRegisterClass *RC = PhysReg.second;
5715 if (OpInfo.ConstraintVT == MVT::Other)
5716 ValueVT = *RC->vt_begin();
5718 // Get the actual register value type. This is important, because the user
5719 // may have asked for (e.g.) the AX register in i32 type. We need to
5720 // remember that AX is actually i16 to get the right extension.
5721 RegVT = *RC->vt_begin();
5723 // This is a explicit reference to a physical register.
5724 Regs.push_back(AssignedReg);
5726 // If this is an expanded reference, add the rest of the regs to Regs.
5728 TargetRegisterClass::iterator I = RC->begin();
5729 for (; *I != AssignedReg; ++I)
5730 assert(I != RC->end() && "Didn't find reg!");
5732 // Already added the first reg.
5734 for (; NumRegs; --NumRegs, ++I) {
5735 assert(I != RC->end() && "Ran out of registers to allocate!");
5740 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5744 // Otherwise, if this was a reference to an LLVM register class, create vregs
5745 // for this reference.
5746 if (const TargetRegisterClass *RC = PhysReg.second) {
5747 RegVT = *RC->vt_begin();
5748 if (OpInfo.ConstraintVT == MVT::Other)
5751 // Create the appropriate number of virtual registers.
5752 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5753 for (; NumRegs; --NumRegs)
5754 Regs.push_back(RegInfo.createVirtualRegister(RC));
5756 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5760 // Otherwise, we couldn't allocate enough registers for this.
5763 /// visitInlineAsm - Handle a call to an InlineAsm object.
5765 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5766 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5768 /// ConstraintOperands - Information about all of the constraints.
5769 SDISelAsmOperandInfoVector ConstraintOperands;
5771 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5772 TargetLowering::AsmOperandInfoVector TargetConstraints =
5773 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5775 bool hasMemory = false;
5777 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5778 unsigned ResNo = 0; // ResNo - The result number of the next output.
5779 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5780 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5781 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5783 MVT OpVT = MVT::Other;
5785 // Compute the value type for each operand.
5786 switch (OpInfo.Type) {
5787 case InlineAsm::isOutput:
5788 // Indirect outputs just consume an argument.
5789 if (OpInfo.isIndirect) {
5790 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5794 // The return value of the call is this value. As such, there is no
5795 // corresponding argument.
5796 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5797 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5798 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5800 assert(ResNo == 0 && "Asm only has one result!");
5801 OpVT = TLI.getSimpleValueType(CS.getType());
5805 case InlineAsm::isInput:
5806 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5808 case InlineAsm::isClobber:
5813 // If this is an input or an indirect output, process the call argument.
5814 // BasicBlocks are labels, currently appearing only in asm's.
5815 if (OpInfo.CallOperandVal) {
5816 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5817 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5819 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5823 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5826 OpInfo.ConstraintVT = OpVT;
5828 // Indirect operand accesses access memory.
5829 if (OpInfo.isIndirect)
5832 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5833 TargetLowering::ConstraintType
5834 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5835 if (CType == TargetLowering::C_Memory) {
5843 SDValue Chain, Flag;
5845 // We won't need to flush pending loads if this asm doesn't touch
5846 // memory and is nonvolatile.
5847 if (hasMemory || IA->hasSideEffects())
5850 Chain = DAG.getRoot();
5852 // Second pass over the constraints: compute which constraint option to use
5853 // and assign registers to constraints that want a specific physreg.
5854 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5855 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5857 // If this is an output operand with a matching input operand, look up the
5858 // matching input. If their types mismatch, e.g. one is an integer, the
5859 // other is floating point, or their sizes are different, flag it as an
5861 if (OpInfo.hasMatchingInput()) {
5862 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5864 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5865 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5866 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5867 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5868 OpInfo.ConstraintVT);
5869 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5870 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5871 Input.ConstraintVT);
5872 if ((OpInfo.ConstraintVT.isInteger() !=
5873 Input.ConstraintVT.isInteger()) ||
5874 (MatchRC.second != InputRC.second)) {
5875 report_fatal_error("Unsupported asm: input constraint"
5876 " with a matching output constraint of"
5877 " incompatible type!");
5879 Input.ConstraintVT = OpInfo.ConstraintVT;
5883 // Compute the constraint code and ConstraintType to use.
5884 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5886 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5887 OpInfo.Type == InlineAsm::isClobber)
5890 // If this is a memory input, and if the operand is not indirect, do what we
5891 // need to to provide an address for the memory input.
5892 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5893 !OpInfo.isIndirect) {
5894 assert((OpInfo.isMultipleAlternative ||
5895 (OpInfo.Type == InlineAsm::isInput)) &&
5896 "Can only indirectify direct input operands!");
5898 // Memory operands really want the address of the value. If we don't have
5899 // an indirect input, put it in the constpool if we can, otherwise spill
5900 // it to a stack slot.
5901 // TODO: This isn't quite right. We need to handle these according to
5902 // the addressing mode that the constraint wants. Also, this may take
5903 // an additional register for the computation and we don't want that
5906 // If the operand is a float, integer, or vector constant, spill to a
5907 // constant pool entry to get its address.
5908 const Value *OpVal = OpInfo.CallOperandVal;
5909 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5910 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5911 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5912 TLI.getPointerTy());
5914 // Otherwise, create a stack slot and emit a store to it before the
5916 Type *Ty = OpVal->getType();
5917 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5918 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5919 MachineFunction &MF = DAG.getMachineFunction();
5920 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5921 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5922 Chain = DAG.getStore(Chain, getCurSDLoc(),
5923 OpInfo.CallOperand, StackSlot,
5924 MachinePointerInfo::getFixedStack(SSFI),
5926 OpInfo.CallOperand = StackSlot;
5929 // There is no longer a Value* corresponding to this operand.
5930 OpInfo.CallOperandVal = nullptr;
5932 // It is now an indirect operand.
5933 OpInfo.isIndirect = true;
5936 // If this constraint is for a specific register, allocate it before
5938 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5939 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5942 // Second pass - Loop over all of the operands, assigning virtual or physregs
5943 // to register class operands.
5944 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5945 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5947 // C_Register operands have already been allocated, Other/Memory don't need
5949 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5950 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5953 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5954 std::vector<SDValue> AsmNodeOperands;
5955 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5956 AsmNodeOperands.push_back(
5957 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5958 TLI.getPointerTy()));
5960 // If we have a !srcloc metadata node associated with it, we want to attach
5961 // this to the ultimately generated inline asm machineinstr. To do this, we
5962 // pass in the third operand as this (potentially null) inline asm MDNode.
5963 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5964 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5966 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
5967 // bits as operand 3.
5968 unsigned ExtraInfo = 0;
5969 if (IA->hasSideEffects())
5970 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5971 if (IA->isAlignStack())
5972 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5973 // Set the asm dialect.
5974 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
5976 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
5977 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5978 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
5980 // Compute the constraint code and ConstraintType to use.
5981 TLI.ComputeConstraintToUse(OpInfo, SDValue());
5983 // Ideally, we would only check against memory constraints. However, the
5984 // meaning of an other constraint can be target-specific and we can't easily
5985 // reason about it. Therefore, be conservative and set MayLoad/MayStore
5986 // for other constriants as well.
5987 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
5988 OpInfo.ConstraintType == TargetLowering::C_Other) {
5989 if (OpInfo.Type == InlineAsm::isInput)
5990 ExtraInfo |= InlineAsm::Extra_MayLoad;
5991 else if (OpInfo.Type == InlineAsm::isOutput)
5992 ExtraInfo |= InlineAsm::Extra_MayStore;
5993 else if (OpInfo.Type == InlineAsm::isClobber)
5994 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
5998 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, getCurSDLoc(),
5999 TLI.getPointerTy()));
6001 // Loop over all of the inputs, copying the operand values into the
6002 // appropriate registers and processing the output regs.
6003 RegsForValue RetValRegs;
6005 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6006 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6008 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6009 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6011 switch (OpInfo.Type) {
6012 case InlineAsm::isOutput: {
6013 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6014 OpInfo.ConstraintType != TargetLowering::C_Register) {
6015 // Memory output, or 'other' output (e.g. 'X' constraint).
6016 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6018 unsigned ConstraintID =
6019 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6020 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6021 "Failed to convert memory constraint code to constraint id.");
6023 // Add information to the INLINEASM node to know about this output.
6024 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6025 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6026 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6028 AsmNodeOperands.push_back(OpInfo.CallOperand);
6032 // Otherwise, this is a register or register class output.
6034 // Copy the output from the appropriate register. Find a register that
6036 if (OpInfo.AssignedRegs.Regs.empty()) {
6037 LLVMContext &Ctx = *DAG.getContext();
6038 Ctx.emitError(CS.getInstruction(),
6039 "couldn't allocate output register for constraint '" +
6040 Twine(OpInfo.ConstraintCode) + "'");
6044 // If this is an indirect operand, store through the pointer after the
6046 if (OpInfo.isIndirect) {
6047 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6048 OpInfo.CallOperandVal));
6050 // This is the result value of the call.
6051 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6052 // Concatenate this output onto the outputs list.
6053 RetValRegs.append(OpInfo.AssignedRegs);
6056 // Add information to the INLINEASM node to know that this register is
6059 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6060 ? InlineAsm::Kind_RegDefEarlyClobber
6061 : InlineAsm::Kind_RegDef,
6062 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6065 case InlineAsm::isInput: {
6066 SDValue InOperandVal = OpInfo.CallOperand;
6068 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6069 // If this is required to match an output register we have already set,
6070 // just use its register.
6071 unsigned OperandNo = OpInfo.getMatchedOperand();
6073 // Scan until we find the definition we already emitted of this operand.
6074 // When we find it, create a RegsForValue operand.
6075 unsigned CurOp = InlineAsm::Op_FirstOperand;
6076 for (; OperandNo; --OperandNo) {
6077 // Advance to the next operand.
6079 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6080 assert((InlineAsm::isRegDefKind(OpFlag) ||
6081 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6082 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6083 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6087 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6088 if (InlineAsm::isRegDefKind(OpFlag) ||
6089 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6090 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6091 if (OpInfo.isIndirect) {
6092 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6093 LLVMContext &Ctx = *DAG.getContext();
6094 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6095 " don't know how to handle tied "
6096 "indirect register inputs");
6100 RegsForValue MatchedRegs;
6101 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6102 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6103 MatchedRegs.RegVTs.push_back(RegVT);
6104 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6105 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6107 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6108 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6110 LLVMContext &Ctx = *DAG.getContext();
6111 Ctx.emitError(CS.getInstruction(),
6112 "inline asm error: This value"
6113 " type register class is not natively supported!");
6117 SDLoc dl = getCurSDLoc();
6118 // Use the produced MatchedRegs object to
6119 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6120 Chain, &Flag, CS.getInstruction());
6121 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6122 true, OpInfo.getMatchedOperand(), dl,
6123 DAG, AsmNodeOperands);
6127 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6128 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6129 "Unexpected number of operands");
6130 // Add information to the INLINEASM node to know about this input.
6131 // See InlineAsm.h isUseOperandTiedToDef.
6132 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6133 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6134 OpInfo.getMatchedOperand());
6135 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, getCurSDLoc(),
6136 TLI.getPointerTy()));
6137 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6141 // Treat indirect 'X' constraint as memory.
6142 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6144 OpInfo.ConstraintType = TargetLowering::C_Memory;
6146 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6147 std::vector<SDValue> Ops;
6148 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6151 LLVMContext &Ctx = *DAG.getContext();
6152 Ctx.emitError(CS.getInstruction(),
6153 "invalid operand for inline asm constraint '" +
6154 Twine(OpInfo.ConstraintCode) + "'");
6158 // Add information to the INLINEASM node to know about this input.
6159 unsigned ResOpType =
6160 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6161 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6163 TLI.getPointerTy()));
6164 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6168 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6169 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6170 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6171 "Memory operands expect pointer values");
6173 unsigned ConstraintID =
6174 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6175 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6176 "Failed to convert memory constraint code to constraint id.");
6178 // Add information to the INLINEASM node to know about this input.
6179 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6180 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6181 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6184 AsmNodeOperands.push_back(InOperandVal);
6188 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6189 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6190 "Unknown constraint type!");
6192 // TODO: Support this.
6193 if (OpInfo.isIndirect) {
6194 LLVMContext &Ctx = *DAG.getContext();
6195 Ctx.emitError(CS.getInstruction(),
6196 "Don't know how to handle indirect register inputs yet "
6197 "for constraint '" +
6198 Twine(OpInfo.ConstraintCode) + "'");
6202 // Copy the input into the appropriate registers.
6203 if (OpInfo.AssignedRegs.Regs.empty()) {
6204 LLVMContext &Ctx = *DAG.getContext();
6205 Ctx.emitError(CS.getInstruction(),
6206 "couldn't allocate input reg for constraint '" +
6207 Twine(OpInfo.ConstraintCode) + "'");
6211 SDLoc dl = getCurSDLoc();
6213 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6214 Chain, &Flag, CS.getInstruction());
6216 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6217 dl, DAG, AsmNodeOperands);
6220 case InlineAsm::isClobber: {
6221 // Add the clobbered value to the operand list, so that the register
6222 // allocator is aware that the physreg got clobbered.
6223 if (!OpInfo.AssignedRegs.Regs.empty())
6224 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6225 false, 0, getCurSDLoc(), DAG,
6232 // Finish up input operands. Set the input chain and add the flag last.
6233 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6234 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6236 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6237 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6238 Flag = Chain.getValue(1);
6240 // If this asm returns a register value, copy the result from that register
6241 // and set it as the value of the call.
6242 if (!RetValRegs.Regs.empty()) {
6243 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6244 Chain, &Flag, CS.getInstruction());
6246 // FIXME: Why don't we do this for inline asms with MRVs?
6247 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6248 EVT ResultType = TLI.getValueType(CS.getType());
6250 // If any of the results of the inline asm is a vector, it may have the
6251 // wrong width/num elts. This can happen for register classes that can
6252 // contain multiple different value types. The preg or vreg allocated may
6253 // not have the same VT as was expected. Convert it to the right type
6254 // with bit_convert.
6255 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6256 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6259 } else if (ResultType != Val.getValueType() &&
6260 ResultType.isInteger() && Val.getValueType().isInteger()) {
6261 // If a result value was tied to an input value, the computed result may
6262 // have a wider width than the expected result. Extract the relevant
6264 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6267 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6270 setValue(CS.getInstruction(), Val);
6271 // Don't need to use this as a chain in this case.
6272 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6276 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6278 // Process indirect outputs, first output all of the flagged copies out of
6280 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6281 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6282 const Value *Ptr = IndirectStoresToEmit[i].second;
6283 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6285 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6288 // Emit the non-flagged stores from the physregs.
6289 SmallVector<SDValue, 8> OutChains;
6290 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6291 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6292 StoresToEmit[i].first,
6293 getValue(StoresToEmit[i].second),
6294 MachinePointerInfo(StoresToEmit[i].second),
6296 OutChains.push_back(Val);
6299 if (!OutChains.empty())
6300 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6305 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6306 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6307 MVT::Other, getRoot(),
6308 getValue(I.getArgOperand(0)),
6309 DAG.getSrcValue(I.getArgOperand(0))));
6312 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6314 const DataLayout &DL = *TLI.getDataLayout();
6315 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6316 getRoot(), getValue(I.getOperand(0)),
6317 DAG.getSrcValue(I.getOperand(0)),
6318 DL.getABITypeAlignment(I.getType()));
6320 DAG.setRoot(V.getValue(1));
6323 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6324 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6325 MVT::Other, getRoot(),
6326 getValue(I.getArgOperand(0)),
6327 DAG.getSrcValue(I.getArgOperand(0))));
6330 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6331 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6332 MVT::Other, getRoot(),
6333 getValue(I.getArgOperand(0)),
6334 getValue(I.getArgOperand(1)),
6335 DAG.getSrcValue(I.getArgOperand(0)),
6336 DAG.getSrcValue(I.getArgOperand(1))));
6339 /// \brief Lower an argument list according to the target calling convention.
6341 /// \return A tuple of <return-value, token-chain>
6343 /// This is a helper for lowering intrinsics that follow a target calling
6344 /// convention or require stack pointer adjustment. Only a subset of the
6345 /// intrinsic's operands need to participate in the calling convention.
6346 std::pair<SDValue, SDValue>
6347 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6348 unsigned NumArgs, SDValue Callee,
6350 MachineBasicBlock *LandingPad,
6351 bool IsPatchPoint) {
6352 TargetLowering::ArgListTy Args;
6353 Args.reserve(NumArgs);
6355 // Populate the argument list.
6356 // Attributes for args start at offset 1, after the return attribute.
6357 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6358 ArgI != ArgE; ++ArgI) {
6359 const Value *V = CS->getOperand(ArgI);
6361 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6363 TargetLowering::ArgListEntry Entry;
6364 Entry.Node = getValue(V);
6365 Entry.Ty = V->getType();
6366 Entry.setAttributes(&CS, AttrI);
6367 Args.push_back(Entry);
6370 TargetLowering::CallLoweringInfo CLI(DAG);
6371 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6372 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6373 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6375 return lowerInvokable(CLI, LandingPad);
6378 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6379 /// or patchpoint target node's operand list.
6381 /// Constants are converted to TargetConstants purely as an optimization to
6382 /// avoid constant materialization and register allocation.
6384 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6385 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6386 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6387 /// address materialization and register allocation, but may also be required
6388 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6389 /// alloca in the entry block, then the runtime may assume that the alloca's
6390 /// StackMap location can be read immediately after compilation and that the
6391 /// location is valid at any point during execution (this is similar to the
6392 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6393 /// only available in a register, then the runtime would need to trap when
6394 /// execution reaches the StackMap in order to read the alloca's location.
6395 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6396 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6397 SelectionDAGBuilder &Builder) {
6398 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6399 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6402 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6404 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6405 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6406 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6408 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6410 Ops.push_back(OpVal);
6414 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6415 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6416 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6417 // [live variables...])
6419 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6421 SDValue Chain, InFlag, Callee, NullPtr;
6422 SmallVector<SDValue, 32> Ops;
6424 SDLoc DL = getCurSDLoc();
6425 Callee = getValue(CI.getCalledValue());
6426 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6428 // The stackmap intrinsic only records the live variables (the arguemnts
6429 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6430 // intrinsic, this won't be lowered to a function call. This means we don't
6431 // have to worry about calling conventions and target specific lowering code.
6432 // Instead we perform the call lowering right here.
6434 // chain, flag = CALLSEQ_START(chain, 0)
6435 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6436 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6438 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6439 InFlag = Chain.getValue(1);
6441 // Add the <id> and <numBytes> constants.
6442 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6443 Ops.push_back(DAG.getTargetConstant(
6444 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6445 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6446 Ops.push_back(DAG.getTargetConstant(
6447 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6450 // Push live variables for the stack map.
6451 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6453 // We are not pushing any register mask info here on the operands list,
6454 // because the stackmap doesn't clobber anything.
6456 // Push the chain and the glue flag.
6457 Ops.push_back(Chain);
6458 Ops.push_back(InFlag);
6460 // Create the STACKMAP node.
6461 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6462 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6463 Chain = SDValue(SM, 0);
6464 InFlag = Chain.getValue(1);
6466 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6468 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6470 // Set the root to the target-lowered call chain.
6473 // Inform the Frame Information that we have a stackmap in this function.
6474 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6477 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6478 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6479 MachineBasicBlock *LandingPad) {
6480 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6485 // [live variables...])
6487 CallingConv::ID CC = CS.getCallingConv();
6488 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6489 bool HasDef = !CS->getType()->isVoidTy();
6490 SDLoc dl = getCurSDLoc();
6491 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6493 // Handle immediate and symbolic callees.
6494 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6495 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6497 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6498 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6499 SDLoc(SymbolicCallee),
6500 SymbolicCallee->getValueType(0));
6502 // Get the real number of arguments participating in the call <numArgs>
6503 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6504 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6506 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6507 // Intrinsics include all meta-operands up to but not including CC.
6508 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6509 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6510 "Not enough arguments provided to the patchpoint intrinsic");
6512 // For AnyRegCC the arguments are lowered later on manually.
6513 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6515 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6516 std::pair<SDValue, SDValue> Result =
6517 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6520 SDNode *CallEnd = Result.second.getNode();
6521 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6522 CallEnd = CallEnd->getOperand(0).getNode();
6524 /// Get a call instruction from the call sequence chain.
6525 /// Tail calls are not allowed.
6526 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6527 "Expected a callseq node.");
6528 SDNode *Call = CallEnd->getOperand(0).getNode();
6529 bool HasGlue = Call->getGluedNode();
6531 // Replace the target specific call node with the patchable intrinsic.
6532 SmallVector<SDValue, 8> Ops;
6534 // Add the <id> and <numBytes> constants.
6535 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6536 Ops.push_back(DAG.getTargetConstant(
6537 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6538 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6539 Ops.push_back(DAG.getTargetConstant(
6540 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6544 Ops.push_back(Callee);
6546 // Adjust <numArgs> to account for any arguments that have been passed on the
6548 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6549 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6550 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6551 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6553 // Add the calling convention
6554 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6556 // Add the arguments we omitted previously. The register allocator should
6557 // place these in any free register.
6559 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6560 Ops.push_back(getValue(CS.getArgument(i)));
6562 // Push the arguments from the call instruction up to the register mask.
6563 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6564 Ops.append(Call->op_begin() + 2, e);
6566 // Push live variables for the stack map.
6567 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6569 // Push the register mask info.
6571 Ops.push_back(*(Call->op_end()-2));
6573 Ops.push_back(*(Call->op_end()-1));
6575 // Push the chain (this is originally the first operand of the call, but
6576 // becomes now the last or second to last operand).
6577 Ops.push_back(*(Call->op_begin()));
6579 // Push the glue flag (last operand).
6581 Ops.push_back(*(Call->op_end()-1));
6584 if (IsAnyRegCC && HasDef) {
6585 // Create the return types based on the intrinsic definition
6586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6587 SmallVector<EVT, 3> ValueVTs;
6588 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6589 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6591 // There is always a chain and a glue type at the end
6592 ValueVTs.push_back(MVT::Other);
6593 ValueVTs.push_back(MVT::Glue);
6594 NodeTys = DAG.getVTList(ValueVTs);
6596 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6598 // Replace the target specific call node with a PATCHPOINT node.
6599 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6602 // Update the NodeMap.
6605 setValue(CS.getInstruction(), SDValue(MN, 0));
6607 setValue(CS.getInstruction(), Result.first);
6610 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6611 // call sequence. Furthermore the location of the chain and glue can change
6612 // when the AnyReg calling convention is used and the intrinsic returns a
6614 if (IsAnyRegCC && HasDef) {
6615 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6616 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6617 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6619 DAG.ReplaceAllUsesWith(Call, MN);
6620 DAG.DeleteNode(Call);
6622 // Inform the Frame Information that we have a patchpoint in this function.
6623 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6626 /// Returns an AttributeSet representing the attributes applied to the return
6627 /// value of the given call.
6628 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6629 SmallVector<Attribute::AttrKind, 2> Attrs;
6631 Attrs.push_back(Attribute::SExt);
6633 Attrs.push_back(Attribute::ZExt);
6635 Attrs.push_back(Attribute::InReg);
6637 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6641 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6642 /// implementation, which just calls LowerCall.
6643 /// FIXME: When all targets are
6644 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6645 std::pair<SDValue, SDValue>
6646 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6647 // Handle the incoming return values from the call.
6649 Type *OrigRetTy = CLI.RetTy;
6650 SmallVector<EVT, 4> RetTys;
6651 SmallVector<uint64_t, 4> Offsets;
6652 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6654 SmallVector<ISD::OutputArg, 4> Outs;
6655 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6657 bool CanLowerReturn =
6658 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6659 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6661 SDValue DemoteStackSlot;
6662 int DemoteStackIdx = -100;
6663 if (!CanLowerReturn) {
6664 // FIXME: equivalent assert?
6665 // assert(!CS.hasInAllocaArgument() &&
6666 // "sret demotion is incompatible with inalloca");
6667 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6668 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6669 MachineFunction &MF = CLI.DAG.getMachineFunction();
6670 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6671 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6673 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6675 Entry.Node = DemoteStackSlot;
6676 Entry.Ty = StackSlotPtrType;
6677 Entry.isSExt = false;
6678 Entry.isZExt = false;
6679 Entry.isInReg = false;
6680 Entry.isSRet = true;
6681 Entry.isNest = false;
6682 Entry.isByVal = false;
6683 Entry.isReturned = false;
6684 Entry.Alignment = Align;
6685 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6686 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6688 // sret demotion isn't compatible with tail-calls, since the sret argument
6689 // points into the callers stack frame.
6690 CLI.IsTailCall = false;
6692 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6694 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6695 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6696 for (unsigned i = 0; i != NumRegs; ++i) {
6697 ISD::InputArg MyFlags;
6698 MyFlags.VT = RegisterVT;
6700 MyFlags.Used = CLI.IsReturnValueUsed;
6702 MyFlags.Flags.setSExt();
6704 MyFlags.Flags.setZExt();
6706 MyFlags.Flags.setInReg();
6707 CLI.Ins.push_back(MyFlags);
6712 // Handle all of the outgoing arguments.
6714 CLI.OutVals.clear();
6715 ArgListTy &Args = CLI.getArgs();
6716 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6717 SmallVector<EVT, 4> ValueVTs;
6718 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6719 Type *FinalType = Args[i].Ty;
6720 if (Args[i].isByVal)
6721 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6722 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6723 FinalType, CLI.CallConv, CLI.IsVarArg);
6724 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6726 EVT VT = ValueVTs[Value];
6727 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6728 SDValue Op = SDValue(Args[i].Node.getNode(),
6729 Args[i].Node.getResNo() + Value);
6730 ISD::ArgFlagsTy Flags;
6731 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6737 if (Args[i].isInReg)
6741 if (Args[i].isByVal)
6743 if (Args[i].isInAlloca) {
6744 Flags.setInAlloca();
6745 // Set the byval flag for CCAssignFn callbacks that don't know about
6746 // inalloca. This way we can know how many bytes we should've allocated
6747 // and how many bytes a callee cleanup function will pop. If we port
6748 // inalloca to more targets, we'll have to add custom inalloca handling
6749 // in the various CC lowering callbacks.
6752 if (Args[i].isByVal || Args[i].isInAlloca) {
6753 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6754 Type *ElementTy = Ty->getElementType();
6755 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6756 // For ByVal, alignment should come from FE. BE will guess if this
6757 // info is not there but there are cases it cannot get right.
6758 unsigned FrameAlign;
6759 if (Args[i].Alignment)
6760 FrameAlign = Args[i].Alignment;
6762 FrameAlign = getByValTypeAlignment(ElementTy);
6763 Flags.setByValAlign(FrameAlign);
6768 Flags.setInConsecutiveRegs();
6769 Flags.setOrigAlign(OriginalAlignment);
6771 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6772 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6773 SmallVector<SDValue, 4> Parts(NumParts);
6774 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6777 ExtendKind = ISD::SIGN_EXTEND;
6778 else if (Args[i].isZExt)
6779 ExtendKind = ISD::ZERO_EXTEND;
6781 // Conservatively only handle 'returned' on non-vectors for now
6782 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6783 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6784 "unexpected use of 'returned'");
6785 // Before passing 'returned' to the target lowering code, ensure that
6786 // either the register MVT and the actual EVT are the same size or that
6787 // the return value and argument are extended in the same way; in these
6788 // cases it's safe to pass the argument register value unchanged as the
6789 // return register value (although it's at the target's option whether
6791 // TODO: allow code generation to take advantage of partially preserved
6792 // registers rather than clobbering the entire register when the
6793 // parameter extension method is not compatible with the return
6795 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6796 (ExtendKind != ISD::ANY_EXTEND &&
6797 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6798 Flags.setReturned();
6801 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6802 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6804 for (unsigned j = 0; j != NumParts; ++j) {
6805 // if it isn't first piece, alignment must be 1
6806 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6807 i < CLI.NumFixedArgs,
6808 i, j*Parts[j].getValueType().getStoreSize());
6809 if (NumParts > 1 && j == 0)
6810 MyFlags.Flags.setSplit();
6812 MyFlags.Flags.setOrigAlign(1);
6814 CLI.Outs.push_back(MyFlags);
6815 CLI.OutVals.push_back(Parts[j]);
6818 if (NeedsRegBlock && Value == NumValues - 1)
6819 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6823 SmallVector<SDValue, 4> InVals;
6824 CLI.Chain = LowerCall(CLI, InVals);
6826 // Verify that the target's LowerCall behaved as expected.
6827 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6828 "LowerCall didn't return a valid chain!");
6829 assert((!CLI.IsTailCall || InVals.empty()) &&
6830 "LowerCall emitted a return value for a tail call!");
6831 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6832 "LowerCall didn't emit the correct number of values!");
6834 // For a tail call, the return value is merely live-out and there aren't
6835 // any nodes in the DAG representing it. Return a special value to
6836 // indicate that a tail call has been emitted and no more Instructions
6837 // should be processed in the current block.
6838 if (CLI.IsTailCall) {
6839 CLI.DAG.setRoot(CLI.Chain);
6840 return std::make_pair(SDValue(), SDValue());
6843 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6844 assert(InVals[i].getNode() &&
6845 "LowerCall emitted a null value!");
6846 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6847 "LowerCall emitted a value with the wrong type!");
6850 SmallVector<SDValue, 4> ReturnValues;
6851 if (!CanLowerReturn) {
6852 // The instruction result is the result of loading from the
6853 // hidden sret parameter.
6854 SmallVector<EVT, 1> PVTs;
6855 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6857 ComputeValueVTs(*this, PtrRetTy, PVTs);
6858 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6859 EVT PtrVT = PVTs[0];
6861 unsigned NumValues = RetTys.size();
6862 ReturnValues.resize(NumValues);
6863 SmallVector<SDValue, 4> Chains(NumValues);
6865 for (unsigned i = 0; i < NumValues; ++i) {
6866 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6867 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6869 SDValue L = CLI.DAG.getLoad(
6870 RetTys[i], CLI.DL, CLI.Chain, Add,
6871 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6873 ReturnValues[i] = L;
6874 Chains[i] = L.getValue(1);
6877 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6879 // Collect the legal value parts into potentially illegal values
6880 // that correspond to the original function's return values.
6881 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6883 AssertOp = ISD::AssertSext;
6884 else if (CLI.RetZExt)
6885 AssertOp = ISD::AssertZext;
6886 unsigned CurReg = 0;
6887 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6889 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6890 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6892 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6893 NumRegs, RegisterVT, VT, nullptr,
6898 // For a function returning void, there is no return value. We can't create
6899 // such a node, so we just return a null return value in that case. In
6900 // that case, nothing will actually look at the value.
6901 if (ReturnValues.empty())
6902 return std::make_pair(SDValue(), CLI.Chain);
6905 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6906 CLI.DAG.getVTList(RetTys), ReturnValues);
6907 return std::make_pair(Res, CLI.Chain);
6910 void TargetLowering::LowerOperationWrapper(SDNode *N,
6911 SmallVectorImpl<SDValue> &Results,
6912 SelectionDAG &DAG) const {
6913 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6915 Results.push_back(Res);
6918 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6919 llvm_unreachable("LowerOperation not implemented for this target!");
6923 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6924 SDValue Op = getNonRegisterValue(V);
6925 assert((Op.getOpcode() != ISD::CopyFromReg ||
6926 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6927 "Copy from a reg to the same reg!");
6928 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6930 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6931 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6932 SDValue Chain = DAG.getEntryNode();
6934 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
6935 FuncInfo.PreferredExtendType.end())
6937 : FuncInfo.PreferredExtendType[V];
6938 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
6939 PendingExports.push_back(Chain);
6942 #include "llvm/CodeGen/SelectionDAGISel.h"
6944 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6945 /// entry block, return true. This includes arguments used by switches, since
6946 /// the switch may expand into multiple basic blocks.
6947 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6948 // With FastISel active, we may be splitting blocks, so force creation
6949 // of virtual registers for all non-dead arguments.
6951 return A->use_empty();
6953 const BasicBlock *Entry = A->getParent()->begin();
6954 for (const User *U : A->users())
6955 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6956 return false; // Use not in entry block.
6961 void SelectionDAGISel::LowerArguments(const Function &F) {
6962 SelectionDAG &DAG = SDB->DAG;
6963 SDLoc dl = SDB->getCurSDLoc();
6964 const DataLayout *DL = TLI->getDataLayout();
6965 SmallVector<ISD::InputArg, 16> Ins;
6967 if (!FuncInfo->CanLowerReturn) {
6968 // Put in an sret pointer parameter before all the other parameters.
6969 SmallVector<EVT, 1> ValueVTs;
6970 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6972 // NOTE: Assuming that a pointer will never break down to more than one VT
6974 ISD::ArgFlagsTy Flags;
6976 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
6977 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
6978 ISD::InputArg::NoArgIndex, 0);
6979 Ins.push_back(RetArg);
6982 // Set up the incoming argument description vector.
6984 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6985 I != E; ++I, ++Idx) {
6986 SmallVector<EVT, 4> ValueVTs;
6987 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6988 bool isArgValueUsed = !I->use_empty();
6989 unsigned PartBase = 0;
6990 Type *FinalType = I->getType();
6991 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
6992 FinalType = cast<PointerType>(FinalType)->getElementType();
6993 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
6994 FinalType, F.getCallingConv(), F.isVarArg());
6995 for (unsigned Value = 0, NumValues = ValueVTs.size();
6996 Value != NumValues; ++Value) {
6997 EVT VT = ValueVTs[Value];
6998 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6999 ISD::ArgFlagsTy Flags;
7000 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7002 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7004 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7006 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7008 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7010 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7012 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7013 Flags.setInAlloca();
7014 // Set the byval flag for CCAssignFn callbacks that don't know about
7015 // inalloca. This way we can know how many bytes we should've allocated
7016 // and how many bytes a callee cleanup function will pop. If we port
7017 // inalloca to more targets, we'll have to add custom inalloca handling
7018 // in the various CC lowering callbacks.
7021 if (Flags.isByVal() || Flags.isInAlloca()) {
7022 PointerType *Ty = cast<PointerType>(I->getType());
7023 Type *ElementTy = Ty->getElementType();
7024 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7025 // For ByVal, alignment should be passed from FE. BE will guess if
7026 // this info is not there but there are cases it cannot get right.
7027 unsigned FrameAlign;
7028 if (F.getParamAlignment(Idx))
7029 FrameAlign = F.getParamAlignment(Idx);
7031 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7032 Flags.setByValAlign(FrameAlign);
7034 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7037 Flags.setInConsecutiveRegs();
7038 Flags.setOrigAlign(OriginalAlignment);
7040 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7041 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7042 for (unsigned i = 0; i != NumRegs; ++i) {
7043 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7044 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7045 if (NumRegs > 1 && i == 0)
7046 MyFlags.Flags.setSplit();
7047 // if it isn't first piece, alignment must be 1
7049 MyFlags.Flags.setOrigAlign(1);
7050 Ins.push_back(MyFlags);
7052 if (NeedsRegBlock && Value == NumValues - 1)
7053 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7054 PartBase += VT.getStoreSize();
7058 // Call the target to set up the argument values.
7059 SmallVector<SDValue, 8> InVals;
7060 SDValue NewRoot = TLI->LowerFormalArguments(
7061 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7063 // Verify that the target's LowerFormalArguments behaved as expected.
7064 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7065 "LowerFormalArguments didn't return a valid chain!");
7066 assert(InVals.size() == Ins.size() &&
7067 "LowerFormalArguments didn't emit the correct number of values!");
7069 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7070 assert(InVals[i].getNode() &&
7071 "LowerFormalArguments emitted a null value!");
7072 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7073 "LowerFormalArguments emitted a value with the wrong type!");
7077 // Update the DAG with the new chain value resulting from argument lowering.
7078 DAG.setRoot(NewRoot);
7080 // Set up the argument values.
7083 if (!FuncInfo->CanLowerReturn) {
7084 // Create a virtual register for the sret pointer, and put in a copy
7085 // from the sret argument into it.
7086 SmallVector<EVT, 1> ValueVTs;
7087 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7088 MVT VT = ValueVTs[0].getSimpleVT();
7089 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7090 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7091 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7092 RegVT, VT, nullptr, AssertOp);
7094 MachineFunction& MF = SDB->DAG.getMachineFunction();
7095 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7096 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7097 FuncInfo->DemoteRegister = SRetReg;
7099 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7100 DAG.setRoot(NewRoot);
7102 // i indexes lowered arguments. Bump it past the hidden sret argument.
7103 // Idx indexes LLVM arguments. Don't touch it.
7107 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7109 SmallVector<SDValue, 4> ArgValues;
7110 SmallVector<EVT, 4> ValueVTs;
7111 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7112 unsigned NumValues = ValueVTs.size();
7114 // If this argument is unused then remember its value. It is used to generate
7115 // debugging information.
7116 if (I->use_empty() && NumValues) {
7117 SDB->setUnusedArgValue(I, InVals[i]);
7119 // Also remember any frame index for use in FastISel.
7120 if (FrameIndexSDNode *FI =
7121 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7122 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7125 for (unsigned Val = 0; Val != NumValues; ++Val) {
7126 EVT VT = ValueVTs[Val];
7127 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7128 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7130 if (!I->use_empty()) {
7131 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7132 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7133 AssertOp = ISD::AssertSext;
7134 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7135 AssertOp = ISD::AssertZext;
7137 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7138 NumParts, PartVT, VT,
7139 nullptr, AssertOp));
7145 // We don't need to do anything else for unused arguments.
7146 if (ArgValues.empty())
7149 // Note down frame index.
7150 if (FrameIndexSDNode *FI =
7151 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7152 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7154 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7155 SDB->getCurSDLoc());
7157 SDB->setValue(I, Res);
7158 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7159 if (LoadSDNode *LNode =
7160 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7161 if (FrameIndexSDNode *FI =
7162 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7163 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7166 // If this argument is live outside of the entry block, insert a copy from
7167 // wherever we got it to the vreg that other BB's will reference it as.
7168 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7169 // If we can, though, try to skip creating an unnecessary vreg.
7170 // FIXME: This isn't very clean... it would be nice to make this more
7171 // general. It's also subtly incompatible with the hacks FastISel
7173 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7174 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7175 FuncInfo->ValueMap[I] = Reg;
7179 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7180 FuncInfo->InitializeRegForValue(I);
7181 SDB->CopyToExportRegsIfNeeded(I);
7185 assert(i == InVals.size() && "Argument register count mismatch!");
7187 // Finally, if the target has anything special to do, allow it to do so.
7188 EmitFunctionEntryCode();
7191 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7192 /// ensure constants are generated when needed. Remember the virtual registers
7193 /// that need to be added to the Machine PHI nodes as input. We cannot just
7194 /// directly add them, because expansion might result in multiple MBB's for one
7195 /// BB. As such, the start of the BB might correspond to a different MBB than
7199 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7200 const TerminatorInst *TI = LLVMBB->getTerminator();
7202 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7204 // Check PHI nodes in successors that expect a value to be available from this
7206 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7207 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7208 if (!isa<PHINode>(SuccBB->begin())) continue;
7209 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7211 // If this terminator has multiple identical successors (common for
7212 // switches), only handle each succ once.
7213 if (!SuccsHandled.insert(SuccMBB).second)
7216 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7218 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7219 // nodes and Machine PHI nodes, but the incoming operands have not been
7221 for (BasicBlock::const_iterator I = SuccBB->begin();
7222 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7223 // Ignore dead phi's.
7224 if (PN->use_empty()) continue;
7227 if (PN->getType()->isEmptyTy())
7231 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7233 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7234 unsigned &RegOut = ConstantsOut[C];
7236 RegOut = FuncInfo.CreateRegs(C->getType());
7237 CopyValueToVirtualRegister(C, RegOut);
7241 DenseMap<const Value *, unsigned>::iterator I =
7242 FuncInfo.ValueMap.find(PHIOp);
7243 if (I != FuncInfo.ValueMap.end())
7246 assert(isa<AllocaInst>(PHIOp) &&
7247 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7248 "Didn't codegen value into a register!??");
7249 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7250 CopyValueToVirtualRegister(PHIOp, Reg);
7254 // Remember that this register needs to added to the machine PHI node as
7255 // the input for this MBB.
7256 SmallVector<EVT, 4> ValueVTs;
7257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7258 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7259 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7260 EVT VT = ValueVTs[vti];
7261 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7262 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7263 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7264 Reg += NumRegisters;
7269 ConstantsOut.clear();
7272 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7275 SelectionDAGBuilder::StackProtectorDescriptor::
7276 AddSuccessorMBB(const BasicBlock *BB,
7277 MachineBasicBlock *ParentMBB,
7279 MachineBasicBlock *SuccMBB) {
7280 // If SuccBB has not been created yet, create it.
7282 MachineFunction *MF = ParentMBB->getParent();
7283 MachineFunction::iterator BBI = ParentMBB;
7284 SuccMBB = MF->CreateMachineBasicBlock(BB);
7285 MF->insert(++BBI, SuccMBB);
7287 // Add it as a successor of ParentMBB.
7288 ParentMBB->addSuccessor(
7289 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7293 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7294 MachineFunction::iterator I = MBB;
7295 if (++I == FuncInfo.MF->end())
7300 /// During lowering new call nodes can be created (such as memset, etc.).
7301 /// Those will become new roots of the current DAG, but complications arise
7302 /// when they are tail calls. In such cases, the call lowering will update
7303 /// the root, but the builder still needs to know that a tail call has been
7304 /// lowered in order to avoid generating an additional return.
7305 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7306 // If the node is null, we do have a tail call.
7307 if (MaybeTC.getNode() != nullptr)
7308 DAG.setRoot(MaybeTC);
7313 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7314 unsigned *TotalCases, unsigned First,
7316 assert(Last >= First);
7317 assert(TotalCases[Last] >= TotalCases[First]);
7319 APInt LowCase = Clusters[First].Low->getValue();
7320 APInt HighCase = Clusters[Last].High->getValue();
7321 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7323 // FIXME: A range of consecutive cases has 100% density, but only requires one
7324 // comparison to lower. We should discriminate against such consecutive ranges
7327 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7328 uint64_t Range = Diff + 1;
7331 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7333 assert(NumCases < UINT64_MAX / 100);
7334 assert(Range >= NumCases);
7336 return NumCases * 100 >= Range * MinJumpTableDensity;
7339 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7340 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7341 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7344 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7345 unsigned First, unsigned Last,
7346 const SwitchInst *SI,
7347 MachineBasicBlock *DefaultMBB,
7348 CaseCluster &JTCluster) {
7349 assert(First <= Last);
7351 uint32_t Weight = 0;
7352 unsigned NumCmps = 0;
7353 std::vector<MachineBasicBlock*> Table;
7354 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7355 for (unsigned I = First; I <= Last; ++I) {
7356 assert(Clusters[I].Kind == CC_Range);
7357 Weight += Clusters[I].Weight;
7358 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7359 APInt Low = Clusters[I].Low->getValue();
7360 APInt High = Clusters[I].High->getValue();
7361 NumCmps += (Low == High) ? 1 : 2;
7363 // Fill the gap between this and the previous cluster.
7364 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7365 assert(PreviousHigh.slt(Low));
7366 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7367 for (uint64_t J = 0; J < Gap; J++)
7368 Table.push_back(DefaultMBB);
7370 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7371 for (uint64_t J = 0; J < ClusterSize; ++J)
7372 Table.push_back(Clusters[I].MBB);
7373 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7376 unsigned NumDests = JTWeights.size();
7377 if (isSuitableForBitTests(NumDests, NumCmps,
7378 Clusters[First].Low->getValue(),
7379 Clusters[Last].High->getValue())) {
7380 // Clusters[First..Last] should be lowered as bit tests instead.
7384 // Create the MBB that will load from and jump through the table.
7385 // Note: We create it here, but it's not inserted into the function yet.
7386 MachineFunction *CurMF = FuncInfo.MF;
7387 MachineBasicBlock *JumpTableMBB =
7388 CurMF->CreateMachineBasicBlock(SI->getParent());
7390 // Add successors. Note: use table order for determinism.
7391 SmallPtrSet<MachineBasicBlock *, 8> Done;
7392 for (MachineBasicBlock *Succ : Table) {
7393 if (Done.count(Succ))
7395 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7399 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7400 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7401 ->createJumpTableIndex(Table);
7403 // Set up the jump table info.
7404 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7405 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7406 Clusters[Last].High->getValue(), SI->getCondition(),
7408 JTCases.push_back(JumpTableBlock(JTH, JT));
7410 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7411 JTCases.size() - 1, Weight);
7415 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7416 const SwitchInst *SI,
7417 MachineBasicBlock *DefaultMBB) {
7419 // Clusters must be non-empty, sorted, and only contain Range clusters.
7420 assert(!Clusters.empty());
7421 for (CaseCluster &C : Clusters)
7422 assert(C.Kind == CC_Range);
7423 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7424 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7428 if (!areJTsAllowed(TLI))
7431 const int64_t N = Clusters.size();
7432 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7434 // Split Clusters into minimum number of dense partitions. The algorithm uses
7435 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7436 // for the Case Statement'" (1994), but builds the MinPartitions array in
7437 // reverse order to make it easier to reconstruct the partitions in ascending
7438 // order. In the choice between two optimal partitionings, it picks the one
7439 // which yields more jump tables.
7441 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7442 SmallVector<unsigned, 8> MinPartitions(N);
7443 // LastElement[i] is the last element of the partition starting at i.
7444 SmallVector<unsigned, 8> LastElement(N);
7445 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7446 SmallVector<unsigned, 8> NumTables(N);
7447 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7448 SmallVector<unsigned, 8> TotalCases(N);
7450 for (unsigned i = 0; i < N; ++i) {
7451 APInt Hi = Clusters[i].High->getValue();
7452 APInt Lo = Clusters[i].Low->getValue();
7453 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7455 TotalCases[i] += TotalCases[i - 1];
7458 // Base case: There is only one way to partition Clusters[N-1].
7459 MinPartitions[N - 1] = 1;
7460 LastElement[N - 1] = N - 1;
7461 assert(MinJumpTableSize > 1);
7462 NumTables[N - 1] = 0;
7464 // Note: loop indexes are signed to avoid underflow.
7465 for (int64_t i = N - 2; i >= 0; i--) {
7466 // Find optimal partitioning of Clusters[i..N-1].
7467 // Baseline: Put Clusters[i] into a partition on its own.
7468 MinPartitions[i] = MinPartitions[i + 1] + 1;
7470 NumTables[i] = NumTables[i + 1];
7472 // Search for a solution that results in fewer partitions.
7473 for (int64_t j = N - 1; j > i; j--) {
7474 // Try building a partition from Clusters[i..j].
7475 if (isDense(Clusters, &TotalCases[0], i, j)) {
7476 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7477 bool IsTable = j - i + 1 >= MinJumpTableSize;
7478 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7480 // If this j leads to fewer partitions, or same number of partitions
7481 // with more lookup tables, it is a better partitioning.
7482 if (NumPartitions < MinPartitions[i] ||
7483 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7484 MinPartitions[i] = NumPartitions;
7486 NumTables[i] = Tables;
7492 // Iterate over the partitions, replacing some with jump tables in-place.
7493 unsigned DstIndex = 0;
7494 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7495 Last = LastElement[First];
7496 assert(Last >= First);
7497 assert(DstIndex <= First);
7498 unsigned NumClusters = Last - First + 1;
7500 CaseCluster JTCluster;
7501 if (NumClusters >= MinJumpTableSize &&
7502 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7503 Clusters[DstIndex++] = JTCluster;
7505 for (unsigned I = First; I <= Last; ++I)
7506 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7509 Clusters.resize(DstIndex);
7512 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7513 // FIXME: Using the pointer type doesn't seem ideal.
7514 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7515 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7519 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7522 const APInt &High) {
7523 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7524 // range of cases both require only one branch to lower. Just looking at the
7525 // number of clusters and destinations should be enough to decide whether to
7528 // To lower a range with bit tests, the range must fit the bitwidth of a
7530 if (!rangeFitsInWord(Low, High))
7533 // Decide whether it's profitable to lower this range with bit tests. Each
7534 // destination requires a bit test and branch, and there is an overall range
7535 // check branch. For a small number of clusters, separate comparisons might be
7536 // cheaper, and for many destinations, splitting the range might be better.
7537 return (NumDests == 1 && NumCmps >= 3) ||
7538 (NumDests == 2 && NumCmps >= 5) ||
7539 (NumDests == 3 && NumCmps >= 6);
7542 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7543 unsigned First, unsigned Last,
7544 const SwitchInst *SI,
7545 CaseCluster &BTCluster) {
7546 assert(First <= Last);
7550 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7551 unsigned NumCmps = 0;
7552 for (int64_t I = First; I <= Last; ++I) {
7553 assert(Clusters[I].Kind == CC_Range);
7554 Dests.set(Clusters[I].MBB->getNumber());
7555 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7557 unsigned NumDests = Dests.count();
7559 APInt Low = Clusters[First].Low->getValue();
7560 APInt High = Clusters[Last].High->getValue();
7561 assert(Low.slt(High));
7563 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7569 const int BitWidth =
7570 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7571 assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
7573 if (Low.isNonNegative() && High.slt(BitWidth)) {
7574 // Optimize the case where all the case values fit in a
7575 // word without having to subtract minValue. In this case,
7576 // we can optimize away the subtraction.
7577 LowBound = APInt::getNullValue(Low.getBitWidth());
7581 CmpRange = High - Low;
7585 uint32_t TotalWeight = 0;
7586 for (unsigned i = First; i <= Last; ++i) {
7587 // Find the CaseBits for this destination.
7589 for (j = 0; j < CBV.size(); ++j)
7590 if (CBV[j].BB == Clusters[i].MBB)
7592 if (j == CBV.size())
7593 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7594 CaseBits *CB = &CBV[j];
7596 // Update Mask, Bits and ExtraWeight.
7597 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7598 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7599 for (uint64_t j = Lo; j <= Hi; ++j) {
7600 CB->Mask |= 1ULL << j;
7603 CB->ExtraWeight += Clusters[i].Weight;
7604 TotalWeight += Clusters[i].Weight;
7605 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7609 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7610 // Sort by weight first, number of bits second.
7611 if (a.ExtraWeight != b.ExtraWeight)
7612 return a.ExtraWeight > b.ExtraWeight;
7613 return a.Bits > b.Bits;
7616 for (auto &CB : CBV) {
7617 MachineBasicBlock *BitTestBB =
7618 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7619 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7621 BitTestCases.push_back(BitTestBlock(LowBound, CmpRange, SI->getCondition(),
7622 -1U, MVT::Other, false, nullptr,
7623 nullptr, std::move(BTI)));
7625 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7626 BitTestCases.size() - 1, TotalWeight);
7630 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7631 const SwitchInst *SI) {
7632 // Partition Clusters into as few subsets as possible, where each subset has a
7633 // range that fits in a machine word and has <= 3 unique destinations.
7636 // Clusters must be sorted and contain Range or JumpTable clusters.
7637 assert(!Clusters.empty());
7638 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7639 for (const CaseCluster &C : Clusters)
7640 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7641 for (unsigned i = 1; i < Clusters.size(); ++i)
7642 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7645 // If target does not have legal shift left, do not emit bit tests at all.
7646 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7647 EVT PTy = TLI.getPointerTy();
7648 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7651 int BitWidth = PTy.getSizeInBits();
7652 const int64_t N = Clusters.size();
7654 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7655 SmallVector<unsigned, 8> MinPartitions(N);
7656 // LastElement[i] is the last element of the partition starting at i.
7657 SmallVector<unsigned, 8> LastElement(N);
7659 // FIXME: This might not be the best algorithm for finding bit test clusters.
7661 // Base case: There is only one way to partition Clusters[N-1].
7662 MinPartitions[N - 1] = 1;
7663 LastElement[N - 1] = N - 1;
7665 // Note: loop indexes are signed to avoid underflow.
7666 for (int64_t i = N - 2; i >= 0; --i) {
7667 // Find optimal partitioning of Clusters[i..N-1].
7668 // Baseline: Put Clusters[i] into a partition on its own.
7669 MinPartitions[i] = MinPartitions[i + 1] + 1;
7672 // Search for a solution that results in fewer partitions.
7673 // Note: the search is limited by BitWidth, reducing time complexity.
7674 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7675 // Try building a partition from Clusters[i..j].
7678 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7679 Clusters[j].High->getValue()))
7682 // Check nbr of destinations and cluster types.
7683 // FIXME: This works, but doesn't seem very efficient.
7684 bool RangesOnly = true;
7685 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7686 for (int64_t k = i; k <= j; k++) {
7687 if (Clusters[k].Kind != CC_Range) {
7691 Dests.set(Clusters[k].MBB->getNumber());
7693 if (!RangesOnly || Dests.count() > 3)
7696 // Check if it's a better partition.
7697 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7698 if (NumPartitions < MinPartitions[i]) {
7699 // Found a better partition.
7700 MinPartitions[i] = NumPartitions;
7706 // Iterate over the partitions, replacing with bit-test clusters in-place.
7707 unsigned DstIndex = 0;
7708 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7709 Last = LastElement[First];
7710 assert(First <= Last);
7711 assert(DstIndex <= First);
7713 CaseCluster BitTestCluster;
7714 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7715 Clusters[DstIndex++] = BitTestCluster;
7717 for (unsigned I = First; I <= Last; ++I)
7718 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7721 Clusters.resize(DstIndex);
7724 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7725 MachineBasicBlock *SwitchMBB,
7726 MachineBasicBlock *DefaultMBB) {
7727 MachineFunction *CurMF = FuncInfo.MF;
7728 MachineBasicBlock *NextMBB = nullptr;
7729 MachineFunction::iterator BBI = W.MBB;
7730 if (++BBI != FuncInfo.MF->end())
7733 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7735 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7737 if (Size == 2 && W.MBB == SwitchMBB) {
7738 // If any two of the cases has the same destination, and if one value
7739 // is the same as the other, but has one bit unset that the other has set,
7740 // use bit manipulation to do two compares at once. For example:
7741 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7742 // TODO: This could be extended to merge any 2 cases in switches with 3
7744 // TODO: Handle cases where W.CaseBB != SwitchBB.
7745 CaseCluster &Small = *W.FirstCluster;
7746 CaseCluster &Big = *W.LastCluster;
7748 if (Small.Low == Small.High && Big.Low == Big.High &&
7749 Small.MBB == Big.MBB) {
7750 const APInt &SmallValue = Small.Low->getValue();
7751 const APInt &BigValue = Big.Low->getValue();
7753 // Check that there is only one bit different.
7754 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
7755 (SmallValue | BigValue) == BigValue) {
7756 // Isolate the common bit.
7757 APInt CommonBit = BigValue & ~SmallValue;
7758 assert((SmallValue | CommonBit) == BigValue &&
7759 CommonBit.countPopulation() == 1 && "Not a common bit?");
7761 SDValue CondLHS = getValue(Cond);
7762 EVT VT = CondLHS.getValueType();
7763 SDLoc DL = getCurSDLoc();
7765 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7766 DAG.getConstant(CommonBit, DL, VT));
7767 SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
7768 DAG.getConstant(BigValue, DL, VT),
7771 // Update successor info.
7772 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7773 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7774 addSuccessorWithWeight(
7775 SwitchMBB, DefaultMBB,
7776 // The default destination is the first successor in IR.
7777 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7780 // Insert the true branch.
7782 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7783 DAG.getBasicBlock(Small.MBB));
7784 // Insert the false branch.
7785 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7786 DAG.getBasicBlock(DefaultMBB));
7788 DAG.setRoot(BrCond);
7794 if (TM.getOptLevel() != CodeGenOpt::None) {
7795 // Order cases by weight so the most likely case will be checked first.
7796 std::sort(W.FirstCluster, W.LastCluster + 1,
7797 [](const CaseCluster &a, const CaseCluster &b) {
7798 return a.Weight > b.Weight;
7801 // Rearrange the case blocks so that the last one falls through if possible
7802 // without without changing the order of weights.
7803 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7805 if (I->Weight > W.LastCluster->Weight)
7807 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7808 std::swap(*I, *W.LastCluster);
7814 // Compute total weight.
7815 uint32_t UnhandledWeights = 0;
7816 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7817 UnhandledWeights += I->Weight;
7818 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7821 MachineBasicBlock *CurMBB = W.MBB;
7822 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7823 MachineBasicBlock *Fallthrough;
7824 if (I == W.LastCluster) {
7825 // For the last cluster, fall through to the default destination.
7826 Fallthrough = DefaultMBB;
7828 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7829 CurMF->insert(BBI, Fallthrough);
7830 // Put Cond in a virtual register to make it available from the new blocks.
7831 ExportFromCurrentBlock(Cond);
7835 case CC_JumpTable: {
7836 // FIXME: Optimize away range check based on pivot comparisons.
7837 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7838 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7840 // The jump block hasn't been inserted yet; insert it here.
7841 MachineBasicBlock *JumpMBB = JT->MBB;
7842 CurMF->insert(BBI, JumpMBB);
7843 addSuccessorWithWeight(CurMBB, Fallthrough);
7844 addSuccessorWithWeight(CurMBB, JumpMBB);
7846 // The jump table header will be inserted in our current block, do the
7847 // range check, and fall through to our fallthrough block.
7848 JTH->HeaderBB = CurMBB;
7849 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7851 // If we're in the right place, emit the jump table header right now.
7852 if (CurMBB == SwitchMBB) {
7853 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7854 JTH->Emitted = true;
7859 // FIXME: Optimize away range check based on pivot comparisons.
7860 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7862 // The bit test blocks haven't been inserted yet; insert them here.
7863 for (BitTestCase &BTC : BTB->Cases)
7864 CurMF->insert(BBI, BTC.ThisBB);
7866 // Fill in fields of the BitTestBlock.
7867 BTB->Parent = CurMBB;
7868 BTB->Default = Fallthrough;
7870 // If we're in the right place, emit the bit test header header right now.
7871 if (CurMBB ==SwitchMBB) {
7872 visitBitTestHeader(*BTB, SwitchMBB);
7873 BTB->Emitted = true;
7878 const Value *RHS, *LHS, *MHS;
7880 if (I->Low == I->High) {
7881 // Check Cond == I->Low.
7887 // Check I->Low <= Cond <= I->High.
7894 // The false weight is the sum of all unhandled cases.
7895 UnhandledWeights -= I->Weight;
7896 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7899 if (CurMBB == SwitchMBB)
7900 visitSwitchCase(CB, SwitchMBB);
7902 SwitchCases.push_back(CB);
7907 CurMBB = Fallthrough;
7911 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7912 const SwitchWorkListItem &W,
7914 MachineBasicBlock *SwitchMBB) {
7915 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7916 "Clusters not sorted?");
7918 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
7920 // Balance the tree based on branch weights to create a near-optimal (in terms
7921 // of search time given key frequency) binary search tree. See e.g. Kurt
7922 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
7923 CaseClusterIt LastLeft = W.FirstCluster;
7924 CaseClusterIt FirstRight = W.LastCluster;
7925 uint32_t LeftWeight = LastLeft->Weight;
7926 uint32_t RightWeight = FirstRight->Weight;
7928 // Move LastLeft and FirstRight towards each other from opposite directions to
7929 // find a partitioning of the clusters which balances the weight on both
7930 // sides. If LeftWeight and RightWeight are equal, alternate which side is
7931 // taken to ensure 0-weight nodes are distributed evenly.
7933 while (LastLeft + 1 < FirstRight) {
7934 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
7935 LeftWeight += (++LastLeft)->Weight;
7937 RightWeight += (--FirstRight)->Weight;
7940 assert(LastLeft + 1 == FirstRight);
7941 assert(LastLeft >= W.FirstCluster);
7942 assert(FirstRight <= W.LastCluster);
7944 // Use the first element on the right as pivot since we will make less-than
7945 // comparisons against it.
7946 CaseClusterIt PivotCluster = FirstRight;
7947 assert(PivotCluster > W.FirstCluster);
7948 assert(PivotCluster <= W.LastCluster);
7950 CaseClusterIt FirstLeft = W.FirstCluster;
7951 CaseClusterIt LastRight = W.LastCluster;
7953 const ConstantInt *Pivot = PivotCluster->Low;
7955 // New blocks will be inserted immediately after the current one.
7956 MachineFunction::iterator BBI = W.MBB;
7959 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
7960 // we can branch to its destination directly if it's squeezed exactly in
7961 // between the known lower bound and Pivot - 1.
7962 MachineBasicBlock *LeftMBB;
7963 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
7964 FirstLeft->Low == W.GE &&
7965 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
7966 LeftMBB = FirstLeft->MBB;
7968 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
7969 FuncInfo.MF->insert(BBI, LeftMBB);
7970 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
7971 // Put Cond in a virtual register to make it available from the new blocks.
7972 ExportFromCurrentBlock(Cond);
7975 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
7976 // single cluster, RHS.Low == Pivot, and we can branch to its destination
7977 // directly if RHS.High equals the current upper bound.
7978 MachineBasicBlock *RightMBB;
7979 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
7980 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
7981 RightMBB = FirstRight->MBB;
7983 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
7984 FuncInfo.MF->insert(BBI, RightMBB);
7985 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
7986 // Put Cond in a virtual register to make it available from the new blocks.
7987 ExportFromCurrentBlock(Cond);
7990 // Create the CaseBlock record that will be used to lower the branch.
7991 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
7992 LeftWeight, RightWeight);
7994 if (W.MBB == SwitchMBB)
7995 visitSwitchCase(CB, SwitchMBB);
7997 SwitchCases.push_back(CB);
8000 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8001 // Extract cases from the switch.
8002 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8003 CaseClusterVector Clusters;
8004 Clusters.reserve(SI.getNumCases());
8005 for (auto I : SI.cases()) {
8006 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8007 const ConstantInt *CaseVal = I.getCaseValue();
8009 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8010 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8013 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8015 // Cluster adjacent cases with the same destination. We do this at all
8016 // optimization levels because it's cheap to do and will make codegen faster
8017 // if there are many clusters.
8018 sortAndRangeify(Clusters);
8020 if (TM.getOptLevel() != CodeGenOpt::None) {
8021 // Replace an unreachable default with the most popular destination.
8022 // FIXME: Exploit unreachable default more aggressively.
8023 bool UnreachableDefault =
8024 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8025 if (UnreachableDefault && !Clusters.empty()) {
8026 DenseMap<const BasicBlock *, unsigned> Popularity;
8027 unsigned MaxPop = 0;
8028 const BasicBlock *MaxBB = nullptr;
8029 for (auto I : SI.cases()) {
8030 const BasicBlock *BB = I.getCaseSuccessor();
8031 if (++Popularity[BB] > MaxPop) {
8032 MaxPop = Popularity[BB];
8037 assert(MaxPop > 0 && MaxBB);
8038 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8040 // Remove cases that were pointing to the destination that is now the
8042 CaseClusterVector New;
8043 New.reserve(Clusters.size());
8044 for (CaseCluster &CC : Clusters) {
8045 if (CC.MBB != DefaultMBB)
8048 Clusters = std::move(New);
8052 // If there is only the default destination, jump there directly.
8053 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8054 if (Clusters.empty()) {
8055 SwitchMBB->addSuccessor(DefaultMBB);
8056 if (DefaultMBB != NextBlock(SwitchMBB)) {
8057 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8058 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8063 if (TM.getOptLevel() != CodeGenOpt::None) {
8064 findJumpTables(Clusters, &SI, DefaultMBB);
8065 findBitTestClusters(Clusters, &SI);
8070 dbgs() << "Case clusters: ";
8071 for (const CaseCluster &C : Clusters) {
8072 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8073 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8075 C.Low->getValue().print(dbgs(), true);
8076 if (C.Low != C.High) {
8078 C.High->getValue().print(dbgs(), true);
8085 assert(!Clusters.empty());
8086 SwitchWorkList WorkList;
8087 CaseClusterIt First = Clusters.begin();
8088 CaseClusterIt Last = Clusters.end() - 1;
8089 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8091 while (!WorkList.empty()) {
8092 SwitchWorkListItem W = WorkList.back();
8093 WorkList.pop_back();
8094 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8096 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8097 // For optimized builds, lower large range as a balanced binary tree.
8098 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8102 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);