1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static cl::opt<unsigned>
88 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
89 cl::init(64), cl::Hidden);
91 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
92 const SDValue *Parts, unsigned NumParts,
93 EVT PartVT, EVT ValueVT);
95 /// getCopyFromParts - Create a value that contains the specified legal parts
96 /// combined into the value they represent. If the parts combine to a type
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
100 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
101 const SDValue *Parts,
102 unsigned NumParts, EVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
107 assert(NumParts > 0 && "No parts to assemble!");
108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
109 SDValue Val = Parts[0];
112 // Assemble the value from multiple parts.
113 if (ValueVT.isInteger()) {
114 unsigned PartBits = PartVT.getSizeInBits();
115 unsigned ValueBits = ValueVT.getSizeInBits();
117 // Assemble the power of 2 part.
118 unsigned RoundParts = NumParts & (NumParts - 1) ?
119 1 << Log2_32(NumParts) : NumParts;
120 unsigned RoundBits = PartBits * RoundParts;
121 EVT RoundVT = RoundBits == ValueBits ?
122 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
125 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
127 if (RoundParts > 2) {
128 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
130 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
131 RoundParts / 2, PartVT, HalfVT);
133 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
134 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
137 if (TLI.isBigEndian())
140 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
142 if (RoundParts < NumParts) {
143 // Assemble the trailing non-power-of-2 part.
144 unsigned OddParts = NumParts - RoundParts;
145 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
146 Hi = getCopyFromParts(DAG, DL,
147 Parts + RoundParts, OddParts, PartVT, OddVT);
149 // Combine the round and odd parts.
151 if (TLI.isBigEndian())
153 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
154 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
155 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
156 DAG.getConstant(Lo.getValueType().getSizeInBits(),
157 TLI.getPointerTy()));
158 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
159 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
161 } else if (PartVT.isFloatingPoint()) {
162 // FP split into multiple FP parts (for ppcf128)
163 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
166 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
167 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
168 if (TLI.isBigEndian())
170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
172 // FP split into integer parts (soft fp)
173 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
174 !PartVT.isVector() && "Unexpected split");
175 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
176 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
180 // There is now one part, held in Val. Correct it to match ValueVT.
181 PartVT = Val.getValueType();
183 if (PartVT == ValueVT)
186 if (PartVT.isInteger() && ValueVT.isInteger()) {
187 if (ValueVT.bitsLT(PartVT)) {
188 // For a truncate, see if we have any information to
189 // indicate whether the truncated bits will always be
190 // zero or sign-extension.
191 if (AssertOp != ISD::DELETED_NODE)
192 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
193 DAG.getValueType(ValueVT));
194 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
196 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
199 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
200 // FP_ROUND's are always exact here.
201 if (ValueVT.bitsLT(Val.getValueType()))
202 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
203 DAG.getIntPtrConstant(1));
205 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
208 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
209 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
211 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromParts - Create a value that contains the specified legal parts
216 /// combined into the value they represent. If the parts combine to a type
217 /// larger then ValueVT then AssertOp can be used to specify whether the extra
218 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
219 /// (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 EVT PartVT, EVT ValueVT) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
230 EVT IntermediateVT, RegisterVT;
231 unsigned NumIntermediates;
233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
234 NumIntermediates, RegisterVT);
235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
236 NumParts = NumRegs; // Silence a compiler warning.
237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
238 assert(RegisterVT == Parts[0].getValueType() &&
239 "Part type doesn't match part!");
241 // Assemble the parts into intermediate operands.
242 SmallVector<SDValue, 8> Ops(NumIntermediates);
243 if (NumIntermediates == NumParts) {
244 // If the register was not expanded, truncate or copy the value,
246 for (unsigned i = 0; i != NumParts; ++i)
247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
248 PartVT, IntermediateVT);
249 } else if (NumParts > 0) {
250 // If the intermediate type was expanded, build the intermediate
251 // operands from the parts.
252 assert(NumParts % NumIntermediates == 0 &&
253 "Must expand into a divisible number of parts!");
254 unsigned Factor = NumParts / NumIntermediates;
255 for (unsigned i = 0; i != NumIntermediates; ++i)
256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
257 PartVT, IntermediateVT);
260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
261 // intermediate operands.
262 Val = DAG.getNode(IntermediateVT.isVector() ?
263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
264 ValueVT, &Ops[0], NumIntermediates);
267 // There is now one part, held in Val. Correct it to match ValueVT.
268 PartVT = Val.getValueType();
270 if (PartVT == ValueVT)
273 if (PartVT.isVector()) {
274 // If the element type of the source/dest vectors are the same, but the
275 // parts vector has more elements than the value vector, then we have a
276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
280 "Cannot narrow, it would be a lossy transformation");
281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
282 DAG.getIntPtrConstant(0));
285 // Vector/Vector bitcast.
286 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
289 assert(ValueVT.getVectorElementType() == PartVT &&
290 ValueVT.getVectorNumElements() == 1 &&
291 "Only trivial scalar-to-vector conversions should get here!");
292 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
298 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
299 SDValue Val, SDValue *Parts, unsigned NumParts,
302 /// getCopyToParts - Create a series of nodes that contain the specified value
303 /// split into legal parts. If the parts contain more bits than Val, then, for
304 /// integers, ExtendKind can be used to specify how to generate the extra bits.
305 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
306 SDValue Val, SDValue *Parts, unsigned NumParts,
308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
309 EVT ValueVT = Val.getValueType();
311 // Handle the vector case separately.
312 if (ValueVT.isVector())
313 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
316 unsigned PartBits = PartVT.getSizeInBits();
317 unsigned OrigNumParts = NumParts;
318 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
323 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
324 if (PartVT == ValueVT) {
325 assert(NumParts == 1 && "No-op copy with multiple parts!");
330 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
331 // If the parts cover more bits than the value has, promote the value.
332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
333 assert(NumParts == 1 && "Do not know what to promote to!");
334 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
336 assert(PartVT.isInteger() && ValueVT.isInteger() &&
337 "Unknown mismatch!");
338 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
339 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
341 } else if (PartBits == ValueVT.getSizeInBits()) {
342 // Different types of the same size.
343 assert(NumParts == 1 && PartVT != ValueVT);
344 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
345 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
346 // If the parts cover less bits than value has, truncate the value.
347 assert(PartVT.isInteger() && ValueVT.isInteger() &&
348 "Unknown mismatch!");
349 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
353 // The value may have changed - recompute ValueVT.
354 ValueVT = Val.getValueType();
355 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
356 "Failed to tile the value with PartVT!");
359 assert(PartVT == ValueVT && "Type conversion failed!");
364 // Expand the value into multiple parts.
365 if (NumParts & (NumParts - 1)) {
366 // The number of parts is not a power of 2. Split off and copy the tail.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Do not know what to expand to!");
369 unsigned RoundParts = 1 << Log2_32(NumParts);
370 unsigned RoundBits = RoundParts * PartBits;
371 unsigned OddParts = NumParts - RoundParts;
372 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
373 DAG.getIntPtrConstant(RoundBits));
374 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
376 if (TLI.isBigEndian())
377 // The odd parts were reversed by getCopyToParts - unreverse them.
378 std::reverse(Parts + RoundParts, Parts + NumParts);
380 NumParts = RoundParts;
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
385 // The number of parts is a power of 2. Repeatedly bisect the value using
387 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
388 EVT::getIntegerVT(*DAG.getContext(),
389 ValueVT.getSizeInBits()),
392 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
393 for (unsigned i = 0; i < NumParts; i += StepSize) {
394 unsigned ThisBits = StepSize * PartBits / 2;
395 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
396 SDValue &Part0 = Parts[i];
397 SDValue &Part1 = Parts[i+StepSize/2];
399 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
400 ThisVT, Part0, DAG.getIntPtrConstant(1));
401 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
402 ThisVT, Part0, DAG.getIntPtrConstant(0));
404 if (ThisBits == PartBits && ThisVT != PartVT) {
405 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
406 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
411 if (TLI.isBigEndian())
412 std::reverse(Parts, Parts + OrigNumParts);
416 /// getCopyToPartsVector - Create a series of nodes that contain the specified
417 /// value split into legal parts.
418 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
419 SDValue Val, SDValue *Parts, unsigned NumParts,
421 EVT ValueVT = Val.getValueType();
422 assert(ValueVT.isVector() && "Not a vector");
423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
426 if (PartVT == ValueVT) {
428 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
429 // Bitconvert vector->vector case.
430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
431 } else if (PartVT.isVector() &&
432 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
433 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
434 EVT ElementVT = PartVT.getVectorElementType();
435 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
437 SmallVector<SDValue, 16> Ops;
438 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
439 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
440 ElementVT, Val, DAG.getIntPtrConstant(i)));
442 for (unsigned i = ValueVT.getVectorNumElements(),
443 e = PartVT.getVectorNumElements(); i != e; ++i)
444 Ops.push_back(DAG.getUNDEF(ElementVT));
446 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
448 // FIXME: Use CONCAT for 2x -> 4x.
450 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
451 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
453 // Vector -> scalar conversion.
454 assert(ValueVT.getVectorElementType() == PartVT &&
455 ValueVT.getVectorNumElements() == 1 &&
456 "Only trivial vector-to-scalar conversions should get here!");
457 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
458 PartVT, Val, DAG.getIntPtrConstant(0));
465 // Handle a multi-element vector.
466 EVT IntermediateVT, RegisterVT;
467 unsigned NumIntermediates;
468 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
470 NumIntermediates, RegisterVT);
471 unsigned NumElements = ValueVT.getVectorNumElements();
473 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
474 NumParts = NumRegs; // Silence a compiler warning.
475 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
477 // Split the vector into intermediate operands.
478 SmallVector<SDValue, 8> Ops(NumIntermediates);
479 for (unsigned i = 0; i != NumIntermediates; ++i) {
480 if (IntermediateVT.isVector())
481 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
483 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
485 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 IntermediateVT, Val, DAG.getIntPtrConstant(i));
489 // Split the intermediate operands into legal parts.
490 if (NumParts == NumIntermediates) {
491 // If the register was not expanded, promote or copy the value,
493 for (unsigned i = 0; i != NumParts; ++i)
494 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
495 } else if (NumParts > 0) {
496 // If the intermediate type was expanded, split each the value into
498 assert(NumParts % NumIntermediates == 0 &&
499 "Must expand into a divisible number of parts!");
500 unsigned Factor = NumParts / NumIntermediates;
501 for (unsigned i = 0; i != NumIntermediates; ++i)
502 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
510 /// RegsForValue - This struct represents the registers (physical or virtual)
511 /// that a particular set of values is assigned, and the type information
512 /// about the value. The most common situation is to represent one value at a
513 /// time, but struct or array values are handled element-wise as multiple
514 /// values. The splitting of aggregates is performed recursively, so that we
515 /// never have aggregate-typed registers. The values at this point do not
516 /// necessarily have legal types, so each value may require one or more
517 /// registers of some legal type.
519 struct RegsForValue {
520 /// ValueVTs - The value types of the values, which may not be legal, and
521 /// may need be promoted or synthesized from one or more registers.
523 SmallVector<EVT, 4> ValueVTs;
525 /// RegVTs - The value types of the registers. This is the same size as
526 /// ValueVTs and it records, for each value, what the type of the assigned
527 /// register or registers are. (Individual values are never synthesized
528 /// from more than one type of register.)
530 /// With virtual registers, the contents of RegVTs is redundant with TLI's
531 /// getRegisterType member function, however when with physical registers
532 /// it is necessary to have a separate record of the types.
534 SmallVector<EVT, 4> RegVTs;
536 /// Regs - This list holds the registers assigned to the values.
537 /// Each legal or promoted value requires one register, and each
538 /// expanded value requires multiple registers.
540 SmallVector<unsigned, 4> Regs;
544 RegsForValue(const SmallVector<unsigned, 4> ®s,
545 EVT regvt, EVT valuevt)
546 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
548 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
549 unsigned Reg, const Type *Ty) {
550 ComputeValueVTs(tli, Ty, ValueVTs);
552 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
553 EVT ValueVT = ValueVTs[Value];
554 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
555 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
556 for (unsigned i = 0; i != NumRegs; ++i)
557 Regs.push_back(Reg + i);
558 RegVTs.push_back(RegisterVT);
563 /// areValueTypesLegal - Return true if types of all the values are legal.
564 bool areValueTypesLegal(const TargetLowering &TLI) {
565 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
566 EVT RegisterVT = RegVTs[Value];
567 if (!TLI.isTypeLegal(RegisterVT))
573 /// append - Add the specified values to this one.
574 void append(const RegsForValue &RHS) {
575 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
576 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
577 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
580 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
581 /// this value and returns the result as a ValueVTs value. This uses
582 /// Chain/Flag as the input and updates them for the output Chain/Flag.
583 /// If the Flag pointer is NULL, no flag is used.
584 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
586 SDValue &Chain, SDValue *Flag) const;
588 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
589 /// specified value into the registers specified by this object. This uses
590 /// Chain/Flag as the input and updates them for the output Chain/Flag.
591 /// If the Flag pointer is NULL, no flag is used.
592 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
593 SDValue &Chain, SDValue *Flag) const;
595 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
596 /// operand list. This adds the code marker, matching input operand index
597 /// (if applicable), and includes the number of values added into it.
598 void AddInlineAsmOperands(unsigned Kind,
599 bool HasMatching, unsigned MatchingIdx,
601 std::vector<SDValue> &Ops) const;
605 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
606 /// this value and returns the result as a ValueVT value. This uses
607 /// Chain/Flag as the input and updates them for the output Chain/Flag.
608 /// If the Flag pointer is NULL, no flag is used.
609 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
610 FunctionLoweringInfo &FuncInfo,
612 SDValue &Chain, SDValue *Flag) const {
613 // A Value with type {} or [0 x %t] needs no registers.
614 if (ValueVTs.empty())
617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
619 // Assemble the legal parts into the final values.
620 SmallVector<SDValue, 4> Values(ValueVTs.size());
621 SmallVector<SDValue, 8> Parts;
622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 // Copy the legal parts from the registers.
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
626 EVT RegisterVT = RegVTs[Value];
628 Parts.resize(NumRegs);
629 for (unsigned i = 0; i != NumRegs; ++i) {
632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
635 *Flag = P.getValue(2);
638 Chain = P.getValue(1);
641 // If the source register was virtual and if we know something about it,
642 // add an assert node.
643 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
644 !RegisterVT.isInteger() || RegisterVT.isVector() ||
645 !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i]))
648 const FunctionLoweringInfo::LiveOutInfo &LOI =
649 FuncInfo.LiveOutRegInfo[Regs[Part+i]];
651 unsigned RegSize = RegisterVT.getSizeInBits();
652 unsigned NumSignBits = LOI.NumSignBits;
653 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
655 // FIXME: We capture more information than the dag can represent. For
656 // now, just use the tightest assertzext/assertsext possible.
658 EVT FromVT(MVT::Other);
659 if (NumSignBits == RegSize)
660 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
661 else if (NumZeroBits >= RegSize-1)
662 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
663 else if (NumSignBits > RegSize-8)
664 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
665 else if (NumZeroBits >= RegSize-8)
666 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
667 else if (NumSignBits > RegSize-16)
668 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
669 else if (NumZeroBits >= RegSize-16)
670 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
671 else if (NumSignBits > RegSize-32)
672 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
673 else if (NumZeroBits >= RegSize-32)
674 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
678 // Add an assertion node.
679 assert(FromVT != MVT::Other);
680 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
681 RegisterVT, P, DAG.getValueType(FromVT));
684 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
685 NumRegs, RegisterVT, ValueVT);
690 return DAG.getNode(ISD::MERGE_VALUES, dl,
691 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
692 &Values[0], ValueVTs.size());
695 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
696 /// specified value into the registers specified by this object. This uses
697 /// Chain/Flag as the input and updates them for the output Chain/Flag.
698 /// If the Flag pointer is NULL, no flag is used.
699 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
700 SDValue &Chain, SDValue *Flag) const {
701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
703 // Get the list of the values's legal parts.
704 unsigned NumRegs = Regs.size();
705 SmallVector<SDValue, 8> Parts(NumRegs);
706 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
707 EVT ValueVT = ValueVTs[Value];
708 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
709 EVT RegisterVT = RegVTs[Value];
711 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
712 &Parts[Part], NumParts, RegisterVT);
716 // Copy the parts into the registers.
717 SmallVector<SDValue, 8> Chains(NumRegs);
718 for (unsigned i = 0; i != NumRegs; ++i) {
721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
723 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
724 *Flag = Part.getValue(1);
727 Chains[i] = Part.getValue(0);
730 if (NumRegs == 1 || Flag)
731 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
732 // flagged to it. That is the CopyToReg nodes and the user are considered
733 // a single scheduling unit. If we create a TokenFactor and return it as
734 // chain, then the TokenFactor is both a predecessor (operand) of the
735 // user as well as a successor (the TF operands are flagged to the user).
736 // c1, f1 = CopyToReg
737 // c2, f2 = CopyToReg
738 // c3 = TokenFactor c1, c2
741 Chain = Chains[NumRegs-1];
743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
746 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
747 /// operand list. This adds the code marker and includes the number of
748 /// values added into it.
749 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
750 unsigned MatchingIdx,
752 std::vector<SDValue> &Ops) const {
753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
755 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
757 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
758 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
761 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
762 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
763 EVT RegisterVT = RegVTs[Value];
764 for (unsigned i = 0; i != NumRegs; ++i) {
765 assert(Reg < Regs.size() && "Mismatch in # registers expected");
766 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
771 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
774 TD = DAG.getTarget().getTargetData();
777 /// clear - Clear out the current SelectionDAG and the associated
778 /// state and prepare this SelectionDAGBuilder object to be used
779 /// for a new block. This doesn't clear out information about
780 /// additional blocks that are needed to complete switch lowering
781 /// or PHI node updating; that information is cleared out as it is
783 void SelectionDAGBuilder::clear() {
785 UnusedArgNodeMap.clear();
786 PendingLoads.clear();
787 PendingExports.clear();
788 DanglingDebugInfoMap.clear();
789 CurDebugLoc = DebugLoc();
793 /// getRoot - Return the current virtual root of the Selection DAG,
794 /// flushing any PendingLoad items. This must be done before emitting
795 /// a store or any other node that may need to be ordered after any
796 /// prior load instructions.
798 SDValue SelectionDAGBuilder::getRoot() {
799 if (PendingLoads.empty())
800 return DAG.getRoot();
802 if (PendingLoads.size() == 1) {
803 SDValue Root = PendingLoads[0];
805 PendingLoads.clear();
809 // Otherwise, we have to make a token factor node.
810 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
811 &PendingLoads[0], PendingLoads.size());
812 PendingLoads.clear();
817 /// getControlRoot - Similar to getRoot, but instead of flushing all the
818 /// PendingLoad items, flush all the PendingExports items. It is necessary
819 /// to do this before emitting a terminator instruction.
821 SDValue SelectionDAGBuilder::getControlRoot() {
822 SDValue Root = DAG.getRoot();
824 if (PendingExports.empty())
827 // Turn all of the CopyToReg chains into one factored node.
828 if (Root.getOpcode() != ISD::EntryToken) {
829 unsigned i = 0, e = PendingExports.size();
830 for (; i != e; ++i) {
831 assert(PendingExports[i].getNode()->getNumOperands() > 1);
832 if (PendingExports[i].getNode()->getOperand(0) == Root)
833 break; // Don't add the root if we already indirectly depend on it.
837 PendingExports.push_back(Root);
840 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
842 PendingExports.size());
843 PendingExports.clear();
848 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
849 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
850 DAG.AssignOrdering(Node, SDNodeOrder);
852 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
853 AssignOrderingToNode(Node->getOperand(I).getNode());
856 void SelectionDAGBuilder::visit(const Instruction &I) {
857 // Set up outgoing PHI node register values before emitting the terminator.
858 if (isa<TerminatorInst>(&I))
859 HandlePHINodesInSuccessorBlocks(I.getParent());
861 CurDebugLoc = I.getDebugLoc();
863 visit(I.getOpcode(), I);
865 if (!isa<TerminatorInst>(&I) && !HasTailCall)
866 CopyToExportRegsIfNeeded(&I);
868 CurDebugLoc = DebugLoc();
871 void SelectionDAGBuilder::visitPHI(const PHINode &) {
872 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
875 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
876 // Note: this doesn't use InstVisitor, because it has to work with
877 // ConstantExpr's in addition to instructions.
879 default: llvm_unreachable("Unknown instruction type encountered!");
880 // Build the switch statement using the Instruction.def file.
881 #define HANDLE_INST(NUM, OPCODE, CLASS) \
882 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
883 #include "llvm/Instruction.def"
886 // Assign the ordering to the freshly created DAG nodes.
887 if (NodeMap.count(&I)) {
889 AssignOrderingToNode(getValue(&I).getNode());
893 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
894 // generate the debug data structures now that we've seen its definition.
895 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
897 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
899 const DbgValueInst *DI = DDI.getDI();
900 DebugLoc dl = DDI.getdl();
901 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
902 MDNode *Variable = DI->getVariable();
903 uint64_t Offset = DI->getOffset();
906 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
907 SDV = DAG.getDbgValue(Variable, Val.getNode(),
908 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
909 DAG.AddDbgValue(SDV, Val.getNode(), false);
912 DEBUG(dbgs() << "Dropping debug info for " << DI);
913 DanglingDebugInfoMap[V] = DanglingDebugInfo();
917 // getValue - Return an SDValue for the given Value.
918 SDValue SelectionDAGBuilder::getValue(const Value *V) {
919 // If we already have an SDValue for this value, use it. It's important
920 // to do this first, so that we don't create a CopyFromReg if we already
921 // have a regular SDValue.
922 SDValue &N = NodeMap[V];
923 if (N.getNode()) return N;
925 // If there's a virtual register allocated and initialized for this
927 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
928 if (It != FuncInfo.ValueMap.end()) {
929 unsigned InReg = It->second;
930 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
931 SDValue Chain = DAG.getEntryNode();
932 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
933 resolveDanglingDebugInfo(V, N);
937 // Otherwise create a new SDValue and remember it.
938 SDValue Val = getValueImpl(V);
940 resolveDanglingDebugInfo(V, Val);
944 /// getNonRegisterValue - Return an SDValue for the given Value, but
945 /// don't look in FuncInfo.ValueMap for a virtual register.
946 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
947 // If we already have an SDValue for this value, use it.
948 SDValue &N = NodeMap[V];
949 if (N.getNode()) return N;
951 // Otherwise create a new SDValue and remember it.
952 SDValue Val = getValueImpl(V);
954 resolveDanglingDebugInfo(V, Val);
958 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
959 /// Create an SDValue for the given value.
960 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
961 if (const Constant *C = dyn_cast<Constant>(V)) {
962 EVT VT = TLI.getValueType(V->getType(), true);
964 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
965 return DAG.getConstant(*CI, VT);
967 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
968 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
970 if (isa<ConstantPointerNull>(C))
971 return DAG.getConstant(0, TLI.getPointerTy());
973 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
974 return DAG.getConstantFP(*CFP, VT);
976 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
977 return DAG.getUNDEF(VT);
979 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
980 visit(CE->getOpcode(), *CE);
981 SDValue N1 = NodeMap[V];
982 assert(N1.getNode() && "visit didn't populate the NodeMap!");
986 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
987 SmallVector<SDValue, 4> Constants;
988 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
990 SDNode *Val = getValue(*OI).getNode();
991 // If the operand is an empty aggregate, there are no values.
993 // Add each leaf value from the operand to the Constants list
994 // to form a flattened list of all the values.
995 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
996 Constants.push_back(SDValue(Val, i));
999 return DAG.getMergeValues(&Constants[0], Constants.size(),
1003 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1004 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1005 "Unknown struct or array constant!");
1007 SmallVector<EVT, 4> ValueVTs;
1008 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1009 unsigned NumElts = ValueVTs.size();
1011 return SDValue(); // empty struct
1012 SmallVector<SDValue, 4> Constants(NumElts);
1013 for (unsigned i = 0; i != NumElts; ++i) {
1014 EVT EltVT = ValueVTs[i];
1015 if (isa<UndefValue>(C))
1016 Constants[i] = DAG.getUNDEF(EltVT);
1017 else if (EltVT.isFloatingPoint())
1018 Constants[i] = DAG.getConstantFP(0, EltVT);
1020 Constants[i] = DAG.getConstant(0, EltVT);
1023 return DAG.getMergeValues(&Constants[0], NumElts,
1027 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1028 return DAG.getBlockAddress(BA, VT);
1030 const VectorType *VecTy = cast<VectorType>(V->getType());
1031 unsigned NumElements = VecTy->getNumElements();
1033 // Now that we know the number and type of the elements, get that number of
1034 // elements into the Ops array based on what kind of constant it is.
1035 SmallVector<SDValue, 16> Ops;
1036 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1037 for (unsigned i = 0; i != NumElements; ++i)
1038 Ops.push_back(getValue(CP->getOperand(i)));
1040 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1041 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1044 if (EltVT.isFloatingPoint())
1045 Op = DAG.getConstantFP(0, EltVT);
1047 Op = DAG.getConstant(0, EltVT);
1048 Ops.assign(NumElements, Op);
1051 // Create a BUILD_VECTOR node.
1052 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1053 VT, &Ops[0], Ops.size());
1056 // If this is a static alloca, generate it as the frameindex instead of
1058 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1059 DenseMap<const AllocaInst*, int>::iterator SI =
1060 FuncInfo.StaticAllocaMap.find(AI);
1061 if (SI != FuncInfo.StaticAllocaMap.end())
1062 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1065 // If this is an instruction which fast-isel has deferred, select it now.
1066 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1067 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1068 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1069 SDValue Chain = DAG.getEntryNode();
1070 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1073 llvm_unreachable("Can't get register for value!");
1077 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1078 SDValue Chain = getControlRoot();
1079 SmallVector<ISD::OutputArg, 8> Outs;
1080 SmallVector<SDValue, 8> OutVals;
1082 if (!FuncInfo.CanLowerReturn) {
1083 unsigned DemoteReg = FuncInfo.DemoteRegister;
1084 const Function *F = I.getParent()->getParent();
1086 // Emit a store of the return value through the virtual register.
1087 // Leave Outs empty so that LowerReturn won't try to load return
1088 // registers the usual way.
1089 SmallVector<EVT, 1> PtrValueVTs;
1090 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1093 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1094 SDValue RetOp = getValue(I.getOperand(0));
1096 SmallVector<EVT, 4> ValueVTs;
1097 SmallVector<uint64_t, 4> Offsets;
1098 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1099 unsigned NumValues = ValueVTs.size();
1101 SmallVector<SDValue, 4> Chains(NumValues);
1102 for (unsigned i = 0; i != NumValues; ++i) {
1103 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1104 RetPtr.getValueType(), RetPtr,
1105 DAG.getIntPtrConstant(Offsets[i]));
1107 DAG.getStore(Chain, getCurDebugLoc(),
1108 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1109 // FIXME: better loc info would be nice.
1110 Add, MachinePointerInfo(), false, false, 0);
1113 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1114 MVT::Other, &Chains[0], NumValues);
1115 } else if (I.getNumOperands() != 0) {
1116 SmallVector<EVT, 4> ValueVTs;
1117 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1118 unsigned NumValues = ValueVTs.size();
1120 SDValue RetOp = getValue(I.getOperand(0));
1121 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1122 EVT VT = ValueVTs[j];
1124 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1126 const Function *F = I.getParent()->getParent();
1127 if (F->paramHasAttr(0, Attribute::SExt))
1128 ExtendKind = ISD::SIGN_EXTEND;
1129 else if (F->paramHasAttr(0, Attribute::ZExt))
1130 ExtendKind = ISD::ZERO_EXTEND;
1132 // FIXME: C calling convention requires the return type to be promoted
1133 // to at least 32-bit. But this is not necessary for non-C calling
1134 // conventions. The frontend should mark functions whose return values
1135 // require promoting with signext or zeroext attributes.
1136 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1137 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1138 if (VT.bitsLT(MinVT))
1142 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1143 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1144 SmallVector<SDValue, 4> Parts(NumParts);
1145 getCopyToParts(DAG, getCurDebugLoc(),
1146 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1147 &Parts[0], NumParts, PartVT, ExtendKind);
1149 // 'inreg' on function refers to return value
1150 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1151 if (F->paramHasAttr(0, Attribute::InReg))
1154 // Propagate extension type if any
1155 if (F->paramHasAttr(0, Attribute::SExt))
1157 else if (F->paramHasAttr(0, Attribute::ZExt))
1160 for (unsigned i = 0; i < NumParts; ++i) {
1161 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1163 OutVals.push_back(Parts[i]);
1169 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1170 CallingConv::ID CallConv =
1171 DAG.getMachineFunction().getFunction()->getCallingConv();
1172 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1173 Outs, OutVals, getCurDebugLoc(), DAG);
1175 // Verify that the target's LowerReturn behaved as expected.
1176 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1177 "LowerReturn didn't return a valid chain!");
1179 // Update the DAG with the new chain value resulting from return lowering.
1183 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1184 /// created for it, emit nodes to copy the value into the virtual
1186 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1187 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1188 if (VMI != FuncInfo.ValueMap.end()) {
1189 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1190 CopyValueToVirtualRegister(V, VMI->second);
1194 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1195 /// the current basic block, add it to ValueMap now so that we'll get a
1197 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1198 // No need to export constants.
1199 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1201 // Already exported?
1202 if (FuncInfo.isExportedInst(V)) return;
1204 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1205 CopyValueToVirtualRegister(V, Reg);
1208 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1209 const BasicBlock *FromBB) {
1210 // The operands of the setcc have to be in this block. We don't know
1211 // how to export them from some other block.
1212 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1213 // Can export from current BB.
1214 if (VI->getParent() == FromBB)
1217 // Is already exported, noop.
1218 return FuncInfo.isExportedInst(V);
1221 // If this is an argument, we can export it if the BB is the entry block or
1222 // if it is already exported.
1223 if (isa<Argument>(V)) {
1224 if (FromBB == &FromBB->getParent()->getEntryBlock())
1227 // Otherwise, can only export this if it is already exported.
1228 return FuncInfo.isExportedInst(V);
1231 // Otherwise, constants can always be exported.
1235 static bool InBlock(const Value *V, const BasicBlock *BB) {
1236 if (const Instruction *I = dyn_cast<Instruction>(V))
1237 return I->getParent() == BB;
1241 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1242 /// This function emits a branch and is used at the leaves of an OR or an
1243 /// AND operator tree.
1246 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1247 MachineBasicBlock *TBB,
1248 MachineBasicBlock *FBB,
1249 MachineBasicBlock *CurBB,
1250 MachineBasicBlock *SwitchBB) {
1251 const BasicBlock *BB = CurBB->getBasicBlock();
1253 // If the leaf of the tree is a comparison, merge the condition into
1255 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1256 // The operands of the cmp have to be in this block. We don't know
1257 // how to export them from some other block. If this is the first block
1258 // of the sequence, no exporting is needed.
1259 if (CurBB == SwitchBB ||
1260 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1261 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1262 ISD::CondCode Condition;
1263 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1264 Condition = getICmpCondCode(IC->getPredicate());
1265 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1266 Condition = getFCmpCondCode(FC->getPredicate());
1268 Condition = ISD::SETEQ; // silence warning.
1269 llvm_unreachable("Unknown compare instruction");
1272 CaseBlock CB(Condition, BOp->getOperand(0),
1273 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1274 SwitchCases.push_back(CB);
1279 // Create a CaseBlock record representing this branch.
1280 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1281 NULL, TBB, FBB, CurBB);
1282 SwitchCases.push_back(CB);
1285 /// FindMergedConditions - If Cond is an expression like
1286 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1287 MachineBasicBlock *TBB,
1288 MachineBasicBlock *FBB,
1289 MachineBasicBlock *CurBB,
1290 MachineBasicBlock *SwitchBB,
1292 // If this node is not part of the or/and tree, emit it as a branch.
1293 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1294 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1295 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1296 BOp->getParent() != CurBB->getBasicBlock() ||
1297 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1298 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1299 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1303 // Create TmpBB after CurBB.
1304 MachineFunction::iterator BBI = CurBB;
1305 MachineFunction &MF = DAG.getMachineFunction();
1306 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1307 CurBB->getParent()->insert(++BBI, TmpBB);
1309 if (Opc == Instruction::Or) {
1310 // Codegen X | Y as:
1318 // Emit the LHS condition.
1319 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1321 // Emit the RHS condition into TmpBB.
1322 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1324 assert(Opc == Instruction::And && "Unknown merge op!");
1325 // Codegen X & Y as:
1332 // This requires creation of TmpBB after CurBB.
1334 // Emit the LHS condition.
1335 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1337 // Emit the RHS condition into TmpBB.
1338 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1342 /// If the set of cases should be emitted as a series of branches, return true.
1343 /// If we should emit this as a bunch of and/or'd together conditions, return
1346 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1347 if (Cases.size() != 2) return true;
1349 // If this is two comparisons of the same values or'd or and'd together, they
1350 // will get folded into a single comparison, so don't emit two blocks.
1351 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1352 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1353 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1354 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1358 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1359 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1360 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1361 Cases[0].CC == Cases[1].CC &&
1362 isa<Constant>(Cases[0].CmpRHS) &&
1363 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1364 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1366 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1373 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1374 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1376 // Update machine-CFG edges.
1377 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1379 // Figure out which block is immediately after the current one.
1380 MachineBasicBlock *NextBlock = 0;
1381 MachineFunction::iterator BBI = BrMBB;
1382 if (++BBI != FuncInfo.MF->end())
1385 if (I.isUnconditional()) {
1386 // Update machine-CFG edges.
1387 BrMBB->addSuccessor(Succ0MBB);
1389 // If this is not a fall-through branch, emit the branch.
1390 if (Succ0MBB != NextBlock)
1391 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1392 MVT::Other, getControlRoot(),
1393 DAG.getBasicBlock(Succ0MBB)));
1398 // If this condition is one of the special cases we handle, do special stuff
1400 const Value *CondVal = I.getCondition();
1401 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1403 // If this is a series of conditions that are or'd or and'd together, emit
1404 // this as a sequence of branches instead of setcc's with and/or operations.
1405 // As long as jumps are not expensive, this should improve performance.
1406 // For example, instead of something like:
1419 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1420 if (!TLI.isJumpExpensive() &&
1422 (BOp->getOpcode() == Instruction::And ||
1423 BOp->getOpcode() == Instruction::Or)) {
1424 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1426 // If the compares in later blocks need to use values not currently
1427 // exported from this block, export them now. This block should always
1428 // be the first entry.
1429 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1431 // Allow some cases to be rejected.
1432 if (ShouldEmitAsBranches(SwitchCases)) {
1433 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1434 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1435 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1438 // Emit the branch for this block.
1439 visitSwitchCase(SwitchCases[0], BrMBB);
1440 SwitchCases.erase(SwitchCases.begin());
1444 // Okay, we decided not to do this, remove any inserted MBB's and clear
1446 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1447 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1449 SwitchCases.clear();
1453 // Create a CaseBlock record representing this branch.
1454 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1455 NULL, Succ0MBB, Succ1MBB, BrMBB);
1457 // Use visitSwitchCase to actually insert the fast branch sequence for this
1459 visitSwitchCase(CB, BrMBB);
1462 /// visitSwitchCase - Emits the necessary code to represent a single node in
1463 /// the binary search tree resulting from lowering a switch instruction.
1464 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1465 MachineBasicBlock *SwitchBB) {
1467 SDValue CondLHS = getValue(CB.CmpLHS);
1468 DebugLoc dl = getCurDebugLoc();
1470 // Build the setcc now.
1471 if (CB.CmpMHS == NULL) {
1472 // Fold "(X == true)" to X and "(X == false)" to !X to
1473 // handle common cases produced by branch lowering.
1474 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1475 CB.CC == ISD::SETEQ)
1477 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1478 CB.CC == ISD::SETEQ) {
1479 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1480 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1482 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1484 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1486 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1487 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1489 SDValue CmpOp = getValue(CB.CmpMHS);
1490 EVT VT = CmpOp.getValueType();
1492 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1493 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1496 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1497 VT, CmpOp, DAG.getConstant(Low, VT));
1498 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1499 DAG.getConstant(High-Low, VT), ISD::SETULE);
1503 // Update successor info
1504 SwitchBB->addSuccessor(CB.TrueBB);
1505 SwitchBB->addSuccessor(CB.FalseBB);
1507 // Set NextBlock to be the MBB immediately after the current one, if any.
1508 // This is used to avoid emitting unnecessary branches to the next block.
1509 MachineBasicBlock *NextBlock = 0;
1510 MachineFunction::iterator BBI = SwitchBB;
1511 if (++BBI != FuncInfo.MF->end())
1514 // If the lhs block is the next block, invert the condition so that we can
1515 // fall through to the lhs instead of the rhs block.
1516 if (CB.TrueBB == NextBlock) {
1517 std::swap(CB.TrueBB, CB.FalseBB);
1518 SDValue True = DAG.getConstant(1, Cond.getValueType());
1519 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1522 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1523 MVT::Other, getControlRoot(), Cond,
1524 DAG.getBasicBlock(CB.TrueBB));
1526 // Insert the false branch. Do this even if it's a fall through branch,
1527 // this makes it easier to do DAG optimizations which require inverting
1528 // the branch condition.
1529 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1530 DAG.getBasicBlock(CB.FalseBB));
1532 DAG.setRoot(BrCond);
1535 /// visitJumpTable - Emit JumpTable node in the current MBB
1536 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1537 // Emit the code for the jump table
1538 assert(JT.Reg != -1U && "Should lower JT Header first!");
1539 EVT PTy = TLI.getPointerTy();
1540 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1542 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1543 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1544 MVT::Other, Index.getValue(1),
1546 DAG.setRoot(BrJumpTable);
1549 /// visitJumpTableHeader - This function emits necessary code to produce index
1550 /// in the JumpTable from switch case.
1551 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1552 JumpTableHeader &JTH,
1553 MachineBasicBlock *SwitchBB) {
1554 // Subtract the lowest switch case value from the value being switched on and
1555 // conditional branch to default mbb if the result is greater than the
1556 // difference between smallest and largest cases.
1557 SDValue SwitchOp = getValue(JTH.SValue);
1558 EVT VT = SwitchOp.getValueType();
1559 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1560 DAG.getConstant(JTH.First, VT));
1562 // The SDNode we just created, which holds the value being switched on minus
1563 // the smallest case value, needs to be copied to a virtual register so it
1564 // can be used as an index into the jump table in a subsequent basic block.
1565 // This value may be smaller or larger than the target's pointer type, and
1566 // therefore require extension or truncating.
1567 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1569 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1570 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1571 JumpTableReg, SwitchOp);
1572 JT.Reg = JumpTableReg;
1574 // Emit the range check for the jump table, and branch to the default block
1575 // for the switch statement if the value being switched on exceeds the largest
1576 // case in the switch.
1577 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1578 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1579 DAG.getConstant(JTH.Last-JTH.First,VT),
1582 // Set NextBlock to be the MBB immediately after the current one, if any.
1583 // This is used to avoid emitting unnecessary branches to the next block.
1584 MachineBasicBlock *NextBlock = 0;
1585 MachineFunction::iterator BBI = SwitchBB;
1587 if (++BBI != FuncInfo.MF->end())
1590 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1591 MVT::Other, CopyTo, CMP,
1592 DAG.getBasicBlock(JT.Default));
1594 if (JT.MBB != NextBlock)
1595 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1596 DAG.getBasicBlock(JT.MBB));
1598 DAG.setRoot(BrCond);
1601 /// visitBitTestHeader - This function emits necessary code to produce value
1602 /// suitable for "bit tests"
1603 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1604 MachineBasicBlock *SwitchBB) {
1605 // Subtract the minimum value
1606 SDValue SwitchOp = getValue(B.SValue);
1607 EVT VT = SwitchOp.getValueType();
1608 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1609 DAG.getConstant(B.First, VT));
1612 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1613 TLI.getSetCCResultType(Sub.getValueType()),
1614 Sub, DAG.getConstant(B.Range, VT),
1617 // Determine the type of the test operands.
1618 bool UsePtrType = false;
1619 if (!TLI.isTypeLegal(VT))
1622 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1623 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1624 // Switch table case range are encoded into series of masks.
1625 // Just use pointer type, it's guaranteed to fit.
1631 VT = TLI.getPointerTy();
1632 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1636 B.Reg = FuncInfo.CreateReg(VT);
1637 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1640 // Set NextBlock to be the MBB immediately after the current one, if any.
1641 // This is used to avoid emitting unnecessary branches to the next block.
1642 MachineBasicBlock *NextBlock = 0;
1643 MachineFunction::iterator BBI = SwitchBB;
1644 if (++BBI != FuncInfo.MF->end())
1647 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1649 SwitchBB->addSuccessor(B.Default);
1650 SwitchBB->addSuccessor(MBB);
1652 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1653 MVT::Other, CopyTo, RangeCmp,
1654 DAG.getBasicBlock(B.Default));
1656 if (MBB != NextBlock)
1657 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1658 DAG.getBasicBlock(MBB));
1660 DAG.setRoot(BrRange);
1663 /// visitBitTestCase - this function produces one "bit test"
1664 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1665 MachineBasicBlock* NextMBB,
1668 MachineBasicBlock *SwitchBB) {
1670 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1673 if (CountPopulation_64(B.Mask) == 1) {
1674 // Testing for a single bit; just compare the shift count with what it
1675 // would need to be to shift a 1 bit in that position.
1676 Cmp = DAG.getSetCC(getCurDebugLoc(),
1677 TLI.getSetCCResultType(VT),
1679 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1682 // Make desired shift
1683 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1684 DAG.getConstant(1, VT), ShiftOp);
1686 // Emit bit tests and jumps
1687 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1688 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1689 Cmp = DAG.getSetCC(getCurDebugLoc(),
1690 TLI.getSetCCResultType(VT),
1691 AndOp, DAG.getConstant(0, VT),
1695 SwitchBB->addSuccessor(B.TargetBB);
1696 SwitchBB->addSuccessor(NextMBB);
1698 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1699 MVT::Other, getControlRoot(),
1700 Cmp, DAG.getBasicBlock(B.TargetBB));
1702 // Set NextBlock to be the MBB immediately after the current one, if any.
1703 // This is used to avoid emitting unnecessary branches to the next block.
1704 MachineBasicBlock *NextBlock = 0;
1705 MachineFunction::iterator BBI = SwitchBB;
1706 if (++BBI != FuncInfo.MF->end())
1709 if (NextMBB != NextBlock)
1710 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1711 DAG.getBasicBlock(NextMBB));
1716 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1717 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1719 // Retrieve successors.
1720 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1721 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1723 const Value *Callee(I.getCalledValue());
1724 if (isa<InlineAsm>(Callee))
1727 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1729 // If the value of the invoke is used outside of its defining block, make it
1730 // available as a virtual register.
1731 CopyToExportRegsIfNeeded(&I);
1733 // Update successor info
1734 InvokeMBB->addSuccessor(Return);
1735 InvokeMBB->addSuccessor(LandingPad);
1737 // Drop into normal successor.
1738 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1739 MVT::Other, getControlRoot(),
1740 DAG.getBasicBlock(Return)));
1743 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1746 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1747 /// small case ranges).
1748 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1749 CaseRecVector& WorkList,
1751 MachineBasicBlock *Default,
1752 MachineBasicBlock *SwitchBB) {
1753 Case& BackCase = *(CR.Range.second-1);
1755 // Size is the number of Cases represented by this range.
1756 size_t Size = CR.Range.second - CR.Range.first;
1760 // Get the MachineFunction which holds the current MBB. This is used when
1761 // inserting any additional MBBs necessary to represent the switch.
1762 MachineFunction *CurMF = FuncInfo.MF;
1764 // Figure out which block is immediately after the current one.
1765 MachineBasicBlock *NextBlock = 0;
1766 MachineFunction::iterator BBI = CR.CaseBB;
1768 if (++BBI != FuncInfo.MF->end())
1771 // If any two of the cases has the same destination, and if one value
1772 // is the same as the other, but has one bit unset that the other has set,
1773 // use bit manipulation to do two compares at once. For example:
1774 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1775 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1776 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1777 if (Size == 2 && CR.CaseBB == SwitchBB) {
1778 Case &Small = *CR.Range.first;
1779 Case &Big = *(CR.Range.second-1);
1781 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1782 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1783 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1785 // Check that there is only one bit different.
1786 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1787 (SmallValue | BigValue) == BigValue) {
1788 // Isolate the common bit.
1789 APInt CommonBit = BigValue & ~SmallValue;
1790 assert((SmallValue | CommonBit) == BigValue &&
1791 CommonBit.countPopulation() == 1 && "Not a common bit?");
1793 SDValue CondLHS = getValue(SV);
1794 EVT VT = CondLHS.getValueType();
1795 DebugLoc DL = getCurDebugLoc();
1797 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1798 DAG.getConstant(CommonBit, VT));
1799 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1800 Or, DAG.getConstant(BigValue, VT),
1803 // Update successor info.
1804 SwitchBB->addSuccessor(Small.BB);
1805 SwitchBB->addSuccessor(Default);
1807 // Insert the true branch.
1808 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1809 getControlRoot(), Cond,
1810 DAG.getBasicBlock(Small.BB));
1812 // Insert the false branch.
1813 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1814 DAG.getBasicBlock(Default));
1816 DAG.setRoot(BrCond);
1822 // Rearrange the case blocks so that the last one falls through if possible.
1823 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1824 // The last case block won't fall through into 'NextBlock' if we emit the
1825 // branches in this order. See if rearranging a case value would help.
1826 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1827 if (I->BB == NextBlock) {
1828 std::swap(*I, BackCase);
1834 // Create a CaseBlock record representing a conditional branch to
1835 // the Case's target mbb if the value being switched on SV is equal
1837 MachineBasicBlock *CurBlock = CR.CaseBB;
1838 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1839 MachineBasicBlock *FallThrough;
1841 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1842 CurMF->insert(BBI, FallThrough);
1844 // Put SV in a virtual register to make it available from the new blocks.
1845 ExportFromCurrentBlock(SV);
1847 // If the last case doesn't match, go to the default block.
1848 FallThrough = Default;
1851 const Value *RHS, *LHS, *MHS;
1853 if (I->High == I->Low) {
1854 // This is just small small case range :) containing exactly 1 case
1856 LHS = SV; RHS = I->High; MHS = NULL;
1859 LHS = I->Low; MHS = SV; RHS = I->High;
1861 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1863 // If emitting the first comparison, just call visitSwitchCase to emit the
1864 // code into the current block. Otherwise, push the CaseBlock onto the
1865 // vector to be later processed by SDISel, and insert the node's MBB
1866 // before the next MBB.
1867 if (CurBlock == SwitchBB)
1868 visitSwitchCase(CB, SwitchBB);
1870 SwitchCases.push_back(CB);
1872 CurBlock = FallThrough;
1878 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1879 return !DisableJumpTables &&
1880 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1881 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1884 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1885 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1886 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1887 return (LastExt - FirstExt + 1ULL);
1890 /// handleJTSwitchCase - Emit jumptable for current switch case range
1891 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1892 CaseRecVector& WorkList,
1894 MachineBasicBlock* Default,
1895 MachineBasicBlock *SwitchBB) {
1896 Case& FrontCase = *CR.Range.first;
1897 Case& BackCase = *(CR.Range.second-1);
1899 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1900 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1902 APInt TSize(First.getBitWidth(), 0);
1903 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1907 if (!areJTsAllowed(TLI) || TSize.ult(4))
1910 APInt Range = ComputeRange(First, Last);
1911 double Density = TSize.roundToDouble() / Range.roundToDouble();
1915 DEBUG(dbgs() << "Lowering jump table\n"
1916 << "First entry: " << First << ". Last entry: " << Last << '\n'
1917 << "Range: " << Range
1918 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1920 // Get the MachineFunction which holds the current MBB. This is used when
1921 // inserting any additional MBBs necessary to represent the switch.
1922 MachineFunction *CurMF = FuncInfo.MF;
1924 // Figure out which block is immediately after the current one.
1925 MachineFunction::iterator BBI = CR.CaseBB;
1928 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1930 // Create a new basic block to hold the code for loading the address
1931 // of the jump table, and jumping to it. Update successor information;
1932 // we will either branch to the default case for the switch, or the jump
1934 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1935 CurMF->insert(BBI, JumpTableBB);
1936 CR.CaseBB->addSuccessor(Default);
1937 CR.CaseBB->addSuccessor(JumpTableBB);
1939 // Build a vector of destination BBs, corresponding to each target
1940 // of the jump table. If the value of the jump table slot corresponds to
1941 // a case statement, push the case's BB onto the vector, otherwise, push
1943 std::vector<MachineBasicBlock*> DestBBs;
1945 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1946 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1947 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1949 if (Low.sle(TEI) && TEI.sle(High)) {
1950 DestBBs.push_back(I->BB);
1954 DestBBs.push_back(Default);
1958 // Update successor info. Add one edge to each unique successor.
1959 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1960 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1961 E = DestBBs.end(); I != E; ++I) {
1962 if (!SuccsHandled[(*I)->getNumber()]) {
1963 SuccsHandled[(*I)->getNumber()] = true;
1964 JumpTableBB->addSuccessor(*I);
1968 // Create a jump table index for this jump table.
1969 unsigned JTEncoding = TLI.getJumpTableEncoding();
1970 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1971 ->createJumpTableIndex(DestBBs);
1973 // Set the jump table information so that we can codegen it as a second
1974 // MachineBasicBlock
1975 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1976 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1977 if (CR.CaseBB == SwitchBB)
1978 visitJumpTableHeader(JT, JTH, SwitchBB);
1980 JTCases.push_back(JumpTableBlock(JTH, JT));
1985 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1987 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1988 CaseRecVector& WorkList,
1990 MachineBasicBlock *Default,
1991 MachineBasicBlock *SwitchBB) {
1992 // Get the MachineFunction which holds the current MBB. This is used when
1993 // inserting any additional MBBs necessary to represent the switch.
1994 MachineFunction *CurMF = FuncInfo.MF;
1996 // Figure out which block is immediately after the current one.
1997 MachineFunction::iterator BBI = CR.CaseBB;
2000 Case& FrontCase = *CR.Range.first;
2001 Case& BackCase = *(CR.Range.second-1);
2002 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2004 // Size is the number of Cases represented by this range.
2005 unsigned Size = CR.Range.second - CR.Range.first;
2007 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2008 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2010 CaseItr Pivot = CR.Range.first + Size/2;
2012 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2013 // (heuristically) allow us to emit JumpTable's later.
2014 APInt TSize(First.getBitWidth(), 0);
2015 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2019 APInt LSize = FrontCase.size();
2020 APInt RSize = TSize-LSize;
2021 DEBUG(dbgs() << "Selecting best pivot: \n"
2022 << "First: " << First << ", Last: " << Last <<'\n'
2023 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2024 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2026 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2027 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2028 APInt Range = ComputeRange(LEnd, RBegin);
2029 assert((Range - 2ULL).isNonNegative() &&
2030 "Invalid case distance");
2031 double LDensity = (double)LSize.roundToDouble() /
2032 (LEnd - First + 1ULL).roundToDouble();
2033 double RDensity = (double)RSize.roundToDouble() /
2034 (Last - RBegin + 1ULL).roundToDouble();
2035 double Metric = Range.logBase2()*(LDensity+RDensity);
2036 // Should always split in some non-trivial place
2037 DEBUG(dbgs() <<"=>Step\n"
2038 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2039 << "LDensity: " << LDensity
2040 << ", RDensity: " << RDensity << '\n'
2041 << "Metric: " << Metric << '\n');
2042 if (FMetric < Metric) {
2045 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2051 if (areJTsAllowed(TLI)) {
2052 // If our case is dense we *really* should handle it earlier!
2053 assert((FMetric > 0) && "Should handle dense range earlier!");
2055 Pivot = CR.Range.first + Size/2;
2058 CaseRange LHSR(CR.Range.first, Pivot);
2059 CaseRange RHSR(Pivot, CR.Range.second);
2060 Constant *C = Pivot->Low;
2061 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2063 // We know that we branch to the LHS if the Value being switched on is
2064 // less than the Pivot value, C. We use this to optimize our binary
2065 // tree a bit, by recognizing that if SV is greater than or equal to the
2066 // LHS's Case Value, and that Case Value is exactly one less than the
2067 // Pivot's Value, then we can branch directly to the LHS's Target,
2068 // rather than creating a leaf node for it.
2069 if ((LHSR.second - LHSR.first) == 1 &&
2070 LHSR.first->High == CR.GE &&
2071 cast<ConstantInt>(C)->getValue() ==
2072 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2073 TrueBB = LHSR.first->BB;
2075 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2076 CurMF->insert(BBI, TrueBB);
2077 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2079 // Put SV in a virtual register to make it available from the new blocks.
2080 ExportFromCurrentBlock(SV);
2083 // Similar to the optimization above, if the Value being switched on is
2084 // known to be less than the Constant CR.LT, and the current Case Value
2085 // is CR.LT - 1, then we can branch directly to the target block for
2086 // the current Case Value, rather than emitting a RHS leaf node for it.
2087 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2088 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2089 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2090 FalseBB = RHSR.first->BB;
2092 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2093 CurMF->insert(BBI, FalseBB);
2094 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2096 // Put SV in a virtual register to make it available from the new blocks.
2097 ExportFromCurrentBlock(SV);
2100 // Create a CaseBlock record representing a conditional branch to
2101 // the LHS node if the value being switched on SV is less than C.
2102 // Otherwise, branch to LHS.
2103 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2105 if (CR.CaseBB == SwitchBB)
2106 visitSwitchCase(CB, SwitchBB);
2108 SwitchCases.push_back(CB);
2113 /// handleBitTestsSwitchCase - if current case range has few destination and
2114 /// range span less, than machine word bitwidth, encode case range into series
2115 /// of masks and emit bit tests with these masks.
2116 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2117 CaseRecVector& WorkList,
2119 MachineBasicBlock* Default,
2120 MachineBasicBlock *SwitchBB){
2121 EVT PTy = TLI.getPointerTy();
2122 unsigned IntPtrBits = PTy.getSizeInBits();
2124 Case& FrontCase = *CR.Range.first;
2125 Case& BackCase = *(CR.Range.second-1);
2127 // Get the MachineFunction which holds the current MBB. This is used when
2128 // inserting any additional MBBs necessary to represent the switch.
2129 MachineFunction *CurMF = FuncInfo.MF;
2131 // If target does not have legal shift left, do not emit bit tests at all.
2132 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2136 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2138 // Single case counts one, case range - two.
2139 numCmps += (I->Low == I->High ? 1 : 2);
2142 // Count unique destinations
2143 SmallSet<MachineBasicBlock*, 4> Dests;
2144 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2145 Dests.insert(I->BB);
2146 if (Dests.size() > 3)
2147 // Don't bother the code below, if there are too much unique destinations
2150 DEBUG(dbgs() << "Total number of unique destinations: "
2151 << Dests.size() << '\n'
2152 << "Total number of comparisons: " << numCmps << '\n');
2154 // Compute span of values.
2155 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2156 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2157 APInt cmpRange = maxValue - minValue;
2159 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2160 << "Low bound: " << minValue << '\n'
2161 << "High bound: " << maxValue << '\n');
2163 if (cmpRange.uge(IntPtrBits) ||
2164 (!(Dests.size() == 1 && numCmps >= 3) &&
2165 !(Dests.size() == 2 && numCmps >= 5) &&
2166 !(Dests.size() >= 3 && numCmps >= 6)))
2169 DEBUG(dbgs() << "Emitting bit tests\n");
2170 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2172 // Optimize the case where all the case values fit in a
2173 // word without having to subtract minValue. In this case,
2174 // we can optimize away the subtraction.
2175 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2176 cmpRange = maxValue;
2178 lowBound = minValue;
2181 CaseBitsVector CasesBits;
2182 unsigned i, count = 0;
2184 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2185 MachineBasicBlock* Dest = I->BB;
2186 for (i = 0; i < count; ++i)
2187 if (Dest == CasesBits[i].BB)
2191 assert((count < 3) && "Too much destinations to test!");
2192 CasesBits.push_back(CaseBits(0, Dest, 0));
2196 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2197 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2199 uint64_t lo = (lowValue - lowBound).getZExtValue();
2200 uint64_t hi = (highValue - lowBound).getZExtValue();
2202 for (uint64_t j = lo; j <= hi; j++) {
2203 CasesBits[i].Mask |= 1ULL << j;
2204 CasesBits[i].Bits++;
2208 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2212 // Figure out which block is immediately after the current one.
2213 MachineFunction::iterator BBI = CR.CaseBB;
2216 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2218 DEBUG(dbgs() << "Cases:\n");
2219 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2220 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2221 << ", Bits: " << CasesBits[i].Bits
2222 << ", BB: " << CasesBits[i].BB << '\n');
2224 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2225 CurMF->insert(BBI, CaseBB);
2226 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2230 // Put SV in a virtual register to make it available from the new blocks.
2231 ExportFromCurrentBlock(SV);
2234 BitTestBlock BTB(lowBound, cmpRange, SV,
2235 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2236 CR.CaseBB, Default, BTC);
2238 if (CR.CaseBB == SwitchBB)
2239 visitBitTestHeader(BTB, SwitchBB);
2241 BitTestCases.push_back(BTB);
2246 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2247 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2248 const SwitchInst& SI) {
2251 // Start with "simple" cases
2252 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2253 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2254 Cases.push_back(Case(SI.getSuccessorValue(i),
2255 SI.getSuccessorValue(i),
2258 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2260 // Merge case into clusters
2261 if (Cases.size() >= 2)
2262 // Must recompute end() each iteration because it may be
2263 // invalidated by erase if we hold on to it
2264 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2265 J != Cases.end(); ) {
2266 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2267 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2268 MachineBasicBlock* nextBB = J->BB;
2269 MachineBasicBlock* currentBB = I->BB;
2271 // If the two neighboring cases go to the same destination, merge them
2272 // into a single case.
2273 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2281 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2282 if (I->Low != I->High)
2283 // A range counts double, since it requires two compares.
2290 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2291 MachineBasicBlock *Last) {
2293 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2294 if (JTCases[i].first.HeaderBB == First)
2295 JTCases[i].first.HeaderBB = Last;
2297 // Update BitTestCases.
2298 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2299 if (BitTestCases[i].Parent == First)
2300 BitTestCases[i].Parent = Last;
2303 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2304 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2306 // Figure out which block is immediately after the current one.
2307 MachineBasicBlock *NextBlock = 0;
2308 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2310 // If there is only the default destination, branch to it if it is not the
2311 // next basic block. Otherwise, just fall through.
2312 if (SI.getNumOperands() == 2) {
2313 // Update machine-CFG edges.
2315 // If this is not a fall-through branch, emit the branch.
2316 SwitchMBB->addSuccessor(Default);
2317 if (Default != NextBlock)
2318 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2319 MVT::Other, getControlRoot(),
2320 DAG.getBasicBlock(Default)));
2325 // If there are any non-default case statements, create a vector of Cases
2326 // representing each one, and sort the vector so that we can efficiently
2327 // create a binary search tree from them.
2329 size_t numCmps = Clusterify(Cases, SI);
2330 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2331 << ". Total compares: " << numCmps << '\n');
2334 // Get the Value to be switched on and default basic blocks, which will be
2335 // inserted into CaseBlock records, representing basic blocks in the binary
2337 const Value *SV = SI.getOperand(0);
2339 // Push the initial CaseRec onto the worklist
2340 CaseRecVector WorkList;
2341 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2342 CaseRange(Cases.begin(),Cases.end())));
2344 while (!WorkList.empty()) {
2345 // Grab a record representing a case range to process off the worklist
2346 CaseRec CR = WorkList.back();
2347 WorkList.pop_back();
2349 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2352 // If the range has few cases (two or less) emit a series of specific
2354 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2357 // If the switch has more than 5 blocks, and at least 40% dense, and the
2358 // target supports indirect branches, then emit a jump table rather than
2359 // lowering the switch to a binary tree of conditional branches.
2360 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2363 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2364 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2365 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2369 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2370 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2372 // Update machine-CFG edges with unique successors.
2373 SmallVector<BasicBlock*, 32> succs;
2374 succs.reserve(I.getNumSuccessors());
2375 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2376 succs.push_back(I.getSuccessor(i));
2377 array_pod_sort(succs.begin(), succs.end());
2378 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2379 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2380 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2382 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2383 MVT::Other, getControlRoot(),
2384 getValue(I.getAddress())));
2387 void SelectionDAGBuilder::visitFSub(const User &I) {
2388 // -0.0 - X --> fneg
2389 const Type *Ty = I.getType();
2390 if (isa<Constant>(I.getOperand(0)) &&
2391 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2392 SDValue Op2 = getValue(I.getOperand(1));
2393 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2394 Op2.getValueType(), Op2));
2398 visitBinary(I, ISD::FSUB);
2401 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2402 SDValue Op1 = getValue(I.getOperand(0));
2403 SDValue Op2 = getValue(I.getOperand(1));
2404 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2405 Op1.getValueType(), Op1, Op2));
2408 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2409 SDValue Op1 = getValue(I.getOperand(0));
2410 SDValue Op2 = getValue(I.getOperand(1));
2412 MVT ShiftTy = TLI.getShiftAmountTy();
2414 // Coerce the shift amount to the right type if we can.
2415 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2416 unsigned ShiftSize = ShiftTy.getSizeInBits();
2417 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2418 DebugLoc DL = getCurDebugLoc();
2420 // If the operand is smaller than the shift count type, promote it.
2421 if (ShiftSize > Op2Size)
2422 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2424 // If the operand is larger than the shift count type but the shift
2425 // count type has enough bits to represent any shift value, truncate
2426 // it now. This is a common case and it exposes the truncate to
2427 // optimization early.
2428 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2429 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2430 // Otherwise we'll need to temporarily settle for some other convenient
2431 // type. Type legalization will make adjustments once the shiftee is split.
2433 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2436 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2437 Op1.getValueType(), Op1, Op2));
2440 void SelectionDAGBuilder::visitICmp(const User &I) {
2441 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2442 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2443 predicate = IC->getPredicate();
2444 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2445 predicate = ICmpInst::Predicate(IC->getPredicate());
2446 SDValue Op1 = getValue(I.getOperand(0));
2447 SDValue Op2 = getValue(I.getOperand(1));
2448 ISD::CondCode Opcode = getICmpCondCode(predicate);
2450 EVT DestVT = TLI.getValueType(I.getType());
2451 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2454 void SelectionDAGBuilder::visitFCmp(const User &I) {
2455 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2456 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2457 predicate = FC->getPredicate();
2458 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2459 predicate = FCmpInst::Predicate(FC->getPredicate());
2460 SDValue Op1 = getValue(I.getOperand(0));
2461 SDValue Op2 = getValue(I.getOperand(1));
2462 ISD::CondCode Condition = getFCmpCondCode(predicate);
2463 EVT DestVT = TLI.getValueType(I.getType());
2464 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2467 void SelectionDAGBuilder::visitSelect(const User &I) {
2468 SmallVector<EVT, 4> ValueVTs;
2469 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2470 unsigned NumValues = ValueVTs.size();
2471 if (NumValues == 0) return;
2473 SmallVector<SDValue, 4> Values(NumValues);
2474 SDValue Cond = getValue(I.getOperand(0));
2475 SDValue TrueVal = getValue(I.getOperand(1));
2476 SDValue FalseVal = getValue(I.getOperand(2));
2478 for (unsigned i = 0; i != NumValues; ++i)
2479 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2480 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2482 SDValue(TrueVal.getNode(),
2483 TrueVal.getResNo() + i),
2484 SDValue(FalseVal.getNode(),
2485 FalseVal.getResNo() + i));
2487 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2488 DAG.getVTList(&ValueVTs[0], NumValues),
2489 &Values[0], NumValues));
2492 void SelectionDAGBuilder::visitTrunc(const User &I) {
2493 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2494 SDValue N = getValue(I.getOperand(0));
2495 EVT DestVT = TLI.getValueType(I.getType());
2496 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2499 void SelectionDAGBuilder::visitZExt(const User &I) {
2500 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2501 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2502 SDValue N = getValue(I.getOperand(0));
2503 EVT DestVT = TLI.getValueType(I.getType());
2504 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2507 void SelectionDAGBuilder::visitSExt(const User &I) {
2508 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2509 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2510 SDValue N = getValue(I.getOperand(0));
2511 EVT DestVT = TLI.getValueType(I.getType());
2512 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2515 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2516 // FPTrunc is never a no-op cast, no need to check
2517 SDValue N = getValue(I.getOperand(0));
2518 EVT DestVT = TLI.getValueType(I.getType());
2519 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2520 DestVT, N, DAG.getIntPtrConstant(0)));
2523 void SelectionDAGBuilder::visitFPExt(const User &I){
2524 // FPTrunc is never a no-op cast, no need to check
2525 SDValue N = getValue(I.getOperand(0));
2526 EVT DestVT = TLI.getValueType(I.getType());
2527 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2530 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2531 // FPToUI is never a no-op cast, no need to check
2532 SDValue N = getValue(I.getOperand(0));
2533 EVT DestVT = TLI.getValueType(I.getType());
2534 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2537 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2538 // FPToSI is never a no-op cast, no need to check
2539 SDValue N = getValue(I.getOperand(0));
2540 EVT DestVT = TLI.getValueType(I.getType());
2541 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2544 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2545 // UIToFP is never a no-op cast, no need to check
2546 SDValue N = getValue(I.getOperand(0));
2547 EVT DestVT = TLI.getValueType(I.getType());
2548 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2551 void SelectionDAGBuilder::visitSIToFP(const User &I){
2552 // SIToFP is never a no-op cast, no need to check
2553 SDValue N = getValue(I.getOperand(0));
2554 EVT DestVT = TLI.getValueType(I.getType());
2555 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2558 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2559 // What to do depends on the size of the integer and the size of the pointer.
2560 // We can either truncate, zero extend, or no-op, accordingly.
2561 SDValue N = getValue(I.getOperand(0));
2562 EVT DestVT = TLI.getValueType(I.getType());
2563 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2566 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2567 // What to do depends on the size of the integer and the size of the pointer.
2568 // We can either truncate, zero extend, or no-op, accordingly.
2569 SDValue N = getValue(I.getOperand(0));
2570 EVT DestVT = TLI.getValueType(I.getType());
2571 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2574 void SelectionDAGBuilder::visitBitCast(const User &I) {
2575 SDValue N = getValue(I.getOperand(0));
2576 EVT DestVT = TLI.getValueType(I.getType());
2578 // BitCast assures us that source and destination are the same size so this is
2579 // either a BITCAST or a no-op.
2580 if (DestVT != N.getValueType())
2581 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2582 DestVT, N)); // convert types.
2584 setValue(&I, N); // noop cast.
2587 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2588 SDValue InVec = getValue(I.getOperand(0));
2589 SDValue InVal = getValue(I.getOperand(1));
2590 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2592 getValue(I.getOperand(2)));
2593 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2594 TLI.getValueType(I.getType()),
2595 InVec, InVal, InIdx));
2598 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2599 SDValue InVec = getValue(I.getOperand(0));
2600 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2602 getValue(I.getOperand(1)));
2603 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2604 TLI.getValueType(I.getType()), InVec, InIdx));
2607 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2608 // from SIndx and increasing to the element length (undefs are allowed).
2609 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2610 unsigned MaskNumElts = Mask.size();
2611 for (unsigned i = 0; i != MaskNumElts; ++i)
2612 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2617 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2618 SmallVector<int, 8> Mask;
2619 SDValue Src1 = getValue(I.getOperand(0));
2620 SDValue Src2 = getValue(I.getOperand(1));
2622 // Convert the ConstantVector mask operand into an array of ints, with -1
2623 // representing undef values.
2624 SmallVector<Constant*, 8> MaskElts;
2625 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2626 unsigned MaskNumElts = MaskElts.size();
2627 for (unsigned i = 0; i != MaskNumElts; ++i) {
2628 if (isa<UndefValue>(MaskElts[i]))
2631 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2634 EVT VT = TLI.getValueType(I.getType());
2635 EVT SrcVT = Src1.getValueType();
2636 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2638 if (SrcNumElts == MaskNumElts) {
2639 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2644 // Normalize the shuffle vector since mask and vector length don't match.
2645 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2646 // Mask is longer than the source vectors and is a multiple of the source
2647 // vectors. We can use concatenate vector to make the mask and vectors
2649 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2650 // The shuffle is concatenating two vectors together.
2651 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2656 // Pad both vectors with undefs to make them the same length as the mask.
2657 unsigned NumConcat = MaskNumElts / SrcNumElts;
2658 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2659 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2660 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2662 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2663 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2667 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2668 getCurDebugLoc(), VT,
2669 &MOps1[0], NumConcat);
2670 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2671 getCurDebugLoc(), VT,
2672 &MOps2[0], NumConcat);
2674 // Readjust mask for new input vector length.
2675 SmallVector<int, 8> MappedOps;
2676 for (unsigned i = 0; i != MaskNumElts; ++i) {
2678 if (Idx < (int)SrcNumElts)
2679 MappedOps.push_back(Idx);
2681 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2684 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2689 if (SrcNumElts > MaskNumElts) {
2690 // Analyze the access pattern of the vector to see if we can extract
2691 // two subvectors and do the shuffle. The analysis is done by calculating
2692 // the range of elements the mask access on both vectors.
2693 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2694 int MaxRange[2] = {-1, -1};
2696 for (unsigned i = 0; i != MaskNumElts; ++i) {
2702 if (Idx >= (int)SrcNumElts) {
2706 if (Idx > MaxRange[Input])
2707 MaxRange[Input] = Idx;
2708 if (Idx < MinRange[Input])
2709 MinRange[Input] = Idx;
2712 // Check if the access is smaller than the vector size and can we find
2713 // a reasonable extract index.
2714 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2716 int StartIdx[2]; // StartIdx to extract from
2717 for (int Input=0; Input < 2; ++Input) {
2718 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2719 RangeUse[Input] = 0; // Unused
2720 StartIdx[Input] = 0;
2721 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2722 // Fits within range but we should see if we can find a good
2723 // start index that is a multiple of the mask length.
2724 if (MaxRange[Input] < (int)MaskNumElts) {
2725 RangeUse[Input] = 1; // Extract from beginning of the vector
2726 StartIdx[Input] = 0;
2728 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2729 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2730 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2731 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2736 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2737 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2740 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2741 // Extract appropriate subvector and generate a vector shuffle
2742 for (int Input=0; Input < 2; ++Input) {
2743 SDValue &Src = Input == 0 ? Src1 : Src2;
2744 if (RangeUse[Input] == 0)
2745 Src = DAG.getUNDEF(VT);
2747 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2748 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2751 // Calculate new mask.
2752 SmallVector<int, 8> MappedOps;
2753 for (unsigned i = 0; i != MaskNumElts; ++i) {
2756 MappedOps.push_back(Idx);
2757 else if (Idx < (int)SrcNumElts)
2758 MappedOps.push_back(Idx - StartIdx[0]);
2760 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2763 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2769 // We can't use either concat vectors or extract subvectors so fall back to
2770 // replacing the shuffle with extract and build vector.
2771 // to insert and build vector.
2772 EVT EltVT = VT.getVectorElementType();
2773 EVT PtrVT = TLI.getPointerTy();
2774 SmallVector<SDValue,8> Ops;
2775 for (unsigned i = 0; i != MaskNumElts; ++i) {
2777 Ops.push_back(DAG.getUNDEF(EltVT));
2782 if (Idx < (int)SrcNumElts)
2783 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2784 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2786 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2788 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2794 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2795 VT, &Ops[0], Ops.size()));
2798 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2799 const Value *Op0 = I.getOperand(0);
2800 const Value *Op1 = I.getOperand(1);
2801 const Type *AggTy = I.getType();
2802 const Type *ValTy = Op1->getType();
2803 bool IntoUndef = isa<UndefValue>(Op0);
2804 bool FromUndef = isa<UndefValue>(Op1);
2806 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2808 SmallVector<EVT, 4> AggValueVTs;
2809 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2810 SmallVector<EVT, 4> ValValueVTs;
2811 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2813 unsigned NumAggValues = AggValueVTs.size();
2814 unsigned NumValValues = ValValueVTs.size();
2815 SmallVector<SDValue, 4> Values(NumAggValues);
2817 SDValue Agg = getValue(Op0);
2818 SDValue Val = getValue(Op1);
2820 // Copy the beginning value(s) from the original aggregate.
2821 for (; i != LinearIndex; ++i)
2822 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2823 SDValue(Agg.getNode(), Agg.getResNo() + i);
2824 // Copy values from the inserted value(s).
2825 for (; i != LinearIndex + NumValValues; ++i)
2826 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2827 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2828 // Copy remaining value(s) from the original aggregate.
2829 for (; i != NumAggValues; ++i)
2830 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2831 SDValue(Agg.getNode(), Agg.getResNo() + i);
2833 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2834 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2835 &Values[0], NumAggValues));
2838 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2839 const Value *Op0 = I.getOperand(0);
2840 const Type *AggTy = Op0->getType();
2841 const Type *ValTy = I.getType();
2842 bool OutOfUndef = isa<UndefValue>(Op0);
2844 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2846 SmallVector<EVT, 4> ValValueVTs;
2847 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2849 unsigned NumValValues = ValValueVTs.size();
2850 SmallVector<SDValue, 4> Values(NumValValues);
2852 SDValue Agg = getValue(Op0);
2853 // Copy out the selected value(s).
2854 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2855 Values[i - LinearIndex] =
2857 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2858 SDValue(Agg.getNode(), Agg.getResNo() + i);
2860 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2861 DAG.getVTList(&ValValueVTs[0], NumValValues),
2862 &Values[0], NumValValues));
2865 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2866 SDValue N = getValue(I.getOperand(0));
2867 const Type *Ty = I.getOperand(0)->getType();
2869 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2871 const Value *Idx = *OI;
2872 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2873 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2876 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2877 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2878 DAG.getIntPtrConstant(Offset));
2881 Ty = StTy->getElementType(Field);
2883 Ty = cast<SequentialType>(Ty)->getElementType();
2885 // If this is a constant subscript, handle it quickly.
2886 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2887 if (CI->isZero()) continue;
2889 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2891 EVT PTy = TLI.getPointerTy();
2892 unsigned PtrBits = PTy.getSizeInBits();
2894 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2896 DAG.getConstant(Offs, MVT::i64));
2898 OffsVal = DAG.getIntPtrConstant(Offs);
2900 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2905 // N = N + Idx * ElementSize;
2906 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2907 TD->getTypeAllocSize(Ty));
2908 SDValue IdxN = getValue(Idx);
2910 // If the index is smaller or larger than intptr_t, truncate or extend
2912 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2914 // If this is a multiply by a power of two, turn it into a shl
2915 // immediately. This is a very common case.
2916 if (ElementSize != 1) {
2917 if (ElementSize.isPowerOf2()) {
2918 unsigned Amt = ElementSize.logBase2();
2919 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2920 N.getValueType(), IdxN,
2921 DAG.getConstant(Amt, TLI.getPointerTy()));
2923 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2924 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2925 N.getValueType(), IdxN, Scale);
2929 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2930 N.getValueType(), N, IdxN);
2937 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2938 // If this is a fixed sized alloca in the entry block of the function,
2939 // allocate it statically on the stack.
2940 if (FuncInfo.StaticAllocaMap.count(&I))
2941 return; // getValue will auto-populate this.
2943 const Type *Ty = I.getAllocatedType();
2944 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2946 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2949 SDValue AllocSize = getValue(I.getArraySize());
2951 EVT IntPtr = TLI.getPointerTy();
2952 if (AllocSize.getValueType() != IntPtr)
2953 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2955 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2957 DAG.getConstant(TySize, IntPtr));
2959 // Handle alignment. If the requested alignment is less than or equal to
2960 // the stack alignment, ignore it. If the size is greater than or equal to
2961 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2962 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2963 if (Align <= StackAlign)
2966 // Round the size of the allocation up to the stack alignment size
2967 // by add SA-1 to the size.
2968 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2969 AllocSize.getValueType(), AllocSize,
2970 DAG.getIntPtrConstant(StackAlign-1));
2972 // Mask out the low bits for alignment purposes.
2973 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2974 AllocSize.getValueType(), AllocSize,
2975 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2977 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2978 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2979 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2982 DAG.setRoot(DSA.getValue(1));
2984 // Inform the Frame Information that we have just allocated a variable-sized
2986 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2989 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2990 const Value *SV = I.getOperand(0);
2991 SDValue Ptr = getValue(SV);
2993 const Type *Ty = I.getType();
2995 bool isVolatile = I.isVolatile();
2996 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2997 unsigned Alignment = I.getAlignment();
2998 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3000 SmallVector<EVT, 4> ValueVTs;
3001 SmallVector<uint64_t, 4> Offsets;
3002 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3003 unsigned NumValues = ValueVTs.size();
3008 bool ConstantMemory = false;
3009 if (I.isVolatile() || NumValues > MaxParallelChains)
3010 // Serialize volatile loads with other side effects.
3012 else if (AA->pointsToConstantMemory(
3013 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3014 // Do not serialize (non-volatile) loads of constant memory with anything.
3015 Root = DAG.getEntryNode();
3016 ConstantMemory = true;
3018 // Do not serialize non-volatile loads against each other.
3019 Root = DAG.getRoot();
3022 SmallVector<SDValue, 4> Values(NumValues);
3023 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3025 EVT PtrVT = Ptr.getValueType();
3026 unsigned ChainI = 0;
3027 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3028 // Serializing loads here may result in excessive register pressure, and
3029 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3030 // could recover a bit by hoisting nodes upward in the chain by recognizing
3031 // they are side-effect free or do not alias. The optimizer should really
3032 // avoid this case by converting large object/array copies to llvm.memcpy
3033 // (MaxParallelChains should always remain as failsafe).
3034 if (ChainI == MaxParallelChains) {
3035 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3036 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3037 MVT::Other, &Chains[0], ChainI);
3041 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3043 DAG.getConstant(Offsets[i], PtrVT));
3044 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3045 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3046 isNonTemporal, Alignment, TBAAInfo);
3049 Chains[ChainI] = L.getValue(1);
3052 if (!ConstantMemory) {
3053 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3054 MVT::Other, &Chains[0], ChainI);
3058 PendingLoads.push_back(Chain);
3061 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3062 DAG.getVTList(&ValueVTs[0], NumValues),
3063 &Values[0], NumValues));
3066 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3067 const Value *SrcV = I.getOperand(0);
3068 const Value *PtrV = I.getOperand(1);
3070 SmallVector<EVT, 4> ValueVTs;
3071 SmallVector<uint64_t, 4> Offsets;
3072 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3073 unsigned NumValues = ValueVTs.size();
3077 // Get the lowered operands. Note that we do this after
3078 // checking if NumResults is zero, because with zero results
3079 // the operands won't have values in the map.
3080 SDValue Src = getValue(SrcV);
3081 SDValue Ptr = getValue(PtrV);
3083 SDValue Root = getRoot();
3084 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3086 EVT PtrVT = Ptr.getValueType();
3087 bool isVolatile = I.isVolatile();
3088 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3089 unsigned Alignment = I.getAlignment();
3090 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3092 unsigned ChainI = 0;
3093 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3094 // See visitLoad comments.
3095 if (ChainI == MaxParallelChains) {
3096 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3097 MVT::Other, &Chains[0], ChainI);
3101 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3102 DAG.getConstant(Offsets[i], PtrVT));
3103 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3104 SDValue(Src.getNode(), Src.getResNo() + i),
3105 Add, MachinePointerInfo(PtrV, Offsets[i]),
3106 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3107 Chains[ChainI] = St;
3110 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3111 MVT::Other, &Chains[0], ChainI);
3113 AssignOrderingToNode(StoreNode.getNode());
3114 DAG.setRoot(StoreNode);
3117 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3119 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3120 unsigned Intrinsic) {
3121 bool HasChain = !I.doesNotAccessMemory();
3122 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3124 // Build the operand list.
3125 SmallVector<SDValue, 8> Ops;
3126 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3128 // We don't need to serialize loads against other loads.
3129 Ops.push_back(DAG.getRoot());
3131 Ops.push_back(getRoot());
3135 // Info is set by getTgtMemInstrinsic
3136 TargetLowering::IntrinsicInfo Info;
3137 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3139 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3140 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3141 Info.opc == ISD::INTRINSIC_W_CHAIN)
3142 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3144 // Add all operands of the call to the operand list.
3145 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3146 SDValue Op = getValue(I.getArgOperand(i));
3147 assert(TLI.isTypeLegal(Op.getValueType()) &&
3148 "Intrinsic uses a non-legal type?");
3152 SmallVector<EVT, 4> ValueVTs;
3153 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3155 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3156 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3157 "Intrinsic uses a non-legal type?");
3162 ValueVTs.push_back(MVT::Other);
3164 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3168 if (IsTgtIntrinsic) {
3169 // This is target intrinsic that touches memory
3170 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3171 VTs, &Ops[0], Ops.size(),
3173 MachinePointerInfo(Info.ptrVal, Info.offset),
3174 Info.align, Info.vol,
3175 Info.readMem, Info.writeMem);
3176 } else if (!HasChain) {
3177 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3178 VTs, &Ops[0], Ops.size());
3179 } else if (!I.getType()->isVoidTy()) {
3180 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3181 VTs, &Ops[0], Ops.size());
3183 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3184 VTs, &Ops[0], Ops.size());
3188 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3190 PendingLoads.push_back(Chain);
3195 if (!I.getType()->isVoidTy()) {
3196 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3197 EVT VT = TLI.getValueType(PTy);
3198 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3201 setValue(&I, Result);
3205 /// GetSignificand - Get the significand and build it into a floating-point
3206 /// number with exponent of 1:
3208 /// Op = (Op & 0x007fffff) | 0x3f800000;
3210 /// where Op is the hexidecimal representation of floating point value.
3212 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3213 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3214 DAG.getConstant(0x007fffff, MVT::i32));
3215 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3216 DAG.getConstant(0x3f800000, MVT::i32));
3217 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3220 /// GetExponent - Get the exponent:
3222 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3224 /// where Op is the hexidecimal representation of floating point value.
3226 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3228 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3229 DAG.getConstant(0x7f800000, MVT::i32));
3230 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3231 DAG.getConstant(23, TLI.getPointerTy()));
3232 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3233 DAG.getConstant(127, MVT::i32));
3234 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3237 /// getF32Constant - Get 32-bit floating point constant.
3239 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3240 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3243 /// Inlined utility function to implement binary input atomic intrinsics for
3244 /// visitIntrinsicCall: I is a call instruction
3245 /// Op is the associated NodeType for I
3247 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3249 SDValue Root = getRoot();
3251 DAG.getAtomic(Op, getCurDebugLoc(),
3252 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3254 getValue(I.getArgOperand(0)),
3255 getValue(I.getArgOperand(1)),
3256 I.getArgOperand(0));
3258 DAG.setRoot(L.getValue(1));
3262 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3264 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3265 SDValue Op1 = getValue(I.getArgOperand(0));
3266 SDValue Op2 = getValue(I.getArgOperand(1));
3268 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3269 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3273 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3274 /// limited-precision mode.
3276 SelectionDAGBuilder::visitExp(const CallInst &I) {
3278 DebugLoc dl = getCurDebugLoc();
3280 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3281 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3282 SDValue Op = getValue(I.getArgOperand(0));
3284 // Put the exponent in the right bit position for later addition to the
3287 // #define LOG2OFe 1.4426950f
3288 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3289 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3290 getF32Constant(DAG, 0x3fb8aa3b));
3291 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3293 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3294 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3295 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3297 // IntegerPartOfX <<= 23;
3298 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3299 DAG.getConstant(23, TLI.getPointerTy()));
3301 if (LimitFloatPrecision <= 6) {
3302 // For floating-point precision of 6:
3304 // TwoToFractionalPartOfX =
3306 // (0.735607626f + 0.252464424f * x) * x;
3308 // error 0.0144103317, which is 6 bits
3309 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3310 getF32Constant(DAG, 0x3e814304));
3311 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3312 getF32Constant(DAG, 0x3f3c50c8));
3313 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3314 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3315 getF32Constant(DAG, 0x3f7f5e7e));
3316 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3318 // Add the exponent into the result in integer domain.
3319 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3320 TwoToFracPartOfX, IntegerPartOfX);
3322 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3323 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3324 // For floating-point precision of 12:
3326 // TwoToFractionalPartOfX =
3329 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3331 // 0.000107046256 error, which is 13 to 14 bits
3332 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3333 getF32Constant(DAG, 0x3da235e3));
3334 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3335 getF32Constant(DAG, 0x3e65b8f3));
3336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3337 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3338 getF32Constant(DAG, 0x3f324b07));
3339 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3340 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3341 getF32Constant(DAG, 0x3f7ff8fd));
3342 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3344 // Add the exponent into the result in integer domain.
3345 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3346 TwoToFracPartOfX, IntegerPartOfX);
3348 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3349 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3350 // For floating-point precision of 18:
3352 // TwoToFractionalPartOfX =
3356 // (0.554906021e-1f +
3357 // (0.961591928e-2f +
3358 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3360 // error 2.47208000*10^(-7), which is better than 18 bits
3361 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3362 getF32Constant(DAG, 0x3924b03e));
3363 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3364 getF32Constant(DAG, 0x3ab24b87));
3365 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3366 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3367 getF32Constant(DAG, 0x3c1d8c17));
3368 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3369 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3370 getF32Constant(DAG, 0x3d634a1d));
3371 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3372 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3373 getF32Constant(DAG, 0x3e75fe14));
3374 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3375 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3376 getF32Constant(DAG, 0x3f317234));
3377 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3378 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3379 getF32Constant(DAG, 0x3f800000));
3380 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3383 // Add the exponent into the result in integer domain.
3384 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3385 TwoToFracPartOfX, IntegerPartOfX);
3387 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3390 // No special expansion.
3391 result = DAG.getNode(ISD::FEXP, dl,
3392 getValue(I.getArgOperand(0)).getValueType(),
3393 getValue(I.getArgOperand(0)));
3396 setValue(&I, result);
3399 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3400 /// limited-precision mode.
3402 SelectionDAGBuilder::visitLog(const CallInst &I) {
3404 DebugLoc dl = getCurDebugLoc();
3406 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3407 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3408 SDValue Op = getValue(I.getArgOperand(0));
3409 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3411 // Scale the exponent by log(2) [0.69314718f].
3412 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3413 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3414 getF32Constant(DAG, 0x3f317218));
3416 // Get the significand and build it into a floating-point number with
3418 SDValue X = GetSignificand(DAG, Op1, dl);
3420 if (LimitFloatPrecision <= 6) {
3421 // For floating-point precision of 6:
3425 // (1.4034025f - 0.23903021f * x) * x;
3427 // error 0.0034276066, which is better than 8 bits
3428 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3429 getF32Constant(DAG, 0xbe74c456));
3430 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3431 getF32Constant(DAG, 0x3fb3a2b1));
3432 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3433 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3434 getF32Constant(DAG, 0x3f949a29));
3436 result = DAG.getNode(ISD::FADD, dl,
3437 MVT::f32, LogOfExponent, LogOfMantissa);
3438 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3439 // For floating-point precision of 12:
3445 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3447 // error 0.000061011436, which is 14 bits
3448 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3449 getF32Constant(DAG, 0xbd67b6d6));
3450 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3451 getF32Constant(DAG, 0x3ee4f4b8));
3452 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3453 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3454 getF32Constant(DAG, 0x3fbc278b));
3455 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3456 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3457 getF32Constant(DAG, 0x40348e95));
3458 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3459 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3460 getF32Constant(DAG, 0x3fdef31a));
3462 result = DAG.getNode(ISD::FADD, dl,
3463 MVT::f32, LogOfExponent, LogOfMantissa);
3464 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3465 // For floating-point precision of 18:
3473 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3475 // error 0.0000023660568, which is better than 18 bits
3476 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3477 getF32Constant(DAG, 0xbc91e5ac));
3478 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3479 getF32Constant(DAG, 0x3e4350aa));
3480 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3481 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3482 getF32Constant(DAG, 0x3f60d3e3));
3483 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3484 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3485 getF32Constant(DAG, 0x4011cdf0));
3486 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3487 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3488 getF32Constant(DAG, 0x406cfd1c));
3489 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3490 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3491 getF32Constant(DAG, 0x408797cb));
3492 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3493 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3494 getF32Constant(DAG, 0x4006dcab));
3496 result = DAG.getNode(ISD::FADD, dl,
3497 MVT::f32, LogOfExponent, LogOfMantissa);
3500 // No special expansion.
3501 result = DAG.getNode(ISD::FLOG, dl,
3502 getValue(I.getArgOperand(0)).getValueType(),
3503 getValue(I.getArgOperand(0)));
3506 setValue(&I, result);
3509 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3510 /// limited-precision mode.
3512 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3514 DebugLoc dl = getCurDebugLoc();
3516 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3517 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3518 SDValue Op = getValue(I.getArgOperand(0));
3519 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3521 // Get the exponent.
3522 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3524 // Get the significand and build it into a floating-point number with
3526 SDValue X = GetSignificand(DAG, Op1, dl);
3528 // Different possible minimax approximations of significand in
3529 // floating-point for various degrees of accuracy over [1,2].
3530 if (LimitFloatPrecision <= 6) {
3531 // For floating-point precision of 6:
3533 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3535 // error 0.0049451742, which is more than 7 bits
3536 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3537 getF32Constant(DAG, 0xbeb08fe0));
3538 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3539 getF32Constant(DAG, 0x40019463));
3540 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3541 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3542 getF32Constant(DAG, 0x3fd6633d));
3544 result = DAG.getNode(ISD::FADD, dl,
3545 MVT::f32, LogOfExponent, Log2ofMantissa);
3546 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3547 // For floating-point precision of 12:
3553 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3555 // error 0.0000876136000, which is better than 13 bits
3556 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3557 getF32Constant(DAG, 0xbda7262e));
3558 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3559 getF32Constant(DAG, 0x3f25280b));
3560 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3561 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3562 getF32Constant(DAG, 0x4007b923));
3563 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3564 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3565 getF32Constant(DAG, 0x40823e2f));
3566 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3567 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3568 getF32Constant(DAG, 0x4020d29c));
3570 result = DAG.getNode(ISD::FADD, dl,
3571 MVT::f32, LogOfExponent, Log2ofMantissa);
3572 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3573 // For floating-point precision of 18:
3582 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3584 // error 0.0000018516, which is better than 18 bits
3585 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3586 getF32Constant(DAG, 0xbcd2769e));
3587 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3588 getF32Constant(DAG, 0x3e8ce0b9));
3589 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3590 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3591 getF32Constant(DAG, 0x3fa22ae7));
3592 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3593 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3594 getF32Constant(DAG, 0x40525723));
3595 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3596 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3597 getF32Constant(DAG, 0x40aaf200));
3598 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3599 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3600 getF32Constant(DAG, 0x40c39dad));
3601 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3602 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3603 getF32Constant(DAG, 0x4042902c));
3605 result = DAG.getNode(ISD::FADD, dl,
3606 MVT::f32, LogOfExponent, Log2ofMantissa);
3609 // No special expansion.
3610 result = DAG.getNode(ISD::FLOG2, dl,
3611 getValue(I.getArgOperand(0)).getValueType(),
3612 getValue(I.getArgOperand(0)));
3615 setValue(&I, result);
3618 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3619 /// limited-precision mode.
3621 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3623 DebugLoc dl = getCurDebugLoc();
3625 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3626 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3627 SDValue Op = getValue(I.getArgOperand(0));
3628 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3630 // Scale the exponent by log10(2) [0.30102999f].
3631 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3632 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3633 getF32Constant(DAG, 0x3e9a209a));
3635 // Get the significand and build it into a floating-point number with
3637 SDValue X = GetSignificand(DAG, Op1, dl);
3639 if (LimitFloatPrecision <= 6) {
3640 // For floating-point precision of 6:
3642 // Log10ofMantissa =
3644 // (0.60948995f - 0.10380950f * x) * x;
3646 // error 0.0014886165, which is 6 bits
3647 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3648 getF32Constant(DAG, 0xbdd49a13));
3649 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3650 getF32Constant(DAG, 0x3f1c0789));
3651 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3652 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3653 getF32Constant(DAG, 0x3f011300));
3655 result = DAG.getNode(ISD::FADD, dl,
3656 MVT::f32, LogOfExponent, Log10ofMantissa);
3657 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3658 // For floating-point precision of 12:
3660 // Log10ofMantissa =
3663 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3665 // error 0.00019228036, which is better than 12 bits
3666 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3667 getF32Constant(DAG, 0x3d431f31));
3668 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3669 getF32Constant(DAG, 0x3ea21fb2));
3670 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3671 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3672 getF32Constant(DAG, 0x3f6ae232));
3673 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3674 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3675 getF32Constant(DAG, 0x3f25f7c3));
3677 result = DAG.getNode(ISD::FADD, dl,
3678 MVT::f32, LogOfExponent, Log10ofMantissa);
3679 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3680 // For floating-point precision of 18:
3682 // Log10ofMantissa =
3687 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3689 // error 0.0000037995730, which is better than 18 bits
3690 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3691 getF32Constant(DAG, 0x3c5d51ce));
3692 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3693 getF32Constant(DAG, 0x3e00685a));
3694 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3695 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3696 getF32Constant(DAG, 0x3efb6798));
3697 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3698 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3699 getF32Constant(DAG, 0x3f88d192));
3700 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3701 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3702 getF32Constant(DAG, 0x3fc4316c));
3703 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3704 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3705 getF32Constant(DAG, 0x3f57ce70));
3707 result = DAG.getNode(ISD::FADD, dl,
3708 MVT::f32, LogOfExponent, Log10ofMantissa);
3711 // No special expansion.
3712 result = DAG.getNode(ISD::FLOG10, dl,
3713 getValue(I.getArgOperand(0)).getValueType(),
3714 getValue(I.getArgOperand(0)));
3717 setValue(&I, result);
3720 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3721 /// limited-precision mode.
3723 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3725 DebugLoc dl = getCurDebugLoc();
3727 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3728 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3729 SDValue Op = getValue(I.getArgOperand(0));
3731 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3733 // FractionalPartOfX = x - (float)IntegerPartOfX;
3734 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3735 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3737 // IntegerPartOfX <<= 23;
3738 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3739 DAG.getConstant(23, TLI.getPointerTy()));
3741 if (LimitFloatPrecision <= 6) {
3742 // For floating-point precision of 6:
3744 // TwoToFractionalPartOfX =
3746 // (0.735607626f + 0.252464424f * x) * x;
3748 // error 0.0144103317, which is 6 bits
3749 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3750 getF32Constant(DAG, 0x3e814304));
3751 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3752 getF32Constant(DAG, 0x3f3c50c8));
3753 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3754 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3755 getF32Constant(DAG, 0x3f7f5e7e));
3756 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3757 SDValue TwoToFractionalPartOfX =
3758 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3760 result = DAG.getNode(ISD::BITCAST, dl,
3761 MVT::f32, TwoToFractionalPartOfX);
3762 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3763 // For floating-point precision of 12:
3765 // TwoToFractionalPartOfX =
3768 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3770 // error 0.000107046256, which is 13 to 14 bits
3771 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3772 getF32Constant(DAG, 0x3da235e3));
3773 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3774 getF32Constant(DAG, 0x3e65b8f3));
3775 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3776 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3777 getF32Constant(DAG, 0x3f324b07));
3778 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3779 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3780 getF32Constant(DAG, 0x3f7ff8fd));
3781 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3782 SDValue TwoToFractionalPartOfX =
3783 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3785 result = DAG.getNode(ISD::BITCAST, dl,
3786 MVT::f32, TwoToFractionalPartOfX);
3787 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3788 // For floating-point precision of 18:
3790 // TwoToFractionalPartOfX =
3794 // (0.554906021e-1f +
3795 // (0.961591928e-2f +
3796 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3797 // error 2.47208000*10^(-7), which is better than 18 bits
3798 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3799 getF32Constant(DAG, 0x3924b03e));
3800 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3801 getF32Constant(DAG, 0x3ab24b87));
3802 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3803 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3804 getF32Constant(DAG, 0x3c1d8c17));
3805 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3806 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3807 getF32Constant(DAG, 0x3d634a1d));
3808 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3809 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3810 getF32Constant(DAG, 0x3e75fe14));
3811 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3812 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3813 getF32Constant(DAG, 0x3f317234));
3814 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3815 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3816 getF32Constant(DAG, 0x3f800000));
3817 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3818 SDValue TwoToFractionalPartOfX =
3819 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3821 result = DAG.getNode(ISD::BITCAST, dl,
3822 MVT::f32, TwoToFractionalPartOfX);
3825 // No special expansion.
3826 result = DAG.getNode(ISD::FEXP2, dl,
3827 getValue(I.getArgOperand(0)).getValueType(),
3828 getValue(I.getArgOperand(0)));
3831 setValue(&I, result);
3834 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3835 /// limited-precision mode with x == 10.0f.
3837 SelectionDAGBuilder::visitPow(const CallInst &I) {
3839 const Value *Val = I.getArgOperand(0);
3840 DebugLoc dl = getCurDebugLoc();
3841 bool IsExp10 = false;
3843 if (getValue(Val).getValueType() == MVT::f32 &&
3844 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3845 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3846 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3847 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3849 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3854 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3855 SDValue Op = getValue(I.getArgOperand(1));
3857 // Put the exponent in the right bit position for later addition to the
3860 // #define LOG2OF10 3.3219281f
3861 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3862 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3863 getF32Constant(DAG, 0x40549a78));
3864 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3866 // FractionalPartOfX = x - (float)IntegerPartOfX;
3867 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3868 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3870 // IntegerPartOfX <<= 23;
3871 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3872 DAG.getConstant(23, TLI.getPointerTy()));
3874 if (LimitFloatPrecision <= 6) {
3875 // For floating-point precision of 6:
3877 // twoToFractionalPartOfX =
3879 // (0.735607626f + 0.252464424f * x) * x;
3881 // error 0.0144103317, which is 6 bits
3882 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3883 getF32Constant(DAG, 0x3e814304));
3884 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3885 getF32Constant(DAG, 0x3f3c50c8));
3886 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3887 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3888 getF32Constant(DAG, 0x3f7f5e7e));
3889 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3890 SDValue TwoToFractionalPartOfX =
3891 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3893 result = DAG.getNode(ISD::BITCAST, dl,
3894 MVT::f32, TwoToFractionalPartOfX);
3895 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3896 // For floating-point precision of 12:
3898 // TwoToFractionalPartOfX =
3901 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3903 // error 0.000107046256, which is 13 to 14 bits
3904 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3905 getF32Constant(DAG, 0x3da235e3));
3906 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3907 getF32Constant(DAG, 0x3e65b8f3));
3908 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3909 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3910 getF32Constant(DAG, 0x3f324b07));
3911 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3912 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3913 getF32Constant(DAG, 0x3f7ff8fd));
3914 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3915 SDValue TwoToFractionalPartOfX =
3916 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3918 result = DAG.getNode(ISD::BITCAST, dl,
3919 MVT::f32, TwoToFractionalPartOfX);
3920 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3921 // For floating-point precision of 18:
3923 // TwoToFractionalPartOfX =
3927 // (0.554906021e-1f +
3928 // (0.961591928e-2f +
3929 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3930 // error 2.47208000*10^(-7), which is better than 18 bits
3931 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3932 getF32Constant(DAG, 0x3924b03e));
3933 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3934 getF32Constant(DAG, 0x3ab24b87));
3935 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3936 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3937 getF32Constant(DAG, 0x3c1d8c17));
3938 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3939 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3940 getF32Constant(DAG, 0x3d634a1d));
3941 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3942 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3943 getF32Constant(DAG, 0x3e75fe14));
3944 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3945 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3946 getF32Constant(DAG, 0x3f317234));
3947 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3948 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3949 getF32Constant(DAG, 0x3f800000));
3950 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3951 SDValue TwoToFractionalPartOfX =
3952 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3954 result = DAG.getNode(ISD::BITCAST, dl,
3955 MVT::f32, TwoToFractionalPartOfX);
3958 // No special expansion.
3959 result = DAG.getNode(ISD::FPOW, dl,
3960 getValue(I.getArgOperand(0)).getValueType(),
3961 getValue(I.getArgOperand(0)),
3962 getValue(I.getArgOperand(1)));
3965 setValue(&I, result);
3969 /// ExpandPowI - Expand a llvm.powi intrinsic.
3970 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3971 SelectionDAG &DAG) {
3972 // If RHS is a constant, we can expand this out to a multiplication tree,
3973 // otherwise we end up lowering to a call to __powidf2 (for example). When
3974 // optimizing for size, we only want to do this if the expansion would produce
3975 // a small number of multiplies, otherwise we do the full expansion.
3976 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3977 // Get the exponent as a positive value.
3978 unsigned Val = RHSC->getSExtValue();
3979 if ((int)Val < 0) Val = -Val;
3981 // powi(x, 0) -> 1.0
3983 return DAG.getConstantFP(1.0, LHS.getValueType());
3985 const Function *F = DAG.getMachineFunction().getFunction();
3986 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3987 // If optimizing for size, don't insert too many multiplies. This
3988 // inserts up to 5 multiplies.
3989 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3990 // We use the simple binary decomposition method to generate the multiply
3991 // sequence. There are more optimal ways to do this (for example,
3992 // powi(x,15) generates one more multiply than it should), but this has
3993 // the benefit of being both really simple and much better than a libcall.
3994 SDValue Res; // Logically starts equal to 1.0
3995 SDValue CurSquare = LHS;
3999 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4001 Res = CurSquare; // 1.0*CurSquare.
4004 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4005 CurSquare, CurSquare);
4009 // If the original was negative, invert the result, producing 1/(x*x*x).
4010 if (RHSC->getSExtValue() < 0)
4011 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4012 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4017 // Otherwise, expand to a libcall.
4018 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4021 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4022 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4023 /// At the end of instruction selection, they will be inserted to the entry BB.
4025 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4028 const Argument *Arg = dyn_cast<Argument>(V);
4032 MachineFunction &MF = DAG.getMachineFunction();
4033 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4034 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4036 // Ignore inlined function arguments here.
4037 DIVariable DV(Variable);
4038 if (DV.isInlinedFnArgument(MF.getFunction()))
4041 MachineBasicBlock *MBB = FuncInfo.MBB;
4042 if (MBB != &MF.front())
4046 if (Arg->hasByValAttr()) {
4047 // Byval arguments' frame index is recorded during argument lowering.
4048 // Use this info directly.
4049 Reg = TRI->getFrameRegister(MF);
4050 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4051 // If byval argument ofset is not recorded then ignore this.
4056 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4057 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4058 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4059 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4060 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4067 // Check if ValueMap has reg number.
4068 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4069 if (VMI != FuncInfo.ValueMap.end())
4073 if (!Reg && N.getNode()) {
4074 // Check if frame index is available.
4075 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4076 if (FrameIndexSDNode *FINode =
4077 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4078 Reg = TRI->getFrameRegister(MF);
4079 Offset = FINode->getIndex();
4086 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4087 TII->get(TargetOpcode::DBG_VALUE))
4088 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4089 FuncInfo.ArgDbgValues.push_back(&*MIB);
4093 // VisualStudio defines setjmp as _setjmp
4094 #if defined(_MSC_VER) && defined(setjmp) && \
4095 !defined(setjmp_undefined_for_msvc)
4096 # pragma push_macro("setjmp")
4098 # define setjmp_undefined_for_msvc
4101 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4102 /// we want to emit this as a call to a named external function, return the name
4103 /// otherwise lower it and return null.
4105 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4106 DebugLoc dl = getCurDebugLoc();
4109 switch (Intrinsic) {
4111 // By default, turn this into a target intrinsic node.
4112 visitTargetIntrinsic(I, Intrinsic);
4114 case Intrinsic::vastart: visitVAStart(I); return 0;
4115 case Intrinsic::vaend: visitVAEnd(I); return 0;
4116 case Intrinsic::vacopy: visitVACopy(I); return 0;
4117 case Intrinsic::returnaddress:
4118 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4119 getValue(I.getArgOperand(0))));
4121 case Intrinsic::frameaddress:
4122 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4123 getValue(I.getArgOperand(0))));
4125 case Intrinsic::setjmp:
4126 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4127 case Intrinsic::longjmp:
4128 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4129 case Intrinsic::memcpy: {
4130 // Assert for address < 256 since we support only user defined address
4132 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4134 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4136 "Unknown address space");
4137 SDValue Op1 = getValue(I.getArgOperand(0));
4138 SDValue Op2 = getValue(I.getArgOperand(1));
4139 SDValue Op3 = getValue(I.getArgOperand(2));
4140 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4141 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4142 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4143 MachinePointerInfo(I.getArgOperand(0)),
4144 MachinePointerInfo(I.getArgOperand(1))));
4147 case Intrinsic::memset: {
4148 // Assert for address < 256 since we support only user defined address
4150 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4152 "Unknown address space");
4153 SDValue Op1 = getValue(I.getArgOperand(0));
4154 SDValue Op2 = getValue(I.getArgOperand(1));
4155 SDValue Op3 = getValue(I.getArgOperand(2));
4156 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4157 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4158 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4159 MachinePointerInfo(I.getArgOperand(0))));
4162 case Intrinsic::memmove: {
4163 // Assert for address < 256 since we support only user defined address
4165 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4167 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4169 "Unknown address space");
4170 SDValue Op1 = getValue(I.getArgOperand(0));
4171 SDValue Op2 = getValue(I.getArgOperand(1));
4172 SDValue Op3 = getValue(I.getArgOperand(2));
4173 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4174 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4175 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4176 MachinePointerInfo(I.getArgOperand(0)),
4177 MachinePointerInfo(I.getArgOperand(1))));
4180 case Intrinsic::dbg_declare: {
4181 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4182 MDNode *Variable = DI.getVariable();
4183 const Value *Address = DI.getAddress();
4184 if (!Address || !DIVariable(DI.getVariable()).Verify())
4187 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4188 // but do not always have a corresponding SDNode built. The SDNodeOrder
4189 // absolute, but not relative, values are different depending on whether
4190 // debug info exists.
4193 // Check if address has undef value.
4194 if (isa<UndefValue>(Address) ||
4195 (Address->use_empty() && !isa<Argument>(Address))) {
4196 DEBUG(dbgs() << "Dropping debug info for " << DI);
4200 SDValue &N = NodeMap[Address];
4201 if (!N.getNode() && isa<Argument>(Address))
4202 // Check unused arguments map.
4203 N = UnusedArgNodeMap[Address];
4206 // Parameters are handled specially.
4208 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4209 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4210 Address = BCI->getOperand(0);
4211 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4213 if (isParameter && !AI) {
4214 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4216 // Byval parameter. We have a frame index at this point.
4217 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4218 0, dl, SDNodeOrder);
4220 // Can't do anything with other non-AI cases yet. This might be a
4221 // parameter of a callee function that got inlined, for example.
4222 DEBUG(dbgs() << "Dropping debug info for " << DI);
4226 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4227 0, dl, SDNodeOrder);
4229 // Can't do anything with other non-AI cases yet.
4230 DEBUG(dbgs() << "Dropping debug info for " << DI);
4233 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4235 // If Address is an argument then try to emit its dbg value using
4236 // virtual register info from the FuncInfo.ValueMap.
4237 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4238 // If variable is pinned by a alloca in dominating bb then
4239 // use StaticAllocaMap.
4240 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4241 if (AI->getParent() != DI.getParent()) {
4242 DenseMap<const AllocaInst*, int>::iterator SI =
4243 FuncInfo.StaticAllocaMap.find(AI);
4244 if (SI != FuncInfo.StaticAllocaMap.end()) {
4245 SDV = DAG.getDbgValue(Variable, SI->second,
4246 0, dl, SDNodeOrder);
4247 DAG.AddDbgValue(SDV, 0, false);
4252 DEBUG(dbgs() << "Dropping debug info for " << DI);
4257 case Intrinsic::dbg_value: {
4258 const DbgValueInst &DI = cast<DbgValueInst>(I);
4259 if (!DIVariable(DI.getVariable()).Verify())
4262 MDNode *Variable = DI.getVariable();
4263 uint64_t Offset = DI.getOffset();
4264 const Value *V = DI.getValue();
4268 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4269 // but do not always have a corresponding SDNode built. The SDNodeOrder
4270 // absolute, but not relative, values are different depending on whether
4271 // debug info exists.
4274 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4275 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4276 DAG.AddDbgValue(SDV, 0, false);
4278 // Do not use getValue() in here; we don't want to generate code at
4279 // this point if it hasn't been done yet.
4280 SDValue N = NodeMap[V];
4281 if (!N.getNode() && isa<Argument>(V))
4282 // Check unused arguments map.
4283 N = UnusedArgNodeMap[V];
4285 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4286 SDV = DAG.getDbgValue(Variable, N.getNode(),
4287 N.getResNo(), Offset, dl, SDNodeOrder);
4288 DAG.AddDbgValue(SDV, N.getNode(), false);
4290 } else if (!V->use_empty() ) {
4291 // Do not call getValue(V) yet, as we don't want to generate code.
4292 // Remember it for later.
4293 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4294 DanglingDebugInfoMap[V] = DDI;
4296 // We may expand this to cover more cases. One case where we have no
4297 // data available is an unreferenced parameter.
4298 DEBUG(dbgs() << "Dropping debug info for " << DI);
4302 // Build a debug info table entry.
4303 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4304 V = BCI->getOperand(0);
4305 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4306 // Don't handle byval struct arguments or VLAs, for example.
4309 DenseMap<const AllocaInst*, int>::iterator SI =
4310 FuncInfo.StaticAllocaMap.find(AI);
4311 if (SI == FuncInfo.StaticAllocaMap.end())
4313 int FI = SI->second;
4315 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4316 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4317 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4320 case Intrinsic::eh_exception: {
4321 // Insert the EXCEPTIONADDR instruction.
4322 assert(FuncInfo.MBB->isLandingPad() &&
4323 "Call to eh.exception not in landing pad!");
4324 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4326 Ops[0] = DAG.getRoot();
4327 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4329 DAG.setRoot(Op.getValue(1));
4333 case Intrinsic::eh_selector: {
4334 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4335 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4336 if (CallMBB->isLandingPad())
4337 AddCatchInfo(I, &MMI, CallMBB);
4340 FuncInfo.CatchInfoLost.insert(&I);
4342 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4343 unsigned Reg = TLI.getExceptionSelectorRegister();
4344 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4347 // Insert the EHSELECTION instruction.
4348 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4350 Ops[0] = getValue(I.getArgOperand(0));
4352 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4353 DAG.setRoot(Op.getValue(1));
4354 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4358 case Intrinsic::eh_typeid_for: {
4359 // Find the type id for the given typeinfo.
4360 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4361 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4362 Res = DAG.getConstant(TypeID, MVT::i32);
4367 case Intrinsic::eh_return_i32:
4368 case Intrinsic::eh_return_i64:
4369 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4370 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4373 getValue(I.getArgOperand(0)),
4374 getValue(I.getArgOperand(1))));
4376 case Intrinsic::eh_unwind_init:
4377 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4379 case Intrinsic::eh_dwarf_cfa: {
4380 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4381 TLI.getPointerTy());
4382 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4384 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4385 TLI.getPointerTy()),
4387 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4389 DAG.getConstant(0, TLI.getPointerTy()));
4390 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4394 case Intrinsic::eh_sjlj_callsite: {
4395 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4396 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4397 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4398 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4400 MMI.setCurrentCallSite(CI->getZExtValue());
4403 case Intrinsic::eh_sjlj_setjmp: {
4404 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4405 getValue(I.getArgOperand(0))));
4408 case Intrinsic::eh_sjlj_longjmp: {
4409 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4410 getRoot(), getValue(I.getArgOperand(0))));
4413 case Intrinsic::eh_sjlj_dispatch_setup: {
4414 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4415 getRoot(), getValue(I.getArgOperand(0))));
4419 case Intrinsic::x86_mmx_pslli_w:
4420 case Intrinsic::x86_mmx_pslli_d:
4421 case Intrinsic::x86_mmx_pslli_q:
4422 case Intrinsic::x86_mmx_psrli_w:
4423 case Intrinsic::x86_mmx_psrli_d:
4424 case Intrinsic::x86_mmx_psrli_q:
4425 case Intrinsic::x86_mmx_psrai_w:
4426 case Intrinsic::x86_mmx_psrai_d: {
4427 SDValue ShAmt = getValue(I.getArgOperand(1));
4428 if (isa<ConstantSDNode>(ShAmt)) {
4429 visitTargetIntrinsic(I, Intrinsic);
4432 unsigned NewIntrinsic = 0;
4433 EVT ShAmtVT = MVT::v2i32;
4434 switch (Intrinsic) {
4435 case Intrinsic::x86_mmx_pslli_w:
4436 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4438 case Intrinsic::x86_mmx_pslli_d:
4439 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4441 case Intrinsic::x86_mmx_pslli_q:
4442 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4444 case Intrinsic::x86_mmx_psrli_w:
4445 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4447 case Intrinsic::x86_mmx_psrli_d:
4448 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4450 case Intrinsic::x86_mmx_psrli_q:
4451 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4453 case Intrinsic::x86_mmx_psrai_w:
4454 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4456 case Intrinsic::x86_mmx_psrai_d:
4457 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4459 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4462 // The vector shift intrinsics with scalars uses 32b shift amounts but
4463 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4465 // We must do this early because v2i32 is not a legal type.
4466 DebugLoc dl = getCurDebugLoc();
4469 ShOps[1] = DAG.getConstant(0, MVT::i32);
4470 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4471 EVT DestVT = TLI.getValueType(I.getType());
4472 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4473 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4474 DAG.getConstant(NewIntrinsic, MVT::i32),
4475 getValue(I.getArgOperand(0)), ShAmt);
4479 case Intrinsic::convertff:
4480 case Intrinsic::convertfsi:
4481 case Intrinsic::convertfui:
4482 case Intrinsic::convertsif:
4483 case Intrinsic::convertuif:
4484 case Intrinsic::convertss:
4485 case Intrinsic::convertsu:
4486 case Intrinsic::convertus:
4487 case Intrinsic::convertuu: {
4488 ISD::CvtCode Code = ISD::CVT_INVALID;
4489 switch (Intrinsic) {
4490 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4491 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4492 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4493 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4494 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4495 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4496 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4497 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4498 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4500 EVT DestVT = TLI.getValueType(I.getType());
4501 const Value *Op1 = I.getArgOperand(0);
4502 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4503 DAG.getValueType(DestVT),
4504 DAG.getValueType(getValue(Op1).getValueType()),
4505 getValue(I.getArgOperand(1)),
4506 getValue(I.getArgOperand(2)),
4511 case Intrinsic::sqrt:
4512 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4513 getValue(I.getArgOperand(0)).getValueType(),
4514 getValue(I.getArgOperand(0))));
4516 case Intrinsic::powi:
4517 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4518 getValue(I.getArgOperand(1)), DAG));
4520 case Intrinsic::sin:
4521 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4522 getValue(I.getArgOperand(0)).getValueType(),
4523 getValue(I.getArgOperand(0))));
4525 case Intrinsic::cos:
4526 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4527 getValue(I.getArgOperand(0)).getValueType(),
4528 getValue(I.getArgOperand(0))));
4530 case Intrinsic::log:
4533 case Intrinsic::log2:
4536 case Intrinsic::log10:
4539 case Intrinsic::exp:
4542 case Intrinsic::exp2:
4545 case Intrinsic::pow:
4548 case Intrinsic::convert_to_fp16:
4549 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4550 MVT::i16, getValue(I.getArgOperand(0))));
4552 case Intrinsic::convert_from_fp16:
4553 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4554 MVT::f32, getValue(I.getArgOperand(0))));
4556 case Intrinsic::pcmarker: {
4557 SDValue Tmp = getValue(I.getArgOperand(0));
4558 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4561 case Intrinsic::readcyclecounter: {
4562 SDValue Op = getRoot();
4563 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4564 DAG.getVTList(MVT::i64, MVT::Other),
4567 DAG.setRoot(Res.getValue(1));
4570 case Intrinsic::bswap:
4571 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4572 getValue(I.getArgOperand(0)).getValueType(),
4573 getValue(I.getArgOperand(0))));
4575 case Intrinsic::cttz: {
4576 SDValue Arg = getValue(I.getArgOperand(0));
4577 EVT Ty = Arg.getValueType();
4578 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4581 case Intrinsic::ctlz: {
4582 SDValue Arg = getValue(I.getArgOperand(0));
4583 EVT Ty = Arg.getValueType();
4584 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4587 case Intrinsic::ctpop: {
4588 SDValue Arg = getValue(I.getArgOperand(0));
4589 EVT Ty = Arg.getValueType();
4590 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4593 case Intrinsic::stacksave: {
4594 SDValue Op = getRoot();
4595 Res = DAG.getNode(ISD::STACKSAVE, dl,
4596 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4598 DAG.setRoot(Res.getValue(1));
4601 case Intrinsic::stackrestore: {
4602 Res = getValue(I.getArgOperand(0));
4603 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4606 case Intrinsic::stackprotector: {
4607 // Emit code into the DAG to store the stack guard onto the stack.
4608 MachineFunction &MF = DAG.getMachineFunction();
4609 MachineFrameInfo *MFI = MF.getFrameInfo();
4610 EVT PtrTy = TLI.getPointerTy();
4612 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4613 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4615 int FI = FuncInfo.StaticAllocaMap[Slot];
4616 MFI->setStackProtectorIndex(FI);
4618 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4620 // Store the stack protector onto the stack.
4621 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4622 MachinePointerInfo::getFixedStack(FI),
4628 case Intrinsic::objectsize: {
4629 // If we don't know by now, we're never going to know.
4630 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4632 assert(CI && "Non-constant type in __builtin_object_size?");
4634 SDValue Arg = getValue(I.getCalledValue());
4635 EVT Ty = Arg.getValueType();
4638 Res = DAG.getConstant(-1ULL, Ty);
4640 Res = DAG.getConstant(0, Ty);
4645 case Intrinsic::var_annotation:
4646 // Discard annotate attributes
4649 case Intrinsic::init_trampoline: {
4650 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4654 Ops[1] = getValue(I.getArgOperand(0));
4655 Ops[2] = getValue(I.getArgOperand(1));
4656 Ops[3] = getValue(I.getArgOperand(2));
4657 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4658 Ops[5] = DAG.getSrcValue(F);
4660 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4661 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4665 DAG.setRoot(Res.getValue(1));
4668 case Intrinsic::gcroot:
4670 const Value *Alloca = I.getArgOperand(0);
4671 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4673 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4674 GFI->addStackRoot(FI->getIndex(), TypeMap);
4677 case Intrinsic::gcread:
4678 case Intrinsic::gcwrite:
4679 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4681 case Intrinsic::flt_rounds:
4682 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4684 case Intrinsic::trap:
4685 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4687 case Intrinsic::uadd_with_overflow:
4688 return implVisitAluOverflow(I, ISD::UADDO);
4689 case Intrinsic::sadd_with_overflow:
4690 return implVisitAluOverflow(I, ISD::SADDO);
4691 case Intrinsic::usub_with_overflow:
4692 return implVisitAluOverflow(I, ISD::USUBO);
4693 case Intrinsic::ssub_with_overflow:
4694 return implVisitAluOverflow(I, ISD::SSUBO);
4695 case Intrinsic::umul_with_overflow:
4696 return implVisitAluOverflow(I, ISD::UMULO);
4697 case Intrinsic::smul_with_overflow:
4698 return implVisitAluOverflow(I, ISD::SMULO);
4700 case Intrinsic::prefetch: {
4702 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4704 Ops[1] = getValue(I.getArgOperand(0));
4705 Ops[2] = getValue(I.getArgOperand(1));
4706 Ops[3] = getValue(I.getArgOperand(2));
4707 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4708 DAG.getVTList(MVT::Other),
4710 EVT::getIntegerVT(*Context, 8),
4711 MachinePointerInfo(I.getArgOperand(0)),
4713 false, /* volatile */
4715 rw==1)); /* write */
4718 case Intrinsic::memory_barrier: {
4721 for (int x = 1; x < 6; ++x)
4722 Ops[x] = getValue(I.getArgOperand(x - 1));
4724 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4727 case Intrinsic::atomic_cmp_swap: {
4728 SDValue Root = getRoot();
4730 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4731 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4733 getValue(I.getArgOperand(0)),
4734 getValue(I.getArgOperand(1)),
4735 getValue(I.getArgOperand(2)),
4736 MachinePointerInfo(I.getArgOperand(0)));
4738 DAG.setRoot(L.getValue(1));
4741 case Intrinsic::atomic_load_add:
4742 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4743 case Intrinsic::atomic_load_sub:
4744 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4745 case Intrinsic::atomic_load_or:
4746 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4747 case Intrinsic::atomic_load_xor:
4748 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4749 case Intrinsic::atomic_load_and:
4750 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4751 case Intrinsic::atomic_load_nand:
4752 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4753 case Intrinsic::atomic_load_max:
4754 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4755 case Intrinsic::atomic_load_min:
4756 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4757 case Intrinsic::atomic_load_umin:
4758 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4759 case Intrinsic::atomic_load_umax:
4760 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4761 case Intrinsic::atomic_swap:
4762 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4764 case Intrinsic::invariant_start:
4765 case Intrinsic::lifetime_start:
4766 // Discard region information.
4767 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4769 case Intrinsic::invariant_end:
4770 case Intrinsic::lifetime_end:
4771 // Discard region information.
4776 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4778 MachineBasicBlock *LandingPad) {
4779 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4780 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4781 const Type *RetTy = FTy->getReturnType();
4782 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4783 MCSymbol *BeginLabel = 0;
4785 TargetLowering::ArgListTy Args;
4786 TargetLowering::ArgListEntry Entry;
4787 Args.reserve(CS.arg_size());
4789 // Check whether the function can return without sret-demotion.
4790 SmallVector<ISD::OutputArg, 4> Outs;
4791 SmallVector<uint64_t, 4> Offsets;
4792 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4793 Outs, TLI, &Offsets);
4795 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4796 FTy->isVarArg(), Outs, FTy->getContext());
4798 SDValue DemoteStackSlot;
4799 int DemoteStackIdx = -100;
4801 if (!CanLowerReturn) {
4802 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4803 FTy->getReturnType());
4804 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4805 FTy->getReturnType());
4806 MachineFunction &MF = DAG.getMachineFunction();
4807 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4808 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4810 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4811 Entry.Node = DemoteStackSlot;
4812 Entry.Ty = StackSlotPtrType;
4813 Entry.isSExt = false;
4814 Entry.isZExt = false;
4815 Entry.isInReg = false;
4816 Entry.isSRet = true;
4817 Entry.isNest = false;
4818 Entry.isByVal = false;
4819 Entry.Alignment = Align;
4820 Args.push_back(Entry);
4821 RetTy = Type::getVoidTy(FTy->getContext());
4824 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4826 SDValue ArgNode = getValue(*i);
4827 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4829 unsigned attrInd = i - CS.arg_begin() + 1;
4830 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4831 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4832 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4833 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4834 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4835 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4836 Entry.Alignment = CS.getParamAlignment(attrInd);
4837 Args.push_back(Entry);
4841 // Insert a label before the invoke call to mark the try range. This can be
4842 // used to detect deletion of the invoke via the MachineModuleInfo.
4843 BeginLabel = MMI.getContext().CreateTempSymbol();
4845 // For SjLj, keep track of which landing pads go with which invokes
4846 // so as to maintain the ordering of pads in the LSDA.
4847 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4848 if (CallSiteIndex) {
4849 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4850 // Now that the call site is handled, stop tracking it.
4851 MMI.setCurrentCallSite(0);
4854 // Both PendingLoads and PendingExports must be flushed here;
4855 // this call might not return.
4857 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4860 // Check if target-independent constraints permit a tail call here.
4861 // Target-dependent constraints are checked within TLI.LowerCallTo.
4863 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4866 // If there's a possibility that fast-isel has already selected some amount
4867 // of the current basic block, don't emit a tail call.
4868 if (isTailCall && EnableFastISel)
4871 std::pair<SDValue,SDValue> Result =
4872 TLI.LowerCallTo(getRoot(), RetTy,
4873 CS.paramHasAttr(0, Attribute::SExt),
4874 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4875 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4876 CS.getCallingConv(),
4878 !CS.getInstruction()->use_empty(),
4879 Callee, Args, DAG, getCurDebugLoc());
4880 assert((isTailCall || Result.second.getNode()) &&
4881 "Non-null chain expected with non-tail call!");
4882 assert((Result.second.getNode() || !Result.first.getNode()) &&
4883 "Null value expected with tail call!");
4884 if (Result.first.getNode()) {
4885 setValue(CS.getInstruction(), Result.first);
4886 } else if (!CanLowerReturn && Result.second.getNode()) {
4887 // The instruction result is the result of loading from the
4888 // hidden sret parameter.
4889 SmallVector<EVT, 1> PVTs;
4890 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4892 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4893 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4894 EVT PtrVT = PVTs[0];
4895 unsigned NumValues = Outs.size();
4896 SmallVector<SDValue, 4> Values(NumValues);
4897 SmallVector<SDValue, 4> Chains(NumValues);
4899 for (unsigned i = 0; i < NumValues; ++i) {
4900 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4902 DAG.getConstant(Offsets[i], PtrVT));
4903 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4905 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4908 Chains[i] = L.getValue(1);
4911 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4912 MVT::Other, &Chains[0], NumValues);
4913 PendingLoads.push_back(Chain);
4915 // Collect the legal value parts into potentially illegal values
4916 // that correspond to the original function's return values.
4917 SmallVector<EVT, 4> RetTys;
4918 RetTy = FTy->getReturnType();
4919 ComputeValueVTs(TLI, RetTy, RetTys);
4920 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4921 SmallVector<SDValue, 4> ReturnValues;
4922 unsigned CurReg = 0;
4923 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4925 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4926 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4928 SDValue ReturnValue =
4929 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4930 RegisterVT, VT, AssertOp);
4931 ReturnValues.push_back(ReturnValue);
4935 setValue(CS.getInstruction(),
4936 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4937 DAG.getVTList(&RetTys[0], RetTys.size()),
4938 &ReturnValues[0], ReturnValues.size()));
4942 // As a special case, a null chain means that a tail call has been emitted and
4943 // the DAG root is already updated.
4944 if (Result.second.getNode())
4945 DAG.setRoot(Result.second);
4950 // Insert a label at the end of the invoke call to mark the try range. This
4951 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4952 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4953 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4955 // Inform MachineModuleInfo of range.
4956 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4960 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4961 /// value is equal or not-equal to zero.
4962 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4963 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4965 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4966 if (IC->isEquality())
4967 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4968 if (C->isNullValue())
4970 // Unknown instruction.
4976 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4978 SelectionDAGBuilder &Builder) {
4980 // Check to see if this load can be trivially constant folded, e.g. if the
4981 // input is from a string literal.
4982 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4983 // Cast pointer to the type we really want to load.
4984 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4985 PointerType::getUnqual(LoadTy));
4987 if (const Constant *LoadCst =
4988 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4990 return Builder.getValue(LoadCst);
4993 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4994 // still constant memory, the input chain can be the entry node.
4996 bool ConstantMemory = false;
4998 // Do not serialize (non-volatile) loads of constant memory with anything.
4999 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5000 Root = Builder.DAG.getEntryNode();
5001 ConstantMemory = true;
5003 // Do not serialize non-volatile loads against each other.
5004 Root = Builder.DAG.getRoot();
5007 SDValue Ptr = Builder.getValue(PtrVal);
5008 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5009 Ptr, MachinePointerInfo(PtrVal),
5011 false /*nontemporal*/, 1 /* align=1 */);
5013 if (!ConstantMemory)
5014 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5019 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5020 /// If so, return true and lower it, otherwise return false and it will be
5021 /// lowered like a normal call.
5022 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5023 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5024 if (I.getNumArgOperands() != 3)
5027 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5028 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5029 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5030 !I.getType()->isIntegerTy())
5033 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5035 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5036 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5037 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5038 bool ActuallyDoIt = true;
5041 switch (Size->getZExtValue()) {
5043 LoadVT = MVT::Other;
5045 ActuallyDoIt = false;
5049 LoadTy = Type::getInt16Ty(Size->getContext());
5053 LoadTy = Type::getInt32Ty(Size->getContext());
5057 LoadTy = Type::getInt64Ty(Size->getContext());
5061 LoadVT = MVT::v4i32;
5062 LoadTy = Type::getInt32Ty(Size->getContext());
5063 LoadTy = VectorType::get(LoadTy, 4);
5068 // This turns into unaligned loads. We only do this if the target natively
5069 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5070 // we'll only produce a small number of byte loads.
5072 // Require that we can find a legal MVT, and only do this if the target
5073 // supports unaligned loads of that type. Expanding into byte loads would
5075 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5076 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5077 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5078 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5079 ActuallyDoIt = false;
5083 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5084 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5086 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5088 EVT CallVT = TLI.getValueType(I.getType(), true);
5089 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5099 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5100 // Handle inline assembly differently.
5101 if (isa<InlineAsm>(I.getCalledValue())) {
5106 // See if any floating point values are being passed to this function. This is
5107 // used to emit an undefined reference to fltused on Windows.
5108 const FunctionType *FT =
5109 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5110 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5111 if (FT->isVarArg() &&
5112 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5113 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5114 const Type* T = I.getArgOperand(i)->getType();
5115 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5117 if (!i->isFloatingPointTy()) continue;
5118 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5124 const char *RenameFn = 0;
5125 if (Function *F = I.getCalledFunction()) {
5126 if (F->isDeclaration()) {
5127 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5128 if (unsigned IID = II->getIntrinsicID(F)) {
5129 RenameFn = visitIntrinsicCall(I, IID);
5134 if (unsigned IID = F->getIntrinsicID()) {
5135 RenameFn = visitIntrinsicCall(I, IID);
5141 // Check for well-known libc/libm calls. If the function is internal, it
5142 // can't be a library call.
5143 if (!F->hasLocalLinkage() && F->hasName()) {
5144 StringRef Name = F->getName();
5145 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5146 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5147 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5148 I.getType() == I.getArgOperand(0)->getType() &&
5149 I.getType() == I.getArgOperand(1)->getType()) {
5150 SDValue LHS = getValue(I.getArgOperand(0));
5151 SDValue RHS = getValue(I.getArgOperand(1));
5152 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5153 LHS.getValueType(), LHS, RHS));
5156 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5157 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5158 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5159 I.getType() == I.getArgOperand(0)->getType()) {
5160 SDValue Tmp = getValue(I.getArgOperand(0));
5161 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5162 Tmp.getValueType(), Tmp));
5165 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5166 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5167 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5168 I.getType() == I.getArgOperand(0)->getType() &&
5169 I.onlyReadsMemory()) {
5170 SDValue Tmp = getValue(I.getArgOperand(0));
5171 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5172 Tmp.getValueType(), Tmp));
5175 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5176 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5177 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5178 I.getType() == I.getArgOperand(0)->getType() &&
5179 I.onlyReadsMemory()) {
5180 SDValue Tmp = getValue(I.getArgOperand(0));
5181 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5182 Tmp.getValueType(), Tmp));
5185 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5186 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5187 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5188 I.getType() == I.getArgOperand(0)->getType() &&
5189 I.onlyReadsMemory()) {
5190 SDValue Tmp = getValue(I.getArgOperand(0));
5191 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5192 Tmp.getValueType(), Tmp));
5195 } else if (Name == "memcmp") {
5196 if (visitMemCmpCall(I))
5204 Callee = getValue(I.getCalledValue());
5206 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5208 // Check if we can potentially perform a tail call. More detailed checking is
5209 // be done within LowerCallTo, after more information about the call is known.
5210 LowerCallTo(&I, Callee, I.isTailCall());
5215 /// AsmOperandInfo - This contains information for each constraint that we are
5217 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5218 public TargetLowering::AsmOperandInfo {
5220 /// CallOperand - If this is the result output operand or a clobber
5221 /// this is null, otherwise it is the incoming operand to the CallInst.
5222 /// This gets modified as the asm is processed.
5223 SDValue CallOperand;
5225 /// AssignedRegs - If this is a register or register class operand, this
5226 /// contains the set of register corresponding to the operand.
5227 RegsForValue AssignedRegs;
5229 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5230 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5233 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5234 /// busy in OutputRegs/InputRegs.
5235 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5236 std::set<unsigned> &OutputRegs,
5237 std::set<unsigned> &InputRegs,
5238 const TargetRegisterInfo &TRI) const {
5240 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5241 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5244 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5245 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5249 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5250 /// corresponds to. If there is no Value* for this operand, it returns
5252 EVT getCallOperandValEVT(LLVMContext &Context,
5253 const TargetLowering &TLI,
5254 const TargetData *TD) const {
5255 if (CallOperandVal == 0) return MVT::Other;
5257 if (isa<BasicBlock>(CallOperandVal))
5258 return TLI.getPointerTy();
5260 const llvm::Type *OpTy = CallOperandVal->getType();
5262 // If this is an indirect operand, the operand is a pointer to the
5265 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5267 report_fatal_error("Indirect operand for inline asm not a pointer!");
5268 OpTy = PtrTy->getElementType();
5271 // If OpTy is not a single value, it may be a struct/union that we
5272 // can tile with integers.
5273 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5274 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5283 OpTy = IntegerType::get(Context, BitSize);
5288 return TLI.getValueType(OpTy, true);
5292 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5294 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5295 const TargetRegisterInfo &TRI) {
5296 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5298 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5299 for (; *Aliases; ++Aliases)
5300 Regs.insert(*Aliases);
5304 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5306 } // end llvm namespace.
5308 /// isAllocatableRegister - If the specified register is safe to allocate,
5309 /// i.e. it isn't a stack pointer or some other special register, return the
5310 /// register class for the register. Otherwise, return null.
5311 static const TargetRegisterClass *
5312 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5313 const TargetLowering &TLI,
5314 const TargetRegisterInfo *TRI) {
5315 EVT FoundVT = MVT::Other;
5316 const TargetRegisterClass *FoundRC = 0;
5317 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5318 E = TRI->regclass_end(); RCI != E; ++RCI) {
5319 EVT ThisVT = MVT::Other;
5321 const TargetRegisterClass *RC = *RCI;
5322 // If none of the value types for this register class are valid, we
5323 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5324 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5326 if (TLI.isTypeLegal(*I)) {
5327 // If we have already found this register in a different register class,
5328 // choose the one with the largest VT specified. For example, on
5329 // PowerPC, we favor f64 register classes over f32.
5330 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5337 if (ThisVT == MVT::Other) continue;
5339 // NOTE: This isn't ideal. In particular, this might allocate the
5340 // frame pointer in functions that need it (due to them not being taken
5341 // out of allocation, because a variable sized allocation hasn't been seen
5342 // yet). This is a slight code pessimization, but should still work.
5343 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5344 E = RC->allocation_order_end(MF); I != E; ++I)
5346 // We found a matching register class. Keep looking at others in case
5347 // we find one with larger registers that this physreg is also in.
5356 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5357 /// specified operand. We prefer to assign virtual registers, to allow the
5358 /// register allocator to handle the assignment process. However, if the asm
5359 /// uses features that we can't model on machineinstrs, we have SDISel do the
5360 /// allocation. This produces generally horrible, but correct, code.
5362 /// OpInfo describes the operand.
5363 /// Input and OutputRegs are the set of already allocated physical registers.
5365 void SelectionDAGBuilder::
5366 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5367 std::set<unsigned> &OutputRegs,
5368 std::set<unsigned> &InputRegs) {
5369 LLVMContext &Context = FuncInfo.Fn->getContext();
5371 // Compute whether this value requires an input register, an output register,
5373 bool isOutReg = false;
5374 bool isInReg = false;
5375 switch (OpInfo.Type) {
5376 case InlineAsm::isOutput:
5379 // If there is an input constraint that matches this, we need to reserve
5380 // the input register so no other inputs allocate to it.
5381 isInReg = OpInfo.hasMatchingInput();
5383 case InlineAsm::isInput:
5387 case InlineAsm::isClobber:
5394 MachineFunction &MF = DAG.getMachineFunction();
5395 SmallVector<unsigned, 4> Regs;
5397 // If this is a constraint for a single physreg, or a constraint for a
5398 // register class, find it.
5399 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5400 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5401 OpInfo.ConstraintVT);
5403 unsigned NumRegs = 1;
5404 if (OpInfo.ConstraintVT != MVT::Other) {
5405 // If this is a FP input in an integer register (or visa versa) insert a bit
5406 // cast of the input value. More generally, handle any case where the input
5407 // value disagrees with the register class we plan to stick this in.
5408 if (OpInfo.Type == InlineAsm::isInput &&
5409 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5410 // Try to convert to the first EVT that the reg class contains. If the
5411 // types are identical size, use a bitcast to convert (e.g. two differing
5413 EVT RegVT = *PhysReg.second->vt_begin();
5414 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5415 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5416 RegVT, OpInfo.CallOperand);
5417 OpInfo.ConstraintVT = RegVT;
5418 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5419 // If the input is a FP value and we want it in FP registers, do a
5420 // bitcast to the corresponding integer type. This turns an f64 value
5421 // into i64, which can be passed with two i32 values on a 32-bit
5423 RegVT = EVT::getIntegerVT(Context,
5424 OpInfo.ConstraintVT.getSizeInBits());
5425 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5426 RegVT, OpInfo.CallOperand);
5427 OpInfo.ConstraintVT = RegVT;
5431 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5435 EVT ValueVT = OpInfo.ConstraintVT;
5437 // If this is a constraint for a specific physical register, like {r17},
5439 if (unsigned AssignedReg = PhysReg.first) {
5440 const TargetRegisterClass *RC = PhysReg.second;
5441 if (OpInfo.ConstraintVT == MVT::Other)
5442 ValueVT = *RC->vt_begin();
5444 // Get the actual register value type. This is important, because the user
5445 // may have asked for (e.g.) the AX register in i32 type. We need to
5446 // remember that AX is actually i16 to get the right extension.
5447 RegVT = *RC->vt_begin();
5449 // This is a explicit reference to a physical register.
5450 Regs.push_back(AssignedReg);
5452 // If this is an expanded reference, add the rest of the regs to Regs.
5454 TargetRegisterClass::iterator I = RC->begin();
5455 for (; *I != AssignedReg; ++I)
5456 assert(I != RC->end() && "Didn't find reg!");
5458 // Already added the first reg.
5460 for (; NumRegs; --NumRegs, ++I) {
5461 assert(I != RC->end() && "Ran out of registers to allocate!");
5466 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5467 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5468 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5472 // Otherwise, if this was a reference to an LLVM register class, create vregs
5473 // for this reference.
5474 if (const TargetRegisterClass *RC = PhysReg.second) {
5475 RegVT = *RC->vt_begin();
5476 if (OpInfo.ConstraintVT == MVT::Other)
5479 // Create the appropriate number of virtual registers.
5480 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5481 for (; NumRegs; --NumRegs)
5482 Regs.push_back(RegInfo.createVirtualRegister(RC));
5484 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5488 // This is a reference to a register class that doesn't directly correspond
5489 // to an LLVM register class. Allocate NumRegs consecutive, available,
5490 // registers from the class.
5491 std::vector<unsigned> RegClassRegs
5492 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5493 OpInfo.ConstraintVT);
5495 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5496 unsigned NumAllocated = 0;
5497 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5498 unsigned Reg = RegClassRegs[i];
5499 // See if this register is available.
5500 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5501 (isInReg && InputRegs.count(Reg))) { // Already used.
5502 // Make sure we find consecutive registers.
5507 // Check to see if this register is allocatable (i.e. don't give out the
5509 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5510 if (!RC) { // Couldn't allocate this register.
5511 // Reset NumAllocated to make sure we return consecutive registers.
5516 // Okay, this register is good, we can use it.
5519 // If we allocated enough consecutive registers, succeed.
5520 if (NumAllocated == NumRegs) {
5521 unsigned RegStart = (i-NumAllocated)+1;
5522 unsigned RegEnd = i+1;
5523 // Mark all of the allocated registers used.
5524 for (unsigned i = RegStart; i != RegEnd; ++i)
5525 Regs.push_back(RegClassRegs[i]);
5527 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5528 OpInfo.ConstraintVT);
5529 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5534 // Otherwise, we couldn't allocate enough registers for this.
5537 /// visitInlineAsm - Handle a call to an InlineAsm object.
5539 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5540 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5542 /// ConstraintOperands - Information about all of the constraints.
5543 SDISelAsmOperandInfoVector ConstraintOperands;
5545 std::set<unsigned> OutputRegs, InputRegs;
5547 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5548 bool hasMemory = false;
5550 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5551 unsigned ResNo = 0; // ResNo - The result number of the next output.
5552 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5553 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5554 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5556 EVT OpVT = MVT::Other;
5558 // Compute the value type for each operand.
5559 switch (OpInfo.Type) {
5560 case InlineAsm::isOutput:
5561 // Indirect outputs just consume an argument.
5562 if (OpInfo.isIndirect) {
5563 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5567 // The return value of the call is this value. As such, there is no
5568 // corresponding argument.
5569 assert(!CS.getType()->isVoidTy() &&
5571 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5572 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5574 assert(ResNo == 0 && "Asm only has one result!");
5575 OpVT = TLI.getValueType(CS.getType());
5579 case InlineAsm::isInput:
5580 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5582 case InlineAsm::isClobber:
5587 // If this is an input or an indirect output, process the call argument.
5588 // BasicBlocks are labels, currently appearing only in asm's.
5589 if (OpInfo.CallOperandVal) {
5590 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5591 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5593 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5596 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5599 OpInfo.ConstraintVT = OpVT;
5601 // Indirect operand accesses access memory.
5602 if (OpInfo.isIndirect)
5605 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5606 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5607 if (CType == TargetLowering::C_Memory) {
5615 SDValue Chain, Flag;
5617 // We won't need to flush pending loads if this asm doesn't touch
5618 // memory and is nonvolatile.
5619 if (hasMemory || IA->hasSideEffects())
5622 Chain = DAG.getRoot();
5624 // Second pass over the constraints: compute which constraint option to use
5625 // and assign registers to constraints that want a specific physreg.
5626 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5627 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5629 // If this is an output operand with a matching input operand, look up the
5630 // matching input. If their types mismatch, e.g. one is an integer, the
5631 // other is floating point, or their sizes are different, flag it as an
5633 if (OpInfo.hasMatchingInput()) {
5634 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5636 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5637 if ((OpInfo.ConstraintVT.isInteger() !=
5638 Input.ConstraintVT.isInteger()) ||
5639 (OpInfo.ConstraintVT.getSizeInBits() !=
5640 Input.ConstraintVT.getSizeInBits())) {
5641 report_fatal_error("Unsupported asm: input constraint"
5642 " with a matching output constraint of"
5643 " incompatible type!");
5645 Input.ConstraintVT = OpInfo.ConstraintVT;
5649 // Compute the constraint code and ConstraintType to use.
5650 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5652 // If this is a memory input, and if the operand is not indirect, do what we
5653 // need to to provide an address for the memory input.
5654 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5655 !OpInfo.isIndirect) {
5656 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5657 "Can only indirectify direct input operands!");
5659 // Memory operands really want the address of the value. If we don't have
5660 // an indirect input, put it in the constpool if we can, otherwise spill
5661 // it to a stack slot.
5663 // If the operand is a float, integer, or vector constant, spill to a
5664 // constant pool entry to get its address.
5665 const Value *OpVal = OpInfo.CallOperandVal;
5666 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5667 isa<ConstantVector>(OpVal)) {
5668 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5669 TLI.getPointerTy());
5671 // Otherwise, create a stack slot and emit a store to it before the
5673 const Type *Ty = OpVal->getType();
5674 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5675 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5676 MachineFunction &MF = DAG.getMachineFunction();
5677 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5678 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5679 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5680 OpInfo.CallOperand, StackSlot,
5681 MachinePointerInfo::getFixedStack(SSFI),
5683 OpInfo.CallOperand = StackSlot;
5686 // There is no longer a Value* corresponding to this operand.
5687 OpInfo.CallOperandVal = 0;
5689 // It is now an indirect operand.
5690 OpInfo.isIndirect = true;
5693 // If this constraint is for a specific register, allocate it before
5695 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5696 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5699 // Second pass - Loop over all of the operands, assigning virtual or physregs
5700 // to register class operands.
5701 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5702 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5704 // C_Register operands have already been allocated, Other/Memory don't need
5706 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5707 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5710 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5711 std::vector<SDValue> AsmNodeOperands;
5712 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5713 AsmNodeOperands.push_back(
5714 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5715 TLI.getPointerTy()));
5717 // If we have a !srcloc metadata node associated with it, we want to attach
5718 // this to the ultimately generated inline asm machineinstr. To do this, we
5719 // pass in the third operand as this (potentially null) inline asm MDNode.
5720 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5721 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5723 // Remember the HasSideEffect and AlignStack bits as operand 3.
5724 unsigned ExtraInfo = 0;
5725 if (IA->hasSideEffects())
5726 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5727 if (IA->isAlignStack())
5728 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5729 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5730 TLI.getPointerTy()));
5732 // Loop over all of the inputs, copying the operand values into the
5733 // appropriate registers and processing the output regs.
5734 RegsForValue RetValRegs;
5736 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5737 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5739 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5740 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5742 switch (OpInfo.Type) {
5743 case InlineAsm::isOutput: {
5744 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5745 OpInfo.ConstraintType != TargetLowering::C_Register) {
5746 // Memory output, or 'other' output (e.g. 'X' constraint).
5747 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5749 // Add information to the INLINEASM node to know about this output.
5750 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5751 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5752 TLI.getPointerTy()));
5753 AsmNodeOperands.push_back(OpInfo.CallOperand);
5757 // Otherwise, this is a register or register class output.
5759 // Copy the output from the appropriate register. Find a register that
5761 if (OpInfo.AssignedRegs.Regs.empty())
5762 report_fatal_error("Couldn't allocate output reg for constraint '" +
5763 Twine(OpInfo.ConstraintCode) + "'!");
5765 // If this is an indirect operand, store through the pointer after the
5767 if (OpInfo.isIndirect) {
5768 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5769 OpInfo.CallOperandVal));
5771 // This is the result value of the call.
5772 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5773 // Concatenate this output onto the outputs list.
5774 RetValRegs.append(OpInfo.AssignedRegs);
5777 // Add information to the INLINEASM node to know that this register is
5779 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5780 InlineAsm::Kind_RegDefEarlyClobber :
5781 InlineAsm::Kind_RegDef,
5788 case InlineAsm::isInput: {
5789 SDValue InOperandVal = OpInfo.CallOperand;
5791 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5792 // If this is required to match an output register we have already set,
5793 // just use its register.
5794 unsigned OperandNo = OpInfo.getMatchedOperand();
5796 // Scan until we find the definition we already emitted of this operand.
5797 // When we find it, create a RegsForValue operand.
5798 unsigned CurOp = InlineAsm::Op_FirstOperand;
5799 for (; OperandNo; --OperandNo) {
5800 // Advance to the next operand.
5802 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5803 assert((InlineAsm::isRegDefKind(OpFlag) ||
5804 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5805 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5806 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5810 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5811 if (InlineAsm::isRegDefKind(OpFlag) ||
5812 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5813 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5814 if (OpInfo.isIndirect) {
5815 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5816 LLVMContext &Ctx = *DAG.getContext();
5817 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5818 " don't know how to handle tied "
5819 "indirect register inputs");
5822 RegsForValue MatchedRegs;
5823 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5824 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5825 MatchedRegs.RegVTs.push_back(RegVT);
5826 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5827 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5829 MatchedRegs.Regs.push_back
5830 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5832 // Use the produced MatchedRegs object to
5833 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5835 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5836 true, OpInfo.getMatchedOperand(),
5837 DAG, AsmNodeOperands);
5841 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5842 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5843 "Unexpected number of operands");
5844 // Add information to the INLINEASM node to know about this input.
5845 // See InlineAsm.h isUseOperandTiedToDef.
5846 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5847 OpInfo.getMatchedOperand());
5848 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5849 TLI.getPointerTy()));
5850 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5854 // Treat indirect 'X' constraint as memory.
5855 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5857 OpInfo.ConstraintType = TargetLowering::C_Memory;
5859 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5860 std::vector<SDValue> Ops;
5861 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5864 report_fatal_error("Invalid operand for inline asm constraint '" +
5865 Twine(OpInfo.ConstraintCode) + "'!");
5867 // Add information to the INLINEASM node to know about this input.
5868 unsigned ResOpType =
5869 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5870 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5871 TLI.getPointerTy()));
5872 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5876 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5877 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5878 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5879 "Memory operands expect pointer values");
5881 // Add information to the INLINEASM node to know about this input.
5882 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5883 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5884 TLI.getPointerTy()));
5885 AsmNodeOperands.push_back(InOperandVal);
5889 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5890 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5891 "Unknown constraint type!");
5892 assert(!OpInfo.isIndirect &&
5893 "Don't know how to handle indirect register inputs yet!");
5895 // Copy the input into the appropriate registers.
5896 if (OpInfo.AssignedRegs.Regs.empty() ||
5897 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5898 report_fatal_error("Couldn't allocate input reg for constraint '" +
5899 Twine(OpInfo.ConstraintCode) + "'!");
5901 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5904 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5905 DAG, AsmNodeOperands);
5908 case InlineAsm::isClobber: {
5909 // Add the clobbered value to the operand list, so that the register
5910 // allocator is aware that the physreg got clobbered.
5911 if (!OpInfo.AssignedRegs.Regs.empty())
5912 OpInfo.AssignedRegs.AddInlineAsmOperands(
5913 InlineAsm::Kind_RegDefEarlyClobber,
5921 // Finish up input operands. Set the input chain and add the flag last.
5922 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5923 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5925 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5926 DAG.getVTList(MVT::Other, MVT::Glue),
5927 &AsmNodeOperands[0], AsmNodeOperands.size());
5928 Flag = Chain.getValue(1);
5930 // If this asm returns a register value, copy the result from that register
5931 // and set it as the value of the call.
5932 if (!RetValRegs.Regs.empty()) {
5933 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5936 // FIXME: Why don't we do this for inline asms with MRVs?
5937 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5938 EVT ResultType = TLI.getValueType(CS.getType());
5940 // If any of the results of the inline asm is a vector, it may have the
5941 // wrong width/num elts. This can happen for register classes that can
5942 // contain multiple different value types. The preg or vreg allocated may
5943 // not have the same VT as was expected. Convert it to the right type
5944 // with bit_convert.
5945 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5946 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5949 } else if (ResultType != Val.getValueType() &&
5950 ResultType.isInteger() && Val.getValueType().isInteger()) {
5951 // If a result value was tied to an input value, the computed result may
5952 // have a wider width than the expected result. Extract the relevant
5954 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5957 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5960 setValue(CS.getInstruction(), Val);
5961 // Don't need to use this as a chain in this case.
5962 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5966 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5968 // Process indirect outputs, first output all of the flagged copies out of
5970 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5971 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5972 const Value *Ptr = IndirectStoresToEmit[i].second;
5973 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5975 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5978 // Emit the non-flagged stores from the physregs.
5979 SmallVector<SDValue, 8> OutChains;
5980 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5981 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5982 StoresToEmit[i].first,
5983 getValue(StoresToEmit[i].second),
5984 MachinePointerInfo(StoresToEmit[i].second),
5986 OutChains.push_back(Val);
5989 if (!OutChains.empty())
5990 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5991 &OutChains[0], OutChains.size());
5996 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5997 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5998 MVT::Other, getRoot(),
5999 getValue(I.getArgOperand(0)),
6000 DAG.getSrcValue(I.getArgOperand(0))));
6003 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6004 const TargetData &TD = *TLI.getTargetData();
6005 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6006 getRoot(), getValue(I.getOperand(0)),
6007 DAG.getSrcValue(I.getOperand(0)),
6008 TD.getABITypeAlignment(I.getType()));
6010 DAG.setRoot(V.getValue(1));
6013 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6014 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6015 MVT::Other, getRoot(),
6016 getValue(I.getArgOperand(0)),
6017 DAG.getSrcValue(I.getArgOperand(0))));
6020 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6021 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6022 MVT::Other, getRoot(),
6023 getValue(I.getArgOperand(0)),
6024 getValue(I.getArgOperand(1)),
6025 DAG.getSrcValue(I.getArgOperand(0)),
6026 DAG.getSrcValue(I.getArgOperand(1))));
6029 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6030 /// implementation, which just calls LowerCall.
6031 /// FIXME: When all targets are
6032 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6033 std::pair<SDValue, SDValue>
6034 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6035 bool RetSExt, bool RetZExt, bool isVarArg,
6036 bool isInreg, unsigned NumFixedArgs,
6037 CallingConv::ID CallConv, bool isTailCall,
6038 bool isReturnValueUsed,
6040 ArgListTy &Args, SelectionDAG &DAG,
6041 DebugLoc dl) const {
6042 // Handle all of the outgoing arguments.
6043 SmallVector<ISD::OutputArg, 32> Outs;
6044 SmallVector<SDValue, 32> OutVals;
6045 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6046 SmallVector<EVT, 4> ValueVTs;
6047 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6048 for (unsigned Value = 0, NumValues = ValueVTs.size();
6049 Value != NumValues; ++Value) {
6050 EVT VT = ValueVTs[Value];
6051 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6052 SDValue Op = SDValue(Args[i].Node.getNode(),
6053 Args[i].Node.getResNo() + Value);
6054 ISD::ArgFlagsTy Flags;
6055 unsigned OriginalAlignment =
6056 getTargetData()->getABITypeAlignment(ArgTy);
6062 if (Args[i].isInReg)
6066 if (Args[i].isByVal) {
6068 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6069 const Type *ElementTy = Ty->getElementType();
6070 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6071 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6072 // For ByVal, alignment should come from FE. BE will guess if this
6073 // info is not there but there are cases it cannot get right.
6074 if (Args[i].Alignment)
6075 FrameAlign = Args[i].Alignment;
6076 Flags.setByValAlign(FrameAlign);
6077 Flags.setByValSize(FrameSize);
6081 Flags.setOrigAlign(OriginalAlignment);
6083 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6084 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6085 SmallVector<SDValue, 4> Parts(NumParts);
6086 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6089 ExtendKind = ISD::SIGN_EXTEND;
6090 else if (Args[i].isZExt)
6091 ExtendKind = ISD::ZERO_EXTEND;
6093 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6094 PartVT, ExtendKind);
6096 for (unsigned j = 0; j != NumParts; ++j) {
6097 // if it isn't first piece, alignment must be 1
6098 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6100 if (NumParts > 1 && j == 0)
6101 MyFlags.Flags.setSplit();
6103 MyFlags.Flags.setOrigAlign(1);
6105 Outs.push_back(MyFlags);
6106 OutVals.push_back(Parts[j]);
6111 // Handle the incoming return values from the call.
6112 SmallVector<ISD::InputArg, 32> Ins;
6113 SmallVector<EVT, 4> RetTys;
6114 ComputeValueVTs(*this, RetTy, RetTys);
6115 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6117 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6118 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6119 for (unsigned i = 0; i != NumRegs; ++i) {
6120 ISD::InputArg MyFlags;
6121 MyFlags.VT = RegisterVT.getSimpleVT();
6122 MyFlags.Used = isReturnValueUsed;
6124 MyFlags.Flags.setSExt();
6126 MyFlags.Flags.setZExt();
6128 MyFlags.Flags.setInReg();
6129 Ins.push_back(MyFlags);
6133 SmallVector<SDValue, 4> InVals;
6134 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6135 Outs, OutVals, Ins, dl, DAG, InVals);
6137 // Verify that the target's LowerCall behaved as expected.
6138 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6139 "LowerCall didn't return a valid chain!");
6140 assert((!isTailCall || InVals.empty()) &&
6141 "LowerCall emitted a return value for a tail call!");
6142 assert((isTailCall || InVals.size() == Ins.size()) &&
6143 "LowerCall didn't emit the correct number of values!");
6145 // For a tail call, the return value is merely live-out and there aren't
6146 // any nodes in the DAG representing it. Return a special value to
6147 // indicate that a tail call has been emitted and no more Instructions
6148 // should be processed in the current block.
6151 return std::make_pair(SDValue(), SDValue());
6154 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6155 assert(InVals[i].getNode() &&
6156 "LowerCall emitted a null value!");
6157 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6158 "LowerCall emitted a value with the wrong type!");
6161 // Collect the legal value parts into potentially illegal values
6162 // that correspond to the original function's return values.
6163 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6165 AssertOp = ISD::AssertSext;
6167 AssertOp = ISD::AssertZext;
6168 SmallVector<SDValue, 4> ReturnValues;
6169 unsigned CurReg = 0;
6170 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6172 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6173 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6175 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6176 NumRegs, RegisterVT, VT,
6181 // For a function returning void, there is no return value. We can't create
6182 // such a node, so we just return a null return value in that case. In
6183 // that case, nothing will actualy look at the value.
6184 if (ReturnValues.empty())
6185 return std::make_pair(SDValue(), Chain);
6187 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6188 DAG.getVTList(&RetTys[0], RetTys.size()),
6189 &ReturnValues[0], ReturnValues.size());
6190 return std::make_pair(Res, Chain);
6193 void TargetLowering::LowerOperationWrapper(SDNode *N,
6194 SmallVectorImpl<SDValue> &Results,
6195 SelectionDAG &DAG) const {
6196 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6198 Results.push_back(Res);
6201 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6202 llvm_unreachable("LowerOperation not implemented for this target!");
6207 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6208 SDValue Op = getNonRegisterValue(V);
6209 assert((Op.getOpcode() != ISD::CopyFromReg ||
6210 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6211 "Copy from a reg to the same reg!");
6212 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6214 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6215 SDValue Chain = DAG.getEntryNode();
6216 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6217 PendingExports.push_back(Chain);
6220 #include "llvm/CodeGen/SelectionDAGISel.h"
6222 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6223 // If this is the entry block, emit arguments.
6224 const Function &F = *LLVMBB->getParent();
6225 SelectionDAG &DAG = SDB->DAG;
6226 DebugLoc dl = SDB->getCurDebugLoc();
6227 const TargetData *TD = TLI.getTargetData();
6228 SmallVector<ISD::InputArg, 16> Ins;
6230 // Check whether the function can return without sret-demotion.
6231 SmallVector<ISD::OutputArg, 4> Outs;
6232 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6235 if (!FuncInfo->CanLowerReturn) {
6236 // Put in an sret pointer parameter before all the other parameters.
6237 SmallVector<EVT, 1> ValueVTs;
6238 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6240 // NOTE: Assuming that a pointer will never break down to more than one VT
6242 ISD::ArgFlagsTy Flags;
6244 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6245 ISD::InputArg RetArg(Flags, RegisterVT, true);
6246 Ins.push_back(RetArg);
6249 // Set up the incoming argument description vector.
6251 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6252 I != E; ++I, ++Idx) {
6253 SmallVector<EVT, 4> ValueVTs;
6254 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6255 bool isArgValueUsed = !I->use_empty();
6256 for (unsigned Value = 0, NumValues = ValueVTs.size();
6257 Value != NumValues; ++Value) {
6258 EVT VT = ValueVTs[Value];
6259 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6260 ISD::ArgFlagsTy Flags;
6261 unsigned OriginalAlignment =
6262 TD->getABITypeAlignment(ArgTy);
6264 if (F.paramHasAttr(Idx, Attribute::ZExt))
6266 if (F.paramHasAttr(Idx, Attribute::SExt))
6268 if (F.paramHasAttr(Idx, Attribute::InReg))
6270 if (F.paramHasAttr(Idx, Attribute::StructRet))
6272 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6274 const PointerType *Ty = cast<PointerType>(I->getType());
6275 const Type *ElementTy = Ty->getElementType();
6276 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6277 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6278 // For ByVal, alignment should be passed from FE. BE will guess if
6279 // this info is not there but there are cases it cannot get right.
6280 if (F.getParamAlignment(Idx))
6281 FrameAlign = F.getParamAlignment(Idx);
6282 Flags.setByValAlign(FrameAlign);
6283 Flags.setByValSize(FrameSize);
6285 if (F.paramHasAttr(Idx, Attribute::Nest))
6287 Flags.setOrigAlign(OriginalAlignment);
6289 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6290 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6291 for (unsigned i = 0; i != NumRegs; ++i) {
6292 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6293 if (NumRegs > 1 && i == 0)
6294 MyFlags.Flags.setSplit();
6295 // if it isn't first piece, alignment must be 1
6297 MyFlags.Flags.setOrigAlign(1);
6298 Ins.push_back(MyFlags);
6303 // Call the target to set up the argument values.
6304 SmallVector<SDValue, 8> InVals;
6305 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6309 // Verify that the target's LowerFormalArguments behaved as expected.
6310 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6311 "LowerFormalArguments didn't return a valid chain!");
6312 assert(InVals.size() == Ins.size() &&
6313 "LowerFormalArguments didn't emit the correct number of values!");
6315 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6316 assert(InVals[i].getNode() &&
6317 "LowerFormalArguments emitted a null value!");
6318 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6319 "LowerFormalArguments emitted a value with the wrong type!");
6323 // Update the DAG with the new chain value resulting from argument lowering.
6324 DAG.setRoot(NewRoot);
6326 // Set up the argument values.
6329 if (!FuncInfo->CanLowerReturn) {
6330 // Create a virtual register for the sret pointer, and put in a copy
6331 // from the sret argument into it.
6332 SmallVector<EVT, 1> ValueVTs;
6333 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6334 EVT VT = ValueVTs[0];
6335 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6336 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6337 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6338 RegVT, VT, AssertOp);
6340 MachineFunction& MF = SDB->DAG.getMachineFunction();
6341 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6342 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6343 FuncInfo->DemoteRegister = SRetReg;
6344 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6346 DAG.setRoot(NewRoot);
6348 // i indexes lowered arguments. Bump it past the hidden sret argument.
6349 // Idx indexes LLVM arguments. Don't touch it.
6353 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6355 SmallVector<SDValue, 4> ArgValues;
6356 SmallVector<EVT, 4> ValueVTs;
6357 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6358 unsigned NumValues = ValueVTs.size();
6360 // If this argument is unused then remember its value. It is used to generate
6361 // debugging information.
6362 if (I->use_empty() && NumValues)
6363 SDB->setUnusedArgValue(I, InVals[i]);
6365 for (unsigned Value = 0; Value != NumValues; ++Value) {
6366 EVT VT = ValueVTs[Value];
6367 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6368 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6370 if (!I->use_empty()) {
6371 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6372 if (F.paramHasAttr(Idx, Attribute::SExt))
6373 AssertOp = ISD::AssertSext;
6374 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6375 AssertOp = ISD::AssertZext;
6377 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6378 NumParts, PartVT, VT,
6385 // Note down frame index for byval arguments.
6386 if (I->hasByValAttr() && !ArgValues.empty())
6387 if (FrameIndexSDNode *FI =
6388 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6389 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6391 if (!I->use_empty()) {
6393 if (!ArgValues.empty())
6394 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6395 SDB->getCurDebugLoc());
6396 SDB->setValue(I, Res);
6398 // If this argument is live outside of the entry block, insert a copy from
6399 // whereever we got it to the vreg that other BB's will reference it as.
6400 SDB->CopyToExportRegsIfNeeded(I);
6404 assert(i == InVals.size() && "Argument register count mismatch!");
6406 // Finally, if the target has anything special to do, allow it to do so.
6407 // FIXME: this should insert code into the DAG!
6408 EmitFunctionEntryCode();
6411 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6412 /// ensure constants are generated when needed. Remember the virtual registers
6413 /// that need to be added to the Machine PHI nodes as input. We cannot just
6414 /// directly add them, because expansion might result in multiple MBB's for one
6415 /// BB. As such, the start of the BB might correspond to a different MBB than
6419 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6420 const TerminatorInst *TI = LLVMBB->getTerminator();
6422 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6424 // Check successor nodes' PHI nodes that expect a constant to be available
6426 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6427 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6428 if (!isa<PHINode>(SuccBB->begin())) continue;
6429 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6431 // If this terminator has multiple identical successors (common for
6432 // switches), only handle each succ once.
6433 if (!SuccsHandled.insert(SuccMBB)) continue;
6435 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6437 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6438 // nodes and Machine PHI nodes, but the incoming operands have not been
6440 for (BasicBlock::const_iterator I = SuccBB->begin();
6441 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6442 // Ignore dead phi's.
6443 if (PN->use_empty()) continue;
6446 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6448 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6449 unsigned &RegOut = ConstantsOut[C];
6451 RegOut = FuncInfo.CreateRegs(C->getType());
6452 CopyValueToVirtualRegister(C, RegOut);
6456 DenseMap<const Value *, unsigned>::iterator I =
6457 FuncInfo.ValueMap.find(PHIOp);
6458 if (I != FuncInfo.ValueMap.end())
6461 assert(isa<AllocaInst>(PHIOp) &&
6462 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6463 "Didn't codegen value into a register!??");
6464 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6465 CopyValueToVirtualRegister(PHIOp, Reg);
6469 // Remember that this register needs to added to the machine PHI node as
6470 // the input for this MBB.
6471 SmallVector<EVT, 4> ValueVTs;
6472 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6473 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6474 EVT VT = ValueVTs[vti];
6475 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6476 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6477 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6478 Reg += NumRegisters;
6482 ConstantsOut.clear();