1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/DebugInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetIntrinsicInfo.h"
58 #include "llvm/Target/TargetLibraryInfo.h"
59 #include "llvm/Target/TargetLowering.h"
60 #include "llvm/Target/TargetOptions.h"
61 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 /// LimitFloatPrecision - Generate low-precision inline sequences for
66 /// some float libcalls (6, 8 or 12 bits).
67 static unsigned LimitFloatPrecision;
69 static cl::opt<unsigned, true>
70 LimitFPPrecision("limit-float-precision",
71 cl::desc("Generate low-precision inline sequences "
72 "for some float libcalls"),
73 cl::location(LimitFloatPrecision),
76 // Limit the width of DAG chains. This is important in general to prevent
77 // prevent DAG-based analysis from blowing up. For example, alias analysis and
78 // load clustering may not complete in reasonable time. It is difficult to
79 // recognize and avoid this situation within each individual analysis, and
80 // future analyses are likely to have the same behavior. Limiting DAG width is
81 // the safe approach, and will be especially important with global DAGs.
83 // MaxParallelChains default is arbitrarily high to avoid affecting
84 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
85 // sequence over this should have been converted to llvm.memcpy by the
86 // frontend. It easy to induce this behavior with .ll code such as:
87 // %buffer = alloca [4096 x i8]
88 // %data = load [4096 x i8]* %argPtr
89 // store [4096 x i8] %data, [4096 x i8]* %buffer
90 static const unsigned MaxParallelChains = 64;
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
93 const SDValue *Parts, unsigned NumParts,
94 MVT PartVT, EVT ValueVT, const Value *V);
96 /// getCopyFromParts - Create a value that contains the specified legal parts
97 /// combined into the value they represent. If the parts combine to a type
98 /// larger then ValueVT then AssertOp can be used to specify whether the extra
99 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
100 /// (ISD::AssertSext).
101 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts,
103 unsigned NumParts, MVT PartVT, EVT ValueVT,
105 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
106 if (ValueVT.isVector())
107 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
110 assert(NumParts > 0 && "No parts to assemble!");
111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
112 SDValue Val = Parts[0];
115 // Assemble the value from multiple parts.
116 if (ValueVT.isInteger()) {
117 unsigned PartBits = PartVT.getSizeInBits();
118 unsigned ValueBits = ValueVT.getSizeInBits();
120 // Assemble the power of 2 part.
121 unsigned RoundParts = NumParts & (NumParts - 1) ?
122 1 << Log2_32(NumParts) : NumParts;
123 unsigned RoundBits = PartBits * RoundParts;
124 EVT RoundVT = RoundBits == ValueBits ?
125 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
128 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
130 if (RoundParts > 2) {
131 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
133 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
134 RoundParts / 2, PartVT, HalfVT, V);
136 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
137 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
140 if (TLI.isBigEndian())
143 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
145 if (RoundParts < NumParts) {
146 // Assemble the trailing non-power-of-2 part.
147 unsigned OddParts = NumParts - RoundParts;
148 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
149 Hi = getCopyFromParts(DAG, DL,
150 Parts + RoundParts, OddParts, PartVT, OddVT, V);
152 // Combine the round and odd parts.
154 if (TLI.isBigEndian())
156 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
157 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
158 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
159 DAG.getConstant(Lo.getValueType().getSizeInBits(),
160 TLI.getPointerTy()));
161 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
162 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
164 } else if (PartVT.isFloatingPoint()) {
165 // FP split into multiple FP parts (for ppcf128)
166 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
171 if (TLI.isBigEndian())
173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
175 // FP split into integer parts (soft fp)
176 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
177 !PartVT.isVector() && "Unexpected split");
178 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
179 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
183 // There is now one part, held in Val. Correct it to match ValueVT.
184 EVT PartEVT = Val.getValueType();
186 if (PartEVT == ValueVT)
189 if (PartEVT.isInteger() && ValueVT.isInteger()) {
190 if (ValueVT.bitsLT(PartEVT)) {
191 // For a truncate, see if we have any information to
192 // indicate whether the truncated bits will always be
193 // zero or sign-extension.
194 if (AssertOp != ISD::DELETED_NODE)
195 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
196 DAG.getValueType(ValueVT));
197 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
199 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
202 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
203 // FP_ROUND's are always exact here.
204 if (ValueVT.bitsLT(Val.getValueType()))
205 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
206 DAG.getTargetConstant(1, TLI.getPointerTy()));
208 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
211 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
212 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
214 llvm_unreachable("Unknown mismatch!");
217 /// getCopyFromPartsVector - Create a value that contains the specified legal
218 /// parts combined into the value they represent. If the parts combine to a
219 /// type larger then ValueVT then AssertOp can be used to specify whether the
220 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
221 /// ValueVT (ISD::AssertSext).
222 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
223 const SDValue *Parts, unsigned NumParts,
224 MVT PartVT, EVT ValueVT, const Value *V) {
225 assert(ValueVT.isVector() && "Not a vector value");
226 assert(NumParts > 0 && "No parts to assemble!");
227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
228 SDValue Val = Parts[0];
230 // Handle a multi-element vector.
234 unsigned NumIntermediates;
236 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
237 NumIntermediates, RegisterVT);
238 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
239 NumParts = NumRegs; // Silence a compiler warning.
240 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
241 assert(RegisterVT == Parts[0].getSimpleValueType() &&
242 "Part type doesn't match part!");
244 // Assemble the parts into intermediate operands.
245 SmallVector<SDValue, 8> Ops(NumIntermediates);
246 if (NumIntermediates == NumParts) {
247 // If the register was not expanded, truncate or copy the value,
249 for (unsigned i = 0; i != NumParts; ++i)
250 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
251 PartVT, IntermediateVT, V);
252 } else if (NumParts > 0) {
253 // If the intermediate type was expanded, build the intermediate
254 // operands from the parts.
255 assert(NumParts % NumIntermediates == 0 &&
256 "Must expand into a divisible number of parts!");
257 unsigned Factor = NumParts / NumIntermediates;
258 for (unsigned i = 0; i != NumIntermediates; ++i)
259 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
260 PartVT, IntermediateVT, V);
263 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
264 // intermediate operands.
265 Val = DAG.getNode(IntermediateVT.isVector() ?
266 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
267 ValueVT, &Ops[0], NumIntermediates);
270 // There is now one part, held in Val. Correct it to match ValueVT.
271 EVT PartEVT = Val.getValueType();
273 if (PartEVT == ValueVT)
276 if (PartEVT.isVector()) {
277 // If the element type of the source/dest vectors are the same, but the
278 // parts vector has more elements than the value vector, then we have a
279 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
281 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
282 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
283 "Cannot narrow, it would be a lossy transformation");
284 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
285 DAG.getConstant(0, TLI.getVectorIdxTy()));
288 // Vector/Vector bitcast.
289 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
290 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
292 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
293 "Cannot handle this kind of promotion");
294 // Promoted vector extract
295 bool Smaller = ValueVT.bitsLE(PartEVT);
296 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
301 // Trivial bitcast if the types are the same size and the destination
302 // vector type is legal.
303 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
304 TLI.isTypeLegal(ValueVT))
305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
307 // Handle cases such as i8 -> <1 x i1>
308 if (ValueVT.getVectorNumElements() != 1) {
309 LLVMContext &Ctx = *DAG.getContext();
310 Twine ErrMsg("non-trivial scalar-to-vector conversion");
311 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
312 if (const CallInst *CI = dyn_cast<CallInst>(I))
313 if (isa<InlineAsm>(CI->getCalledValue()))
314 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
315 Ctx.emitError(I, ErrMsg);
317 Ctx.emitError(ErrMsg);
319 return DAG.getUNDEF(ValueVT);
322 if (ValueVT.getVectorNumElements() == 1 &&
323 ValueVT.getVectorElementType() != PartEVT) {
324 bool Smaller = ValueVT.bitsLE(PartEVT);
325 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
326 DL, ValueVT.getScalarType(), Val);
329 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
332 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
333 SDValue Val, SDValue *Parts, unsigned NumParts,
334 MVT PartVT, const Value *V);
336 /// getCopyToParts - Create a series of nodes that contain the specified value
337 /// split into legal parts. If the parts contain more bits than Val, then, for
338 /// integers, ExtendKind can be used to specify how to generate the extra bits.
339 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
340 SDValue Val, SDValue *Parts, unsigned NumParts,
341 MVT PartVT, const Value *V,
342 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
343 EVT ValueVT = Val.getValueType();
345 // Handle the vector case separately.
346 if (ValueVT.isVector())
347 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
350 unsigned PartBits = PartVT.getSizeInBits();
351 unsigned OrigNumParts = NumParts;
352 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
357 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
358 EVT PartEVT = PartVT;
359 if (PartEVT == ValueVT) {
360 assert(NumParts == 1 && "No-op copy with multiple parts!");
365 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
366 // If the parts cover more bits than the value has, promote the value.
367 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
368 assert(NumParts == 1 && "Do not know what to promote to!");
369 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
371 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
372 ValueVT.isInteger() &&
373 "Unknown mismatch!");
374 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
375 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
376 if (PartVT == MVT::x86mmx)
377 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 } else if (PartBits == ValueVT.getSizeInBits()) {
380 // Different types of the same size.
381 assert(NumParts == 1 && PartEVT != ValueVT);
382 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
383 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
384 // If the parts cover less bits than value has, truncate the value.
385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
386 ValueVT.isInteger() &&
387 "Unknown mismatch!");
388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
389 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
390 if (PartVT == MVT::x86mmx)
391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 // The value may have changed - recompute ValueVT.
395 ValueVT = Val.getValueType();
396 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
397 "Failed to tile the value with PartVT!");
400 if (PartEVT != ValueVT) {
401 LLVMContext &Ctx = *DAG.getContext();
402 Twine ErrMsg("scalar-to-vector conversion failed");
403 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
404 if (const CallInst *CI = dyn_cast<CallInst>(I))
405 if (isa<InlineAsm>(CI->getCalledValue()))
406 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
407 Ctx.emitError(I, ErrMsg);
409 Ctx.emitError(ErrMsg);
417 // Expand the value into multiple parts.
418 if (NumParts & (NumParts - 1)) {
419 // The number of parts is not a power of 2. Split off and copy the tail.
420 assert(PartVT.isInteger() && ValueVT.isInteger() &&
421 "Do not know what to expand to!");
422 unsigned RoundParts = 1 << Log2_32(NumParts);
423 unsigned RoundBits = RoundParts * PartBits;
424 unsigned OddParts = NumParts - RoundParts;
425 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
426 DAG.getIntPtrConstant(RoundBits));
427 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
429 if (TLI.isBigEndian())
430 // The odd parts were reversed by getCopyToParts - unreverse them.
431 std::reverse(Parts + RoundParts, Parts + NumParts);
433 NumParts = RoundParts;
434 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
435 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
438 // The number of parts is a power of 2. Repeatedly bisect the value using
440 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
441 EVT::getIntegerVT(*DAG.getContext(),
442 ValueVT.getSizeInBits()),
445 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
446 for (unsigned i = 0; i < NumParts; i += StepSize) {
447 unsigned ThisBits = StepSize * PartBits / 2;
448 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
449 SDValue &Part0 = Parts[i];
450 SDValue &Part1 = Parts[i+StepSize/2];
452 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(1));
454 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(0));
457 if (ThisBits == PartBits && ThisVT != PartVT) {
458 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
459 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
464 if (TLI.isBigEndian())
465 std::reverse(Parts, Parts + OrigNumParts);
469 /// getCopyToPartsVector - Create a series of nodes that contain the specified
470 /// value split into legal parts.
471 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
472 SDValue Val, SDValue *Parts, unsigned NumParts,
473 MVT PartVT, const Value *V) {
474 EVT ValueVT = Val.getValueType();
475 assert(ValueVT.isVector() && "Not a vector");
476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
479 EVT PartEVT = PartVT;
480 if (PartEVT == ValueVT) {
482 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
483 // Bitconvert vector->vector case.
484 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
485 } else if (PartVT.isVector() &&
486 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
487 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
488 EVT ElementVT = PartVT.getVectorElementType();
489 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
491 SmallVector<SDValue, 16> Ops;
492 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
493 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
494 ElementVT, Val, DAG.getConstant(i,
495 TLI.getVectorIdxTy())));
497 for (unsigned i = ValueVT.getVectorNumElements(),
498 e = PartVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getUNDEF(ElementVT));
501 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
503 // FIXME: Use CONCAT for 2x -> 4x.
505 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
506 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
507 } else if (PartVT.isVector() &&
508 PartEVT.getVectorElementType().bitsGE(
509 ValueVT.getVectorElementType()) &&
510 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
512 // Promoted vector extract
513 bool Smaller = PartEVT.bitsLE(ValueVT);
514 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
517 // Vector -> scalar conversion.
518 assert(ValueVT.getVectorNumElements() == 1 &&
519 "Only trivial vector-to-scalar conversions should get here!");
520 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
521 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
523 bool Smaller = ValueVT.bitsLE(PartVT);
524 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
532 // Handle a multi-element vector.
535 unsigned NumIntermediates;
536 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
538 NumIntermediates, RegisterVT);
539 unsigned NumElements = ValueVT.getVectorNumElements();
541 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
542 NumParts = NumRegs; // Silence a compiler warning.
543 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
545 // Split the vector into intermediate operands.
546 SmallVector<SDValue, 8> Ops(NumIntermediates);
547 for (unsigned i = 0; i != NumIntermediates; ++i) {
548 if (IntermediateVT.isVector())
549 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
551 DAG.getConstant(i * (NumElements / NumIntermediates),
552 TLI.getVectorIdxTy()));
554 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
556 DAG.getConstant(i, TLI.getVectorIdxTy()));
559 // Split the intermediate operands into legal parts.
560 if (NumParts == NumIntermediates) {
561 // If the register was not expanded, promote or copy the value,
563 for (unsigned i = 0; i != NumParts; ++i)
564 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
565 } else if (NumParts > 0) {
566 // If the intermediate type was expanded, split each the value into
568 assert(NumParts % NumIntermediates == 0 &&
569 "Must expand into a divisible number of parts!");
570 unsigned Factor = NumParts / NumIntermediates;
571 for (unsigned i = 0; i != NumIntermediates; ++i)
572 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
577 /// RegsForValue - This struct represents the registers (physical or virtual)
578 /// that a particular set of values is assigned, and the type information
579 /// about the value. The most common situation is to represent one value at a
580 /// time, but struct or array values are handled element-wise as multiple
581 /// values. The splitting of aggregates is performed recursively, so that we
582 /// never have aggregate-typed registers. The values at this point do not
583 /// necessarily have legal types, so each value may require one or more
584 /// registers of some legal type.
586 struct RegsForValue {
587 /// ValueVTs - The value types of the values, which may not be legal, and
588 /// may need be promoted or synthesized from one or more registers.
590 SmallVector<EVT, 4> ValueVTs;
592 /// RegVTs - The value types of the registers. This is the same size as
593 /// ValueVTs and it records, for each value, what the type of the assigned
594 /// register or registers are. (Individual values are never synthesized
595 /// from more than one type of register.)
597 /// With virtual registers, the contents of RegVTs is redundant with TLI's
598 /// getRegisterType member function, however when with physical registers
599 /// it is necessary to have a separate record of the types.
601 SmallVector<MVT, 4> RegVTs;
603 /// Regs - This list holds the registers assigned to the values.
604 /// Each legal or promoted value requires one register, and each
605 /// expanded value requires multiple registers.
607 SmallVector<unsigned, 4> Regs;
611 RegsForValue(const SmallVector<unsigned, 4> ®s,
612 MVT regvt, EVT valuevt)
613 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
615 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
616 unsigned Reg, Type *Ty) {
617 ComputeValueVTs(tli, Ty, ValueVTs);
619 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
622 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
623 for (unsigned i = 0; i != NumRegs; ++i)
624 Regs.push_back(Reg + i);
625 RegVTs.push_back(RegisterVT);
630 /// areValueTypesLegal - Return true if types of all the values are legal.
631 bool areValueTypesLegal(const TargetLowering &TLI) {
632 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
633 MVT RegisterVT = RegVTs[Value];
634 if (!TLI.isTypeLegal(RegisterVT))
640 /// append - Add the specified values to this one.
641 void append(const RegsForValue &RHS) {
642 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
643 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
644 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
647 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
648 /// this value and returns the result as a ValueVTs value. This uses
649 /// Chain/Flag as the input and updates them for the output Chain/Flag.
650 /// If the Flag pointer is NULL, no flag is used.
651 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
653 SDValue &Chain, SDValue *Flag,
654 const Value *V = 0) const;
656 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
657 /// specified value into the registers specified by this object. This uses
658 /// Chain/Flag as the input and updates them for the output Chain/Flag.
659 /// If the Flag pointer is NULL, no flag is used.
660 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
661 SDValue &Chain, SDValue *Flag, const Value *V) const;
663 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
664 /// operand list. This adds the code marker, matching input operand index
665 /// (if applicable), and includes the number of values added into it.
666 void AddInlineAsmOperands(unsigned Kind,
667 bool HasMatching, unsigned MatchingIdx,
669 std::vector<SDValue> &Ops) const;
673 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
674 /// this value and returns the result as a ValueVT value. This uses
675 /// Chain/Flag as the input and updates them for the output Chain/Flag.
676 /// If the Flag pointer is NULL, no flag is used.
677 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
678 FunctionLoweringInfo &FuncInfo,
680 SDValue &Chain, SDValue *Flag,
681 const Value *V) const {
682 // A Value with type {} or [0 x %t] needs no registers.
683 if (ValueVTs.empty())
686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
688 // Assemble the legal parts into the final values.
689 SmallVector<SDValue, 4> Values(ValueVTs.size());
690 SmallVector<SDValue, 8> Parts;
691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
692 // Copy the legal parts from the registers.
693 EVT ValueVT = ValueVTs[Value];
694 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
695 MVT RegisterVT = RegVTs[Value];
697 Parts.resize(NumRegs);
698 for (unsigned i = 0; i != NumRegs; ++i) {
701 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
703 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
704 *Flag = P.getValue(2);
707 Chain = P.getValue(1);
710 // If the source register was virtual and if we know something about it,
711 // add an assert node.
712 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
713 !RegisterVT.isInteger() || RegisterVT.isVector())
716 const FunctionLoweringInfo::LiveOutInfo *LOI =
717 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
721 unsigned RegSize = RegisterVT.getSizeInBits();
722 unsigned NumSignBits = LOI->NumSignBits;
723 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
725 if (NumZeroBits == RegSize) {
726 // The current value is a zero.
727 // Explicitly express that as it would be easier for
728 // optimizations to kick in.
729 Parts[i] = DAG.getConstant(0, RegisterVT);
733 // FIXME: We capture more information than the dag can represent. For
734 // now, just use the tightest assertzext/assertsext possible.
736 EVT FromVT(MVT::Other);
737 if (NumSignBits == RegSize)
738 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
739 else if (NumZeroBits >= RegSize-1)
740 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
741 else if (NumSignBits > RegSize-8)
742 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
743 else if (NumZeroBits >= RegSize-8)
744 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
745 else if (NumSignBits > RegSize-16)
746 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
747 else if (NumZeroBits >= RegSize-16)
748 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
749 else if (NumSignBits > RegSize-32)
750 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
751 else if (NumZeroBits >= RegSize-32)
752 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
756 // Add an assertion node.
757 assert(FromVT != MVT::Other);
758 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
759 RegisterVT, P, DAG.getValueType(FromVT));
762 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
763 NumRegs, RegisterVT, ValueVT, V);
768 return DAG.getNode(ISD::MERGE_VALUES, dl,
769 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
770 &Values[0], ValueVTs.size());
773 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
774 /// specified value into the registers specified by this object. This uses
775 /// Chain/Flag as the input and updates them for the output Chain/Flag.
776 /// If the Flag pointer is NULL, no flag is used.
777 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
778 SDValue &Chain, SDValue *Flag,
779 const Value *V) const {
780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
782 // Get the list of the values's legal parts.
783 unsigned NumRegs = Regs.size();
784 SmallVector<SDValue, 8> Parts(NumRegs);
785 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
786 EVT ValueVT = ValueVTs[Value];
787 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
788 MVT RegisterVT = RegVTs[Value];
789 ISD::NodeType ExtendKind =
790 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
792 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
793 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
797 // Copy the parts into the registers.
798 SmallVector<SDValue, 8> Chains(NumRegs);
799 for (unsigned i = 0; i != NumRegs; ++i) {
802 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
804 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
805 *Flag = Part.getValue(1);
808 Chains[i] = Part.getValue(0);
811 if (NumRegs == 1 || Flag)
812 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
813 // flagged to it. That is the CopyToReg nodes and the user are considered
814 // a single scheduling unit. If we create a TokenFactor and return it as
815 // chain, then the TokenFactor is both a predecessor (operand) of the
816 // user as well as a successor (the TF operands are flagged to the user).
817 // c1, f1 = CopyToReg
818 // c2, f2 = CopyToReg
819 // c3 = TokenFactor c1, c2
822 Chain = Chains[NumRegs-1];
824 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
827 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
828 /// operand list. This adds the code marker and includes the number of
829 /// values added into it.
830 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
831 unsigned MatchingIdx,
833 std::vector<SDValue> &Ops) const {
834 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
836 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
838 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
839 else if (!Regs.empty() &&
840 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
841 // Put the register class of the virtual registers in the flag word. That
842 // way, later passes can recompute register class constraints for inline
843 // assembly as well as normal instructions.
844 // Don't do this for tied operands that can use the regclass information
846 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
847 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
848 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
851 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
854 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
855 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
856 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
857 MVT RegisterVT = RegVTs[Value];
858 for (unsigned i = 0; i != NumRegs; ++i) {
859 assert(Reg < Regs.size() && "Mismatch in # registers expected");
860 unsigned TheReg = Regs[Reg++];
861 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
863 // Notice if we clobbered the stack pointer. Yes, inline asm can do this.
864 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
865 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
866 MFI->setHasInlineAsmWithSPAdjust(true);
872 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
873 const TargetLibraryInfo *li) {
877 TD = DAG.getTarget().getDataLayout();
878 Context = DAG.getContext();
879 LPadToCallSiteMap.clear();
882 /// clear - Clear out the current SelectionDAG and the associated
883 /// state and prepare this SelectionDAGBuilder object to be used
884 /// for a new block. This doesn't clear out information about
885 /// additional blocks that are needed to complete switch lowering
886 /// or PHI node updating; that information is cleared out as it is
888 void SelectionDAGBuilder::clear() {
890 UnusedArgNodeMap.clear();
891 PendingLoads.clear();
892 PendingExports.clear();
895 SDNodeOrder = LowestSDNodeOrder;
898 /// clearDanglingDebugInfo - Clear the dangling debug information
899 /// map. This function is separated from the clear so that debug
900 /// information that is dangling in a basic block can be properly
901 /// resolved in a different basic block. This allows the
902 /// SelectionDAG to resolve dangling debug information attached
904 void SelectionDAGBuilder::clearDanglingDebugInfo() {
905 DanglingDebugInfoMap.clear();
908 /// getRoot - Return the current virtual root of the Selection DAG,
909 /// flushing any PendingLoad items. This must be done before emitting
910 /// a store or any other node that may need to be ordered after any
911 /// prior load instructions.
913 SDValue SelectionDAGBuilder::getRoot() {
914 if (PendingLoads.empty())
915 return DAG.getRoot();
917 if (PendingLoads.size() == 1) {
918 SDValue Root = PendingLoads[0];
920 PendingLoads.clear();
924 // Otherwise, we have to make a token factor node.
925 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
926 &PendingLoads[0], PendingLoads.size());
927 PendingLoads.clear();
932 /// getControlRoot - Similar to getRoot, but instead of flushing all the
933 /// PendingLoad items, flush all the PendingExports items. It is necessary
934 /// to do this before emitting a terminator instruction.
936 SDValue SelectionDAGBuilder::getControlRoot() {
937 SDValue Root = DAG.getRoot();
939 if (PendingExports.empty())
942 // Turn all of the CopyToReg chains into one factored node.
943 if (Root.getOpcode() != ISD::EntryToken) {
944 unsigned i = 0, e = PendingExports.size();
945 for (; i != e; ++i) {
946 assert(PendingExports[i].getNode()->getNumOperands() > 1);
947 if (PendingExports[i].getNode()->getOperand(0) == Root)
948 break; // Don't add the root if we already indirectly depend on it.
952 PendingExports.push_back(Root);
955 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
957 PendingExports.size());
958 PendingExports.clear();
963 void SelectionDAGBuilder::visit(const Instruction &I) {
964 // Set up outgoing PHI node register values before emitting the terminator.
965 if (isa<TerminatorInst>(&I))
966 HandlePHINodesInSuccessorBlocks(I.getParent());
972 visit(I.getOpcode(), I);
974 if (!isa<TerminatorInst>(&I) && !HasTailCall)
975 CopyToExportRegsIfNeeded(&I);
980 void SelectionDAGBuilder::visitPHI(const PHINode &) {
981 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
984 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
985 // Note: this doesn't use InstVisitor, because it has to work with
986 // ConstantExpr's in addition to instructions.
988 default: llvm_unreachable("Unknown instruction type encountered!");
989 // Build the switch statement using the Instruction.def file.
990 #define HANDLE_INST(NUM, OPCODE, CLASS) \
991 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
992 #include "llvm/IR/Instruction.def"
996 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
997 // generate the debug data structures now that we've seen its definition.
998 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1000 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
1002 const DbgValueInst *DI = DDI.getDI();
1003 DebugLoc dl = DDI.getdl();
1004 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1005 MDNode *Variable = DI->getVariable();
1006 uint64_t Offset = DI->getOffset();
1008 if (Val.getNode()) {
1009 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
1010 SDV = DAG.getDbgValue(Variable, Val.getNode(),
1011 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
1012 DAG.AddDbgValue(SDV, Val.getNode(), false);
1015 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1016 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1020 /// getValue - Return an SDValue for the given Value.
1021 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1022 // If we already have an SDValue for this value, use it. It's important
1023 // to do this first, so that we don't create a CopyFromReg if we already
1024 // have a regular SDValue.
1025 SDValue &N = NodeMap[V];
1026 if (N.getNode()) return N;
1028 // If there's a virtual register allocated and initialized for this
1030 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1031 if (It != FuncInfo.ValueMap.end()) {
1032 unsigned InReg = It->second;
1033 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1034 InReg, V->getType());
1035 SDValue Chain = DAG.getEntryNode();
1036 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1037 resolveDanglingDebugInfo(V, N);
1041 // Otherwise create a new SDValue and remember it.
1042 SDValue Val = getValueImpl(V);
1044 resolveDanglingDebugInfo(V, Val);
1048 /// getNonRegisterValue - Return an SDValue for the given Value, but
1049 /// don't look in FuncInfo.ValueMap for a virtual register.
1050 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1051 // If we already have an SDValue for this value, use it.
1052 SDValue &N = NodeMap[V];
1053 if (N.getNode()) return N;
1055 // Otherwise create a new SDValue and remember it.
1056 SDValue Val = getValueImpl(V);
1058 resolveDanglingDebugInfo(V, Val);
1062 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1063 /// Create an SDValue for the given value.
1064 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1065 const TargetLowering *TLI = TM.getTargetLowering();
1067 if (const Constant *C = dyn_cast<Constant>(V)) {
1068 EVT VT = TLI->getValueType(V->getType(), true);
1070 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1071 return DAG.getConstant(*CI, VT);
1073 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1074 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1076 if (isa<ConstantPointerNull>(C)) {
1077 unsigned AS = V->getType()->getPointerAddressSpace();
1078 return DAG.getConstant(0, TLI->getPointerTy(AS));
1081 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1082 return DAG.getConstantFP(*CFP, VT);
1084 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1085 return DAG.getUNDEF(VT);
1087 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1088 visit(CE->getOpcode(), *CE);
1089 SDValue N1 = NodeMap[V];
1090 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1094 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1095 SmallVector<SDValue, 4> Constants;
1096 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1098 SDNode *Val = getValue(*OI).getNode();
1099 // If the operand is an empty aggregate, there are no values.
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Constants.push_back(SDValue(Val, i));
1107 return DAG.getMergeValues(&Constants[0], Constants.size(),
1111 if (const ConstantDataSequential *CDS =
1112 dyn_cast<ConstantDataSequential>(C)) {
1113 SmallVector<SDValue, 4> Ops;
1114 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1115 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1116 // Add each leaf value from the operand to the Constants list
1117 // to form a flattened list of all the values.
1118 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1119 Ops.push_back(SDValue(Val, i));
1122 if (isa<ArrayType>(CDS->getType()))
1123 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1124 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1125 VT, &Ops[0], Ops.size());
1128 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1129 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1130 "Unknown struct or array constant!");
1132 SmallVector<EVT, 4> ValueVTs;
1133 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1134 unsigned NumElts = ValueVTs.size();
1136 return SDValue(); // empty struct
1137 SmallVector<SDValue, 4> Constants(NumElts);
1138 for (unsigned i = 0; i != NumElts; ++i) {
1139 EVT EltVT = ValueVTs[i];
1140 if (isa<UndefValue>(C))
1141 Constants[i] = DAG.getUNDEF(EltVT);
1142 else if (EltVT.isFloatingPoint())
1143 Constants[i] = DAG.getConstantFP(0, EltVT);
1145 Constants[i] = DAG.getConstant(0, EltVT);
1148 return DAG.getMergeValues(&Constants[0], NumElts,
1152 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1153 return DAG.getBlockAddress(BA, VT);
1155 VectorType *VecTy = cast<VectorType>(V->getType());
1156 unsigned NumElements = VecTy->getNumElements();
1158 // Now that we know the number and type of the elements, get that number of
1159 // elements into the Ops array based on what kind of constant it is.
1160 SmallVector<SDValue, 16> Ops;
1161 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1162 for (unsigned i = 0; i != NumElements; ++i)
1163 Ops.push_back(getValue(CV->getOperand(i)));
1165 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1166 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1169 if (EltVT.isFloatingPoint())
1170 Op = DAG.getConstantFP(0, EltVT);
1172 Op = DAG.getConstant(0, EltVT);
1173 Ops.assign(NumElements, Op);
1176 // Create a BUILD_VECTOR node.
1177 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1178 VT, &Ops[0], Ops.size());
1181 // If this is a static alloca, generate it as the frameindex instead of
1183 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1184 DenseMap<const AllocaInst*, int>::iterator SI =
1185 FuncInfo.StaticAllocaMap.find(AI);
1186 if (SI != FuncInfo.StaticAllocaMap.end())
1187 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1190 // If this is an instruction which fast-isel has deferred, select it now.
1191 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1192 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1193 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1194 SDValue Chain = DAG.getEntryNode();
1195 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1198 llvm_unreachable("Can't get register for value!");
1201 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1202 const TargetLowering *TLI = TM.getTargetLowering();
1203 SDValue Chain = getControlRoot();
1204 SmallVector<ISD::OutputArg, 8> Outs;
1205 SmallVector<SDValue, 8> OutVals;
1207 if (!FuncInfo.CanLowerReturn) {
1208 unsigned DemoteReg = FuncInfo.DemoteRegister;
1209 const Function *F = I.getParent()->getParent();
1211 // Emit a store of the return value through the virtual register.
1212 // Leave Outs empty so that LowerReturn won't try to load return
1213 // registers the usual way.
1214 SmallVector<EVT, 1> PtrValueVTs;
1215 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1218 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1219 SDValue RetOp = getValue(I.getOperand(0));
1221 SmallVector<EVT, 4> ValueVTs;
1222 SmallVector<uint64_t, 4> Offsets;
1223 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1224 unsigned NumValues = ValueVTs.size();
1226 SmallVector<SDValue, 4> Chains(NumValues);
1227 for (unsigned i = 0; i != NumValues; ++i) {
1228 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1229 RetPtr.getValueType(), RetPtr,
1230 DAG.getIntPtrConstant(Offsets[i]));
1232 DAG.getStore(Chain, getCurSDLoc(),
1233 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1234 // FIXME: better loc info would be nice.
1235 Add, MachinePointerInfo(), false, false, 0);
1238 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1239 MVT::Other, &Chains[0], NumValues);
1240 } else if (I.getNumOperands() != 0) {
1241 SmallVector<EVT, 4> ValueVTs;
1242 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1243 unsigned NumValues = ValueVTs.size();
1245 SDValue RetOp = getValue(I.getOperand(0));
1246 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1247 EVT VT = ValueVTs[j];
1249 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1251 const Function *F = I.getParent()->getParent();
1252 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1254 ExtendKind = ISD::SIGN_EXTEND;
1255 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1257 ExtendKind = ISD::ZERO_EXTEND;
1259 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1260 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1262 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1263 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1264 SmallVector<SDValue, 4> Parts(NumParts);
1265 getCopyToParts(DAG, getCurSDLoc(),
1266 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1267 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1269 // 'inreg' on function refers to return value
1270 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1271 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1275 // Propagate extension type if any
1276 if (ExtendKind == ISD::SIGN_EXTEND)
1278 else if (ExtendKind == ISD::ZERO_EXTEND)
1281 for (unsigned i = 0; i < NumParts; ++i) {
1282 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1283 VT, /*isfixed=*/true, 0, 0));
1284 OutVals.push_back(Parts[i]);
1290 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1291 CallingConv::ID CallConv =
1292 DAG.getMachineFunction().getFunction()->getCallingConv();
1293 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1294 Outs, OutVals, getCurSDLoc(),
1297 // Verify that the target's LowerReturn behaved as expected.
1298 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1299 "LowerReturn didn't return a valid chain!");
1301 // Update the DAG with the new chain value resulting from return lowering.
1305 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1306 /// created for it, emit nodes to copy the value into the virtual
1308 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1310 if (V->getType()->isEmptyTy())
1313 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1314 if (VMI != FuncInfo.ValueMap.end()) {
1315 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1316 CopyValueToVirtualRegister(V, VMI->second);
1320 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1321 /// the current basic block, add it to ValueMap now so that we'll get a
1323 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1324 // No need to export constants.
1325 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1327 // Already exported?
1328 if (FuncInfo.isExportedInst(V)) return;
1330 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1331 CopyValueToVirtualRegister(V, Reg);
1334 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1335 const BasicBlock *FromBB) {
1336 // The operands of the setcc have to be in this block. We don't know
1337 // how to export them from some other block.
1338 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1339 // Can export from current BB.
1340 if (VI->getParent() == FromBB)
1343 // Is already exported, noop.
1344 return FuncInfo.isExportedInst(V);
1347 // If this is an argument, we can export it if the BB is the entry block or
1348 // if it is already exported.
1349 if (isa<Argument>(V)) {
1350 if (FromBB == &FromBB->getParent()->getEntryBlock())
1353 // Otherwise, can only export this if it is already exported.
1354 return FuncInfo.isExportedInst(V);
1357 // Otherwise, constants can always be exported.
1361 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1362 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1363 const MachineBasicBlock *Dst) const {
1364 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1367 const BasicBlock *SrcBB = Src->getBasicBlock();
1368 const BasicBlock *DstBB = Dst->getBasicBlock();
1369 return BPI->getEdgeWeight(SrcBB, DstBB);
1372 void SelectionDAGBuilder::
1373 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1374 uint32_t Weight /* = 0 */) {
1376 Weight = getEdgeWeight(Src, Dst);
1377 Src->addSuccessor(Dst, Weight);
1381 static bool InBlock(const Value *V, const BasicBlock *BB) {
1382 if (const Instruction *I = dyn_cast<Instruction>(V))
1383 return I->getParent() == BB;
1387 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1388 /// This function emits a branch and is used at the leaves of an OR or an
1389 /// AND operator tree.
1392 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1393 MachineBasicBlock *TBB,
1394 MachineBasicBlock *FBB,
1395 MachineBasicBlock *CurBB,
1396 MachineBasicBlock *SwitchBB) {
1397 const BasicBlock *BB = CurBB->getBasicBlock();
1399 // If the leaf of the tree is a comparison, merge the condition into
1401 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1402 // The operands of the cmp have to be in this block. We don't know
1403 // how to export them from some other block. If this is the first block
1404 // of the sequence, no exporting is needed.
1405 if (CurBB == SwitchBB ||
1406 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1407 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1408 ISD::CondCode Condition;
1409 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1410 Condition = getICmpCondCode(IC->getPredicate());
1411 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1412 Condition = getFCmpCondCode(FC->getPredicate());
1413 if (TM.Options.NoNaNsFPMath)
1414 Condition = getFCmpCodeWithoutNaN(Condition);
1416 Condition = ISD::SETEQ; // silence warning.
1417 llvm_unreachable("Unknown compare instruction");
1420 CaseBlock CB(Condition, BOp->getOperand(0),
1421 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1422 SwitchCases.push_back(CB);
1427 // Create a CaseBlock record representing this branch.
1428 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1429 NULL, TBB, FBB, CurBB);
1430 SwitchCases.push_back(CB);
1433 /// FindMergedConditions - If Cond is an expression like
1434 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1435 MachineBasicBlock *TBB,
1436 MachineBasicBlock *FBB,
1437 MachineBasicBlock *CurBB,
1438 MachineBasicBlock *SwitchBB,
1440 // If this node is not part of the or/and tree, emit it as a branch.
1441 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1442 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1443 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1444 BOp->getParent() != CurBB->getBasicBlock() ||
1445 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1446 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1447 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1451 // Create TmpBB after CurBB.
1452 MachineFunction::iterator BBI = CurBB;
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1455 CurBB->getParent()->insert(++BBI, TmpBB);
1457 if (Opc == Instruction::Or) {
1458 // Codegen X | Y as:
1466 // Emit the LHS condition.
1467 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1469 // Emit the RHS condition into TmpBB.
1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1472 assert(Opc == Instruction::And && "Unknown merge op!");
1473 // Codegen X & Y as:
1480 // This requires creation of TmpBB after CurBB.
1482 // Emit the LHS condition.
1483 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1485 // Emit the RHS condition into TmpBB.
1486 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1490 /// If the set of cases should be emitted as a series of branches, return true.
1491 /// If we should emit this as a bunch of and/or'd together conditions, return
1494 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1495 if (Cases.size() != 2) return true;
1497 // If this is two comparisons of the same values or'd or and'd together, they
1498 // will get folded into a single comparison, so don't emit two blocks.
1499 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1500 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1501 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1502 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1506 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1507 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1508 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1509 Cases[0].CC == Cases[1].CC &&
1510 isa<Constant>(Cases[0].CmpRHS) &&
1511 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1512 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1514 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1521 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1522 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1524 // Update machine-CFG edges.
1525 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1527 // Figure out which block is immediately after the current one.
1528 MachineBasicBlock *NextBlock = 0;
1529 MachineFunction::iterator BBI = BrMBB;
1530 if (++BBI != FuncInfo.MF->end())
1533 if (I.isUnconditional()) {
1534 // Update machine-CFG edges.
1535 BrMBB->addSuccessor(Succ0MBB);
1537 // If this is not a fall-through branch, emit the branch.
1538 if (Succ0MBB != NextBlock)
1539 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1540 MVT::Other, getControlRoot(),
1541 DAG.getBasicBlock(Succ0MBB)));
1546 // If this condition is one of the special cases we handle, do special stuff
1548 const Value *CondVal = I.getCondition();
1549 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1551 // If this is a series of conditions that are or'd or and'd together, emit
1552 // this as a sequence of branches instead of setcc's with and/or operations.
1553 // As long as jumps are not expensive, this should improve performance.
1554 // For example, instead of something like:
1567 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1568 if (!TM.getTargetLowering()->isJumpExpensive() &&
1570 (BOp->getOpcode() == Instruction::And ||
1571 BOp->getOpcode() == Instruction::Or)) {
1572 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1574 // If the compares in later blocks need to use values not currently
1575 // exported from this block, export them now. This block should always
1576 // be the first entry.
1577 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1579 // Allow some cases to be rejected.
1580 if (ShouldEmitAsBranches(SwitchCases)) {
1581 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1582 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1583 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1586 // Emit the branch for this block.
1587 visitSwitchCase(SwitchCases[0], BrMBB);
1588 SwitchCases.erase(SwitchCases.begin());
1592 // Okay, we decided not to do this, remove any inserted MBB's and clear
1594 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1595 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1597 SwitchCases.clear();
1601 // Create a CaseBlock record representing this branch.
1602 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1603 NULL, Succ0MBB, Succ1MBB, BrMBB);
1605 // Use visitSwitchCase to actually insert the fast branch sequence for this
1607 visitSwitchCase(CB, BrMBB);
1610 /// visitSwitchCase - Emits the necessary code to represent a single node in
1611 /// the binary search tree resulting from lowering a switch instruction.
1612 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1613 MachineBasicBlock *SwitchBB) {
1615 SDValue CondLHS = getValue(CB.CmpLHS);
1616 SDLoc dl = getCurSDLoc();
1618 // Build the setcc now.
1619 if (CB.CmpMHS == NULL) {
1620 // Fold "(X == true)" to X and "(X == false)" to !X to
1621 // handle common cases produced by branch lowering.
1622 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1623 CB.CC == ISD::SETEQ)
1625 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1626 CB.CC == ISD::SETEQ) {
1627 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1628 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1630 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1632 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1634 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1635 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1637 SDValue CmpOp = getValue(CB.CmpMHS);
1638 EVT VT = CmpOp.getValueType();
1640 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1641 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1644 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1645 VT, CmpOp, DAG.getConstant(Low, VT));
1646 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1647 DAG.getConstant(High-Low, VT), ISD::SETULE);
1651 // Update successor info
1652 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1653 // TrueBB and FalseBB are always different unless the incoming IR is
1654 // degenerate. This only happens when running llc on weird IR.
1655 if (CB.TrueBB != CB.FalseBB)
1656 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1658 // Set NextBlock to be the MBB immediately after the current one, if any.
1659 // This is used to avoid emitting unnecessary branches to the next block.
1660 MachineBasicBlock *NextBlock = 0;
1661 MachineFunction::iterator BBI = SwitchBB;
1662 if (++BBI != FuncInfo.MF->end())
1665 // If the lhs block is the next block, invert the condition so that we can
1666 // fall through to the lhs instead of the rhs block.
1667 if (CB.TrueBB == NextBlock) {
1668 std::swap(CB.TrueBB, CB.FalseBB);
1669 SDValue True = DAG.getConstant(1, Cond.getValueType());
1670 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1673 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1674 MVT::Other, getControlRoot(), Cond,
1675 DAG.getBasicBlock(CB.TrueBB));
1677 // Insert the false branch. Do this even if it's a fall through branch,
1678 // this makes it easier to do DAG optimizations which require inverting
1679 // the branch condition.
1680 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1681 DAG.getBasicBlock(CB.FalseBB));
1683 DAG.setRoot(BrCond);
1686 /// visitJumpTable - Emit JumpTable node in the current MBB
1687 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1688 // Emit the code for the jump table
1689 assert(JT.Reg != -1U && "Should lower JT Header first!");
1690 EVT PTy = TM.getTargetLowering()->getPointerTy();
1691 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1693 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1694 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1695 MVT::Other, Index.getValue(1),
1697 DAG.setRoot(BrJumpTable);
1700 /// visitJumpTableHeader - This function emits necessary code to produce index
1701 /// in the JumpTable from switch case.
1702 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1703 JumpTableHeader &JTH,
1704 MachineBasicBlock *SwitchBB) {
1705 // Subtract the lowest switch case value from the value being switched on and
1706 // conditional branch to default mbb if the result is greater than the
1707 // difference between smallest and largest cases.
1708 SDValue SwitchOp = getValue(JTH.SValue);
1709 EVT VT = SwitchOp.getValueType();
1710 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1711 DAG.getConstant(JTH.First, VT));
1713 // The SDNode we just created, which holds the value being switched on minus
1714 // the smallest case value, needs to be copied to a virtual register so it
1715 // can be used as an index into the jump table in a subsequent basic block.
1716 // This value may be smaller or larger than the target's pointer type, and
1717 // therefore require extension or truncating.
1718 const TargetLowering *TLI = TM.getTargetLowering();
1719 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1721 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1722 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1723 JumpTableReg, SwitchOp);
1724 JT.Reg = JumpTableReg;
1726 // Emit the range check for the jump table, and branch to the default block
1727 // for the switch statement if the value being switched on exceeds the largest
1728 // case in the switch.
1729 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1730 TLI->getSetCCResultType(*DAG.getContext(),
1731 Sub.getValueType()),
1733 DAG.getConstant(JTH.Last - JTH.First,VT),
1736 // Set NextBlock to be the MBB immediately after the current one, if any.
1737 // This is used to avoid emitting unnecessary branches to the next block.
1738 MachineBasicBlock *NextBlock = 0;
1739 MachineFunction::iterator BBI = SwitchBB;
1741 if (++BBI != FuncInfo.MF->end())
1744 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1745 MVT::Other, CopyTo, CMP,
1746 DAG.getBasicBlock(JT.Default));
1748 if (JT.MBB != NextBlock)
1749 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1750 DAG.getBasicBlock(JT.MBB));
1752 DAG.setRoot(BrCond);
1755 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1756 /// tail spliced into a stack protector check success bb.
1758 /// For a high level explanation of how this fits into the stack protector
1759 /// generation see the comment on the declaration of class
1760 /// StackProtectorDescriptor.
1761 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1762 MachineBasicBlock *ParentBB) {
1764 // First create the loads to the guard/stack slot for the comparison.
1765 const TargetLowering *TLI = TM.getTargetLowering();
1766 EVT PtrTy = TLI->getPointerTy();
1768 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1769 int FI = MFI->getStackProtectorIndex();
1771 const Value *IRGuard = SPD.getGuard();
1772 SDValue GuardPtr = getValue(IRGuard);
1773 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1776 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1777 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1778 GuardPtr, MachinePointerInfo(IRGuard, 0),
1779 true, false, false, Align);
1781 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1783 MachinePointerInfo::getFixedStack(FI),
1784 true, false, false, Align);
1786 // Perform the comparison via a subtract/getsetcc.
1787 EVT VT = Guard.getValueType();
1788 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1790 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1791 TLI->getSetCCResultType(*DAG.getContext(),
1792 Sub.getValueType()),
1793 Sub, DAG.getConstant(0, VT),
1796 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1797 // branch to failure MBB.
1798 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1799 MVT::Other, StackSlot.getOperand(0),
1800 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1801 // Otherwise branch to success MBB.
1802 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1804 DAG.getBasicBlock(SPD.getSuccessMBB()));
1809 /// Codegen the failure basic block for a stack protector check.
1811 /// A failure stack protector machine basic block consists simply of a call to
1812 /// __stack_chk_fail().
1814 /// For a high level explanation of how this fits into the stack protector
1815 /// generation see the comment on the declaration of class
1816 /// StackProtectorDescriptor.
1818 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1819 const TargetLowering *TLI = TM.getTargetLowering();
1820 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1821 MVT::isVoid, 0, 0, false, getCurSDLoc(),
1822 false, false).second;
1826 /// visitBitTestHeader - This function emits necessary code to produce value
1827 /// suitable for "bit tests"
1828 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1829 MachineBasicBlock *SwitchBB) {
1830 // Subtract the minimum value
1831 SDValue SwitchOp = getValue(B.SValue);
1832 EVT VT = SwitchOp.getValueType();
1833 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1834 DAG.getConstant(B.First, VT));
1837 const TargetLowering *TLI = TM.getTargetLowering();
1838 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1839 TLI->getSetCCResultType(*DAG.getContext(),
1840 Sub.getValueType()),
1841 Sub, DAG.getConstant(B.Range, VT),
1844 // Determine the type of the test operands.
1845 bool UsePtrType = false;
1846 if (!TLI->isTypeLegal(VT))
1849 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1850 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1851 // Switch table case range are encoded into series of masks.
1852 // Just use pointer type, it's guaranteed to fit.
1858 VT = TLI->getPointerTy();
1859 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1862 B.RegVT = VT.getSimpleVT();
1863 B.Reg = FuncInfo.CreateReg(B.RegVT);
1864 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1867 // Set NextBlock to be the MBB immediately after the current one, if any.
1868 // This is used to avoid emitting unnecessary branches to the next block.
1869 MachineBasicBlock *NextBlock = 0;
1870 MachineFunction::iterator BBI = SwitchBB;
1871 if (++BBI != FuncInfo.MF->end())
1874 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1876 addSuccessorWithWeight(SwitchBB, B.Default);
1877 addSuccessorWithWeight(SwitchBB, MBB);
1879 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1880 MVT::Other, CopyTo, RangeCmp,
1881 DAG.getBasicBlock(B.Default));
1883 if (MBB != NextBlock)
1884 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1885 DAG.getBasicBlock(MBB));
1887 DAG.setRoot(BrRange);
1890 /// visitBitTestCase - this function produces one "bit test"
1891 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1892 MachineBasicBlock* NextMBB,
1893 uint32_t BranchWeightToNext,
1896 MachineBasicBlock *SwitchBB) {
1898 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1901 unsigned PopCount = CountPopulation_64(B.Mask);
1902 const TargetLowering *TLI = TM.getTargetLowering();
1903 if (PopCount == 1) {
1904 // Testing for a single bit; just compare the shift count with what it
1905 // would need to be to shift a 1 bit in that position.
1906 Cmp = DAG.getSetCC(getCurSDLoc(),
1907 TLI->getSetCCResultType(*DAG.getContext(), VT),
1909 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1911 } else if (PopCount == BB.Range) {
1912 // There is only one zero bit in the range, test for it directly.
1913 Cmp = DAG.getSetCC(getCurSDLoc(),
1914 TLI->getSetCCResultType(*DAG.getContext(), VT),
1916 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1919 // Make desired shift
1920 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1921 DAG.getConstant(1, VT), ShiftOp);
1923 // Emit bit tests and jumps
1924 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1925 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1926 Cmp = DAG.getSetCC(getCurSDLoc(),
1927 TLI->getSetCCResultType(*DAG.getContext(), VT),
1928 AndOp, DAG.getConstant(0, VT),
1932 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1933 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1934 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1935 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1937 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1938 MVT::Other, getControlRoot(),
1939 Cmp, DAG.getBasicBlock(B.TargetBB));
1941 // Set NextBlock to be the MBB immediately after the current one, if any.
1942 // This is used to avoid emitting unnecessary branches to the next block.
1943 MachineBasicBlock *NextBlock = 0;
1944 MachineFunction::iterator BBI = SwitchBB;
1945 if (++BBI != FuncInfo.MF->end())
1948 if (NextMBB != NextBlock)
1949 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1950 DAG.getBasicBlock(NextMBB));
1955 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1956 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1958 // Retrieve successors.
1959 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1960 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1962 const Value *Callee(I.getCalledValue());
1963 const Function *Fn = dyn_cast<Function>(Callee);
1964 if (isa<InlineAsm>(Callee))
1966 else if (Fn && Fn->isIntrinsic()) {
1967 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1968 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1970 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1972 // If the value of the invoke is used outside of its defining block, make it
1973 // available as a virtual register.
1974 CopyToExportRegsIfNeeded(&I);
1976 // Update successor info
1977 addSuccessorWithWeight(InvokeMBB, Return);
1978 addSuccessorWithWeight(InvokeMBB, LandingPad);
1980 // Drop into normal successor.
1981 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1982 MVT::Other, getControlRoot(),
1983 DAG.getBasicBlock(Return)));
1986 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1987 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1990 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1991 assert(FuncInfo.MBB->isLandingPad() &&
1992 "Call to landingpad not in landing pad!");
1994 MachineBasicBlock *MBB = FuncInfo.MBB;
1995 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1996 AddLandingPadInfo(LP, MMI, MBB);
1998 // If there aren't registers to copy the values into (e.g., during SjLj
1999 // exceptions), then don't bother to create these DAG nodes.
2000 const TargetLowering *TLI = TM.getTargetLowering();
2001 if (TLI->getExceptionPointerRegister() == 0 &&
2002 TLI->getExceptionSelectorRegister() == 0)
2005 SmallVector<EVT, 2> ValueVTs;
2006 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2007 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2009 // Get the two live-in registers as SDValues. The physregs have already been
2010 // copied into virtual registers.
2012 Ops[0] = DAG.getZExtOrTrunc(
2013 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2014 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2015 getCurSDLoc(), ValueVTs[0]);
2016 Ops[1] = DAG.getZExtOrTrunc(
2017 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2018 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2019 getCurSDLoc(), ValueVTs[1]);
2022 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2023 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
2028 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2029 /// small case ranges).
2030 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2031 CaseRecVector& WorkList,
2033 MachineBasicBlock *Default,
2034 MachineBasicBlock *SwitchBB) {
2035 // Size is the number of Cases represented by this range.
2036 size_t Size = CR.Range.second - CR.Range.first;
2040 // Get the MachineFunction which holds the current MBB. This is used when
2041 // inserting any additional MBBs necessary to represent the switch.
2042 MachineFunction *CurMF = FuncInfo.MF;
2044 // Figure out which block is immediately after the current one.
2045 MachineBasicBlock *NextBlock = 0;
2046 MachineFunction::iterator BBI = CR.CaseBB;
2048 if (++BBI != FuncInfo.MF->end())
2051 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2052 // If any two of the cases has the same destination, and if one value
2053 // is the same as the other, but has one bit unset that the other has set,
2054 // use bit manipulation to do two compares at once. For example:
2055 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2056 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2057 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2058 if (Size == 2 && CR.CaseBB == SwitchBB) {
2059 Case &Small = *CR.Range.first;
2060 Case &Big = *(CR.Range.second-1);
2062 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2063 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2064 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2066 // Check that there is only one bit different.
2067 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2068 (SmallValue | BigValue) == BigValue) {
2069 // Isolate the common bit.
2070 APInt CommonBit = BigValue & ~SmallValue;
2071 assert((SmallValue | CommonBit) == BigValue &&
2072 CommonBit.countPopulation() == 1 && "Not a common bit?");
2074 SDValue CondLHS = getValue(SV);
2075 EVT VT = CondLHS.getValueType();
2076 SDLoc DL = getCurSDLoc();
2078 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2079 DAG.getConstant(CommonBit, VT));
2080 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2081 Or, DAG.getConstant(BigValue, VT),
2084 // Update successor info.
2085 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2086 addSuccessorWithWeight(SwitchBB, Small.BB,
2087 Small.ExtraWeight + Big.ExtraWeight);
2088 addSuccessorWithWeight(SwitchBB, Default,
2089 // The default destination is the first successor in IR.
2090 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2092 // Insert the true branch.
2093 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2094 getControlRoot(), Cond,
2095 DAG.getBasicBlock(Small.BB));
2097 // Insert the false branch.
2098 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2099 DAG.getBasicBlock(Default));
2101 DAG.setRoot(BrCond);
2107 // Order cases by weight so the most likely case will be checked first.
2108 uint32_t UnhandledWeights = 0;
2110 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2111 uint32_t IWeight = I->ExtraWeight;
2112 UnhandledWeights += IWeight;
2113 for (CaseItr J = CR.Range.first; J < I; ++J) {
2114 uint32_t JWeight = J->ExtraWeight;
2115 if (IWeight > JWeight)
2120 // Rearrange the case blocks so that the last one falls through if possible.
2121 Case &BackCase = *(CR.Range.second-1);
2123 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2124 // The last case block won't fall through into 'NextBlock' if we emit the
2125 // branches in this order. See if rearranging a case value would help.
2126 // We start at the bottom as it's the case with the least weight.
2127 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2128 if (I->BB == NextBlock) {
2129 std::swap(*I, BackCase);
2134 // Create a CaseBlock record representing a conditional branch to
2135 // the Case's target mbb if the value being switched on SV is equal
2137 MachineBasicBlock *CurBlock = CR.CaseBB;
2138 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2139 MachineBasicBlock *FallThrough;
2141 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2142 CurMF->insert(BBI, FallThrough);
2144 // Put SV in a virtual register to make it available from the new blocks.
2145 ExportFromCurrentBlock(SV);
2147 // If the last case doesn't match, go to the default block.
2148 FallThrough = Default;
2151 const Value *RHS, *LHS, *MHS;
2153 if (I->High == I->Low) {
2154 // This is just small small case range :) containing exactly 1 case
2156 LHS = SV; RHS = I->High; MHS = NULL;
2159 LHS = I->Low; MHS = SV; RHS = I->High;
2162 // The false weight should be sum of all un-handled cases.
2163 UnhandledWeights -= I->ExtraWeight;
2164 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2166 /* trueweight */ I->ExtraWeight,
2167 /* falseweight */ UnhandledWeights);
2169 // If emitting the first comparison, just call visitSwitchCase to emit the
2170 // code into the current block. Otherwise, push the CaseBlock onto the
2171 // vector to be later processed by SDISel, and insert the node's MBB
2172 // before the next MBB.
2173 if (CurBlock == SwitchBB)
2174 visitSwitchCase(CB, SwitchBB);
2176 SwitchCases.push_back(CB);
2178 CurBlock = FallThrough;
2184 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2185 return TLI.supportJumpTables() &&
2186 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2187 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2190 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2191 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2192 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2193 return (LastExt - FirstExt + 1ULL);
2196 /// handleJTSwitchCase - Emit jumptable for current switch case range
2197 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2198 CaseRecVector &WorkList,
2200 MachineBasicBlock *Default,
2201 MachineBasicBlock *SwitchBB) {
2202 Case& FrontCase = *CR.Range.first;
2203 Case& BackCase = *(CR.Range.second-1);
2205 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2206 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2208 APInt TSize(First.getBitWidth(), 0);
2209 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2212 const TargetLowering *TLI = TM.getTargetLowering();
2213 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2216 APInt Range = ComputeRange(First, Last);
2217 // The density is TSize / Range. Require at least 40%.
2218 // It should not be possible for IntTSize to saturate for sane code, but make
2219 // sure we handle Range saturation correctly.
2220 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2221 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2222 if (IntTSize * 10 < IntRange * 4)
2225 DEBUG(dbgs() << "Lowering jump table\n"
2226 << "First entry: " << First << ". Last entry: " << Last << '\n'
2227 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2229 // Get the MachineFunction which holds the current MBB. This is used when
2230 // inserting any additional MBBs necessary to represent the switch.
2231 MachineFunction *CurMF = FuncInfo.MF;
2233 // Figure out which block is immediately after the current one.
2234 MachineFunction::iterator BBI = CR.CaseBB;
2237 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2239 // Create a new basic block to hold the code for loading the address
2240 // of the jump table, and jumping to it. Update successor information;
2241 // we will either branch to the default case for the switch, or the jump
2243 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2244 CurMF->insert(BBI, JumpTableBB);
2246 addSuccessorWithWeight(CR.CaseBB, Default);
2247 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2249 // Build a vector of destination BBs, corresponding to each target
2250 // of the jump table. If the value of the jump table slot corresponds to
2251 // a case statement, push the case's BB onto the vector, otherwise, push
2253 std::vector<MachineBasicBlock*> DestBBs;
2255 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2256 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2257 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2259 if (Low.sle(TEI) && TEI.sle(High)) {
2260 DestBBs.push_back(I->BB);
2264 DestBBs.push_back(Default);
2268 // Calculate weight for each unique destination in CR.
2269 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2271 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2272 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2273 DestWeights.find(I->BB);
2274 if (Itr != DestWeights.end())
2275 Itr->second += I->ExtraWeight;
2277 DestWeights[I->BB] = I->ExtraWeight;
2280 // Update successor info. Add one edge to each unique successor.
2281 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2282 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2283 E = DestBBs.end(); I != E; ++I) {
2284 if (!SuccsHandled[(*I)->getNumber()]) {
2285 SuccsHandled[(*I)->getNumber()] = true;
2286 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2287 DestWeights.find(*I);
2288 addSuccessorWithWeight(JumpTableBB, *I,
2289 Itr != DestWeights.end() ? Itr->second : 0);
2293 // Create a jump table index for this jump table.
2294 unsigned JTEncoding = TLI->getJumpTableEncoding();
2295 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2296 ->createJumpTableIndex(DestBBs);
2298 // Set the jump table information so that we can codegen it as a second
2299 // MachineBasicBlock
2300 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2301 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2302 if (CR.CaseBB == SwitchBB)
2303 visitJumpTableHeader(JT, JTH, SwitchBB);
2305 JTCases.push_back(JumpTableBlock(JTH, JT));
2309 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2311 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2312 CaseRecVector& WorkList,
2314 MachineBasicBlock* Default,
2315 MachineBasicBlock* SwitchBB) {
2316 // Get the MachineFunction which holds the current MBB. This is used when
2317 // inserting any additional MBBs necessary to represent the switch.
2318 MachineFunction *CurMF = FuncInfo.MF;
2320 // Figure out which block is immediately after the current one.
2321 MachineFunction::iterator BBI = CR.CaseBB;
2324 Case& FrontCase = *CR.Range.first;
2325 Case& BackCase = *(CR.Range.second-1);
2326 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2328 // Size is the number of Cases represented by this range.
2329 unsigned Size = CR.Range.second - CR.Range.first;
2331 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2332 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2334 CaseItr Pivot = CR.Range.first + Size/2;
2336 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2337 // (heuristically) allow us to emit JumpTable's later.
2338 APInt TSize(First.getBitWidth(), 0);
2339 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2343 APInt LSize = FrontCase.size();
2344 APInt RSize = TSize-LSize;
2345 DEBUG(dbgs() << "Selecting best pivot: \n"
2346 << "First: " << First << ", Last: " << Last <<'\n'
2347 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2348 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2350 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2351 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2352 APInt Range = ComputeRange(LEnd, RBegin);
2353 assert((Range - 2ULL).isNonNegative() &&
2354 "Invalid case distance");
2355 // Use volatile double here to avoid excess precision issues on some hosts,
2356 // e.g. that use 80-bit X87 registers.
2357 volatile double LDensity =
2358 (double)LSize.roundToDouble() /
2359 (LEnd - First + 1ULL).roundToDouble();
2360 volatile double RDensity =
2361 (double)RSize.roundToDouble() /
2362 (Last - RBegin + 1ULL).roundToDouble();
2363 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2364 // Should always split in some non-trivial place
2365 DEBUG(dbgs() <<"=>Step\n"
2366 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2367 << "LDensity: " << LDensity
2368 << ", RDensity: " << RDensity << '\n'
2369 << "Metric: " << Metric << '\n');
2370 if (FMetric < Metric) {
2373 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2380 const TargetLowering *TLI = TM.getTargetLowering();
2381 if (areJTsAllowed(*TLI)) {
2382 // If our case is dense we *really* should handle it earlier!
2383 assert((FMetric > 0) && "Should handle dense range earlier!");
2385 Pivot = CR.Range.first + Size/2;
2388 CaseRange LHSR(CR.Range.first, Pivot);
2389 CaseRange RHSR(Pivot, CR.Range.second);
2390 const Constant *C = Pivot->Low;
2391 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2393 // We know that we branch to the LHS if the Value being switched on is
2394 // less than the Pivot value, C. We use this to optimize our binary
2395 // tree a bit, by recognizing that if SV is greater than or equal to the
2396 // LHS's Case Value, and that Case Value is exactly one less than the
2397 // Pivot's Value, then we can branch directly to the LHS's Target,
2398 // rather than creating a leaf node for it.
2399 if ((LHSR.second - LHSR.first) == 1 &&
2400 LHSR.first->High == CR.GE &&
2401 cast<ConstantInt>(C)->getValue() ==
2402 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2403 TrueBB = LHSR.first->BB;
2405 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2406 CurMF->insert(BBI, TrueBB);
2407 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2409 // Put SV in a virtual register to make it available from the new blocks.
2410 ExportFromCurrentBlock(SV);
2413 // Similar to the optimization above, if the Value being switched on is
2414 // known to be less than the Constant CR.LT, and the current Case Value
2415 // is CR.LT - 1, then we can branch directly to the target block for
2416 // the current Case Value, rather than emitting a RHS leaf node for it.
2417 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2418 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2419 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2420 FalseBB = RHSR.first->BB;
2422 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2423 CurMF->insert(BBI, FalseBB);
2424 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2426 // Put SV in a virtual register to make it available from the new blocks.
2427 ExportFromCurrentBlock(SV);
2430 // Create a CaseBlock record representing a conditional branch to
2431 // the LHS node if the value being switched on SV is less than C.
2432 // Otherwise, branch to LHS.
2433 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2435 if (CR.CaseBB == SwitchBB)
2436 visitSwitchCase(CB, SwitchBB);
2438 SwitchCases.push_back(CB);
2443 /// handleBitTestsSwitchCase - if current case range has few destination and
2444 /// range span less, than machine word bitwidth, encode case range into series
2445 /// of masks and emit bit tests with these masks.
2446 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2447 CaseRecVector& WorkList,
2449 MachineBasicBlock* Default,
2450 MachineBasicBlock* SwitchBB) {
2451 const TargetLowering *TLI = TM.getTargetLowering();
2452 EVT PTy = TLI->getPointerTy();
2453 unsigned IntPtrBits = PTy.getSizeInBits();
2455 Case& FrontCase = *CR.Range.first;
2456 Case& BackCase = *(CR.Range.second-1);
2458 // Get the MachineFunction which holds the current MBB. This is used when
2459 // inserting any additional MBBs necessary to represent the switch.
2460 MachineFunction *CurMF = FuncInfo.MF;
2462 // If target does not have legal shift left, do not emit bit tests at all.
2463 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2467 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2469 // Single case counts one, case range - two.
2470 numCmps += (I->Low == I->High ? 1 : 2);
2473 // Count unique destinations
2474 SmallSet<MachineBasicBlock*, 4> Dests;
2475 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2476 Dests.insert(I->BB);
2477 if (Dests.size() > 3)
2478 // Don't bother the code below, if there are too much unique destinations
2481 DEBUG(dbgs() << "Total number of unique destinations: "
2482 << Dests.size() << '\n'
2483 << "Total number of comparisons: " << numCmps << '\n');
2485 // Compute span of values.
2486 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2487 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2488 APInt cmpRange = maxValue - minValue;
2490 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2491 << "Low bound: " << minValue << '\n'
2492 << "High bound: " << maxValue << '\n');
2494 if (cmpRange.uge(IntPtrBits) ||
2495 (!(Dests.size() == 1 && numCmps >= 3) &&
2496 !(Dests.size() == 2 && numCmps >= 5) &&
2497 !(Dests.size() >= 3 && numCmps >= 6)))
2500 DEBUG(dbgs() << "Emitting bit tests\n");
2501 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2503 // Optimize the case where all the case values fit in a
2504 // word without having to subtract minValue. In this case,
2505 // we can optimize away the subtraction.
2506 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2507 cmpRange = maxValue;
2509 lowBound = minValue;
2512 CaseBitsVector CasesBits;
2513 unsigned i, count = 0;
2515 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2516 MachineBasicBlock* Dest = I->BB;
2517 for (i = 0; i < count; ++i)
2518 if (Dest == CasesBits[i].BB)
2522 assert((count < 3) && "Too much destinations to test!");
2523 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2527 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2528 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2530 uint64_t lo = (lowValue - lowBound).getZExtValue();
2531 uint64_t hi = (highValue - lowBound).getZExtValue();
2532 CasesBits[i].ExtraWeight += I->ExtraWeight;
2534 for (uint64_t j = lo; j <= hi; j++) {
2535 CasesBits[i].Mask |= 1ULL << j;
2536 CasesBits[i].Bits++;
2540 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2544 // Figure out which block is immediately after the current one.
2545 MachineFunction::iterator BBI = CR.CaseBB;
2548 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2550 DEBUG(dbgs() << "Cases:\n");
2551 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2552 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2553 << ", Bits: " << CasesBits[i].Bits
2554 << ", BB: " << CasesBits[i].BB << '\n');
2556 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2557 CurMF->insert(BBI, CaseBB);
2558 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2560 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2562 // Put SV in a virtual register to make it available from the new blocks.
2563 ExportFromCurrentBlock(SV);
2566 BitTestBlock BTB(lowBound, cmpRange, SV,
2567 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2568 CR.CaseBB, Default, BTC);
2570 if (CR.CaseBB == SwitchBB)
2571 visitBitTestHeader(BTB, SwitchBB);
2573 BitTestCases.push_back(BTB);
2578 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2579 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2580 const SwitchInst& SI) {
2583 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2584 // Start with "simple" cases
2585 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2587 const BasicBlock *SuccBB = i.getCaseSuccessor();
2588 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2590 uint32_t ExtraWeight =
2591 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2593 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2594 SMBB, ExtraWeight));
2596 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2598 // Merge case into clusters
2599 if (Cases.size() >= 2)
2600 // Must recompute end() each iteration because it may be
2601 // invalidated by erase if we hold on to it
2602 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2603 J != Cases.end(); ) {
2604 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2605 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2606 MachineBasicBlock* nextBB = J->BB;
2607 MachineBasicBlock* currentBB = I->BB;
2609 // If the two neighboring cases go to the same destination, merge them
2610 // into a single case.
2611 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2613 I->ExtraWeight += J->ExtraWeight;
2620 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2621 if (I->Low != I->High)
2622 // A range counts double, since it requires two compares.
2629 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2630 MachineBasicBlock *Last) {
2632 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2633 if (JTCases[i].first.HeaderBB == First)
2634 JTCases[i].first.HeaderBB = Last;
2636 // Update BitTestCases.
2637 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2638 if (BitTestCases[i].Parent == First)
2639 BitTestCases[i].Parent = Last;
2642 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2643 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2645 // Figure out which block is immediately after the current one.
2646 MachineBasicBlock *NextBlock = 0;
2647 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2649 // If there is only the default destination, branch to it if it is not the
2650 // next basic block. Otherwise, just fall through.
2651 if (!SI.getNumCases()) {
2652 // Update machine-CFG edges.
2654 // If this is not a fall-through branch, emit the branch.
2655 SwitchMBB->addSuccessor(Default);
2656 if (Default != NextBlock)
2657 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2658 MVT::Other, getControlRoot(),
2659 DAG.getBasicBlock(Default)));
2664 // If there are any non-default case statements, create a vector of Cases
2665 // representing each one, and sort the vector so that we can efficiently
2666 // create a binary search tree from them.
2668 size_t numCmps = Clusterify(Cases, SI);
2669 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2670 << ". Total compares: " << numCmps << '\n');
2673 // Get the Value to be switched on and default basic blocks, which will be
2674 // inserted into CaseBlock records, representing basic blocks in the binary
2676 const Value *SV = SI.getCondition();
2678 // Push the initial CaseRec onto the worklist
2679 CaseRecVector WorkList;
2680 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2681 CaseRange(Cases.begin(),Cases.end())));
2683 while (!WorkList.empty()) {
2684 // Grab a record representing a case range to process off the worklist
2685 CaseRec CR = WorkList.back();
2686 WorkList.pop_back();
2688 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2691 // If the range has few cases (two or less) emit a series of specific
2693 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2696 // If the switch has more than N blocks, and is at least 40% dense, and the
2697 // target supports indirect branches, then emit a jump table rather than
2698 // lowering the switch to a binary tree of conditional branches.
2699 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2700 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2703 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2704 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2705 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2709 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2710 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2712 // Update machine-CFG edges with unique successors.
2713 SmallSet<BasicBlock*, 32> Done;
2714 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2715 BasicBlock *BB = I.getSuccessor(i);
2716 bool Inserted = Done.insert(BB);
2720 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2721 addSuccessorWithWeight(IndirectBrMBB, Succ);
2724 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2725 MVT::Other, getControlRoot(),
2726 getValue(I.getAddress())));
2729 void SelectionDAGBuilder::visitFSub(const User &I) {
2730 // -0.0 - X --> fneg
2731 Type *Ty = I.getType();
2732 if (isa<Constant>(I.getOperand(0)) &&
2733 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2734 SDValue Op2 = getValue(I.getOperand(1));
2735 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2736 Op2.getValueType(), Op2));
2740 visitBinary(I, ISD::FSUB);
2743 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2744 SDValue Op1 = getValue(I.getOperand(0));
2745 SDValue Op2 = getValue(I.getOperand(1));
2746 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2747 Op1.getValueType(), Op1, Op2));
2750 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2751 SDValue Op1 = getValue(I.getOperand(0));
2752 SDValue Op2 = getValue(I.getOperand(1));
2754 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2756 // Coerce the shift amount to the right type if we can.
2757 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2758 unsigned ShiftSize = ShiftTy.getSizeInBits();
2759 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2760 SDLoc DL = getCurSDLoc();
2762 // If the operand is smaller than the shift count type, promote it.
2763 if (ShiftSize > Op2Size)
2764 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2766 // If the operand is larger than the shift count type but the shift
2767 // count type has enough bits to represent any shift value, truncate
2768 // it now. This is a common case and it exposes the truncate to
2769 // optimization early.
2770 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2771 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2772 // Otherwise we'll need to temporarily settle for some other convenient
2773 // type. Type legalization will make adjustments once the shiftee is split.
2775 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2778 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2779 Op1.getValueType(), Op1, Op2));
2782 void SelectionDAGBuilder::visitSDiv(const User &I) {
2783 SDValue Op1 = getValue(I.getOperand(0));
2784 SDValue Op2 = getValue(I.getOperand(1));
2786 // Turn exact SDivs into multiplications.
2787 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2789 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2790 !isa<ConstantSDNode>(Op1) &&
2791 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2792 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2793 getCurSDLoc(), DAG));
2795 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2799 void SelectionDAGBuilder::visitICmp(const User &I) {
2800 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2801 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2802 predicate = IC->getPredicate();
2803 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2804 predicate = ICmpInst::Predicate(IC->getPredicate());
2805 SDValue Op1 = getValue(I.getOperand(0));
2806 SDValue Op2 = getValue(I.getOperand(1));
2807 ISD::CondCode Opcode = getICmpCondCode(predicate);
2809 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2810 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2813 void SelectionDAGBuilder::visitFCmp(const User &I) {
2814 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2815 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2816 predicate = FC->getPredicate();
2817 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2818 predicate = FCmpInst::Predicate(FC->getPredicate());
2819 SDValue Op1 = getValue(I.getOperand(0));
2820 SDValue Op2 = getValue(I.getOperand(1));
2821 ISD::CondCode Condition = getFCmpCondCode(predicate);
2822 if (TM.Options.NoNaNsFPMath)
2823 Condition = getFCmpCodeWithoutNaN(Condition);
2824 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2825 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2828 void SelectionDAGBuilder::visitSelect(const User &I) {
2829 SmallVector<EVT, 4> ValueVTs;
2830 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2831 unsigned NumValues = ValueVTs.size();
2832 if (NumValues == 0) return;
2834 SmallVector<SDValue, 4> Values(NumValues);
2835 SDValue Cond = getValue(I.getOperand(0));
2836 SDValue TrueVal = getValue(I.getOperand(1));
2837 SDValue FalseVal = getValue(I.getOperand(2));
2838 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2839 ISD::VSELECT : ISD::SELECT;
2841 for (unsigned i = 0; i != NumValues; ++i)
2842 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2843 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2845 SDValue(TrueVal.getNode(),
2846 TrueVal.getResNo() + i),
2847 SDValue(FalseVal.getNode(),
2848 FalseVal.getResNo() + i));
2850 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2851 DAG.getVTList(&ValueVTs[0], NumValues),
2852 &Values[0], NumValues));
2855 void SelectionDAGBuilder::visitTrunc(const User &I) {
2856 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2857 SDValue N = getValue(I.getOperand(0));
2858 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2859 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2862 void SelectionDAGBuilder::visitZExt(const User &I) {
2863 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2864 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2865 SDValue N = getValue(I.getOperand(0));
2866 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2867 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2870 void SelectionDAGBuilder::visitSExt(const User &I) {
2871 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2872 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2873 SDValue N = getValue(I.getOperand(0));
2874 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2875 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2878 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2879 // FPTrunc is never a no-op cast, no need to check
2880 SDValue N = getValue(I.getOperand(0));
2881 const TargetLowering *TLI = TM.getTargetLowering();
2882 EVT DestVT = TLI->getValueType(I.getType());
2883 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2885 DAG.getTargetConstant(0, TLI->getPointerTy())));
2888 void SelectionDAGBuilder::visitFPExt(const User &I) {
2889 // FPExt is never a no-op cast, no need to check
2890 SDValue N = getValue(I.getOperand(0));
2891 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2892 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2895 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2896 // FPToUI is never a no-op cast, no need to check
2897 SDValue N = getValue(I.getOperand(0));
2898 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2899 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2902 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2903 // FPToSI is never a no-op cast, no need to check
2904 SDValue N = getValue(I.getOperand(0));
2905 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2906 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2909 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2910 // UIToFP is never a no-op cast, no need to check
2911 SDValue N = getValue(I.getOperand(0));
2912 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2913 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2916 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2917 // SIToFP is never a no-op cast, no need to check
2918 SDValue N = getValue(I.getOperand(0));
2919 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2920 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2923 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2924 // What to do depends on the size of the integer and the size of the pointer.
2925 // We can either truncate, zero extend, or no-op, accordingly.
2926 SDValue N = getValue(I.getOperand(0));
2927 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2928 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2931 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2932 // What to do depends on the size of the integer and the size of the pointer.
2933 // We can either truncate, zero extend, or no-op, accordingly.
2934 SDValue N = getValue(I.getOperand(0));
2935 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2936 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2939 void SelectionDAGBuilder::visitBitCast(const User &I) {
2940 SDValue N = getValue(I.getOperand(0));
2941 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2943 // BitCast assures us that source and destination are the same size so this is
2944 // either a BITCAST or a no-op.
2945 if (DestVT != N.getValueType())
2946 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2947 DestVT, N)); // convert types.
2949 setValue(&I, N); // noop cast.
2952 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2953 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2954 const Value *SV = I.getOperand(0);
2955 SDValue N = getValue(SV);
2956 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2958 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2959 unsigned DestAS = I.getType()->getPointerAddressSpace();
2961 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2962 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2967 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2969 SDValue InVec = getValue(I.getOperand(0));
2970 SDValue InVal = getValue(I.getOperand(1));
2971 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2972 getCurSDLoc(), TLI.getVectorIdxTy());
2973 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2974 TM.getTargetLowering()->getValueType(I.getType()),
2975 InVec, InVal, InIdx));
2978 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2980 SDValue InVec = getValue(I.getOperand(0));
2981 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2982 getCurSDLoc(), TLI.getVectorIdxTy());
2983 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2984 TM.getTargetLowering()->getValueType(I.getType()),
2988 // Utility for visitShuffleVector - Return true if every element in Mask,
2989 // beginning from position Pos and ending in Pos+Size, falls within the
2990 // specified sequential range [L, L+Pos). or is undef.
2991 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2992 unsigned Pos, unsigned Size, int Low) {
2993 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2994 if (Mask[i] >= 0 && Mask[i] != Low)
2999 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3000 SDValue Src1 = getValue(I.getOperand(0));
3001 SDValue Src2 = getValue(I.getOperand(1));
3003 SmallVector<int, 8> Mask;
3004 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3005 unsigned MaskNumElts = Mask.size();
3007 const TargetLowering *TLI = TM.getTargetLowering();
3008 EVT VT = TLI->getValueType(I.getType());
3009 EVT SrcVT = Src1.getValueType();
3010 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3012 if (SrcNumElts == MaskNumElts) {
3013 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3018 // Normalize the shuffle vector since mask and vector length don't match.
3019 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3020 // Mask is longer than the source vectors and is a multiple of the source
3021 // vectors. We can use concatenate vector to make the mask and vectors
3023 if (SrcNumElts*2 == MaskNumElts) {
3024 // First check for Src1 in low and Src2 in high
3025 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3026 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3027 // The shuffle is concatenating two vectors together.
3028 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3032 // Then check for Src2 in low and Src1 in high
3033 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3034 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3035 // The shuffle is concatenating two vectors together.
3036 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3042 // Pad both vectors with undefs to make them the same length as the mask.
3043 unsigned NumConcat = MaskNumElts / SrcNumElts;
3044 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3045 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3046 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3048 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3049 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3053 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3055 &MOps1[0], NumConcat);
3056 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3058 &MOps2[0], NumConcat);
3060 // Readjust mask for new input vector length.
3061 SmallVector<int, 8> MappedOps;
3062 for (unsigned i = 0; i != MaskNumElts; ++i) {
3064 if (Idx >= (int)SrcNumElts)
3065 Idx -= SrcNumElts - MaskNumElts;
3066 MappedOps.push_back(Idx);
3069 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3074 if (SrcNumElts > MaskNumElts) {
3075 // Analyze the access pattern of the vector to see if we can extract
3076 // two subvectors and do the shuffle. The analysis is done by calculating
3077 // the range of elements the mask access on both vectors.
3078 int MinRange[2] = { static_cast<int>(SrcNumElts),
3079 static_cast<int>(SrcNumElts)};
3080 int MaxRange[2] = {-1, -1};
3082 for (unsigned i = 0; i != MaskNumElts; ++i) {
3088 if (Idx >= (int)SrcNumElts) {
3092 if (Idx > MaxRange[Input])
3093 MaxRange[Input] = Idx;
3094 if (Idx < MinRange[Input])
3095 MinRange[Input] = Idx;
3098 // Check if the access is smaller than the vector size and can we find
3099 // a reasonable extract index.
3100 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3102 int StartIdx[2]; // StartIdx to extract from
3103 for (unsigned Input = 0; Input < 2; ++Input) {
3104 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3105 RangeUse[Input] = 0; // Unused
3106 StartIdx[Input] = 0;
3110 // Find a good start index that is a multiple of the mask length. Then
3111 // see if the rest of the elements are in range.
3112 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3113 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3114 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3115 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3118 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3119 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3122 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3123 // Extract appropriate subvector and generate a vector shuffle
3124 for (unsigned Input = 0; Input < 2; ++Input) {
3125 SDValue &Src = Input == 0 ? Src1 : Src2;
3126 if (RangeUse[Input] == 0)
3127 Src = DAG.getUNDEF(VT);
3129 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3130 Src, DAG.getConstant(StartIdx[Input],
3131 TLI->getVectorIdxTy()));
3134 // Calculate new mask.
3135 SmallVector<int, 8> MappedOps;
3136 for (unsigned i = 0; i != MaskNumElts; ++i) {
3139 if (Idx < (int)SrcNumElts)
3142 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3144 MappedOps.push_back(Idx);
3147 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3153 // We can't use either concat vectors or extract subvectors so fall back to
3154 // replacing the shuffle with extract and build vector.
3155 // to insert and build vector.
3156 EVT EltVT = VT.getVectorElementType();
3157 EVT IdxVT = TLI->getVectorIdxTy();
3158 SmallVector<SDValue,8> Ops;
3159 for (unsigned i = 0; i != MaskNumElts; ++i) {
3164 Res = DAG.getUNDEF(EltVT);
3166 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3167 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3169 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3170 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3176 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3177 VT, &Ops[0], Ops.size()));
3180 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3181 const Value *Op0 = I.getOperand(0);
3182 const Value *Op1 = I.getOperand(1);
3183 Type *AggTy = I.getType();
3184 Type *ValTy = Op1->getType();
3185 bool IntoUndef = isa<UndefValue>(Op0);
3186 bool FromUndef = isa<UndefValue>(Op1);
3188 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3190 const TargetLowering *TLI = TM.getTargetLowering();
3191 SmallVector<EVT, 4> AggValueVTs;
3192 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3193 SmallVector<EVT, 4> ValValueVTs;
3194 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3196 unsigned NumAggValues = AggValueVTs.size();
3197 unsigned NumValValues = ValValueVTs.size();
3198 SmallVector<SDValue, 4> Values(NumAggValues);
3200 SDValue Agg = getValue(Op0);
3202 // Copy the beginning value(s) from the original aggregate.
3203 for (; i != LinearIndex; ++i)
3204 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3205 SDValue(Agg.getNode(), Agg.getResNo() + i);
3206 // Copy values from the inserted value(s).
3208 SDValue Val = getValue(Op1);
3209 for (; i != LinearIndex + NumValValues; ++i)
3210 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3211 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3213 // Copy remaining value(s) from the original aggregate.
3214 for (; i != NumAggValues; ++i)
3215 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3216 SDValue(Agg.getNode(), Agg.getResNo() + i);
3218 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3219 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3220 &Values[0], NumAggValues));
3223 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3224 const Value *Op0 = I.getOperand(0);
3225 Type *AggTy = Op0->getType();
3226 Type *ValTy = I.getType();
3227 bool OutOfUndef = isa<UndefValue>(Op0);
3229 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3231 const TargetLowering *TLI = TM.getTargetLowering();
3232 SmallVector<EVT, 4> ValValueVTs;
3233 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3235 unsigned NumValValues = ValValueVTs.size();
3237 // Ignore a extractvalue that produces an empty object
3238 if (!NumValValues) {
3239 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3243 SmallVector<SDValue, 4> Values(NumValValues);
3245 SDValue Agg = getValue(Op0);
3246 // Copy out the selected value(s).
3247 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3248 Values[i - LinearIndex] =
3250 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3251 SDValue(Agg.getNode(), Agg.getResNo() + i);
3253 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3254 DAG.getVTList(&ValValueVTs[0], NumValValues),
3255 &Values[0], NumValValues));
3258 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3259 Value *Op0 = I.getOperand(0);
3260 // Note that the pointer operand may be a vector of pointers. Take the scalar
3261 // element which holds a pointer.
3262 Type *Ty = Op0->getType()->getScalarType();
3263 unsigned AS = Ty->getPointerAddressSpace();
3264 SDValue N = getValue(Op0);
3266 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3268 const Value *Idx = *OI;
3269 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3270 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3273 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3274 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3275 DAG.getConstant(Offset, N.getValueType()));
3278 Ty = StTy->getElementType(Field);
3280 Ty = cast<SequentialType>(Ty)->getElementType();
3282 // If this is a constant subscript, handle it quickly.
3283 const TargetLowering *TLI = TM.getTargetLowering();
3284 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3285 if (CI->isZero()) continue;
3287 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3289 EVT PTy = TLI->getPointerTy(AS);
3290 unsigned PtrBits = PTy.getSizeInBits();
3292 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3293 DAG.getConstant(Offs, MVT::i64));
3295 OffsVal = DAG.getConstant(Offs, PTy);
3297 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3302 // N = N + Idx * ElementSize;
3303 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3304 TD->getTypeAllocSize(Ty));
3305 SDValue IdxN = getValue(Idx);
3307 // If the index is smaller or larger than intptr_t, truncate or extend
3309 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3311 // If this is a multiply by a power of two, turn it into a shl
3312 // immediately. This is a very common case.
3313 if (ElementSize != 1) {
3314 if (ElementSize.isPowerOf2()) {
3315 unsigned Amt = ElementSize.logBase2();
3316 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3317 N.getValueType(), IdxN,
3318 DAG.getConstant(Amt, IdxN.getValueType()));
3320 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3321 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3322 N.getValueType(), IdxN, Scale);
3326 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3327 N.getValueType(), N, IdxN);
3334 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3335 // If this is a fixed sized alloca in the entry block of the function,
3336 // allocate it statically on the stack.
3337 if (FuncInfo.StaticAllocaMap.count(&I))
3338 return; // getValue will auto-populate this.
3340 Type *Ty = I.getAllocatedType();
3341 const TargetLowering *TLI = TM.getTargetLowering();
3342 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3344 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3347 SDValue AllocSize = getValue(I.getArraySize());
3349 EVT IntPtr = TLI->getPointerTy();
3350 if (AllocSize.getValueType() != IntPtr)
3351 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3353 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3355 DAG.getConstant(TySize, IntPtr));
3357 // Handle alignment. If the requested alignment is less than or equal to
3358 // the stack alignment, ignore it. If the size is greater than or equal to
3359 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3360 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3361 if (Align <= StackAlign)
3364 // Round the size of the allocation up to the stack alignment size
3365 // by add SA-1 to the size.
3366 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3367 AllocSize.getValueType(), AllocSize,
3368 DAG.getIntPtrConstant(StackAlign-1));
3370 // Mask out the low bits for alignment purposes.
3371 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3372 AllocSize.getValueType(), AllocSize,
3373 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3375 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3376 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3377 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3380 DAG.setRoot(DSA.getValue(1));
3382 // Inform the Frame Information that we have just allocated a variable-sized
3384 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, &I);
3387 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3389 return visitAtomicLoad(I);
3391 const Value *SV = I.getOperand(0);
3392 SDValue Ptr = getValue(SV);
3394 Type *Ty = I.getType();
3396 bool isVolatile = I.isVolatile();
3397 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3398 bool isInvariant = I.getMetadata("invariant.load") != 0;
3399 unsigned Alignment = I.getAlignment();
3400 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3401 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3403 SmallVector<EVT, 4> ValueVTs;
3404 SmallVector<uint64_t, 4> Offsets;
3405 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3406 unsigned NumValues = ValueVTs.size();
3411 bool ConstantMemory = false;
3412 if (isVolatile || NumValues > MaxParallelChains)
3413 // Serialize volatile loads with other side effects.
3415 else if (AA->pointsToConstantMemory(
3416 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3417 // Do not serialize (non-volatile) loads of constant memory with anything.
3418 Root = DAG.getEntryNode();
3419 ConstantMemory = true;
3421 // Do not serialize non-volatile loads against each other.
3422 Root = DAG.getRoot();
3425 const TargetLowering *TLI = TM.getTargetLowering();
3427 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3429 SmallVector<SDValue, 4> Values(NumValues);
3430 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3432 EVT PtrVT = Ptr.getValueType();
3433 unsigned ChainI = 0;
3434 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3435 // Serializing loads here may result in excessive register pressure, and
3436 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3437 // could recover a bit by hoisting nodes upward in the chain by recognizing
3438 // they are side-effect free or do not alias. The optimizer should really
3439 // avoid this case by converting large object/array copies to llvm.memcpy
3440 // (MaxParallelChains should always remain as failsafe).
3441 if (ChainI == MaxParallelChains) {
3442 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3443 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3444 MVT::Other, &Chains[0], ChainI);
3448 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3450 DAG.getConstant(Offsets[i], PtrVT));
3451 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3452 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3453 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3457 Chains[ChainI] = L.getValue(1);
3460 if (!ConstantMemory) {
3461 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3462 MVT::Other, &Chains[0], ChainI);
3466 PendingLoads.push_back(Chain);
3469 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3470 DAG.getVTList(&ValueVTs[0], NumValues),
3471 &Values[0], NumValues));
3474 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3476 return visitAtomicStore(I);
3478 const Value *SrcV = I.getOperand(0);
3479 const Value *PtrV = I.getOperand(1);
3481 SmallVector<EVT, 4> ValueVTs;
3482 SmallVector<uint64_t, 4> Offsets;
3483 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3484 unsigned NumValues = ValueVTs.size();
3488 // Get the lowered operands. Note that we do this after
3489 // checking if NumResults is zero, because with zero results
3490 // the operands won't have values in the map.
3491 SDValue Src = getValue(SrcV);
3492 SDValue Ptr = getValue(PtrV);
3494 SDValue Root = getRoot();
3495 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3497 EVT PtrVT = Ptr.getValueType();
3498 bool isVolatile = I.isVolatile();
3499 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3500 unsigned Alignment = I.getAlignment();
3501 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3503 unsigned ChainI = 0;
3504 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3505 // See visitLoad comments.
3506 if (ChainI == MaxParallelChains) {
3507 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3508 MVT::Other, &Chains[0], ChainI);
3512 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3513 DAG.getConstant(Offsets[i], PtrVT));
3514 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3515 SDValue(Src.getNode(), Src.getResNo() + i),
3516 Add, MachinePointerInfo(PtrV, Offsets[i]),
3517 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3518 Chains[ChainI] = St;
3521 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3522 MVT::Other, &Chains[0], ChainI);
3523 DAG.setRoot(StoreNode);
3526 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3527 SynchronizationScope Scope,
3528 bool Before, SDLoc dl,
3530 const TargetLowering &TLI) {
3531 // Fence, if necessary
3533 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3535 else if (Order == Acquire || Order == Monotonic)
3538 if (Order == AcquireRelease)
3540 else if (Order == Release || Order == Monotonic)
3545 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3546 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3547 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3550 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3551 SDLoc dl = getCurSDLoc();
3552 AtomicOrdering Order = I.getOrdering();
3553 SynchronizationScope Scope = I.getSynchScope();
3555 SDValue InChain = getRoot();
3557 const TargetLowering *TLI = TM.getTargetLowering();
3558 if (TLI->getInsertFencesForAtomic())
3559 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3563 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3564 getValue(I.getCompareOperand()).getSimpleValueType(),
3566 getValue(I.getPointerOperand()),
3567 getValue(I.getCompareOperand()),
3568 getValue(I.getNewValOperand()),
3569 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3570 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3573 SDValue OutChain = L.getValue(1);
3575 if (TLI->getInsertFencesForAtomic())
3576 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3580 DAG.setRoot(OutChain);
3583 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3584 SDLoc dl = getCurSDLoc();
3586 switch (I.getOperation()) {
3587 default: llvm_unreachable("Unknown atomicrmw operation");
3588 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3589 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3590 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3591 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3592 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3593 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3594 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3595 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3596 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3597 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3598 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3600 AtomicOrdering Order = I.getOrdering();
3601 SynchronizationScope Scope = I.getSynchScope();
3603 SDValue InChain = getRoot();
3605 const TargetLowering *TLI = TM.getTargetLowering();
3606 if (TLI->getInsertFencesForAtomic())
3607 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3611 DAG.getAtomic(NT, dl,
3612 getValue(I.getValOperand()).getSimpleValueType(),
3614 getValue(I.getPointerOperand()),
3615 getValue(I.getValOperand()),
3616 I.getPointerOperand(), 0 /* Alignment */,
3617 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3620 SDValue OutChain = L.getValue(1);
3622 if (TLI->getInsertFencesForAtomic())
3623 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3627 DAG.setRoot(OutChain);
3630 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3631 SDLoc dl = getCurSDLoc();
3632 const TargetLowering *TLI = TM.getTargetLowering();
3635 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3636 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3637 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3640 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3641 SDLoc dl = getCurSDLoc();
3642 AtomicOrdering Order = I.getOrdering();
3643 SynchronizationScope Scope = I.getSynchScope();
3645 SDValue InChain = getRoot();
3647 const TargetLowering *TLI = TM.getTargetLowering();
3648 EVT VT = TLI->getValueType(I.getType());
3650 if (I.getAlignment() < VT.getSizeInBits() / 8)
3651 report_fatal_error("Cannot generate unaligned atomic load");
3653 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3655 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3656 getValue(I.getPointerOperand()),
3657 I.getPointerOperand(), I.getAlignment(),
3658 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3661 SDValue OutChain = L.getValue(1);
3663 if (TLI->getInsertFencesForAtomic())
3664 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3668 DAG.setRoot(OutChain);
3671 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3672 SDLoc dl = getCurSDLoc();
3674 AtomicOrdering Order = I.getOrdering();
3675 SynchronizationScope Scope = I.getSynchScope();
3677 SDValue InChain = getRoot();
3679 const TargetLowering *TLI = TM.getTargetLowering();
3680 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3682 if (I.getAlignment() < VT.getSizeInBits() / 8)
3683 report_fatal_error("Cannot generate unaligned atomic store");
3685 if (TLI->getInsertFencesForAtomic())
3686 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3690 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3692 getValue(I.getPointerOperand()),
3693 getValue(I.getValueOperand()),
3694 I.getPointerOperand(), I.getAlignment(),
3695 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3698 if (TLI->getInsertFencesForAtomic())
3699 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3702 DAG.setRoot(OutChain);
3705 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3707 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3708 unsigned Intrinsic) {
3709 bool HasChain = !I.doesNotAccessMemory();
3710 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3712 // Build the operand list.
3713 SmallVector<SDValue, 8> Ops;
3714 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3716 // We don't need to serialize loads against other loads.
3717 Ops.push_back(DAG.getRoot());
3719 Ops.push_back(getRoot());
3723 // Info is set by getTgtMemInstrinsic
3724 TargetLowering::IntrinsicInfo Info;
3725 const TargetLowering *TLI = TM.getTargetLowering();
3726 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3728 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3729 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3730 Info.opc == ISD::INTRINSIC_W_CHAIN)
3731 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3733 // Add all operands of the call to the operand list.
3734 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3735 SDValue Op = getValue(I.getArgOperand(i));
3739 SmallVector<EVT, 4> ValueVTs;
3740 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3743 ValueVTs.push_back(MVT::Other);
3745 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3749 if (IsTgtIntrinsic) {
3750 // This is target intrinsic that touches memory
3751 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3752 VTs, &Ops[0], Ops.size(),
3754 MachinePointerInfo(Info.ptrVal, Info.offset),
3755 Info.align, Info.vol,
3756 Info.readMem, Info.writeMem);
3757 } else if (!HasChain) {
3758 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3759 VTs, &Ops[0], Ops.size());
3760 } else if (!I.getType()->isVoidTy()) {
3761 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3762 VTs, &Ops[0], Ops.size());
3764 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3765 VTs, &Ops[0], Ops.size());
3769 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3771 PendingLoads.push_back(Chain);
3776 if (!I.getType()->isVoidTy()) {
3777 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3778 EVT VT = TLI->getValueType(PTy);
3779 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3782 setValue(&I, Result);
3786 /// GetSignificand - Get the significand and build it into a floating-point
3787 /// number with exponent of 1:
3789 /// Op = (Op & 0x007fffff) | 0x3f800000;
3791 /// where Op is the hexadecimal representation of floating point value.
3793 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3794 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3795 DAG.getConstant(0x007fffff, MVT::i32));
3796 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3797 DAG.getConstant(0x3f800000, MVT::i32));
3798 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3801 /// GetExponent - Get the exponent:
3803 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3805 /// where Op is the hexadecimal representation of floating point value.
3807 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3809 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3810 DAG.getConstant(0x7f800000, MVT::i32));
3811 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3812 DAG.getConstant(23, TLI.getPointerTy()));
3813 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3814 DAG.getConstant(127, MVT::i32));
3815 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3818 /// getF32Constant - Get 32-bit floating point constant.
3820 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3821 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3825 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3826 /// limited-precision mode.
3827 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3828 const TargetLowering &TLI) {
3829 if (Op.getValueType() == MVT::f32 &&
3830 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3832 // Put the exponent in the right bit position for later addition to the
3835 // #define LOG2OFe 1.4426950f
3836 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3837 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3838 getF32Constant(DAG, 0x3fb8aa3b));
3839 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3841 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3842 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3843 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3845 // IntegerPartOfX <<= 23;
3846 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3847 DAG.getConstant(23, TLI.getPointerTy()));
3849 SDValue TwoToFracPartOfX;
3850 if (LimitFloatPrecision <= 6) {
3851 // For floating-point precision of 6:
3853 // TwoToFractionalPartOfX =
3855 // (0.735607626f + 0.252464424f * x) * x;
3857 // error 0.0144103317, which is 6 bits
3858 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3859 getF32Constant(DAG, 0x3e814304));
3860 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3861 getF32Constant(DAG, 0x3f3c50c8));
3862 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3863 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3864 getF32Constant(DAG, 0x3f7f5e7e));
3865 } else if (LimitFloatPrecision <= 12) {
3866 // For floating-point precision of 12:
3868 // TwoToFractionalPartOfX =
3871 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3873 // 0.000107046256 error, which is 13 to 14 bits
3874 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3875 getF32Constant(DAG, 0x3da235e3));
3876 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3877 getF32Constant(DAG, 0x3e65b8f3));
3878 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3879 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3880 getF32Constant(DAG, 0x3f324b07));
3881 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3882 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3883 getF32Constant(DAG, 0x3f7ff8fd));
3884 } else { // LimitFloatPrecision <= 18
3885 // For floating-point precision of 18:
3887 // TwoToFractionalPartOfX =
3891 // (0.554906021e-1f +
3892 // (0.961591928e-2f +
3893 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3895 // error 2.47208000*10^(-7), which is better than 18 bits
3896 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3897 getF32Constant(DAG, 0x3924b03e));
3898 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3899 getF32Constant(DAG, 0x3ab24b87));
3900 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3901 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3902 getF32Constant(DAG, 0x3c1d8c17));
3903 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3904 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3905 getF32Constant(DAG, 0x3d634a1d));
3906 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3907 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3908 getF32Constant(DAG, 0x3e75fe14));
3909 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3910 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3911 getF32Constant(DAG, 0x3f317234));
3912 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3913 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3914 getF32Constant(DAG, 0x3f800000));
3917 // Add the exponent into the result in integer domain.
3918 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3919 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3920 DAG.getNode(ISD::ADD, dl, MVT::i32,
3921 t13, IntegerPartOfX));
3924 // No special expansion.
3925 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3928 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3929 /// limited-precision mode.
3930 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3931 const TargetLowering &TLI) {
3932 if (Op.getValueType() == MVT::f32 &&
3933 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3934 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3936 // Scale the exponent by log(2) [0.69314718f].
3937 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3938 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3939 getF32Constant(DAG, 0x3f317218));
3941 // Get the significand and build it into a floating-point number with
3943 SDValue X = GetSignificand(DAG, Op1, dl);
3945 SDValue LogOfMantissa;
3946 if (LimitFloatPrecision <= 6) {
3947 // For floating-point precision of 6:
3951 // (1.4034025f - 0.23903021f * x) * x;
3953 // error 0.0034276066, which is better than 8 bits
3954 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3955 getF32Constant(DAG, 0xbe74c456));
3956 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3957 getF32Constant(DAG, 0x3fb3a2b1));
3958 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3959 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3960 getF32Constant(DAG, 0x3f949a29));
3961 } else if (LimitFloatPrecision <= 12) {
3962 // For floating-point precision of 12:
3968 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3970 // error 0.000061011436, which is 14 bits
3971 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3972 getF32Constant(DAG, 0xbd67b6d6));
3973 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3974 getF32Constant(DAG, 0x3ee4f4b8));
3975 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3976 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3977 getF32Constant(DAG, 0x3fbc278b));
3978 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3979 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3980 getF32Constant(DAG, 0x40348e95));
3981 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3982 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3983 getF32Constant(DAG, 0x3fdef31a));
3984 } else { // LimitFloatPrecision <= 18
3985 // For floating-point precision of 18:
3993 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3995 // error 0.0000023660568, which is better than 18 bits
3996 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3997 getF32Constant(DAG, 0xbc91e5ac));
3998 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3999 getF32Constant(DAG, 0x3e4350aa));
4000 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4001 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4002 getF32Constant(DAG, 0x3f60d3e3));
4003 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4004 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4005 getF32Constant(DAG, 0x4011cdf0));
4006 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4007 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4008 getF32Constant(DAG, 0x406cfd1c));
4009 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4010 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4011 getF32Constant(DAG, 0x408797cb));
4012 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4013 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4014 getF32Constant(DAG, 0x4006dcab));
4017 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4020 // No special expansion.
4021 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4024 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4025 /// limited-precision mode.
4026 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4027 const TargetLowering &TLI) {
4028 if (Op.getValueType() == MVT::f32 &&
4029 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4030 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4032 // Get the exponent.
4033 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4035 // Get the significand and build it into a floating-point number with
4037 SDValue X = GetSignificand(DAG, Op1, dl);
4039 // Different possible minimax approximations of significand in
4040 // floating-point for various degrees of accuracy over [1,2].
4041 SDValue Log2ofMantissa;
4042 if (LimitFloatPrecision <= 6) {
4043 // For floating-point precision of 6:
4045 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4047 // error 0.0049451742, which is more than 7 bits
4048 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4049 getF32Constant(DAG, 0xbeb08fe0));
4050 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4051 getF32Constant(DAG, 0x40019463));
4052 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4053 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4054 getF32Constant(DAG, 0x3fd6633d));
4055 } else if (LimitFloatPrecision <= 12) {
4056 // For floating-point precision of 12:
4062 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4064 // error 0.0000876136000, which is better than 13 bits
4065 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4066 getF32Constant(DAG, 0xbda7262e));
4067 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4068 getF32Constant(DAG, 0x3f25280b));
4069 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4070 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4071 getF32Constant(DAG, 0x4007b923));
4072 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4073 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4074 getF32Constant(DAG, 0x40823e2f));
4075 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4076 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4077 getF32Constant(DAG, 0x4020d29c));
4078 } else { // LimitFloatPrecision <= 18
4079 // For floating-point precision of 18:
4088 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4090 // error 0.0000018516, which is better than 18 bits
4091 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4092 getF32Constant(DAG, 0xbcd2769e));
4093 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4094 getF32Constant(DAG, 0x3e8ce0b9));
4095 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4096 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4097 getF32Constant(DAG, 0x3fa22ae7));
4098 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4099 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4100 getF32Constant(DAG, 0x40525723));
4101 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4102 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4103 getF32Constant(DAG, 0x40aaf200));
4104 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4105 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4106 getF32Constant(DAG, 0x40c39dad));
4107 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4108 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4109 getF32Constant(DAG, 0x4042902c));
4112 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4115 // No special expansion.
4116 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4119 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4120 /// limited-precision mode.
4121 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4122 const TargetLowering &TLI) {
4123 if (Op.getValueType() == MVT::f32 &&
4124 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4125 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4127 // Scale the exponent by log10(2) [0.30102999f].
4128 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4129 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4130 getF32Constant(DAG, 0x3e9a209a));
4132 // Get the significand and build it into a floating-point number with
4134 SDValue X = GetSignificand(DAG, Op1, dl);
4136 SDValue Log10ofMantissa;
4137 if (LimitFloatPrecision <= 6) {
4138 // For floating-point precision of 6:
4140 // Log10ofMantissa =
4142 // (0.60948995f - 0.10380950f * x) * x;
4144 // error 0.0014886165, which is 6 bits
4145 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4146 getF32Constant(DAG, 0xbdd49a13));
4147 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4148 getF32Constant(DAG, 0x3f1c0789));
4149 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4150 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4151 getF32Constant(DAG, 0x3f011300));
4152 } else if (LimitFloatPrecision <= 12) {
4153 // For floating-point precision of 12:
4155 // Log10ofMantissa =
4158 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4160 // error 0.00019228036, which is better than 12 bits
4161 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4162 getF32Constant(DAG, 0x3d431f31));
4163 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4164 getF32Constant(DAG, 0x3ea21fb2));
4165 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4166 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4167 getF32Constant(DAG, 0x3f6ae232));
4168 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4169 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4170 getF32Constant(DAG, 0x3f25f7c3));
4171 } else { // LimitFloatPrecision <= 18
4172 // For floating-point precision of 18:
4174 // Log10ofMantissa =
4179 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4181 // error 0.0000037995730, which is better than 18 bits
4182 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4183 getF32Constant(DAG, 0x3c5d51ce));
4184 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4185 getF32Constant(DAG, 0x3e00685a));
4186 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4187 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4188 getF32Constant(DAG, 0x3efb6798));
4189 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4190 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4191 getF32Constant(DAG, 0x3f88d192));
4192 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4193 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4194 getF32Constant(DAG, 0x3fc4316c));
4195 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4196 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4197 getF32Constant(DAG, 0x3f57ce70));
4200 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4203 // No special expansion.
4204 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4207 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4208 /// limited-precision mode.
4209 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4210 const TargetLowering &TLI) {
4211 if (Op.getValueType() == MVT::f32 &&
4212 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4213 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4215 // FractionalPartOfX = x - (float)IntegerPartOfX;
4216 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4217 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4219 // IntegerPartOfX <<= 23;
4220 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4221 DAG.getConstant(23, TLI.getPointerTy()));
4223 SDValue TwoToFractionalPartOfX;
4224 if (LimitFloatPrecision <= 6) {
4225 // For floating-point precision of 6:
4227 // TwoToFractionalPartOfX =
4229 // (0.735607626f + 0.252464424f * x) * x;
4231 // error 0.0144103317, which is 6 bits
4232 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4233 getF32Constant(DAG, 0x3e814304));
4234 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4235 getF32Constant(DAG, 0x3f3c50c8));
4236 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4237 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4238 getF32Constant(DAG, 0x3f7f5e7e));
4239 } else if (LimitFloatPrecision <= 12) {
4240 // For floating-point precision of 12:
4242 // TwoToFractionalPartOfX =
4245 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4247 // error 0.000107046256, which is 13 to 14 bits
4248 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4249 getF32Constant(DAG, 0x3da235e3));
4250 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4251 getF32Constant(DAG, 0x3e65b8f3));
4252 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4253 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4254 getF32Constant(DAG, 0x3f324b07));
4255 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4256 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4257 getF32Constant(DAG, 0x3f7ff8fd));
4258 } else { // LimitFloatPrecision <= 18
4259 // For floating-point precision of 18:
4261 // TwoToFractionalPartOfX =
4265 // (0.554906021e-1f +
4266 // (0.961591928e-2f +
4267 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4268 // error 2.47208000*10^(-7), which is better than 18 bits
4269 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4270 getF32Constant(DAG, 0x3924b03e));
4271 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4272 getF32Constant(DAG, 0x3ab24b87));
4273 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4274 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4275 getF32Constant(DAG, 0x3c1d8c17));
4276 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4277 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4278 getF32Constant(DAG, 0x3d634a1d));
4279 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4280 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4281 getF32Constant(DAG, 0x3e75fe14));
4282 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4283 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4284 getF32Constant(DAG, 0x3f317234));
4285 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4286 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4287 getF32Constant(DAG, 0x3f800000));
4290 // Add the exponent into the result in integer domain.
4291 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4292 TwoToFractionalPartOfX);
4293 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4294 DAG.getNode(ISD::ADD, dl, MVT::i32,
4295 t13, IntegerPartOfX));
4298 // No special expansion.
4299 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4302 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4303 /// limited-precision mode with x == 10.0f.
4304 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4305 SelectionDAG &DAG, const TargetLowering &TLI) {
4306 bool IsExp10 = false;
4307 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4308 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4309 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4311 IsExp10 = LHSC->isExactlyValue(Ten);
4316 // Put the exponent in the right bit position for later addition to the
4319 // #define LOG2OF10 3.3219281f
4320 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4321 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4322 getF32Constant(DAG, 0x40549a78));
4323 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4325 // FractionalPartOfX = x - (float)IntegerPartOfX;
4326 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4327 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4329 // IntegerPartOfX <<= 23;
4330 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4331 DAG.getConstant(23, TLI.getPointerTy()));
4333 SDValue TwoToFractionalPartOfX;
4334 if (LimitFloatPrecision <= 6) {
4335 // For floating-point precision of 6:
4337 // twoToFractionalPartOfX =
4339 // (0.735607626f + 0.252464424f * x) * x;
4341 // error 0.0144103317, which is 6 bits
4342 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4343 getF32Constant(DAG, 0x3e814304));
4344 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4345 getF32Constant(DAG, 0x3f3c50c8));
4346 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4347 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4348 getF32Constant(DAG, 0x3f7f5e7e));
4349 } else if (LimitFloatPrecision <= 12) {
4350 // For floating-point precision of 12:
4352 // TwoToFractionalPartOfX =
4355 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4357 // error 0.000107046256, which is 13 to 14 bits
4358 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4359 getF32Constant(DAG, 0x3da235e3));
4360 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4361 getF32Constant(DAG, 0x3e65b8f3));
4362 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4363 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4364 getF32Constant(DAG, 0x3f324b07));
4365 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4366 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4367 getF32Constant(DAG, 0x3f7ff8fd));
4368 } else { // LimitFloatPrecision <= 18
4369 // For floating-point precision of 18:
4371 // TwoToFractionalPartOfX =
4375 // (0.554906021e-1f +
4376 // (0.961591928e-2f +
4377 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4378 // error 2.47208000*10^(-7), which is better than 18 bits
4379 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4380 getF32Constant(DAG, 0x3924b03e));
4381 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4382 getF32Constant(DAG, 0x3ab24b87));
4383 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4384 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4385 getF32Constant(DAG, 0x3c1d8c17));
4386 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4387 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4388 getF32Constant(DAG, 0x3d634a1d));
4389 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4390 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4391 getF32Constant(DAG, 0x3e75fe14));
4392 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4393 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4394 getF32Constant(DAG, 0x3f317234));
4395 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4396 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4397 getF32Constant(DAG, 0x3f800000));
4400 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4401 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4402 DAG.getNode(ISD::ADD, dl, MVT::i32,
4403 t13, IntegerPartOfX));
4406 // No special expansion.
4407 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4411 /// ExpandPowI - Expand a llvm.powi intrinsic.
4412 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4413 SelectionDAG &DAG) {
4414 // If RHS is a constant, we can expand this out to a multiplication tree,
4415 // otherwise we end up lowering to a call to __powidf2 (for example). When
4416 // optimizing for size, we only want to do this if the expansion would produce
4417 // a small number of multiplies, otherwise we do the full expansion.
4418 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4419 // Get the exponent as a positive value.
4420 unsigned Val = RHSC->getSExtValue();
4421 if ((int)Val < 0) Val = -Val;
4423 // powi(x, 0) -> 1.0
4425 return DAG.getConstantFP(1.0, LHS.getValueType());
4427 const Function *F = DAG.getMachineFunction().getFunction();
4428 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4429 Attribute::OptimizeForSize) ||
4430 // If optimizing for size, don't insert too many multiplies. This
4431 // inserts up to 5 multiplies.
4432 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4433 // We use the simple binary decomposition method to generate the multiply
4434 // sequence. There are more optimal ways to do this (for example,
4435 // powi(x,15) generates one more multiply than it should), but this has
4436 // the benefit of being both really simple and much better than a libcall.
4437 SDValue Res; // Logically starts equal to 1.0
4438 SDValue CurSquare = LHS;
4442 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4444 Res = CurSquare; // 1.0*CurSquare.
4447 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4448 CurSquare, CurSquare);
4452 // If the original was negative, invert the result, producing 1/(x*x*x).
4453 if (RHSC->getSExtValue() < 0)
4454 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4455 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4460 // Otherwise, expand to a libcall.
4461 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4464 // getTruncatedArgReg - Find underlying register used for an truncated
4466 static unsigned getTruncatedArgReg(const SDValue &N) {
4467 if (N.getOpcode() != ISD::TRUNCATE)
4470 const SDValue &Ext = N.getOperand(0);
4471 if (Ext.getOpcode() == ISD::AssertZext ||
4472 Ext.getOpcode() == ISD::AssertSext) {
4473 const SDValue &CFR = Ext.getOperand(0);
4474 if (CFR.getOpcode() == ISD::CopyFromReg)
4475 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4476 if (CFR.getOpcode() == ISD::TRUNCATE)
4477 return getTruncatedArgReg(CFR);
4482 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4483 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4484 /// At the end of instruction selection, they will be inserted to the entry BB.
4486 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4489 const Argument *Arg = dyn_cast<Argument>(V);
4493 MachineFunction &MF = DAG.getMachineFunction();
4494 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4496 // Ignore inlined function arguments here.
4497 DIVariable DV(Variable);
4498 if (DV.isInlinedFnArgument(MF.getFunction()))
4501 Optional<MachineOperand> Op;
4502 // Some arguments' frame index is recorded during argument lowering.
4503 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4504 Op = MachineOperand::CreateFI(FI);
4506 if (!Op && N.getNode()) {
4508 if (N.getOpcode() == ISD::CopyFromReg)
4509 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4511 Reg = getTruncatedArgReg(N);
4512 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4513 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4514 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4519 Op = MachineOperand::CreateReg(Reg, false);
4523 // Check if ValueMap has reg number.
4524 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4525 if (VMI != FuncInfo.ValueMap.end())
4526 Op = MachineOperand::CreateReg(VMI->second, false);
4529 if (!Op && N.getNode())
4530 // Check if frame index is available.
4531 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4532 if (FrameIndexSDNode *FINode =
4533 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4534 Op = MachineOperand::CreateFI(FINode->getIndex());
4539 // FIXME: This does not handle register-indirect values at offset 0.
4540 bool IsIndirect = Offset != 0;
4542 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4543 TII->get(TargetOpcode::DBG_VALUE),
4545 Op->getReg(), Offset, Variable));
4547 FuncInfo.ArgDbgValues.push_back(
4548 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4549 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4554 // VisualStudio defines setjmp as _setjmp
4555 #if defined(_MSC_VER) && defined(setjmp) && \
4556 !defined(setjmp_undefined_for_msvc)
4557 # pragma push_macro("setjmp")
4559 # define setjmp_undefined_for_msvc
4562 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4563 /// we want to emit this as a call to a named external function, return the name
4564 /// otherwise lower it and return null.
4566 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4567 const TargetLowering *TLI = TM.getTargetLowering();
4568 SDLoc sdl = getCurSDLoc();
4569 DebugLoc dl = getCurDebugLoc();
4572 switch (Intrinsic) {
4574 // By default, turn this into a target intrinsic node.
4575 visitTargetIntrinsic(I, Intrinsic);
4577 case Intrinsic::vastart: visitVAStart(I); return 0;
4578 case Intrinsic::vaend: visitVAEnd(I); return 0;
4579 case Intrinsic::vacopy: visitVACopy(I); return 0;
4580 case Intrinsic::returnaddress:
4581 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4582 getValue(I.getArgOperand(0))));
4584 case Intrinsic::frameaddress:
4585 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4586 getValue(I.getArgOperand(0))));
4588 case Intrinsic::setjmp:
4589 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4590 case Intrinsic::longjmp:
4591 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4592 case Intrinsic::memcpy: {
4593 // Assert for address < 256 since we support only user defined address
4595 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4597 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4599 "Unknown address space");
4600 SDValue Op1 = getValue(I.getArgOperand(0));
4601 SDValue Op2 = getValue(I.getArgOperand(1));
4602 SDValue Op3 = getValue(I.getArgOperand(2));
4603 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4605 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4606 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4607 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4608 MachinePointerInfo(I.getArgOperand(0)),
4609 MachinePointerInfo(I.getArgOperand(1))));
4612 case Intrinsic::memset: {
4613 // Assert for address < 256 since we support only user defined address
4615 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4617 "Unknown address space");
4618 SDValue Op1 = getValue(I.getArgOperand(0));
4619 SDValue Op2 = getValue(I.getArgOperand(1));
4620 SDValue Op3 = getValue(I.getArgOperand(2));
4621 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4623 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4624 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4625 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4626 MachinePointerInfo(I.getArgOperand(0))));
4629 case Intrinsic::memmove: {
4630 // Assert for address < 256 since we support only user defined address
4632 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4634 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4636 "Unknown address space");
4637 SDValue Op1 = getValue(I.getArgOperand(0));
4638 SDValue Op2 = getValue(I.getArgOperand(1));
4639 SDValue Op3 = getValue(I.getArgOperand(2));
4640 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4642 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4643 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4644 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4645 MachinePointerInfo(I.getArgOperand(0)),
4646 MachinePointerInfo(I.getArgOperand(1))));
4649 case Intrinsic::dbg_declare: {
4650 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4651 MDNode *Variable = DI.getVariable();
4652 const Value *Address = DI.getAddress();
4653 DIVariable DIVar(Variable);
4654 assert((!DIVar || DIVar.isVariable()) &&
4655 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4656 if (!Address || !DIVar) {
4657 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4661 // Check if address has undef value.
4662 if (isa<UndefValue>(Address) ||
4663 (Address->use_empty() && !isa<Argument>(Address))) {
4664 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4668 SDValue &N = NodeMap[Address];
4669 if (!N.getNode() && isa<Argument>(Address))
4670 // Check unused arguments map.
4671 N = UnusedArgNodeMap[Address];
4674 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4675 Address = BCI->getOperand(0);
4676 // Parameters are handled specially.
4678 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4679 isa<Argument>(Address));
4681 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4683 if (isParameter && !AI) {
4684 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4686 // Byval parameter. We have a frame index at this point.
4687 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4688 0, dl, SDNodeOrder);
4690 // Address is an argument, so try to emit its dbg value using
4691 // virtual register info from the FuncInfo.ValueMap.
4692 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4696 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4697 0, dl, SDNodeOrder);
4699 // Can't do anything with other non-AI cases yet.
4700 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4701 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4702 DEBUG(Address->dump());
4705 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4707 // If Address is an argument then try to emit its dbg value using
4708 // virtual register info from the FuncInfo.ValueMap.
4709 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4710 // If variable is pinned by a alloca in dominating bb then
4711 // use StaticAllocaMap.
4712 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4713 if (AI->getParent() != DI.getParent()) {
4714 DenseMap<const AllocaInst*, int>::iterator SI =
4715 FuncInfo.StaticAllocaMap.find(AI);
4716 if (SI != FuncInfo.StaticAllocaMap.end()) {
4717 SDV = DAG.getDbgValue(Variable, SI->second,
4718 0, dl, SDNodeOrder);
4719 DAG.AddDbgValue(SDV, 0, false);
4724 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4729 case Intrinsic::dbg_value: {
4730 const DbgValueInst &DI = cast<DbgValueInst>(I);
4731 DIVariable DIVar(DI.getVariable());
4732 assert((!DIVar || DIVar.isVariable()) &&
4733 "Variable in DbgValueInst should be either null or a DIVariable.");
4737 MDNode *Variable = DI.getVariable();
4738 uint64_t Offset = DI.getOffset();
4739 const Value *V = DI.getValue();
4744 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4745 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4746 DAG.AddDbgValue(SDV, 0, false);
4748 // Do not use getValue() in here; we don't want to generate code at
4749 // this point if it hasn't been done yet.
4750 SDValue N = NodeMap[V];
4751 if (!N.getNode() && isa<Argument>(V))
4752 // Check unused arguments map.
4753 N = UnusedArgNodeMap[V];
4755 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4756 SDV = DAG.getDbgValue(Variable, N.getNode(),
4757 N.getResNo(), Offset, dl, SDNodeOrder);
4758 DAG.AddDbgValue(SDV, N.getNode(), false);
4760 } else if (!V->use_empty() ) {
4761 // Do not call getValue(V) yet, as we don't want to generate code.
4762 // Remember it for later.
4763 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4764 DanglingDebugInfoMap[V] = DDI;
4766 // We may expand this to cover more cases. One case where we have no
4767 // data available is an unreferenced parameter.
4768 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4772 // Build a debug info table entry.
4773 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4774 V = BCI->getOperand(0);
4775 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4776 // Don't handle byval struct arguments or VLAs, for example.
4778 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4779 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4782 DenseMap<const AllocaInst*, int>::iterator SI =
4783 FuncInfo.StaticAllocaMap.find(AI);
4784 if (SI == FuncInfo.StaticAllocaMap.end())
4786 int FI = SI->second;
4788 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4789 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4790 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4794 case Intrinsic::eh_typeid_for: {
4795 // Find the type id for the given typeinfo.
4796 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4797 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4798 Res = DAG.getConstant(TypeID, MVT::i32);
4803 case Intrinsic::eh_return_i32:
4804 case Intrinsic::eh_return_i64:
4805 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4806 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4809 getValue(I.getArgOperand(0)),
4810 getValue(I.getArgOperand(1))));
4812 case Intrinsic::eh_unwind_init:
4813 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4815 case Intrinsic::eh_dwarf_cfa: {
4816 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4817 TLI->getPointerTy());
4818 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4819 CfaArg.getValueType(),
4820 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4821 CfaArg.getValueType()),
4823 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4824 TLI->getPointerTy(),
4825 DAG.getConstant(0, TLI->getPointerTy()));
4826 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4830 case Intrinsic::eh_sjlj_callsite: {
4831 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4832 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4833 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4834 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4836 MMI.setCurrentCallSite(CI->getZExtValue());
4839 case Intrinsic::eh_sjlj_functioncontext: {
4840 // Get and store the index of the function context.
4841 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4843 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4844 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4845 MFI->setFunctionContextIndex(FI);
4848 case Intrinsic::eh_sjlj_setjmp: {
4851 Ops[1] = getValue(I.getArgOperand(0));
4852 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4853 DAG.getVTList(MVT::i32, MVT::Other),
4855 setValue(&I, Op.getValue(0));
4856 DAG.setRoot(Op.getValue(1));
4859 case Intrinsic::eh_sjlj_longjmp: {
4860 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4861 getRoot(), getValue(I.getArgOperand(0))));
4865 case Intrinsic::x86_mmx_pslli_w:
4866 case Intrinsic::x86_mmx_pslli_d:
4867 case Intrinsic::x86_mmx_pslli_q:
4868 case Intrinsic::x86_mmx_psrli_w:
4869 case Intrinsic::x86_mmx_psrli_d:
4870 case Intrinsic::x86_mmx_psrli_q:
4871 case Intrinsic::x86_mmx_psrai_w:
4872 case Intrinsic::x86_mmx_psrai_d: {
4873 SDValue ShAmt = getValue(I.getArgOperand(1));
4874 if (isa<ConstantSDNode>(ShAmt)) {
4875 visitTargetIntrinsic(I, Intrinsic);
4878 unsigned NewIntrinsic = 0;
4879 EVT ShAmtVT = MVT::v2i32;
4880 switch (Intrinsic) {
4881 case Intrinsic::x86_mmx_pslli_w:
4882 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4884 case Intrinsic::x86_mmx_pslli_d:
4885 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4887 case Intrinsic::x86_mmx_pslli_q:
4888 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4890 case Intrinsic::x86_mmx_psrli_w:
4891 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4893 case Intrinsic::x86_mmx_psrli_d:
4894 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4896 case Intrinsic::x86_mmx_psrli_q:
4897 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4899 case Intrinsic::x86_mmx_psrai_w:
4900 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4902 case Intrinsic::x86_mmx_psrai_d:
4903 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4905 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4908 // The vector shift intrinsics with scalars uses 32b shift amounts but
4909 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4911 // We must do this early because v2i32 is not a legal type.
4914 ShOps[1] = DAG.getConstant(0, MVT::i32);
4915 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4916 EVT DestVT = TLI->getValueType(I.getType());
4917 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4918 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4919 DAG.getConstant(NewIntrinsic, MVT::i32),
4920 getValue(I.getArgOperand(0)), ShAmt);
4924 case Intrinsic::x86_avx_vinsertf128_pd_256:
4925 case Intrinsic::x86_avx_vinsertf128_ps_256:
4926 case Intrinsic::x86_avx_vinsertf128_si_256:
4927 case Intrinsic::x86_avx2_vinserti128: {
4928 EVT DestVT = TLI->getValueType(I.getType());
4929 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4930 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4931 ElVT.getVectorNumElements();
4932 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4933 getValue(I.getArgOperand(0)),
4934 getValue(I.getArgOperand(1)),
4935 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4939 case Intrinsic::x86_avx_vextractf128_pd_256:
4940 case Intrinsic::x86_avx_vextractf128_ps_256:
4941 case Intrinsic::x86_avx_vextractf128_si_256:
4942 case Intrinsic::x86_avx2_vextracti128: {
4943 EVT DestVT = TLI->getValueType(I.getType());
4944 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4945 DestVT.getVectorNumElements();
4946 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
4947 getValue(I.getArgOperand(0)),
4948 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4952 case Intrinsic::convertff:
4953 case Intrinsic::convertfsi:
4954 case Intrinsic::convertfui:
4955 case Intrinsic::convertsif:
4956 case Intrinsic::convertuif:
4957 case Intrinsic::convertss:
4958 case Intrinsic::convertsu:
4959 case Intrinsic::convertus:
4960 case Intrinsic::convertuu: {
4961 ISD::CvtCode Code = ISD::CVT_INVALID;
4962 switch (Intrinsic) {
4963 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4964 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4965 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4966 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4967 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4968 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4969 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4970 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4971 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4972 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4974 EVT DestVT = TLI->getValueType(I.getType());
4975 const Value *Op1 = I.getArgOperand(0);
4976 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4977 DAG.getValueType(DestVT),
4978 DAG.getValueType(getValue(Op1).getValueType()),
4979 getValue(I.getArgOperand(1)),
4980 getValue(I.getArgOperand(2)),
4985 case Intrinsic::powi:
4986 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4987 getValue(I.getArgOperand(1)), DAG));
4989 case Intrinsic::log:
4990 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4992 case Intrinsic::log2:
4993 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4995 case Intrinsic::log10:
4996 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
4998 case Intrinsic::exp:
4999 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5001 case Intrinsic::exp2:
5002 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5004 case Intrinsic::pow:
5005 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5006 getValue(I.getArgOperand(1)), DAG, *TLI));
5008 case Intrinsic::sqrt:
5009 case Intrinsic::fabs:
5010 case Intrinsic::sin:
5011 case Intrinsic::cos:
5012 case Intrinsic::floor:
5013 case Intrinsic::ceil:
5014 case Intrinsic::trunc:
5015 case Intrinsic::rint:
5016 case Intrinsic::nearbyint:
5017 case Intrinsic::round: {
5019 switch (Intrinsic) {
5020 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5021 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5022 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5023 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5024 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5025 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5026 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5027 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5028 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5029 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5030 case Intrinsic::round: Opcode = ISD::FROUND; break;
5033 setValue(&I, DAG.getNode(Opcode, sdl,
5034 getValue(I.getArgOperand(0)).getValueType(),
5035 getValue(I.getArgOperand(0))));
5038 case Intrinsic::copysign:
5039 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5040 getValue(I.getArgOperand(0)).getValueType(),
5041 getValue(I.getArgOperand(0)),
5042 getValue(I.getArgOperand(1))));
5044 case Intrinsic::fma:
5045 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5046 getValue(I.getArgOperand(0)).getValueType(),
5047 getValue(I.getArgOperand(0)),
5048 getValue(I.getArgOperand(1)),
5049 getValue(I.getArgOperand(2))));
5051 case Intrinsic::fmuladd: {
5052 EVT VT = TLI->getValueType(I.getType());
5053 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5054 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5055 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5056 getValue(I.getArgOperand(0)).getValueType(),
5057 getValue(I.getArgOperand(0)),
5058 getValue(I.getArgOperand(1)),
5059 getValue(I.getArgOperand(2))));
5061 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5062 getValue(I.getArgOperand(0)).getValueType(),
5063 getValue(I.getArgOperand(0)),
5064 getValue(I.getArgOperand(1)));
5065 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5066 getValue(I.getArgOperand(0)).getValueType(),
5068 getValue(I.getArgOperand(2)));
5073 case Intrinsic::convert_to_fp16:
5074 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
5075 MVT::i16, getValue(I.getArgOperand(0))));
5077 case Intrinsic::convert_from_fp16:
5078 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
5079 MVT::f32, getValue(I.getArgOperand(0))));
5081 case Intrinsic::pcmarker: {
5082 SDValue Tmp = getValue(I.getArgOperand(0));
5083 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5086 case Intrinsic::readcyclecounter: {
5087 SDValue Op = getRoot();
5088 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5089 DAG.getVTList(MVT::i64, MVT::Other),
5092 DAG.setRoot(Res.getValue(1));
5095 case Intrinsic::bswap:
5096 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5097 getValue(I.getArgOperand(0)).getValueType(),
5098 getValue(I.getArgOperand(0))));
5100 case Intrinsic::cttz: {
5101 SDValue Arg = getValue(I.getArgOperand(0));
5102 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5103 EVT Ty = Arg.getValueType();
5104 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5108 case Intrinsic::ctlz: {
5109 SDValue Arg = getValue(I.getArgOperand(0));
5110 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5111 EVT Ty = Arg.getValueType();
5112 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5116 case Intrinsic::ctpop: {
5117 SDValue Arg = getValue(I.getArgOperand(0));
5118 EVT Ty = Arg.getValueType();
5119 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5122 case Intrinsic::stacksave: {
5123 SDValue Op = getRoot();
5124 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5125 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5127 DAG.setRoot(Res.getValue(1));
5130 case Intrinsic::stackrestore: {
5131 Res = getValue(I.getArgOperand(0));
5132 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5135 case Intrinsic::stackprotector: {
5136 // Emit code into the DAG to store the stack guard onto the stack.
5137 MachineFunction &MF = DAG.getMachineFunction();
5138 MachineFrameInfo *MFI = MF.getFrameInfo();
5139 EVT PtrTy = TLI->getPointerTy();
5141 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5142 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5144 int FI = FuncInfo.StaticAllocaMap[Slot];
5145 MFI->setStackProtectorIndex(FI);
5147 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5149 // Store the stack protector onto the stack.
5150 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5151 MachinePointerInfo::getFixedStack(FI),
5157 case Intrinsic::objectsize: {
5158 // If we don't know by now, we're never going to know.
5159 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5161 assert(CI && "Non-constant type in __builtin_object_size?");
5163 SDValue Arg = getValue(I.getCalledValue());
5164 EVT Ty = Arg.getValueType();
5167 Res = DAG.getConstant(-1ULL, Ty);
5169 Res = DAG.getConstant(0, Ty);
5174 case Intrinsic::annotation:
5175 case Intrinsic::ptr_annotation:
5176 // Drop the intrinsic, but forward the value
5177 setValue(&I, getValue(I.getOperand(0)));
5179 case Intrinsic::var_annotation:
5180 // Discard annotate attributes
5183 case Intrinsic::init_trampoline: {
5184 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5188 Ops[1] = getValue(I.getArgOperand(0));
5189 Ops[2] = getValue(I.getArgOperand(1));
5190 Ops[3] = getValue(I.getArgOperand(2));
5191 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5192 Ops[5] = DAG.getSrcValue(F);
5194 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5199 case Intrinsic::adjust_trampoline: {
5200 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5201 TLI->getPointerTy(),
5202 getValue(I.getArgOperand(0))));
5205 case Intrinsic::gcroot:
5207 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5208 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5210 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5211 GFI->addStackRoot(FI->getIndex(), TypeMap);
5214 case Intrinsic::gcread:
5215 case Intrinsic::gcwrite:
5216 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5217 case Intrinsic::flt_rounds:
5218 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5221 case Intrinsic::expect: {
5222 // Just replace __builtin_expect(exp, c) with EXP.
5223 setValue(&I, getValue(I.getArgOperand(0)));
5227 case Intrinsic::debugtrap:
5228 case Intrinsic::trap: {
5229 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5230 if (TrapFuncName.empty()) {
5231 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5232 ISD::TRAP : ISD::DEBUGTRAP;
5233 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5236 TargetLowering::ArgListTy Args;
5238 CallLoweringInfo CLI(getRoot(), I.getType(),
5239 false, false, false, false, 0, CallingConv::C,
5240 /*isTailCall=*/false,
5241 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5242 DAG.getExternalSymbol(TrapFuncName.data(),
5243 TLI->getPointerTy()),
5245 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5246 DAG.setRoot(Result.second);
5250 case Intrinsic::uadd_with_overflow:
5251 case Intrinsic::sadd_with_overflow:
5252 case Intrinsic::usub_with_overflow:
5253 case Intrinsic::ssub_with_overflow:
5254 case Intrinsic::umul_with_overflow:
5255 case Intrinsic::smul_with_overflow: {
5257 switch (Intrinsic) {
5258 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5259 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5260 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5261 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5262 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5263 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5264 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5266 SDValue Op1 = getValue(I.getArgOperand(0));
5267 SDValue Op2 = getValue(I.getArgOperand(1));
5269 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5270 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5273 case Intrinsic::prefetch: {
5275 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5277 Ops[1] = getValue(I.getArgOperand(0));
5278 Ops[2] = getValue(I.getArgOperand(1));
5279 Ops[3] = getValue(I.getArgOperand(2));
5280 Ops[4] = getValue(I.getArgOperand(3));
5281 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5282 DAG.getVTList(MVT::Other),
5284 EVT::getIntegerVT(*Context, 8),
5285 MachinePointerInfo(I.getArgOperand(0)),
5287 false, /* volatile */
5289 rw==1)); /* write */
5292 case Intrinsic::lifetime_start:
5293 case Intrinsic::lifetime_end: {
5294 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5295 // Stack coloring is not enabled in O0, discard region information.
5296 if (TM.getOptLevel() == CodeGenOpt::None)
5299 SmallVector<Value *, 4> Allocas;
5300 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5302 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5303 E = Allocas.end(); Object != E; ++Object) {
5304 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5306 // Could not find an Alloca.
5307 if (!LifetimeObject)
5310 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5314 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5315 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5317 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5322 case Intrinsic::invariant_start:
5323 // Discard region information.
5324 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5326 case Intrinsic::invariant_end:
5327 // Discard region information.
5329 case Intrinsic::stackprotectorcheck: {
5330 // Do not actually emit anything for this basic block. Instead we initialize
5331 // the stack protector descriptor and export the guard variable so we can
5332 // access it in FinishBasicBlock.
5333 const BasicBlock *BB = I.getParent();
5334 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5335 ExportFromCurrentBlock(SPDescriptor.getGuard());
5337 // Flush our exports since we are going to process a terminator.
5338 (void)getControlRoot();
5341 case Intrinsic::donothing:
5344 case Intrinsic::experimental_stackmap: {
5348 case Intrinsic::experimental_patchpoint_void:
5349 case Intrinsic::experimental_patchpoint_i64: {
5356 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5358 MachineBasicBlock *LandingPad) {
5359 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5360 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5361 Type *RetTy = FTy->getReturnType();
5362 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5363 MCSymbol *BeginLabel = 0;
5365 TargetLowering::ArgListTy Args;
5366 TargetLowering::ArgListEntry Entry;
5367 Args.reserve(CS.arg_size());
5369 // Check whether the function can return without sret-demotion.
5370 SmallVector<ISD::OutputArg, 4> Outs;
5371 const TargetLowering *TLI = TM.getTargetLowering();
5372 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5374 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5375 DAG.getMachineFunction(),
5376 FTy->isVarArg(), Outs,
5379 SDValue DemoteStackSlot;
5380 int DemoteStackIdx = -100;
5382 if (!CanLowerReturn) {
5383 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5384 FTy->getReturnType());
5385 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5386 FTy->getReturnType());
5387 MachineFunction &MF = DAG.getMachineFunction();
5388 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5389 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5391 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5392 Entry.Node = DemoteStackSlot;
5393 Entry.Ty = StackSlotPtrType;
5394 Entry.isSExt = false;
5395 Entry.isZExt = false;
5396 Entry.isInReg = false;
5397 Entry.isSRet = true;
5398 Entry.isNest = false;
5399 Entry.isByVal = false;
5400 Entry.isReturned = false;
5401 Entry.Alignment = Align;
5402 Args.push_back(Entry);
5403 RetTy = Type::getVoidTy(FTy->getContext());
5406 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5408 const Value *V = *i;
5411 if (V->getType()->isEmptyTy())
5414 SDValue ArgNode = getValue(V);
5415 Entry.Node = ArgNode; Entry.Ty = V->getType();
5417 // Skip the first return-type Attribute to get to params.
5418 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5419 Args.push_back(Entry);
5423 // Insert a label before the invoke call to mark the try range. This can be
5424 // used to detect deletion of the invoke via the MachineModuleInfo.
5425 BeginLabel = MMI.getContext().CreateTempSymbol();
5427 // For SjLj, keep track of which landing pads go with which invokes
5428 // so as to maintain the ordering of pads in the LSDA.
5429 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5430 if (CallSiteIndex) {
5431 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5432 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5434 // Now that the call site is handled, stop tracking it.
5435 MMI.setCurrentCallSite(0);
5438 // Both PendingLoads and PendingExports must be flushed here;
5439 // this call might not return.
5441 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5444 // Check if target-independent constraints permit a tail call here.
5445 // Target-dependent constraints are checked within TLI->LowerCallTo.
5446 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5450 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5452 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5453 assert((isTailCall || Result.second.getNode()) &&
5454 "Non-null chain expected with non-tail call!");
5455 assert((Result.second.getNode() || !Result.first.getNode()) &&
5456 "Null value expected with tail call!");
5457 if (Result.first.getNode()) {
5458 setValue(CS.getInstruction(), Result.first);
5459 } else if (!CanLowerReturn && Result.second.getNode()) {
5460 // The instruction result is the result of loading from the
5461 // hidden sret parameter.
5462 SmallVector<EVT, 1> PVTs;
5463 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5465 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5466 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5467 EVT PtrVT = PVTs[0];
5469 SmallVector<EVT, 4> RetTys;
5470 SmallVector<uint64_t, 4> Offsets;
5471 RetTy = FTy->getReturnType();
5472 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5474 unsigned NumValues = RetTys.size();
5475 SmallVector<SDValue, 4> Values(NumValues);
5476 SmallVector<SDValue, 4> Chains(NumValues);
5478 for (unsigned i = 0; i < NumValues; ++i) {
5479 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5481 DAG.getConstant(Offsets[i], PtrVT));
5482 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5483 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5484 false, false, false, 1);
5486 Chains[i] = L.getValue(1);
5489 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5490 MVT::Other, &Chains[0], NumValues);
5491 PendingLoads.push_back(Chain);
5493 setValue(CS.getInstruction(),
5494 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5495 DAG.getVTList(&RetTys[0], RetTys.size()),
5496 &Values[0], Values.size()));
5499 if (!Result.second.getNode()) {
5500 // As a special case, a null chain means that a tail call has been emitted
5501 // and the DAG root is already updated.
5504 // Since there's no actual continuation from this block, nothing can be
5505 // relying on us setting vregs for them.
5506 PendingExports.clear();
5508 DAG.setRoot(Result.second);
5512 // Insert a label at the end of the invoke call to mark the try range. This
5513 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5514 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5515 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5517 // Inform MachineModuleInfo of range.
5518 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5522 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5523 /// value is equal or not-equal to zero.
5524 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5525 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5527 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5528 if (IC->isEquality())
5529 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5530 if (C->isNullValue())
5532 // Unknown instruction.
5538 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5540 SelectionDAGBuilder &Builder) {
5542 // Check to see if this load can be trivially constant folded, e.g. if the
5543 // input is from a string literal.
5544 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5545 // Cast pointer to the type we really want to load.
5546 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5547 PointerType::getUnqual(LoadTy));
5549 if (const Constant *LoadCst =
5550 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5552 return Builder.getValue(LoadCst);
5555 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5556 // still constant memory, the input chain can be the entry node.
5558 bool ConstantMemory = false;
5560 // Do not serialize (non-volatile) loads of constant memory with anything.
5561 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5562 Root = Builder.DAG.getEntryNode();
5563 ConstantMemory = true;
5565 // Do not serialize non-volatile loads against each other.
5566 Root = Builder.DAG.getRoot();
5569 SDValue Ptr = Builder.getValue(PtrVal);
5570 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5571 Ptr, MachinePointerInfo(PtrVal),
5573 false /*nontemporal*/,
5574 false /*isinvariant*/, 1 /* align=1 */);
5576 if (!ConstantMemory)
5577 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5581 /// processIntegerCallValue - Record the value for an instruction that
5582 /// produces an integer result, converting the type where necessary.
5583 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5586 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true);
5588 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5590 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5591 setValue(&I, Value);
5594 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5595 /// If so, return true and lower it, otherwise return false and it will be
5596 /// lowered like a normal call.
5597 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5598 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5599 if (I.getNumArgOperands() != 3)
5602 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5603 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5604 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5605 !I.getType()->isIntegerTy())
5608 const Value *Size = I.getArgOperand(2);
5609 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5610 if (CSize && CSize->getZExtValue() == 0) {
5611 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true);
5612 setValue(&I, DAG.getConstant(0, CallVT));
5616 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5617 std::pair<SDValue, SDValue> Res =
5618 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5619 getValue(LHS), getValue(RHS), getValue(Size),
5620 MachinePointerInfo(LHS),
5621 MachinePointerInfo(RHS));
5622 if (Res.first.getNode()) {
5623 processIntegerCallValue(I, Res.first, true);
5624 PendingLoads.push_back(Res.second);
5628 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5629 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5630 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5631 bool ActuallyDoIt = true;
5634 switch (CSize->getZExtValue()) {
5636 LoadVT = MVT::Other;
5638 ActuallyDoIt = false;
5642 LoadTy = Type::getInt16Ty(CSize->getContext());
5646 LoadTy = Type::getInt32Ty(CSize->getContext());
5650 LoadTy = Type::getInt64Ty(CSize->getContext());
5654 LoadVT = MVT::v4i32;
5655 LoadTy = Type::getInt32Ty(CSize->getContext());
5656 LoadTy = VectorType::get(LoadTy, 4);
5661 // This turns into unaligned loads. We only do this if the target natively
5662 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5663 // we'll only produce a small number of byte loads.
5665 // Require that we can find a legal MVT, and only do this if the target
5666 // supports unaligned loads of that type. Expanding into byte loads would
5668 const TargetLowering *TLI = TM.getTargetLowering();
5669 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5670 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5671 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5672 if (!TLI->isTypeLegal(LoadVT) ||!TLI->allowsUnalignedMemoryAccesses(LoadVT))
5673 ActuallyDoIt = false;
5677 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5678 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5680 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5682 processIntegerCallValue(I, Res, false);
5691 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5692 /// form. If so, return true and lower it, otherwise return false and it
5693 /// will be lowered like a normal call.
5694 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5695 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5696 if (I.getNumArgOperands() != 3)
5699 const Value *Src = I.getArgOperand(0);
5700 const Value *Char = I.getArgOperand(1);
5701 const Value *Length = I.getArgOperand(2);
5702 if (!Src->getType()->isPointerTy() ||
5703 !Char->getType()->isIntegerTy() ||
5704 !Length->getType()->isIntegerTy() ||
5705 !I.getType()->isPointerTy())
5708 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5709 std::pair<SDValue, SDValue> Res =
5710 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5711 getValue(Src), getValue(Char), getValue(Length),
5712 MachinePointerInfo(Src));
5713 if (Res.first.getNode()) {
5714 setValue(&I, Res.first);
5715 PendingLoads.push_back(Res.second);
5722 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5723 /// optimized form. If so, return true and lower it, otherwise return false
5724 /// and it will be lowered like a normal call.
5725 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5726 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5727 if (I.getNumArgOperands() != 2)
5730 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5731 if (!Arg0->getType()->isPointerTy() ||
5732 !Arg1->getType()->isPointerTy() ||
5733 !I.getType()->isPointerTy())
5736 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5737 std::pair<SDValue, SDValue> Res =
5738 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5739 getValue(Arg0), getValue(Arg1),
5740 MachinePointerInfo(Arg0),
5741 MachinePointerInfo(Arg1), isStpcpy);
5742 if (Res.first.getNode()) {
5743 setValue(&I, Res.first);
5744 DAG.setRoot(Res.second);
5751 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5752 /// If so, return true and lower it, otherwise return false and it will be
5753 /// lowered like a normal call.
5754 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5755 // Verify that the prototype makes sense. int strcmp(void*,void*)
5756 if (I.getNumArgOperands() != 2)
5759 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5760 if (!Arg0->getType()->isPointerTy() ||
5761 !Arg1->getType()->isPointerTy() ||
5762 !I.getType()->isIntegerTy())
5765 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5766 std::pair<SDValue, SDValue> Res =
5767 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5768 getValue(Arg0), getValue(Arg1),
5769 MachinePointerInfo(Arg0),
5770 MachinePointerInfo(Arg1));
5771 if (Res.first.getNode()) {
5772 processIntegerCallValue(I, Res.first, true);
5773 PendingLoads.push_back(Res.second);
5780 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5781 /// form. If so, return true and lower it, otherwise return false and it
5782 /// will be lowered like a normal call.
5783 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5784 // Verify that the prototype makes sense. size_t strlen(char *)
5785 if (I.getNumArgOperands() != 1)
5788 const Value *Arg0 = I.getArgOperand(0);
5789 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5792 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5793 std::pair<SDValue, SDValue> Res =
5794 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5795 getValue(Arg0), MachinePointerInfo(Arg0));
5796 if (Res.first.getNode()) {
5797 processIntegerCallValue(I, Res.first, false);
5798 PendingLoads.push_back(Res.second);
5805 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5806 /// form. If so, return true and lower it, otherwise return false and it
5807 /// will be lowered like a normal call.
5808 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5809 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5810 if (I.getNumArgOperands() != 2)
5813 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5814 if (!Arg0->getType()->isPointerTy() ||
5815 !Arg1->getType()->isIntegerTy() ||
5816 !I.getType()->isIntegerTy())
5819 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5820 std::pair<SDValue, SDValue> Res =
5821 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5822 getValue(Arg0), getValue(Arg1),
5823 MachinePointerInfo(Arg0));
5824 if (Res.first.getNode()) {
5825 processIntegerCallValue(I, Res.first, false);
5826 PendingLoads.push_back(Res.second);
5833 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5834 /// operation (as expected), translate it to an SDNode with the specified opcode
5835 /// and return true.
5836 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5838 // Sanity check that it really is a unary floating-point call.
5839 if (I.getNumArgOperands() != 1 ||
5840 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5841 I.getType() != I.getArgOperand(0)->getType() ||
5842 !I.onlyReadsMemory())
5845 SDValue Tmp = getValue(I.getArgOperand(0));
5846 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5850 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5851 // Handle inline assembly differently.
5852 if (isa<InlineAsm>(I.getCalledValue())) {
5857 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5858 ComputeUsesVAFloatArgument(I, &MMI);
5860 const char *RenameFn = 0;
5861 if (Function *F = I.getCalledFunction()) {
5862 if (F->isDeclaration()) {
5863 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5864 if (unsigned IID = II->getIntrinsicID(F)) {
5865 RenameFn = visitIntrinsicCall(I, IID);
5870 if (unsigned IID = F->getIntrinsicID()) {
5871 RenameFn = visitIntrinsicCall(I, IID);
5877 // Check for well-known libc/libm calls. If the function is internal, it
5878 // can't be a library call.
5880 if (!F->hasLocalLinkage() && F->hasName() &&
5881 LibInfo->getLibFunc(F->getName(), Func) &&
5882 LibInfo->hasOptimizedCodeGen(Func)) {
5885 case LibFunc::copysign:
5886 case LibFunc::copysignf:
5887 case LibFunc::copysignl:
5888 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5889 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5890 I.getType() == I.getArgOperand(0)->getType() &&
5891 I.getType() == I.getArgOperand(1)->getType() &&
5892 I.onlyReadsMemory()) {
5893 SDValue LHS = getValue(I.getArgOperand(0));
5894 SDValue RHS = getValue(I.getArgOperand(1));
5895 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5896 LHS.getValueType(), LHS, RHS));
5901 case LibFunc::fabsf:
5902 case LibFunc::fabsl:
5903 if (visitUnaryFloatCall(I, ISD::FABS))
5909 if (visitUnaryFloatCall(I, ISD::FSIN))
5915 if (visitUnaryFloatCall(I, ISD::FCOS))
5919 case LibFunc::sqrtf:
5920 case LibFunc::sqrtl:
5921 case LibFunc::sqrt_finite:
5922 case LibFunc::sqrtf_finite:
5923 case LibFunc::sqrtl_finite:
5924 if (visitUnaryFloatCall(I, ISD::FSQRT))
5927 case LibFunc::floor:
5928 case LibFunc::floorf:
5929 case LibFunc::floorl:
5930 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5933 case LibFunc::nearbyint:
5934 case LibFunc::nearbyintf:
5935 case LibFunc::nearbyintl:
5936 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5940 case LibFunc::ceilf:
5941 case LibFunc::ceill:
5942 if (visitUnaryFloatCall(I, ISD::FCEIL))
5946 case LibFunc::rintf:
5947 case LibFunc::rintl:
5948 if (visitUnaryFloatCall(I, ISD::FRINT))
5951 case LibFunc::round:
5952 case LibFunc::roundf:
5953 case LibFunc::roundl:
5954 if (visitUnaryFloatCall(I, ISD::FROUND))
5957 case LibFunc::trunc:
5958 case LibFunc::truncf:
5959 case LibFunc::truncl:
5960 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5964 case LibFunc::log2f:
5965 case LibFunc::log2l:
5966 if (visitUnaryFloatCall(I, ISD::FLOG2))
5970 case LibFunc::exp2f:
5971 case LibFunc::exp2l:
5972 if (visitUnaryFloatCall(I, ISD::FEXP2))
5975 case LibFunc::memcmp:
5976 if (visitMemCmpCall(I))
5979 case LibFunc::memchr:
5980 if (visitMemChrCall(I))
5983 case LibFunc::strcpy:
5984 if (visitStrCpyCall(I, false))
5987 case LibFunc::stpcpy:
5988 if (visitStrCpyCall(I, true))
5991 case LibFunc::strcmp:
5992 if (visitStrCmpCall(I))
5995 case LibFunc::strlen:
5996 if (visitStrLenCall(I))
5999 case LibFunc::strnlen:
6000 if (visitStrNLenCall(I))
6009 Callee = getValue(I.getCalledValue());
6011 Callee = DAG.getExternalSymbol(RenameFn,
6012 TM.getTargetLowering()->getPointerTy());
6014 // Check if we can potentially perform a tail call. More detailed checking is
6015 // be done within LowerCallTo, after more information about the call is known.
6016 LowerCallTo(&I, Callee, I.isTailCall());
6021 /// AsmOperandInfo - This contains information for each constraint that we are
6023 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6025 /// CallOperand - If this is the result output operand or a clobber
6026 /// this is null, otherwise it is the incoming operand to the CallInst.
6027 /// This gets modified as the asm is processed.
6028 SDValue CallOperand;
6030 /// AssignedRegs - If this is a register or register class operand, this
6031 /// contains the set of register corresponding to the operand.
6032 RegsForValue AssignedRegs;
6034 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6035 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
6038 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6039 /// corresponds to. If there is no Value* for this operand, it returns
6041 EVT getCallOperandValEVT(LLVMContext &Context,
6042 const TargetLowering &TLI,
6043 const DataLayout *TD) const {
6044 if (CallOperandVal == 0) return MVT::Other;
6046 if (isa<BasicBlock>(CallOperandVal))
6047 return TLI.getPointerTy();
6049 llvm::Type *OpTy = CallOperandVal->getType();
6051 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6052 // If this is an indirect operand, the operand is a pointer to the
6055 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6057 report_fatal_error("Indirect operand for inline asm not a pointer!");
6058 OpTy = PtrTy->getElementType();
6061 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6062 if (StructType *STy = dyn_cast<StructType>(OpTy))
6063 if (STy->getNumElements() == 1)
6064 OpTy = STy->getElementType(0);
6066 // If OpTy is not a single value, it may be a struct/union that we
6067 // can tile with integers.
6068 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6069 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
6078 OpTy = IntegerType::get(Context, BitSize);
6083 return TLI.getValueType(OpTy, true);
6087 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6089 } // end anonymous namespace
6091 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6092 /// specified operand. We prefer to assign virtual registers, to allow the
6093 /// register allocator to handle the assignment process. However, if the asm
6094 /// uses features that we can't model on machineinstrs, we have SDISel do the
6095 /// allocation. This produces generally horrible, but correct, code.
6097 /// OpInfo describes the operand.
6099 static void GetRegistersForValue(SelectionDAG &DAG,
6100 const TargetLowering &TLI,
6102 SDISelAsmOperandInfo &OpInfo) {
6103 LLVMContext &Context = *DAG.getContext();
6105 MachineFunction &MF = DAG.getMachineFunction();
6106 SmallVector<unsigned, 4> Regs;
6108 // If this is a constraint for a single physreg, or a constraint for a
6109 // register class, find it.
6110 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6111 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6112 OpInfo.ConstraintVT);
6114 unsigned NumRegs = 1;
6115 if (OpInfo.ConstraintVT != MVT::Other) {
6116 // If this is a FP input in an integer register (or visa versa) insert a bit
6117 // cast of the input value. More generally, handle any case where the input
6118 // value disagrees with the register class we plan to stick this in.
6119 if (OpInfo.Type == InlineAsm::isInput &&
6120 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6121 // Try to convert to the first EVT that the reg class contains. If the
6122 // types are identical size, use a bitcast to convert (e.g. two differing
6124 MVT RegVT = *PhysReg.second->vt_begin();
6125 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
6126 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6127 RegVT, OpInfo.CallOperand);
6128 OpInfo.ConstraintVT = RegVT;
6129 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6130 // If the input is a FP value and we want it in FP registers, do a
6131 // bitcast to the corresponding integer type. This turns an f64 value
6132 // into i64, which can be passed with two i32 values on a 32-bit
6134 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6135 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6136 RegVT, OpInfo.CallOperand);
6137 OpInfo.ConstraintVT = RegVT;
6141 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6145 EVT ValueVT = OpInfo.ConstraintVT;
6147 // If this is a constraint for a specific physical register, like {r17},
6149 if (unsigned AssignedReg = PhysReg.first) {
6150 const TargetRegisterClass *RC = PhysReg.second;
6151 if (OpInfo.ConstraintVT == MVT::Other)
6152 ValueVT = *RC->vt_begin();
6154 // Get the actual register value type. This is important, because the user
6155 // may have asked for (e.g.) the AX register in i32 type. We need to
6156 // remember that AX is actually i16 to get the right extension.
6157 RegVT = *RC->vt_begin();
6159 // This is a explicit reference to a physical register.
6160 Regs.push_back(AssignedReg);
6162 // If this is an expanded reference, add the rest of the regs to Regs.
6164 TargetRegisterClass::iterator I = RC->begin();
6165 for (; *I != AssignedReg; ++I)
6166 assert(I != RC->end() && "Didn't find reg!");
6168 // Already added the first reg.
6170 for (; NumRegs; --NumRegs, ++I) {
6171 assert(I != RC->end() && "Ran out of registers to allocate!");
6176 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6180 // Otherwise, if this was a reference to an LLVM register class, create vregs
6181 // for this reference.
6182 if (const TargetRegisterClass *RC = PhysReg.second) {
6183 RegVT = *RC->vt_begin();
6184 if (OpInfo.ConstraintVT == MVT::Other)
6187 // Create the appropriate number of virtual registers.
6188 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6189 for (; NumRegs; --NumRegs)
6190 Regs.push_back(RegInfo.createVirtualRegister(RC));
6192 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6196 // Otherwise, we couldn't allocate enough registers for this.
6199 /// visitInlineAsm - Handle a call to an InlineAsm object.
6201 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6202 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6204 /// ConstraintOperands - Information about all of the constraints.
6205 SDISelAsmOperandInfoVector ConstraintOperands;
6207 const TargetLowering *TLI = TM.getTargetLowering();
6208 TargetLowering::AsmOperandInfoVector
6209 TargetConstraints = TLI->ParseConstraints(CS);
6211 bool hasMemory = false;
6213 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6214 unsigned ResNo = 0; // ResNo - The result number of the next output.
6215 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6216 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6217 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6219 MVT OpVT = MVT::Other;
6221 // Compute the value type for each operand.
6222 switch (OpInfo.Type) {
6223 case InlineAsm::isOutput:
6224 // Indirect outputs just consume an argument.
6225 if (OpInfo.isIndirect) {
6226 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6230 // The return value of the call is this value. As such, there is no
6231 // corresponding argument.
6232 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6233 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6234 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6236 assert(ResNo == 0 && "Asm only has one result!");
6237 OpVT = TLI->getSimpleValueType(CS.getType());
6241 case InlineAsm::isInput:
6242 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6244 case InlineAsm::isClobber:
6249 // If this is an input or an indirect output, process the call argument.
6250 // BasicBlocks are labels, currently appearing only in asm's.
6251 if (OpInfo.CallOperandVal) {
6252 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6253 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6255 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6258 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD).
6262 OpInfo.ConstraintVT = OpVT;
6264 // Indirect operand accesses access memory.
6265 if (OpInfo.isIndirect)
6268 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6269 TargetLowering::ConstraintType
6270 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6271 if (CType == TargetLowering::C_Memory) {
6279 SDValue Chain, Flag;
6281 // We won't need to flush pending loads if this asm doesn't touch
6282 // memory and is nonvolatile.
6283 if (hasMemory || IA->hasSideEffects())
6286 Chain = DAG.getRoot();
6288 // Second pass over the constraints: compute which constraint option to use
6289 // and assign registers to constraints that want a specific physreg.
6290 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6291 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6293 // If this is an output operand with a matching input operand, look up the
6294 // matching input. If their types mismatch, e.g. one is an integer, the
6295 // other is floating point, or their sizes are different, flag it as an
6297 if (OpInfo.hasMatchingInput()) {
6298 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6300 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6301 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6302 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6303 OpInfo.ConstraintVT);
6304 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6305 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6306 Input.ConstraintVT);
6307 if ((OpInfo.ConstraintVT.isInteger() !=
6308 Input.ConstraintVT.isInteger()) ||
6309 (MatchRC.second != InputRC.second)) {
6310 report_fatal_error("Unsupported asm: input constraint"
6311 " with a matching output constraint of"
6312 " incompatible type!");
6314 Input.ConstraintVT = OpInfo.ConstraintVT;
6318 // Compute the constraint code and ConstraintType to use.
6319 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6321 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6322 OpInfo.Type == InlineAsm::isClobber)
6325 // If this is a memory input, and if the operand is not indirect, do what we
6326 // need to to provide an address for the memory input.
6327 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6328 !OpInfo.isIndirect) {
6329 assert((OpInfo.isMultipleAlternative ||
6330 (OpInfo.Type == InlineAsm::isInput)) &&
6331 "Can only indirectify direct input operands!");
6333 // Memory operands really want the address of the value. If we don't have
6334 // an indirect input, put it in the constpool if we can, otherwise spill
6335 // it to a stack slot.
6336 // TODO: This isn't quite right. We need to handle these according to
6337 // the addressing mode that the constraint wants. Also, this may take
6338 // an additional register for the computation and we don't want that
6341 // If the operand is a float, integer, or vector constant, spill to a
6342 // constant pool entry to get its address.
6343 const Value *OpVal = OpInfo.CallOperandVal;
6344 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6345 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6346 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6347 TLI->getPointerTy());
6349 // Otherwise, create a stack slot and emit a store to it before the
6351 Type *Ty = OpVal->getType();
6352 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6353 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6354 MachineFunction &MF = DAG.getMachineFunction();
6355 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6356 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6357 Chain = DAG.getStore(Chain, getCurSDLoc(),
6358 OpInfo.CallOperand, StackSlot,
6359 MachinePointerInfo::getFixedStack(SSFI),
6361 OpInfo.CallOperand = StackSlot;
6364 // There is no longer a Value* corresponding to this operand.
6365 OpInfo.CallOperandVal = 0;
6367 // It is now an indirect operand.
6368 OpInfo.isIndirect = true;
6371 // If this constraint is for a specific register, allocate it before
6373 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6374 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6377 // Second pass - Loop over all of the operands, assigning virtual or physregs
6378 // to register class operands.
6379 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6380 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6382 // C_Register operands have already been allocated, Other/Memory don't need
6384 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6385 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6388 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6389 std::vector<SDValue> AsmNodeOperands;
6390 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6391 AsmNodeOperands.push_back(
6392 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6393 TLI->getPointerTy()));
6395 // If we have a !srcloc metadata node associated with it, we want to attach
6396 // this to the ultimately generated inline asm machineinstr. To do this, we
6397 // pass in the third operand as this (potentially null) inline asm MDNode.
6398 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6399 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6401 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6402 // bits as operand 3.
6403 unsigned ExtraInfo = 0;
6404 if (IA->hasSideEffects())
6405 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6406 if (IA->isAlignStack())
6407 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6408 // Set the asm dialect.
6409 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6411 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6412 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6413 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6415 // Compute the constraint code and ConstraintType to use.
6416 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6418 // Ideally, we would only check against memory constraints. However, the
6419 // meaning of an other constraint can be target-specific and we can't easily
6420 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6421 // for other constriants as well.
6422 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6423 OpInfo.ConstraintType == TargetLowering::C_Other) {
6424 if (OpInfo.Type == InlineAsm::isInput)
6425 ExtraInfo |= InlineAsm::Extra_MayLoad;
6426 else if (OpInfo.Type == InlineAsm::isOutput)
6427 ExtraInfo |= InlineAsm::Extra_MayStore;
6428 else if (OpInfo.Type == InlineAsm::isClobber)
6429 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6433 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6434 TLI->getPointerTy()));
6436 // Loop over all of the inputs, copying the operand values into the
6437 // appropriate registers and processing the output regs.
6438 RegsForValue RetValRegs;
6440 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6441 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6443 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6444 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6446 switch (OpInfo.Type) {
6447 case InlineAsm::isOutput: {
6448 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6449 OpInfo.ConstraintType != TargetLowering::C_Register) {
6450 // Memory output, or 'other' output (e.g. 'X' constraint).
6451 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6453 // Add information to the INLINEASM node to know about this output.
6454 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6455 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6456 TLI->getPointerTy()));
6457 AsmNodeOperands.push_back(OpInfo.CallOperand);
6461 // Otherwise, this is a register or register class output.
6463 // Copy the output from the appropriate register. Find a register that
6465 if (OpInfo.AssignedRegs.Regs.empty()) {
6466 LLVMContext &Ctx = *DAG.getContext();
6467 Ctx.emitError(CS.getInstruction(),
6468 "couldn't allocate output register for constraint '" +
6469 Twine(OpInfo.ConstraintCode) + "'");
6473 // If this is an indirect operand, store through the pointer after the
6475 if (OpInfo.isIndirect) {
6476 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6477 OpInfo.CallOperandVal));
6479 // This is the result value of the call.
6480 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6481 // Concatenate this output onto the outputs list.
6482 RetValRegs.append(OpInfo.AssignedRegs);
6485 // Add information to the INLINEASM node to know that this register is
6488 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6489 ? InlineAsm::Kind_RegDefEarlyClobber
6490 : InlineAsm::Kind_RegDef,
6491 false, 0, DAG, AsmNodeOperands);
6494 case InlineAsm::isInput: {
6495 SDValue InOperandVal = OpInfo.CallOperand;
6497 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6498 // If this is required to match an output register we have already set,
6499 // just use its register.
6500 unsigned OperandNo = OpInfo.getMatchedOperand();
6502 // Scan until we find the definition we already emitted of this operand.
6503 // When we find it, create a RegsForValue operand.
6504 unsigned CurOp = InlineAsm::Op_FirstOperand;
6505 for (; OperandNo; --OperandNo) {
6506 // Advance to the next operand.
6508 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6509 assert((InlineAsm::isRegDefKind(OpFlag) ||
6510 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6511 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6512 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6516 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6517 if (InlineAsm::isRegDefKind(OpFlag) ||
6518 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6519 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6520 if (OpInfo.isIndirect) {
6521 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6522 LLVMContext &Ctx = *DAG.getContext();
6523 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6524 " don't know how to handle tied "
6525 "indirect register inputs");
6529 RegsForValue MatchedRegs;
6530 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6531 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6532 MatchedRegs.RegVTs.push_back(RegVT);
6533 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6534 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6536 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6537 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6539 LLVMContext &Ctx = *DAG.getContext();
6540 Ctx.emitError(CS.getInstruction(),
6541 "inline asm error: This value"
6542 " type register class is not natively supported!");
6546 // Use the produced MatchedRegs object to
6547 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6548 Chain, &Flag, CS.getInstruction());
6549 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6550 true, OpInfo.getMatchedOperand(),
6551 DAG, AsmNodeOperands);
6555 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6556 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6557 "Unexpected number of operands");
6558 // Add information to the INLINEASM node to know about this input.
6559 // See InlineAsm.h isUseOperandTiedToDef.
6560 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6561 OpInfo.getMatchedOperand());
6562 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6563 TLI->getPointerTy()));
6564 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6568 // Treat indirect 'X' constraint as memory.
6569 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6571 OpInfo.ConstraintType = TargetLowering::C_Memory;
6573 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6574 std::vector<SDValue> Ops;
6575 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6578 LLVMContext &Ctx = *DAG.getContext();
6579 Ctx.emitError(CS.getInstruction(),
6580 "invalid operand for inline asm constraint '" +
6581 Twine(OpInfo.ConstraintCode) + "'");
6585 // Add information to the INLINEASM node to know about this input.
6586 unsigned ResOpType =
6587 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6588 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6589 TLI->getPointerTy()));
6590 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6594 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6595 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6596 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6597 "Memory operands expect pointer values");
6599 // Add information to the INLINEASM node to know about this input.
6600 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6601 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6602 TLI->getPointerTy()));
6603 AsmNodeOperands.push_back(InOperandVal);
6607 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6608 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6609 "Unknown constraint type!");
6611 // TODO: Support this.
6612 if (OpInfo.isIndirect) {
6613 LLVMContext &Ctx = *DAG.getContext();
6614 Ctx.emitError(CS.getInstruction(),
6615 "Don't know how to handle indirect register inputs yet "
6616 "for constraint '" +
6617 Twine(OpInfo.ConstraintCode) + "'");
6621 // Copy the input into the appropriate registers.
6622 if (OpInfo.AssignedRegs.Regs.empty()) {
6623 LLVMContext &Ctx = *DAG.getContext();
6624 Ctx.emitError(CS.getInstruction(),
6625 "couldn't allocate input reg for constraint '" +
6626 Twine(OpInfo.ConstraintCode) + "'");
6630 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6631 Chain, &Flag, CS.getInstruction());
6633 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6634 DAG, AsmNodeOperands);
6637 case InlineAsm::isClobber: {
6638 // Add the clobbered value to the operand list, so that the register
6639 // allocator is aware that the physreg got clobbered.
6640 if (!OpInfo.AssignedRegs.Regs.empty())
6641 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6649 // Finish up input operands. Set the input chain and add the flag last.
6650 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6651 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6653 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6654 DAG.getVTList(MVT::Other, MVT::Glue),
6655 &AsmNodeOperands[0], AsmNodeOperands.size());
6656 Flag = Chain.getValue(1);
6658 // If this asm returns a register value, copy the result from that register
6659 // and set it as the value of the call.
6660 if (!RetValRegs.Regs.empty()) {
6661 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6662 Chain, &Flag, CS.getInstruction());
6664 // FIXME: Why don't we do this for inline asms with MRVs?
6665 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6666 EVT ResultType = TLI->getValueType(CS.getType());
6668 // If any of the results of the inline asm is a vector, it may have the
6669 // wrong width/num elts. This can happen for register classes that can
6670 // contain multiple different value types. The preg or vreg allocated may
6671 // not have the same VT as was expected. Convert it to the right type
6672 // with bit_convert.
6673 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6674 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6677 } else if (ResultType != Val.getValueType() &&
6678 ResultType.isInteger() && Val.getValueType().isInteger()) {
6679 // If a result value was tied to an input value, the computed result may
6680 // have a wider width than the expected result. Extract the relevant
6682 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6685 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6688 setValue(CS.getInstruction(), Val);
6689 // Don't need to use this as a chain in this case.
6690 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6694 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6696 // Process indirect outputs, first output all of the flagged copies out of
6698 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6699 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6700 const Value *Ptr = IndirectStoresToEmit[i].second;
6701 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6703 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6706 // Emit the non-flagged stores from the physregs.
6707 SmallVector<SDValue, 8> OutChains;
6708 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6709 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6710 StoresToEmit[i].first,
6711 getValue(StoresToEmit[i].second),
6712 MachinePointerInfo(StoresToEmit[i].second),
6714 OutChains.push_back(Val);
6717 if (!OutChains.empty())
6718 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6719 &OutChains[0], OutChains.size());
6724 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6725 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6726 MVT::Other, getRoot(),
6727 getValue(I.getArgOperand(0)),
6728 DAG.getSrcValue(I.getArgOperand(0))));
6731 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6732 const TargetLowering *TLI = TM.getTargetLowering();
6733 const DataLayout &TD = *TLI->getDataLayout();
6734 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6735 getRoot(), getValue(I.getOperand(0)),
6736 DAG.getSrcValue(I.getOperand(0)),
6737 TD.getABITypeAlignment(I.getType()));
6739 DAG.setRoot(V.getValue(1));
6742 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6743 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6744 MVT::Other, getRoot(),
6745 getValue(I.getArgOperand(0)),
6746 DAG.getSrcValue(I.getArgOperand(0))));
6749 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6750 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6751 MVT::Other, getRoot(),
6752 getValue(I.getArgOperand(0)),
6753 getValue(I.getArgOperand(1)),
6754 DAG.getSrcValue(I.getArgOperand(0)),
6755 DAG.getSrcValue(I.getArgOperand(1))));
6758 /// \brief Lower an argument list according to the target calling convention.
6760 /// \return A tuple of <return-value, token-chain>
6762 /// This is a helper for lowering intrinsics that follow a target calling
6763 /// convention or require stack pointer adjustment. Only a subset of the
6764 /// intrinsic's operands need to participate in the calling convention.
6765 std::pair<SDValue, SDValue>
6766 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6767 unsigned NumArgs, SDValue Callee,
6769 TargetLowering::ArgListTy Args;
6770 Args.reserve(NumArgs);
6772 // Populate the argument list.
6773 // Attributes for args start at offset 1, after the return attribute.
6774 ImmutableCallSite CS(&CI);
6775 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6776 ArgI != ArgE; ++ArgI) {
6777 const Value *V = CI.getOperand(ArgI);
6779 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6781 TargetLowering::ArgListEntry Entry;
6782 Entry.Node = getValue(V);
6783 Entry.Ty = V->getType();
6784 Entry.setAttributes(&CS, AttrI);
6785 Args.push_back(Entry);
6788 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6789 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false,
6790 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs,
6791 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false,
6792 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc());
6794 const TargetLowering *TLI = TM.getTargetLowering();
6795 return TLI->LowerCallTo(CLI);
6798 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6799 /// or patchpoint target node's operand list.
6801 /// Constants are converted to TargetConstants purely as an optimization to
6802 /// avoid constant materialization and register allocation.
6804 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6805 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6806 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6807 /// address materialization and register allocation, but may also be required
6808 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6809 /// alloca in the entry block, then the runtime may assume that the alloca's
6810 /// StackMap location can be read immediately after compilation and that the
6811 /// location is valid at any point during execution (this is similar to the
6812 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6813 /// only available in a register, then the runtime would need to trap when
6814 /// execution reaches the StackMap in order to read the alloca's location.
6815 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6816 SmallVectorImpl<SDValue> &Ops,
6817 SelectionDAGBuilder &Builder) {
6818 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6819 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6822 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6824 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6825 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6826 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6828 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6830 Ops.push_back(OpVal);
6834 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6835 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6836 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6837 // [live variables...])
6839 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6841 SDValue Callee = getValue(CI.getCalledValue());
6843 // Lower into a call sequence with no args and no return value.
6844 std::pair<SDValue, SDValue> Result = LowerCallOperands(CI, 0, 0, Callee);
6845 // Set the root to the target-lowered call chain.
6846 SDValue Chain = Result.second;
6849 /// Get a call instruction from the call sequence chain.
6850 /// Tail calls are not allowed.
6851 SDNode *CallEnd = Chain.getNode();
6852 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6853 "Expected a callseq node.");
6854 SDNode *Call = CallEnd->getOperand(0).getNode();
6855 bool hasGlue = Call->getGluedNode();
6857 // Replace the target specific call node with the stackmap intrinsic.
6858 SmallVector<SDValue, 8> Ops;
6860 // Add the <id> and <numShadowBytes> constants.
6861 for (unsigned i = 0; i < 2; ++i) {
6862 SDValue tmp = getValue(CI.getOperand(i));
6863 Ops.push_back(DAG.getTargetConstant(
6864 cast<ConstantSDNode>(tmp)->getZExtValue(), MVT::i32));
6866 // Push live variables for the stack map.
6867 addStackMapLiveVars(CI, 2, Ops, *this);
6869 // Push the chain (this is originally the first operand of the call, but
6870 // becomes now the last or second to last operand).
6871 Ops.push_back(*(Call->op_begin()));
6873 // Push the glue flag (last operand).
6875 Ops.push_back(*(Call->op_end()-1));
6877 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6879 // Replace the target specific call node with a STACKMAP node.
6880 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::STACKMAP, getCurSDLoc(),
6883 // StackMap generates no value, so nothing goes in the NodeMap.
6885 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6887 DAG.ReplaceAllUsesWith(Call, MN);
6889 DAG.DeleteNode(Call);
6891 // Inform the Frame Information that we have a stackmap in this function.
6892 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6895 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6896 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6897 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6902 // [live variables...])
6904 CallingConv::ID CC = CI.getCallingConv();
6905 bool isAnyRegCC = CC == CallingConv::AnyReg;
6906 bool hasDef = !CI.getType()->isVoidTy();
6907 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6909 // Get the real number of arguments participating in the call <numArgs>
6910 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6911 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6913 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6914 // Intrinsics include all meta-operands up to but not including CC.
6915 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6916 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6917 "Not enough arguments provided to the patchpoint intrinsic");
6919 // For AnyRegCC the arguments are lowered later on manually.
6920 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6921 std::pair<SDValue, SDValue> Result =
6922 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6924 // Set the root to the target-lowered call chain.
6925 SDValue Chain = Result.second;
6928 SDNode *CallEnd = Chain.getNode();
6929 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6930 CallEnd = CallEnd->getOperand(0).getNode();
6932 /// Get a call instruction from the call sequence chain.
6933 /// Tail calls are not allowed.
6934 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6935 "Expected a callseq node.");
6936 SDNode *Call = CallEnd->getOperand(0).getNode();
6937 bool hasGlue = Call->getGluedNode();
6939 // Replace the target specific call node with the patchable intrinsic.
6940 SmallVector<SDValue, 8> Ops;
6942 // Add the <id> and <numBytes> constants.
6943 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6944 Ops.push_back(DAG.getTargetConstant(
6945 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6946 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6947 Ops.push_back(DAG.getTargetConstant(
6948 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6950 // Assume that the Callee is a constant address.
6951 // FIXME: handle function symbols in the future.
6953 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
6954 /*isTarget=*/true));
6956 // Adjust <numArgs> to account for any arguments that have been passed on the
6958 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6959 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
6960 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
6961 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
6963 // Add the calling convention
6964 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
6966 // Add the arguments we omitted previously. The register allocator should
6967 // place these in any free register.
6969 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6970 Ops.push_back(getValue(CI.getArgOperand(i)));
6972 // Push the arguments from the call instruction up to the register mask.
6973 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
6974 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
6977 // Push live variables for the stack map.
6978 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
6980 // Push the register mask info.
6982 Ops.push_back(*(Call->op_end()-2));
6984 Ops.push_back(*(Call->op_end()-1));
6986 // Push the chain (this is originally the first operand of the call, but
6987 // becomes now the last or second to last operand).
6988 Ops.push_back(*(Call->op_begin()));
6990 // Push the glue flag (last operand).
6992 Ops.push_back(*(Call->op_end()-1));
6995 if (isAnyRegCC && hasDef) {
6996 // Create the return types based on the intrinsic definition
6997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6998 SmallVector<EVT, 3> ValueVTs;
6999 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7000 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7002 // There is always a chain and a glue type at the end
7003 ValueVTs.push_back(MVT::Other);
7004 ValueVTs.push_back(MVT::Glue);
7005 NodeTys = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
7007 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7009 // Replace the target specific call node with a PATCHPOINT node.
7010 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7011 getCurSDLoc(), NodeTys, Ops);
7013 // Update the NodeMap.
7016 setValue(&CI, SDValue(MN, 0));
7018 setValue(&CI, Result.first);
7021 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7022 // call sequence. Furthermore the location of the chain and glue can change
7023 // when the AnyReg calling convention is used and the intrinsic returns a
7025 if (isAnyRegCC && hasDef) {
7026 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7027 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7028 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7030 DAG.ReplaceAllUsesWith(Call, MN);
7031 DAG.DeleteNode(Call);
7033 // Inform the Frame Information that we have a patchpoint in this function.
7034 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7037 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7038 /// implementation, which just calls LowerCall.
7039 /// FIXME: When all targets are
7040 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7041 std::pair<SDValue, SDValue>
7042 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7043 // Handle the incoming return values from the call.
7045 SmallVector<EVT, 4> RetTys;
7046 ComputeValueVTs(*this, CLI.RetTy, RetTys);
7047 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7049 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7050 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7051 for (unsigned i = 0; i != NumRegs; ++i) {
7052 ISD::InputArg MyFlags;
7053 MyFlags.VT = RegisterVT;
7055 MyFlags.Used = CLI.IsReturnValueUsed;
7057 MyFlags.Flags.setSExt();
7059 MyFlags.Flags.setZExt();
7061 MyFlags.Flags.setInReg();
7062 CLI.Ins.push_back(MyFlags);
7066 // Handle all of the outgoing arguments.
7068 CLI.OutVals.clear();
7069 ArgListTy &Args = CLI.Args;
7070 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7071 SmallVector<EVT, 4> ValueVTs;
7072 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7073 for (unsigned Value = 0, NumValues = ValueVTs.size();
7074 Value != NumValues; ++Value) {
7075 EVT VT = ValueVTs[Value];
7076 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7077 SDValue Op = SDValue(Args[i].Node.getNode(),
7078 Args[i].Node.getResNo() + Value);
7079 ISD::ArgFlagsTy Flags;
7080 unsigned OriginalAlignment =
7081 getDataLayout()->getABITypeAlignment(ArgTy);
7087 if (Args[i].isInReg)
7091 if (Args[i].isByVal) {
7093 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7094 Type *ElementTy = Ty->getElementType();
7095 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7096 // For ByVal, alignment should come from FE. BE will guess if this
7097 // info is not there but there are cases it cannot get right.
7098 unsigned FrameAlign;
7099 if (Args[i].Alignment)
7100 FrameAlign = Args[i].Alignment;
7102 FrameAlign = getByValTypeAlignment(ElementTy);
7103 Flags.setByValAlign(FrameAlign);
7107 Flags.setOrigAlign(OriginalAlignment);
7109 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7110 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7111 SmallVector<SDValue, 4> Parts(NumParts);
7112 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7115 ExtendKind = ISD::SIGN_EXTEND;
7116 else if (Args[i].isZExt)
7117 ExtendKind = ISD::ZERO_EXTEND;
7119 // Conservatively only handle 'returned' on non-vectors for now
7120 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7121 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7122 "unexpected use of 'returned'");
7123 // Before passing 'returned' to the target lowering code, ensure that
7124 // either the register MVT and the actual EVT are the same size or that
7125 // the return value and argument are extended in the same way; in these
7126 // cases it's safe to pass the argument register value unchanged as the
7127 // return register value (although it's at the target's option whether
7129 // TODO: allow code generation to take advantage of partially preserved
7130 // registers rather than clobbering the entire register when the
7131 // parameter extension method is not compatible with the return
7133 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7134 (ExtendKind != ISD::ANY_EXTEND &&
7135 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7136 Flags.setReturned();
7139 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
7140 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
7142 for (unsigned j = 0; j != NumParts; ++j) {
7143 // if it isn't first piece, alignment must be 1
7144 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7145 i < CLI.NumFixedArgs,
7146 i, j*Parts[j].getValueType().getStoreSize());
7147 if (NumParts > 1 && j == 0)
7148 MyFlags.Flags.setSplit();
7150 MyFlags.Flags.setOrigAlign(1);
7152 CLI.Outs.push_back(MyFlags);
7153 CLI.OutVals.push_back(Parts[j]);
7158 SmallVector<SDValue, 4> InVals;
7159 CLI.Chain = LowerCall(CLI, InVals);
7161 // Verify that the target's LowerCall behaved as expected.
7162 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7163 "LowerCall didn't return a valid chain!");
7164 assert((!CLI.IsTailCall || InVals.empty()) &&
7165 "LowerCall emitted a return value for a tail call!");
7166 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7167 "LowerCall didn't emit the correct number of values!");
7169 // For a tail call, the return value is merely live-out and there aren't
7170 // any nodes in the DAG representing it. Return a special value to
7171 // indicate that a tail call has been emitted and no more Instructions
7172 // should be processed in the current block.
7173 if (CLI.IsTailCall) {
7174 CLI.DAG.setRoot(CLI.Chain);
7175 return std::make_pair(SDValue(), SDValue());
7178 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7179 assert(InVals[i].getNode() &&
7180 "LowerCall emitted a null value!");
7181 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7182 "LowerCall emitted a value with the wrong type!");
7185 // Collect the legal value parts into potentially illegal values
7186 // that correspond to the original function's return values.
7187 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7189 AssertOp = ISD::AssertSext;
7190 else if (CLI.RetZExt)
7191 AssertOp = ISD::AssertZext;
7192 SmallVector<SDValue, 4> ReturnValues;
7193 unsigned CurReg = 0;
7194 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7196 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7197 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7199 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7200 NumRegs, RegisterVT, VT, NULL,
7205 // For a function returning void, there is no return value. We can't create
7206 // such a node, so we just return a null return value in that case. In
7207 // that case, nothing will actually look at the value.
7208 if (ReturnValues.empty())
7209 return std::make_pair(SDValue(), CLI.Chain);
7211 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7212 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
7213 &ReturnValues[0], ReturnValues.size());
7214 return std::make_pair(Res, CLI.Chain);
7217 void TargetLowering::LowerOperationWrapper(SDNode *N,
7218 SmallVectorImpl<SDValue> &Results,
7219 SelectionDAG &DAG) const {
7220 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7222 Results.push_back(Res);
7225 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7226 llvm_unreachable("LowerOperation not implemented for this target!");
7230 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7231 SDValue Op = getNonRegisterValue(V);
7232 assert((Op.getOpcode() != ISD::CopyFromReg ||
7233 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7234 "Copy from a reg to the same reg!");
7235 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7237 const TargetLowering *TLI = TM.getTargetLowering();
7238 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7239 SDValue Chain = DAG.getEntryNode();
7240 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
7241 PendingExports.push_back(Chain);
7244 #include "llvm/CodeGen/SelectionDAGISel.h"
7246 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7247 /// entry block, return true. This includes arguments used by switches, since
7248 /// the switch may expand into multiple basic blocks.
7249 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7250 // With FastISel active, we may be splitting blocks, so force creation
7251 // of virtual registers for all non-dead arguments.
7253 return A->use_empty();
7255 const BasicBlock *Entry = A->getParent()->begin();
7256 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
7258 const User *U = *UI;
7259 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7260 return false; // Use not in entry block.
7265 void SelectionDAGISel::LowerArguments(const Function &F) {
7266 SelectionDAG &DAG = SDB->DAG;
7267 SDLoc dl = SDB->getCurSDLoc();
7268 const TargetLowering *TLI = getTargetLowering();
7269 const DataLayout *TD = TLI->getDataLayout();
7270 SmallVector<ISD::InputArg, 16> Ins;
7272 if (!FuncInfo->CanLowerReturn) {
7273 // Put in an sret pointer parameter before all the other parameters.
7274 SmallVector<EVT, 1> ValueVTs;
7275 ComputeValueVTs(*getTargetLowering(),
7276 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7278 // NOTE: Assuming that a pointer will never break down to more than one VT
7280 ISD::ArgFlagsTy Flags;
7282 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7283 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7284 Ins.push_back(RetArg);
7287 // Set up the incoming argument description vector.
7289 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7290 I != E; ++I, ++Idx) {
7291 SmallVector<EVT, 4> ValueVTs;
7292 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7293 bool isArgValueUsed = !I->use_empty();
7294 unsigned PartBase = 0;
7295 for (unsigned Value = 0, NumValues = ValueVTs.size();
7296 Value != NumValues; ++Value) {
7297 EVT VT = ValueVTs[Value];
7298 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7299 ISD::ArgFlagsTy Flags;
7300 unsigned OriginalAlignment =
7301 TD->getABITypeAlignment(ArgTy);
7303 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7305 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7307 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7309 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7311 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
7313 PointerType *Ty = cast<PointerType>(I->getType());
7314 Type *ElementTy = Ty->getElementType();
7315 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
7316 // For ByVal, alignment should be passed from FE. BE will guess if
7317 // this info is not there but there are cases it cannot get right.
7318 unsigned FrameAlign;
7319 if (F.getParamAlignment(Idx))
7320 FrameAlign = F.getParamAlignment(Idx);
7322 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7323 Flags.setByValAlign(FrameAlign);
7325 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7327 Flags.setOrigAlign(OriginalAlignment);
7329 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7330 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7331 for (unsigned i = 0; i != NumRegs; ++i) {
7332 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7333 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7334 if (NumRegs > 1 && i == 0)
7335 MyFlags.Flags.setSplit();
7336 // if it isn't first piece, alignment must be 1
7338 MyFlags.Flags.setOrigAlign(1);
7339 Ins.push_back(MyFlags);
7341 PartBase += VT.getStoreSize();
7345 // Call the target to set up the argument values.
7346 SmallVector<SDValue, 8> InVals;
7347 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7351 // Verify that the target's LowerFormalArguments behaved as expected.
7352 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7353 "LowerFormalArguments didn't return a valid chain!");
7354 assert(InVals.size() == Ins.size() &&
7355 "LowerFormalArguments didn't emit the correct number of values!");
7357 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7358 assert(InVals[i].getNode() &&
7359 "LowerFormalArguments emitted a null value!");
7360 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7361 "LowerFormalArguments emitted a value with the wrong type!");
7365 // Update the DAG with the new chain value resulting from argument lowering.
7366 DAG.setRoot(NewRoot);
7368 // Set up the argument values.
7371 if (!FuncInfo->CanLowerReturn) {
7372 // Create a virtual register for the sret pointer, and put in a copy
7373 // from the sret argument into it.
7374 SmallVector<EVT, 1> ValueVTs;
7375 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7376 MVT VT = ValueVTs[0].getSimpleVT();
7377 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7378 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7379 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7380 RegVT, VT, NULL, AssertOp);
7382 MachineFunction& MF = SDB->DAG.getMachineFunction();
7383 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7384 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7385 FuncInfo->DemoteRegister = SRetReg;
7386 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7388 DAG.setRoot(NewRoot);
7390 // i indexes lowered arguments. Bump it past the hidden sret argument.
7391 // Idx indexes LLVM arguments. Don't touch it.
7395 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7397 SmallVector<SDValue, 4> ArgValues;
7398 SmallVector<EVT, 4> ValueVTs;
7399 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7400 unsigned NumValues = ValueVTs.size();
7402 // If this argument is unused then remember its value. It is used to generate
7403 // debugging information.
7404 if (I->use_empty() && NumValues) {
7405 SDB->setUnusedArgValue(I, InVals[i]);
7407 // Also remember any frame index for use in FastISel.
7408 if (FrameIndexSDNode *FI =
7409 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7410 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7413 for (unsigned Val = 0; Val != NumValues; ++Val) {
7414 EVT VT = ValueVTs[Val];
7415 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7416 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7418 if (!I->use_empty()) {
7419 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7420 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7421 AssertOp = ISD::AssertSext;
7422 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7423 AssertOp = ISD::AssertZext;
7425 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7426 NumParts, PartVT, VT,
7433 // We don't need to do anything else for unused arguments.
7434 if (ArgValues.empty())
7437 // Note down frame index.
7438 if (FrameIndexSDNode *FI =
7439 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7440 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7442 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7443 SDB->getCurSDLoc());
7445 SDB->setValue(I, Res);
7446 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7447 if (LoadSDNode *LNode =
7448 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7449 if (FrameIndexSDNode *FI =
7450 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7451 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7454 // If this argument is live outside of the entry block, insert a copy from
7455 // wherever we got it to the vreg that other BB's will reference it as.
7456 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7457 // If we can, though, try to skip creating an unnecessary vreg.
7458 // FIXME: This isn't very clean... it would be nice to make this more
7459 // general. It's also subtly incompatible with the hacks FastISel
7461 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7462 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7463 FuncInfo->ValueMap[I] = Reg;
7467 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7468 FuncInfo->InitializeRegForValue(I);
7469 SDB->CopyToExportRegsIfNeeded(I);
7473 assert(i == InVals.size() && "Argument register count mismatch!");
7475 // Finally, if the target has anything special to do, allow it to do so.
7476 // FIXME: this should insert code into the DAG!
7477 EmitFunctionEntryCode();
7480 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7481 /// ensure constants are generated when needed. Remember the virtual registers
7482 /// that need to be added to the Machine PHI nodes as input. We cannot just
7483 /// directly add them, because expansion might result in multiple MBB's for one
7484 /// BB. As such, the start of the BB might correspond to a different MBB than
7488 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7489 const TerminatorInst *TI = LLVMBB->getTerminator();
7491 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7493 // Check successor nodes' PHI nodes that expect a constant to be available
7495 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7496 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7497 if (!isa<PHINode>(SuccBB->begin())) continue;
7498 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7500 // If this terminator has multiple identical successors (common for
7501 // switches), only handle each succ once.
7502 if (!SuccsHandled.insert(SuccMBB)) continue;
7504 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7506 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7507 // nodes and Machine PHI nodes, but the incoming operands have not been
7509 for (BasicBlock::const_iterator I = SuccBB->begin();
7510 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7511 // Ignore dead phi's.
7512 if (PN->use_empty()) continue;
7515 if (PN->getType()->isEmptyTy())
7519 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7521 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7522 unsigned &RegOut = ConstantsOut[C];
7524 RegOut = FuncInfo.CreateRegs(C->getType());
7525 CopyValueToVirtualRegister(C, RegOut);
7529 DenseMap<const Value *, unsigned>::iterator I =
7530 FuncInfo.ValueMap.find(PHIOp);
7531 if (I != FuncInfo.ValueMap.end())
7534 assert(isa<AllocaInst>(PHIOp) &&
7535 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7536 "Didn't codegen value into a register!??");
7537 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7538 CopyValueToVirtualRegister(PHIOp, Reg);
7542 // Remember that this register needs to added to the machine PHI node as
7543 // the input for this MBB.
7544 SmallVector<EVT, 4> ValueVTs;
7545 const TargetLowering *TLI = TM.getTargetLowering();
7546 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7547 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7548 EVT VT = ValueVTs[vti];
7549 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7550 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7551 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7552 Reg += NumRegisters;
7557 ConstantsOut.clear();
7560 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7563 SelectionDAGBuilder::StackProtectorDescriptor::
7564 AddSuccessorMBB(const BasicBlock *BB,
7565 MachineBasicBlock *ParentMBB,
7566 MachineBasicBlock *SuccMBB) {
7567 // If SuccBB has not been created yet, create it.
7569 MachineFunction *MF = ParentMBB->getParent();
7570 MachineFunction::iterator BBI = ParentMBB;
7571 SuccMBB = MF->CreateMachineBasicBlock(BB);
7572 MF->insert(++BBI, SuccMBB);
7574 // Add it as a successor of ParentMBB.
7575 ParentMBB->addSuccessor(SuccMBB);