1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(ValueVT.getVectorElementType() == PartVT &&
287 ValueVT.getVectorNumElements() == 1 &&
288 "Only trivial scalar-to-vector conversions should get here!");
289 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
295 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
296 SDValue Val, SDValue *Parts, unsigned NumParts,
299 /// getCopyToParts - Create a series of nodes that contain the specified value
300 /// split into legal parts. If the parts contain more bits than Val, then, for
301 /// integers, ExtendKind can be used to specify how to generate the extra bits.
302 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
303 SDValue Val, SDValue *Parts, unsigned NumParts,
305 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
306 EVT ValueVT = Val.getValueType();
308 // Handle the vector case separately.
309 if (ValueVT.isVector())
310 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
312 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
313 unsigned PartBits = PartVT.getSizeInBits();
314 unsigned OrigNumParts = NumParts;
315 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
320 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
321 if (PartVT == ValueVT) {
322 assert(NumParts == 1 && "No-op copy with multiple parts!");
327 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
328 // If the parts cover more bits than the value has, promote the value.
329 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
330 assert(NumParts == 1 && "Do not know what to promote to!");
331 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
333 assert(PartVT.isInteger() && ValueVT.isInteger() &&
334 "Unknown mismatch!");
335 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
336 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
338 } else if (PartBits == ValueVT.getSizeInBits()) {
339 // Different types of the same size.
340 assert(NumParts == 1 && PartVT != ValueVT);
341 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
342 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
343 // If the parts cover less bits than value has, truncate the value.
344 assert(PartVT.isInteger() && ValueVT.isInteger() &&
345 "Unknown mismatch!");
346 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
347 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
350 // The value may have changed - recompute ValueVT.
351 ValueVT = Val.getValueType();
352 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
353 "Failed to tile the value with PartVT!");
356 assert(PartVT == ValueVT && "Type conversion failed!");
361 // Expand the value into multiple parts.
362 if (NumParts & (NumParts - 1)) {
363 // The number of parts is not a power of 2. Split off and copy the tail.
364 assert(PartVT.isInteger() && ValueVT.isInteger() &&
365 "Do not know what to expand to!");
366 unsigned RoundParts = 1 << Log2_32(NumParts);
367 unsigned RoundBits = RoundParts * PartBits;
368 unsigned OddParts = NumParts - RoundParts;
369 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
370 DAG.getIntPtrConstant(RoundBits));
371 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
373 if (TLI.isBigEndian())
374 // The odd parts were reversed by getCopyToParts - unreverse them.
375 std::reverse(Parts + RoundParts, Parts + NumParts);
377 NumParts = RoundParts;
378 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
379 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
382 // The number of parts is a power of 2. Repeatedly bisect the value using
384 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
385 EVT::getIntegerVT(*DAG.getContext(),
386 ValueVT.getSizeInBits()),
389 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
390 for (unsigned i = 0; i < NumParts; i += StepSize) {
391 unsigned ThisBits = StepSize * PartBits / 2;
392 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
393 SDValue &Part0 = Parts[i];
394 SDValue &Part1 = Parts[i+StepSize/2];
396 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
397 ThisVT, Part0, DAG.getIntPtrConstant(1));
398 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
399 ThisVT, Part0, DAG.getIntPtrConstant(0));
401 if (ThisBits == PartBits && ThisVT != PartVT) {
402 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
403 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
408 if (TLI.isBigEndian())
409 std::reverse(Parts, Parts + OrigNumParts);
413 /// getCopyToPartsVector - Create a series of nodes that contain the specified
414 /// value split into legal parts.
415 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
416 SDValue Val, SDValue *Parts, unsigned NumParts,
418 EVT ValueVT = Val.getValueType();
419 assert(ValueVT.isVector() && "Not a vector");
420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
423 if (PartVT == ValueVT) {
425 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
426 // Bitconvert vector->vector case.
427 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
428 } else if (PartVT.isVector() &&
429 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
430 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
431 EVT ElementVT = PartVT.getVectorElementType();
432 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
434 SmallVector<SDValue, 16> Ops;
435 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
436 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
437 ElementVT, Val, DAG.getIntPtrConstant(i)));
439 for (unsigned i = ValueVT.getVectorNumElements(),
440 e = PartVT.getVectorNumElements(); i != e; ++i)
441 Ops.push_back(DAG.getUNDEF(ElementVT));
443 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
445 // FIXME: Use CONCAT for 2x -> 4x.
447 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
448 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
450 // Vector -> scalar conversion.
451 assert(ValueVT.getVectorElementType() == PartVT &&
452 ValueVT.getVectorNumElements() == 1 &&
453 "Only trivial vector-to-scalar conversions should get here!");
454 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
455 PartVT, Val, DAG.getIntPtrConstant(0));
462 // Handle a multi-element vector.
463 EVT IntermediateVT, RegisterVT;
464 unsigned NumIntermediates;
465 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
467 NumIntermediates, RegisterVT);
468 unsigned NumElements = ValueVT.getVectorNumElements();
470 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
471 NumParts = NumRegs; // Silence a compiler warning.
472 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
474 // Split the vector into intermediate operands.
475 SmallVector<SDValue, 8> Ops(NumIntermediates);
476 for (unsigned i = 0; i != NumIntermediates; ++i) {
477 if (IntermediateVT.isVector())
478 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
480 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
482 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
483 IntermediateVT, Val, DAG.getIntPtrConstant(i));
486 // Split the intermediate operands into legal parts.
487 if (NumParts == NumIntermediates) {
488 // If the register was not expanded, promote or copy the value,
490 for (unsigned i = 0; i != NumParts; ++i)
491 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
492 } else if (NumParts > 0) {
493 // If the intermediate type was expanded, split each the value into
495 assert(NumParts % NumIntermediates == 0 &&
496 "Must expand into a divisible number of parts!");
497 unsigned Factor = NumParts / NumIntermediates;
498 for (unsigned i = 0; i != NumIntermediates; ++i)
499 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
507 /// RegsForValue - This struct represents the registers (physical or virtual)
508 /// that a particular set of values is assigned, and the type information
509 /// about the value. The most common situation is to represent one value at a
510 /// time, but struct or array values are handled element-wise as multiple
511 /// values. The splitting of aggregates is performed recursively, so that we
512 /// never have aggregate-typed registers. The values at this point do not
513 /// necessarily have legal types, so each value may require one or more
514 /// registers of some legal type.
516 struct RegsForValue {
517 /// ValueVTs - The value types of the values, which may not be legal, and
518 /// may need be promoted or synthesized from one or more registers.
520 SmallVector<EVT, 4> ValueVTs;
522 /// RegVTs - The value types of the registers. This is the same size as
523 /// ValueVTs and it records, for each value, what the type of the assigned
524 /// register or registers are. (Individual values are never synthesized
525 /// from more than one type of register.)
527 /// With virtual registers, the contents of RegVTs is redundant with TLI's
528 /// getRegisterType member function, however when with physical registers
529 /// it is necessary to have a separate record of the types.
531 SmallVector<EVT, 4> RegVTs;
533 /// Regs - This list holds the registers assigned to the values.
534 /// Each legal or promoted value requires one register, and each
535 /// expanded value requires multiple registers.
537 SmallVector<unsigned, 4> Regs;
541 RegsForValue(const SmallVector<unsigned, 4> ®s,
542 EVT regvt, EVT valuevt)
543 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
545 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
546 unsigned Reg, const Type *Ty) {
547 ComputeValueVTs(tli, Ty, ValueVTs);
549 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
550 EVT ValueVT = ValueVTs[Value];
551 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
552 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
553 for (unsigned i = 0; i != NumRegs; ++i)
554 Regs.push_back(Reg + i);
555 RegVTs.push_back(RegisterVT);
560 /// areValueTypesLegal - Return true if types of all the values are legal.
561 bool areValueTypesLegal(const TargetLowering &TLI) {
562 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
563 EVT RegisterVT = RegVTs[Value];
564 if (!TLI.isTypeLegal(RegisterVT))
570 /// append - Add the specified values to this one.
571 void append(const RegsForValue &RHS) {
572 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
573 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
574 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
577 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
578 /// this value and returns the result as a ValueVTs value. This uses
579 /// Chain/Flag as the input and updates them for the output Chain/Flag.
580 /// If the Flag pointer is NULL, no flag is used.
581 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
583 SDValue &Chain, SDValue *Flag) const;
585 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
586 /// specified value into the registers specified by this object. This uses
587 /// Chain/Flag as the input and updates them for the output Chain/Flag.
588 /// If the Flag pointer is NULL, no flag is used.
589 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
590 SDValue &Chain, SDValue *Flag) const;
592 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
593 /// operand list. This adds the code marker, matching input operand index
594 /// (if applicable), and includes the number of values added into it.
595 void AddInlineAsmOperands(unsigned Kind,
596 bool HasMatching, unsigned MatchingIdx,
598 std::vector<SDValue> &Ops) const;
602 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
603 /// this value and returns the result as a ValueVT value. This uses
604 /// Chain/Flag as the input and updates them for the output Chain/Flag.
605 /// If the Flag pointer is NULL, no flag is used.
606 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
607 FunctionLoweringInfo &FuncInfo,
609 SDValue &Chain, SDValue *Flag) const {
610 // A Value with type {} or [0 x %t] needs no registers.
611 if (ValueVTs.empty())
614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
616 // Assemble the legal parts into the final values.
617 SmallVector<SDValue, 4> Values(ValueVTs.size());
618 SmallVector<SDValue, 8> Parts;
619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 // Copy the legal parts from the registers.
621 EVT ValueVT = ValueVTs[Value];
622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
623 EVT RegisterVT = RegVTs[Value];
625 Parts.resize(NumRegs);
626 for (unsigned i = 0; i != NumRegs; ++i) {
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
632 *Flag = P.getValue(2);
635 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
641 !RegisterVT.isInteger() || RegisterVT.isVector())
644 const FunctionLoweringInfo::LiveOutInfo *LOI =
645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
649 unsigned RegSize = RegisterVT.getSizeInBits();
650 unsigned NumSignBits = LOI->NumSignBits;
651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
653 // FIXME: We capture more information than the dag can represent. For
654 // now, just use the tightest assertzext/assertsext possible.
656 EVT FromVT(MVT::Other);
657 if (NumSignBits == RegSize)
658 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
659 else if (NumZeroBits >= RegSize-1)
660 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
661 else if (NumSignBits > RegSize-8)
662 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
663 else if (NumZeroBits >= RegSize-8)
664 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
665 else if (NumSignBits > RegSize-16)
666 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
667 else if (NumZeroBits >= RegSize-16)
668 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
669 else if (NumSignBits > RegSize-32)
670 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
671 else if (NumZeroBits >= RegSize-32)
672 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
676 // Add an assertion node.
677 assert(FromVT != MVT::Other);
678 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
679 RegisterVT, P, DAG.getValueType(FromVT));
682 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
683 NumRegs, RegisterVT, ValueVT);
688 return DAG.getNode(ISD::MERGE_VALUES, dl,
689 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
690 &Values[0], ValueVTs.size());
693 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
694 /// specified value into the registers specified by this object. This uses
695 /// Chain/Flag as the input and updates them for the output Chain/Flag.
696 /// If the Flag pointer is NULL, no flag is used.
697 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
698 SDValue &Chain, SDValue *Flag) const {
699 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
701 // Get the list of the values's legal parts.
702 unsigned NumRegs = Regs.size();
703 SmallVector<SDValue, 8> Parts(NumRegs);
704 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
705 EVT ValueVT = ValueVTs[Value];
706 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
707 EVT RegisterVT = RegVTs[Value];
709 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
710 &Parts[Part], NumParts, RegisterVT);
714 // Copy the parts into the registers.
715 SmallVector<SDValue, 8> Chains(NumRegs);
716 for (unsigned i = 0; i != NumRegs; ++i) {
719 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
722 *Flag = Part.getValue(1);
725 Chains[i] = Part.getValue(0);
728 if (NumRegs == 1 || Flag)
729 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
730 // flagged to it. That is the CopyToReg nodes and the user are considered
731 // a single scheduling unit. If we create a TokenFactor and return it as
732 // chain, then the TokenFactor is both a predecessor (operand) of the
733 // user as well as a successor (the TF operands are flagged to the user).
734 // c1, f1 = CopyToReg
735 // c2, f2 = CopyToReg
736 // c3 = TokenFactor c1, c2
739 Chain = Chains[NumRegs-1];
741 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
744 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
745 /// operand list. This adds the code marker and includes the number of
746 /// values added into it.
747 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
748 unsigned MatchingIdx,
750 std::vector<SDValue> &Ops) const {
751 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
753 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
755 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
756 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
759 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
760 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
761 EVT RegisterVT = RegVTs[Value];
762 for (unsigned i = 0; i != NumRegs; ++i) {
763 assert(Reg < Regs.size() && "Mismatch in # registers expected");
764 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
769 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
772 TD = DAG.getTarget().getTargetData();
775 /// clear - Clear out the current SelectionDAG and the associated
776 /// state and prepare this SelectionDAGBuilder object to be used
777 /// for a new block. This doesn't clear out information about
778 /// additional blocks that are needed to complete switch lowering
779 /// or PHI node updating; that information is cleared out as it is
781 void SelectionDAGBuilder::clear() {
783 UnusedArgNodeMap.clear();
784 PendingLoads.clear();
785 PendingExports.clear();
786 DanglingDebugInfoMap.clear();
787 CurDebugLoc = DebugLoc();
791 /// getRoot - Return the current virtual root of the Selection DAG,
792 /// flushing any PendingLoad items. This must be done before emitting
793 /// a store or any other node that may need to be ordered after any
794 /// prior load instructions.
796 SDValue SelectionDAGBuilder::getRoot() {
797 if (PendingLoads.empty())
798 return DAG.getRoot();
800 if (PendingLoads.size() == 1) {
801 SDValue Root = PendingLoads[0];
803 PendingLoads.clear();
807 // Otherwise, we have to make a token factor node.
808 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
809 &PendingLoads[0], PendingLoads.size());
810 PendingLoads.clear();
815 /// getControlRoot - Similar to getRoot, but instead of flushing all the
816 /// PendingLoad items, flush all the PendingExports items. It is necessary
817 /// to do this before emitting a terminator instruction.
819 SDValue SelectionDAGBuilder::getControlRoot() {
820 SDValue Root = DAG.getRoot();
822 if (PendingExports.empty())
825 // Turn all of the CopyToReg chains into one factored node.
826 if (Root.getOpcode() != ISD::EntryToken) {
827 unsigned i = 0, e = PendingExports.size();
828 for (; i != e; ++i) {
829 assert(PendingExports[i].getNode()->getNumOperands() > 1);
830 if (PendingExports[i].getNode()->getOperand(0) == Root)
831 break; // Don't add the root if we already indirectly depend on it.
835 PendingExports.push_back(Root);
838 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
840 PendingExports.size());
841 PendingExports.clear();
846 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
847 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
848 DAG.AssignOrdering(Node, SDNodeOrder);
850 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
851 AssignOrderingToNode(Node->getOperand(I).getNode());
854 void SelectionDAGBuilder::visit(const Instruction &I) {
855 // Set up outgoing PHI node register values before emitting the terminator.
856 if (isa<TerminatorInst>(&I))
857 HandlePHINodesInSuccessorBlocks(I.getParent());
859 CurDebugLoc = I.getDebugLoc();
861 visit(I.getOpcode(), I);
863 if (!isa<TerminatorInst>(&I) && !HasTailCall)
864 CopyToExportRegsIfNeeded(&I);
866 CurDebugLoc = DebugLoc();
869 void SelectionDAGBuilder::visitPHI(const PHINode &) {
870 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
873 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
874 // Note: this doesn't use InstVisitor, because it has to work with
875 // ConstantExpr's in addition to instructions.
877 default: llvm_unreachable("Unknown instruction type encountered!");
878 // Build the switch statement using the Instruction.def file.
879 #define HANDLE_INST(NUM, OPCODE, CLASS) \
880 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
881 #include "llvm/Instruction.def"
884 // Assign the ordering to the freshly created DAG nodes.
885 if (NodeMap.count(&I)) {
887 AssignOrderingToNode(getValue(&I).getNode());
891 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
892 // generate the debug data structures now that we've seen its definition.
893 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
895 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
897 const DbgValueInst *DI = DDI.getDI();
898 DebugLoc dl = DDI.getdl();
899 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
900 MDNode *Variable = DI->getVariable();
901 uint64_t Offset = DI->getOffset();
904 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
905 SDV = DAG.getDbgValue(Variable, Val.getNode(),
906 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
907 DAG.AddDbgValue(SDV, Val.getNode(), false);
910 DEBUG(dbgs() << "Dropping debug info for " << DI);
911 DanglingDebugInfoMap[V] = DanglingDebugInfo();
915 // getValue - Return an SDValue for the given Value.
916 SDValue SelectionDAGBuilder::getValue(const Value *V) {
917 // If we already have an SDValue for this value, use it. It's important
918 // to do this first, so that we don't create a CopyFromReg if we already
919 // have a regular SDValue.
920 SDValue &N = NodeMap[V];
921 if (N.getNode()) return N;
923 // If there's a virtual register allocated and initialized for this
925 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
926 if (It != FuncInfo.ValueMap.end()) {
927 unsigned InReg = It->second;
928 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
929 SDValue Chain = DAG.getEntryNode();
930 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
931 resolveDanglingDebugInfo(V, N);
935 // Otherwise create a new SDValue and remember it.
936 SDValue Val = getValueImpl(V);
938 resolveDanglingDebugInfo(V, Val);
942 /// getNonRegisterValue - Return an SDValue for the given Value, but
943 /// don't look in FuncInfo.ValueMap for a virtual register.
944 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
945 // If we already have an SDValue for this value, use it.
946 SDValue &N = NodeMap[V];
947 if (N.getNode()) return N;
949 // Otherwise create a new SDValue and remember it.
950 SDValue Val = getValueImpl(V);
952 resolveDanglingDebugInfo(V, Val);
956 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
957 /// Create an SDValue for the given value.
958 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
959 if (const Constant *C = dyn_cast<Constant>(V)) {
960 EVT VT = TLI.getValueType(V->getType(), true);
962 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
963 return DAG.getConstant(*CI, VT);
965 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
966 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
968 if (isa<ConstantPointerNull>(C))
969 return DAG.getConstant(0, TLI.getPointerTy());
971 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
972 return DAG.getConstantFP(*CFP, VT);
974 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
975 return DAG.getUNDEF(VT);
977 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
978 visit(CE->getOpcode(), *CE);
979 SDValue N1 = NodeMap[V];
980 assert(N1.getNode() && "visit didn't populate the NodeMap!");
984 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
985 SmallVector<SDValue, 4> Constants;
986 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
988 SDNode *Val = getValue(*OI).getNode();
989 // If the operand is an empty aggregate, there are no values.
991 // Add each leaf value from the operand to the Constants list
992 // to form a flattened list of all the values.
993 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
994 Constants.push_back(SDValue(Val, i));
997 return DAG.getMergeValues(&Constants[0], Constants.size(),
1001 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1002 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1003 "Unknown struct or array constant!");
1005 SmallVector<EVT, 4> ValueVTs;
1006 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1007 unsigned NumElts = ValueVTs.size();
1009 return SDValue(); // empty struct
1010 SmallVector<SDValue, 4> Constants(NumElts);
1011 for (unsigned i = 0; i != NumElts; ++i) {
1012 EVT EltVT = ValueVTs[i];
1013 if (isa<UndefValue>(C))
1014 Constants[i] = DAG.getUNDEF(EltVT);
1015 else if (EltVT.isFloatingPoint())
1016 Constants[i] = DAG.getConstantFP(0, EltVT);
1018 Constants[i] = DAG.getConstant(0, EltVT);
1021 return DAG.getMergeValues(&Constants[0], NumElts,
1025 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1026 return DAG.getBlockAddress(BA, VT);
1028 const VectorType *VecTy = cast<VectorType>(V->getType());
1029 unsigned NumElements = VecTy->getNumElements();
1031 // Now that we know the number and type of the elements, get that number of
1032 // elements into the Ops array based on what kind of constant it is.
1033 SmallVector<SDValue, 16> Ops;
1034 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1035 for (unsigned i = 0; i != NumElements; ++i)
1036 Ops.push_back(getValue(CP->getOperand(i)));
1038 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1039 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1042 if (EltVT.isFloatingPoint())
1043 Op = DAG.getConstantFP(0, EltVT);
1045 Op = DAG.getConstant(0, EltVT);
1046 Ops.assign(NumElements, Op);
1049 // Create a BUILD_VECTOR node.
1050 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1051 VT, &Ops[0], Ops.size());
1054 // If this is a static alloca, generate it as the frameindex instead of
1056 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1057 DenseMap<const AllocaInst*, int>::iterator SI =
1058 FuncInfo.StaticAllocaMap.find(AI);
1059 if (SI != FuncInfo.StaticAllocaMap.end())
1060 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1063 // If this is an instruction which fast-isel has deferred, select it now.
1064 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1065 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1066 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1067 SDValue Chain = DAG.getEntryNode();
1068 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1071 llvm_unreachable("Can't get register for value!");
1075 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1076 SDValue Chain = getControlRoot();
1077 SmallVector<ISD::OutputArg, 8> Outs;
1078 SmallVector<SDValue, 8> OutVals;
1080 if (!FuncInfo.CanLowerReturn) {
1081 unsigned DemoteReg = FuncInfo.DemoteRegister;
1082 const Function *F = I.getParent()->getParent();
1084 // Emit a store of the return value through the virtual register.
1085 // Leave Outs empty so that LowerReturn won't try to load return
1086 // registers the usual way.
1087 SmallVector<EVT, 1> PtrValueVTs;
1088 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1091 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1092 SDValue RetOp = getValue(I.getOperand(0));
1094 SmallVector<EVT, 4> ValueVTs;
1095 SmallVector<uint64_t, 4> Offsets;
1096 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1097 unsigned NumValues = ValueVTs.size();
1099 SmallVector<SDValue, 4> Chains(NumValues);
1100 for (unsigned i = 0; i != NumValues; ++i) {
1101 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1102 RetPtr.getValueType(), RetPtr,
1103 DAG.getIntPtrConstant(Offsets[i]));
1105 DAG.getStore(Chain, getCurDebugLoc(),
1106 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1107 // FIXME: better loc info would be nice.
1108 Add, MachinePointerInfo(), false, false, 0);
1111 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1112 MVT::Other, &Chains[0], NumValues);
1113 } else if (I.getNumOperands() != 0) {
1114 SmallVector<EVT, 4> ValueVTs;
1115 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1116 unsigned NumValues = ValueVTs.size();
1118 SDValue RetOp = getValue(I.getOperand(0));
1119 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1120 EVT VT = ValueVTs[j];
1122 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1124 const Function *F = I.getParent()->getParent();
1125 if (F->paramHasAttr(0, Attribute::SExt))
1126 ExtendKind = ISD::SIGN_EXTEND;
1127 else if (F->paramHasAttr(0, Attribute::ZExt))
1128 ExtendKind = ISD::ZERO_EXTEND;
1130 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1131 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1133 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1134 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1135 SmallVector<SDValue, 4> Parts(NumParts);
1136 getCopyToParts(DAG, getCurDebugLoc(),
1137 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1138 &Parts[0], NumParts, PartVT, ExtendKind);
1140 // 'inreg' on function refers to return value
1141 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1142 if (F->paramHasAttr(0, Attribute::InReg))
1145 // Propagate extension type if any
1146 if (ExtendKind == ISD::SIGN_EXTEND)
1148 else if (ExtendKind == ISD::ZERO_EXTEND)
1151 for (unsigned i = 0; i < NumParts; ++i) {
1152 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1154 OutVals.push_back(Parts[i]);
1160 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1161 CallingConv::ID CallConv =
1162 DAG.getMachineFunction().getFunction()->getCallingConv();
1163 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1164 Outs, OutVals, getCurDebugLoc(), DAG);
1166 // Verify that the target's LowerReturn behaved as expected.
1167 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1168 "LowerReturn didn't return a valid chain!");
1170 // Update the DAG with the new chain value resulting from return lowering.
1174 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1175 /// created for it, emit nodes to copy the value into the virtual
1177 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1178 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1179 if (VMI != FuncInfo.ValueMap.end()) {
1180 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1181 CopyValueToVirtualRegister(V, VMI->second);
1185 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1186 /// the current basic block, add it to ValueMap now so that we'll get a
1188 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1189 // No need to export constants.
1190 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1192 // Already exported?
1193 if (FuncInfo.isExportedInst(V)) return;
1195 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1196 CopyValueToVirtualRegister(V, Reg);
1199 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1200 const BasicBlock *FromBB) {
1201 // The operands of the setcc have to be in this block. We don't know
1202 // how to export them from some other block.
1203 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1204 // Can export from current BB.
1205 if (VI->getParent() == FromBB)
1208 // Is already exported, noop.
1209 return FuncInfo.isExportedInst(V);
1212 // If this is an argument, we can export it if the BB is the entry block or
1213 // if it is already exported.
1214 if (isa<Argument>(V)) {
1215 if (FromBB == &FromBB->getParent()->getEntryBlock())
1218 // Otherwise, can only export this if it is already exported.
1219 return FuncInfo.isExportedInst(V);
1222 // Otherwise, constants can always be exported.
1226 static bool InBlock(const Value *V, const BasicBlock *BB) {
1227 if (const Instruction *I = dyn_cast<Instruction>(V))
1228 return I->getParent() == BB;
1232 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1233 /// This function emits a branch and is used at the leaves of an OR or an
1234 /// AND operator tree.
1237 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1238 MachineBasicBlock *TBB,
1239 MachineBasicBlock *FBB,
1240 MachineBasicBlock *CurBB,
1241 MachineBasicBlock *SwitchBB) {
1242 const BasicBlock *BB = CurBB->getBasicBlock();
1244 // If the leaf of the tree is a comparison, merge the condition into
1246 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1247 // The operands of the cmp have to be in this block. We don't know
1248 // how to export them from some other block. If this is the first block
1249 // of the sequence, no exporting is needed.
1250 if (CurBB == SwitchBB ||
1251 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1252 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1253 ISD::CondCode Condition;
1254 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1255 Condition = getICmpCondCode(IC->getPredicate());
1256 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1257 Condition = getFCmpCondCode(FC->getPredicate());
1259 Condition = ISD::SETEQ; // silence warning.
1260 llvm_unreachable("Unknown compare instruction");
1263 CaseBlock CB(Condition, BOp->getOperand(0),
1264 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1265 SwitchCases.push_back(CB);
1270 // Create a CaseBlock record representing this branch.
1271 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1272 NULL, TBB, FBB, CurBB);
1273 SwitchCases.push_back(CB);
1276 /// FindMergedConditions - If Cond is an expression like
1277 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1278 MachineBasicBlock *TBB,
1279 MachineBasicBlock *FBB,
1280 MachineBasicBlock *CurBB,
1281 MachineBasicBlock *SwitchBB,
1283 // If this node is not part of the or/and tree, emit it as a branch.
1284 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1285 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1286 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1287 BOp->getParent() != CurBB->getBasicBlock() ||
1288 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1289 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1290 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1294 // Create TmpBB after CurBB.
1295 MachineFunction::iterator BBI = CurBB;
1296 MachineFunction &MF = DAG.getMachineFunction();
1297 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1298 CurBB->getParent()->insert(++BBI, TmpBB);
1300 if (Opc == Instruction::Or) {
1301 // Codegen X | Y as:
1309 // Emit the LHS condition.
1310 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1312 // Emit the RHS condition into TmpBB.
1313 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1315 assert(Opc == Instruction::And && "Unknown merge op!");
1316 // Codegen X & Y as:
1323 // This requires creation of TmpBB after CurBB.
1325 // Emit the LHS condition.
1326 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1328 // Emit the RHS condition into TmpBB.
1329 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1333 /// If the set of cases should be emitted as a series of branches, return true.
1334 /// If we should emit this as a bunch of and/or'd together conditions, return
1337 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1338 if (Cases.size() != 2) return true;
1340 // If this is two comparisons of the same values or'd or and'd together, they
1341 // will get folded into a single comparison, so don't emit two blocks.
1342 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1343 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1344 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1345 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1349 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1350 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1351 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1352 Cases[0].CC == Cases[1].CC &&
1353 isa<Constant>(Cases[0].CmpRHS) &&
1354 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1355 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1357 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1364 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1365 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1367 // Update machine-CFG edges.
1368 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1370 // Figure out which block is immediately after the current one.
1371 MachineBasicBlock *NextBlock = 0;
1372 MachineFunction::iterator BBI = BrMBB;
1373 if (++BBI != FuncInfo.MF->end())
1376 if (I.isUnconditional()) {
1377 // Update machine-CFG edges.
1378 BrMBB->addSuccessor(Succ0MBB);
1380 // If this is not a fall-through branch, emit the branch.
1381 if (Succ0MBB != NextBlock)
1382 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1383 MVT::Other, getControlRoot(),
1384 DAG.getBasicBlock(Succ0MBB)));
1389 // If this condition is one of the special cases we handle, do special stuff
1391 const Value *CondVal = I.getCondition();
1392 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1394 // If this is a series of conditions that are or'd or and'd together, emit
1395 // this as a sequence of branches instead of setcc's with and/or operations.
1396 // As long as jumps are not expensive, this should improve performance.
1397 // For example, instead of something like:
1410 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1411 if (!TLI.isJumpExpensive() &&
1413 (BOp->getOpcode() == Instruction::And ||
1414 BOp->getOpcode() == Instruction::Or)) {
1415 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1417 // If the compares in later blocks need to use values not currently
1418 // exported from this block, export them now. This block should always
1419 // be the first entry.
1420 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1422 // Allow some cases to be rejected.
1423 if (ShouldEmitAsBranches(SwitchCases)) {
1424 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1425 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1426 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1429 // Emit the branch for this block.
1430 visitSwitchCase(SwitchCases[0], BrMBB);
1431 SwitchCases.erase(SwitchCases.begin());
1435 // Okay, we decided not to do this, remove any inserted MBB's and clear
1437 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1438 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1440 SwitchCases.clear();
1444 // Create a CaseBlock record representing this branch.
1445 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1446 NULL, Succ0MBB, Succ1MBB, BrMBB);
1448 // Use visitSwitchCase to actually insert the fast branch sequence for this
1450 visitSwitchCase(CB, BrMBB);
1453 /// visitSwitchCase - Emits the necessary code to represent a single node in
1454 /// the binary search tree resulting from lowering a switch instruction.
1455 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1456 MachineBasicBlock *SwitchBB) {
1458 SDValue CondLHS = getValue(CB.CmpLHS);
1459 DebugLoc dl = getCurDebugLoc();
1461 // Build the setcc now.
1462 if (CB.CmpMHS == NULL) {
1463 // Fold "(X == true)" to X and "(X == false)" to !X to
1464 // handle common cases produced by branch lowering.
1465 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1466 CB.CC == ISD::SETEQ)
1468 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1469 CB.CC == ISD::SETEQ) {
1470 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1471 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1473 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1475 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1477 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1478 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1480 SDValue CmpOp = getValue(CB.CmpMHS);
1481 EVT VT = CmpOp.getValueType();
1483 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1484 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1487 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1488 VT, CmpOp, DAG.getConstant(Low, VT));
1489 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1490 DAG.getConstant(High-Low, VT), ISD::SETULE);
1494 // Update successor info
1495 SwitchBB->addSuccessor(CB.TrueBB);
1496 SwitchBB->addSuccessor(CB.FalseBB);
1498 // Set NextBlock to be the MBB immediately after the current one, if any.
1499 // This is used to avoid emitting unnecessary branches to the next block.
1500 MachineBasicBlock *NextBlock = 0;
1501 MachineFunction::iterator BBI = SwitchBB;
1502 if (++BBI != FuncInfo.MF->end())
1505 // If the lhs block is the next block, invert the condition so that we can
1506 // fall through to the lhs instead of the rhs block.
1507 if (CB.TrueBB == NextBlock) {
1508 std::swap(CB.TrueBB, CB.FalseBB);
1509 SDValue True = DAG.getConstant(1, Cond.getValueType());
1510 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1513 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1514 MVT::Other, getControlRoot(), Cond,
1515 DAG.getBasicBlock(CB.TrueBB));
1517 // Insert the false branch. Do this even if it's a fall through branch,
1518 // this makes it easier to do DAG optimizations which require inverting
1519 // the branch condition.
1520 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1521 DAG.getBasicBlock(CB.FalseBB));
1523 DAG.setRoot(BrCond);
1526 /// visitJumpTable - Emit JumpTable node in the current MBB
1527 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1528 // Emit the code for the jump table
1529 assert(JT.Reg != -1U && "Should lower JT Header first!");
1530 EVT PTy = TLI.getPointerTy();
1531 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1533 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1534 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1535 MVT::Other, Index.getValue(1),
1537 DAG.setRoot(BrJumpTable);
1540 /// visitJumpTableHeader - This function emits necessary code to produce index
1541 /// in the JumpTable from switch case.
1542 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1543 JumpTableHeader &JTH,
1544 MachineBasicBlock *SwitchBB) {
1545 // Subtract the lowest switch case value from the value being switched on and
1546 // conditional branch to default mbb if the result is greater than the
1547 // difference between smallest and largest cases.
1548 SDValue SwitchOp = getValue(JTH.SValue);
1549 EVT VT = SwitchOp.getValueType();
1550 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1551 DAG.getConstant(JTH.First, VT));
1553 // The SDNode we just created, which holds the value being switched on minus
1554 // the smallest case value, needs to be copied to a virtual register so it
1555 // can be used as an index into the jump table in a subsequent basic block.
1556 // This value may be smaller or larger than the target's pointer type, and
1557 // therefore require extension or truncating.
1558 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1560 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1561 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1562 JumpTableReg, SwitchOp);
1563 JT.Reg = JumpTableReg;
1565 // Emit the range check for the jump table, and branch to the default block
1566 // for the switch statement if the value being switched on exceeds the largest
1567 // case in the switch.
1568 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1569 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1570 DAG.getConstant(JTH.Last-JTH.First,VT),
1573 // Set NextBlock to be the MBB immediately after the current one, if any.
1574 // This is used to avoid emitting unnecessary branches to the next block.
1575 MachineBasicBlock *NextBlock = 0;
1576 MachineFunction::iterator BBI = SwitchBB;
1578 if (++BBI != FuncInfo.MF->end())
1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1582 MVT::Other, CopyTo, CMP,
1583 DAG.getBasicBlock(JT.Default));
1585 if (JT.MBB != NextBlock)
1586 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1587 DAG.getBasicBlock(JT.MBB));
1589 DAG.setRoot(BrCond);
1592 /// visitBitTestHeader - This function emits necessary code to produce value
1593 /// suitable for "bit tests"
1594 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1595 MachineBasicBlock *SwitchBB) {
1596 // Subtract the minimum value
1597 SDValue SwitchOp = getValue(B.SValue);
1598 EVT VT = SwitchOp.getValueType();
1599 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1600 DAG.getConstant(B.First, VT));
1603 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1604 TLI.getSetCCResultType(Sub.getValueType()),
1605 Sub, DAG.getConstant(B.Range, VT),
1608 // Determine the type of the test operands.
1609 bool UsePtrType = false;
1610 if (!TLI.isTypeLegal(VT))
1613 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1614 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1615 // Switch table case range are encoded into series of masks.
1616 // Just use pointer type, it's guaranteed to fit.
1622 VT = TLI.getPointerTy();
1623 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1627 B.Reg = FuncInfo.CreateReg(VT);
1628 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1631 // Set NextBlock to be the MBB immediately after the current one, if any.
1632 // This is used to avoid emitting unnecessary branches to the next block.
1633 MachineBasicBlock *NextBlock = 0;
1634 MachineFunction::iterator BBI = SwitchBB;
1635 if (++BBI != FuncInfo.MF->end())
1638 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1640 SwitchBB->addSuccessor(B.Default);
1641 SwitchBB->addSuccessor(MBB);
1643 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1644 MVT::Other, CopyTo, RangeCmp,
1645 DAG.getBasicBlock(B.Default));
1647 if (MBB != NextBlock)
1648 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1649 DAG.getBasicBlock(MBB));
1651 DAG.setRoot(BrRange);
1654 /// visitBitTestCase - this function produces one "bit test"
1655 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1656 MachineBasicBlock* NextMBB,
1659 MachineBasicBlock *SwitchBB) {
1661 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1664 if (CountPopulation_64(B.Mask) == 1) {
1665 // Testing for a single bit; just compare the shift count with what it
1666 // would need to be to shift a 1 bit in that position.
1667 Cmp = DAG.getSetCC(getCurDebugLoc(),
1668 TLI.getSetCCResultType(VT),
1670 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1673 // Make desired shift
1674 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1675 DAG.getConstant(1, VT), ShiftOp);
1677 // Emit bit tests and jumps
1678 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1679 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1680 Cmp = DAG.getSetCC(getCurDebugLoc(),
1681 TLI.getSetCCResultType(VT),
1682 AndOp, DAG.getConstant(0, VT),
1686 SwitchBB->addSuccessor(B.TargetBB);
1687 SwitchBB->addSuccessor(NextMBB);
1689 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1690 MVT::Other, getControlRoot(),
1691 Cmp, DAG.getBasicBlock(B.TargetBB));
1693 // Set NextBlock to be the MBB immediately after the current one, if any.
1694 // This is used to avoid emitting unnecessary branches to the next block.
1695 MachineBasicBlock *NextBlock = 0;
1696 MachineFunction::iterator BBI = SwitchBB;
1697 if (++BBI != FuncInfo.MF->end())
1700 if (NextMBB != NextBlock)
1701 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1702 DAG.getBasicBlock(NextMBB));
1707 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1708 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1710 // Retrieve successors.
1711 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1712 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1714 const Value *Callee(I.getCalledValue());
1715 if (isa<InlineAsm>(Callee))
1718 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1720 // If the value of the invoke is used outside of its defining block, make it
1721 // available as a virtual register.
1722 CopyToExportRegsIfNeeded(&I);
1724 // Update successor info
1725 InvokeMBB->addSuccessor(Return);
1726 InvokeMBB->addSuccessor(LandingPad);
1728 // Drop into normal successor.
1729 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1730 MVT::Other, getControlRoot(),
1731 DAG.getBasicBlock(Return)));
1734 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1737 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1738 /// small case ranges).
1739 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1740 CaseRecVector& WorkList,
1742 MachineBasicBlock *Default,
1743 MachineBasicBlock *SwitchBB) {
1744 Case& BackCase = *(CR.Range.second-1);
1746 // Size is the number of Cases represented by this range.
1747 size_t Size = CR.Range.second - CR.Range.first;
1751 // Get the MachineFunction which holds the current MBB. This is used when
1752 // inserting any additional MBBs necessary to represent the switch.
1753 MachineFunction *CurMF = FuncInfo.MF;
1755 // Figure out which block is immediately after the current one.
1756 MachineBasicBlock *NextBlock = 0;
1757 MachineFunction::iterator BBI = CR.CaseBB;
1759 if (++BBI != FuncInfo.MF->end())
1762 // If any two of the cases has the same destination, and if one value
1763 // is the same as the other, but has one bit unset that the other has set,
1764 // use bit manipulation to do two compares at once. For example:
1765 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1766 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1767 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1768 if (Size == 2 && CR.CaseBB == SwitchBB) {
1769 Case &Small = *CR.Range.first;
1770 Case &Big = *(CR.Range.second-1);
1772 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1773 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1774 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1776 // Check that there is only one bit different.
1777 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1778 (SmallValue | BigValue) == BigValue) {
1779 // Isolate the common bit.
1780 APInt CommonBit = BigValue & ~SmallValue;
1781 assert((SmallValue | CommonBit) == BigValue &&
1782 CommonBit.countPopulation() == 1 && "Not a common bit?");
1784 SDValue CondLHS = getValue(SV);
1785 EVT VT = CondLHS.getValueType();
1786 DebugLoc DL = getCurDebugLoc();
1788 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1789 DAG.getConstant(CommonBit, VT));
1790 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1791 Or, DAG.getConstant(BigValue, VT),
1794 // Update successor info.
1795 SwitchBB->addSuccessor(Small.BB);
1796 SwitchBB->addSuccessor(Default);
1798 // Insert the true branch.
1799 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1800 getControlRoot(), Cond,
1801 DAG.getBasicBlock(Small.BB));
1803 // Insert the false branch.
1804 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1805 DAG.getBasicBlock(Default));
1807 DAG.setRoot(BrCond);
1813 // Rearrange the case blocks so that the last one falls through if possible.
1814 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1815 // The last case block won't fall through into 'NextBlock' if we emit the
1816 // branches in this order. See if rearranging a case value would help.
1817 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1818 if (I->BB == NextBlock) {
1819 std::swap(*I, BackCase);
1825 // Create a CaseBlock record representing a conditional branch to
1826 // the Case's target mbb if the value being switched on SV is equal
1828 MachineBasicBlock *CurBlock = CR.CaseBB;
1829 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1830 MachineBasicBlock *FallThrough;
1832 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1833 CurMF->insert(BBI, FallThrough);
1835 // Put SV in a virtual register to make it available from the new blocks.
1836 ExportFromCurrentBlock(SV);
1838 // If the last case doesn't match, go to the default block.
1839 FallThrough = Default;
1842 const Value *RHS, *LHS, *MHS;
1844 if (I->High == I->Low) {
1845 // This is just small small case range :) containing exactly 1 case
1847 LHS = SV; RHS = I->High; MHS = NULL;
1850 LHS = I->Low; MHS = SV; RHS = I->High;
1852 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1854 // If emitting the first comparison, just call visitSwitchCase to emit the
1855 // code into the current block. Otherwise, push the CaseBlock onto the
1856 // vector to be later processed by SDISel, and insert the node's MBB
1857 // before the next MBB.
1858 if (CurBlock == SwitchBB)
1859 visitSwitchCase(CB, SwitchBB);
1861 SwitchCases.push_back(CB);
1863 CurBlock = FallThrough;
1869 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1870 return !DisableJumpTables &&
1871 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1872 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1875 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1876 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1877 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1878 return (LastExt - FirstExt + 1ULL);
1881 /// handleJTSwitchCase - Emit jumptable for current switch case range
1882 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1883 CaseRecVector& WorkList,
1885 MachineBasicBlock* Default,
1886 MachineBasicBlock *SwitchBB) {
1887 Case& FrontCase = *CR.Range.first;
1888 Case& BackCase = *(CR.Range.second-1);
1890 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1891 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1893 APInt TSize(First.getBitWidth(), 0);
1894 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1898 if (!areJTsAllowed(TLI) || TSize.ult(4))
1901 APInt Range = ComputeRange(First, Last);
1902 double Density = TSize.roundToDouble() / Range.roundToDouble();
1906 DEBUG(dbgs() << "Lowering jump table\n"
1907 << "First entry: " << First << ". Last entry: " << Last << '\n'
1908 << "Range: " << Range
1909 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1911 // Get the MachineFunction which holds the current MBB. This is used when
1912 // inserting any additional MBBs necessary to represent the switch.
1913 MachineFunction *CurMF = FuncInfo.MF;
1915 // Figure out which block is immediately after the current one.
1916 MachineFunction::iterator BBI = CR.CaseBB;
1919 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1921 // Create a new basic block to hold the code for loading the address
1922 // of the jump table, and jumping to it. Update successor information;
1923 // we will either branch to the default case for the switch, or the jump
1925 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1926 CurMF->insert(BBI, JumpTableBB);
1927 CR.CaseBB->addSuccessor(Default);
1928 CR.CaseBB->addSuccessor(JumpTableBB);
1930 // Build a vector of destination BBs, corresponding to each target
1931 // of the jump table. If the value of the jump table slot corresponds to
1932 // a case statement, push the case's BB onto the vector, otherwise, push
1934 std::vector<MachineBasicBlock*> DestBBs;
1936 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1937 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1938 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1940 if (Low.sle(TEI) && TEI.sle(High)) {
1941 DestBBs.push_back(I->BB);
1945 DestBBs.push_back(Default);
1949 // Update successor info. Add one edge to each unique successor.
1950 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1951 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1952 E = DestBBs.end(); I != E; ++I) {
1953 if (!SuccsHandled[(*I)->getNumber()]) {
1954 SuccsHandled[(*I)->getNumber()] = true;
1955 JumpTableBB->addSuccessor(*I);
1959 // Create a jump table index for this jump table.
1960 unsigned JTEncoding = TLI.getJumpTableEncoding();
1961 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1962 ->createJumpTableIndex(DestBBs);
1964 // Set the jump table information so that we can codegen it as a second
1965 // MachineBasicBlock
1966 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1967 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1968 if (CR.CaseBB == SwitchBB)
1969 visitJumpTableHeader(JT, JTH, SwitchBB);
1971 JTCases.push_back(JumpTableBlock(JTH, JT));
1976 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1978 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1979 CaseRecVector& WorkList,
1981 MachineBasicBlock *Default,
1982 MachineBasicBlock *SwitchBB) {
1983 // Get the MachineFunction which holds the current MBB. This is used when
1984 // inserting any additional MBBs necessary to represent the switch.
1985 MachineFunction *CurMF = FuncInfo.MF;
1987 // Figure out which block is immediately after the current one.
1988 MachineFunction::iterator BBI = CR.CaseBB;
1991 Case& FrontCase = *CR.Range.first;
1992 Case& BackCase = *(CR.Range.second-1);
1993 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1995 // Size is the number of Cases represented by this range.
1996 unsigned Size = CR.Range.second - CR.Range.first;
1998 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1999 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2001 CaseItr Pivot = CR.Range.first + Size/2;
2003 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2004 // (heuristically) allow us to emit JumpTable's later.
2005 APInt TSize(First.getBitWidth(), 0);
2006 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2010 APInt LSize = FrontCase.size();
2011 APInt RSize = TSize-LSize;
2012 DEBUG(dbgs() << "Selecting best pivot: \n"
2013 << "First: " << First << ", Last: " << Last <<'\n'
2014 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2015 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2017 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2018 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2019 APInt Range = ComputeRange(LEnd, RBegin);
2020 assert((Range - 2ULL).isNonNegative() &&
2021 "Invalid case distance");
2022 double LDensity = (double)LSize.roundToDouble() /
2023 (LEnd - First + 1ULL).roundToDouble();
2024 double RDensity = (double)RSize.roundToDouble() /
2025 (Last - RBegin + 1ULL).roundToDouble();
2026 double Metric = Range.logBase2()*(LDensity+RDensity);
2027 // Should always split in some non-trivial place
2028 DEBUG(dbgs() <<"=>Step\n"
2029 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2030 << "LDensity: " << LDensity
2031 << ", RDensity: " << RDensity << '\n'
2032 << "Metric: " << Metric << '\n');
2033 if (FMetric < Metric) {
2036 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2042 if (areJTsAllowed(TLI)) {
2043 // If our case is dense we *really* should handle it earlier!
2044 assert((FMetric > 0) && "Should handle dense range earlier!");
2046 Pivot = CR.Range.first + Size/2;
2049 CaseRange LHSR(CR.Range.first, Pivot);
2050 CaseRange RHSR(Pivot, CR.Range.second);
2051 Constant *C = Pivot->Low;
2052 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2054 // We know that we branch to the LHS if the Value being switched on is
2055 // less than the Pivot value, C. We use this to optimize our binary
2056 // tree a bit, by recognizing that if SV is greater than or equal to the
2057 // LHS's Case Value, and that Case Value is exactly one less than the
2058 // Pivot's Value, then we can branch directly to the LHS's Target,
2059 // rather than creating a leaf node for it.
2060 if ((LHSR.second - LHSR.first) == 1 &&
2061 LHSR.first->High == CR.GE &&
2062 cast<ConstantInt>(C)->getValue() ==
2063 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2064 TrueBB = LHSR.first->BB;
2066 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2067 CurMF->insert(BBI, TrueBB);
2068 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2070 // Put SV in a virtual register to make it available from the new blocks.
2071 ExportFromCurrentBlock(SV);
2074 // Similar to the optimization above, if the Value being switched on is
2075 // known to be less than the Constant CR.LT, and the current Case Value
2076 // is CR.LT - 1, then we can branch directly to the target block for
2077 // the current Case Value, rather than emitting a RHS leaf node for it.
2078 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2079 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2080 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2081 FalseBB = RHSR.first->BB;
2083 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2084 CurMF->insert(BBI, FalseBB);
2085 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2087 // Put SV in a virtual register to make it available from the new blocks.
2088 ExportFromCurrentBlock(SV);
2091 // Create a CaseBlock record representing a conditional branch to
2092 // the LHS node if the value being switched on SV is less than C.
2093 // Otherwise, branch to LHS.
2094 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2096 if (CR.CaseBB == SwitchBB)
2097 visitSwitchCase(CB, SwitchBB);
2099 SwitchCases.push_back(CB);
2104 /// handleBitTestsSwitchCase - if current case range has few destination and
2105 /// range span less, than machine word bitwidth, encode case range into series
2106 /// of masks and emit bit tests with these masks.
2107 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2108 CaseRecVector& WorkList,
2110 MachineBasicBlock* Default,
2111 MachineBasicBlock *SwitchBB){
2112 EVT PTy = TLI.getPointerTy();
2113 unsigned IntPtrBits = PTy.getSizeInBits();
2115 Case& FrontCase = *CR.Range.first;
2116 Case& BackCase = *(CR.Range.second-1);
2118 // Get the MachineFunction which holds the current MBB. This is used when
2119 // inserting any additional MBBs necessary to represent the switch.
2120 MachineFunction *CurMF = FuncInfo.MF;
2122 // If target does not have legal shift left, do not emit bit tests at all.
2123 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2127 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2129 // Single case counts one, case range - two.
2130 numCmps += (I->Low == I->High ? 1 : 2);
2133 // Count unique destinations
2134 SmallSet<MachineBasicBlock*, 4> Dests;
2135 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2136 Dests.insert(I->BB);
2137 if (Dests.size() > 3)
2138 // Don't bother the code below, if there are too much unique destinations
2141 DEBUG(dbgs() << "Total number of unique destinations: "
2142 << Dests.size() << '\n'
2143 << "Total number of comparisons: " << numCmps << '\n');
2145 // Compute span of values.
2146 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2147 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2148 APInt cmpRange = maxValue - minValue;
2150 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2151 << "Low bound: " << minValue << '\n'
2152 << "High bound: " << maxValue << '\n');
2154 if (cmpRange.uge(IntPtrBits) ||
2155 (!(Dests.size() == 1 && numCmps >= 3) &&
2156 !(Dests.size() == 2 && numCmps >= 5) &&
2157 !(Dests.size() >= 3 && numCmps >= 6)))
2160 DEBUG(dbgs() << "Emitting bit tests\n");
2161 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2163 // Optimize the case where all the case values fit in a
2164 // word without having to subtract minValue. In this case,
2165 // we can optimize away the subtraction.
2166 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2167 cmpRange = maxValue;
2169 lowBound = minValue;
2172 CaseBitsVector CasesBits;
2173 unsigned i, count = 0;
2175 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2176 MachineBasicBlock* Dest = I->BB;
2177 for (i = 0; i < count; ++i)
2178 if (Dest == CasesBits[i].BB)
2182 assert((count < 3) && "Too much destinations to test!");
2183 CasesBits.push_back(CaseBits(0, Dest, 0));
2187 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2188 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2190 uint64_t lo = (lowValue - lowBound).getZExtValue();
2191 uint64_t hi = (highValue - lowBound).getZExtValue();
2193 for (uint64_t j = lo; j <= hi; j++) {
2194 CasesBits[i].Mask |= 1ULL << j;
2195 CasesBits[i].Bits++;
2199 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2203 // Figure out which block is immediately after the current one.
2204 MachineFunction::iterator BBI = CR.CaseBB;
2207 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2209 DEBUG(dbgs() << "Cases:\n");
2210 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2211 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2212 << ", Bits: " << CasesBits[i].Bits
2213 << ", BB: " << CasesBits[i].BB << '\n');
2215 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2216 CurMF->insert(BBI, CaseBB);
2217 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2221 // Put SV in a virtual register to make it available from the new blocks.
2222 ExportFromCurrentBlock(SV);
2225 BitTestBlock BTB(lowBound, cmpRange, SV,
2226 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2227 CR.CaseBB, Default, BTC);
2229 if (CR.CaseBB == SwitchBB)
2230 visitBitTestHeader(BTB, SwitchBB);
2232 BitTestCases.push_back(BTB);
2237 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2238 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2239 const SwitchInst& SI) {
2242 // Start with "simple" cases
2243 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2244 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2245 Cases.push_back(Case(SI.getSuccessorValue(i),
2246 SI.getSuccessorValue(i),
2249 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2251 // Merge case into clusters
2252 if (Cases.size() >= 2)
2253 // Must recompute end() each iteration because it may be
2254 // invalidated by erase if we hold on to it
2255 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2256 J != Cases.end(); ) {
2257 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2258 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2259 MachineBasicBlock* nextBB = J->BB;
2260 MachineBasicBlock* currentBB = I->BB;
2262 // If the two neighboring cases go to the same destination, merge them
2263 // into a single case.
2264 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2272 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2273 if (I->Low != I->High)
2274 // A range counts double, since it requires two compares.
2281 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2282 MachineBasicBlock *Last) {
2284 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2285 if (JTCases[i].first.HeaderBB == First)
2286 JTCases[i].first.HeaderBB = Last;
2288 // Update BitTestCases.
2289 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2290 if (BitTestCases[i].Parent == First)
2291 BitTestCases[i].Parent = Last;
2294 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2295 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2297 // Figure out which block is immediately after the current one.
2298 MachineBasicBlock *NextBlock = 0;
2299 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2301 // If there is only the default destination, branch to it if it is not the
2302 // next basic block. Otherwise, just fall through.
2303 if (SI.getNumOperands() == 2) {
2304 // Update machine-CFG edges.
2306 // If this is not a fall-through branch, emit the branch.
2307 SwitchMBB->addSuccessor(Default);
2308 if (Default != NextBlock)
2309 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2310 MVT::Other, getControlRoot(),
2311 DAG.getBasicBlock(Default)));
2316 // If there are any non-default case statements, create a vector of Cases
2317 // representing each one, and sort the vector so that we can efficiently
2318 // create a binary search tree from them.
2320 size_t numCmps = Clusterify(Cases, SI);
2321 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2322 << ". Total compares: " << numCmps << '\n');
2325 // Get the Value to be switched on and default basic blocks, which will be
2326 // inserted into CaseBlock records, representing basic blocks in the binary
2328 const Value *SV = SI.getOperand(0);
2330 // Push the initial CaseRec onto the worklist
2331 CaseRecVector WorkList;
2332 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2333 CaseRange(Cases.begin(),Cases.end())));
2335 while (!WorkList.empty()) {
2336 // Grab a record representing a case range to process off the worklist
2337 CaseRec CR = WorkList.back();
2338 WorkList.pop_back();
2340 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2343 // If the range has few cases (two or less) emit a series of specific
2345 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2348 // If the switch has more than 5 blocks, and at least 40% dense, and the
2349 // target supports indirect branches, then emit a jump table rather than
2350 // lowering the switch to a binary tree of conditional branches.
2351 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2354 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2355 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2356 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2360 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2361 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2363 // Update machine-CFG edges with unique successors.
2364 SmallVector<BasicBlock*, 32> succs;
2365 succs.reserve(I.getNumSuccessors());
2366 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2367 succs.push_back(I.getSuccessor(i));
2368 array_pod_sort(succs.begin(), succs.end());
2369 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2370 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2371 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2373 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2374 MVT::Other, getControlRoot(),
2375 getValue(I.getAddress())));
2378 void SelectionDAGBuilder::visitFSub(const User &I) {
2379 // -0.0 - X --> fneg
2380 const Type *Ty = I.getType();
2381 if (isa<Constant>(I.getOperand(0)) &&
2382 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2383 SDValue Op2 = getValue(I.getOperand(1));
2384 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2385 Op2.getValueType(), Op2));
2389 visitBinary(I, ISD::FSUB);
2392 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2393 SDValue Op1 = getValue(I.getOperand(0));
2394 SDValue Op2 = getValue(I.getOperand(1));
2395 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2396 Op1.getValueType(), Op1, Op2));
2399 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2400 SDValue Op1 = getValue(I.getOperand(0));
2401 SDValue Op2 = getValue(I.getOperand(1));
2403 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2405 // Coerce the shift amount to the right type if we can.
2406 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2407 unsigned ShiftSize = ShiftTy.getSizeInBits();
2408 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2409 DebugLoc DL = getCurDebugLoc();
2411 // If the operand is smaller than the shift count type, promote it.
2412 if (ShiftSize > Op2Size)
2413 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2415 // If the operand is larger than the shift count type but the shift
2416 // count type has enough bits to represent any shift value, truncate
2417 // it now. This is a common case and it exposes the truncate to
2418 // optimization early.
2419 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2420 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2421 // Otherwise we'll need to temporarily settle for some other convenient
2422 // type. Type legalization will make adjustments once the shiftee is split.
2424 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2427 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2428 Op1.getValueType(), Op1, Op2));
2431 void SelectionDAGBuilder::visitICmp(const User &I) {
2432 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2433 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2434 predicate = IC->getPredicate();
2435 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2436 predicate = ICmpInst::Predicate(IC->getPredicate());
2437 SDValue Op1 = getValue(I.getOperand(0));
2438 SDValue Op2 = getValue(I.getOperand(1));
2439 ISD::CondCode Opcode = getICmpCondCode(predicate);
2441 EVT DestVT = TLI.getValueType(I.getType());
2442 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2445 void SelectionDAGBuilder::visitFCmp(const User &I) {
2446 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2447 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2448 predicate = FC->getPredicate();
2449 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2450 predicate = FCmpInst::Predicate(FC->getPredicate());
2451 SDValue Op1 = getValue(I.getOperand(0));
2452 SDValue Op2 = getValue(I.getOperand(1));
2453 ISD::CondCode Condition = getFCmpCondCode(predicate);
2454 EVT DestVT = TLI.getValueType(I.getType());
2455 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2458 void SelectionDAGBuilder::visitSelect(const User &I) {
2459 SmallVector<EVT, 4> ValueVTs;
2460 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2461 unsigned NumValues = ValueVTs.size();
2462 if (NumValues == 0) return;
2464 SmallVector<SDValue, 4> Values(NumValues);
2465 SDValue Cond = getValue(I.getOperand(0));
2466 SDValue TrueVal = getValue(I.getOperand(1));
2467 SDValue FalseVal = getValue(I.getOperand(2));
2469 for (unsigned i = 0; i != NumValues; ++i)
2470 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2471 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2473 SDValue(TrueVal.getNode(),
2474 TrueVal.getResNo() + i),
2475 SDValue(FalseVal.getNode(),
2476 FalseVal.getResNo() + i));
2478 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2479 DAG.getVTList(&ValueVTs[0], NumValues),
2480 &Values[0], NumValues));
2483 void SelectionDAGBuilder::visitTrunc(const User &I) {
2484 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2485 SDValue N = getValue(I.getOperand(0));
2486 EVT DestVT = TLI.getValueType(I.getType());
2487 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2490 void SelectionDAGBuilder::visitZExt(const User &I) {
2491 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2492 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2493 SDValue N = getValue(I.getOperand(0));
2494 EVT DestVT = TLI.getValueType(I.getType());
2495 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2498 void SelectionDAGBuilder::visitSExt(const User &I) {
2499 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2500 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2501 SDValue N = getValue(I.getOperand(0));
2502 EVT DestVT = TLI.getValueType(I.getType());
2503 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2506 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2507 // FPTrunc is never a no-op cast, no need to check
2508 SDValue N = getValue(I.getOperand(0));
2509 EVT DestVT = TLI.getValueType(I.getType());
2510 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2511 DestVT, N, DAG.getIntPtrConstant(0)));
2514 void SelectionDAGBuilder::visitFPExt(const User &I){
2515 // FPTrunc is never a no-op cast, no need to check
2516 SDValue N = getValue(I.getOperand(0));
2517 EVT DestVT = TLI.getValueType(I.getType());
2518 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2521 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2522 // FPToUI is never a no-op cast, no need to check
2523 SDValue N = getValue(I.getOperand(0));
2524 EVT DestVT = TLI.getValueType(I.getType());
2525 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2528 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2529 // FPToSI is never a no-op cast, no need to check
2530 SDValue N = getValue(I.getOperand(0));
2531 EVT DestVT = TLI.getValueType(I.getType());
2532 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2535 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2536 // UIToFP is never a no-op cast, no need to check
2537 SDValue N = getValue(I.getOperand(0));
2538 EVT DestVT = TLI.getValueType(I.getType());
2539 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2542 void SelectionDAGBuilder::visitSIToFP(const User &I){
2543 // SIToFP is never a no-op cast, no need to check
2544 SDValue N = getValue(I.getOperand(0));
2545 EVT DestVT = TLI.getValueType(I.getType());
2546 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2549 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2550 // What to do depends on the size of the integer and the size of the pointer.
2551 // We can either truncate, zero extend, or no-op, accordingly.
2552 SDValue N = getValue(I.getOperand(0));
2553 EVT DestVT = TLI.getValueType(I.getType());
2554 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2557 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2558 // What to do depends on the size of the integer and the size of the pointer.
2559 // We can either truncate, zero extend, or no-op, accordingly.
2560 SDValue N = getValue(I.getOperand(0));
2561 EVT DestVT = TLI.getValueType(I.getType());
2562 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2565 void SelectionDAGBuilder::visitBitCast(const User &I) {
2566 SDValue N = getValue(I.getOperand(0));
2567 EVT DestVT = TLI.getValueType(I.getType());
2569 // BitCast assures us that source and destination are the same size so this is
2570 // either a BITCAST or a no-op.
2571 if (DestVT != N.getValueType())
2572 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2573 DestVT, N)); // convert types.
2575 setValue(&I, N); // noop cast.
2578 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2579 SDValue InVec = getValue(I.getOperand(0));
2580 SDValue InVal = getValue(I.getOperand(1));
2581 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2583 getValue(I.getOperand(2)));
2584 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2585 TLI.getValueType(I.getType()),
2586 InVec, InVal, InIdx));
2589 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2590 SDValue InVec = getValue(I.getOperand(0));
2591 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2593 getValue(I.getOperand(1)));
2594 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2595 TLI.getValueType(I.getType()), InVec, InIdx));
2598 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2599 // from SIndx and increasing to the element length (undefs are allowed).
2600 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2601 unsigned MaskNumElts = Mask.size();
2602 for (unsigned i = 0; i != MaskNumElts; ++i)
2603 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2608 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2609 SmallVector<int, 8> Mask;
2610 SDValue Src1 = getValue(I.getOperand(0));
2611 SDValue Src2 = getValue(I.getOperand(1));
2613 // Convert the ConstantVector mask operand into an array of ints, with -1
2614 // representing undef values.
2615 SmallVector<Constant*, 8> MaskElts;
2616 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2617 unsigned MaskNumElts = MaskElts.size();
2618 for (unsigned i = 0; i != MaskNumElts; ++i) {
2619 if (isa<UndefValue>(MaskElts[i]))
2622 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2625 EVT VT = TLI.getValueType(I.getType());
2626 EVT SrcVT = Src1.getValueType();
2627 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2629 if (SrcNumElts == MaskNumElts) {
2630 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2635 // Normalize the shuffle vector since mask and vector length don't match.
2636 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2637 // Mask is longer than the source vectors and is a multiple of the source
2638 // vectors. We can use concatenate vector to make the mask and vectors
2640 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2641 // The shuffle is concatenating two vectors together.
2642 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2647 // Pad both vectors with undefs to make them the same length as the mask.
2648 unsigned NumConcat = MaskNumElts / SrcNumElts;
2649 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2650 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2651 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2653 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2654 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2658 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2659 getCurDebugLoc(), VT,
2660 &MOps1[0], NumConcat);
2661 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2662 getCurDebugLoc(), VT,
2663 &MOps2[0], NumConcat);
2665 // Readjust mask for new input vector length.
2666 SmallVector<int, 8> MappedOps;
2667 for (unsigned i = 0; i != MaskNumElts; ++i) {
2669 if (Idx < (int)SrcNumElts)
2670 MappedOps.push_back(Idx);
2672 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2675 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2680 if (SrcNumElts > MaskNumElts) {
2681 // Analyze the access pattern of the vector to see if we can extract
2682 // two subvectors and do the shuffle. The analysis is done by calculating
2683 // the range of elements the mask access on both vectors.
2684 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2685 int MaxRange[2] = {-1, -1};
2687 for (unsigned i = 0; i != MaskNumElts; ++i) {
2693 if (Idx >= (int)SrcNumElts) {
2697 if (Idx > MaxRange[Input])
2698 MaxRange[Input] = Idx;
2699 if (Idx < MinRange[Input])
2700 MinRange[Input] = Idx;
2703 // Check if the access is smaller than the vector size and can we find
2704 // a reasonable extract index.
2705 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2707 int StartIdx[2]; // StartIdx to extract from
2708 for (int Input=0; Input < 2; ++Input) {
2709 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2710 RangeUse[Input] = 0; // Unused
2711 StartIdx[Input] = 0;
2712 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2713 // Fits within range but we should see if we can find a good
2714 // start index that is a multiple of the mask length.
2715 if (MaxRange[Input] < (int)MaskNumElts) {
2716 RangeUse[Input] = 1; // Extract from beginning of the vector
2717 StartIdx[Input] = 0;
2719 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2720 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2721 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2722 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2727 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2728 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2731 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2732 // Extract appropriate subvector and generate a vector shuffle
2733 for (int Input=0; Input < 2; ++Input) {
2734 SDValue &Src = Input == 0 ? Src1 : Src2;
2735 if (RangeUse[Input] == 0)
2736 Src = DAG.getUNDEF(VT);
2738 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2739 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2742 // Calculate new mask.
2743 SmallVector<int, 8> MappedOps;
2744 for (unsigned i = 0; i != MaskNumElts; ++i) {
2747 MappedOps.push_back(Idx);
2748 else if (Idx < (int)SrcNumElts)
2749 MappedOps.push_back(Idx - StartIdx[0]);
2751 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2754 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2760 // We can't use either concat vectors or extract subvectors so fall back to
2761 // replacing the shuffle with extract and build vector.
2762 // to insert and build vector.
2763 EVT EltVT = VT.getVectorElementType();
2764 EVT PtrVT = TLI.getPointerTy();
2765 SmallVector<SDValue,8> Ops;
2766 for (unsigned i = 0; i != MaskNumElts; ++i) {
2768 Ops.push_back(DAG.getUNDEF(EltVT));
2773 if (Idx < (int)SrcNumElts)
2774 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2775 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2777 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2779 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2785 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2786 VT, &Ops[0], Ops.size()));
2789 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2790 const Value *Op0 = I.getOperand(0);
2791 const Value *Op1 = I.getOperand(1);
2792 const Type *AggTy = I.getType();
2793 const Type *ValTy = Op1->getType();
2794 bool IntoUndef = isa<UndefValue>(Op0);
2795 bool FromUndef = isa<UndefValue>(Op1);
2797 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2799 SmallVector<EVT, 4> AggValueVTs;
2800 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2801 SmallVector<EVT, 4> ValValueVTs;
2802 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2804 unsigned NumAggValues = AggValueVTs.size();
2805 unsigned NumValValues = ValValueVTs.size();
2806 SmallVector<SDValue, 4> Values(NumAggValues);
2808 SDValue Agg = getValue(Op0);
2809 SDValue Val = getValue(Op1);
2811 // Copy the beginning value(s) from the original aggregate.
2812 for (; i != LinearIndex; ++i)
2813 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2814 SDValue(Agg.getNode(), Agg.getResNo() + i);
2815 // Copy values from the inserted value(s).
2816 for (; i != LinearIndex + NumValValues; ++i)
2817 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2818 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2819 // Copy remaining value(s) from the original aggregate.
2820 for (; i != NumAggValues; ++i)
2821 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2822 SDValue(Agg.getNode(), Agg.getResNo() + i);
2824 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2825 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2826 &Values[0], NumAggValues));
2829 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2830 const Value *Op0 = I.getOperand(0);
2831 const Type *AggTy = Op0->getType();
2832 const Type *ValTy = I.getType();
2833 bool OutOfUndef = isa<UndefValue>(Op0);
2835 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2837 SmallVector<EVT, 4> ValValueVTs;
2838 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2840 unsigned NumValValues = ValValueVTs.size();
2841 SmallVector<SDValue, 4> Values(NumValValues);
2843 SDValue Agg = getValue(Op0);
2844 // Copy out the selected value(s).
2845 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2846 Values[i - LinearIndex] =
2848 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2849 SDValue(Agg.getNode(), Agg.getResNo() + i);
2851 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2852 DAG.getVTList(&ValValueVTs[0], NumValValues),
2853 &Values[0], NumValValues));
2856 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2857 SDValue N = getValue(I.getOperand(0));
2858 const Type *Ty = I.getOperand(0)->getType();
2860 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2862 const Value *Idx = *OI;
2863 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2864 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2867 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2868 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2869 DAG.getIntPtrConstant(Offset));
2872 Ty = StTy->getElementType(Field);
2874 Ty = cast<SequentialType>(Ty)->getElementType();
2876 // If this is a constant subscript, handle it quickly.
2877 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2878 if (CI->isZero()) continue;
2880 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2882 EVT PTy = TLI.getPointerTy();
2883 unsigned PtrBits = PTy.getSizeInBits();
2885 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2887 DAG.getConstant(Offs, MVT::i64));
2889 OffsVal = DAG.getIntPtrConstant(Offs);
2891 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2896 // N = N + Idx * ElementSize;
2897 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2898 TD->getTypeAllocSize(Ty));
2899 SDValue IdxN = getValue(Idx);
2901 // If the index is smaller or larger than intptr_t, truncate or extend
2903 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2905 // If this is a multiply by a power of two, turn it into a shl
2906 // immediately. This is a very common case.
2907 if (ElementSize != 1) {
2908 if (ElementSize.isPowerOf2()) {
2909 unsigned Amt = ElementSize.logBase2();
2910 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2911 N.getValueType(), IdxN,
2912 DAG.getConstant(Amt, TLI.getPointerTy()));
2914 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2915 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2916 N.getValueType(), IdxN, Scale);
2920 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2921 N.getValueType(), N, IdxN);
2928 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2929 // If this is a fixed sized alloca in the entry block of the function,
2930 // allocate it statically on the stack.
2931 if (FuncInfo.StaticAllocaMap.count(&I))
2932 return; // getValue will auto-populate this.
2934 const Type *Ty = I.getAllocatedType();
2935 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2937 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2940 SDValue AllocSize = getValue(I.getArraySize());
2942 EVT IntPtr = TLI.getPointerTy();
2943 if (AllocSize.getValueType() != IntPtr)
2944 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2946 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2948 DAG.getConstant(TySize, IntPtr));
2950 // Handle alignment. If the requested alignment is less than or equal to
2951 // the stack alignment, ignore it. If the size is greater than or equal to
2952 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2953 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2954 if (Align <= StackAlign)
2957 // Round the size of the allocation up to the stack alignment size
2958 // by add SA-1 to the size.
2959 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2960 AllocSize.getValueType(), AllocSize,
2961 DAG.getIntPtrConstant(StackAlign-1));
2963 // Mask out the low bits for alignment purposes.
2964 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2965 AllocSize.getValueType(), AllocSize,
2966 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2968 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2969 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2970 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2973 DAG.setRoot(DSA.getValue(1));
2975 // Inform the Frame Information that we have just allocated a variable-sized
2977 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2980 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2981 const Value *SV = I.getOperand(0);
2982 SDValue Ptr = getValue(SV);
2984 const Type *Ty = I.getType();
2986 bool isVolatile = I.isVolatile();
2987 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2988 unsigned Alignment = I.getAlignment();
2989 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
2991 SmallVector<EVT, 4> ValueVTs;
2992 SmallVector<uint64_t, 4> Offsets;
2993 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2994 unsigned NumValues = ValueVTs.size();
2999 bool ConstantMemory = false;
3000 if (I.isVolatile() || NumValues > MaxParallelChains)
3001 // Serialize volatile loads with other side effects.
3003 else if (AA->pointsToConstantMemory(
3004 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3005 // Do not serialize (non-volatile) loads of constant memory with anything.
3006 Root = DAG.getEntryNode();
3007 ConstantMemory = true;
3009 // Do not serialize non-volatile loads against each other.
3010 Root = DAG.getRoot();
3013 SmallVector<SDValue, 4> Values(NumValues);
3014 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3016 EVT PtrVT = Ptr.getValueType();
3017 unsigned ChainI = 0;
3018 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3019 // Serializing loads here may result in excessive register pressure, and
3020 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3021 // could recover a bit by hoisting nodes upward in the chain by recognizing
3022 // they are side-effect free or do not alias. The optimizer should really
3023 // avoid this case by converting large object/array copies to llvm.memcpy
3024 // (MaxParallelChains should always remain as failsafe).
3025 if (ChainI == MaxParallelChains) {
3026 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3027 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3028 MVT::Other, &Chains[0], ChainI);
3032 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3034 DAG.getConstant(Offsets[i], PtrVT));
3035 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3036 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3037 isNonTemporal, Alignment, TBAAInfo);
3040 Chains[ChainI] = L.getValue(1);
3043 if (!ConstantMemory) {
3044 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3045 MVT::Other, &Chains[0], ChainI);
3049 PendingLoads.push_back(Chain);
3052 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3053 DAG.getVTList(&ValueVTs[0], NumValues),
3054 &Values[0], NumValues));
3057 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3058 const Value *SrcV = I.getOperand(0);
3059 const Value *PtrV = I.getOperand(1);
3061 SmallVector<EVT, 4> ValueVTs;
3062 SmallVector<uint64_t, 4> Offsets;
3063 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3064 unsigned NumValues = ValueVTs.size();
3068 // Get the lowered operands. Note that we do this after
3069 // checking if NumResults is zero, because with zero results
3070 // the operands won't have values in the map.
3071 SDValue Src = getValue(SrcV);
3072 SDValue Ptr = getValue(PtrV);
3074 SDValue Root = getRoot();
3075 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3077 EVT PtrVT = Ptr.getValueType();
3078 bool isVolatile = I.isVolatile();
3079 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3080 unsigned Alignment = I.getAlignment();
3081 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3083 unsigned ChainI = 0;
3084 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3085 // See visitLoad comments.
3086 if (ChainI == MaxParallelChains) {
3087 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3088 MVT::Other, &Chains[0], ChainI);
3092 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3093 DAG.getConstant(Offsets[i], PtrVT));
3094 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3095 SDValue(Src.getNode(), Src.getResNo() + i),
3096 Add, MachinePointerInfo(PtrV, Offsets[i]),
3097 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3098 Chains[ChainI] = St;
3101 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3102 MVT::Other, &Chains[0], ChainI);
3104 AssignOrderingToNode(StoreNode.getNode());
3105 DAG.setRoot(StoreNode);
3108 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3110 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3111 unsigned Intrinsic) {
3112 bool HasChain = !I.doesNotAccessMemory();
3113 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3115 // Build the operand list.
3116 SmallVector<SDValue, 8> Ops;
3117 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3119 // We don't need to serialize loads against other loads.
3120 Ops.push_back(DAG.getRoot());
3122 Ops.push_back(getRoot());
3126 // Info is set by getTgtMemInstrinsic
3127 TargetLowering::IntrinsicInfo Info;
3128 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3130 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3131 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3132 Info.opc == ISD::INTRINSIC_W_CHAIN)
3133 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3135 // Add all operands of the call to the operand list.
3136 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3137 SDValue Op = getValue(I.getArgOperand(i));
3138 assert(TLI.isTypeLegal(Op.getValueType()) &&
3139 "Intrinsic uses a non-legal type?");
3143 SmallVector<EVT, 4> ValueVTs;
3144 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3146 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3147 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3148 "Intrinsic uses a non-legal type?");
3153 ValueVTs.push_back(MVT::Other);
3155 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3159 if (IsTgtIntrinsic) {
3160 // This is target intrinsic that touches memory
3161 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3162 VTs, &Ops[0], Ops.size(),
3164 MachinePointerInfo(Info.ptrVal, Info.offset),
3165 Info.align, Info.vol,
3166 Info.readMem, Info.writeMem);
3167 } else if (!HasChain) {
3168 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3169 VTs, &Ops[0], Ops.size());
3170 } else if (!I.getType()->isVoidTy()) {
3171 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3172 VTs, &Ops[0], Ops.size());
3174 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3175 VTs, &Ops[0], Ops.size());
3179 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3181 PendingLoads.push_back(Chain);
3186 if (!I.getType()->isVoidTy()) {
3187 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3188 EVT VT = TLI.getValueType(PTy);
3189 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3192 setValue(&I, Result);
3196 /// GetSignificand - Get the significand and build it into a floating-point
3197 /// number with exponent of 1:
3199 /// Op = (Op & 0x007fffff) | 0x3f800000;
3201 /// where Op is the hexidecimal representation of floating point value.
3203 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3204 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3205 DAG.getConstant(0x007fffff, MVT::i32));
3206 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3207 DAG.getConstant(0x3f800000, MVT::i32));
3208 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3211 /// GetExponent - Get the exponent:
3213 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3215 /// where Op is the hexidecimal representation of floating point value.
3217 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3219 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3220 DAG.getConstant(0x7f800000, MVT::i32));
3221 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3222 DAG.getConstant(23, TLI.getPointerTy()));
3223 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3224 DAG.getConstant(127, MVT::i32));
3225 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3228 /// getF32Constant - Get 32-bit floating point constant.
3230 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3231 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3234 /// Inlined utility function to implement binary input atomic intrinsics for
3235 /// visitIntrinsicCall: I is a call instruction
3236 /// Op is the associated NodeType for I
3238 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3240 SDValue Root = getRoot();
3242 DAG.getAtomic(Op, getCurDebugLoc(),
3243 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3245 getValue(I.getArgOperand(0)),
3246 getValue(I.getArgOperand(1)),
3247 I.getArgOperand(0));
3249 DAG.setRoot(L.getValue(1));
3253 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3255 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3256 SDValue Op1 = getValue(I.getArgOperand(0));
3257 SDValue Op2 = getValue(I.getArgOperand(1));
3259 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3260 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3264 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3265 /// limited-precision mode.
3267 SelectionDAGBuilder::visitExp(const CallInst &I) {
3269 DebugLoc dl = getCurDebugLoc();
3271 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3272 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3273 SDValue Op = getValue(I.getArgOperand(0));
3275 // Put the exponent in the right bit position for later addition to the
3278 // #define LOG2OFe 1.4426950f
3279 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3280 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3281 getF32Constant(DAG, 0x3fb8aa3b));
3282 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3284 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3285 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3286 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3288 // IntegerPartOfX <<= 23;
3289 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3290 DAG.getConstant(23, TLI.getPointerTy()));
3292 if (LimitFloatPrecision <= 6) {
3293 // For floating-point precision of 6:
3295 // TwoToFractionalPartOfX =
3297 // (0.735607626f + 0.252464424f * x) * x;
3299 // error 0.0144103317, which is 6 bits
3300 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3301 getF32Constant(DAG, 0x3e814304));
3302 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3303 getF32Constant(DAG, 0x3f3c50c8));
3304 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3305 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3306 getF32Constant(DAG, 0x3f7f5e7e));
3307 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3309 // Add the exponent into the result in integer domain.
3310 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3311 TwoToFracPartOfX, IntegerPartOfX);
3313 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3314 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3315 // For floating-point precision of 12:
3317 // TwoToFractionalPartOfX =
3320 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3322 // 0.000107046256 error, which is 13 to 14 bits
3323 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3324 getF32Constant(DAG, 0x3da235e3));
3325 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3326 getF32Constant(DAG, 0x3e65b8f3));
3327 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3328 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3329 getF32Constant(DAG, 0x3f324b07));
3330 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3331 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3332 getF32Constant(DAG, 0x3f7ff8fd));
3333 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3335 // Add the exponent into the result in integer domain.
3336 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3337 TwoToFracPartOfX, IntegerPartOfX);
3339 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3340 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3341 // For floating-point precision of 18:
3343 // TwoToFractionalPartOfX =
3347 // (0.554906021e-1f +
3348 // (0.961591928e-2f +
3349 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3351 // error 2.47208000*10^(-7), which is better than 18 bits
3352 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3353 getF32Constant(DAG, 0x3924b03e));
3354 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3355 getF32Constant(DAG, 0x3ab24b87));
3356 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3357 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3358 getF32Constant(DAG, 0x3c1d8c17));
3359 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3360 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3361 getF32Constant(DAG, 0x3d634a1d));
3362 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3363 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3364 getF32Constant(DAG, 0x3e75fe14));
3365 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3366 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3367 getF32Constant(DAG, 0x3f317234));
3368 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3369 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3370 getF32Constant(DAG, 0x3f800000));
3371 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3374 // Add the exponent into the result in integer domain.
3375 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3376 TwoToFracPartOfX, IntegerPartOfX);
3378 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3381 // No special expansion.
3382 result = DAG.getNode(ISD::FEXP, dl,
3383 getValue(I.getArgOperand(0)).getValueType(),
3384 getValue(I.getArgOperand(0)));
3387 setValue(&I, result);
3390 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3391 /// limited-precision mode.
3393 SelectionDAGBuilder::visitLog(const CallInst &I) {
3395 DebugLoc dl = getCurDebugLoc();
3397 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3398 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3399 SDValue Op = getValue(I.getArgOperand(0));
3400 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3402 // Scale the exponent by log(2) [0.69314718f].
3403 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3404 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3405 getF32Constant(DAG, 0x3f317218));
3407 // Get the significand and build it into a floating-point number with
3409 SDValue X = GetSignificand(DAG, Op1, dl);
3411 if (LimitFloatPrecision <= 6) {
3412 // For floating-point precision of 6:
3416 // (1.4034025f - 0.23903021f * x) * x;
3418 // error 0.0034276066, which is better than 8 bits
3419 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3420 getF32Constant(DAG, 0xbe74c456));
3421 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3422 getF32Constant(DAG, 0x3fb3a2b1));
3423 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3424 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3425 getF32Constant(DAG, 0x3f949a29));
3427 result = DAG.getNode(ISD::FADD, dl,
3428 MVT::f32, LogOfExponent, LogOfMantissa);
3429 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3430 // For floating-point precision of 12:
3436 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3438 // error 0.000061011436, which is 14 bits
3439 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3440 getF32Constant(DAG, 0xbd67b6d6));
3441 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3442 getF32Constant(DAG, 0x3ee4f4b8));
3443 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3444 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3445 getF32Constant(DAG, 0x3fbc278b));
3446 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3447 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3448 getF32Constant(DAG, 0x40348e95));
3449 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3450 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3451 getF32Constant(DAG, 0x3fdef31a));
3453 result = DAG.getNode(ISD::FADD, dl,
3454 MVT::f32, LogOfExponent, LogOfMantissa);
3455 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3456 // For floating-point precision of 18:
3464 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3466 // error 0.0000023660568, which is better than 18 bits
3467 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3468 getF32Constant(DAG, 0xbc91e5ac));
3469 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3470 getF32Constant(DAG, 0x3e4350aa));
3471 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3472 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3473 getF32Constant(DAG, 0x3f60d3e3));
3474 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3475 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3476 getF32Constant(DAG, 0x4011cdf0));
3477 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3478 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3479 getF32Constant(DAG, 0x406cfd1c));
3480 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3481 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3482 getF32Constant(DAG, 0x408797cb));
3483 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3484 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3485 getF32Constant(DAG, 0x4006dcab));
3487 result = DAG.getNode(ISD::FADD, dl,
3488 MVT::f32, LogOfExponent, LogOfMantissa);
3491 // No special expansion.
3492 result = DAG.getNode(ISD::FLOG, dl,
3493 getValue(I.getArgOperand(0)).getValueType(),
3494 getValue(I.getArgOperand(0)));
3497 setValue(&I, result);
3500 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3501 /// limited-precision mode.
3503 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3505 DebugLoc dl = getCurDebugLoc();
3507 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3508 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3509 SDValue Op = getValue(I.getArgOperand(0));
3510 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3512 // Get the exponent.
3513 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3515 // Get the significand and build it into a floating-point number with
3517 SDValue X = GetSignificand(DAG, Op1, dl);
3519 // Different possible minimax approximations of significand in
3520 // floating-point for various degrees of accuracy over [1,2].
3521 if (LimitFloatPrecision <= 6) {
3522 // For floating-point precision of 6:
3524 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3526 // error 0.0049451742, which is more than 7 bits
3527 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3528 getF32Constant(DAG, 0xbeb08fe0));
3529 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3530 getF32Constant(DAG, 0x40019463));
3531 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3532 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3533 getF32Constant(DAG, 0x3fd6633d));
3535 result = DAG.getNode(ISD::FADD, dl,
3536 MVT::f32, LogOfExponent, Log2ofMantissa);
3537 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3538 // For floating-point precision of 12:
3544 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3546 // error 0.0000876136000, which is better than 13 bits
3547 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3548 getF32Constant(DAG, 0xbda7262e));
3549 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3550 getF32Constant(DAG, 0x3f25280b));
3551 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3552 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3553 getF32Constant(DAG, 0x4007b923));
3554 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3555 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3556 getF32Constant(DAG, 0x40823e2f));
3557 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3558 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3559 getF32Constant(DAG, 0x4020d29c));
3561 result = DAG.getNode(ISD::FADD, dl,
3562 MVT::f32, LogOfExponent, Log2ofMantissa);
3563 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3564 // For floating-point precision of 18:
3573 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3575 // error 0.0000018516, which is better than 18 bits
3576 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3577 getF32Constant(DAG, 0xbcd2769e));
3578 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3579 getF32Constant(DAG, 0x3e8ce0b9));
3580 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3581 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3582 getF32Constant(DAG, 0x3fa22ae7));
3583 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3584 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3585 getF32Constant(DAG, 0x40525723));
3586 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3587 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3588 getF32Constant(DAG, 0x40aaf200));
3589 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3590 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3591 getF32Constant(DAG, 0x40c39dad));
3592 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3593 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3594 getF32Constant(DAG, 0x4042902c));
3596 result = DAG.getNode(ISD::FADD, dl,
3597 MVT::f32, LogOfExponent, Log2ofMantissa);
3600 // No special expansion.
3601 result = DAG.getNode(ISD::FLOG2, dl,
3602 getValue(I.getArgOperand(0)).getValueType(),
3603 getValue(I.getArgOperand(0)));
3606 setValue(&I, result);
3609 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3610 /// limited-precision mode.
3612 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3614 DebugLoc dl = getCurDebugLoc();
3616 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3617 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3618 SDValue Op = getValue(I.getArgOperand(0));
3619 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3621 // Scale the exponent by log10(2) [0.30102999f].
3622 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3623 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3624 getF32Constant(DAG, 0x3e9a209a));
3626 // Get the significand and build it into a floating-point number with
3628 SDValue X = GetSignificand(DAG, Op1, dl);
3630 if (LimitFloatPrecision <= 6) {
3631 // For floating-point precision of 6:
3633 // Log10ofMantissa =
3635 // (0.60948995f - 0.10380950f * x) * x;
3637 // error 0.0014886165, which is 6 bits
3638 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3639 getF32Constant(DAG, 0xbdd49a13));
3640 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3641 getF32Constant(DAG, 0x3f1c0789));
3642 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3643 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3644 getF32Constant(DAG, 0x3f011300));
3646 result = DAG.getNode(ISD::FADD, dl,
3647 MVT::f32, LogOfExponent, Log10ofMantissa);
3648 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3649 // For floating-point precision of 12:
3651 // Log10ofMantissa =
3654 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3656 // error 0.00019228036, which is better than 12 bits
3657 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3658 getF32Constant(DAG, 0x3d431f31));
3659 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3660 getF32Constant(DAG, 0x3ea21fb2));
3661 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3662 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3663 getF32Constant(DAG, 0x3f6ae232));
3664 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3665 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3666 getF32Constant(DAG, 0x3f25f7c3));
3668 result = DAG.getNode(ISD::FADD, dl,
3669 MVT::f32, LogOfExponent, Log10ofMantissa);
3670 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3671 // For floating-point precision of 18:
3673 // Log10ofMantissa =
3678 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3680 // error 0.0000037995730, which is better than 18 bits
3681 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3682 getF32Constant(DAG, 0x3c5d51ce));
3683 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3684 getF32Constant(DAG, 0x3e00685a));
3685 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3686 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3687 getF32Constant(DAG, 0x3efb6798));
3688 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3689 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3690 getF32Constant(DAG, 0x3f88d192));
3691 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3692 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3693 getF32Constant(DAG, 0x3fc4316c));
3694 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3695 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3696 getF32Constant(DAG, 0x3f57ce70));
3698 result = DAG.getNode(ISD::FADD, dl,
3699 MVT::f32, LogOfExponent, Log10ofMantissa);
3702 // No special expansion.
3703 result = DAG.getNode(ISD::FLOG10, dl,
3704 getValue(I.getArgOperand(0)).getValueType(),
3705 getValue(I.getArgOperand(0)));
3708 setValue(&I, result);
3711 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3712 /// limited-precision mode.
3714 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3716 DebugLoc dl = getCurDebugLoc();
3718 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3719 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3720 SDValue Op = getValue(I.getArgOperand(0));
3722 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3724 // FractionalPartOfX = x - (float)IntegerPartOfX;
3725 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3726 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3728 // IntegerPartOfX <<= 23;
3729 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3730 DAG.getConstant(23, TLI.getPointerTy()));
3732 if (LimitFloatPrecision <= 6) {
3733 // For floating-point precision of 6:
3735 // TwoToFractionalPartOfX =
3737 // (0.735607626f + 0.252464424f * x) * x;
3739 // error 0.0144103317, which is 6 bits
3740 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3741 getF32Constant(DAG, 0x3e814304));
3742 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3743 getF32Constant(DAG, 0x3f3c50c8));
3744 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3745 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3746 getF32Constant(DAG, 0x3f7f5e7e));
3747 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3748 SDValue TwoToFractionalPartOfX =
3749 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3751 result = DAG.getNode(ISD::BITCAST, dl,
3752 MVT::f32, TwoToFractionalPartOfX);
3753 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3754 // For floating-point precision of 12:
3756 // TwoToFractionalPartOfX =
3759 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3761 // error 0.000107046256, which is 13 to 14 bits
3762 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3763 getF32Constant(DAG, 0x3da235e3));
3764 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3765 getF32Constant(DAG, 0x3e65b8f3));
3766 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3767 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3768 getF32Constant(DAG, 0x3f324b07));
3769 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3770 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3771 getF32Constant(DAG, 0x3f7ff8fd));
3772 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3773 SDValue TwoToFractionalPartOfX =
3774 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3776 result = DAG.getNode(ISD::BITCAST, dl,
3777 MVT::f32, TwoToFractionalPartOfX);
3778 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3779 // For floating-point precision of 18:
3781 // TwoToFractionalPartOfX =
3785 // (0.554906021e-1f +
3786 // (0.961591928e-2f +
3787 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3788 // error 2.47208000*10^(-7), which is better than 18 bits
3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3790 getF32Constant(DAG, 0x3924b03e));
3791 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3792 getF32Constant(DAG, 0x3ab24b87));
3793 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3794 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3795 getF32Constant(DAG, 0x3c1d8c17));
3796 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3797 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3798 getF32Constant(DAG, 0x3d634a1d));
3799 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3800 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3801 getF32Constant(DAG, 0x3e75fe14));
3802 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3803 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3804 getF32Constant(DAG, 0x3f317234));
3805 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3806 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3807 getF32Constant(DAG, 0x3f800000));
3808 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3809 SDValue TwoToFractionalPartOfX =
3810 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3812 result = DAG.getNode(ISD::BITCAST, dl,
3813 MVT::f32, TwoToFractionalPartOfX);
3816 // No special expansion.
3817 result = DAG.getNode(ISD::FEXP2, dl,
3818 getValue(I.getArgOperand(0)).getValueType(),
3819 getValue(I.getArgOperand(0)));
3822 setValue(&I, result);
3825 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3826 /// limited-precision mode with x == 10.0f.
3828 SelectionDAGBuilder::visitPow(const CallInst &I) {
3830 const Value *Val = I.getArgOperand(0);
3831 DebugLoc dl = getCurDebugLoc();
3832 bool IsExp10 = false;
3834 if (getValue(Val).getValueType() == MVT::f32 &&
3835 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3836 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3837 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3838 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3840 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3845 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3846 SDValue Op = getValue(I.getArgOperand(1));
3848 // Put the exponent in the right bit position for later addition to the
3851 // #define LOG2OF10 3.3219281f
3852 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3853 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3854 getF32Constant(DAG, 0x40549a78));
3855 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3857 // FractionalPartOfX = x - (float)IntegerPartOfX;
3858 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3859 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3861 // IntegerPartOfX <<= 23;
3862 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3863 DAG.getConstant(23, TLI.getPointerTy()));
3865 if (LimitFloatPrecision <= 6) {
3866 // For floating-point precision of 6:
3868 // twoToFractionalPartOfX =
3870 // (0.735607626f + 0.252464424f * x) * x;
3872 // error 0.0144103317, which is 6 bits
3873 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3874 getF32Constant(DAG, 0x3e814304));
3875 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3876 getF32Constant(DAG, 0x3f3c50c8));
3877 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3878 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3879 getF32Constant(DAG, 0x3f7f5e7e));
3880 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3881 SDValue TwoToFractionalPartOfX =
3882 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3884 result = DAG.getNode(ISD::BITCAST, dl,
3885 MVT::f32, TwoToFractionalPartOfX);
3886 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3887 // For floating-point precision of 12:
3889 // TwoToFractionalPartOfX =
3892 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3894 // error 0.000107046256, which is 13 to 14 bits
3895 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3896 getF32Constant(DAG, 0x3da235e3));
3897 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3898 getF32Constant(DAG, 0x3e65b8f3));
3899 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3900 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3901 getF32Constant(DAG, 0x3f324b07));
3902 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3903 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3904 getF32Constant(DAG, 0x3f7ff8fd));
3905 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3906 SDValue TwoToFractionalPartOfX =
3907 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3909 result = DAG.getNode(ISD::BITCAST, dl,
3910 MVT::f32, TwoToFractionalPartOfX);
3911 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3912 // For floating-point precision of 18:
3914 // TwoToFractionalPartOfX =
3918 // (0.554906021e-1f +
3919 // (0.961591928e-2f +
3920 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3921 // error 2.47208000*10^(-7), which is better than 18 bits
3922 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3923 getF32Constant(DAG, 0x3924b03e));
3924 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3925 getF32Constant(DAG, 0x3ab24b87));
3926 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3927 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3928 getF32Constant(DAG, 0x3c1d8c17));
3929 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3930 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3931 getF32Constant(DAG, 0x3d634a1d));
3932 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3933 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3934 getF32Constant(DAG, 0x3e75fe14));
3935 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3936 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3937 getF32Constant(DAG, 0x3f317234));
3938 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3939 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3940 getF32Constant(DAG, 0x3f800000));
3941 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3942 SDValue TwoToFractionalPartOfX =
3943 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3945 result = DAG.getNode(ISD::BITCAST, dl,
3946 MVT::f32, TwoToFractionalPartOfX);
3949 // No special expansion.
3950 result = DAG.getNode(ISD::FPOW, dl,
3951 getValue(I.getArgOperand(0)).getValueType(),
3952 getValue(I.getArgOperand(0)),
3953 getValue(I.getArgOperand(1)));
3956 setValue(&I, result);
3960 /// ExpandPowI - Expand a llvm.powi intrinsic.
3961 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3962 SelectionDAG &DAG) {
3963 // If RHS is a constant, we can expand this out to a multiplication tree,
3964 // otherwise we end up lowering to a call to __powidf2 (for example). When
3965 // optimizing for size, we only want to do this if the expansion would produce
3966 // a small number of multiplies, otherwise we do the full expansion.
3967 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3968 // Get the exponent as a positive value.
3969 unsigned Val = RHSC->getSExtValue();
3970 if ((int)Val < 0) Val = -Val;
3972 // powi(x, 0) -> 1.0
3974 return DAG.getConstantFP(1.0, LHS.getValueType());
3976 const Function *F = DAG.getMachineFunction().getFunction();
3977 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3978 // If optimizing for size, don't insert too many multiplies. This
3979 // inserts up to 5 multiplies.
3980 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3981 // We use the simple binary decomposition method to generate the multiply
3982 // sequence. There are more optimal ways to do this (for example,
3983 // powi(x,15) generates one more multiply than it should), but this has
3984 // the benefit of being both really simple and much better than a libcall.
3985 SDValue Res; // Logically starts equal to 1.0
3986 SDValue CurSquare = LHS;
3990 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3992 Res = CurSquare; // 1.0*CurSquare.
3995 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3996 CurSquare, CurSquare);
4000 // If the original was negative, invert the result, producing 1/(x*x*x).
4001 if (RHSC->getSExtValue() < 0)
4002 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4003 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4008 // Otherwise, expand to a libcall.
4009 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4012 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4013 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4014 /// At the end of instruction selection, they will be inserted to the entry BB.
4016 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4019 const Argument *Arg = dyn_cast<Argument>(V);
4023 MachineFunction &MF = DAG.getMachineFunction();
4024 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4025 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4027 // Ignore inlined function arguments here.
4028 DIVariable DV(Variable);
4029 if (DV.isInlinedFnArgument(MF.getFunction()))
4032 MachineBasicBlock *MBB = FuncInfo.MBB;
4033 if (MBB != &MF.front())
4037 if (Arg->hasByValAttr()) {
4038 // Byval arguments' frame index is recorded during argument lowering.
4039 // Use this info directly.
4040 Reg = TRI->getFrameRegister(MF);
4041 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4042 // If byval argument ofset is not recorded then ignore this.
4047 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4048 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4049 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4050 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4051 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4058 // Check if ValueMap has reg number.
4059 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4060 if (VMI != FuncInfo.ValueMap.end())
4064 if (!Reg && N.getNode()) {
4065 // Check if frame index is available.
4066 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4067 if (FrameIndexSDNode *FINode =
4068 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4069 Reg = TRI->getFrameRegister(MF);
4070 Offset = FINode->getIndex();
4077 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4078 TII->get(TargetOpcode::DBG_VALUE))
4079 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4080 FuncInfo.ArgDbgValues.push_back(&*MIB);
4084 // VisualStudio defines setjmp as _setjmp
4085 #if defined(_MSC_VER) && defined(setjmp) && \
4086 !defined(setjmp_undefined_for_msvc)
4087 # pragma push_macro("setjmp")
4089 # define setjmp_undefined_for_msvc
4092 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4093 /// we want to emit this as a call to a named external function, return the name
4094 /// otherwise lower it and return null.
4096 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4097 DebugLoc dl = getCurDebugLoc();
4100 switch (Intrinsic) {
4102 // By default, turn this into a target intrinsic node.
4103 visitTargetIntrinsic(I, Intrinsic);
4105 case Intrinsic::vastart: visitVAStart(I); return 0;
4106 case Intrinsic::vaend: visitVAEnd(I); return 0;
4107 case Intrinsic::vacopy: visitVACopy(I); return 0;
4108 case Intrinsic::returnaddress:
4109 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4110 getValue(I.getArgOperand(0))));
4112 case Intrinsic::frameaddress:
4113 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4114 getValue(I.getArgOperand(0))));
4116 case Intrinsic::setjmp:
4117 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4118 case Intrinsic::longjmp:
4119 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4120 case Intrinsic::memcpy: {
4121 // Assert for address < 256 since we support only user defined address
4123 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4125 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4127 "Unknown address space");
4128 SDValue Op1 = getValue(I.getArgOperand(0));
4129 SDValue Op2 = getValue(I.getArgOperand(1));
4130 SDValue Op3 = getValue(I.getArgOperand(2));
4131 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4132 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4133 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4134 MachinePointerInfo(I.getArgOperand(0)),
4135 MachinePointerInfo(I.getArgOperand(1))));
4138 case Intrinsic::memset: {
4139 // Assert for address < 256 since we support only user defined address
4141 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4143 "Unknown address space");
4144 SDValue Op1 = getValue(I.getArgOperand(0));
4145 SDValue Op2 = getValue(I.getArgOperand(1));
4146 SDValue Op3 = getValue(I.getArgOperand(2));
4147 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4148 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4149 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4150 MachinePointerInfo(I.getArgOperand(0))));
4153 case Intrinsic::memmove: {
4154 // Assert for address < 256 since we support only user defined address
4156 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4158 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4160 "Unknown address space");
4161 SDValue Op1 = getValue(I.getArgOperand(0));
4162 SDValue Op2 = getValue(I.getArgOperand(1));
4163 SDValue Op3 = getValue(I.getArgOperand(2));
4164 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4165 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4166 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4167 MachinePointerInfo(I.getArgOperand(0)),
4168 MachinePointerInfo(I.getArgOperand(1))));
4171 case Intrinsic::dbg_declare: {
4172 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4173 MDNode *Variable = DI.getVariable();
4174 const Value *Address = DI.getAddress();
4175 if (!Address || !DIVariable(DI.getVariable()).Verify())
4178 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4179 // but do not always have a corresponding SDNode built. The SDNodeOrder
4180 // absolute, but not relative, values are different depending on whether
4181 // debug info exists.
4184 // Check if address has undef value.
4185 if (isa<UndefValue>(Address) ||
4186 (Address->use_empty() && !isa<Argument>(Address))) {
4187 DEBUG(dbgs() << "Dropping debug info for " << DI);
4191 SDValue &N = NodeMap[Address];
4192 if (!N.getNode() && isa<Argument>(Address))
4193 // Check unused arguments map.
4194 N = UnusedArgNodeMap[Address];
4197 // Parameters are handled specially.
4199 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4200 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4201 Address = BCI->getOperand(0);
4202 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4204 if (isParameter && !AI) {
4205 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4207 // Byval parameter. We have a frame index at this point.
4208 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4209 0, dl, SDNodeOrder);
4211 // Can't do anything with other non-AI cases yet. This might be a
4212 // parameter of a callee function that got inlined, for example.
4213 DEBUG(dbgs() << "Dropping debug info for " << DI);
4217 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4218 0, dl, SDNodeOrder);
4220 // Can't do anything with other non-AI cases yet.
4221 DEBUG(dbgs() << "Dropping debug info for " << DI);
4224 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4226 // If Address is an argument then try to emit its dbg value using
4227 // virtual register info from the FuncInfo.ValueMap.
4228 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4229 // If variable is pinned by a alloca in dominating bb then
4230 // use StaticAllocaMap.
4231 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4232 if (AI->getParent() != DI.getParent()) {
4233 DenseMap<const AllocaInst*, int>::iterator SI =
4234 FuncInfo.StaticAllocaMap.find(AI);
4235 if (SI != FuncInfo.StaticAllocaMap.end()) {
4236 SDV = DAG.getDbgValue(Variable, SI->second,
4237 0, dl, SDNodeOrder);
4238 DAG.AddDbgValue(SDV, 0, false);
4243 DEBUG(dbgs() << "Dropping debug info for " << DI);
4248 case Intrinsic::dbg_value: {
4249 const DbgValueInst &DI = cast<DbgValueInst>(I);
4250 if (!DIVariable(DI.getVariable()).Verify())
4253 MDNode *Variable = DI.getVariable();
4254 uint64_t Offset = DI.getOffset();
4255 const Value *V = DI.getValue();
4259 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4260 // but do not always have a corresponding SDNode built. The SDNodeOrder
4261 // absolute, but not relative, values are different depending on whether
4262 // debug info exists.
4265 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4266 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4267 DAG.AddDbgValue(SDV, 0, false);
4269 // Do not use getValue() in here; we don't want to generate code at
4270 // this point if it hasn't been done yet.
4271 SDValue N = NodeMap[V];
4272 if (!N.getNode() && isa<Argument>(V))
4273 // Check unused arguments map.
4274 N = UnusedArgNodeMap[V];
4276 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4277 SDV = DAG.getDbgValue(Variable, N.getNode(),
4278 N.getResNo(), Offset, dl, SDNodeOrder);
4279 DAG.AddDbgValue(SDV, N.getNode(), false);
4281 } else if (!V->use_empty() ) {
4282 // Do not call getValue(V) yet, as we don't want to generate code.
4283 // Remember it for later.
4284 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4285 DanglingDebugInfoMap[V] = DDI;
4287 // We may expand this to cover more cases. One case where we have no
4288 // data available is an unreferenced parameter.
4289 DEBUG(dbgs() << "Dropping debug info for " << DI);
4293 // Build a debug info table entry.
4294 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4295 V = BCI->getOperand(0);
4296 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4297 // Don't handle byval struct arguments or VLAs, for example.
4300 DenseMap<const AllocaInst*, int>::iterator SI =
4301 FuncInfo.StaticAllocaMap.find(AI);
4302 if (SI == FuncInfo.StaticAllocaMap.end())
4304 int FI = SI->second;
4306 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4307 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4308 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4311 case Intrinsic::eh_exception: {
4312 // Insert the EXCEPTIONADDR instruction.
4313 assert(FuncInfo.MBB->isLandingPad() &&
4314 "Call to eh.exception not in landing pad!");
4315 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4317 Ops[0] = DAG.getRoot();
4318 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4320 DAG.setRoot(Op.getValue(1));
4324 case Intrinsic::eh_selector: {
4325 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4326 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4327 if (CallMBB->isLandingPad())
4328 AddCatchInfo(I, &MMI, CallMBB);
4331 FuncInfo.CatchInfoLost.insert(&I);
4333 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4334 unsigned Reg = TLI.getExceptionSelectorRegister();
4335 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4338 // Insert the EHSELECTION instruction.
4339 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4341 Ops[0] = getValue(I.getArgOperand(0));
4343 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4344 DAG.setRoot(Op.getValue(1));
4345 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4349 case Intrinsic::eh_typeid_for: {
4350 // Find the type id for the given typeinfo.
4351 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4352 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4353 Res = DAG.getConstant(TypeID, MVT::i32);
4358 case Intrinsic::eh_return_i32:
4359 case Intrinsic::eh_return_i64:
4360 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4361 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4364 getValue(I.getArgOperand(0)),
4365 getValue(I.getArgOperand(1))));
4367 case Intrinsic::eh_unwind_init:
4368 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4370 case Intrinsic::eh_dwarf_cfa: {
4371 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4372 TLI.getPointerTy());
4373 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4375 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4376 TLI.getPointerTy()),
4378 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4380 DAG.getConstant(0, TLI.getPointerTy()));
4381 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4385 case Intrinsic::eh_sjlj_callsite: {
4386 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4387 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4388 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4389 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4391 MMI.setCurrentCallSite(CI->getZExtValue());
4394 case Intrinsic::eh_sjlj_setjmp: {
4395 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4396 getValue(I.getArgOperand(0))));
4399 case Intrinsic::eh_sjlj_longjmp: {
4400 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4401 getRoot(), getValue(I.getArgOperand(0))));
4404 case Intrinsic::eh_sjlj_dispatch_setup: {
4405 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4406 getRoot(), getValue(I.getArgOperand(0))));
4410 case Intrinsic::x86_mmx_pslli_w:
4411 case Intrinsic::x86_mmx_pslli_d:
4412 case Intrinsic::x86_mmx_pslli_q:
4413 case Intrinsic::x86_mmx_psrli_w:
4414 case Intrinsic::x86_mmx_psrli_d:
4415 case Intrinsic::x86_mmx_psrli_q:
4416 case Intrinsic::x86_mmx_psrai_w:
4417 case Intrinsic::x86_mmx_psrai_d: {
4418 SDValue ShAmt = getValue(I.getArgOperand(1));
4419 if (isa<ConstantSDNode>(ShAmt)) {
4420 visitTargetIntrinsic(I, Intrinsic);
4423 unsigned NewIntrinsic = 0;
4424 EVT ShAmtVT = MVT::v2i32;
4425 switch (Intrinsic) {
4426 case Intrinsic::x86_mmx_pslli_w:
4427 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4429 case Intrinsic::x86_mmx_pslli_d:
4430 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4432 case Intrinsic::x86_mmx_pslli_q:
4433 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4435 case Intrinsic::x86_mmx_psrli_w:
4436 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4438 case Intrinsic::x86_mmx_psrli_d:
4439 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4441 case Intrinsic::x86_mmx_psrli_q:
4442 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4444 case Intrinsic::x86_mmx_psrai_w:
4445 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4447 case Intrinsic::x86_mmx_psrai_d:
4448 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4450 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4453 // The vector shift intrinsics with scalars uses 32b shift amounts but
4454 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4456 // We must do this early because v2i32 is not a legal type.
4457 DebugLoc dl = getCurDebugLoc();
4460 ShOps[1] = DAG.getConstant(0, MVT::i32);
4461 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4462 EVT DestVT = TLI.getValueType(I.getType());
4463 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4464 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4465 DAG.getConstant(NewIntrinsic, MVT::i32),
4466 getValue(I.getArgOperand(0)), ShAmt);
4470 case Intrinsic::convertff:
4471 case Intrinsic::convertfsi:
4472 case Intrinsic::convertfui:
4473 case Intrinsic::convertsif:
4474 case Intrinsic::convertuif:
4475 case Intrinsic::convertss:
4476 case Intrinsic::convertsu:
4477 case Intrinsic::convertus:
4478 case Intrinsic::convertuu: {
4479 ISD::CvtCode Code = ISD::CVT_INVALID;
4480 switch (Intrinsic) {
4481 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4482 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4483 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4484 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4485 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4486 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4487 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4488 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4489 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4491 EVT DestVT = TLI.getValueType(I.getType());
4492 const Value *Op1 = I.getArgOperand(0);
4493 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4494 DAG.getValueType(DestVT),
4495 DAG.getValueType(getValue(Op1).getValueType()),
4496 getValue(I.getArgOperand(1)),
4497 getValue(I.getArgOperand(2)),
4502 case Intrinsic::sqrt:
4503 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4504 getValue(I.getArgOperand(0)).getValueType(),
4505 getValue(I.getArgOperand(0))));
4507 case Intrinsic::powi:
4508 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4509 getValue(I.getArgOperand(1)), DAG));
4511 case Intrinsic::sin:
4512 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4513 getValue(I.getArgOperand(0)).getValueType(),
4514 getValue(I.getArgOperand(0))));
4516 case Intrinsic::cos:
4517 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4518 getValue(I.getArgOperand(0)).getValueType(),
4519 getValue(I.getArgOperand(0))));
4521 case Intrinsic::log:
4524 case Intrinsic::log2:
4527 case Intrinsic::log10:
4530 case Intrinsic::exp:
4533 case Intrinsic::exp2:
4536 case Intrinsic::pow:
4539 case Intrinsic::convert_to_fp16:
4540 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4541 MVT::i16, getValue(I.getArgOperand(0))));
4543 case Intrinsic::convert_from_fp16:
4544 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4545 MVT::f32, getValue(I.getArgOperand(0))));
4547 case Intrinsic::pcmarker: {
4548 SDValue Tmp = getValue(I.getArgOperand(0));
4549 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4552 case Intrinsic::readcyclecounter: {
4553 SDValue Op = getRoot();
4554 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4555 DAG.getVTList(MVT::i64, MVT::Other),
4558 DAG.setRoot(Res.getValue(1));
4561 case Intrinsic::bswap:
4562 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4563 getValue(I.getArgOperand(0)).getValueType(),
4564 getValue(I.getArgOperand(0))));
4566 case Intrinsic::cttz: {
4567 SDValue Arg = getValue(I.getArgOperand(0));
4568 EVT Ty = Arg.getValueType();
4569 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4572 case Intrinsic::ctlz: {
4573 SDValue Arg = getValue(I.getArgOperand(0));
4574 EVT Ty = Arg.getValueType();
4575 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4578 case Intrinsic::ctpop: {
4579 SDValue Arg = getValue(I.getArgOperand(0));
4580 EVT Ty = Arg.getValueType();
4581 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4584 case Intrinsic::stacksave: {
4585 SDValue Op = getRoot();
4586 Res = DAG.getNode(ISD::STACKSAVE, dl,
4587 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4589 DAG.setRoot(Res.getValue(1));
4592 case Intrinsic::stackrestore: {
4593 Res = getValue(I.getArgOperand(0));
4594 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4597 case Intrinsic::stackprotector: {
4598 // Emit code into the DAG to store the stack guard onto the stack.
4599 MachineFunction &MF = DAG.getMachineFunction();
4600 MachineFrameInfo *MFI = MF.getFrameInfo();
4601 EVT PtrTy = TLI.getPointerTy();
4603 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4604 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4606 int FI = FuncInfo.StaticAllocaMap[Slot];
4607 MFI->setStackProtectorIndex(FI);
4609 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4611 // Store the stack protector onto the stack.
4612 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4613 MachinePointerInfo::getFixedStack(FI),
4619 case Intrinsic::objectsize: {
4620 // If we don't know by now, we're never going to know.
4621 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4623 assert(CI && "Non-constant type in __builtin_object_size?");
4625 SDValue Arg = getValue(I.getCalledValue());
4626 EVT Ty = Arg.getValueType();
4629 Res = DAG.getConstant(-1ULL, Ty);
4631 Res = DAG.getConstant(0, Ty);
4636 case Intrinsic::var_annotation:
4637 // Discard annotate attributes
4640 case Intrinsic::init_trampoline: {
4641 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4645 Ops[1] = getValue(I.getArgOperand(0));
4646 Ops[2] = getValue(I.getArgOperand(1));
4647 Ops[3] = getValue(I.getArgOperand(2));
4648 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4649 Ops[5] = DAG.getSrcValue(F);
4651 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4652 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4656 DAG.setRoot(Res.getValue(1));
4659 case Intrinsic::gcroot:
4661 const Value *Alloca = I.getArgOperand(0);
4662 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4664 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4665 GFI->addStackRoot(FI->getIndex(), TypeMap);
4668 case Intrinsic::gcread:
4669 case Intrinsic::gcwrite:
4670 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4672 case Intrinsic::flt_rounds:
4673 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4675 case Intrinsic::trap:
4676 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4678 case Intrinsic::uadd_with_overflow:
4679 return implVisitAluOverflow(I, ISD::UADDO);
4680 case Intrinsic::sadd_with_overflow:
4681 return implVisitAluOverflow(I, ISD::SADDO);
4682 case Intrinsic::usub_with_overflow:
4683 return implVisitAluOverflow(I, ISD::USUBO);
4684 case Intrinsic::ssub_with_overflow:
4685 return implVisitAluOverflow(I, ISD::SSUBO);
4686 case Intrinsic::umul_with_overflow:
4687 return implVisitAluOverflow(I, ISD::UMULO);
4688 case Intrinsic::smul_with_overflow:
4689 return implVisitAluOverflow(I, ISD::SMULO);
4691 case Intrinsic::prefetch: {
4693 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4695 Ops[1] = getValue(I.getArgOperand(0));
4696 Ops[2] = getValue(I.getArgOperand(1));
4697 Ops[3] = getValue(I.getArgOperand(2));
4698 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4699 DAG.getVTList(MVT::Other),
4701 EVT::getIntegerVT(*Context, 8),
4702 MachinePointerInfo(I.getArgOperand(0)),
4704 false, /* volatile */
4706 rw==1)); /* write */
4709 case Intrinsic::memory_barrier: {
4712 for (int x = 1; x < 6; ++x)
4713 Ops[x] = getValue(I.getArgOperand(x - 1));
4715 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4718 case Intrinsic::atomic_cmp_swap: {
4719 SDValue Root = getRoot();
4721 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4722 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4724 getValue(I.getArgOperand(0)),
4725 getValue(I.getArgOperand(1)),
4726 getValue(I.getArgOperand(2)),
4727 MachinePointerInfo(I.getArgOperand(0)));
4729 DAG.setRoot(L.getValue(1));
4732 case Intrinsic::atomic_load_add:
4733 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4734 case Intrinsic::atomic_load_sub:
4735 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4736 case Intrinsic::atomic_load_or:
4737 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4738 case Intrinsic::atomic_load_xor:
4739 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4740 case Intrinsic::atomic_load_and:
4741 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4742 case Intrinsic::atomic_load_nand:
4743 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4744 case Intrinsic::atomic_load_max:
4745 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4746 case Intrinsic::atomic_load_min:
4747 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4748 case Intrinsic::atomic_load_umin:
4749 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4750 case Intrinsic::atomic_load_umax:
4751 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4752 case Intrinsic::atomic_swap:
4753 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4755 case Intrinsic::invariant_start:
4756 case Intrinsic::lifetime_start:
4757 // Discard region information.
4758 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4760 case Intrinsic::invariant_end:
4761 case Intrinsic::lifetime_end:
4762 // Discard region information.
4767 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4769 MachineBasicBlock *LandingPad) {
4770 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4771 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4772 const Type *RetTy = FTy->getReturnType();
4773 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4774 MCSymbol *BeginLabel = 0;
4776 TargetLowering::ArgListTy Args;
4777 TargetLowering::ArgListEntry Entry;
4778 Args.reserve(CS.arg_size());
4780 // Check whether the function can return without sret-demotion.
4781 SmallVector<ISD::OutputArg, 4> Outs;
4782 SmallVector<uint64_t, 4> Offsets;
4783 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4784 Outs, TLI, &Offsets);
4786 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4787 FTy->isVarArg(), Outs, FTy->getContext());
4789 SDValue DemoteStackSlot;
4790 int DemoteStackIdx = -100;
4792 if (!CanLowerReturn) {
4793 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4794 FTy->getReturnType());
4795 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4796 FTy->getReturnType());
4797 MachineFunction &MF = DAG.getMachineFunction();
4798 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4799 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4801 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4802 Entry.Node = DemoteStackSlot;
4803 Entry.Ty = StackSlotPtrType;
4804 Entry.isSExt = false;
4805 Entry.isZExt = false;
4806 Entry.isInReg = false;
4807 Entry.isSRet = true;
4808 Entry.isNest = false;
4809 Entry.isByVal = false;
4810 Entry.Alignment = Align;
4811 Args.push_back(Entry);
4812 RetTy = Type::getVoidTy(FTy->getContext());
4815 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4817 SDValue ArgNode = getValue(*i);
4818 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4820 unsigned attrInd = i - CS.arg_begin() + 1;
4821 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4822 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4823 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4824 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4825 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4826 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4827 Entry.Alignment = CS.getParamAlignment(attrInd);
4828 Args.push_back(Entry);
4832 // Insert a label before the invoke call to mark the try range. This can be
4833 // used to detect deletion of the invoke via the MachineModuleInfo.
4834 BeginLabel = MMI.getContext().CreateTempSymbol();
4836 // For SjLj, keep track of which landing pads go with which invokes
4837 // so as to maintain the ordering of pads in the LSDA.
4838 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4839 if (CallSiteIndex) {
4840 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4841 // Now that the call site is handled, stop tracking it.
4842 MMI.setCurrentCallSite(0);
4845 // Both PendingLoads and PendingExports must be flushed here;
4846 // this call might not return.
4848 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4851 // Check if target-independent constraints permit a tail call here.
4852 // Target-dependent constraints are checked within TLI.LowerCallTo.
4854 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4857 // If there's a possibility that fast-isel has already selected some amount
4858 // of the current basic block, don't emit a tail call.
4859 if (isTailCall && EnableFastISel)
4862 std::pair<SDValue,SDValue> Result =
4863 TLI.LowerCallTo(getRoot(), RetTy,
4864 CS.paramHasAttr(0, Attribute::SExt),
4865 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4866 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4867 CS.getCallingConv(),
4869 !CS.getInstruction()->use_empty(),
4870 Callee, Args, DAG, getCurDebugLoc());
4871 assert((isTailCall || Result.second.getNode()) &&
4872 "Non-null chain expected with non-tail call!");
4873 assert((Result.second.getNode() || !Result.first.getNode()) &&
4874 "Null value expected with tail call!");
4875 if (Result.first.getNode()) {
4876 setValue(CS.getInstruction(), Result.first);
4877 } else if (!CanLowerReturn && Result.second.getNode()) {
4878 // The instruction result is the result of loading from the
4879 // hidden sret parameter.
4880 SmallVector<EVT, 1> PVTs;
4881 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4883 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4884 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4885 EVT PtrVT = PVTs[0];
4886 unsigned NumValues = Outs.size();
4887 SmallVector<SDValue, 4> Values(NumValues);
4888 SmallVector<SDValue, 4> Chains(NumValues);
4890 for (unsigned i = 0; i < NumValues; ++i) {
4891 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4893 DAG.getConstant(Offsets[i], PtrVT));
4894 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4896 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4899 Chains[i] = L.getValue(1);
4902 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4903 MVT::Other, &Chains[0], NumValues);
4904 PendingLoads.push_back(Chain);
4906 // Collect the legal value parts into potentially illegal values
4907 // that correspond to the original function's return values.
4908 SmallVector<EVT, 4> RetTys;
4909 RetTy = FTy->getReturnType();
4910 ComputeValueVTs(TLI, RetTy, RetTys);
4911 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4912 SmallVector<SDValue, 4> ReturnValues;
4913 unsigned CurReg = 0;
4914 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4916 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4917 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4919 SDValue ReturnValue =
4920 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4921 RegisterVT, VT, AssertOp);
4922 ReturnValues.push_back(ReturnValue);
4926 setValue(CS.getInstruction(),
4927 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4928 DAG.getVTList(&RetTys[0], RetTys.size()),
4929 &ReturnValues[0], ReturnValues.size()));
4932 // As a special case, a null chain means that a tail call has been emitted and
4933 // the DAG root is already updated.
4934 if (!Result.second.getNode()) {
4937 AssignOrderingToNode(DAG.getRoot().getNode());
4939 DAG.setRoot(Result.second);
4941 AssignOrderingToNode(Result.second.getNode());
4945 // Insert a label at the end of the invoke call to mark the try range. This
4946 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4947 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4948 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4950 // Inform MachineModuleInfo of range.
4951 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4955 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4956 /// value is equal or not-equal to zero.
4957 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4958 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4960 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4961 if (IC->isEquality())
4962 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4963 if (C->isNullValue())
4965 // Unknown instruction.
4971 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4973 SelectionDAGBuilder &Builder) {
4975 // Check to see if this load can be trivially constant folded, e.g. if the
4976 // input is from a string literal.
4977 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4978 // Cast pointer to the type we really want to load.
4979 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4980 PointerType::getUnqual(LoadTy));
4982 if (const Constant *LoadCst =
4983 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4985 return Builder.getValue(LoadCst);
4988 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4989 // still constant memory, the input chain can be the entry node.
4991 bool ConstantMemory = false;
4993 // Do not serialize (non-volatile) loads of constant memory with anything.
4994 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4995 Root = Builder.DAG.getEntryNode();
4996 ConstantMemory = true;
4998 // Do not serialize non-volatile loads against each other.
4999 Root = Builder.DAG.getRoot();
5002 SDValue Ptr = Builder.getValue(PtrVal);
5003 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5004 Ptr, MachinePointerInfo(PtrVal),
5006 false /*nontemporal*/, 1 /* align=1 */);
5008 if (!ConstantMemory)
5009 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5014 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5015 /// If so, return true and lower it, otherwise return false and it will be
5016 /// lowered like a normal call.
5017 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5018 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5019 if (I.getNumArgOperands() != 3)
5022 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5023 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5024 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5025 !I.getType()->isIntegerTy())
5028 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5030 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5031 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5032 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5033 bool ActuallyDoIt = true;
5036 switch (Size->getZExtValue()) {
5038 LoadVT = MVT::Other;
5040 ActuallyDoIt = false;
5044 LoadTy = Type::getInt16Ty(Size->getContext());
5048 LoadTy = Type::getInt32Ty(Size->getContext());
5052 LoadTy = Type::getInt64Ty(Size->getContext());
5056 LoadVT = MVT::v4i32;
5057 LoadTy = Type::getInt32Ty(Size->getContext());
5058 LoadTy = VectorType::get(LoadTy, 4);
5063 // This turns into unaligned loads. We only do this if the target natively
5064 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5065 // we'll only produce a small number of byte loads.
5067 // Require that we can find a legal MVT, and only do this if the target
5068 // supports unaligned loads of that type. Expanding into byte loads would
5070 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5071 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5072 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5073 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5074 ActuallyDoIt = false;
5078 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5079 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5081 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5083 EVT CallVT = TLI.getValueType(I.getType(), true);
5084 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5094 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5095 // Handle inline assembly differently.
5096 if (isa<InlineAsm>(I.getCalledValue())) {
5101 // See if any floating point values are being passed to this function. This is
5102 // used to emit an undefined reference to fltused on Windows.
5103 const FunctionType *FT =
5104 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5105 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5106 if (FT->isVarArg() &&
5107 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5108 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5109 const Type* T = I.getArgOperand(i)->getType();
5110 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5112 if (!i->isFloatingPointTy()) continue;
5113 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5119 const char *RenameFn = 0;
5120 if (Function *F = I.getCalledFunction()) {
5121 if (F->isDeclaration()) {
5122 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5123 if (unsigned IID = II->getIntrinsicID(F)) {
5124 RenameFn = visitIntrinsicCall(I, IID);
5129 if (unsigned IID = F->getIntrinsicID()) {
5130 RenameFn = visitIntrinsicCall(I, IID);
5136 // Check for well-known libc/libm calls. If the function is internal, it
5137 // can't be a library call.
5138 if (!F->hasLocalLinkage() && F->hasName()) {
5139 StringRef Name = F->getName();
5140 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5141 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5142 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5143 I.getType() == I.getArgOperand(0)->getType() &&
5144 I.getType() == I.getArgOperand(1)->getType()) {
5145 SDValue LHS = getValue(I.getArgOperand(0));
5146 SDValue RHS = getValue(I.getArgOperand(1));
5147 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5148 LHS.getValueType(), LHS, RHS));
5151 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5152 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5153 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5154 I.getType() == I.getArgOperand(0)->getType()) {
5155 SDValue Tmp = getValue(I.getArgOperand(0));
5156 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5157 Tmp.getValueType(), Tmp));
5160 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5161 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5162 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5163 I.getType() == I.getArgOperand(0)->getType() &&
5164 I.onlyReadsMemory()) {
5165 SDValue Tmp = getValue(I.getArgOperand(0));
5166 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5167 Tmp.getValueType(), Tmp));
5170 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5171 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5172 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5173 I.getType() == I.getArgOperand(0)->getType() &&
5174 I.onlyReadsMemory()) {
5175 SDValue Tmp = getValue(I.getArgOperand(0));
5176 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5177 Tmp.getValueType(), Tmp));
5180 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5181 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5182 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5183 I.getType() == I.getArgOperand(0)->getType() &&
5184 I.onlyReadsMemory()) {
5185 SDValue Tmp = getValue(I.getArgOperand(0));
5186 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5187 Tmp.getValueType(), Tmp));
5190 } else if (Name == "memcmp") {
5191 if (visitMemCmpCall(I))
5199 Callee = getValue(I.getCalledValue());
5201 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5203 // Check if we can potentially perform a tail call. More detailed checking is
5204 // be done within LowerCallTo, after more information about the call is known.
5205 LowerCallTo(&I, Callee, I.isTailCall());
5210 /// AsmOperandInfo - This contains information for each constraint that we are
5212 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5214 /// CallOperand - If this is the result output operand or a clobber
5215 /// this is null, otherwise it is the incoming operand to the CallInst.
5216 /// This gets modified as the asm is processed.
5217 SDValue CallOperand;
5219 /// AssignedRegs - If this is a register or register class operand, this
5220 /// contains the set of register corresponding to the operand.
5221 RegsForValue AssignedRegs;
5223 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5224 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5227 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5228 /// busy in OutputRegs/InputRegs.
5229 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5230 std::set<unsigned> &OutputRegs,
5231 std::set<unsigned> &InputRegs,
5232 const TargetRegisterInfo &TRI) const {
5234 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5235 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5238 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5239 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5243 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5244 /// corresponds to. If there is no Value* for this operand, it returns
5246 EVT getCallOperandValEVT(LLVMContext &Context,
5247 const TargetLowering &TLI,
5248 const TargetData *TD) const {
5249 if (CallOperandVal == 0) return MVT::Other;
5251 if (isa<BasicBlock>(CallOperandVal))
5252 return TLI.getPointerTy();
5254 const llvm::Type *OpTy = CallOperandVal->getType();
5256 // If this is an indirect operand, the operand is a pointer to the
5259 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5261 report_fatal_error("Indirect operand for inline asm not a pointer!");
5262 OpTy = PtrTy->getElementType();
5265 // If OpTy is not a single value, it may be a struct/union that we
5266 // can tile with integers.
5267 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5268 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5277 OpTy = IntegerType::get(Context, BitSize);
5282 return TLI.getValueType(OpTy, true);
5286 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5288 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5289 const TargetRegisterInfo &TRI) {
5290 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5292 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5293 for (; *Aliases; ++Aliases)
5294 Regs.insert(*Aliases);
5298 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5300 } // end anonymous namespace
5302 /// isAllocatableRegister - If the specified register is safe to allocate,
5303 /// i.e. it isn't a stack pointer or some other special register, return the
5304 /// register class for the register. Otherwise, return null.
5305 static const TargetRegisterClass *
5306 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5307 const TargetLowering &TLI,
5308 const TargetRegisterInfo *TRI) {
5309 EVT FoundVT = MVT::Other;
5310 const TargetRegisterClass *FoundRC = 0;
5311 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5312 E = TRI->regclass_end(); RCI != E; ++RCI) {
5313 EVT ThisVT = MVT::Other;
5315 const TargetRegisterClass *RC = *RCI;
5316 // If none of the value types for this register class are valid, we
5317 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5318 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5320 if (TLI.isTypeLegal(*I)) {
5321 // If we have already found this register in a different register class,
5322 // choose the one with the largest VT specified. For example, on
5323 // PowerPC, we favor f64 register classes over f32.
5324 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5331 if (ThisVT == MVT::Other) continue;
5333 // NOTE: This isn't ideal. In particular, this might allocate the
5334 // frame pointer in functions that need it (due to them not being taken
5335 // out of allocation, because a variable sized allocation hasn't been seen
5336 // yet). This is a slight code pessimization, but should still work.
5337 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5338 E = RC->allocation_order_end(MF); I != E; ++I)
5340 // We found a matching register class. Keep looking at others in case
5341 // we find one with larger registers that this physreg is also in.
5350 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5351 /// specified operand. We prefer to assign virtual registers, to allow the
5352 /// register allocator to handle the assignment process. However, if the asm
5353 /// uses features that we can't model on machineinstrs, we have SDISel do the
5354 /// allocation. This produces generally horrible, but correct, code.
5356 /// OpInfo describes the operand.
5357 /// Input and OutputRegs are the set of already allocated physical registers.
5359 static void GetRegistersForValue(SelectionDAG &DAG,
5360 const TargetLowering &TLI,
5362 SDISelAsmOperandInfo &OpInfo,
5363 std::set<unsigned> &OutputRegs,
5364 std::set<unsigned> &InputRegs) {
5365 LLVMContext &Context = *DAG.getContext();
5367 // Compute whether this value requires an input register, an output register,
5369 bool isOutReg = false;
5370 bool isInReg = false;
5371 switch (OpInfo.Type) {
5372 case InlineAsm::isOutput:
5375 // If there is an input constraint that matches this, we need to reserve
5376 // the input register so no other inputs allocate to it.
5377 isInReg = OpInfo.hasMatchingInput();
5379 case InlineAsm::isInput:
5383 case InlineAsm::isClobber:
5390 MachineFunction &MF = DAG.getMachineFunction();
5391 SmallVector<unsigned, 4> Regs;
5393 // If this is a constraint for a single physreg, or a constraint for a
5394 // register class, find it.
5395 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5396 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5397 OpInfo.ConstraintVT);
5399 unsigned NumRegs = 1;
5400 if (OpInfo.ConstraintVT != MVT::Other) {
5401 // If this is a FP input in an integer register (or visa versa) insert a bit
5402 // cast of the input value. More generally, handle any case where the input
5403 // value disagrees with the register class we plan to stick this in.
5404 if (OpInfo.Type == InlineAsm::isInput &&
5405 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5406 // Try to convert to the first EVT that the reg class contains. If the
5407 // types are identical size, use a bitcast to convert (e.g. two differing
5409 EVT RegVT = *PhysReg.second->vt_begin();
5410 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5411 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5412 RegVT, OpInfo.CallOperand);
5413 OpInfo.ConstraintVT = RegVT;
5414 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5415 // If the input is a FP value and we want it in FP registers, do a
5416 // bitcast to the corresponding integer type. This turns an f64 value
5417 // into i64, which can be passed with two i32 values on a 32-bit
5419 RegVT = EVT::getIntegerVT(Context,
5420 OpInfo.ConstraintVT.getSizeInBits());
5421 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5422 RegVT, OpInfo.CallOperand);
5423 OpInfo.ConstraintVT = RegVT;
5427 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5431 EVT ValueVT = OpInfo.ConstraintVT;
5433 // If this is a constraint for a specific physical register, like {r17},
5435 if (unsigned AssignedReg = PhysReg.first) {
5436 const TargetRegisterClass *RC = PhysReg.second;
5437 if (OpInfo.ConstraintVT == MVT::Other)
5438 ValueVT = *RC->vt_begin();
5440 // Get the actual register value type. This is important, because the user
5441 // may have asked for (e.g.) the AX register in i32 type. We need to
5442 // remember that AX is actually i16 to get the right extension.
5443 RegVT = *RC->vt_begin();
5445 // This is a explicit reference to a physical register.
5446 Regs.push_back(AssignedReg);
5448 // If this is an expanded reference, add the rest of the regs to Regs.
5450 TargetRegisterClass::iterator I = RC->begin();
5451 for (; *I != AssignedReg; ++I)
5452 assert(I != RC->end() && "Didn't find reg!");
5454 // Already added the first reg.
5456 for (; NumRegs; --NumRegs, ++I) {
5457 assert(I != RC->end() && "Ran out of registers to allocate!");
5462 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5463 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5464 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5468 // Otherwise, if this was a reference to an LLVM register class, create vregs
5469 // for this reference.
5470 if (const TargetRegisterClass *RC = PhysReg.second) {
5471 RegVT = *RC->vt_begin();
5472 if (OpInfo.ConstraintVT == MVT::Other)
5475 // Create the appropriate number of virtual registers.
5476 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5477 for (; NumRegs; --NumRegs)
5478 Regs.push_back(RegInfo.createVirtualRegister(RC));
5480 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5484 // This is a reference to a register class that doesn't directly correspond
5485 // to an LLVM register class. Allocate NumRegs consecutive, available,
5486 // registers from the class.
5487 std::vector<unsigned> RegClassRegs
5488 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5489 OpInfo.ConstraintVT);
5491 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5492 unsigned NumAllocated = 0;
5493 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5494 unsigned Reg = RegClassRegs[i];
5495 // See if this register is available.
5496 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5497 (isInReg && InputRegs.count(Reg))) { // Already used.
5498 // Make sure we find consecutive registers.
5503 // Check to see if this register is allocatable (i.e. don't give out the
5505 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5506 if (!RC) { // Couldn't allocate this register.
5507 // Reset NumAllocated to make sure we return consecutive registers.
5512 // Okay, this register is good, we can use it.
5515 // If we allocated enough consecutive registers, succeed.
5516 if (NumAllocated == NumRegs) {
5517 unsigned RegStart = (i-NumAllocated)+1;
5518 unsigned RegEnd = i+1;
5519 // Mark all of the allocated registers used.
5520 for (unsigned i = RegStart; i != RegEnd; ++i)
5521 Regs.push_back(RegClassRegs[i]);
5523 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5524 OpInfo.ConstraintVT);
5525 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5530 // Otherwise, we couldn't allocate enough registers for this.
5533 /// visitInlineAsm - Handle a call to an InlineAsm object.
5535 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5536 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5538 /// ConstraintOperands - Information about all of the constraints.
5539 SDISelAsmOperandInfoVector ConstraintOperands;
5541 std::set<unsigned> OutputRegs, InputRegs;
5543 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5544 bool hasMemory = false;
5546 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5547 unsigned ResNo = 0; // ResNo - The result number of the next output.
5548 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5549 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5550 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5552 EVT OpVT = MVT::Other;
5554 // Compute the value type for each operand.
5555 switch (OpInfo.Type) {
5556 case InlineAsm::isOutput:
5557 // Indirect outputs just consume an argument.
5558 if (OpInfo.isIndirect) {
5559 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5563 // The return value of the call is this value. As such, there is no
5564 // corresponding argument.
5565 assert(!CS.getType()->isVoidTy() &&
5567 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5568 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5570 assert(ResNo == 0 && "Asm only has one result!");
5571 OpVT = TLI.getValueType(CS.getType());
5575 case InlineAsm::isInput:
5576 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5578 case InlineAsm::isClobber:
5583 // If this is an input or an indirect output, process the call argument.
5584 // BasicBlocks are labels, currently appearing only in asm's.
5585 if (OpInfo.CallOperandVal) {
5586 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5587 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5589 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5592 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5595 OpInfo.ConstraintVT = OpVT;
5597 // Indirect operand accesses access memory.
5598 if (OpInfo.isIndirect)
5601 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5602 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5603 if (CType == TargetLowering::C_Memory) {
5611 SDValue Chain, Flag;
5613 // We won't need to flush pending loads if this asm doesn't touch
5614 // memory and is nonvolatile.
5615 if (hasMemory || IA->hasSideEffects())
5618 Chain = DAG.getRoot();
5620 // Second pass over the constraints: compute which constraint option to use
5621 // and assign registers to constraints that want a specific physreg.
5622 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5623 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5625 // If this is an output operand with a matching input operand, look up the
5626 // matching input. If their types mismatch, e.g. one is an integer, the
5627 // other is floating point, or their sizes are different, flag it as an
5629 if (OpInfo.hasMatchingInput()) {
5630 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5632 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5633 if ((OpInfo.ConstraintVT.isInteger() !=
5634 Input.ConstraintVT.isInteger()) ||
5635 (OpInfo.ConstraintVT.getSizeInBits() !=
5636 Input.ConstraintVT.getSizeInBits())) {
5637 report_fatal_error("Unsupported asm: input constraint"
5638 " with a matching output constraint of"
5639 " incompatible type!");
5641 Input.ConstraintVT = OpInfo.ConstraintVT;
5645 // Compute the constraint code and ConstraintType to use.
5646 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5648 // If this is a memory input, and if the operand is not indirect, do what we
5649 // need to to provide an address for the memory input.
5650 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5651 !OpInfo.isIndirect) {
5652 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5653 "Can only indirectify direct input operands!");
5655 // Memory operands really want the address of the value. If we don't have
5656 // an indirect input, put it in the constpool if we can, otherwise spill
5657 // it to a stack slot.
5659 // If the operand is a float, integer, or vector constant, spill to a
5660 // constant pool entry to get its address.
5661 const Value *OpVal = OpInfo.CallOperandVal;
5662 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5663 isa<ConstantVector>(OpVal)) {
5664 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5665 TLI.getPointerTy());
5667 // Otherwise, create a stack slot and emit a store to it before the
5669 const Type *Ty = OpVal->getType();
5670 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5671 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5672 MachineFunction &MF = DAG.getMachineFunction();
5673 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5674 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5675 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5676 OpInfo.CallOperand, StackSlot,
5677 MachinePointerInfo::getFixedStack(SSFI),
5679 OpInfo.CallOperand = StackSlot;
5682 // There is no longer a Value* corresponding to this operand.
5683 OpInfo.CallOperandVal = 0;
5685 // It is now an indirect operand.
5686 OpInfo.isIndirect = true;
5689 // If this constraint is for a specific register, allocate it before
5691 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5692 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5696 // Second pass - Loop over all of the operands, assigning virtual or physregs
5697 // to register class operands.
5698 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5699 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5701 // C_Register operands have already been allocated, Other/Memory don't need
5703 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5704 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5708 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5709 std::vector<SDValue> AsmNodeOperands;
5710 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5711 AsmNodeOperands.push_back(
5712 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5713 TLI.getPointerTy()));
5715 // If we have a !srcloc metadata node associated with it, we want to attach
5716 // this to the ultimately generated inline asm machineinstr. To do this, we
5717 // pass in the third operand as this (potentially null) inline asm MDNode.
5718 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5719 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5721 // Remember the HasSideEffect and AlignStack bits as operand 3.
5722 unsigned ExtraInfo = 0;
5723 if (IA->hasSideEffects())
5724 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5725 if (IA->isAlignStack())
5726 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5727 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5728 TLI.getPointerTy()));
5730 // Loop over all of the inputs, copying the operand values into the
5731 // appropriate registers and processing the output regs.
5732 RegsForValue RetValRegs;
5734 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5735 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5737 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5738 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5740 switch (OpInfo.Type) {
5741 case InlineAsm::isOutput: {
5742 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5743 OpInfo.ConstraintType != TargetLowering::C_Register) {
5744 // Memory output, or 'other' output (e.g. 'X' constraint).
5745 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5747 // Add information to the INLINEASM node to know about this output.
5748 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5749 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5750 TLI.getPointerTy()));
5751 AsmNodeOperands.push_back(OpInfo.CallOperand);
5755 // Otherwise, this is a register or register class output.
5757 // Copy the output from the appropriate register. Find a register that
5759 if (OpInfo.AssignedRegs.Regs.empty())
5760 report_fatal_error("Couldn't allocate output reg for constraint '" +
5761 Twine(OpInfo.ConstraintCode) + "'!");
5763 // If this is an indirect operand, store through the pointer after the
5765 if (OpInfo.isIndirect) {
5766 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5767 OpInfo.CallOperandVal));
5769 // This is the result value of the call.
5770 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5771 // Concatenate this output onto the outputs list.
5772 RetValRegs.append(OpInfo.AssignedRegs);
5775 // Add information to the INLINEASM node to know that this register is
5777 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5778 InlineAsm::Kind_RegDefEarlyClobber :
5779 InlineAsm::Kind_RegDef,
5786 case InlineAsm::isInput: {
5787 SDValue InOperandVal = OpInfo.CallOperand;
5789 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5790 // If this is required to match an output register we have already set,
5791 // just use its register.
5792 unsigned OperandNo = OpInfo.getMatchedOperand();
5794 // Scan until we find the definition we already emitted of this operand.
5795 // When we find it, create a RegsForValue operand.
5796 unsigned CurOp = InlineAsm::Op_FirstOperand;
5797 for (; OperandNo; --OperandNo) {
5798 // Advance to the next operand.
5800 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5801 assert((InlineAsm::isRegDefKind(OpFlag) ||
5802 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5803 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5804 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5808 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5809 if (InlineAsm::isRegDefKind(OpFlag) ||
5810 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5811 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5812 if (OpInfo.isIndirect) {
5813 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5814 LLVMContext &Ctx = *DAG.getContext();
5815 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5816 " don't know how to handle tied "
5817 "indirect register inputs");
5820 RegsForValue MatchedRegs;
5821 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5822 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5823 MatchedRegs.RegVTs.push_back(RegVT);
5824 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5825 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5827 MatchedRegs.Regs.push_back
5828 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5830 // Use the produced MatchedRegs object to
5831 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5833 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5834 true, OpInfo.getMatchedOperand(),
5835 DAG, AsmNodeOperands);
5839 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5840 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5841 "Unexpected number of operands");
5842 // Add information to the INLINEASM node to know about this input.
5843 // See InlineAsm.h isUseOperandTiedToDef.
5844 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5845 OpInfo.getMatchedOperand());
5846 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5847 TLI.getPointerTy()));
5848 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5852 // Treat indirect 'X' constraint as memory.
5853 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5855 OpInfo.ConstraintType = TargetLowering::C_Memory;
5857 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5858 std::vector<SDValue> Ops;
5859 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5862 report_fatal_error("Invalid operand for inline asm constraint '" +
5863 Twine(OpInfo.ConstraintCode) + "'!");
5865 // Add information to the INLINEASM node to know about this input.
5866 unsigned ResOpType =
5867 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5868 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5869 TLI.getPointerTy()));
5870 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5874 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5875 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5876 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5877 "Memory operands expect pointer values");
5879 // Add information to the INLINEASM node to know about this input.
5880 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5881 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5882 TLI.getPointerTy()));
5883 AsmNodeOperands.push_back(InOperandVal);
5887 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5888 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5889 "Unknown constraint type!");
5890 assert(!OpInfo.isIndirect &&
5891 "Don't know how to handle indirect register inputs yet!");
5893 // Copy the input into the appropriate registers.
5894 if (OpInfo.AssignedRegs.Regs.empty() ||
5895 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5896 report_fatal_error("Couldn't allocate input reg for constraint '" +
5897 Twine(OpInfo.ConstraintCode) + "'!");
5899 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5902 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5903 DAG, AsmNodeOperands);
5906 case InlineAsm::isClobber: {
5907 // Add the clobbered value to the operand list, so that the register
5908 // allocator is aware that the physreg got clobbered.
5909 if (!OpInfo.AssignedRegs.Regs.empty())
5910 OpInfo.AssignedRegs.AddInlineAsmOperands(
5911 InlineAsm::Kind_RegDefEarlyClobber,
5919 // Finish up input operands. Set the input chain and add the flag last.
5920 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5921 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5923 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5924 DAG.getVTList(MVT::Other, MVT::Glue),
5925 &AsmNodeOperands[0], AsmNodeOperands.size());
5926 Flag = Chain.getValue(1);
5928 // If this asm returns a register value, copy the result from that register
5929 // and set it as the value of the call.
5930 if (!RetValRegs.Regs.empty()) {
5931 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5934 // FIXME: Why don't we do this for inline asms with MRVs?
5935 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5936 EVT ResultType = TLI.getValueType(CS.getType());
5938 // If any of the results of the inline asm is a vector, it may have the
5939 // wrong width/num elts. This can happen for register classes that can
5940 // contain multiple different value types. The preg or vreg allocated may
5941 // not have the same VT as was expected. Convert it to the right type
5942 // with bit_convert.
5943 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5944 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5947 } else if (ResultType != Val.getValueType() &&
5948 ResultType.isInteger() && Val.getValueType().isInteger()) {
5949 // If a result value was tied to an input value, the computed result may
5950 // have a wider width than the expected result. Extract the relevant
5952 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5955 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5958 setValue(CS.getInstruction(), Val);
5959 // Don't need to use this as a chain in this case.
5960 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5964 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5966 // Process indirect outputs, first output all of the flagged copies out of
5968 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5969 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5970 const Value *Ptr = IndirectStoresToEmit[i].second;
5971 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5973 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5976 // Emit the non-flagged stores from the physregs.
5977 SmallVector<SDValue, 8> OutChains;
5978 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5979 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5980 StoresToEmit[i].first,
5981 getValue(StoresToEmit[i].second),
5982 MachinePointerInfo(StoresToEmit[i].second),
5984 OutChains.push_back(Val);
5987 if (!OutChains.empty())
5988 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5989 &OutChains[0], OutChains.size());
5994 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5995 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5996 MVT::Other, getRoot(),
5997 getValue(I.getArgOperand(0)),
5998 DAG.getSrcValue(I.getArgOperand(0))));
6001 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6002 const TargetData &TD = *TLI.getTargetData();
6003 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6004 getRoot(), getValue(I.getOperand(0)),
6005 DAG.getSrcValue(I.getOperand(0)),
6006 TD.getABITypeAlignment(I.getType()));
6008 DAG.setRoot(V.getValue(1));
6011 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6012 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6013 MVT::Other, getRoot(),
6014 getValue(I.getArgOperand(0)),
6015 DAG.getSrcValue(I.getArgOperand(0))));
6018 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6019 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6020 MVT::Other, getRoot(),
6021 getValue(I.getArgOperand(0)),
6022 getValue(I.getArgOperand(1)),
6023 DAG.getSrcValue(I.getArgOperand(0)),
6024 DAG.getSrcValue(I.getArgOperand(1))));
6027 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6028 /// implementation, which just calls LowerCall.
6029 /// FIXME: When all targets are
6030 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6031 std::pair<SDValue, SDValue>
6032 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6033 bool RetSExt, bool RetZExt, bool isVarArg,
6034 bool isInreg, unsigned NumFixedArgs,
6035 CallingConv::ID CallConv, bool isTailCall,
6036 bool isReturnValueUsed,
6038 ArgListTy &Args, SelectionDAG &DAG,
6039 DebugLoc dl) const {
6040 // Handle all of the outgoing arguments.
6041 SmallVector<ISD::OutputArg, 32> Outs;
6042 SmallVector<SDValue, 32> OutVals;
6043 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6044 SmallVector<EVT, 4> ValueVTs;
6045 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6046 for (unsigned Value = 0, NumValues = ValueVTs.size();
6047 Value != NumValues; ++Value) {
6048 EVT VT = ValueVTs[Value];
6049 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6050 SDValue Op = SDValue(Args[i].Node.getNode(),
6051 Args[i].Node.getResNo() + Value);
6052 ISD::ArgFlagsTy Flags;
6053 unsigned OriginalAlignment =
6054 getTargetData()->getABITypeAlignment(ArgTy);
6060 if (Args[i].isInReg)
6064 if (Args[i].isByVal) {
6066 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6067 const Type *ElementTy = Ty->getElementType();
6068 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6069 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6070 // For ByVal, alignment should come from FE. BE will guess if this
6071 // info is not there but there are cases it cannot get right.
6072 if (Args[i].Alignment)
6073 FrameAlign = Args[i].Alignment;
6074 Flags.setByValAlign(FrameAlign);
6075 Flags.setByValSize(FrameSize);
6079 Flags.setOrigAlign(OriginalAlignment);
6081 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6082 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6083 SmallVector<SDValue, 4> Parts(NumParts);
6084 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6087 ExtendKind = ISD::SIGN_EXTEND;
6088 else if (Args[i].isZExt)
6089 ExtendKind = ISD::ZERO_EXTEND;
6091 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6092 PartVT, ExtendKind);
6094 for (unsigned j = 0; j != NumParts; ++j) {
6095 // if it isn't first piece, alignment must be 1
6096 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6098 if (NumParts > 1 && j == 0)
6099 MyFlags.Flags.setSplit();
6101 MyFlags.Flags.setOrigAlign(1);
6103 Outs.push_back(MyFlags);
6104 OutVals.push_back(Parts[j]);
6109 // Handle the incoming return values from the call.
6110 SmallVector<ISD::InputArg, 32> Ins;
6111 SmallVector<EVT, 4> RetTys;
6112 ComputeValueVTs(*this, RetTy, RetTys);
6113 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6115 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6116 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6117 for (unsigned i = 0; i != NumRegs; ++i) {
6118 ISD::InputArg MyFlags;
6119 MyFlags.VT = RegisterVT.getSimpleVT();
6120 MyFlags.Used = isReturnValueUsed;
6122 MyFlags.Flags.setSExt();
6124 MyFlags.Flags.setZExt();
6126 MyFlags.Flags.setInReg();
6127 Ins.push_back(MyFlags);
6131 SmallVector<SDValue, 4> InVals;
6132 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6133 Outs, OutVals, Ins, dl, DAG, InVals);
6135 // Verify that the target's LowerCall behaved as expected.
6136 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6137 "LowerCall didn't return a valid chain!");
6138 assert((!isTailCall || InVals.empty()) &&
6139 "LowerCall emitted a return value for a tail call!");
6140 assert((isTailCall || InVals.size() == Ins.size()) &&
6141 "LowerCall didn't emit the correct number of values!");
6143 // For a tail call, the return value is merely live-out and there aren't
6144 // any nodes in the DAG representing it. Return a special value to
6145 // indicate that a tail call has been emitted and no more Instructions
6146 // should be processed in the current block.
6149 return std::make_pair(SDValue(), SDValue());
6152 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6153 assert(InVals[i].getNode() &&
6154 "LowerCall emitted a null value!");
6155 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6156 "LowerCall emitted a value with the wrong type!");
6159 // Collect the legal value parts into potentially illegal values
6160 // that correspond to the original function's return values.
6161 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6163 AssertOp = ISD::AssertSext;
6165 AssertOp = ISD::AssertZext;
6166 SmallVector<SDValue, 4> ReturnValues;
6167 unsigned CurReg = 0;
6168 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6170 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6171 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6173 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6174 NumRegs, RegisterVT, VT,
6179 // For a function returning void, there is no return value. We can't create
6180 // such a node, so we just return a null return value in that case. In
6181 // that case, nothing will actualy look at the value.
6182 if (ReturnValues.empty())
6183 return std::make_pair(SDValue(), Chain);
6185 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6186 DAG.getVTList(&RetTys[0], RetTys.size()),
6187 &ReturnValues[0], ReturnValues.size());
6188 return std::make_pair(Res, Chain);
6191 void TargetLowering::LowerOperationWrapper(SDNode *N,
6192 SmallVectorImpl<SDValue> &Results,
6193 SelectionDAG &DAG) const {
6194 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6196 Results.push_back(Res);
6199 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6200 llvm_unreachable("LowerOperation not implemented for this target!");
6205 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6206 SDValue Op = getNonRegisterValue(V);
6207 assert((Op.getOpcode() != ISD::CopyFromReg ||
6208 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6209 "Copy from a reg to the same reg!");
6210 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6212 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6213 SDValue Chain = DAG.getEntryNode();
6214 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6215 PendingExports.push_back(Chain);
6218 #include "llvm/CodeGen/SelectionDAGISel.h"
6220 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6221 // If this is the entry block, emit arguments.
6222 const Function &F = *LLVMBB->getParent();
6223 SelectionDAG &DAG = SDB->DAG;
6224 DebugLoc dl = SDB->getCurDebugLoc();
6225 const TargetData *TD = TLI.getTargetData();
6226 SmallVector<ISD::InputArg, 16> Ins;
6228 // Check whether the function can return without sret-demotion.
6229 SmallVector<ISD::OutputArg, 4> Outs;
6230 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6233 if (!FuncInfo->CanLowerReturn) {
6234 // Put in an sret pointer parameter before all the other parameters.
6235 SmallVector<EVT, 1> ValueVTs;
6236 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6238 // NOTE: Assuming that a pointer will never break down to more than one VT
6240 ISD::ArgFlagsTy Flags;
6242 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6243 ISD::InputArg RetArg(Flags, RegisterVT, true);
6244 Ins.push_back(RetArg);
6247 // Set up the incoming argument description vector.
6249 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6250 I != E; ++I, ++Idx) {
6251 SmallVector<EVT, 4> ValueVTs;
6252 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6253 bool isArgValueUsed = !I->use_empty();
6254 for (unsigned Value = 0, NumValues = ValueVTs.size();
6255 Value != NumValues; ++Value) {
6256 EVT VT = ValueVTs[Value];
6257 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6258 ISD::ArgFlagsTy Flags;
6259 unsigned OriginalAlignment =
6260 TD->getABITypeAlignment(ArgTy);
6262 if (F.paramHasAttr(Idx, Attribute::ZExt))
6264 if (F.paramHasAttr(Idx, Attribute::SExt))
6266 if (F.paramHasAttr(Idx, Attribute::InReg))
6268 if (F.paramHasAttr(Idx, Attribute::StructRet))
6270 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6272 const PointerType *Ty = cast<PointerType>(I->getType());
6273 const Type *ElementTy = Ty->getElementType();
6274 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6275 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6276 // For ByVal, alignment should be passed from FE. BE will guess if
6277 // this info is not there but there are cases it cannot get right.
6278 if (F.getParamAlignment(Idx))
6279 FrameAlign = F.getParamAlignment(Idx);
6280 Flags.setByValAlign(FrameAlign);
6281 Flags.setByValSize(FrameSize);
6283 if (F.paramHasAttr(Idx, Attribute::Nest))
6285 Flags.setOrigAlign(OriginalAlignment);
6287 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6288 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6289 for (unsigned i = 0; i != NumRegs; ++i) {
6290 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6291 if (NumRegs > 1 && i == 0)
6292 MyFlags.Flags.setSplit();
6293 // if it isn't first piece, alignment must be 1
6295 MyFlags.Flags.setOrigAlign(1);
6296 Ins.push_back(MyFlags);
6301 // Call the target to set up the argument values.
6302 SmallVector<SDValue, 8> InVals;
6303 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6307 // Verify that the target's LowerFormalArguments behaved as expected.
6308 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6309 "LowerFormalArguments didn't return a valid chain!");
6310 assert(InVals.size() == Ins.size() &&
6311 "LowerFormalArguments didn't emit the correct number of values!");
6313 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6314 assert(InVals[i].getNode() &&
6315 "LowerFormalArguments emitted a null value!");
6316 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6317 "LowerFormalArguments emitted a value with the wrong type!");
6321 // Update the DAG with the new chain value resulting from argument lowering.
6322 DAG.setRoot(NewRoot);
6324 // Set up the argument values.
6327 if (!FuncInfo->CanLowerReturn) {
6328 // Create a virtual register for the sret pointer, and put in a copy
6329 // from the sret argument into it.
6330 SmallVector<EVT, 1> ValueVTs;
6331 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6332 EVT VT = ValueVTs[0];
6333 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6334 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6335 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6336 RegVT, VT, AssertOp);
6338 MachineFunction& MF = SDB->DAG.getMachineFunction();
6339 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6340 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6341 FuncInfo->DemoteRegister = SRetReg;
6342 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6344 DAG.setRoot(NewRoot);
6346 // i indexes lowered arguments. Bump it past the hidden sret argument.
6347 // Idx indexes LLVM arguments. Don't touch it.
6351 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6353 SmallVector<SDValue, 4> ArgValues;
6354 SmallVector<EVT, 4> ValueVTs;
6355 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6356 unsigned NumValues = ValueVTs.size();
6358 // If this argument is unused then remember its value. It is used to generate
6359 // debugging information.
6360 if (I->use_empty() && NumValues)
6361 SDB->setUnusedArgValue(I, InVals[i]);
6363 for (unsigned Value = 0; Value != NumValues; ++Value) {
6364 EVT VT = ValueVTs[Value];
6365 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6366 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6368 if (!I->use_empty()) {
6369 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6370 if (F.paramHasAttr(Idx, Attribute::SExt))
6371 AssertOp = ISD::AssertSext;
6372 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6373 AssertOp = ISD::AssertZext;
6375 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6376 NumParts, PartVT, VT,
6383 // Note down frame index for byval arguments.
6384 if (I->hasByValAttr() && !ArgValues.empty())
6385 if (FrameIndexSDNode *FI =
6386 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6387 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6389 if (!I->use_empty()) {
6391 if (!ArgValues.empty())
6392 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6393 SDB->getCurDebugLoc());
6394 SDB->setValue(I, Res);
6396 // If this argument is live outside of the entry block, insert a copy from
6397 // whereever we got it to the vreg that other BB's will reference it as.
6398 SDB->CopyToExportRegsIfNeeded(I);
6402 assert(i == InVals.size() && "Argument register count mismatch!");
6404 // Finally, if the target has anything special to do, allow it to do so.
6405 // FIXME: this should insert code into the DAG!
6406 EmitFunctionEntryCode();
6409 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6410 /// ensure constants are generated when needed. Remember the virtual registers
6411 /// that need to be added to the Machine PHI nodes as input. We cannot just
6412 /// directly add them, because expansion might result in multiple MBB's for one
6413 /// BB. As such, the start of the BB might correspond to a different MBB than
6417 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6418 const TerminatorInst *TI = LLVMBB->getTerminator();
6420 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6422 // Check successor nodes' PHI nodes that expect a constant to be available
6424 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6425 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6426 if (!isa<PHINode>(SuccBB->begin())) continue;
6427 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6429 // If this terminator has multiple identical successors (common for
6430 // switches), only handle each succ once.
6431 if (!SuccsHandled.insert(SuccMBB)) continue;
6433 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6435 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6436 // nodes and Machine PHI nodes, but the incoming operands have not been
6438 for (BasicBlock::const_iterator I = SuccBB->begin();
6439 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6440 // Ignore dead phi's.
6441 if (PN->use_empty()) continue;
6444 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6446 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6447 unsigned &RegOut = ConstantsOut[C];
6449 RegOut = FuncInfo.CreateRegs(C->getType());
6450 CopyValueToVirtualRegister(C, RegOut);
6454 DenseMap<const Value *, unsigned>::iterator I =
6455 FuncInfo.ValueMap.find(PHIOp);
6456 if (I != FuncInfo.ValueMap.end())
6459 assert(isa<AllocaInst>(PHIOp) &&
6460 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6461 "Didn't codegen value into a register!??");
6462 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6463 CopyValueToVirtualRegister(PHIOp, Reg);
6467 // Remember that this register needs to added to the machine PHI node as
6468 // the input for this MBB.
6469 SmallVector<EVT, 4> ValueVTs;
6470 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6471 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6472 EVT VT = ValueVTs[vti];
6473 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6474 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6475 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6476 Reg += NumRegisters;
6480 ConstantsOut.clear();